[Intel-gfx] ✓ Fi.CI.IGT: success for Refactor Gen11+ SAGV support (rev3)
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev3)
URL : https://patchwork.freedesktop.org/series/68028/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7159_full -> Patchwork_14944_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14944_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {shard-tglb}: NOTRUN -> ([FAIL][1], [FAIL][2], [FAIL][3],
[FAIL][4], [FAIL][5], [FAIL][6], [FAIL][7], [FAIL][8], [FAIL][9], [FAIL][10],
[FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15], [FAIL][16],
[FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], [FAIL][21], [FAIL][22],
[FAIL][23], [FAIL][24], [FAIL][25], [FAIL][26], [FAIL][27], [FAIL][28],
[FAIL][29], [FAIL][30], [FAIL][31])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb1/igt@run...@aborted.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb7/igt@run...@aborted.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb2/igt@run...@aborted.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb2/igt@run...@aborted.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb3/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb5/igt@run...@aborted.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb7/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb8/igt@run...@aborted.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb7/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb8/igt@run...@aborted.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb5/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb5/igt@run...@aborted.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb6/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb4/igt@run...@aborted.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb6/igt@run...@aborted.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb3/igt@run...@aborted.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb7/igt@run...@aborted.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb8/igt@run...@aborted.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb8/igt@run...@aborted.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb5/igt@run...@aborted.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb1/igt@run...@aborted.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb8/igt@run...@aborted.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb2/igt@run...@aborted.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb5/igt@run...@aborted.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb6/igt@run...@aborted.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb2/igt@run...@aborted.html
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb7/igt@run...@aborted.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb8/igt@run...@aborted.html
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb5/igt@run...@aborted.html
[30]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb4/igt@run...@aborted.html
[31]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-tglb5/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_14944_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_busy@busy-vcs1:
- shard-iclb: [PASS][32] -> [SKIP][33] ([fdo#112080]) +10 similar
issues
[32]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/shard-iclb1/igt@gem_b...@busy-vcs1.html
[33]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/shard-iclb8/igt@gem_b...@busy-vcs1.html
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][34] -> [SKIP][35] ([fdo#109276] /
[fdo#112080]) +1 similar issue
[34]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/shard-iclb4/igt@gem_ctx_isolat...@vcs1-dirty-create.html
[35]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Try to more gracefully quiesce the system before resets
== Series Details == Series: drm/i915/gt: Try to more gracefully quiesce the system before resets URL : https://patchwork.freedesktop.org/series/68445/ State : success == Summary == CI Bug Log - changes from CI_DRM_7159_full -> Patchwork_14943_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14943_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/shard-iclb4/igt@gem_ctx_isolat...@vcs1-dirty-create.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/shard-iclb8/igt@gem_ctx_isolat...@vcs1-dirty-create.html * igt@gem_ctx_switch@vcs1-heavy-queue: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112080]) +6 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/shard-iclb1/igt@gem_ctx_swi...@vcs1-heavy-queue.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/shard-iclb5/igt@gem_ctx_swi...@vcs1-heavy-queue.html * igt@gem_eio@in-flight-contexts-1us: - shard-hsw: [PASS][5] -> [SKIP][6] ([fdo#109271]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/shard-hsw5/igt@gem_...@in-flight-contexts-1us.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/shard-hsw4/igt@gem_...@in-flight-contexts-1us.html * igt@gem_eio@in-flight-external: - shard-snb: [PASS][7] -> [SKIP][8] ([fdo#109271]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/shard-snb2/igt@gem_...@in-flight-external.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/shard-snb5/igt@gem_...@in-flight-external.html * igt@gem_exec_schedule@out-order-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/shard-iclb5/igt@gem_exec_sched...@out-order-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/shard-iclb1/igt@gem_exec_sched...@out-order-bsd.html * igt@gem_ringfill@basic-default-hang: - shard-kbl: [PASS][11] -> [SKIP][12] ([fdo#109271]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/shard-kbl7/igt@gem_ringf...@basic-default-hang.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/shard-kbl3/igt@gem_ringf...@basic-default-hang.html * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: - shard-snb: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/shard-snb6/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/shard-snb7/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html * igt@gem_userptr_blits@sync-unmap-after-close: - shard-hsw: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/shard-hsw7/igt@gem_userptr_bl...@sync-unmap-after-close.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/shard-hsw5/igt@gem_userptr_bl...@sync-unmap-after-close.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +7 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/shard-apl6/igt@i915_susp...@fence-restore-tiled2untiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_busy@extended-pageflip-hang-newfb-render-c: - shard-skl: [PASS][19] -> [SKIP][20] ([fdo#109271]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/shard-skl8/igt@kms_b...@extended-pageflip-hang-newfb-render-c.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/shard-skl7/igt@kms_b...@extended-pageflip-hang-newfb-render-c.html * igt@kms_flip@blocking-absolute-wf_vblank-interruptible: - shard-apl: [PASS][21] -> [INCOMPLETE][22] ([fdo#103927]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/shard-apl8/igt@kms_flip@blocking-absolute-wf_vblank-interruptible.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/shard-apl4/igt@kms_flip@blocking-absolute-wf_vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103167]) +5 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-render.html [24]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/dp: Add function to parse EDID descriptors for adaptive sync limits
== Series Details ==
Series: drm/dp: Add function to parse EDID descriptors for adaptive sync limits
URL : https://patchwork.freedesktop.org/series/68488/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7167 -> Patchwork_14959
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14959 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14959, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14959/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14959:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_execlists:
- fi-cfl-8109u: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14959/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
Known issues
Here are the changes found in Patchwork_14959 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14959/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [PASS][5] -> [WARN][6] ([fdo#109483])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14959/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
Possible fixes
* igt@gem_sync@basic-store-all:
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111880]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-tgl-u/igt@gem_s...@basic-store-all.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14959/fi-tgl-u/igt@gem_s...@basic-store-all.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-skl-6600u: [FAIL][9] ([fdo#107707]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14959/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
* {igt@i915_selftest@live_gt_heartbeat}:
- {fi-icl-dsi}: [DMESG-FAIL][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14959/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
* igt@kms_busy@basic-flip-a:
- {fi-tgl-u2}:[DMESG-WARN][13] ([fdo#111600]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14959/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111407]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14959/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_vgem@basic-fence-wait-default:
- fi-icl-u3: [DMESG-WARN][17] ([fdo#107724]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14959/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
Participating hosts (52 -> 45)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Flush any i915_active callback work as well
== Series Details ==
Series: drm/i915/selftests: Flush any i915_active callback work as well
URL : https://patchwork.freedesktop.org/series/68487/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7167 -> Patchwork_14958
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14958:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-glk-dsi: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-glk-dsi/igt@i915_selftest@live_gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/fi-glk-dsi/igt@i915_selftest@live_gt_heartbeat.html
Known issues
Here are the changes found in Patchwork_14958 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [PASS][3] -> [DMESG-FAIL][4] ([fdo#112050 ])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
* igt@prime_vgem@basic-write:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-u3/igt@prime_v...@basic-write.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/fi-icl-u3/igt@prime_v...@basic-write.html
Possible fixes
* igt@gem_sync@basic-store-all:
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111880]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-tgl-u/igt@gem_s...@basic-store-all.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/fi-tgl-u/igt@gem_s...@basic-store-all.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-skl-6600u: [FAIL][9] ([fdo#107707]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
* {igt@i915_selftest@live_gt_heartbeat}:
- {fi-icl-dsi}: [DMESG-FAIL][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
- fi-kbl-8809g: [DMESG-FAIL][13] ([fdo#112096]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
* igt@prime_vgem@basic-fence-wait-default:
- fi-icl-u3: [DMESG-WARN][15] ([fdo#107724]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111407]) -> [FAIL][18] ([fdo#111045]
/ [fdo#111096])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14958/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#112050 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112050
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (52 -> 43)
--
Missing(9): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-skl-guc
Re: [Intel-gfx] [PATCH V5 4/6] mdev: introduce virtio device and its device ops
On 2019/10/24 上午5:57, Alex Williamson wrote:
On Wed, 23 Oct 2019 21:07:50 +0800
Jason Wang wrote:
This patch implements basic support for mdev driver that supports
virtio transport for kernel virtio driver.
Signed-off-by: Jason Wang
---
drivers/vfio/mdev/mdev_core.c| 20
drivers/vfio/mdev/mdev_private.h | 2 +
include/linux/mdev.h | 6 ++
include/linux/virtio_mdev_ops.h | 159 +++
4 files changed, 187 insertions(+)
create mode 100644 include/linux/virtio_mdev_ops.h
diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
index 555bd61d8c38..9b00c3513120 100644
--- a/drivers/vfio/mdev/mdev_core.c
+++ b/drivers/vfio/mdev/mdev_core.c
@@ -76,6 +76,26 @@ const struct vfio_mdev_device_ops *mdev_get_vfio_ops(struct
mdev_device *mdev)
}
EXPORT_SYMBOL(mdev_get_vfio_ops);
+/* Specify the virtio device ops for the mdev device, this
+ * must be called during create() callback for virtio mdev device.
+ */
+void mdev_set_virtio_ops(struct mdev_device *mdev,
+const struct virtio_mdev_device_ops *virtio_ops)
+{
+ mdev_set_class(mdev, MDEV_CLASS_ID_VIRTIO);
+ mdev->virtio_ops = virtio_ops;
+}
+EXPORT_SYMBOL(mdev_set_virtio_ops);
+
+/* Get the virtio device ops for the mdev device. */
+const struct virtio_mdev_device_ops *
+mdev_get_virtio_ops(struct mdev_device *mdev)
+{
+ WARN_ON(mdev->class_id != MDEV_CLASS_ID_VIRTIO);
+ return mdev->virtio_ops;
+}
+EXPORT_SYMBOL(mdev_get_virtio_ops);
+
struct device *mdev_dev(struct mdev_device *mdev)
{
return >dev;
diff --git a/drivers/vfio/mdev/mdev_private.h b/drivers/vfio/mdev/mdev_private.h
index 0770410ded2a..7b47890c34e7 100644
--- a/drivers/vfio/mdev/mdev_private.h
+++ b/drivers/vfio/mdev/mdev_private.h
@@ -11,6 +11,7 @@
#define MDEV_PRIVATE_H
#include
+#include
int mdev_bus_register(void);
void mdev_bus_unregister(void);
@@ -38,6 +39,7 @@ struct mdev_device {
u16 class_id;
union {
const struct vfio_mdev_device_ops *vfio_ops;
+ const struct virtio_mdev_device_ops *virtio_ops;
};
};
diff --git a/include/linux/mdev.h b/include/linux/mdev.h
index 4625f1a11014..9b69b0bbebfd 100644
--- a/include/linux/mdev.h
+++ b/include/linux/mdev.h
@@ -17,6 +17,7 @@
struct mdev_device;
struct vfio_mdev_device_ops;
+struct virtio_mdev_device_ops;
/*
* Called by the parent device driver to set the device which represents
@@ -112,6 +113,10 @@ void mdev_set_class(struct mdev_device *mdev, u16 id);
void mdev_set_vfio_ops(struct mdev_device *mdev,
const struct vfio_mdev_device_ops *vfio_ops);
const struct vfio_mdev_device_ops *mdev_get_vfio_ops(struct mdev_device
*mdev);
+void mdev_set_virtio_ops(struct mdev_device *mdev,
+const struct virtio_mdev_device_ops *virtio_ops);
+const struct virtio_mdev_device_ops *
+mdev_get_virtio_ops(struct mdev_device *mdev);
extern struct bus_type mdev_bus_type;
@@ -127,6 +132,7 @@ struct mdev_device *mdev_from_dev(struct device *dev);
enum {
MDEV_CLASS_ID_VFIO = 1,
+ MDEV_CLASS_ID_VIRTIO = 2,
/* New entries must be added here */
};
diff --git a/include/linux/virtio_mdev_ops.h b/include/linux/virtio_mdev_ops.h
new file mode 100644
index ..d417b41f2845
--- /dev/null
+++ b/include/linux/virtio_mdev_ops.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Virtio mediated device driver
+ *
+ * Copyright 2019, Red Hat Corp.
+ * Author: Jason Wang
+ */
+#ifndef _LINUX_VIRTIO_MDEV_H
+#define _LINUX_VIRTIO_MDEV_H
+
+#include
+#include
+#include
+
+#define VIRTIO_MDEV_DEVICE_API_STRING "virtio-mdev"
+#define VIRTIO_MDEV_F_VERSION_1 0x1
+
+struct virtio_mdev_callback {
+ irqreturn_t (*callback)(void *data);
+ void *private;
+};
+
+/**
+ * struct vfio_mdev_device_ops - Structure to be registered for each
+ * mdev device to register the device for virtio/vhost drivers.
+ *
+ * The device ops that is supported by VIRTIO_MDEV_F_VERSION_1, the
+ * callbacks are mandatory unless explicity mentioned.
If the version of the callbacks is returned by a callback within the
structure defined by the version... isn't that a bit circular? This
seems redundant to me versus the class id. The fact that the parent
driver defines the device as MDEV_CLASS_ID_VIRTIO should tell us this
already. If it was incremented, we'd need an MDEV_CLASS_ID_VIRTIOv2,
which the virtio-mdev bus driver could add to its id table and handle
differently.
My understanding is versions are only allowed to increase monotonically,
this seems less flexible than features. E.g we have features A, B, C,
mdev device can choose to support only a subset. E.g when mdev device
can support dirty page logging, it can add a new feature bit for driver
to know that it support new device ops. MDEV_CLASS_ID_VIRTIOv2 may only
be
Re: [Intel-gfx] [PATCH V5 2/6] modpost: add support for mdev class id
On 2019/10/24 上午5:42, Alex Williamson wrote:
On Wed, 23 Oct 2019 21:07:48 +0800
Jason Wang wrote:
Add support to parse mdev class id table.
Reviewed-by: Parav Pandit
Signed-off-by: Jason Wang
---
drivers/vfio/mdev/vfio_mdev.c | 2 ++
scripts/mod/devicetable-offsets.c | 3 +++
scripts/mod/file2alias.c | 10 ++
3 files changed, 15 insertions(+)
diff --git a/drivers/vfio/mdev/vfio_mdev.c b/drivers/vfio/mdev/vfio_mdev.c
index 7b24ee9cb8dd..cb701cd646f0 100644
--- a/drivers/vfio/mdev/vfio_mdev.c
+++ b/drivers/vfio/mdev/vfio_mdev.c
@@ -125,6 +125,8 @@ static const struct mdev_class_id id_table[] = {
{ 0 },
};
+MODULE_DEVICE_TABLE(mdev, id_table);
+
Two questions, first we have:
#define MODULE_DEVICE_TABLE(type, name) \
extern typeof(name) __mod_##type##__##name##_device_table \
__attribute__ ((unused, alias(__stringify(name
Therefore we're defining __mod_mdev__id_table_device_table with alias
id_table. When the virtio mdev bus driver is added in 5/6 it uses the
same name value. I see virtio types all register this way (virtio,
id_table), so I assume there's no conflict, but pci types mostly (not
entirely) seem to use unique names. Is there a preference to one way
or the other or it simply doesn't matter?
It looks to me that those symbol were local, so it doesn't matter. But
if you wish I can switch to use unique name.
static struct mdev_driver vfio_mdev_driver = {
.name = "vfio_mdev",
.probe = vfio_mdev_probe,
diff --git a/scripts/mod/devicetable-offsets.c
b/scripts/mod/devicetable-offsets.c
index 054405b90ba4..6cbb1062488a 100644
--- a/scripts/mod/devicetable-offsets.c
+++ b/scripts/mod/devicetable-offsets.c
@@ -231,5 +231,8 @@ int main(void)
DEVID(wmi_device_id);
DEVID_FIELD(wmi_device_id, guid_string);
+ DEVID(mdev_class_id);
+ DEVID_FIELD(mdev_class_id, id);
+
return 0;
}
diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c
index c91eba751804..d365dfe7c718 100644
--- a/scripts/mod/file2alias.c
+++ b/scripts/mod/file2alias.c
@@ -1335,6 +1335,15 @@ static int do_wmi_entry(const char *filename, void
*symval, char *alias)
return 1;
}
+/* looks like: "mdev:cN" */
+static int do_mdev_entry(const char *filename, void *symval, char *alias)
+{
+ DEF_FIELD(symval, mdev_class_id, id);
+
+ sprintf(alias, "mdev:c%02X", id);
A lot of entries call add_wildcard() here, should we? Sorry for the
basic questions, I haven't played in this code. Thanks,
It's really good question. My understanding is we won't have a module
that can deal with all kinds of classes like CLASS_ID_ANY. So there's
probably no need for the wildcard.
Thanks
Alex
+ return 1;
+}
+
/* Does namelen bytes of name exactly match the symbol? */
static bool sym_is(const char *name, unsigned namelen, const char *symbol)
{
@@ -1407,6 +1416,7 @@ static const struct devtable devtable[] = {
{"typec", SIZE_typec_device_id, do_typec_entry},
{"tee", SIZE_tee_client_device_id, do_tee_entry},
{"wmi", SIZE_wmi_device_id, do_wmi_entry},
+ {"mdev", SIZE_mdev_class_id, do_mdev_entry},
};
/* Create MODULE_ALIAS() statements.
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V5 1/6] mdev: class id support
On 2019/10/24 上午5:42, Alex Williamson wrote:
On Wed, 23 Oct 2019 21:07:47 +0800
Jason Wang wrote:
Mdev bus only supports vfio driver right now, so it doesn't implement
match method. But in the future, we may add drivers other than vfio,
the first driver could be virtio-mdev. This means we need to add
device class id support in bus match method to pair the mdev device
and mdev driver correctly.
So this patch adds id_table to mdev_driver and class_id for mdev
device with the match method for mdev bus.
Signed-off-by: Jason Wang
---
.../driver-api/vfio-mediated-device.rst | 5 +
drivers/gpu/drm/i915/gvt/kvmgt.c | 1 +
drivers/s390/cio/vfio_ccw_ops.c | 1 +
drivers/s390/crypto/vfio_ap_ops.c | 1 +
drivers/vfio/mdev/mdev_core.c | 18 +++
drivers/vfio/mdev/mdev_driver.c | 22 +++
drivers/vfio/mdev/mdev_private.h | 1 +
drivers/vfio/mdev/vfio_mdev.c | 6 +
include/linux/mdev.h | 8 +++
include/linux/mod_devicetable.h | 8 +++
samples/vfio-mdev/mbochs.c| 1 +
samples/vfio-mdev/mdpy.c | 1 +
samples/vfio-mdev/mtty.c | 1 +
13 files changed, 74 insertions(+)
diff --git a/Documentation/driver-api/vfio-mediated-device.rst
b/Documentation/driver-api/vfio-mediated-device.rst
index 25eb7d5b834b..6709413bee29 100644
--- a/Documentation/driver-api/vfio-mediated-device.rst
+++ b/Documentation/driver-api/vfio-mediated-device.rst
@@ -102,12 +102,14 @@ structure to represent a mediated device's driver::
* @probe: called when new device created
* @remove: called when device removed
* @driver: device driver structure
+ * @id_table: the ids serviced by this driver
*/
struct mdev_driver {
const char *name;
int (*probe) (struct device *dev);
void (*remove) (struct device *dev);
struct device_driverdriver;
+const struct mdev_class_id *id_table;
};
A mediated bus driver for mdev should use this structure in the function calls
@@ -170,6 +172,9 @@ that a driver should use to unregister itself with the mdev
core driver::
extern void mdev_unregister_device(struct device *dev);
+It is also required to specify the class_id in create() callback through::
+
+ int mdev_set_class(struct mdev_device *mdev, u16 id);
Mediated Device Management Interface Through sysfs
==
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 343d79c1cb7e..6420f0dbd31b 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -678,6 +678,7 @@ static int intel_vgpu_create(struct kobject *kobj, struct
mdev_device *mdev)
dev_name(mdev_dev(mdev)));
ret = 0;
+ mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
out:
return ret;
}
diff --git a/drivers/s390/cio/vfio_ccw_ops.c b/drivers/s390/cio/vfio_ccw_ops.c
index f0d71ab77c50..cf2c013ae32f 100644
--- a/drivers/s390/cio/vfio_ccw_ops.c
+++ b/drivers/s390/cio/vfio_ccw_ops.c
@@ -129,6 +129,7 @@ static int vfio_ccw_mdev_create(struct kobject *kobj,
struct mdev_device *mdev)
private->sch->schid.ssid,
private->sch->schid.sch_no);
+ mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
return 0;
}
diff --git a/drivers/s390/crypto/vfio_ap_ops.c b/drivers/s390/crypto/vfio_ap_ops.c
index 5c0f53c6dde7..07c31070afeb 100644
--- a/drivers/s390/crypto/vfio_ap_ops.c
+++ b/drivers/s390/crypto/vfio_ap_ops.c
@@ -343,6 +343,7 @@ static int vfio_ap_mdev_create(struct kobject *kobj, struct
mdev_device *mdev)
list_add(_mdev->node, _dev->mdev_list);
mutex_unlock(_dev->lock);
+ mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
return 0;
}
diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
index b558d4cfd082..3a9c52d71b4e 100644
--- a/drivers/vfio/mdev/mdev_core.c
+++ b/drivers/vfio/mdev/mdev_core.c
@@ -45,6 +45,16 @@ void mdev_set_drvdata(struct mdev_device *mdev, void *data)
}
EXPORT_SYMBOL(mdev_set_drvdata);
+/* Specify the class for the mdev device, this must be called during
+ * create() callback.
+ */
+void mdev_set_class(struct mdev_device *mdev, u16 id)
+{
+ WARN_ON(mdev->class_id);
+ mdev->class_id = id;
+}
+EXPORT_SYMBOL(mdev_set_class);
+
struct device *mdev_dev(struct mdev_device *mdev)
{
return >dev;
@@ -135,6 +145,7 @@ static int mdev_device_remove_cb(struct device *dev, void
*data)
* mdev_register_device : Register a device
* @dev: device structure representing parent device.
* @ops: Parent device operation structure to be registered.
+ * @id: class id.
*
* Add device to list of registered parent
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Flush interrupts before disabling tasklets
== Series Details ==
Series: drm/i915/selftests: Flush interrupts before disabling tasklets
URL : https://patchwork.freedesktop.org/series/68486/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7167 -> Patchwork_14957
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/index.html
Known issues
Here are the changes found in Patchwork_14957 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-u3/igt@gem_mmap_...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/fi-icl-u3/igt@gem_mmap_...@basic.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [PASS][3] -> [DMESG-FAIL][4] ([fdo#112050 ])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
Possible fixes
* igt@gem_sync@basic-store-all:
- {fi-tgl-u}: [INCOMPLETE][5] ([fdo#111880]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-tgl-u/igt@gem_s...@basic-store-all.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/fi-tgl-u/igt@gem_s...@basic-store-all.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-skl-6600u: [FAIL][7] ([fdo#107707]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-kbl-8809g: [DMESG-FAIL][9] ([fdo#112096]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
* igt@kms_busy@basic-flip-a:
- {fi-tgl-u2}:[DMESG-WARN][11] ([fdo#111600]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
* igt@prime_vgem@basic-fence-wait-default:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#112050 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112050
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (52 -> 45)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7167 -> Patchwork_14957
CI-20190529: 20190529
CI_DRM_7167: a62b1c4e7739c6777d51e7b2d66406b935131451 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5236: 8153b95b53bdef26d2c3e318197d174e982b4265 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14957: d179199a3774c6f792d2455df296e2d01e686422 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d179199a3774 drm/i915/selftests: Flush interrupts before disabling tasklets
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14957/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/psr: Print in debugfs if PSR is not enabled because of sink
== Series Details ==
Series: drm/i915/display/psr: Print in debugfs if PSR is not enabled because of
sink
URL : https://patchwork.freedesktop.org/series/68482/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7167 -> Patchwork_14955
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/index.html
Known issues
Here are the changes found in Patchwork_14955 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][3] -> [FAIL][4] ([fdo#108511])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
Possible fixes
* igt@gem_sync@basic-store-all:
- {fi-tgl-u}: [INCOMPLETE][5] ([fdo#111880]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-tgl-u/igt@gem_s...@basic-store-all.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/fi-tgl-u/igt@gem_s...@basic-store-all.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-skl-6600u: [FAIL][7] ([fdo#107707]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
* {igt@i915_selftest@live_gt_heartbeat}:
- {fi-icl-dsi}: [DMESG-FAIL][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
- fi-kbl-8809g: [DMESG-FAIL][11] ([fdo#112096]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111407]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_vgem@basic-fence-wait-default:
- fi-icl-u3: [DMESG-WARN][15] ([fdo#107724]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (52 -> 45)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7167 -> Patchwork_14955
CI-20190529: 20190529
CI_DRM_7167: a62b1c4e7739c6777d51e7b2d66406b935131451 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5236: 8153b95b53bdef26d2c3e318197d174e982b4265 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14955: de5b4714b44ee28db5921e8614ed27cc96193c81 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
de5b4714b44e drm/i915/display/psr: Print in debugfs if PSR is not enabled
because of sink
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14955/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Flush interrupts before disabling tasklets
== Series Details == Series: drm/i915/selftests: Flush interrupts before disabling tasklets URL : https://patchwork.freedesktop.org/series/68486/ State : warning == Summary == $ dim checkpatch origin/drm-tip d179199a3774 drm/i915/selftests: Flush interrupts before disabling tasklets -:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #10: <0> [472.951428] i915_sel-44420d..1 466527056us : __i915_request_submit: rcs0 fence 11659:2, current 0 total: 0 errors, 1 warnings, 0 checks, 16 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for string-choice: add yesno(), onoff(), enableddisabled(), plural() helpers (rev2)
== Series Details == Series: string-choice: add yesno(), onoff(), enableddisabled(), plural() helpers (rev2) URL : https://patchwork.freedesktop.org/series/68461/ State : failure == Summary == Applying: string-choice: add yesno(), onoff(), enableddisabled(), plural() helpers error: sha1 information is lacking or useless (include/linux/string-choice.h). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 string-choice: add yesno(), onoff(), enableddisabled(), plural() helpers When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix PCH reference clock for FDI on HSW/BDW (rev2)
== Series Details ==
Series: drm/i915: Fix PCH reference clock for FDI on HSW/BDW (rev2)
URL : https://patchwork.freedesktop.org/series/68411/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7167 -> Patchwork_14953
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/index.html
Known issues
Here are the changes found in Patchwork_14953 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-u3/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/fi-icl-u3/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch.html
Possible fixes
* igt@gem_sync@basic-store-all:
- {fi-tgl-u}: [INCOMPLETE][3] ([fdo#111880]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-tgl-u/igt@gem_s...@basic-store-all.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/fi-tgl-u/igt@gem_s...@basic-store-all.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-skl-6600u: [FAIL][5] ([fdo#107707]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
* {igt@i915_selftest@live_gt_heartbeat}:
- {fi-icl-dsi}: [DMESG-FAIL][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#111407]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_vgem@basic-fence-wait-default:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
Participating hosts (52 -> 43)
--
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-bdw-samus fi-byt-clapper fi-skl-6700k2 fi-kbl-r
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7167 -> Patchwork_14953
CI-20190529: 20190529
CI_DRM_7167: a62b1c4e7739c6777d51e7b2d66406b935131451 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5236: 8153b95b53bdef26d2c3e318197d174e982b4265 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14953: ffe180767d438e9f8d91e5305fb83dc6dd671e54 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ffe180767d43 drm/i915: Fix PCH reference clock for FDI on HSW/BDW
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14953/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm: Add support for integrated privacy screens
== Series Details == Series: drm: Add support for integrated privacy screens URL : https://patchwork.freedesktop.org/series/68472/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) Building modules, stage 2. MODPOST 122 modules ERROR: "drm_privacy_screen_present" [drivers/gpu/drm/i915/i915.ko] undefined! scripts/Makefile.modpost:93: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1282: recipe for target 'modules' failed make: *** [modules] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI 1/5] drm/i915/gt: Try to more gracefully quiesce the system before resets
On 2019-10-23 at 14:31:04 +0100, Chris Wilson wrote:
> If we are doing a normal GPU reset triggered after detecting a long
> period of stalled work, we can take our time and allow the engines to
> quiesce. Since we've stopped submission to the engine, and if we wait
> long enough an innocent context should complete, leaving the engine idle.
> So by waiting a short amount of time, we should prevent clobbering other
> users when resetting a stuck context.
>
> Suggested-by: Joonas Lahtinen
> Suggested-by: Jon Bloomfield
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Joonas Lahtinen
> Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/Kconfig.profile | 11 +++
> drivers/gpu/drm/i915/gt/intel_engine_cs.c| 20 +++-
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 4
> 3 files changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/Kconfig.profile
> b/drivers/gpu/drm/i915/Kconfig.profile
> index 48df8889a88a..3a3881d5e44b 100644
> --- a/drivers/gpu/drm/i915/Kconfig.profile
> +++ b/drivers/gpu/drm/i915/Kconfig.profile
> @@ -25,3 +25,14 @@ config DRM_I915_SPIN_REQUEST
> May be 0 to disable the initial spin. In practice, we estimate
> the cost of enabling the interrupt (if currently disabled) to be
> a few microseconds.
> +
> +config DRM_I915_STOP_TIMEOUT
> + int "How long to wait for an engine to quiesce gracefully before reset
> (ms)"
> + default 100 # milliseconds
> + help
> + By stopping submission and sleeping for a short time before resetting
> + the GPU, we allow the innocent contexts also on the system to quiesce.
> + It is then less likely for a hanging context to cause collateral
> + damage as the system is reset in order to recover. The corollary is
> + that the reset itself may take longer and so be more disruptive to
> + interactive or low latency workloads.
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 0e20713603ec..e4203eb44139 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -308,6 +308,9 @@ static int intel_engine_setup(struct intel_gt *gt, enum
> intel_engine_id id)
> engine->instance = info->instance;
> __sprint_engine_name(engine);
>
> + engine->props.stop_timeout_ms =
> + CONFIG_DRM_I915_STOP_TIMEOUT;
Compare to previous version where you used the CONFIG variable directly,
what is the benefit of using it through a variable? So that we could
alter it in runtime?
-Ram
> +
> /*
>* To be overridden by the backend on setup. However to facilitate
>* cleanup on error during setup, we always provide the destroy vfunc.
> @@ -875,6 +878,21 @@ u64 intel_engine_get_last_batch_head(const struct
> intel_engine_cs *engine)
> return bbaddr;
> }
>
> +static unsigned long stop_timeout(const struct intel_engine_cs *engine)
> +{
> + if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */
> + return 0;
> +
> + /*
> + * If we are doing a normal GPU reset, we can take our time and allow
> + * the engine to quiesce. We've stopped submission to the engine, and
> + * if we wait long enough an innocent context should complete and
> + * leave the engine idle. So they should not be caught unaware by
> + * the forthcoming GPU reset (which usually follows the stop_cs)!
> + */
> + return READ_ONCE(engine->props.stop_timeout_ms);
> +}
> +
> int intel_engine_stop_cs(struct intel_engine_cs *engine)
> {
> struct intel_uncore *uncore = engine->uncore;
> @@ -892,7 +910,7 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
> err = 0;
> if (__intel_wait_for_register_fw(uncore,
>mode, MODE_IDLE, MODE_IDLE,
> - 1000, 0,
> + 1000, stop_timeout(engine),
>NULL)) {
> GEM_TRACE("%s: timed out on STOP_RING -> IDLE\n", engine->name);
> err = -ETIMEDOUT;
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 3451be034caf..87d5c4ef3ae7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -542,6 +542,10 @@ struct intel_engine_cs {
>*/
> ktime_t total;
> } stats;
> +
> + struct {
> + unsigned long stop_timeout_ms;
> + } props;
> };
>
> static inline bool
> --
> 2.24.0.rc0
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/property: Enforce more lifetime rules
== Series Details ==
Series: series starting with [1/2] drm/property: Enforce more lifetime rules
URL : https://patchwork.freedesktop.org/series/68467/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7167 -> Patchwork_14952
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/index.html
Known issues
Here are the changes found in Patchwork_14952 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [PASS][1] -> [DMESG-FAIL][2] ([fdo#112050 ])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
Possible fixes
* igt@gem_sync@basic-store-all:
- {fi-tgl-u}: [INCOMPLETE][3] ([fdo#111880]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-tgl-u/igt@gem_s...@basic-store-all.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/fi-tgl-u/igt@gem_s...@basic-store-all.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-skl-6600u: [FAIL][5] ([fdo#107707]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
* {igt@i915_selftest@live_gt_heartbeat}:
- {fi-icl-dsi}: [DMESG-FAIL][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
- fi-kbl-8809g: [DMESG-FAIL][9] ([fdo#112096]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111407]) -> [FAIL][12] ([fdo#111045]
/ [fdo#111096])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#112050 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112050
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (52 -> 45)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7167 -> Patchwork_14952
CI-20190529: 20190529
CI_DRM_7167: a62b1c4e7739c6777d51e7b2d66406b935131451 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5236: 8153b95b53bdef26d2c3e318197d174e982b4265 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14952: 85155761fd1fd0f023f36abdf6d760b1909891b6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
85155761fd1f drm/todo: Add entry to remove load/unload hooks
33ce34335c16 drm/property: Enforce more lifetime rules
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14952/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: register vga switcheroo later, unregister earlier (rev2)
== Series Details ==
Series: drm/i915: register vga switcheroo later, unregister earlier (rev2)
URL : https://patchwork.freedesktop.org/series/67644/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7167 -> Patchwork_14951
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/index.html
Known issues
Here are the changes found in Patchwork_14951 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_workarounds@basic-read:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-u3/igt@gem_workarou...@basic-read.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/fi-icl-u3/igt@gem_workarou...@basic-read.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][3] -> [FAIL][4] ([fdo#108511])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [PASS][5] -> [DMESG-FAIL][6] ([fdo#112050 ])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
Possible fixes
* igt@gem_sync@basic-store-all:
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111880]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-tgl-u/igt@gem_s...@basic-store-all.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/fi-tgl-u/igt@gem_s...@basic-store-all.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-skl-6600u: [FAIL][9] ([fdo#107707]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
* {igt@i915_selftest@live_gt_heartbeat}:
- {fi-icl-dsi}: [DMESG-FAIL][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
- fi-kbl-8809g: [DMESG-FAIL][13] ([fdo#112096]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
* igt@kms_busy@basic-flip-a:
- {fi-tgl-u2}:[DMESG-WARN][15] ([fdo#111600]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
* igt@prime_vgem@basic-fence-wait-default:
- fi-icl-u3: [DMESG-WARN][17] ([fdo#107724]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][19] ([fdo#111407]) -> [FAIL][20] ([fdo#111045]
/ [fdo#111096])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14951/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#112050 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112050
[fdo#112096]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/property: Enforce more lifetime rules
== Series Details == Series: series starting with [1/2] drm/property: Enforce more lifetime rules URL : https://patchwork.freedesktop.org/series/68467/ State : warning == Summary == $ dim checkpatch origin/drm-tip 33ce34335c16 drm/property: Enforce more lifetime rules -:40: CHECK:LINE_SPACING: Please don't use multiple blank lines #40: FILE: drivers/gpu/drm/drm_mode_object.c:238: + + -:51: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter ' total: 0 errors, 1 warnings, 1 checks, 26 lines checked 85155761fd1f drm/todo: Add entry to remove load/unload hooks -:45: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 23 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Making loglevel of PSR2/SU logs same.
== Series Details ==
Series: drm/i915: Making loglevel of PSR2/SU logs same.
URL : https://patchwork.freedesktop.org/series/68439/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14940_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14940_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_fence_thrash@bo-write-verify-threaded-y:
- {shard-tglb}: [PASS][1] -> [INCOMPLETE][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb6/igt@gem_fence_thr...@bo-write-verify-threaded-y.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-tglb4/igt@gem_fence_thr...@bo-write-verify-threaded-y.html
Known issues
Here are the changes found in Patchwork_14940_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@vcs1-none:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080])
+1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb1/igt@gem_ctx_isolat...@vcs1-none.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-iclb6/igt@gem_ctx_isolat...@vcs1-none.html
* igt@gem_ctx_switch@vcs1:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +5 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb1/igt@gem_ctx_swi...@vcs1.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-iclb6/igt@gem_ctx_swi...@vcs1.html
* igt@gem_eio@reset-stress:
- shard-snb: [PASS][7] -> [FAIL][8] ([fdo#109661])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb2/igt@gem_...@reset-stress.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-snb2/igt@gem_...@reset-stress.html
* igt@gem_exec_reloc@basic-cpu-gtt-active:
- shard-skl: [PASS][9] -> [DMESG-WARN][10] ([fdo#106107])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl6/igt@gem_exec_re...@basic-cpu-gtt-active.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-skl8/igt@gem_exec_re...@basic-cpu-gtt-active.html
* igt@gem_exec_schedule@preempt-queue-bsd2:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +15 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb2/igt@gem_exec_sched...@preempt-queue-bsd2.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-iclb5/igt@gem_exec_sched...@preempt-queue-bsd2.html
* igt@gem_exec_schedule@preempt-self-bsd:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#111325]) +3 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb6/igt@gem_exec_sched...@preempt-self-bsd.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-iclb1/igt@gem_exec_sched...@preempt-self-bsd.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-hsw: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw2/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-hsw2/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) +1
similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-snb7/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
* igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
- shard-apl: [PASS][19] -> [INCOMPLETE][20] ([fdo#103927])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl2/igt@kms_cursor_leg...@cursor-vs-flip-varying-size.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-apl6/igt@kms_cursor_leg...@cursor-vs-flip-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#102670] / [fdo#106081])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl5/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14940/shard-skl2/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#105363]) +1 similar
issue
[Intel-gfx] ✓ Fi.CI.BAT: success for mdev based hardware virtio offloading support (rev6)
== Series Details ==
Series: mdev based hardware virtio offloading support (rev6)
URL : https://patchwork.freedesktop.org/series/66989/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7167 -> Patchwork_14949
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14949:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-glk-dsi: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-glk-dsi/igt@i915_selftest@live_gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/fi-glk-dsi/igt@i915_selftest@live_gt_heartbeat.html
Known issues
Here are the changes found in Patchwork_14949 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ringfill@basic-default-fd:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-u3/igt@gem_ringf...@basic-default-fd.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/fi-icl-u3/igt@gem_ringf...@basic-default-fd.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [PASS][7] -> [DMESG-FAIL][8] ([fdo#112050 ])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
Possible fixes
* igt@gem_sync@basic-store-all:
- {fi-tgl-u}: [INCOMPLETE][9] ([fdo#111880]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-tgl-u/igt@gem_s...@basic-store-all.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/fi-tgl-u/igt@gem_s...@basic-store-all.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-skl-6600u: [FAIL][11] ([fdo#107707]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html
* {igt@i915_selftest@live_gt_heartbeat}:
- {fi-icl-dsi}: [DMESG-FAIL][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
- fi-kbl-8809g: [DMESG-FAIL][15] ([fdo#112096]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
* igt@prime_vgem@basic-fence-wait-default:
- fi-icl-u3: [DMESG-WARN][17] ([fdo#107724]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/fi-icl-u3/igt@prime_v...@basic-fence-wait-default.html
Warnings
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-guc: [SKIP][19] ([fdo#109271]) -> [FAIL][20] ([fdo#110829])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7167/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14949/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#110829]: https://bugs.freedesktop.org/show_bug.cgi?id=110829
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [CI,1/5] drm/i915/gt: Try to more gracefully quiesce the system before resets
== Series Details == Series: series starting with [CI,1/5] drm/i915/gt: Try to more gracefully quiesce the system before resets URL : https://patchwork.freedesktop.org/series/68463/ State : failure == Summary == Applying: drm/i915/gt: Try to more gracefully quiesce the system before resets Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/Kconfig.profile M drivers/gpu/drm/i915/gt/intel_engine_cs.c M drivers/gpu/drm/i915/gt/intel_engine_types.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gt/intel_engine_types.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_engine_types.h Auto-merging drivers/gpu/drm/i915/gt/intel_engine_cs.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_engine_cs.c Auto-merging drivers/gpu/drm/i915/Kconfig.profile error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915/gt: Try to more gracefully quiesce the system before resets When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
Hi RK,
> -Original Message-
> From: Sripada, Radhakrishna
> Sent: Tuesday, October 22, 2019 5:09 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Sripada, Radhakrishna ; Ville Syrjala
> ; Pandiyan, Dhinakaran
> ; Kondapally, Kalyan
> ; Antognolli, Rafael
> ; Chery, Nanley G
> Subject: [PATCH v5 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen
> 12 render compression with Clear Color
>
> Gen12 display can decompress surfaces compressed by render engine with Clear
> Color, add
> a new modifier as the driver needs to know the surface was compressed by
> render engine.
>
> V2: Description changes as suggested by Rafael.
> V3: Mention the Clear Color size of 64 bits in the comments(DK)
> v4: Fix trailing whitespaces
> v5: Explain Clear Color in the documentation.
>
> Cc: Ville Syrjala
> Cc: Dhinakaran Pandiyan
> Cc: Kalyan Kondapally
> Cc: Rafael Antognolli
> Cc: Nanley Chery
> Signed-off-by: Radhakrishna Sripada
> ---
> include/uapi/drm/drm_fourcc.h | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 1aa6d468c048..6b4d36e0ccd0 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -434,6 +434,24 @@ extern "C" {
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
>
> +/*
> + * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render
> compression.
A couple nit-picks here:
- It's not clear to me why "clear color" is capitalized but "color control
surfaces" is not.
- It also isn't clear why "surfaces" is plural here but singular in the
Y_TILED_CCS comment.
- A space is missing between "Color" and "(CCS_CC)".
- Perhaps insert a "with" between "color control surface" and "clear color"?
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC is
> linear
> + * and at index 1. The clear color is stored at index 2, and the pitch should
I thought "CCS_CC" would be referring to the CCS with clear color, not the CCS
by itself. I can't find this term in the BSpec. Perhaps we shouldn't create a
new one here to avoid confusion?
-Nanley
> + * be ignored. The clear color structure is 256 bits. The first 128 bits
> represents
> + * Raw Clear Color Red, Green, Blue and Alpha color each represented by 32
> bits.
> + * The raw clear color is consumed by the 3d engine and generates the
> converted
> + * clear color of size 64 bits. The first 32 bits store the Lower Converted
> Clear
> + * Color value and the next 32 bits store the Higher Converted Clear Color
> value
> + * when applicable. The Converted Clear Color values are consumed by the DE.
> The
> + * last 64 bits are used to store Color Discard Enable and Depth Clear Value
> Valid
> + * which are ignored by the DE. A CCS_CC cache line corresponds to an area
> of 4x1
> + * tiles in the main surface. The main surface pitch is required to be a
> multiple
> + * of 4 tile widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> *
> --
> 2.20.1
>
>
___
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[Intel-gfx] [PATCH] drm/dp: Add function to parse EDID descriptors for adaptive sync limits
Adaptive Sync is a VESA feature so add a DRM core helper to parse
the EDID's detailed descritors to obtain the adaptive sync monitor range.
Store this info as part fo drm_display_info so it can be used
across all drivers.
This part of the code is stripped out of amdgpu's function
amdgpu_dm_update_freesync_caps() to make it generic and be used
across all DRM drivers
Cc: Ville Syrjälä
Cc: Harry Wentland
Cc: Clinton A Taylor
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/drm_edid.c | 49 +
include/drm/drm_connector.h | 25 +++
include/drm/drm_edid.h | 2 ++
3 files changed, 76 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 474ac04d5600..97dd1200773e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4707,6 +4707,52 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
}
}
+void drm_get_adaptive_sync_limits(struct drm_connector *connector,
+ const struct edid *edid)
+{
+ struct drm_display_info *info = >display_info;
+ const struct detailed_timing *timing;
+ const struct detailed_non_pixel *data;
+ const struct detailed_data_monitor_range *range;
+ int i;
+
+ /*
+* Restrict Adaptive Sync only for dp and edp
+*/
+ if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort &&
+ connector->connector_type != DRM_MODE_CONNECTOR_eDP)
+ return;
+
+ if (edid->version <= 1 && !(edid->version == 1 && edid->revision > 1))
+ return;
+
+ for (i = 0; i < 4; i++) {
+ timing = >detailed_timings[i];
+ data= >data.other_data;
+ range = >data.range;
+ /*
+* Check if monitor has continuous frequency mode
+*/
+ if (data->type != EDID_DETAIL_MONITOR_RANGE)
+ continue;
+ /*
+* Check for flag range limits only. If flag == 1 then
+* no additional timing information provided.
+* Default GTF, GTF Secondary curve and CVT are not
+* supported
+*/
+ if (range->flags != 1)
+ continue;
+
+ info->adaptive_sync.min_vfreq = range->min_vfreq;
+ info->adaptive_sync.max_vfreq = range->max_vfreq;
+ info->adaptive_sync.pixel_clock_mhz =
+ range->pixel_clock_mhz * 10;
+ break;
+ }
+}
+EXPORT_SYMBOL(drm_get_adaptive_sync_limits);
+
/* A connector has no EDID information, so we've got no EDID to compute quirks
from. Reset
* all of the values which would have been set from EDID
*/
@@ -4728,6 +4774,7 @@ drm_reset_display_info(struct drm_connector *connector)
memset(>hdmi, 0, sizeof(info->hdmi));
info->non_desktop = 0;
+ memset(>adaptive_sync, 0, sizeof(info->adaptive_sync));
}
u32 drm_add_display_info(struct drm_connector *connector, const struct edid
*edid)
@@ -4743,6 +4790,8 @@ u32 drm_add_display_info(struct drm_connector *connector,
const struct edid *edi
info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
+ drm_get_adaptive_sync_limits(connector, edid);
+
DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
if (edid->revision < 3)
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 5f8c3389d46f..a27a84270d8d 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -254,6 +254,26 @@ enum drm_panel_orientation {
DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
};
+/**
+ * struct drm_adaptive_sync_info - Panel's Adaptive Sync capabilities for
+ * _display_info
+ *
+ * This struct is used to store a Panel's Adaptive Sync capabilities
+ * as parsed from EDID's detailed monitor range descriptor block.
+ *
+ * @min_vfreq: This is the min supported refresh rate in Hz from
+ * EDID's detailed monitor range.
+ * @max_vfreq: This is the max supported refresh rate in Hz from
+ * EDID's detailed monitor range
+ * @pixel_clock_mhz: This is the dotclock in MHz from
+ * EDID's detailed monitor range
+ */
+struct drm_adaptive_sync_info {
+ int min_vfreq;
+ int max_vfreq;
+ int pixel_clock_mhz;
+};
+
/*
* This is a consolidated colorimetry list supported by HDMI and
* DP protocol standard. The respective connectors will register
@@ -465,6 +485,11 @@ struct drm_display_info {
* @non_desktop: Non desktop display (HMD).
*/
bool non_desktop;
+
+ /**
+* @adaptive_sync: Adaptive Sync capabilities of the DP/eDP sink
+*/
+ struct drm_adaptive_sync_info adaptive_sync;
};
int drm_display_info_set_bus_formats(struct drm_display_info *info,
diff --git a/include/drm/drm_edid.h
[Intel-gfx] [PATCH] drm/i915/selftests: Flush any i915_active callback work as well
Make trebly sure that all possible callbacks and their delayed brethren
are complete before asserting that the i915_active should be idle after
flushing all barriers.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
index 9fb5d30c43bb..768f032e6578 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
@@ -55,6 +55,7 @@ static void pulse_unlock_wait(struct pulse *p)
{
mutex_lock(>active.mutex);
mutex_unlock(>active.mutex);
+ flush_work(>active.work);
}
static int __live_idle_pulse(struct intel_engine_cs *engine,
--
2.24.0.rc0
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Re: [Intel-gfx] [PATCH v4] string-choice: add yesno(), onoff(), enableddisabled(), plural() helpers
On Wed, 2019-10-23 at 15:56 -0700, Andrew Morton wrote: > And doing this will cause additional savings: calling a single-arg > out-of-line function generates less .text than calling yesno(). I get no change in size at all with any of extern static __always_inline with either of bool or int argument. gcc 8.3, defconfig with CONFIG_CHELSIO_T4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mdev based hardware virtio offloading support (rev6)
== Series Details == Series: mdev based hardware virtio offloading support (rev6) URL : https://patchwork.freedesktop.org/series/66989/ State : warning == Summary == $ dim checkpatch origin/drm-tip dbcc3602f990 mdev: class id support cdfeed47be7f modpost: add support for mdev class id d18fa8d08a1d mdev: introduce device specific ops -:258: CHECK:LINE_SPACING: Please don't use multiple blank lines #258: FILE: drivers/vfio/mdev/mdev_core.c:48: + -:263: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #263: FILE: drivers/vfio/mdev/mdev_core.c:51: + * provided by each class. */ -:500: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #500: new file mode 100644 total: 0 errors, 2 warnings, 1 checks, 620 lines checked 091ee68346c6 mdev: introduce virtio device and its device ops -:94: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #94: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 223 lines checked 76b1265016b1 virtio: introduce a mdev based transport -:26: WARNING:CONFIG_DESCRIPTION: please write a paragraph that describes the config symbol fully #26: FILE: drivers/virtio/Kconfig:46: +config VIRTIO_MDEV_DEVICE -:46: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #46: new file mode 100644 -:106: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #106: FILE: drivers/virtio/virtio_mdev.c:56: +static void virtio_mdev_get(struct virtio_device *vdev, unsigned offset, -:107: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #107: FILE: drivers/virtio/virtio_mdev.c:57: + void *buf, unsigned len) -:115: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #115: FILE: drivers/virtio/virtio_mdev.c:65: +static void virtio_mdev_set(struct virtio_device *vdev, unsigned offset, -:116: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #116: FILE: drivers/virtio/virtio_mdev.c:66: + const void *buf, unsigned len) -:186: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #186: FILE: drivers/virtio/virtio_mdev.c:136: +virtio_mdev_setup_vq(struct virtio_device *vdev, unsigned index, -:265: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #265: FILE: drivers/virtio/virtio_mdev.c:215: + +} -:297: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #297: FILE: drivers/virtio/virtio_mdev.c:247: +static int virtio_mdev_find_vqs(struct virtio_device *vdev, unsigned nvqs, total: 0 errors, 8 warnings, 1 checks, 430 lines checked e114c74e4182 docs: sample driver to demonstrate how to implement virtio-mdev framework -:39: WARNING:CONFIG_DESCRIPTION: please write a paragraph that describes the config symbol fully #39: FILE: samples/Kconfig:134: +config SAMPLE_VIRTIO_MDEV_NET -:59: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #59: new file mode 100644 -:147: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment #147: FILE: samples/vfio-mdev/mvnet.c:84: + spinlock_t lock; -:180: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #180: FILE: samples/vfio-mdev/mvnet.c:117: + vringh_init_kern(>vring, mvnet_features, MVNET_QUEUE_MAX, + false, 0, 0, 0); -:285: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!addr" #285: FILE: samples/vfio-mdev/mvnet.c:222: + if (addr == NULL) -:288: CHECK:SPACING: No space is necessary after a cast #288: FILE: samples/vfio-mdev/mvnet.c:225: + *dma_addr = (dma_addr_t) addr; -:318: CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*mvnet)...) over kzalloc(sizeof(struct mvnet_state)...) #318: FILE: samples/vfio-mdev/mvnet.c:255: + mvnet = kzalloc(sizeof(struct mvnet_state), GFP_KERNEL); -:319: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!mvnet" #319: FILE: samples/vfio-mdev/mvnet.c:256: + if (mvnet == NULL) -:375: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #375: FILE: samples/vfio-mdev/mvnet.c:312: +sample_mvnet_dev_show(struct device *dev, struct device_attribute *attr, +char *buf) total: 0 errors, 2 warnings, 7 checks, 715 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/dmabuf: Implement pwrite() callback
== Series Details ==
Series: series starting with [1/3] drm/i915/dmabuf: Implement pwrite() callback
URL : https://patchwork.freedesktop.org/series/68428/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14939_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14939_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_selftest@live_gt_heartbeat}:
- shard-apl: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl3/igt@i915_selftest@live_gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14939/shard-apl7/igt@i915_selftest@live_gt_heartbeat.html
Known issues
Here are the changes found in Patchwork_14939_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@vcs1-none:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080])
+1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb1/igt@gem_ctx_isolat...@vcs1-none.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14939/shard-iclb7/igt@gem_ctx_isolat...@vcs1-none.html
* igt@gem_ctx_switch@legacy-bsd1:
- shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb7/igt@gem_ctx_swi...@legacy-bsd1.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14939/shard-iclb7/igt@gem_ctx_swi...@legacy-bsd1.html
* igt@gem_ctx_switch@vcs1:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112080]) +9 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb1/igt@gem_ctx_swi...@vcs1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14939/shard-iclb7/igt@gem_ctx_swi...@vcs1.html
* igt@gem_eio@reset-stress:
- shard-snb: [PASS][9] -> [FAIL][10] ([fdo#109661])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb2/igt@gem_...@reset-stress.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14939/shard-snb1/igt@gem_...@reset-stress.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +11 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_exec_sched...@out-order-bsd2.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14939/shard-iclb8/igt@gem_exec_sched...@out-order-bsd2.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#111325]) +2 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb8/igt@gem_exec_sched...@preemptive-hang-bsd.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14939/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html
* igt@gem_linear_blits@interruptible:
- shard-apl: [PASS][15] -> [INCOMPLETE][16] ([fdo#103927] /
[fdo#112067])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl7/igt@gem_linear_bl...@interruptible.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14939/shard-apl4/igt@gem_linear_bl...@interruptible.html
*
igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
- shard-hsw: [PASS][17] -> [TIMEOUT][18] ([fdo#112068 ])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw6/igt@gem_persistent_rel...@forked-interruptible-faulting-reloc-thrash-inactive.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14939/shard-hsw4/igt@gem_persistent_rel...@forked-interruptible-faulting-reloc-thrash-inactive.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) +1
similar issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14939/shard-snb1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
- shard-hsw: [PASS][21] -> [DMESG-WARN][22] ([fdo#111870]) +1
similar issue
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14939/shard-hsw7/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-kbl: [PASS][23] -> [INCOMPLETE][24] ([fdo#103665] /
[fdo#107807])
[23]:
Re: [Intel-gfx] [CI 4/4] drm/i915/gem: Cancel contexts when hangchecking is disabled
Quoting Kumar Valsan, Prathap (2019-10-24 00:26:06) > On Wed, Oct 23, 2019 at 01:21:51PM +0100, Chris Wilson wrote: > > + > > + /* > > + * If the user has disabled hangchecking, we can not be sure that > > + * the batches will ever complete after the context is closed, > > + * keeping the context and all resources pinned forever. So in this > > + * case we opt to forcibly kill off all remaining requests on > > + * context close. > > + */ > > + if (!i915_modparams.enable_hangcheck) > > + kill_context(ctx); > > Why not killing the context always when a context is closed? Because we historically have not and so desktop userspace has come to depend on that behaviour (think one client handing over a framebuffer to the display server with pending rendering). > When hang_check is enabled, how would it know the context is closed and > we should release its resources, unless and untill the context has > hanged? Exactly. The contexts persist until complete. The same dos prevention rules apply to the outstanding work as applied when the context was open. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Flush interrupts before disabling tasklets
When setting up the system to perform the atomic reset, we need to
serialise with any ongoing interrupt tasklet or else:
<0> [472.951428] i915_sel-44420d..1 466527056us : __i915_request_submit:
rcs0 fence 11659:2, current 0
<0> [472.951554] i915_sel-44420d..1 466527059us :
__execlists_submission_tasklet: rcs0: queue_priority_hint:-2147483648,
submit:yes
<0> [472.951681] i915_sel-44420d..1 466527061us : trace_ports: rcs0: submit
{ 11659:2, 0:0 }
<0> [472.951805] i915_sel-44420 466527114us :
__igt_atomic_reset_engine: i915_reset_engine(rcs0:active) under hardirq
<0> [472.951932] i915_sel-44420d... 466527115us : intel_engine_reset: rcs0
flags=11d
<0> [472.952056] i915_sel-44420d... 466527117us : execlists_reset_prepare:
rcs0: depth<-1
<0> [472.952179] i915_sel-44420d... 466527119us : intel_engine_stop_cs: rcs0
<0> [472.952305] -0 1..s1 466527119us : process_csb: rcs0 cs-irq
head=3, tail=4
<0> [472.952431] i915_sel-44420d... 466527122us : __intel_gt_reset:
engine_mask=1
<0> [472.952557] -0 1..s1 466527124us : process_csb: rcs0 csb[4]:
status=0x0001:0x
<0> [472.952683] -0 1..s1 466527130us : trace_ports: rcs0:
promote { 11659:2*, 0:0 }
<0> [472.952808] i915_sel-44420d... 466527131us : execlists_reset: rcs0
<0> [472.952933] i915_sel-44420d..1 466527133us : process_csb: rcs0 cs-irq
head=3, tail=4
<0> [472.953059] i915_sel-44420d..1 466527134us : process_csb: rcs0 csb[4]:
status=0x0001:0x
<0> [472.953185] i915_sel-44420d..1 466527136us : trace_ports: rcs0:
preempted { 11659:2*, 0:0 }
<0> [472.953310] i915_sel-44420d..1 466527150us : assert_pending_valid:
Nothing pending for promotion!
<0> [472.953436] i915_sel-44420d..1 466527158us : process_csb:
process_csb:1930 GEM_BUG_ON(!assert_pending_valid(execlists, "promote"))
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112069
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index b892b47348ab..ba761fcf397b 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1563,7 +1563,7 @@ static int __igt_atomic_reset_engine(struct
intel_engine_cs *engine,
GEM_TRACE("i915_reset_engine(%s:%s) under %s\n",
engine->name, mode, p->name);
- tasklet_disable_nosync(t);
+ tasklet_disable(t);
p->critical_section_begin();
err = intel_engine_reset(engine, NULL);
diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c
b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 6efb9221b7fa..6ad6aca315f6 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -126,7 +126,7 @@ static int igt_atomic_engine_reset(void *arg)
goto out_unlock;
for_each_engine(engine, gt, id) {
- tasklet_disable_nosync(>execlists.tasklet);
+ tasklet_disable(>execlists.tasklet);
intel_engine_pm_get(engine);
for (p = igt_atomic_phases; p->name; p++) {
--
2.24.0.rc0
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Re: [Intel-gfx] [CI 4/4] drm/i915/gem: Cancel contexts when hangchecking is disabled
On Wed, Oct 23, 2019 at 01:21:51PM +0100, Chris Wilson wrote:
> Normally, we rely on our hangcheck to prevent persistent batches from
> hogging the GPU. However, if the user disables hangcheck, this mechanism
> breaks down. Despite our insistence that this is unsafe, the users are
> equally insistent that they want to use endless batches and will disable
> the hangcheck mechanism. We are looking at replacing hangcheck, in the
> next patch, with a softer mechanism, that sends a pulse down the engine
> to check if it is well. We can use the same preemptive pulse to flush an
> active context off the GPU upon context close, preventing resources
> being lost and unkillable requests remaining on the GPU after process
> termination.
>
> Testcase: igt/gem_ctx_exec/basic-nohangcheck
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Michał Winiarski
> Cc: Jon Bloomfield
> Reviewed-by: Jon Bloomfield
> Reviewed-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 141
> 1 file changed, 141 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 7b01f4605f21..b2f042d87be0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -70,6 +70,7 @@
> #include
>
> #include "gt/intel_lrc_reg.h"
> +#include "gt/intel_engine_heartbeat.h"
> #include "gt/intel_engine_user.h"
>
> #include "i915_gem_context.h"
> @@ -276,6 +277,135 @@ void i915_gem_context_release(struct kref *ref)
> schedule_work(>free_work);
> }
>
> +static inline struct i915_gem_engines *
> +__context_engines_static(const struct i915_gem_context *ctx)
> +{
> + return rcu_dereference_protected(ctx->engines, true);
> +}
> +
> +static bool __reset_engine(struct intel_engine_cs *engine)
> +{
> + struct intel_gt *gt = engine->gt;
> + bool success = false;
> +
> + if (!intel_has_reset_engine(gt))
> + return false;
> +
> + if (!test_and_set_bit(I915_RESET_ENGINE + engine->id,
> + >reset.flags)) {
> + success = intel_engine_reset(engine, NULL) == 0;
> + clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
> + >reset.flags);
> + }
> +
> + return success;
> +}
> +
> +static void __reset_context(struct i915_gem_context *ctx,
> + struct intel_engine_cs *engine)
> +{
> + intel_gt_handle_error(engine->gt, engine->mask, 0,
> + "context closure in %s", ctx->name);
> +}
> +
> +static bool __cancel_engine(struct intel_engine_cs *engine)
> +{
> + /*
> + * Send a "high priority pulse" down the engine to cause the
> + * current request to be momentarily preempted. (If it fails to
> + * be preempted, it will be reset). As we have marked our context
> + * as banned, any incomplete request, including any running, will
> + * be skipped following the preemption.
> + *
> + * If there is no hangchecking (one of the reasons why we try to
> + * cancel the context) and no forced preemption, there may be no
> + * means by which we reset the GPU and evict the persistent hog.
> + * Ergo if we are unable to inject a preemptive pulse that can
> + * kill the banned context, we fallback to doing a local reset
> + * instead.
> + */
> + if (CONFIG_DRM_I915_PREEMPT_TIMEOUT && !intel_engine_pulse(engine))
> + return true;
> +
> + /* If we are unable to send a pulse, try resetting this engine. */
> + return __reset_engine(engine);
> +}
> +
> +static struct intel_engine_cs *
> +active_engine(struct dma_fence *fence, struct intel_context *ce)
> +{
> + struct i915_request *rq = to_request(fence);
> + struct intel_engine_cs *engine, *locked;
> +
> + /*
> + * Serialise with __i915_request_submit() so that it sees
> + * is-banned?, or we know the request is already inflight.
> + */
> + locked = READ_ONCE(rq->engine);
> + spin_lock_irq(>active.lock);
> + while (unlikely(locked != (engine = READ_ONCE(rq->engine {
> + spin_unlock(>active.lock);
> + spin_lock(>active.lock);
> + locked = engine;
> + }
> +
> + engine = NULL;
> + if (i915_request_is_active(rq) && !rq->fence.error)
> + engine = rq->engine;
> +
> + spin_unlock_irq(>active.lock);
> +
> + return engine;
> +}
> +
> +static void kill_context(struct i915_gem_context *ctx)
> +{
> + struct i915_gem_engines_iter it;
> + struct intel_context *ce;
> +
> + /*
> + * If we are already banned, it was due to a guilty request causing
> + * a reset and the entire context being evicted from the GPU.
> + */
> + if (i915_gem_context_is_banned(ctx))
> + return;
> +
> + i915_gem_context_set_banned(ctx);
> +
> + /*
> + * Map the
[Intel-gfx] [PATCH 2/8] drm/i915: Put future HW and their uAPIs under STAGING & BROKEN
We would like some freedom to break the user API/ABI for future HW but yet still expose the driver for upstream development on that HW. Currently, we have the i915.force_probe module parameter to avoid binding to HW while the driver is under development, but that is still a little too soft with respect to the stringent no-regression rules if we also plan to be redesigning the uAPI to go along with the new HW. To allow the uAPI to be changed during development, only expose that API and in development HW under STAGING (and BROKEN). Hopefully, making it explicit that such interfaces to that HW are under development and not to be blindly enabled by distributions. Signed-off-by: Chris Wilson Cc: Daniel Vetter Cc: Joonas Lahtinen Cc: Jani Nikula Cc: Rodrigo Vivi Cc: Dave Airlie --- drivers/gpu/drm/i915/Kconfig | 8 drivers/gpu/drm/i915/Kconfig.debug| 1 + drivers/gpu/drm/i915/Kconfig.unstable | 20 3 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/i915/Kconfig.unstable diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 3c6d57df262d..1fd9e665b742 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -148,3 +148,11 @@ menu "drm/i915 Profile Guided Optimisation" depends on DRM_I915 source "drivers/gpu/drm/i915/Kconfig.profile" endmenu + +menu "drm/i915 Ustable Evolution" + visible if EXPERT + visible if STAGING + visible if BROKEN + depends on DRM_I915 + source "drivers/gpu/drm/i915/Kconfig.unstable" +endmenu diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug index d2ba8f7e5e50..ef123eb29168 100644 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -44,6 +44,7 @@ config DRM_I915_DEBUG select DRM_I915_SELFTEST select DRM_I915_DEBUG_RUNTIME_PM select DRM_I915_DEBUG_MMIO + select BROKEN # for prototype uAPI default n help Choose this option to turn on extra driver debugging that may affect diff --git a/drivers/gpu/drm/i915/Kconfig.unstable b/drivers/gpu/drm/i915/Kconfig.unstable new file mode 100644 index ..ecc8458b5a32 --- /dev/null +++ b/drivers/gpu/drm/i915/Kconfig.unstable @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-only +config DRM_I915_UNSTABLE + bool "Enable unstable API for early prototype development" + depends on EXPERT + depends on STAGING + depends on BROKEN # should never be enabled by distros! + # We use the dependency on !COMPILE_TEST to not be enabled in + # allmodconfig or allyesconfig configurations + depends on !COMPILE_TEST + default n + help + Enable prototype uAPI under general discussion before they are + finalized. Such prototypes may be withdrawn or substantially + changed before release. They are only enabled here so that a wide + number of interested parties (userspace driver developers) can + verify that the uAPI meet their expectations. + + Recommended for driver developers _only_. + + If in the slightest bit of doubt, say "N". -- 2.24.0.rc0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/8] drm/i915/gt: Expose engine->mmio_base via sysfs
Use the per-engine sysfs directory to let userspace discover the
mmio_base of each engine. Prior to recent generations, the user
accessible registers on each engine are at a fixed offset relative to
each engine -- but require absolute addressing. As the absolute address
depends on the actual physical engine, this is not always possible to
determine from userspace (for example icl may expose vcs1 or vcs2 as the
second vcs engine). Make this easy for userspace to discover by
providing the mmio_base in sysfs.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
index df263af3a9ea..abddd8d0f9ae 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
@@ -48,6 +48,15 @@ inst_show(struct kobject *kobj, struct kobj_attribute *attr,
char *buf)
static struct kobj_attribute inst_attr =
__ATTR(instance, 0444, inst_show, NULL);
+static ssize_t
+mmio_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ return sprintf(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base);
+}
+
+static struct kobj_attribute mmio_attr =
+__ATTR(mmio_base, 0444, mmio_show, NULL);
+
static const char * const vcs_caps[] = {
[ilog2(I915_VIDEO_CLASS_CAPABILITY_HEVC)] = "hevc",
[ilog2(I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC)] = "sfc",
@@ -170,6 +179,7 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915)
_attr.attr,
_attr.attr,
_attr.attr,
+ _attr.attr,
_attr.attr,
_caps_attr.attr,
NULL
--
2.24.0.rc0
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[Intel-gfx] [PATCH 8/8] drm/i915/gt: Expose heartbeat interval via sysfs
We monitor the health of the system via periodic heartbeat pulses. The
pulses also provide the opportunity to perform garbage collection.
However, we interpret an incomplete pulse (a missed heartbeat) as an
indication that the system is no longer responsive, i.e. hung, and
perform an engine or full GPU reset. Given that the preemption
granularity can be very coarse on a system, we let the sysadmin override
our legacy timeouts which were "optimised" for desktop applications.
The heartbeat interval can be adjusted per-engine using,
/sys/class/drm/card?/engine/*/heartbeat_interval_ms
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Kconfig.profile | 3 ++
drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 37
2 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index 066ea9ba2756..aad214d3160d 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -20,6 +20,9 @@ config DRM_I915_HEARTBEAT_INTERVAL
check the health of the GPU and undertake regular house-keeping of
internal driver state.
+ This is adjustable via
+ /sys/class/drm/card?/engine/*/heartbeat_interval_ms
+
May be 0 to disable heartbeats and therefore disable automatic GPU
hang detection.
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
index 1c726a758b32..49f000f07ee3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
@@ -9,6 +9,7 @@
#include "i915_drv.h"
#include "intel_engine.h"
+#include "intel_engine_heartbeat.h"
#include "intel_engine_sysfs.h"
struct kobj_engine {
@@ -241,6 +242,39 @@ preempt_timeout_store(struct kobject *kobj, struct
kobj_attribute *attr,
static struct kobj_attribute preempt_timeout_attr =
__ATTR(preempt_timeout_ms, 0644, preempt_timeout_show, preempt_timeout_store);
+static ssize_t
+heartbeat_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+
+ return sprintf(buf, "%lu\n", engine->props.heartbeat_interval_ms);
+}
+
+static ssize_t
+heartbeat_store(struct kobject *kobj, struct kobj_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+ unsigned long long delay;
+ int err;
+
+ err = kstrtoull(buf, 0, );
+ if (err)
+ return err;
+
+ if (delay >= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT))
+ return -EINVAL;
+
+ err = intel_engine_set_heartbeat(engine, delay);
+ if (err)
+ return err;
+
+ return count;
+}
+
+static struct kobj_attribute heartbeat_interval_attr =
+__ATTR(heartbeat_interval_ms, 0644, heartbeat_show, heartbeat_store);
+
static void kobj_engine_release(struct kobject *kobj)
{
kfree(kobj);
@@ -282,6 +316,9 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915)
_attr.attr,
_caps_attr.attr,
_timeout_attr.attr,
+#if CONFIG_DRM_I915_HEARTBEAT_INTERVAL
+ _interval_attr.attr,
+#endif
NULL
};
--
2.24.0.rc0
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[Intel-gfx] [PATCH 5/8] drm/i915/gt: Expose timeslice duration to sysfs
Execlists uses a scheduling quantum (a timeslice) to alternate execution
between ready-to-run contexts of equal priority. This ensures that all
users (though only if they of equal importance) have the opportunity to
run and prevents livelocks where contexts may have implicit ordering due
to userspace semaphores.
The timeslicing mechanism can be compiled out with
./scripts/config --set-val DRM_I915_TIMESLICE_DURATION 0
The timeslice duration can be adjusted per-engine using,
/sys/class/drm/card?/engine/*/timeslice_duration_ms
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/Kconfig.profile | 18 +
drivers/gpu/drm/i915/gt/intel_engine.h | 9 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 +
drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 38 +++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 39 ++--
drivers/gpu/drm/i915/gt/selftest_lrc.c | 13 ++-
7 files changed, 106 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index 8ab7af5eb311..b87c8f485a24 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -59,3 +59,21 @@ config DRM_I915_STOP_TIMEOUT
damage as the system is reset in order to recover. The corollary is
that the reset itself may take longer and so be more disruptive to
interactive or low latency workloads.
+
+config DRM_I915_TIMESLICE_DURATION
+ int "Scheduling quantum for userspace batches (ms, jiffy granularity)"
+ default 1 # milliseconds
+ help
+ When two user batches of equal priority are executing, we will
+ alternate execution of each batch to ensure forward progress of
+ all users. This is necessary in some cases where there may be
+ an implicit dependency between those batches that requires
+ concurrent execution in order for them to proceed, e.g. they
+ interact with each other via userspace semaphores. Each context
+ is scheduled for execution for the timeslice duration, before
+ switching to the next context.
+
+ This is adjustable via
+ /sys/class/drm/card?/engine/*/timeslice_duration_ms
+
+ May be 0 to disable timeslicing.
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index ee47444a6ad4..c7f93d05c8e0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -504,4 +504,13 @@ intel_engine_has_preempt_reset(const struct
intel_engine_cs *engine)
return intel_engine_has_preemption(engine);
}
+static inline bool
+intel_engine_has_timeslices(const struct intel_engine_cs *engine)
+{
+ if (!CONFIG_DRM_I915_TIMESLICE_DURATION)
+ return 0;
+
+ return intel_engine_has_semaphores(engine);
+}
+
#endif /* _INTEL_RINGBUFFER_H_ */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 8b5129e0b49d..cd4caf54c59c 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -314,6 +314,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
CONFIG_DRM_I915_PREEMPT_TIMEOUT;
engine->props.stop_timeout_ms =
CONFIG_DRM_I915_STOP_TIMEOUT;
+ engine->props.timeslice_duration_ms =
+ CONFIG_DRM_I915_TIMESLICE_DURATION;
/*
* To be overridden by the backend on setup. However to facilitate
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
index abddd8d0f9ae..b696b1be2d16 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
@@ -142,6 +142,40 @@ all_caps_show(struct kobject *kobj, struct kobj_attribute
*attr, char *buf)
static struct kobj_attribute all_caps_attr =
__ATTR(known_capabilities, 0444, all_caps_show, NULL);
+static ssize_t
+timeslice_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+
+ return sprintf(buf, "%lu\n", engine->props.timeslice_duration_ms);
+}
+
+static ssize_t
+timeslice_store(struct kobject *kobj, struct kobj_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+ unsigned long long duration;
+ int err;
+
+ err = kstrtoull(buf, 0, );
+ if (err)
+ return err;
+
+ if (duration > jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT))
+ return -EINVAL;
+
+ WRITE_ONCE(engine->props.timeslice_duration_ms, duration);
+
+ if (execlists_active(>execlists))
+ set_timer_ms(>execlists.timer, duration);
+
+ return
[Intel-gfx] [PATCH 6/8] drm/i915/gt: Expose reset stop timeout via sysfs
When we allow ourselves to sleep before a GPU reset after disabling
submission, even for a few milliseconds, gives an innocent context the
opportunity to clear the GPU before the reset occurs. However, how long
to sleep depends on the typical non-preemptible duration (a similar
problem to determining the ideal preempt-reset timeout or even the
heartbeat interval). As this seems of a hard policy decision, punt it to
userspace.
The timeout can be adjusted using
/sys/class/drm/card?/engine/*/stop_timeout_ms
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
---
drivers/gpu/drm/i915/Kconfig.profile | 3 ++
drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 31
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index b87c8f485a24..76145d25ce65 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -60,6 +60,9 @@ config DRM_I915_STOP_TIMEOUT
that the reset itself may take longer and so be more disruptive to
interactive or low latency workloads.
+ This is adjustable via
+ /sys/class/drm/card?/engine/*/stop_timeout_ms
+
config DRM_I915_TIMESLICE_DURATION
int "Scheduling quantum for userspace batches (ms, jiffy granularity)"
default 1 # milliseconds
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
index b696b1be2d16..e4f557098e9a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
@@ -176,6 +176,36 @@ timeslice_store(struct kobject *kobj, struct
kobj_attribute *attr,
static struct kobj_attribute timeslice_duration_attr =
__ATTR(timeslice_duration_ms, 0644, timeslice_show, timeslice_store);
+static ssize_t
+stop_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+
+ return sprintf(buf, "%lu\n", engine->props.stop_timeout_ms);
+}
+
+static ssize_t
+stop_store(struct kobject *kobj, struct kobj_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+ unsigned long long duration;
+ int err;
+
+ err = kstrtoull(buf, 0, );
+ if (err)
+ return err;
+
+ if (duration > jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT))
+ return -EINVAL;
+
+ WRITE_ONCE(engine->props.stop_timeout_ms, duration);
+ return count;
+}
+
+static struct kobj_attribute stop_timeout_attr =
+__ATTR(stop_timeout_ms, 0644, stop_show, stop_store);
+
static void kobj_engine_release(struct kobject *kobj)
{
kfree(kobj);
@@ -216,6 +246,7 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915)
_attr.attr,
_attr.attr,
_caps_attr.attr,
+ _timeout_attr.attr,
NULL
};
--
2.24.0.rc0
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[Intel-gfx] [PATCH 3/8] drm/i915/gt: Expose engine properties via sysfs
Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
that we can expose properties on each engine to the sysadmin.
To start with we have basic analogues of the i915_query ioctl so that we
can pretty print engine discovery from the shell, and flesh out the
directory structure. Later we will add writeable sysadmin properties such
as per-engine timeout controls.
An example tree of the engine properties on Braswell:
/sys/class/drm/card0
└── engine
├── bcs0
│ ├── capabilities
│ ├── class
│ ├── instance
│ ├── known_capabilities
│ └── name
├── rcs0
│ ├── capabilities
│ ├── class
│ ├── instance
│ ├── known_capabilities
│ └── name
├── vcs0
│ ├── capabilities
│ ├── class
│ ├── instance
│ ├── known_capabilities
│ └── name
└── vecs0
├── capabilities
├── class
├── instance
├── known_capabilities
└── name
v2: Include stringified capabilities
v3: Include all known capabilities for futureproofing.
v4: Combine the two caps loops into one
v5: Hide underneath Kconfig.unstable for wider discussion
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Acked-by: Rodrigo Vivi
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/Kconfig.unstable| 7 +
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 208 +++
drivers/gpu/drm/i915/gt/intel_engine_sysfs.h | 14 ++
drivers/gpu/drm/i915/i915_sysfs.c| 3 +
5 files changed, 233 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_sysfs.h
diff --git a/drivers/gpu/drm/i915/Kconfig.unstable
b/drivers/gpu/drm/i915/Kconfig.unstable
index ecc8458b5a32..a0e9adfdd8eb 100644
--- a/drivers/gpu/drm/i915/Kconfig.unstable
+++ b/drivers/gpu/drm/i915/Kconfig.unstable
@@ -18,3 +18,10 @@ config DRM_I915_UNSTABLE
Recommended for driver developers _only_.
If in the slightest bit of doubt, say "N".
+
+config DRM_I915_UNSTABLE_SYSFS
+ bool "Enable the experimental sysfs properties"
+ depends on DRM_I915_UNSTABLE
+ default n
+ help
+ Explore the HW property space from the shell command line!
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 21601bb27b22..a91e0a487a79 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -81,6 +81,7 @@ gt-y += \
gt/intel_engine_heartbeat.o \
gt/intel_engine_pm.o \
gt/intel_engine_pool.o \
+ gt/intel_engine_sysfs.o \
gt/intel_engine_user.o \
gt/intel_gt.o \
gt/intel_gt_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
new file mode 100644
index ..df263af3a9ea
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
@@ -0,0 +1,208 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include
+#include
+
+#include "i915_drv.h"
+#include "intel_engine.h"
+#include "intel_engine_sysfs.h"
+
+struct kobj_engine {
+ struct kobject base;
+ struct intel_engine_cs *engine;
+};
+
+static struct intel_engine_cs *kobj_to_engine(struct kobject *kobj)
+{
+ return container_of(kobj, struct kobj_engine, base)->engine;
+}
+
+static ssize_t
+name_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%s\n", kobj_to_engine(kobj)->name);
+}
+
+static struct kobj_attribute name_attr =
+__ATTR(name, 0444, name_show, NULL);
+
+static ssize_t
+class_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", kobj_to_engine(kobj)->uabi_class);
+}
+
+static struct kobj_attribute class_attr =
+__ATTR(class, 0444, class_show, NULL);
+
+static ssize_t
+inst_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", kobj_to_engine(kobj)->uabi_instance);
+}
+
+static struct kobj_attribute inst_attr =
+__ATTR(instance, 0444, inst_show, NULL);
+
+static const char * const vcs_caps[] = {
+ [ilog2(I915_VIDEO_CLASS_CAPABILITY_HEVC)] = "hevc",
+ [ilog2(I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC)] = "sfc",
+};
+
+static const char * const vecs_caps[] = {
+ [ilog2(I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC)] = "sfc",
+};
+
+static ssize_t repr_trim(char *buf, ssize_t len)
+{
+ /* Trim off the trailing space and replace with a newline */
+ if (len > PAGE_SIZE)
+ len = PAGE_SIZE;
+ if (len > 0)
+ buf[len - 1] = '\n';
+
+ return len;
+}
+
+static ssize_t
+__caps_show(struct intel_engine_cs *engine,
+
[Intel-gfx] [PATCH 1/8] drm/i915/gem: Make context persistence optional
Our existing behaviour is to allow contexts and their GPU requests to
persist past the point of closure until the requests are complete. This
allows clients to operate in a 'fire-and-forget' manner where they can
setup a rendering pipeline and hand it over to the display server and
immediately exiting. As the rendering pipeline is kept alive until
completion, the display server (or other consumer) can use the results
in the future and present them to the user.
However, not all clients want this persistent behaviour and would prefer
that the contexts are cleaned up immediately upon closure. This ensures
that when clients are run without hangchecking, any GPU hang is
terminated with the process and does not continue to hog resources.
By defining a context property to allow clients to control persistence
explicitly, we can remove the blanket advice to disable hangchecking
that seems to be far too prevalent.
The default behaviour for new controls is the legacy persistence mode.
New clients will have to opt out for immediate cleanup on context
closure. If the hangchecking modparam is disabled, so is persistent
context support -- all contexts will be terminated on closure.
Testcase: igt/gem_ctx_persistence
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michał Winiarski
Cc: Jon Bloomfield
Reviewed-by: Jon Bloomfield
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 50 ++-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 15 ++
.../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
.../gpu/drm/i915/gem/selftests/mock_context.c | 2 +
include/uapi/drm/i915_drm.h | 15 ++
5 files changed, 82 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index b2f042d87be0..f92fa04c8e4a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -436,12 +436,39 @@ static void context_close(struct i915_gem_context *ctx)
* case we opt to forcibly kill off all remaining requests on
* context close.
*/
- if (!i915_modparams.enable_hangcheck)
+ if (!i915_gem_context_is_persistent(ctx) ||
+ !i915_modparams.enable_hangcheck)
kill_context(ctx);
i915_gem_context_put(ctx);
}
+static int __context_set_persistence(struct i915_gem_context *ctx, bool state)
+{
+ if (i915_gem_context_is_persistent(ctx) == state)
+ return 0;
+
+ if (state) {
+ /*
+* Only contexts that are short-lived [that will expire or be
+* reset] are allowed to survive past termination. We require
+* hangcheck to ensure that the persistent requests are healthy.
+*/
+ if (!i915_modparams.enable_hangcheck)
+ return -EINVAL;
+
+ i915_gem_context_set_persistence(ctx);
+ } else {
+ /* To cancel a context we use "preempt-to-idle" */
+ if (!(ctx->i915->caps.scheduler &
I915_SCHEDULER_CAP_PREEMPTION))
+ return -ENODEV;
+
+ i915_gem_context_clear_persistence(ctx);
+ }
+
+ return 0;
+}
+
static struct i915_gem_context *
__create_context(struct drm_i915_private *i915)
{
@@ -476,6 +503,7 @@ __create_context(struct drm_i915_private *i915)
i915_gem_context_set_bannable(ctx);
i915_gem_context_set_recoverable(ctx);
+ __context_set_persistence(ctx, true /* cgroup hook? */);
for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
@@ -632,6 +660,7 @@ i915_gem_context_create_kernel(struct drm_i915_private
*i915, int prio)
return ctx;
i915_gem_context_clear_bannable(ctx);
+ i915_gem_context_set_persistence(ctx);
ctx->sched.priority = I915_USER_PRIORITY(prio);
GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
@@ -1742,6 +1771,16 @@ get_engines(struct i915_gem_context *ctx,
return err;
}
+static int
+set_persistence(struct i915_gem_context *ctx,
+ const struct drm_i915_gem_context_param *args)
+{
+ if (args->size)
+ return -EINVAL;
+
+ return __context_set_persistence(ctx, args->value);
+}
+
static int ctx_setparam(struct drm_i915_file_private *fpriv,
struct i915_gem_context *ctx,
struct drm_i915_gem_context_param *args)
@@ -1819,6 +1858,10 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
ret = set_engines(ctx, args);
break;
+ case I915_CONTEXT_PARAM_PERSISTENCE:
+ ret = set_persistence(ctx, args);
+ break;
+
case I915_CONTEXT_PARAM_BAN_PERIOD:
default:
ret = -EINVAL;
@@ -2271,6 +2314,11 @@ int
[Intel-gfx] [PATCH 7/8] drm/i915/gt: Expose preempt reset timeout via sysfs
After initialising a preemption request, we give the current resident a
small amount of time to vacate the GPU. The preemption request is for a
higher priority context and should be immediate to maintain high
quality of service (and avoid priority inversion). However, the
preemption granularity of the GPU can be quite coarse and so we need a
compromise.
The preempt timeout can be adjusted per-engine using,
/sys/class/drm/card?/engine/*/preempt_timeout_ms
and can be disabled by setting it to 0.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Kconfig.profile | 3 ++
drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 39
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index 76145d25ce65..066ea9ba2756 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -33,6 +33,9 @@ config DRM_I915_PREEMPT_TIMEOUT
expires, the HW will be reset to allow the more important context
to execute.
+ This is adjustable via
+ /sys/class/drm/card?/engine/*/preempt_timeout_ms
+
May be 0 to disable the timeout.
config DRM_I915_SPIN_REQUEST
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
index e4f557098e9a..1c726a758b32 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
@@ -206,6 +206,41 @@ stop_store(struct kobject *kobj, struct kobj_attribute
*attr,
static struct kobj_attribute stop_timeout_attr =
__ATTR(stop_timeout_ms, 0644, stop_show, stop_store);
+static ssize_t
+preempt_timeout_show(struct kobject *kobj, struct kobj_attribute *attr,
+char *buf)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+
+ return sprintf(buf, "%lu\n", engine->props.preempt_timeout_ms);
+}
+
+static ssize_t
+preempt_timeout_store(struct kobject *kobj, struct kobj_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct intel_engine_cs *engine = kobj_to_engine(kobj);
+ unsigned long long timeout;
+ int err;
+
+ err = kstrtoull(buf, 0, );
+ if (err)
+ return err;
+
+ if (timeout > jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT))
+ return -EINVAL;
+
+ WRITE_ONCE(engine->props.preempt_timeout_ms, timeout);
+
+ if (READ_ONCE(engine->execlists.pending[0]))
+ set_timer_ms(>execlists.preempt, timeout);
+
+ return count;
+}
+
+static struct kobj_attribute preempt_timeout_attr =
+__ATTR(preempt_timeout_ms, 0644, preempt_timeout_show, preempt_timeout_store);
+
static void kobj_engine_release(struct kobject *kobj)
{
kfree(kobj);
@@ -275,6 +310,10 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915)
sysfs_create_file(kobj, _duration_attr.attr))
goto err_engine;
+ if (intel_engine_has_preempt_reset(engine) &&
+ sysfs_create_file(kobj, _timeout_attr.attr))
+ goto err_engine;
+
if (0) {
err_object:
kobject_put(kobj);
--
2.24.0.rc0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4] string-choice: add yesno(), onoff(), enableddisabled(), plural() helpers
On Wed, 23 Oct 2019 16:13:08 +0300 Jani Nikula wrote:
> The kernel has plenty of ternary operators to choose between constant
> strings, such as condition ? "yes" : "no", as well as value == 1 ? "" :
> "s":
>
> $ git grep '? "yes" : "no"' | wc -l
> 258
> $ git grep '? "on" : "off"' | wc -l
> 204
> $ git grep '? "enabled" : "disabled"' | wc -l
> 196
> $ git grep '? "" : "s"' | wc -l
> 25
>
> Additionally, there are some occurences of the same in reverse order,
> split to multiple lines, or otherwise not caught by the simple grep.
>
> Add helpers to return the constant strings. Remove existing equivalent
> and conflicting functions in i915, cxgb4, and USB core. Further
> conversion can be done incrementally.
>
> The main goal here is to abstract recurring patterns, and slightly clean
> up the code base by not open coding the ternary operators.
Fair enough.
> --- /dev/null
> +++ b/include/linux/string-choice.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#ifndef __STRING_CHOICE_H__
> +#define __STRING_CHOICE_H__
> +
> +#include
> +
> +static inline const char *yesno(bool v)
> +{
> + return v ? "yes" : "no";
> +}
> +
> +static inline const char *onoff(bool v)
> +{
> + return v ? "on" : "off";
> +}
> +
> +static inline const char *enableddisabled(bool v)
> +{
> + return v ? "enabled" : "disabled";
> +}
> +
> +static inline const char *plural(long v)
> +{
> + return v == 1 ? "" : "s";
> +}
> +
> +#endif /* __STRING_CHOICE_H__ */
These aren't very good function names. Better to create a kernel-style
namespace such as "choice_" and then add the expected underscores:
choice_yes_no()
choice_enabled_disabled()
choice_plural()
(Example: note that slabinfo.c already has an "onoff()").
Also, I worry that making these functions inline means that each .o
file will contain its own copy of the strings ("yes", "no", "enabled",
etc) if the .c file calls the relevant helper. I'm not sure if the
linker is smart enough (yet) to fix this up. If not, we will end up
with a smaller kernel by uninlining these functions.
lib/string-choice.c would suit.
And doing this will cause additional savings: calling a single-arg
out-of-line function generates less .text than calling yesno(). When I
did this:
---
a/include/linux/string-choice.h~string-choice-add-yesno-onoff-enableddisabled-plural-helpers-fix
+++ a/include/linux/string-choice.h
@@ -8,10 +8,7 @@
#include
-static inline const char *yesno(bool v)
-{
- return v ? "yes" : "no";
-}
+const char *yesno(bool v);
static inline const char *onoff(bool v)
{
The text segment of drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.o
(78 callsites) shrunk by 118 bytes.
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/3] drm/i915/guc: Enable guc logging on guc log relay write
On 10/23/19 8:14 AM, Patchwork wrote:
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/guc: Enable guc logging on guc
log relay write
URL : https://patchwork.freedesktop.org/series/68406/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14932_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_14932_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14932_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14932_full:
### IGT changes ###
Warnings
* igt@i915_pm_rc6_residency@media-rc6-accuracy:
- shard-iclb: [SKIP][1] ([fdo#109289]) -> [SKIP][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb8/igt@i915_pm_rc6_reside...@media-rc6-accuracy.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-iclb1/igt@i915_pm_rc6_reside...@media-rc6-accuracy.html
This signature has shown up on other runs, so not caused by this series.
Patches pushed.
Daniele
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_fence_thrash@bo-write-verify-threaded-y:
- {shard-tglb}: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb6/igt@gem_fence_thr...@bo-write-verify-threaded-y.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-tglb6/igt@gem_fence_thr...@bo-write-verify-threaded-y.html
Known issues
Here are the changes found in Patchwork_14932_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@vcs1-s3:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_ctx_isolat...@vcs1-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-iclb3/igt@gem_ctx_isolat...@vcs1-s3.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-snb: [PASS][7] -> [FAIL][8] ([fdo#111925])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb7/igt@gem_...@in-flight-contexts-immediate.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-snb2/igt@gem_...@in-flight-contexts-immediate.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +8 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_exec_sched...@out-order-bsd2.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-iclb3/igt@gem_exec_sched...@out-order-bsd2.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#111325]) +3 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb8/igt@gem_exec_sched...@preemptive-hang-bsd.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#104108])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl10/igt@gem_soft...@noreloc-s3.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-skl8/igt@gem_soft...@noreloc-s3.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-snb: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) +2
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-snb6/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103665])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl4/igt@gem_workarou...@suspend-resume-fd.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-kbl4/igt@gem_workarou...@suspend-resume-fd.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-apl: [PASS][19] -> [SKIP][20] ([fdo#109271])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl6/igt@i915_pm_rc6_reside...@rc6-accuracy.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-apl4/igt@i915_pm_rc6_reside...@rc6-accuracy.html
- shard-skl:
Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: skip the second CRC even for GEN 7 GPUs
Hi,
Even though I tried to link this patch with it's first version by
specifying --in-reply-to=, it wasn't successful. So here is
the link to the first version of the patch and the discussion.
https://patchwork.freedesktop.org/patch/305153/?series=60697=1
The first version of this patch has been "Acked-by" but wasn't
"Reviewed-by" as the patch adds another workaround on top of an already
existing workaround. The patch doesn't fix the cause of invalid CRCs
being generated which still needs to be investigated and fixed. I am
rebasing and resending the patch to seek feedback on how to move
further with this patch.
Thank You
Harish
On Wed, 2019-10-23 at 00:24 -0700, Harish Chegondi wrote:
> display_pipe_crc_irq_handler() skips the first CRC for all GPUs and
> the
> second CRC for GEN8+ GPUs. The second CRC is invalid even for BYT
> which
> is a GEN7 GPU. So, skip the second CRC even for GEN7 GPUs.
>
> v2: Rebase
>
> Cc: Jani Saarinen
> Cc: Tomi Sarvela
> Cc: Petri Latvala
> Cc: Ville Syrjälä
> Cc: Maarten Lankhorst
> Acked-by: Jani Nikula
> Signed-off-by: Harish Chegondi
> References: https://bugs.freedesktop.org/show_bug.cgi?id=103191
> ---
> drivers/gpu/drm/i915/i915_irq.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 572a5c37cc61..312ca9d5292a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1565,11 +1565,11 @@ static void
> display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>* bonkers. So let's just wait for the next vblank and read
>* out the buggy result.
>*
> - * On GEN8+ sometimes the second CRC is bonkers as well, so
> + * On GEN7+ sometimes the second CRC is bonkers as well, so
>* don't trust that one either.
>*/
> if (pipe_crc->skipped <= 0 ||
> - (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
> + (INTEL_GEN(dev_priv) >= 7 && pipe_crc->skipped == 1)) {
> pipe_crc->skipped++;
> spin_unlock(_crc->lock);
> return;
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/gt: Try to more gracefully quiesce the system before resets
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/gt: Try to more gracefully
quiesce the system before resets
URL : https://patchwork.freedesktop.org/series/68457/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7165 -> Patchwork_14948
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14948:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-glk-dsi: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-glk-dsi/igt@i915_selftest@live_gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/fi-glk-dsi/igt@i915_selftest@live_gt_heartbeat.html
Known issues
Here are the changes found in Patchwork_14948 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@basic:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724] /
[fdo#112052 ])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-icl-u3/igt@gem_flink_ba...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/fi-icl-u3/igt@gem_flink_ba...@basic.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][5] -> [DMESG-WARN][6] ([fdo#102614])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
* igt@prime_busy@basic-before-default:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-icl-u3/igt@prime_b...@basic-before-default.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/fi-icl-u3/igt@prime_b...@basic-before-default.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [INCOMPLETE][9] ([fdo#103927]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
- {fi-tgl-u2}:[INCOMPLETE][11] ([fdo#111735]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* {igt@i915_selftest@live_gt_timelines}:
- {fi-tgl-u}: [INCOMPLETE][15] ([fdo#111831]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_gt_timelines.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/fi-tgl-u/igt@i915_selftest@live_gt_timelines.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][17] ([fdo#109483]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-7500u: [FAIL][19] ([fdo#103375]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-kbl-7500u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/fi-kbl-7500u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][21] ([fdo#111407]) -> [FAIL][22] ([fdo#111045]
/ [fdo#111096])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14948/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103375]:
Re: [Intel-gfx] [PATCH V5 4/6] mdev: introduce virtio device and its device ops
On Wed, 23 Oct 2019 21:07:50 +0800
Jason Wang wrote:
> This patch implements basic support for mdev driver that supports
> virtio transport for kernel virtio driver.
>
> Signed-off-by: Jason Wang
> ---
> drivers/vfio/mdev/mdev_core.c| 20
> drivers/vfio/mdev/mdev_private.h | 2 +
> include/linux/mdev.h | 6 ++
> include/linux/virtio_mdev_ops.h | 159 +++
> 4 files changed, 187 insertions(+)
> create mode 100644 include/linux/virtio_mdev_ops.h
>
> diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
> index 555bd61d8c38..9b00c3513120 100644
> --- a/drivers/vfio/mdev/mdev_core.c
> +++ b/drivers/vfio/mdev/mdev_core.c
> @@ -76,6 +76,26 @@ const struct vfio_mdev_device_ops
> *mdev_get_vfio_ops(struct mdev_device *mdev)
> }
> EXPORT_SYMBOL(mdev_get_vfio_ops);
>
> +/* Specify the virtio device ops for the mdev device, this
> + * must be called during create() callback for virtio mdev device.
> + */
> +void mdev_set_virtio_ops(struct mdev_device *mdev,
> + const struct virtio_mdev_device_ops *virtio_ops)
> +{
> + mdev_set_class(mdev, MDEV_CLASS_ID_VIRTIO);
> + mdev->virtio_ops = virtio_ops;
> +}
> +EXPORT_SYMBOL(mdev_set_virtio_ops);
> +
> +/* Get the virtio device ops for the mdev device. */
> +const struct virtio_mdev_device_ops *
> +mdev_get_virtio_ops(struct mdev_device *mdev)
> +{
> + WARN_ON(mdev->class_id != MDEV_CLASS_ID_VIRTIO);
> + return mdev->virtio_ops;
> +}
> +EXPORT_SYMBOL(mdev_get_virtio_ops);
> +
> struct device *mdev_dev(struct mdev_device *mdev)
> {
> return >dev;
> diff --git a/drivers/vfio/mdev/mdev_private.h
> b/drivers/vfio/mdev/mdev_private.h
> index 0770410ded2a..7b47890c34e7 100644
> --- a/drivers/vfio/mdev/mdev_private.h
> +++ b/drivers/vfio/mdev/mdev_private.h
> @@ -11,6 +11,7 @@
> #define MDEV_PRIVATE_H
>
> #include
> +#include
>
> int mdev_bus_register(void);
> void mdev_bus_unregister(void);
> @@ -38,6 +39,7 @@ struct mdev_device {
> u16 class_id;
> union {
> const struct vfio_mdev_device_ops *vfio_ops;
> + const struct virtio_mdev_device_ops *virtio_ops;
> };
> };
>
> diff --git a/include/linux/mdev.h b/include/linux/mdev.h
> index 4625f1a11014..9b69b0bbebfd 100644
> --- a/include/linux/mdev.h
> +++ b/include/linux/mdev.h
> @@ -17,6 +17,7 @@
>
> struct mdev_device;
> struct vfio_mdev_device_ops;
> +struct virtio_mdev_device_ops;
>
> /*
> * Called by the parent device driver to set the device which represents
> @@ -112,6 +113,10 @@ void mdev_set_class(struct mdev_device *mdev, u16 id);
> void mdev_set_vfio_ops(struct mdev_device *mdev,
> const struct vfio_mdev_device_ops *vfio_ops);
> const struct vfio_mdev_device_ops *mdev_get_vfio_ops(struct mdev_device
> *mdev);
> +void mdev_set_virtio_ops(struct mdev_device *mdev,
> + const struct virtio_mdev_device_ops *virtio_ops);
> +const struct virtio_mdev_device_ops *
> +mdev_get_virtio_ops(struct mdev_device *mdev);
>
> extern struct bus_type mdev_bus_type;
>
> @@ -127,6 +132,7 @@ struct mdev_device *mdev_from_dev(struct device *dev);
>
> enum {
> MDEV_CLASS_ID_VFIO = 1,
> + MDEV_CLASS_ID_VIRTIO = 2,
> /* New entries must be added here */
> };
>
> diff --git a/include/linux/virtio_mdev_ops.h b/include/linux/virtio_mdev_ops.h
> new file mode 100644
> index ..d417b41f2845
> --- /dev/null
> +++ b/include/linux/virtio_mdev_ops.h
> @@ -0,0 +1,159 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Virtio mediated device driver
> + *
> + * Copyright 2019, Red Hat Corp.
> + * Author: Jason Wang
> + */
> +#ifndef _LINUX_VIRTIO_MDEV_H
> +#define _LINUX_VIRTIO_MDEV_H
> +
> +#include
> +#include
> +#include
> +
> +#define VIRTIO_MDEV_DEVICE_API_STRING"virtio-mdev"
> +#define VIRTIO_MDEV_F_VERSION_1 0x1
> +
> +struct virtio_mdev_callback {
> + irqreturn_t (*callback)(void *data);
> + void *private;
> +};
> +
> +/**
> + * struct vfio_mdev_device_ops - Structure to be registered for each
> + * mdev device to register the device for virtio/vhost drivers.
> + *
> + * The device ops that is supported by VIRTIO_MDEV_F_VERSION_1, the
> + * callbacks are mandatory unless explicity mentioned.
If the version of the callbacks is returned by a callback within the
structure defined by the version... isn't that a bit circular? This
seems redundant to me versus the class id. The fact that the parent
driver defines the device as MDEV_CLASS_ID_VIRTIO should tell us this
already. If it was incremented, we'd need an MDEV_CLASS_ID_VIRTIOv2,
which the virtio-mdev bus driver could add to its id table and handle
differently.
> + *
> + * @set_vq_address: Set the address of virtqueue
> + * @mdev: mediated device
> + * @idx: virtqueue index
> + * @desc_area:
Re: [Intel-gfx] [PATCH V5 1/6] mdev: class id support
> -Original Message-
> From: Jason Wang
> Sent: Wednesday, October 23, 2019 8:08 AM
> To: k...@vger.kernel.org; linux-s...@vger.kernel.org; linux-
> ker...@vger.kernel.org; dri-de...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org;
> kwankh...@nvidia.com; alex.william...@redhat.com; m...@redhat.com;
> tiwei@intel.com
> Cc: virtualizat...@lists.linux-foundation.org; net...@vger.kernel.org;
> coh...@redhat.com; maxime.coque...@redhat.com;
> cunming.li...@intel.com; zhihong.w...@intel.com;
> rob.mil...@broadcom.com; xiao.w.w...@intel.com;
> haotian.w...@sifive.com; zhen...@linux.intel.com; zhi.a.w...@intel.com;
> jani.nik...@linux.intel.com; joonas.lahti...@linux.intel.com;
> rodrigo.v...@intel.com; airl...@linux.ie; dan...@ffwll.ch;
> far...@linux.ibm.com; pa...@linux.ibm.com; seb...@linux.ibm.com;
> ober...@linux.ibm.com; heiko.carst...@de.ibm.com; g...@linux.ibm.com;
> borntrae...@de.ibm.com; akrow...@linux.ibm.com; fre...@linux.ibm.com;
> lingshan@intel.com; Ido Shamay ;
> epere...@redhat.com; l...@redhat.com; Parav Pandit
> ; christophe.de.dinec...@gmail.com;
> kevin.t...@intel.com; stefa...@redhat.com; Jason Wang
>
> Subject: [PATCH V5 1/6] mdev: class id support
>
> Mdev bus only supports vfio driver right now, so it doesn't implement match
> method. But in the future, we may add drivers other than vfio, the first
> driver
> could be virtio-mdev. This means we need to add device class id support in bus
> match method to pair the mdev device and mdev driver correctly.
>
> So this patch adds id_table to mdev_driver and class_id for mdev device with
> the match method for mdev bus.
>
> Signed-off-by: Jason Wang
> ---
> .../driver-api/vfio-mediated-device.rst | 5 +
> drivers/gpu/drm/i915/gvt/kvmgt.c | 1 +
> drivers/s390/cio/vfio_ccw_ops.c | 1 +
> drivers/s390/crypto/vfio_ap_ops.c | 1 +
> drivers/vfio/mdev/mdev_core.c | 18 +++
> drivers/vfio/mdev/mdev_driver.c | 22 +++
> drivers/vfio/mdev/mdev_private.h | 1 +
> drivers/vfio/mdev/vfio_mdev.c | 6 +
> include/linux/mdev.h | 8 +++
> include/linux/mod_devicetable.h | 8 +++
> samples/vfio-mdev/mbochs.c| 1 +
> samples/vfio-mdev/mdpy.c | 1 +
> samples/vfio-mdev/mtty.c | 1 +
> 13 files changed, 74 insertions(+)
>
> diff --git a/Documentation/driver-api/vfio-mediated-device.rst
> b/Documentation/driver-api/vfio-mediated-device.rst
> index 25eb7d5b834b..6709413bee29 100644
> --- a/Documentation/driver-api/vfio-mediated-device.rst
> +++ b/Documentation/driver-api/vfio-mediated-device.rst
> @@ -102,12 +102,14 @@ structure to represent a mediated device's driver::
>* @probe: called when new device created
>* @remove: called when device removed
>* @driver: device driver structure
> + * @id_table: the ids serviced by this driver
>*/
> struct mdev_driver {
>const char *name;
>int (*probe) (struct device *dev);
>void (*remove) (struct device *dev);
>struct device_driverdriver;
> + const struct mdev_class_id *id_table;
> };
>
> A mediated bus driver for mdev should use this structure in the function
> calls
> @@ -170,6 +172,9 @@ that a driver should use to unregister itself with the
> mdev core driver::
>
> extern void mdev_unregister_device(struct device *dev);
>
> +It is also required to specify the class_id in create() callback through::
> +
> + int mdev_set_class(struct mdev_device *mdev, u16 id);
>
> Mediated Device Management Interface Through sysfs
> ==
> diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c
> b/drivers/gpu/drm/i915/gvt/kvmgt.c
> index 343d79c1cb7e..6420f0dbd31b 100644
> --- a/drivers/gpu/drm/i915/gvt/kvmgt.c
> +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
> @@ -678,6 +678,7 @@ static int intel_vgpu_create(struct kobject *kobj, struct
> mdev_device *mdev)
>dev_name(mdev_dev(mdev)));
> ret = 0;
>
> + mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
> out:
> return ret;
> }
> diff --git a/drivers/s390/cio/vfio_ccw_ops.c b/drivers/s390/cio/vfio_ccw_ops.c
> index f0d71ab77c50..cf2c013ae32f 100644
> --- a/drivers/s390/cio/vfio_ccw_ops.c
> +++ b/drivers/s390/cio/vfio_ccw_ops.c
> @@ -129,6 +129,7 @@ static int vfio_ccw_mdev_create(struct kobject *kobj,
> struct mdev_device *mdev)
> private->sch->schid.ssid,
> private->sch->schid.sch_no);
>
> + mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
> return 0;
> }
>
> diff --git a/drivers/s390/crypto/vfio_ap_ops.c
> b/drivers/s390/crypto/vfio_ap_ops.c
> index 5c0f53c6dde7..07c31070afeb 100644
> ---
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
Quoting Patchwork (2019-10-23 22:20:49)
> * igt@i915_selftest@live_workarounds:
> - {fi-tgl-u}: [PASS][3] -> [DMESG-FAIL][4]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_workarounds.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u/igt@i915_selftest@live_workarounds.html
That does seem to be genuine and worth following up with.
-Chris
___
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[Intel-gfx] [PATCH] drm/i915/display/psr: Print in debugfs if PSR is not enabled because of sink
Right now if sink reported any PSR error or if it fails to
acknowledge the PSR wakeup it sets a flag and do not attempt to
enable PSR anymore. That is the safest approach to avoid repetitive
glitches and allowed us to have PSR enabled by default.
But from time to time even good PSR panels have a PSR error, causing
tests to fail. And for now we are not yet to the point were we could
try to recover from PSR errors, so lets add this information to the
debugfs so IGT can check if PSR is disabled because of sink errors or
not and eliminate this noise from CI runs.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Cc: Matt Roper
Cc: Ap Kamal
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index bc0bdf0419e0..07e368ec4fb8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2194,8 +2194,12 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
status = "disabled";
seq_printf(m, "PSR mode: %s\n", status);
- if (!psr->enabled)
+ if (!psr->enabled) {
+ seq_printf(m, "PSR sink not reliable: %s\n",
+ yesno(psr->sink_not_reliable));
+
goto unlock;
+ }
if (psr->psr2_enabled) {
val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
--
2.23.0
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/4] drm/i915/gt: Try to more gracefully quiesce the system before resets
== Series Details == Series: series starting with [CI,1/4] drm/i915/gt: Try to more gracefully quiesce the system before resets URL : https://patchwork.freedesktop.org/series/68457/ State : warning == Summary == $ dim checkpatch origin/drm-tip 139aa7679696 drm/i915/gt: Try to more gracefully quiesce the system before resets -:58: ERROR:IN_ATOMIC: do not use in_atomic in drivers #58: FILE: drivers/gpu/drm/i915/gt/intel_engine_cs.c:883: + if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */ total: 1 errors, 0 warnings, 0 checks, 62 lines checked de7f703951e2 drm/i915/execlists: Force preemption 5432266dcd68 drm/i915/execlists: Cancel banned contexts on schedule-out c5ae74589e9e drm/i915/gem: Cancel contexts when hangchecking is disabled ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V5 2/6] modpost: add support for mdev class id
On Wed, 23 Oct 2019 21:07:48 +0800
Jason Wang wrote:
> Add support to parse mdev class id table.
>
> Reviewed-by: Parav Pandit
> Signed-off-by: Jason Wang
> ---
> drivers/vfio/mdev/vfio_mdev.c | 2 ++
> scripts/mod/devicetable-offsets.c | 3 +++
> scripts/mod/file2alias.c | 10 ++
> 3 files changed, 15 insertions(+)
>
> diff --git a/drivers/vfio/mdev/vfio_mdev.c b/drivers/vfio/mdev/vfio_mdev.c
> index 7b24ee9cb8dd..cb701cd646f0 100644
> --- a/drivers/vfio/mdev/vfio_mdev.c
> +++ b/drivers/vfio/mdev/vfio_mdev.c
> @@ -125,6 +125,8 @@ static const struct mdev_class_id id_table[] = {
> { 0 },
> };
>
> +MODULE_DEVICE_TABLE(mdev, id_table);
> +
Two questions, first we have:
#define MODULE_DEVICE_TABLE(type, name) \
extern typeof(name) __mod_##type##__##name##_device_table \
__attribute__ ((unused, alias(__stringify(name
Therefore we're defining __mod_mdev__id_table_device_table with alias
id_table. When the virtio mdev bus driver is added in 5/6 it uses the
same name value. I see virtio types all register this way (virtio,
id_table), so I assume there's no conflict, but pci types mostly (not
entirely) seem to use unique names. Is there a preference to one way
or the other or it simply doesn't matter?
> static struct mdev_driver vfio_mdev_driver = {
> .name = "vfio_mdev",
> .probe = vfio_mdev_probe,
> diff --git a/scripts/mod/devicetable-offsets.c
> b/scripts/mod/devicetable-offsets.c
> index 054405b90ba4..6cbb1062488a 100644
> --- a/scripts/mod/devicetable-offsets.c
> +++ b/scripts/mod/devicetable-offsets.c
> @@ -231,5 +231,8 @@ int main(void)
> DEVID(wmi_device_id);
> DEVID_FIELD(wmi_device_id, guid_string);
>
> + DEVID(mdev_class_id);
> + DEVID_FIELD(mdev_class_id, id);
> +
> return 0;
> }
> diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c
> index c91eba751804..d365dfe7c718 100644
> --- a/scripts/mod/file2alias.c
> +++ b/scripts/mod/file2alias.c
> @@ -1335,6 +1335,15 @@ static int do_wmi_entry(const char *filename, void
> *symval, char *alias)
> return 1;
> }
>
> +/* looks like: "mdev:cN" */
> +static int do_mdev_entry(const char *filename, void *symval, char *alias)
> +{
> + DEF_FIELD(symval, mdev_class_id, id);
> +
> + sprintf(alias, "mdev:c%02X", id);
A lot of entries call add_wildcard() here, should we? Sorry for the
basic questions, I haven't played in this code. Thanks,
Alex
> + return 1;
> +}
> +
> /* Does namelen bytes of name exactly match the symbol? */
> static bool sym_is(const char *name, unsigned namelen, const char *symbol)
> {
> @@ -1407,6 +1416,7 @@ static const struct devtable devtable[] = {
> {"typec", SIZE_typec_device_id, do_typec_entry},
> {"tee", SIZE_tee_client_device_id, do_tee_entry},
> {"wmi", SIZE_wmi_device_id, do_wmi_entry},
> + {"mdev", SIZE_mdev_class_id, do_mdev_entry},
> };
>
> /* Create MODULE_ALIAS() statements.
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH V5 1/6] mdev: class id support
On Wed, 23 Oct 2019 21:07:47 +0800
Jason Wang wrote:
> Mdev bus only supports vfio driver right now, so it doesn't implement
> match method. But in the future, we may add drivers other than vfio,
> the first driver could be virtio-mdev. This means we need to add
> device class id support in bus match method to pair the mdev device
> and mdev driver correctly.
>
> So this patch adds id_table to mdev_driver and class_id for mdev
> device with the match method for mdev bus.
>
> Signed-off-by: Jason Wang
> ---
> .../driver-api/vfio-mediated-device.rst | 5 +
> drivers/gpu/drm/i915/gvt/kvmgt.c | 1 +
> drivers/s390/cio/vfio_ccw_ops.c | 1 +
> drivers/s390/crypto/vfio_ap_ops.c | 1 +
> drivers/vfio/mdev/mdev_core.c | 18 +++
> drivers/vfio/mdev/mdev_driver.c | 22 +++
> drivers/vfio/mdev/mdev_private.h | 1 +
> drivers/vfio/mdev/vfio_mdev.c | 6 +
> include/linux/mdev.h | 8 +++
> include/linux/mod_devicetable.h | 8 +++
> samples/vfio-mdev/mbochs.c| 1 +
> samples/vfio-mdev/mdpy.c | 1 +
> samples/vfio-mdev/mtty.c | 1 +
> 13 files changed, 74 insertions(+)
>
> diff --git a/Documentation/driver-api/vfio-mediated-device.rst
> b/Documentation/driver-api/vfio-mediated-device.rst
> index 25eb7d5b834b..6709413bee29 100644
> --- a/Documentation/driver-api/vfio-mediated-device.rst
> +++ b/Documentation/driver-api/vfio-mediated-device.rst
> @@ -102,12 +102,14 @@ structure to represent a mediated device's driver::
>* @probe: called when new device created
>* @remove: called when device removed
>* @driver: device driver structure
> + * @id_table: the ids serviced by this driver
>*/
> struct mdev_driver {
>const char *name;
>int (*probe) (struct device *dev);
>void (*remove) (struct device *dev);
>struct device_driverdriver;
> + const struct mdev_class_id *id_table;
> };
>
> A mediated bus driver for mdev should use this structure in the function
> calls
> @@ -170,6 +172,9 @@ that a driver should use to unregister itself with the
> mdev core driver::
>
> extern void mdev_unregister_device(struct device *dev);
>
> +It is also required to specify the class_id in create() callback through::
> +
> + int mdev_set_class(struct mdev_device *mdev, u16 id);
>
> Mediated Device Management Interface Through sysfs
> ==
> diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c
> b/drivers/gpu/drm/i915/gvt/kvmgt.c
> index 343d79c1cb7e..6420f0dbd31b 100644
> --- a/drivers/gpu/drm/i915/gvt/kvmgt.c
> +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
> @@ -678,6 +678,7 @@ static int intel_vgpu_create(struct kobject *kobj, struct
> mdev_device *mdev)
>dev_name(mdev_dev(mdev)));
> ret = 0;
>
> + mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
> out:
> return ret;
> }
> diff --git a/drivers/s390/cio/vfio_ccw_ops.c b/drivers/s390/cio/vfio_ccw_ops.c
> index f0d71ab77c50..cf2c013ae32f 100644
> --- a/drivers/s390/cio/vfio_ccw_ops.c
> +++ b/drivers/s390/cio/vfio_ccw_ops.c
> @@ -129,6 +129,7 @@ static int vfio_ccw_mdev_create(struct kobject *kobj,
> struct mdev_device *mdev)
> private->sch->schid.ssid,
> private->sch->schid.sch_no);
>
> + mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
> return 0;
> }
>
> diff --git a/drivers/s390/crypto/vfio_ap_ops.c
> b/drivers/s390/crypto/vfio_ap_ops.c
> index 5c0f53c6dde7..07c31070afeb 100644
> --- a/drivers/s390/crypto/vfio_ap_ops.c
> +++ b/drivers/s390/crypto/vfio_ap_ops.c
> @@ -343,6 +343,7 @@ static int vfio_ap_mdev_create(struct kobject *kobj,
> struct mdev_device *mdev)
> list_add(_mdev->node, _dev->mdev_list);
> mutex_unlock(_dev->lock);
>
> + mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
> return 0;
> }
>
> diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
> index b558d4cfd082..3a9c52d71b4e 100644
> --- a/drivers/vfio/mdev/mdev_core.c
> +++ b/drivers/vfio/mdev/mdev_core.c
> @@ -45,6 +45,16 @@ void mdev_set_drvdata(struct mdev_device *mdev, void *data)
> }
> EXPORT_SYMBOL(mdev_set_drvdata);
>
> +/* Specify the class for the mdev device, this must be called during
> + * create() callback.
> + */
> +void mdev_set_class(struct mdev_device *mdev, u16 id)
> +{
> + WARN_ON(mdev->class_id);
> + mdev->class_id = id;
> +}
> +EXPORT_SYMBOL(mdev_set_class);
> +
> struct device *mdev_dev(struct mdev_device *mdev)
> {
> return >dev;
> @@ -135,6 +145,7 @@ static int mdev_device_remove_cb(struct device *dev, void
> *data)
> * mdev_register_device : Register a device
> * @dev: device structure representing parent device.
> *
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
== Series Details ==
Series: drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
URL : https://patchwork.freedesktop.org/series/68455/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7165 -> Patchwork_14947
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14947 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14947, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14947:
### IGT changes ###
Possible regressions
* igt@i915_pm_rpm@basic-rte:
- fi-skl-6600u: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-skl-6600u/igt@i915_pm_...@basic-rte.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-skl-6600u/igt@i915_pm_...@basic-rte.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_workarounds:
- {fi-tgl-u}: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_workarounds.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u/igt@i915_selftest@live_workarounds.html
Known issues
Here are the changes found in Patchwork_14947 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@bad-flink:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
* igt@i915_selftest@live_coherency:
- fi-cfl-8109u: [PASS][7] -> [TIMEOUT][8] ([fdo#111944])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-cfl-8109u/igt@i915_selftest@live_coherency.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-cfl-8109u/igt@i915_selftest@live_coherency.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [INCOMPLETE][9] ([fdo#103927]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
- {fi-tgl-u2}:[INCOMPLETE][11] ([fdo#111735]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* {igt@i915_selftest@live_gt_timelines}:
- {fi-tgl-u}: [INCOMPLETE][15] ([fdo#111831]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-tgl-u/igt@i915_selftest@live_gt_timelines.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-tgl-u/igt@i915_selftest@live_gt_timelines.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][17] ([fdo#109483]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
- fi-kbl-7500u: [FAIL][19] ([fdo#111407]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-7500u: [FAIL][21] ([fdo#103375]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7165/fi-kbl-7500u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14947/fi-kbl-7500u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS,
[Intel-gfx] ✓ Fi.CI.IGT: success for adding gamma state checker for icl+ platforms (rev6)
== Series Details ==
Series: adding gamma state checker for icl+ platforms (rev6)
URL : https://patchwork.freedesktop.org/series/66811/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7128_full -> Patchwork_14880_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_14880_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14880_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14880_full:
### IGT changes ###
Warnings
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [FAIL][1] ([fdo#103232]) -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/shard-skl3/igt@kms_cursor_...@pipe-b-cursor-suspend.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14880/shard-skl2/igt@kms_cursor_...@pipe-b-cursor-suspend.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_reg_read@timestamp-moving:
- {shard-tglb}: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/shard-tglb6/igt@gem_reg_r...@timestamp-moving.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14880/shard-tglb5/igt@gem_reg_r...@timestamp-moving.html
Known issues
Here are the changes found in Patchwork_14880_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +6
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/shard-apl1/igt@gem_ctx_isolat...@rcs0-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14880/shard-apl2/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_ctx_isolation@vcs1-none:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [fdo#112080])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/shard-iclb2/igt@gem_ctx_isolat...@vcs1-none.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14880/shard-iclb7/igt@gem_ctx_isolat...@vcs1-none.html
* igt@gem_ctx_switch@bcs0:
- shard-apl: [PASS][9] -> [INCOMPLETE][10] ([fdo#103927])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/shard-apl6/igt@gem_ctx_swi...@bcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14880/shard-apl2/igt@gem_ctx_swi...@bcs0.html
* igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#111325]) +4 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/shard-iclb5/igt@gem_exec_sched...@in-order-bsd.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14880/shard-iclb1/igt@gem_exec_sched...@in-order-bsd.html
* igt@gem_exec_schedule@in-order-bsd2:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109276]) +13 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/shard-iclb4/igt@gem_exec_sched...@in-order-bsd2.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14880/shard-iclb8/igt@gem_exec_sched...@in-order-bsd2.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#112037])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/shard-iclb6/igt@gem_persistent_rel...@forked-thrashing.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14880/shard-iclb2/igt@gem_persistent_rel...@forked-thrashing.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-hsw: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) +1
similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/shard-hsw8/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14880/shard-hsw2/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) +1
similar issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/shard-snb5/igt@gem_userptr_bl...@sync-unmap-cycles.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14880/shard-snb2/igt@gem_userptr_bl...@sync-unmap-cycles.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-hsw: [PASS][21] -> [INCOMPLETE][22] ([fdo#103540] /
[fdo#107807])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/shard-hsw7/igt@i915_pm_...@modeset-non-lpsp.html
[22]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
== Series Details ==
Series: drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
URL : https://patchwork.freedesktop.org/series/68455/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
aaf5cc0a4c3b drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
-:9: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 3fe0107e45ab ("drm/i915/icl:
whitelist PS_(DEPTH|INVOCATION)_COUNT")'
#9:
As with commit 3fe0107e45ab, this change fixes multiple tests that are
total: 1 errors, 0 warnings, 0 checks, 26 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Add coverage of mocs registers
On Tue, Oct 22, 2019 at 12:57:05PM +0100, Chris Wilson wrote:
> Probe the mocs registers for new contexts and across GPU resets. Similar
> to intel_workarounds, we have tables of what register values we expect
> to see, so verify that user contexts are affected by them. In the
> future, we should add tests similar to intel_sseu to cover dynamic
> reconfigurations.
>
> Signed-off-by: Chris Wilson
> Cc: Prathap Kumar Valsan
> Cc: Mika Kuoppala
s/for_each_engine/for_each_uabi_engine ?
Otherwise
Reviewed-by: Prathap Kumar Valsan
> ---
> drivers/gpu/drm/i915/gt/intel_mocs.c | 4 +
> drivers/gpu/drm/i915/gt/selftest_mocs.c | 393 ++
> .../drm/i915/selftests/i915_live_selftests.h | 1 +
> 3 files changed, 398 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/gt/selftest_mocs.c
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 445ec025bda0..06dba7ff294e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -448,3 +448,7 @@ void intel_mocs_init(struct intel_gt *gt)
> if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
> init_global_mocs(gt);
> }
> +
> +#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> +#include "selftest_mocs.c"
> +#endif
> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> new file mode 100644
> index ..ca9679c3ee68
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> @@ -0,0 +1,393 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#include "gt/intel_engine_pm.h"
> +#include "i915_selftest.h"
> +
> +#include "gem/selftests/mock_context.h"
> +#include "selftests/igt_reset.h"
> +#include "selftests/igt_spinner.h"
> +
> +struct live_mocs {
> + struct drm_i915_mocs_table table;
> + struct i915_vma *scratch;
> + void *vaddr;
> +};
> +
> +static int request_add_sync(struct i915_request *rq, int err)
> +{
> + i915_request_get(rq);
> + i915_request_add(rq);
> + if (i915_request_wait(rq, 0, HZ / 5) < 0)
> + err = -ETIME;
> + i915_request_put(rq);
> +
> + return err;
> +}
> +
> +static int request_add_spin(struct i915_request *rq, struct igt_spinner
> *spin)
> +{
> + int err = 0;
> +
> + i915_request_get(rq);
> + i915_request_add(rq);
> + if (spin && !igt_wait_for_spinner(spin, rq))
> + err = -ETIME;
> + i915_request_put(rq);
> +
> + return err;
> +}
> +
> +static struct i915_vma *create_scratch(struct intel_gt *gt)
> +{
> + struct drm_i915_gem_object *obj;
> + struct i915_vma *vma;
> + int err;
> +
> + obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
> + if (IS_ERR(obj))
> + return ERR_CAST(obj);
> +
> + i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
> +
> + vma = i915_vma_instance(obj, >ggtt->vm, NULL);
> + if (IS_ERR(vma)) {
> + i915_gem_object_put(obj);
> + return vma;
> + }
> +
> + err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
> + if (err) {
> + i915_gem_object_put(obj);
> + return ERR_PTR(err);
> + }
> +
> + return vma;
> +}
> +
> +static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
> +{
> + int err;
> +
> + if (!get_mocs_settings(gt->i915, >table))
> + return -EINVAL;
> +
> + arg->scratch = create_scratch(gt);
> + if (IS_ERR(arg->scratch))
> + return PTR_ERR(arg->scratch);
> +
> + arg->vaddr = i915_gem_object_pin_map(arg->scratch->obj, I915_MAP_WB);
> + if (IS_ERR(arg->vaddr)) {
> + err = PTR_ERR(arg->vaddr);
> + goto err_scratch;
> + }
> +
> + return 0;
> +
> +err_scratch:
> + i915_vma_unpin_and_release(>scratch, 0);
> + return err;
> +}
> +
> +static void live_mocs_fini(struct live_mocs *arg)
> +{
> + i915_vma_unpin_and_release(>scratch, I915_VMA_RELEASE_MAP);
> +}
> +
> +static int read_regs(struct i915_request *rq,
> + u32 addr, unsigned int count,
> + uint32_t *offset)
> +{
> + unsigned int i;
> + u32 *cs;
> +
> + GEM_BUG_ON(!IS_ALIGNED(*offset, sizeof(u32)));
> +
> + cs = intel_ring_begin(rq, 4 * count);
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> +
> + for (i = 0; i < count; i++) {
> + *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
> + *cs++ = addr;
> + *cs++ = *offset;
> + *cs++ = 0;
> +
> + addr += sizeof(u32);
> + *offset += sizeof(u32);
> + }
> +
> + intel_ring_advance(rq, cs);
> +
> + return 0;
> +}
> +
> +static int read_mocs_table(struct i915_request *rq,
> +const struct drm_i915_mocs_table *table,
> +uint32_t *offset)
> +{
> + u32 addr;
> +
> + if
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/simple-kms: Standardize arguments for callbacks
== Series Details ==
Series: drm/simple-kms: Standardize arguments for callbacks
URL : https://patchwork.freedesktop.org/series/68452/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7163 -> Patchwork_14946
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14946/index.html
Known issues
Here are the changes found in Patchwork_14946 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-small-bo:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7163/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14946/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [PASS][3] -> [WARN][4] ([fdo#109483])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7163/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14946/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-icl-u4}:[INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7163/fi-icl-u4/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14946/fi-icl-u4/igt@gem_ctx_cre...@basic-files.html
- {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111735]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7163/fi-tgl-u/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14946/fi-tgl-u/igt@gem_ctx_cre...@basic-files.html
- fi-apl-guc: [INCOMPLETE][9] ([fdo#103927]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7163/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14946/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_create@basic:
- fi-icl-u2: [INCOMPLETE][11] ([fdo#107713]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7163/fi-icl-u2/igt@gem_exec_cre...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14946/fi-icl-u2/igt@gem_exec_cre...@basic.html
* igt@gem_flink_basic@bad-flink:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7163/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14946/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
* igt@gem_sync@basic-many-each:
- {fi-tgl-u2}:[INCOMPLETE][15] ([fdo#111647]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7163/fi-tgl-u2/igt@gem_s...@basic-many-each.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14946/fi-tgl-u2/igt@gem_s...@basic-many-each.html
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-cfl-8700k: [DMESG-FAIL][17] ([fdo#112096]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7163/fi-cfl-8700k/igt@i915_selftest@live_gt_heartbeat.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14946/fi-cfl-8700k/igt@i915_selftest@live_gt_heartbeat.html
- fi-kbl-8809g: [DMESG-FAIL][19] ([fdo#112096]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7163/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14946/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
- fi-skl-iommu: [DMESG-FAIL][21] ([fdo#112096]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7163/fi-skl-iommu/igt@i915_selftest@live_gt_heartbeat.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14946/fi-skl-iommu/igt@i915_selftest@live_gt_heartbeat.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (51 -> 45)
--
Additional (1): fi-bdw-gvtdvm
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
Re: [Intel-gfx] [PATCH 1/5] drm/i915/display: Handle fused off display correctly
On Wed, 2019-10-23 at 16:23 +0300, Jani Nikula wrote:
> On Wed, 23 Oct 2019, Ramalingam C wrote:
> > On 2019-10-18 at 17:41:20 -0700, José Roberto de Souza wrote:
> > > If all pipes are fused off it means that display is disabled,
> > > similar
> > > like we handle for GEN 7 and 8 right above but for GEN9+ spec
> > > says
> > > that hardware will override the pipe output to a solid color, so
> > > some display is there and maybe we would need to shutdown display
> > > to save power, so setting disable_display = true, to keep
> > > consistent
> > > to HAS_DISPLAY() and INTEL_DISPLAY_ENABLED().
> > >
> > > In addition to have all pipes fused off, GEN/display 9 have the
> > > bit 30 "Internal Display Disable", not sure if all pipes will be
> > > set
> > > as unfused when this bit is set so handling both.
> > >
> > > Cc: Jani Nikula
> > > Cc: Lucas De Marchi
> > > Cc: Ville Syrjälä
> > > Cc: Martin Peres
> > > Signed-off-by: José Roberto de Souza
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 21 +++---
> > > ---
> > > drivers/gpu/drm/i915/intel_device_info.c | 14 ++
> > > 2 files changed, 21 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 855db888516c..6e3ae6e9cbb8 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7651,16 +7651,17 @@ enum {
> > > #define MASK_WAKEMEM (1 << 13)
> > > #define CNL_DDI_CLOCK_REG_ACCESS_ON(1 << 7)
> > >
> > > -#define SKL_DFSM _MMIO(0x51000)
> > > -#define SKL_DFSM_CDCLK_LIMIT_MASK(3 << 23)
> > > -#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
> > > -#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> > > -#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
> > > -#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> > > -#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
> > > -#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> > > -#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> > > -#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
> > > +#define SKL_DFSM _MMIO(0x51000)
> > > +#define SKL_DFSM_INTERNAL_DISPLAY_DISABLE(1 << 30)
> > > +#define SKL_DFSM_CDCLK_LIMIT_MASK(3 << 23)
> > > +#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
> > > +#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> > > +#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
> > > +#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> > > +#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
> > > +#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> > > +#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> > > +#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
> > >
> > > #define SKL_DSSM _MMIO(0x51004)
> > > #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > > b/drivers/gpu/drm/i915/intel_device_info.c
> > > index 85e480bdc673..8d6492afdd6a 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > @@ -972,15 +972,21 @@ void intel_device_info_runtime_init(struct
> > > drm_i915_private *dev_priv)
> > > enabled_mask &= ~BIT(PIPE_D);
> > >
> > > /*
> > > - * At least one pipe should be enabled and if there are
> > > - * disabled pipes, they should be the last ones, with
> > > no holes
> > > - * in the mask.
> > > + * If there are disabled pipes, they should be the last
> > > ones,
> > > + * with no holes in the mask.
> > >*/
> > > - if (enabled_mask == 0 || !is_power_of_2(enabled_mask +
> > > 1))
> > > + if (enabled_mask && !is_power_of_2(enabled_mask + 1))
> > > DRM_ERROR("invalid pipe fuse configuration:
> > > enabled_mask=0x%x\n",
> > > enabled_mask);
> > > else
> > > info->pipe_mask = enabled_mask;
> > > +
> > > + if ((INTEL_GEN(dev_priv) == 9 &&
> > > !IS_GEMINILAKE(dev_priv)) &&
> > > + (dfsm & SKL_DFSM_INTERNAL_DISPLAY_DISABLE))
> > > + i915_modparams.disable_display = true;
> > > +
> > > + if (!enabled_mask)
> > > + i915_modparams.disable_display = true;
> > Do we really need to set the disable_display here? on Gen 7 and 8
> > when
> > it is fused off, we were setting pipe_mask to 0. why that wont work
> > here?
> >
> > INTEL_NUM_PIPES and HAS_DISPLAY both are based on pipe_mask only.
Like said in the commit description, GEN9+ even when fused off the pipe
still outputs some solid color so in future we would need to shut it
down using INTEL_DISPLAY_ENABLED().
>
> Indeed that's one of the problematic features of the patch; the
> ->pipe_mask won't reflect reality. But then
Re: [Intel-gfx] [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
On 23/10/2019 19:12, Mika Kuoppala wrote:
Tapani Pälli writes:
As with commit 3fe0107e45ab, this change fixes multiple tests that are
using the invocation counts. Documentation doesn't list the workaround
for TGL but applying it fixes the tests.
Signed-off-by: Tapani Pälli
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index af8a8183154a..86ded203b2dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs
*engine)
static void tgl_whitelist_build(struct intel_engine_cs *engine)
{
+ struct i915_wa_list *w = >whitelist;
+
+ switch (engine->class) {
+ case RENDER_CLASS:
+ /*
+* WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
Tried to find info about this but failed.
It probably got renamed, it started with CFL stepping C+ and wasn't
listed for ICL.
¯\_(ツ)_/¯
-Lionel
+*
+* This covers 4 registers which are next to one another :
+* - PS_INVOCATION_COUNT
+* - PS_INVOCATION_COUNT_UDW
+* - PS_DEPTH_COUNT
+* - PS_DEPTH_COUNT_UDW
+*/
+ whitelist_reg_ext(w, PS_INVOCATION_COUNT,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
The register spec is identical with gen11 so ok to whitelist.
Reviewed-by: Mika Kuoppala
+ break;
+ default:
+ break;
+ }
}
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
--
2.21.0
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add new CNL PCH ID seen on a CML platform
On Tue, Oct 22, 2019 at 07:09:47PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Add new CNL PCH ID seen on a CML platform
> URL : https://patchwork.freedesktop.org/series/68375/
> State : success
Thanks for the review, pushed to -dinq.
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7147_full -> Patchwork_14914_full
>
>
> Summary
> ---
>
> **SUCCESS**
>
> No regressions found.
>
>
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_14914_full:
>
> ### IGT changes ###
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@kms_cursor_crc@pipe-a-cursor-128x128-random:
> - {shard-tglb}: [FAIL][1] ([fdo#111703]) -> [INCOMPLETE][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7147/shard-tglb2/igt@kms_cursor_...@pipe-a-cursor-128x128-random.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14914/shard-tglb7/igt@kms_cursor_...@pipe-a-cursor-128x128-random.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_14914_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_busy@busy-vcs1:
> - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112080]) +17 similar
> issues
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7147/shard-iclb2/igt@gem_b...@busy-vcs1.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14914/shard-iclb5/igt@gem_b...@busy-vcs1.html
>
> * igt@gem_ctx_isolation@vcs1-reset:
> - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] /
> [fdo#112080]) +2 similar issues
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7147/shard-iclb2/igt@gem_ctx_isolat...@vcs1-reset.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14914/shard-iclb8/igt@gem_ctx_isolat...@vcs1-reset.html
>
> * igt@gem_ctx_isolation@vecs0-s3:
> - shard-kbl: [PASS][7] -> [INCOMPLETE][8] ([fdo#103665])
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7147/shard-kbl6/igt@gem_ctx_isolat...@vecs0-s3.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14914/shard-kbl4/igt@gem_ctx_isolat...@vecs0-s3.html
>
> * igt@gem_exec_parallel@rcs0-contexts:
> - shard-apl: [PASS][9] -> [INCOMPLETE][10] ([fdo#103927])
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7147/shard-apl1/igt@gem_exec_paral...@rcs0-contexts.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14914/shard-apl7/igt@gem_exec_paral...@rcs0-contexts.html
>
> * igt@gem_exec_schedule@preempt-contexts-bsd2:
> - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +18 similar
> issues
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7147/shard-iclb4/igt@gem_exec_sched...@preempt-contexts-bsd2.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14914/shard-iclb3/igt@gem_exec_sched...@preempt-contexts-bsd2.html
>
> * igt@gem_exec_schedule@reorder-wide-bsd:
> - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#111325]) +8 similar
> issues
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7147/shard-iclb8/igt@gem_exec_sched...@reorder-wide-bsd.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14914/shard-iclb1/igt@gem_exec_sched...@reorder-wide-bsd.html
>
> * igt@gem_fence_thrash@bo-write-verify-threaded-y:
> - shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713] /
> [fdo#109100])
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7147/shard-iclb7/igt@gem_fence_thr...@bo-write-verify-threaded-y.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14914/shard-iclb7/igt@gem_fence_thr...@bo-write-verify-threaded-y.html
>
> * igt@gem_persistent_relocs@forked-interruptible-thrashing:
> - shard-hsw: [PASS][17] -> [FAIL][18] ([fdo#112037])
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7147/shard-hsw8/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14914/shard-hsw8/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
>
> * igt@gem_userptr_blits@map-fixed-invalidate-busy:
> - shard-snb: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) +1
> similar issue
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7147/shard-snb2/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
>[20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14914/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html
>
> * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
> - shard-hsw: [PASS][21] -> [DMESG-WARN][22] ([fdo#111870])
>[21]:
Re: [Intel-gfx] [PATCH 2/5] drm/i915/display: Handle fused off HDCP
On Wed, 2019-10-23 at 19:07 +0530, Ramalingam C wrote:
> On 2019-10-18 at 17:41:21 -0700, José Roberto de Souza wrote:
> > HDCP could be fused off, so not all GEN9+ platforms will support
> > it.
> Here HDCP stands for HDCP1.4, so please call it so.
Okay, will update the commit description with the version.
> > Cc: Ville Syrjälä
> > Cc: Martin Peres
> > Reviewed-by: Ville Syrjälä
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> > drivers/gpu/drm/i915/i915_pci.c | 2 ++
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_device_info.c | 3 +++
> > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > 5 files changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index e69fa34528df..f1f41ca8402b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct
> > work_struct *work)
> > bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum
> > port port)
> > {
> > /* PORT E doesn't have HDCP, and PORT F is disabled */
> > - return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
> > + return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
> > }
> >
> > static int
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index f9a3bfe68689..f2280709c8c9 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -612,6 +612,7 @@ static const struct intel_device_info
> > intel_cherryview_info = {
> > .has_logical_ring_preemption = 1, \
> > .display.has_csr = 1, \
> > .has_gt_uc = 1, \
> > + .display.has_hdcp = 1, \
> We dont support HDCP1.4 on chv, though hw supports it.
> > .display.has_ipc = 1, \
> > .ddb_size = 896
> >
> > @@ -655,6 +656,7 @@ static const struct intel_device_info
> > intel_skylake_gt4_info = {
> > .display.has_ddi = 1, \
> > .has_fpga_dbg = 1, \
> > .display.has_fbc = 1, \
> > + .display.has_hdcp = 1, \
> Need not add for each platform, Instead add it into GEN9_FEATURES and
> GEN9_LP_FEATURES.
> HDCP1.4 is supported on all Gen 9+ unless it is fused off.
It was added only to GEN9_FEATURES and GEN9_LP_FEATURES but the git
diff it what you commented, you can check the real output of this patch
here:
https://github.com/zehortigoza/linux/blob/e54a6cfcafffbd210a77dbbafc1cfa09f0def84a/drivers/gpu/drm/i915/i915_pci.c
>
> -Ram.
> > .display.has_psr = 1, \
> > .has_runtime_pm = 1, \
> > .display.has_csr = 1, \
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 6e3ae6e9cbb8..eacc5ba307b0 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7653,6 +7653,7 @@ enum {
> >
> > #define SKL_DFSM _MMIO(0x51000)
> > #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE (1 << 30)
> > +#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
> > #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
> > #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
> > #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index 8d6492afdd6a..753c2cf2fbf4 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -987,6 +987,9 @@ void intel_device_info_runtime_init(struct
> > drm_i915_private *dev_priv)
> >
> > if (!enabled_mask)
> > i915_modparams.disable_display = true;
> > +
> > + if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> > + info->display.has_hdcp = 0;
> > }
> >
> > /* Initialize slice/subslice/EU info */
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index e9940f932d26..118d922261e2 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -138,6 +138,7 @@ enum intel_ppgtt_type {
> > func(has_dsb); \
> > func(has_fbc); \
> > func(has_gmch); \
> > + func(has_hdcp); \
> > func(has_hotplug); \
> > func(has_ipc); \
> > func(has_modular_fia); \
> > --
> > 2.23.0
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/simple-kms: Standardize arguments for callbacks
== Series Details == Series: drm/simple-kms: Standardize arguments for callbacks URL : https://patchwork.freedesktop.org/series/68452/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2d7d097edac5 drm/simple-kms: Standardize arguments for callbacks -:15: WARNING:BAD_SIGN_OFF: 'Acked-by:' is the preferred signature form #15: Acked-By: Thomas Zimmermann (v1) -:26: WARNING:OBSOLETE: drivers/gpu/drm/cirrus/cirrus.c is marked as 'obsolete' in the MAINTAINERS hierarchy. No unnecessary modifications please. -:29: WARNING:OBSOLETE: drivers/gpu/drm/cirrus/cirrus.c is marked as 'obsolete' in the MAINTAINERS hierarchy. No unnecessary modifications please. -:101: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter ' total: 0 errors, 4 warnings, 0 checks, 51 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/bios: add compression parameter block definition
On Tue, Oct 22, 2019 at 05:03:00PM +0300, Jani Nikula wrote:
> Add definition for block 56, the compression parameters.
>
Would this be used on DP connectors for DSC as well?
Manasi
> Cc: Vandita Kulkarni
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 50 +++
> 1 file changed, 50 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index e3045ced4bfe..7f222196d2d5 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -114,6 +114,7 @@ enum bdb_block_id {
> BDB_LVDS_POWER = 44,
> BDB_MIPI_CONFIG = 52,
> BDB_MIPI_SEQUENCE = 53,
> + BDB_COMPRESSION_PARAMETERS = 56,
> BDB_SKIP= 254, /* VBIOS private block, ignore */
> };
>
> @@ -811,4 +812,53 @@ struct bdb_mipi_sequence {
> u8 data[0]; /* up to 6 variable length blocks */
> } __packed;
>
> +/*
> + * Block 56 - Compression Parameters
> + */
> +
> +#define VBT_RC_BUFFER_BLOCK_SIZE_1KB 0
> +#define VBT_RC_BUFFER_BLOCK_SIZE_4KB 1
> +#define VBT_RC_BUFFER_BLOCK_SIZE_16KB2
> +#define VBT_RC_BUFFER_BLOCK_SIZE_64KB3
> +
> +#define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value) ((vbt_value) + 8) /* bits */
> +#define VBT_DSC_MAX_BPP(vbt_value) (6 + (vbt_value) * 2)
> +
> +struct dsc_compression_parameters_entry {
> + u8 version_major:4;
> + u8 version_minor:4;
> +
> + u8 rc_buffer_block_size:2;
> + u8 reserved1:6;
> +
> + /*
> + * Buffer size in bytes:
> + *
> + * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes
> + */
> + u8 rc_buffer_size;
> + u32 slices_per_line;
> +
> + u8 line_buffer_depth:4;
> + u8 reserved2:4;
> +
> + /* Flag Bits 1 */
> + u8 block_prediction_enable:1;
> + u8 reserved3:7;
> +
> + u8 max_bpp; /* mapping */
> +
> + /* Color depth capabilities */
> + u8 reserved4:1;
> + u8 support_8bpc:1;
> + u8 support_10bpc:1;
> + u8 support_12bpc:1;
> + u8 reserved5:4;
> +} __packed;
> +
> +struct bdb_compression_parameters {
> + u16 entry_size;
> + struct dsc_compression_parameters_entry data[16];
> +} __packed;
> +
> #endif /* _INTEL_VBT_DEFS_H_ */
> --
> 2.20.1
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 5/5] drm/i915/display/cnl+: Handle fused off DSC
On Fri, Oct 18, 2019 at 05:41:24PM -0700, José Roberto de Souza wrote:
> DSC could be fused off, so not all GEN10+ platforms will support it.
>
> Cc: Manasi Navare
> Cc: Martin Peres
> Signed-off-by: José Roberto de Souza
Reviewed-by: Manasi Navare
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.c | 4
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 5 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3792d143bea9..e01690701fdd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1888,6 +1888,9 @@ static bool intel_dp_source_supports_dsc(struct
> intel_dp *intel_dp,
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> + if (!INTEL_INFO(dev_priv)->display.has_dsc)
> + return false;
> +
> /* On TGL, DSC is supported on all Pipes */
> if (INTEL_GEN(dev_priv) >= 12)
> return true;
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index f2280709c8c9..09dbfea7c81f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -737,6 +737,7 @@ static const struct intel_device_info
> intel_coffeelake_gt3_info = {
> GEN9_FEATURES, \
> GEN(10), \
> .ddb_size = 1024, \
> + .display.has_dsc = 1, \
> .has_coherent_ggtt = false, \
> GLK_COLORS
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 84fca4f3af5a..bfa301759b6c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7665,6 +7665,7 @@ enum {
> #define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> #define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> #define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
> +#define CNL_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
>
> #define SKL_DSSM _MMIO(0x51004)
> #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 97d962944e48..6a24e85c6d10 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -996,6 +996,10 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
>
> if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
> info->display.has_csr = 0;
> +
> + if (INTEL_GEN(dev_priv) >= 10 &&
> + (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
> + info->display.has_dsc = 0;
> }
>
> /* Initialize slice/subslice/EU info */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 118d922261e2..ba31d68bb7ba 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -136,6 +136,7 @@ enum intel_ppgtt_type {
> func(has_ddi); \
> func(has_dp_mst); \
> func(has_dsb); \
> + func(has_dsc); \
> func(has_fbc); \
> func(has_gmch); \
> func(has_hdcp); \
> --
> 2.23.0
>
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for Extract rps and guc
== Series Details ==
Series: Extract rps and guc
URL : https://patchwork.freedesktop.org/series/68449/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7162 -> Patchwork_14945
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14945/index.html
Known issues
Here are the changes found in Patchwork_14945 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7162/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14945/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] /
[fdo#108569])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7162/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14945/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
Possible fixes
* igt@gem_basic@create-close:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7162/fi-icl-u3/igt@gem_ba...@create-close.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14945/fi-icl-u3/igt@gem_ba...@create-close.html
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-kbl-r: [DMESG-FAIL][7] ([fdo#112096]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7162/fi-kbl-r/igt@i915_selftest@live_gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14945/fi-kbl-r/igt@i915_selftest@live_gt_heartbeat.html
- fi-kbl-guc: [DMESG-FAIL][9] ([fdo#112096]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7162/fi-kbl-guc/igt@i915_selftest@live_gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14945/fi-kbl-guc/igt@i915_selftest@live_gt_heartbeat.html
- fi-icl-u2: [DMESG-FAIL][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7162/fi-icl-u2/igt@i915_selftest@live_gt_heartbeat.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14945/fi-icl-u2/igt@i915_selftest@live_gt_heartbeat.html
* igt@i915_selftest@live_hangcheck:
- fi-bsw-n3050: [INCOMPLETE][13] ([fdo#105876]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7162/fi-bsw-n3050/igt@i915_selftest@live_hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14945/fi-bsw-n3050/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#105876]: https://bugs.freedesktop.org/show_bug.cgi?id=105876
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#110503]: https://bugs.freedesktop.org/show_bug.cgi?id=110503
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (51 -> 45)
--
Additional (1): fi-tgl-u2
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7162 -> Patchwork_14945
CI-20190529: 20190529
CI_DRM_7162: 863a8a1bef9666c2423fc2799d829f465770b514 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5236: 8153b95b53bdef26d2c3e318197d174e982b4265 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14945: ce85c18a87c8501759bffa57c98b6772297aa572 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ce85c18a87c8 drm/i915: Extract the GuC interrupt handlers
0ebf20b3737a drm/i915: Extract GT render power state management
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14945/index.html
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Extract rps and guc
== Series Details == Series: Extract rps and guc URL : https://patchwork.freedesktop.org/series/68449/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0ebf20b3737a drm/i915: Extract GT render power state management -:279: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #279: new file mode 100644 -:284: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #284: FILE: drivers/gpu/drm/i915/gt/intel_rps.c:1: +/* -:285: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #285: FILE: drivers/gpu/drm/i915/gt/intel_rps.c:2: + * SPDX-License-Identifier: MIT -:2162: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #2162: FILE: drivers/gpu/drm/i915/gt/intel_rps.h:1: +/* -:2163: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #2163: FILE: drivers/gpu/drm/i915/gt/intel_rps.h:2: + * SPDX-License-Identifier: MIT -:2205: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #2205: FILE: drivers/gpu/drm/i915/gt/intel_rps_types.h:1: +/* -:2206: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #2206: FILE: drivers/gpu/drm/i915/gt/intel_rps_types.h:2: + * SPDX-License-Identifier: MIT -:2280: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment #2280: FILE: drivers/gpu/drm/i915/gt/intel_rps_types.h:76: + struct mutex mutex; -:2324: WARNING:LONG_LINE: line over 100 characters #2324: FILE: drivers/gpu/drm/i915/gt/selftest_llc.c:50: + intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)), -:2333: WARNING:LONG_LINE: line over 100 characters #2333: FILE: drivers/gpu/drm/i915/gt/selftest_llc.c:60: + intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)), -:5676: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Andi Shyti ' total: 0 errors, 10 warnings, 1 checks, 5468 lines checked ce85c18a87c8 drm/i915: Extract the GuC interrupt handlers ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Making loglevel of PSR2/SU logs same.
On Wed, 2019-10-23 at 13:55 +0530, kamal...@intel.com wrote:
> From: "Ap Kamal"
>
> 'Link CRC error' will now have same error level as
> other PSR2 errors like 'RFB storage error' and
> 'VSC SDP uncorrectable error'.
Yeah this should also be a debug message.
Will push it as soon as we get a shards result.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ap Kamal
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 50f22abcd30e..a6a992729cf5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1437,7 +1437,7 @@ void intel_psr_short_pulse(struct intel_dp
> *intel_dp)
> if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
> DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error,
> disabling PSR\n");
> if (val & DP_PSR_LINK_CRC_ERROR)
> - DRM_ERROR("PSR Link CRC error, disabling PSR\n");
> + DRM_DEBUG_KMS("PSR Link CRC error, disabling PSR\n");
>
> if (val & ~errors)
> DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for Clear Color Support for TGL Render Decompression (rev7)
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev7)
URL : https://patchwork.freedesktop.org/series/66814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14937_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14937_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- {shard-tglb}: [PASS][1] -> [FAIL][2] +2 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb2/igt@kms_pl...@pixel-format-pipe-b-planes-source-clamping.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-tglb3/igt@kms_pl...@pixel-format-pipe-b-planes-source-clamping.html
* igt@kms_plane@pixel-format-pipe-d-planes:
- {shard-tglb}: NOTRUN -> [FAIL][3] +2 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-tglb3/igt@kms_pl...@pixel-format-pipe-d-planes.html
Known issues
Here are the changes found in Patchwork_14937_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@vcs1-clean:
- shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#109276] / [fdo#112080])
+1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_ctx_isolat...@vcs1-clean.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb7/igt@gem_ctx_isolat...@vcs1-clean.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#109276]) +16 similar
issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_exec_sched...@out-order-bsd2.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb3/igt@gem_exec_sched...@out-order-bsd2.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#111325]) +1 similar issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb8/igt@gem_exec_sched...@preemptive-hang-bsd.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-snb: [PASS][10] -> [FAIL][11] ([fdo#112037])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb1/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-snb4/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][12] -> [DMESG-WARN][13] ([fdo#111870])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb7/igt@gem_userptr_bl...@dmabuf-unsync.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-snb6/igt@gem_userptr_bl...@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-hsw: [PASS][14] -> [DMESG-WARN][15] ([fdo#111870])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-hsw5/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
* igt@i915_pm_rpm@modeset-stress-extra-wait:
- shard-glk: [PASS][16] -> [DMESG-WARN][17] ([fdo#105763] /
[fdo#106538])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-glk2/igt@i915_pm_...@modeset-stress-extra-wait.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-glk8/igt@i915_pm_...@modeset-stress-extra-wait.html
* igt@kms_busy@basic-flip-c:
- shard-skl: [PASS][18] -> [DMESG-WARN][19] ([fdo#106107])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl3/igt@kms_b...@basic-flip-c.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-skl8/igt@kms_b...@basic-flip-c.html
* igt@kms_busy@extended-pageflip-hang-oldfb-render-a:
- shard-iclb: [PASS][20] -> [INCOMPLETE][21] ([fdo#107713])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb3/igt@kms_b...@extended-pageflip-hang-oldfb-render-a.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14937/shard-iclb7/igt@kms_b...@extended-pageflip-hang-oldfb-render-a.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][22] -> [INCOMPLETE][23] ([fdo#103665])
[22]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Release ctx->engine_mutex after iteration
== Series Details == Series: drm/i915/selftests: Release ctx->engine_mutex after iteration URL : https://patchwork.freedesktop.org/series/68420/ State : success == Summary == CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14936_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14936_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([fdo#104108]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl10/igt@gem_soft...@noreloc-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14936/shard-skl6/igt@gem_soft...@noreloc-s3.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-hsw: [PASS][3] -> [DMESG-WARN][4] ([fdo#111870]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14936/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: - shard-snb: [PASS][5] -> [DMESG-WARN][6] ([fdo#111870]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14936/shard-snb2/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html * igt@i915_pm_rpm@fences: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([fdo#103313]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl4/igt@i915_pm_...@fences.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14936/shard-kbl2/igt@i915_pm_...@fences.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl2/igt@i915_susp...@sysfs-reader.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14936/shard-apl5/igt@i915_susp...@sysfs-reader.html * igt@kms_color@pipe-a-ctm-0-5: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([fdo#106107]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl6/igt@kms_co...@pipe-a-ctm-0-5.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14936/shard-skl10/igt@kms_co...@pipe-a-ctm-0-5.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#110741]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl8/igt@kms_cursor_...@pipe-a-cursor-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14936/shard-skl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#109507]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl10/igt@kms_f...@flip-vs-suspend-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14936/shard-skl6/igt@kms_f...@flip-vs-suspend-interruptible.html - shard-hsw: [PASS][17] -> [INCOMPLETE][18] ([fdo#103540]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw2/igt@kms_f...@flip-vs-suspend-interruptible.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14936/shard-hsw6/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [fdo#110403]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl7/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14936/shard-skl8/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html Possible fixes * igt@gem_userptr_blits@dmabuf-unsync: - shard-hsw: [DMESG-WARN][21] ([fdo#111870]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw5/igt@gem_userptr_bl...@dmabuf-unsync.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14936/shard-hsw2/igt@gem_userptr_bl...@dmabuf-unsync.html * igt@gem_userptr_blits@map-fixed-invalidate-busy: - shard-snb: [DMESG-WARN][23] ([fdo#111870]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb5/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14936/shard-snb1/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html * igt@gem_userptr_blits@unsync-unmap-cycles: - shard-apl: [INCOMPLETE][25] ([fdo#103927]) -> [PASS][26] +1
[Intel-gfx] [PATCH] drm: Add support for integrated privacy screens
Certain laptops now come with panels that have integrated privacy
screens on them. This patch adds support for such panels by adding
a privacy-screen property to the drm_connector for the panel, that
the userspace can then use to control and check the status. The idea
was discussed here:
https://lkml.org/lkml/2019/10/1/786
ACPI methods are used to identify, query and control privacy screen:
* Identifying an ACPI object corresponding to the panel: The patch
follows ACPI Spec 6.3 (available at
https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf).
Pages 1119 - 1123 describe what I believe, is a standard way of
identifying / addressing "display panels" in the ACPI tables, thus
allowing kernel to attach ACPI nodes to the panel. IMHO, this ability
to identify and attach ACPI nodes to drm connectors may be useful for
reasons other privacy-screens, in future.
* Identifying the presence of privacy screen, and controlling it, is done
via ACPI _DSM methods.
Currently, this is done only for the Intel display ports. But in future,
this can be done for any other ports if the hardware becomes available
(e.g. external monitors supporting integrated privacy screens?).
Also, this code can be extended in future to support non-ACPI methods
(e.g. using a kernel GPIO driver to toggle a gpio that controls the
privacy-screen).
Signed-off-by: Rajat Jain
---
drivers/gpu/drm/Makefile| 1 +
drivers/gpu/drm/drm_atomic_uapi.c | 5 +
drivers/gpu/drm/drm_connector.c | 38 +
drivers/gpu/drm/drm_privacy_screen.c| 176
drivers/gpu/drm/i915/display/intel_dp.c | 3 +
include/drm/drm_connector.h | 18 +++
include/drm/drm_mode_config.h | 7 +
include/drm/drm_privacy_screen.h| 33 +
8 files changed, 281 insertions(+)
create mode 100644 drivers/gpu/drm/drm_privacy_screen.c
create mode 100644 include/drm/drm_privacy_screen.h
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 82ff826b33cc..e1fc33d69bb7 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -19,6 +19,7 @@ drm-y :=drm_auth.o drm_cache.o \
drm_syncobj.o drm_lease.o drm_writeback.o drm_client.o \
drm_client_modeset.o drm_atomic_uapi.o drm_hdcp.o
+drm-$(CONFIG_ACPI) += drm_privacy_screen.o
drm-$(CONFIG_DRM_LEGACY) += drm_legacy_misc.o drm_bufs.o drm_context.o
drm_dma.o drm_scatter.o drm_lock.o
drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o
drm-$(CONFIG_DRM_VM) += drm_vm.o
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 7a26bfb5329c..44131165e4ea 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#include
#include
@@ -766,6 +767,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
fence_ptr);
} else if (property == connector->max_bpc_property) {
state->max_requested_bpc = val;
+ } else if (property == config->privacy_screen_property) {
+ drm_privacy_screen_set_val(connector, val);
} else if (connector->funcs->atomic_set_property) {
return connector->funcs->atomic_set_property(connector,
state, property, val);
@@ -842,6 +845,8 @@ drm_atomic_connector_get_property(struct drm_connector
*connector,
*val = 0;
} else if (property == connector->max_bpc_property) {
*val = state->max_requested_bpc;
+ } else if (property == config->privacy_screen_property) {
+ *val = drm_privacy_screen_get_val(connector);
} else if (connector->funcs->atomic_get_property) {
return connector->funcs->atomic_get_property(connector,
state, property, val);
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 4c766624b20d..a31e0382132b 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -821,6 +821,11 @@ static const struct drm_prop_enum_list
drm_panel_orientation_enum_list[] = {
{ DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, "Right Side Up" },
};
+static const struct drm_prop_enum_list drm_privacy_screen_enum_list[] = {
+ { DRM_PRIVACY_SCREEN_DISABLED, "Disabled" },
+ { DRM_PRIVACY_SCREEN_ENABLED, "Enabled" },
+};
+
static const struct drm_prop_enum_list drm_dvi_i_select_enum_list[] = {
{ DRM_MODE_SUBCONNECTOR_Automatic, "Automatic" }, /* DVI-I and TV-out */
{ DRM_MODE_SUBCONNECTOR_DVID, "DVI-D" }, /* DVI-I */
@@ -2253,6 +2258,39 @@ static void drm_tile_group_free(struct kref *kref)
kfree(tg);
}
+/**
+ * drm_connector_init_privacy_screen_property -
+ * create and attach the connecter's privacy-screen property.
+ * @connector:
Re: [Intel-gfx] [PATCH i-g-t v2] tests/kms_content_protection: check i915 and generic debugfs name for HDCP caps
On 2019-10-21 3:42 p.m., Bhawanpreet Lakha wrote:
> The content protection tests only start if this debugfs entry exists.
> Since the name is specific to intel driver these tests cannot be used with
> other drivers. So we should check generic debugfs name also
>
> v2: Check i915_* if device is i915, otherwise check the generic name.
>
> Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
Harry
> ---
> tests/kms_content_protection.c | 12 ++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/tests/kms_content_protection.c b/tests/kms_content_protection.c
> index e676b60b..42fdc459 100644
> --- a/tests/kms_content_protection.c
> +++ b/tests/kms_content_protection.c
> @@ -554,7 +554,11 @@ static bool sink_hdcp_capable(igt_output_t *output)
> if (fd < 0)
> return false;
>
> - debugfs_read(fd, "i915_hdcp_sink_capability", buf);
> + if (is_i915_device(data.drm_fd))
> + debugfs_read(fd, "i915_hdcp_sink_capability", buf);
> + else
> + debugfs_read(fd, "hdcp_sink_capability", buf);
> +
> close(fd);
>
> igt_debug("Sink capability: %s\n", buf);
> @@ -571,7 +575,11 @@ static bool sink_hdcp2_capable(igt_output_t *output)
> if (fd < 0)
> return false;
>
> - debugfs_read(fd, "i915_hdcp_sink_capability", buf);
> + if (is_i915_device(data.drm_fd))
> + debugfs_read(fd, "i915_hdcp_sink_capability", buf);
> + else
> + debugfs_read(fd, "hdcp_sink_capability", buf);
> +
> close(fd);
>
> igt_debug("Sink capability: %s\n", buf);
>
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: pfit/scaler rework prep stuff
== Series Details ==
Series: drm/i915: pfit/scaler rework prep stuff
URL : https://patchwork.freedesktop.org/series/68409/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14934_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14934_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_crc@pipe-c-cursor-size-change:
- {shard-tglb}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb5/igt@kms_cursor_...@pipe-c-cursor-size-change.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-tglb3/igt@kms_cursor_...@pipe-c-cursor-size-change.html
Known issues
Here are the changes found in Patchwork_14934_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@vcs1-s3:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_ctx_isolat...@vcs1-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb8/igt@gem_ctx_isolat...@vcs1-s3.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-snb: [PASS][5] -> [FAIL][6] ([fdo#111925])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb7/igt@gem_...@in-flight-contexts-immediate.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-snb5/igt@gem_...@in-flight-contexts-immediate.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +14 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_exec_sched...@out-order-bsd2.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb8/igt@gem_exec_sched...@out-order-bsd2.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +4 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb8/igt@gem_exec_sched...@preemptive-hang-bsd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-iclb2/igt@gem_exec_sched...@preemptive-hang-bsd.html
*
igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
- shard-hsw: [PASS][11] -> [TIMEOUT][12] ([fdo#112068 ])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw6/igt@gem_persistent_rel...@forked-interruptible-faulting-reloc-thrash-inactive.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-hsw6/igt@gem_persistent_rel...@forked-interruptible-faulting-reloc-thrash-inactive.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-snb: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870]) +2
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-hsw: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-hsw4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103665])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl4/igt@gem_workarou...@suspend-resume-fd.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-kbl3/igt@gem_workarou...@suspend-resume-fd.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +6
similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl2/igt@i915_susp...@sysfs-reader.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-apl8/igt@i915_susp...@sysfs-reader.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-hsw: [PASS][21] -> [INCOMPLETE][22] ([fdo#103540])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw1/igt@kms_f...@2x-flip-vs-suspend.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14934/shard-hsw2/igt@kms_f...@2x-flip-vs-suspend.html
*
Re: [Intel-gfx] [PATCH] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
Tapani Pälli writes:
> As with commit 3fe0107e45ab, this change fixes multiple tests that are
> using the invocation counts. Documentation doesn't list the workaround
> for TGL but applying it fixes the tests.
>
> Signed-off-by: Tapani Pälli
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 20
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index af8a8183154a..86ded203b2dd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs
> *engine)
>
> static void tgl_whitelist_build(struct intel_engine_cs *engine)
> {
> + struct i915_wa_list *w = >whitelist;
> +
> + switch (engine->class) {
> + case RENDER_CLASS:
> + /*
> + * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
Tried to find info about this but failed.
> + *
> + * This covers 4 registers which are next to one another :
> + * - PS_INVOCATION_COUNT
> + * - PS_INVOCATION_COUNT_UDW
> + * - PS_DEPTH_COUNT
> + * - PS_DEPTH_COUNT_UDW
> + */
> + whitelist_reg_ext(w, PS_INVOCATION_COUNT,
> + RING_FORCE_TO_NONPRIV_ACCESS_RD |
> + RING_FORCE_TO_NONPRIV_RANGE_4);
The register spec is identical with gen11 so ok to whitelist.
Reviewed-by: Mika Kuoppala
> + break;
> + default:
> + break;
> + }
> }
>
> void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> --
> 2.21.0
>
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [RFC PATCH v2 1/3] tests/gem_exec_reloc: Don't filter out addresses on full PPGTT
Quoting Janusz Krzysztofik (2019-10-23 16:29:15)
> Commit a355b2d6eb42 ("igt/gem_exec_reloc: Filter out unavailable
> addresses for !ppgtt") introduced filtering of addresses possibly
> occupied by other users of shared GTT. Unfortunately, that filtering
> is unconditional, no matter if running on old shared GTT or not. When
> running on full (non-aliasing) PPGTT, that may result in errors other
> than those intended to be skipped over being silently ignored.
>
> Skip over unavailable addresses only when not running on full PPGTT.
>
> Signed-off-by: Janusz Krzysztofik
> Cc: Chris Wilson
> ---
> tests/i915/gem_exec_reloc.c | 26 ++
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c
> index fdd9661d..f7fc0ea7 100644
> --- a/tests/i915/gem_exec_reloc.c
> +++ b/tests/i915/gem_exec_reloc.c
> @@ -539,12 +539,13 @@ static void basic_range(int fd, unsigned flags)
> obj[n].offset = (1ull << (i + 12)) - 4096;
> obj[n].offset = gen8_canonical_address(obj[n].offset);
> obj[n].flags = EXEC_OBJECT_PINNED |
> EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> - gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
> - execbuf.buffers_ptr = to_user_pointer([n]);
> - execbuf.buffer_count = 1;
> - if (__gem_execbuf(fd, ))
> - continue;
> -
> + if (!gem_uses_full_ppgtt(fd)) {
Oh boy, I can think of an [unmentionable] instance where this isn't true
either.
It should be true indeed unless the kernel is interfering with the
user's GTT...
-Chris
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Re: [Intel-gfx] [PATCH] drm/simple-kms: Standardize arguments for callbacks
On Wed, Oct 23, 2019 at 12:13 PM Daniel Vetter wrote: > Passing the wrong type feels icky, everywhere else we use the pipe as > the first parameter. Spotted while discussing patches with Thomas > Zimmermann. > > v2: Make xen compile correctly > > Acked-By: Thomas Zimmermann (v1) > Cc: Thomas Zimmermann > Cc: Noralf Trønnes > Cc: Gerd Hoffmann > Cc: Eric Anholt > Cc: Emil Velikov > Cc: virtualizat...@lists.linux-foundation.org > Cc: Linus Walleij > Signed-off-by: Daniel Vetter Makes perfect sense. Reviewed-by: Linus Walleij Yours, Linus Walleij ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/10] drm/i915: Flush idle barriers when waiting
Quoting Tvrtko Ursulin (2019-10-14 14:08:12)
>
> On 11/10/2019 16:11, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-10-11 15:56:35)
> >>
> >> On 10/10/2019 08:14, Chris Wilson wrote:
> >>> If we do find ourselves with an idle barrier inside our active while
> >>> waiting, attempt to flush it by emitting a pulse using the kernel
> >>> context.
> >>
> >> The point of this one completely escapes me at the moment. Idle barriers
> >> are kept in there to be consumed by the engine_pm parking, so if any
> >> random waiter finds some (there will always be some, as long as the
> >> engine executed some user context, right?),
> >
> > Not any random waiter; the waiter has to be waiting on a context that
> > was active and so setup a barrier.
> >
> >> why would it want to handle
> >> them? Again just to use the opportunity for some house keeping? But what
> >> if the system is otherwise quite busy and a low-priority client just
> >> happens to want to wait on something silly?
> >
> > There's no guarantee that it will ever be flushed. So why wouldn't we
> > use a low priority request to give a semblance of forward progress and
> > give a guarantee that the wait will complete.
> >
> > It's a hypothetical point, there are no waiters that need to wait upon
> > their own barriers at present. We are just completing the picture for
> > idle barrier tracking.
>
> Hm I was mistakenly remembering things like rpcs reconfiguration would
> wait on ce->active, but I forgot about your trick with putting kernel
> context request on an user timeline.
>
> I guess it is fine there, but since, and as you have said, it is
> hypothetical, then this patch is dead code and can wait.
Ok, I have a use for this now! In "drm/i915: Allow userspace to specify
ringsize on construction" we need to wait on the context itself to idle,
i.e. i915_active_wait(>active) and so now it is possible for us to
be waiting on an idle_barrier() and so the flush be beneficial.
static int __apply_ringsize(struct intel_context *ce, void *sz)
{
int err;
err = i915_active_wait(>active);
if (err < 0)
return err;
if (intel_context_lock_pinned(ce))
return -EINTR;
if (intel_context_is_pinned(ce)) {
err = -EBUSY; /* In active use, come back later! */
goto unlock;
}
if (test_bit(CONTEXT_ALLOC_BIT, >flags)) {
struct intel_ring *ring;
/* Replace the existing ringbuffer */
ring = intel_engine_create_ring(ce->engine,
(unsigned long)sz);
if (IS_ERR(ring)) {
err = PTR_ERR(ring);
goto unlock;
}
intel_ring_put(ce->ring);
ce->ring = ring;
/* Context image will be updated on next pin */
} else {
ce->ring = sz;
}
unlock:
intel_context_unlock_pinned(ce);
return err;
}
-Chris
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[Intel-gfx] [RFC PATCH v2 1/3] tests/gem_exec_reloc: Don't filter out addresses on full PPGTT
Commit a355b2d6eb42 ("igt/gem_exec_reloc: Filter out unavailable
addresses for !ppgtt") introduced filtering of addresses possibly
occupied by other users of shared GTT. Unfortunately, that filtering
is unconditional, no matter if running on old shared GTT or not. When
running on full (non-aliasing) PPGTT, that may result in errors other
than those intended to be skipped over being silently ignored.
Skip over unavailable addresses only when not running on full PPGTT.
Signed-off-by: Janusz Krzysztofik
Cc: Chris Wilson
---
tests/i915/gem_exec_reloc.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c
index fdd9661d..f7fc0ea7 100644
--- a/tests/i915/gem_exec_reloc.c
+++ b/tests/i915/gem_exec_reloc.c
@@ -539,12 +539,13 @@ static void basic_range(int fd, unsigned flags)
obj[n].offset = (1ull << (i + 12)) - 4096;
obj[n].offset = gen8_canonical_address(obj[n].offset);
obj[n].flags = EXEC_OBJECT_PINNED |
EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
- gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
- execbuf.buffers_ptr = to_user_pointer([n]);
- execbuf.buffer_count = 1;
- if (__gem_execbuf(fd, ))
- continue;
-
+ if (!gem_uses_full_ppgtt(fd)) {
+ gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
+ execbuf.buffers_ptr = to_user_pointer([n]);
+ execbuf.buffer_count = 1;
+ if (__gem_execbuf(fd, ))
+ continue;
+ }
igt_debug("obj[%d] handle=%d, address=%llx\n",
n, obj[n].handle, (long long)obj[n].offset);
@@ -559,12 +560,13 @@ static void basic_range(int fd, unsigned flags)
obj[n].offset = 1ull << (i + 12);
obj[n].offset = gen8_canonical_address(obj[n].offset);
obj[n].flags = EXEC_OBJECT_PINNED |
EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
- gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
- execbuf.buffers_ptr = to_user_pointer([n]);
- execbuf.buffer_count = 1;
- if (__gem_execbuf(fd, ))
- continue;
-
+ if (!gem_uses_full_ppgtt(fd)) {
+ gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
+ execbuf.buffers_ptr = to_user_pointer([n]);
+ execbuf.buffer_count = 1;
+ if (__gem_execbuf(fd, ))
+ continue;
+ }
igt_debug("obj[%d] handle=%d, address=%llx\n",
n, obj[n].handle, (long long)obj[n].offset);
--
2.21.0
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[Intel-gfx] [RFC PATCH v2 3/3] tests/gem_exec_reloc: Detect minimum batch size
The basic-range subtest have been already taught to calculate softpin
offsets from minimum batch size, however it still uses a hardcoded
value of 4kB. On future backends with possibly bigger minimum batch
sizes this subtest will fail as buffer objects may overlap.
Detect minimum batch size instead of using a hardcoded value. To avoid
conflicts with addresses occupied by other users, do that only when
running on full PPGTT. Platforms without full PPGTT are not expected
to support backends with minimum batch sizes greater than 4kB.
Signed-off-by: Janusz Krzysztofik
---
tests/i915/gem_exec_reloc.c | 41 +++--
1 file changed, 39 insertions(+), 2 deletions(-)
diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c
index 61401ea7..b71fe0be 100644
--- a/tests/i915/gem_exec_reloc.c
+++ b/tests/i915/gem_exec_reloc.c
@@ -511,6 +511,42 @@ static uint64_t gen8_canonical_address(uint64_t address)
return sign_extend(address, 47);
}
+static int local_gem_minimum_batch_order(int fd)
+{
+ struct drm_i915_gem_exec_object2 obj;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ uint64_t gtt_size = gem_aperture_size(fd);
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ int batch_order = 12;
+ uint64_t batch_size = 1ull << batch_order; /* 4096 */
+
+ if (!gem_uses_full_ppgtt(fd) || !gem_has_softpin(fd))
+ return batch_order;
+
+ memset(, 0, sizeof(obj));
+ memset(, 0, sizeof(execbuf));
+
+ obj.handle = gem_create(fd, 4096);
+ obj.flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ while (batch_size < gtt_size) {
+ obj.offset = gtt_size - batch_size;
+ obj.offset = gen8_canonical_address(obj.offset);
+ gem_write(fd, obj.handle, 0, , sizeof(bbe));
+ execbuf.buffers_ptr = to_user_pointer();
+ execbuf.buffer_count = 1;
+ if (!__gem_execbuf(fd, )) {
+ igt_debug("batch_order=%d, batch_size=%llx\n",
+ batch_order, (long long)batch_size);
+ break;
+ }
+ batch_size <<= 1;
+ batch_order++;
+ }
+ gem_close(fd, obj.handle);
+ igt_require(batch_size < gtt_size);
+ return batch_order;
+}
+
static void basic_range(int fd, unsigned flags)
{
struct drm_i915_gem_relocation_entry reloc[128];
@@ -520,8 +556,8 @@ static void basic_range(int fd, unsigned flags)
uint64_t gtt_size = gem_aperture_size(fd);
const uint32_t bbe = MI_BATCH_BUFFER_END;
igt_spin_t *spin = NULL;
- int batch_order = 12;
- uint64_t batch_size = 1ull << batch_order; /* 4096 */
+ int batch_order = local_gem_minimum_batch_order(fd);
+ uint64_t batch_size = 1ull << batch_order;
int count, n;
igt_require(gem_has_softpin(fd));
@@ -530,6 +566,7 @@ static void basic_range(int fd, unsigned flags)
;
count -= batch_order;
+ igt_require(count);
memset(obj, 0, sizeof(obj));
memset(reloc, 0, sizeof(reloc));
--
2.21.0
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[Intel-gfx] [RFC PATCH v2 2/3] tests/gem_exec_reloc: Calculate softpin offsets from batch size
From: Janusz Krzysztofik
The basic-range subtest assumes 4kB minimum batch size. On future
backends with possibly bigger minimum batch sizes this subtest will
fail as buffer objects may overlap on softpin. To avoid object
overlapping, softpin offsets need to be calculated with actual minimum
batch size in mind.
Replace hardcoded constants corresponding to the assumed 4kB value with
variables supposed to reflect actual batch size. For now, the
variables are still initialized with values specific to the 4kB minimum
batch size, which are suitable for backends currently supported by IGT.
Signed-off-by: Janusz Krzysztofik
Cc: Katarzyna Dec
Cc: Stuart Summers
---
tests/i915/gem_exec_reloc.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c
index f7fc0ea7..61401ea7 100644
--- a/tests/i915/gem_exec_reloc.c
+++ b/tests/i915/gem_exec_reloc.c
@@ -520,14 +520,16 @@ static void basic_range(int fd, unsigned flags)
uint64_t gtt_size = gem_aperture_size(fd);
const uint32_t bbe = MI_BATCH_BUFFER_END;
igt_spin_t *spin = NULL;
+ int batch_order = 12;
+ uint64_t batch_size = 1ull << batch_order; /* 4096 */
int count, n;
igt_require(gem_has_softpin(fd));
- for (count = 12; gtt_size >> (count + 1); count++)
+ for (count = batch_order; gtt_size >> (count + 1); count++)
;
- count -= 12;
+ count -= batch_order;
memset(obj, 0, sizeof(obj));
memset(reloc, 0, sizeof(reloc));
@@ -536,7 +538,7 @@ static void basic_range(int fd, unsigned flags)
n = 0;
for (int i = 0; i <= count; i++) {
obj[n].handle = gem_create(fd, 4096);
- obj[n].offset = (1ull << (i + 12)) - 4096;
+ obj[n].offset = (1ull << (i + batch_order)) - batch_size;
obj[n].offset = gen8_canonical_address(obj[n].offset);
obj[n].flags = EXEC_OBJECT_PINNED |
EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
if (!gem_uses_full_ppgtt(fd)) {
@@ -557,7 +559,7 @@ static void basic_range(int fd, unsigned flags)
}
for (int i = 1; i < count; i++) {
obj[n].handle = gem_create(fd, 4096);
- obj[n].offset = 1ull << (i + 12);
+ obj[n].offset = 1ull << (i + batch_order);
obj[n].offset = gen8_canonical_address(obj[n].offset);
obj[n].flags = EXEC_OBJECT_PINNED |
EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
if (!gem_uses_full_ppgtt(fd)) {
--
2.21.0
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Re: [Intel-gfx] [PATCH i-g-t v2] tests/kms_content_protection: check i915 and generic debugfs name for HDCP caps
On 2019-10-21 at 15:42:59 -0400, Bhawanpreet Lakha wrote:
> The content protection tests only start if this debugfs entry exists.
> Since the name is specific to intel driver these tests cannot be used with
> other drivers. So we should check generic debugfs name also
>
> v2: Check i915_* if device is i915, otherwise check the generic name.
>
> Signed-off-by: Bhawanpreet Lakha
Looks good to me.
Reviewed-by: Ramalingam C
> ---
> tests/kms_content_protection.c | 12 ++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/tests/kms_content_protection.c b/tests/kms_content_protection.c
> index e676b60b..42fdc459 100644
> --- a/tests/kms_content_protection.c
> +++ b/tests/kms_content_protection.c
> @@ -554,7 +554,11 @@ static bool sink_hdcp_capable(igt_output_t *output)
> if (fd < 0)
> return false;
>
> - debugfs_read(fd, "i915_hdcp_sink_capability", buf);
> + if (is_i915_device(data.drm_fd))
> + debugfs_read(fd, "i915_hdcp_sink_capability", buf);
> + else
> + debugfs_read(fd, "hdcp_sink_capability", buf);
> +
> close(fd);
>
> igt_debug("Sink capability: %s\n", buf);
> @@ -571,7 +575,11 @@ static bool sink_hdcp2_capable(igt_output_t *output)
> if (fd < 0)
> return false;
>
> - debugfs_read(fd, "i915_hdcp_sink_capability", buf);
> + if (is_i915_device(data.drm_fd))
> + debugfs_read(fd, "i915_hdcp_sink_capability", buf);
> + else
> + debugfs_read(fd, "hdcp_sink_capability", buf);
> +
> close(fd);
>
> igt_debug("Sink capability: %s\n", buf);
> --
> 2.17.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support (rev3)
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev3)
URL : https://patchwork.freedesktop.org/series/68028/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7159 -> Patchwork_14944
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14944:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-tgl-u}: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/fi-tgl-u/igt@run...@aborted.html
- {fi-tgl-u2}:NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/fi-tgl-u2/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_14944 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/fi-bxt-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@rcs0:
- fi-apl-guc: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-apl-guc/igt@gem_ctx_swi...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/fi-apl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@gem_flink_basic@basic:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724] /
[fdo#112052 ])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-icl-u3/igt@gem_flink_ba...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/fi-icl-u3/igt@gem_flink_ba...@basic.html
* igt@i915_module_load@reload-with-fault-injection:
- fi-bsw-n3050: [PASS][9] -> [INCOMPLETE][10] ([fdo#105876])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-bsw-n3050/igt@i915_module_l...@reload-with-fault-injection.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/fi-bsw-n3050/igt@i915_module_l...@reload-with-fault-injection.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][11] -> [DMESG-FAIL][12] ([fdo#111678])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
* igt@kms_prop_blob@basic:
- fi-icl-u3: [PASS][13] -> [DMESG-WARN][14] ([fdo#107724]) +2
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-icl-u3/igt@kms_prop_b...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/fi-icl-u3/igt@kms_prop_b...@basic.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-bdw-gvtdvm: [INCOMPLETE][15] ([fdo#112063]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-bdw-gvtdvm/igt@gem_ctx_cre...@basic-files.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/fi-bdw-gvtdvm/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_fence@basic-wait-default:
- fi-icl-u3: [DMESG-WARN][17] ([fdo#107724]) -> [PASS][18] +2
similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-icl-u3/igt@gem_exec_fe...@basic-wait-default.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/fi-icl-u3/igt@gem_exec_fe...@basic-wait-default.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [DMESG-FAIL][19] ([fdo#112050 ]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-whl-u: [DMESG-FAIL][21] -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-whl-u/igt@i915_selftest@live_gt_heartbeat.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/fi-whl-u/igt@i915_selftest@live_gt_heartbeat.html
- fi-skl-iommu: [DMESG-FAIL][23] ([fdo#112096]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-skl-iommu/igt@i915_selftest@live_gt_heartbeat.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14944/fi-skl-iommu/igt@i915_selftest@live_gt_heartbeat.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [DMESG-FAIL][25]
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/3] drm/i915/guc: Enable guc logging on guc log relay write
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/guc: Enable guc logging on guc
log relay write
URL : https://patchwork.freedesktop.org/series/68406/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14932_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_14932_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14932_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14932_full:
### IGT changes ###
Warnings
* igt@i915_pm_rc6_residency@media-rc6-accuracy:
- shard-iclb: [SKIP][1] ([fdo#109289]) -> [SKIP][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb8/igt@i915_pm_rc6_reside...@media-rc6-accuracy.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-iclb1/igt@i915_pm_rc6_reside...@media-rc6-accuracy.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_fence_thrash@bo-write-verify-threaded-y:
- {shard-tglb}: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-tglb6/igt@gem_fence_thr...@bo-write-verify-threaded-y.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-tglb6/igt@gem_fence_thr...@bo-write-verify-threaded-y.html
Known issues
Here are the changes found in Patchwork_14932_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@vcs1-s3:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_ctx_isolat...@vcs1-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-iclb3/igt@gem_ctx_isolat...@vcs1-s3.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-snb: [PASS][7] -> [FAIL][8] ([fdo#111925])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb7/igt@gem_...@in-flight-contexts-immediate.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-snb2/igt@gem_...@in-flight-contexts-immediate.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +8 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_exec_sched...@out-order-bsd2.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-iclb3/igt@gem_exec_sched...@out-order-bsd2.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#111325]) +3 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb8/igt@gem_exec_sched...@preemptive-hang-bsd.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#104108])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl10/igt@gem_soft...@noreloc-s3.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-skl8/igt@gem_soft...@noreloc-s3.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-snb: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) +2
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-snb6/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103665])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl4/igt@gem_workarou...@suspend-resume-fd.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-kbl4/igt@gem_workarou...@suspend-resume-fd.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-apl: [PASS][19] -> [SKIP][20] ([fdo#109271])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl6/igt@i915_pm_rc6_reside...@rc6-accuracy.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14932/shard-apl4/igt@i915_pm_rc6_reside...@rc6-accuracy.html
- shard-skl: [PASS][21] -> [SKIP][22] ([fdo#109271])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl9/igt@i915_pm_rc6_reside...@rc6-accuracy.html
[22]:
Re: [Intel-gfx] [PATCH 08/14] drm/i915: Complete crtc hw/uapi split, v2.
Op 22-10-2019 om 20:32 schreef Ville Syrjälä:
> On Thu, Oct 17, 2019 at 03:20:59PM +0200, Maarten Lankhorst wrote:
>> Now that we separated everything into uapi and hw, it's
>> time to make the split definitive. Remove the union and
>> make a copy of the hw state on modeset and fastset.
>>
>> Color blobs are copied in crtc atomic_check(), right
>> before color management is checked.
>>
>> Changes since v1:
>> - Copy all blobs immediately after drm_atomic_helper_check_modeset().
>> - Clear crtc_state->hw on disable, instead of using clear_intel_crtc_state().
>>
>> Signed-off-by: Maarten Lankhorst
>> ---
>> drivers/gpu/drm/i915/display/intel_atomic.c | 44 ++
>> drivers/gpu/drm/i915/display/intel_atomic.h | 2 +
>> drivers/gpu/drm/i915/display/intel_display.c | 45 ---
>> .../drm/i915/display/intel_display_types.h| 9 ++--
>> 4 files changed, 89 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
>> b/drivers/gpu/drm/i915/display/intel_atomic.c
>> index 7cf13b9c7d38..266d0ce9d03d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
>> @@ -195,6 +195,14 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>>
>> __drm_atomic_helper_crtc_duplicate_state(crtc, _state->uapi);
>>
>> +/* copy color blobs */
>> +if (crtc_state->hw.degamma_lut)
>> +drm_property_blob_get(crtc_state->hw.degamma_lut);
>> +if (crtc_state->hw.ctm)
>> +drm_property_blob_get(crtc_state->hw.ctm);
>> +if (crtc_state->hw.gamma_lut)
>> +drm_property_blob_get(crtc_state->hw.gamma_lut);
>> +
>> crtc_state->update_pipe = false;
>> crtc_state->disable_lp_wm = false;
>> crtc_state->disable_cxsr = false;
>> @@ -208,6 +216,41 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>> return _state->uapi;
>> }
>>
>> +static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
>> +{
>> +drm_property_blob_put(crtc_state->hw.degamma_lut);
>> +drm_property_blob_put(crtc_state->hw.gamma_lut);
>> +drm_property_blob_put(crtc_state->hw.ctm);
>> +}
>> +
>> +void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
>> +{
>> +intel_crtc_put_color_blobs(crtc_state);
>> +}
>> +
>> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
>> +{
>> +intel_crtc_put_color_blobs(crtc_state);
>> +
>> +if (crtc_state->uapi.degamma_lut)
>> +crtc_state->hw.degamma_lut =
>> +drm_property_blob_get(crtc_state->uapi.degamma_lut);
>> +else
>> +crtc_state->hw.degamma_lut = NULL;
> Side note: If drm_property_blob_get() would pass NULL through this kind
> of stuff would look a lot less annoying.
>
>> +
>> +if (crtc_state->uapi.gamma_lut)
>> +crtc_state->hw.gamma_lut =
>> +drm_property_blob_get(crtc_state->uapi.gamma_lut);
>> +else
>> +crtc_state->hw.gamma_lut = NULL;
>> +
>> +if (crtc_state->uapi.ctm)
>> +crtc_state->hw.ctm =
>> +drm_property_blob_get(crtc_state->uapi.ctm);
>> +else
>> +crtc_state->hw.ctm = NULL;
>> +}
>> +
>> /**
>> * intel_crtc_destroy_state - destroy crtc state
>> * @crtc: drm crtc
>> @@ -223,6 +266,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
>> struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
>>
>> __drm_atomic_helper_crtc_destroy_state(_state->uapi);
>> +intel_crtc_free_hw_state(crtc_state);
>> kfree(crtc_state);
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
>> b/drivers/gpu/drm/i915/display/intel_atomic.h
>> index 58065d3161a3..42be91e0772a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
>> @@ -35,6 +35,8 @@ intel_digital_connector_duplicate_state(struct
>> drm_connector *connector);
>> struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
>> void intel_crtc_destroy_state(struct drm_crtc *crtc,
>> struct drm_crtc_state *state);
>> +void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
>> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
>> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
>> void intel_atomic_state_clear(struct drm_atomic_state *state);
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index 06c593d56d92..c009489641bd 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -114,6 +114,7 @@ static const u64 cursor_format_modifiers[] = {
>> DRM_FORMAT_MOD_INVALID
>> };
>>
>> +static void copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state);
>> static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
>>
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev3)
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev3)
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ffa7a93754dd drm/i915: Refactor intel_can_enable_sagv
-:94: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#94: FILE: drivers/gpu/drm/i915/intel_pm.c:3840:
+ for_each_new_intel_crtc_in_state(state, crtc,
+new_crtc_state, i) {
-:95: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#95: FILE: drivers/gpu/drm/i915/intel_pm.c:3841:
+new_crtc_state, i) {
+
-:111: ERROR:OPEN_BRACE: that open brace { should be on the previous line
#111: FILE: drivers/gpu/drm/i915/intel_pm.c:3857:
+ for (level = ilk_wm_max_level(dev_priv);
+!wm->wm[level].plane_en; --level)
+{ }
-:160: WARNING:LINE_SPACING: Missing a blank line after declarations
#160: FILE: drivers/gpu/drm/i915/intel_pm.c:4032:
+ u32 latency = dev_priv->wm.skl_latency[level];
+ skl_compute_plane_wm(crtc_state, level, latency, , , );
-:170: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#170: FILE: drivers/gpu/drm/i915/intel_pm.c:4386:
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
+ struct skl_ddb_allocation *ddb /* out */)
-:195: CHECK:LINE_SPACING: Please don't use multiple blank lines
#195: FILE: drivers/gpu/drm/i915/intel_pm.c:4411:
+
+
-:228: WARNING:BRACES: braces {} are not necessary for single statement blocks
#228: FILE: drivers/gpu/drm/i915/intel_pm.c::
+ if (blocks > alloc_size) {
+ return -ENOSPC;
+ }
-:291: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#291: FILE: drivers/gpu/drm/i915/intel_pm.c:5038:
+ skl_compute_plane_wm(crtc_state, level, latency,
+wm_params, result_prev,
-:294: ERROR:TRAILING_WHITESPACE: trailing whitespace
#294: FILE: drivers/gpu/drm/i915/intel_pm.c:5041:
+^I^I^Ielse $
-:294: ERROR:ELSE_AFTER_BRACE: else should follow close brace '}'
#294: FILE: drivers/gpu/drm/i915/intel_pm.c:5041:
+ }
+ else
-:296: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#296: FILE: drivers/gpu/drm/i915/intel_pm.c:5043:
+ memcpy(_wm->sagv_wm_l0, [0],
+ sizeof(struct skl_wm_level));
-:375: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#375: FILE: drivers/gpu/drm/i915/intel_pm.c:5780:
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
-:377: WARNING:LINE_SPACING: Missing a blank line after declarations
#377: FILE: drivers/gpu/drm/i915/intel_pm.c:5782:
+ struct intel_plane *plane;
+ for_each_intel_plane_on_crtc(_priv->drm, crtc,
plane) {
-:379: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#379: FILE: drivers/gpu/drm/i915/intel_pm.c:5784:
+ struct skl_plane_wm *plane_wm = \
-:383: WARNING:LINE_SPACING: Missing a blank line after declarations
#383: FILE: drivers/gpu/drm/i915/intel_pm.c:5788:
+ struct skl_wm_level *l0_wm0 = _wm->wm[0];
+ memcpy(l0_wm0, sagv_wm0, sizeof(struct
skl_wm_level));
total: 3 errors, 5 warnings, 7 checks, 339 lines checked
601d1798c1e2 drm/i915: Restrict qgv points which don't have enough bandwidth.
-:125: CHECK:LINE_SPACING: Please don't use multiple blank lines
#125: FILE: drivers/gpu/drm/i915/display/intel_bw.c:138:
+
+
-:330: CHECK:BRACES: braces {} should be used on all arms of this statement
#330: FILE: drivers/gpu/drm/i915/display/intel_display.c:14644:
+ if (INTEL_GEN(dev_priv) < 11) {
[...]
+ else
[...]
-:334: ERROR:ELSE_AFTER_BRACE: else should follow close brace '}'
#334: FILE: drivers/gpu/drm/i915/display/intel_display.c:14648:
+ }
+ else
total: 1 errors, 0 warnings, 2 checks, 298 lines checked
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/todo: Add entry to remove load/unload hooks
They're midlayer, broken, and because of the old gunk, we can't fix them. For examples see the various checks in drm_mode_object.c against dev->registered, which cannot be enforced if the driver still uses the load hook. Unfortunately our biggest driver still uses load/unload, so this would be really great to get fixed. Cc: Alex Deucher Cc: Harry Wentland Signed-off-by: Daniel Vetter --- Documentation/gpu/todo.rst | 17 + 1 file changed, 17 insertions(+) diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst index 73c51b5a0997..5a44f46380c2 100644 --- a/Documentation/gpu/todo.rst +++ b/Documentation/gpu/todo.rst @@ -351,6 +351,23 @@ connector register/unregister fixes Level: Intermediate +Remove load/unload callbacks from all non-DRIVER_LEGACY drivers +--- + +The load/unload callbacks in struct _driver are very much midlayers, plus +for historical reasons they get the ordering wrong (and we can't fix that) +between setting up the _driver structure and calling drm_dev_register(). + +- Rework drivers to no longer use the load/unload callbacks, directly coding the + load/unload sequence into the driver's probe function. + +- Once all non-DRIVER_LEGACY drivers are converted, disallow the load/unload + callbacks for all modern drivers. + +Contact: Daniel Vetter + +Level: Intermediate + Core refactorings = -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor Gen11+ SAGV support (rev3)
== Series Details == Series: Refactor Gen11+ SAGV support (rev3) URL : https://patchwork.freedesktop.org/series/68028/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915: Refactor intel_can_enable_sagv +drivers/gpu/drm/i915/intel_pm.c:3754:6: warning: symbol 'skl_can_enable_sagv' was not declared. Should it be static? +drivers/gpu/drm/i915/intel_pm.c:3820:6: warning: symbol 'icl_can_enable_sagv' was not declared. Should it be static? Commit: drm/i915: Restrict qgv points which don't have enough bandwidth. Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Try to more gracefully quiesce the system before resets
== Series Details ==
Series: drm/i915/gt: Try to more gracefully quiesce the system before resets
URL : https://patchwork.freedesktop.org/series/68445/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7159 -> Patchwork_14943
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/index.html
Known issues
Here are the changes found in Patchwork_14943 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ringfill@basic-default-fd:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-icl-u3/igt@gem_ringf...@basic-default-fd.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/fi-icl-u3/igt@gem_ringf...@basic-default-fd.html
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#109635 ] / [fdo#110387])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-bdw-gvtdvm: [INCOMPLETE][5] ([fdo#112063]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-bdw-gvtdvm/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/fi-bdw-gvtdvm/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_create@basic:
- {fi-tgl-u2}:[INCOMPLETE][7] ([fdo#111736]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-tgl-u2/igt@gem_exec_cre...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/fi-tgl-u2/igt@gem_exec_cre...@basic.html
* igt@gem_exec_fence@basic-wait-default:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +2
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-icl-u3/igt@gem_exec_fe...@basic-wait-default.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/fi-icl-u3/igt@gem_exec_fe...@basic-wait-default.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [DMESG-FAIL][11] ([fdo#112050 ]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-whl-u: [DMESG-FAIL][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-whl-u/igt@i915_selftest@live_gt_heartbeat.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/fi-whl-u/igt@i915_selftest@live_gt_heartbeat.html
- fi-skl-iommu: [DMESG-FAIL][15] ([fdo#112096]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-skl-iommu/igt@i915_selftest@live_gt_heartbeat.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/fi-skl-iommu/igt@i915_selftest@live_gt_heartbeat.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [DMESG-FAIL][17] ([fdo#111678]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: [DMESG-WARN][19] ([fdo#106107]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- {fi-icl-u4}:[FAIL][21] ([fdo#111045]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-icl-u4/igt@kms_chamel...@hdmi-hpd-fast.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/fi-icl-u4/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][23] ([fdo#102614]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14943/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][25] ([fdo#111407]) -> [FAIL][26] ([fdo#111045]
/ [fdo#111096])
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7159/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[26]:
[Intel-gfx] [PATCH 1/2] drm/property: Enforce more lifetime rules
Properties can't be attached after registering, userspace would get
confused (no one bothers to reprobe really).
- Add kerneldoc
- Enforce this with some checks. This needs a somewhat ugly check
since connectors can be added later on, but we still need to attach
all properties before they go public.
Note that we already enforce that properties themselves are created
before the entire device is registered.
Cc: Jani Nikula
Cc: Rajat Jain
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_mode_object.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/drm_mode_object.c
b/drivers/gpu/drm/drm_mode_object.c
index 6a23e36ed4fe..35c2719407a8 100644
--- a/drivers/gpu/drm/drm_mode_object.c
+++ b/drivers/gpu/drm/drm_mode_object.c
@@ -224,12 +224,26 @@ EXPORT_SYMBOL(drm_mode_object_get);
* This attaches the given property to the modeset object with the given
initial
* value. Currently this function cannot fail since the properties are stored
in
* a statically sized array.
+ *
+ * Note that all properties must be attached before the object itself is
+ * registered and accessible from userspace.
*/
void drm_object_attach_property(struct drm_mode_object *obj,
struct drm_property *property,
uint64_t init_val)
{
int count = obj->properties->count;
+ struct drm_device *dev = property->dev;
+
+
+ if (obj->type == DRM_MODE_OBJECT_CONNECTOR) {
+ struct drm_connector *connector = obj_to_connector(obj);
+
+ WARN_ON(!dev->driver->load &&
+ connector->registration_state ==
DRM_CONNECTOR_REGISTERED);
+ } else {
+ WARN_ON(!dev->driver->load && dev->registered);
+ }
if (count == DRM_OBJECT_MAX_PROPERTY) {
WARN(1, "Failed to attach object property (type: 0x%x). Please "
--
2.23.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Try to more gracefully quiesce the system before resets
== Series Details == Series: drm/i915/gt: Try to more gracefully quiesce the system before resets URL : https://patchwork.freedesktop.org/series/68445/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2e59d4f9691e drm/i915/gt: Try to more gracefully quiesce the system before resets -:47: ERROR:IN_ATOMIC: do not use in_atomic in drivers #47: FILE: drivers/gpu/drm/i915/gt/intel_engine_cs.c:880: + if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */ total: 1 errors, 0 warnings, 0 checks, 43 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/bios: add compression parameter block definition
== Series Details ==
Series: drm/i915/bios: add compression parameter block definition
URL : https://patchwork.freedesktop.org/series/68396/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14928_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14928_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@i915_selftest@live_gt_heartbeat}:
- shard-skl: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl4/igt@i915_selftest@live_gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14928/shard-skl6/igt@i915_selftest@live_gt_heartbeat.html
Known issues
Here are the changes found in Patchwork_14928_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@vcs1-none:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080])
+2 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb1/igt@gem_ctx_isolat...@vcs1-none.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14928/shard-iclb6/igt@gem_ctx_isolat...@vcs1-none.html
* igt@gem_ctx_switch@vcs1:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +6 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb1/igt@gem_ctx_swi...@vcs1.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14928/shard-iclb6/igt@gem_ctx_swi...@vcs1.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +12 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_exec_sched...@out-order-bsd2.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14928/shard-iclb3/igt@gem_exec_sched...@out-order-bsd2.html
* igt@gem_exec_schedule@preempt-queue-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +3 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb5/igt@gem_exec_sched...@preempt-queue-bsd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14928/shard-iclb4/igt@gem_exec_sched...@preempt-queue-bsd.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-snb: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14928/shard-snb7/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-hsw: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870]) +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw4/igt@gem_userptr_bl...@sync-unmap-cycles.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14928/shard-hsw6/igt@gem_userptr_bl...@sync-unmap-cycles.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#104108]) +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl8/igt@gem_workarou...@suspend-resume-fd.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14928/shard-skl3/igt@gem_workarou...@suspend-resume-fd.html
* igt@i915_suspend@sysfs-reader:
- shard-kbl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103665] /
[fdo#108767])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl2/igt@i915_susp...@sysfs-reader.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14928/shard-kbl2/igt@i915_susp...@sysfs-reader.html
* igt@kms_color@pipe-a-ctm-red-to-blue:
- shard-skl: [PASS][19] -> [DMESG-WARN][20] ([fdo#106107])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl2/igt@kms_co...@pipe-a-ctm-red-to-blue.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14928/shard-skl5/igt@kms_co...@pipe-a-ctm-red-to-blue.html
* igt@kms_flip@basic-flip-vs-dpms:
- shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([fdo#103313] /
[fdo#105345])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl7/igt@kms_f...@basic-flip-vs-dpms.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14928/shard-kbl2/igt@kms_f...@basic-flip-vs-dpms.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103167]) +9 similar
issues
[23]:
Re: [Intel-gfx] [PATCH 3/5] drm/i915/display: Check if FBC is fused off
On 2019-10-18 at 17:41:22 -0700, José Roberto de Souza wrote:
> Check if FBC is fused off and handle it.
>
> Cc: Ville Syrjälä
> Cc: Martin Peres
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.c | 3 +++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eacc5ba307b0..31375ddc2b3b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7653,6 +7653,7 @@ enum {
>
> #define SKL_DFSM _MMIO(0x51000)
> #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE(1 << 30)
> +#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
May be you want to add two char like
#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
Either way
Reviewed-by: Ramalingam C
-Ram
> #define SKL_DFSM_DISPLAY_HDCP_DISABLE(1 << 25)
> #define SKL_DFSM_CDCLK_LIMIT_MASK(3 << 23)
> #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 753c2cf2fbf4..b6a9f527f8f9 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -990,6 +990,9 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
>
> if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> info->display.has_hdcp = 0;
> +
> + if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
> + info->display.has_fbc = 0;
> }
>
> /* Initialize slice/subslice/EU info */
> --
> 2.23.0
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915/display: Handle fused off display correctly
On 2019-10-18 at 17:41:20 -0700, José Roberto de Souza wrote:
> If all pipes are fused off it means that display is disabled, similar
> like we handle for GEN 7 and 8 right above but for GEN9+ spec says
> that hardware will override the pipe output to a solid color, so
> some display is there and maybe we would need to shutdown display
> to save power, so setting disable_display = true, to keep consistent
> to HAS_DISPLAY() and INTEL_DISPLAY_ENABLED().
>
> In addition to have all pipes fused off, GEN/display 9 have the
> bit 30 "Internal Display Disable", not sure if all pipes will be set
> as unfused when this bit is set so handling both.
>
> Cc: Jani Nikula
> Cc: Lucas De Marchi
> Cc: Ville Syrjälä
> Cc: Martin Peres
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_reg.h | 21 +++--
> drivers/gpu/drm/i915/intel_device_info.c | 14 ++
> 2 files changed, 21 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 855db888516c..6e3ae6e9cbb8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7651,16 +7651,17 @@ enum {
> #define MASK_WAKEMEM (1 << 13)
> #define CNL_DDI_CLOCK_REG_ACCESS_ON(1 << 7)
>
> -#define SKL_DFSM _MMIO(0x51000)
> -#define SKL_DFSM_CDCLK_LIMIT_MASK(3 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> -#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
> -#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> -#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> -#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
> +#define SKL_DFSM _MMIO(0x51000)
> +#define SKL_DFSM_INTERNAL_DISPLAY_DISABLE(1 << 30)
As we are touching all of these anyway, we can add two char space
before the bit definitions as usual.
-Ram
> +#define SKL_DFSM_CDCLK_LIMIT_MASK(3 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> +#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
> +#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> +#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> +#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
>
> #define SKL_DSSM _MMIO(0x51004)
> #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 85e480bdc673..8d6492afdd6a 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -972,15 +972,21 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
> enabled_mask &= ~BIT(PIPE_D);
>
> /*
> - * At least one pipe should be enabled and if there are
> - * disabled pipes, they should be the last ones, with no holes
> - * in the mask.
> + * If there are disabled pipes, they should be the last ones,
> + * with no holes in the mask.
>*/
> - if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
> + if (enabled_mask && !is_power_of_2(enabled_mask + 1))
> DRM_ERROR("invalid pipe fuse configuration:
> enabled_mask=0x%x\n",
> enabled_mask);
> else
> info->pipe_mask = enabled_mask;
> +
> + if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) &&
> + (dfsm & SKL_DFSM_INTERNAL_DISPLAY_DISABLE))
> + i915_modparams.disable_display = true;
> +
> + if (!enabled_mask)
> + i915_modparams.disable_display = true;
> }
>
> /* Initialize slice/subslice/EU info */
> --
> 2.23.0
>
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Re: [Intel-gfx] [PATCH 2/5] drm/i915/display: Handle fused off HDCP
On 2019-10-18 at 17:41:21 -0700, José Roberto de Souza wrote:
> HDCP could be fused off, so not all GEN9+ platforms will support it.
Here HDCP stands for HDCP1.4, so please call it so.
>
> Cc: Ville Syrjälä
> Cc: Martin Peres
> Reviewed-by: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> drivers/gpu/drm/i915/i915_pci.c | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.c | 3 +++
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 5 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index e69fa34528df..f1f41ca8402b 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
> bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
> {
> /* PORT E doesn't have HDCP, and PORT F is disabled */
> - return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
> + return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
> }
>
> static int
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index f9a3bfe68689..f2280709c8c9 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -612,6 +612,7 @@ static const struct intel_device_info
> intel_cherryview_info = {
> .has_logical_ring_preemption = 1, \
> .display.has_csr = 1, \
> .has_gt_uc = 1, \
> + .display.has_hdcp = 1, \
We dont support HDCP1.4 on chv, though hw supports it.
> .display.has_ipc = 1, \
> .ddb_size = 896
>
> @@ -655,6 +656,7 @@ static const struct intel_device_info
> intel_skylake_gt4_info = {
> .display.has_ddi = 1, \
> .has_fpga_dbg = 1, \
> .display.has_fbc = 1, \
> + .display.has_hdcp = 1, \
Need not add for each platform, Instead add it into GEN9_FEATURES and
GEN9_LP_FEATURES.
HDCP1.4 is supported on all Gen 9+ unless it is fused off.
-Ram.
> .display.has_psr = 1, \
> .has_runtime_pm = 1, \
> .display.has_csr = 1, \
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6e3ae6e9cbb8..eacc5ba307b0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7653,6 +7653,7 @@ enum {
>
> #define SKL_DFSM _MMIO(0x51000)
> #define SKL_DFSM_INTERNAL_DISPLAY_DISABLE(1 << 30)
> +#define SKL_DFSM_DISPLAY_HDCP_DISABLE(1 << 25)
> #define SKL_DFSM_CDCLK_LIMIT_MASK(3 << 23)
> #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
> #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 8d6492afdd6a..753c2cf2fbf4 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -987,6 +987,9 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
>
> if (!enabled_mask)
> i915_modparams.disable_display = true;
> +
> + if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
> + info->display.has_hdcp = 0;
> }
>
> /* Initialize slice/subslice/EU info */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index e9940f932d26..118d922261e2 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -138,6 +138,7 @@ enum intel_ppgtt_type {
> func(has_dsb); \
> func(has_fbc); \
> func(has_gmch); \
> + func(has_hdcp); \
> func(has_hotplug); \
> func(has_ipc); \
> func(has_modular_fia); \
> --
> 2.23.0
>
> ___
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[Intel-gfx] [PATCH v3 5/7] drm/i915/selftests: extend coverage to include LMEM huge-pages
Add LMEM objects to list of backends we test for huge-GTT-pages.
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 121 +-
1 file changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index dac8344507c1..687e9ac9b58a 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -9,6 +9,7 @@
#include "i915_selftest.h"
#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_pm.h"
#include "gt/intel_gt.h"
@@ -983,7 +984,7 @@ static int gpu_write(struct intel_context *ce,
vma->size >> PAGE_SHIFT, val);
}
-static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+static int __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32
val)
{
unsigned int needs_flush;
unsigned long n;
@@ -1015,6 +1016,51 @@ static int cpu_check(struct drm_i915_gem_object *obj,
u32 dword, u32 val)
return err;
}
+static int __cpu_check_lmem(struct drm_i915_gem_object *obj, u32 dword, u32
val)
+{
+ unsigned long n;
+ int err;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = i915_gem_object_lmem_io_map_page_atomic(obj, n);
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ if (i915_gem_object_has_struct_page(obj))
+ return __cpu_check_shmem(obj, dword, val);
+ else if (i915_gem_object_is_lmem(obj))
+ return __cpu_check_lmem(obj, dword, val);
+
+ return -ENODEV;
+}
+
static int __igt_write_huge(struct intel_context *ce,
struct drm_i915_gem_object *obj,
u64 size, u64 offset,
@@ -1399,6 +1445,78 @@ static int igt_ppgtt_gemfs_huge(void *arg)
return err;
}
+static int igt_ppgtt_lmem_huge(void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+ struct drm_i915_private *i915 = ctx->i915;
+ struct drm_i915_gem_object *obj;
+ static const unsigned int sizes[] = {
+ SZ_64K,
+ SZ_512K,
+ SZ_1M,
+ SZ_2M,
+ };
+ int i;
+ int err;
+
+ if (!HAS_LMEM(i915)) {
+ pr_info("device lacks LMEM support, skipping\n");
+ return 0;
+ }
+
+ /*
+* Sanity check that the HW uses huge pages correctly through LMEM
+* -- ensure that our writes land in the right place.
+*/
+
+ for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
+ unsigned int size = sizes[i];
+
+ obj = i915_gem_object_create_lmem(i915, size,
I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ if (err == -E2BIG) {
+ pr_info("object too big for region!\n");
+ return 0;
+ }
+
+ return err;
+ }
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto out_put;
+
+ if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
+ pr_info("LMEM unable to allocate huge-page(s) with
size=%u\n",
+ size);
+ goto out_unpin;
+ }
+
+ err = igt_write_huge(ctx, obj);
+ if (err) {
+ pr_err("LMEM write-huge failed with size=%u\n", size);
+ goto out_unpin;
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
+ i915_gem_object_put(obj);
+ }
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_ppgtt_pin_update(void *arg)
{
struct i915_gem_context *ctx = arg;
@@
[Intel-gfx] [PATCH v3 7/7] drm/i915/selftests: add sanity selftest for huge-GTT-pages
Now that for all the relevant backends we do randomised testing, we need
to make sure we still sanity check the obvious cases that might blow up,
such that introducing a temporary regression is less likely. Also
rather than do this for every backend, just limit to our two memory
types: system and local.
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 99 +++
1 file changed, 99 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index b176d719bdef..9a9569fe6003 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1341,6 +1341,12 @@ igt_create_internal(struct drm_i915_private *i915, u32
size, u32 flags)
return i915_gem_object_create_internal(i915, size);
}
+static struct drm_i915_gem_object *
+igt_create_system(struct drm_i915_private *i915, u32 size, u32 flags)
+{
+ return huge_pages_object(i915, size, size);
+}
+
static struct drm_i915_gem_object *
igt_create_local(struct drm_i915_private *i915, u32 size, u32 flags)
{
@@ -1451,6 +1457,98 @@ static int igt_ppgtt_smoke_huge(void *arg)
return err;
}
+static int igt_ppgtt_sanity_check(void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+ struct drm_i915_private *i915 = ctx->i915;
+ unsigned int supported = INTEL_INFO(i915)->page_sizes;
+ struct {
+ igt_create_fn fn;
+ unsigned int flags;
+ } backends[] = {
+ { igt_create_system, 0,},
+ { igt_create_local, I915_BO_ALLOC_CONTIGUOUS, },
+ };
+ struct {
+ u32 size;
+ u32 pages;
+ } combos[] = {
+ { SZ_64K, SZ_64K, },
+ { SZ_2M, SZ_2M, },
+ { SZ_2M, SZ_64K, },
+ { SZ_2M - SZ_64K, SZ_64K, },
+ { SZ_2M - SZ_4K, SZ_64K | SZ_4K, },
+ { SZ_2M + SZ_4K, SZ_64K | SZ_4K, },
+ { SZ_2M + SZ_4K, SZ_2M | SZ_4K, },
+ { SZ_2M + SZ_64K, SZ_2M | SZ_64K, },
+ };
+ int i, j;
+ int err;
+
+ if (supported == I915_GTT_PAGE_SIZE_4K)
+ return 0;
+
+ /*
+* Sanity check that the HW behaves with a limited set of combinations.
+* We already have a bunch of randomised testing, which should give us
+* a decent amount of variation between runs, however we should keep
+* this to limit the chances of introducing a temporary regression, by
+* testing the most obvious cases that might make something blow up.
+*/
+
+ for (i = 0; i < ARRAY_SIZE(backends); ++i) {
+ for (j = 0; j < ARRAY_SIZE(combos); ++j) {
+ struct drm_i915_gem_object *obj;
+ u32 size = combos[j].size;
+ u32 pages = combos[j].pages;
+
+ obj = backends[i].fn(i915, size, backends[i].flags);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ if (err == -ENODEV) {
+ pr_info("Device lacks local memory,
skipping\n");
+ err = 0;
+ break;
+ }
+
+ return err;
+ }
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err) {
+ i915_gem_object_put(obj);
+ goto out;
+ }
+
+ GEM_BUG_ON(pages > obj->base.size);
+ pages = pages & supported;
+
+ if (pages)
+ obj->mm.page_sizes.sg = pages;
+
+ err = igt_write_huge(ctx, obj);
+
+ i915_gem_object_unpin_pages(obj);
+ __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
+ i915_gem_object_put(obj);
+
+ if (err) {
+ pr_err("%s write-huge failed with size=%u
pages=%u i=%d, j=%d\n",
+ __func__, size, pages, i, j);
+ goto out;
+ }
+ }
+
+ cond_resched();
+ }
+
+out:
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_ppgtt_pin_update(void *arg)
{
struct i915_gem_context *ctx = arg;
@@ -1811,6 +1909,7 @@ int i915_gem_huge_page_live_selftests(struct
drm_i915_private *i915)
SUBTEST(igt_tmpfs_fallback),
[Intel-gfx] [PATCH v3 6/7] drm/i915/selftests: prefer random sizes for the huge-GTT-page smoke tests
Ditch the dubious static list of sizes to enumerate, in favour of
choosing a random size within the limits of each backing store. With
repeated CI runs this should give us a wider range of object sizes, and
in turn more page-size combinations, while using less machine time.
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 228 ++
1 file changed, 80 insertions(+), 148 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 687e9ac9b58a..b176d719bdef 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1316,203 +1316,137 @@ static int igt_ppgtt_exhaust_huge(void *arg)
return err;
}
-static int igt_ppgtt_internal_huge(void *arg)
-{
- struct i915_gem_context *ctx = arg;
- struct drm_i915_private *i915 = ctx->i915;
- struct drm_i915_gem_object *obj;
- static const unsigned int sizes[] = {
- SZ_64K,
- SZ_128K,
- SZ_256K,
- SZ_512K,
- SZ_1M,
- SZ_2M,
- };
- int i;
- int err;
-
- /*
-* Sanity check that the HW uses huge pages correctly through internal
-* -- ensure that our writes land in the right place.
-*/
-
- for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
- unsigned int size = sizes[i];
-
- obj = i915_gem_object_create_internal(i915, size);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
-
- err = i915_gem_object_pin_pages(obj);
- if (err)
- goto out_put;
-
- if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
- pr_info("internal unable to allocate huge-page(s) with
size=%u\n",
- size);
- goto out_unpin;
- }
-
- err = igt_write_huge(ctx, obj);
- if (err) {
- pr_err("internal write-huge failed with size=%u\n",
- size);
- goto out_unpin;
- }
-
- i915_gem_object_unpin_pages(obj);
- __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
- i915_gem_object_put(obj);
- }
-
- return 0;
-
-out_unpin:
- i915_gem_object_unpin_pages(obj);
-out_put:
- i915_gem_object_put(obj);
-
- return err;
-}
+typedef struct drm_i915_gem_object *
+(*igt_create_fn)(struct drm_i915_private *i915, u32 size, u32 flags);
static inline bool igt_can_allocate_thp(struct drm_i915_private *i915)
{
return i915->mm.gemfs && has_transparent_hugepage();
}
-static int igt_ppgtt_gemfs_huge(void *arg)
+static struct drm_i915_gem_object *
+igt_create_shmem(struct drm_i915_private *i915, u32 size, u32 flags)
{
- struct i915_gem_context *ctx = arg;
- struct drm_i915_private *i915 = ctx->i915;
- struct drm_i915_gem_object *obj;
- static const unsigned int sizes[] = {
- SZ_2M,
- SZ_4M,
- SZ_8M,
- SZ_16M,
- SZ_32M,
- };
- int i;
- int err;
-
- /*
-* Sanity check that the HW uses huge pages correctly through gemfs --
-* ensure that our writes land in the right place.
-*/
-
if (!igt_can_allocate_thp(i915)) {
- pr_info("missing THP support, skipping\n");
- return 0;
+ pr_info("%s missing THP support, skipping\n", __func__);
+ return ERR_PTR(-ENODEV);
}
- for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
- unsigned int size = sizes[i];
-
- obj = i915_gem_object_create_shmem(i915, size);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
-
- err = i915_gem_object_pin_pages(obj);
- if (err)
- goto out_put;
+ return i915_gem_object_create_shmem(i915, size);
+}
- if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_2M) {
- pr_info("finishing test early, gemfs unable to allocate
huge-page(s) with size=%u\n",
- size);
- goto out_unpin;
- }
+static struct drm_i915_gem_object *
+igt_create_internal(struct drm_i915_private *i915, u32 size, u32 flags)
+{
+ return i915_gem_object_create_internal(i915, size);
+}
- err = igt_write_huge(ctx, obj);
- if (err) {
- pr_err("gemfs write-huge failed with size=%u\n",
- size);
- goto out_unpin;
- }
+static struct drm_i915_gem_object *
+igt_create_local(struct drm_i915_private *i915, u32 size, u32 flags)
+{
+
[Intel-gfx] [PATCH v3 2/7] drm/i915: setup io-mapping for LMEM
From: Abdiel Janulgue
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_region_lmem.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
index 199532056e1b..9a351af45ce6 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -9,8 +9,32 @@
#include "gem/i915_gem_region.h"
#include "intel_region_lmem.h"
+static void
+region_lmem_release(struct intel_memory_region *mem)
+{
+ io_mapping_fini(>iomap);
+ intel_memory_region_release_buddy(mem);
+}
+
+static int
+region_lmem_init(struct intel_memory_region *mem)
+{
+ int ret;
+
+ if (!io_mapping_init_wc(>iomap,
+ mem->io_start,
+ resource_size(>region)))
+ return -EIO;
+
+ ret = intel_memory_region_init_buddy(mem);
+ if (ret)
+ io_mapping_fini(>iomap);
+
+ return ret;
+}
+
const struct intel_memory_region_ops intel_region_lmem_ops = {
- .init = intel_memory_region_init_buddy,
- .release = intel_memory_region_release_buddy,
+ .init = region_lmem_init,
+ .release = region_lmem_release,
.create_object = __i915_gem_lmem_object_create,
};
--
2.20.1
___
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[Intel-gfx] [PATCH V5 3/6] mdev: introduce device specific ops
Currently, except for the create and remove, the rest of
mdev_parent_ops is designed for vfio-mdev driver only and may not help
for kernel mdev driver. With the help of class id, this patch
introduces device specific callbacks inside mdev_device
structure. This allows different set of callback to be used by
vfio-mdev and virtio-mdev.
Signed-off-by: Jason Wang
---
.../driver-api/vfio-mediated-device.rst | 35 +
MAINTAINERS | 1 +
drivers/gpu/drm/i915/gvt/kvmgt.c | 18 ---
drivers/s390/cio/vfio_ccw_ops.c | 18 ---
drivers/s390/crypto/vfio_ap_ops.c | 14 +++--
drivers/vfio/mdev/mdev_core.c | 25 -
drivers/vfio/mdev/mdev_private.h | 5 ++
drivers/vfio/mdev/vfio_mdev.c | 37 ++---
include/linux/mdev.h | 43 ---
include/linux/vfio_mdev_ops.h | 52 +++
samples/vfio-mdev/mbochs.c| 20 ---
samples/vfio-mdev/mdpy.c | 20 ---
samples/vfio-mdev/mtty.c | 18 ---
13 files changed, 206 insertions(+), 100 deletions(-)
create mode 100644 include/linux/vfio_mdev_ops.h
diff --git a/Documentation/driver-api/vfio-mediated-device.rst
b/Documentation/driver-api/vfio-mediated-device.rst
index 6709413bee29..0d8f9e7d7983 100644
--- a/Documentation/driver-api/vfio-mediated-device.rst
+++ b/Documentation/driver-api/vfio-mediated-device.rst
@@ -152,15 +152,6 @@ callbacks per mdev parent device, per mdev type, or any
other categorization.
Vendor drivers are expected to be fully asynchronous in this respect or
provide their own internal resource protection.)
-The callbacks in the mdev_parent_ops structure are as follows:
-
-* open: open callback of mediated device
-* close: close callback of mediated device
-* ioctl: ioctl callback of mediated device
-* read : read emulation callback
-* write: write emulation callback
-* mmap: mmap emulation callback
-
A driver should use the mdev_parent_ops structure in the function call to
register itself with the mdev core driver::
@@ -172,10 +163,34 @@ that a driver should use to unregister itself with the
mdev core driver::
extern void mdev_unregister_device(struct device *dev);
-It is also required to specify the class_id in create() callback through::
+As multiple types of mediated devices may be supported, class id needs
+to be specified in the create callback(). This could be done
+explicitly for the device that does not use on mdev bus for its
+operation through:
int mdev_set_class(struct mdev_device *mdev, u16 id);
+For the device that uses on the mdev bus for its operation, the class
+should provide helper function to set class id and device specific
+ops. E.g for vfio-mdev devices, the function to be called is::
+
+ int mdev_set_vfio_ops(struct mdev_device *mdev,
+ const struct vfio_mdev_ops *vfio_ops);
+
+The class id (set by this function to MDEV_CLASS_ID_VFIO) is used to
+match a device with an mdev driver via its id table. The device
+specific callbacks (specified in *vfio_ops) are obtainable via
+mdev_get_vfio_ops() (for use by the mdev bus driver). A vfio-mdev
+device (class id MDEV_CLASS_ID_VFIO) uses the following
+device-specific ops:
+
+* open: open callback of vfio mediated device
+* close: close callback of vfio mediated device
+* ioctl: ioctl callback of vfio mediated device
+* read : read emulation callback
+* write: write emulation callback
+* mmap: mmap emulation callback
+
Mediated Device Management Interface Through sysfs
==
diff --git a/MAINTAINERS b/MAINTAINERS
index e51a68bf8ca8..9e10ae9c2b4d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17121,6 +17121,7 @@ S: Maintained
F: Documentation/driver-api/vfio-mediated-device.rst
F: drivers/vfio/mdev/
F: include/linux/mdev.h
+F: include/linux/vfio_mdev_ops.h
F: samples/vfio-mdev/
VFIO PLATFORM DRIVER
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 6420f0dbd31b..c2b7f9dbe4d1 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -42,6 +42,7 @@
#include
#include
#include
+#include
#include
#include
@@ -643,6 +644,8 @@ static void kvmgt_put_vfio_device(void *vgpu)
vfio_device_put(((struct intel_vgpu *)vgpu)->vdev.vfio_device);
}
+static const struct vfio_mdev_device_ops intel_vfio_vgpu_dev_ops;
+
static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev)
{
struct intel_vgpu *vgpu = NULL;
@@ -678,7 +681,7 @@ static int intel_vgpu_create(struct kobject *kobj, struct
mdev_device *mdev)
dev_name(mdev_dev(mdev)));
ret = 0;
- mdev_set_class(mdev, MDEV_CLASS_ID_VFIO);
+ mdev_set_vfio_ops(mdev, _vfio_vgpu_dev_ops);
[Intel-gfx] [PATCH v3 4/7] drm/i915/selftests: add write-dword test for LMEM
Simple test writing to dwords across an object, using various engines in
a randomized order, checking that our writes land from the cpu.
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
.../drm/i915/selftests/intel_memory_region.c | 166 ++
1 file changed, 166 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 292489371842..8e14ef3e1e32 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -11,9 +11,11 @@
#include "mock_gem_device.h"
#include "mock_region.h"
+#include "gem/i915_gem_context.h"
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_object_blt.h"
+#include "gem/selftests/igt_gem_utils.h"
#include "gem/selftests/mock_context.h"
#include "gt/intel_gt.h"
#include "selftests/igt_flush_test.h"
@@ -256,6 +258,125 @@ static int igt_mock_contiguous(void *arg)
return err;
}
+static int igt_gpu_write_dw(struct intel_context *ce,
+ struct i915_vma *vma,
+ u32 dword,
+ u32 value)
+{
+ return igt_gpu_fill_dw(ce, vma, dword * sizeof(u32),
+ vma->size >> PAGE_SHIFT, value);
+}
+
+static int igt_cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ unsigned long n;
+ int err;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = i915_gem_object_lmem_io_map_page_atomic(obj, n);
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int igt_gpu_write(struct i915_gem_context *ctx,
+struct drm_i915_gem_object *obj)
+{
+ struct drm_i915_private *i915 = ctx->i915;
+ struct i915_address_space *vm = ctx->vm ?: >ggtt.vm;
+ struct i915_gem_engines *engines;
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+ I915_RND_STATE(prng);
+ IGT_TIMEOUT(end_time);
+ unsigned int count;
+ struct i915_vma *vma;
+ int *order;
+ int i, n;
+ int err = 0;
+
+ GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
+
+ n = 0;
+ count = 0;
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ count++;
+ if (!intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ n++;
+ }
+ i915_gem_context_unlock_engines(ctx);
+ if (!n)
+ return 0;
+
+ order = i915_random_order(count * count, );
+ if (!order)
+ return -ENOMEM;
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_free;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto out_free;
+
+ i = 0;
+ engines = i915_gem_context_lock_engines(ctx);
+ do {
+ u32 rng = prandom_u32_state();
+ u32 dword = offset_in_page(rng) / 4;
+
+ ce = engines->engines[order[i] % engines->num_engines];
+ i = (i + 1) % (count * count);
+ if (!ce || !intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ err = igt_gpu_write_dw(ce, vma, dword, rng);
+ if (err)
+ break;
+
+ err = igt_cpu_check(obj, dword, rng);
+ if (err)
+ break;
+ } while (!__igt_timeout(end_time, NULL));
+ i915_gem_context_unlock_engines(ctx);
+
+out_free:
+ kfree(order);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_lmem_create(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -277,6 +398,50 @@ static int igt_lmem_create(void *arg)
return err;
}
+static int igt_lmem_write_gpu(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *obj;
+ struct i915_gem_context *ctx;
+ struct drm_file *file;
+ I915_RND_STATE(prng);
+ u32 sz;
+ int err;
+
+ file = mock_file(i915);
+
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc
== Series Details == Series: series starting with [1/2] drm/i915/dsc: rename crtc state dsc_params member to dsc URL : https://patchwork.freedesktop.org/series/68394/ State : success == Summary == CI Bug Log - changes from CI_DRM_7155_full -> Patchwork_14926_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14926_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs1-s3: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_ctx_isolat...@vcs1-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb7/igt@gem_ctx_isolat...@vcs1-s3.html * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +15 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb4/igt@gem_exec_sched...@out-order-bsd2.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb7/igt@gem_exec_sched...@out-order-bsd2.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb3/igt@gem_exec_sched...@reorder-wide-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb2/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#112037]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-iclb5/igt@gem_persistent_rel...@forked-interruptible-thrashing.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-iclb8/igt@gem_persistent_rel...@forked-interruptible-thrashing.html * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: - shard-snb: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-snb5/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-hsw1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html * igt@gem_workarounds@suspend-resume: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl6/igt@gem_workarou...@suspend-resume.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-apl6/igt@gem_workarou...@suspend-resume.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][15] -> [INCOMPLETE][16] ([fdo#103665]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-kbl4/igt@gem_workarou...@suspend-resume-fd.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-kbl1/igt@gem_workarou...@suspend-resume-fd.html * igt@kms_color@pipe-b-ctm-0-5: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([fdo#106107]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl3/igt@kms_co...@pipe-b-ctm-0-5.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-skl7/igt@kms_co...@pipe-b-ctm-0-5.html * igt@kms_cursor_legacy@cursor-vs-flip-varying-size: - shard-apl: [PASS][19] -> [INCOMPLETE][20] ([fdo#103927]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-apl2/igt@kms_cursor_leg...@cursor-vs-flip-varying-size.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-apl5/igt@kms_cursor_leg...@cursor-vs-flip-varying-size.html * igt@kms_flip@flip-vs-suspend: - shard-hsw: [PASS][21] -> [INCOMPLETE][22] ([fdo#103540]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-hsw1/igt@kms_f...@flip-vs-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-hsw6/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#100368]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7155/shard-skl10/igt@kms_f...@plain-flip-ts-check-interruptible.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14926/shard-skl4/igt@kms_f...@plain-flip-ts-check-interruptible.html *
[Intel-gfx] [PATCH V5 2/6] modpost: add support for mdev class id
Add support to parse mdev class id table.
Reviewed-by: Parav Pandit
Signed-off-by: Jason Wang
---
drivers/vfio/mdev/vfio_mdev.c | 2 ++
scripts/mod/devicetable-offsets.c | 3 +++
scripts/mod/file2alias.c | 10 ++
3 files changed, 15 insertions(+)
diff --git a/drivers/vfio/mdev/vfio_mdev.c b/drivers/vfio/mdev/vfio_mdev.c
index 7b24ee9cb8dd..cb701cd646f0 100644
--- a/drivers/vfio/mdev/vfio_mdev.c
+++ b/drivers/vfio/mdev/vfio_mdev.c
@@ -125,6 +125,8 @@ static const struct mdev_class_id id_table[] = {
{ 0 },
};
+MODULE_DEVICE_TABLE(mdev, id_table);
+
static struct mdev_driver vfio_mdev_driver = {
.name = "vfio_mdev",
.probe = vfio_mdev_probe,
diff --git a/scripts/mod/devicetable-offsets.c
b/scripts/mod/devicetable-offsets.c
index 054405b90ba4..6cbb1062488a 100644
--- a/scripts/mod/devicetable-offsets.c
+++ b/scripts/mod/devicetable-offsets.c
@@ -231,5 +231,8 @@ int main(void)
DEVID(wmi_device_id);
DEVID_FIELD(wmi_device_id, guid_string);
+ DEVID(mdev_class_id);
+ DEVID_FIELD(mdev_class_id, id);
+
return 0;
}
diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c
index c91eba751804..d365dfe7c718 100644
--- a/scripts/mod/file2alias.c
+++ b/scripts/mod/file2alias.c
@@ -1335,6 +1335,15 @@ static int do_wmi_entry(const char *filename, void
*symval, char *alias)
return 1;
}
+/* looks like: "mdev:cN" */
+static int do_mdev_entry(const char *filename, void *symval, char *alias)
+{
+ DEF_FIELD(symval, mdev_class_id, id);
+
+ sprintf(alias, "mdev:c%02X", id);
+ return 1;
+}
+
/* Does namelen bytes of name exactly match the symbol? */
static bool sym_is(const char *name, unsigned namelen, const char *symbol)
{
@@ -1407,6 +1416,7 @@ static const struct devtable devtable[] = {
{"typec", SIZE_typec_device_id, do_typec_entry},
{"tee", SIZE_tee_client_device_id, do_tee_entry},
{"wmi", SIZE_wmi_device_id, do_wmi_entry},
+ {"mdev", SIZE_mdev_class_id, do_mdev_entry},
};
/* Create MODULE_ALIAS() statements.
--
2.19.1
___
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/dsc: move crtc state dp_dsc_cfg member under dsc as config
On Tue, 22 Oct 2019, Manasi Navare wrote:
> On Tue, Oct 22, 2019 at 04:34:14PM +0300, Jani Nikula wrote:
>> DSC isn't DP specific, so remove the dp_ prefix from the crtc state
>> member name. Also moving the member under the dsc sub-struct gives us
>> enough context to allow shortening the name to just config. No
>> functional changes.
>>
>> Cc: Manasi Navare
>> Signed-off-by: Jani Nikula
>
> Sounds good to me and I guess works better with expanding this code
> to other connectors
>
> Reviewed-by: Manasi Navare
Thanks for the review, pushed both.
BR,
Jani.
>
> Manasi
>
>> ---
>> drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
>> drivers/gpu/drm/i915/display/intel_vdsc.c | 6 +++---
>> 2 files changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index db66f9d623f8..bac40482a2aa 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -986,8 +986,8 @@ struct intel_crtc_state {
>> bool dsc_split;
>> u16 compressed_bpp;
>> u8 slice_count;
>> +struct drm_dsc_config config;
>> } dsc;
>> -struct drm_dsc_config dp_dsc_cfg;
>>
>> /* Forward Error correction State */
>> bool fec_enable;
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index f41a9336476b..896b0c334f5e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -322,7 +322,7 @@ static int get_column_index_for_rc_params(u8
>> bits_per_component)
>> int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>> struct intel_crtc_state *pipe_config)
>> {
>> -struct drm_dsc_config *vdsc_cfg = _config->dp_dsc_cfg;
>> +struct drm_dsc_config *vdsc_cfg = _config->dsc.config;
>> u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
>> u8 i = 0;
>> int row_index = 0;
>> @@ -485,7 +485,7 @@ static void intel_configure_pps_for_dsc_encoder(struct
>> intel_encoder *encoder,
>> {
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> -const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
>> +const struct drm_dsc_config *vdsc_cfg = _state->dsc.config;
>> enum pipe pipe = crtc->pipe;
>> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> u32 pps_val = 0;
>> @@ -885,7 +885,7 @@ static void intel_dp_write_dsc_pps_sdp(struct
>> intel_encoder *encoder,
>> {
>> struct intel_dp *intel_dp = enc_to_intel_dp(>base);
>> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>> -const struct drm_dsc_config *vdsc_cfg = _state->dp_dsc_cfg;
>> +const struct drm_dsc_config *vdsc_cfg = _state->dsc.config;
>> struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
>>
>> /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
>> --
>> 2.20.1
>>
--
Jani Nikula, Intel Open Source Graphics Center
___
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Intel-gfx@lists.freedesktop.org
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915: Allow i915 to manage the vma offset nodes instead of drm core
== Series Details == Series: series starting with [1/5] drm/i915: Allow i915 to manage the vma offset nodes instead of drm core URL : https://patchwork.freedesktop.org/series/68444/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7158 -> Patchwork_14942 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14942 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14942, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14942/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14942: ### IGT changes ### Possible regressions * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: - fi-gdg-551: [PASS][1] -> [FAIL][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7158/fi-gdg-551/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14942/fi-gdg-551/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-a.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-ilk-650: [PASS][3] -> [FAIL][4] +6 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7158/fi-ilk-650/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-a-frame-sequence.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14942/fi-ilk-650/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-a-frame-sequence.html - fi-elk-e7500: [PASS][5] -> [FAIL][6] +6 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7158/fi-elk-e7500/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-a-frame-sequence.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14942/fi-elk-e7500/igt@kms_pipe_crc_ba...@nonblocking-crc-pipe-a-frame-sequence.html * igt@kms_pipe_crc_basic@read-crc-pipe-a: - fi-bwr-2160:[PASS][7] -> [FAIL][8] +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7158/fi-bwr-2160/igt@kms_pipe_crc_ba...@read-crc-pipe-a.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14942/fi-bwr-2160/igt@kms_pipe_crc_ba...@read-crc-pipe-a.html * igt@kms_pipe_crc_basic@read-crc-pipe-b: - fi-blb-e6850: [PASS][9] -> [FAIL][10] +6 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7158/fi-blb-e6850/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14942/fi-blb-e6850/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-bsw-kefka: [PASS][11] -> [FAIL][12] +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7158/fi-bsw-kefka/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14942/fi-bsw-kefka/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html * igt@runner@aborted: - fi-bdw-gvtdvm: NOTRUN -> [FAIL][13] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14942/fi-bdw-gvtdvm/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_14942 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_create@basic-files: - fi-bdw-gvtdvm: [PASS][14] -> [TIMEOUT][15] ([fdo#111220]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7158/fi-bdw-gvtdvm/igt@gem_ctx_cre...@basic-files.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14942/fi-bdw-gvtdvm/igt@gem_ctx_cre...@basic-files.html * igt@gem_ctx_switch@legacy-render: - fi-bxt-dsi: [PASS][16] -> [INCOMPLETE][17] ([fdo#103927] / [fdo#111381]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7158/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14942/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html * igt@gem_ringfill@basic-default-interruptible: - fi-icl-u3: [PASS][18] -> [DMESG-WARN][19] ([fdo#107724]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7158/fi-icl-u3/igt@gem_ringf...@basic-default-interruptible.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14942/fi-icl-u3/igt@gem_ringf...@basic-default-interruptible.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: [PASS][20] -> [FAIL][21] ([fdo#109483]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7158/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14942/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][22] -> [DMESG-WARN][23]
[Intel-gfx] [CI 2/5] drm/i915/execlists: Force preemption
If the preempted context takes too long to relinquish control, e.g. it
is stuck inside a shader with arbitration disabled, evict that context
with an engine reset. This ensures that preemptions are reasonably
responsive, providing a tighter QoS for the more important context at
the cost of flagging unresponsive contexts more frequently (i.e. instead
of using an ~10s hangcheck, we now evict at ~100ms). The challenge of
lies in picking a timeout that can be reasonably serviced by HW for
typical workloads, balancing the existing clients against the needs for
responsiveness.
Note that coupled with timeslicing, this will lead to rapid GPU "hang"
detection with multiple active contexts vying for GPU time.
The forced preemption mechanism can be compiled out with
./scripts/config --set-val DRM_I915_PREEMPT_TIMEOUT 0
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/Kconfig.profile | 12 +++
drivers/gpu/drm/i915/gt/intel_engine.h | 9 ++
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 5 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 6 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 93 +++--
drivers/gpu/drm/i915/gt/selftest_lrc.c | 100 +++
drivers/gpu/drm/i915/i915_gem.h | 14 ---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/i915_utils.c| 29 ++
drivers/gpu/drm/i915/i915_utils.h| 9 ++
10 files changed, 255 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index 3a3881d5e44b..b071b6024152 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -12,6 +12,18 @@ config DRM_I915_USERFAULT_AUTOSUSPEND
May be 0 to disable the extra delay and solely use the device level
runtime pm autosuspend delay tunable.
+config DRM_I915_PREEMPT_TIMEOUT
+ int "Preempt timeout (ms, jiffy granularity)"
+ default 100 # milliseconds
+ help
+ How long to wait (in milliseconds) for a preemption event to occur
+ when submitting a new context via execlists. If the current context
+ does not hit an arbitration point and yield to HW before the timer
+ expires, the HW will be reset to allow the more important context
+ to execute.
+
+ May be 0 to disable the timeout.
+
config DRM_I915_SPIN_REQUEST
int "Busywait for request completion (us)"
default 5 # microseconds
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index c2d9d67c63d9..9409b7856299 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -527,4 +527,13 @@ void intel_engine_init_active(struct intel_engine_cs
*engine,
#define ENGINE_MOCK1
#define ENGINE_VIRTUAL 2
+static inline bool
+intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
+{
+ if (!CONFIG_DRM_I915_PREEMPT_TIMEOUT)
+ return 0;
+
+ return intel_engine_has_preemption(engine);
+}
+
#endif /* _INTEL_RINGBUFFER_H_ */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index e4203eb44139..b91ea07f4819 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -308,6 +308,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
engine->instance = info->instance;
__sprint_engine_name(engine);
+ engine->props.preempt_timeout_ms =
+ CONFIG_DRM_I915_PREEMPT_TIMEOUT;
engine->props.stop_timeout_ms =
CONFIG_DRM_I915_STOP_TIMEOUT;
@@ -1338,10 +1340,11 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
unsigned int idx;
u8 read, write;
- drm_printf(m, "\tExeclist tasklet queued? %s (%s), timeslice?
%s\n",
+ drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s,
timeslice? %s\n",
yesno(test_bit(TASKLET_STATE_SCHED,
>execlists.tasklet.state)),
enableddisabled(!atomic_read(>execlists.tasklet.count)),
+ repr_timer(>execlists.preempt),
repr_timer(>execlists.timer));
read = execlists->csb_head;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 87d5c4ef3ae7..1251dac91f31 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -174,6 +174,11 @@ struct intel_engine_execlists {
*/
struct timer_list timer;
+ /**
+* @preempt: reset the current context if it fails to give way
+*/
+
