Re: [Intel-gfx] [PATCH v2] kernel-doc: rename the kernel-doc directive 'functions' to 'identifiers'
Am 29.10.19 um 01:31 schrieb Changbin Du:
But is it, really? I agree with Jon about the distinction between None
and '' being confusing.
Here python is different from C. Both empty string and None are False in python.
Note such condition is common in python.
The one is a empty string str(''), its bool('') value is False.
| >>> type(''), bool('')
| (, False)
The other is a NoneType, its bool(None) value is False.
| >>> type(None), bool(None)
| (, False)
None often used like NULL (pointer). E.g if a function does not give an explicit
return value, the returned value is None.
| >>> def foo():
| ... pass
| ...
| >>> print(foo())
| None
-- Markus --
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/tgl: add support to one DP-MST stream (rev2)
== Series Details ==
Series: drm/i915/tgl: add support to one DP-MST stream (rev2)
URL : https://patchwork.freedesktop.org/series/68671/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15041
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_15041 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15041, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15041/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_15041:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_blt:
- fi-icl-u3: [PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@i915_selftest@live_blt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15041/fi-icl-u3/igt@i915_selftest@live_blt.html
- fi-kbl-8809g: [PASS][3] -> [TIMEOUT][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-8809g/igt@i915_selftest@live_blt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15041/fi-kbl-8809g/igt@i915_selftest@live_blt.html
- fi-glk-dsi: [PASS][5] -> [TIMEOUT][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-glk-dsi/igt@i915_selftest@live_blt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15041/fi-glk-dsi/igt@i915_selftest@live_blt.html
- fi-skl-6600u: [PASS][7] -> [TIMEOUT][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-skl-6600u/igt@i915_selftest@live_blt.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15041/fi-skl-6600u/igt@i915_selftest@live_blt.html
* igt@runner@aborted:
- fi-kbl-8809g: NOTRUN -> [FAIL][9]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15041/fi-kbl-8809g/igt@run...@aborted.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_blt:
- {fi-icl-dsi}: NOTRUN -> [TIMEOUT][10]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15041/fi-icl-dsi/igt@i915_selftest@live_blt.html
Known issues
Here are the changes found in Patchwork_15041 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [PASS][11] -> [DMESG-WARN][12] ([fdo#107724])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15041/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-icl-dsi}: [INCOMPLETE][13] ([fdo#107713] / [fdo#109100]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15041/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][15] ([fdo#103927] / [fdo#111381]) ->
[PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15041/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [DMESG-WARN][17] ([fdo#107724]) -> [PASS][18] +2
similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15041/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
* igt@i915_selftest@live_blt:
- fi-kbl-guc: [TIMEOUT][19] -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-guc/igt@i915_selftest@live_blt.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15041/fi-kbl-guc/igt@i915_selftest@live_blt.html
- fi-apl-guc: [TIMEOUT][21] -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-apl-guc/igt@i915_selftest@live_blt.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15041/fi-apl-guc/igt@i915_selftest@live_blt.html
- fi-kbl-r: [TIMEOUT][23] -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-r/igt@i915_selftest@live_blt.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15041/fi-kbl-r/igt@i915_selftest@live_blt.html
- fi-icl-u2: [TIMEOUT][25]
[Intel-gfx] [PATCH v2] drm/i915/tgl: add support to one DP-MST stream
This is the minimum change to support 1 (and only 1) DP-MST monitor
connected on Tiger Lake. This change was isolated from previous patch
from José. In order to support more streams we will need to create a
master-slave relation on the transcoders and that is not currently
working yet.
v2: remove unused macro and use REG_FIELD_PREP() (Ville)
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 281594bcbfae..fed7fc56dd92 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1905,6 +1905,9 @@ intel_ddi_transcoder_func_reg_val_get(const struct
intel_crtc_state *crtc_state)
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
temp |= TRANS_DDI_MODE_SELECT_DP_MST;
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ temp |=
TRANS_DDI_MST_TRANSPORT_SELECT(crtc_state->cpu_transcoder);
} else {
temp |= TRANS_DDI_MODE_SELECT_DP_SST;
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb33b164ce55..97ec3d0bbd11 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9586,6 +9586,9 @@ enum skl_power_gate {
#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
+#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(12, 10)
+#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
+ REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
--
2.23.0
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dp: Do not switch aux to TBT mode for non-TC ports
== Series Details ==
Series: drm/i915/dp: Do not switch aux to TBT mode for non-TC ports
URL : https://patchwork.freedesktop.org/series/68691/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15040
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_15040 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15040, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15040/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_15040:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_blt:
- fi-skl-6600u: [PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-skl-6600u/igt@i915_selftest@live_blt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15040/fi-skl-6600u/igt@i915_selftest@live_blt.html
- fi-skl-6770hq: [PASS][3] -> [TIMEOUT][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-skl-6770hq/igt@i915_selftest@live_blt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15040/fi-skl-6770hq/igt@i915_selftest@live_blt.html
- fi-skl-guc: [PASS][5] -> [TIMEOUT][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-skl-guc/igt@i915_selftest@live_blt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15040/fi-skl-guc/igt@i915_selftest@live_blt.html
Known issues
Here are the changes found in Patchwork_15040 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_create@basic:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@gem_exec_cre...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15040/fi-icl-u3/igt@gem_exec_cre...@basic.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-icl-dsi}: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15040/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][11] ([fdo#103927] / [fdo#111381]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15040/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@i915_selftest@live_blt:
- fi-kbl-guc: [TIMEOUT][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-guc/igt@i915_selftest@live_blt.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15040/fi-kbl-guc/igt@i915_selftest@live_blt.html
- fi-apl-guc: [TIMEOUT][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-apl-guc/igt@i915_selftest@live_blt.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15040/fi-apl-guc/igt@i915_selftest@live_blt.html
- fi-kbl-r: [TIMEOUT][17] -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-r/igt@i915_selftest@live_blt.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15040/fi-kbl-r/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_client:
- fi-cfl-8700k: [INCOMPLETE][19] -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cfl-8700k/igt@i915_selftest@live_client.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15040/fi-cfl-8700k/igt@i915_selftest@live_client.html
* igt@prime_vgem@basic-fence-mmap:
- fi-icl-u3: [DMESG-WARN][21] ([fdo#107724]) -> [PASS][22] +1
similar issue
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@prime_v...@basic-fence-mmap.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15040/fi-icl-u3/igt@prime_v...@basic-fence-mmap.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
Participating hosts (50 -> 41)
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915/selftests: Drop global engine lookup for gt selftests
== Series Details == Series: series starting with [1/5] drm/i915/selftests: Drop global engine lookup for gt selftests URL : https://patchwork.freedesktop.org/series/68623/ State : success == Summary == CI Bug Log - changes from CI_DRM_7196_full -> Patchwork_15016_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15016_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs1-clean: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@gem_ctx_isolat...@vcs1-clean.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb3/igt@gem_ctx_isolat...@vcs1-clean.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb4/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb6/igt@gem_exec_balan...@smoke.html * igt@gem_exec_big@single: - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb3/igt@gem_exec_...@single.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb7/igt@gem_exec_...@single.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112080]) +14 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb2/igt@gem_exec_paral...@vcs1-fds.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb3/igt@gem_exec_paral...@vcs1-fds.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +7 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb7/igt@gem_exec_sched...@preempt-other-chain-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb1/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_persistent_relocs@forked-faulting-reloc-thrashing: - shard-iclb: [PASS][11] -> [TIMEOUT][12] ([fdo#112068 ]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb7/igt@gem_persistent_rel...@forked-faulting-reloc-thrashing.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb8/igt@gem_persistent_rel...@forked-faulting-reloc-thrashing.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-snb: [PASS][13] -> [FAIL][14] ([fdo#112037]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-snb5/igt@gem_persistent_rel...@forked-interruptible-thrashing.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-snb2/igt@gem_persistent_rel...@forked-interruptible-thrashing.html - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#112037]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-iclb1/igt@gem_persistent_rel...@forked-interruptible-thrashing.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-iclb4/igt@gem_persistent_rel...@forked-interruptible-thrashing.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: - shard-hsw: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-hsw1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html * igt@gem_userptr_blits@sync-unmap-after-close: - shard-snb: [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-snb7/igt@gem_userptr_bl...@sync-unmap-after-close.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-snb4/igt@gem_userptr_bl...@sync-unmap-after-close.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-kbl6/igt@gem_workarou...@suspend-resume-fd.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-kbl2/igt@gem_workarou...@suspend-resume-fd.html * igt@i915_pm_rpm@system-suspend-modeset: - shard-kbl: [PASS][23] -> [INCOMPLETE][24] ([fdo#103665] / [fdo#107807]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7196/shard-kbl7/igt@i915_pm_...@system-suspend-modeset.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15016/shard-kbl1/igt@i915_pm_...@system-suspend-modeset.html *
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/blt: fixup block_size rounding (rev3)
== Series Details ==
Series: drm/i915/blt: fixup block_size rounding (rev3)
URL : https://patchwork.freedesktop.org/series/68670/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15039
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15039/index.html
Known issues
Here are the changes found in Patchwork_15039 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@bad-flink:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15039/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
* igt@i915_selftest@live_blt:
- fi-hsw-peppy: [PASS][3] -> [DMESG-FAIL][4] ([fdo#112147])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-hsw-peppy/igt@i915_selftest@live_blt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15039/fi-hsw-peppy/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-bsw-kefka: [PASS][5] -> [INCOMPLETE][6] ([fdo# 111542])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15039/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#103167])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15039/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-icl-dsi}: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15039/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_suspend@basic-s3:
- {fi-cml-s}: [DMESG-WARN][11] ([fdo#111764]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cml-s/igt@gem_exec_susp...@basic-s3.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15039/fi-cml-s/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +2
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15039/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
* igt@i915_selftest@live_blt:
- fi-kbl-guc: [TIMEOUT][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-guc/igt@i915_selftest@live_blt.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15039/fi-kbl-guc/igt@i915_selftest@live_blt.html
- fi-apl-guc: [TIMEOUT][17] -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-apl-guc/igt@i915_selftest@live_blt.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15039/fi-apl-guc/igt@i915_selftest@live_blt.html
- fi-kbl-r: [TIMEOUT][19] -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-r/igt@i915_selftest@live_blt.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15039/fi-kbl-r/igt@i915_selftest@live_blt.html
- fi-icl-u2: [TIMEOUT][21] -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u2/igt@i915_selftest@live_blt.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15039/fi-icl-u2/igt@i915_selftest@live_blt.html
- {fi-icl-u4}:[TIMEOUT][23] -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u4/igt@i915_selftest@live_blt.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15039/fi-icl-u4/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_client:
- fi-cfl-8700k: [INCOMPLETE][25] -> [PASS][26]
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cfl-8700k/igt@i915_selftest@live_client.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15039/fi-cfl-8700k/igt@i915_selftest@live_client.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Adding YUV444 packed format support for skl+ (rev2)
== Series Details ==
Series: drm/i915: Adding YUV444 packed format support for skl+ (rev2)
URL : https://patchwork.freedesktop.org/series/66770/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15038
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_15038 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15038, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_15038:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_blt:
- fi-glk-dsi: [PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-glk-dsi/igt@i915_selftest@live_blt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-glk-dsi/igt@i915_selftest@live_blt.html
- fi-cml-u2: [PASS][3] -> [TIMEOUT][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cml-u2/igt@i915_selftest@live_blt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-cml-u2/igt@i915_selftest@live_blt.html
- fi-skl-lmem:[PASS][5] -> [TIMEOUT][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-skl-lmem/igt@i915_selftest@live_blt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-skl-lmem/igt@i915_selftest@live_blt.html
- fi-cfl-guc: [PASS][7] -> [TIMEOUT][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cfl-guc/igt@i915_selftest@live_blt.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-cfl-guc/igt@i915_selftest@live_blt.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_blt:
- {fi-icl-dsi}: NOTRUN -> [TIMEOUT][9]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-icl-dsi/igt@i915_selftest@live_blt.html
Known issues
Here are the changes found in Patchwork_15038 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_gem_contexts:
- fi-bsw-n3050: [PASS][10] -> [INCOMPLETE][11] ([fdo# 111542])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
* igt@prime_vgem@basic-fence-flip:
- fi-icl-u3: [PASS][12] -> [DMESG-WARN][13] ([fdo#107724]) +1
similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-icl-dsi}: [INCOMPLETE][14] ([fdo#107713] / [fdo#109100]) ->
[PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][16] ([fdo#103927] / [fdo#111381]) ->
[PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [DMESG-WARN][18] ([fdo#107724]) -> [PASS][19] +2
similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
* igt@i915_selftest@live_blt:
- fi-kbl-guc: [TIMEOUT][20] -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-guc/igt@i915_selftest@live_blt.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-kbl-guc/igt@i915_selftest@live_blt.html
- fi-apl-guc: [TIMEOUT][22] -> [PASS][23]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-apl-guc/igt@i915_selftest@live_blt.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15038/fi-apl-guc/igt@i915_selftest@live_blt.html
- fi-kbl-r: [TIMEOUT][24] -> [PASS][25]
[24]:
[Intel-gfx] [PATCH] drm/i915/dp: Do not switch aux to TBT mode for non-TC ports
Non-TC ports always have tc_mode == TC_PORT_TBT_ALT so it was
switching aux to TC mode for all combo-phy ports, happily this did
not caused any issue but is better follow BSpec.
Also this is reserved bit before ICL.
Fixes: 6f211ed43438 ("drm/i915/icl: Set TBT IO in Aux transaction")
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 86989ec25bc6..379623397301 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1291,6 +1291,9 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
u32 unused)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *i915 =
+ to_i915(intel_dig_port->base.base.dev);
+ enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
u32 ret;
ret = DP_AUX_CH_CTL_SEND_BUSY |
@@ -1303,7 +1306,8 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
- if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
+ if (intel_phy_is_tc(i915, phy) &&
+ intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
ret |= DP_AUX_CH_CTL_TBT_IO;
return ret;
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Adding YUV444 packed format support for skl+ (rev2)
== Series Details == Series: drm/i915: Adding YUV444 packed format support for skl+ (rev2) URL : https://patchwork.freedesktop.org/series/66770/ State : warning == Summary == $ dim checkpatch origin/drm-tip d19968439852 drm/i915: Adding YUV444 packed format support for skl+ (V13) -:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #9: PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification. total: 0 errors, 1 warnings, 0 checks, 66 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc: Skip suspend/resume GuC action on platforms w/o GuC submission
== Series Details ==
Series: drm/i915/guc: Skip suspend/resume GuC action on platforms w/o GuC
submission
URL : https://patchwork.freedesktop.org/series/68685/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15037
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_15037 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15037, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15037/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_15037:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_blt:
- fi-kbl-8809g: [PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-8809g/igt@i915_selftest@live_blt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15037/fi-kbl-8809g/igt@i915_selftest@live_blt.html
- fi-bxt-dsi: NOTRUN -> [TIMEOUT][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15037/fi-bxt-dsi/igt@i915_selftest@live_blt.html
- fi-skl-lmem:[PASS][4] -> [TIMEOUT][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-skl-lmem/igt@i915_selftest@live_blt.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15037/fi-skl-lmem/igt@i915_selftest@live_blt.html
- fi-cfl-8700k: [PASS][6] -> [TIMEOUT][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cfl-8700k/igt@i915_selftest@live_blt.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15037/fi-cfl-8700k/igt@i915_selftest@live_blt.html
- fi-skl-guc: [PASS][8] -> [TIMEOUT][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-skl-guc/igt@i915_selftest@live_blt.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15037/fi-skl-guc/igt@i915_selftest@live_blt.html
- fi-cfl-guc: [PASS][10] -> [TIMEOUT][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cfl-guc/igt@i915_selftest@live_blt.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15037/fi-cfl-guc/igt@i915_selftest@live_blt.html
- fi-skl-iommu: [PASS][12] -> [TIMEOUT][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-skl-iommu/igt@i915_selftest@live_blt.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15037/fi-skl-iommu/igt@i915_selftest@live_blt.html
* igt@runner@aborted:
- fi-bxt-dsi: NOTRUN -> [FAIL][14]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15037/fi-bxt-dsi/igt@run...@aborted.html
- fi-cfl-8700k: NOTRUN -> [FAIL][15]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15037/fi-cfl-8700k/igt@run...@aborted.html
- fi-kbl-8809g: NOTRUN -> [FAIL][16]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15037/fi-kbl-8809g/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_15037 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@flink-lifetime:
- fi-icl-u3: [PASS][17] -> [DMESG-WARN][18] ([fdo#107724]) +1
similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15037/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-icl-dsi}: [INCOMPLETE][19] ([fdo#107713] / [fdo#109100]) ->
[PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15037/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][21] ([fdo#103927] / [fdo#111381]) ->
[PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15037/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [DMESG-WARN][23] ([fdo#107724]) -> [PASS][24] +2
similar issues
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15037/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
* igt@i915_selftest@live_blt:
- fi-kbl-r: [TIMEOUT][25] -> [PASS][26]
[25]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for Clear Color Support for TGL Render Decompression (rev9)
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev9)
URL : https://patchwork.freedesktop.org/series/66814/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15035
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_15035 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15035, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_15035:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_blt:
- fi-cml-u2: [PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cml-u2/igt@i915_selftest@live_blt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-cml-u2/igt@i915_selftest@live_blt.html
- fi-cfl-guc: [PASS][3] -> [TIMEOUT][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cfl-guc/igt@i915_selftest@live_blt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-cfl-guc/igt@i915_selftest@live_blt.html
Known issues
Here are the changes found in Patchwork_15035 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [PASS][5] -> [FAIL][6] ([fdo#103167])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
- fi-hsw-peppy: [PASS][7] -> [DMESG-WARN][8] ([fdo#102614])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-icl-dsi}: [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_suspend@basic-s3:
- {fi-cml-s}: [DMESG-WARN][11] ([fdo#111764]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cml-s/igt@gem_exec_susp...@basic-s3.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-cml-s/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +2
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
* igt@i915_selftest@live_blt:
- fi-kbl-guc: [TIMEOUT][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-guc/igt@i915_selftest@live_blt.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-kbl-guc/igt@i915_selftest@live_blt.html
- fi-kbl-r: [TIMEOUT][17] -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-r/igt@i915_selftest@live_blt.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-kbl-r/igt@i915_selftest@live_blt.html
- fi-icl-u2: [TIMEOUT][19] -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u2/igt@i915_selftest@live_blt.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-icl-u2/igt@i915_selftest@live_blt.html
- {fi-icl-u4}:[TIMEOUT][21] -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u4/igt@i915_selftest@live_blt.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-icl-u4/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_client:
- fi-cfl-8700k: [INCOMPLETE][23] -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cfl-8700k/igt@i915_selftest@live_client.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15035/fi-cfl-8700k/igt@i915_selftest@live_client.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[Intel-gfx] ✗ Fi.CI.BUILD: failure for lib/color_encoding: Fix up support for XYUV format.
== Series Details == Series: lib/color_encoding: Fix up support for XYUV format. URL : https://patchwork.freedesktop.org/series/68684/ State : failure == Summary == Applying: lib/color_encoding: Fix up support for XYUV format. error: sha1 information is lacking or useless (lib/igt_color_encoding.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 lib/color_encoding: Fix up support for XYUV format. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/vbt: Handle generic DTD block (rev2)
== Series Details ==
Series: drm/i915/vbt: Handle generic DTD block (rev2)
URL : https://patchwork.freedesktop.org/series/67811/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7206 -> Patchwork_15033
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_15033 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15033, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15033/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_15033:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_blt:
- fi-skl-6770hq: [PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-skl-6770hq/igt@i915_selftest@live_blt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15033/fi-skl-6770hq/igt@i915_selftest@live_blt.html
- fi-cfl-8109u: [PASS][3] -> [TIMEOUT][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-cfl-8109u/igt@i915_selftest@live_blt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15033/fi-cfl-8109u/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_client:
- fi-skl-iommu: [PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-skl-iommu/igt@i915_selftest@live_client.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15033/fi-skl-iommu/igt@i915_selftest@live_client.html
* igt@runner@aborted:
- fi-cfl-8109u: NOTRUN -> [FAIL][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15033/fi-cfl-8109u/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_15033 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-short:
- fi-icl-u3: [PASS][8] -> [DMESG-WARN][9] ([fdo#107724]) +1
similar issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@gem_mmap_...@basic-short.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15033/fi-icl-u3/igt@gem_mmap_...@basic-short.html
* igt@i915_selftest@live_gem_contexts:
- fi-bsw-n3050: [PASS][10] -> [INCOMPLETE][11] ([fdo# 111542])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15033/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
* igt@kms_busy@basic-flip-a:
- fi-icl-u2: [PASS][12] -> [INCOMPLETE][13] ([fdo#107713])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u2/igt@kms_b...@basic-flip-a.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15033/fi-icl-u2/igt@kms_b...@basic-flip-a.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-icl-dsi}: [INCOMPLETE][14] ([fdo#107713] / [fdo#109100]) ->
[PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15033/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][16] ([fdo#103927] / [fdo#111381]) ->
[PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15033/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [DMESG-WARN][18] ([fdo#107724]) -> [PASS][19] +2
similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15033/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html
* igt@i915_selftest@live_blt:
- fi-kbl-guc: [TIMEOUT][20] -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-guc/igt@i915_selftest@live_blt.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15033/fi-kbl-guc/igt@i915_selftest@live_blt.html
- fi-apl-guc: [TIMEOUT][22] -> [PASS][23]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-apl-guc/igt@i915_selftest@live_blt.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15033/fi-apl-guc/igt@i915_selftest@live_blt.html
- fi-kbl-r: [TIMEOUT][24] -> [PASS][25]
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7206/fi-kbl-r/igt@i915_selftest@live_blt.html
[25]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev9)
== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev9)
URL : https://patchwork.freedesktop.org/series/66814/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
10f566048768 drm/framebuffer: Format modifier for Intel Gen-12 render
compression
7d2dee12e37d drm/i915: Use intel_tile_height() instead of re-implementing
12645a88b91a drm/i915: Move CCS stride alignment W/A inside
intel_fb_stride_alignment
32c32c8b500b drm/i915/tgl: Gen-12 render decompression
ba040ad811f0 drm/i915: Extract framebufer CCS offset checks into a function
39c6f2f2c9f9 drm/framebuffer: Format modifier for Intel Gen-12 media compression
124bad1a7799 drm/fb: Extend format_info member arrays to handle four planes
c36e200e5975 Gen-12 display can decompress surfaces compressed by the media
engine.
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#13:
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
-:113: WARNING:LONG_LINE: line over 100 characters
#113: FILE: drivers/gpu/drm/i915/display/intel_display.c:2726:
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct
drm_framebuffer *fb, int color_plane)
-:120: WARNING:LONG_LINE: line over 100 characters
#120: FILE: drivers/gpu/drm/i915/display/intel_display.c:2733:
+ } mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2,
16}, .vsub = {1, 32, 2, 32} };
total: 0 errors, 3 warnings, 0 checks, 509 lines checked
2858e81f6a9e drm/framebuffer/tgl: Format modifier for Intel Gen 12 render
compression with Clear Color
e9980fa6b761 drm/i915/tgl: Add Clear Color support for TGL Render Decompression
-:253: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible
side-effects?
#253: FILE: drivers/gpu/drm/i915/i915_reg.h:6801:
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
total: 0 errors, 0 warnings, 1 checks, 198 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gem: Limit the blitter sizes to ensure low preemption latency (rev2)
== Series Details == Series: drm/i915/gem: Limit the blitter sizes to ensure low preemption latency (rev2) URL : https://patchwork.freedesktop.org/series/68584/ State : failure == Summary == Applying: drm/i915/gem: Limit the blitter sizes to ensure low preemption latency Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gem/i915_gem_object_blt.c Falling back to patching base and 3-way merge... No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Avoid HPD poll detect triggering a new detect cycle (rev2)
Hi Chris, Lakshmi, On Mon, Oct 28, 2019 at 10:01:13PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915: Avoid HPD poll detect triggering a new detect cycle (rev2) > URL : https://patchwork.freedesktop.org/series/68644/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_7205 -> Patchwork_15031 > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_15031 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_15031, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/index.html > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_15031: > > ### IGT changes ### > > Possible regressions > > * igt@i915_selftest@live_blt: > - fi-kbl-guc: [PASS][1] -> [TIMEOUT][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-kbl-guc/igt@i915_selftest@live_blt.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-kbl-guc/igt@i915_selftest@live_blt.html This and the 2 other ones below seem unrelated. The patch changes the display detection path only, but there is no detection going on when the bug happens. For the above one the trace is: <4>[ 754.304899] RIP: 0010:intel_emit_vma_fill_blt+0x139/0x340 [i915] <4>[ 754.304901] Code: c1 e1 10 80 cd 04 80 bb e2 0b 00 00 07 77 a9 89 48 0c 4c 89 10 48 8d 48 18 c7 40 08 00 00 00 00 44 89 40 10 44 89 68 14 eb b1 41 04 00 00 00 05 48 8b 45 18 48 8b b8 50 01 00 00 e8 70 2d fb <4>[ 754.304902] RSP: 0018:c96c7e48 EFLAGS: 00010246 <4>[ 754.304904] RAX: c9576000 RBX: 8881d58a RCX: c9575ffc <4>[ 754.304905] RDX: 0080 RSI: RDI: 0001d000 <4>[ 754.304906] RBP: 88815a2d7480 R08: ff81d000 R09: 03f010005435 <4>[ 754.304907] R10: 03f010005434 R11: R12: 88821cbddc00 <4>[ 754.304907] R13: 11b89215 R14: 888182ef1540 R15: 11b89215 <4>[ 754.304909] FS: () GS:88822ea8() knlGS: <4>[ 754.304910] CS: 0010 DS: ES: CR0: 80050033 <4>[ 754.304911] CR2: c9576000 CR3: 000228de2004 CR4: 003606e0 <4>[ 754.304911] DR0: DR1: DR2: <4>[ 754.304912] DR3: DR6: fffe0ff0 DR7: 0400 <3>[ 754.304914] BUG: sleeping function called from invalid context at ./include/linux/percpu-rwsem.h:38 <3>[ 754.304915] in_atomic(): 0, irqs_disabled(): 1, non_block: 0, pid: 6111, name: igt/blt-8 <4>[ 754.304916] INFO: lockdep is turned off. <4>[ 754.304917] irq event stamp: 104082 <4>[ 754.304920] hardirqs last enabled at (104081): [] __slab_alloc.isra.84.constprop.89+0x4d/0x70 <4>[ 754.304922] hardirqs last disabled at (104082): [] trace_hardirqs_off_thunk+0x1a/0x20 <4>[ 754.304924] softirqs last enabled at (104078): [] __do_softirq+0x385/0x47f <4>[ 754.304926] softirqs last disabled at (104071): [] irq_exit+0xba/0xc0 <4>[ 754.304927] CPU: 5 PID: 6111 Comm: igt/blt-8 Tainted: G UD 5.4.0-rc4-CI-Patchwork_15031+ #1 <4>[ 754.304928] Hardware name: System manufacturer System Product Name/Z170M-PLUS, BIOS 3610 03/29/2018 <4>[ 754.304929] Call Trace: <4>[ 754.304932] dump_stack+0x67/0x9b <4>[ 754.304934] ___might_sleep+0x178/0x260 <4>[ 754.304936] exit_signals+0x2b/0x350 <4>[ 754.304938] do_exit+0xa3/0xd70 <4>[ 754.304972] ? i915_gem_object_fill_blt+0x380/0x380 [i915] <4>[ 754.304974] ? kthread+0x119/0x130 <4>[ 754.304976] rewind_stack_do_exit+0x17/0x20 Could we open a new ticket for these? > - fi-icl-u2: [PASS][3] -> [TIMEOUT][4] >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-icl-u2/igt@i915_selftest@live_blt.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-icl-u2/igt@i915_selftest@live_blt.html > > * igt@i915_selftest@live_client: > - fi-whl-u: [PASS][5] -> [INCOMPLETE][6] >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-whl-u/igt@i915_selftest@live_client.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-whl-u/igt@i915_selftest@live_client.html > > * igt@runner@aborted: > - fi-kbl-guc: NOTRUN -> [FAIL][7] >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-kbl-guc/igt@run...@aborted.html > > > Known issues > > > Here are the changes found in Patchwork_15031 that come from known issues: > > ### IGT changes ### > > Issues hit > > *
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Program LUT before intel_color_commit() if LUT was not previously set (rev2)
== Series Details == Series: drm/i915: Program LUT before intel_color_commit() if LUT was not previously set (rev2) URL : https://patchwork.freedesktop.org/series/68278/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7205 -> Patchwork_15032 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15032 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15032, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15032/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15032: ### IGT changes ### Possible regressions * igt@i915_selftest@live_blt: - fi-kbl-soraka: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-kbl-soraka/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15032/fi-kbl-soraka/igt@i915_selftest@live_blt.html - fi-kbl-8809g: [PASS][3] -> [TIMEOUT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-kbl-8809g/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15032/fi-kbl-8809g/igt@i915_selftest@live_blt.html - fi-apl-guc: [PASS][5] -> [TIMEOUT][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-apl-guc/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15032/fi-apl-guc/igt@i915_selftest@live_blt.html - fi-skl-6770hq: [PASS][7] -> [TIMEOUT][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-skl-6770hq/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15032/fi-skl-6770hq/igt@i915_selftest@live_blt.html - fi-cfl-8109u: [PASS][9] -> [TIMEOUT][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-cfl-8109u/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15032/fi-cfl-8109u/igt@i915_selftest@live_blt.html - fi-skl-guc: [PASS][11] -> [TIMEOUT][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-skl-guc/igt@i915_selftest@live_blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15032/fi-skl-guc/igt@i915_selftest@live_blt.html - fi-cfl-guc: [PASS][13] -> [TIMEOUT][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-cfl-guc/igt@i915_selftest@live_blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15032/fi-cfl-guc/igt@i915_selftest@live_blt.html * igt@runner@aborted: - fi-cfl-8109u: NOTRUN -> [FAIL][15] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15032/fi-cfl-8109u/igt@run...@aborted.html - fi-kbl-soraka: NOTRUN -> [FAIL][16] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15032/fi-kbl-soraka/igt@run...@aborted.html - fi-kbl-8809g: NOTRUN -> [FAIL][17] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15032/fi-kbl-8809g/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_15032 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_switch@legacy-render: - fi-icl-u2: [PASS][18] -> [INCOMPLETE][19] ([fdo#107713] / [fdo#111381]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15032/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][20] -> [DMESG-WARN][21] ([fdo#102614]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15032/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html * igt@vgem_basic@setversion: - fi-icl-u3: [PASS][22] -> [DMESG-WARN][23] ([fdo#107724]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-icl-u3/igt@vgem_ba...@setversion.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15032/fi-icl-u3/igt@vgem_ba...@setversion.html Possible fixes * igt@gem_ctx_switch@legacy-render: - fi-bxt-dsi: [INCOMPLETE][24] ([fdo#103927] / [fdo#111381]) -> [PASS][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15032/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html * igt@gem_exec_reloc@basic-gtt-read: - fi-icl-u3: [DMESG-WARN][26]
[Intel-gfx] [CI] drm/i915/blt: fixup block_size rounding
From: Matthew Auld There is nothing to say that the obj->base.size is actually a multiple of the block_size. v2: Use round_up() as block_size is a power-of-two Reported-by: Chris Wilson Signed-off-by: Matthew Auld Cc: Chris Wilson Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c index 51acffd31575..1c04ccaa1805 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c @@ -30,7 +30,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, GEM_BUG_ON(intel_engine_is_virtual(ce->engine)); intel_engine_pm_get(ce->engine); - count = div_u64(vma->size, block_size); + count = round_up(vma->size, block_size) / block_size; size = (1 + 8 * count) * sizeof(u32); size = round_up(size, PAGE_SIZE); pool = intel_engine_get_pool(ce->engine, size); @@ -214,7 +214,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, GEM_BUG_ON(intel_engine_is_virtual(ce->engine)); intel_engine_pm_get(ce->engine); - count = div_u64(dst->size, block_size); + count = round_up(dst->size, block_size) / block_size; size = (1 + 11 * count) * sizeof(u32); size = round_up(size, PAGE_SIZE); pool = intel_engine_get_pool(ce->engine, size); -- 2.24.0.rc1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Avoid HPD poll detect triggering a new detect cycle (rev2)
== Series Details ==
Series: drm/i915: Avoid HPD poll detect triggering a new detect cycle (rev2)
URL : https://patchwork.freedesktop.org/series/68644/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7205 -> Patchwork_15031
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_15031 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15031, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_15031:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_blt:
- fi-kbl-guc: [PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-kbl-guc/igt@i915_selftest@live_blt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-kbl-guc/igt@i915_selftest@live_blt.html
- fi-icl-u2: [PASS][3] -> [TIMEOUT][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-icl-u2/igt@i915_selftest@live_blt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-icl-u2/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_client:
- fi-whl-u: [PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-whl-u/igt@i915_selftest@live_client.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-whl-u/igt@i915_selftest@live_client.html
* igt@runner@aborted:
- fi-kbl-guc: NOTRUN -> [FAIL][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-kbl-guc/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_15031 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_reloc@basic-write-read-noreloc:
- fi-icl-u3: [PASS][8] -> [DMESG-WARN][9] ([fdo#107724]) +1
similar issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-icl-u3/igt@gem_exec_re...@basic-write-read-noreloc.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-icl-u3/igt@gem_exec_re...@basic-write-read-noreloc.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2: [PASS][10] -> [FAIL][11] ([fdo#109570])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
Possible fixes
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][12] ([fdo#103927] / [fdo#111381]) ->
[PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_reloc@basic-gtt-read:
- fi-icl-u3: [DMESG-WARN][14] ([fdo#107724]) -> [PASS][15] +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read.html
* igt@i915_selftest@live_blt:
- fi-glk-dsi: [TIMEOUT][16] -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-glk-dsi/igt@i915_selftest@live_blt.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-glk-dsi/igt@i915_selftest@live_blt.html
- fi-cfl-8700k: [TIMEOUT][18] -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-cfl-8700k/igt@i915_selftest@live_blt.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-cfl-8700k/igt@i915_selftest@live_blt.html
- fi-skl-iommu: [TIMEOUT][20] -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-skl-iommu/igt@i915_selftest@live_blt.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-skl-iommu/igt@i915_selftest@live_blt.html
- {fi-tgl-u}: [TIMEOUT][22] -> [PASS][23]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-tgl-u/igt@i915_selftest@live_blt.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-tgl-u/igt@i915_selftest@live_blt.html
Warnings
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [DMESG-WARN][24] ([fdo#102505] / [fdo#106107] /
[fdo#110390]) -> [DMESG-WARN][25] ([fdo#102505] / [fdo#110390])
[24]:
[Intel-gfx] [PATCH] drm/i915/blt: fixup block_size rounding
From: Matthew Auld There is nothing to say that the obj->base.size is actually a multiple of the block_size. v2: Use round_up() as block_size is a power-of-two Reported-by: Chris Wilson Signed-off-by: Matthew Auld Cc: Chris Wilson Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c index 51acffd31575..07341cea46fd 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c @@ -30,7 +30,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, GEM_BUG_ON(intel_engine_is_virtual(ce->engine)); intel_engine_pm_get(ce->engine); - count = div_u64(vma->size, block_size); + count = round_up(vma->size, block_size) / block_size; size = (1 + 8 * count) * sizeof(u32); size = round_up(size, PAGE_SIZE); pool = intel_engine_get_pool(ce->engine, size); @@ -214,7 +214,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, GEM_BUG_ON(intel_engine_is_virtual(ce->engine)); intel_engine_pm_get(ce->engine); - count = div_u64(dst->size, block_size); + count = round_up(vma->size, block_size) / block_size; size = (1 + 11 * count) * sizeof(u32); size = round_up(size, PAGE_SIZE); pool = intel_engine_get_pool(ce->engine, size); -- 2.24.0.rc1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Adding YUV444 packed format support for skl+ (V13)
From: Stanislav Lisovskiy
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use XYUV instead of AYUV, as we don't use alpha.
v6: Removed unneeded initializer for new XYUV format.
v7: Added scaling support for DRM_FORMAT_XYUV
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Added missing XYUV format to sprite planes for skl+.
v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV.
v12: Fixed rebase conflicts
V13: Rebased.
Added format to ICL format lists.
v12:
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
This has been updated to support GEN11 along with rebasing it to
the latest drm-tip. A patch to igt has also been posted that gives
igt the ability to test this format.
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9dce2e9e5376..2018e2714c78 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2996,6 +2996,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool
alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XYUV:
+ return DRM_FORMAT_XYUV;
case PLANE_CTL_FORMAT_P010:
return DRM_FORMAT_P010;
case PLANE_CTL_FORMAT_P012:
@@ -4070,6 +4072,8 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
return PLANE_CTL_FORMAT_XRGB_16161616F;
+ case DRM_FORMAT_XYUV:
+ return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -5669,6 +5673,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index edc41fc40726..a0e6e7717a65 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2412,6 +2412,7 @@ static const u32 skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV,
};
static const u32 skl_planar_formats[] = {
@@ -2430,6 +2431,7 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_NV12,
+ DRM_FORMAT_XYUV,
};
static const u32 glk_planar_formats[] = {
@@ -2497,6 +2499,7 @@ static const u32 icl_sdr_uv_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV,
};
static const u32 icl_hdr_plane_formats[] = {
@@ -2526,6 +2529,7 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV,
};
static const u64 skl_plane_format_modifiers_noccs[] = {
@@ -2676,6 +2680,7 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb33b164ce55..88cfb22df3dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6687,7 +6687,7 @@ enum {
#define PLANE_CTL_FORMAT_P012(5 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
#define PLANE_CTL_FORMAT_P016(7 << 24)
-#define PLANE_CTL_FORMAT_AYUV(8 << 24)
+#define PLANE_CTL_FORMAT_XYUV(8 << 24)
#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK
[Intel-gfx] [PATCH] drm/i915/guc: Skip suspend/resume GuC action on platforms w/o GuC submission
From: Don Hiatt
On some platforms (e.g. KBL) that do not support GuC submission, but
the user enabled the GuC communication (e.g for HuC authentication)
calling the GuC EXIT_S_STATE action results in lose of ability to
enter RC6. We can remove the GuC suspend/remove entirely as we do
not need to save the GuC submission status.
v2: Do not suspend/resume the GuC on platforms that do not support
Guc Submission.
Signed-off-by: Don Hiatt
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 3fdbc935d155..04031564f0b1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -572,10 +572,19 @@ void intel_uc_runtime_suspend(struct intel_uc *uc)
if (!intel_guc_is_running(guc))
return;
+ /*
+* If GuC communciation is enabled but submission is not supported,
+* we do not need to suspend the GuC but we do need to disable the
+* GuC communication on suspend.
+*/
+ if (!guc->submission_supported)
+ goto guc_disable_comm;
+
err = intel_guc_suspend(guc);
if (err)
DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
+guc_disable_comm:
guc_disable_communication(guc);
}
@@ -605,6 +614,14 @@ static int __uc_resume(struct intel_uc *uc, bool
enable_communication)
if (enable_communication)
guc_enable_communication(guc);
+ /*
+* If GuC communciation is enabled but submission is not supported,
+* we do not need to resume the GuC but we do need to enable the
+* GuC communication on resume (above).
+*/
+ if (!guc->submission_supported)
+ return 0;
+
err = intel_guc_resume(guc);
if (err) {
DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
--
2.20.1
___
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Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC submission but enabled
> > From: Ceraolo Spurio, Daniele
> > Sent: Monday, October 28, 2019 11:30 AM
> > To: Hiatt, Don ; intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o
> GuC
> > submission but enabled
> >
> >
> >
> > On 10/28/19 11:17 AM, Hiatt, Don wrote:
> > >> From: Ceraolo Spurio, Daniele
> > >> Sent: Monday, October 28, 2019 9:44 AM
> > >> To: Hiatt, Don ; intel-gfx@lists.freedesktop.org
> > >> Subject: Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms
> > >> w/o
> > GuC
> > >> submission but enabled
> > >>
> > >>
> > >>
> > >> On 10/24/19 9:29 AM, don.hi...@intel.com wrote:
> > >>> From: Don Hiatt
> > >>>
> > >>> Check to see if GuC submission is enabled before requesting the
> > >>> EXIT_S_STATE action.
> > >>>
> > >>
> > >> You're only skipping the resume, but does it make any sense to do the
> > >> suspend action if we're not going to call the resume one? Does guc do
> > >> anything in the suspend action that we still require? I thought it only
> > >> saved the submission status, which we don't care about if guc submission
> > >> is disabled.
> > >>
> > >> Daniele
> > >>
> > >
> > > Hi Daniele,
> > >
> > > I tried skipping the suspend all together but then the HuC gets timeouts
> > > waiting for the GuC to acknowledge the authentication request which leads
> to
> > a
> > > wedged GPU. ☹
> > >
> >
> > Do we know why? if we skip the suspend/resume H2G and reload the blobs
> > after resetting the HW it should look like a clean boot from the HW
> > perspective, so the fact that HuC auth times out feels weird and might
> > hide other issues. I asked one of the guc devs and he also thinks this
> > is not expected behavior. Can you dig a bit more?
> >
> > Thanks,
> > Daniele
> >
>
> No idea why but I'll do some digging and see what I find.
>
> Thanks!
>
> don
>
Hi Daniele,
I was a little overzealous on my removal of suspend/resume. We still need to go
through the steps of enable/disable GuC communication on suspend/resume but
just not send the GuC action. My first attempt was not handling the GuC
communication
properly so that is why I was seeing the HuC authentication timesouts.
I'm submitting new patch -- with the proper 'drm/i915' -- and will CC you.
Thanks!
don
> > > BTW, I made a typo in the patch, should be 'drm/i915' not '914', I'll fix
> > > that
> > > up.
> > >
> > > Thanks,
> > >
> > > don
> > >
> > >
> > >>> On some platforms (e.g. KBL) that do not support GuC submission, but
> > >>> the user enabled the GuC communication (e.g for HuC authentication)
> > >>> calling the GuC EXIT_S_STATE action results in lose of ability to
> > >>> enter RC6. Guard against this by only requesting the GuC action on
> > >>> platforms that support GuC submission.
> > >>>
> > >>> I've verfied that intel_guc_resume() only gets called when driver
> > >>> is loaded with: guc_enable={1,2,3}, all other cases (no args,
> > >>> guc_enable={0,-1} the intel_guc_resume() is not called.
> > >>>
> > >>> Signed-off-by: Don Hiatt
> > >>> ---
> > >>>drivers/gpu/drm/i915/gt/uc/intel_guc.c | 5 -
> > >>>1 file changed, 4 insertions(+), 1 deletion(-)
> > >>>
> > >>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > >> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > >>> index 37f7bcbf7dac..33318ed135c0 100644
> > >>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > >>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > >>> @@ -565,7 +565,10 @@ int intel_guc_resume(struct intel_guc *guc)
> > >>> GUC_POWER_D0,
> > >>> };
> > >>>
> > >>> - return intel_guc_send(guc, action, ARRAY_SIZE(action));
> > >>> + if (guc->submission_supported)
> > >>> + return intel_guc_send(guc, action, ARRAY_SIZE(action));
> > >>> +
> > >>> + return 0;
> > >>>}
> > >>>
> > >>>/**
> > >>>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] [PATCH] lib/color_encoding: Fix up support for XYUV format.
Add XYUV to the list of DRM Formats to test.
Also fix the byte order for the format.
Signed-off-by: Bob Paauwe
---
lib/igt_color_encoding.c | 1 +
lib/igt_fb.c | 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/lib/igt_color_encoding.c b/lib/igt_color_encoding.c
index 7de6d5ab..a7bd2b22 100644
--- a/lib/igt_color_encoding.c
+++ b/lib/igt_color_encoding.c
@@ -160,6 +160,7 @@ static const struct color_encoding_format {
{ DRM_FORMAT_XVYU2101010, 1023.f, 64.f, 940.f, 64.f, 512.f, 960.f },
{ DRM_FORMAT_XVYU12_16161616, 65520.f, 4096.f, 60160.f, 4096.f,
32768.f, 61440.f },
{ DRM_FORMAT_XVYU16161616, 65535.f, 4096.f, 60160.f, 4096.f, 32768.f,
61440.f },
+ { DRM_FORMAT_XYUV, 255.f, 16.f, 235.f, 16.f, 128.f, 240.f },
};
static const struct color_encoding_format *lookup_fourcc(uint32_t fourcc)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 4adca967..fe5fa74b 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -2423,9 +2423,9 @@ static void get_yuv_parameters(struct igt_fb *fb, struct
yuv_parameters *params)
break;
case DRM_FORMAT_XYUV:
- params->y_offset = fb->offsets[0] + 1;
- params->u_offset = fb->offsets[0] + 2;
- params->v_offset = fb->offsets[0] + 3;
+ params->y_offset = fb->offsets[0] + 2;
+ params->u_offset = fb->offsets[0] + 1;
+ params->v_offset = fb->offsets[0] + 0;
break;
}
}
--
2.21.0
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Tidy up rps irq handler to use intel_gt
== Series Details ==
Series: drm/i915/gt: Tidy up rps irq handler to use intel_gt
URL : https://patchwork.freedesktop.org/series/68616/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7195_full -> Patchwork_15014_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_15014_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_suspend@basic-s0}:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15014/shard-tglb4/igt@gem_exec_susp...@basic-s0.html
Known issues
Here are the changes found in Patchwork_15014_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@bcs0-s3:
- shard-kbl: [PASS][2] -> [DMESG-WARN][3] ([fdo#108566]) +1
similar issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-kbl2/igt@gem_ctx_isolat...@bcs0-s3.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15014/shard-kbl2/igt@gem_ctx_isolat...@bcs0-s3.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-skl: [PASS][4] -> [INCOMPLETE][5] ([fdo#104108])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-skl5/igt@gem_ctx_isolat...@rcs0-s3.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15014/shard-skl10/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_ctx_isolation@vcs1-clean:
- shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#109276] / [fdo#112080])
+1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-iclb1/igt@gem_ctx_isolat...@vcs1-clean.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15014/shard-iclb5/igt@gem_ctx_isolat...@vcs1-clean.html
* igt@gem_ctx_switch@vcs1-heavy-queue:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#112080]) +9 similar
issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-iclb1/igt@gem_ctx_swi...@vcs1-heavy-queue.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15014/shard-iclb8/igt@gem_ctx_swi...@vcs1-heavy-queue.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#110854])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-iclb4/igt@gem_exec_balan...@smoke.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15014/shard-iclb7/igt@gem_exec_balan...@smoke.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#112146]) +3 similar
issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-iclb8/igt@gem_exec_sched...@preempt-other-chain-bsd.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15014/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-iclb: [PASS][14] -> [FAIL][15] ([fdo#112037])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-iclb8/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15014/shard-iclb2/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-hsw: [PASS][16] -> [DMESG-WARN][17] ([fdo#111870])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-hsw8/igt@gem_userptr_bl...@sync-unmap-cycles.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15014/shard-hsw8/igt@gem_userptr_bl...@sync-unmap-cycles.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][18] -> [FAIL][19] ([fdo#105363])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-skl8/igt@kms_f...@flip-vs-expired-vblank.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15014/shard-skl1/igt@kms_f...@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-hsw: [PASS][20] -> [FAIL][21] ([fdo#105363])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-hsw8/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15014/shard-hsw8/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend:
- shard-iclb: [PASS][22] -> [INCOMPLETE][23] ([fdo#107713] /
[fdo#109507])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-iclb6/igt@kms_f...@flip-vs-suspend.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15014/shard-iclb3/igt@kms_f...@flip-vs-suspend.html
*
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: add support to one DP-MST stream
== Series Details ==
Series: drm/i915/tgl: add support to one DP-MST stream
URL : https://patchwork.freedesktop.org/series/68671/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7204 -> Patchwork_15030
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15030/index.html
Known issues
Here are the changes found in Patchwork_15030 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fence@basic-wait-default:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u3/igt@gem_exec_fe...@basic-wait-default.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15030/fi-icl-u3/igt@gem_exec_fe...@basic-wait-default.html
Possible fixes
* igt@gem_ctx_exec@basic:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u3/igt@gem_ctx_e...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15030/fi-icl-u3/igt@gem_ctx_e...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
Participating hosts (50 -> 43)
--
Additional (1): fi-kbl-soraka
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-tgl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7204 -> Patchwork_15030
CI-20190529: 20190529
CI_DRM_7204: 2ec2c26b76ebf320dfecf692a928ed85797dc6b9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5248: 81e55f1f97d73e48f00caa7e4fb98295023c5afa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15030: cce4d3a6591939df0ff05e9e19a6b0af5f07ab88 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cce4d3a65919 drm/i915/tgl: add support to one DP-MST stream
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15030/index.html
___
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Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Use vfunc to check engine submission mode (rev2)
Quoting Patchwork (2019-10-28 20:33:10) > == Series Details == > > Series: drm/i915/execlists: Use vfunc to check engine submission mode (rev2) > URL : https://patchwork.freedesktop.org/series/68654/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_7204 -> Patchwork_15029 > > > Summary > --- > > **SUCCESS** > > No regressions found. And pushed, thanks for the patch and review. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 00/10] Clear Color Support for TGL Render Decompression
Support for Clear Color is contained in the last two patches submitted by Radhakrishna Sripada. The first 8 patches are currently undergoing review/revision changes. The first 8 patches are cherry-picked from the series https://patchwork.freedesktop.org/series/67078/ Expecting feedback for the 9th patches. The series is tested with kms_cube and custom Mesa branch by Nanley. Resending due to a wrong patch sent to the ML. Dhinakaran Pandiyan (8): drm/framebuffer: Format modifier for Intel Gen-12 render compression drm/i915: Use intel_tile_height() instead of re-implementing drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment drm/i915/tgl: Gen-12 render decompression drm/i915: Extract framebufer CCS offset checks into a function drm/framebuffer: Format modifier for Intel Gen-12 media compression drm/fb: Extend format_info member arrays to handle four planes Gen-12 display can decompress surfaces compressed by the media engine. Radhakrishna Sripada (2): drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color drm/i915/tgl: Add Clear Color support for TGL Render Decompression drivers/gpu/drm/i915/display/intel_display.c | 434 ++ .../drm/i915/display/intel_display_types.h| 5 +- drivers/gpu/drm/i915/display/intel_sprite.c | 70 ++- drivers/gpu/drm/i915/i915_reg.h | 14 + include/drm/drm_fourcc.h | 8 +- include/uapi/drm/drm_fourcc.h | 43 ++ 6 files changed, 460 insertions(+), 114 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 07/10] drm/fb: Extend format_info member arrays to handle four planes
From: Dhinakaran Pandiyan
addfb() uAPI has supported four planes for a while now, make format_info
compatible with that.
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Dhinakaran Pandiyan
---
include/drm/drm_fourcc.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 306d1efeb5e0..156b122c0ad5 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -78,7 +78,7 @@ struct drm_format_info {
* triplet @char_per_block, @block_w, @block_h for better
* describing the pixel format.
*/
- u8 cpp[3];
+ u8 cpp[4];
/**
* @char_per_block:
@@ -104,7 +104,7 @@ struct drm_format_info {
* information from their drm_mode_config.get_format_info hook
* if they want the core to be validating the pitch.
*/
- u8 char_per_block[3];
+ u8 char_per_block[4];
};
/**
@@ -113,7 +113,7 @@ struct drm_format_info {
* Block width in pixels, this is intended to be accessed through
* drm_format_info_block_width()
*/
- u8 block_w[3];
+ u8 block_w[4];
/**
* @block_h:
@@ -121,7 +121,7 @@ struct drm_format_info {
* Block height in pixels, this is intended to be accessed through
* drm_format_info_block_height()
*/
- u8 block_h[3];
+ u8 block_h[4];
/** @hsub: Horizontal chroma subsampling factor */
u8 hsub;
--
2.20.1
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[Intel-gfx] [PATCH v6 03/10] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment
From: Dhinakaran Pandiyan
Easier to read if all the alignment changes are in one place and contained
within a function.
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/display/intel_display.c | 31 ++--
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 3796547ba018..b8ef99eac254 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2573,7 +2573,22 @@ intel_fb_stride_alignment(const struct drm_framebuffer
*fb, int color_plane)
else
return 64;
} else {
- return intel_tile_width_bytes(fb, color_plane);
+ u32 tile_width = intel_tile_width_bytes(fb, color_plane);
+
+ /*
+* Display WA #0531: skl,bxt,kbl,glk
+*
+* Render decompression and plane width > 3840
+* combined with horizontal panning requires the
+* plane stride to be a multiple of 4. We'll just
+* require the entire fb to accommodate that to avoid
+* potential runtime errors at plane configuration time.
+*/
+ if (IS_GEN(dev_priv, 9) && is_ccs_modifier(fb->modifier) &&
+ color_plane == 0 && fb->width > 3840)
+ tile_width *= 4;
+
+ return tile_width;
}
}
@@ -16306,20 +16321,6 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
}
stride_alignment = intel_fb_stride_alignment(fb, i);
-
- /*
-* Display WA #0531: skl,bxt,kbl,glk
-*
-* Render decompression and plane width > 3840
-* combined with horizontal panning requires the
-* plane stride to be a multiple of 4. We'll just
-* require the entire fb to accommodate that to avoid
-* potential runtime errors at plane configuration time.
-*/
- if (IS_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 &&
- is_ccs_modifier(fb->modifier))
- stride_alignment *= 4;
-
if (fb->pitches[i] & (stride_alignment - 1)) {
DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u
byte aligned\n",
i, fb->pitches[i], stride_alignment);
--
2.20.1
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[Intel-gfx] [PATCH v6 01/10] drm/framebuffer: Format modifier for Intel Gen-12 render compression
From: Dhinakaran Pandiyan
Gen-12 has a new compression format, add a new modifier to indicate that.
Cc: Ville Syrjälä
Cc: Matt Roper
Cc: Nanley G Chery
Cc: Jason Ekstrand
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
include/uapi/drm/drm_fourcc.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 8caaaf7ff91b..5ba481f49931 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,17 @@ extern "C" {
#define I915_FORMAT_MOD_Y_TILED_CCSfourcc_mod_code(INTEL, 4)
#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
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[Intel-gfx] [PATCH v6 10/10] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.
v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
plane config(Matt). Fix Lookup error.
v3: Fix the panic while running kms_cube
v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt)
v5: Fix typos and wrap comments(Matt)
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjala
Cc: Shashank Sharma
Cc: Rafael Antognolli
Cc: Nanley G Chery
Reviewed-by: Matt Roper
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/display/intel_display.c | 52 +++
.../drm/i915/display/intel_display_types.h| 3 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
drivers/gpu/drm/i915/i915_reg.h | 12 +
4 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 20ad089da6ee..6d6eab8d4776 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1944,6 +1944,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
if (color_plane == 1)
return 64;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ if (color_plane == 1 || color_plane == 2)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -2085,6 +2089,7 @@ static unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
return 256 * 1024;
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2287,6 +2292,8 @@ static bool is_surface_linear(u64 modifier, int
color_plane)
return true;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return color_plane == 1;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return color_plane == 1 || color_plane == 2;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return color_plane == 1 || color_plane == 3;
default:
@@ -2480,6 +2487,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
fb_modifier)
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2533,6 +2541,21 @@ static const struct drm_format_info gen12_ccs_formats[]
= {
.cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
};
+/*
+ * Same as gen12_ccs_formats[] above, but with additional surface used
+ * to pass Clear Color information in plane 2 with 64 bits of data.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+ { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2560,6 +2583,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return lookup_format_info(gen12_ccs_cc_formats,
+ ARRAY_SIZE(gen12_ccs_cc_formats),
+ cmd->pixel_format);
default:
return NULL;
}
@@ -2569,6 +2596,7 @@ bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
modifier ==
[Intel-gfx] [PATCH v6 09/10] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
Gen12 display can decompress surfaces compressed by render engine with
Clear Color, add a new modifier as the driver needs to know the surface
was compressed by render engine.
V2: Description changes as suggested by Rafael.
V3: Mention the Clear Color size of 64 bits in the comments(DK)
v4: Fix trailing whitespaces
v5: Explain Clear Color in the documentation.
v6: Documentation Nitpicks(Nanley)
Cc: Ville Syrjala
Cc: Dhinakaran Pandiyan
Cc: Kalyan Kondapally
Cc: Rafael Antognolli
Cc: Nanley Chery
Signed-off-by: Radhakrishna Sripada
---
include/uapi/drm/drm_fourcc.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 1aa6d468c048..4aa7f3f9712a 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -434,6 +434,25 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
+ * compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
+ * and at index 1. The clear color is stored at index 2, and the pitch should
+ * be ignored. The clear color structure is 256 bits. The first 128 bits
+ * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
+ * by 32 bits. The raw clear color is consumed by the 3d engine and generates
+ * the converted clear color of size 64 bits. The first 32 bits store the Lower
+ * Converted Clear Color value and the next 32 bits store the Higher Converted
+ * Clear Color value when applicable. The Converted Clear Color values are
+ * consumed by the DE. The last 64 bits are used to store Color Discard Enable
+ * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
+ * corresponds to an area of 4x1 tiles in the main surface. The main surface
+ * pitch is required to be a multiple of 4 tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
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[Intel-gfx] [PATCH v6 08/10] Gen-12 display can decompress surfaces compressed by the media engine.
From: Dhinakaran Pandiyan
Detect the modifier corresponding to media compression to enable
display decompression for YUV and xRGB packed formats. A new modifier is
added so that the driver can distinguish between media and render
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
support media decompression.
v2: Fix checkpatch warnings on code style (Lucas)
From DK:
Separate modifier array for planes that cannot decompress media (Ville)
v3: Support planar formats
Cc: Nanley G Chery
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 237 +-
.../drm/i915/display/intel_display_types.h| 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 44 +++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
4 files changed, 220 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0f22ccc6660d..20ad089da6ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1936,6 +1936,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
if (color_plane == 1)
return 128;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ if (color_plane == 3)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
if (color_plane == 1)
return 64;
@@ -2278,8 +2282,16 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static bool is_surface_linear(u64 modifier, int color_plane)
{
- return modifier == DRM_FORMAT_MOD_LINEAR ||
- (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane
== 1);
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ return true;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return color_plane == 1;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ return color_plane == 1 || color_plane == 3;
+ default:
+ return false;
+ }
}
static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2467,6 +2479,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2514,6 +2527,10 @@ static const struct drm_format_info gen12_ccs_formats[]
= {
.cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
{ .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
.cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_YUYV, .num_planes = 2,
+ .cpp = { 2, 1, }, .hsub = 4, .vsub = 32, .is_yuv = true },
+ { .format = DRM_FORMAT_NV12, .num_planes = 4,
+ .cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
};
static const struct drm_format_info *
@@ -2551,6 +2568,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -2614,7 +2632,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer
*fb, int color_plane)
}
tile_width = intel_tile_width_bytes(fb, color_plane);
- if (is_ccs_modifier(fb->modifier) && color_plane == 0) {
+ if (is_ccs_modifier(fb->modifier)) {
/*
* Display WA #0531: skl,bxt,kbl,glk
*
@@ -2624,7 +2642,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer
*fb, int color_plane)
* require the entire fb to accommodate that to avoid
* potential runtime errors at plane configuration time.
*/
- if (IS_GEN(dev_priv, 9) && fb->width > 3840)
+ if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
tile_width *= 4;
/*
* The main surface pitch must be padded to a multiple of four
@@ -2704,25 +2722,71 @@ static bool intel_plane_needs_remap(const struct
intel_plane_state *plane_state)
return stride > max_stride;
}
+static void
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct
drm_framebuffer *fb, int color_plane)
+{
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) {
+ static const struct {
+
[Intel-gfx] [PATCH v6 06/10] drm/framebuffer: Format modifier for Intel Gen-12 media compression
From: Dhinakaran Pandiyan
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
Cc: Nanley G Chery
Cc: Matt Roper
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
include/uapi/drm/drm_fourcc.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 5ba481f49931..1aa6d468c048 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -421,6 +421,19 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths. For semi-planar formats like NV12, CCS plane follows the
+ * Y and UV planes i.e., planes 0 and 2 are used for Y and UV surfaces,
+ * planes 1 and 3 for the respective CCS.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.20.1
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[Intel-gfx] [PATCH v6 02/10] drm/i915: Use intel_tile_height() instead of re-implementing
From: Dhinakaran Pandiyan intel_tile_dims() computes tile height using size and width, when there is already a function to do just that - intel_tile_height() Cc: Ville Syrjälä Cc: Matt Roper Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9dce2e9e5376..3796547ba018 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1982,7 +1982,7 @@ static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane, unsigned int cpp = fb->format->cpp[color_plane]; *tile_width = tile_width_bytes / cpp; - *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes; + *tile_height = intel_tile_height(fb, color_plane); } unsigned int -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 04/10] drm/i915/tgl: Gen-12 render decompression
From: Dhinakaran Pandiyan
Gen-12 display decompression operates on Y-tiled compressed main surface.
The CCS is linear and has 4 bits of metadata for each main surface cache
line pair, a size ratio of 1:256. Gen-12 display decompression is
incompatible with buffers compressed by earlier GPUs, so make use of a new
modifier to identify gen-12 compression. Another notable change is that
render decompression is supported on all planes except cursor and on all
pipes. Start by adding render decompression support for [A,X]BGR888 pixel
formats.
v2: Fix checkpatch warnings (Lucas)
v3:
Rebase, disable color clear, styling changes and modify
intel_tile_width_bytes and intel_tile_height to handle linear CCS
Cc: Ville Syrjälä
Cc: Matt Roper
Cc: Nanley G Chery
Cc: Jason Ekstrand
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 85
drivers/gpu/drm/i915/display/intel_sprite.c | 23 --
drivers/gpu/drm/i915/i915_reg.h | 1 +
3 files changed, 84 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index b8ef99eac254..194e508430db 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1936,6 +1936,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
if (color_plane == 1)
return 128;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ if (color_plane == 1)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -1969,8 +1973,15 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
static unsigned int
intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
{
- return intel_tile_size(to_i915(fb->dev)) /
- intel_tile_width_bytes(fb, color_plane);
+ switch (fb->modifier) {
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ if (color_plane == 1)
+ return 1;
+ /* fall through */
+ default:
+ return intel_tile_size(to_i915(fb->dev)) /
+ intel_tile_width_bytes(fb, color_plane);
+ }
}
/* Return the tile dimensions in pixel units */
@@ -2069,6 +2080,8 @@ static unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
if (INTEL_GEN(dev_priv) >= 9)
return 256 * 1024;
return 0;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
@@ -2265,7 +2278,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static bool is_surface_linear(u64 modifier, int color_plane)
{
- return modifier == DRM_FORMAT_MOD_LINEAR;
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane
== 1);
}
static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2452,6 +2466,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
fb_modifier)
return I915_TILING_X;
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2472,7 +2487,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
fb_modifier)
* us a ratio of one byte in the CCS for each 8x16 pixels in the
* main surface.
*/
-static const struct drm_format_info ccs_formats[] = {
+static const struct drm_format_info skl_ccs_formats[] = {
{ .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
{ .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
@@ -2483,6 +2498,24 @@ static const struct drm_format_info ccs_formats[] = {
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
};
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
+ * the main surface.
+ */
+static const struct drm_format_info gen12_ccs_formats[] = {
+ { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, },
[Intel-gfx] [PATCH v6 05/10] drm/i915: Extract framebufer CCS offset checks into a function
From: Dhinakaran Pandiyan
intel_fill_fb_info() has grown quite large and wrapping the offset checks
into a separate function makes the loop a bit easier to follow.
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/display/intel_display.c | 69
1 file changed, 40 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 194e508430db..0f22ccc6660d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2704,6 +2704,43 @@ static bool intel_plane_needs_remap(const struct
intel_plane_state *plane_state)
return stride > max_stride;
}
+static int
+intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int x, int y)
+{
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+ int hsub = fb->format->hsub;
+ int vsub = fb->format->vsub;
+ int tile_width, tile_height;
+ int ccs_x, ccs_y;
+ int main_x, main_y;
+
+ intel_tile_dims(fb, 1, _width, _height);
+
+ tile_width *= hsub;
+ tile_height *= vsub;
+
+ ccs_x = (x * hsub) % tile_width;
+ ccs_y = (y * vsub) % tile_height;
+ main_x = intel_fb->normal[0].x % tile_width;
+ main_y = intel_fb->normal[0].y % tile_height;
+
+ /*
+* CCS doesn't have its own x/y offset register, so the intra CCS tile
+* x/y offsets must match between CCS and the main surface.
+*/
+ if (main_x != ccs_x || main_y != ccs_y) {
+ DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main
%d,%d ccs %d,%d)\n",
+ main_x, main_y,
+ ccs_x, ccs_y,
+ intel_fb->normal[0].x,
+ intel_fb->normal[0].y,
+ x, y);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int
intel_fill_fb_info(struct drm_i915_private *dev_priv,
struct drm_framebuffer *fb)
@@ -2735,35 +2772,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
}
if (is_ccs_modifier(fb->modifier) && i == 1) {
- int hsub = fb->format->hsub;
- int vsub = fb->format->vsub;
- int tile_width, tile_height;
- int main_x, main_y;
- int ccs_x, ccs_y;
-
- intel_tile_dims(fb, i, _width, _height);
-
- tile_width *= hsub;
- tile_height *= vsub;
-
- ccs_x = (x * hsub) % tile_width;
- ccs_y = (y * vsub) % tile_height;
- main_x = intel_fb->normal[0].x % tile_width;
- main_y = intel_fb->normal[0].y % tile_height;
-
- /*
-* CCS doesn't have its own x/y offset register, so the
intra CCS tile
-* x/y offsets must match between CCS and the main
surface.
-*/
- if (main_x != ccs_x || main_y != ccs_y) {
- DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs
%d,%d) full (main %d,%d ccs %d,%d)\n",
- main_x, main_y,
- ccs_x, ccs_y,
- intel_fb->normal[0].x,
- intel_fb->normal[0].y,
- x, y);
- return -EINVAL;
- }
+ ret = intel_fb_check_ccs_xy(fb, x, y);
+ if (ret)
+ return ret;
}
/*
--
2.20.1
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: add support to one DP-MST stream
== Series Details ==
Series: drm/i915/tgl: add support to one DP-MST stream
URL : https://patchwork.freedesktop.org/series/68671/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cce4d3a65919 drm/i915/tgl: add support to one DP-MST stream
-:29: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#29: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1910:
+ temp |= TRANS_DDI_MST_TRANSPORT_SELECT(
total: 0 errors, 0 warnings, 1 checks, 19 lines checked
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Use vfunc to check engine submission mode (rev2)
== Series Details ==
Series: drm/i915/execlists: Use vfunc to check engine submission mode (rev2)
URL : https://patchwork.freedesktop.org/series/68654/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7204 -> Patchwork_15029
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/index.html
Known issues
Here are the changes found in Patchwork_15029 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
Possible fixes
* igt@gem_mmap_gtt@basic:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4] +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u3/igt@gem_mmap_...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/fi-icl-u3/igt@gem_mmap_...@basic.html
* igt@kms_chamelium@hdmi-crc-fast:
- {fi-icl-u4}:[FAIL][5] ([fdo#111045]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u4/igt@kms_chamel...@hdmi-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/fi-icl-u4/igt@kms_chamel...@hdmi-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831
Participating hosts (50 -> 41)
--
Additional (1): fi-kbl-soraka
Missing(10): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-kbl-8809g fi-icl-y fi-bdw-samus fi-tgl-y fi-byt-clapper fi-skl-6600u
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7204 -> Patchwork_15029
CI-20190529: 20190529
CI_DRM_7204: 2ec2c26b76ebf320dfecf692a928ed85797dc6b9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5248: 81e55f1f97d73e48f00caa7e4fb98295023c5afa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15029: 62c8964189e2eef0ca8635084b875246583a1fdd @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
62c8964189e2 drm/i915/execlists: Use vfunc to check engine submission mode
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/index.html
___
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[Intel-gfx] [CI] drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
Currently we insert a arbitration point every 128MiB during a blitter
copy. At 8GiB/s, this is around 30ms. This is a little on the large side
if we need to inject a high priority work, so reduced it down to 8MiB or
roughly 1ms.
v2: Don't forget both fill/copy.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index 516e61e99212..51acffd31575 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -17,7 +17,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context
*ce,
u32 value)
{
struct drm_i915_private *i915 = ce->vm->i915;
- const u32 block_size = S16_MAX * PAGE_SIZE;
+ const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */
struct intel_engine_pool_node *pool;
struct i915_vma *batch;
u64 offset;
@@ -201,7 +201,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct
intel_context *ce,
struct i915_vma *dst)
{
struct drm_i915_private *i915 = ce->vm->i915;
- const u32 block_size = S16_MAX * PAGE_SIZE;
+ const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */
struct intel_engine_pool_node *pool;
struct i915_vma *batch;
u64 src_offset, dst_offset;
--
2.24.0.rc1
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/blt: fixup block_size rounding
== Series Details ==
Series: drm/i915/blt: fixup block_size rounding
URL : https://patchwork.freedesktop.org/series/68670/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7204 -> Patchwork_15028
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15028/index.html
Known issues
Here are the changes found in Patchwork_15028 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15028/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html
* igt@gem_mmap@basic-small-bo:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u3/igt@gem_m...@basic-small-bo.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15028/fi-icl-u3/igt@gem_m...@basic-small-bo.html
Possible fixes
* igt@gem_mmap_gtt@basic:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u3/igt@gem_mmap_...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15028/fi-icl-u3/igt@gem_mmap_...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
Participating hosts (50 -> 42)
--
Additional (1): fi-kbl-soraka
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan
fi-icl-y fi-tgl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7204 -> Patchwork_15028
CI-20190529: 20190529
CI_DRM_7204: 2ec2c26b76ebf320dfecf692a928ed85797dc6b9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5248: 81e55f1f97d73e48f00caa7e4fb98295023c5afa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15028: e8c18c56739789adcdb63d279683f7b49c9563b3 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e8c18c567397 drm/i915/blt: fixup block_size rounding
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15028/index.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Drop global engine lookup for gt selftests
== Series Details ==
Series: drm/i915/selftests: Drop global engine lookup for gt selftests
URL : https://patchwork.freedesktop.org/series/68615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7195_full -> Patchwork_15013_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_15013_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_draw_crc@draw-method-xrgb-render-xtiled:
- {shard-tglb}: [PASS][1] -> [INCOMPLETE][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-tglb7/igt@kms_draw_...@draw-method-xrgb-render-xtiled.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15013/shard-tglb7/igt@kms_draw_...@draw-method-xrgb-render-xtiled.html
Known issues
Here are the changes found in Patchwork_15013_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +3
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-kbl4/igt@gem_ctx_isolat...@rcs0-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15013/shard-kbl7/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_ctx_switch@vcs1-heavy-queue:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +6 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-iclb1/igt@gem_ctx_swi...@vcs1-heavy-queue.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15013/shard-iclb7/igt@gem_ctx_swi...@vcs1-heavy-queue.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +14 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-iclb2/igt@gem_exec_sched...@promotion-bsd1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15013/shard-iclb7/igt@gem_exec_sched...@promotion-bsd1.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +3 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-iclb6/igt@gem_exec_sched...@reorder-wide-bsd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15013/shard-iclb2/igt@gem_exec_sched...@reorder-wide-bsd.html
* igt@gem_linear_blits@normal:
- shard-apl: [PASS][11] -> [INCOMPLETE][12] ([fdo#103927])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-apl2/igt@gem_linear_bl...@normal.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15013/shard-apl8/igt@gem_linear_bl...@normal.html
* igt@i915_selftest@live_hangcheck:
- shard-iclb: [PASS][13] -> [INCOMPLETE][14] ([fdo#107713] /
[fdo#108569])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-iclb1/igt@i915_selftest@live_hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15013/shard-iclb2/igt@i915_selftest@live_hangcheck.html
* igt@kms_color@pipe-a-ctm-0-5:
- shard-skl: [PASS][15] -> [DMESG-WARN][16] ([fdo#106107])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-skl10/igt@kms_co...@pipe-a-ctm-0-5.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15013/shard-skl2/igt@kms_co...@pipe-a-ctm-0-5.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-apl6/igt@kms_cursor_...@pipe-c-cursor-suspend.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15013/shard-apl6/igt@kms_cursor_...@pipe-c-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#105363])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-skl8/igt@kms_f...@flip-vs-expired-vblank.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15013/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +4 similar
issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7195/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15013/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-iclb: [PASS][23] -> [INCOMPLETE][24] ([fdo#107713])
[23]:
Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC submission but enabled
> From: Ceraolo Spurio, Daniele
> Sent: Monday, October 28, 2019 11:30 AM
> To: Hiatt, Don ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC
> submission but enabled
>
>
>
> On 10/28/19 11:17 AM, Hiatt, Don wrote:
> >> From: Ceraolo Spurio, Daniele
> >> Sent: Monday, October 28, 2019 9:44 AM
> >> To: Hiatt, Don ; intel-gfx@lists.freedesktop.org
> >> Subject: Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o
> GuC
> >> submission but enabled
> >>
> >>
> >>
> >> On 10/24/19 9:29 AM, don.hi...@intel.com wrote:
> >>> From: Don Hiatt
> >>>
> >>> Check to see if GuC submission is enabled before requesting the
> >>> EXIT_S_STATE action.
> >>>
> >>
> >> You're only skipping the resume, but does it make any sense to do the
> >> suspend action if we're not going to call the resume one? Does guc do
> >> anything in the suspend action that we still require? I thought it only
> >> saved the submission status, which we don't care about if guc submission
> >> is disabled.
> >>
> >> Daniele
> >>
> >
> > Hi Daniele,
> >
> > I tried skipping the suspend all together but then the HuC gets timeouts
> > waiting for the GuC to acknowledge the authentication request which leads to
> a
> > wedged GPU. ☹
> >
>
> Do we know why? if we skip the suspend/resume H2G and reload the blobs
> after resetting the HW it should look like a clean boot from the HW
> perspective, so the fact that HuC auth times out feels weird and might
> hide other issues. I asked one of the guc devs and he also thinks this
> is not expected behavior. Can you dig a bit more?
>
> Thanks,
> Daniele
>
No idea why but I'll do some digging and see what I find.
Thanks!
don
> > BTW, I made a typo in the patch, should be 'drm/i915' not '914', I'll fix
> > that
> > up.
> >
> > Thanks,
> >
> > don
> >
> >
> >>> On some platforms (e.g. KBL) that do not support GuC submission, but
> >>> the user enabled the GuC communication (e.g for HuC authentication)
> >>> calling the GuC EXIT_S_STATE action results in lose of ability to
> >>> enter RC6. Guard against this by only requesting the GuC action on
> >>> platforms that support GuC submission.
> >>>
> >>> I've verfied that intel_guc_resume() only gets called when driver
> >>> is loaded with: guc_enable={1,2,3}, all other cases (no args,
> >>> guc_enable={0,-1} the intel_guc_resume() is not called.
> >>>
> >>> Signed-off-by: Don Hiatt
> >>> ---
> >>>drivers/gpu/drm/i915/gt/uc/intel_guc.c | 5 -
> >>>1 file changed, 4 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> >> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> >>> index 37f7bcbf7dac..33318ed135c0 100644
> >>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> >>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> >>> @@ -565,7 +565,10 @@ int intel_guc_resume(struct intel_guc *guc)
> >>> GUC_POWER_D0,
> >>> };
> >>>
> >>> - return intel_guc_send(guc, action, ARRAY_SIZE(action));
> >>> + if (guc->submission_supported)
> >>> + return intel_guc_send(guc, action, ARRAY_SIZE(action));
> >>> +
> >>> + return 0;
> >>>}
> >>>
> >>>/**
> >>>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/vbt: Handle generic DTD block
VBT revision 229 adds a new "Generic DTD" block 58 and deprecates the
old LFP panel mode data in block 42. Let's start parsing this block to
fill in the panel fixed mode on devices with a >=229 VBT.
v2:
* Update according to the recent updates:
- DTD size is now 16 bits instead of 24
- polarity is now just a single bit for hsync and vsync and is
properly documented
* Minor checkpatch fix
Bspec: 54751
Bspec: 20148
Cc: Jani Nikula
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bios.c | 87 ++-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 31 +++
2 files changed, 115 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 63c1bd4c2954..0d1504e23a49 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -202,6 +202,72 @@ get_lvds_fp_timing(const struct bdb_header *bdb,
return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
}
+static struct drm_display_mode *
+parse_generic_dtd(struct drm_i915_private *dev_priv,
+ const struct bdb_generic_dtd *generic_dtd)
+{
+ const struct bdb_generic_dtd_entry *dtd;
+ struct drm_display_mode *panel_fixed_mode;
+ int num_dtd;
+
+ if (generic_dtd->gdtd_size < sizeof(struct bdb_generic_dtd_entry)) {
+ DRM_ERROR("GDTD size %u is too small.\n",
+ generic_dtd->gdtd_size);
+ return NULL;
+ } else if (generic_dtd->gdtd_size !=
+ sizeof(struct bdb_generic_dtd_entry)) {
+ DRM_ERROR("Unexpected GDTD size %u\n", generic_dtd->gdtd_size);
+ /* DTD has unknown fields, but keep going */
+ }
+
+ num_dtd = (get_blocksize(generic_dtd) -
+ sizeof(struct bdb_generic_dtd)) / generic_dtd->gdtd_size;
+ if (dev_priv->vbt.panel_type > num_dtd) {
+ DRM_ERROR("Panel type %d not found in table of %d DTD's\n",
+ dev_priv->vbt.panel_type, num_dtd);
+ return NULL;
+ }
+
+ dtd = _dtd->dtd[dev_priv->vbt.panel_type];
+
+ panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
+ if (!panel_fixed_mode)
+ return NULL;
+
+ panel_fixed_mode->hdisplay = dtd->hactive;
+ panel_fixed_mode->hsync_start =
+ panel_fixed_mode->hdisplay + dtd->hfront_porch;
+ panel_fixed_mode->hsync_end =
+ panel_fixed_mode->hsync_start + dtd->hsync;
+ panel_fixed_mode->htotal = panel_fixed_mode->hsync_end;
+
+ panel_fixed_mode->vdisplay = dtd->vactive;
+ panel_fixed_mode->vsync_start =
+ panel_fixed_mode->vdisplay + dtd->vfront_porch;
+ panel_fixed_mode->vsync_end =
+ panel_fixed_mode->vsync_start + dtd->vsync;
+ panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end;
+
+ panel_fixed_mode->clock = dtd->pixel_clock;
+ panel_fixed_mode->width_mm = dtd->width_mm;
+ panel_fixed_mode->height_mm = dtd->height_mm;
+
+ panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
+ drm_mode_set_name(panel_fixed_mode);
+
+ if (dtd->hsync_polarity)
+ panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC;
+ else
+ panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC;
+
+ if (dtd->vsync_polarity)
+ panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC;
+ else
+ panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;
+
+ return panel_fixed_mode;
+}
+
/* Try to find integrated panel data */
static void
parse_lfp_panel_data(struct drm_i915_private *dev_priv,
@@ -210,6 +276,7 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
const struct bdb_lvds_options *lvds_options;
const struct bdb_lvds_lfp_data *lvds_lfp_data;
const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
+ const struct bdb_generic_dtd *generic_dtd;
const struct lvds_dvo_timing *panel_dvo_timing;
const struct lvds_fp_timing *fp_timing;
struct drm_display_mode *panel_fixed_mode;
@@ -262,6 +329,18 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
break;
}
+ if (bdb->version >= 229) {
+ generic_dtd = find_section(bdb, BDB_GENERIC_DTD);
+ if (!generic_dtd)
+ return;
+
+ panel_fixed_mode = parse_generic_dtd(dev_priv, generic_dtd);
+ if (!panel_fixed_mode)
+ return;
+
+ goto skip_legacy_lfp;
+ }
+
lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
if (!lvds_lfp_data)
return;
@@ -282,9 +361,6 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
- DRM_DEBUG_KMS("Found panel mode in BIOS VBT
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/5] drm/dsi: clean up DSI data type definitions
== Series Details == Series: series starting with [v2,1/5] drm/dsi: clean up DSI data type definitions URL : https://patchwork.freedesktop.org/series/68664/ State : success == Summary == CI Bug Log - changes from CI_DRM_7204 -> Patchwork_15027 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/index.html Known issues Here are the changes found in Patchwork_15027 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_switch@legacy-render: - fi-bxt-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927] / [fdo#111381]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html * igt@gem_flink_basic@basic: - fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724] / [fdo#112052 ]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u3/igt@gem_flink_ba...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/fi-icl-u3/igt@gem_flink_ba...@basic.html * igt@kms_chamelium@dp-edid-read: - fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#106766]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html * igt@prime_self_import@basic-llseek-bad: - fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u3/igt@prime_self_imp...@basic-llseek-bad.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/fi-icl-u3/igt@prime_self_imp...@basic-llseek-bad.html Possible fixes * igt@gem_mmap_gtt@basic: - fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u3/igt@gem_mmap_...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/fi-icl-u3/igt@gem_mmap_...@basic.html [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#106766]: https://bugs.freedesktop.org/show_bug.cgi?id=106766 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381 [fdo#112052 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112052 Participating hosts (50 -> 43) -- Additional (1): fi-kbl-soraka Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-tgl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7204 -> Patchwork_15027 CI-20190529: 20190529 CI_DRM_7204: 2ec2c26b76ebf320dfecf692a928ed85797dc6b9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5248: 81e55f1f97d73e48f00caa7e4fb98295023c5afa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15027: 17cabd00dabc9a12834db06227139823f6b94894 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 17cabd00dabc drm/dsi: add helpers for DSI compression mode and PPS packets 4473cd70ee71 drm/dsi: rename MIPI_DCS_SET_PARTIAL_AREA to MIPI_DCS_SET_PARTIAL_ROWS 496dc977089e drm/dsi: add missing DSI DCS commands 1e7022690364 drm/dsi: add missing DSI data types b48e99db722b drm/dsi: clean up DSI data type definitions == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/print: cleanup and new drm_device based logging (rev3)
== Series Details ==
Series: drm/print: cleanup and new drm_device based logging (rev3)
URL : https://patchwork.freedesktop.org/series/67795/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7204 -> Patchwork_15026
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/index.html
Known issues
Here are the changes found in Patchwork_15026 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u3/igt@gem_m...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/fi-icl-u3/igt@gem_m...@basic.html
* igt@kms_busy@basic-flip-a:
- fi-icl-u2: [PASS][3] -> [TIMEOUT][4] ([fdo#111800])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u2/igt@kms_b...@basic-flip-a.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/fi-icl-u2/igt@kms_b...@basic-flip-a.html
Possible fixes
* igt@gem_mmap_gtt@basic:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/fi-icl-u3/igt@gem_mmap_...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/fi-icl-u3/igt@gem_mmap_...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678
[fdo#111800]: https://bugs.freedesktop.org/show_bug.cgi?id=111800
Participating hosts (50 -> 42)
--
Additional (1): fi-kbl-soraka
Missing(9): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-tgl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7204 -> Patchwork_15026
CI-20190529: 20190529
CI_DRM_7204: 2ec2c26b76ebf320dfecf692a928ed85797dc6b9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5248: 81e55f1f97d73e48f00caa7e4fb98295023c5afa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15026: 6d6978fc4683e82d1f7facb6fc22a0b926b71ad0 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6d6978fc4683 drm/print: introduce new struct drm_device based logging macros
d11f6509835f drm/print: group logging functions by prink or device based
a43e2082e8f4 drm/print: convert debug category macros into an enum
38759991f3bd drm/print: underscore prefix functions that should be private to
print
87f85c36af54 drm/print: rename drm_debug to __drm_debug to discourage use
9fd22e6ab31c drm/amdgpu: use drm_debug_enabled() to check for debug categories
98a1b348acd0 drm/nouveau: use drm_debug_enabled() to check for debug categories
40c33aad0053 drm/i915: use drm_debug_enabled() to check for debug categories
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/5] drm/dsi: clean up DSI data type definitions
== Series Details == Series: series starting with [v2,1/5] drm/dsi: clean up DSI data type definitions URL : https://patchwork.freedesktop.org/series/68664/ State : warning == Summary == $ dim checkpatch origin/drm-tip b48e99db722b drm/dsi: clean up DSI data type definitions 1e7022690364 drm/dsi: add missing DSI data types 496dc977089e drm/dsi: add missing DSI DCS commands 4473cd70ee71 drm/dsi: rename MIPI_DCS_SET_PARTIAL_AREA to MIPI_DCS_SET_PARTIAL_ROWS -:38: WARNING:LONG_LINE_COMMENT: line over 100 characters #38: FILE: include/video/mipi_display.h:111: + MIPI_DCS_SET_PARTIAL_ROWS = 0x30, /* MIPI DCS 1.02 - MIPI_DCS_SET_PARTIAL_AREA before that */ total: 0 errors, 1 warnings, 0 checks, 16 lines checked 17cabd00dabc drm/dsi: add helpers for DSI compression mode and PPS packets ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Program LUT before intel_color_commit() if LUT was not previously set v2
Since commit 051a6d8d3ca0 ("drm/i915: Move LUT programming to happen after
vblank waits"), I am seeing an ugly colored flash of the first few display
lines on 2 Cherry Trail devices when the gamma table gets set for the first
time. A blue flash on a GPD win and a yellow flash on an Asus T100HA.
The problem is that since this change, the LUT is programmed after the
write *and latching* of the double-buffered register which causes the LUT
to be used starting at the next frame. This means that the old LUT is still
used for the first couple of lines of the display. If no LUT was in use
before then the LUT registers may contain bogus values. This leads to
messed up colors until the new LUT values are written. At least on CHT DSI
panels this causes messed up colors on the first few lines.
This commit fixes this by adding a load_lut_before_commit boolean,
modifying commit_pipe_config() to load the luts earlier if this is set.
and setting this from intel_color_check when enabling gamma (rather then
updating an existing gamma table).
Changes in v2:
-Simply check for setting load_lut_before_commit to:
if (!old_crtc_state->gamma_enable && new_crtc_state->gamma_enable)
Fixes: 051a6d8d3ca0 ("drm/i915: Move LUT programming to happen after vblank
waits")
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/display/intel_color.c | 14 ++
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
3 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index fa44eb73d088..954a232c15d1 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1063,6 +1063,8 @@ intel_color_add_affected_planes(struct intel_crtc_state
*new_crtc_state)
intel_atomic_get_old_crtc_state(state, crtc);
struct intel_plane *plane;
+ new_crtc_state->load_lut_before_commit = false;
+
if (!new_crtc_state->base.active ||
drm_atomic_crtc_needs_modeset(_crtc_state->base))
return 0;
@@ -1071,6 +1073,18 @@ intel_color_add_affected_planes(struct intel_crtc_state
*new_crtc_state)
new_crtc_state->csc_enable == old_crtc_state->csc_enable)
return 0;
+ /*
+* Normally we load the LUTs after vblank / after the double-buffer
+* registers written by commit have been latched, this avoids a
+* gamma change mid-way the screen. This does mean that the first
+* few lines of the display will (sometimes) still use the old
+* table. This is fine when changing an existing LUT, but if this
+* is the first time the LUT gets loaded, then the hw may contain
+* random values, causing the first lines to have funky colors.
+*/
+ if (!old_crtc_state->gamma_enable && new_crtc_state->gamma_enable)
+ new_crtc_state->load_lut_before_commit = true;
+
for_each_intel_plane_on_crtc(_priv->drm, crtc, plane) {
struct intel_plane_state *plane_state;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index cbf9cf30050c..6b1dc5a5aeb1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14168,8 +14168,11 @@ static void commit_pipe_config(struct
intel_atomic_state *state,
*/
if (!modeset) {
if (new_crtc_state->base.color_mgmt_changed ||
- new_crtc_state->update_pipe)
+ new_crtc_state->update_pipe) {
+ if (new_crtc_state->load_lut_before_commit)
+ intel_color_load_luts(new_crtc_state);
intel_color_commit(new_crtc_state);
+ }
if (INTEL_GEN(dev_priv) >= 9)
skl_detach_scalers(new_crtc_state);
@@ -14717,6 +14720,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (new_crtc_state->base.active &&
!needs_modeset(new_crtc_state) &&
+ !new_crtc_state->load_lut_before_commit &&
(new_crtc_state->base.color_mgmt_changed ||
new_crtc_state->update_pipe))
intel_color_load_luts(new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 40184e823c84..6bcc997b7ecb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -990,6 +990,9 @@ struct intel_crtc_state {
/* enable pipe csc? */
bool csc_enable;
+ /* load luts before color settings commit */
+ bool
Re: [Intel-gfx] [PATCH] drm/i915: Program LUT before intel_color_commit() if LUT was not previously set
Hi,
On 25-10-2019 21:45, Ville Syrjälä wrote:
On Fri, Oct 25, 2019 at 09:23:47PM +0200, Hans de Goede wrote:
Hi,
On 21-10-2019 16:39, Ville Syrjälä wrote:
On Sun, Oct 20, 2019 at 08:19:33PM +0200, Hans de Goede wrote:
Since commit 051a6d8d3ca0 ("drm/i915: Move LUT programming to happen after
vblank waits"), I am seeing an ugly colored flash of the first few display
lines on 2 Cherry Trail devices when the gamma table gets set for the first
time. A blue flash on a GPD win and a yellow flash on an Asus T100HA.
The problem is that since this change, the LUT is programmed after the
write *and latching* of the double-buffered register which causes the LUT
to be used starting at the next frame. This means that the old LUT is still
used for the first couple of lines of the display. If no LUT was in use
before then the LUT registers may contain bogus values. This leads to
messed up colors until the new LUT values are written. At least on CHT DSI
panels this causes messed up colors on the first few lines.
This commit fixes this by adding a load_lut_before_commit boolean,
modifying intel_begin_crtc_commit to load the luts earlier if this is set,
and setting this from intel_color_check when a LUT table was not in use
before (and thus may contain bogus values), or when the table size
changes.
The real solution is vblank workers, which I have somewhat implemented
here:
git://github.com/vsyrjala/linux.git vblank_worker_8_kthread
Though even with the qos tricks there we still probably can't quite make
it in time. Essentially we have a bit less than one scanline after start
of vblank to do the work before pixels start to flow through the pipe.
We might be extend that to almost four scanlines but that partocular
thing is documeted as debug feature so not sure we should really use it.
Also I don't think four scanlines is always enough either. So it's still
very much possible that we get the first 100 or so pixels with the old LUT.
Thank you for the info and for the review.
Fixes: 051a6d8d3ca0 ("drm/i915: Move LUT programming to happen after vblank
waits")
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/i915/display/intel_color.c| 26 +++
drivers/gpu/drm/i915/display/intel_display.c | 7 +
.../drm/i915/display/intel_display_types.h| 3 +++
3 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 71a0201437a9..0da6dcc5bebd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1052,6 +1052,32 @@ intel_color_add_affected_planes(struct intel_crtc_state
*new_crtc_state)
new_crtc_state->update_planes |= BIT(plane->id);
}
+ /*
+* Normally we load the LUTs after vblank / after the double-buffer
+* registers written by commit have been latched, this avoids a
+* gamma change mid-way the screen. This does mean that the first
+* few lines of the display will (sometimes) still use the old
+* table. This is fine when changing an existing LUT, but if this
+* is the first time the LUT gets loaded, then the hw may contain
+* random values, causing the first lines to have funky colors.
+*
+* So if were enabling a LUT for the first time or changing the table
+* size, then we must do this before the commit to avoid corrupting
+* the first lines of the display.
+*/
+ if (!old_crtc_state->base.gamma_lut && new_crtc_state->base.gamma_lut)
+ new_crtc_state->load_lut_before_commit = true;
+ else if (!old_crtc_state->base.degamma_lut &&
+new_crtc_state->base.degamma_lut)
+ new_crtc_state->load_lut_before_commit = true;
+ else if (old_crtc_state->base.gamma_lut &&
+new_crtc_state->base.gamma_lut &&
+lut_is_legacy(old_crtc_state->base.gamma_lut) !=
+ lut_is_legacy(new_crtc_state->base.gamma_lut))
+ new_crtc_state->load_lut_before_commit = true;
+ else
+ new_crtc_state->load_lut_before_commit = false;
The 'no gamma -> yes gamma' thing I might be willing to accept. The rest
not so much. I was already pondering about such optimizations for the
plane gamma/csc stuff in my vblank branch.
Ok, so I can submit a v2 based on dinq with only the
if (!old_crtc_state->base.gamma_lut && new_crtc_state->base.gamma_lut)
check, or
But for the fastboot case I think what we could do is just sanitize
the LUT(s) after readout if gamma wasn't enabled by the BIOS.
We could do this, but this falls a bit outside of my expertise, I would be
more then happy to test a patch on one of the machines which needs this
LUTS sanitizing though. I get a very visible flash of a couple of bright
blue or yellow (2 different machines) on the upper few lines the first
time the gamma table gets loaded, so
[Intel-gfx] [PATCH v6 10/10] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse new Clear Color information and extend Gen12 render decompression
functionality to the newly added modifier.
v2: Fix has_alpha flag for modifiers, omit CC modifier during initial
plane config(Matt). Fix Lookup error.
v3: Fix the panic while running kms_cube
v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt)
v5: Fix typos and wrap comments(Matt)
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjala
Cc: Shashank Sharma
Cc: Rafael Antognolli
Cc: Nanley G Chery
Reviewed-by: Matt Roper
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/display/intel_display.c | 52 +++
.../drm/i915/display/intel_display_types.h| 3 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++-
drivers/gpu/drm/i915/i915_reg.h | 12 +
4 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 20ad089da6ee..6d6eab8d4776 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1944,6 +1944,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
if (color_plane == 1)
return 64;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ if (color_plane == 1 || color_plane == 2)
+ return 64;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -2085,6 +2089,7 @@ static unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
return 256 * 1024;
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return 16 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2287,6 +2292,8 @@ static bool is_surface_linear(u64 modifier, int
color_plane)
return true;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return color_plane == 1;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return color_plane == 1 || color_plane == 2;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return color_plane == 1 || color_plane == 3;
default:
@@ -2480,6 +2487,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64
fb_modifier)
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2533,6 +2541,21 @@ static const struct drm_format_info gen12_ccs_formats[]
= {
.cpp = { 1, 1, 2, 1}, .hsub = 2, .vsub = 2, .is_yuv = true },
};
+/*
+ * Same as gen12_ccs_formats[] above, but with additional surface used
+ * to pass Clear Color information in plane 2 with 64 bits of data.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+ { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 3,
+ .cpp = { 4, 1, 0, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2560,6 +2583,10 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ return lookup_format_info(gen12_ccs_cc_formats,
+ ARRAY_SIZE(gen12_ccs_cc_formats),
+ cmd->pixel_format);
default:
return NULL;
}
@@ -2569,6 +2596,7 @@ bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
modifier ==
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/print: cleanup and new drm_device based logging (rev3)
== Series Details == Series: drm/print: cleanup and new drm_device based logging (rev3) URL : https://patchwork.freedesktop.org/series/67795/ State : warning == Summary == $ dim checkpatch origin/drm-tip 40c33aad0053 drm/i915: use drm_debug_enabled() to check for debug categories 98a1b348acd0 drm/nouveau: use drm_debug_enabled() to check for debug categories 9fd22e6ab31c drm/amdgpu: use drm_debug_enabled() to check for debug categories 87f85c36af54 drm/print: rename drm_debug to __drm_debug to discourage use 38759991f3bd drm/print: underscore prefix functions that should be private to print a43e2082e8f4 drm/print: convert debug category macros into an enum d11f6509835f drm/print: group logging functions by prink or device based -:202: CHECK:LINE_SPACING: Please don't use multiple blank lines #202: FILE: include/drm/drm_print.h:478: + + total: 0 errors, 0 warnings, 1 checks, 193 lines checked 6d6978fc4683 drm/print: introduce new struct drm_device based logging macros -:77: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #77: FILE: include/drm/drm_print.h:429: +#define __drm_printk(drm, level, type, fmt, ...) \ + dev_##level##type(drm->dev, "[drm] " fmt, ##__VA_ARGS__) -:80: CHECK:LINE_SPACING: Please don't use multiple blank lines #80: FILE: include/drm/drm_print.h:432: + + -:82: ERROR:SPACING: space required after that ',' (ctx:VxO) #82: FILE: include/drm/drm_print.h:434: + __drm_printk(drm, info,, fmt, ##__VA_ARGS__) ^ -:85: ERROR:SPACING: space required after that ',' (ctx:VxO) #85: FILE: include/drm/drm_print.h:437: + __drm_printk(drm, notice,, fmt, ##__VA_ARGS__) ^ -:88: ERROR:SPACING: space required after that ',' (ctx:VxO) #88: FILE: include/drm/drm_print.h:440: + __drm_printk(drm, warn,, fmt, ##__VA_ARGS__) ^ -:91: ERROR:SPACING: space required after that ',' (ctx:VxO) #91: FILE: include/drm/drm_print.h:443: + __drm_printk(drm, err,, "*ERROR* " fmt, ##__VA_ARGS__) ^ -:93: CHECK:LINE_SPACING: Please don't use multiple blank lines #93: FILE: include/drm/drm_print.h:445: + + -:106: CHECK:LINE_SPACING: Please don't use multiple blank lines #106: FILE: include/drm/drm_print.h:458: + + -:110: CHECK:LINE_SPACING: Please don't use multiple blank lines #110: FILE: include/drm/drm_print.h:462: + + -:111: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #111: FILE: include/drm/drm_print.h:463: +#define drm_dbg_core(drm, fmt, ...)\ + drm_dev_dbg(drm->dev, DRM_UT_CORE, fmt, ##__VA_ARGS__) -:113: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #113: FILE: include/drm/drm_print.h:465: +#define drm_dbg(drm, fmt, ...) \ + drm_dev_dbg(drm->dev, DRM_UT_DRIVER, fmt, ##__VA_ARGS__) -:115: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #115: FILE: include/drm/drm_print.h:467: +#define drm_dbg_kms(drm, fmt, ...) \ + drm_dev_dbg(drm->dev, DRM_UT_KMS, fmt, ##__VA_ARGS__) -:117: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #117: FILE: include/drm/drm_print.h:469: +#define drm_dbg_prime(drm, fmt, ...) \ + drm_dev_dbg(drm->dev, DRM_UT_PRIME, fmt, ##__VA_ARGS__) -:119: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #119: FILE: include/drm/drm_print.h:471: +#define drm_dbg_atomic(drm, fmt, ...) \ + drm_dev_dbg(drm->dev, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__) -:121: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #121: FILE: include/drm/drm_print.h:473: +#define drm_dbg_vbl(drm, fmt, ...) \ + drm_dev_dbg(drm->dev, DRM_UT_VBL, fmt, ##__VA_ARGS__) -:123: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #123: FILE: include/drm/drm_print.h:475: +#define drm_dbg_state(drm, fmt, ...) \ + drm_dev_dbg(drm->dev, DRM_UT_STATE, fmt, ##__VA_ARGS__) -:125: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #125: FILE: include/drm/drm_print.h:477: +#define drm_dbg_lease(drm, fmt, ...) \ + drm_dev_dbg(drm->dev, DRM_UT_LEASE, fmt, ##__VA_ARGS__) -:127: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'drm' may be better as '(drm)' to avoid precedence issues #127: FILE: include/drm/drm_print.h:479: +#define drm_dbg_dp(drm, fmt, ...)
Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC submission but enabled
On 10/28/19 11:17 AM, Hiatt, Don wrote:
From: Ceraolo Spurio, Daniele
Sent: Monday, October 28, 2019 9:44 AM
To: Hiatt, Don ; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC
submission but enabled
On 10/24/19 9:29 AM, don.hi...@intel.com wrote:
From: Don Hiatt
Check to see if GuC submission is enabled before requesting the
EXIT_S_STATE action.
You're only skipping the resume, but does it make any sense to do the
suspend action if we're not going to call the resume one? Does guc do
anything in the suspend action that we still require? I thought it only
saved the submission status, which we don't care about if guc submission
is disabled.
Daniele
Hi Daniele,
I tried skipping the suspend all together but then the HuC gets timeouts
waiting for the GuC to acknowledge the authentication request which leads to a
wedged GPU. ☹
Do we know why? if we skip the suspend/resume H2G and reload the blobs
after resetting the HW it should look like a clean boot from the HW
perspective, so the fact that HuC auth times out feels weird and might
hide other issues. I asked one of the guc devs and he also thinks this
is not expected behavior. Can you dig a bit more?
Thanks,
Daniele
BTW, I made a typo in the patch, should be 'drm/i915' not '914', I'll fix that
up.
Thanks,
don
On some platforms (e.g. KBL) that do not support GuC submission, but
the user enabled the GuC communication (e.g for HuC authentication)
calling the GuC EXIT_S_STATE action results in lose of ability to
enter RC6. Guard against this by only requesting the GuC action on
platforms that support GuC submission.
I've verfied that intel_guc_resume() only gets called when driver
is loaded with: guc_enable={1,2,3}, all other cases (no args,
guc_enable={0,-1} the intel_guc_resume() is not called.
Signed-off-by: Don Hiatt
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 37f7bcbf7dac..33318ed135c0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -565,7 +565,10 @@ int intel_guc_resume(struct intel_guc *guc)
GUC_POWER_D0,
};
- return intel_guc_send(guc, action, ARRAY_SIZE(action));
+ if (guc->submission_supported)
+ return intel_guc_send(guc, action, ARRAY_SIZE(action));
+
+ return 0;
}
/**
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Initialise ret
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Initialise ret
URL : https://patchwork.freedesktop.org/series/68662/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7203 -> Patchwork_15025
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/index.html
Known issues
Here are the changes found in Patchwork_15025 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-write-read-distinct:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/fi-icl-u3/igt@gem_mmap_...@basic-write-read-distinct.html
Possible fixes
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4] +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
* igt@i915_selftest@live_blt:
- fi-hsw-peppy: [DMESG-FAIL][5] ([fdo#112147]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/fi-hsw-peppy/igt@i915_selftest@live_blt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/fi-hsw-peppy/igt@i915_selftest@live_blt.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#112147]: https://bugs.freedesktop.org/show_bug.cgi?id=112147
Participating hosts (52 -> 42)
--
Missing(10): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-kbl-7500u fi-icl-y fi-tgl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7203 -> Patchwork_15025
CI-20190529: 20190529
CI_DRM_7203: 912b87256ca0b04ed5f73682068bf6062dd93e6d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5248: 81e55f1f97d73e48f00caa7e4fb98295023c5afa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15025: b2538d08bab1ee98a7fd28556ce281803eff4e51 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b2538d08bab1 drm/i915/display: Mark conn as initialised by iterator
a204f00d5275 drm/i915/selftests: Initialise ret
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/index.html
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[Intel-gfx] [PATCH v2] drm/i915: Avoid HPD poll detect triggering a new detect cycle
For the HPD interrupt functionality the HW depends on power wells in the
display core domain to be on. Accordingly when enabling these power
wells the HPD polling logic will force an HPD detection cycle to account
for hotplug events that may have happened when such a power well was
off.
Thus a detect cycle started by polling could start a new detect cycle if
a power well in the display core domain gets enabled during detect and
stays enabled after detect completes. That in turn can lead to a
detection cycle runaway.
To prevent re-triggering a poll-detect cycle make sure we drop all power
references we acquired during detect synchronously by the end of detect.
This will let the poll-detect logic continue with polling (matching the
off state of the corresponding power wells) instead of scheduling a new
detection cycle.
Fixes: 6cfe7ec02e85 ("drm/i915: Remove the unneeded AUX power ref from
intel_dp_detect()")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112125
Reported-and-tested-by: Val Kulkov
Reported-and-tested-by: wangqr
Cc: Val Kulkov
Cc: wangqr
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_crt.c | 7 +++
drivers/gpu/drm/i915/display/intel_dp.c | 6 ++
drivers/gpu/drm/i915/display/intel_hdmi.c | 6 ++
3 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index ff6126ea793c..834bf1d43bb8 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -864,6 +864,13 @@ intel_crt_detect(struct drm_connector *connector,
out:
intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
+
+ /*
+* Make sure the refs for power wells enabled during detect are
+* dropped to avoid a new detect cycle triggered by HPD polling.
+*/
+ intel_display_power_flush_work(dev_priv);
+
return status;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 86989ec25bc6..486fe203f56c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5688,6 +5688,12 @@ intel_dp_detect(struct drm_connector *connector,
if (status != connector_status_connected && !intel_dp->is_mst)
intel_dp_unset_edid(intel_dp);
+ /*
+* Make sure the refs for power wells enabled during detect are
+* dropped to avoid a new detect cycle triggered by HPD polling.
+*/
+ intel_display_power_flush_work(dev_priv);
+
return status;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b54ccbb5aad5..ff71a4da3d00 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2626,6 +2626,12 @@ intel_hdmi_detect(struct drm_connector *connector, bool
force)
if (status != connector_status_connected)
cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
+ /*
+* Make sure the refs for power wells enabled during detect are
+* dropped to avoid a new detect cycle triggered by HPD polling.
+*/
+ intel_display_power_flush_work(dev_priv);
+
return status;
}
--
2.17.1
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Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC submission but enabled
> From: Ceraolo Spurio, Daniele
> Sent: Monday, October 28, 2019 9:44 AM
> To: Hiatt, Don ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC
> submission but enabled
>
>
>
> On 10/24/19 9:29 AM, don.hi...@intel.com wrote:
> > From: Don Hiatt
> >
> > Check to see if GuC submission is enabled before requesting the
> > EXIT_S_STATE action.
> >
>
> You're only skipping the resume, but does it make any sense to do the
> suspend action if we're not going to call the resume one? Does guc do
> anything in the suspend action that we still require? I thought it only
> saved the submission status, which we don't care about if guc submission
> is disabled.
>
> Daniele
>
Hi Daniele,
I tried skipping the suspend all together but then the HuC gets timeouts
waiting for the GuC to acknowledge the authentication request which leads to a
wedged GPU. ☹
BTW, I made a typo in the patch, should be 'drm/i915' not '914', I'll fix that
up.
Thanks,
don
> > On some platforms (e.g. KBL) that do not support GuC submission, but
> > the user enabled the GuC communication (e.g for HuC authentication)
> > calling the GuC EXIT_S_STATE action results in lose of ability to
> > enter RC6. Guard against this by only requesting the GuC action on
> > platforms that support GuC submission.
> >
> > I've verfied that intel_guc_resume() only gets called when driver
> > is loaded with: guc_enable={1,2,3}, all other cases (no args,
> > guc_enable={0,-1} the intel_guc_resume() is not called.
> >
> > Signed-off-by: Don Hiatt
> > ---
> > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 5 -
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > index 37f7bcbf7dac..33318ed135c0 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > @@ -565,7 +565,10 @@ int intel_guc_resume(struct intel_guc *guc)
> > GUC_POWER_D0,
> > };
> >
> > - return intel_guc_send(guc, action, ARRAY_SIZE(action));
> > + if (guc->submission_supported)
> > + return intel_guc_send(guc, action, ARRAY_SIZE(action));
> > +
> > + return 0;
> > }
> >
> > /**
> >
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Re: [Intel-gfx] [PATCH] drm/i915: Avoid HPD poll detect triggering a new detect cycle
On Mon, Oct 28, 2019 at 07:45:09PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 28, 2019 at 01:00:31PM +0200, Imre Deak wrote:
> > For the HPD interrupt functionality the HW depends on power wells in the
> > display core domain to be on. Accordingly when enabling these power
> > wells the HPD polling logic will force an HPD detection cycle to account
> > for hotplug events that may have happened when such a power well was
> > off.
> >
> > Thus a detect cycle started by polling could start a new detect cycle if
> > a power well in the display core domain gets enabled during detect and
> > stays enabled after detect completes. That in turn can lead to a
> > detection cycle runaway.
> >
> > To prevent re-triggering a poll-detect cycle make sure we drop all power
> > references we acquired during detect synchronously by the end of detect.
> > This will let the poll-detect logic continue with polling (matching the
> > off state of the corresponding power wells) instead of scheduling a new
> > detection cycle.
> >
> > Fixes: 6cfe7ec02e85 ("drm/i915: Remove the unneeded AUX power ref from
> > intel_dp_detect()")
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112125
> > Reported-by: Val Kulkov
> > Reported-and-tested-by: wangqr < wqr@gmail.com>
> > Cc: Val Kulkov
> > Cc: wangqr < wqr@gmail.com>
> > Cc: Ville Syrjälä
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_crt.c | 7 +++
> > drivers/gpu/drm/i915/display/intel_dp.c | 24 ++-
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 6 ++
> > 3 files changed, 28 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> > b/drivers/gpu/drm/i915/display/intel_crt.c
> > index ff6126ea793c..834bf1d43bb8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> > @@ -864,6 +864,13 @@ intel_crt_detect(struct drm_connector *connector,
> >
> > out:
> > intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
> > +
> > + /*
> > +* Make sure the refs for power wells enabled during detect are
> > +* dropped to avoid a new detect cycle triggered by HPD polling.
> > +*/
> > + intel_display_power_flush_work(dev_priv);
> > +
> > return status;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 86989ec25bc6..f4e0ec05d7c9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -5600,6 +5600,7 @@ intel_dp_detect(struct drm_connector *connector,
> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > struct intel_encoder *encoder = _port->base;
> > enum drm_connector_status status;
> > + int err = 0;
> >
> > DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
> > connector->base.id, connector->name);
> > @@ -5626,7 +5627,7 @@ intel_dp_detect(struct drm_connector *connector,
> > intel_dp->is_mst);
> > }
> >
> > - goto out;
> > + goto out_update_edid;
> > }
> >
> > if (intel_dp->reset_link_params) {
> > @@ -5654,7 +5655,7 @@ intel_dp_detect(struct drm_connector *connector,
> > * with EDID on it
> > */
> > status = connector_status_disconnected;
> > - goto out;
> > + goto out_update_edid;
> > }
> >
> > /*
> > @@ -5662,11 +5663,9 @@ intel_dp_detect(struct drm_connector *connector,
> > * with an IRQ_HPD, so force a link status check.
> > */
> > if (!intel_dp_is_edp(intel_dp)) {
> > - int ret;
> > -
> > - ret = intel_dp_retrain_link(encoder, ctx);
> > - if (ret)
> > - return ret;
> > + err = intel_dp_retrain_link(encoder, ctx);
> > + if (err)
>
> This should probably read
> if (err == -EDEADLK)
>
> Also I don't think we need to change this to a goto since it just
> means we're going to retry the whole thing again, so the straight
> return should be fine.
Ok, will resend it keeping this as-is. The retry will be done without
dropping mode_config.mutex, so keeping the power refs in that case
shouldn't cause a problem.
>
> > + goto out_sync_power;
> > }
> >
> > /*
> > @@ -5684,11 +5683,18 @@ intel_dp_detect(struct drm_connector *connector,
> >
> > intel_dp_check_service_irq(intel_dp);
> >
> > -out:
> > +out_update_edid:
> > if (status != connector_status_connected && !intel_dp->is_mst)
> > intel_dp_unset_edid(intel_dp);
> >
> > - return status;
> > +out_sync_power:
> > + /*
> > +* Make sure the refs for power wells enabled during detect are
> > +* dropped to avoid a new detect cycle triggered by HPD polling.
> > +*/
> > + intel_display_power_flush_work(dev_priv);
> > +
> > + return err ?
Re: [Intel-gfx] [PATCH] drm/i915/tgl: add support to one DP-MST stream
On Mon, Oct 28, 2019 at 10:04:57AM -0700, Lucas De Marchi wrote:
> This is the minimum change to support 1 (and only 1) DP-MST monitor
> connected on Tiger Lake. This change was isolated from previous patch
> from José. In order to support more streams we will need to create a
> master-slave relation on the transcoders and that is currently not
> working yet.
>
> Cc: José Roberto de Souza
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 281594bcbfae..32d9c74c5838 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1905,6 +1905,10 @@ intel_ddi_transcoder_func_reg_val_get(const struct
> intel_crtc_state *crtc_state)
> } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
> temp |= TRANS_DDI_MODE_SELECT_DP_MST;
> temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> +
> + if (INTEL_GEN(dev_priv) >= 12)
> + temp |= TRANS_DDI_MST_TRANSPORT_SELECT(
> + crtc_state->cpu_transcoder);
> } else {
> temp |= TRANS_DDI_MODE_SELECT_DP_SST;
> temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dee3168efd86..e08c4ea3b747 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9550,6 +9550,9 @@ enum skl_power_gate {
> #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
> #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
> #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
> +#define TRANS_DDI_MST_TRANSPORT_SELECT_SHIFT10
unused.
> +#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(12, 10)
> +#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) ((trans) << 10)
I guess this should be REG_FIELD_PREP() if you want to be modern (as
your REG_GENMASK() usage suggests).
> #define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
> #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
> #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
> --
> 2.23.0
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
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Intel
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: Initialise ret
== Series Details == Series: series starting with [1/2] drm/i915/selftests: Initialise ret URL : https://patchwork.freedesktop.org/series/68662/ State : warning == Summary == $ dim checkpatch origin/drm-tip a204f00d5275 drm/i915/selftests: Initialise ret -:8: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #8: drivers/gpu/drm/i915//gem/selftests/i915_gem_context.c:1268 __igt_ctx_sseu() error: uninitialized symbol 'ret'. total: 0 errors, 1 warnings, 0 checks, 8 lines checked b2538d08bab1 drm/i915/display: Mark conn as initialised by iterator -:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #7: drivers/gpu/drm/i915//display/intel_display.c:14403 intel_set_dp_tp_ctl_normal() error: uninitialized symbol 'conn'. -:22: WARNING:FUNCTION_ARGUMENTS: function definition argument 'conn' should also have an identifier name #22: FILE: drivers/gpu/drm/i915/display/intel_display.c:14394: + struct drm_connector *uninitialized_var(conn); total: 0 errors, 2 warnings, 0 checks, 9 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Simply walk back along request timeline on reset (rev6)
== Series Details ==
Series: drm/i915/execlists: Simply walk back along request timeline on reset
(rev6)
URL : https://patchwork.freedesktop.org/series/68601/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7203 -> Patchwork_15023
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/index.html
Known issues
Here are the changes found in Patchwork_15023 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-kbl-r: [PASS][1] -> [INCOMPLETE][2] ([fdo#112002])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/fi-kbl-r/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/fi-kbl-r/igt@gem_exec_susp...@basic-s3.html
* igt@gem_flink_basic@flink-lifetime:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][5] -> [DMESG-WARN][6] ([fdo#102614])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
* igt@i915_selftest@live_blt:
- fi-hsw-peppy: [DMESG-FAIL][9] ([fdo#112147]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/fi-hsw-peppy/igt@i915_selftest@live_blt.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/fi-hsw-peppy/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_hangcheck:
- {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111747]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/fi-tgl-u/igt@i915_selftest@live_hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/fi-tgl-u/igt@i915_selftest@live_hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#112002]: https://bugs.freedesktop.org/show_bug.cgi?id=112002
[fdo#112147]: https://bugs.freedesktop.org/show_bug.cgi?id=112147
Participating hosts (52 -> 41)
--
Missing(11): fi-kbl-soraka fi-ilk-m540 fi-bsw-n3050 fi-hsw-4200u
fi-byt-squawks fi-bsw-cyan fi-kbl-7500u fi-icl-y fi-tgl-y fi-byt-clapper
fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7203 -> Patchwork_15023
CI-20190529: 20190529
CI_DRM_7203: 912b87256ca0b04ed5f73682068bf6062dd93e6d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5248: 81e55f1f97d73e48f00caa7e4fb98295023c5afa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15023: d2e8420ff470cd3639ddecb509010f3f979765bf @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d2e8420ff470 drm/i915/execlists: Simply walk back along request timeline on
reset
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/index.html
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for sna/video/overlay: Declare support for depth 8 and 30
== Series Details == Series: sna/video/overlay: Declare support for depth 8 and 30 URL : https://patchwork.freedesktop.org/series/68655/ State : failure == Summary == Applying: sna/video/overlay: Declare support for depth 8 and 30 error: sha1 information is lacking or useless (src/sna/sna_video_overlay.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 sna/video/overlay: Declare support for depth 8 and 30 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Avoid HPD poll detect triggering a new detect cycle
On Mon, Oct 28, 2019 at 01:00:31PM +0200, Imre Deak wrote:
> For the HPD interrupt functionality the HW depends on power wells in the
> display core domain to be on. Accordingly when enabling these power
> wells the HPD polling logic will force an HPD detection cycle to account
> for hotplug events that may have happened when such a power well was
> off.
>
> Thus a detect cycle started by polling could start a new detect cycle if
> a power well in the display core domain gets enabled during detect and
> stays enabled after detect completes. That in turn can lead to a
> detection cycle runaway.
>
> To prevent re-triggering a poll-detect cycle make sure we drop all power
> references we acquired during detect synchronously by the end of detect.
> This will let the poll-detect logic continue with polling (matching the
> off state of the corresponding power wells) instead of scheduling a new
> detection cycle.
>
> Fixes: 6cfe7ec02e85 ("drm/i915: Remove the unneeded AUX power ref from
> intel_dp_detect()")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112125
> Reported-by: Val Kulkov
> Reported-and-tested-by: wangqr < wqr@gmail.com>
> Cc: Val Kulkov
> Cc: wangqr < wqr@gmail.com>
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_crt.c | 7 +++
> drivers/gpu/drm/i915/display/intel_dp.c | 24 ++-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 6 ++
> 3 files changed, 28 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index ff6126ea793c..834bf1d43bb8 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -864,6 +864,13 @@ intel_crt_detect(struct drm_connector *connector,
>
> out:
> intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
> +
> + /*
> + * Make sure the refs for power wells enabled during detect are
> + * dropped to avoid a new detect cycle triggered by HPD polling.
> + */
> + intel_display_power_flush_work(dev_priv);
> +
> return status;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 86989ec25bc6..f4e0ec05d7c9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5600,6 +5600,7 @@ intel_dp_detect(struct drm_connector *connector,
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct intel_encoder *encoder = _port->base;
> enum drm_connector_status status;
> + int err = 0;
>
> DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
> connector->base.id, connector->name);
> @@ -5626,7 +5627,7 @@ intel_dp_detect(struct drm_connector *connector,
> intel_dp->is_mst);
> }
>
> - goto out;
> + goto out_update_edid;
> }
>
> if (intel_dp->reset_link_params) {
> @@ -5654,7 +5655,7 @@ intel_dp_detect(struct drm_connector *connector,
>* with EDID on it
>*/
> status = connector_status_disconnected;
> - goto out;
> + goto out_update_edid;
> }
>
> /*
> @@ -5662,11 +5663,9 @@ intel_dp_detect(struct drm_connector *connector,
>* with an IRQ_HPD, so force a link status check.
>*/
> if (!intel_dp_is_edp(intel_dp)) {
> - int ret;
> -
> - ret = intel_dp_retrain_link(encoder, ctx);
> - if (ret)
> - return ret;
> + err = intel_dp_retrain_link(encoder, ctx);
> + if (err)
This should probably read
if (err == -EDEADLK)
Also I don't think we need to change this to a goto since it just
means we're going to retry the whole thing again, so the straight
return should be fine.
> + goto out_sync_power;
> }
>
> /*
> @@ -5684,11 +5683,18 @@ intel_dp_detect(struct drm_connector *connector,
>
> intel_dp_check_service_irq(intel_dp);
>
> -out:
> +out_update_edid:
> if (status != connector_status_connected && !intel_dp->is_mst)
> intel_dp_unset_edid(intel_dp);
>
> - return status;
> +out_sync_power:
> + /*
> + * Make sure the refs for power wells enabled during detect are
> + * dropped to avoid a new detect cycle triggered by HPD polling.
> + */
> + intel_display_power_flush_work(dev_priv);
> +
> + return err ? err : status;
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index b54ccbb5aad5..ff71a4da3d00 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2626,6 +2626,12 @@ intel_hdmi_detect(struct drm_connector *connector,
> bool force)
>
Re: [Intel-gfx] [PATCH] drm/i915/blt: fixup block_size rounding
Quoting Ville Syrjälä (2019-10-28 16:46:46) > On Mon, Oct 28, 2019 at 04:39:50PM +, Matthew Auld wrote: > > There is nothing to say that the obj->base.size is actually a multiple > > of the block_size. > > > > Reported-by: Chris Wilson > > Signed-off-by: Matthew Auld > > Cc: Chris Wilson > > --- > > drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > > b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > > index 516e61e99212..5597f1345a63 100644 > > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > > @@ -30,7 +30,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct > > intel_context *ce, > > GEM_BUG_ON(intel_engine_is_virtual(ce->engine)); > > intel_engine_pm_get(ce->engine); > > > > - count = div_u64(vma->size, block_size); > > + count = DIV64_U64_ROUND_UP(vma->size, block_size); > > block_size size look to be u32? And we can control it to be a pot. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Avoid HPD poll detect triggering a new detect cycle
On Mon, 28 Oct 2019 at 07:02, Imre Deak wrote:
>
> For the HPD interrupt functionality the HW depends on power wells in the
> display core domain to be on. Accordingly when enabling these power
> wells the HPD polling logic will force an HPD detection cycle to account
> for hotplug events that may have happened when such a power well was
> off.
>
> Thus a detect cycle started by polling could start a new detect cycle if
> a power well in the display core domain gets enabled during detect and
> stays enabled after detect completes. That in turn can lead to a
> detection cycle runaway.
>
> To prevent re-triggering a poll-detect cycle make sure we drop all power
> references we acquired during detect synchronously by the end of detect.
> This will let the poll-detect logic continue with polling (matching the
> off state of the corresponding power wells) instead of scheduling a new
> detection cycle.
>
> Fixes: 6cfe7ec02e85 ("drm/i915: Remove the unneeded AUX power ref from
> intel_dp_detect()")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112125
> Reported-by: Val Kulkov
> Reported-and-tested-by: wangqr < wqr@gmail.com>
> Cc: Val Kulkov
> Cc: wangqr < wqr@gmail.com>
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
The patch has been tested with linux-drm-tip-git
5.4.865162.dd5bccfa3b5d-1 on Eglobal NUC Fanless Mini PC Intel N3150
and Intel NUC D34010WYK. In both cases, the reported problem was no
longer observed.
Tested-by: Val Kulkov
___
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Re: [Intel-gfx] [PATCH] drm/i915/tgl: add support to one DP-MST stream
On Mon, 2019-10-28 at 10:04 -0700, Lucas De Marchi wrote:
> This is the minimum change to support 1 (and only 1) DP-MST monitor
> connected on Tiger Lake. This change was isolated from previous patch
> from José. In order to support more streams we will need to create a
> master-slave relation on the transcoders and that is currently not
> working yet.
Reviewed-by: José Roberto de Souza
>
> Cc: José Roberto de Souza
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 281594bcbfae..32d9c74c5838 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1905,6 +1905,10 @@ intel_ddi_transcoder_func_reg_val_get(const
> struct intel_crtc_state *crtc_state)
> } else if (intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_DP_MST)) {
> temp |= TRANS_DDI_MODE_SELECT_DP_MST;
> temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> +
> + if (INTEL_GEN(dev_priv) >= 12)
> + temp |= TRANS_DDI_MST_TRANSPORT_SELECT(
> + crtc_state->cpu_transcoder);
> } else {
> temp |= TRANS_DDI_MODE_SELECT_DP_SST;
> temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index dee3168efd86..e08c4ea3b747 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9550,6 +9550,9 @@ enum skl_power_gate {
> #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
> #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
> #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
> +#define TRANS_DDI_MST_TRANSPORT_SELECT_SHIFT10
> +#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(12, 10)
> +#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) ((trans) << 10)
> #define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
> #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
> #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Put future HW and their uAPIs under STAGING & BROKEN
== Series Details ==
Series: drm/i915: Put future HW and their uAPIs under STAGING & BROKEN
URL : https://patchwork.freedesktop.org/series/68612/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7194_full -> Patchwork_15012_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_15012_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge:
- {shard-tglb}: [PASS][1] -> [INCOMPLETE][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-tglb6/igt@kms_cursor_edge_w...@pipe-b-128x128-left-edge.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15012/shard-tglb5/igt@kms_cursor_edge_w...@pipe-b-128x128-left-edge.html
* igt@kms_universal_plane@universal-plane-pipe-a-functional:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15012/shard-tglb4/igt@kms_universal_pl...@universal-plane-pipe-a-functional.html
Known issues
Here are the changes found in Patchwork_15012_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_exec@basic-invalid-context-vcs1:
- shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#112080]) +4 similar
issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-iclb4/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15012/shard-iclb8/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#109276] / [fdo#112080])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-iclb4/igt@gem_ctx_isolat...@vcs1-dirty-create.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15012/shard-iclb8/igt@gem_ctx_isolat...@vcs1-dirty-create.html
* igt@gem_exec_schedule@out-order-bsd:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#112146]) +1 similar issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-iclb3/igt@gem_exec_sched...@out-order-bsd.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15012/shard-iclb1/igt@gem_exec_sched...@out-order-bsd.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276]) +8 similar
issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-iclb2/igt@gem_exec_sched...@promotion-bsd1.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15012/shard-iclb3/igt@gem_exec_sched...@promotion-bsd1.html
* igt@gem_persistent_relocs@forked-faulting-reloc-thrashing:
- shard-iclb: [PASS][12] -> [TIMEOUT][13] ([fdo#112068 ])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-iclb5/igt@gem_persistent_rel...@forked-faulting-reloc-thrashing.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15012/shard-iclb3/igt@gem_persistent_rel...@forked-faulting-reloc-thrashing.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-iclb: [PASS][14] -> [FAIL][15] ([fdo#112037])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-iclb5/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15012/shard-iclb7/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-snb: [PASS][16] -> [DMESG-WARN][17] ([fdo#111870]) +1
similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-snb2/igt@gem_userptr_bl...@dmabuf-sync.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15012/shard-snb6/igt@gem_userptr_bl...@dmabuf-sync.html
- shard-hsw: [PASS][18] -> [DMESG-WARN][19] ([fdo#111870])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-hsw2/igt@gem_userptr_bl...@dmabuf-sync.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15012/shard-hsw5/igt@gem_userptr_bl...@dmabuf-sync.html
* igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge:
- shard-apl: [PASS][20] -> [INCOMPLETE][21] ([fdo#103927])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-apl2/igt@kms_cursor_edge_w...@pipe-c-64x64-left-edge.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15012/shard-apl8/igt@kms_cursor_edge_w...@pipe-c-64x64-left-edge.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][22] -> [FAIL][23] ([fdo#105363])
[22]:
Re: [Intel-gfx] [PATCH RESEND 8/8] drm/print: introduce new struct drm_device based logging macros
On Mon, Oct 28, 2019 at 12:38:22PM +0200, Jani Nikula wrote: > Add new struct drm_device based logging macros modeled after the core > kernel device based logging macros. These would be preferred over the > drm printk and struct device based macros in drm code, where possible. > > We have existing drm specific struct device based logging functions, but > they are too verbose to use for two main reasons: > > * The names are unnecessarily long, for example DRM_DEV_DEBUG_KMS(). > > * The use of struct device over struct drm_device is too generic for >most users, leading to an extra dereference. > > For example: > > DRM_DEV_DEBUG_KMS(drm->dev, "Hello, world\n"); > > vs. > > drm_dbg_kms(drm, "Hello, world\n"); > > It's a matter of taste, but the SHOUTING UPPERCASE has been argued to be > less readable than lowercase. > > Some names are changed from old DRM names to be based on the core kernel > logging functions. For example, NOTE -> notice, ERROR -> err, DEBUG -> > dbg. > > Due to the conflation of DRM_DEBUG and DRM_DEBUG_DRIVER macro use > (DRM_DEBUG is used widely in drivers though it's supposed to be a core > debugging category), they are named as drm_dbg_core and drm_dbg, > respectively. > > The drm_err and _once/_ratelimited variants no longer include the > function name in order to be able to use the core device based logging > macros. Arguably this is not a significant change; error messages should > not be so common to be only distinguishable by the function name. > > Ratelimited debug logging macros are to be added later. > > Cc: Sam Ravnborg > Signed-off-by: Jani Nikula > > --- > > With something like this, I think i915 could start migrating to > drm_device based logging. I have a hard time convincing myself or anyone > about migrating to the DRM_DEV_* variants. Looks reasonable enough to me. For the series Acked-by: Ville Syrjälä One thing that still bugs me about drm_dbg() is that the category check is inside it. So we pay the function call overhead for every debug statement even when debugging is disabled. So I'd also like to see a patch moving the category check back into the macros/static inline (IIRC it was there originally). > --- > include/drm/drm_print.h | 65 + > 1 file changed, 65 insertions(+) > > diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h > index 085a9685270c..e4040dea0d8c 100644 > --- a/include/drm/drm_print.h > +++ b/include/drm/drm_print.h > @@ -322,6 +322,8 @@ static inline bool drm_debug_enabled(enum > drm_debug_category category) > > /* > * struct device based logging > + * > + * Prefer drm_device based logging over device or prink based logging. > */ > > __printf(3, 4) > @@ -417,8 +419,71 @@ void drm_dev_dbg(const struct device *dev, enum > drm_debug_category category, > _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, DRM_UT_PRIME,\ > fmt, ##__VA_ARGS__) > > +/* > + * struct drm_device based logging > + * > + * Prefer drm_device based logging over device or prink based logging. > + */ > + > +/* Helper for struct drm_device based logging. */ > +#define __drm_printk(drm, level, type, fmt, ...) \ > + dev_##level##type(drm->dev, "[drm] " fmt, ##__VA_ARGS__) > + > + > +#define drm_info(drm, fmt, ...) \ > + __drm_printk(drm, info,, fmt, ##__VA_ARGS__) > + > +#define drm_notice(drm, fmt, ...)\ > + __drm_printk(drm, notice,, fmt, ##__VA_ARGS__) > + > +#define drm_warn(drm, fmt, ...) \ > + __drm_printk(drm, warn,, fmt, ##__VA_ARGS__) > + > +#define drm_err(drm, fmt, ...) \ > + __drm_printk(drm, err,, "*ERROR* " fmt, ##__VA_ARGS__) > + > + > +#define drm_info_once(drm, fmt, ...) \ > + __drm_printk(drm, info, _once, fmt, ##__VA_ARGS__) > + > +#define drm_notice_once(drm, fmt, ...) \ > + __drm_printk(drm, notice, _once, fmt, ##__VA_ARGS__) > + > +#define drm_warn_once(drm, fmt, ...) \ > + __drm_printk(drm, warn, _once, fmt, ##__VA_ARGS__) > + > +#define drm_err_once(drm, fmt, ...) \ > + __drm_printk(drm, err, _once, "*ERROR* " fmt, ##__VA_ARGS__) > + > + > +#define drm_err_ratelimited(drm, fmt, ...) \ > + __drm_printk(drm, err, _ratelimited, "*ERROR* " fmt, ##__VA_ARGS__) > + > + > +#define drm_dbg_core(drm, fmt, ...) \ > + drm_dev_dbg(drm->dev, DRM_UT_CORE, fmt, ##__VA_ARGS__) > +#define drm_dbg(drm, fmt, ...) > \ > + drm_dev_dbg(drm->dev, DRM_UT_DRIVER, fmt, ##__VA_ARGS__) > +#define drm_dbg_kms(drm, fmt, ...) \ > + drm_dev_dbg(drm->dev, DRM_UT_KMS, fmt, ##__VA_ARGS__) > +#define
[Intel-gfx] [PATCH] drm/i915/tgl: add support to one DP-MST stream
This is the minimum change to support 1 (and only 1) DP-MST monitor
connected on Tiger Lake. This change was isolated from previous patch
from José. In order to support more streams we will need to create a
master-slave relation on the transcoders and that is currently not
working yet.
Cc: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 281594bcbfae..32d9c74c5838 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1905,6 +1905,10 @@ intel_ddi_transcoder_func_reg_val_get(const struct
intel_crtc_state *crtc_state)
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
temp |= TRANS_DDI_MODE_SELECT_DP_MST;
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ temp |= TRANS_DDI_MST_TRANSPORT_SELECT(
+ crtc_state->cpu_transcoder);
} else {
temp |= TRANS_DDI_MODE_SELECT_DP_SST;
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dee3168efd86..e08c4ea3b747 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9550,6 +9550,9 @@ enum skl_power_gate {
#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
+#define TRANS_DDI_MST_TRANSPORT_SELECT_SHIFT 10
+#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(12, 10)
+#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) ((trans) << 10)
#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
--
2.23.0
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Re: [Intel-gfx] [PATCH] drm/i915/blt: fixup block_size rounding
On Mon, Oct 28, 2019 at 04:39:50PM +, Matthew Auld wrote: > There is nothing to say that the obj->base.size is actually a multiple > of the block_size. > > Reported-by: Chris Wilson > Signed-off-by: Matthew Auld > Cc: Chris Wilson > --- > drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > index 516e61e99212..5597f1345a63 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > @@ -30,7 +30,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct > intel_context *ce, > GEM_BUG_ON(intel_engine_is_virtual(ce->engine)); > intel_engine_pm_get(ce->engine); > > - count = div_u64(vma->size, block_size); > + count = DIV64_U64_ROUND_UP(vma->size, block_size); block_size size look to be u32? > size = (1 + 8 * count) * sizeof(u32); > size = round_up(size, PAGE_SIZE); > pool = intel_engine_get_pool(ce->engine, size); > @@ -214,7 +214,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct > intel_context *ce, > GEM_BUG_ON(intel_engine_is_virtual(ce->engine)); > intel_engine_pm_get(ce->engine); > > - count = div_u64(dst->size, block_size); > + count = DIV64_U64_ROUND_UP(dst->size, block_size); > size = (1 + 11 * count) * sizeof(u32); > size = round_up(size, PAGE_SIZE); > pool = intel_engine_get_pool(ce->engine, size); > -- > 2.20.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/execlists: Use vfunc to check engine submission mode
While processing CSB there is no need to look at GuC submission
settings, just check if engine is configured for execlists mode.
While today GuC submission is disabled it's settings are still
based on modparam values that might not correctly reflect actual
submission status in case of any fallback. Until that is fully
fixed, use alternate method to confirm that engine really runs in
execlists mode by comparing set_default_submission vfunc.
v2: add other immediate use of new helper
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Janusz Krzysztofik
Reviewed-by: Janusz Krzysztofik
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 8 +++-
drivers/gpu/drm/i915/gt/intel_lrc.h | 2 ++
drivers/gpu/drm/i915/i915_perf.c| 10 +-
3 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 16340740139d..c0d564b28beb 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2022,7 +2022,7 @@ static void process_csb(struct intel_engine_cs *engine)
*/
GEM_BUG_ON(!tasklet_is_locked(>tasklet) &&
!reset_in_progress(execlists));
- GEM_BUG_ON(USES_GUC_SUBMISSION(engine->i915));
+ GEM_BUG_ON(!intel_engine_in_execlists_submission_mode(engine));
/*
* Note that csb_write, csb_status may be either in HWSP or mmio.
@@ -4711,6 +4711,12 @@ void intel_lr_context_reset(struct intel_engine_cs
*engine,
__execlists_update_reg_state(ce, engine);
}
+bool intel_engine_in_execlists_submission_mode(struct intel_engine_cs *engine)
+{
+ return engine->set_default_submission ==
+ intel_execlists_set_default_submission;
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_lrc.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h
b/drivers/gpu/drm/i915/gt/intel_lrc.h
index 99dc576a4e25..23dde9083349 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -145,4 +145,6 @@ struct intel_engine_cs *
intel_virtual_engine_get_sibling(struct intel_engine_cs *engine,
unsigned int sibling);
+bool intel_engine_in_execlists_submission_mode(struct intel_engine_cs *engine);
+
#endif /* _INTEL_LRC_H_ */
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 38d3de2dfaa6..a807b6f0dfa3 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1261,7 +1261,11 @@ static int oa_get_render_ctx_id(struct i915_perf_stream
*stream)
case 8:
case 9:
case 10:
- if (USES_GUC_SUBMISSION(ce->engine->i915)) {
+ if (intel_engine_in_execlists_submission_mode(ce->engine)) {
+ stream->specific_ctx_id_mask =
+ (1U << GEN8_CTX_ID_WIDTH) - 1;
+ stream->specific_ctx_id = stream->specific_ctx_id_mask;
+ } else {
/*
* When using GuC, the context descriptor we write in
* i915 is read by GuC and rewritten before it's
@@ -1281,10 +1285,6 @@ static int oa_get_render_ctx_id(struct i915_perf_stream
*stream)
*/
stream->specific_ctx_id_mask =
(1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
- } else {
- stream->specific_ctx_id_mask =
- (1U << GEN8_CTX_ID_WIDTH) - 1;
- stream->specific_ctx_id = stream->specific_ctx_id_mask;
}
break;
--
2.19.2
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Re: [Intel-gfx] [PATCH] drm/i914/guc: Fix resume on platforms w/o GuC submission but enabled
On 10/24/19 9:29 AM, don.hi...@intel.com wrote:
From: Don Hiatt
Check to see if GuC submission is enabled before requesting the
EXIT_S_STATE action.
You're only skipping the resume, but does it make any sense to do the
suspend action if we're not going to call the resume one? Does guc do
anything in the suspend action that we still require? I thought it only
saved the submission status, which we don't care about if guc submission
is disabled.
Daniele
On some platforms (e.g. KBL) that do not support GuC submission, but
the user enabled the GuC communication (e.g for HuC authentication)
calling the GuC EXIT_S_STATE action results in lose of ability to
enter RC6. Guard against this by only requesting the GuC action on
platforms that support GuC submission.
I've verfied that intel_guc_resume() only gets called when driver
is loaded with: guc_enable={1,2,3}, all other cases (no args,
guc_enable={0,-1} the intel_guc_resume() is not called.
Signed-off-by: Don Hiatt
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 37f7bcbf7dac..33318ed135c0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -565,7 +565,10 @@ int intel_guc_resume(struct intel_guc *guc)
GUC_POWER_D0,
};
- return intel_guc_send(guc, action, ARRAY_SIZE(action));
+ if (guc->submission_supported)
+ return intel_guc_send(guc, action, ARRAY_SIZE(action));
+
+ return 0;
}
/**
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Re: [Intel-gfx] [PATCH 4/5] drm/i915: Provide more information on DP AUX failures
On Fri, Oct 25, 2019 at 04:06:22PM -0700, Matt Roper wrote:
> We're seeing some failures where an aux transaction still shows as
> 'busy' well after the timeout limit that the hardware is supposed to
> enforce. Improve the error message so that we can see exactly which aux
> channel this error happened on and what the status bits were during this
> case that isn't supposed to happen.
Pretty sure I have a patch somewhere that adds the aux name
to all the messages. I should probably dig that up and post it.
>
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 65bab46f7b43..2b4915b5cf52 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1190,7 +1190,8 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
> trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
>
> if (!done)
> - DRM_ERROR("dp aux hw did not signal timeout!\n");
> + DRM_ERROR("%s did not complete or timeout within 10ms (status
> 0x%08x)\n",
> + intel_dp->aux.name ?: "AUX", status);
> #undef C
>
> return status;
> --
> 2.21.0
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Intel
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Re: [Intel-gfx] [PATCH] drm/i915/gem: Limit the blitter sizes to ensure low preemption latency
On Fri, 25 Oct 2019 at 22:06, Chris Wilson wrote:
>
> Currently we insert a arbitration point every 128MiB during a blitter
> copy. At 8GiB/s, this is around 30ms. This is a little on the large side
> if we need to inject a high priority work, so reduced it down to 8MiB or
> roughly 1ms.
>
> Signed-off-by: Chris Wilson
> Cc: Matthew Auld
> ---
> Ok, I need to do a selftest to ensure we are exceeding the estimated
> blitter throughtput, and I would also like a test to measure the
> preemption latency directly. Remind me!
> ---
> drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> index 516e61e99212..7e25f05939bc 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
> @@ -17,7 +17,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct
> intel_context *ce,
> u32 value)
> {
> struct drm_i915_private *i915 = ce->vm->i915;
> - const u32 block_size = S16_MAX * PAGE_SIZE;
> + const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */
Also update the copy?
Not sure if this will need more tuning.
Reviewed-by: Matthew Auld
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[Intel-gfx] [PATCH] drm/i915/blt: fixup block_size rounding
There is nothing to say that the obj->base.size is actually a multiple of the block_size. Reported-by: Chris Wilson Signed-off-by: Matthew Auld Cc: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c index 516e61e99212..5597f1345a63 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c @@ -30,7 +30,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, GEM_BUG_ON(intel_engine_is_virtual(ce->engine)); intel_engine_pm_get(ce->engine); - count = div_u64(vma->size, block_size); + count = DIV64_U64_ROUND_UP(vma->size, block_size); size = (1 + 8 * count) * sizeof(u32); size = round_up(size, PAGE_SIZE); pool = intel_engine_get_pool(ce->engine, size); @@ -214,7 +214,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, GEM_BUG_ON(intel_engine_is_virtual(ce->engine)); intel_engine_pm_get(ce->engine); - count = div_u64(dst->size, block_size); + count = DIV64_U64_ROUND_UP(dst->size, block_size); size = (1 + 11 * count) * sizeof(u32); size = round_up(size, PAGE_SIZE); pool = intel_engine_get_pool(ce->engine, size); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Check a few more fixed locations within the context image
== Series Details ==
Series: drm/i915/selftests: Check a few more fixed locations within the context
image
URL : https://patchwork.freedesktop.org/series/68611/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7194_full -> Patchwork_15011_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_15011_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_cursor_crc@pipe-d-cursor-64x64-offscreen}:
- {shard-tglb}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-tglb4/igt@kms_cursor_...@pipe-d-cursor-64x64-offscreen.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15011/shard-tglb3/igt@kms_cursor_...@pipe-d-cursor-64x64-offscreen.html
Known issues
Here are the changes found in Patchwork_15011_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_exec@basic-invalid-context-vcs1:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112080]) +7 similar
issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-iclb4/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15011/shard-iclb5/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080])
+1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-iclb4/igt@gem_ctx_isolat...@vcs1-dirty-create.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15011/shard-iclb5/igt@gem_ctx_isolat...@vcs1-dirty-create.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110841])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15011/shard-iclb4/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@preempt-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +1 similar
issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-iclb6/igt@gem_exec_sched...@preempt-bsd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15011/shard-iclb2/igt@gem_exec_sched...@preempt-bsd.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +9 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-iclb2/igt@gem_exec_sched...@promotion-bsd1.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15011/shard-iclb6/igt@gem_exec_sched...@promotion-bsd1.html
* igt@gem_linear_blits@normal:
- shard-apl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927]) +2
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-apl3/igt@gem_linear_bl...@normal.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15011/shard-apl3/igt@gem_linear_bl...@normal.html
* igt@gem_softpin@noreloc-s3:
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-kbl3/igt@gem_soft...@noreloc-s3.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15011/shard-kbl2/igt@gem_soft...@noreloc-s3.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-snb: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-snb2/igt@gem_userptr_bl...@dmabuf-sync.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15011/shard-snb4/igt@gem_userptr_bl...@dmabuf-sync.html
* igt@kms_color@pipe-b-ctm-0-25:
- shard-skl: [PASS][19] -> [DMESG-WARN][20] ([fdo#106107])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-skl5/igt@kms_co...@pipe-b-ctm-0-25.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15011/shard-skl2/igt@kms_co...@pipe-b-ctm-0-25.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [PASS][21] -> [INCOMPLETE][22] ([fdo#110741])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-skl1/igt@kms_cursor_...@pipe-c-cursor-suspend.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15011/shard-skl8/igt@kms_cursor_...@pipe-c-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [PASS][23] -> [FAIL][24] ([fdo#105363])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-glk6/igt@kms_f...@flip-vs-expired-vblank.html
[24]:
Re: [Intel-gfx] [PATCH 1/6] drm/i915: Fix i845/i865 cursor width
Op 28-10-2019 om 16:05 schreef Ville Syrjälä:
> On Mon, Oct 28, 2019 at 03:20:34PM +0100, Maarten Lankhorst wrote:
>> Op 28-10-2019 om 12:30 schreef Ville Syrjala:
>>> From: Ville Syrjälä
>>>
>>> The change from the uapi coordinates to the internal coordinates
>>> broke the cursor on i845/i865 due to src and dst getting swapped.
>>> Fix it.
>>>
>>> Cc: Maarten Lankhorst
>>> Fixes: 3a612765f423 ("drm/i915: Remove cursor use of properties for
>>> coordinates")
>>> Signed-off-by: Ville Syrjälä
>>> ---
>>> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>>> b/drivers/gpu/drm/i915/display/intel_display.c
>>> index 0f0c582a56d5..47a3aef0fb61 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>> @@ -10947,7 +10947,7 @@ static void i845_update_cursor(struct intel_plane
>>> *plane,
>>> unsigned long irqflags;
>>>
>>> if (plane_state && plane_state->base.visible) {
>>> - unsigned int width = drm_rect_width(_state->base.src);
>>> + unsigned int width = drm_rect_width(_state->base.dst);
>>> unsigned int height = drm_rect_height(_state->base.dst);
>>>
>>> cntl = plane_state->ctl |
>> Yeah, I guess theoretically fixes, should be ok regardless because no
>> scaling is supported on the cursor so rectangles are identical. :)
> No. One is .16 fixed point other is integer. Ie. totally broken atm,
> as proven by the cursor being smeared over the whole screen on my i865.
>
Ah right, missed that. :)
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[Intel-gfx] [RFC PATCH i-g-t v3 4/4] tests/gem_ctx_shared: Calculate object attributs from actual page size
exec-shared-gtt-* subtests use hardcoded values for object size and softpin offset, based on 4kB page size assumption. That may result in those subtests failing when run on future backing stores with possibly larger minimum page sizes. Replace hardcoded constants with values derived from minimum page size of actual backing store the test is running on. Signed-off-by: Janusz Krzysztofik Cc: Chris Wilson --- tests/i915/gem_ctx_shared.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c index f7852482..d386de65 100644 --- a/tests/i915/gem_ctx_shared.c +++ b/tests/i915/gem_ctx_shared.c @@ -195,6 +195,7 @@ static void exec_shared_gtt(int i915, unsigned int ring) uint32_t scratch, *s; uint32_t batch, cs[16]; uint64_t offset; + uint64_t page_size; int i; gem_require_ring(i915, ring); @@ -203,7 +204,8 @@ static void exec_shared_gtt(int i915, unsigned int ring) clone = gem_context_clone(i915, 0, I915_CONTEXT_CLONE_VM, 0); /* Find a hole big enough for both objects later */ - scratch = gem_create(i915, 16384); + page_size = 1ull << gem_min_page_size_order(i915); + scratch = gem_create(i915, 4 * page_size); gem_write(i915, scratch, 0, , sizeof(bbe)); obj.handle = scratch; gem_execbuf(i915, ); @@ -246,7 +248,7 @@ static void exec_shared_gtt(int i915, unsigned int ring) gem_write(i915, batch, 0, cs, sizeof(cs)); obj.handle = batch; - obj.offset += 8192; /* make sure we don't cause an eviction! */ + obj.offset += 2 * page_size; /* make sure we don't cause an eviction! */ execbuf.rsvd1 = clone; if (gen > 3 && gen < 6) execbuf.flags |= I915_EXEC_SECURE; -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH i-g-t v3 1/4] lib: Move redundant local helpers to lib/
Two tests - gem_exec_reloc and gem_softpin - define local helpers for
calculation of softpin offset canonical addresses. As more users are
expected, replace those local instances with a single shared one under
lib/.
Signed-off-by: Janusz Krzysztofik
Cc: Chris Wilson
---
lib/igt_x86.c | 13 +
lib/igt_x86.h | 5 +
tests/i915/gem_exec_reloc.c | 16 +++-
tests/i915/gem_softpin.c| 13 +
4 files changed, 22 insertions(+), 25 deletions(-)
diff --git a/lib/igt_x86.c b/lib/igt_x86.c
index 6ac700df..13d7c6e5 100644
--- a/lib/igt_x86.c
+++ b/lib/igt_x86.c
@@ -190,6 +190,19 @@ char *igt_x86_features_to_string(unsigned features, char
*line)
}
#endif
+/**
+ * gen8_canonical_addr
+ * Used to convert any address into canonical form, i.e. [63:48] == [47].
+ * Based on kernel's sign_extend64 implementation.
+ * @address - a virtual address
+ */
+uint64_t gen8_canonical_addr(uint64_t address)
+{
+ int shift = 63 - GEN8_HIGH_ADDRESS_BIT;
+
+ return (int64_t)(address << shift) >> shift;
+}
+
#if defined(__x86_64__) && !defined(__clang__)
#pragma GCC push_options
#pragma GCC target("sse4.1")
diff --git a/lib/igt_x86.h b/lib/igt_x86.h
index c7b84dec..8c7eb5e8 100644
--- a/lib/igt_x86.h
+++ b/lib/igt_x86.h
@@ -30,6 +30,8 @@
#ifndef IGT_X86_H
#define IGT_X86_H
+#include
+
#define MMX0x1
#define SSE0x2
#define SSE2 0x4
@@ -56,6 +58,9 @@ static inline char *igt_x86_features_to_string(unsigned
features, char *line)
}
#endif
+#define GEN8_HIGH_ADDRESS_BIT 47
+uint64_t gen8_canonical_addr(uint64_t address);
+
void igt_memcpy_from_wc(void *dst, const void *src, unsigned long len);
#endif /* IGT_X86_H */
diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c
index fdd9661d..61f8b755 100644
--- a/tests/i915/gem_exec_reloc.c
+++ b/tests/i915/gem_exec_reloc.c
@@ -23,6 +23,7 @@
#include "igt.h"
#include "igt_dummyload.h"
+#include "igt_x86.h"
IGT_TEST_DESCRIPTION("Basic sanity check of execbuf-ioctl relocations.");
@@ -500,17 +501,6 @@ static void basic_reloc(int fd, unsigned before, unsigned
after, unsigned flags)
gem_close(fd, obj.handle);
}
-static inline uint64_t sign_extend(uint64_t x, int index)
-{
- int shift = 63 - index;
- return (int64_t)(x << shift) >> shift;
-}
-
-static uint64_t gen8_canonical_address(uint64_t address)
-{
- return sign_extend(address, 47);
-}
-
static void basic_range(int fd, unsigned flags)
{
struct drm_i915_gem_relocation_entry reloc[128];
@@ -537,7 +527,7 @@ static void basic_range(int fd, unsigned flags)
for (int i = 0; i <= count; i++) {
obj[n].handle = gem_create(fd, 4096);
obj[n].offset = (1ull << (i + 12)) - 4096;
- obj[n].offset = gen8_canonical_address(obj[n].offset);
+ obj[n].offset = gen8_canonical_addr(obj[n].offset);
obj[n].flags = EXEC_OBJECT_PINNED |
EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
execbuf.buffers_ptr = to_user_pointer([n]);
@@ -557,7 +547,7 @@ static void basic_range(int fd, unsigned flags)
for (int i = 1; i < count; i++) {
obj[n].handle = gem_create(fd, 4096);
obj[n].offset = 1ull << (i + 12);
- obj[n].offset = gen8_canonical_address(obj[n].offset);
+ obj[n].offset = gen8_canonical_addr(obj[n].offset);
obj[n].flags = EXEC_OBJECT_PINNED |
EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
execbuf.buffers_ptr = to_user_pointer([n]);
diff --git a/tests/i915/gem_softpin.c b/tests/i915/gem_softpin.c
index b9ff532e..17bd40a4 100644
--- a/tests/i915/gem_softpin.c
+++ b/tests/i915/gem_softpin.c
@@ -27,22 +27,11 @@
*/
#include "igt.h"
+#include "igt_x86.h"
#define EXEC_OBJECT_PINNED (1<<4)
#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
-/* gen8_canonical_addr
- * Used to convert any address into canonical form, i.e. [63:48] == [47].
- * Based on kernel's sign_extend64 implementation.
- * @address - a virtual address
-*/
-#define GEN8_HIGH_ADDRESS_BIT 47
-static uint64_t gen8_canonical_addr(uint64_t address)
-{
- __u8 shift = 63 - GEN8_HIGH_ADDRESS_BIT;
- return (__s64)(address << shift) >> shift;
-}
-
static void test_invalid(int fd)
{
const uint32_t bbe = MI_BATCH_BUFFER_END;
--
2.21.0
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[Intel-gfx] [RFC PATCH i-g-t v3 2/4] lib: Add GEM minimum page size helper
Some tests assume 4kB page size while using softpin. That assumption
may be wrong on future GEM backends with possibly larger minimum page
sizes. As a result, those tests may either fail on softpin at offsets
which are incorrectly aligned, may silently skip such incorrectly
aligned addresses assuming them occupied by other users, or may always
succeed when examining invalid use patterns.
Provide a helper function that detects minimum page size and returns
the size order. Tests may use it to calculate softpin offsets suitable
for actually used backing store.
Signed-off-by: Janusz Krzysztofik
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Stuart Summers
---
lib/ioctl_wrappers.c | 82
lib/ioctl_wrappers.h | 1 +
2 files changed, 83 insertions(+)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 280fdd62..a4313832 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -54,6 +54,7 @@
#include "intel_io.h"
#include "igt_debugfs.h"
#include "igt_sysfs.h"
+#include "igt_x86.h"
#include "config.h"
#ifdef HAVE_VALGRIND
@@ -1157,6 +1158,87 @@ bool gem_has_softpin(int fd)
return has_softpin;
}
+static int __min_page_size_order(int fd, struct drm_i915_gem_exec_object2 *obj,
+struct drm_i915_gem_execbuffer2 *eb,
+uint64_t offset, int min_order, int max_order)
+{
+ static const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint64_t page_size = 1ull << max_order;
+ int order;
+
+ if (max_order > min_order) {
+ /* explore upper half of the max_order@offset area */
+ order = __min_page_size_order(fd, obj, eb, offset, min_order,
+ max_order - 1);
+ if (order < max_order)
+ return order;
+ }
+
+ obj->offset = gen8_canonical_addr(offset - page_size);
+ gem_write(fd, obj->handle, 0, , sizeof(bbe));
+ if (!__gem_execbuf(fd, eb)) {
+ /* upper half not occupied, must be the minimum */
+ igt_debug("found min page size=%#llx, size order=%d\n",
+ (long long)page_size, max_order);
+ return max_order;
+ }
+
+ if (max_order > min_order) {
+ /* explore lower half of in case the upper half was occupied */
+ page_size >>= 1;
+ order = __min_page_size_order(fd, obj, eb, offset - page_size,
+ min_order, max_order - 1);
+ if (order < max_order)
+ return order;
+ }
+
+ return max_order + 1;
+}
+
+/**
+ * gem_min_page_size_order:
+ * @fd: open i915 drm file descriptor
+ *
+ * This function detects the minimum size of a gem object allocated from
+ * a default backing store. It is useful for calculating correctly aligned
+ * softpin offsets.
+ * Since size order to size conversion (size = 1 << order) is less trivial
+ * than the opposite, the function returns the size order as more handy.
+ *
+ * Returns:
+ * Size order of the minimum page size
+ */
+int gem_min_page_size_order(int fd)
+{
+ struct drm_i915_gem_exec_object2 obj;
+ struct drm_i915_gem_execbuffer2 eb;
+ uint64_t gtt_size = gem_aperture_size(fd);
+ int min_order = 12; /* current I915_GTT_PAGE_SIZE equivalent */
+ uint64_t page_size = 1ull << min_order;
+ int max_order = 21; /* current I915_GTT_MAX_PAGE_SIZE equivalent */
+
+ /* no softpin => 4kB page size */
+ if (!gem_has_softpin(fd))
+ return min_order;
+
+ memset(, 0, sizeof(obj));
+ memset(, 0, sizeof(eb));
+
+ obj.handle = gem_create(fd, page_size);
+ obj.flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ eb.buffers_ptr = to_user_pointer();
+ eb.buffer_count = 1;
+
+ min_order = __min_page_size_order(fd, , , gtt_size, min_order,
+ max_order);
+
+ gem_close(fd, obj.handle);
+
+ igt_require(min_order <= max_order);
+
+ return min_order;
+}
+
/**
* gem_has_exec_fence:
* @fd: open i915 drm file descriptor
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 03211c97..91690847 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -138,6 +138,7 @@ uint64_t gem_aperture_size(int fd);
uint64_t gem_global_aperture_size(int fd);
uint64_t gem_mappable_aperture_size(void);
bool gem_has_softpin(int fd);
+int gem_min_page_size_order(int fd);
bool gem_has_exec_fence(int fd);
/* check functions which auto-skip tests by calling igt_skip() */
--
2.21.0
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[Intel-gfx] [RFC PATCH i-g-t v3 0/4] Calculate softpin offsets from actual page size
Some tests assume 4kB page size while using softpin. That assumption may be wrong on future GEM backends with possibly larger minimum page sizes. As a result, those tests may either fail on softpin at offsets which are incorrectly aligned, may silently skip such incorrectly aligned addresses assuming them occupied by other users, or may always succeed when examining invalid use patterns. Provide a helper function that detects minimum page size and returns the size order. Use it in test which perform softpin to calculate offsets suitable for actually used backing store. Changelog: v2: Don't skip failing offsets only when on full PPGTT, - simplify the code by reversing the size->order conversion, - drop irrelevant modifications of requested object sizes. v3: Drop patch 1/2 "Don't filter out addresses when on PPGTT" - I don't know how to detect if the kernel is interfering with the user's GTT, - introduce patch 1/4 "lib: Move redundant local helpers to lib/", subsequent patch will use the helper, - introduce patch 2/4 "lib: Add GEM minimum page size helper", subsequent patches will use the new helper (inspired by Chris), - in former patch 2/2, now 3/4, initialize page size order with an actual minimum returned by the new helper (inspired by Chris), - add a new fix for gem_ctx_shared test (patch 4/4). Janusz Krzysztofik (4): lib/i915: Move redundant local helpers to lib/ lib/i915: Add GEM minimum page size helper tests/gem_exec_reloc: Calculate softpin offsets from actual page size tests/gem_ctx_shared: Calculate object attributes from actual page size lib/igt_x86.c | 13 ++ lib/igt_x86.h | 5 +++ lib/ioctl_wrappers.c| 82 + lib/ioctl_wrappers.h| 1 + tests/i915/gem_ctx_shared.c | 6 ++- tests/i915/gem_exec_reloc.c | 26 tests/i915/gem_softpin.c| 13 +- 7 files changed, 115 insertions(+), 31 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH i-g-t v3 3/4] tests/gem_exec_reloc: Calculate softpin offsets from actual page size
From: Janusz Krzysztofik
The basic-range subtest assumes 4kB page size while calculating softpin
offsets. On future backends with possibly larger minimum page sizes
a half of calculated offsets to be tested may be incorrectly detected
as occupied by other users and skiped, significantly distoring the
intended test pattern.
Replace hardcoded constants corresponding to the assumed 4kB page size
with variables initialized with actual minimum page size and order.
v2: Simplify the code by reversing the size->order conversion,
- drop irrelevant modifications of requested object sizes.
v3: Initialize page size order with an actual minimum returned by a new
helper (inspired by Chris).
Signed-off-by: Janusz Krzysztofik
Cc: Katarzyna Dec
Cc: Stuart Summers
Cc: Chris Wilson
---
tests/i915/gem_exec_reloc.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c
index 61f8b755..5e7df8ed 100644
--- a/tests/i915/gem_exec_reloc.c
+++ b/tests/i915/gem_exec_reloc.c
@@ -510,14 +510,16 @@ static void basic_range(int fd, unsigned flags)
uint64_t gtt_size = gem_aperture_size(fd);
const uint32_t bbe = MI_BATCH_BUFFER_END;
igt_spin_t *spin = NULL;
+ int page_order = gem_min_page_size_order(fd);
+ uint64_t page_size = 1ull << page_order;
int count, n;
igt_require(gem_has_softpin(fd));
- for (count = 12; gtt_size >> (count + 1); count++)
+ for (count = page_order; gtt_size >> (count + 1); count++)
;
- count -= 12;
+ count -= page_order;
memset(obj, 0, sizeof(obj));
memset(reloc, 0, sizeof(reloc));
@@ -526,7 +528,7 @@ static void basic_range(int fd, unsigned flags)
n = 0;
for (int i = 0; i <= count; i++) {
obj[n].handle = gem_create(fd, 4096);
- obj[n].offset = (1ull << (i + 12)) - 4096;
+ obj[n].offset = (1ull << (i + page_order)) - page_size;
obj[n].offset = gen8_canonical_addr(obj[n].offset);
obj[n].flags = EXEC_OBJECT_PINNED |
EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
@@ -546,7 +548,7 @@ static void basic_range(int fd, unsigned flags)
}
for (int i = 1; i < count; i++) {
obj[n].handle = gem_create(fd, 4096);
- obj[n].offset = 1ull << (i + 12);
+ obj[n].offset = 1ull << (i + page_order);
obj[n].offset = gen8_canonical_addr(obj[n].offset);
obj[n].flags = EXEC_OBJECT_PINNED |
EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
--
2.21.0
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Re: [Intel-gfx] [PATCH] drm/i915/execlists: Use vfunc to check engine submission mode
Quoting Michal Wajdeczko (2019-10-28 14:22:29) > On Mon, 28 Oct 2019 14:09:05 +0100, Chris Wilson > wrote: > > > Quoting Michal Wajdeczko (2019-10-28 12:57:03) > >> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h > >> b/drivers/gpu/drm/i915/gt/intel_lrc.h > >> index 99dc576a4e25..23dde9083349 100644 > >> --- a/drivers/gpu/drm/i915/gt/intel_lrc.h > >> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.h > >> @@ -145,4 +145,6 @@ struct intel_engine_cs * > >> intel_virtual_engine_get_sibling(struct intel_engine_cs *engine, > >> unsigned int sibling); > >> > >> +bool intel_engine_in_execlists_submission_mode(struct intel_engine_cs > >> *engine); > > > > Planning to use it outside? > > Yes, there are few places where global USES_GUC_SUBMISSION(i915) is used, > and some of them can be replaced by in_execlists_submission_mode(e) right > away (i915_perf.c). Aye, perf looks like a good candidate to put this to immediate use. Care to include that with Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm: Add support for integrated privacy screens
On Fri, Oct 25, 2019 at 4:36 AM Thierry Reding wrote:
>
> On Thu, Oct 24, 2019 at 01:45:16PM -0700, Rajat Jain wrote:
> > Hi,
> >
> > Thanks for your review and comments. Please see inline below.
> >
> > On Thu, Oct 24, 2019 at 4:20 AM Thierry Reding
> > wrote:
> > >
> > > On Tue, Oct 22, 2019 at 05:12:06PM -0700, Rajat Jain wrote:
> > > > Certain laptops now come with panels that have integrated privacy
> > > > screens on them. This patch adds support for such panels by adding
> > > > a privacy-screen property to the drm_connector for the panel, that
> > > > the userspace can then use to control and check the status. The idea
> > > > was discussed here:
> > > >
> > > > https://lkml.org/lkml/2019/10/1/786
> > > >
> > > > ACPI methods are used to identify, query and control privacy screen:
> > > >
> > > > * Identifying an ACPI object corresponding to the panel: The patch
> > > > follows ACPI Spec 6.3 (available at
> > > > https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf).
> > > > Pages 1119 - 1123 describe what I believe, is a standard way of
> > > > identifying / addressing "display panels" in the ACPI tables, thus
> > > > allowing kernel to attach ACPI nodes to the panel. IMHO, this ability
> > > > to identify and attach ACPI nodes to drm connectors may be useful for
> > > > reasons other privacy-screens, in future.
> > > >
> > > > * Identifying the presence of privacy screen, and controlling it, is
> > > > done
> > > > via ACPI _DSM methods.
> > > >
> > > > Currently, this is done only for the Intel display ports. But in future,
> > > > this can be done for any other ports if the hardware becomes available
> > > > (e.g. external monitors supporting integrated privacy screens?).
> > > >
> > > > Also, this code can be extended in future to support non-ACPI methods
> > > > (e.g. using a kernel GPIO driver to toggle a gpio that controls the
> > > > privacy-screen).
> > > >
> > > > Signed-off-by: Rajat Jain
> > > > ---
> > > > drivers/gpu/drm/Makefile| 1 +
> > > > drivers/gpu/drm/drm_atomic_uapi.c | 5 +
> > > > drivers/gpu/drm/drm_connector.c | 38 +
> > > > drivers/gpu/drm/drm_privacy_screen.c| 176
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 3 +
> > > > include/drm/drm_connector.h | 18 +++
> > > > include/drm/drm_mode_config.h | 7 +
> > > > include/drm/drm_privacy_screen.h| 33 +
> > > > 8 files changed, 281 insertions(+)
> > > > create mode 100644 drivers/gpu/drm/drm_privacy_screen.c
> > > > create mode 100644 include/drm/drm_privacy_screen.h
> > >
> > > I like this much better than the prior proposal to use sysfs. However
> > > the support currently looks a bit tangled. I realize that we only have a
> > > single implementation for this in hardware right now, so there's no use
> > > in over-engineering things, but I think we can do a better job from the
> > > start without getting into too many abstractions. See below.
> > >
> > > > diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> > > > index 82ff826b33cc..e1fc33d69bb7 100644
> > > > --- a/drivers/gpu/drm/Makefile
> > > > +++ b/drivers/gpu/drm/Makefile
> > > > @@ -19,6 +19,7 @@ drm-y := drm_auth.o drm_cache.o \
> > > > drm_syncobj.o drm_lease.o drm_writeback.o drm_client.o \
> > > > drm_client_modeset.o drm_atomic_uapi.o drm_hdcp.o
> > > >
> > > > +drm-$(CONFIG_ACPI) += drm_privacy_screen.o
> > > > drm-$(CONFIG_DRM_LEGACY) += drm_legacy_misc.o drm_bufs.o drm_context.o
> > > > drm_dma.o drm_scatter.o drm_lock.o
> > > > drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o
> > > > drm-$(CONFIG_DRM_VM) += drm_vm.o
> > > > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> > > > b/drivers/gpu/drm/drm_atomic_uapi.c
> > > > index 7a26bfb5329c..44131165e4ea 100644
> > > > --- a/drivers/gpu/drm/drm_atomic_uapi.c
> > > > +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> > > > @@ -30,6 +30,7 @@
> > > > #include
> > > > #include
> > > > #include
> > > > +#include
> > > > #include
> > > > #include
> > > >
> > > > @@ -766,6 +767,8 @@ static int drm_atomic_connector_set_property(struct
> > > > drm_connector *connector,
> > > > fence_ptr);
> > > > } else if (property == connector->max_bpc_property) {
> > > > state->max_requested_bpc = val;
> > > > + } else if (property == config->privacy_screen_property) {
> > > > + drm_privacy_screen_set_val(connector, val);
> > >
> > > This doesn't look right. Shouldn't you store the value in the connector
> > > state and then leave it up to the connector driver to set it
> > > appropriately? I think that also has the advantage of untangling this
> > > support a little.
> >
> > Hopefully this gets answered in my explanations below.
> >
> > >
> > > > } else if (connector->funcs->atomic_set_property) {
> > > > return
Re: [Intel-gfx] [PATCH tip/core/rcu 03/10] drivers/gpu: Replace rcu_swap_protected() with rcu_replace()
On Mon, Oct 28, 2019 at 02:57:26PM +0200, Joonas Lahtinen wrote: > Quoting paul...@kernel.org (2019-10-22 22:12:08) > > From: "Paul E. McKenney" > > > > This commit replaces the use of rcu_swap_protected() with the more > > intuitively appealing rcu_replace() as a step towards removing > > rcu_swap_protected(). > > > > Link: > > https://lore.kernel.org/lkml/CAHk-=wiAsJLw1egFEE=z7-ggtm6wcvtyytxza1+bhqta4gg...@mail.gmail.com/ > > Reported-by: Linus Torvalds > > [ paulmck: From rcu_replace() to rcu_replace_pointer() per Ingo Molnar. ] > > Signed-off-by: Paul E. McKenney > > Cc: Jani Nikula > > Cc: Joonas Lahtinen > > Cc: Rodrigo Vivi > > Cc: David Airlie > > Cc: Daniel Vetter > > Cc: Chris Wilson > > Cc: Tvrtko Ursulin > > Cc: > > Cc: > > "drm/i915:" preferred as the subject prefix for increased specificity. "drm/i915" it is! > Let me know which tree you end up merging with. I expect to be sending a pull request for inclusion into the -tip tree in a day or three. > Reviewed-by: Joonas Lahtinen Applied, thank you! Thanx, Paul ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Handle AUX interrupts for TC ports (rev2)
On Sat, Oct 26, 2019 at 08:01:35AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tgl: Handle AUX interrupts for TC ports (rev2)
> URL : https://patchwork.freedesktop.org/series/68528/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7176_full -> Patchwork_14972_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_14972_full absolutely need to
> be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_14972_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_14972_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@kms_frontbuffer_tracking@fbc-suspend:
> - shard-snb: [PASS][1] -> [DMESG-WARN][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/shard-snb7/igt@kms_frontbuffer_track...@fbc-suspend.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14972/shard-snb6/igt@kms_frontbuffer_track...@fbc-suspend.html
Unstable system clock following suspend/resume; not related to this
patch.
<6> [1016.423795] ACPI: Waking up from system sleep state S3
<7> [1016.455194] [drm:intel_power_well_enable [i915]] enabling always-on
<4> [1016.455203] [ cut here ]
<4> [1016.455208] Delta way too big! 18446743040866119517
ts=18446744057200346625 write stamp = 1016334227108
If you just came from a suspend/resume,
please switch to the trace global clock:
echo global > /sys/kernel/debug/tracing/trace_clock
or add trace_clock=global to the kernel command line
<4> [1016.455221] WARNING: CPU: 7 PID: 4447 at
kernel/trace/ring_buffer.c:2810 rb_handle_timestamp.isra.44+0x6c/0x70
Applied to dinq. Thanks Jose for the review.
Matt
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@kms_big_fb@linear-64bpp-rotate-0:
> - {shard-tglb}: [PASS][3] -> [INCOMPLETE][4]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/shard-tglb6/igt@kms_big...@linear-64bpp-rotate-0.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14972/shard-tglb6/igt@kms_big...@linear-64bpp-rotate-0.html
>
> * igt@kms_ccs@pipe-b-missing-ccs-buffer:
> - {shard-tglb}: [SKIP][5] ([fdo#111595]) -> [TIMEOUT][6]
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/shard-tglb6/igt@kms_...@pipe-b-missing-ccs-buffer.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14972/shard-tglb8/igt@kms_...@pipe-b-missing-ccs-buffer.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_14972_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_ctx_switch@vcs1:
> - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112080]) +8 similar
> issues
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/shard-iclb4/igt@gem_ctx_swi...@vcs1.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14972/shard-iclb7/igt@gem_ctx_swi...@vcs1.html
>
> * igt@gem_exec_schedule@preemptive-hang-bsd:
> - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +3 similar
> issues
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/shard-iclb3/igt@gem_exec_sched...@preemptive-hang-bsd.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14972/shard-iclb2/igt@gem_exec_sched...@preemptive-hang-bsd.html
>
> * igt@gem_exec_schedule@promotion-bsd1:
> - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +8 similar
> issues
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/shard-iclb4/igt@gem_exec_sched...@promotion-bsd1.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14972/shard-iclb7/igt@gem_exec_sched...@promotion-bsd1.html
>
> * igt@gem_persistent_relocs@forked-interruptible-thrashing:
> - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#112037])
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/shard-iclb1/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14972/shard-iclb4/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
>
> * igt@gem_softpin@noreloc-s3:
> - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566])
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/shard-apl3/igt@gem_soft...@noreloc-s3.html
>[16]:
>
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Check a few more fixed locations within the context image (rev2)
== Series Details ==
Series: drm/i915/selftests: Check a few more fixed locations within the context
image (rev2)
URL : https://patchwork.freedesktop.org/series/68611/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7201 -> Patchwork_15022
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/index.html
Known issues
Here are the changes found in Patchwork_15022 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#103167])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_mmap_gtt@basic-write-gtt-no-prefault:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt-no-prefault.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt-no-prefault.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][7] ([fdo#111407]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (53 -> 43)
--
Missing(10): fi-kbl-soraka fi-ilk-m540 fi-tgl-u2 fi-hsw-4200u
fi-byt-squawks fi-bsw-cyan fi-icl-y fi-tgl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7201 -> Patchwork_15022
CI-20190529: 20190529
CI_DRM_7201: c5ec9a4155c4bac3d44e88fe6a4ddadfa1e5dc45 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5247: 4d1f6036dfc64f92c02475f9ae2cc8ffcc1b @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15022: 97bf5ef24ce3533d1a1a3cacab00ec951ff2694f @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
97bf5ef24ce3 drm/i915/selftests: Check a few more fixed locations within the
context image
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/index.html
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Collect user engines at driver_register phase
== Series Details ==
Series: drm/i915: Collect user engines at driver_register phase
URL : https://patchwork.freedesktop.org/series/68609/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7194_full -> Patchwork_15009_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_15009_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15009_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_15009_full:
### IGT changes ###
Possible regressions
* igt@gem_eio@in-flight-1us:
- shard-snb: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-snb7/igt@gem_...@in-flight-1us.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15009/shard-snb4/igt@gem_...@in-flight-1us.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_mmap_gtt@medium-copy-xy:
- {shard-tglb}: [PASS][3] -> [INCOMPLETE][4] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-tglb8/igt@gem_mmap_...@medium-copy-xy.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15009/shard-tglb2/igt@gem_mmap_...@medium-copy-xy.html
* {igt@i915_selftest@live_gt_heartbeat}:
- shard-glk: NOTRUN -> [DMESG-FAIL][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15009/shard-glk7/igt@i915_selftest@live_gt_heartbeat.html
Known issues
Here are the changes found in Patchwork_15009_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_busy@extended-semaphore-vcs1:
- shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#112080]) +4 similar
issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-iclb1/igt@gem_b...@extended-semaphore-vcs1.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15009/shard-iclb3/igt@gem_b...@extended-semaphore-vcs1.html
* igt@gem_ctx_isolation@vcs1-dirty-switch:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#109276] / [fdo#112080])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-iclb4/igt@gem_ctx_isolat...@vcs1-dirty-switch.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15009/shard-iclb5/igt@gem_ctx_isolat...@vcs1-dirty-switch.html
* igt@gem_eio@reset-stress:
- shard-snb: [PASS][10] -> [DMESG-FAIL][11] ([fdo#109661])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-snb7/igt@gem_...@reset-stress.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15009/shard-snb4/igt@gem_...@reset-stress.html
* igt@gem_exec_schedule@preempt-self-bsd:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#112146]) +1 similar
issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-iclb7/igt@gem_exec_sched...@preempt-self-bsd.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15009/shard-iclb1/igt@gem_exec_sched...@preempt-self-bsd.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-snb: [PASS][14] -> [DMESG-WARN][15] ([fdo#111870])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-snb2/igt@gem_userptr_bl...@dmabuf-sync.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15009/shard-snb7/igt@gem_userptr_bl...@dmabuf-sync.html
* igt@i915_suspend@forcewake:
- shard-apl: [PASS][16] -> [DMESG-WARN][17] ([fdo#108566])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-apl3/igt@i915_susp...@forcewake.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15009/shard-apl1/igt@i915_susp...@forcewake.html
* igt@kms_color@pipe-a-ctm-0-75:
- shard-skl: [PASS][18] -> [DMESG-WARN][19] ([fdo#106107])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-skl6/igt@kms_co...@pipe-a-ctm-0-75.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15009/shard-skl2/igt@kms_co...@pipe-a-ctm-0-75.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-hsw: [PASS][20] -> [FAIL][21] ([fdo#102670])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-hsw2/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15009/shard-hsw6/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: [PASS][22] -> [FAIL][23] ([fdo#105363])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7194/shard-glk5/igt@kms_f...@2x-flip-vs-expired-vblank.html
Re: [Intel-gfx] [PATCH 1/6] drm/i915: Fix i845/i865 cursor width
On Mon, Oct 28, 2019 at 03:20:34PM +0100, Maarten Lankhorst wrote:
> Op 28-10-2019 om 12:30 schreef Ville Syrjala:
> > From: Ville Syrjälä
> >
> > The change from the uapi coordinates to the internal coordinates
> > broke the cursor on i845/i865 due to src and dst getting swapped.
> > Fix it.
> >
> > Cc: Maarten Lankhorst
> > Fixes: 3a612765f423 ("drm/i915: Remove cursor use of properties for
> > coordinates")
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 0f0c582a56d5..47a3aef0fb61 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -10947,7 +10947,7 @@ static void i845_update_cursor(struct intel_plane
> > *plane,
> > unsigned long irqflags;
> >
> > if (plane_state && plane_state->base.visible) {
> > - unsigned int width = drm_rect_width(_state->base.src);
> > + unsigned int width = drm_rect_width(_state->base.dst);
> > unsigned int height = drm_rect_height(_state->base.dst);
> >
> > cntl = plane_state->ctl |
>
> Yeah, I guess theoretically fixes, should be ok regardless because no scaling
> is supported on the cursor so rectangles are identical. :)
No. One is .16 fixed point other is integer. Ie. totally broken atm,
as proven by the cursor being smeared over the whole screen on my i865.
>
> Reviewed-by: Maarten Lankhorst
--
Ville Syrjälä
Intel
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Fix i845/i865 cursor width
== Series Details == Series: series starting with [1/6] drm/i915: Fix i845/i865 cursor width URL : https://patchwork.freedesktop.org/series/68646/ State : success == Summary == CI Bug Log - changes from CI_DRM_7201 -> Patchwork_15021 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/index.html Known issues Here are the changes found in Patchwork_15021 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap_gtt@basic-read-write-distinct: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/fi-icl-u3/igt@gem_mmap_...@basic-read-write-distinct.html * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-gdg-551: [PASS][3] -> [SKIP][4] ([fdo#109271]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/fi-gdg-551/igt@kms_cursor_leg...@basic-flip-before-cursor-varying-size.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/fi-gdg-551/igt@kms_cursor_leg...@basic-flip-before-cursor-varying-size.html Possible fixes * igt@gem_mmap_gtt@basic-write-gtt-no-prefault: - fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt-no-prefault.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/fi-icl-u3/igt@gem_mmap_...@basic-write-gtt-no-prefault.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][7] ([fdo#111407]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 Participating hosts (53 -> 44) -- Missing(9): fi-ilk-m540 fi-hsw-4200u fi-tgl-u2 fi-byt-squawks fi-bsw-cyan fi-icl-y fi-tgl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7201 -> Patchwork_15021 CI-20190529: 20190529 CI_DRM_7201: c5ec9a4155c4bac3d44e88fe6a4ddadfa1e5dc45 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5247: 4d1f6036dfc64f92c02475f9ae2cc8ffcc1b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15021: ff2e006cf58b53f9bb580dbaf395da00d97352d5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ff2e006cf58b drm/i915: Protect overlay colorkey macro arguments c7bd1d944a4b drm/i915: Enable pipe gamma for the overlay db0e1a02849f drm/i915: Configure overlay cc_out precision based on crtc gamma config e8bd89048c9a drm/i915: Fix overlay colorkey for 30bpp and 8bpp 19cde21752fa drm/i915: Fix max cursor size for i915g/gm 4da018f49855 drm/i915: Fix i845/i865 cursor width == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/5] drm/dsi: add missing DSI DCS commands
Update from the DCS specification.
Cc: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
include/video/mipi_display.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index 6b6390dfa203..928f8c4b6658 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -79,7 +79,9 @@ enum {
enum {
MIPI_DCS_NOP= 0x00,
MIPI_DCS_SOFT_RESET = 0x01,
+ MIPI_DCS_GET_COMPRESSION_MODE = 0x03,
MIPI_DCS_GET_DISPLAY_ID = 0x04,
+ MIPI_DCS_GET_ERROR_COUNT_ON_DSI = 0x05,
MIPI_DCS_GET_RED_CHANNEL= 0x06,
MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
@@ -94,6 +96,8 @@ enum {
MIPI_DCS_EXIT_SLEEP_MODE= 0x11,
MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
+ MIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 0x14,
+ MIPI_DCS_GET_IMAGE_CHECKSUM_CT = 0x15,
MIPI_DCS_EXIT_INVERT_MODE = 0x20,
MIPI_DCS_ENTER_INVERT_MODE = 0x21,
MIPI_DCS_SET_GAMMA_CURVE= 0x26,
@@ -105,6 +109,7 @@ enum {
MIPI_DCS_WRITE_LUT = 0x2D,
MIPI_DCS_READ_MEMORY_START = 0x2E,
MIPI_DCS_SET_PARTIAL_AREA = 0x30,
+ MIPI_DCS_SET_PARTIAL_COLUMNS= 0x31,
MIPI_DCS_SET_SCROLL_AREA= 0x33,
MIPI_DCS_SET_TEAR_OFF = 0x34,
MIPI_DCS_SET_TEAR_ON= 0x35,
@@ -114,7 +119,10 @@ enum {
MIPI_DCS_ENTER_IDLE_MODE= 0x39,
MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
+ MIPI_DCS_SET_3D_CONTROL = 0x3D,
MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
+ MIPI_DCS_GET_3D_CONTROL = 0x3F,
+ MIPI_DCS_SET_VSYNC_TIMING = 0x40,
MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
MIPI_DCS_GET_SCANLINE = 0x45,
MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
@@ -126,7 +134,9 @@ enum {
MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E,/* MIPI DCS 1.3 */
MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F,/* MIPI DCS 1.3 */
MIPI_DCS_READ_DDB_START = 0xA1,
+ MIPI_DCS_READ_PPS_START = 0xA2,
MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
+ MIPI_DCS_READ_PPS_CONTINUE = 0xA9,
};
/* MIPI DCS pixel formats */
--
2.20.1
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[Intel-gfx] [PATCH v2 1/5] drm/dsi: clean up DSI data type definitions
Rename picture parameter set (it's a long packet, not a long write) and
compression mode (it's not a DCS command) enumerations according to the
DSI specification. Order the types according to the spec. Use tabs
instead of spaces for indentation. Use all lower case for hex.
Cc: Vandita Kulkarni
Reviewed-by: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_mipi_dsi.c | 4 ++--
include/video/mipi_display.h | 10 +-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index bd2498bbd74a..f237d80828c3 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -373,6 +373,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
case MIPI_DSI_V_SYNC_END:
case MIPI_DSI_H_SYNC_START:
case MIPI_DSI_H_SYNC_END:
+ case MIPI_DSI_COMPRESSION_MODE:
case MIPI_DSI_END_OF_TRANSMISSION:
case MIPI_DSI_COLOR_MODE_OFF:
case MIPI_DSI_COLOR_MODE_ON:
@@ -387,7 +388,6 @@ bool mipi_dsi_packet_format_is_short(u8 type)
case MIPI_DSI_DCS_SHORT_WRITE:
case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
case MIPI_DSI_DCS_READ:
- case MIPI_DSI_DCS_COMPRESSION_MODE:
case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
return true;
}
@@ -406,11 +406,11 @@ EXPORT_SYMBOL(mipi_dsi_packet_format_is_short);
bool mipi_dsi_packet_format_is_long(u8 type)
{
switch (type) {
- case MIPI_DSI_PPS_LONG_WRITE:
case MIPI_DSI_NULL_PACKET:
case MIPI_DSI_BLANKING_PACKET:
case MIPI_DSI_GENERIC_LONG_WRITE:
case MIPI_DSI_DCS_LONG_WRITE:
+ case MIPI_DSI_PICTURE_PARAMETER_SET:
case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index cba57a678daf..79fd71cf4934 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -17,6 +17,9 @@ enum {
MIPI_DSI_H_SYNC_START = 0x21,
MIPI_DSI_H_SYNC_END = 0x31,
+ MIPI_DSI_COMPRESSION_MODE = 0x07,
+ MIPI_DSI_END_OF_TRANSMISSION= 0x08,
+
MIPI_DSI_COLOR_MODE_OFF = 0x02,
MIPI_DSI_COLOR_MODE_ON = 0x12,
MIPI_DSI_SHUTDOWN_PERIPHERAL= 0x22,
@@ -35,18 +38,15 @@ enum {
MIPI_DSI_DCS_READ = 0x06,
- MIPI_DSI_DCS_COMPRESSION_MODE = 0x07,
- MIPI_DSI_PPS_LONG_WRITE = 0x0A,
-
MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
- MIPI_DSI_END_OF_TRANSMISSION= 0x08,
-
MIPI_DSI_NULL_PACKET= 0x09,
MIPI_DSI_BLANKING_PACKET= 0x19,
MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
MIPI_DSI_DCS_LONG_WRITE = 0x39,
+ MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
+
MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20= 0x0c,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24= 0x1c,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16= 0x2c,
--
2.20.1
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[Intel-gfx] [PATCH v2 5/5] drm/dsi: add helpers for DSI compression mode and PPS packets
Add helper functions for sending the DSI compression mode and picture
parameter set data type packets. For the time being, limit the support
to using VESA DSC 1.1 and the default PPS. This may need updating if the
need arises for proprietary compression or non-default PPS, however keep
it simple for starters.
v2: Add missing EXPORT_SYMBOL
Cc: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_mipi_dsi.c | 51 ++
include/drm/drm_mipi_dsi.h | 4 +++
2 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index 3f33f02571fd..55531895dde6 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -33,6 +33,7 @@
#include
#include
+#include
#include
/**
@@ -548,6 +549,56 @@ int mipi_dsi_set_maximum_return_packet_size(struct
mipi_dsi_device *dsi,
}
EXPORT_SYMBOL(mipi_dsi_set_maximum_return_packet_size);
+/**
+ * mipi_dsi_compression_mode() - enable/disable DSC on the peripheral
+ * @dsi: DSI peripheral device
+ * @enable: Whether to enable or disable the DSC
+ *
+ * Enable or disable Display Stream Compression on the peripheral using the
+ * default Picture Parameter Set and VESA DSC 1.1 algorithm.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+ssize_t mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable)
+{
+ /* Note: Needs updating for non-default PPS or algorithm */
+ u8 tx[2] = { enable << 0, 0 };
+ struct mipi_dsi_msg msg = {
+ .channel = dsi->channel,
+ .type = MIPI_DSI_COMPRESSION_MODE,
+ .tx_len = sizeof(tx),
+ .tx_buf = tx,
+ };
+ int ret = mipi_dsi_device_transfer(dsi, );
+
+ return (ret < 0) ? ret : 0;
+}
+EXPORT_SYMBOL(mipi_dsi_compression_mode);
+
+/**
+ * mipi_dsi_picture_parameter_set() - transmit the DSC PPS to the peripheral
+ * @dsi: DSI peripheral device
+ * @pps: VESA DSC 1.1 Picture Parameter Set
+ *
+ * Transmit the VESA DSC 1.1 Picture Parameter Set to the peripheral.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+ssize_t mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi,
+ const struct
drm_dsc_picture_parameter_set *pps)
+{
+ struct mipi_dsi_msg msg = {
+ .channel = dsi->channel,
+ .type = MIPI_DSI_PICTURE_PARAMETER_SET,
+ .tx_len = sizeof(*pps),
+ .tx_buf = pps,
+ };
+ int ret = mipi_dsi_device_transfer(dsi, );
+
+ return (ret < 0) ? ret : 0;
+}
+EXPORT_SYMBOL(mipi_dsi_picture_parameter_set);
+
/**
* mipi_dsi_generic_write() - transmit data using a generic write packet
* @dsi: DSI peripheral device
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 13cf2ae59f6c..360e6377e84b 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -13,6 +13,7 @@
struct mipi_dsi_host;
struct mipi_dsi_device;
+struct drm_dsc_picture_parameter_set;
/* request ACK from peripheral */
#define MIPI_DSI_MSG_REQ_ACK BIT(0)
@@ -228,6 +229,9 @@ int mipi_dsi_shutdown_peripheral(struct mipi_dsi_device
*dsi);
int mipi_dsi_turn_on_peripheral(struct mipi_dsi_device *dsi);
int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
u16 value);
+ssize_t mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable);
+ssize_t mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi,
+ const struct
drm_dsc_picture_parameter_set *pps);
ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void
*payload,
size_t size);
--
2.20.1
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[Intel-gfx] [PATCH v2 4/5] drm/dsi: rename MIPI_DCS_SET_PARTIAL_AREA to MIPI_DCS_SET_PARTIAL_ROWS
The DCS command has been named SET_PARTIAL_ROWS in the DCS spec since
v1.02, for more than a decade. Rename the enumeration to match the spec.
v2: add comment about the rename (David Lechner)
Cc: David Lechner
Cc: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/tiny/st7586.c | 2 +-
include/video/mipi_display.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tiny/st7586.c b/drivers/gpu/drm/tiny/st7586.c
index 3cc21a1b30c8..060cc756194f 100644
--- a/drivers/gpu/drm/tiny/st7586.c
+++ b/drivers/gpu/drm/tiny/st7586.c
@@ -240,7 +240,7 @@ static void st7586_pipe_enable(struct
drm_simple_display_pipe *pipe,
mipi_dbi_command(dbi, ST7586_SET_DISP_DUTY, 0x7f);
mipi_dbi_command(dbi, ST7586_SET_PART_DISP, 0xa0);
- mipi_dbi_command(dbi, MIPI_DCS_SET_PARTIAL_AREA, 0x00, 0x00, 0x00,
0x77);
+ mipi_dbi_command(dbi, MIPI_DCS_SET_PARTIAL_ROWS, 0x00, 0x00, 0x00,
0x77);
mipi_dbi_command(dbi, MIPI_DCS_EXIT_INVERT_MODE);
msleep(100);
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index 928f8c4b6658..b6d8b874233f 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -108,7 +108,7 @@ enum {
MIPI_DCS_WRITE_MEMORY_START = 0x2C,
MIPI_DCS_WRITE_LUT = 0x2D,
MIPI_DCS_READ_MEMORY_START = 0x2E,
- MIPI_DCS_SET_PARTIAL_AREA = 0x30,
+ MIPI_DCS_SET_PARTIAL_ROWS = 0x30, /* MIPI DCS 1.02 -
MIPI_DCS_SET_PARTIAL_AREA before that */
MIPI_DCS_SET_PARTIAL_COLUMNS= 0x31,
MIPI_DCS_SET_SCROLL_AREA= 0x33,
MIPI_DCS_SET_TEAR_OFF = 0x34,
--
2.20.1
___
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[Intel-gfx] [PATCH v2 2/5] drm/dsi: add missing DSI data types
Add execute queue and compressed pixel stream packet data types for
completeness.
Cc: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_mipi_dsi.c | 2 ++
include/video/mipi_display.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index f237d80828c3..3f33f02571fd 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -388,6 +388,7 @@ bool mipi_dsi_packet_format_is_short(u8 type)
case MIPI_DSI_DCS_SHORT_WRITE:
case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
case MIPI_DSI_DCS_READ:
+ case MIPI_DSI_EXECUTE_QUEUE:
case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
return true;
}
@@ -411,6 +412,7 @@ bool mipi_dsi_packet_format_is_long(u8 type)
case MIPI_DSI_GENERIC_LONG_WRITE:
case MIPI_DSI_DCS_LONG_WRITE:
case MIPI_DSI_PICTURE_PARAMETER_SET:
+ case MIPI_DSI_COMPRESSED_PIXEL_STREAM:
case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20:
case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24:
case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16:
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index 79fd71cf4934..6b6390dfa203 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -37,6 +37,7 @@ enum {
MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
MIPI_DSI_DCS_READ = 0x06,
+ MIPI_DSI_EXECUTE_QUEUE = 0x16,
MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
@@ -46,6 +47,7 @@ enum {
MIPI_DSI_DCS_LONG_WRITE = 0x39,
MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a,
+ MIPI_DSI_COMPRESSED_PIXEL_STREAM= 0x0b,
MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20= 0x0c,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24= 0x1c,
--
2.20.1
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: Mark conn as initialised by iterator
Chris Wilson writes:
> smatch complains about
> drivers/gpu/drm/i915//display/intel_display.c:14403
> intel_set_dp_tp_ctl_normal() error: uninitialized symbol 'conn'.
> because it has no way to determine that the loop must have an entry.
> Tell the static analysers to ignore the local, it will always be set.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 0f0c582a56d5..9dce2e9e5376 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14391,8 +14391,8 @@ static void intel_crtc_enable_trans_port_sync(struct
> intel_crtc *crtc,
> static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
> struct intel_atomic_state *state)
> {
> + struct drm_connector *uninitialized_var(conn);
> struct drm_connector_state *conn_state;
> - struct drm_connector *conn;
> struct intel_dp *intel_dp;
> int i;
>
> --
> 2.24.0.rc1
>
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Re: [Intel-gfx] [PATCH 3/5] drm/i915: Add missing AUX channel H & I support
On Fri, Oct 25, 2019 at 04:13:40PM -0700, Lucas De Marchi wrote:
> On Fri, Oct 25, 2019 at 04:06:21PM -0700, Matt Roper wrote:
> > TGL's extra ports also bring extra AUX channels.
> >
> > Signed-off-by: Matt Roper
> > ---
> > drivers/gpu/drm/i915/display/intel_bios.c | 6
> > drivers/gpu/drm/i915/display/intel_display.c | 36 +--
> > drivers/gpu/drm/i915/display/intel_display.h | 2 ++
> > drivers/gpu/drm/i915/display/intel_dp.c | 4 +++
> > drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 ++
> > 5 files changed, 22 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index fe302338b7fd..3867b41338a7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -2339,6 +2339,12 @@ enum aux_ch intel_bios_port_aux_ch(struct
> > drm_i915_private *dev_priv,
> > case DP_AUX_G:
> > aux_ch = AUX_CH_G;
> > break;
> > + case DP_AUX_H:
> > + aux_ch = AUX_CH_H;
> > + break;
> > + case DP_AUX_I:
> > + aux_ch = AUX_CH_I;
> > + break;
>
> I'd rather drop H/I from all other places since we are not using them.
I'm not sure I understand what you mean here. My understanding was that
OEM's can use non-standard association of port<->aux that's dependent on
their board design. If we don't honor their desired AUX setting here in
the VBT (or handle it elsewhere in the driver) don't we risk having
display fail on some platforms?
Matt
>
> Lucas De Marchi
>
>
> > default:
> > MISSING_CASE(info->alternate_aux_channel);
> > aux_ch = AUX_CH_A;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index cbf9cf30050c..e45ed0c07d0d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6847,39 +6847,19 @@ intel_aux_power_domain(struct intel_digital_port
> > *dig_port)
> >
> > if (intel_phy_is_tc(dev_priv, phy) &&
> > dig_port->tc_mode == TC_PORT_TBT_ALT) {
> > - switch (dig_port->aux_ch) {
> > - case AUX_CH_C:
> > - return POWER_DOMAIN_AUX_C_TBT;
> > - case AUX_CH_D:
> > - return POWER_DOMAIN_AUX_D_TBT;
> > - case AUX_CH_E:
> > - return POWER_DOMAIN_AUX_E_TBT;
> > - case AUX_CH_F:
> > - return POWER_DOMAIN_AUX_F_TBT;
> > - case AUX_CH_G:
> > - return POWER_DOMAIN_AUX_G_TBT;
> > - default:
> > + if (dig_port->aux_ch >= AUX_CH_C &&
> > + dig_port->aux_ch <= AUX_CH_I) {
> > + return POWER_DOMAIN_AUX_C_TBT + dig_port->aux_ch -
> > + AUX_CH_C;
> > + } else {
> > MISSING_CASE(dig_port->aux_ch);
> > return POWER_DOMAIN_AUX_C_TBT;
> > }
> > }
> >
> > - switch (dig_port->aux_ch) {
> > - case AUX_CH_A:
> > - return POWER_DOMAIN_AUX_A;
> > - case AUX_CH_B:
> > - return POWER_DOMAIN_AUX_B;
> > - case AUX_CH_C:
> > - return POWER_DOMAIN_AUX_C;
> > - case AUX_CH_D:
> > - return POWER_DOMAIN_AUX_D;
> > - case AUX_CH_E:
> > - return POWER_DOMAIN_AUX_E;
> > - case AUX_CH_F:
> > - return POWER_DOMAIN_AUX_F;
> > - case AUX_CH_G:
> > - return POWER_DOMAIN_AUX_G;
> > - default:
> > + if (dig_port->aux_ch <= AUX_CH_I) {
> > + return POWER_DOMAIN_AUX_A + dig_port->aux_ch;
> > + } else {
> > MISSING_CASE(dig_port->aux_ch);
> > return POWER_DOMAIN_AUX_A;
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> > b/drivers/gpu/drm/i915/display/intel_display.h
> > index ca7ca2804d8b..9ccaae41a8ad 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > @@ -275,6 +275,8 @@ enum aux_ch {
> > AUX_CH_E, /* ICL+ */
> > AUX_CH_F,
> > AUX_CH_G,
> > + AUX_CH_H,
> > + AUX_CH_I,
> > };
> >
> > #define aux_ch_name(a) ((a) + 'A')
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 86989ec25bc6..65bab46f7b43 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1667,6 +1667,8 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp
> > *intel_dp)
> > case AUX_CH_E:
> > case AUX_CH_F:
> > case AUX_CH_G:
> > + case AUX_CH_H:
> > + case AUX_CH_I:
> > return DP_AUX_CH_CTL(aux_ch);
> > default:
> > MISSING_CASE(aux_ch);
> > @@ -1688,6 +1690,8 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp
> > *intel_dp, int index)
> > case AUX_CH_E:
> > case AUX_CH_F:
> >
Re: [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Initialise ret
Chris Wilson writes:
> Keep smatch quiet,
>
> drivers/gpu/drm/i915//gem/selftests/i915_gem_context.c:1268 __igt_ctx_sseu()
> error: uninitialized symbol 'ret'.
> drivers/gpu/drm/i915//gem/selftests/i915_gem_context.c:1280 __igt_ctx_sseu()
> error: uninitialized symbol 'ret'.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> index d1d873f23338..c6e61564bb5e 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> @@ -1188,7 +1188,7 @@ __igt_ctx_sseu(struct drm_i915_private *i915,
> {
> struct drm_i915_gem_object *obj;
> int inst = 0;
> - int ret;
> + int ret = 0;
>
> if (INTEL_GEN(i915) < 9 || !RUNTIME_INFO(i915)->sseu.has_slice_pg)
> return 0;
> --
> 2.24.0.rc1
>
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Fix i845/i865 cursor width
== Series Details == Series: series starting with [1/6] drm/i915: Fix i845/i865 cursor width URL : https://patchwork.freedesktop.org/series/68646/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4da018f49855 drm/i915: Fix i845/i865 cursor width 19cde21752fa drm/i915: Fix max cursor size for i915g/gm e8bd89048c9a drm/i915: Fix overlay colorkey for 30bpp and 8bpp -:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'c' - possible side-effects? #26: FILE: drivers/gpu/drm/i915/display/intel_overlay.c:105: +#define RGB30_TO_COLORKEY(c) \ + (((c & 0x3FC0) >> 6) | ((c & 0x000FF000) >> 4) | ((c & 0x03FC) >> 2)) -:26: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'c' may be better as '(c)' to avoid precedence issues #26: FILE: drivers/gpu/drm/i915/display/intel_overlay.c:105: +#define RGB30_TO_COLORKEY(c) \ + (((c & 0x3FC0) >> 6) | ((c & 0x000FF000) >> 4) | ((c & 0x03FC) >> 2)) -:32: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'c' - possible side-effects? #32: FILE: drivers/gpu/drm/i915/display/intel_overlay.c:111: +#define RGB8I_TO_COLORKEY(c) \ + (((c & 0xFF) << 16) | ((c & 0XFF) << 8) | ((c & 0xFF) << 0)) -:32: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'c' may be better as '(c)' to avoid precedence issues #32: FILE: drivers/gpu/drm/i915/display/intel_overlay.c:111: +#define RGB8I_TO_COLORKEY(c) \ + (((c & 0xFF) << 16) | ((c & 0XFF) << 8) | ((c & 0xFF) << 0)) total: 0 errors, 0 warnings, 4 checks, 37 lines checked db0e1a02849f drm/i915: Configure overlay cc_out precision based on crtc gamma config c7bd1d944a4b drm/i915: Enable pipe gamma for the overlay ff2e006cf58b drm/i915: Protect overlay colorkey macro arguments ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Measure basic throughput of blit routines (rev2)
== Series Details == Series: drm/i915/selftests: Measure basic throughput of blit routines (rev2) URL : https://patchwork.freedesktop.org/series/68610/ State : failure == Summary == Applying: drm/i915/selftests: Measure basic throughput of blit routines Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c Falling back to patching base and 3-way merge... No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/selftests: Initialise ret
Keep smatch quiet,
drivers/gpu/drm/i915//gem/selftests/i915_gem_context.c:1268 __igt_ctx_sseu()
error: uninitialized symbol 'ret'.
drivers/gpu/drm/i915//gem/selftests/i915_gem_context.c:1280 __igt_ctx_sseu()
error: uninitialized symbol 'ret'.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index d1d873f23338..c6e61564bb5e 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1188,7 +1188,7 @@ __igt_ctx_sseu(struct drm_i915_private *i915,
{
struct drm_i915_gem_object *obj;
int inst = 0;
- int ret;
+ int ret = 0;
if (INTEL_GEN(i915) < 9 || !RUNTIME_INFO(i915)->sseu.has_slice_pg)
return 0;
--
2.24.0.rc1
___
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