Re: [Intel-gfx] [PATCH 1/5] drm/i915: Add two spaces before the SKL_DFSM registers
On 2019-10-25 at 17:13:19 -0700, José Roberto de Souza wrote:
> The next patches are going to touch this registers so here already
> fixing it for older registers and make it consistent with most of
> the other registers in this file.
>
> Cc: Ramalingam C
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_reg.h | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 746326784a4d..09cb43f4e976 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7663,15 +7663,15 @@ enum {
> #define CNL_DDI_CLOCK_REG_ACCESS_ON(1 << 7)
>
> #define SKL_DFSM _MMIO(0x51000)
> -#define SKL_DFSM_CDCLK_LIMIT_MASK(3 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
> -#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> -#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
> -#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
> -#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
> -#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
> +#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
> +#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
> +#define SKL_DFSM_PIPE_A_DISABLE(1 << 30)
> +#define SKL_DFSM_PIPE_B_DISABLE(1 << 21)
> +#define SKL_DFSM_PIPE_C_DISABLE(1 << 28)
> +#define TGL_DFSM_PIPE_D_DISABLE(1 << 22)
Looks good to me.
Reviewed-by: Ramalingam C
>
> #define SKL_DSSM _MMIO(0x51004)
> #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
> --
> 2.23.0
>
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Skip suspend/resume GuC action on platforms w/o GuC submission (rev3)
== Series Details ==
Series: drm/i915/guc: Skip suspend/resume GuC action on platforms w/o GuC
submission (rev3)
URL : https://patchwork.freedesktop.org/series/68685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7227_full -> Patchwork_15079_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_15079_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_big_fb@y-tiled-16bpp-rotate-270:
- {shard-tglb}: [PASS][1] -> [INCOMPLETE][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7227/shard-tglb7/igt@kms_big...@y-tiled-16bpp-rotate-270.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15079/shard-tglb3/igt@kms_big...@y-tiled-16bpp-rotate-270.html
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- {shard-tglb}: NOTRUN -> [INCOMPLETE][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15079/shard-tglb2/igt@kms_b...@extended-modeset-hang-newfb-render-a.html
Known issues
Here are the changes found in Patchwork_15079_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_exec@basic-invalid-context-vcs1:
- shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#112080]) +7 similar
issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7227/shard-iclb4/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15079/shard-iclb5/igt@gem_ctx_e...@basic-invalid-context-vcs1.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][6] -> [DMESG-WARN][7] ([fdo#108566]) +6
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7227/shard-kbl7/igt@gem_ctx_isolat...@rcs0-s3.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15079/shard-kbl7/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_ctx_isolation@vcs1-s3:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#109276] / [fdo#112080])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7227/shard-iclb2/igt@gem_ctx_isolat...@vcs1-s3.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15079/shard-iclb3/igt@gem_ctx_isolat...@vcs1-s3.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276]) +19 similar
issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7227/shard-iclb2/igt@gem_exec_sched...@preempt-queue-bsd1.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15079/shard-iclb5/igt@gem_exec_sched...@preempt-queue-bsd1.html
* igt@gem_exec_schedule@preempt-self-bsd:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#112146]) +4 similar
issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7227/shard-iclb5/igt@gem_exec_sched...@preempt-self-bsd.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15079/shard-iclb2/igt@gem_exec_sched...@preempt-self-bsd.html
* igt@gem_tiled_swapping@non-threaded:
- shard-kbl: [PASS][14] -> [DMESG-WARN][15] ([fdo#108686])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7227/shard-kbl1/igt@gem_tiled_swapp...@non-threaded.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15079/shard-kbl1/igt@gem_tiled_swapp...@non-threaded.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-hsw: [PASS][16] -> [DMESG-WARN][17] ([fdo#111870])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7227/shard-hsw5/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15079/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-apl: [PASS][18] -> [INCOMPLETE][19] ([fdo#103927]) +1
similar issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7227/shard-apl7/igt@kms_b...@extended-modeset-hang-newfb-render-a.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15079/shard-apl8/igt@kms_b...@extended-modeset-hang-newfb-render-a.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [PASS][20] -> [DMESG-WARN][21] ([fdo#108566])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7227/shard-apl8/igt@kms_cursor_...@pipe-a-cursor-suspend.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15079/shard-apl4/igt@kms_cursor_...@pipe-a-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][22] -> [FAIL][23] ([fdo#105363])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7227/shard-skl10/igt@kms_f...@flip-vs-expired-vblank.html
[23]:
Re: [Intel-gfx] [PATCH] drm/i915: update rawclk also on resume
On Thu, Oct 31, 2019, Ville Syrjala wrote:
>On Thu, Oct 31, 2019 at 01:14:07PM +0200, Jani Nikula wrote:
>> Since CNP it's possible for rawclk to have two different values, 19.2
>> and 24 MHz. If the value indicated by SFUSE_STRAP register is
>> different from the power on default for PCH_RAWCLK_FREQ, we'll end up
>> having a mismatch between the rawclk hardware and software states
>> after suspend/resume. On previous platforms this used to work by
>> accident, because the power on defaults worked just fine.
>>
>> Update the rawclk also on resume. The natural place to do this is
>> intel_modeset_init_hw(), however VLV/CHV need it done before
>> intel_power_domains_init_hw(). Split the update accordingly, even if
>> that's slighly ugly. This means moving the update later for
>> non-VLV/CHV platforms in probe.
>>
>> Reported-by: Shawn Lee
>> Cc: Shawn Lee
>> Cc: Ville Syrjala
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 5 +
>> drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++
>> drivers/gpu/drm/i915/i915_drv.c| 3 ---
>> 3 files changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index e56a75c07043..e31697fdffd3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -16610,6 +16610,11 @@ void intel_init_display_hooks(struct
>> drm_i915_private *dev_priv)
>>
>> void intel_modeset_init_hw(struct drm_i915_private *i915) {
>> +/*
>> + * VLV/CHV update rawclk earlier in intel_power_domains_init_hw().
>> + */
>> +if (!IS_VALLEYVIEW(i915) && !IS_CHERRYVIEW(i915))
>> +intel_update_rawclk(i915);
>> intel_update_cdclk(i915);
>> intel_dump_cdclk_state(>cdclk.hw, "Current CDCLK");
>> i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw; diff
>> --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>> b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 707ac110e271..999133d1f088 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -5015,6 +5015,13 @@ void intel_power_domains_init_hw(struct
>> drm_i915_private *i915, bool resume)
>>
>> power_domains->initializing = true;
>>
>> +/*
>> + * Must happen before power domain init on VLV/CHV, the rest update
>> + * rawclk later in intel_modeset_init_hw().
>> + */
>> +if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
>> +intel_update_rawclk(i915);
>
>Can't we just do it here unconditionally? I think this gets called on the
>resume path as well.
>
Try to do intel_update_rawclk() here and remove it at intel_modeset_init_hw()
and i915_driver_modeset_probe().
Here will be executed before intel_modeset_init_hw(). So it looks good to me
just do it here.
Best regards,
Shawn
>> +
>> if (INTEL_GEN(i915) >= 11) {
>> icl_display_core_init(i915, resume);
>> } else if (IS_CANNONLAKE(i915)) {
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> b/drivers/gpu/drm/i915/i915_drv.c index 21273b516dbe..62906336298a
>> 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -296,9 +296,6 @@ static int i915_driver_modeset_probe(struct
>> drm_i915_private *i915)
>> if (ret)
>> goto cleanup_vga_client;
>>
>> -/* must happen before intel_power_domains_init_hw() on VLV/CHV */
>> -intel_update_rawclk(i915);
>> -
>> intel_power_domains_init_hw(i915, false);
>>
>> intel_csr_ucode_init(i915);
>> --
>> 2.20.1
>
>--
>Ville Syrjälä
>Intel
>
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/11] drm/i915: Split detaching and removing the vma
== Series Details == Series: series starting with [01/11] drm/i915: Split detaching and removing the vma URL : https://patchwork.freedesktop.org/series/68788/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7226_full -> Patchwork_15078_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15078_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15078_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15078_full: ### IGT changes ### Possible regressions * igt@gem_ctx_param@invalid-ctx-get: - shard-skl: [PASS][1] -> [DMESG-WARN][2] +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-skl9/igt@gem_ctx_pa...@invalid-ctx-get.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-skl5/igt@gem_ctx_pa...@invalid-ctx-get.html * igt@gem_exec_schedule@out-order-vebox: - shard-skl: [PASS][3] -> [INCOMPLETE][4] +22 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-skl4/igt@gem_exec_sched...@out-order-vebox.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-skl1/igt@gem_exec_sched...@out-order-vebox.html * igt@gem_exec_schedule@preempt-hang-bsd: - shard-glk: [PASS][5] -> [DMESG-WARN][6] +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-glk4/igt@gem_exec_sched...@preempt-hang-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-glk7/igt@gem_exec_sched...@preempt-hang-bsd.html * igt@gem_exec_schedule@preempt-hang-bsd2: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-kbl7/igt@gem_exec_sched...@preempt-hang-bsd2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-kbl2/igt@gem_exec_sched...@preempt-hang-bsd2.html * igt@gem_exec_schedule@preempt-hang-render: - shard-apl: [PASS][9] -> [DMESG-WARN][10] +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-apl6/igt@gem_exec_sched...@preempt-hang-render.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-apl4/igt@gem_exec_sched...@preempt-hang-render.html - shard-iclb: [PASS][11] -> [DMESG-WARN][12] +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-iclb6/igt@gem_exec_sched...@preempt-hang-render.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-iclb3/igt@gem_exec_sched...@preempt-hang-render.html * igt@gem_exec_schedule@preempt-hang-vebox: - shard-iclb: NOTRUN -> [DMESG-WARN][13] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-iclb3/igt@gem_exec_sched...@preempt-hang-vebox.html * igt@runner@aborted: - shard-hsw: NOTRUN -> [FAIL][14] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-hsw8/igt@run...@aborted.html - shard-kbl: NOTRUN -> ([FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], [FAIL][21], [FAIL][22], [FAIL][23], [FAIL][24], [FAIL][25], [FAIL][26], [FAIL][27], [FAIL][28]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-kbl2/igt@run...@aborted.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-kbl3/igt@run...@aborted.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-kbl2/igt@run...@aborted.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-kbl3/igt@run...@aborted.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-kbl2/igt@run...@aborted.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-kbl2/igt@run...@aborted.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-kbl3/igt@run...@aborted.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-kbl2/igt@run...@aborted.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-kbl2/igt@run...@aborted.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-kbl3/igt@run...@aborted.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-kbl7/igt@run...@aborted.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-kbl6/igt@run...@aborted.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15078/shard-kbl6/igt@run...@aborted.html [28]:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/psr: Share the computation of idle frames
== Series Details ==
Series: series starting with [1/3] drm/i915/psr: Share the computation of idle
frames
URL : https://patchwork.freedesktop.org/series/68844/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7234 -> Patchwork_15097
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15097/index.html
Known issues
Here are the changes found in Patchwork_15097 that come from known issues:
### IGT changes ###
Issues hit
* igt@vgem_basic@second-client:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-icl-u3/igt@vgem_ba...@second-client.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15097/fi-icl-u3/igt@vgem_ba...@second-client.html
Possible fixes
* igt@gem_busy@busy-all:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-icl-u3/igt@gem_b...@busy-all.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15097/fi-icl-u3/igt@gem_b...@busy-all.html
* igt@gem_flink_basic@basic:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724] / [fdo#112052 ]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-icl-u3/igt@gem_flink_ba...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15097/fi-icl-u3/igt@gem_flink_ba...@basic.html
Warnings
* igt@i915_pm_rpm@module-reload:
- fi-icl-u2: [DMESG-WARN][7] ([fdo#110595]) -> [DMESG-WARN][8]
([fdo#106107] / [fdo#110595])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-icl-u2/igt@i915_pm_...@module-reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15097/fi-icl-u2/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595
[fdo#112052 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112052
Participating hosts (52 -> 41)
--
Missing(11): fi-ilk-m540 fi-bxt-dsi fi-bsw-n3050 fi-hsw-4200u
fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-cfl-8109u fi-pnv-d510 fi-byt-clapper
fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7234 -> Patchwork_15097
CI-20190529: 20190529
CI_DRM_7234: 4163f8c46b6ef75ea32737f08aa3f5fd429a4462 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5255: b21b6a7aaa0db2159f22ee4427804e5a16fe2261 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15097: 992cc413b400eaaf0373d9eca9e5918f88314f3e @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
992cc413b400 drm/i915/dc3co: Avoid full modeset when EXITLINE needs to be
changed
b7f54f2ed8c5 drm/i915/dc3co: Check for DC3C0 exit state instead of sleep
3eca46244cc4 drm/i915/psr: Share the computation of idle frames
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15097/index.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Split detaching and removing the vma
== Series Details ==
Series: drm/i915: Split detaching and removing the vma
URL : https://patchwork.freedesktop.org/series/68787/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7226_full -> Patchwork_15077_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_15077_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15077_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_15077_full:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_execlists:
- shard-apl: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-apl3/igt@i915_selftest@live_execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15077/shard-apl1/igt@i915_selftest@live_execlists.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_draw_crc@draw-method-xrgb-mmap-gtt-ytiled:
- {shard-tglb}: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-tglb3/igt@kms_draw_...@draw-method-xrgb-mmap-gtt-ytiled.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15077/shard-tglb6/igt@kms_draw_...@draw-method-xrgb-mmap-gtt-ytiled.html
Known issues
Here are the changes found in Patchwork_15077_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_busy@busy-vcs1:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +14 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-iclb2/igt@gem_b...@busy-vcs1.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15077/shard-iclb3/igt@gem_b...@busy-vcs1.html
* igt@gem_ctx_isolation@vcs1-none:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [fdo#112080])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-iclb2/igt@gem_ctx_isolat...@vcs1-none.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15077/shard-iclb3/igt@gem_ctx_isolat...@vcs1-none.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +3 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-iclb7/igt@gem_exec_sched...@preempt-other-chain-bsd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15077/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-hsw6/igt@gem_userptr_bl...@dmabuf-sync.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15077/shard-hsw1/igt@gem_userptr_bl...@dmabuf-sync.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-snb4/igt@gem_userptr_bl...@sync-unmap.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15077/shard-snb7/igt@gem_userptr_bl...@sync-unmap.html
* igt@i915_selftest@mock_requests:
- shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#112156])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-skl1/igt@i915_selftest@mock_requests.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15077/shard-skl5/igt@i915_selftest@mock_requests.html
* igt@kms_color@pipe-b-ctm-blue-to-red:
- shard-skl: [PASS][17] -> [DMESG-WARN][18] ([fdo#106107])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-skl5/igt@kms_co...@pipe-b-ctm-blue-to-red.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15077/shard-skl2/igt@kms_co...@pipe-b-ctm-blue-to-red.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: [PASS][19] -> [FAIL][20] ([fdo#105363])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-glk9/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15077/shard-glk1/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#105363])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-skl1/igt@kms_f...@flip-vs-expired-vblank.html
[22]:
Re: [Intel-gfx] [PATCH 0/5] tgl: MST support
I plan to debug MST with this patches next week but I guess at least the 4 first patches can be merged. The 5th too if someone else reviews it, the selection of the master transcoder was tested by me and Lucas and the problem in not in any of this patches. On Tue, 2019-10-29 at 18:24 -0700, Lucas De Marchi wrote: > Additional code to support more than one display when using MST with > TGL. It's still WIP! From what I could check on my tests we are > correctly > tracking the master transcoder and setting it accordingly on > TRANS_DDI_FUNC_CTL and DP_TP_CTL. > > I tried also setting MST mode on the slave's DP_TP_CTL. I could get > the > second display to show up some times and we don't get stuck on > "timeout > waiting for ACT" error message. This is not according to the spec > though, and it still doesn't work most of the time. So... I didn't > add > it here. > > I guess now I need another pair of eyes to check what I'm doing wrong > since continuing to stare at the spec and code isn't helping. José, > Imre? > > José Roberto de Souza (2): > drm/i915: Add for_each_new_intel_connector_in_state() > drm/i915/tgl: Select master transcoder in DP MST > > Lucas De Marchi (3): > drm/i915: add wrappers to get intel connector state > drm/i915/tgl: do not enable transcoder clock twice on MST > drm/i915: avoid reading DP_TP_CTL twice > > drivers/gpu/drm/i915/display/intel_ddi.c | 54 +++--- > drivers/gpu/drm/i915/display/intel_display.c | 16 ++ > drivers/gpu/drm/i915/display/intel_display.h | 8 + > .../drm/i915/display/intel_display_types.h| 21 +++ > drivers/gpu/drm/i915/display/intel_dp_mst.c | 159 > +- > drivers/gpu/drm/i915/display/intel_dp_mst.h | 2 + > 6 files changed, 236 insertions(+), 24 deletions(-) > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915: avoid reading DP_TP_CTL twice
On Tue, 2019-10-29 at 18:24 -0700, Lucas De Marchi wrote:
> Just avoid the additional read in case DP_TP_CTL is enabled:
> read it once and save the value.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 33
>
> 1 file changed, 17 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 2ce998529d08..41b9b9a6772a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4148,37 +4148,38 @@ static void
> intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv =
> to_i915(intel_dig_port->base.base.dev);
> enum port port = intel_dig_port->base.port;
> - u32 val;
> + u32 dp_tp_ctl, ddi_buf_ctl;
> bool wait = false;
>
> - if (I915_READ(intel_dp->regs.dp_tp_ctl) & DP_TP_CTL_ENABLE) {
> - val = I915_READ(DDI_BUF_CTL(port));
> - if (val & DDI_BUF_CTL_ENABLE) {
> - val &= ~DDI_BUF_CTL_ENABLE;
> - I915_WRITE(DDI_BUF_CTL(port), val);
> + dp_tp_ctl = I915_READ(intel_dp->regs.dp_tp_ctl);
> +
> + if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
> + ddi_buf_ctl = I915_READ(DDI_BUF_CTL(port));
> + if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
> + I915_WRITE(DDI_BUF_CTL(port),
> +ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
> wait = true;
> }
>
> - val = I915_READ(intel_dp->regs.dp_tp_ctl);
> - val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> - val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> - I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
> + dp_tp_ctl &= ~(DP_TP_CTL_ENABLE |
> DP_TP_CTL_LINK_TRAIN_MASK);
> + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
> + I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
> POSTING_READ(intel_dp->regs.dp_tp_ctl);
>
> if (wait)
> intel_wait_ddi_buf_idle(dev_priv, port);
> }
>
> - val = DP_TP_CTL_ENABLE |
> - DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
> + dp_tp_ctl = DP_TP_CTL_ENABLE |
> + DP_TP_CTL_LINK_TRAIN_PAT1 |
> DP_TP_CTL_SCRAMBLE_DISABLE;
> if (intel_dp->link_mst)
> - val |= DP_TP_CTL_MODE_MST;
> + dp_tp_ctl |= DP_TP_CTL_MODE_MST;
> else {
> - val |= DP_TP_CTL_MODE_SST;
> + dp_tp_ctl |= DP_TP_CTL_MODE_SST;
> if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> - val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
> + dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
> }
> - I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
> + I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
> POSTING_READ(intel_dp->regs.dp_tp_ctl);
>
> intel_dp->DP |= DDI_BUF_CTL_ENABLE;
___
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Re: [Intel-gfx] [PATCH 3/5] drm/i915/tgl: do not enable transcoder clock twice on MST
On Tue, 2019-10-29 at 18:24 -0700, Lucas De Marchi wrote:
> For MST on Tiger Lake there are different moments when we need to
> configure the transcoder clock select. For the first link this is in
> step
> 7.a of the spec, before training the link. For additional streams
> this
> should be done as part of step 8.b after programming receiver VC
> Payload
> ID.
>
> Bspec: 49190
>
Reviewed-by: José Roberto de Souza
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c| 7 ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +---
> 2 files changed, 17 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index fed7fc56dd92..2ce998529d08 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3462,9 +3462,10 @@ static void tgl_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
> icl_program_mg_dp_mode(dig_port, crtc_state);
>
> /*
> - * 7.a - Steps in this function should only be executed over
> MST
> - * master, what will be taken in care by MST hook
> - * intel_mst_pre_enable_dp()
> + * 7.a - single stream or multi-stream master transcoder:
> Configure
> + * Transcoder Clock Select. For additional MST streams this
> will be done
> + * by intel_mst_pre_enable_dp() after programming VC Payload ID
> through
> + * AUX.
>*/
> intel_ddi_enable_pipe_clock(crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index a9962846a503..ad54618f6142 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -299,21 +299,23 @@ static void intel_mst_pre_enable_dp(struct
> intel_encoder *encoder,
> to_intel_connector(conn_state->connector);
> int ret;
> u32 temp;
> + bool first_mst_stream;
>
> /* MST encoders are bound to a crtc, not to a connector,
>* force the mapping here for get_hw_state.
>*/
> connector->encoder = encoder;
> intel_mst->connector = connector;
> + first_mst_stream = intel_dp->active_mst_links == 0;
>
> DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
>
> - if (intel_dp->active_mst_links == 0)
> + if (first_mst_stream)
> intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>
> drm_dp_send_power_updown_phy(_dp->mst_mgr, connector-
> >port, true);
>
> - if (intel_dp->active_mst_links == 0)
> + if (first_mst_stream)
> intel_dig_port->base.pre_enable(_dig_port->base,
> pipe_config, NULL);
>
> @@ -330,7 +332,15 @@ static void intel_mst_pre_enable_dp(struct
> intel_encoder *encoder,
>
> ret = drm_dp_update_payload_part1(_dp->mst_mgr);
>
> - intel_ddi_enable_pipe_clock(pipe_config);
> + /*
> + * Before Gen 12 this is not done as part of
> + * intel_dig_port->base.pre_enable() and should be done here.
> For
> + * Gen 12+ the step in which this should be done is different
> for the
> + * first MST stream, so it's done on the DDI for the first
> stream and
> + * here for the following ones.
> + */
> + if (INTEL_GEN(dev_priv) < 12 || !first_mst_stream)
> + intel_ddi_enable_pipe_clock(pipe_config);
> }
>
> static void intel_mst_enable_dp(struct intel_encoder *encoder,
___
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Re: [Intel-gfx] [PATCH 2/5] drm/i915: add wrappers to get intel connector state
On Tue, 2019-10-29 at 18:24 -0700, Lucas De Marchi wrote:
> Wrap drm_atomic_get_old_connector_state so we can get the
> intel_digital_connector_state and make it easier to migrate to intel
> types.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Lucas De Marchi
> ---
> .../gpu/drm/i915/display/intel_display_types.h | 18
> ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 40184e823c84..a550abb48b3c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1527,6 +1527,24 @@ intel_atomic_get_new_crtc_state(struct
> intel_atomic_state *state,
>
> >base));
> }
>
> +static inline struct intel_digital_connector_state *
> +intel_atomic_get_new_connector_state(struct intel_atomic_state
> *state,
> + struct intel_connector *connector)
> +{
> + return to_intel_digital_connector_state(
> + drm_atomic_get_new_connector_state(
> >base,
> + >base));
> +}
> +
> +static inline struct intel_digital_connector_state *
> +intel_atomic_get_old_connector_state(struct intel_atomic_state
> *state,
> + struct intel_connector *connector)
> +{
> + return to_intel_digital_connector_state(
> + drm_atomic_get_old_connector_state(
> >base,
> + >base));
> +}
> +
> /* intel_display.c */
> static inline bool
> intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
___
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[Intel-gfx] [PATCH 2/3] drm/i915/dc3co: Check for DC3C0 exit state instead of sleep
DC3C0 could have already exit so no need to always sleep, so lets read the register with the state. Cc: Imre Deak Cc: Anshuman Gupta Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 707ac110e271..00037c529a33 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -812,7 +812,7 @@ static void tgl_disable_dc3co(struct drm_i915_private *dev_priv) /* * Delay of 200us DC3CO Exit time B.Spec 49196 */ - usleep_range(200, 210); + intel_de_wait_for_set(dev_priv, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 1); } static void bxt_enable_dc9(struct drm_i915_private *dev_priv) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915/dc3co: Avoid full modeset when EXITLINE needs to be changed
A recent change in BSpec allow us to change EXTLINE while transcoder
is enabled so this allow us to change it even when doing the first
fastset after taking over previous hardware state set by BIOS.
BIOS don't enable PSR, so if sink supports PSR it will be enabled on
the first fastset, so moving the EXTLINE compute and set to PSR flows
allow us to simplfy a bunch of code.
This will save a lot of time in all the IGT tests that uses CRC, as
when PSR2 is enabled CRCs are not generated, so we switch to PSR1, so
the previous code would compute dc3co_exitline=0 causing a full
modeset that would shutdown pipe, enable and train link.
BSpec: 49196
Cc: Imre Deak
Cc: Anshuman Gupta
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 86
drivers/gpu/drm/i915/display/intel_display.c | 1 -
drivers/gpu/drm/i915/display/intel_psr.c | 47 +++
3 files changed, 47 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index b51f244ad7a5..f52fb7619d46 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3339,86 +3339,6 @@ static void intel_ddi_disable_fec_state(struct
intel_encoder *encoder,
POSTING_READ(intel_dp->regs.dp_tp_ctl);
}
-static void
-tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
-{
- struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
- u32 val;
-
- if (!cstate->dc3co_exitline)
- return;
-
- val = I915_READ(EXITLINE(cstate->cpu_transcoder));
- val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
- I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
-}
-
-static void
-tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
-{
- u32 val, exit_scanlines;
- struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
-
- if (!cstate->dc3co_exitline)
- return;
-
- exit_scanlines = cstate->dc3co_exitline;
- exit_scanlines <<= EXITLINE_SHIFT;
- val = I915_READ(EXITLINE(cstate->cpu_transcoder));
- val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
- val |= exit_scanlines;
- val |= EXITLINE_ENABLE;
- I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
-}
-
-static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
- struct intel_crtc_state *cstate)
-{
- u32 exit_scanlines;
- struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
- u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
-
- cstate->dc3co_exitline = 0;
-
- if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
- return;
-
- /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
- if (to_intel_crtc(cstate->base.crtc)->pipe != PIPE_A ||
- encoder->port != PORT_A)
- return;
-
- if (!cstate->has_psr2 || !cstate->base.active)
- return;
-
- /*
-* DC3CO Exit time 200us B.Spec 49196
-* PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
-*/
- exit_scanlines =
- intel_usecs_to_scanlines(>base.adjusted_mode, 200) + 1;
-
- if (WARN_ON(exit_scanlines > crtc_vdisplay))
- return;
-
- cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines;
- DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate->dc3co_exitline);
-}
-
-static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state)
-{
- u32 val;
- struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
-
- if (INTEL_GEN(dev_priv) < 12)
- return;
-
- val = I915_READ(EXITLINE(crtc_state->cpu_transcoder));
-
- if (val & EXITLINE_ENABLE)
- crtc_state->dc3co_exitline = val & EXITLINE_MASK;
-}
-
static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
@@ -3431,7 +3351,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder
*encoder,
int level = intel_ddi_dp_level(intel_dp);
enum transcoder transcoder = crtc_state->cpu_transcoder;
- tgl_set_psr2_transcoder_exitline(crtc_state);
intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
crtc_state->lane_count, is_mst);
@@ -3760,7 +3679,6 @@ static void intel_ddi_post_disable_dp(struct
intel_encoder *encoder,
dig_port->ddi_io_power_domain);
intel_ddi_clk_disable(encoder);
- tgl_clear_psr2_transcoder_exitline(old_crtc_state);
}
static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
@@ -4308,9 +4226,6 @@ void
[Intel-gfx] [PATCH 1/3] drm/i915/psr: Share the computation of idle frames
Both activate functions and the dc3co disable function were doing the
same thing, so better move to a function and share.
Also while at it adding a WARN_ON to catch invalid values.
Cc: Anshuman Gupta
Cc: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 43 +++-
1 file changed, 19 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 6a9f322d3fca..bb9b5349b72a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -451,22 +451,29 @@ static u32 intel_psr1_get_tp_time(struct intel_dp
*intel_dp)
return val;
}
-static void hsw_activate_psr1(struct intel_dp *intel_dp)
+static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 max_sleep_time = 0x1f;
- u32 val = EDP_PSR_ENABLE;
+ int idle_frames;
/* Let's use 6 as the minimum to cover all known cases including the
* off-by-one issue that HW has in some cases.
*/
- int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-
- /* sink_sync_latency of 8 means source has to wait for more than 8
-* frames, we'll go with 9 frames for now
-*/
+ idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
- val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
+
+ WARN_ON(idle_frames > 0xf);
+
+ return idle_frames;
+}
+
+static void hsw_activate_psr1(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u32 max_sleep_time = 0x1f;
+ u32 val = EDP_PSR_ENABLE;
+
+ val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT;
val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
if (IS_HASWELL(dev_priv))
@@ -490,13 +497,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 val;
- /* Let's use 6 as the minimum to cover all known cases including the
-* off-by-one issue that HW has in some cases.
-*/
- int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-
- idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
- val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
+ val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
@@ -563,16 +564,10 @@ static void tgl_psr2_enable_dc3co(struct drm_i915_private
*dev_priv)
static void tgl_psr2_disable_dc3co(struct drm_i915_private *dev_priv)
{
- int idle_frames;
+ struct intel_dp *intel_dp = dev_priv->psr.dp;
intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
- /*
-* Restore PSR2 idle frame let's use 6 as the minimum to cover all known
-* cases including the off-by-one issue that HW has in some cases.
-*/
- idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
- idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
- psr2_program_idle_frames(dev_priv, idle_frames);
+ psr2_program_idle_frames(dev_priv, psr_compute_idle_frames(intel_dp));
}
static void tgl_dc5_idle_thread(struct work_struct *work)
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Spin on all engines simultaneously (rev3)
== Series Details ==
Series: drm/i915/selftests: Spin on all engines simultaneously (rev3)
URL : https://patchwork.freedesktop.org/series/68836/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7234 -> Patchwork_15096
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_15096 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15096, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15096/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_15096:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_requests:
- fi-hsw-peppy: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-hsw-peppy/igt@i915_selftest@live_requests.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15096/fi-hsw-peppy/igt@i915_selftest@live_requests.html
- fi-byt-n2820: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-byt-n2820/igt@i915_selftest@live_requests.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15096/fi-byt-n2820/igt@i915_selftest@live_requests.html
- fi-ivb-3770:[PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-ivb-3770/igt@i915_selftest@live_requests.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15096/fi-ivb-3770/igt@i915_selftest@live_requests.html
- fi-hsw-4770:[PASS][7] -> [DMESG-FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-hsw-4770/igt@i915_selftest@live_requests.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15096/fi-hsw-4770/igt@i915_selftest@live_requests.html
- fi-byt-j1900: [PASS][9] -> [DMESG-FAIL][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-byt-j1900/igt@i915_selftest@live_requests.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15096/fi-byt-j1900/igt@i915_selftest@live_requests.html
- fi-elk-e7500: [PASS][11] -> [DMESG-FAIL][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-elk-e7500/igt@i915_selftest@live_requests.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15096/fi-elk-e7500/igt@i915_selftest@live_requests.html
- fi-ilk-650: [PASS][13] -> [DMESG-FAIL][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-ilk-650/igt@i915_selftest@live_requests.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15096/fi-ilk-650/igt@i915_selftest@live_requests.html
Known issues
Here are the changes found in Patchwork_15096 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713] /
[fdo#109100])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15096/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [PASS][17] -> [INCOMPLETE][18] ([fdo#103927])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15096/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6600u: [PASS][19] -> [INCOMPLETE][20] ([fdo#107807])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-skl-6600u/igt@i915_pm_...@module-reload.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15096/fi-skl-6600u/igt@i915_pm_...@module-reload.html
Possible fixes
* igt@gem_busy@busy-all:
- fi-icl-u3: [DMESG-WARN][21] ([fdo#107724]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-icl-u3/igt@gem_b...@busy-all.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15096/fi-icl-u3/igt@gem_b...@busy-all.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
Participating hosts (52 -> 45)
--
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/fbdev: Fallback to non tiled mode if all tiles not present
== Series Details ==
Series: drm/fbdev: Fallback to non tiled mode if all tiles not present
URL : https://patchwork.freedesktop.org/series/68838/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7234 -> Patchwork_15095
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15095/index.html
Known issues
Here are the changes found in Patchwork_15095 that come from known issues:
### IGT changes ###
Possible fixes
* igt@gem_busy@busy-all:
- fi-icl-u3: [DMESG-WARN][1] ([fdo#107724]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-icl-u3/igt@gem_b...@busy-all.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15095/fi-icl-u3/igt@gem_b...@busy-all.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (52 -> 44)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-pnv-d510 fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7234 -> Patchwork_15095
CI-20190529: 20190529
CI_DRM_7234: 4163f8c46b6ef75ea32737f08aa3f5fd429a4462 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5255: b21b6a7aaa0db2159f22ee4427804e5a16fe2261 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15095: 64383a27c565ee7f40d36d69c1265276a10ddfcb @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
64383a27c565 drm/fbdev: Fallback to non tiled mode if all tiles not present
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15095/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Preload LUTs if the hw isn't currently using them
== Series Details ==
Series: drm/i915: Preload LUTs if the hw isn't currently using them
URL : https://patchwork.freedesktop.org/series/68785/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7226_full -> Patchwork_15076_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_15076_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_psr@psr2_no_drrs:
- {shard-tglb}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-tglb4/igt@kms_psr@psr2_no_drrs.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15076/shard-tglb5/igt@kms_psr@psr2_no_drrs.html
Known issues
Here are the changes found in Patchwork_15076_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_busy@busy-vcs1:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112080]) +10 similar
issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-iclb2/igt@gem_b...@busy-vcs1.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15076/shard-iclb8/igt@gem_b...@busy-vcs1.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +10
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-kbl3/igt@gem_ctx_isolat...@rcs0-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15076/shard-kbl1/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_ctx_isolation@vcs1-none:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [fdo#112080])
+1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-iclb2/igt@gem_ctx_isolat...@vcs1-none.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15076/shard-iclb8/igt@gem_ctx_isolat...@vcs1-none.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#110841])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-iclb5/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15076/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +5 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-iclb5/igt@gem_exec_sched...@in-order-bsd.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15076/shard-iclb2/igt@gem_exec_sched...@in-order-bsd.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109276]) +8 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-iclb2/igt@gem_exec_sched...@out-order-bsd2.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15076/shard-iclb8/igt@gem_exec_sched...@out-order-bsd2.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-snb2/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15076/shard-snb5/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([fdo#107713] /
[fdo#108840])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-iclb5/igt@i915_pm_...@dpms-mode-unset-lpsp.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15076/shard-iclb2/igt@i915_pm_...@dpms-mode-unset-lpsp.html
* igt@kms_color@pipe-b-ctm-0-25:
- shard-skl: [PASS][19] -> [DMESG-WARN][20] ([fdo#106107])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-skl1/igt@kms_co...@pipe-b-ctm-0-25.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15076/shard-skl5/igt@kms_co...@pipe-b-ctm-0-25.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-wc-untiled:
- shard-snb: [PASS][21] -> [SKIP][22] ([fdo#109271]) +1 similar
issue
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-snb7/igt@kms_draw_...@draw-method-rgb565-mmap-wc-untiled.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15076/shard-snb4/igt@kms_draw_...@draw-method-rgb565-mmap-wc-untiled.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: [PASS][23] -> [INCOMPLETE][24] ([fdo#104108])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-skl4/igt@kms_fbcon_...@psr-suspend.html
[24]:
[Intel-gfx] [CI] drm/i915/selftests: Spin on all engines simultaneously
Vanshidhar Konda asked for the simplest test "to verify that the kernel
can submit and hardware can execute batch buffers on all the command
streamers in parallel." We have a number of tests in userspace that
submit load to each engine and verify that it is present, but strictly
we have no selftest to prove that the kernel can _simultaneously_
execute on all known engines. (We have tests to demonstrate that we can
submit to HW in parallel, but we don't insist that they execute in
parallel.)
v2: Improve the igt_spinner support for older gen.
Suggested-by: Vanshidhar Konda
Signed-off-by: Chris Wilson
Cc: Vanshidhar Konda
Cc: Matthew Auld
Reviewed-by: Vanshidhar Konda
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/selftests/i915_request.c | 76 +++
drivers/gpu/drm/i915/selftests/igt_spinner.c | 36 ++---
3 files changed, 109 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a22d969cb352..0c3ab6020bc6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -891,6 +891,10 @@ struct intel_cdclk_state {
u8 voltage_level;
};
+struct i915_selftest_stash {
+ atomic_t counter;
+};
+
struct drm_i915_private {
struct drm_device drm;
@@ -1286,6 +1290,8 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
+
/*
* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
* will be rejected. Instead look for a better place.
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 30ae34f62176..4efc24c3eed7 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -32,6 +32,7 @@
#include "i915_random.h"
#include "i915_selftest.h"
#include "igt_live_test.h"
+#include "igt_spinner.h"
#include "lib_sw_fence.h"
#include "mock_drm.h"
@@ -1115,12 +1116,85 @@ static int __live_parallel_engineN(void *arg)
return 0;
}
+static bool wake_all(struct drm_i915_private *i915)
+{
+ if (atomic_dec_and_test(>selftest.counter)) {
+ wake_up_var(>selftest.counter);
+ return true;
+ }
+
+ return false;
+}
+
+static int wait_for_all(struct drm_i915_private *i915)
+{
+ if (wake_all(i915))
+ return 0;
+
+ if (wait_var_event_timeout(>selftest.counter,
+ !atomic_read(>selftest.counter),
+ i915_selftest.timeout_jiffies))
+ return 0;
+
+ return -ETIME;
+}
+
+static int __live_parallel_spin(void *arg)
+{
+ struct intel_engine_cs *engine = arg;
+ struct igt_spinner spin;
+ struct i915_request *rq;
+ int err = 0;
+
+ /*
+* Create a spinner running for eternity on each engine. If a second
+* spinner is incorrectly placed on the same engine, it will not be
+* able to start in time.
+*/
+
+ if (igt_spinner_init(, engine->gt)) {
+ wake_all(engine->i915);
+ return -ENOMEM;
+ }
+
+ rq = igt_spinner_create_request(,
+ engine->kernel_context,
+ MI_NOOP); /* no preemption */
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ if (err == -ENODEV)
+ err = 0;
+ wake_all(engine->i915);
+ goto out_spin;
+ }
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (igt_wait_for_spinner(, rq)) {
+ /* Occupy this engine for the whole test */
+ err = wait_for_all(engine->i915);
+ } else {
+ pr_err("Failed to start spinner on %s\n", engine->name);
+ err = -EINVAL;
+ }
+ igt_spinner_end();
+
+ if (err == 0 && i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+
+out_spin:
+ igt_spinner_fini();
+ return err;
+}
+
static int live_parallel_engines(void *arg)
{
struct drm_i915_private *i915 = arg;
static int (* const func[])(void *arg) = {
__live_parallel_engine1,
__live_parallel_engineN,
+ __live_parallel_spin,
NULL,
};
const unsigned int nengines = num_uabi_engines(i915);
@@ -1146,6 +1220,8 @@ static int live_parallel_engines(void *arg)
if (err)
break;
+ atomic_set(>selftest.counter, nengines);
+
idx = 0;
for_each_uabi_engine(engine, i915) {
tsk[idx] = kthread_run(*fn, engine,
diff --git
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/fbdev: Fallback to non tiled mode if all tiles not present
== Series Details == Series: drm/fbdev: Fallback to non tiled mode if all tiles not present URL : https://patchwork.freedesktop.org/series/68838/ State : warning == Summary == $ dim checkpatch origin/drm-tip 64383a27c565 drm/fbdev: Fallback to non tiled mode if all tiles not present -:62: ERROR:SPACING: space prohibited before that '++' (ctx:WxO) #62: FILE: drivers/gpu/drm/drm_client_modeset.c:373: + num_tiled_conns ++; ^ total: 1 errors, 0 warnings, 0 checks, 49 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Spin on all engines simultaneously (rev2)
== Series Details == Series: drm/i915/selftests: Spin on all engines simultaneously (rev2) URL : https://patchwork.freedesktop.org/series/68836/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7234 -> Patchwork_15094 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15094 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15094, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15094/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15094: ### IGT changes ### Possible regressions * igt@i915_selftest@live_requests: - fi-byt-n2820: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-byt-n2820/igt@i915_selftest@live_requests.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15094/fi-byt-n2820/igt@i915_selftest@live_requests.html - fi-ivb-3770:[PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-ivb-3770/igt@i915_selftest@live_requests.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15094/fi-ivb-3770/igt@i915_selftest@live_requests.html - fi-hsw-4770:[PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-hsw-4770/igt@i915_selftest@live_requests.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15094/fi-hsw-4770/igt@i915_selftest@live_requests.html - fi-elk-e7500: [PASS][7] -> [DMESG-FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-elk-e7500/igt@i915_selftest@live_requests.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15094/fi-elk-e7500/igt@i915_selftest@live_requests.html - fi-ilk-650: [PASS][9] -> [DMESG-FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-ilk-650/igt@i915_selftest@live_requests.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15094/fi-ilk-650/igt@i915_selftest@live_requests.html - fi-snb-2520m: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-snb-2520m/igt@i915_selftest@live_requests.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15094/fi-snb-2520m/igt@i915_selftest@live_requests.html - fi-snb-2600:[PASS][13] -> [DMESG-FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-snb-2600/igt@i915_selftest@live_requests.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15094/fi-snb-2600/igt@i915_selftest@live_requests.html Known issues Here are the changes found in Patchwork_15094 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_param@basic: - fi-bxt-dsi: [PASS][15] -> [INCOMPLETE][16] ([fdo#103927]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-bxt-dsi/igt@gem_ctx_pa...@basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15094/fi-bxt-dsi/igt@gem_ctx_pa...@basic.html * igt@gem_exec_reloc@basic-write-read-noreloc: - fi-icl-u3: [PASS][17] -> [DMESG-WARN][18] ([fdo#107724]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-icl-u3/igt@gem_exec_re...@basic-write-read-noreloc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15094/fi-icl-u3/igt@gem_exec_re...@basic-write-read-noreloc.html * igt@i915_selftest@live_requests: - fi-byt-j1900: [PASS][19] -> [INCOMPLETE][20] ([fdo#102657]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-byt-j1900/igt@i915_selftest@live_requests.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15094/fi-byt-j1900/igt@i915_selftest@live_requests.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][21] -> [FAIL][22] ([fdo#109483] / [fdo#109635 ]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15094/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html Possible fixes * igt@gem_busy@busy-all: - fi-icl-u3: [DMESG-WARN][23] ([fdo#107724]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7234/fi-icl-u3/igt@gem_b...@busy-all.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15094/fi-icl-u3/igt@gem_b...@busy-all.html * igt@gem_flink_basic@basic: - fi-icl-u3: [DMESG-WARN][25] ([fdo#107724] / [fdo#112052 ]) -> [PASS][26] [25]:
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Spin on all engines simultaneously
On Thu, Oct 31, 2019 at 09:23:36PM +, Chris Wilson wrote:
Vanshidhar Konda asked for the simplest test "to verify that the kernel
can submit and hardware can execute batch buffers on all the command
streamers in parallel." We have a number of tests in userspace that
submit load to each engine and verify that it is present, but strictly
we have no selftest to prove that the kernel can _simultaneously_
execute on all known engines. (We have tests to demonstrate that we can
submit to HW in parallel, but we don't insist that they execute in
parallel.)
Suggested-by: Vanshidhar Konda
Signed-off-by: Chris Wilson
Cc: Vanshidhar Konda
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/selftests/i915_request.c | 63 +++
2 files changed, 69 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a22d969cb352..0c3ab6020bc6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -891,6 +891,10 @@ struct intel_cdclk_state {
u8 voltage_level;
};
+struct i915_selftest_stash {
+ atomic_t counter;
+};
+
struct drm_i915_private {
struct drm_device drm;
@@ -1286,6 +1290,8 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
+
/*
* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
* will be rejected. Instead look for a better place.
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 30ae34f62176..6181b327b4ac 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -32,6 +32,7 @@
#include "i915_random.h"
#include "i915_selftest.h"
#include "igt_live_test.h"
+#include "igt_spinner.h"
#include "lib_sw_fence.h"
#include "mock_drm.h"
@@ -1115,12 +1116,72 @@ static int __live_parallel_engineN(void *arg)
return 0;
}
+static int wait_for_all(struct drm_i915_private *i915)
+{
+ if (atomic_dec_and_test(>selftest.counter)) {
+ wake_up_var(>selftest.counter);
+ return 0;
+ }
+
+ if (wait_var_event_timeout(>selftest.counter,
+ !atomic_read(>selftest.counter),
+ i915_selftest.timeout_jiffies))
+ return 0;
+
+ return -ETIME;
+}
+
+static int __live_parallel_spin(void *arg)
+{
+ struct intel_engine_cs *engine = arg;
+ struct igt_spinner spin;
+ struct i915_request *rq;
+ int err = 0;
+
+ /*
+* Create a spinner running for eternity on each engine. If a second
+* spinner is incorrectly placed on the same engine, it will not be
+* able to start in time.
+*/
+
+ if (igt_spinner_init(, engine->gt))
+ return -ENOMEM;
+
+ rq = igt_spinner_create_request(,
+ engine->kernel_context,
+ MI_NOOP); /* no preemption */
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_spin;
+ }
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (igt_wait_for_spinner(, rq)) {
+ /* Occupy this engine for the whole test */
+ err = wait_for_all(engine->i915);
+ } else {
+ pr_err("Failed to start spinner on %s\n", engine->name);
+ err = -EINVAL;
+ }
+ igt_spinner_end();
+
+ if (err == 0 && i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+
+out_spin:
+ igt_spinner_fini();
+ return err;
+}
+
static int live_parallel_engines(void *arg)
{
struct drm_i915_private *i915 = arg;
static int (* const func[])(void *arg) = {
__live_parallel_engine1,
__live_parallel_engineN,
+ __live_parallel_spin,
NULL,
};
const unsigned int nengines = num_uabi_engines(i915);
@@ -1146,6 +1207,8 @@ static int live_parallel_engines(void *arg)
if (err)
break;
+ atomic_set(>selftest.counter, nengines);
+
idx = 0;
for_each_uabi_engine(engine, i915) {
tsk[idx] = kthread_run(*fn, engine,
--
2.24.0.rc2
Reviewed-by: Vanshidhar Konda
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/fbdev: Fallback to non tiled mode if all tiles not present
In case of tiled displays, if we hotplug just one connector,
fbcon currently just selects the preferred mode and if it is
tiled mode then that becomes a problem if rest of the tiles are
not present.
So in the fbdev driver on hotplug when we probe the client modeset,
we we dont find all the connectors for all tiles, then on a connector
with one tile, just fallback to the first available non tiled mode
to display over a single connector.
Suggested-by: Ville Syrjälä
Suggested-by: Dave Airlie
Cc: Ville Syrjälä
Cc: Dave Airlie
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/drm_client_modeset.c | 29
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/drm_client_modeset.c
b/drivers/gpu/drm/drm_client_modeset.c
index 895b73f23079..e28a723587db 100644
--- a/drivers/gpu/drm/drm_client_modeset.c
+++ b/drivers/gpu/drm/drm_client_modeset.c
@@ -114,6 +114,20 @@ drm_client_find_modeset(struct drm_client_dev *client,
struct drm_crtc *crtc)
return NULL;
}
+static struct drm_display_mode *
+drm_connector_fallback_non_tiled_mode(struct drm_connector *connector)
+{
+ struct drm_display_mode *mode;
+
+ list_for_each_entry(mode, >modes, head) {
+ if (mode->hdisplay == connector->tile_h_size &&
+ mode->vdisplay == connector->tile_v_size)
+ continue;
+ return mode;
+ }
+ return NULL;
+}
+
static struct drm_display_mode *
drm_connector_has_preferred_mode(struct drm_connector *connector, int width,
int height)
{
@@ -348,8 +362,17 @@ static bool drm_client_target_preferred(struct
drm_connector **connectors,
struct drm_connector *connector;
u64 conn_configured = 0;
int tile_pass = 0;
+ int num_tiled_conns = 0;
int i;
+ for (i = 0; i < connector_count; i++) {
+ connector = connectors[i];
+ if (!connector->has_tile)
+ continue;
+
+ num_tiled_conns ++;
+ }
+
retry:
for (i = 0; i < connector_count; i++) {
connector = connectors[i];
@@ -394,6 +417,12 @@ static bool drm_client_target_preferred(struct
drm_connector **connectors,
connector->base.id, connector->tile_group
? connector->tile_group->id : 0);
modes[i] = drm_connector_has_preferred_mode(connector,
width, height);
}
+ if (connector->has_tile &&
+ num_tiled_conns < connector->num_h_tile *
connector->num_v_tile) {
+ DRM_DEBUG_KMS("Falling back to non tiled mode on
Connector %d\n",
+ connector->base.id);
+ modes[i] =
drm_connector_fallback_non_tiled_mode(connector);
+ }
/* No preferred modes, pick one off the list */
if (!modes[i] && !list_empty(>modes)) {
list_for_each_entry(modes[i], >modes, head)
--
2.19.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Spin on all engines simultaneously
Vanshidhar Konda asked for the simplest test "to verify that the kernel
can submit and hardware can execute batch buffers on all the command
streamers in parallel." We have a number of tests in userspace that
submit load to each engine and verify that it is present, but strictly
we have no selftest to prove that the kernel can _simultaneously_
execute on all known engines. (We have tests to demonstrate that we can
submit to HW in parallel, but we don't insist that they execute in
parallel.)
Suggested-by: Vanshidhar Konda
Signed-off-by: Chris Wilson
Cc: Vanshidhar Konda
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/selftests/i915_request.c | 63 +++
2 files changed, 69 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a22d969cb352..0c3ab6020bc6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -891,6 +891,10 @@ struct intel_cdclk_state {
u8 voltage_level;
};
+struct i915_selftest_stash {
+ atomic_t counter;
+};
+
struct drm_i915_private {
struct drm_device drm;
@@ -1286,6 +1290,8 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
+
/*
* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
* will be rejected. Instead look for a better place.
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 30ae34f62176..6181b327b4ac 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -32,6 +32,7 @@
#include "i915_random.h"
#include "i915_selftest.h"
#include "igt_live_test.h"
+#include "igt_spinner.h"
#include "lib_sw_fence.h"
#include "mock_drm.h"
@@ -1115,12 +1116,72 @@ static int __live_parallel_engineN(void *arg)
return 0;
}
+static int wait_for_all(struct drm_i915_private *i915)
+{
+ if (atomic_dec_and_test(>selftest.counter)) {
+ wake_up_var(>selftest.counter);
+ return 0;
+ }
+
+ if (wait_var_event_timeout(>selftest.counter,
+ !atomic_read(>selftest.counter),
+ i915_selftest.timeout_jiffies))
+ return 0;
+
+ return -ETIME;
+}
+
+static int __live_parallel_spin(void *arg)
+{
+ struct intel_engine_cs *engine = arg;
+ struct igt_spinner spin;
+ struct i915_request *rq;
+ int err = 0;
+
+ /*
+* Create a spinner running for eternity on each engine. If a second
+* spinner is incorrectly placed on the same engine, it will not be
+* able to start in time.
+*/
+
+ if (igt_spinner_init(, engine->gt))
+ return -ENOMEM;
+
+ rq = igt_spinner_create_request(,
+ engine->kernel_context,
+ MI_NOOP); /* no preemption */
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_spin;
+ }
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (igt_wait_for_spinner(, rq)) {
+ /* Occupy this engine for the whole test */
+ err = wait_for_all(engine->i915);
+ } else {
+ pr_err("Failed to start spinner on %s\n", engine->name);
+ err = -EINVAL;
+ }
+ igt_spinner_end();
+
+ if (err == 0 && i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+
+out_spin:
+ igt_spinner_fini();
+ return err;
+}
+
static int live_parallel_engines(void *arg)
{
struct drm_i915_private *i915 = arg;
static int (* const func[])(void *arg) = {
__live_parallel_engine1,
__live_parallel_engineN,
+ __live_parallel_spin,
NULL,
};
const unsigned int nengines = num_uabi_engines(i915);
@@ -1146,6 +1207,8 @@ static int live_parallel_engines(void *arg)
if (err)
break;
+ atomic_set(>selftest.counter, nengines);
+
idx = 0;
for_each_uabi_engine(engine, i915) {
tsk[idx] = kthread_run(*fn, engine,
--
2.24.0.rc2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Spin on all engines simultaneously
Vanshidhar Konda asked for the simplest test "to verify that the kernel
can submit and hardware can execute batch buffers on all the command
streamers in parallel." We have a number of tests in userspace that
submit load to each engine and verify that it is present, but strictly
we have no selftest to prove that the kernel can _simultaneously_
execute on all known engines. (We have tests to demonstrate that we can
submit to HW in parallel, but we don't insist that they execute in
parallel.)
Suggested-by: Vanshidhar Konda
Signed-off-by: Chris Wilson
Cc: Vanshidhar Konda
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/selftests/i915_request.c | 63 +++
2 files changed, 69 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a22d969cb352..0c3ab6020bc6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -891,6 +891,10 @@ struct intel_cdclk_state {
u8 voltage_level;
};
+struct i915_selftest_stash {
+ atomic_t counter;
+};
+
struct drm_i915_private {
struct drm_device drm;
@@ -1286,6 +1290,8 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
+
/*
* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
* will be rejected. Instead look for a better place.
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 30ae34f62176..191c4f8c35c9 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -32,6 +32,7 @@
#include "i915_random.h"
#include "i915_selftest.h"
#include "igt_live_test.h"
+#include "igt_spinner.h"
#include "lib_sw_fence.h"
#include "mock_drm.h"
@@ -1115,12 +1116,72 @@ static int __live_parallel_engineN(void *arg)
return 0;
}
+static int wait_for_all(struct drm_i915_private *i915)
+{
+ if (atomic_dec_and_test(>selftest.counter)) {
+ wake_up_var(>selftest.counter);
+ return 0;
+ }
+
+ if (!wait_var_event_timeout(>selftest.counter,
+ !atomic_read(>selftest.counter),
+ i915_selftest.timeout_jiffies))
+ return 0;
+
+ return -ETIME;
+}
+
+static int __live_parallel_spin(void *arg)
+{
+ struct intel_engine_cs *engine = arg;
+ struct igt_spinner spin;
+ struct i915_request *rq;
+ int err = 0;
+
+ /*
+* Create a spinner running for eternity on each engine. If a second
+* spinner is incorrectly placed on the same engine, it will not be
+* able to start in time.
+*/
+
+ if (igt_spinner_init(, engine->gt))
+ return -ENOMEM;
+
+ rq = igt_spinner_create_request(,
+ engine->kernel_context,
+ MI_NOOP); /* no preemption */
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_spin;
+ }
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (igt_wait_for_spinner(, rq)) {
+ /* Occupy this engine for the whole test */
+ err = wait_for_all(engine->i915);
+ } else {
+ pr_err("Failed to start spinner on %s\n", engine->name);
+ err = -EINVAL;
+ }
+ igt_spinner_end();
+
+ if (err == 0 && i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+
+out_spin:
+ igt_spinner_fini();
+ return err;
+}
+
static int live_parallel_engines(void *arg)
{
struct drm_i915_private *i915 = arg;
static int (* const func[])(void *arg) = {
__live_parallel_engine1,
__live_parallel_engineN,
+ __live_parallel_spin,
NULL,
};
const unsigned int nengines = num_uabi_engines(i915);
@@ -1146,6 +1207,8 @@ static int live_parallel_engines(void *arg)
if (err)
break;
+ atomic_set(>selftest.counter, nengines);
+
idx = 0;
for_each_uabi_engine(engine, i915) {
tsk[idx] = kthread_run(*fn, engine,
--
2.24.0.rc2
___
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Re: [Intel-gfx] [RESEND PATCH] drm/dp: Increase link status size
Whoops, replied to the wrong one
Reviewed-by: Lyude Paul
On Tue, 2019-10-29 at 15:03 +0100, Thierry Reding wrote:
> From: Thierry Reding
>
> The current link status contains bytes 0x202 through 0x207, but we also
> want to make sure to include the DP_ADJUST_REQUEST_POST_CURSOR2 (0x20c)
> so that the post-cursor adjustment can be queried during link training.
>
> Reported-by: coverity-bot
> Addresses-Coverity-ID: 1487366 ("Memory - corruptions")
> Fixes: 79465e0ffeb9 ("drm/dp: Add helper to get post-cursor adjustments")
> Signed-off-by: Thierry Reding
> ---
> include/drm/drm_dp_helper.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 51ecb5112ef8..9581dec900ba 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1121,7 +1121,7 @@
> #define DP_MST_PHYSICAL_PORT_0 0
> #define DP_MST_LOGICAL_PORT_0 8
>
> -#define DP_LINK_STATUS_SIZE 6
> +#define DP_LINK_STATUS_SIZE 11
> bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
> int lane_count);
> bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
--
Cheers,
Lyude Paul
___
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Re: [Intel-gfx] [PATCH] drm/i915/lmem: add the fake lmem region
Quoting Arkadiusz Hiler (2019-10-31 12:40:35) > On Wed, Oct 30, 2019 at 10:22:37PM +, Matthew Auld wrote: > > On Tue, 29 Oct 2019 at 16:51, Matthew Auld wrote: > > > > > > Intended for upstream testing so that we can still exercise the LMEM > > > plumbing and !i915_ggtt_has_aperture paths. Smoke tested on Skull Canyon > > > device. This works by allocating an intel_memory_region for a reserved > > > portion of system memory, which we treat like LMEM. For the LMEMBAR we > > > steal the aperture and 1:1 it map to the stolen region. > > > > > > To enable simply set the i915 modparam fake_lmem_start= on the kernel > > > cmdline with the start of reserved region(see memmap=). The size of the > > > region we can use is determined by the size of the mappable aperture, so > > > the size of reserved region should be >= mappable_end. For now we only > > > enable for the selftests. Depends on CONFIG_DRM_I915_UNSTABLE being > > > enabled. > > > > > > eg. memmap=2G$16G i915.fake_lmem_start=0x4 > > > > Hi Arek, > > > > Would you be able to update the fi-skl-lmem kernel cmd line with > > s/i915_fake_lmem_start/i915.fake_lmem_start? > > done <6>[ 497.897456] [drm] Intel graphics fake LMEM: [mem 0x1-0x13fff] <6>[ 497.897459] [drm] Intel graphics fake LMEM IO start: 4000 <6>[ 497.897461] [drm] Intel graphics fake LMEM size: 4000 All present. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/lmem: add the fake lmem region (rev2)
== Series Details ==
Series: drm/i915/lmem: add the fake lmem region (rev2)
URL : https://patchwork.freedesktop.org/series/68733/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7226_full -> Patchwork_15075_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_15075_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_plane@plane-position-covered-pipe-d-planes:
- {shard-tglb}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-tglb7/igt@kms_pl...@plane-position-covered-pipe-d-planes.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15075/shard-tglb2/igt@kms_pl...@plane-position-covered-pipe-d-planes.html
Known issues
Here are the changes found in Patchwork_15075_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +8
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-kbl3/igt@gem_ctx_isolat...@rcs0-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15075/shard-kbl6/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_ctx_isolation@vcs1-s3:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-iclb1/igt@gem_ctx_isolat...@vcs1-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15075/shard-iclb6/igt@gem_ctx_isolat...@vcs1-s3.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110841])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-iclb5/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15075/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +2 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-iclb5/igt@gem_exec_sched...@in-order-bsd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15075/shard-iclb1/igt@gem_exec_sched...@in-order-bsd.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-snb: [PASS][11] -> [FAIL][12] ([fdo#112037])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-snb6/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15075/shard-snb1/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-snb2/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15075/shard-snb2/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html
* igt@gem_wait@await-vcs1:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#112080]) +2 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-iclb1/igt@gem_w...@await-vcs1.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15075/shard-iclb6/igt@gem_w...@await-vcs1.html
* igt@i915_selftest@mock_requests:
- shard-skl: [PASS][17] -> [INCOMPLETE][18] ([fdo#112156])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-skl1/igt@i915_selftest@mock_requests.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15075/shard-skl6/igt@i915_selftest@mock_requests.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: [PASS][19] -> [FAIL][20] ([fdo#105363])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-glk9/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15075/shard-glk9/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +4 similar
issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7226/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-blt.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15075/shard-iclb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][23] -> [FAIL][24]
[Intel-gfx] [PULL] drm-misc-next
Hi Dave & Daniel, Here's the last -misc-next pull request for 5.5. Lots of refactoring going on this week which results in a negative diffstat. Only thing to highlight is the dma-buf heap introduction and revert, which you are already aware of, so hopefully no other surprises here. drm-misc-next-2019-10-31: drm-misc-next for 5.5: UAPI Changes: -dma-buf: Introduce and revert dma-buf heap (Andrew/John/Sean) Cross-subsystem Changes: - None Core Changes: -dma-buf: add dynamic mapping to allow exporters to choose dma_resv lock state on mmap/munmap (Christian) -vram: add prepare/cleanup fb helpers to vram helpers (Thomas) -ttm: always keep bo's on the lru + ttm cleanups (Christian) -sched: allow a free_job routine to sleep (Steven) -fb_helper: remove unused drm_fb_helper_defio_init() (Thomas) Driver Changes: -bochs/hibmc/vboxvideo: Use new vram helpers for prepare/cleanup fb (Thomas) -amdgpu: Implement dma-buf import/export without drm helpers (Christian) -panfrost: Simplify devfreq integration in driver (Steven) Cc: Christian König Cc: Thomas Zimmermann Cc: Steven Price Cc: Andrew F. Davis Cc: John Stultz Cc: Sean Paul Cheers, Sean The following changes since commit 9a42c7c647a9ad0f7ebb147a52eda3dcb7c84292: drm/tegra: Move drm_dp_link helpers to Tegra DRM (2019-10-23 18:22:10 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2019-10-31 for you to fetch changes up to fae7d7d5f374eadbb0b5dd31b39162e7176e9c3d: Revert "dma-buf: Add dma-buf heaps framework" (2019-10-30 16:41:49 -0400) drm-misc-next for 5.5: UAPI Changes: -dma-buf: Introduce and revert dma-buf heap (Andrew/John/Sean) Cross-subsystem Changes: - None Core Changes: -dma-buf: add dynamic mapping to allow exporters to choose dma_resv lock state on mmap/munmap (Christian) -vram: add prepare/cleanup fb helpers to vram helpers (Thomas) -ttm: always keep bo's on the lru + ttm cleanups (Christian) -sched: allow a free_job routine to sleep (Steven) -fb_helper: remove unused drm_fb_helper_defio_init() (Thomas) Driver Changes: -bochs/hibmc/vboxvideo: Use new vram helpers for prepare/cleanup fb (Thomas) -amdgpu: Implement dma-buf import/export without drm helpers (Christian) -panfrost: Simplify devfreq integration in driver (Steven) Cc: Christian König Cc: Thomas Zimmermann Cc: Steven Price Cc: Andrew F. Davis Cc: John Stultz Cc: Sean Paul Andrew F. Davis (1): dma-buf: Add dma-buf heaps framework Anna Karas (1): doc: drm: Update references to previously renamed files Bhanusree (3): drm/gpu: Add comment for memory barrier drm/gpu: Fix Missing blank line after declarations drm/gpu: Fix Memory barrier without comment Issue Christian König (10): dma-buf: change DMA-buf locking convention v3 dma-buf: stop using the dmabuf->lock so much v2 drm/ttm, drm/vmwgfx: move cpu_writers handling into vmwgfx drm/ttm: always keep BOs on the LRU drm/ttm: remove pointers to globals drm/ttm: use the parent resv for ghost objects v3 drm/qxl: stop using TTM to call driver internal functions drm/ttm: stop exporting ttm_mem_io_* functions drm/amdgpu: add independent DMA-buf export v8 drm/amdgpu: add independent DMA-buf import v9 Daniel Vetter (1): drm/simple-kms: Standardize arguments for callbacks Geert Uytterhoeven (1): drm: Spelling s/connet/connect/ Hans de Goede (1): drm/vboxvideo: Use drm_gem_fb_create_with_dirty instead of drm_gem_fb_create John Stultz (4): dma-buf: heaps: Add heap helpers dma-buf: heaps: Add system heap to dmabuf heaps dma-buf: heaps: Add CMA heap to dmabuf heaps kselftests: Add dma-heap test Rob Herring (1): drm/gem: Fix mmap fake offset handling for drm_gem_object_funcs.mmap Sean Paul (5): Revert "kselftests: Add dma-heap test" Revert "dma-buf: heaps: Add CMA heap to dmabuf heaps" Revert "dma-buf: heaps: Add system heap to dmabuf heaps" Revert "dma-buf: heaps: Add heap helpers" Revert "dma-buf: Add dma-buf heaps framework" Steven Price (3): drm: Don't free jobs in wait_event_interruptible() drm/panfrost: Use generic code for devfreq drm/panfrost: Simplify devfreq utilisation tracking Thomas Zimmermann (6): drm/vram-helpers: Add helpers for prepare_fb() and cleanup_fb() drm/bochs: Replace prepare_fb()/cleanup_fb() with GEM VRAM helpers drm/hisilicon/hibmc: Use GEM VRAM's prepare_fb() and cleanup_fb() helpers drm/vboxvideo: Replace prepare_fb()/cleanup_fb() with GEM VRAM helpers drm/fb-helper: Remove drm_fb_helper_defio_init() and update docs drm/todo: Clarify situation around fbdev and defio Wambui Karuga (1): drm/mediatek: remove cast to pointers passed to kfree
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Replace rcu_swap_protected() with rcu_replace_pointer()
== Series Details == Series: drm/i915: Replace rcu_swap_protected() with rcu_replace_pointer() URL : https://patchwork.freedesktop.org/series/68833/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h AR drivers/gpu/drm/i915/built-in.a CC [M] drivers/gpu/drm/i915/gem/i915_gem_context.o drivers/gpu/drm/i915/gem/i915_gem_context.c: In function ‘set_engines’: drivers/gpu/drm/i915/gem/i915_gem_context.c:1667:16: error: implicit declaration of function ‘rcu_replace_pointer’; did you mean ‘rb_replace_node’? [-Werror=implicit-function-declaration] set.engines = rcu_replace_pointer(ctx->engines, set.engines, 1); ^~~ rb_replace_node drivers/gpu/drm/i915/gem/i915_gem_context.c:1667:14: error: assignment makes pointer from integer without a cast [-Werror=int-conversion] set.engines = rcu_replace_pointer(ctx->engines, set.engines, 1); ^ cc1: all warnings being treated as errors scripts/Makefile.build:265: recipe for target 'drivers/gpu/drm/i915/gem/i915_gem_context.o' failed make[4]: *** [drivers/gpu/drm/i915/gem/i915_gem_context.o] Error 1 scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:509: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1649: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Expose more formats
== Series Details ==
Series: drm/i915: Expose more formats
URL : https://patchwork.freedesktop.org/series/68832/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7233 -> Patchwork_15092
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15092/index.html
Known issues
Here are the changes found in Patchwork_15092 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ringfill@basic-default:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7233/fi-icl-u3/igt@gem_ringf...@basic-default.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15092/fi-icl-u3/igt@gem_ringf...@basic-default.html
Possible fixes
* igt@gem_mmap_gtt@basic-small-bo-tiledy:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7233/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15092/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][5] ([fdo#111045] / [fdo#111096]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7233/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15092/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
Participating hosts (53 -> 45)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-tgl-u2 fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7233 -> Patchwork_15092
CI-20190529: 20190529
CI_DRM_7233: 1cdd3a3d9f5a2b0e0879d0d2468d4c88efdcda4f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5255: b21b6a7aaa0db2159f22ee4427804e5a16fe2261 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15092: e21cfa158d0f0507257ec37839c2a5912ec378b6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e21cfa158d0f drm/i915: Eliminate redundancy in intel_primary_plane_create()
a2d1c9390e49 drm/i915: Sort format arrays consistently
35629ab74c44 drm/i915: Add 10bpc formats with alpha for icl+
0cebeab39475 drm/i915: Expose C8 on VLV/CHV sprite planes
65f2c2a216ec drm/i915: Add missing 10bpc formats for pipe B sprites on CHV
8bb2c5008932 drm/i915: Expose alpha formats on VLV/CHV primary planes
a24c3ea05189 drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15092/index.html
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Skip MCHBAR queries on dgfx
== Series Details ==
Series: drm/i915: Skip MCHBAR queries on dgfx
URL : https://patchwork.freedesktop.org/series/68829/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7233 -> Patchwork_15091
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15091/index.html
Known issues
Here are the changes found in Patchwork_15091 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7233/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15091/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html
* igt@kms_busy@basic-flip-b:
- fi-skl-6600u: [PASS][3] -> [DMESG-WARN][4] ([fdo#106107])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7233/fi-skl-6600u/igt@kms_b...@basic-flip-b.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15091/fi-skl-6600u/igt@kms_b...@basic-flip-b.html
Possible fixes
* igt@gem_exec_create@basic:
- {fi-tgl-u2}:[INCOMPLETE][5] ([fdo#111736]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7233/fi-tgl-u2/igt@gem_exec_cre...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15091/fi-tgl-u2/igt@gem_exec_cre...@basic.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][7] ([fdo#111045] / [fdo#111096]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7233/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15091/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
Participating hosts (53 -> 45)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-icl-u3 fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7233 -> Patchwork_15091
CI-20190529: 20190529
CI_DRM_7233: 1cdd3a3d9f5a2b0e0879d0d2468d4c88efdcda4f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5255: b21b6a7aaa0db2159f22ee4427804e5a16fe2261 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15091: dcec0a01e85eb76b0e2ea2ed8cae0f014cbd5419 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
dcec0a01e85e drm/i915: Skip MCHBAR queries on dgfx
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15091/index.html
___
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: Do not switch aux to TBT mode for non-TC ports (rev2)
On Thu, 2019-10-31 at 05:38 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dp: Do not switch aux to TBT mode for non-TC ports
> (rev2)
> URL : https://patchwork.freedesktop.org/series/68691/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7221_full -> Patchwork_15062_full
>
>
> Summary
> ---
>
> **SUCCESS**
>
> No regressions found.
Thanks for the review Imre, pushed to dinq.
>
>
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_15062_full:
>
> ### IGT changes ###
>
> Suppressed
>
> The following results come from untrusted machines, tests, or
> statuses.
> They do not affect the overall result.
>
> * {igt@gem_ctx_persistence@vcs2-hostile}:
> - {shard-tglb}: NOTRUN -> [SKIP][1]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15062/shard-tglb6/igt@gem_ctx_persiste...@vcs2-hostile.html
>
> * {igt@gem_ctx_persistence@vecs0-queued}:
> - shard-apl: NOTRUN -> [FAIL][2]
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15062/shard-apl4/igt@gem_ctx_persiste...@vecs0-queued.html
>
> * igt@gem_exec_schedule@smoketest-vebox:
> - {shard-tglb}: [PASS][3] -> [INCOMPLETE][4] +2 similar
> issues
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-tglb7/igt@gem_exec_sched...@smoketest-vebox.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15062/shard-tglb6/igt@gem_exec_sched...@smoketest-vebox.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_15062_full that come from
> known issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_ctx_isolation@vcs0-s3:
> - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108])
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-skl6/igt@gem_ctx_isolat...@vcs0-s3.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15062/shard-skl2/igt@gem_ctx_isolat...@vcs0-s3.html
>
> * igt@gem_ctx_isolation@vcs1-clean:
> - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] /
> [fdo#112080])
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb1/igt@gem_ctx_isolat...@vcs1-clean.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15062/shard-iclb7/igt@gem_ctx_isolat...@vcs1-clean.html
>
> * igt@gem_eio@unwedge-stress:
> - shard-snb: [PASS][9] -> [FAIL][10] ([fdo#109661])
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-snb6/igt@gem_...@unwedge-stress.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15062/shard-snb2/igt@gem_...@unwedge-stress.html
>
> * igt@gem_exec_balancer@smoke:
> - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#110854])
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb1/igt@gem_exec_balan...@smoke.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15062/shard-iclb6/igt@gem_exec_balan...@smoke.html
>
> * igt@gem_exec_schedule@preemptive-hang-bsd:
> - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +3
> similar issues
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-iclb6/igt@gem_exec_sched...@preemptive-hang-bsd.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15062/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html
>
> * igt@gem_softpin@noreloc-s3:
> - shard-apl: [PASS][15] -> [DMESG-WARN][16]
> ([fdo#108566]) +1 similar issue
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-apl4/igt@gem_soft...@noreloc-s3.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15062/shard-apl6/igt@gem_soft...@noreloc-s3.html
>
> * igt@gem_userptr_blits@dmabuf-unsync:
> - shard-hsw: [PASS][17] -> [DMESG-WARN][18]
> ([fdo#111870])
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-hsw1/igt@gem_userptr_bl...@dmabuf-unsync.html
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15062/shard-hsw5/igt@gem_userptr_bl...@dmabuf-unsync.html
>
> * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
> - shard-snb: [PASS][19] -> [DMESG-WARN][20]
> ([fdo#111870])
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-snb2/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
>[20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15062/shard-snb4/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding:
> - shard-apl: [PASS][21] -> [INCOMPLETE][22]
> ([fdo#103927]) +2 similar issues
>[21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7221/shard-apl8/igt@kms_cursor_...@pipe-a-cursor-256x85-sliding.html
>[22]:
>
Re: [Intel-gfx] [PATCH v2] kernel-doc: rename the kernel-doc directive 'functions' to 'identifiers'
On Tue, Oct 29, 2019 at 02:00:27AM -0600, Jonathan Corbet wrote: > On Tue, 29 Oct 2019 08:31:22 +0800 > Changbin Du wrote: > > > Here python is different from C. Both empty string and None are False in > > python. > > Note such condition is common in python. > > Treating both as a False value is reasonably common. Treating them > elsewhere in the same code block as separate values is less > so; that's the part I would prefer to avoid. > ok, please check update in v3. > Thanks, > > jon -- Cheers, Changbin Du ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [tip: core/rcu] drm/i915: Replace rcu_swap_protected() with rcu_replace_pointer()
The following commit has been merged into the core/rcu branch of tip: Commit-ID: 1feace5d6a4a1acf44dde2bfb5c36cc0b1cf559c Gitweb: https://git.kernel.org/tip/1feace5d6a4a1acf44dde2bfb5c36cc0b1cf559c Author:Paul E. McKenney AuthorDate:Mon, 23 Sep 2019 15:22:15 -07:00 Committer: Paul E. McKenney CommitterDate: Wed, 30 Oct 2019 08:44:04 -07:00 drm/i915: Replace rcu_swap_protected() with rcu_replace_pointer() This commit replaces the use of rcu_swap_protected() with the more intuitively appealing rcu_replace_pointer() as a step towards removing rcu_swap_protected(). Link: https://lore.kernel.org/lkml/CAHk-=wiAsJLw1egFEE=z7-ggtm6wcvtyytxza1+bhqta4gg...@mail.gmail.com/ Reported-by: Linus Torvalds [ paulmck: From rcu_replace() to rcu_replace_pointer() per Ingo Molnar. ] Signed-off-by: Paul E. McKenney Reviewed-by: Joonas Lahtinen Cc: Jani Nikula Cc: Rodrigo Vivi Cc: David Airlie Cc: Daniel Vetter Cc: Chris Wilson Cc: Tvrtko Ursulin Cc: Cc: --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 1cdfe05..3f3e803 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -1629,7 +1629,7 @@ replace: i915_gem_context_set_user_engines(ctx); else i915_gem_context_clear_user_engines(ctx); - rcu_swap_protected(ctx->engines, set.engines, 1); + set.engines = rcu_replace_pointer(ctx->engines, set.engines, 1); mutex_unlock(>engines_mutex); call_rcu(>rcu, free_engines_rcu); ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave and Daniel, Here goes drm-intel-fixes-2019-10-31: - Fix PCH reference clock for FDI on HSW/BDW which was causing users blank screen - Small documentation fix for TGL display PLLs Thanks, Rodrigo. The following changes since commit d6d5df1db6e9d7f8f76d2911707f7d5877251b02: Linux 5.4-rc5 (2019-10-27 13:19:19 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2019-10-31 for you to fetch changes up to 59cd826fb5e7889515bf5771e295e0624c348571: drm/i915: Fix PCH reference clock for FDI on HSW/BDW (2019-10-29 21:50:24 -0700) - Fix PCH reference clock for FDI on HSW/BDW which was causing users blank screen - Small documentation fix for TGL display PLLs Anna Karas (1): drm/i915/tgl: Fix doc not corresponding to code Ville Syrjälä (1): drm/i915: Fix PCH reference clock for FDI on HSW/BDW drivers/gpu/drm/i915/display/intel_display.c | 11 ++- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 15 +++ drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++-- drivers/gpu/drm/i915/i915_drv.h | 2 ++ 4 files changed, 25 insertions(+), 7 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH i-g-t v4 4/4] tests/gem_ctx_shared: Align objects using minimum GTT alignment
On Thu, Oct 31, 2019 at 04:28:57PM +0100, Janusz Krzysztofik wrote: exec-shared-gtt-* subtests use hardcoded values for object size and softpin offset, based on 4kB GTT alignment assumption. That may result in those subtests failing when run on future backing stores with possibly larger minimum page sizes. Replace hardcoded constants with values calculated from minimum GTT alignment of actual backing store the test is running on. v2: Update helper name, use 'minimum GTT alignment' term across the change, adjust variable name. Signed-off-by: Janusz Krzysztofik Cc: Chris Wilson --- tests/i915/gem_ctx_shared.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c index 6d8cbcce..1e9c7f78 100644 --- a/tests/i915/gem_ctx_shared.c +++ b/tests/i915/gem_ctx_shared.c @@ -195,6 +195,7 @@ static void exec_shared_gtt(int i915, unsigned int ring) uint32_t scratch, *s; uint32_t batch, cs[16]; uint64_t offset; + uint64_t alignment; int i; gem_require_ring(i915, ring); @@ -203,7 +204,8 @@ static void exec_shared_gtt(int i915, unsigned int ring) clone = gem_context_clone(i915, 0, I915_CONTEXT_CLONE_VM, 0); /* Find a hole big enough for both objects later */ - scratch = gem_create(i915, 16384); + alignment = 2 * gem_gtt_min_alignment(i915); + scratch = gem_create(i915, 2 * alignment); gem_write(i915, scratch, 0, , sizeof(bbe)); obj.handle = scratch; gem_execbuf(i915, ); @@ -246,7 +248,7 @@ static void exec_shared_gtt(int i915, unsigned int ring) gem_write(i915, batch, 0, cs, sizeof(cs)); obj.handle = batch; - obj.offset += 8192; /* make sure we don't cause an eviction! */ + obj.offset += alignment; /* make sure we don't cause an eviction! */ execbuf.rsvd1 = clone; if (gen > 3 && gen < 6) execbuf.flags |= I915_EXEC_SECURE; -- 2.21.0 Looks good to me. Vanshi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH i-g-t v4 1/4] tests/gem_exec_reloc: Don't filter out invalid addresses
May be this patch can just be merged with the other patch in this series
that changes gem_exec_reloc.
Vanshi
On Thu, Oct 31, 2019 at 04:28:54PM +0100, Janusz Krzysztofik wrote:
Commit a355b2d6eb42 ("igt/gem_exec_reloc: Filter out unavailable
addresses for !ppgtt") introduced filtering of addresses possibly
occupied by other users of shared GTT. Unfortunately, that filtering
doesn't distinguish between actually occupied addresses and otherwise
invalid softpin offsets. As soon as incorrect GTT alignment is assumed
when running on future backends with possibly larger minimum page
sizes, a half of calculated offsets to be tested will be incorrectly
detected as occupied by other users and silently skipped instead of
reported as a problem. That will significantly distort the intended
test pattern.
Filter out failing addresses only if not reported as invalid.
v2: Skip unavailable addresses only when not running on full PPGTT.
v3: Replace the not on full PPGTT requirement for skipping with error
code checking.
Signed-off-by: Janusz Krzysztofik
Cc: Chris Wilson
---
tests/i915/gem_exec_reloc.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c
index 5f59fe99..423fed8b 100644
--- a/tests/i915/gem_exec_reloc.c
+++ b/tests/i915/gem_exec_reloc.c
@@ -520,7 +520,7 @@ static void basic_range(int fd, unsigned flags)
uint64_t gtt_size = gem_aperture_size(fd);
const uint32_t bbe = MI_BATCH_BUFFER_END;
igt_spin_t *spin = NULL;
- int count, n;
+ int count, n, err;
igt_require(gem_has_softpin(fd));
@@ -542,8 +542,11 @@ static void basic_range(int fd, unsigned flags)
gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
execbuf.buffers_ptr = to_user_pointer([n]);
execbuf.buffer_count = 1;
- if (__gem_execbuf(fd, ))
+ err = __gem_execbuf(fd, );
+ if (err) {
+ igt_assert(err != -EINVAL);
continue;
+ }
igt_debug("obj[%d] handle=%d, address=%llx\n",
n, obj[n].handle, (long long)obj[n].offset);
@@ -562,8 +565,11 @@ static void basic_range(int fd, unsigned flags)
gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
execbuf.buffers_ptr = to_user_pointer([n]);
execbuf.buffer_count = 1;
- if (__gem_execbuf(fd, ))
+ err = __gem_execbuf(fd, );
+ if (err) {
+ igt_assert(err != -EINVAL);
continue;
+ }
igt_debug("obj[%d] handle=%d, address=%llx\n",
n, obj[n].handle, (long long)obj[n].offset);
--
2.21.0
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Re: [Intel-gfx] [RFC PATCH i-g-t v4 2/4] lib: Add minimum GTT alignment helper
On Thu, Oct 31, 2019 at 04:28:55PM +0100, Janusz Krzysztofik wrote:
Some tests assume 4kB offset alignment while using softpin. That
assumption may be wrong on future GEM backends with possibly larger
minimum page sizes. As a result, those tests may either fail on
softpin at offsets which are incorrectly aligned, may silently skip
such incorrectly aligned addresses assuming them occupied by other
users if incorrect detection method is used, or may always succeed
when examining invalid use patterns.
Provide a helper function that detects minimum GTT alignment. Tests
may use it to calculate softpin offsets valid for actually used backing
store.
v2: Rename the helper, use 'minimum GTT alignment' term across the
change (Chris),
- use error numbers to distinguish between invalid offsets and
addresses occupied by other users, then
- simplify the code (Chris).
Signed-off-by: Janusz Krzysztofik
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Stuart Summers
---
lib/ioctl_wrappers.c | 46
lib/ioctl_wrappers.h | 2 ++
2 files changed, 48 insertions(+)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 628f8b83..f0ef8b2e 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -54,6 +54,7 @@
#include "intel_io.h"
#include "igt_debugfs.h"
#include "igt_sysfs.h"
+#include "igt_x86.h"
#include "config.h"
#ifdef HAVE_VALGRIND
@@ -1158,6 +1159,51 @@ bool gem_has_softpin(int fd)
return has_softpin;
}
+/**
+ * gem_gtt_min_alignment_order:
+ * @fd: open i915 drm file descriptor
+ *
+ * This function detects the minimum possible alignment of a soft-pinned gem
+ * object allocated from a default backing store. It is useful for calculating
+ * correctly aligned softpin offsets.
+ * Since size order to size conversion (size = 1 << order) is less trivial
+ * than the opposite, the function returns the alignment order as more handy.
+ *
+ * Returns:
+ * Size order of the minimum GTT alignment
+ */
+int gem_gtt_min_alignment_order(int fd)
+{
+ struct drm_i915_gem_exec_object2 obj;
+ struct drm_i915_gem_execbuffer2 eb;
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ int order;
+
+ /* no softpin => 4kB page size */
+ if (!gem_has_softpin(fd))
+ return 12;
+
+ memset(, 0, sizeof(obj));
+ memset(, 0, sizeof(eb));
+
+ obj.handle = gem_create(fd, 4096);
+ obj.flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ eb.buffers_ptr = to_user_pointer();
+ eb.buffer_count = 1;
+ gem_write(fd, obj.handle, 0, , sizeof(bbe));
I think it will be safer to create a new context to execute this
execbuffer. For a new context the address space should be empty reducing
the chance that there is another object mapped by the caller of the
helper function at the address we start testing.
Otherwise it looks good to me.
Vanshi
+
+ for (order = 12; order < 64; order++) {
+ obj.offset = 1ull << order;
+ if (__gem_execbuf(fd, ) != -EINVAL)
+ break;
+ }
+ igt_assert(obj.offset < gem_aperture_size(fd));
+
+ gem_close(fd, obj.handle);
+ igt_debug("minimum GTT alignment is %#llx\n", (long long)obj.offset);
+ return order;
+}
+
/**
* gem_has_exec_fence:
* @fd: open i915 drm file descriptor
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 03211c97..c8d57a7c 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -138,6 +138,8 @@ uint64_t gem_aperture_size(int fd);
uint64_t gem_global_aperture_size(int fd);
uint64_t gem_mappable_aperture_size(void);
bool gem_has_softpin(int fd);
+int gem_gtt_min_alignment_order(int fd);
+#define gem_gtt_min_alignment(fd) (1ull << gem_gtt_min_alignment_order(fd))
bool gem_has_exec_fence(int fd);
/* check functions which auto-skip tests by calling igt_skip() */
--
2.21.0
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Perform some basic cycle counting of MI ops (rev2)
== Series Details == Series: drm/i915/selftests: Perform some basic cycle counting of MI ops (rev2) URL : https://patchwork.freedesktop.org/series/68824/ State : success == Summary == CI Bug Log - changes from CI_DRM_7231 -> Patchwork_15090 Summary --- **WARNING** Minor unknown changes coming with Patchwork_15090 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15090, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15090: ### IGT changes ### Warnings * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [SKIP][1] ([fdo#109271]) -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/fi-kbl-guc/igt@i915_pm_...@basic-rte.html New tests - New tests have been introduced between CI_DRM_7231 and Patchwork_15090: ### New IGT tests (1) ### * igt@i915_selftest@live_gt_engine_cs: - Statuses : 43 pass(s) - Exec time: [0.40, 1.43] s Known issues Here are the changes found in Patchwork_15090 that come from known issues: ### IGT changes ### Issues hit * igt@gem_render_linear_blits@basic: - fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/fi-icl-u3/igt@gem_render_linear_bl...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/fi-icl-u3/igt@gem_render_linear_bl...@basic.html Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7231/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 Participating hosts (52 -> 45) -- Additional (1): fi-tgl-u Missing(8): fi-ilk-m540 fi-hsw-4200u fi-tgl-u2 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7231 -> Patchwork_15090 CI-20190529: 20190529 CI_DRM_7231: 9c304eaf3dae009ccb96d56eca58a81837303fc6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5255: b21b6a7aaa0db2159f22ee4427804e5a16fe2261 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15090: c08fccd51739d9ca8ca7adaccad4054c0052f744 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c08fccd51739 drm/i915/selftests: Perform some basic cycle counting of MI ops == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15090/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/7] drm/i915: Add missing 10bpc formats for pipe B sprites on CHV
From: Ville Syrjälä
CHV pipe B sprites gained support for the 10bpc X/ARGB pixel formats.
On VLV and CHV pipe A/C these are only supported by the primary
plane. Add the require bits to expose the new formats.
v2: Reorder the formats for consistency
Signed-off-by: Ville Syrjälä
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_sprite.c | 33 +++--
drivers/gpu/drm/i915/i915_reg.h | 14 +
2 files changed, 39 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 514b620378d5..150ad367cf9e 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -987,6 +987,12 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_ABGR2101010:
sprctl |= SP_FORMAT_RGBA1010102;
break;
+ case DRM_FORMAT_XRGB2101010:
+ sprctl |= SP_FORMAT_BGRX1010102;
+ break;
+ case DRM_FORMAT_ARGB2101010:
+ sprctl |= SP_FORMAT_BGRA1010102;
+ break;
case DRM_FORMAT_XBGR:
sprctl |= SP_FORMAT_RGBX;
break;
@@ -2411,6 +2417,22 @@ static const u32 vlv_plane_formats[] = {
DRM_FORMAT_VYUY,
};
+static const u32 chv_pipe_b_sprite_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+};
+
static const u32 skl_plane_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
@@ -2643,6 +2665,8 @@ static bool vlv_sprite_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_XRGB:
case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_ARGB2101010:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
@@ -3041,8 +3065,13 @@ intel_sprite_plane_create(struct drm_i915_private
*dev_priv,
plane->check_plane = vlv_sprite_check;
plane->min_cdclk = vlv_plane_min_cdclk;
- formats = vlv_plane_formats;
- num_formats = ARRAY_SIZE(vlv_plane_formats);
+ if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
+ formats = chv_pipe_b_sprite_formats;
+ num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats);
+ } else {
+ formats = vlv_plane_formats;
+ num_formats = ARRAY_SIZE(vlv_plane_formats);
+ }
modifiers = i9xx_plane_format_modifiers;
plane_funcs = _sprite_funcs;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b819392ba700..78dfdcfc724a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6628,12 +6628,14 @@ enum {
#define SP_ENABLE(1 << 31)
#define SP_GAMMA_ENABLE (1 << 30)
#define SP_PIXFORMAT_MASK(0xf << 26)
-#define SP_FORMAT_YUV422 (0 << 26)
-#define SP_FORMAT_BGR565 (5 << 26)
-#define SP_FORMAT_BGRX (6 << 26)
-#define SP_FORMAT_BGRA (7 << 26)
-#define SP_FORMAT_RGBX1010102(8 << 26)
-#define SP_FORMAT_RGBA1010102(9 << 26)
+#define SP_FORMAT_YUV422 (0x0 << 26)
+#define SP_FORMAT_BGR565 (0x5 << 26)
+#define SP_FORMAT_BGRX (0x6 << 26)
+#define SP_FORMAT_BGRA (0x7 << 26)
+#define SP_FORMAT_RGBX1010102(0x8 << 26)
+#define SP_FORMAT_RGBA1010102(0x9 << 26)
+#define SP_FORMAT_BGRX1010102(0xa << 26) /* CHV pipe B */
+#define SP_FORMAT_BGRA1010102(0xb << 26) /* CHV pipe B */
#define SP_FORMAT_RGBX (0xe << 26)
#define SP_FORMAT_RGBA (0xf << 26)
#define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
--
2.23.0
___
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[Intel-gfx] [PATCH 6/7] drm/i915: Sort format arrays consistently
From: Ville Syrjälä
Let's try to keep the pixel format arrays somewhat sorted:
1. RGB before YUV
2. smaller bpp before larger bpp
3. X before A
4. RGB before BGR
Signed-off-by: Ville Syrjälä
Reviewed-by: Juha-Pekka Heikkila
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index aba2381716d3..9cf6b13f79fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -85,8 +85,8 @@
/* Primary plane formats for gen <= 3 */
static const u32 i8xx_primary_formats[] = {
DRM_FORMAT_C8,
- DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB,
};
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 73cb3e13657f..92c04dc72b00 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2409,10 +2409,10 @@ static const u32 snb_plane_formats[] = {
static const u32 vlv_plane_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
- DRM_FORMAT_ABGR,
- DRM_FORMAT_ARGB,
- DRM_FORMAT_XBGR,
DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
DRM_FORMAT_XBGR2101010,
DRM_FORMAT_ABGR2101010,
DRM_FORMAT_YUYV,
--
2.23.0
___
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[Intel-gfx] [PATCH 5/7] drm/i915: Add 10bpc formats with alpha for icl+
From: Ville Syrjälä
ICL+ again supports alpha blending with 10bpc pixel formats.
Expose them.
v2: Add all the stuff I missed earlier!
Signed-off-by: Ville Syrjälä
Reviewed-by: Juha-Pekka Heikkila
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_display.c | 19 +++
drivers/gpu/drm/i915/display/intel_sprite.c | 10 ++
2 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 27fb24c1892f..aba2381716d3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3053,10 +3053,17 @@ int skl_format_to_fourcc(int format, bool rgb_order,
bool alpha)
return DRM_FORMAT_XRGB;
}
case PLANE_CTL_FORMAT_XRGB_2101010:
- if (rgb_order)
- return DRM_FORMAT_XBGR2101010;
- else
- return DRM_FORMAT_XRGB2101010;
+ if (rgb_order) {
+ if (alpha)
+ return DRM_FORMAT_ABGR2101010;
+ else
+ return DRM_FORMAT_XBGR2101010;
+ } else {
+ if (alpha)
+ return DRM_FORMAT_ARGB2101010;
+ else
+ return DRM_FORMAT_XRGB2101010;
+ }
case PLANE_CTL_FORMAT_XRGB_16161616F:
if (rgb_order) {
if (alpha)
@@ -4101,8 +4108,10 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
case DRM_FORMAT_ARGB:
return PLANE_CTL_FORMAT_XRGB_;
case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ABGR2101010:
return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_ARGB2101010:
return PLANE_CTL_FORMAT_XRGB_2101010;
case DRM_FORMAT_XBGR16161616F:
case DRM_FORMAT_ABGR16161616F:
@@ -5704,6 +5713,8 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_ARGB:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 5b329ced63eb..73cb3e13657f 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2503,6 +2503,8 @@ static const u32 icl_sdr_y_plane_formats[] = {
DRM_FORMAT_ABGR,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
@@ -2524,6 +2526,8 @@ static const u32 icl_sdr_uv_plane_formats[] = {
DRM_FORMAT_ABGR,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
@@ -2549,6 +2553,8 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_ABGR,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
DRM_FORMAT_XRGB16161616F,
DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_ARGB16161616F,
@@ -2717,6 +2723,8 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_RGB565:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
@@ -2769,6 +2777,8 @@ static bool gen12_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_RGB565:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
--
2.23.0
___
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[Intel-gfx] [PATCH 2/7] drm/i915: Expose alpha formats on VLV/CHV primary planes
From: Ville Syrjälä
Currently we expose VLV/CHV alpha blending only on the sprite
planes, but the primary planes can do it as well. Let's flip
it on.
v2: Rebase due to fp16 landing
Signed-off-by: Ville Syrjälä
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_display.c | 62 +++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 60 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 348ce0456696..27fb24c1892f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -111,6 +111,21 @@ static const u32 i965_primary_formats[] = {
DRM_FORMAT_XBGR16161616F,
};
+/* Primary plane formats for vlv/chv */
+static const u32 vlv_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_XBGR16161616F,
+};
+
static const u64 i9xx_format_modifiers[] = {
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2971,6 +2986,8 @@ static int i9xx_format_to_fourcc(int format)
switch (format) {
case DISPPLANE_8BPP:
return DRM_FORMAT_C8;
+ case DISPPLANE_BGRA555:
+ return DRM_FORMAT_ARGB1555;
case DISPPLANE_BGRX555:
return DRM_FORMAT_XRGB1555;
case DISPPLANE_BGRX565:
@@ -2980,10 +2997,18 @@ static int i9xx_format_to_fourcc(int format)
return DRM_FORMAT_XRGB;
case DISPPLANE_RGBX888:
return DRM_FORMAT_XBGR;
+ case DISPPLANE_BGRA888:
+ return DRM_FORMAT_ARGB;
+ case DISPPLANE_RGBA888:
+ return DRM_FORMAT_ABGR;
case DISPPLANE_BGRX101010:
return DRM_FORMAT_XRGB2101010;
case DISPPLANE_RGBX101010:
return DRM_FORMAT_XBGR2101010;
+ case DISPPLANE_BGRA101010:
+ return DRM_FORMAT_ARGB2101010;
+ case DISPPLANE_RGBA101010:
+ return DRM_FORMAT_ABGR2101010;
case DISPPLANE_RGBX161616:
return DRM_FORMAT_XBGR16161616F;
}
@@ -3707,6 +3732,9 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_XRGB1555:
dspcntr |= DISPPLANE_BGRX555;
break;
+ case DRM_FORMAT_ARGB1555:
+ dspcntr |= DISPPLANE_BGRA555;
+ break;
case DRM_FORMAT_RGB565:
dspcntr |= DISPPLANE_BGRX565;
break;
@@ -3716,12 +3744,24 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_XBGR:
dspcntr |= DISPPLANE_RGBX888;
break;
+ case DRM_FORMAT_ARGB:
+ dspcntr |= DISPPLANE_BGRA888;
+ break;
+ case DRM_FORMAT_ABGR:
+ dspcntr |= DISPPLANE_RGBA888;
+ break;
case DRM_FORMAT_XRGB2101010:
dspcntr |= DISPPLANE_BGRX101010;
break;
case DRM_FORMAT_XBGR2101010:
dspcntr |= DISPPLANE_RGBX101010;
break;
+ case DRM_FORMAT_ARGB2101010:
+ dspcntr |= DISPPLANE_BGRA101010;
+ break;
+ case DRM_FORMAT_ABGR2101010:
+ dspcntr |= DISPPLANE_RGBA101010;
+ break;
case DRM_FORMAT_XBGR16161616F:
dspcntr |= DISPPLANE_RGBX161616;
break;
@@ -15219,8 +15259,12 @@ static bool i965_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_RGB565:
case DRM_FORMAT_XRGB:
case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ARGB:
+ case DRM_FORMAT_ABGR:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_ABGR2101010:
case DRM_FORMAT_XBGR16161616F:
return modifier == DRM_FORMAT_MOD_LINEAR ||
modifier == I915_FORMAT_MOD_X_TILED;
@@ -15441,7 +15485,20 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
}
- if (INTEL_GEN(dev_priv) >= 4) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ formats = vlv_primary_formats;
+ num_formats = ARRAY_SIZE(vlv_primary_formats);
+ modifiers = i9xx_format_modifiers;
+
+ plane->max_stride = i9xx_plane_max_stride;
+ plane->update_plane = i9xx_update_plane;
+ plane->disable_plane = i9xx_disable_plane;
+
[Intel-gfx] [PATCH 0/7] drm/i915: Expose more formats
From: Ville Syrjälä Same series as before but fp16 caused a bunch of rebasing. I also dropped the ckey stuff for now. It's probably time to write actual tests for that stuff. Everything here is reviewed already. Ville Syrjälä (7): drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites drm/i915: Expose alpha formats on VLV/CHV primary planes drm/i915: Add missing 10bpc formats for pipe B sprites on CHV drm/i915: Expose C8 on VLV/CHV sprite planes drm/i915: Add 10bpc formats with alpha for icl+ drm/i915: Sort format arrays consistently drm/i915: Eliminate redundancy in intel_primary_plane_create() drivers/gpu/drm/i915/display/intel_display.c | 121 +-- drivers/gpu/drm/i915/display/intel_sprite.c | 69 ++- drivers/gpu/drm/i915/i915_reg.h | 16 ++- 3 files changed, 161 insertions(+), 45 deletions(-) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/7] drm/i915: Expose C8 on VLV/CHV sprite planes
From: Ville Syrjälä
VLV/CHV sprite planes also support the C8 format. Let's expose that.
Signed-off-by: Ville Syrjälä
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 150ad367cf9e..5b329ced63eb 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -972,6 +972,9 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_VYUY:
sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
break;
+ case DRM_FORMAT_C8:
+ sprctl |= SP_FORMAT_8BPP;
+ break;
case DRM_FORMAT_RGB565:
sprctl |= SP_FORMAT_BGR565;
break;
@@ -2404,6 +2407,7 @@ static const u32 snb_plane_formats[] = {
};
static const u32 vlv_plane_formats[] = {
+ DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
DRM_FORMAT_ABGR,
DRM_FORMAT_ARGB,
@@ -2418,6 +2422,7 @@ static const u32 vlv_plane_formats[] = {
};
static const u32 chv_pipe_b_sprite_formats[] = {
+ DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB,
DRM_FORMAT_XBGR,
@@ -2658,6 +2663,7 @@ static bool vlv_sprite_format_mod_supported(struct
drm_plane *_plane,
}
switch (format) {
+ case DRM_FORMAT_C8:
case DRM_FORMAT_RGB565:
case DRM_FORMAT_ABGR:
case DRM_FORMAT_ARGB:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 78dfdcfc724a..a607ea520829 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6629,6 +6629,7 @@ enum {
#define SP_GAMMA_ENABLE (1 << 30)
#define SP_PIXFORMAT_MASK(0xf << 26)
#define SP_FORMAT_YUV422 (0x0 << 26)
+#define SP_FORMAT_8BPP (0x2 << 26)
#define SP_FORMAT_BGR565 (0x5 << 26)
#define SP_FORMAT_BGRX (0x6 << 26)
#define SP_FORMAT_BGRA (0x7 << 26)
--
2.23.0
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[Intel-gfx] [PATCH 7/7] drm/i915: Eliminate redundancy in intel_primary_plane_create()
From: Ville Syrjälä
Lots of redundant assignments inside intel_primary_plane_create().
Get rid of them.
v2: Rebase due to fp16 landing
Signed-off-by: Ville Syrjälä
Reviewed-by: Juha-Pekka Heikkila
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_display.c | 60 +++-
1 file changed, 22 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9cf6b13f79fe..12e4e7ef1a34 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15464,7 +15464,6 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
const struct drm_plane_funcs *plane_funcs;
unsigned int supported_rotations;
unsigned int possible_crtcs;
- const u64 *modifiers;
const u32 *formats;
int num_formats;
int ret, zpos;
@@ -15499,16 +15498,6 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
formats = vlv_primary_formats;
num_formats = ARRAY_SIZE(vlv_primary_formats);
- modifiers = i9xx_format_modifiers;
-
- plane->max_stride = i9xx_plane_max_stride;
- plane->update_plane = i9xx_update_plane;
- plane->disable_plane = i9xx_disable_plane;
- plane->get_hw_state = i9xx_plane_get_hw_state;
- plane->check_plane = i9xx_plane_check;
- plane->min_cdclk = vlv_plane_min_cdclk;
-
- plane_funcs = _plane_funcs;
} else if (INTEL_GEN(dev_priv) >= 4) {
/*
* WaFP16GammaEnabling:ivb
@@ -15530,50 +15519,45 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
formats = i965_primary_formats;
num_formats = ARRAY_SIZE(i965_primary_formats);
}
-
- modifiers = i9xx_format_modifiers;
-
- plane->max_stride = i9xx_plane_max_stride;
- plane->update_plane = i9xx_update_plane;
- plane->disable_plane = i9xx_disable_plane;
- plane->get_hw_state = i9xx_plane_get_hw_state;
- plane->check_plane = i9xx_plane_check;
-
- if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
- plane->min_cdclk = hsw_plane_min_cdclk;
- else if (IS_IVYBRIDGE(dev_priv))
- plane->min_cdclk = ivb_plane_min_cdclk;
- else
- plane->min_cdclk = i9xx_plane_min_cdclk;
-
- plane_funcs = _plane_funcs;
} else {
formats = i8xx_primary_formats;
num_formats = ARRAY_SIZE(i8xx_primary_formats);
- modifiers = i9xx_format_modifiers;
+ }
- plane->max_stride = i9xx_plane_max_stride;
- plane->update_plane = i9xx_update_plane;
- plane->disable_plane = i9xx_disable_plane;
- plane->get_hw_state = i9xx_plane_get_hw_state;
- plane->check_plane = i9xx_plane_check;
+ if (INTEL_GEN(dev_priv) >= 4)
+ plane_funcs = _plane_funcs;
+ else
+ plane_funcs = _plane_funcs;
+
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ plane->min_cdclk = vlv_plane_min_cdclk;
+ else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+ plane->min_cdclk = hsw_plane_min_cdclk;
+ else if (IS_IVYBRIDGE(dev_priv))
+ plane->min_cdclk = ivb_plane_min_cdclk;
+ else
plane->min_cdclk = i9xx_plane_min_cdclk;
- plane_funcs = _plane_funcs;
- }
+ plane->max_stride = i9xx_plane_max_stride;
+ plane->update_plane = i9xx_update_plane;
+ plane->disable_plane = i9xx_disable_plane;
+ plane->get_hw_state = i9xx_plane_get_hw_state;
+ plane->check_plane = i9xx_plane_check;
possible_crtcs = BIT(pipe);
if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
ret = drm_universal_plane_init(_priv->drm, >base,
possible_crtcs, plane_funcs,
- formats, num_formats, modifiers,
+ formats, num_formats,
+ i9xx_format_modifiers,
DRM_PLANE_TYPE_PRIMARY,
"primary %c", pipe_name(pipe));
else
ret = drm_universal_plane_init(_priv->drm, >base,
possible_crtcs, plane_funcs,
- formats, num_formats, modifiers,
+
[Intel-gfx] [PATCH 1/7] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
From: Ville Syrjälä
SNB-BDW support 10:10:10 formats on the sprite planes. Let's expose
them.
v2: Rebase due to fp16 landing
Signed-off-by: Ville Syrjälä
Reviewed-by: Juha-Pekka Heikkila
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_sprite.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index edc41fc40726..514b620378d5 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1348,6 +1348,12 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_XRGB:
sprctl |= SPRITE_FORMAT_RGBX888;
break;
+ case DRM_FORMAT_XBGR2101010:
+ sprctl |= SPRITE_FORMAT_RGBX101010 | SPRITE_RGB_ORDER_RGBX;
+ break;
+ case DRM_FORMAT_XRGB2101010:
+ sprctl |= SPRITE_FORMAT_RGBX101010;
+ break;
case DRM_FORMAT_XBGR16161616F:
sprctl |= SPRITE_FORMAT_RGBX161616 | SPRITE_RGB_ORDER_RGBX;
break;
@@ -1653,6 +1659,12 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_XRGB:
dvscntr |= DVS_FORMAT_RGBX888;
break;
+ case DRM_FORMAT_XBGR2101010:
+ dvscntr |= DVS_FORMAT_RGBX101010 | DVS_RGB_ORDER_XBGR;
+ break;
+ case DRM_FORMAT_XRGB2101010:
+ dvscntr |= DVS_FORMAT_RGBX101010;
+ break;
case DRM_FORMAT_XBGR16161616F:
dvscntr |= DVS_FORMAT_RGBX161616 | DVS_RGB_ORDER_XBGR;
break;
@@ -2375,6 +2387,8 @@ static const u64 i9xx_plane_format_modifiers[] = {
static const u32 snb_plane_formats[] = {
DRM_FORMAT_XRGB,
DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
DRM_FORMAT_XRGB16161616F,
DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_YUYV,
@@ -2593,6 +2607,8 @@ static bool snb_sprite_format_mod_supported(struct
drm_plane *_plane,
switch (format) {
case DRM_FORMAT_XRGB:
case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_XBGR16161616F:
case DRM_FORMAT_YUYV:
--
2.23.0
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/guc: drop guc shared area
On Wed, Oct 30, 2019 at 06:30:40PM -0700, Daniele Ceraolo Spurio wrote: Recent GuC doesn't require the shared area. We still have one user in i915 (engine reset via guc) because we haven't updated the command to match the current guc submission flow [1]. Since the flow in guc is about to change again, just disable the command for now and add a note that we'll implement it as part of the new flow. [1] https://patchwork.freedesktop.org/patch/295038/ Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: John Harrison Cc: Matthew Brost Cc: Fernando Pacheco --- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 50 ++ drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 -- 2 files changed, 3 insertions(+), 49 deletions(-) This patch also works with the GuC redesign work being done. Reviewed-by: Matthew Brost ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,01/12] drm/i915: Handle a few more cases for crtc hw/uapi split, v3.
== Series Details == Series: series starting with [CI,01/12] drm/i915: Handle a few more cases for crtc hw/uapi split, v3. URL : https://patchwork.freedesktop.org/series/68775/ State : success == Summary == CI Bug Log - changes from CI_DRM_7224_full -> Patchwork_15074_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_15074_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15074_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15074_full: ### IGT changes ### Warnings * igt@i915_selftest@mock_requests: - shard-glk: [INCOMPLETE][1] ([fdo#103359] / [k.org#198133]) -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7224/shard-glk9/igt@i915_selftest@mock_requests.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15074/shard-glk7/igt@i915_selftest@mock_requests.html Known issues Here are the changes found in Patchwork_15074_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7224/shard-iclb4/igt@gem_ctx_isolat...@vcs1-dirty-create.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15074/shard-iclb3/igt@gem_ctx_isolat...@vcs1-dirty-create.html * igt@gem_ctx_switch@vcs1-heavy-queue: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +12 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7224/shard-iclb2/igt@gem_ctx_swi...@vcs1-heavy-queue.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15074/shard-iclb7/igt@gem_ctx_swi...@vcs1-heavy-queue.html * igt@gem_exec_blt@cold: - shard-apl: [PASS][7] -> [INCOMPLETE][8] ([fdo#103927]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7224/shard-apl4/igt@gem_exec_...@cold.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15074/shard-apl2/igt@gem_exec_...@cold.html * igt@gem_exec_reloc@basic-write-wc-active: - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([fdo#106107]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7224/shard-skl2/igt@gem_exec_re...@basic-write-wc-active.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15074/shard-skl6/igt@gem_exec_re...@basic-write-wc-active.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +15 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7224/shard-iclb2/igt@gem_exec_sched...@independent-bsd2.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15074/shard-iclb7/igt@gem_exec_sched...@independent-bsd2.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7224/shard-iclb7/igt@gem_exec_sched...@preempt-other-chain-bsd.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15074/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#104108]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7224/shard-skl1/igt@gem_soft...@noreloc-s3.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15074/shard-skl4/igt@gem_soft...@noreloc-s3.html * igt@gem_userptr_blits@sync-unmap-cycles: - shard-hsw: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7224/shard-hsw6/igt@gem_userptr_bl...@sync-unmap-cycles.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15074/shard-hsw6/igt@gem_userptr_bl...@sync-unmap-cycles.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +6 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7224/shard-kbl2/igt@gem_workarou...@suspend-resume-fd.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15074/shard-kbl3/igt@gem_workarou...@suspend-resume-fd.html * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-kbl: [PASS][21] -> [SKIP][22] ([fdo#109271]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7224/shard-kbl1/igt@i915_pm_rc6_reside...@rc6-accuracy.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15074/shard-kbl1/igt@i915_pm_rc6_reside...@rc6-accuracy.html * igt@i915_selftest@mock_requests: -
Re: [Intel-gfx] [PATCH 1/2] drm/i915: drop lrc header page
On Wed, Oct 30, 2019 at 06:30:39PM -0700, Daniele Ceraolo Spurio wrote: Recent GuC binaries (including all the ones we're currently using) don't require this shared area anymore, having moved the relevant entries into the stage pool instead. i915 itself doesn't write anything into it either, so we can safely drop it. Signed-off-by: Daniele Ceraolo Spurio Cc: Chris Wilson Cc: Michal Wajdeczko Cc: John Harrison Cc: Matthew Brost --- drivers/gpu/drm/i915/gt/intel_lrc.c| 22 +++-- drivers/gpu/drm/i915/gt/intel_lrc.h| 23 ++ drivers/gpu/drm/i915/gt/selftest_context.c | 3 --- drivers/gpu/drm/i915/gvt/scheduler.c | 4 ++-- 4 files changed, 7 insertions(+), 45 deletions(-) This patch works with the GuC redesign work being done. Reviewed-by: Matthew Brost ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [RFC PATCH i-g-t v3] tests/gem_exec_reloc: Don't filter out invalid addresses
On Thu, Oct 31, 2019 at 08:40:58AM +0100, Janusz Krzysztofik wrote:
On Wednesday, October 30, 2019 10:19:43 PM CET Vanshidhar Konda wrote:
On Wed, Oct 30, 2019 at 06:15:35PM +0100, Janusz Krzysztofik wrote:
>Commit a355b2d6eb42 ("igt/gem_exec_reloc: Filter out unavailable
>addresses for !ppgtt") introduced filtering of addresses possibly
>occupied by other users of shared GTT. Unfortunately, that filtering
>doesn't distinguish actually occupied addresses from otherwise invalid
>softpin offsets. For example, on a future hardware backing store with
>a page size larger than 4 kB incorrect object alignment is assumed and
>the test results are distorted as it happily skips over incorrectly
>aligned objects instead of reporting the problem.
>
>Filter out failing addresses only if not reported as invalid.
>
>Signed-off-by: Janusz Krzysztofik
>Cc: Chris Wilson
>---
> tests/i915/gem_exec_reloc.c | 12 +---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
>diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c
>index fdd9661d..1d0c791e 100644
>--- a/tests/i915/gem_exec_reloc.c
>+++ b/tests/i915/gem_exec_reloc.c
>@@ -520,7 +520,7 @@ static void basic_range(int fd, unsigned flags)
>uint64_t gtt_size = gem_aperture_size(fd);
>const uint32_t bbe = MI_BATCH_BUFFER_END;
>igt_spin_t *spin = NULL;
>- int count, n;
>+ int count, n, err;
>
>igt_require(gem_has_softpin(fd));
>
>@@ -542,8 +542,11 @@ static void basic_range(int fd, unsigned flags)
>gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
>execbuf.buffers_ptr = to_user_pointer([n]);
>execbuf.buffer_count = 1;
>- if (__gem_execbuf(fd, ))
>+ err = __gem_execbuf(fd, );
>+ if (err) {
>+ igt_assert(err != -EINVAL);
>continue;
The addresses to which the object is being pinned is generated as part
of the test. The code is just assuming that the address needs to be 4K
aligned instead of figuring out what the alignment requirement for the
device is.
Shouldn't the test be updated to generate virtual addresses per the
alignment requirements of the test device instead of just assuming 4K
increments are good?
You're perfectly right, and that's what I've been trying to achieve in my
series https://lists.freedesktop.org/archives/igt-dev/2019-October/017081.html.
Thanks for providing the context for the changes.
As suggested by Chris
(https://lists.freedesktop.org/archives/igt-dev/2019-October/016936.html),
I've been trying to add a library function that detects the alignment
requirement of a device. We haven't agreed yet on necessity of my approach to
distinguish failures caused by incorrect offset alignment from those which are
simply coming from addresses being occupied by other users, and how to do
For a context that has just been created, I would assume that the PPGTTs would
be
empty as no object should be mapped by default in it. With this
assumption, is it safe to assume that unaligned addresses would be the
only ones that return an EINVAL error?
I'll take a look at the latest version of the patch series for this.
Thanks,
Vanshi
that distinction. In my current approach, I'm retrying at different offsets
to conclude possible failure reasons, but maybe error codes can be used for
that.
Back to this patch, skipping over invalid offsets, calculated from incorrectly
assumed or detected alignment requirements still seems wrong to me, anyway.
That's the reason for this patch.
Thanks,
Janusz
Vanshi
>+ }
>
>igt_debug("obj[%d] handle=%d, address=%llx\n",
> n, obj[n].handle, (long long)obj[n].offset);
>@@ -562,8 +565,11 @@ static void basic_range(int fd, unsigned flags)
>gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
>execbuf.buffers_ptr = to_user_pointer([n]);
>execbuf.buffer_count = 1;
>- if (__gem_execbuf(fd, ))
>+ err = __gem_execbuf(fd, );
>+ if (err) {
>+ igt_assert(err != -EINVAL);
>continue;
>+ }
>
>igt_debug("obj[%d] handle=%d, address=%llx\n",
> n, obj[n].handle, (long long)obj[n].offset);
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Re: [Intel-gfx] [PATCH] drm/i915: Skip MCHBAR queries on dgfx
On Thu, Oct 31, 2019 at 08:11:24AM -0700, Stuart Summers wrote: > dgfx does not map the MCHBAR MMIO into the GFX device BAR. > Skip this sequence when running on dgfx. > > Signed-off-by: Stuart Summers Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_drv.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 21273b516dbe..1de46bfa5a19 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -1056,7 +1056,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv) >*/ > dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv); > > - if (INTEL_GEN(dev_priv) < 9) > + if (INTEL_GEN(dev_priv) < 9 || IS_DGFX(dev_priv)) > return; > > if (IS_GEN9_LP(dev_priv)) > -- > 2.22.0 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH i-g-t v4 0/4] Calculate softpin offsets from minimum GTT alignment
Some tests assume 4kB page size while using softpin. That assumption may be wrong on future GEM backends with possibly larger minimum page sizes. As a result, those tests may either fail on softpin at offsets which are incorrectly aligned, may silently skip such incorrectly aligned addresses assuming them occupied by other users, or may always succeed when examining invalid use patterns. Provide a helper function that detects minimum page size and returns the size order. Use it in test which perform softpin to calculate offsets suitable for actually used backing store. Changelog: v2: Don't skip failing offsets only when on full PPGTT, - simplify the code by reversing the size->order conversion, - drop irrelevant modifications of requested object sizes. v3: Drop patch 1/2 "Don't filter out addresses when on PPGTT" - I don't know how to detect if the kernel is interfering with the user's GTT, - introduce patch 1/4 "lib: Move redundant local helpers to lib/", subsequent patch will use the helper, - introduce patch 2/4 "lib: Add GEM minimum page size helper", subsequent patches will use the new helper (inspired by Chris), - in former patch 2/2, now 3/4, initialize page size order with an actual minimum returned by the new helper (inspired by Chris), - add a new fix for gem_ctx_shared test (patch 4/4). v4: Rename the helper, use 'minimum GTT alignment' term across the changes (Chris), - update variable names accordingly, - use error numbers to distinguish between invalid offsets and addresses occupied by other users, then - simplify the helper code (Chris), - drop no longer required patch 1/4 "lib: Move redundant local helpers to lib/", - reintroduce former patch 1/2 as 1/4 "tests/gem_exec_reloc: Don't filter out invalid addresses" with the former not on full PPGTT requirement for skipping now replaced with error code checking. Janusz Krzysztofik (4): tests/gem_exec_reloc: Don't filter out invalid addresses lib: Add minimum GTT alignment helper tests/gem_exec_reloc: Calculate offsets from minimum GTT alignment tests/gem_ctx_shared: Align objects using minimum GTT alignment lib/ioctl_wrappers.c| 46 + lib/ioctl_wrappers.h| 2 ++ tests/i915/gem_ctx_shared.c | 6 +++-- tests/i915/gem_exec_reloc.c | 22 -- 4 files changed, 67 insertions(+), 9 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH i-g-t v4 2/4] lib: Add minimum GTT alignment helper
Some tests assume 4kB offset alignment while using softpin. That
assumption may be wrong on future GEM backends with possibly larger
minimum page sizes. As a result, those tests may either fail on
softpin at offsets which are incorrectly aligned, may silently skip
such incorrectly aligned addresses assuming them occupied by other
users if incorrect detection method is used, or may always succeed
when examining invalid use patterns.
Provide a helper function that detects minimum GTT alignment. Tests
may use it to calculate softpin offsets valid for actually used backing
store.
v2: Rename the helper, use 'minimum GTT alignment' term across the
change (Chris),
- use error numbers to distinguish between invalid offsets and
addresses occupied by other users, then
- simplify the code (Chris).
Signed-off-by: Janusz Krzysztofik
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Stuart Summers
---
lib/ioctl_wrappers.c | 46
lib/ioctl_wrappers.h | 2 ++
2 files changed, 48 insertions(+)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 628f8b83..f0ef8b2e 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -54,6 +54,7 @@
#include "intel_io.h"
#include "igt_debugfs.h"
#include "igt_sysfs.h"
+#include "igt_x86.h"
#include "config.h"
#ifdef HAVE_VALGRIND
@@ -1158,6 +1159,51 @@ bool gem_has_softpin(int fd)
return has_softpin;
}
+/**
+ * gem_gtt_min_alignment_order:
+ * @fd: open i915 drm file descriptor
+ *
+ * This function detects the minimum possible alignment of a soft-pinned gem
+ * object allocated from a default backing store. It is useful for calculating
+ * correctly aligned softpin offsets.
+ * Since size order to size conversion (size = 1 << order) is less trivial
+ * than the opposite, the function returns the alignment order as more handy.
+ *
+ * Returns:
+ * Size order of the minimum GTT alignment
+ */
+int gem_gtt_min_alignment_order(int fd)
+{
+ struct drm_i915_gem_exec_object2 obj;
+ struct drm_i915_gem_execbuffer2 eb;
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ int order;
+
+ /* no softpin => 4kB page size */
+ if (!gem_has_softpin(fd))
+ return 12;
+
+ memset(, 0, sizeof(obj));
+ memset(, 0, sizeof(eb));
+
+ obj.handle = gem_create(fd, 4096);
+ obj.flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ eb.buffers_ptr = to_user_pointer();
+ eb.buffer_count = 1;
+ gem_write(fd, obj.handle, 0, , sizeof(bbe));
+
+ for (order = 12; order < 64; order++) {
+ obj.offset = 1ull << order;
+ if (__gem_execbuf(fd, ) != -EINVAL)
+ break;
+ }
+ igt_assert(obj.offset < gem_aperture_size(fd));
+
+ gem_close(fd, obj.handle);
+ igt_debug("minimum GTT alignment is %#llx\n", (long long)obj.offset);
+ return order;
+}
+
/**
* gem_has_exec_fence:
* @fd: open i915 drm file descriptor
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 03211c97..c8d57a7c 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -138,6 +138,8 @@ uint64_t gem_aperture_size(int fd);
uint64_t gem_global_aperture_size(int fd);
uint64_t gem_mappable_aperture_size(void);
bool gem_has_softpin(int fd);
+int gem_gtt_min_alignment_order(int fd);
+#define gem_gtt_min_alignment(fd) (1ull << gem_gtt_min_alignment_order(fd))
bool gem_has_exec_fence(int fd);
/* check functions which auto-skip tests by calling igt_skip() */
--
2.21.0
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[Intel-gfx] [RFC PATCH i-g-t v4 1/4] tests/gem_exec_reloc: Don't filter out invalid addresses
Commit a355b2d6eb42 ("igt/gem_exec_reloc: Filter out unavailable
addresses for !ppgtt") introduced filtering of addresses possibly
occupied by other users of shared GTT. Unfortunately, that filtering
doesn't distinguish between actually occupied addresses and otherwise
invalid softpin offsets. As soon as incorrect GTT alignment is assumed
when running on future backends with possibly larger minimum page
sizes, a half of calculated offsets to be tested will be incorrectly
detected as occupied by other users and silently skipped instead of
reported as a problem. That will significantly distort the intended
test pattern.
Filter out failing addresses only if not reported as invalid.
v2: Skip unavailable addresses only when not running on full PPGTT.
v3: Replace the not on full PPGTT requirement for skipping with error
code checking.
Signed-off-by: Janusz Krzysztofik
Cc: Chris Wilson
---
tests/i915/gem_exec_reloc.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c
index 5f59fe99..423fed8b 100644
--- a/tests/i915/gem_exec_reloc.c
+++ b/tests/i915/gem_exec_reloc.c
@@ -520,7 +520,7 @@ static void basic_range(int fd, unsigned flags)
uint64_t gtt_size = gem_aperture_size(fd);
const uint32_t bbe = MI_BATCH_BUFFER_END;
igt_spin_t *spin = NULL;
- int count, n;
+ int count, n, err;
igt_require(gem_has_softpin(fd));
@@ -542,8 +542,11 @@ static void basic_range(int fd, unsigned flags)
gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
execbuf.buffers_ptr = to_user_pointer([n]);
execbuf.buffer_count = 1;
- if (__gem_execbuf(fd, ))
+ err = __gem_execbuf(fd, );
+ if (err) {
+ igt_assert(err != -EINVAL);
continue;
+ }
igt_debug("obj[%d] handle=%d, address=%llx\n",
n, obj[n].handle, (long long)obj[n].offset);
@@ -562,8 +565,11 @@ static void basic_range(int fd, unsigned flags)
gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
execbuf.buffers_ptr = to_user_pointer([n]);
execbuf.buffer_count = 1;
- if (__gem_execbuf(fd, ))
+ err = __gem_execbuf(fd, );
+ if (err) {
+ igt_assert(err != -EINVAL);
continue;
+ }
igt_debug("obj[%d] handle=%d, address=%llx\n",
n, obj[n].handle, (long long)obj[n].offset);
--
2.21.0
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[Intel-gfx] [RFC PATCH i-g-t v4 4/4] tests/gem_ctx_shared: Align objects using minimum GTT alignment
exec-shared-gtt-* subtests use hardcoded values for object size and softpin offset, based on 4kB GTT alignment assumption. That may result in those subtests failing when run on future backing stores with possibly larger minimum page sizes. Replace hardcoded constants with values calculated from minimum GTT alignment of actual backing store the test is running on. v2: Update helper name, use 'minimum GTT alignment' term across the change, adjust variable name. Signed-off-by: Janusz Krzysztofik Cc: Chris Wilson --- tests/i915/gem_ctx_shared.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c index 6d8cbcce..1e9c7f78 100644 --- a/tests/i915/gem_ctx_shared.c +++ b/tests/i915/gem_ctx_shared.c @@ -195,6 +195,7 @@ static void exec_shared_gtt(int i915, unsigned int ring) uint32_t scratch, *s; uint32_t batch, cs[16]; uint64_t offset; + uint64_t alignment; int i; gem_require_ring(i915, ring); @@ -203,7 +204,8 @@ static void exec_shared_gtt(int i915, unsigned int ring) clone = gem_context_clone(i915, 0, I915_CONTEXT_CLONE_VM, 0); /* Find a hole big enough for both objects later */ - scratch = gem_create(i915, 16384); + alignment = 2 * gem_gtt_min_alignment(i915); + scratch = gem_create(i915, 2 * alignment); gem_write(i915, scratch, 0, , sizeof(bbe)); obj.handle = scratch; gem_execbuf(i915, ); @@ -246,7 +248,7 @@ static void exec_shared_gtt(int i915, unsigned int ring) gem_write(i915, batch, 0, cs, sizeof(cs)); obj.handle = batch; - obj.offset += 8192; /* make sure we don't cause an eviction! */ + obj.offset += alignment; /* make sure we don't cause an eviction! */ execbuf.rsvd1 = clone; if (gen > 3 && gen < 6) execbuf.flags |= I915_EXEC_SECURE; -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH i-g-t v4 3/4] tests/gem_exec_reloc: Calculate offsets from minimum GTT alignment
The basic-range subtest assumes 4kB GTT alignment while calculating
softpin offsets. On future backends with possibly larger minimum page
sizes the test will fail as a half of calculated offsets to be tested
will be incorrectly aligned.
Replace hardcoded constants corresponding to the assumed 4kB GTT
alignment with variables initialized with actual minimum GTT alignment
size and order.
v2: Simplify the code by reversing the size->order conversion,
- drop irrelevant modifications of requested object sizes.
v3: Reword commit message after removal of patch "Don't filter out
addresses on full PPGTT" from the series,
- initialize page size order with an actual minimum returned by a new
helper (inspired by Chris).
v4: Update the helper name, use the term 'minimum GTT alignment' across
the change, adjust variable names,
- refresh the commit message on top of the reintroduced patch that
fixes invalid offsets incorrectly assumed as occupied.
Signed-off-by: Janusz Krzysztofik
Cc: Katarzyna Dec
Cc: Stuart Summers
Cc: Chris Wilson
---
tests/i915/gem_exec_reloc.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c
index 423fed8b..8050cd3e 100644
--- a/tests/i915/gem_exec_reloc.c
+++ b/tests/i915/gem_exec_reloc.c
@@ -520,14 +520,16 @@ static void basic_range(int fd, unsigned flags)
uint64_t gtt_size = gem_aperture_size(fd);
const uint32_t bbe = MI_BATCH_BUFFER_END;
igt_spin_t *spin = NULL;
+ int alignment_order = gem_gtt_min_alignment_order(fd);
+ uint64_t alignment = 1ull << alignment_order;
int count, n, err;
igt_require(gem_has_softpin(fd));
- for (count = 12; gtt_size >> (count + 1); count++)
+ for (count = alignment_order; gtt_size >> (count + 1); count++)
;
- count -= 12;
+ count -= alignment_order;
memset(obj, 0, sizeof(obj));
memset(reloc, 0, sizeof(reloc));
@@ -536,7 +538,7 @@ static void basic_range(int fd, unsigned flags)
n = 0;
for (int i = 0; i <= count; i++) {
obj[n].handle = gem_create(fd, 4096);
- obj[n].offset = (1ull << (i + 12)) - 4096;
+ obj[n].offset = (1ull << (i + alignment_order)) - alignment;
obj[n].offset = gen8_canonical_address(obj[n].offset);
obj[n].flags = EXEC_OBJECT_PINNED |
EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
@@ -559,7 +561,7 @@ static void basic_range(int fd, unsigned flags)
}
for (int i = 1; i < count; i++) {
obj[n].handle = gem_create(fd, 4096);
- obj[n].offset = 1ull << (i + 12);
+ obj[n].offset = 1ull << (i + alignment_order);
obj[n].offset = gen8_canonical_address(obj[n].offset);
obj[n].flags = EXEC_OBJECT_PINNED |
EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
gem_write(fd, obj[n].handle, 0, , sizeof(bbe));
--
2.21.0
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[Intel-gfx] [PATCH] drm/i915: Skip MCHBAR queries on dgfx
dgfx does not map the MCHBAR MMIO into the GFX device BAR. Skip this sequence when running on dgfx. Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/i915_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 21273b516dbe..1de46bfa5a19 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1056,7 +1056,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv) */ dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv); - if (INTEL_GEN(dev_priv) < 9) + if (INTEL_GEN(dev_priv) < 9 || IS_DGFX(dev_priv)) return; if (IS_GEN9_LP(dev_priv)) -- 2.22.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/12] drm/i915: Add aliases for uapi and hw to plane_state
On Thu, Oct 31, 2019 at 12:26:05PM +0100, Maarten Lankhorst wrote:
> Prepare to split up hw and uapi machinally, by adding a uapi and
> hw alias. We will remove the base in a bit. This is a split from the
> original uapi/hw patch, which did it all in one go.
>
> Signed-off-by: Maarten Lankhorst
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c| 16
> .../gpu/drm/i915/display/intel_display_types.h | 8 ++--
> 2 files changed, 14 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 4558c0b29fc1..393fb97a3dca 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -80,22 +80,20 @@ void intel_plane_free(struct intel_plane *plane)
> struct drm_plane_state *
> intel_plane_duplicate_state(struct drm_plane *plane)
> {
> - struct drm_plane_state *state;
> struct intel_plane_state *intel_state;
>
> - intel_state = kmemdup(plane->state, sizeof(*intel_state), GFP_KERNEL);
> + intel_state = to_intel_plane_state(plane->state);
> + intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
>
> if (!intel_state)
> return NULL;
>
> - state = _state->base;
> -
> - __drm_atomic_helper_plane_duplicate_state(plane, state);
> + __drm_atomic_helper_plane_duplicate_state(plane, _state->base);
>
> intel_state->vma = NULL;
> intel_state->flags = 0;
>
> - return state;
> + return _state->base;
Could use a bit of cleanup on the variable names, but let's do that
later.
Reviewed-by: Ville Syrjälä
> }
>
> /**
> @@ -110,9 +108,11 @@ void
> intel_plane_destroy_state(struct drm_plane *plane,
> struct drm_plane_state *state)
> {
> - WARN_ON(to_intel_plane_state(state)->vma);
> + struct intel_plane_state *plane_state = to_intel_plane_state(state);
> + WARN_ON(plane_state->vma);
>
> - drm_atomic_helper_plane_destroy_state(plane, state);
> + __drm_atomic_helper_plane_destroy_state(_state->base);
> + kfree(plane_state);
> }
>
> unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9319ca682105..6036b2b3980b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -523,7 +523,11 @@ struct intel_atomic_state {
> };
>
> struct intel_plane_state {
> - struct drm_plane_state base;
> + union {
> + struct drm_plane_state base;
> + struct drm_plane_state uapi;
> + struct drm_plane_state hw;
> + };
> struct i915_ggtt_view view;
> struct i915_vma *vma;
> unsigned long flags;
> @@ -1143,7 +1147,7 @@ struct cxsr_latency {
> #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
> #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer,
> base)
> #define to_intel_plane(x) container_of(x, struct intel_plane, base)
> -#define to_intel_plane_state(x) container_of(x, struct intel_plane_state,
> base)
> +#define to_intel_plane_state(x) container_of(x, struct intel_plane_state,
> uapi)
> #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
>
> struct intel_hdmi {
> --
> 2.24.0.rc1
>
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--
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Re: [Intel-gfx] [PATCH] drm/i915/execlists: Verify context register state before execution
Chris Wilson writes:
> Quoting Mika Kuoppala (2019-10-31 14:32:05)
>> Chris Wilson writes:
>>
>> > Check that the context's ring register state still matches our
>> > expectations prior to execution.
>> >
>> > Signed-off-by: Chris Wilson
>> > Cc: Mika Kuoppala
>> > ---
>> > drivers/gpu/drm/i915/gt/intel_lrc.c | 73 -
>> > drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 4 +-
>> > drivers/gpu/drm/i915/gt/selftest_lrc.c | 4 +-
>> > 3 files changed, 63 insertions(+), 18 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> > b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> > index 5f61cd128d9c..666e70931524 100644
>> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> > @@ -1146,6 +1146,60 @@ execlists_schedule_out(struct i915_request *rq)
>> > i915_request_put(rq);
>> > }
>> >
>> > +static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
>> > +{
>> > + if (INTEL_GEN(engine->i915) >= 12)
>> > + return 0x60;
>> > + else if (INTEL_GEN(engine->i915) >= 9)
>> > + return 0x54;
>> > + else if (engine->class == RENDER_CLASS)
>> > + return 0x58;
>> > + else
>> > + return -1;
>> > +}
>> > +
>> > +static void
>> > +execlists_check_context(const struct intel_context *ce,
>> > + const struct intel_engine_cs *engine)
>> > +{
>> > + const struct intel_ring *ring = ce->ring;
>> > + u32 *regs = ce->lrc_reg_state;
>> > + int x;
>> > +
>> > + if (regs[CTX_RING_START] != i915_ggtt_offset(ring->vma)) {
>> > + pr_err_once("%s: context submitted with incorrect
>> > RING_BUFFER_START [%08x], expected %08x\n",
>> > + engine->name,
>> > + regs[CTX_RING_START],
>> > + i915_ggtt_offset(ring->vma));
>> > + regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
>> > + }
>> > +
>> > + if ((regs[CTX_RING_CTL] & ~(RING_WAIT | RING_WAIT_SEMAPHORE)) !=
>> > + (RING_CTL_SIZE(ring->size) | RING_VALID)) {
>> > + pr_err_once("%s: context submitted with incorrect
>> > RING_BUFFER_CONTROL [%08x], expected %08x\n",
>> > + engine->name,
>> > + regs[CTX_RING_CTL],
>> > + (u32)(RING_CTL_SIZE(ring->size) | RING_VALID));
>> > + regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
>>
>> We are going to submit by clearing the waits. First I thought this will
>> lead to disaster but the hardware works so that we clear on writing '1'.
>
> Afaik, they are only indicator bits. So the HW ignores those bits when
> we write to the register.
>
I did check on reviewing. For Gen12 it states that: writing 0 == no
effect, writing 1 == clear.
-Mika
>> > + if (regs[CTX_BB_STATE] != RING_BB_PPGTT) {
>> > + pr_err_once("%s: context submitted with incorrect BB_STATE
>> > [%08x], expected %08x\n",
>> > + engine->name,
>> > + regs[CTX_BB_STATE],
>> > + RING_BB_PPGTT);
>> > + regs[CTX_BB_STATE] = RING_BB_PPGTT;
>> > + }
>> > +
>> > + x = lrc_ring_mi_mode(engine);
>> > + if (x != -1 && regs[x + 1] & STOP_RING) {
>> > + pr_err_once("%s: context submitted with STOP_RING [%08x] in
>> > RING_MI_MODE\n",
>> > + engine->name, regs[x + 1]);
>> > + regs[x + 1] &= ~STOP_RING;
>> > + regs[x + 1] |= STOP_RING << 16;
>>
>> Ok you want only to care about this one. Was pondering of restoring rest
>> of the state from previous.
>
> It was mostly in the spirit of "now that we are here, we might as well
> fix it up". It's mainly the paranoia in trying to ascertain if we are
> feeding garbage into the GPU. There's probably a lot more we can check,
> but the ring registers are essential :)
>
>> Will the hardware even care on masks at this point or is the saving part
>> setting them accordingly?
>
> Aiui, it uses the masks on the implicit LRI in the context restore to
> control where or not to actually apply the bits. Not that I have checked
> to see what the HW is doing (we will see if it ever flags an error), but
> memory says from elsewere it uses 0x.
> -Chris
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Re: [Intel-gfx] [PATCH 02/12] drm/i915: Add aliases for uapi and hw to crtc_state
On Thu, Oct 31, 2019 at 12:26:00PM +0100, Maarten Lankhorst wrote:
> Prepare to split up hw and uapi machinally, by adding a uapi and
> hw alias. We will remove the base in a bit. This is a split from the
> original uapi/hw patch, which did it all in one go.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 8 --
> drivers/gpu/drm/i915/display/intel_display.c | 2 ++
> drivers/gpu/drm/i915/display/intel_display.h | 6 ++---
> .../drm/i915/display/intel_display_types.h| 27 ++-
> 4 files changed, 37 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 9cd6d2348a1e..4826aa4ee8e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -186,9 +186,10 @@ intel_digital_connector_duplicate_state(struct
> drm_connector *connector)
> struct drm_crtc_state *
> intel_crtc_duplicate_state(struct drm_crtc *crtc)
> {
> + const struct intel_crtc_state *old_crtc_state =
> to_intel_crtc_state(crtc->state);
> struct intel_crtc_state *crtc_state;
>
> - crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), GFP_KERNEL);
> + crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
> if (!crtc_state)
> return NULL;
>
> @@ -219,7 +220,10 @@ void
> intel_crtc_destroy_state(struct drm_crtc *crtc,
>struct drm_crtc_state *state)
> {
> - drm_atomic_helper_crtc_destroy_state(crtc, state);
> + struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
> +
> + __drm_atomic_helper_crtc_destroy_state(_state->base);
> + kfree(crtc_state);
> }
>
> static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state
> *scaler_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 397ed1205704..939dff68bba1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12592,6 +12592,8 @@ clear_intel_crtc_state(struct intel_crtc_state
> *crtc_state)
>
> /* Keep base drm_crtc_state intact, only clear our extended struct */
> BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
> + BUILD_BUG_ON(offsetof(struct intel_crtc_state, uapi));
> + BUILD_BUG_ON(offsetof(struct intel_crtc_state, hw));
> memcpy(_state->base + 1, _state->base + 1,
> sizeof(*crtc_state) - sizeof(crtc_state->base));
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 355c50088589..476bc71e6a83 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -447,10 +447,10 @@ enum phy_fia {
> #define intel_atomic_crtc_state_for_each_plane_state( \
> plane, plane_state, \
> crtc_state) \
> - for_each_intel_plane_mask(((crtc_state)->base.state->dev), (plane), \
> - ((crtc_state)->base.plane_mask)) \
> + for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
> + ((crtc_state)->uapi.plane_mask)) \
> for_each_if ((plane_state = \
> -
> to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state,
> >base
> +
> to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state,
> >base
>
> void intel_link_compute_m_n(u16 bpp, int nlanes,
> int pixel_clock, int link_clock,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 40184e823c84..e84343d3bf8d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -757,7 +757,32 @@ enum intel_output_format {
> };
>
> struct intel_crtc_state {
> + union {
> struct drm_crtc_state base;
> + /*
> + * uapi (drm) state. This is the software state shown to userspace.
> + * In particular, the following members are used for bookkeeping:
> + * - crtc
> + * - state
> + * - *_changed
> + * - event
> + * - commit
> + * - mode_blob
> + */
> + struct drm_crtc_state uapi;
> +
> + /*
> + * actual hardware state, the state we program to the hardware.
> + * The following members are used to verify the hardware state:
> + * - enable
> + * - active
> + * - mode / adjusted_mode
> + * - color property blobs.
> + *
> + * During initial hw readout, they need to be copied to uapi.
> + */
> + struct drm_crtc_state hw;
> + };
>
> /**
>* quirks - bitfield with hw state
Re: [Intel-gfx] [PATCH 09/12] drm/i915: Perform automated conversions for plane uapi/hw split, base -> hw.
On Thu, Oct 31, 2019 at 12:26:07PM +0100, Maarten Lankhorst wrote:
> Split up plane_state->base to hw. This is done using the following patch:
>
> @@
> struct intel_plane_state *T;
> identifier x =~
> "^(crtc|fb|alpha|pixel_blend_mode|rotation|color_encoding|color_range)$";
> @@
> -T->base.x
> +T->hw.x
>
> Signed-off-by: Maarten Lankhorst
> Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 6 +-
> .../gpu/drm/i915/display/intel_atomic_plane.c | 8 +-
> drivers/gpu/drm/i915/display/intel_display.c | 126 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 8 +-
> drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 90 ++---
> drivers/gpu/drm/i915/intel_pm.c | 32 ++---
> 7 files changed, 136 insertions(+), 136 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 3301c178da03..0a5eee4c350f 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -283,9 +283,9 @@ static void intel_atomic_setup_scaler(struct
> intel_crtc_scaler_state *scaler_sta
> return;
>
> /* set scaler mode */
> - if (plane_state && plane_state->base.fb &&
> - plane_state->base.fb->format->is_yuv &&
> - plane_state->base.fb->format->num_planes > 1) {
> + if (plane_state && plane_state->hw.fb &&
> + plane_state->hw.fb->format->is_yuv &&
> + plane_state->hw.fb->format->num_planes > 1) {
> struct intel_plane *plane =
> to_intel_plane(plane_state->base.plane);
> if (IS_GEN(dev_priv, 9) &&
> !IS_GEMINILAKE(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 416cfa439f33..633535b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -118,7 +118,7 @@ intel_plane_destroy_state(struct drm_plane *plane,
> unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> - const struct drm_framebuffer *fb = plane_state->base.fb;
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> unsigned int cpp;
>
> if (!plane_state->base.visible)
> @@ -144,7 +144,7 @@ bool intel_plane_calc_min_cdclk(struct intel_atomic_state
> *state,
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> const struct intel_plane_state *plane_state =
> intel_atomic_get_new_plane_state(state, plane);
> - struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
Good :)
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 06/12] drm/i915: Complete crtc hw/uapi split, v6.
On Thu, Oct 31, 2019 at 12:26:04PM +0100, Maarten Lankhorst wrote:
> Now that we separated everything into uapi and hw, it's
> time to make the split definitive. Remove the union and
> make a copy of the hw state on modeset and fastset.
>
> Color blobs are copied in crtc atomic_check(), right
> before color management is checked.
>
> Changes since v1:
> - Copy all blobs immediately after drm_atomic_helper_check_modeset().
> - Clear crtc_state->hw on disable, instead of using clear_intel_crtc_state().
> Changes since v2:
> - Use intel_crtc_free_hw_state + clear in intel_crtc_disable_noatomic().
> - Make a intel_crtc_prepare_state() function that clears the crtc_state
> and copies hw members.
> - Remove setting uapi.adjusted_mode, we now have a direct call to
> drm_calc_timestamping_constants().
> Changes since v3:
> - Rename prefix copy_hw_to_uapi_state() with intel_crtc.
> - Copy color blobs to uapi as well.
> - Add a intel_crtc_copy_uapi_to_hw_state_nomodeset() function for clarity.
> Changes since v4:
> - Copy hw.adjusted_mode back to uapi.adjusted_mode, to shut up
> the call to drm_calc_timestamping_constants() in
> drm_atomic_helper_update_legacy_modeset_state().
> - Use drm_property_replace_blob (Ville).
> Changes since v5:
> - Use hw->mode in intel_modeset_readout_hw_state(). (Ville)
> - Copy to uapi.mode using drm_atomic_set_mode_for_crtc(). (Ville)
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 31 +++
> drivers/gpu/drm/i915/display/intel_atomic.h | 2 +
> drivers/gpu/drm/i915/display/intel_display.c | 90 +++
> .../drm/i915/display/intel_display_types.h| 9 +-
> 4 files changed, 109 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 48964f33c0c1..3301c178da03 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -195,6 +195,14 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>
> __drm_atomic_helper_crtc_duplicate_state(crtc, _state->uapi);
>
> + /* copy color blobs */
> + if (crtc_state->hw.degamma_lut)
> + drm_property_blob_get(crtc_state->hw.degamma_lut);
> + if (crtc_state->hw.ctm)
> + drm_property_blob_get(crtc_state->hw.ctm);
> + if (crtc_state->hw.gamma_lut)
> + drm_property_blob_get(crtc_state->hw.gamma_lut);
> +
> crtc_state->update_pipe = false;
> crtc_state->disable_lp_wm = false;
> crtc_state->disable_cxsr = false;
> @@ -208,6 +216,28 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> return _state->uapi;
> }
>
> +static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
> +{
> + drm_property_blob_put(crtc_state->hw.degamma_lut);
> + drm_property_blob_put(crtc_state->hw.gamma_lut);
> + drm_property_blob_put(crtc_state->hw.ctm);
> +}
> +
> +void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
> +{
> + intel_crtc_put_color_blobs(crtc_state);
> +}
> +
> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
> +{
> + drm_property_replace_blob(_state->hw.degamma_lut,
> + crtc_state->uapi.degamma_lut);
> + drm_property_replace_blob(_state->hw.gamma_lut,
> + crtc_state->uapi.gamma_lut);
> + drm_property_replace_blob(_state->hw.ctm,
> + crtc_state->uapi.ctm);
> +}
> +
> /**
> * intel_crtc_destroy_state - destroy crtc state
> * @crtc: drm crtc
> @@ -223,6 +253,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
> struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
>
> __drm_atomic_helper_crtc_destroy_state(_state->uapi);
> + intel_crtc_free_hw_state(crtc_state);
> kfree(crtc_state);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
> b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 49d5cb1b9e0a..7b49623419ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -36,6 +36,8 @@ intel_digital_connector_duplicate_state(struct
> drm_connector *connector);
> struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
> void intel_crtc_destroy_state(struct drm_crtc *crtc,
> struct drm_crtc_state *state);
> +void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> void intel_atomic_state_clear(struct drm_atomic_state *state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4a9dc14f2ee2..373c57a4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++
[Intel-gfx] [PATCH v2] drm/i915/selftests: Perform some basic cycle counting of MI ops
Some basic information that is useful to know, such as how many cycles
is a MI_NOOP.
Signed-off-by: Chris Wilson
Cc: Anna Karas
Cc: Tvrtko Ursulin
---
Having remember to ask for a fixed frequency!
---
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 339 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
2 files changed, 339 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index 3880f07c29b8..bdd82d142602 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -4,7 +4,344 @@
* Copyright © 2018 Intel Corporation
*/
-#include "../i915_selftest.h"
+#include
+
+#include "intel_gt_pm.h"
+#include "intel_rps.h"
+
+#include "i915_selftest.h"
+#include "selftests/igt_flush_test.h"
+
+#define COUNT 5
+
+static int cmp_u32(const void *A, const void *B)
+{
+ const u32 *a = A, *b = B;
+
+ return *a - *b;
+}
+
+static void perf_begin(struct intel_gt *gt)
+{
+ intel_gt_pm_get(gt);
+
+ /* Boost gpufreq to max [waitboost] and keep it fixed */
+ atomic_inc(>rps.num_waiters);
+ schedule_work(>rps.work);
+ flush_work(>rps.work);
+}
+
+static int perf_end(struct intel_gt *gt)
+{
+ atomic_dec(>rps.num_waiters);
+ intel_gt_pm_put(gt);
+
+ return igt_flush_test(gt->i915);
+}
+
+static int write_timestamp(struct i915_request *rq, int slot)
+{
+ u32 cmd;
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
+ if (INTEL_GEN(rq->i915) >= 8)
+ cmd++;
+ *cs++ = cmd;
+ *cs++ = rq->engine->mmio_base + 0x358;
+ *cs++ = i915_request_timeline(rq)->hwsp_offset + slot * sizeof(u32);
+ *cs++ = 0;
+
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
+static struct i915_vma *create_empty_batch(struct intel_context *ce)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ u32 *cs;
+ int err;
+
+ obj = i915_gem_object_create_internal(ce->engine->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ i915_gem_object_put(obj);
+ return ERR_CAST(cs);
+ }
+
+ cs[0] = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(obj);
+ i915_gem_object_unpin_map(obj);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static u32 trifilter(u32 *a)
+{
+ u64 sum;
+
+ sort(a, COUNT, sizeof(*a), cmp_u32, NULL);
+
+ sum += mul_u32_u32(a[2], 2);
+ sum += a[1];
+ sum += a[3];
+
+ return sum >> 2;
+}
+
+static int perf_mi_bb_start(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+ return 0;
+
+ perf_begin(gt);
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_vma *batch;
+ u32 cycles[COUNT];
+ int i;
+
+ batch = create_empty_batch(ce);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ break;
+ }
+
+ err = i915_vma_sync(batch);
+ if (err) {
+ i915_vma_put(batch);
+ break;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cycles); i++) {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ err = write_timestamp(rq, 2);
+ if (err)
+ goto out;
+
+ err = rq->engine->emit_bb_start(rq,
+ batch->node.start, 8,
+ 0);
+ if (err)
+ goto out;
+
+ err = write_timestamp(rq, 3);
+ if (err)
+ goto out;
+
+out:
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (i915_request_wait(rq, 0, HZ
Re: [Intel-gfx] [PATCH] drm/i915/execlists: Verify context register state before execution
Quoting Mika Kuoppala (2019-10-31 14:32:05)
> Chris Wilson writes:
>
> > Check that the context's ring register state still matches our
> > expectations prior to execution.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Mika Kuoppala
> > ---
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 73 -
> > drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 4 +-
> > drivers/gpu/drm/i915/gt/selftest_lrc.c | 4 +-
> > 3 files changed, 63 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index 5f61cd128d9c..666e70931524 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -1146,6 +1146,60 @@ execlists_schedule_out(struct i915_request *rq)
> > i915_request_put(rq);
> > }
> >
> > +static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
> > +{
> > + if (INTEL_GEN(engine->i915) >= 12)
> > + return 0x60;
> > + else if (INTEL_GEN(engine->i915) >= 9)
> > + return 0x54;
> > + else if (engine->class == RENDER_CLASS)
> > + return 0x58;
> > + else
> > + return -1;
> > +}
> > +
> > +static void
> > +execlists_check_context(const struct intel_context *ce,
> > + const struct intel_engine_cs *engine)
> > +{
> > + const struct intel_ring *ring = ce->ring;
> > + u32 *regs = ce->lrc_reg_state;
> > + int x;
> > +
> > + if (regs[CTX_RING_START] != i915_ggtt_offset(ring->vma)) {
> > + pr_err_once("%s: context submitted with incorrect
> > RING_BUFFER_START [%08x], expected %08x\n",
> > + engine->name,
> > + regs[CTX_RING_START],
> > + i915_ggtt_offset(ring->vma));
> > + regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
> > + }
> > +
> > + if ((regs[CTX_RING_CTL] & ~(RING_WAIT | RING_WAIT_SEMAPHORE)) !=
> > + (RING_CTL_SIZE(ring->size) | RING_VALID)) {
> > + pr_err_once("%s: context submitted with incorrect
> > RING_BUFFER_CONTROL [%08x], expected %08x\n",
> > + engine->name,
> > + regs[CTX_RING_CTL],
> > + (u32)(RING_CTL_SIZE(ring->size) | RING_VALID));
> > + regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
>
> We are going to submit by clearing the waits. First I thought this will
> lead to disaster but the hardware works so that we clear on writing '1'.
Afaik, they are only indicator bits. So the HW ignores those bits when
we write to the register.
> > + if (regs[CTX_BB_STATE] != RING_BB_PPGTT) {
> > + pr_err_once("%s: context submitted with incorrect BB_STATE
> > [%08x], expected %08x\n",
> > + engine->name,
> > + regs[CTX_BB_STATE],
> > + RING_BB_PPGTT);
> > + regs[CTX_BB_STATE] = RING_BB_PPGTT;
> > + }
> > +
> > + x = lrc_ring_mi_mode(engine);
> > + if (x != -1 && regs[x + 1] & STOP_RING) {
> > + pr_err_once("%s: context submitted with STOP_RING [%08x] in
> > RING_MI_MODE\n",
> > + engine->name, regs[x + 1]);
> > + regs[x + 1] &= ~STOP_RING;
> > + regs[x + 1] |= STOP_RING << 16;
>
> Ok you want only to care about this one. Was pondering of restoring rest
> of the state from previous.
It was mostly in the spirit of "now that we are here, we might as well
fix it up". It's mainly the paranoia in trying to ascertain if we are
feeding garbage into the GPU. There's probably a lot more we can check,
but the ring registers are essential :)
> Will the hardware even care on masks at this point or is the saving part
> setting them accordingly?
Aiui, it uses the masks on the implicit LRI in the context restore to
control where or not to actually apply the bits. Not that I have checked
to see what the HW is doing (we will see if it ever flags an error), but
memory says from elsewere it uses 0x.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Pretty print the i915_active
Chris Wilson writes:
> If the idle_pulse fails to flush the i915_active, dump the tree to see
> if that has any clues.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> .../drm/i915/gt/selftest_engine_heartbeat.c | 4 ++
> drivers/gpu/drm/i915/i915_active.h| 2 +
> drivers/gpu/drm/i915/selftests/i915_active.c | 45 +++
> 3 files changed, 51 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
> b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
> index 155c508024df..131c49ddf33f 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
> @@ -100,8 +100,12 @@ static int __live_idle_pulse(struct intel_engine_cs
> *engine,
> pulse_unlock_wait(p); /* synchronize with the retirement callback */
>
> if (!i915_active_is_idle(>active)) {
> + struct drm_printer m = drm_err_printer("pulse");
> +
> pr_err("%s: heartbeat pulse did not flush idle tasks\n",
> engine->name);
> + i915_active_print(>active, );
> +
> err = -EINVAL;
> goto out;
> }
> diff --git a/drivers/gpu/drm/i915/i915_active.h
> b/drivers/gpu/drm/i915/i915_active.h
> index 4f52fe6146d2..44859356ce97 100644
> --- a/drivers/gpu/drm/i915/i915_active.h
> +++ b/drivers/gpu/drm/i915/i915_active.h
> @@ -214,4 +214,6 @@ int i915_active_acquire_preallocate_barrier(struct
> i915_active *ref,
> void i915_active_acquire_barrier(struct i915_active *ref);
> void i915_request_add_active_barriers(struct i915_request *rq);
>
> +void i915_active_print(struct i915_active *ref, struct drm_printer *m);
> +
> #endif /* _I915_ACTIVE_H_ */
> diff --git a/drivers/gpu/drm/i915/selftests/i915_active.c
> b/drivers/gpu/drm/i915/selftests/i915_active.c
> index 96513a7d4739..260b0ee5d1e3 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_active.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_active.c
> @@ -205,3 +205,48 @@ int i915_active_live_selftests(struct drm_i915_private
> *i915)
>
> return i915_subtests(tests, i915);
> }
> +
> +static struct intel_engine_cs *node_to_barrier(struct active_node *it)
> +{
> + struct intel_engine_cs *engine;
> +
> + if (!is_barrier(>base))
> + return NULL;
> +
> + engine = __barrier_to_engine(it);
> + smp_rmb(); /* serialise with add_active_barriers */
> + if (!is_barrier(>base))
> + return NULL;
> +
> + return engine;
> +}
> +
> +void i915_active_print(struct i915_active *ref, struct drm_printer *m)
> +{
> + drm_printf(m, "active %pS:%pS\n", ref->active, ref->retire);
> + drm_printf(m, "\tcount: %d\n", atomic_read(>count));
> + drm_printf(m, "\tpreallocated barriers? %s\n",
> +yesno(!llist_empty(>preallocated_barriers)));
> +
> + if (i915_active_acquire_if_busy(ref)) {
> + struct active_node *it, *n;
> +
> + rbtree_postorder_for_each_entry_safe(it, n, >tree, node) {
> + struct intel_engine_cs *engine;
> +
> + engine = node_to_barrier(it);
> + if (engine) {
> + drm_printf(m, "\tbarrier: %s\n", engine->name);
> + continue;
> + }
> +
> + if (i915_active_fence_isset(>base)) {
> + drm_printf(m,
> +"\ttimeline: %llx\n", it->timeline);
> + continue;
> + }
> + }
> +
> + i915_active_release(ref);
> + }
> +}
> --
> 2.24.0.rc1
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Pretty print the i915_active
Quoting Chris Wilson (2019-10-31 14:18:56) > My memory says, and my assumption in this code, is that the > the iterator is safe against insertions -- we won't get horribly lost if > the tree is rebalanced as we walk. Actually, the iterator is not perfect across rebalances. It won't matter here in the selftest, since we are the only accessor, the two other users deserve throught. In __active_retire, we have exclusive access to the tree as we are freeing the nodes. Safe. In i915_active_wait() [we can't take the mutex here due to shrinker inversions!], we walk the tree to kick signaling on the nodes. So the iterator is not perfect, but calling enable_signaling() is mostly an optimisation so that we don't have to wait upon the background flush. So I think we are safe to miss nodes, so long as the iterator itself is bounded (which it must be). -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/execlists: Verify context register state before execution
Chris Wilson writes:
> Check that the context's ring register state still matches our
> expectations prior to execution.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 73 -
> drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 4 +-
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 4 +-
> 3 files changed, 63 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 5f61cd128d9c..666e70931524 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1146,6 +1146,60 @@ execlists_schedule_out(struct i915_request *rq)
> i915_request_put(rq);
> }
>
> +static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
> +{
> + if (INTEL_GEN(engine->i915) >= 12)
> + return 0x60;
> + else if (INTEL_GEN(engine->i915) >= 9)
> + return 0x54;
> + else if (engine->class == RENDER_CLASS)
> + return 0x58;
> + else
> + return -1;
> +}
> +
> +static void
> +execlists_check_context(const struct intel_context *ce,
> + const struct intel_engine_cs *engine)
> +{
> + const struct intel_ring *ring = ce->ring;
> + u32 *regs = ce->lrc_reg_state;
> + int x;
> +
> + if (regs[CTX_RING_START] != i915_ggtt_offset(ring->vma)) {
> + pr_err_once("%s: context submitted with incorrect
> RING_BUFFER_START [%08x], expected %08x\n",
> + engine->name,
> + regs[CTX_RING_START],
> + i915_ggtt_offset(ring->vma));
> + regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
> + }
> +
> + if ((regs[CTX_RING_CTL] & ~(RING_WAIT | RING_WAIT_SEMAPHORE)) !=
> + (RING_CTL_SIZE(ring->size) | RING_VALID)) {
> + pr_err_once("%s: context submitted with incorrect
> RING_BUFFER_CONTROL [%08x], expected %08x\n",
> + engine->name,
> + regs[CTX_RING_CTL],
> + (u32)(RING_CTL_SIZE(ring->size) | RING_VALID));
> + regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
We are going to submit by clearing the waits. First I thought this will
lead to disaster but the hardware works so that we clear on writing '1'.
> + }
> +
> + if (regs[CTX_BB_STATE] != RING_BB_PPGTT) {
> + pr_err_once("%s: context submitted with incorrect BB_STATE
> [%08x], expected %08x\n",
> + engine->name,
> + regs[CTX_BB_STATE],
> + RING_BB_PPGTT);
> + regs[CTX_BB_STATE] = RING_BB_PPGTT;
> + }
> +
> + x = lrc_ring_mi_mode(engine);
> + if (x != -1 && regs[x + 1] & STOP_RING) {
> + pr_err_once("%s: context submitted with STOP_RING [%08x] in
> RING_MI_MODE\n",
> + engine->name, regs[x + 1]);
> + regs[x + 1] &= ~STOP_RING;
> + regs[x + 1] |= STOP_RING << 16;
Ok you want only to care about this one. Was pondering of restoring rest
of the state from previous.
Will the hardware even care on masks at this point or is the saving part
setting them accordingly?
Not affecting this patch tho, just curious.
Reviewed-by: Mika Kuoppala
> + }
> +}
> +
> static u64 execlists_update_context(const struct i915_request *rq)
> {
> struct intel_context *ce = rq->context;
> @@ -1154,6 +1208,9 @@ static u64 execlists_update_context(const struct
> i915_request *rq)
> ce->lrc_reg_state[CTX_RING_TAIL] =
> intel_ring_set_tail(rq->ring, rq->tail);
>
> + if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> + execlists_check_context(ce, rq->engine);
> +
> /*
>* Make sure the context image is complete before we submit it to HW.
>*
> @@ -2355,7 +2412,7 @@ __execlists_update_reg_state(const struct intel_context
> *ce,
> GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
> GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
>
> - regs[CTX_RING_BUFFER_START] = i915_ggtt_offset(ring->vma);
> + regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
> regs[CTX_RING_HEAD] = ring->head;
> regs[CTX_RING_TAIL] = ring->tail;
>
> @@ -2942,18 +2999,6 @@ static void reset_csb_pointers(struct intel_engine_cs
> *engine)
> >csb_status[reset_value]);
> }
>
> -static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
> -{
> - if (INTEL_GEN(engine->i915) >= 12)
> - return 0x60;
> - else if (INTEL_GEN(engine->i915) >= 9)
> - return 0x54;
> - else if (engine->class == RENDER_CLASS)
> - return 0x58;
> - else
> - return -1;
> -}
> -
> static void __execlists_reset_reg_state(const struct intel_context *ce,
> const struct
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/12] drm/i915: Handle a few more cases for crtc hw/uapi split, v3.
== Series Details ==
Series: series starting with [01/12] drm/i915: Handle a few more cases for crtc
hw/uapi split, v3.
URL : https://patchwork.freedesktop.org/series/68818/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7228 -> Patchwork_15089
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15089/index.html
Known issues
Here are the changes found in Patchwork_15089 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([fdo#109635 ])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15089/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][3] -> [DMESG-WARN][4] ([fdo#102614])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15089/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15089/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
* igt@gem_exec_suspend@basic-s3:
- {fi-cml-s}: [DMESG-WARN][7] ([fdo#111764]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-cml-s/igt@gem_exec_susp...@basic-s3.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15089/fi-cml-s/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live_blt:
- fi-bsw-n3050: [DMESG-FAIL][9] ([fdo#112176]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-bsw-n3050/igt@i915_selftest@live_blt.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15089/fi-bsw-n3050/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-u4}:[INCOMPLETE][11] ([fdo#107713] / [fdo#108569]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15089/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-7500u: [FAIL][13] ([fdo#109483]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15089/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111045] / [fdo#111096]) ->
[FAIL][16] ([fdo#111407])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15089/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
[fdo#112176]: https://bugs.freedesktop.org/show_bug.cgi?id=112176
Participating hosts (50 -> 41)
--
Additional (1): fi-kbl-soraka
Missing(10): fi-ilk-m540 fi-tgl-u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-bwr-2160 fi-gdg-551 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7228 -> Patchwork_15089
CI-20190529: 20190529
CI_DRM_7228: 5efc505498d2612451f6230a6347f4e0e1960e50 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5253: d46ccb32cf693e8d8253543e9a4fbe5eaef4aa41 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15089: 11fff1570363ce0ec997d6655f410943f69ba036 @
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Pretty print the i915_active
Quoting Mika Kuoppala (2019-10-31 14:11:58)
> Chris Wilson writes:
>
> > If the idle_pulse fails to flush the i915_active, dump the tree to see
> > if that has any clues.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > .../drm/i915/gt/selftest_engine_heartbeat.c | 4 ++
> > drivers/gpu/drm/i915/i915_active.h| 2 +
> > drivers/gpu/drm/i915/selftests/i915_active.c | 45 +++
> > 3 files changed, 51 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
> > b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
> > index 155c508024df..131c49ddf33f 100644
> > --- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
> > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
> > @@ -100,8 +100,12 @@ static int __live_idle_pulse(struct intel_engine_cs
> > *engine,
> > pulse_unlock_wait(p); /* synchronize with the retirement callback */
> >
> > if (!i915_active_is_idle(>active)) {
> > + struct drm_printer m = drm_err_printer("pulse");
> > +
> > pr_err("%s: heartbeat pulse did not flush idle tasks\n",
> > engine->name);
> > + i915_active_print(>active, );
> > +
> > err = -EINVAL;
> > goto out;
> > }
> > diff --git a/drivers/gpu/drm/i915/i915_active.h
> > b/drivers/gpu/drm/i915/i915_active.h
> > index 4f52fe6146d2..44859356ce97 100644
> > --- a/drivers/gpu/drm/i915/i915_active.h
> > +++ b/drivers/gpu/drm/i915/i915_active.h
> > @@ -214,4 +214,6 @@ int i915_active_acquire_preallocate_barrier(struct
> > i915_active *ref,
> > void i915_active_acquire_barrier(struct i915_active *ref);
> > void i915_request_add_active_barriers(struct i915_request *rq);
> >
> > +void i915_active_print(struct i915_active *ref, struct drm_printer *m);
> > +
> > #endif /* _I915_ACTIVE_H_ */
> > diff --git a/drivers/gpu/drm/i915/selftests/i915_active.c
> > b/drivers/gpu/drm/i915/selftests/i915_active.c
> > index 96513a7d4739..260b0ee5d1e3 100644
> > --- a/drivers/gpu/drm/i915/selftests/i915_active.c
> > +++ b/drivers/gpu/drm/i915/selftests/i915_active.c
> > @@ -205,3 +205,48 @@ int i915_active_live_selftests(struct drm_i915_private
> > *i915)
> >
> > return i915_subtests(tests, i915);
> > }
> > +
> > +static struct intel_engine_cs *node_to_barrier(struct active_node *it)
> > +{
> > + struct intel_engine_cs *engine;
> > +
> > + if (!is_barrier(>base))
> > + return NULL;
> > +
> > + engine = __barrier_to_engine(it);
> > + smp_rmb(); /* serialise with add_active_barriers */
>
> I did find the pair. Builds confidence.
>
> > + if (!is_barrier(>base))
> > + return NULL;
> > +
> > + return engine;
> > +}
> > +
> > +void i915_active_print(struct i915_active *ref, struct drm_printer *m)
> > +{
> > + drm_printf(m, "active %pS:%pS\n", ref->active, ref->retire);
> > + drm_printf(m, "\tcount: %d\n", atomic_read(>count));
> > + drm_printf(m, "\tpreallocated barriers? %s\n",
> > +yesno(!llist_empty(>preallocated_barriers)));
> > +
> > + if (i915_active_acquire_if_busy(ref)) {
> > + struct active_node *it, *n;
> > +
> > + rbtree_postorder_for_each_entry_safe(it, n, >tree, node)
> > {
> > + struct intel_engine_cs *engine;
> > +
>
> Does the aquire of ref keep the other lefs alive?
> we seem to be safe on interation but the poking about
> the fence set and timeline below is a question mark.
It prevents the tree+nodes from being freed, so we only have to worry
about the validity of the meaning of the contents.
My memory says, and my assumption in this code, is that the
the iterator is safe against insertions -- we won't get horribly lost if
the tree is rebalanced as we walk.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Pretty print the i915_active
Chris Wilson writes:
> If the idle_pulse fails to flush the i915_active, dump the tree to see
> if that has any clues.
>
> Signed-off-by: Chris Wilson
> ---
> .../drm/i915/gt/selftest_engine_heartbeat.c | 4 ++
> drivers/gpu/drm/i915/i915_active.h| 2 +
> drivers/gpu/drm/i915/selftests/i915_active.c | 45 +++
> 3 files changed, 51 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
> b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
> index 155c508024df..131c49ddf33f 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
> @@ -100,8 +100,12 @@ static int __live_idle_pulse(struct intel_engine_cs
> *engine,
> pulse_unlock_wait(p); /* synchronize with the retirement callback */
>
> if (!i915_active_is_idle(>active)) {
> + struct drm_printer m = drm_err_printer("pulse");
> +
> pr_err("%s: heartbeat pulse did not flush idle tasks\n",
> engine->name);
> + i915_active_print(>active, );
> +
> err = -EINVAL;
> goto out;
> }
> diff --git a/drivers/gpu/drm/i915/i915_active.h
> b/drivers/gpu/drm/i915/i915_active.h
> index 4f52fe6146d2..44859356ce97 100644
> --- a/drivers/gpu/drm/i915/i915_active.h
> +++ b/drivers/gpu/drm/i915/i915_active.h
> @@ -214,4 +214,6 @@ int i915_active_acquire_preallocate_barrier(struct
> i915_active *ref,
> void i915_active_acquire_barrier(struct i915_active *ref);
> void i915_request_add_active_barriers(struct i915_request *rq);
>
> +void i915_active_print(struct i915_active *ref, struct drm_printer *m);
> +
> #endif /* _I915_ACTIVE_H_ */
> diff --git a/drivers/gpu/drm/i915/selftests/i915_active.c
> b/drivers/gpu/drm/i915/selftests/i915_active.c
> index 96513a7d4739..260b0ee5d1e3 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_active.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_active.c
> @@ -205,3 +205,48 @@ int i915_active_live_selftests(struct drm_i915_private
> *i915)
>
> return i915_subtests(tests, i915);
> }
> +
> +static struct intel_engine_cs *node_to_barrier(struct active_node *it)
> +{
> + struct intel_engine_cs *engine;
> +
> + if (!is_barrier(>base))
> + return NULL;
> +
> + engine = __barrier_to_engine(it);
> + smp_rmb(); /* serialise with add_active_barriers */
I did find the pair. Builds confidence.
> + if (!is_barrier(>base))
> + return NULL;
> +
> + return engine;
> +}
> +
> +void i915_active_print(struct i915_active *ref, struct drm_printer *m)
> +{
> + drm_printf(m, "active %pS:%pS\n", ref->active, ref->retire);
> + drm_printf(m, "\tcount: %d\n", atomic_read(>count));
> + drm_printf(m, "\tpreallocated barriers? %s\n",
> +yesno(!llist_empty(>preallocated_barriers)));
> +
> + if (i915_active_acquire_if_busy(ref)) {
> + struct active_node *it, *n;
> +
> + rbtree_postorder_for_each_entry_safe(it, n, >tree, node) {
> + struct intel_engine_cs *engine;
> +
Does the aquire of ref keep the other lefs alive?
we seem to be safe on interation but the poking about
the fence set and timeline below is a question mark.
-Mika
> + engine = node_to_barrier(it);
> + if (engine) {
> + drm_printf(m, "\tbarrier: %s\n", engine->name);
> + continue;
> + }
> +
> + if (i915_active_fence_isset(>base)) {
> + drm_printf(m,
> +"\ttimeline: %llx\n", it->timeline);
> + continue;
> + }
> + }
> +
> + i915_active_release(ref);
> + }
> +}
> --
> 2.24.0.rc1
>
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/12] drm/i915: Handle a few more cases for crtc hw/uapi split, v3.
== Series Details == Series: series starting with [01/12] drm/i915: Handle a few more cases for crtc hw/uapi split, v3. URL : https://patchwork.freedesktop.org/series/68818/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9b2cc20d8bdd drm/i915: Handle a few more cases for crtc hw/uapi split, v3. 78143d4c9617 drm/i915: Add aliases for uapi and hw to crtc_state -:67: WARNING:LONG_LINE: line over 100 characters #67: FILE: drivers/gpu/drm/i915/display/intel_display.h:453: + to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, >base total: 0 errors, 1 warnings, 0 checks, 83 lines checked eb466377bcbc drm/i915: Perform manual conversions for crtc uapi/hw split, v2. 1fbed6b1a84d drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw. -:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #10: Split up crtc_state->base to hw where appropriate. This is done using the following patch: -:1414: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #1414: FILE: drivers/gpu/drm/i915/display/intel_display.c:17290: + crtc_state->hw.active = crtc_state->hw.enable = total: 0 errors, 1 warnings, 1 checks, 2062 lines checked f959eaf1a286 drm/i915: Perform automated conversions for crtc uapi/hw split, base -> uapi. -:2400: ERROR:CODE_INDENT: code indent should use tabs where possible #2400: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:211: +^I^I^I^I new_crtc_state->uapi.event);$ -:2400: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #2400: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:211: + drm_crtc_arm_vblank_event(>base, + new_crtc_state->uapi.event); total: 1 errors, 0 warnings, 1 checks, 2552 lines checked b358921c226b drm/i915: Complete crtc hw/uapi split, v6. -:15: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #15: - Clear crtc_state->hw on disable, instead of using clear_intel_crtc_state(). total: 0 errors, 1 warnings, 0 checks, 256 lines checked c676c7bb5999 drm/i915: Add aliases for uapi and hw to plane_state -:49: WARNING:LINE_SPACING: Missing a blank line after declarations #49: FILE: drivers/gpu/drm/i915/display/intel_atomic_plane.c:112: + struct intel_plane_state *plane_state = to_intel_plane_state(state); + WARN_ON(plane_state->vma); total: 0 errors, 1 warnings, 0 checks, 59 lines checked 0ecc60519b7c drm/i915: Perform manual conversions for plane uapi/hw split, v2. c2b6232f3d9c drm/i915: Perform automated conversions for plane uapi/hw split, base -> hw. -:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #14: identifier x =~ "^(crtc|fb|alpha|pixel_blend_mode|rotation|color_encoding|color_range)$"; -:921: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "plane_state->hw.fb" #921: FILE: drivers/gpu/drm/i915/intel_pm.c:804: + return plane_state->hw.fb != NULL; total: 0 errors, 1 warnings, 1 checks, 898 lines checked 55cbd4882027 drm/i915: Perform automated conversions for plane uapi/hw split, base -> uapi. -:745: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #745: FILE: drivers/gpu/drm/i915/display/intel_display.c:11181: + unsigned width = drm_rect_width(_state->uapi.dst); -:746: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #746: FILE: drivers/gpu/drm/i915/display/intel_display.c:11182: + unsigned height = drm_rect_height(_state->uapi.dst); -:814: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #814: FILE: drivers/gpu/drm/i915/display/intel_display.c:11781: + plane_state->uapi.visible = visible = false; -:1541: WARNING:LONG_LINE: line over 100 characters #1541: FILE: drivers/gpu/drm/i915/intel_pm.c:3103: + (drm_rect_width(>uapi.dst) != drm_rect_width(>uapi.src) >> 16 || -:1542: WARNING:LONG_LINE: line over 100 characters #1542: FILE: drivers/gpu/drm/i915/intel_pm.c:3104: +drm_rect_height(>uapi.dst) != drm_rect_height(>uapi.src) >> 16); total: 0 errors, 4 warnings, 1 checks, 1438 lines checked 8f679719a098 drm/i915: Complete plane hw and uapi split, v2. -:143: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u16' over 'uint16_t' #143: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:538: + uint16_t pixel_blend_mode; total: 0 errors, 0 warnings, 1 checks, 107 lines checked 11fff1570363 drm/i915: Remove special case slave handling during hw programming, v3. -:19: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #19: - Use the correct color_plane for pre-gen11 by using planar_linked_plane != NULL. total: 0 errors, 1
[Intel-gfx] [PATCH] drm/i915/selftests: Perform some basic cycle counting of MI ops
Some basic information that is useful to know, such as how many cycles
is a MI_NOOP.
Signed-off-by: Chris Wilson
Cc: Anna Karas
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 324 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
2 files changed, 324 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index 3880f07c29b8..f8697b784955 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -4,7 +4,329 @@
* Copyright © 2018 Intel Corporation
*/
-#include "../i915_selftest.h"
+#include
+
+#include "i915_selftest.h"
+#include "selftests/igt_flush_test.h"
+
+#define COUNT 5
+
+static int cmp_u32(const void *A, const void *B)
+{
+ const u32 *a = A, *b = B;
+
+ if (*a < *b)
+ return -1;
+ else if (*a > *b)
+ return 1;
+ else
+ return 0;
+}
+
+static int write_timestamp(struct i915_request *rq, int slot)
+{
+ u32 cmd;
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
+ if (INTEL_GEN(rq->i915) >= 8)
+ cmd++;
+ *cs++ = cmd;
+ *cs++ = rq->engine->mmio_base + 0x358;
+ *cs++ = i915_request_active_timeline(rq)->hwsp_offset +
+ slot * sizeof(u32);
+ *cs++ = 0;
+
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
+static struct i915_vma *create_empty_batch(struct intel_context *ce)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ u32 *cs;
+ int err;
+
+ obj = i915_gem_object_create_internal(ce->engine->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ i915_gem_object_put(obj);
+ return ERR_CAST(cs);
+ }
+
+ cs[0] = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(obj);
+ i915_gem_object_unpin_map(obj);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static u32 trifilter(u32 *a)
+{
+ u64 sum;
+
+ sort(a, COUNT, sizeof(*a), cmp_u32, NULL);
+
+ sum += mul_u32_u32(a[2], 2);
+ sum += a[1];
+ sum += a[3];
+
+ return sum >> 2;
+}
+
+static int perf_mi_bb_start(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+ return 0;
+
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce = engine->kernel_context;
+ struct i915_vma *batch;
+ u32 cycles[COUNT];
+ int i;
+
+ batch = create_empty_batch(ce);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ break;
+ }
+
+ err = i915_vma_sync(batch);
+ if (err) {
+ i915_vma_put(batch);
+ break;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cycles); i++) {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ err = write_timestamp(rq, 2);
+ if (err)
+ goto out;
+
+ err = rq->engine->emit_bb_start(rq,
+ batch->node.start, 8,
+ 0);
+ if (err)
+ goto out;
+
+ err = write_timestamp(rq, 3);
+ if (err)
+ goto out;
+
+out:
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+ if (err)
+ break;
+
+ cycles[i] = rq->hwsp_seqno[3] - rq->hwsp_seqno[2];
+ }
+ i915_vma_put(batch);
+ if (err)
+ break;
+
+ pr_info("%s:
Re: [Intel-gfx] [PATCH] drm/i915: update rawclk also on resume
On Thu, Oct 31, 2019 at 01:14:07PM +0200, Jani Nikula wrote:
> Since CNP it's possible for rawclk to have two different values, 19.2
> and 24 MHz. If the value indicated by SFUSE_STRAP register is different
> from the power on default for PCH_RAWCLK_FREQ, we'll end up having a
> mismatch between the rawclk hardware and software states after
> suspend/resume. On previous platforms this used to work by accident,
> because the power on defaults worked just fine.
>
> Update the rawclk also on resume. The natural place to do this is
> intel_modeset_init_hw(), however VLV/CHV need it done before
> intel_power_domains_init_hw(). Split the update accordingly, even if
> that's slighly ugly. This means moving the update later for non-VLV/CHV
> platforms in probe.
>
> Reported-by: Shawn Lee
> Cc: Shawn Lee
> Cc: Ville Syrjala
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 +
> drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++
> drivers/gpu/drm/i915/i915_drv.c| 3 ---
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e56a75c07043..e31697fdffd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16610,6 +16610,11 @@ void intel_init_display_hooks(struct
> drm_i915_private *dev_priv)
>
> void intel_modeset_init_hw(struct drm_i915_private *i915)
> {
> + /*
> + * VLV/CHV update rawclk earlier in intel_power_domains_init_hw().
> + */
> + if (!IS_VALLEYVIEW(i915) && !IS_CHERRYVIEW(i915))
> + intel_update_rawclk(i915);
> intel_update_cdclk(i915);
> intel_dump_cdclk_state(>cdclk.hw, "Current CDCLK");
> i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 707ac110e271..999133d1f088 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5015,6 +5015,13 @@ void intel_power_domains_init_hw(struct
> drm_i915_private *i915, bool resume)
>
> power_domains->initializing = true;
>
> + /*
> + * Must happen before power domain init on VLV/CHV, the rest update
> + * rawclk later in intel_modeset_init_hw().
> + */
> + if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> + intel_update_rawclk(i915);
Can't we just do it here unconditionally? I think this gets called on
the resume path as well.
> +
> if (INTEL_GEN(i915) >= 11) {
> icl_display_core_init(i915, resume);
> } else if (IS_CANNONLAKE(i915)) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 21273b516dbe..62906336298a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -296,9 +296,6 @@ static int i915_driver_modeset_probe(struct
> drm_i915_private *i915)
> if (ret)
> goto cleanup_vga_client;
>
> - /* must happen before intel_power_domains_init_hw() on VLV/CHV */
> - intel_update_rawclk(i915);
> -
> intel_power_domains_init_hw(i915, false);
>
> intel_csr_ucode_init(i915);
> --
> 2.20.1
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: update rawclk also on resume
== Series Details ==
Series: drm/i915: update rawclk also on resume
URL : https://patchwork.freedesktop.org/series/68817/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7228 -> Patchwork_15088
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/index.html
Known issues
Here are the changes found in Patchwork_15088 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_basic@bad-close:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-icl-u3/igt@gem_ba...@bad-close.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/fi-icl-u3/igt@gem_ba...@bad-close.html
* igt@gem_ctx_switch@rcs0:
- fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-bxt-dsi/igt@gem_ctx_swi...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/fi-bxt-dsi/igt@gem_ctx_swi...@rcs0.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-u4}:[INCOMPLETE][7] ([fdo#107713] / [fdo#108569]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-7500u: [FAIL][9] ([fdo#109483]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111045] / [fdo#111096]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
Participating hosts (50 -> 41)
--
Additional (1): fi-kbl-soraka
Missing(10): fi-ilk-m540 fi-tgl-u fi-hsw-4200u fi-bsw-n3050
fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-icl-y fi-bsw-kefka fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7228 -> Patchwork_15088
CI-20190529: 20190529
CI_DRM_7228: 5efc505498d2612451f6230a6347f4e0e1960e50 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5253: d46ccb32cf693e8d8253543e9a4fbe5eaef4aa41 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15088: 853a8863d3fe4157cb8f50dafab5b471c3fef978 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
853a8863d3fe drm/i915: update rawclk also on resume
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15088/index.html
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Re: [Intel-gfx] [PATCH 01/11] drm/i915: Split detaching and removing the vma
On Wed, 30 Oct 2019 at 19:22, Chris Wilson wrote: > > In order to keep the assert_bind_count() valid, we need to hold the vma > page reference until after we drop the bind count. However, we must also > keep the drm_mm_remove_node() as the last action of i915_vma_unbind() so > that it serialises with the unlocked check inside i915_vma_destroy(). So > we need to split up i915_vma_remove() so that we order the detach, drop > pages and remove as required during unbind. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112067 > Signed-off-by: Chris Wilson > Cc: Matthew Auld Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Plump dev_priv all the way to icl_{hdr, sdr_y}_plane_mask()
Minor nit.
s/Plump/Plumb/
M
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Thursday, October 31, 2019 6:59 AM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 4/4] drm/i915: Plump dev_priv all the way to
>icl_{hdr, sdr_y}_plane_mask()
>
>From: Ville Syrjälä
>
>We're going to need platforms specific decisions in
>icl_sdr_y_plane_mask(), so let's plumb dev_priv all the way
>down. For consistency we'll do the same for icl_hdr_plane_mask().
>
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_sprite.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_sprite.h | 24
> 3 files changed, 19 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 8e1160f8d988..b690ea26cc89 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -9613,7 +9613,7 @@ static void bdw_set_pipemisc(const struct
>intel_crtc_state *crtc_state)
> PIPEMISC_YUV420_MODE_FULL_BLEND;
>
> if (INTEL_GEN(dev_priv) >= 11 &&
>- (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
>+ (crtc_state->active_planes & ~(icl_hdr_plane_mask(dev_priv) |
> BIT(PLANE_CURSOR))) == 0)
> val |= PIPEMISC_HDR_MODE_PRECISION;
>
>@@ -11955,7 +11955,7 @@ static int icl_check_nv12_planes(struct
>intel_crtc_state *crtc_state)
> continue;
>
> for_each_intel_plane_on_crtc(_priv->drm, crtc, linked) {
>- if (!icl_is_sdr_y_plane(linked->id))
>+ if (!icl_is_sdr_y_plane(dev_priv, linked->id))
> continue;
>
> if (crtc_state->active_planes & BIT(linked->id))
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index ba344d9e2e19..b486287b9fb1 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -2849,7 +2849,7 @@ static const u32 *icl_get_plane_formats(struct
>drm_i915_private *dev_priv,
> if (icl_is_hdr_plane(dev_priv, plane_id)) {
> *num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
> return icl_hdr_plane_formats;
>- } else if (icl_is_sdr_y_plane(plane_id)) {
>+ } else if (icl_is_sdr_y_plane(dev_priv, plane_id)) {
> *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats);
> return icl_sdr_y_plane_formats;
> } else {
>@@ -2910,7 +2910,7 @@ skl_universal_plane_create(struct drm_i915_private
>*dev_priv,
> plane->get_hw_state = skl_plane_get_hw_state;
> plane->check_plane = skl_plane_check;
> plane->min_cdclk = skl_plane_min_cdclk;
>- if (icl_is_sdr_y_plane(plane_id))
>+ if (icl_is_sdr_y_plane(dev_priv, plane_id))
> plane->update_slave = icl_update_slave;
>
> if (INTEL_GEN(dev_priv) >= 11)
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h
>b/drivers/gpu/drm/i915/display/intel_sprite.h
>index ffb03ee640ed..d9efac5e157f 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.h
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.h
>@@ -32,27 +32,33 @@ struct intel_plane *
> skl_universal_plane_create(struct drm_i915_private *dev_priv,
> enum pipe pipe, enum plane_id plane_id);
>
>-static inline u8 icl_sdr_y_plane_mask(void)
>+static inline u8 icl_sdr_y_plane_mask(struct drm_i915_private *dev_priv)
> {
>- return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
>+ if (INTEL_GEN(dev_priv) >= 11)
>+ return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
>+ else
>+ return 0;
> }
>
>-static inline bool icl_is_sdr_y_plane(enum plane_id id)
>+static inline bool icl_is_sdr_y_plane(struct drm_i915_private *dev_priv,
>+enum plane_id plane_id)
> {
>- return icl_sdr_y_plane_mask() & BIT(id);
>+ return icl_sdr_y_plane_mask(dev_priv) & BIT(plane_id);
> }
>
>-static inline u8 icl_hdr_plane_mask(void)
>+static inline u8 icl_hdr_plane_mask(struct drm_i915_private *dev_priv)
> {
>- return BIT(PLANE_PRIMARY) |
>- BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
>+ if (INTEL_GEN(dev_priv) >= 11)
>+ return BIT(PLANE_PRIMARY) |
>+ BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
>+ else
>+ return 0;
> }
>
> static inline bool icl_is_hdr_plane(struct drm_i915_private *dev_priv,
> enum plane_id plane_id)
> {
>- return INTEL_GEN(dev_priv) >= 11 &&
>- icl_hdr_plane_mask() & BIT(plane_id);
>+ return icl_hdr_plane_mask(dev_priv) & BIT(plane_id);
> }
>
> int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
>--
>2.23.0
>
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Assert that the idle_pulse is sent
Chris Wilson writes:
> When checking the heartbeat pulse, we expect it to have been sent by the
> time we have slept. We can verify this by checking the engine serial
> number to see if that matches the predicted pulse serial. It will always
> be true if, and only if, the pulse was sent by itself (as designed by
> the test).
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
> b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
> index 9e7376b592e5..07a2fffe16a1 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
> @@ -97,6 +97,8 @@ static int __live_idle_pulse(struct intel_engine_cs *engine,
> goto out;
> }
>
> + GEM_BUG_ON(READ_ONCE(engine->serial) != engine->wakeref_serial);
> +
Yes the wakeref_serial seems to be our local copy.
Reviewed-by: Mika Kuoppala
The extra space on starting the subtests, at the end of
the file, caught my eye.
> pulse_unlock_wait(p); /* synchronize with the retirement callback */
>
> if (!i915_active_is_idle(>active)) {
> --
> 2.24.0.rc1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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Re: [Intel-gfx] [PATCH 2/6] drm/i915: Simplfy LVDS crtc_mask setup
From this set patches 2,5,6 look all ok to me. Reviewed-by: Juha-Pekka Heikkila On 2.10.2019 19.25, Ville Syrjala wrote: From: Ville Syrjälä We don't need to special case PCH vs. gen4 when setting up the LVDS crtc_mask. Just claim pipes A|B|C work and intel_encoder_possible_crtcs() will drop out any crtc that doesn't exist. v2: Put the special case first to match what most other encoders do Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_lvds.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 13841d7c455b..cf1cd2295b9b 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -899,12 +899,10 @@ void intel_lvds_init(struct drm_i915_private *dev_priv) intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; intel_encoder->port = PORT_NONE; intel_encoder->cloneable = 0; - if (HAS_PCH_SPLIT(dev_priv)) - intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); - else if (IS_GEN(dev_priv, 4)) - intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B); - else + if (INTEL_GEN(dev_priv) < 4) intel_encoder->crtc_mask = BIT(PIPE_B); + else + intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); drm_connector_helper_add(connector, _lvds_connector_helper_funcs); connector->display_info.subpixel_order = SubPixelHorizontalRGB; ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/lmem: add the fake lmem region
On Wed, Oct 30, 2019 at 10:22:37PM +, Matthew Auld wrote: > On Tue, 29 Oct 2019 at 16:51, Matthew Auld wrote: > > > > Intended for upstream testing so that we can still exercise the LMEM > > plumbing and !i915_ggtt_has_aperture paths. Smoke tested on Skull Canyon > > device. This works by allocating an intel_memory_region for a reserved > > portion of system memory, which we treat like LMEM. For the LMEMBAR we > > steal the aperture and 1:1 it map to the stolen region. > > > > To enable simply set the i915 modparam fake_lmem_start= on the kernel > > cmdline with the start of reserved region(see memmap=). The size of the > > region we can use is determined by the size of the mappable aperture, so > > the size of reserved region should be >= mappable_end. For now we only > > enable for the selftests. Depends on CONFIG_DRM_I915_UNSTABLE being > > enabled. > > > > eg. memmap=2G$16G i915.fake_lmem_start=0x4 > > Hi Arek, > > Would you be able to update the fi-skl-lmem kernel cmd line with > s/i915_fake_lmem_start/i915.fake_lmem_start? done ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Drop GEM context as a direct link from i915_request (rev2)
== Series Details == Series: series starting with [1/3] drm/i915: Drop GEM context as a direct link from i915_request (rev2) URL : https://patchwork.freedesktop.org/series/68769/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7223_full -> Patchwork_15073_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15073_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15073_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15073_full: ### IGT changes ### Possible regressions * igt@gem_eio@wait-wedge-1us: - shard-iclb: [PASS][1] -> [SKIP][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-iclb5/igt@gem_...@wait-wedge-1us.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-iclb5/igt@gem_...@wait-wedge-1us.html * igt@gem_exec_parallel@rcs0-fds: - shard-apl: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-apl6/igt@gem_exec_paral...@rcs0-fds.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-apl8/igt@gem_exec_paral...@rcs0-fds.html - shard-kbl: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-kbl6/igt@gem_exec_paral...@rcs0-fds.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-kbl6/igt@gem_exec_paral...@rcs0-fds.html * igt@gem_exec_parallel@vcs0-fds: - shard-iclb: [PASS][7] -> [FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-iclb5/igt@gem_exec_paral...@vcs0-fds.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-iclb5/igt@gem_exec_paral...@vcs0-fds.html * igt@gem_exec_schedule@independent-blt: - shard-skl: [PASS][9] -> [INCOMPLETE][10] +21 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-skl7/igt@gem_exec_sched...@independent-blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-skl8/igt@gem_exec_sched...@independent-blt.html * igt@gem_exec_schedule@preempt-hang-vebox: - shard-skl: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-skl4/igt@gem_exec_sched...@preempt-hang-vebox.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-skl1/igt@gem_exec_sched...@preempt-hang-vebox.html - shard-glk: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-glk7/igt@gem_exec_sched...@preempt-hang-vebox.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-glk3/igt@gem_exec_sched...@preempt-hang-vebox.html - shard-iclb: [PASS][15] -> [DMESG-WARN][16] +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-iclb7/igt@gem_exec_sched...@preempt-hang-vebox.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-iclb2/igt@gem_exec_sched...@preempt-hang-vebox.html * igt@runner@aborted: - shard-kbl: NOTRUN -> ([FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], [FAIL][21], [FAIL][22], [FAIL][23], [FAIL][24], [FAIL][25], [FAIL][26], [FAIL][27]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-kbl3/igt@run...@aborted.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-kbl4/igt@run...@aborted.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-kbl2/igt@run...@aborted.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-kbl2/igt@run...@aborted.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-kbl7/igt@run...@aborted.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-kbl7/igt@run...@aborted.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-kbl6/igt@run...@aborted.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-kbl6/igt@run...@aborted.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-kbl4/igt@run...@aborted.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-kbl6/igt@run...@aborted.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-kbl6/igt@run...@aborted.html - shard-apl: NOTRUN -> ([FAIL][28], [FAIL][29], [FAIL][30], [FAIL][31]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15073/shard-apl8/igt@run...@aborted.html [29]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Drop inspection of execbuf flags during evict
== Series Details ==
Series: drm/i915: Drop inspection of execbuf flags during evict
URL : https://patchwork.freedesktop.org/series/68816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7228 -> Patchwork_15087
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15087/index.html
Known issues
Here are the changes found in Patchwork_15087 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_switch@legacy-render:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15087/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#109635 ] / [fdo#110387])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15087/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [INCOMPLETE][5] ([fdo#107713] / [fdo#109100]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15087/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-u4}:[INCOMPLETE][7] ([fdo#107713] / [fdo#108569]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15087/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-7500u: [FAIL][9] ([fdo#109483]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15087/fi-kbl-7500u/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111045] / [fdo#111096]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7228/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15087/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
Participating hosts (50 -> 42)
--
Additional (1): fi-kbl-soraka
Missing(9): fi-ilk-m540 fi-tgl-u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-icl-y fi-bdw-samus fi-byt-clapper fi-skl-6600u
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7228 -> Patchwork_15087
CI-20190529: 20190529
CI_DRM_7228: 5efc505498d2612451f6230a6347f4e0e1960e50 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5253: d46ccb32cf693e8d8253543e9a4fbe5eaef4aa41 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15087: b8625b68ff2b9702b1bdf2581e9c6a075e9ca2fb @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b8625b68ff2b drm/i915: Drop inspection of execbuf flags during evict
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15087/index.html
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915/gt: Always track callers to intel_rps_mark_interactive()
== Series Details == Series: series starting with [1/5] drm/i915/gt: Always track callers to intel_rps_mark_interactive() URL : https://patchwork.freedesktop.org/series/68770/ State : success == Summary == CI Bug Log - changes from CI_DRM_7223_full -> Patchwork_15072_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15072_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@busy-vcs1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +15 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-iclb2/igt@gem_b...@busy-vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15072/shard-iclb5/igt@gem_b...@busy-vcs1.html * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-iclb4/igt@gem_ctx_isolat...@vcs1-dirty-create.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15072/shard-iclb7/igt@gem_ctx_isolat...@vcs1-dirty-create.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112146]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-iclb7/igt@gem_exec_sched...@preempt-other-chain-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15072/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +16 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-iclb4/igt@gem_exec_sched...@preempt-queue-bsd1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15072/shard-iclb7/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#112037]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-iclb5/igt@gem_persistent_rel...@forked-interruptible-thrashing.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15072/shard-iclb3/igt@gem_persistent_rel...@forked-interruptible-thrashing.html * igt@gem_userptr_blits@map-fixed-invalidate-busy: - shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-hsw2/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15072/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html * igt@i915_selftest@mock_requests: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#112156]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-skl7/igt@i915_selftest@mock_requests.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15072/shard-skl4/igt@i915_selftest@mock_requests.html * igt@kms_atomic@test_only: - shard-snb: [PASS][15] -> [SKIP][16] ([fdo#109271]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-snb1/igt@kms_atomic@test_only.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15072/shard-snb6/igt@kms_atomic@test_only.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-kbl7/igt@kms_cursor_...@pipe-c-cursor-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15072/shard-kbl7/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][19] -> [FAIL][20] ([fdo#105767]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-hsw5/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15072/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html * igt@kms_cursor_legacy@pipe-a-forked-move: - shard-apl: [PASS][21] -> [INCOMPLETE][22] ([fdo#103927]) +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-apl8/igt@kms_cursor_leg...@pipe-a-forked-move.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15072/shard-apl4/igt@kms_cursor_leg...@pipe-a-forked-move.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-glk: [PASS][23] -> [INCOMPLETE][24] ([fdo#103359] / [k.org#198133]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-glk8/igt@kms_f...@flip-vs-suspend-interruptible.html [24]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Always track callers to intel_rps_mark_interactive() (rev2)
== Series Details == Series: drm/i915/gt: Always track callers to intel_rps_mark_interactive() (rev2) URL : https://patchwork.freedesktop.org/series/68764/ State : success == Summary == CI Bug Log - changes from CI_DRM_7223_full -> Patchwork_15071_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15071_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-iclb4/igt@gem_ctx_isolat...@vcs1-dirty-create.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15071/shard-iclb8/igt@gem_ctx_isolat...@vcs1-dirty-create.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-iclb2/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15071/shard-iclb8/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@preempt-self-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112146]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-iclb5/igt@gem_exec_sched...@preempt-self-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15071/shard-iclb2/igt@gem_exec_sched...@preempt-self-bsd.html * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing: - shard-glk: [PASS][7] -> [TIMEOUT][8] ([fdo#112068 ]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-glk5/igt@gem_persistent_rel...@forked-interruptible-faulting-reloc-thrashing.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15071/shard-glk1/igt@gem_persistent_rel...@forked-interruptible-faulting-reloc-thrashing.html - shard-hsw: [PASS][9] -> [FAIL][10] ([fdo#112037]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-hsw2/igt@gem_persistent_rel...@forked-interruptible-faulting-reloc-thrashing.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15071/shard-hsw5/igt@gem_persistent_rel...@forked-interruptible-faulting-reloc-thrashing.html * igt@gem_pwrite@small-gtt-backwards: - shard-apl: [PASS][11] -> [INCOMPLETE][12] ([fdo#103927]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-apl7/igt@gem_pwr...@small-gtt-backwards.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15071/shard-apl8/igt@gem_pwr...@small-gtt-backwards.html * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-apl3/igt@gem_soft...@noreloc-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15071/shard-apl4/igt@gem_soft...@noreloc-s3.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-hsw: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-hsw6/igt@gem_userptr_bl...@dmabuf-unsync.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15071/shard-hsw6/igt@gem_userptr_bl...@dmabuf-unsync.html * igt@gem_workarounds@suspend-resume: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([fdo#104108]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-skl3/igt@gem_workarou...@suspend-resume.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15071/shard-skl5/igt@gem_workarou...@suspend-resume.html * igt@i915_selftest@live_hangcheck: - shard-iclb: [PASS][19] -> [DMESG-FAIL][20] ([fdo#44] / [fdo#111678]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-iclb4/igt@i915_selftest@live_hangcheck.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15071/shard-iclb4/igt@i915_selftest@live_hangcheck.html * igt@i915_selftest@mock_requests: - shard-glk: [PASS][21] -> [INCOMPLETE][22] ([fdo#103359] / [k.org#198133]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-glk9/igt@i915_selftest@mock_requests.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15071/shard-glk8/igt@i915_selftest@mock_requests.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][23] -> [FAIL][24] ([fdo#105767]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7223/shard-hsw5/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15071/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: -
Re: [Intel-gfx] [CI 08/12] drm/i915: Perform manual conversions for plane uapi/hw split, v2.
Op 31-10-2019 om 11:30 schreef Ville Syrjälä:
> On Thu, Oct 31, 2019 at 10:15:41AM +0100, Maarten Lankhorst wrote:
>> Op 30-10-2019 om 17:19 schreef Ville Syrjälä:
>>> On Wed, Oct 30, 2019 at 03:26:53PM +0100, Maarten Lankhorst wrote:
get_crtc_from_states() is called before plane_state is copied to uapi,
so use the uapi state there.
intel_legacy_cursor_update() could probably get away with looking at
the hw state, but for clarity always look at the uapi state.
Changes since v1:
- Convert entirety of intel_legacy_cursor_update (Ville).
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 8 ++--
drivers/gpu/drm/i915/display/intel_display.c | 45 ++-
2 files changed, 27 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 393fb97a3dca..416cfa439f33 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -225,11 +225,11 @@ static struct intel_crtc *
get_crtc_from_states(const struct intel_plane_state *old_plane_state,
const struct intel_plane_state *new_plane_state)
{
- if (new_plane_state->base.crtc)
- return to_intel_crtc(new_plane_state->base.crtc);
+ if (new_plane_state->uapi.crtc)
+ return to_intel_crtc(new_plane_state->uapi.crtc);
- if (old_plane_state->base.crtc)
- return to_intel_crtc(old_plane_state->base.crtc);
+ if (old_plane_state->uapi.crtc)
+ return to_intel_crtc(old_plane_state->uapi.crtc);
return NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e30f467eec67..b0b2c46e4c0a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15357,12 +15357,12 @@ intel_legacy_cursor_update(struct drm_plane
*_plane,
* take the slowpath. Only changing fb or position should be
* in the fastpath.
*/
- if (old_plane_state->base.crtc != >base ||
- old_plane_state->base.src_w != src_w ||
- old_plane_state->base.src_h != src_h ||
- old_plane_state->base.crtc_w != crtc_w ||
- old_plane_state->base.crtc_h != crtc_h ||
- !old_plane_state->base.fb != !fb)
+ if (old_plane_state->uapi.crtc != >base ||
+ old_plane_state->uapi.src_w != src_w ||
+ old_plane_state->uapi.src_h != src_h ||
+ old_plane_state->uapi.crtc_w != crtc_w ||
+ old_plane_state->uapi.crtc_h != crtc_h ||
+ !old_plane_state->uapi.fb != !fb)
goto slow;
new_plane_state =
to_intel_plane_state(intel_plane_duplicate_state(>base));
@@ -15375,16 +15375,16 @@ intel_legacy_cursor_update(struct drm_plane
*_plane,
goto out_free;
}
- drm_atomic_set_fb_for_plane(_plane_state->base, fb);
+ drm_atomic_set_fb_for_plane(_plane_state->uapi, fb);
- new_plane_state->base.src_x = src_x;
- new_plane_state->base.src_y = src_y;
- new_plane_state->base.src_w = src_w;
- new_plane_state->base.src_h = src_h;
- new_plane_state->base.crtc_x = crtc_x;
- new_plane_state->base.crtc_y = crtc_y;
- new_plane_state->base.crtc_w = crtc_w;
- new_plane_state->base.crtc_h = crtc_h;
+ new_plane_state->uapi.src_x = src_x;
+ new_plane_state->uapi.src_y = src_y;
+ new_plane_state->uapi.src_w = src_w;
+ new_plane_state->uapi.src_h = src_h;
+ new_plane_state->uapi.crtc_x = crtc_x;
+ new_plane_state->uapi.crtc_y = crtc_y;
+ new_plane_state->uapi.crtc_w = crtc_w;
+ new_plane_state->uapi.crtc_h = crtc_h;
ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
old_plane_state,
new_plane_state);
@@ -15395,13 +15395,14 @@ intel_legacy_cursor_update(struct drm_plane
*_plane,
if (ret)
goto out_free;
- intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->base.fb),
ORIGIN_FLIP);
- intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->base.fb),
- to_intel_frontbuffer(new_plane_state->base.fb),
+ intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
+ ORIGIN_FLIP);
+ intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
+ to_intel_frontbuffer(new_plane_state->hw.fb),
plane->frontbuffer_bit);
/* Swap plane state */
-
[Intel-gfx] [PATCH 04/12] drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw.
Split up crtc_state->base to hw where appropriate. This is done using the
following patch:
@@
struct intel_crtc_state *T;
identifier x =~
"^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
@@
-T->base.x
+T->hw.x
@@
struct drm_crtc_state *T;
identifier x =~
"^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
@@
-to_intel_crtc_state(T)->base.x
+to_intel_crtc_state(T)->hw.x
Signed-off-by: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/drm_dp_mst_topology.c | 1 +
drivers/gpu/drm/i915/display/icl_dsi.c| 12 +-
drivers/gpu/drm/i915/display/intel_audio.c| 4 +-
drivers/gpu/drm/i915/display/intel_cdclk.c| 8 +-
drivers/gpu/drm/i915/display/intel_color.c| 108
drivers/gpu/drm/i915/display/intel_crt.c | 18 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 18 +-
drivers/gpu/drm/i915/display/intel_display.c | 259 +-
drivers/gpu/drm/i915/display/intel_dp.c | 22 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +-
drivers/gpu/drm/i915/display/intel_dvo.c | 12 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 20 +-
drivers/gpu/drm/i915/display/intel_lspcon.c | 4 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 8 +-
drivers/gpu/drm/i915/display/intel_panel.c| 8 +-
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 12 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 16 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 8 +-
drivers/gpu/drm/i915/display/intel_tv.c | 4 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
drivers/gpu/drm/i915/display/vlv_dsi.c| 10 +-
drivers/gpu/drm/i915/i915_debugfs.c | 8 +-
drivers/gpu/drm/i915/intel_pm.c | 56 ++--
25 files changed, 317 insertions(+), 313 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 85bef73a6763..fddea7acf7d8 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#endif
#include
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 6e398c33a524..4ec493e4755b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -276,7 +276,7 @@ static void configure_dual_link_mode(struct intel_encoder
*encoder,
if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
const struct drm_display_mode *adjusted_mode =
- _config->base.adjusted_mode;
+ _config->hw.adjusted_mode;
u32 dss_ctl2;
u16 hactive = adjusted_mode->crtc_hdisplay;
u16 dl_buffer_depth;
@@ -768,7 +768,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
const struct drm_display_mode *adjusted_mode =
- _config->base.adjusted_mode;
+ _config->hw.adjusted_mode;
enum port port;
enum transcoder dsi_trans;
/* horizontal timings */
@@ -1216,7 +1216,7 @@ static void gen11_dsi_get_timings(struct intel_encoder
*encoder,
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
struct drm_display_mode *adjusted_mode =
- _config->base.adjusted_mode;
+ _config->hw.adjusted_mode;
if (intel_dsi->dual_link) {
adjusted_mode->crtc_hdisplay *= 2;
@@ -1249,9 +1249,9 @@ static void gen11_dsi_get_config(struct intel_encoder
*encoder,
pipe_config->port_clock =
cnl_calc_wrpll_link(dev_priv, _config->dpll_hw_state);
- pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
+ pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
if (intel_dsi->dual_link)
- pipe_config->base.adjusted_mode.crtc_clock *= 2;
+ pipe_config->hw.adjusted_mode.crtc_clock *= 2;
gen11_dsi_get_timings(encoder, pipe_config);
pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
@@ -1269,7 +1269,7 @@ static int gen11_dsi_compute_config(struct intel_encoder
*encoder,
const struct drm_display_mode *fixed_mode =
intel_connector->panel.fixed_mode;
struct drm_display_mode *adjusted_mode =
- _config->base.adjusted_mode;
+ _config->hw.adjusted_mode;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
[Intel-gfx] [PATCH 09/12] drm/i915: Perform automated conversions for plane uapi/hw split, base -> hw.
Split up plane_state->base to hw. This is done using the following patch:
@@
struct intel_plane_state *T;
identifier x =~
"^(crtc|fb|alpha|pixel_blend_mode|rotation|color_encoding|color_range)$";
@@
-T->base.x
+T->hw.x
Signed-off-by: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic.c | 6 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 8 +-
drivers/gpu/drm/i915/display/intel_display.c | 126 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 8 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 90 ++---
drivers/gpu/drm/i915/intel_pm.c | 32 ++---
7 files changed, 136 insertions(+), 136 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 3301c178da03..0a5eee4c350f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -283,9 +283,9 @@ static void intel_atomic_setup_scaler(struct
intel_crtc_scaler_state *scaler_sta
return;
/* set scaler mode */
- if (plane_state && plane_state->base.fb &&
- plane_state->base.fb->format->is_yuv &&
- plane_state->base.fb->format->num_planes > 1) {
+ if (plane_state && plane_state->hw.fb &&
+ plane_state->hw.fb->format->is_yuv &&
+ plane_state->hw.fb->format->num_planes > 1) {
struct intel_plane *plane =
to_intel_plane(plane_state->base.plane);
if (IS_GEN(dev_priv, 9) &&
!IS_GEMINILAKE(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 416cfa439f33..633535b3 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -118,7 +118,7 @@ intel_plane_destroy_state(struct drm_plane *plane,
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
unsigned int cpp;
if (!plane_state->base.visible)
@@ -144,7 +144,7 @@ bool intel_plane_calc_min_cdclk(struct intel_atomic_state
*state,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
- struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
struct intel_crtc_state *crtc_state;
if (!plane_state->base.visible || !plane->min_cdclk)
@@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
struct intel_plane_state
*new_plane_state)
{
struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
- const struct drm_framebuffer *fb = new_plane_state->base.fb;
+ const struct drm_framebuffer *fb = new_plane_state->hw.fb;
int ret;
new_crtc_state->active_planes &= ~BIT(plane->id);
@@ -192,7 +192,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
new_crtc_state->min_cdclk[plane->id] = 0;
new_plane_state->base.visible = false;
- if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
+ if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
return 0;
ret = plane->check_plane(new_crtc_state, new_plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f244c6a010bc..9c660108d972 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2215,7 +2215,7 @@ u32 intel_fb_xy_to_linear(int x, int y,
const struct intel_plane_state *state,
int color_plane)
{
- const struct drm_framebuffer *fb = state->base.fb;
+ const struct drm_framebuffer *fb = state->hw.fb;
unsigned int cpp = fb->format->cpp[color_plane];
unsigned int pitch = state->color_plane[color_plane].stride;
@@ -2316,8 +2316,8 @@ static u32 intel_plane_adjust_aligned_offset(int *x, int
*y,
int color_plane,
u32 old_offset, u32 new_offset)
{
- return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane,
- state->base.rotation,
+ return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
+ state->hw.rotation,
[Intel-gfx] [PATCH 10/12] drm/i915: Perform automated conversions for plane uapi/hw split, base -> uapi.
Split up plane_state->base to uapi. This is done using the following patch,
ran after the previous commit that splits out any hw references:
@@
struct intel_plane_state *T;
identifier x;
@@
-T->base.x
+T->uapi.x
@@
struct intel_plane_state *T;
@@
-T->base
+T->uapi
Signed-off-by: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic.c | 2 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 30 +-
drivers/gpu/drm/i915/display/intel_display.c | 262 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 12 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 136 -
drivers/gpu/drm/i915/intel_pm.c | 57 ++--
7 files changed, 251 insertions(+), 250 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 0a5eee4c350f..ea24a45dab86 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -286,7 +286,7 @@ static void intel_atomic_setup_scaler(struct
intel_crtc_scaler_state *scaler_sta
if (plane_state && plane_state->hw.fb &&
plane_state->hw.fb->format->is_yuv &&
plane_state->hw.fb->format->num_planes > 1) {
- struct intel_plane *plane =
to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane =
to_intel_plane(plane_state->uapi.plane);
if (IS_GEN(dev_priv, 9) &&
!IS_GEMINILAKE(dev_priv)) {
mode = SKL_PS_SCALER_MODE_NV12;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 633535b3..d456b3dc200c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -56,7 +56,7 @@ struct intel_plane *intel_plane_alloc(void)
return ERR_PTR(-ENOMEM);
}
- __drm_atomic_helper_plane_reset(>base, _state->base);
+ __drm_atomic_helper_plane_reset(>base, _state->uapi);
plane_state->scaler_id = -1;
return plane;
@@ -88,12 +88,12 @@ intel_plane_duplicate_state(struct drm_plane *plane)
if (!intel_state)
return NULL;
- __drm_atomic_helper_plane_duplicate_state(plane, _state->base);
+ __drm_atomic_helper_plane_duplicate_state(plane, _state->uapi);
intel_state->vma = NULL;
intel_state->flags = 0;
- return _state->base;
+ return _state->uapi;
}
/**
@@ -111,7 +111,7 @@ intel_plane_destroy_state(struct drm_plane *plane,
struct intel_plane_state *plane_state = to_intel_plane_state(state);
WARN_ON(plane_state->vma);
- __drm_atomic_helper_plane_destroy_state(_state->base);
+ __drm_atomic_helper_plane_destroy_state(_state->uapi);
kfree(plane_state);
}
@@ -121,7 +121,7 @@ unsigned int intel_plane_data_rate(const struct
intel_crtc_state *crtc_state,
const struct drm_framebuffer *fb = plane_state->hw.fb;
unsigned int cpp;
- if (!plane_state->base.visible)
+ if (!plane_state->uapi.visible)
return 0;
cpp = fb->format->cpp[0];
@@ -147,7 +147,7 @@ bool intel_plane_calc_min_cdclk(struct intel_atomic_state
*state,
struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
struct intel_crtc_state *crtc_state;
- if (!plane_state->base.visible || !plane->min_cdclk)
+ if (!plane_state->uapi.visible || !plane->min_cdclk)
return false;
crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
@@ -181,7 +181,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
const struct intel_plane_state
*old_plane_state,
struct intel_plane_state
*new_plane_state)
{
- struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
const struct drm_framebuffer *fb = new_plane_state->hw.fb;
int ret;
@@ -190,7 +190,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
new_crtc_state->c8_planes &= ~BIT(plane->id);
new_crtc_state->data_rate[plane->id] = 0;
new_crtc_state->min_cdclk[plane->id] = 0;
- new_plane_state->base.visible = false;
+ new_plane_state->uapi.visible = false;
if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
return 0;
@@ -200,18 +200,18 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
return ret;
/* FIXME pre-g4x don't work like this */
- if (new_plane_state->base.visible)
+ if (new_plane_state->uapi.visible)
new_crtc_state->active_planes
[Intel-gfx] [PATCH 03/12] drm/i915: Perform manual conversions for crtc uapi/hw split, v2.
intel_get_load_detect_pipe() needs to set uapi active,
uapi enable is set by the call to drm_atomic_set_mode_for_crtc(),
so we can remove it.
intel_pipe_config_compare() needs to look at hw state, but I didn't
change spatch to look at it. It's easy enough to do manually.
intel_atomic_check() definitely needs to check for uapi enable,
otherwise intel_modeset_pipe_config cannot copy uapi state to hw.
Changes since v1:
- Actually set uapi.active in get_load_detect_pipe().
Signed-off-by: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 42 ++--
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 939dff68bba1..1827d1d728c4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11432,7 +11432,7 @@ int intel_get_load_detect_pipe(struct drm_connector
*connector,
goto fail;
}
- crtc_state->base.active = crtc_state->base.enable = true;
+ crtc_state->uapi.active = true;
ret = drm_atomic_set_mode_for_crtc(_state->base,
_detect_mode);
@@ -13077,19 +13077,19 @@ intel_pipe_config_compare(const struct
intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(output_types);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
PIPE_CONF_CHECK_I(pixel_multiplier);
PIPE_CONF_CHECK_I(output_format);
@@ -13106,17 +13106,17 @@ intel_pipe_config_compare(const struct
intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_INTERLACE);
if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_PHSYNC);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_NHSYNC);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_PVSYNC);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_NVSYNC);
}
@@ -13155,7 +13155,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
if (bp_gamma)
- PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, base.gamma_lut,
bp_gamma);
+ PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut,
bp_gamma);
}
@@ -13200,7 +13200,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
- PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
+ PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
PIPE_CONF_CHECK_I(min_voltage_level);
@@ -14007,7 +14007,7 @@ static int
[Intel-gfx] [PATCH 02/12] drm/i915: Add aliases for uapi and hw to crtc_state
Prepare to split up hw and uapi machinally, by adding a uapi and
hw alias. We will remove the base in a bit. This is a split from the
original uapi/hw patch, which did it all in one go.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 8 --
drivers/gpu/drm/i915/display/intel_display.c | 2 ++
drivers/gpu/drm/i915/display/intel_display.h | 6 ++---
.../drm/i915/display/intel_display_types.h| 27 ++-
4 files changed, 37 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 9cd6d2348a1e..4826aa4ee8e7 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -186,9 +186,10 @@ intel_digital_connector_duplicate_state(struct
drm_connector *connector)
struct drm_crtc_state *
intel_crtc_duplicate_state(struct drm_crtc *crtc)
{
+ const struct intel_crtc_state *old_crtc_state =
to_intel_crtc_state(crtc->state);
struct intel_crtc_state *crtc_state;
- crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), GFP_KERNEL);
+ crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
if (!crtc_state)
return NULL;
@@ -219,7 +220,10 @@ void
intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
- drm_atomic_helper_crtc_destroy_state(crtc, state);
+ struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
+
+ __drm_atomic_helper_crtc_destroy_state(_state->base);
+ kfree(crtc_state);
}
static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state
*scaler_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 397ed1205704..939dff68bba1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12592,6 +12592,8 @@ clear_intel_crtc_state(struct intel_crtc_state
*crtc_state)
/* Keep base drm_crtc_state intact, only clear our extended struct */
BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
+ BUILD_BUG_ON(offsetof(struct intel_crtc_state, uapi));
+ BUILD_BUG_ON(offsetof(struct intel_crtc_state, hw));
memcpy(_state->base + 1, _state->base + 1,
sizeof(*crtc_state) - sizeof(crtc_state->base));
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 355c50088589..476bc71e6a83 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -447,10 +447,10 @@ enum phy_fia {
#define intel_atomic_crtc_state_for_each_plane_state( \
plane, plane_state, \
crtc_state) \
- for_each_intel_plane_mask(((crtc_state)->base.state->dev), (plane), \
- ((crtc_state)->base.plane_mask)) \
+ for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
+ ((crtc_state)->uapi.plane_mask)) \
for_each_if ((plane_state = \
-
to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state,
>base
+
to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state,
>base
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 40184e823c84..e84343d3bf8d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -757,7 +757,32 @@ enum intel_output_format {
};
struct intel_crtc_state {
+ union {
struct drm_crtc_state base;
+ /*
+* uapi (drm) state. This is the software state shown to userspace.
+* In particular, the following members are used for bookkeeping:
+* - crtc
+* - state
+* - *_changed
+* - event
+* - commit
+* - mode_blob
+*/
+ struct drm_crtc_state uapi;
+
+ /*
+* actual hardware state, the state we program to the hardware.
+* The following members are used to verify the hardware state:
+* - enable
+* - active
+* - mode / adjusted_mode
+* - color property blobs.
+*
+* During initial hw readout, they need to be copied to uapi.
+*/
+ struct drm_crtc_state hw;
+ };
/**
* quirks - bitfield with hw state readout quirks
@@ -1112,7 +1137,7 @@ struct cxsr_latency {
#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state,
base)
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
-#define
[Intel-gfx] [PATCH 07/12] drm/i915: Add aliases for uapi and hw to plane_state
Prepare to split up hw and uapi machinally, by adding a uapi and
hw alias. We will remove the base in a bit. This is a split from the
original uapi/hw patch, which did it all in one go.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_atomic_plane.c| 16
.../gpu/drm/i915/display/intel_display_types.h | 8 ++--
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 4558c0b29fc1..393fb97a3dca 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -80,22 +80,20 @@ void intel_plane_free(struct intel_plane *plane)
struct drm_plane_state *
intel_plane_duplicate_state(struct drm_plane *plane)
{
- struct drm_plane_state *state;
struct intel_plane_state *intel_state;
- intel_state = kmemdup(plane->state, sizeof(*intel_state), GFP_KERNEL);
+ intel_state = to_intel_plane_state(plane->state);
+ intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
if (!intel_state)
return NULL;
- state = _state->base;
-
- __drm_atomic_helper_plane_duplicate_state(plane, state);
+ __drm_atomic_helper_plane_duplicate_state(plane, _state->base);
intel_state->vma = NULL;
intel_state->flags = 0;
- return state;
+ return _state->base;
}
/**
@@ -110,9 +108,11 @@ void
intel_plane_destroy_state(struct drm_plane *plane,
struct drm_plane_state *state)
{
- WARN_ON(to_intel_plane_state(state)->vma);
+ struct intel_plane_state *plane_state = to_intel_plane_state(state);
+ WARN_ON(plane_state->vma);
- drm_atomic_helper_plane_destroy_state(plane, state);
+ __drm_atomic_helper_plane_destroy_state(_state->base);
+ kfree(plane_state);
}
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9319ca682105..6036b2b3980b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -523,7 +523,11 @@ struct intel_atomic_state {
};
struct intel_plane_state {
- struct drm_plane_state base;
+ union {
+ struct drm_plane_state base;
+ struct drm_plane_state uapi;
+ struct drm_plane_state hw;
+ };
struct i915_ggtt_view view;
struct i915_vma *vma;
unsigned long flags;
@@ -1143,7 +1147,7 @@ struct cxsr_latency {
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
-#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
+#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
#define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
struct intel_hdmi {
--
2.24.0.rc1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/12] drm/i915: Remove special case slave handling during hw programming, v3.
Now that we split plane_state which I didn't want to do yet, we can
program the slave plane without requiring the master plane.
This is useful for programming bigjoiner slave planes as well. We
will no longer need the master's plane_state.
Changes since v1:
- set src/dst rectangles after copy_uapi_to_hw_state.
Changes since v2:
- Use the correct color_plane for pre-gen11 by using planar_linked_plane !=
NULL.
- Use drm_format_info_is_yuv_semiplanar in skl_plane_check() to fix gen11+.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 30 +-
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 -
drivers/gpu/drm/i915/display/intel_display.c | 18 ++
.../drm/i915/display/intel_display_types.h| 6 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 57 ++-
5 files changed, 40 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 133e6a75c8a0..42b3b3449d2e 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -348,16 +348,6 @@ void intel_update_plane(struct intel_plane *plane,
plane->update_plane(plane, crtc_state, plane_state);
}
-void intel_update_slave(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-
- trace_intel_update_plane(>base, crtc);
- plane->update_slave(plane, crtc_state, plane_state);
-}
-
void intel_disable_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
@@ -390,25 +380,9 @@ void skl_update_planes_on_crtc(struct intel_atomic_state
*state,
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state, plane);
- if (new_plane_state->uapi.visible) {
+ if (new_plane_state->uapi.visible ||
+ new_plane_state->planar_slave) {
intel_update_plane(plane, new_crtc_state,
new_plane_state);
- } else if (new_plane_state->planar_slave) {
- struct intel_plane *master =
- new_plane_state->planar_linked_plane;
-
- /*
-* We update the slave plane from this function because
-* programming it from the master plane's update_plane
-* callback runs into issues when the Y plane is
-* reassigned, disabled or used by a different plane.
-*
-* The slave plane is updated with the master plane's
-* plane_state.
-*/
- new_plane_state =
- intel_atomic_get_new_plane_state(state, master);
-
- intel_update_slave(plane, new_crtc_state,
new_plane_state);
} else {
intel_disable_plane(plane, new_crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index cdb0f97d09f9..5cedafdddb55 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -25,9 +25,6 @@ void intel_plane_copy_uapi_to_hw_state(struct
intel_plane_state *plane_state,
void intel_update_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
-void intel_update_slave(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state);
void intel_disable_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state);
struct intel_plane *intel_plane_alloc(void);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0461b154b3f3..a3e836b6ae0a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11985,6 +11985,24 @@ static int icl_check_nv12_planes(struct
intel_crtc_state *crtc_state)
crtc_state->active_planes |= BIT(linked->id);
crtc_state->update_planes |= BIT(linked->id);
DRM_DEBUG_KMS("Using %s as Y plane for %s\n",
linked->base.name, plane->base.name);
+
+ /* Copy parameters to slave plane */
+ linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
+ linked_state->color_ctl = plane_state->color_ctl;
+
[Intel-gfx] [PATCH 11/12] drm/i915: Complete plane hw and uapi split, v2.
Splitting plane state is easier than splitting crtc_state,
before plane check we copy the drm properties to hw so we can
do the same in bigjoiner later on.
We copy the state after we did all the modeset handling, but fortunately
i915 seems to be split correctly and nothing during modeset looks
at plane_state.
Changes since v1:
- Do not clear hw state on duplication.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 37 ++-
.../gpu/drm/i915/display/intel_atomic_plane.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_types.h| 23 +---
4 files changed, 57 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index d456b3dc200c..133e6a75c8a0 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -93,6 +93,10 @@ intel_plane_duplicate_state(struct drm_plane *plane)
intel_state->vma = NULL;
intel_state->flags = 0;
+ /* add reference to fb */
+ if (intel_state->hw.fb)
+ drm_framebuffer_get(intel_state->hw.fb);
+
return _state->uapi;
}
@@ -112,6 +116,8 @@ intel_plane_destroy_state(struct drm_plane *plane,
WARN_ON(plane_state->vma);
__drm_atomic_helper_plane_destroy_state(_state->uapi);
+ if (plane_state->hw.fb)
+ drm_framebuffer_put(plane_state->hw.fb);
kfree(plane_state);
}
@@ -176,15 +182,44 @@ bool intel_plane_calc_min_cdclk(struct intel_atomic_state
*state,
return false;
}
+static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
+{
+ if (plane_state->hw.fb)
+ drm_framebuffer_put(plane_state->hw.fb);
+
+ memset(_state->hw, 0, sizeof(plane_state->hw));
+}
+
+void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
+ const struct intel_plane_state
*from_plane_state)
+{
+ intel_plane_clear_hw_state(plane_state);
+
+ plane_state->hw.crtc = from_plane_state->uapi.crtc;
+ plane_state->hw.fb = from_plane_state->uapi.fb;
+ if (plane_state->hw.fb)
+ drm_framebuffer_get(plane_state->hw.fb);
+
+ plane_state->hw.alpha = from_plane_state->uapi.alpha;
+ plane_state->hw.pixel_blend_mode =
+ from_plane_state->uapi.pixel_blend_mode;
+ plane_state->hw.rotation = from_plane_state->uapi.rotation;
+ plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
+ plane_state->hw.color_range = from_plane_state->uapi.color_range;
+}
+
int intel_plane_atomic_check_with_state(const struct intel_crtc_state
*old_crtc_state,
struct intel_crtc_state *new_crtc_state,
const struct intel_plane_state
*old_plane_state,
struct intel_plane_state
*new_plane_state)
{
struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
- const struct drm_framebuffer *fb = new_plane_state->hw.fb;
+ const struct drm_framebuffer *fb;
int ret;
+ intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
+ fb = new_plane_state->hw.fb;
+
new_crtc_state->active_planes &= ~BIT(plane->id);
new_crtc_state->nv12_planes &= ~BIT(plane->id);
new_crtc_state->c8_planes &= ~BIT(plane->id);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index e61e9a82aadf..cdb0f97d09f9 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -20,6 +20,8 @@ extern const struct drm_plane_helper_funcs
intel_plane_helper_funcs;
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
+void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
+ const struct intel_plane_state
*from_plane_state);
void intel_update_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 826d1c995496..0461b154b3f3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3283,6 +3283,7 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
plane_state->fb = fb;
plane_state->crtc = _crtc->base;
+ intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
[Intel-gfx] [PATCH 01/12] drm/i915: Handle a few more cases for crtc hw/uapi split, v3.
We are still looking at drm_crtc_state in a few places, convert those
to use intel_crtc_state instead.
Changes since v1:
- Move to before uapi/hw split.
- Add hunks for intel_pm.c as well.
Changes since v2:
- Incorporate Ville's feedback.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 15 ---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 12
drivers/gpu/drm/i915/display/intel_psr.c | 16 +++-
drivers/gpu/drm/i915/intel_pm.c | 6 ++
4 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a23375621185..397ed1205704 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16714,8 +16714,7 @@ static int intel_initial_commit(struct drm_device *dev)
{
struct drm_atomic_state *state = NULL;
struct drm_modeset_acquire_ctx ctx;
- struct drm_crtc *crtc;
- struct drm_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
int ret = 0;
state = drm_atomic_state_alloc(dev);
@@ -16727,15 +16726,17 @@ static int intel_initial_commit(struct drm_device
*dev)
retry:
state->acquire_ctx =
- drm_for_each_crtc(crtc, dev) {
- crtc_state = drm_atomic_get_crtc_state(state, crtc);
+ for_each_intel_crtc(dev, crtc) {
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_crtc_state(state, crtc);
+
if (IS_ERR(crtc_state)) {
ret = PTR_ERR(crtc_state);
goto out;
}
- if (crtc_state->active) {
- ret = drm_atomic_add_affected_planes(state, crtc);
+ if (crtc_state->base.active) {
+ ret = drm_atomic_add_affected_planes(state,
>base);
if (ret)
goto out;
@@ -16745,7 +16746,7 @@ static int intel_initial_commit(struct drm_device *dev)
* having a proper LUT loaded. Remove once we
* have readout for pipe gamma enable.
*/
- crtc_state->color_mgmt_changed = true;
+ crtc_state->base.color_mgmt_changed = true;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index a9962846a503..42d26214fb23 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -168,7 +168,6 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
struct intel_connector *intel_connector =
to_intel_connector(connector);
struct drm_crtc *new_crtc = new_conn_state->crtc;
- struct drm_crtc_state *crtc_state;
struct drm_dp_mst_topology_mgr *mgr;
int ret;
@@ -183,11 +182,16 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
* connector
*/
if (new_crtc) {
- crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
+ struct intel_atomic_state *intel_state =
+ to_intel_atomic_state(state);
+ struct intel_crtc *intel_crtc = to_intel_crtc(new_crtc);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(intel_state,
+ intel_crtc);
if (!crtc_state ||
- !drm_atomic_crtc_needs_modeset(crtc_state) ||
- crtc_state->enable)
+ !drm_atomic_crtc_needs_modeset(_state->base) ||
+ crtc_state->base.enable)
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 6a9f322d3fca..359a60762b49 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include "display/intel_dp.h"
#include "i915_drv.h"
+#include "intel_atomic.h"
#include "intel_display_types.h"
#include "intel_psr.h"
#include "intel_sprite.h"
@@ -1096,7 +1097,7 @@ static int intel_psr_fastset_force(struct
drm_i915_private *dev_priv)
struct drm_device *dev = _priv->drm;
struct drm_modeset_acquire_ctx ctx;
struct drm_atomic_state *state;
- struct drm_crtc *crtc;
+ struct intel_crtc *crtc;
int err;
state = drm_atomic_state_alloc(dev);
@@ -1107,21 +1108,18 @@ static int intel_psr_fastset_force(struct
drm_i915_private *dev_priv)
state->acquire_ctx =
retry:
- drm_for_each_crtc(crtc, dev) {
- struct drm_crtc_state *crtc_state;
- struct
[Intel-gfx] [PATCH 06/12] drm/i915: Complete crtc hw/uapi split, v6.
Now that we separated everything into uapi and hw, it's
time to make the split definitive. Remove the union and
make a copy of the hw state on modeset and fastset.
Color blobs are copied in crtc atomic_check(), right
before color management is checked.
Changes since v1:
- Copy all blobs immediately after drm_atomic_helper_check_modeset().
- Clear crtc_state->hw on disable, instead of using clear_intel_crtc_state().
Changes since v2:
- Use intel_crtc_free_hw_state + clear in intel_crtc_disable_noatomic().
- Make a intel_crtc_prepare_state() function that clears the crtc_state
and copies hw members.
- Remove setting uapi.adjusted_mode, we now have a direct call to
drm_calc_timestamping_constants().
Changes since v3:
- Rename prefix copy_hw_to_uapi_state() with intel_crtc.
- Copy color blobs to uapi as well.
- Add a intel_crtc_copy_uapi_to_hw_state_nomodeset() function for clarity.
Changes since v4:
- Copy hw.adjusted_mode back to uapi.adjusted_mode, to shut up
the call to drm_calc_timestamping_constants() in
drm_atomic_helper_update_legacy_modeset_state().
- Use drm_property_replace_blob (Ville).
Changes since v5:
- Use hw->mode in intel_modeset_readout_hw_state(). (Ville)
- Copy to uapi.mode using drm_atomic_set_mode_for_crtc(). (Ville)
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 31 +++
drivers/gpu/drm/i915/display/intel_atomic.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 90 +++
.../drm/i915/display/intel_display_types.h| 9 +-
4 files changed, 109 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 48964f33c0c1..3301c178da03 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -195,6 +195,14 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
__drm_atomic_helper_crtc_duplicate_state(crtc, _state->uapi);
+ /* copy color blobs */
+ if (crtc_state->hw.degamma_lut)
+ drm_property_blob_get(crtc_state->hw.degamma_lut);
+ if (crtc_state->hw.ctm)
+ drm_property_blob_get(crtc_state->hw.ctm);
+ if (crtc_state->hw.gamma_lut)
+ drm_property_blob_get(crtc_state->hw.gamma_lut);
+
crtc_state->update_pipe = false;
crtc_state->disable_lp_wm = false;
crtc_state->disable_cxsr = false;
@@ -208,6 +216,28 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
return _state->uapi;
}
+static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
+{
+ drm_property_blob_put(crtc_state->hw.degamma_lut);
+ drm_property_blob_put(crtc_state->hw.gamma_lut);
+ drm_property_blob_put(crtc_state->hw.ctm);
+}
+
+void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
+{
+ intel_crtc_put_color_blobs(crtc_state);
+}
+
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
+{
+ drm_property_replace_blob(_state->hw.degamma_lut,
+ crtc_state->uapi.degamma_lut);
+ drm_property_replace_blob(_state->hw.gamma_lut,
+ crtc_state->uapi.gamma_lut);
+ drm_property_replace_blob(_state->hw.ctm,
+ crtc_state->uapi.ctm);
+}
+
/**
* intel_crtc_destroy_state - destroy crtc state
* @crtc: drm crtc
@@ -223,6 +253,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
__drm_atomic_helper_crtc_destroy_state(_state->uapi);
+ intel_crtc_free_hw_state(crtc_state);
kfree(crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
b/drivers/gpu/drm/i915/display/intel_atomic.h
index 49d5cb1b9e0a..7b49623419ba 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -36,6 +36,8 @@ intel_digital_connector_duplicate_state(struct drm_connector
*connector);
struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
void intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
+void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 4a9dc14f2ee2..373c57a4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7185,6 +7185,8 @@ static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc,
crtc->enabled = false;
crtc->state->connector_mask = 0;
crtc->state->encoder_mask = 0;
+
[Intel-gfx] [PATCH 08/12] drm/i915: Perform manual conversions for plane uapi/hw split, v2.
get_crtc_from_states() is called before plane_state is copied to uapi,
so use the uapi state there.
intel_legacy_cursor_update() could probably get away with looking at
the hw state, but for clarity always look at the uapi state.
Changes since v1:
- Convert entirety of intel_legacy_cursor_update (Ville).
Signed-off-by: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 8 ++--
drivers/gpu/drm/i915/display/intel_display.c | 45 ++-
2 files changed, 27 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 393fb97a3dca..416cfa439f33 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -225,11 +225,11 @@ static struct intel_crtc *
get_crtc_from_states(const struct intel_plane_state *old_plane_state,
const struct intel_plane_state *new_plane_state)
{
- if (new_plane_state->base.crtc)
- return to_intel_crtc(new_plane_state->base.crtc);
+ if (new_plane_state->uapi.crtc)
+ return to_intel_crtc(new_plane_state->uapi.crtc);
- if (old_plane_state->base.crtc)
- return to_intel_crtc(old_plane_state->base.crtc);
+ if (old_plane_state->uapi.crtc)
+ return to_intel_crtc(old_plane_state->uapi.crtc);
return NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 373c57a4..f244c6a010bc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15352,12 +15352,12 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
* take the slowpath. Only changing fb or position should be
* in the fastpath.
*/
- if (old_plane_state->base.crtc != >base ||
- old_plane_state->base.src_w != src_w ||
- old_plane_state->base.src_h != src_h ||
- old_plane_state->base.crtc_w != crtc_w ||
- old_plane_state->base.crtc_h != crtc_h ||
- !old_plane_state->base.fb != !fb)
+ if (old_plane_state->uapi.crtc != >base ||
+ old_plane_state->uapi.src_w != src_w ||
+ old_plane_state->uapi.src_h != src_h ||
+ old_plane_state->uapi.crtc_w != crtc_w ||
+ old_plane_state->uapi.crtc_h != crtc_h ||
+ !old_plane_state->uapi.fb != !fb)
goto slow;
new_plane_state =
to_intel_plane_state(intel_plane_duplicate_state(>base));
@@ -15370,16 +15370,16 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
goto out_free;
}
- drm_atomic_set_fb_for_plane(_plane_state->base, fb);
+ drm_atomic_set_fb_for_plane(_plane_state->uapi, fb);
- new_plane_state->base.src_x = src_x;
- new_plane_state->base.src_y = src_y;
- new_plane_state->base.src_w = src_w;
- new_plane_state->base.src_h = src_h;
- new_plane_state->base.crtc_x = crtc_x;
- new_plane_state->base.crtc_y = crtc_y;
- new_plane_state->base.crtc_w = crtc_w;
- new_plane_state->base.crtc_h = crtc_h;
+ new_plane_state->uapi.src_x = src_x;
+ new_plane_state->uapi.src_y = src_y;
+ new_plane_state->uapi.src_w = src_w;
+ new_plane_state->uapi.src_h = src_h;
+ new_plane_state->uapi.crtc_x = crtc_x;
+ new_plane_state->uapi.crtc_y = crtc_y;
+ new_plane_state->uapi.crtc_w = crtc_w;
+ new_plane_state->uapi.crtc_h = crtc_h;
ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
old_plane_state,
new_plane_state);
@@ -15390,13 +15390,14 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
if (ret)
goto out_free;
- intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->base.fb),
ORIGIN_FLIP);
- intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->base.fb),
- to_intel_frontbuffer(new_plane_state->base.fb),
+ intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
+ ORIGIN_FLIP);
+ intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
+ to_intel_frontbuffer(new_plane_state->hw.fb),
plane->frontbuffer_bit);
/* Swap plane state */
- plane->base.state = _plane_state->base;
+ plane->base.state = _plane_state->uapi;
/*
* We cannot swap crtc_state as it may be in use by an atomic commit or
@@ -15410,7 +15411,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
*/
crtc_state->active_planes = new_crtc_state->active_planes;
- if (new_plane_state->base.visible)
+ if (new_plane_state->uapi.visible)
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/4] drm/i915: s/icl_is_nv12_y_plane/icl_is_sdr_y_plane/
== Series Details == Series: series starting with [1/4] drm/i915: s/icl_is_nv12_y_plane/icl_is_sdr_y_plane/ URL : https://patchwork.freedesktop.org/series/68815/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC drivers/gpu/drm/i915/display/intel_sprite.h.s In file included from :0:0: ./drivers/gpu/drm/i915/display/intel_sprite.h: In function ‘icl_sdr_y_plane_mask’: ./drivers/gpu/drm/i915/display/intel_sprite.h:37:6: error: implicit declaration of function ‘INTEL_GEN’; did you mean ‘INTEL_BSM’? [-Werror=implicit-function-declaration] if (INTEL_GEN(dev_priv) >= 11) ^ INTEL_BSM cc1: all warnings being treated as errors scripts/Makefile.build:293: recipe for target 'drivers/gpu/drm/i915/display/intel_sprite.h.s' failed make[5]: *** [drivers/gpu/drm/i915/display/intel_sprite.h.s] Error 1 scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm/i915/display' failed make[4]: *** [drivers/gpu/drm/i915/display] Error 2 scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:509: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1649: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: update rawclk also on resume
Since CNP it's possible for rawclk to have two different values, 19.2
and 24 MHz. If the value indicated by SFUSE_STRAP register is different
from the power on default for PCH_RAWCLK_FREQ, we'll end up having a
mismatch between the rawclk hardware and software states after
suspend/resume. On previous platforms this used to work by accident,
because the power on defaults worked just fine.
Update the rawclk also on resume. The natural place to do this is
intel_modeset_init_hw(), however VLV/CHV need it done before
intel_power_domains_init_hw(). Split the update accordingly, even if
that's slighly ugly. This means moving the update later for non-VLV/CHV
platforms in probe.
Reported-by: Shawn Lee
Cc: Shawn Lee
Cc: Ville Syrjala
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++
drivers/gpu/drm/i915/i915_drv.c| 3 ---
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e56a75c07043..e31697fdffd3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16610,6 +16610,11 @@ void intel_init_display_hooks(struct drm_i915_private
*dev_priv)
void intel_modeset_init_hw(struct drm_i915_private *i915)
{
+ /*
+* VLV/CHV update rawclk earlier in intel_power_domains_init_hw().
+*/
+ if (!IS_VALLEYVIEW(i915) && !IS_CHERRYVIEW(i915))
+ intel_update_rawclk(i915);
intel_update_cdclk(i915);
intel_dump_cdclk_state(>cdclk.hw, "Current CDCLK");
i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 707ac110e271..999133d1f088 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5015,6 +5015,13 @@ void intel_power_domains_init_hw(struct drm_i915_private
*i915, bool resume)
power_domains->initializing = true;
+ /*
+* Must happen before power domain init on VLV/CHV, the rest update
+* rawclk later in intel_modeset_init_hw().
+*/
+ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ intel_update_rawclk(i915);
+
if (INTEL_GEN(i915) >= 11) {
icl_display_core_init(i915, resume);
} else if (IS_CANNONLAKE(i915)) {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 21273b516dbe..62906336298a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -296,9 +296,6 @@ static int i915_driver_modeset_probe(struct
drm_i915_private *i915)
if (ret)
goto cleanup_vga_client;
- /* must happen before intel_power_domains_init_hw() on VLV/CHV */
- intel_update_rawclk(i915);
-
intel_power_domains_init_hw(i915, false);
intel_csr_ucode_init(i915);
--
2.20.1
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[Intel-gfx] [PATCH] drm/i915: Drop inspection of execbuf flags during evict
With the goal of removing the serialisation from around execbuf, we will
no longer have the privilege of there being a single execbuf in flight
at any time and so will only be able to inspect the user's flags within
the carefully controlled execbuf context. i915_gem_evict_for_node() is
the only user outside of execbuf that currently peeks at the flag to
convert an overlapping softpinned request from ENOSPC to EINVAL. Retract
this nicety and only report ENOSPC if the location is in current use,
either due to this execbuf or another.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_evict.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index 7e62c310290f..4e5521fa6f8f 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -318,9 +318,6 @@ int i915_gem_evict_for_node(struct i915_address_space *vm,
/* Overlap of objects in the same batch? */
if (i915_vma_is_pinned(vma)) {
ret = -ENOSPC;
- if (vma->exec_flags &&
- *vma->exec_flags & EXEC_OBJECT_PINNED)
- ret = -EINVAL;
break;
}
--
2.24.0.rc1
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[Intel-gfx] [PATCH 3/4] drm/i915: Move icl_is_hdr_plane() next to its cousins
From: Ville Syrjälä
All the other icl plane type check stuff lives in intel_sprite.h
so move icl_is_hdr_plane() there as well.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 6 --
drivers/gpu/drm/i915/display/intel_sprite.h | 7 ++-
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 9a2ec2c5f890..ba344d9e2e19 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -316,12 +316,6 @@ int intel_plane_check_src_coordinates(struct
intel_plane_state *plane_state)
return 0;
}
-bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id
plane_id)
-{
- return INTEL_GEN(dev_priv) >= 11 &&
- icl_hdr_plane_mask() & BIT(plane_id);
-}
-
static void
skl_plane_ratio(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h
b/drivers/gpu/drm/i915/display/intel_sprite.h
index f38cc46ab282..ffb03ee640ed 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.h
+++ b/drivers/gpu/drm/i915/display/intel_sprite.h
@@ -48,7 +48,12 @@ static inline u8 icl_hdr_plane_mask(void)
BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
}
-bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id
plane_id);
+static inline bool icl_is_hdr_plane(struct drm_i915_private *dev_priv,
+ enum plane_id plane_id)
+{
+ return INTEL_GEN(dev_priv) >= 11 &&
+ icl_hdr_plane_mask() & BIT(plane_id);
+}
int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
--
2.23.0
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[Intel-gfx] [PATCH 2/4] drm/i915: Introduce icl_sdr_y_plane_mask()
From: Ville Syrjälä
Just like we have icl_hdr_plane_mask() let's introduce
icl_sdr_y_plane_mask(). This should make future changes to
the set of supported planes easier.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.h | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h
b/drivers/gpu/drm/i915/display/intel_sprite.h
index 965abc8a57cc..f38cc46ab282 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.h
+++ b/drivers/gpu/drm/i915/display/intel_sprite.h
@@ -32,13 +32,14 @@ struct intel_plane *
skl_universal_plane_create(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id);
+static inline u8 icl_sdr_y_plane_mask(void)
+{
+ return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
+}
+
static inline bool icl_is_sdr_y_plane(enum plane_id id)
{
- /* Don't need to do a gen check, these planes are only available on
gen11 */
- if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
- return true;
-
- return false;
+ return icl_sdr_y_plane_mask() & BIT(id);
}
static inline u8 icl_hdr_plane_mask(void)
--
2.23.0
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