[Intel-gfx] ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev8)
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev8)
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7558_full -> Patchwork_15742_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_15742_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15742_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_15742_full:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- shard-apl: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15742/shard-apl8/igt@run...@aborted.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gen9_exec_parse@allowed-single}:
- shard-skl: [PASS][2] -> [DMESG-WARN][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7558/shard-skl5/igt@gen9_exec_pa...@allowed-single.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15742/shard-skl4/igt@gen9_exec_pa...@allowed-single.html
* {igt@gen9_exec_parse@bb-chained}:
- shard-iclb: NOTRUN -> [SKIP][4] +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15742/shard-iclb6/igt@gen9_exec_pa...@bb-chained.html
* {igt@gen9_exec_parse@bb-start-param}:
- shard-tglb: NOTRUN -> [SKIP][5] +3 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15742/shard-tglb5/igt@gen9_exec_pa...@bb-start-param.html
### Piglit changes ###
Possible regressions
* spec@glsl-1.30@execution@texelfetch@fs-texelfetch-isampler1darray (NEW):
- pig-hsw-4770r: NOTRUN -> [FAIL][6] +1321 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15742/pig-hsw-4770r/spec@glsl-1.30@execution@texelfe...@fs-texelfetch-isampler1darray.html
New tests
-
New tests have been introduced between CI_DRM_7558_full and
Patchwork_15742_full:
### New Piglit tests (1010) ###
* hiz@hiz-depth-read-window-stencil1:
- Statuses : 1 fail(s)
- Exec time: [0.08] s
* object namespace pollution@texture with glbitmap:
- Statuses : 1 fail(s)
- Exec time: [0.24] s
* object namespace pollution@texture with glclear:
- Statuses : 1 fail(s)
- Exec time: [0.19] s
* object namespace pollution@texture with glcleartexsubimage:
- Statuses : 1 fail(s)
- Exec time: [0.18] s
* shaders@glsl-fs-floor:
- Statuses : 1 fail(s)
- Exec time: [0.12] s
* shaders@glsl-fs-texture2dproj-2:
- Statuses : 1 fail(s)
- Exec time: [0.13] s
* spec@!opengl 1.2@copyteximage 3d:
- Statuses : 1 fail(s)
- Exec time: [0.32] s
* spec@!opengl 1.2@getteximage-targets 3d:
- Statuses : 1 fail(s)
- Exec time: [0.14] s
* spec@!opengl 1.2@levelclamp:
- Statuses : 1 fail(s)
- Exec time: [4.79] s
* spec@!opengl 1.2@lodclamp:
- Statuses : 1 fail(s)
- Exec time: [4.74] s
* spec@!opengl 1.2@mipmap-setup:
- Statuses : 1 fail(s)
- Exec time: [4.53] s
* spec@!opengl 1.2@tex3d:
- Statuses : 1 fail(s)
- Exec time: [0.27] s
* spec@!opengl 1.2@texture-packed-formats:
- Statuses : 1 fail(s)
- Exec time: [2.37] s
* spec@!opengl 1.3@tex-border-1:
- Statuses : 1 fail(s)
- Exec time: [0.08] s
* spec@!opengl 1.4@draw-batch:
- Statuses : 1 fail(s)
- Exec time: [0.08] s
* spec@!opengl 1.4@gl-1.4-dlist-multidrawarrays:
- Statuses : 1 fail(s)
- Exec time: [0.11] s
* spec@!opengl 1.4@gl-1.4-polygon-offset:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@!opengl 1.4@tex-miplevel-selection-lod:
- Statuses : 1 fail(s)
- Exec time: [0.17] s
* spec@!opengl 1.4@tex-miplevel-selection-lod-bias:
- Statuses : 1 fail(s)
- Exec time: [1.13] s
* spec@!opengl 1.5@depth-tex-compare:
- Statuses : 1 fail(s)
- Exec time: [0.28] s
* spec@!opengl 1.5@draw-vertices:
- Statuses : 1 fail(s)
- Exec time: [0.21] s
* spec@!opengl 1.5@draw-vertices-user:
- Statuses : 1 fail(s)
- Exec time: [0.18] s
* spec@!opengl 2.0@attribs:
- Statuses : 1 fail(s)
- Exec time: [0.68] s
* spec@!opengl 2.0@depth-tex-modes-glsl:
- Statuses : 1 fail(s)
- Exec time: [0.11] s
* spec@!opengl 2.0@gl-2.0-two-sided-stencil:
- Statuses : 1 fail(s)
- Exec time: [0.12] s
* spec@!opengl 2.0@max-samplers:
- Statuses : 1 fail(s)
- Exec time: [0.53] s
* spec@!opengl 2.0@max-samplers border:
- Statuses : 1 fail(s)
- Exec time: [0.45] s
*
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Read DP link status with DRM helper function
== Series Details ==
Series: drm/i915/display: Read DP link status with DRM helper function
URL : https://patchwork.freedesktop.org/series/70878/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7558_full -> Patchwork_15741_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_15741_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15741_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_15741_full:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- shard-apl: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15741/shard-apl1/igt@run...@aborted.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gen7_exec_parse@oacontrol-tracking}:
- shard-tglb: NOTRUN -> [SKIP][2] +2 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15741/shard-tglb2/igt@gen7_exec_pa...@oacontrol-tracking.html
* {igt@gen9_exec_parse@allowed-single}:
- shard-apl: [PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7558/shard-apl1/igt@gen9_exec_pa...@allowed-single.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15741/shard-apl1/igt@gen9_exec_pa...@allowed-single.html
Known issues
Here are the changes found in Patchwork_15741_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@rcs0-mixed-process:
- shard-skl: [PASS][5] -> [FAIL][6] ([i915#679])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7558/shard-skl2/igt@gem_ctx_persiste...@rcs0-mixed-process.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15741/shard-skl9/igt@gem_ctx_persiste...@rcs0-mixed-process.html
* igt@gem_exec_parallel@vcs1:
- shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([fdo#111593])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7558/shard-tglb3/igt@gem_exec_paral...@vcs1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15741/shard-tglb4/igt@gem_exec_paral...@vcs1.html
* igt@gem_exec_schedule@independent-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7558/shard-iclb8/igt@gem_exec_sched...@independent-bsd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15741/shard-iclb4/igt@gem_exec_sched...@independent-bsd.html
* igt@gem_exec_schedule@preempt-queue-blt:
- shard-tglb: [PASS][11] -> [INCOMPLETE][12] ([fdo#111677])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7558/shard-tglb4/igt@gem_exec_sched...@preempt-queue-blt.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15741/shard-tglb6/igt@gem_exec_sched...@preempt-queue-blt.html
* igt@gem_exec_schedule@preempt-queue-contexts-bsd1:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109276]) +7 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7558/shard-iclb1/igt@gem_exec_sched...@preempt-queue-contexts-bsd1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15741/shard-iclb6/igt@gem_exec_sched...@preempt-queue-contexts-bsd1.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain-vebox:
- shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([fdo#111606] /
[fdo#111677])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7558/shard-tglb7/igt@gem_exec_sched...@preempt-queue-contexts-chain-vebox.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15741/shard-tglb6/igt@gem_exec_sched...@preempt-queue-contexts-chain-vebox.html
* igt@gem_exec_suspend@basic-s0:
- shard-tglb: [PASS][17] -> [INCOMPLETE][18] ([i915#472])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7558/shard-tglb4/igt@gem_exec_susp...@basic-s0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15741/shard-tglb8/igt@gem_exec_susp...@basic-s0.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-tglb: [PASS][19] -> [TIMEOUT][20] ([i915#530])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7558/shard-tglb8/igt@gem_persistent_rel...@forked-thrashing.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15741/shard-tglb5/igt@gem_persistent_rel...@forked-thrashing.html
* igt@gem_softpin@noreloc-s3:
- shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([i915#456])
[21]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: remove a condition
== Series Details ==
Series: drm/i915/selftests: remove a condition
URL : https://patchwork.freedesktop.org/series/70877/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7557_full -> Patchwork_15740_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_15740_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gen9_exec_parse@allowed-single}:
- shard-apl: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7557/shard-apl1/igt@gen9_exec_pa...@allowed-single.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15740/shard-apl1/igt@gen9_exec_pa...@allowed-single.html
* {igt@gen9_exec_parse@batch-zero-length}:
- shard-iclb: NOTRUN -> [SKIP][3] +5 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15740/shard-iclb3/igt@gen9_exec_pa...@batch-zero-length.html
* {igt@gen9_exec_parse@bb-start-param}:
- shard-tglb: NOTRUN -> [SKIP][4] +4 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15740/shard-tglb2/igt@gen9_exec_pa...@bb-start-param.html
Known issues
Here are the changes found in Patchwork_15740_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@bcs0-s3:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +3 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7557/shard-kbl6/igt@gem_ctx_isolat...@bcs0-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15740/shard-kbl4/igt@gem_ctx_isolat...@bcs0-s3.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([i915#456])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7557/shard-tglb2/igt@gem_ctx_isolat...@rcs0-s3.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15740/shard-tglb5/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_ctx_isolation@vcs1-dirty-switch:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276] / [fdo#112080])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7557/shard-iclb1/igt@gem_ctx_isolat...@vcs1-dirty-switch.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15740/shard-iclb8/igt@gem_ctx_isolat...@vcs1-dirty-switch.html
* igt@gem_ctx_persistence@bcs0-mixed-process:
- shard-apl: [PASS][11] -> [FAIL][12] ([i915#679])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7557/shard-apl6/igt@gem_ctx_persiste...@bcs0-mixed-process.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15740/shard-apl3/igt@gem_ctx_persiste...@bcs0-mixed-process.html
* igt@gem_ctx_shared@exec-shared-gtt-bsd2:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109276]) +5 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7557/shard-iclb1/igt@gem_ctx_sha...@exec-shared-gtt-bsd2.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15740/shard-iclb8/igt@gem_ctx_sha...@exec-shared-gtt-bsd2.html
* igt@gem_exec_schedule@preempt-queue-blt:
- shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([fdo#111677]) +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7557/shard-tglb9/igt@gem_exec_sched...@preempt-queue-blt.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15740/shard-tglb6/igt@gem_exec_sched...@preempt-queue-blt.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-glk: [PASS][17] -> [TIMEOUT][18] ([i915#530])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7557/shard-glk2/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15740/shard-glk8/igt@gem_persistent_rel...@forked-interruptible-thrashing.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-kbl: [PASS][19] -> [FAIL][20] ([i915#644])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7557/shard-kbl7/igt@gem_pp...@flink-and-close-vma-leak.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15740/shard-kbl3/igt@gem_pp...@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [PASS][21] -> [DMESG-WARN][22] ([fdo#111870]) +1
similar issue
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7557/shard-snb6/igt@gem_userptr_bl...@sync-unmap-cycles.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15740/shard-snb4/igt@gem_userptr_bl...@sync-unmap-cycles.html
* igt@i915_selftest@mock_sanitycheck:
- shard-hsw: [PASS][23] -> [DMESG-WARN][24] ([i915#747])
[23]:
Re: [Intel-gfx] [PATCH 1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset
On Fri, Dec 13, 2019 at 10:05:49PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 11, 2019 at 01:14:23PM -0800, Manasi Navare wrote:
> > In case of tiled displays, all the tiles are linke dto each other
> > for transcoder port sync. So in intel_atomic_check() we need to make
> > sure that we add all the tiles to the modeset and if one of the
> > tiles needs a full modeset then mark all other tiles for a full modeset.
> >
> > Suggested-by: Ville Syrjälä
> > Cc: Ville Syrjälä
> > Cc: José Roberto de Souza
> > Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 78
> > 1 file changed, 78 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 803993a01ca7..7263eaa66cda 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14066,6 +14066,80 @@ static int intel_atomic_check_crtcs(struct
> > intel_atomic_state *state)
> > return 0;
> > }
> >
> > +static int
> > +intel_dp_modeset_all_tiles(struct drm_i915_private *dev_priv,
> > + struct intel_atomic_state *state, int tile_grp_id)
> > +{
> > + struct drm_connector *conn_iter;
> 'connector'
> > + struct drm_connector_list_iter conn_list_iter;
> > + struct drm_crtc_state *crtc_state;
>
> crtc_state has needlessly wide scope.
>
> > +
> > + drm_connector_list_iter_begin(_priv->drm, _list_iter);
> > + drm_for_each_connector_iter(conn_iter, _list_iter) {
> > + struct drm_connector_state *conn_iter_state;
>
> 'conn_state' is the most popular name.
>
> > +
> > + if (!conn_iter->has_tile)
> > + continue;
> > + conn_iter_state = drm_atomic_get_connector_state(>base,
> > +conn_iter);
> > + if (IS_ERR(conn_iter_state)) {
> > + drm_connector_list_iter_end(_list_iter);
> > + return PTR_ERR(conn_iter_state);
> > + }
> > +
> > + if (!conn_iter_state->crtc)
> > + continue;
> > +
> > + if (conn_iter->tile_group->id != tile_grp_id)
> > + continue;
>
> The tile group check should be part of the same if with the has_tile
> check.
>
> > +
> > + crtc_state = drm_atomic_get_crtc_state(>base,
> > conn_iter_state->crtc);
> > + if (IS_ERR(crtc_state)) {
> > + drm_connector_list_iter_end(_list_iter);
> > + return PTR_ERR(conn_iter_state);
> > + }
> > + crtc_state->mode_changed = true;
> > + }
> > + drm_connector_list_iter_end(_list_iter);
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +intel_dp_atomic_trans_port_sync_check(struct drm_i915_private *dev_priv,
>
> Pointless variable. Can be extracted from the atomic state.
>
> > + struct intel_atomic_state *state)
> > +{
> > + struct drm_connector *connector;
> > + struct drm_crtc_state *crtc_state;
> > + struct drm_connector_state *connector_state;
> > + int i, ret, tile_grp_id = 0;
>
> tile_grp_id is rather pointless. crtc_state and ret can move into
> tighter scope. And the next suggestion allows you to kill crtc_state
> entirely...
Its not clear why tile_grp_id is pointless, I am using tile_grp_id for the
first connector with has_tile
and I make sure that I dont enter into the loop to check modeset again for the
connector with
same tile_grp_id because we have already set its mode changed to true in
intel_dp_modeset_all_tiles()
How can I achieve this instead?
Manasi
>
> > +
> > + if (INTEL_GEN(dev_priv) < 11)
> > + return 0;
> > +
> > + /* Is tiled, mark all other tiled CRTCs as needing a modeset */
> > + for_each_new_connector_in_state(>base, connector,
> > connector_state, i) {
> > + if (!connector->has_tile)
> > + continue;
> > + if (connector_state->crtc &&
> > + tile_grp_id != connector->tile_group->id) {
> > + crtc_state = drm_atomic_get_new_crtc_state(>base,
> > +
> > connector_state->crtc);
> > + if (!drm_atomic_crtc_needs_modeset(crtc_state))
> > + continue;
>
> This should to be able to be shortened to just
> intel_connector_needs_modeset().
>
> > +
> > + tile_grp_id = connector->tile_group->id;
> > + } else
> > + continue;
> > +
> > + ret = intel_dp_modeset_all_tiles(dev_priv, state, tile_grp_id);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > /**
> > * intel_atomic_check - validate state object
> > * @dev: drm device
> > @@ -14093,6
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Serialise object before changing cache-level
== Series Details ==
Series: drm/i915/gem: Serialise object before changing cache-level
URL : https://patchwork.freedesktop.org/series/70917/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7566 -> Patchwork_15758
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15758/index.html
Known issues
Here are the changes found in Patchwork_15758 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_blt:
- fi-bsw-nick:[PASS][1] -> [DMESG-FAIL][2] ([i915#723])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-bsw-nick/igt@i915_selftest@live_blt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15758/fi-bsw-nick/igt@i915_selftest@live_blt.html
Possible fixes
* igt@gem_close_race@basic-threads:
- fi-byt-n2820: [TIMEOUT][3] ([i915#816]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-byt-n2820/igt@gem_close_r...@basic-threads.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15758/fi-byt-n2820/igt@gem_close_r...@basic-threads.html
* igt@gem_exec_gttfill@basic:
- {fi-tgl-u}: [INCOMPLETE][5] ([fdo#111593]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-tgl-u/igt@gem_exec_gttf...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15758/fi-tgl-u/igt@gem_exec_gttf...@basic.html
* igt@gem_sync@basic-all:
- fi-tgl-y: [INCOMPLETE][7] ([i915#470]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-tgl-y/igt@gem_s...@basic-all.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15758/fi-tgl-y/igt@gem_s...@basic-all.html
* igt@i915_selftest@live_gem_contexts:
- fi-skl-lmem:[INCOMPLETE][9] ([i915#424]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15758/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
- fi-hsw-peppy: [INCOMPLETE][11] ([i915#694]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15758/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_requests:
- fi-hsw-4770:[INCOMPLETE][13] ([i915#773]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-hsw-4770/igt@i915_selftest@live_requests.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15758/fi-hsw-4770/igt@i915_selftest@live_requests.html
Warnings
* igt@i915_selftest@live_gem_contexts:
- fi-byt-j1900: [DMESG-FAIL][15] ([i915#722]) -> [INCOMPLETE][16]
([i915#45])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15758/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
* igt@kms_busy@basic-flip-pipe-b:
- fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][18] ([i915#62] / [i915#92]) +3 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-kbl-x1275/igt@kms_b...@basic-flip-pipe-b.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15758/fi-kbl-x1275/igt@kms_b...@basic-flip-pipe-b.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) ->
[DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +9 similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-kbl-x1275/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15758/fi-kbl-x1275/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722
[i915#723]: https://gitlab.freedesktop.org/drm/intel/issues/723
[i915#773]: https://gitlab.freedesktop.org/drm/intel/issues/773
[i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
[i915#92]:
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Some debugfs enhancements (rev5)
== Series Details == Series: Some debugfs enhancements (rev5) URL : https://patchwork.freedesktop.org/series/70658/ State : failure == Summary == Applying: drm/i915/rps: Add frequency translation helpers Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gt/intel_rps.c M drivers/gpu/drm/i915/gt/intel_rps.h M drivers/gpu/drm/i915/i915_debugfs.c M drivers/gpu/drm/i915/i915_sysfs.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_sysfs.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_sysfs.c Auto-merging drivers/gpu/drm/i915/i915_debugfs.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_debugfs.c Auto-merging drivers/gpu/drm/i915/gt/intel_rps.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_rps.h Auto-merging drivers/gpu/drm/i915/gt/intel_rps.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915/rps: Add frequency translation helpers When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gem: Serialise object before changing cache-level
== Series Details ==
Series: drm/i915/gem: Serialise object before changing cache-level
URL : https://patchwork.freedesktop.org/series/70917/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
30034c200ed3 drm/i915/gem: Serialise object before changing cache-level
-:8: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 8b1c78e06e61 ("drm/i915: Avoid
calling i915_gem_object_unbind holding object lock")'
#8:
8b1c78e06e61 ("drm/i915: Avoid calling i915_gem_object_unbind holding
total: 1 errors, 0 warnings, 0 checks, 13 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915: Call hsw_fdi_link_train() directly()
== Series Details ==
Series: series starting with [1/5] drm/i915: Call hsw_fdi_link_train()
directly()
URL : https://patchwork.freedesktop.org/series/70905/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7566 -> Patchwork_15755
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_15755 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15755, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15755/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_15755:
### IGT changes ###
Possible regressions
* igt@gem_sync@basic-each:
- fi-ivb-3770:[PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-ivb-3770/igt@gem_s...@basic-each.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15755/fi-ivb-3770/igt@gem_s...@basic-each.html
Known issues
Here are the changes found in Patchwork_15755 that come from known issues:
### IGT changes ###
Possible fixes
* igt@gem_close_race@basic-threads:
- fi-byt-n2820: [TIMEOUT][3] ([i915#816]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-byt-n2820/igt@gem_close_r...@basic-threads.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15755/fi-byt-n2820/igt@gem_close_r...@basic-threads.html
* igt@gem_exec_gttfill@basic:
- {fi-tgl-u}: [INCOMPLETE][5] ([fdo#111593]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-tgl-u/igt@gem_exec_gttf...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15755/fi-tgl-u/igt@gem_exec_gttf...@basic.html
* igt@gem_sync@basic-all:
- fi-tgl-y: [INCOMPLETE][7] ([i915#470]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-tgl-y/igt@gem_s...@basic-all.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15755/fi-tgl-y/igt@gem_s...@basic-all.html
* igt@i915_selftest@live_gem_contexts:
- fi-skl-lmem:[INCOMPLETE][9] ([i915#424]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15755/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
- fi-byt-j1900: [DMESG-FAIL][11] ([i915#722]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15755/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
- fi-hsw-peppy: [INCOMPLETE][13] ([i915#694]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15755/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_requests:
- fi-hsw-4770:[INCOMPLETE][15] ([i915#773]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-hsw-4770/igt@i915_selftest@live_requests.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15755/fi-hsw-4770/igt@i915_selftest@live_requests.html
Warnings
* igt@i915_selftest@live_blt:
- fi-ivb-3770:[DMESG-FAIL][17] ([i915#725]) -> [DMESG-FAIL][18]
([i915#770])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-ivb-3770/igt@i915_selftest@live_blt.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15755/fi-ivb-3770/igt@i915_selftest@live_blt.html
* igt@kms_busy@basic-flip-pipe-b:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][20] ([i915#62] / [i915#92]) +7 similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-kbl-x1275/igt@kms_b...@basic-flip-pipe-b.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15755/fi-kbl-x1275/igt@kms_b...@basic-flip-pipe-b.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) ->
[DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-kbl-x1275/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15755/fi-kbl-x1275/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/svm: Add SVM support (rev2)
== Series Details == Series: drm/i915/svm: Add SVM support (rev2) URL : https://patchwork.freedesktop.org/series/69908/ State : failure == Summary == Applying: drm/i915/svm: Add SVM documentation Applying: drm/i915/svm: Runtime (RT) allocator support error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_drv.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0002 drm/i915/svm: Runtime (RT) allocator support When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/perf: Register sysctl path globally
== Series Details == Series: series starting with [1/2] drm/i915/perf: Register sysctl path globally URL : https://patchwork.freedesktop.org/series/70906/ State : failure == Summary == Applying: drm/i915/perf: Register sysctl path globally Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_pci.c M drivers/gpu/drm/i915/i915_perf.c M drivers/gpu/drm/i915/i915_perf.h M drivers/gpu/drm/i915/i915_perf_types.h Falling back to patching base and 3-way merge... No changes -- Patch already applied. Applying: drm/i915: Introduce new macros for tracing Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gem/i915_gem_pm.c M drivers/gpu/drm/i915/gt/intel_context.c M drivers/gpu/drm/i915/gt/intel_context.h M drivers/gpu/drm/i915/gt/intel_engine.h M drivers/gpu/drm/i915/gt/intel_engine_cs.c M drivers/gpu/drm/i915/gt/intel_engine_pm.c M drivers/gpu/drm/i915/gt/intel_gt_pm.c M drivers/gpu/drm/i915/gt/intel_lrc.c M drivers/gpu/drm/i915/gt/intel_reset.c M drivers/gpu/drm/i915/gt/intel_ring_submission.c M drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c M drivers/gpu/drm/i915/i915_request.c M drivers/gpu/drm/i915/i915_request.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_request.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_request.h Auto-merging drivers/gpu/drm/i915/i915_request.c Auto-merging drivers/gpu/drm/i915/gt/intel_ring_submission.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_ring_submission.c Auto-merging drivers/gpu/drm/i915/gt/intel_lrc.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_lrc.c Auto-merging drivers/gpu/drm/i915/gt/intel_engine.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_engine.h Auto-merging drivers/gpu/drm/i915/gt/intel_context.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_context.h error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0002 drm/i915: Introduce new macros for tracing When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: Add new modes from CTA-861-G (rev3)
== Series Details ==
Series: drm/edid: Add new modes from CTA-861-G (rev3)
URL : https://patchwork.freedesktop.org/series/63554/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7566 -> Patchwork_15754
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15754/index.html
Known issues
Here are the changes found in Patchwork_15754 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_close_race@basic-threads:
- fi-byt-j1900: [PASS][1] -> [TIMEOUT][2] ([i915#816])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-byt-j1900/igt@gem_close_r...@basic-threads.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15754/fi-byt-j1900/igt@gem_close_r...@basic-threads.html
Possible fixes
* igt@gem_close_race@basic-threads:
- fi-byt-n2820: [TIMEOUT][3] ([i915#816]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-byt-n2820/igt@gem_close_r...@basic-threads.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15754/fi-byt-n2820/igt@gem_close_r...@basic-threads.html
* igt@gem_exec_gttfill@basic:
- {fi-tgl-u}: [INCOMPLETE][5] ([fdo#111593]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-tgl-u/igt@gem_exec_gttf...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15754/fi-tgl-u/igt@gem_exec_gttf...@basic.html
* igt@gem_sync@basic-all:
- fi-tgl-y: [INCOMPLETE][7] ([i915#470]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-tgl-y/igt@gem_s...@basic-all.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15754/fi-tgl-y/igt@gem_s...@basic-all.html
* igt@i915_selftest@live_blt:
- fi-ivb-3770:[DMESG-FAIL][9] ([i915#725]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-ivb-3770/igt@i915_selftest@live_blt.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15754/fi-ivb-3770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-skl-lmem:[INCOMPLETE][11] ([i915#424]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15754/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
- fi-hsw-peppy: [INCOMPLETE][13] ([i915#694]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15754/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_requests:
- fi-hsw-4770:[INCOMPLETE][15] ([i915#773]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-hsw-4770/igt@i915_selftest@live_requests.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15754/fi-hsw-4770/igt@i915_selftest@live_requests.html
Warnings
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [SKIP][17] ([fdo#109271]) -> [FAIL][18] ([i915#579])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-kbl-guc/igt@i915_pm_...@basic-rte.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15754/fi-kbl-guc/igt@i915_pm_...@basic-rte.html
* igt@kms_busy@basic-flip-pipe-b:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][20] ([i915#62] / [i915#92]) +5 similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-kbl-x1275/igt@kms_b...@basic-flip-pipe-b.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15754/fi-kbl-x1275/igt@kms_b...@basic-flip-pipe-b.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) ->
[DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +6 similar issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7566/fi-kbl-x1275/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15754/fi-kbl-x1275/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#694]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dsi: fix pipe D readout for DSI transcoders (rev2)
== Series Details == Series: drm/i915/dsi: fix pipe D readout for DSI transcoders (rev2) URL : https://patchwork.freedesktop.org/series/70752/ State : success == Summary == CI Bug Log - changes from CI_DRM_7545_full -> Patchwork_15696_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15696_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@extended-parallel-vcs1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-iclb2/igt@gem_b...@extended-parallel-vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15696/shard-iclb3/igt@gem_b...@extended-parallel-vcs1.html * igt@gem_ctx_persistence@vcs1-hostile-preempt: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-iclb1/igt@gem_ctx_persiste...@vcs1-hostile-preempt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15696/shard-iclb6/igt@gem_ctx_persiste...@vcs1-hostile-preempt.html * igt@gem_ctx_shared@q-smoketest-blt: - shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([fdo#111735]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-tglb6/igt@gem_ctx_sha...@q-smoketest-blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15696/shard-tglb6/igt@gem_ctx_sha...@q-smoketest-blt.html * igt@gem_eio@suspend: - shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([i915#460]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-tglb1/igt@gem_...@suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15696/shard-tglb3/igt@gem_...@suspend.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-iclb2/igt@gem_exec_sched...@preempt-queue-bsd1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15696/shard-iclb3/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-iclb6/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15696/shard-iclb4/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd2: - shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([fdo#111677]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-tglb3/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd2.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15696/shard-tglb6/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd2.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#644]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-skl1/igt@gem_pp...@flink-and-close-vma-leak.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15696/shard-skl8/igt@gem_pp...@flink-and-close-vma-leak.html * igt@i915_pm_rps@waitboost: - shard-tglb: [PASS][17] -> [FAIL][18] ([i915#413]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-tglb3/igt@i915_pm_...@waitboost.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15696/shard-tglb5/igt@i915_pm_...@waitboost.html * igt@i915_selftest@mock_sanitycheck: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#747]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-skl2/igt@i915_selftest@mock_sanitycheck.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15696/shard-skl4/igt@i915_selftest@mock_sanitycheck.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([i915#456] / [i915#460]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-tglb4/igt@i915_susp...@fence-restore-tiled2untiled.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15696/shard-tglb3/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_color@pipe-a-ctm-max: - shard-skl: [PASS][23] -> [DMESG-WARN][24] ([i915#109]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-skl7/igt@kms_co...@pipe-a-ctm-max.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15696/shard-skl8/igt@kms_co...@pipe-a-ctm-max.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#180]) +8 similar issues [25]:
Re: [Intel-gfx] [PATCH v8 4/4] drm/i915: Correctly map DBUF slices to pipes
On Fri, Dec 13, 2019 at 03:02:28PM +0200, Stanislav Lisovskiy wrote:
> Added proper DBuf slice mapping to correspondent
> pipes, depending on pipe configuration as stated
> in BSpec.
>
> v2:
> - Remove unneeded braces
> - Stop using macro for DBuf assignments as
> it seems to reduce readability.
>
> v3: Start using enabled slices mask in dev_priv
>
> v4: Renamed "enabled_slices" used in dev_priv
> to "enabled_dbuf_slices_mask"(Matt Roper)
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/intel_pm.c | 226 ++--
> 1 file changed, 216 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 111bcafd6e4c..a13052b2c2ef 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3832,13 +3832,30 @@ bool intel_can_enable_sagv(struct intel_atomic_state
> *state)
> return true;
> }
>
> +/*
> + * Calculate initial DBuf slice offset, based on slice size
> + * and mask(i.e if slice size is 1024 and second slice is enabled
> + * offset would be 1024)
> + */
> +static u32 icl_get_first_dbuf_slice_offset(u32 dbuf_slice_mask,
> +u32 slice_size, u32 ddb_size)
> +{
It might be worth just passing the mask + dev_priv to this function and
let it get slice_size / ddb_size on its own to keep the logic simpler at
the callsite.
> + u32 offset = 0;
> +
> + if (!dbuf_slice_mask)
> + return 0;
> +
> + offset = (ffs(dbuf_slice_mask) - 1) * slice_size;
> +
> + WARN_ON(offset >= ddb_size);
> + return offset;
> +}
> +
> static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
> const struct intel_crtc_state *crtc_state,
> const u64 total_data_rate,
> const int num_active)
I probably should have mentioned it on the previous patch, but most of
these parameters are no longer needed now.
> {
> - struct drm_atomic_state *state = crtc_state->uapi.state;
> - struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
>
> WARN_ON(ddb_size == 0);
> @@ -3846,12 +3863,13 @@ static u16 intel_get_ddb_size(struct drm_i915_private
> *dev_priv,
> if (INTEL_GEN(dev_priv) < 11)
> return ddb_size - 4; /* 4 blocks for bypass path allocation */
>
> - intel_state->enabled_dbuf_slices_mask = DBUF_S1_BIT;
> - ddb_size /= 2;
> -
> return ddb_size;
> }
>
> +u32 i915_possible_dbuf_slices(struct drm_i915_private *dev_priv,
> + int pipe, u32 active_pipes,
> + const struct intel_crtc_state *crtc_state);
> +
> static void
> skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> const struct intel_crtc_state *crtc_state,
> @@ -3866,7 +3884,14 @@ skl_ddb_get_pipe_allocation_limits(struct
> drm_i915_private *dev_priv,
> u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
> enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
> u16 ddb_size;
> + u32 ddb_range_size;
> u32 i;
> + u32 dbuf_slice_mask;
> + u32 active_pipes;
> + u32 offset;
> + u32 slice_size;
> + u32 total_slice_mask;
> + u32 start, end;
>
> if (WARN_ON(!state) || !crtc_state->hw.active) {
> alloc->start = 0;
> @@ -3875,14 +3900,19 @@ skl_ddb_get_pipe_allocation_limits(struct
> drm_i915_private *dev_priv,
> return;
> }
>
> - if (intel_state->active_pipe_changes)
> + if (intel_state->active_pipe_changes) {
> *num_active = hweight8(intel_state->active_pipes);
> - else
> + active_pipes = intel_state->active_pipes;
> + } else {
> *num_active = hweight8(dev_priv->active_pipes);
> + active_pipes = dev_priv->active_pipes;
> + }
Might be slightly more intuitive to move the num_active assignment
outside the 'if' as
*num_active = hweight8(active_pipes);
Up to you; doesn't really matter.
>
> ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate,
> *num_active);
>
> + slice_size = ddb_size / INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
> +
> /*
>* If the state doesn't change the active CRTC's or there is no
>* modeset request, then there's no need to recalculate;
> @@ -3900,18 +3930,68 @@ skl_ddb_get_pipe_allocation_limits(struct
> drm_i915_private *dev_priv,
> return;
> }
>
> + /*
> + * Get allowed DBuf slices for correspondent pipe and platform.
> + */
> + dbuf_slice_mask = i915_possible_dbuf_slices(dev_priv, for_pipe,
> + active_pipes, crtc_state);
> +
> + DRM_DEBUG_KMS("DBuf slice mask
Re: [Intel-gfx] [RFC v2 02/12] drm/i915/svm: Runtime (RT) allocator support
On Fri, Dec 13, 2019 at 5:24 PM Niranjan Vishwanathapura <
niranjana.vishwanathap...@intel.com> wrote:
> On Fri, Dec 13, 2019 at 04:58:42PM -0600, Jason Ekstrand wrote:
> >
> > +/**
> > + * struct drm_i915_gem_vm_bind
> > + *
> > + * Bind an object in a vm's page table.
> >
> > First off, this is something I've wanted for a while for Vulkan, it's
> just
> > never made its way high enough up the priority list. However, it's
> going
> > to have to come one way or another soon. I'm glad to see kernel API
> for
> > this being proposed.
> > I do, however, have a few high-level comments/questions about the API:
> >1. In order to be useful for sparse memory support, the API has to go
> the
> > other way around so that it binds a VA range to a range within the
> BO. It
> > also needs to be able to handle overlapping where two different VA
> ranges
> > may map to the same underlying bytes in the BO. This likely means that
> > unbind needs to also take a VA range and only unbind that range.
> >2. If this is going to be useful for managing GL's address space
> where we
> > have lots of BOs, we probably want it to take a list of ranges so we
> > aren't making one ioctl for each thing we want to bind.
>
> Hi Jason,
>
> Yah, some of these requirements came up.
>
Yes, I have raised them every single time an API like this has come across
my e-mail inbox for years and they continue to get ignored. Why are we
landing an API that we know isn't the API we want especially when it's
pretty obvious roughly what the API we want is? It may be less time in the
short term, but long-term it means two ioctls and two implementations in
i915, IGT tests for both code paths, and code in all UMDs to call one or
the other depending on what kernel you're running on, and we have to
maintain all that code going forward forever. Sure, that's a price we pay
today for a variety of things but that's because they all seemed like the
right thing at the time. Landing the wrong API when we know it's the wrong
API seems foolish.
They are not being done here due to time and effort involved in defining
> those requirements, implementing and validating.
>
For #1, yes, it would require more effort but for #2, it really doesn't
take any extra effort to make it take an array...
> However, this ioctl can be extended in a backward compatible way to handle
> those requirements if required.
>
> >3. Why are there no ways to synchronize this with anything? For
> binding,
> > this probably isn't really needed as long as the VA range you're
> binding
> > is empty. However, if you want to move bindings around or unbind
> > something, the only option is to block in userspace and then call
> > bind/unbind. This can be done but it means even more threads in the
> UMD
> > which is unpleasant. One could argue that that's more or less what the
> > kernel is going to have to do so we may as well do it in userspace.
> > However, I'm not 100% convinced that's true.
> > --Jason
> >
>
> Yah, that is the thought.
> But as SVM feature evolves, I think we can consider handling some such
> cases
> if hadling those in driver does make whole lot sense.
>
Sparse binding exists as a feature. It's been in D3D for some time and
it's in Vulkan. We pretty much know what the requirements are. If you go
look at how it's supposed to work in Vulkan, you have a binding queue and
it waits on semaphores before [un]binding and signals semaphores after
[un]binding. The biggest problem from an API (as opposed to
implementation) POV with doing that in i915 is that we have too many
synchronization primitives to choose from. :-(
--Jason
> Thanks,
> Niranjana
>
> >
> > + */
> > +struct drm_i915_gem_vm_bind {
> > + /** VA start to bind **/
> > + __u64 start;
> > +
> > + /** Type of memory to [un]bind **/
> > + __u32 type;
> > +#define I915_GEM_VM_BIND_SVM_OBJ 0
> > +
> > + /** Object handle to [un]bind for I915_GEM_VM_BIND_SVM_OBJ
> type
> > **/
> > + __u32 handle;
> > +
> > + /** vm to [un]bind **/
> > + __u32 vm_id;
> > +
> > + /** Flags **/
> > + __u32 flags;
> > +#define I915_GEM_VM_BIND_UNBIND (1 << 0)
> > +#define I915_GEM_VM_BIND_READONLY(1 << 1)
> > +};
> > +
> > #if defined(__cplusplus)
> > }
> > #endif
> > --
> > 2.21.0.rc0.32.g243a4c7e27
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/edid: Add new modes from CTA-861-G (rev3)
== Series Details == Series: drm/edid: Add new modes from CTA-861-G (rev3) URL : https://patchwork.freedesktop.org/series/63554/ State : warning == Summary == $ dim checkpatch origin/drm-tip f65c5faeb690 drm/edid: Abstract away cea_edid_modes[] -:122: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "cea_mode_for_vic" #122: FILE: drivers/gpu/drm/drm_edid.c:3227: + return cea_mode_for_vic(vic) != NULL; total: 0 errors, 0 warnings, 1 checks, 133 lines checked 1e2d560339b9 drm/edid: Add CTA-861-G modes with VIC >= 193 04407c04c8f5 drm/edid: Throw away the dummy VIC 0 cea mode 1eb2087450a1 drm/edid: Make sure the CEA mode arrays have the correct amount of modes ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 rebased 06/11] drm/i915/display: Share intel_connector_needs_modeset()
On Thu, Dec 12, 2019 at 05:52:49PM +0200, Ville Syrjälä wrote:
On Wed, Dec 11, 2019 at 10:45:21AM -0800, José Roberto de Souza wrote:
intel_connector_needs_modeset() will be used outside of
intel_display.c in a future patch so it would only be necessary to
remove the state and add the prototype to the header file.
But while at it, I simplified the arguments and changed to intel
types and moved it to a better place intel_atomic.c.
That allowed us to convert the whole
intel_encoders_update_prepare/complete to intel type too.
No behavior changes intended here.
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_atomic.c | 32
drivers/gpu/drm/i915/display/intel_atomic.h | 3 ++
drivers/gpu/drm/i915/display/intel_display.c | 53 ++--
3 files changed, 51 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index fd0026fc3618..6e93a39a6fec 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -174,6 +174,38 @@ intel_digital_connector_duplicate_state(struct
drm_connector *connector)
return >base;
}
+/**
+ * intel_digital_connector_needs_modeset - check if connector needs a modeset
+ */
+bool
+intel_digital_connector_needs_modeset(struct intel_atomic_state *state,
Why "digital"? Oh because intel_atomic_get_old_connector_state() return
a ditgital_connector_state. A bit surprising.
I suggest using just drm_connector_state here to keep this function
totally generic.
+ struct intel_connector *connector)
+{
+ struct intel_digital_connector_state *old_connector_state,
*new_connector_state;
+ struct intel_crtc *old_crtc, *new_crtc;
+ struct intel_crtc_state *new_crtc_state;
+
+ old_connector_state = intel_atomic_get_old_connector_state(state,
+ connector);
Could be done when declaring the variable. Dunno which is prettier
though.
+ if (old_connector_state->base.crtc)
+ old_crtc = to_intel_crtc(old_connector_state->base.crtc);
+ else
+ old_crtc = NULL;
Simple
old_crtc = to_intel_crtc(old_connector_state->base.crtc);
will do. Can be done when declaring the variable as well.
+
+ new_connector_state = intel_atomic_get_new_connector_state(state,
+ connector);
+ if (new_connector_state->base.crtc) {
+ new_crtc = to_intel_crtc(new_connector_state->base.crtc);
ditto.
+ new_crtc_state = intel_atomic_get_new_crtc_state(state,
new_crtc);
Then this just becomes
if (new_crtc)
new_crtc_state = ...;
Or maybe
new_crtc_state = new_crtc ? get : NULL;
but that could be a bit ugly.
+ } else {
+ new_crtc_state = NULL;
+ new_crtc = NULL;
+ }
+
+ return new_crtc != old_crtc ||
+ (new_crtc &&
drm_atomic_crtc_needs_modeset(_crtc_state->uapi));
Hmm. In fact this function could be one of those special cases where we
might even want to use all drm_ types internally since we don't actually
need anything else.
so... do you mean to bring intel_connector_needs_modeset() as is?
Lucas De Marchi
+}
+
/**
* intel_crtc_duplicate_state - duplicate crtc state
* @crtc: drm crtc
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
b/drivers/gpu/drm/i915/display/intel_atomic.h
index 7b49623419ba..ba9cc29a5865 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -17,6 +17,7 @@ struct drm_device;
struct drm_i915_private;
struct drm_property;
struct intel_atomic_state;
+struct intel_connector;
struct intel_crtc;
struct intel_crtc_state;
@@ -32,6 +33,8 @@ int intel_digital_connector_atomic_check(struct drm_connector
*conn,
struct drm_atomic_state *state);
struct drm_connector_state *
intel_digital_connector_duplicate_state(struct drm_connector *connector);
+bool intel_digital_connector_needs_modeset(struct intel_atomic_state *state,
+ struct intel_connector *connector);
struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
void intel_crtc_destroy_state(struct drm_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index b4e44d3cd275..39b00a19d752 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6185,71 +6185,50 @@ intel_connector_primary_encoder(struct intel_connector
*connector)
return encoder;
}
-static bool
-intel_connector_needs_modeset(struct intel_atomic_state *state,
- const struct drm_connector_state *old_conn_state,
-
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Use dma_resv locking wrappers
On Mon, Nov 25, 2019 at 10:43:54AM +0100, Daniel Vetter wrote:
> I'll add more fancy logic to them soon, so everyone really has to use
> them. Plus they already provide some nice additional debug
> infrastructure on top of direct ww_mutex usage for the fences tracked
> by dma_resv.
>
> Aside: We might want to create wrappers for i915_vma locking of the
> ->resv like we have for the i915_gem_bo itself already.
>
> Signed-off-by: Daniel Vetter
> Cc: Chris Wilson
> Cc: Tvrtko Ursulin
> Cc: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Jani Nikula
> ---
Maarten/Chris, should I drop this one or keep? I guess this will all
change anyway rsn ...
-Daniel
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 7a87e8270460..7b8f4ebd9986 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -1848,7 +1848,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
> for (i = 0; i < count; i++) {
> struct i915_vma *vma = eb->vma[i];
>
> - err = ww_mutex_lock_interruptible(>resv->lock, );
> + err = dma_resv_lock_interruptible(vma->resv, );
> if (!err)
> continue;
>
> @@ -1859,7 +1859,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
> do {
> int j = i - 1;
>
> - ww_mutex_unlock(>vma[j]->resv->lock);
> + dma_resv_unlock(eb->vma[j]->resv);
>
> swap(eb->flags[i], eb->flags[j]);
> swap(eb->vma[i], eb->vma[j]);
> @@ -1868,7 +1868,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
> GEM_BUG_ON(vma != eb->vma[0]);
> vma->exec_flags = >flags[0];
>
> - err = ww_mutex_lock_slow_interruptible(>resv->lock,
> + err = dma_resv_lock_slow_interruptible(vma->resv,
> );
> }
> if (err)
> --
> 2.24.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RESEND PATCH v2] drm: Add getfb2 ioctl
On Fri, Dec 13, 2019 at 10:52:03PM +, Li, Juston wrote:
> On Fri, 2019-12-13 at 23:36 +0200, Ville Syrjälä wrote:
> > On Thu, Oct 03, 2019 at 11:31:25AM -0700, Juston Li wrote:
> > > From: Daniel Stone
> > >
> > > getfb2 allows us to pass multiple planes and modifiers, just like
> > > addfb2
> > > over addfb.
> > >
> > > Changes since v1:
> > > - unused modifiers set to 0 instead of DRM_FORMAT_MOD_INVALID
> > > - update ioctl number
> > >
> > > Signed-off-by: Daniel Stone
> > > Signed-off-by: Juston Li
> > > ---
> > > drivers/gpu/drm/drm_crtc_internal.h | 2 +
> > > drivers/gpu/drm/drm_framebuffer.c | 110
> > >
> > > drivers/gpu/drm/drm_ioctl.c | 1 +
> > > include/uapi/drm/drm.h | 2 +
> > > 4 files changed, 115 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/drm_crtc_internal.h
> > > b/drivers/gpu/drm/drm_crtc_internal.h
> > > index c7d5e4c21423..16f2413403aa 100644
> > > --- a/drivers/gpu/drm/drm_crtc_internal.h
> > > +++ b/drivers/gpu/drm/drm_crtc_internal.h
> > > @@ -216,6 +216,8 @@ int drm_mode_rmfb_ioctl(struct drm_device *dev,
> > > void *data, struct drm_file *file_priv);
> > > int drm_mode_getfb(struct drm_device *dev,
> > > void *data, struct drm_file *file_priv);
> > > +int drm_mode_getfb2_ioctl(struct drm_device *dev,
> > > + void *data, struct drm_file *file_priv);
> > > int drm_mode_dirtyfb_ioctl(struct drm_device *dev,
> > > void *data, struct drm_file *file_priv);
> > >
> > > diff --git a/drivers/gpu/drm/drm_framebuffer.c
> > > b/drivers/gpu/drm/drm_framebuffer.c
> > > index 57564318ceea..6db54f177443 100644
> > > --- a/drivers/gpu/drm/drm_framebuffer.c
> > > +++ b/drivers/gpu/drm/drm_framebuffer.c
> > > @@ -31,6 +31,7 @@
> > > #include
> > > #include
> > > #include
> > > +#include
> > > #include
> > > #include
> > >
> > > @@ -548,7 +549,116 @@ int drm_mode_getfb(struct drm_device *dev,
> > >
> > > out:
> > > drm_framebuffer_put(fb);
> > > + return ret;
> > > +}
> > > +
> > > +/**
> > > + * drm_mode_getfb2 - get extended FB info
> > > + * @dev: drm device for the ioctl
> > > + * @data: data pointer for the ioctl
> > > + * @file_priv: drm file for the ioctl call
> > > + *
> > > + * Lookup the FB given its ID and return info about it.
> > > + *
> > > + * Called by the user via ioctl.
> > > + *
> > > + * Returns:
> > > + * Zero on success, negative errno on failure.
> > > + */
> > > +int drm_mode_getfb2_ioctl(struct drm_device *dev,
> > > + void *data, struct drm_file *file_priv)
> > > +{
> > > + struct drm_mode_fb_cmd2 *r = data;
> > > + struct drm_framebuffer *fb;
> > > + unsigned int i;
> > > + int ret;
> > > +
> > > + if (!drm_core_check_feature(dev, DRIVER_MODESET))
> > > + return -EINVAL;
> > > +
> > > + fb = drm_framebuffer_lookup(dev, file_priv, r->fb_id);
> > > + if (!fb)
> > > + return -ENOENT;
> > > +
> > > + /* For multi-plane framebuffers, we require the driver to place
> > > the
> > > + * GEM objects directly in the drm_framebuffer. For single-
> > > plane
> > > + * framebuffers, we can fall back to create_handle.
> > > + */
> > > + if (!fb->obj[0] &&
> > > + (fb->format->num_planes > 1 || !fb->funcs->create_handle))
> > > {
> > > + ret = -ENODEV;
> > > + goto out;
> > > + }
> > > +
> > > + r->height = fb->height;
> > > + r->width = fb->width;
> > > + r->pixel_format = fb->format->format;
> > > +
> > > + r->flags = 0;
> > > + if (dev->mode_config.allow_fb_modifiers)
> > > + r->flags |= DRM_MODE_FB_MODIFIERS;
> > > +
> > > + for (i = 0; i < ARRAY_SIZE(r->handles); i++) {
> > > + r->handles[i] = 0;
> > > + r->pitches[i] = 0;
> > > + r->offsets[i] = 0;
> > > + r->modifier[i] = 0;
> > > + }
> > >
> > > + for (i = 0; i < fb->format->num_planes; i++) {
> > > + int j;
> > > +
> > > + r->pitches[i] = fb->pitches[i];
> > > + r->offsets[i] = fb->offsets[i];
> > > + if (dev->mode_config.allow_fb_modifiers)
> > > + r->modifier[i] = fb->modifier;
> > > +
> > > + /* If we reuse the same object for multiple planes,
> > > also
> > > + * return the same handle.
> > > + */
> > > + for (j = 0; j < i; j++) {
> > > + if (fb->obj[i] == fb->obj[j]) {
> > > + r->handles[i] = r->handles[j];
> > > + break;
> > > + }
> > > + }
> > > +
> > > + if (r->handles[i])
> > > + continue;
> > > +
> > > + if (fb->obj[i]) {
> > > + ret = drm_gem_handle_create(file_priv, fb-
> > > >obj[i],
> > > + >handles[i]);
> > > + } else {
> > > + WARN_ON(i > 0);
> > > + ret = fb->funcs->create_handle(fb, file_priv,
> > > +
Re: [Intel-gfx] [PATCH 1/5] drm: Add __drm_atomic_helper_crtc_state_reset() & co.
On Thu, Nov 07, 2019 at 04:24:13PM +0200, Ville Syrjälä wrote:
From: Ville Syrjälä
Annoyingly __drm_atomic_helper_crtc_reset() does two
totally separate things:
a) reset the state to defaults values
b) assign the crtc->state pointer
I just want a) without the b) so let's split out part
a) into __drm_atomic_helper_crtc_state_reset(). And
of course we'll do the same thing for planes and connectors.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic_state_helper.c | 70 ---
include/drm/drm_atomic_state_helper.h | 6 ++
2 files changed, 67 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index d0a937fb0c56..a972068d58cf 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -57,6 +57,22 @@
* for these functions.
*/
+/**
+ * __drm_atomic_helper_crtc_state_reset - reset the CRTC state
+ * @crtc_state: atomic CRTC state, must not be NULL
+ * @crtc: CRTC object, must not be NULL
+ *
+ * Initializes the newly allocated @crtc_state with default
+ * values. This is useful for drivers that subclass the CRTC state.
+ */
+void
+__drm_atomic_helper_crtc_state_reset(struct drm_crtc_state *crtc_state,
+struct drm_crtc *crtc)
+{
+ crtc_state->crtc = crtc;
+}
+EXPORT_SYMBOL(__drm_atomic_helper_crtc_state_reset);
+
/**
* __drm_atomic_helper_crtc_reset - reset state on CRTC
* @crtc: drm CRTC
@@ -74,7 +90,7 @@ __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc,
struct drm_crtc_state *crtc_state)
{
if (crtc_state)
- crtc_state->crtc = crtc;
+ __drm_atomic_helper_crtc_state_reset(crtc_state, crtc);
crtc->state = crtc_state;
}
@@ -212,23 +228,43 @@ void drm_atomic_helper_crtc_destroy_state(struct drm_crtc
*crtc,
EXPORT_SYMBOL(drm_atomic_helper_crtc_destroy_state);
/**
- * __drm_atomic_helper_plane_reset - resets planes state to default values
+ * __drm_atomic_helper_plane_state_reset - resets plane state to default values
+ * @plane_state: atomic plane state, must not be NULL
* @plane: plane object, must not be NULL
- * @state: atomic plane state, must not be NULL
*
- * Initializes plane state to default. This is useful for drivers that subclass
- * the plane state.
+ * Initializes the newly allocated @plane_state with default
+ * values. This is useful for drivers that subclass the CRTC state.
*/
-void __drm_atomic_helper_plane_reset(struct drm_plane *plane,
-struct drm_plane_state *state)
+void __drm_atomic_helper_plane_state_reset(struct drm_plane_state *state,
+ struct drm_plane *plane)
{
state->plane = plane;
state->rotation = DRM_MODE_ROTATE_0;
state->alpha = DRM_BLEND_ALPHA_OPAQUE;
state->pixel_blend_mode = DRM_MODE_BLEND_PREMULTI;
+}
+EXPORT_SYMBOL(__drm_atomic_helper_plane_state_reset);
- plane->state = state;
+/**
+ * __drm_atomic_helper_plane_reset - reset state on plane
+ * @plane: drm plane
+ * @plane_state: plane state to assign
+ *
+ * Initializes the newly allocated @plane_state and assigns it to
+ * the _crtc->state pointer of @plane, usually required when
+ * initializing the drivers or when called from the _plane_funcs.reset
+ * hook.
+ *
+ * This is useful for drivers that subclass the plane state.
+ */
+void __drm_atomic_helper_plane_reset(struct drm_plane *plane,
+struct drm_plane_state *plane_state)
+{
+ if (plane_state)
+ __drm_atomic_helper_plane_state_reset(plane_state, plane);
+
+ plane->state = plane_state;
}
EXPORT_SYMBOL(__drm_atomic_helper_plane_reset);
@@ -335,6 +371,22 @@ void drm_atomic_helper_plane_destroy_state(struct
drm_plane *plane,
}
EXPORT_SYMBOL(drm_atomic_helper_plane_destroy_state);
+/**
+ * __drm_atomic_helper_connector_state_reset - reset the connector state
+ * @conn__state: atomic connector state, must not be NULL
typo here, otherwise
Reviewed-by: Lucas De Marchi
Lucas De Marchi
+ * @connector: connectotr object, must not be NULL
+ *
+ * Initializes the newly allocated @conn_state with default
+ * values. This is useful for drivers that subclass the connector state.
+ */
+void
+__drm_atomic_helper_connector_state_reset(struct drm_connector_state
*conn_state,
+ struct drm_connector *connector)
+{
+ conn_state->connector = connector;
+}
+EXPORT_SYMBOL(__drm_atomic_helper_connector_state_reset);
+
/**
* __drm_atomic_helper_connector_reset - reset state on connector
* @connector: drm connector
@@ -352,7 +404,7 @@ __drm_atomic_helper_connector_reset(struct drm_connector
*connector,
struct drm_connector_state *conn_state)
{
if (conn_state)
- conn_state->connector = connector;
+
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/perf: Register sysctl path globally
== Series Details ==
Series: series starting with [1/2] drm/i915/perf: Register sysctl path globally
URL : https://patchwork.freedesktop.org/series/70871/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7556_full -> Patchwork_15738_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_15738_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15738_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_15738_full:
### IGT changes ###
Possible regressions
* igt@gem_ctx_persistence@bcs0-mixed-process:
- shard-iclb: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7556/shard-iclb1/igt@gem_ctx_persiste...@bcs0-mixed-process.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15738/shard-iclb3/igt@gem_ctx_persiste...@bcs0-mixed-process.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gen9_exec_parse@allowed-all}:
- shard-glk: [PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7556/shard-glk3/igt@gen9_exec_pa...@allowed-all.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15738/shard-glk3/igt@gen9_exec_pa...@allowed-all.html
* {igt@gen9_exec_parse@allowed-single}:
- shard-iclb: NOTRUN -> [SKIP][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15738/shard-iclb6/igt@gen9_exec_pa...@allowed-single.html
* {igt@gen9_exec_parse@basic-rejected-ctx-param}:
- shard-tglb: NOTRUN -> [SKIP][6] +2 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15738/shard-tglb4/igt@gen9_exec_pa...@basic-rejected-ctx-param.html
### Piglit changes ###
Possible regressions
* spec@arb_gpu_shader5@texturegatheroffset@fs-rgba-3-unorm-2drect:
- pig-hsw-4770r: NOTRUN -> [FAIL][7] +236 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15738/pig-hsw-4770r/spec@arb_gpu_shader5@texturegatheroff...@fs-rgba-3-unorm-2drect.html
New tests
-
New tests have been introduced between CI_DRM_7556_full and
Patchwork_15738_full:
### New Piglit tests (24) ###
* spec@arb_gpu_shader5@texturegather@vs-rgb-0-uint-2darray:
- Statuses : 1 fail(s)
- Exec time: [5.04] s
* spec@arb_gpu_shader5@texturegather@vs-rgb-0-uint-2drect:
- Statuses : 1 fail(s)
- Exec time: [1.63] s
* spec@arb_gpu_shader5@texturegather@vs-rgb-0-uint-cube:
- Statuses : 1 fail(s)
- Exec time: [1.60] s
* spec@arb_gpu_shader5@texturegather@vs-rgb-0-uint-cubearray:
- Statuses : 1 fail(s)
- Exec time: [1.69] s
* spec@arb_gpu_shader5@texturegather@vs-rgb-1-uint-2darray:
- Statuses : 1 fail(s)
- Exec time: [4.96] s
* spec@arb_gpu_shader5@texturegather@vs-rgb-1-uint-2drect:
- Statuses : 1 fail(s)
- Exec time: [1.62] s
* spec@arb_gpu_shader5@texturegather@vs-rgb-1-uint-cube:
- Statuses : 1 fail(s)
- Exec time: [1.73] s
* spec@arb_gpu_shader5@texturegather@vs-rgb-1-uint-cubearray:
- Statuses : 1 fail(s)
- Exec time: [1.68] s
* spec@arb_gpu_shader5@texturegather@vs-rgb-2-uint-2darray:
- Statuses : 1 fail(s)
- Exec time: [4.97] s
* spec@arb_gpu_shader5@texturegather@vs-rgb-2-uint-2drect:
- Statuses : 1 fail(s)
- Exec time: [1.66] s
* spec@arb_gpu_shader5@texturegather@vs-rgb-2-uint-cube:
- Statuses : 1 fail(s)
- Exec time: [1.78] s
* spec@arb_gpu_shader5@texturegather@vs-rgb-2-uint-cubearray:
- Statuses : 1 fail(s)
- Exec time: [1.76] s
* spec@arb_gpu_shader5@texturegatheroffset@vs-rgb-0-uint-2drect:
- Statuses : 1 fail(s)
- Exec time: [6.95] s
* spec@arb_gpu_shader5@texturegatheroffset@vs-rgb-0-uint-2drect-const:
- Statuses : 1 fail(s)
- Exec time: [7.03] s
* spec@arb_gpu_shader5@texturegatheroffset@vs-rgb-2-uint-2d-const:
- Statuses : 1 fail(s)
- Exec time: [11.19] s
* spec@arb_gpu_shader5@texturegatheroffsets@vs-rgb-0-uint-2d:
- Statuses : 1 fail(s)
- Exec time: [10.49] s
* spec@arb_gpu_shader5@texturegatheroffsets@vs-rgb-0-uint-2darray:
- Statuses : 1 fail(s)
- Exec time: [6.98] s
* spec@arb_gpu_shader5@texturegatheroffsets@vs-rgb-1-uint-2d:
- Statuses : 1 fail(s)
- Exec time: [10.33] s
* spec@arb_gpu_shader5@texturegatheroffsets@vs-rgb-1-uint-2darray:
- Statuses : 1 fail(s)
- Exec time: [6.91] s
* spec@arb_gpu_shader5@texturegatheroffsets@vs-rgb-2-uint-2d:
- Statuses : 1 fail(s)
- Exec time: [10.43] s
*
[Intel-gfx] [PATCH v5 1/2] drm/i915/rps: Add frequency translation helpers
From: Andi Shyti
Add two helpers that for reading the actual GT's frequency. The
two helpers are:
- intel_rps_read_cagf: reads the frequency and returns it not
normalized
- intel_rps_read_actual_frequency: provides the frequency in Hz.
Use the above helpers in sysfs and debugfs.
Signed-off-by: Andi Shyti
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_rps.c | 30 +
drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++
drivers/gpu/drm/i915/i915_debugfs.c | 21 +---
drivers/gpu/drm/i915/i915_sysfs.c | 14 ++
4 files changed, 39 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 106c9fce9d6c..370a11819d6f 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1682,6 +1682,36 @@ u32 intel_get_cagf(struct intel_rps *rps, u32 rpstat)
return cagf;
}
+u32 intel_rps_read_cagf(struct intel_rps *rps)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ u32 freq;
+
+ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+ vlv_punit_get(i915);
+ freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
+ vlv_punit_put(i915);
+
+ return (freq >> 8) & 0xff;
+ }
+
+ return intel_get_cagf(rps, intel_uncore_read(rps_to_gt(rps)->uncore,
+GEN6_RPSTAT1));
+}
+
+u32 intel_rps_read_actual_frequency(struct intel_rps *rps)
+{
+ struct intel_runtime_pm *rpm = rps_to_gt(rps)->uncore->rpm;
+ intel_wakeref_t wakeref;
+ int freq;
+
+ wakeref = intel_runtime_pm_get(rpm);
+ freq = intel_gpu_freq(rps, intel_rps_read_cagf(rps));
+ intel_runtime_pm_put(rpm, wakeref);
+
+ return freq;
+}
+
/* External interface for intel_ips.ko */
static struct drm_i915_private __rcu *ips_mchdev;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h
b/drivers/gpu/drm/i915/gt/intel_rps.h
index 9518c66c9792..bd12a63ecd4a 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -30,6 +30,8 @@ void intel_rps_mark_interactive(struct intel_rps *rps, bool
interactive);
int intel_gpu_freq(struct intel_rps *rps, int val);
int intel_freq_opcode(struct intel_rps *rps, int val);
u32 intel_get_cagf(struct intel_rps *rps, u32 rpstat1);
+u32 intel_rps_read_cagf(struct intel_rps *rps);
+u32 intel_rps_read_actual_frequency(struct intel_rps *rps);
void gen5_rps_irq_handler(struct intel_rps *rps);
void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9cd5ce5bc93b..3ec26b6a48c1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -881,7 +881,7 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) &
GEN6_CURBSYTAVG_MASK;
- cagf = intel_gpu_freq(rps, intel_get_cagf(rps, rpstat));
+ cagf = intel_rps_read_actual_frequency(rps);
intel_uncore_forcewake_put(_priv->uncore, FORCEWAKE_ALL);
@@ -1623,21 +1623,11 @@ static int i915_rps_boost_info(struct seq_file *m, void
*data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_rps *rps = _priv->gt.rps;
- u32 act_freq = rps->cur_freq;
+ u32 act_freq;
intel_wakeref_t wakeref;
- with_intel_runtime_pm_if_in_use(_priv->runtime_pm, wakeref) {
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- vlv_punit_get(dev_priv);
- act_freq = vlv_punit_read(dev_priv,
- PUNIT_REG_GPU_FREQ_STS);
- vlv_punit_put(dev_priv);
- act_freq = (act_freq >> 8) & 0xff;
- } else {
- act_freq = intel_get_cagf(rps,
- I915_READ(GEN6_RPSTAT1));
- }
- }
+ with_intel_runtime_pm_if_in_use(_priv->runtime_pm, wakeref)
+ act_freq = intel_rps_read_actual_frequency(rps);
seq_printf(m, "RPS enabled? %d\n", rps->enabled);
seq_printf(m, "GPU busy? %s\n", yesno(dev_priv->gt.awake));
@@ -1645,8 +1635,7 @@ static int i915_rps_boost_info(struct seq_file *m, void
*data)
atomic_read(>num_waiters));
seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
seq_printf(m, "Frequency requested %d, actual %d\n",
- intel_gpu_freq(rps, rps->cur_freq),
- intel_gpu_freq(rps, act_freq));
+
Re: [Intel-gfx] [RFC v2 02/12] drm/i915/svm: Runtime (RT) allocator support
On Fri, Dec 13, 2019 at 04:58:42PM -0600, Jason Ekstrand wrote:
+/**
+ * struct drm_i915_gem_vm_bind
+ *
+ * Bind an object in a vm's page table.
First off, this is something I've wanted for a while for Vulkan, it's just
never made its way high enough up the priority list. However, it's going
to have to come one way or another soon. I'm glad to see kernel API for
this being proposed.
I do, however, have a few high-level comments/questions about the API:
1. In order to be useful for sparse memory support, the API has to go the
other way around so that it binds a VA range to a range within the BO. It
also needs to be able to handle overlapping where two different VA ranges
may map to the same underlying bytes in the BO. This likely means that
unbind needs to also take a VA range and only unbind that range.
2. If this is going to be useful for managing GL's address space where we
have lots of BOs, we probably want it to take a list of ranges so we
aren't making one ioctl for each thing we want to bind.
Hi Jason,
Yah, some of these requirements came up.
They are not being done here due to time and effort involved in defining
those requirements, implementing and validating.
However, this ioctl can be extended in a backward compatible way to handle
those requirements if required.
3. Why are there no ways to synchronize this with anything? For binding,
this probably isn't really needed as long as the VA range you're binding
is empty. However, if you want to move bindings around or unbind
something, the only option is to block in userspace and then call
bind/unbind. This can be done but it means even more threads in the UMD
which is unpleasant. One could argue that that's more or less what the
kernel is going to have to do so we may as well do it in userspace.
However, I'm not 100% convinced that's true.
--Jason
Yah, that is the thought.
But as SVM feature evolves, I think we can consider handling some such cases
if hadling those in driver does make whole lot sense.
Thanks,
Niranjana
+ */
+struct drm_i915_gem_vm_bind {
+ /** VA start to bind **/
+ __u64 start;
+
+ /** Type of memory to [un]bind **/
+ __u32 type;
+#define I915_GEM_VM_BIND_SVM_OBJ 0
+
+ /** Object handle to [un]bind for I915_GEM_VM_BIND_SVM_OBJ type
**/
+ __u32 handle;
+
+ /** vm to [un]bind **/
+ __u32 vm_id;
+
+ /** Flags **/
+ __u32 flags;
+#define I915_GEM_VM_BIND_UNBIND (1 << 0)
+#define I915_GEM_VM_BIND_READONLY(1 << 1)
+};
+
#if defined(__cplusplus)
}
#endif
--
2.21.0.rc0.32.g243a4c7e27
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Re: [Intel-gfx] [PATCH] drm/i915/dsi: fix pipe D readout for DSI transcoders
On Wed, Dec 11, 2019 at 05:55:23PM +, Jose Souza wrote:
On Wed, 2019-12-11 at 13:08 +0200, Jani Nikula wrote:
Commit 4d89adc7b56f ("drm/i915/display/dsi: Add support to pipe D")
added pipe D support for DSI, but failed to update the state readout.
Reviewed-by: José Roberto de Souza
pushed, thanks.
Lucas De Marchi
Fixes: 4d89adc7b56f ("drm/i915/display/dsi: Add support to pipe D")
Cc: Lucas De Marchi
Cc: José Roberto de Souza
Cc: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 5a4bd37863e3..3e0874e1b0f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10431,6 +10431,9 @@ static bool hsw_get_transcoder_state(struct
intel_crtc *crtc,
case TRANS_DDI_EDP_INPUT_C_ONOFF:
trans_pipe = PIPE_C;
break;
+ case TRANS_DDI_EDP_INPUT_D_ONOFF:
+ trans_pipe = PIPE_D;
+ break;
}
if (trans_pipe == crtc->pipe) {
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Re: [Intel-gfx] [RFC v2 02/12] drm/i915/svm: Runtime (RT) allocator support
On Fri, Dec 13, 2019 at 4:07 PM Niranjana Vishwanathapura <
niranjana.vishwanathap...@intel.com> wrote:
> Shared Virtual Memory (SVM) runtime allocator support allows
> binding a shared virtual address to a buffer object (BO) in the
> device page table through an ioctl call.
>
> Cc: Joonas Lahtinen
> Cc: Jon Bloomfield
> Cc: Daniel Vetter
> Cc: Sudeep Dutt
> Signed-off-by: Niranjana Vishwanathapura <
> niranjana.vishwanathap...@intel.com>
> ---
> drivers/gpu/drm/i915/Kconfig | 11
> drivers/gpu/drm/i915/Makefile | 3 +
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 58 ++
> drivers/gpu/drm/i915/gem/i915_gem_svm.c | 60 +++
> drivers/gpu/drm/i915/gem/i915_gem_svm.h | 22 +++
> drivers/gpu/drm/i915/i915_drv.c | 21 +++
> drivers/gpu/drm/i915/i915_drv.h | 22 +++
> drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
> drivers/gpu/drm/i915/i915_gem_gtt.h | 13
> include/uapi/drm/i915_drm.h | 27 +
> 10 files changed, 227 insertions(+), 11 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_svm.c
> create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_svm.h
>
> diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
> index ba9595960bbe..c2e48710eec8 100644
> --- a/drivers/gpu/drm/i915/Kconfig
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -137,6 +137,16 @@ config DRM_I915_GVT_KVMGT
> Choose this option if you want to enable KVMGT support for
> Intel GVT-g.
>
> +config DRM_I915_SVM
> + bool "Enable Shared Virtual Memory support in i915"
> + depends on STAGING
> + depends on DRM_I915
> + default n
> + help
> + Choose this option if you want Shared Virtual Memory (SVM)
> + support in i915. With SVM support, one can share the virtual
> + address space between a process and the GPU.
> +
> menu "drm/i915 Debugging"
> depends on DRM_I915
> depends on EXPERT
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index e0fd10c0cfb8..75fe45633779 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -153,6 +153,9 @@ i915-y += \
> intel_region_lmem.o \
> intel_wopcm.o
>
> +# SVM code
> +i915-$(CONFIG_DRM_I915_SVM) += gem/i915_gem_svm.o
> +
> # general-purpose microcontroller (GuC) support
> obj-y += gt/uc/
> i915-y += gt/uc/intel_uc.o \
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 5003e616a1ad..af360238a392 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -2836,10 +2836,14 @@ int
> i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
>struct drm_file *file)
> {
> + struct drm_i915_gem_exec_object2 *exec2_list, *exec2_list_user;
> struct drm_i915_gem_execbuffer2 *args = data;
> - struct drm_i915_gem_exec_object2 *exec2_list;
> - struct drm_syncobj **fences = NULL;
> const size_t count = args->buffer_count;
> + struct drm_syncobj **fences = NULL;
> + unsigned int i = 0, svm_count = 0;
> + struct i915_address_space *vm;
> + struct i915_gem_context *ctx;
> + struct i915_svm_obj *svm_obj;
> int err;
>
> if (!check_buffer_count(count)) {
> @@ -2851,15 +2855,46 @@ i915_gem_execbuffer2_ioctl(struct drm_device *dev,
> void *data,
> if (err)
> return err;
>
> + ctx = i915_gem_context_lookup(file->driver_priv, args->rsvd1);
> + if (!ctx || !rcu_access_pointer(ctx->vm))
> + return -ENOENT;
> +
> + rcu_read_lock();
> + vm = i915_vm_get(ctx->vm);
> + rcu_read_unlock();
> +
> +alloc_again:
> + svm_count = vm->svm_count;
> /* Allocate an extra slot for use by the command parser */
> - exec2_list = kvmalloc_array(count + 1, eb_element_size(),
> + exec2_list = kvmalloc_array(count + svm_count + 1,
> eb_element_size(),
> __GFP_NOWARN | GFP_KERNEL);
> if (exec2_list == NULL) {
> DRM_DEBUG("Failed to allocate exec list for %zd buffers\n",
> - count);
> + count + svm_count);
> return -ENOMEM;
> }
> - if (copy_from_user(exec2_list,
> + mutex_lock(>mutex);
> + if (svm_count != vm->svm_count) {
> + mutex_unlock(>mutex);
> + kvfree(exec2_list);
> + goto alloc_again;
> + }
> +
> + list_for_each_entry(svm_obj, >svm_list, link) {
> + memset(_list[i], 0, sizeof(*exec2_list));
> + exec2_list[i].handle = svm_obj->handle;
> + exec2_list[i].offset = svm_obj->offset;
> +
Re: [Intel-gfx] [RESEND PATCH v2] drm: Add getfb2 ioctl
On Fri, 2019-12-13 at 23:36 +0200, Ville Syrjälä wrote:
> On Thu, Oct 03, 2019 at 11:31:25AM -0700, Juston Li wrote:
> > From: Daniel Stone
> >
> > getfb2 allows us to pass multiple planes and modifiers, just like
> > addfb2
> > over addfb.
> >
> > Changes since v1:
> > - unused modifiers set to 0 instead of DRM_FORMAT_MOD_INVALID
> > - update ioctl number
> >
> > Signed-off-by: Daniel Stone
> > Signed-off-by: Juston Li
> > ---
> > drivers/gpu/drm/drm_crtc_internal.h | 2 +
> > drivers/gpu/drm/drm_framebuffer.c | 110
> >
> > drivers/gpu/drm/drm_ioctl.c | 1 +
> > include/uapi/drm/drm.h | 2 +
> > 4 files changed, 115 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_crtc_internal.h
> > b/drivers/gpu/drm/drm_crtc_internal.h
> > index c7d5e4c21423..16f2413403aa 100644
> > --- a/drivers/gpu/drm/drm_crtc_internal.h
> > +++ b/drivers/gpu/drm/drm_crtc_internal.h
> > @@ -216,6 +216,8 @@ int drm_mode_rmfb_ioctl(struct drm_device *dev,
> > void *data, struct drm_file *file_priv);
> > int drm_mode_getfb(struct drm_device *dev,
> >void *data, struct drm_file *file_priv);
> > +int drm_mode_getfb2_ioctl(struct drm_device *dev,
> > + void *data, struct drm_file *file_priv);
> > int drm_mode_dirtyfb_ioctl(struct drm_device *dev,
> >void *data, struct drm_file *file_priv);
> >
> > diff --git a/drivers/gpu/drm/drm_framebuffer.c
> > b/drivers/gpu/drm/drm_framebuffer.c
> > index 57564318ceea..6db54f177443 100644
> > --- a/drivers/gpu/drm/drm_framebuffer.c
> > +++ b/drivers/gpu/drm/drm_framebuffer.c
> > @@ -31,6 +31,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> >
> > @@ -548,7 +549,116 @@ int drm_mode_getfb(struct drm_device *dev,
> >
> > out:
> > drm_framebuffer_put(fb);
> > + return ret;
> > +}
> > +
> > +/**
> > + * drm_mode_getfb2 - get extended FB info
> > + * @dev: drm device for the ioctl
> > + * @data: data pointer for the ioctl
> > + * @file_priv: drm file for the ioctl call
> > + *
> > + * Lookup the FB given its ID and return info about it.
> > + *
> > + * Called by the user via ioctl.
> > + *
> > + * Returns:
> > + * Zero on success, negative errno on failure.
> > + */
> > +int drm_mode_getfb2_ioctl(struct drm_device *dev,
> > + void *data, struct drm_file *file_priv)
> > +{
> > + struct drm_mode_fb_cmd2 *r = data;
> > + struct drm_framebuffer *fb;
> > + unsigned int i;
> > + int ret;
> > +
> > + if (!drm_core_check_feature(dev, DRIVER_MODESET))
> > + return -EINVAL;
> > +
> > + fb = drm_framebuffer_lookup(dev, file_priv, r->fb_id);
> > + if (!fb)
> > + return -ENOENT;
> > +
> > + /* For multi-plane framebuffers, we require the driver to place
> > the
> > +* GEM objects directly in the drm_framebuffer. For single-
> > plane
> > +* framebuffers, we can fall back to create_handle.
> > +*/
> > + if (!fb->obj[0] &&
> > + (fb->format->num_planes > 1 || !fb->funcs->create_handle))
> > {
> > + ret = -ENODEV;
> > + goto out;
> > + }
> > +
> > + r->height = fb->height;
> > + r->width = fb->width;
> > + r->pixel_format = fb->format->format;
> > +
> > + r->flags = 0;
> > + if (dev->mode_config.allow_fb_modifiers)
> > + r->flags |= DRM_MODE_FB_MODIFIERS;
> > +
> > + for (i = 0; i < ARRAY_SIZE(r->handles); i++) {
> > + r->handles[i] = 0;
> > + r->pitches[i] = 0;
> > + r->offsets[i] = 0;
> > + r->modifier[i] = 0;
> > + }
> >
> > + for (i = 0; i < fb->format->num_planes; i++) {
> > + int j;
> > +
> > + r->pitches[i] = fb->pitches[i];
> > + r->offsets[i] = fb->offsets[i];
> > + if (dev->mode_config.allow_fb_modifiers)
> > + r->modifier[i] = fb->modifier;
> > +
> > + /* If we reuse the same object for multiple planes,
> > also
> > +* return the same handle.
> > +*/
> > + for (j = 0; j < i; j++) {
> > + if (fb->obj[i] == fb->obj[j]) {
> > + r->handles[i] = r->handles[j];
> > + break;
> > + }
> > + }
> > +
> > + if (r->handles[i])
> > + continue;
> > +
> > + if (fb->obj[i]) {
> > + ret = drm_gem_handle_create(file_priv, fb-
> > >obj[i],
> > + >handles[i]);
> > + } else {
> > + WARN_ON(i > 0);
> > + ret = fb->funcs->create_handle(fb, file_priv,
> > + >handles[i]);
> > + }
>
> getfb1 doesn't allow non-master/root to see the handles. Here we
> don't
> seem to have that same protection?
Hmm yeah sorry I missed the protections handling.
I think we can just
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix WARN_ON condition for cursor plane ddb allocation
== Series Details ==
Series: drm/i915: Fix WARN_ON condition for cursor plane ddb allocation
URL : https://patchwork.freedesktop.org/series/70893/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7563 -> Patchwork_15753
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15753/index.html
Known issues
Here are the changes found in Patchwork_15753 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_sync@basic-each:
- fi-tgl-y: [PASS][1] -> [INCOMPLETE][2] ([i915#707])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-tgl-y/igt@gem_s...@basic-each.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15753/fi-tgl-y/igt@gem_s...@basic-each.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [PASS][3] -> [DMESG-WARN][4] ([i915#592])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15753/fi-skl-6770hq/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [PASS][5] -> [DMESG-FAIL][6] ([i915#725])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15753/fi-hsw-4770r/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8700k: [PASS][7] -> [INCOMPLETE][8] ([i915#424])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15753/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_requests:
- fi-ivb-3770:[PASS][9] -> [INCOMPLETE][10] ([i915#773])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-ivb-3770/igt@i915_selftest@live_requests.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15753/fi-ivb-3770/igt@i915_selftest@live_requests.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][11] -> [FAIL][12] ([fdo#109635] / [i915#217])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15753/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
Possible fixes
* igt@gem_exec_gttfill@basic:
- {fi-tgl-guc}: [INCOMPLETE][13] ([fdo#111593]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-tgl-guc/igt@gem_exec_gttf...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15753/fi-tgl-guc/igt@gem_exec_gttf...@basic.html
- {fi-tgl-u}: [INCOMPLETE][15] ([fdo#111593]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-tgl-u/igt@gem_exec_gttf...@basic.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15753/fi-tgl-u/igt@gem_exec_gttf...@basic.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770:[DMESG-FAIL][17] ([i915#553] / [i915#725]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-hsw-4770/igt@i915_selftest@live_blt.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15753/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][19] ([fdo#111096] / [i915#323]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15753/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Warnings
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-x1275: [DMESG-WARN][21] ([fdo#107139] / [i915#62] /
[i915#92] / [i915#95]) -> [DMESG-WARN][22] ([fdo#107139] / [i915#62] /
[i915#92])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-kbl-x1275/igt@gem_exec_susp...@basic-s4-devices.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15753/fi-kbl-x1275/igt@gem_exec_susp...@basic-s4-devices.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][24] ([i915#62] / [i915#92]) +3 similar issues
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-kbl-x1275/igt@i915_pm_...@basic-pci-d3-state.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15753/fi-kbl-x1275/igt@i915_pm_...@basic-pci-d3-state.html
* igt@kms_flip@basic-flip-vs-modeset:
- fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92]) ->
[DMESG-WARN][26] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues
[25]:
[Intel-gfx] [PATCH] drm/i915/gem: Serialise object before changing cache-level
Wait for the object to be idle before changing its cache-level and
unbinding. This was dropped as supposedly superfluous from commit
8b1c78e06e61 ("drm/i915: Avoid calling i915_gem_object_unbind holding
object lock"), but it turns out to prevent some cache dirt escaping.
Smells like papering over a race...
Closes: https://gitlab.freedesktop.org/drm/intel/issues/820
Fixes: 8b1c78e06e61 ("drm/i915: Avoid calling i915_gem_object_unbind holding
object lock")
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 88ab7e71f36c..65f1851e2863 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -190,6 +190,13 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
if (obj->cache_level == cache_level)
return 0;
+ ret = i915_gem_object_wait(obj,
+ I915_WAIT_INTERRUPTIBLE |
+ I915_WAIT_ALL,
+ MAX_SCHEDULE_TIMEOUT);
+ if (ret)
+ return ret;
+
ret = i915_gem_object_lock_interruptible(obj);
if (ret)
return ret;
--
2.24.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add device name to display tracepoints
== Series Details ==
Series: drm/i915: Add device name to display tracepoints
URL : https://patchwork.freedesktop.org/series/70886/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7563 -> Patchwork_15750
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15750/index.html
Known issues
Here are the changes found in Patchwork_15750 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_close_race@basic-threads:
- fi-byt-n2820: [PASS][1] -> [TIMEOUT][2] ([i915#816])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-byt-n2820/igt@gem_close_r...@basic-threads.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15750/fi-byt-n2820/igt@gem_close_r...@basic-threads.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-lmem:[PASS][3] -> [DMESG-WARN][4] ([i915#592])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-skl-lmem/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15750/fi-skl-lmem/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [PASS][5] -> [DMESG-FAIL][6] ([i915#725])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15750/fi-hsw-4770r/igt@i915_selftest@live_blt.html
Possible fixes
* igt@gem_exec_gttfill@basic:
- {fi-tgl-guc}: [INCOMPLETE][7] ([fdo#111593]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-tgl-guc/igt@gem_exec_gttf...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15750/fi-tgl-guc/igt@gem_exec_gttf...@basic.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770:[DMESG-FAIL][9] ([i915#553] / [i915#725]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-hsw-4770/igt@i915_selftest@live_blt.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15750/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-ivb-3770:[DMESG-FAIL][11] ([i915#722]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-ivb-3770/igt@i915_selftest@live_gem_contexts.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15750/fi-ivb-3770/igt@i915_selftest@live_gem_contexts.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111096] / [i915#323]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15750/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Warnings
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][16] ([i915#62] / [i915#92]) +2 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15750/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) ->
[DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +6 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7563/fi-kbl-x1275/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15750/fi-kbl-x1275/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (55 -> 47)
--
Missing(8): fi-icl-1065g7 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7563 -> Patchwork_15750
[Intel-gfx] [RFC v2 09/12] drm/i915/svm: Add functions to blitter copy SVM buffers
Add support function to blitter copy SVM VAs without requiring any
gem objects. Also add function to wait for completion of the copy.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_object.h | 3 +
drivers/gpu/drm/i915/gem/i915_gem_wait.c | 2 +-
drivers/gpu/drm/i915/i915_svm.h| 6 +
drivers/gpu/drm/i915/i915_svm_copy.c | 172 +
5 files changed, 184 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_svm_copy.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b574ec31ea2e..97d40172bf27 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -156,7 +156,8 @@ i915-y += \
# SVM code
i915-$(CONFIG_DRM_I915_SVM) += gem/i915_gem_svm.o \
i915_svm.o \
- i915_svm_devmem.o
+ i915_svm_devmem.o \
+ i915_svm_copy.o
# general-purpose microcontroller (GuC) support
obj-y += gt/uc/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 6d8ca3f0ccf7..1defc227c729 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -478,6 +478,9 @@ static inline void __start_cpu_write(struct
drm_i915_gem_object *obj)
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
unsigned int flags,
long timeout);
+long i915_gem_object_wait_fence(struct dma_fence *fence,
+ unsigned int flags,
+ long timeout);
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
unsigned int flags,
const struct i915_sched_attr *attr);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
index 8af55cd3e690..b7905aa8f821 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
@@ -12,7 +12,7 @@
#include "i915_gem_ioctls.h"
#include "i915_gem_object.h"
-static long
+long
i915_gem_object_wait_fence(struct dma_fence *fence,
unsigned int flags,
long timeout)
diff --git a/drivers/gpu/drm/i915/i915_svm.h b/drivers/gpu/drm/i915/i915_svm.h
index ae39c2ef2f18..f8bedb4569b5 100644
--- a/drivers/gpu/drm/i915/i915_svm.h
+++ b/drivers/gpu/drm/i915/i915_svm.h
@@ -33,6 +33,12 @@ static inline bool i915_vm_is_svm_enabled(struct
i915_address_space *vm)
return vm->svm;
}
+int i915_svm_copy_blt(struct intel_context *ce,
+ u64 src_start, u64 dst_start, u64 size,
+ struct dma_fence **fence);
+int i915_svm_copy_blt_wait(struct drm_i915_private *i915,
+ struct dma_fence *fence);
+
int i915_dmem_convert_pfn(struct drm_i915_private *dev_priv,
struct hmm_range *range);
int i915_gem_vm_prefetch_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_svm_copy.c
b/drivers/gpu/drm/i915/i915_svm_copy.c
new file mode 100644
index ..42f7d563f6b4
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_svm_copy.c
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "gem/i915_gem_object_blt.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_pool.h"
+#include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt.h"
+
+static struct i915_vma *
+intel_emit_svm_copy_blt(struct intel_context *ce,
+ u64 src_start, u64 dst_start, u64 buff_size)
+{
+ struct drm_i915_private *i915 = ce->vm->i915;
+ const u32 block_size = SZ_8M; /* ~1ms at 8GiB/s preemption delay */
+ struct intel_engine_pool_node *pool;
+ struct i915_vma *batch;
+ u64 count, rem;
+ u32 size, *cmd;
+ int err;
+
+ GEM_BUG_ON(intel_engine_is_virtual(ce->engine));
+ intel_engine_pm_get(ce->engine);
+
+ if (INTEL_GEN(i915) < 8)
+ return ERR_PTR(-ENOTSUPP);
+
+ count = div_u64(round_up(buff_size, block_size), block_size);
+ size = (1 + 11 * count) * sizeof(u32);
+ size = round_up(size, PAGE_SIZE);
+ pool = intel_engine_get_pool(ce->engine, size);
+ if (IS_ERR(pool)) {
+ err = PTR_ERR(pool);
+ goto out_pm;
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
+ if (IS_ERR(cmd)) {
+ err = PTR_ERR(cmd);
+ goto out_put;
+ }
+
+ rem = buff_size;
+ do {
+ size = min_t(u64, rem, block_size);
+ GEM_BUG_ON(size >> PAGE_SHIFT >
[Intel-gfx] [RFC v2 10/12] drm/i915/svm: Use blitter copy for migration
Use blitter engine to copy pages during migration.
As blitter context virtual address space is shared with other flows,
ensure virtual address are allocated properly from that address space.
Also ensure completion of blitter copy by waiting on the fence of the
issued request.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/i915_svm_devmem.c | 249 -
1 file changed, 245 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_svm_devmem.c
b/drivers/gpu/drm/i915/i915_svm_devmem.c
index 2b0c7f4c51b8..589cf42bc2da 100644
--- a/drivers/gpu/drm/i915/i915_svm_devmem.c
+++ b/drivers/gpu/drm/i915/i915_svm_devmem.c
@@ -15,7 +15,15 @@ struct i915_devmem_migrate {
enum intel_region_id src_id;
enum intel_region_id dst_id;
+ dma_addr_t *host_dma;
+ bool blitter_copy;
u64 npages;
+
+ /* required for blitter copy */
+ struct drm_mm_node src_node;
+ struct drm_mm_node dst_node;
+ struct intel_context *ce;
+ struct dma_fence *fence;
};
struct i915_devmem {
@@ -148,6 +156,139 @@ i915_devmem_page_free_locked(struct drm_i915_private
*dev_priv,
put_page(page);
}
+static int i915_devmem_bind_addr(struct i915_devmem_migrate *migrate,
+bool is_src)
+{
+ struct i915_gem_context *ctx = migrate->ce->gem_context;
+ struct drm_i915_private *i915 = migrate->i915;
+ struct i915_address_space *vm = ctx->vm;
+ struct intel_memory_region *mem;
+ u64 npages = migrate->npages;
+ enum intel_region_id mem_id;
+ struct drm_mm_node *node;
+ struct scatterlist *sg;
+ u32 sg_page_sizes = 0;
+ struct sg_table st;
+ u64 flags = 0;
+ int i, ret;
+
+ if (unlikely(sg_alloc_table(, npages, GFP_KERNEL)))
+ return -ENOMEM;
+
+ if (is_src) {
+ node = >src_node;
+ mem_id = migrate->src_id;
+ flags |= I915_GTT_SVM_READONLY;
+ } else {
+ node = >dst_node;
+ mem_id = migrate->dst_id;
+ }
+
+ mutex_lock(>mutex);
+ ret = i915_gem_gtt_insert(vm, node, npages * PAGE_SIZE,
+ I915_GTT_PAGE_SIZE_2M, 0,
+ 0, vm->total, PIN_USER);
+ mutex_unlock(>mutex);
+ if (unlikely(ret))
+ return ret;
+
+ sg = NULL;
+ st.nents = 0;
+
+ /*
+* XXX: If the source page is missing, source it from a temporary
+* zero filled page. If needed, destination page missing scenarios
+* can be similarly handled by draining data into a temporary page.
+*/
+ for (i = 0; i < npages; i++) {
+ u64 addr;
+
+ if (mem_id == INTEL_REGION_SMEM) {
+ addr = migrate->host_dma[i];
+ } else {
+ struct page *page;
+ unsigned long mpfn;
+
+ mpfn = is_src ? migrate->args->src[i] :
+ migrate->args->dst[i];
+ page = migrate_pfn_to_page(mpfn);
+ mem = i915->mm.regions[mem_id];
+ addr = page_to_pfn(page) - mem->devmem->pfn_first;
+ addr <<= PAGE_SHIFT;
+ addr += mem->region.start;
+ }
+
+ if (sg && (addr == (sg_dma_address(sg) + sg->length))) {
+ sg->length += PAGE_SIZE;
+ sg_dma_len(sg) += PAGE_SIZE;
+ continue;
+ }
+
+ if (sg)
+ sg_page_sizes |= sg->length;
+
+ sg = sg ? __sg_next(sg) : st.sgl;
+ sg_dma_address(sg) = addr;
+ sg_dma_len(sg) = PAGE_SIZE;
+ sg->length = PAGE_SIZE;
+ st.nents++;
+ }
+
+ sg_page_sizes |= sg->length;
+ sg_mark_end(sg);
+ i915_sg_trim();
+
+ ret = svm_bind_addr(vm, node->start, npages * PAGE_SIZE,
+ flags, , sg_page_sizes);
+ sg_free_table();
+
+ return ret;
+}
+
+static void i915_devmem_unbind_addr(struct i915_devmem_migrate *migrate,
+ bool is_src)
+{
+ struct i915_gem_context *ctx = migrate->ce->gem_context;
+ struct i915_address_space *vm = ctx->vm;
+ struct drm_mm_node *node;
+
+ node = is_src ? >src_node : >dst_node;
+ svm_unbind_addr(vm, node->start, migrate->npages * PAGE_SIZE);
+ mutex_lock(>mutex);
+ drm_mm_remove_node(node);
+ mutex_unlock(>mutex);
+}
+
+static int i915_migrate_blitter_copy(struct i915_devmem_migrate *migrate)
+{
+ struct drm_i915_private *i915 = migrate->i915;
+ int ret;
+
+ migrate->ce = i915->engine[BCS0]->kernel_context;
+
[Intel-gfx] [RFC v2 11/12] drm/i915/svm: Add support to en/disable SVM
Add SVM as a capability and allow user to enable/disable SVM
functionality on a per context basis.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Venkata Sandeep Dhanalakota
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 95 ++-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +
.../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 6 ++
drivers/gpu/drm/i915/gem/i915_gem_object.c| 11 +++
drivers/gpu/drm/i915/i915_drv.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 10 ++
drivers/gpu/drm/i915/i915_getparam.c | 3 +
include/uapi/drm/i915_drm.h | 17
9 files changed, 145 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index d91975efc940..7db09c8bacb5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -77,6 +77,7 @@
#include "i915_gem_context.h"
#include "i915_globals.h"
+#include "i915_svm.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
#include "i915_gem_ioctls.h"
@@ -961,6 +962,78 @@ int i915_gem_vm_destroy_ioctl(struct drm_device *dev, void
*data,
return 0;
}
+static int i915_gem_vm_setparam_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+ struct drm_i915_file_private *file_priv = file->driver_priv;
+ struct drm_i915_gem_vm_param *args = data;
+ struct i915_address_space *vm;
+ int err = 0;
+ u32 id;
+
+ id = args->vm_id;
+ if (!id)
+ return -ENOENT;
+
+ err = mutex_lock_interruptible(_priv->vm_idr_lock);
+ if (err)
+ return err;
+
+ vm = idr_find(_priv->vm_idr, id);
+
+ mutex_unlock(_priv->vm_idr_lock);
+ if (!vm)
+ return -ENOENT;
+
+ switch (lower_32_bits(args->param)) {
+ case I915_GEM_VM_PARAM_SVM:
+ /* FIXME: Ensure ppgtt is empty before switching */
+ if (!i915_has_svm(file_priv->dev_priv))
+ err = -ENOTSUPP;
+ else if (args->value)
+ err = i915_svm_bind_mm(vm);
+ else
+ i915_svm_unbind_mm(vm);
+ break;
+ default:
+ err = -EINVAL;
+ }
+ return err;
+}
+
+static int i915_gem_vm_getparam_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+ struct drm_i915_file_private *file_priv = file->driver_priv;
+ struct drm_i915_gem_vm_param *args = data;
+ struct i915_address_space *vm;
+ int err = 0;
+ u32 id;
+
+ id = args->vm_id;
+ if (!id)
+ return -ENOENT;
+
+ err = mutex_lock_interruptible(_priv->vm_idr_lock);
+ if (err)
+ return err;
+
+ vm = idr_find(_priv->vm_idr, id);
+
+ mutex_unlock(_priv->vm_idr_lock);
+ if (!vm)
+ return -ENOENT;
+
+ switch (lower_32_bits(args->param)) {
+ case I915_GEM_VM_PARAM_SVM:
+ args->value = i915_vm_is_svm_enabled(vm);
+ break;
+ default:
+ err = -EINVAL;
+ }
+ return err;
+}
+
struct context_barrier_task {
struct i915_active base;
void (*task)(void *data);
@@ -2382,6 +2455,21 @@ int i915_gem_context_getparam_ioctl(struct drm_device
*dev, void *data,
return ret;
}
+int i915_gem_getparam_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+ struct drm_i915_gem_context_param *args = data;
+ u32 class = upper_32_bits(args->param);
+
+ switch (class) {
+ case 0:
+ return i915_gem_context_getparam_ioctl(dev, data, file);
+ case 2:
+ return i915_gem_vm_getparam_ioctl(dev, data, file);
+ }
+ return -EINVAL;
+}
+
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
@@ -2404,14 +2492,15 @@ int i915_gem_setparam_ioctl(struct drm_device *dev,
void *data,
struct drm_file *file)
{
struct drm_i915_gem_context_param *args = data;
- u32 object_class = upper_32_bits(args->param);
+ u32 class = upper_32_bits(args->param);
- switch (object_class) {
+ switch (class) {
case 0:
return i915_gem_context_setparam_ioctl(dev, data, file);
case 1:
return i915_gem_object_setparam_ioctl(dev, data, file);
-
+ case 2:
+ return i915_gem_vm_setparam_ioctl(dev, data, file);
}
return -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
[Intel-gfx] [RFC v2 01/12] drm/i915/svm: Add SVM documentation
Add Shared Virtual Memory (SVM) support information. Cc: Joonas Lahtinen Cc: Jon Bloomfield Cc: Daniel Vetter Cc: Sudeep Dutt Signed-off-by: Niranjana Vishwanathapura --- Documentation/gpu/i915.rst | 29 + 1 file changed, 29 insertions(+) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index e539c42a3e78..0bc63489 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -415,6 +415,35 @@ Object Tiling IOCTLs .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c :doc: buffer object tiling +Shared Virtual Memory (SVM) +--- + +Shared Virtual Memory (SVM) allows the programmer to use a single virtual +address space which will be shared between threads executing on CPUs and GPUs. +It abstracts away from the user the location of the backing memory, and hence +simplifies the user programming model. +SVM supports two types of virtual memory allocation methods. +Runtime allocator requires the driver to provide memory allocation and +management interface, like buffer object (BO) interface. +Whereas system allocator makes use of default OS memory allocation and +management support like malloc(). + +Linux kernel has a Heterogeneous Memory Management (HMM) framework to +Support SVM system allocator. HMM’s address space mirroring support allows +sharing of the address space by duplicating sections of CPU page tables in the +device page tables. This enables both CPU and GPU access a physical memory +location using the same virtual address. Linux kernel also provides the ability +to plugin device memory with the system (as a special ZONE_DEVICE type) and +allocates struct page for each device memory page. It also provides a mechanism +to migrate pages from host to device memory and vice versa. +More information on HMM can be found here. +https://www.kernel.org/doc/Documentation/vm/hmm.rst + +i915 supports both SVM system and runtime allocator. As PCIe is a non-coherent +bus, it plugs in device memory as DEVICE_PRIVATE and no memory access across +PCIe link is allowed. Any such access will trigger migration of the page/s +or BOs before the memory is accessed. + Microcontrollers -- 2.21.0.rc0.32.g243a4c7e27 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC v2 12/12] drm/i915/svm: Add page table dump support
Add support to dump page table for debug purpose.
Here is an example dump. Format is,
[] :
Page Table dump start 0x0 len 0x
[0x0fe] 0x7f000: 0x6b0003
[0x1e6] 0x7f798: 0x6c0003
[0x16d] 0x7f79ada00: 0x5f0003
[0x000] 0x7f79ada00: 0x610803
[0x16e] 0x7f79adc00: 0x6d0003
[0x000] 0x7f79adc00: 0x630803
[0x100] 0x8: 0x6f0003
[0x000] 0x8: 0x73
[0x000] 0x8: 0x710003
[0x000] 0x8: 0x5d0803
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/Kconfig.debug| 14 +++
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 1 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 92 +++
drivers/gpu/drm/i915/i915_gem_gtt.h | 14 +++
4 files changed, 121 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index 206882e154bc..257510a38b15 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -221,3 +221,17 @@ config DRM_I915_DEBUG_RUNTIME_PM
driver loading, suspend and resume operations.
If in doubt, say "N"
+
+config DRM_I915_DUMP_PPGTT
+bool "Enable PPGTT Page Table dump support"
+depends on DRM_I915
+default n
+help
+ Choose this option to enable PPGTT page table dump support.
+ The page table snapshot helps developers to debug page table
+ related issues. This will affect performance and dumps a lot of
+ information, so only recommended for developer debug.
+
+ Recommended for driver developers only.
+
+ If in doubt, say "N".
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index a7ac24de2017..2c09d4bdee6f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2678,6 +2678,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
intel_engine_pool_mark_active(eb.batch->private, eb.request);
trace_i915_request_queue(eb.request, eb.batch_flags);
+ ppgtt_dump(eb.context->vm, 0, eb.context->vm->total);
err = eb_submit();
err_request:
add_to_client(eb.request, file);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 192674f03e4e..a473f43c5320 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1227,6 +1227,97 @@ static int gen8_ppgtt_alloc(struct i915_address_space
*vm,
return err;
}
+#ifdef CONFIG_DRM_I915_DUMP_PPGTT
+static void __gen8_ppgtt_dump(struct i915_address_space * const vm,
+ struct i915_page_directory * const pd,
+ u64 start, u64 end, int lvl)
+{
+ char *prefix[4] = { "\t\t\t\t", "\t\t\t", "\t\t", "\t"};
+ char *format = "%s [0x%03x] 0x%llx: 0x%llx\n";
+ unsigned int idx, len;
+ gen8_pte_t *vaddr;
+ unsigned int pdpe;
+ bool is_large;
+
+ GEM_BUG_ON(end > vm->total >> GEN8_PTE_SHIFT);
+
+ len = gen8_pd_range(start, end, lvl--, );
+ GEM_BUG_ON(!len || (idx + len - 1) >> gen8_pd_shift(1));
+
+ spin_lock(>lock);
+ GEM_BUG_ON(!atomic_read(px_used(pd))); /* Must be pinned! */
+ do {
+ struct i915_page_table *pt = pd->entry[idx];
+
+ if (!pt) {
+ start += (1 << gen8_pd_shift(lvl + 1));
+ continue;
+ }
+
+ vaddr = kmap_atomic_px(>pt);
+ pdpe = gen8_pd_index(start, lvl + 1);
+ DRM_DEBUG_DRIVER(format, prefix[lvl + 1], pdpe,
+start, vaddr[pdpe]);
+ is_large = (vaddr[pdpe] & GEN8_PDE_PS_2M);
+ kunmap_atomic(vaddr);
+ if (is_large) {
+ start += (1 << gen8_pd_shift(lvl + 1));
+ continue;
+ }
+
+ if (lvl) {
+ atomic_inc(>used);
+ spin_unlock(>lock);
+
+ __gen8_ppgtt_dump(vm, as_pd(pt),
+ start, end, lvl);
+
+ start += (1 << gen8_pd_shift(lvl + 1));
+ spin_lock(>lock);
+ atomic_dec(>used);
+ GEM_BUG_ON(!atomic_read(>used));
+ } else {
+ unsigned int count = gen8_pt_count(start, end);
+
+ pdpe = gen8_pd_index(start, lvl);
+ vaddr = kmap_atomic_px(pt);
+ while (count) {
+ if (vaddr[pdpe] !=
[Intel-gfx] [RFC v2 05/12] drm/i915/svm: Page table mirroring support
Use HMM page table mirroring support to build device page table.
Implement the bind ioctl and bind the process address range in the
specified context's ppgtt.
Handle invalidation notifications by unbinding the address range.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/Kconfig| 3 +
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.c | 5 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +
drivers/gpu/drm/i915/i915_svm.c | 324
drivers/gpu/drm/i915/i915_svm.h | 50 +
include/uapi/drm/i915_drm.h | 9 +-
8 files changed, 401 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_svm.c
create mode 100644 drivers/gpu/drm/i915/i915_svm.h
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index c2e48710eec8..689e57fe3973 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -141,6 +141,9 @@ config DRM_I915_SVM
bool "Enable Shared Virtual Memory support in i915"
depends on STAGING
depends on DRM_I915
+ depends on MMU
+ select HMM_MIRROR
+ select MMU_NOTIFIER
default n
help
Choose this option if you want Shared Virtual Memory (SVM)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 75fe45633779..7d4cd9eefd12 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -154,7 +154,8 @@ i915-y += \
intel_wopcm.o
# SVM code
-i915-$(CONFIG_DRM_I915_SVM) += gem/i915_gem_svm.o
+i915-$(CONFIG_DRM_I915_SVM) += gem/i915_gem_svm.o \
+ i915_svm.o
# general-purpose microcontroller (GuC) support
obj-y += gt/uc/
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d452ea8e40b3..866d3cbb1edf 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -62,6 +62,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_ioctls.h"
#include "gem/i915_gem_mman.h"
+#include "gem/i915_gem_svm.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
@@ -73,6 +74,7 @@
#include "i915_perf.h"
#include "i915_query.h"
#include "i915_suspend.h"
+#include "i915_svm.h"
#include "i915_switcheroo.h"
#include "i915_sysfs.h"
#include "i915_trace.h"
@@ -2694,6 +2696,9 @@ static int i915_gem_vm_bind_ioctl(struct drm_device *dev,
void *data,
switch (args->type) {
case I915_GEM_VM_BIND_SVM_OBJ:
ret = i915_gem_vm_bind_svm_obj(vm, args, file);
+ break;
+ case I915_GEM_VM_BIND_SVM_BUFFER:
+ ret = i915_gem_vm_bind_svm_buffer(vm, args);
}
i915_vm_put(vm);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6657ff41dc3f..192674f03e4e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -42,6 +42,7 @@
#include "i915_drv.h"
#include "i915_scatterlist.h"
+#include "i915_svm.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -562,6 +563,7 @@ static void i915_address_space_fini(struct
i915_address_space *vm)
drm_mm_takedown(>mm);
mutex_destroy(>mutex);
+ mutex_destroy(>svm_mutex);
}
void __i915_vm_close(struct i915_address_space *vm)
@@ -591,6 +593,7 @@ static void __i915_vm_release(struct work_struct *work)
struct i915_address_space *vm =
container_of(work, struct i915_address_space, rcu.work);
+ i915_svm_unbind_mm(vm);
vm->cleanup(vm);
i915_address_space_fini(vm);
@@ -620,6 +623,7 @@ static void i915_address_space_init(struct
i915_address_space *vm, int subclass)
* attempt holding the lock is immediately reported by lockdep.
*/
mutex_init(>mutex);
+ mutex_init(>svm_mutex);
lockdep_set_subclass(>mutex, subclass);
i915_gem_shrinker_taints_mutex(vm->i915, >mutex);
@@ -631,6 +635,7 @@ static void i915_address_space_init(struct
i915_address_space *vm, int subclass)
INIT_LIST_HEAD(>bound_list);
INIT_LIST_HEAD(>svm_list);
+ RCU_INIT_POINTER(vm->svm, NULL);
}
static int __setup_page_dma(struct i915_address_space *vm,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 8a8a314e1295..e06e6447e0d7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -293,6 +293,8 @@ struct i915_svm_obj {
u64 offset;
};
+struct i915_svm;
+
struct i915_address_space {
struct kref ref;
struct rcu_work rcu;
@@ -342,6 +344,8 @@ struct i915_address_space {
*/
struct list_head svm_list;
unsigned int svm_count;
+ struct i915_svm *svm;
+ struct mutex svm_mutex;
[Intel-gfx] [RFC v2 06/12] drm/i915/svm: Device memory support
Plugin device memory through HMM as DEVICE_PRIVATE.
Add support functions to allocate pages and free pages from device memory.
Implement ioctl to prefetch pages from host to device memory.
For now, only support migrating pages from host memory to device memory.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/Kconfig | 9 +
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_object.c | 13 -
drivers/gpu/drm/i915/i915_buddy.h | 12 +
drivers/gpu/drm/i915/i915_drv.c| 1 +
drivers/gpu/drm/i915/i915_svm.c| 6 +
drivers/gpu/drm/i915/i915_svm.h| 15 +
drivers/gpu/drm/i915/i915_svm_devmem.c | 400 +
drivers/gpu/drm/i915/intel_memory_region.h | 14 +
drivers/gpu/drm/i915/intel_region_lmem.c | 10 +
include/uapi/drm/i915_drm.h| 22 ++
11 files changed, 491 insertions(+), 14 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_svm_devmem.c
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 689e57fe3973..66337f2ca2bf 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -141,9 +141,18 @@ config DRM_I915_SVM
bool "Enable Shared Virtual Memory support in i915"
depends on STAGING
depends on DRM_I915
+ depends on ARCH_ENABLE_MEMORY_HOTPLUG
+ depends on ARCH_ENABLE_MEMORY_HOTREMOVE
+ depends on MEMORY_HOTPLUG
+ depends on MEMORY_HOTREMOVE
+ depends on ARCH_HAS_PTE_DEVMAP
+ depends on SPARSEMEM_VMEMMAP
+ depends on ZONE_DEVICE
+ depends on DEVICE_PRIVATE
depends on MMU
select HMM_MIRROR
select MMU_NOTIFIER
+ select MIGRATE_VMA_HELPER
default n
help
Choose this option if you want Shared Virtual Memory (SVM)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7d4cd9eefd12..b574ec31ea2e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -155,7 +155,8 @@ i915-y += \
# SVM code
i915-$(CONFIG_DRM_I915_SVM) += gem/i915_gem_svm.o \
- i915_svm.o
+ i915_svm.o \
+ i915_svm_devmem.o
# general-purpose microcontroller (GuC) support
obj-y += gt/uc/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 003d81c171d2..f868a301fc04 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -504,19 +504,6 @@ int __init i915_global_objects_init(void)
return 0;
}
-static enum intel_region_id
-__region_id(u32 region)
-{
- enum intel_region_id id;
-
- for (id = 0; id < INTEL_REGION_UNKNOWN; ++id) {
- if (intel_region_map[id] == region)
- return id;
- }
-
- return INTEL_REGION_UNKNOWN;
-}
-
bool
i915_gem_object_svm_mapped(struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/i915_buddy.h
b/drivers/gpu/drm/i915/i915_buddy.h
index ed41f3507cdc..afc493e6c130 100644
--- a/drivers/gpu/drm/i915/i915_buddy.h
+++ b/drivers/gpu/drm/i915/i915_buddy.h
@@ -9,6 +9,9 @@
#include
#include
+/* 512 bits (one per pages) supports 2MB blocks */
+#define I915_BUDDY_MAX_PAGES 512
+
struct i915_buddy_block {
#define I915_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12)
#define I915_BUDDY_HEADER_STATE GENMASK_ULL(11, 10)
@@ -32,6 +35,15 @@ struct i915_buddy_block {
*/
struct list_head link;
struct list_head tmp_link;
+
+ unsigned long pfn_first;
+ /*
+* FIXME: There are other alternatives to bitmap. Like splitting the
+* block into contiguous 4K sized blocks. But it is part of bigger
+* issues involving partially invalidating large mapping, freeing the
+* blocks etc., revisit.
+*/
+ unsigned long bitmap[BITS_TO_LONGS(I915_BUDDY_MAX_PAGES)];
};
#define I915_BUDDY_MAX_ORDER I915_BUDDY_HEADER_ORDER
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 866d3cbb1edf..f1b92fd3d234 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2765,6 +2765,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_VM_BIND, i915_gem_vm_bind_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_VM_PREFETCH, i915_gem_vm_prefetch_ioctl,
DRM_RENDER_ALLOW)
};
static struct drm_driver driver = {
diff --git a/drivers/gpu/drm/i915/i915_svm.c b/drivers/gpu/drm/i915/i915_svm.c
index 5941be5b5803..31a80ae0dd45 100644
---
[Intel-gfx] [RFC v2 07/12] drm/i915/svm: Implicitly migrate pages upon CPU fault
As PCIe is non-coherent link, do not allow direct memory access across
PCIe link. Handle CPU fault by migrating pages back to host memory.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/i915_svm_devmem.c | 70 +-
1 file changed, 69 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_svm_devmem.c
b/drivers/gpu/drm/i915/i915_svm_devmem.c
index 0a1f1394f196..98ab27879041 100644
--- a/drivers/gpu/drm/i915/i915_svm_devmem.c
+++ b/drivers/gpu/drm/i915/i915_svm_devmem.c
@@ -286,9 +286,77 @@ int i915_devmem_migrate_vma(struct intel_memory_region
*mem,
return ret;
}
+static vm_fault_t
+i915_devmem_fault_alloc_and_copy(struct i915_devmem_migrate *migrate)
+{
+ struct device *dev = migrate->i915->drm.dev;
+ struct migrate_vma *args = migrate->args;
+ struct page *dpage, *spage;
+
+ DRM_DEBUG_DRIVER("start 0x%lx\n", args->start);
+ /* Allocate host page */
+ spage = migrate_pfn_to_page(args->src[0]);
+ if (unlikely(!spage || !(args->src[0] & MIGRATE_PFN_MIGRATE)))
+ return 0;
+
+ dpage = alloc_page_vma(GFP_HIGHUSER, args->vma, args->start);
+ if (unlikely(!dpage))
+ return VM_FAULT_SIGBUS;
+ lock_page(dpage);
+
+ args->dst[0] = migrate_pfn(page_to_pfn(dpage)) | MIGRATE_PFN_LOCKED;
+
+ /* Copy the pages */
+ migrate->npages = 1;
+
+ return 0;
+}
+
+void i915_devmem_fault_finalize_and_map(struct i915_devmem_migrate *migrate)
+{
+ DRM_DEBUG_DRIVER("\n");
+}
+
+static inline struct i915_devmem *page_to_devmem(struct page *page)
+{
+ return container_of(page->pgmap, struct i915_devmem, pagemap);
+}
+
static vm_fault_t i915_devmem_migrate_to_ram(struct vm_fault *vmf)
{
- return VM_FAULT_SIGBUS;
+ struct i915_devmem *devmem = page_to_devmem(vmf->page);
+ struct drm_i915_private *i915 = devmem->i915;
+ struct i915_devmem_migrate migrate = {0};
+ unsigned long src = 0, dst = 0;
+ vm_fault_t ret;
+ struct migrate_vma args = {
+ .vma= vmf->vma,
+ .start = vmf->address,
+ .end= vmf->address + PAGE_SIZE,
+ .src= ,
+ .dst= ,
+ };
+
+ /* XXX: Opportunistically migrate more pages? */
+ DRM_DEBUG_DRIVER("addr 0x%lx\n", args.start);
+ migrate.i915 = i915;
+ migrate.args =
+ migrate.src_id = INTEL_REGION_LMEM;
+ migrate.dst_id = INTEL_REGION_SMEM;
+ if (migrate_vma_setup() < 0)
+ return VM_FAULT_SIGBUS;
+ if (!args.cpages)
+ return 0;
+
+ ret = i915_devmem_fault_alloc_and_copy();
+ if (ret || dst == 0)
+ goto done;
+
+ migrate_vma_pages();
+ i915_devmem_fault_finalize_and_map();
+done:
+ migrate_vma_finalize();
+ return ret;
}
static void i915_devmem_page_free(struct page *page)
--
2.21.0.rc0.32.g243a4c7e27
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[Intel-gfx] [RFC v2 00/12] drm/i915/svm: Add SVM support
Shared Virtual Memory (SVM) allows the programmer to use a single virtual address space which will be shared between threads executing on CPUs and GPUs. It abstracts away from the user the location of the backing memory, and hence simplifies the user programming model. SVM supports two types of virtual memory allocation methods. Runtime allocator requires the driver to provide memory allocation and management interface, like buffer object (BO) interface. Whereas system allocator makes use of default OS memory allocation and management support like malloc(). This patch series adds both SVM system and runtime allocator support to i915 driver. The patch series includes - SVM support for both system and runtime allocation. - Plugin in device memory with the Linux kernel. - User API advertising SVM capability and configuration by user on per vm basis. - User API to bind an address range or a BO with a device page table. - User API to prefetch an address range to device memory. - Implicit migration by moving pages or BOs back from device to host memory upon CPU access. - CPU copy and blitter copy support for migrating the pages/BOs. - Large page mapping support - Page table dump support. References: https://www.kernel.org/doc/Documentation/vm/hmm.rst The HMM use cases in the Linux kernel. Test RFC series "[RFC i-g-t 0/7] tests/i915/svm: Shared Virtual Memory (SVM) test" v2: - Use updated HMM API - HMM usage changes as per review feedback - UAPI name change as per review feedback - Reformat RFC series - Some minor fixes Niranjana Vishwanathapura (11): drm/i915/svm: Add SVM documentation drm/i915/svm: Runtime (RT) allocator support drm/i915/svm: Page table update support for SVM drm/i915/svm: Page table mirroring support drm/i915/svm: Device memory support drm/i915/svm: Implicitly migrate pages upon CPU fault drm/i915/svm: Page copy support during migration drm/i915/svm: Add functions to blitter copy SVM buffers drm/i915/svm: Use blitter copy for migration drm/i915/svm: Add support to en/disable SVM drm/i915/svm: Add page table dump support Venkata Sandeep Dhanalakota (1): drm/i915/svm: Implicitly migrate BOs upon CPU access Documentation/gpu/i915.rst| 29 + drivers/gpu/drm/i915/Kconfig | 23 + drivers/gpu/drm/i915/Kconfig.debug| 14 + drivers/gpu/drm/i915/Makefile | 6 + drivers/gpu/drm/i915/gem/i915_gem_context.c | 95 ++- drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 + .../gpu/drm/i915/gem/i915_gem_context_types.h | 1 + .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 65 +- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 10 + drivers/gpu/drm/i915/gem/i915_gem_object.c| 43 +- drivers/gpu/drm/i915/gem/i915_gem_object.h| 6 + drivers/gpu/drm/i915/gem/i915_gem_svm.c | 60 ++ drivers/gpu/drm/i915/gem/i915_gem_svm.h | 22 + drivers/gpu/drm/i915/gem/i915_gem_wait.c | 2 +- drivers/gpu/drm/i915/i915_buddy.h | 12 + drivers/gpu/drm/i915/i915_drv.c | 31 +- drivers/gpu/drm/i915/i915_drv.h | 32 + drivers/gpu/drm/i915/i915_gem_gtt.c | 158 +++- drivers/gpu/drm/i915/i915_gem_gtt.h | 41 + drivers/gpu/drm/i915/i915_getparam.c | 3 + drivers/gpu/drm/i915/i915_svm.c | 330 drivers/gpu/drm/i915/i915_svm.h | 71 ++ drivers/gpu/drm/i915/i915_svm_copy.c | 172 drivers/gpu/drm/i915/i915_svm_devmem.c| 781 ++ drivers/gpu/drm/i915/intel_memory_region.c| 4 - drivers/gpu/drm/i915/intel_memory_region.h| 18 + drivers/gpu/drm/i915/intel_region_lmem.c | 10 + include/uapi/drm/i915_drm.h | 73 ++ 28 files changed, 2078 insertions(+), 36 deletions(-) create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_svm.c create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_svm.h create mode 100644 drivers/gpu/drm/i915/i915_svm.c create mode 100644 drivers/gpu/drm/i915/i915_svm.h create mode 100644 drivers/gpu/drm/i915/i915_svm_copy.c create mode 100644 drivers/gpu/drm/i915/i915_svm_devmem.c -- 2.21.0.rc0.32.g243a4c7e27 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC v2 08/12] drm/i915/svm: Page copy support during migration
Copy the pages duing SVM migration using memcpy().
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/i915_svm_devmem.c | 72 ++
1 file changed, 72 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_svm_devmem.c
b/drivers/gpu/drm/i915/i915_svm_devmem.c
index 98ab27879041..2b0c7f4c51b8 100644
--- a/drivers/gpu/drm/i915/i915_svm_devmem.c
+++ b/drivers/gpu/drm/i915/i915_svm_devmem.c
@@ -148,6 +148,69 @@ i915_devmem_page_free_locked(struct drm_i915_private
*dev_priv,
put_page(page);
}
+static int i915_migrate_cpu_copy(struct i915_devmem_migrate *migrate)
+{
+ const unsigned long *src = migrate->args->src;
+ unsigned long *dst = migrate->args->dst;
+ struct drm_i915_private *i915 = migrate->i915;
+ struct intel_memory_region *mem;
+ void *src_vaddr, *dst_vaddr;
+ u64 src_addr, dst_addr;
+ struct page *page;
+ int i, ret = 0;
+
+ /* XXX: Copy multiple pages at a time */
+ for (i = 0; !ret && i < migrate->npages; i++) {
+ if (!dst[i])
+ continue;
+
+ page = migrate_pfn_to_page(dst[i]);
+ mem = i915->mm.regions[migrate->dst_id];
+ dst_addr = page_to_pfn(page);
+ if (migrate->dst_id != INTEL_REGION_SMEM)
+ dst_addr -= mem->devmem->pfn_first;
+ dst_addr <<= PAGE_SHIFT;
+
+ if (migrate->dst_id == INTEL_REGION_SMEM)
+ dst_vaddr = phys_to_virt(dst_addr);
+ else
+ dst_vaddr = io_mapping_map_atomic_wc(>iomap,
+dst_addr);
+ if (unlikely(!dst_vaddr))
+ return -ENOMEM;
+
+ page = migrate_pfn_to_page(src[i]);
+ mem = i915->mm.regions[migrate->src_id];
+ src_addr = page_to_pfn(page);
+ if (migrate->src_id != INTEL_REGION_SMEM)
+ src_addr -= mem->devmem->pfn_first;
+ src_addr <<= PAGE_SHIFT;
+
+ if (migrate->src_id == INTEL_REGION_SMEM)
+ src_vaddr = phys_to_virt(src_addr);
+ else
+ src_vaddr = io_mapping_map_atomic_wc(>iomap,
+src_addr);
+
+ if (likely(src_vaddr))
+ memcpy(dst_vaddr, src_vaddr, PAGE_SIZE);
+ else
+ ret = -ENOMEM;
+
+ if (migrate->dst_id != INTEL_REGION_SMEM)
+ io_mapping_unmap_atomic(dst_vaddr);
+
+ if (migrate->src_id != INTEL_REGION_SMEM && src_vaddr)
+ io_mapping_unmap_atomic(src_vaddr);
+
+ DRM_DEBUG_DRIVER("src [%d] 0x%llx, dst [%d] 0x%llx\n",
+migrate->src_id, src_addr,
+migrate->dst_id, dst_addr);
+ }
+
+ return ret;
+}
+
static int
i915_devmem_migrate_alloc_and_copy(struct i915_devmem_migrate *migrate)
{
@@ -207,6 +270,8 @@ i915_devmem_migrate_alloc_and_copy(struct
i915_devmem_migrate *migrate)
/* Copy the pages */
migrate->npages = npages;
+ /* XXX: Flush the caches? */
+ ret = i915_migrate_cpu_copy(migrate);
migrate_out:
if (unlikely(ret)) {
for (i = 0; i < npages; i++) {
@@ -292,6 +357,7 @@ i915_devmem_fault_alloc_and_copy(struct i915_devmem_migrate
*migrate)
struct device *dev = migrate->i915->drm.dev;
struct migrate_vma *args = migrate->args;
struct page *dpage, *spage;
+ int err;
DRM_DEBUG_DRIVER("start 0x%lx\n", args->start);
/* Allocate host page */
@@ -308,6 +374,12 @@ i915_devmem_fault_alloc_and_copy(struct
i915_devmem_migrate *migrate)
/* Copy the pages */
migrate->npages = 1;
+ err = i915_migrate_cpu_copy(migrate);
+ if (unlikely(err)) {
+ __free_page(dpage);
+ args->dst[0] = 0;
+ return VM_FAULT_SIGBUS;
+ }
return 0;
}
--
2.21.0.rc0.32.g243a4c7e27
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[Intel-gfx] [RFC v2 03/12] drm/i915/svm: Implicitly migrate BOs upon CPU access
From: Venkata Sandeep Dhanalakota
As PCIe is non-coherent link, do not allow direct access to buffer
objects across the PCIe link for SVM case. Upon CPU accesses (mmap, pread),
migrate buffer object to host memory.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Cc: Niranjana Vishwanathapura
Signed-off-by: Venkata Sandeep Dhanalakota
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 10
drivers/gpu/drm/i915/gem/i915_gem_object.c | 29 +-
drivers/gpu/drm/i915/gem/i915_gem_object.h | 3 +++
drivers/gpu/drm/i915/intel_memory_region.c | 4 ---
drivers/gpu/drm/i915/intel_memory_region.h | 4 +++
5 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 879fff8adc48..fc1a11f0bec9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -14,6 +14,7 @@
#include "i915_drv.h"
#include "i915_gem_gtt.h"
#include "i915_gem_ioctls.h"
+#include "i915_gem_lmem.h"
#include "i915_gem_object.h"
#include "i915_gem_mman.h"
#include "i915_trace.h"
@@ -295,6 +296,15 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
if (i915_gem_object_is_readonly(obj) && write)
return VM_FAULT_SIGBUS;
+ /* Implicitly migrate BO to SMEM if it is SVM mapped */
+ if (i915_gem_object_svm_mapped(obj) && i915_gem_object_is_lmem(obj)) {
+ u32 regions[] = { REGION_MAP(INTEL_MEMORY_SYSTEM, 0) };
+
+ ret = i915_gem_object_migrate_region(obj, regions, 1);
+ if (ret)
+ goto err;
+ }
+
/* We don't use vmf->pgoff since that has the fake offset */
page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 025c26266801..003d81c171d2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -517,12 +517,17 @@ __region_id(u32 region)
return INTEL_REGION_UNKNOWN;
}
+bool
+i915_gem_object_svm_mapped(struct drm_i915_gem_object *obj)
+{
+ return false;
+}
+
static int i915_gem_object_region_select(struct drm_i915_private *dev_priv,
struct drm_i915_gem_object_param *args,
struct drm_file *file,
struct drm_i915_gem_object *obj)
{
- struct intel_context *ce = dev_priv->engine[BCS0]->kernel_context;
u32 __user *uregions = u64_to_user_ptr(args->data);
u32 uregions_copy[INTEL_REGION_UNKNOWN];
int i, ret;
@@ -542,16 +547,28 @@ static int i915_gem_object_region_select(struct
drm_i915_private *dev_priv,
++uregions;
}
+ ret = i915_gem_object_migrate_region(obj, uregions_copy,
+args->size);
+
+ return ret;
+}
+
+int i915_gem_object_migrate_region(struct drm_i915_gem_object *obj,
+ u32 *regions, int size)
+{
+ struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
+ struct intel_context *ce = dev_priv->engine[BCS0]->kernel_context;
+ int i, ret;
+
mutex_lock(_priv->drm.struct_mutex);
ret = i915_gem_object_prepare_move(obj);
if (ret) {
DRM_ERROR("Cannot set memory region, object in use\n");
- goto err;
+ goto err;
}
- for (i = 0; i < args->size; i++) {
- u32 region = uregions_copy[i];
- enum intel_region_id id = __region_id(region);
+ for (i = 0; i < size; i++) {
+ enum intel_region_id id = __region_id(regions[i]);
if (id == INTEL_REGION_UNKNOWN) {
ret = -EINVAL;
@@ -561,7 +578,7 @@ static int i915_gem_object_region_select(struct
drm_i915_private *dev_priv,
ret = i915_gem_object_migrate(obj, ce, id);
if (!ret) {
if (!i915_gem_object_has_pages(obj) &&
- MEMORY_TYPE_FROM_REGION(region) ==
+ MEMORY_TYPE_FROM_REGION(regions[i]) ==
INTEL_MEMORY_LOCAL) {
/*
* TODO: this should be part of get_pages(),
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 87e6b6f18d91..6d8ca3f0ccf7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -47,6 +47,9 @@ int i915_gem_object_prepare_move(struct drm_i915_gem_object
*obj);
int i915_gem_object_migrate(struct drm_i915_gem_object *obj,
struct intel_context *ce,
enum intel_region_id id);
+bool
[Intel-gfx] [RFC v2 02/12] drm/i915/svm: Runtime (RT) allocator support
Shared Virtual Memory (SVM) runtime allocator support allows
binding a shared virtual address to a buffer object (BO) in the
device page table through an ioctl call.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/Kconfig | 11
drivers/gpu/drm/i915/Makefile | 3 +
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 58 ++
drivers/gpu/drm/i915/gem/i915_gem_svm.c | 60 +++
drivers/gpu/drm/i915/gem/i915_gem_svm.h | 22 +++
drivers/gpu/drm/i915/i915_drv.c | 21 +++
drivers/gpu/drm/i915/i915_drv.h | 22 +++
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 13
include/uapi/drm/i915_drm.h | 27 +
10 files changed, 227 insertions(+), 11 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_svm.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_svm.h
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index ba9595960bbe..c2e48710eec8 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -137,6 +137,16 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_SVM
+ bool "Enable Shared Virtual Memory support in i915"
+ depends on STAGING
+ depends on DRM_I915
+ default n
+ help
+ Choose this option if you want Shared Virtual Memory (SVM)
+ support in i915. With SVM support, one can share the virtual
+ address space between a process and the GPU.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e0fd10c0cfb8..75fe45633779 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -153,6 +153,9 @@ i915-y += \
intel_region_lmem.o \
intel_wopcm.o
+# SVM code
+i915-$(CONFIG_DRM_I915_SVM) += gem/i915_gem_svm.o
+
# general-purpose microcontroller (GuC) support
obj-y += gt/uc/
i915-y += gt/uc/intel_uc.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 5003e616a1ad..af360238a392 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2836,10 +2836,14 @@ int
i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
+ struct drm_i915_gem_exec_object2 *exec2_list, *exec2_list_user;
struct drm_i915_gem_execbuffer2 *args = data;
- struct drm_i915_gem_exec_object2 *exec2_list;
- struct drm_syncobj **fences = NULL;
const size_t count = args->buffer_count;
+ struct drm_syncobj **fences = NULL;
+ unsigned int i = 0, svm_count = 0;
+ struct i915_address_space *vm;
+ struct i915_gem_context *ctx;
+ struct i915_svm_obj *svm_obj;
int err;
if (!check_buffer_count(count)) {
@@ -2851,15 +2855,46 @@ i915_gem_execbuffer2_ioctl(struct drm_device *dev, void
*data,
if (err)
return err;
+ ctx = i915_gem_context_lookup(file->driver_priv, args->rsvd1);
+ if (!ctx || !rcu_access_pointer(ctx->vm))
+ return -ENOENT;
+
+ rcu_read_lock();
+ vm = i915_vm_get(ctx->vm);
+ rcu_read_unlock();
+
+alloc_again:
+ svm_count = vm->svm_count;
/* Allocate an extra slot for use by the command parser */
- exec2_list = kvmalloc_array(count + 1, eb_element_size(),
+ exec2_list = kvmalloc_array(count + svm_count + 1, eb_element_size(),
__GFP_NOWARN | GFP_KERNEL);
if (exec2_list == NULL) {
DRM_DEBUG("Failed to allocate exec list for %zd buffers\n",
- count);
+ count + svm_count);
return -ENOMEM;
}
- if (copy_from_user(exec2_list,
+ mutex_lock(>mutex);
+ if (svm_count != vm->svm_count) {
+ mutex_unlock(>mutex);
+ kvfree(exec2_list);
+ goto alloc_again;
+ }
+
+ list_for_each_entry(svm_obj, >svm_list, link) {
+ memset(_list[i], 0, sizeof(*exec2_list));
+ exec2_list[i].handle = svm_obj->handle;
+ exec2_list[i].offset = svm_obj->offset;
+ exec2_list[i].flags = EXEC_OBJECT_PINNED |
+ EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+ i++;
+ }
+ exec2_list_user = _list[i];
+ args->buffer_count += svm_count;
+ mutex_unlock(>mutex);
+ i915_vm_put(vm);
+ i915_gem_context_put(ctx);
+
+ if (copy_from_user(exec2_list_user,
[Intel-gfx] [RFC v2 04/12] drm/i915/svm: Page table update support for SVM
For Shared Virtual Memory (SVM) system (SYS) allocator, there is no
backing buffer object (BO). Add support to bind a VA to PA mapping
in the device page table.
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Vetter
Cc: Sudeep Dutt
Signed-off-by: Niranjana Vishwanathapura
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 60 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 10 +
2 files changed, 68 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7d4f5fa84b02..6657ff41dc3f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -195,6 +195,50 @@ static void ppgtt_unbind_vma(struct i915_vma *vma)
vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
}
+int svm_bind_addr_prepare(struct i915_address_space *vm, u64 start, u64 size)
+{
+ return vm->allocate_va_range(vm, start, size);
+}
+
+int svm_bind_addr_commit(struct i915_address_space *vm, u64 start, u64 size,
+u64 flags, struct sg_table *st, u32 sg_page_sizes)
+{
+ struct i915_vma vma = {0};
+ u32 pte_flags = 0;
+
+ /* use a vma wrapper */
+ vma.page_sizes.sg = sg_page_sizes;
+ vma.node.start = start;
+ vma.node.size = size;
+ vma.pages = st;
+ vma.vm = vm;
+
+ /* Applicable to VLV, and gen8+ */
+ if (flags & I915_GTT_SVM_READONLY)
+ pte_flags |= PTE_READ_ONLY;
+
+ vm->insert_entries(vm, , 0, pte_flags);
+ return 0;
+}
+
+int svm_bind_addr(struct i915_address_space *vm, u64 start, u64 size,
+ u64 flags, struct sg_table *st, u32 sg_page_sizes)
+{
+ int ret;
+
+ ret = svm_bind_addr_prepare(vm, start, size);
+ if (ret)
+ return ret;
+
+ return svm_bind_addr_commit(vm, start, size, flags, st, sg_page_sizes);
+}
+
+void svm_unbind_addr(struct i915_address_space *vm,
+u64 start, u64 size)
+{
+ vm->clear_range(vm, start, size);
+}
+
static int ppgtt_set_pages(struct i915_vma *vma)
{
GEM_BUG_ON(vma->pages);
@@ -985,11 +1029,21 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space
* const vm,
DBG("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d
}\n",
__func__, vm, lvl + 1, start, end,
idx, len, atomic_read(px_used(pd)));
- GEM_BUG_ON(!len || len >= atomic_read(px_used(pd)));
+ /*
+* FIXME: In SVM case, during mmu invalidation, we need to clear ppgtt,
+* but we don't know if the entry exist or not. So, we can't assume
+* that it is called only when the entry exist. revisit.
+* Also need to add the ebility to properly handle partial invalidations
+* by downgrading the large mappings.
+*/
+ GEM_BUG_ON(!len);
do {
struct i915_page_table *pt = pd->entry[idx];
+ if (!pt)
+ continue;
+
if (atomic_fetch_inc(>used) >> gen8_pd_shift(1) &&
gen8_pd_contains(start, end, lvl)) {
DBG("%s(%p):{ lvl:%d, idx:%d, start:%llx, end:%llx }
removing pd\n",
@@ -1012,7 +1066,9 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space *
const vm,
__func__, vm, lvl, start, end,
gen8_pd_index(start, 0), count,
atomic_read(>used));
- GEM_BUG_ON(!count || count >= atomic_read(>used));
+ GEM_BUG_ON(!count);
+ if (count > atomic_read(>used))
+ count = atomic_read(>used);
vaddr = kmap_atomic_px(pt);
memset64(vaddr + gen8_pd_index(start, 0),
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 7c1b54c9677d..8a8a314e1295 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -39,6 +39,7 @@
#include
#include
#include
+#include
#include
@@ -679,4 +680,13 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
#define PIN_OFFSET_MASK(-I915_GTT_PAGE_SIZE)
+/* SVM UAPI */
+#define I915_GTT_SVM_READONLY BIT(0)
+
+int svm_bind_addr_prepare(struct i915_address_space *vm, u64 start, u64 size);
+int svm_bind_addr_commit(struct i915_address_space *vm, u64 start, u64 size,
+u64 flags, struct sg_table *st, u32 sg_page_sizes);
+int svm_bind_addr(struct i915_address_space *vm, u64 start, u64 size,
+ u64 flags, struct sg_table *st, u32 sg_page_sizes);
+void svm_unbind_addr(struct i915_address_space *vm, u64 start, u64 size);
#endif
--
2.21.0.rc0.32.g243a4c7e27
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Use EAGAIN for trylock failures
== Series Details == Series: drm/i915: Use EAGAIN for trylock failures URL : https://patchwork.freedesktop.org/series/70891/ State : failure == Summary == Applying: drm/i915: Use EAGAIN for trylock failures Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gt/intel_timeline.c M drivers/gpu/drm/i915/i915_request.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_request.c No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/perf: Register sysctl path globally
== Series Details == Series: series starting with [1/2] drm/i915/perf: Register sysctl path globally URL : https://patchwork.freedesktop.org/series/70888/ State : failure == Summary == Applying: drm/i915/perf: Register sysctl path globally Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_pci.c M drivers/gpu/drm/i915/i915_perf.c M drivers/gpu/drm/i915/i915_perf.h M drivers/gpu/drm/i915/i915_perf_types.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_perf.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_perf.c Auto-merging drivers/gpu/drm/i915/i915_pci.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915/perf: Register sysctl path globally When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] drm/msm: Use dma_resv locking wrappers
On Fri, Dec 13, 2019 at 12:08 PM Daniel Vetter wrote:
>
> On Mon, Nov 25, 2019 at 10:43:55AM +0100, Daniel Vetter wrote:
> > I'll add more fancy logic to them soon, so everyone really has to use
> > them. Plus they already provide some nice additional debug
> > infrastructure on top of direct ww_mutex usage for the fences tracked
> > by dma_resv.
> >
> > Signed-off-by: Daniel Vetter
> > Cc: Rob Clark
> > Cc: Sean Paul
> > Cc: linux-arm-...@vger.kernel.org
> > Cc: freedr...@lists.freedesktop.org
>
> Ping for some review/acks.
>
> Thanks, Daniel
>
> > ---
> > drivers/gpu/drm/msm/msm_gem_submit.c | 10 +-
> > 1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
> > b/drivers/gpu/drm/msm/msm_gem_submit.c
> > index 7d04c47d0023..385d4965a8d0 100644
> > --- a/drivers/gpu/drm/msm/msm_gem_submit.c
> > +++ b/drivers/gpu/drm/msm/msm_gem_submit.c
> > @@ -157,7 +157,7 @@ static void submit_unlock_unpin_bo(struct
> > msm_gem_submit *submit,
> > msm_gem_unpin_iova(_obj->base, submit->aspace);
> >
> > if (submit->bos[i].flags & BO_LOCKED)
> > - ww_mutex_unlock(_obj->base.resv->lock);
> > + dma_resv_unlock(msm_obj->base.resv);
> >
> > if (backoff && !(submit->bos[i].flags & BO_VALID))
> > submit->bos[i].iova = 0;
> > @@ -180,8 +180,8 @@ static int submit_lock_objects(struct msm_gem_submit
> > *submit)
> > contended = i;
> >
> > if (!(submit->bos[i].flags & BO_LOCKED)) {
> > - ret =
> > ww_mutex_lock_interruptible(_obj->base.resv->lock,
> > - >ticket);
> > + ret = dma_resv_lock_interruptible(msm_obj->base.resv,
> > + >ticket);
> > if (ret)
> > goto fail;
> > submit->bos[i].flags |= BO_LOCKED;
> > @@ -202,8 +202,8 @@ static int submit_lock_objects(struct msm_gem_submit
> > *submit)
> > if (ret == -EDEADLK) {
> > struct msm_gem_object *msm_obj = submit->bos[contended].obj;
> > /* we lost out in a seqno race, lock and retry.. */
> > - ret =
> > ww_mutex_lock_slow_interruptible(_obj->base.resv->lock,
> > - >ticket);
> > + ret = dma_resv_lock_slow_interruptible(msm_obj->base.resv,
> > +>ticket);
> > if (!ret) {
> > submit->bos[contended].flags |= BO_LOCKED;
> > slow_locked = contended;
> > --
> > 2.24.0
> >
Reviewed-by: Eric Anholt
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Re: [Intel-gfx] [PATCH 4/4] drm/vc4: Use dma_resv locking wrappers
On Fri, Dec 13, 2019 at 12:10 PM Daniel Vetter wrote:
>
> On Mon, Nov 25, 2019 at 10:43:56AM +0100, Daniel Vetter wrote:
> > I'll add more fancy logic to them soon, so everyone really has to use
> > them. Plus they already provide some nice additional debug
> > infrastructure on top of direct ww_mutex usage for the fences tracked
> > by dma_resv.
> >
> > Signed-off-by: Daniel Vetter
>
> Ping for some review/acks.
>
> Thanks, Daniel
>
> > ---
> > drivers/gpu/drm/vc4/vc4_gem.c | 11 +--
> > 1 file changed, 5 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c
> > index 7a06cb6e31c5..e1cfc3ccd05a 100644
> > --- a/drivers/gpu/drm/vc4/vc4_gem.c
> > +++ b/drivers/gpu/drm/vc4/vc4_gem.c
> > @@ -568,7 +568,7 @@ vc4_unlock_bo_reservations(struct drm_device *dev,
> > for (i = 0; i < exec->bo_count; i++) {
> > struct drm_gem_object *bo = >bo[i]->base;
> >
> > - ww_mutex_unlock(>resv->lock);
> > + dma_resv_unlock(bo->resv);
> > }
> >
> > ww_acquire_fini(acquire_ctx);
> > @@ -595,8 +595,7 @@ vc4_lock_bo_reservations(struct drm_device *dev,
> > retry:
> > if (contended_lock != -1) {
> > bo = >bo[contended_lock]->base;
> > - ret = ww_mutex_lock_slow_interruptible(>resv->lock,
> > -acquire_ctx);
> > + ret = dma_resv_lock_slow_interruptible(bo->resv, acquire_ctx);
> > if (ret) {
> > ww_acquire_done(acquire_ctx);
> > return ret;
> > @@ -609,19 +608,19 @@ vc4_lock_bo_reservations(struct drm_device *dev,
> >
> > bo = >bo[i]->base;
> >
> > - ret = ww_mutex_lock_interruptible(>resv->lock,
> > acquire_ctx);
> > + ret = dma_resv_lock_interruptible(bo->resv, acquire_ctx);
> > if (ret) {
> > int j;
> >
> > for (j = 0; j < i; j++) {
> > bo = >bo[j]->base;
> > - ww_mutex_unlock(>resv->lock);
> > + dma_resv_unlock(bo->resv);
> > }
> >
> > if (contended_lock != -1 && contended_lock >= i) {
> > bo = >bo[contended_lock]->base;
> >
> > - ww_mutex_unlock(>resv->lock);
> > + dma_resv_unlock(bo->resv);
> > }
> >
> > if (ret == -EDEADLK) {
> > --
> > 2.24.0
> >
Assuming they're supposed to be exactly equivalent currently,
Acked-by: Eric Anholt
but we should really just be using drm_gem_lock_reservations()
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Re: [Intel-gfx] [PATCH v5 2/2] drm/i915/gt: Move power management debug files into a gt aware debugfs
Quoting Andi Shyti (2019-12-13 21:17:36)
> > > The GT system is becoming more and more a stand-alone system in
> > > i915 and it's fair to assign it its own debugfs directory.
> > >
> > > rc6, rps and llc debugfs files are gt related, move them into the
> > > gt debugfs directory.
> > >
> > > Signed-off-by: Andi Shyti
> > > ---
> > > drivers/gpu/drm/i915/Makefile | 2 +
> > > drivers/gpu/drm/i915/gt/intel_debugfs_gt.c | 23 +
> > > drivers/gpu/drm/i915/gt/intel_debugfs_gt.h | 27 +
> > > drivers/gpu/drm/i915/gt/intel_debugfs_pm.c | 623 +
> > > drivers/gpu/drm/i915/gt/intel_debugfs_pm.h | 16 +
> >
> > That's the worst of all worlds. debugfs is not a piece of intel hw.
>
> I don't see other way for having everything grouped by name. We
> can keep the previous patch (v4) with "debugfs_*", then.
>
> Is that fine? If so we can just ignore this version.
I had no objections, just a suggestion for gt-${CONFIG_DEBUGFS} :)
-Chris
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Re: [Intel-gfx] [RESEND PATCH v2] drm: Add getfb2 ioctl
On Thu, Oct 03, 2019 at 11:31:25AM -0700, Juston Li wrote:
> From: Daniel Stone
>
> getfb2 allows us to pass multiple planes and modifiers, just like addfb2
> over addfb.
>
> Changes since v1:
> - unused modifiers set to 0 instead of DRM_FORMAT_MOD_INVALID
> - update ioctl number
>
> Signed-off-by: Daniel Stone
> Signed-off-by: Juston Li
> ---
> drivers/gpu/drm/drm_crtc_internal.h | 2 +
> drivers/gpu/drm/drm_framebuffer.c | 110
> drivers/gpu/drm/drm_ioctl.c | 1 +
> include/uapi/drm/drm.h | 2 +
> 4 files changed, 115 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_crtc_internal.h
> b/drivers/gpu/drm/drm_crtc_internal.h
> index c7d5e4c21423..16f2413403aa 100644
> --- a/drivers/gpu/drm/drm_crtc_internal.h
> +++ b/drivers/gpu/drm/drm_crtc_internal.h
> @@ -216,6 +216,8 @@ int drm_mode_rmfb_ioctl(struct drm_device *dev,
> void *data, struct drm_file *file_priv);
> int drm_mode_getfb(struct drm_device *dev,
> void *data, struct drm_file *file_priv);
> +int drm_mode_getfb2_ioctl(struct drm_device *dev,
> + void *data, struct drm_file *file_priv);
> int drm_mode_dirtyfb_ioctl(struct drm_device *dev,
> void *data, struct drm_file *file_priv);
>
> diff --git a/drivers/gpu/drm/drm_framebuffer.c
> b/drivers/gpu/drm/drm_framebuffer.c
> index 57564318ceea..6db54f177443 100644
> --- a/drivers/gpu/drm/drm_framebuffer.c
> +++ b/drivers/gpu/drm/drm_framebuffer.c
> @@ -31,6 +31,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
>
> @@ -548,7 +549,116 @@ int drm_mode_getfb(struct drm_device *dev,
>
> out:
> drm_framebuffer_put(fb);
> + return ret;
> +}
> +
> +/**
> + * drm_mode_getfb2 - get extended FB info
> + * @dev: drm device for the ioctl
> + * @data: data pointer for the ioctl
> + * @file_priv: drm file for the ioctl call
> + *
> + * Lookup the FB given its ID and return info about it.
> + *
> + * Called by the user via ioctl.
> + *
> + * Returns:
> + * Zero on success, negative errno on failure.
> + */
> +int drm_mode_getfb2_ioctl(struct drm_device *dev,
> + void *data, struct drm_file *file_priv)
> +{
> + struct drm_mode_fb_cmd2 *r = data;
> + struct drm_framebuffer *fb;
> + unsigned int i;
> + int ret;
> +
> + if (!drm_core_check_feature(dev, DRIVER_MODESET))
> + return -EINVAL;
> +
> + fb = drm_framebuffer_lookup(dev, file_priv, r->fb_id);
> + if (!fb)
> + return -ENOENT;
> +
> + /* For multi-plane framebuffers, we require the driver to place the
> + * GEM objects directly in the drm_framebuffer. For single-plane
> + * framebuffers, we can fall back to create_handle.
> + */
> + if (!fb->obj[0] &&
> + (fb->format->num_planes > 1 || !fb->funcs->create_handle)) {
> + ret = -ENODEV;
> + goto out;
> + }
> +
> + r->height = fb->height;
> + r->width = fb->width;
> + r->pixel_format = fb->format->format;
> +
> + r->flags = 0;
> + if (dev->mode_config.allow_fb_modifiers)
> + r->flags |= DRM_MODE_FB_MODIFIERS;
> +
> + for (i = 0; i < ARRAY_SIZE(r->handles); i++) {
> + r->handles[i] = 0;
> + r->pitches[i] = 0;
> + r->offsets[i] = 0;
> + r->modifier[i] = 0;
> + }
>
> + for (i = 0; i < fb->format->num_planes; i++) {
> + int j;
> +
> + r->pitches[i] = fb->pitches[i];
> + r->offsets[i] = fb->offsets[i];
> + if (dev->mode_config.allow_fb_modifiers)
> + r->modifier[i] = fb->modifier;
> +
> + /* If we reuse the same object for multiple planes, also
> + * return the same handle.
> + */
> + for (j = 0; j < i; j++) {
> + if (fb->obj[i] == fb->obj[j]) {
> + r->handles[i] = r->handles[j];
> + break;
> + }
> + }
> +
> + if (r->handles[i])
> + continue;
> +
> + if (fb->obj[i]) {
> + ret = drm_gem_handle_create(file_priv, fb->obj[i],
> + >handles[i]);
> + } else {
> + WARN_ON(i > 0);
> + ret = fb->funcs->create_handle(fb, file_priv,
> +>handles[i]);
> + }
getfb1 doesn't allow non-master/root to see the handles. Here we don't
seem to have that same protection?
> +
> + if (ret != 0)
> + goto out;
Could be just 'break;' and then we wouldn't even need the label.
Rest lgtm.
> + }
> +
> +out:
> + if (ret != 0) {
> + /* Delete any previously-created handles on failure. */
> + for (i = 0; i <
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add device name to display tracepoints
== Series Details ==
Series: drm/i915: Add device name to display tracepoints
URL : https://patchwork.freedesktop.org/series/70886/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
78e6434185eb drm/i915: Add device name to display tracepoints
-:113: WARNING:LONG_LINE: line over 100 characters
#113: FILE: drivers/gpu/drm/i915/i915_trace.h:107:
+ __get_dev_name(dev), pipe_name(__entry->pipe),
__entry->frame, __entry->scanline,
-:129: WARNING:TABSTOP: Statements should start on a tabstop
#129: FILE: drivers/gpu/drm/i915/i915_trace.h:124:
+ struct intel_crtc *crtc =
intel_get_crtc_for_pipe(dev_priv, pipe);
-:130: WARNING:LINE_SPACING: Missing a blank line after declarations
#130: FILE: drivers/gpu/drm/i915/i915_trace.h:125:
+ struct intel_crtc *crtc =
intel_get_crtc_for_pipe(dev_priv, pipe);
+ __assign_dev_name_i915(dev, dev_priv);
-:218: WARNING:LONG_LINE: line over 100 characters
#218: FILE: drivers/gpu/drm/i915/i915_trace.h:234:
+ __get_dev_name(dev), pipe_name(__entry->pipe),
__entry->frame, __entry->scanline,
-:298: WARNING:LONG_LINE: line over 100 characters
#298: FILE: drivers/gpu/drm/i915/i915_trace.h:338:
+ TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u, "
DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
total: 0 errors, 5 warnings, 0 checks, 350 lines checked
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Re: [Intel-gfx] [PATCH 1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset
On Fri, Dec 13, 2019 at 01:05:48PM -0800, Manasi Navare wrote:
> On Fri, Dec 13, 2019 at 10:05:49PM +0200, Ville Syrjälä wrote:
> > On Wed, Dec 11, 2019 at 01:14:23PM -0800, Manasi Navare wrote:
> > > In case of tiled displays, all the tiles are linke dto each other
> > > for transcoder port sync. So in intel_atomic_check() we need to make
> > > sure that we add all the tiles to the modeset and if one of the
> > > tiles needs a full modeset then mark all other tiles for a full modeset.
> > >
> > > Suggested-by: Ville Syrjälä
> > > Cc: Ville Syrjälä
> > > Cc: José Roberto de Souza
> > > Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5
> > > Signed-off-by: Manasi Navare
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 78
> > > 1 file changed, 78 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 803993a01ca7..7263eaa66cda 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -14066,6 +14066,80 @@ static int intel_atomic_check_crtcs(struct
> > > intel_atomic_state *state)
> > > return 0;
> > > }
> > >
> > > +static int
> > > +intel_dp_modeset_all_tiles(struct drm_i915_private *dev_priv,
> > > +struct intel_atomic_state *state, int tile_grp_id)
> > > +{
> > > + struct drm_connector *conn_iter;
> > 'connector'
>
> Ok
>
> > > + struct drm_connector_list_iter conn_list_iter;
> > > + struct drm_crtc_state *crtc_state;
> >
> > crtc_state has needlessly wide scope.
>
> Ok will add it inside the loop
>
> >
> > > +
> > > + drm_connector_list_iter_begin(_priv->drm, _list_iter);
> > > + drm_for_each_connector_iter(conn_iter, _list_iter) {
> > > + struct drm_connector_state *conn_iter_state;
> >
> > 'conn_state' is the most popular name.
> >
> > > +
> > > + if (!conn_iter->has_tile)
> > > + continue;
> > > + conn_iter_state = drm_atomic_get_connector_state(>base,
> > > + conn_iter);
> > > + if (IS_ERR(conn_iter_state)) {
> > > + drm_connector_list_iter_end(_list_iter);
> > > + return PTR_ERR(conn_iter_state);
> > > + }
> > > +
> > > + if (!conn_iter_state->crtc)
> > > + continue;
> > > +
> > > + if (conn_iter->tile_group->id != tile_grp_id)
> > > + continue;
> >
> > The tile group check should be part of the same if with the has_tile
> > check.
>
> Ok yes. So not pass the tile grp id at all just compare with current
> connector's tile_grp_id ?
You still need to pass in the tile_grp_id from the caller's current
connector. What I meant is that you should do
if (!connector->has_tile || connector->tile_grp != tile_grp)
continue;
before you do the drm_atomic_get_connector_state(). We don't want to
needlessly add connectors belonging to some other tile group to our
atomic state.
>
> >
> > > +
> > > + crtc_state = drm_atomic_get_crtc_state(>base,
> > > conn_iter_state->crtc);
> > > + if (IS_ERR(crtc_state)) {
> > > + drm_connector_list_iter_end(_list_iter);
> > > + return PTR_ERR(conn_iter_state);
> > > + }
> > > + crtc_state->mode_changed = true;
> > > + }
> > > + drm_connector_list_iter_end(_list_iter);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int
> > > +intel_dp_atomic_trans_port_sync_check(struct drm_i915_private *dev_priv,
> >
> > Pointless variable. Can be extracted from the atomic state.
> >
> > > + struct intel_atomic_state *state)
> > > +{
> > > + struct drm_connector *connector;
> > > + struct drm_crtc_state *crtc_state;
> > > + struct drm_connector_state *connector_state;
> > > + int i, ret, tile_grp_id = 0;
> >
> > tile_grp_id is rather pointless. crtc_state and ret can move into
> > tighter scope. And the next suggestion allows you to kill crtc_state
> > entirely...
>
> tile_grp_id is useless because I should just use it from current connector
> obtained from state?
I just meant that you use that variable exactly once. So instead you can
just directly do:
ret = intel_dp_modeset_all_tiles(state, connector->tile_grp_id);
...
>
> >
> > > +
> > > + if (INTEL_GEN(dev_priv) < 11)
> > > + return 0;
> > > +
> > > + /* Is tiled, mark all other tiled CRTCs as needing a modeset */
> > > + for_each_new_connector_in_state(>base, connector,
> > > connector_state, i) {
> > > + if (!connector->has_tile)
> > > + continue;
> > > + if (connector_state->crtc &&
> > > + tile_grp_id != connector->tile_group->id) {
> > > + crtc_state = drm_atomic_get_new_crtc_state(>base,
> > > +
> > > connector_state->crtc);
> > > +
Re: [Intel-gfx] [PATCH v5 2/2] drm/i915/gt: Move power management debug files into a gt aware debugfs
> > The GT system is becoming more and more a stand-alone system in > > i915 and it's fair to assign it its own debugfs directory. > > > > rc6, rps and llc debugfs files are gt related, move them into the > > gt debugfs directory. > > > > Signed-off-by: Andi Shyti > > --- > > drivers/gpu/drm/i915/Makefile | 2 + > > drivers/gpu/drm/i915/gt/intel_debugfs_gt.c | 23 + > > drivers/gpu/drm/i915/gt/intel_debugfs_gt.h | 27 + > > drivers/gpu/drm/i915/gt/intel_debugfs_pm.c | 623 + > > drivers/gpu/drm/i915/gt/intel_debugfs_pm.h | 16 + > > That's the worst of all worlds. debugfs is not a piece of intel hw. I don't see other way for having everything grouped by name. We can keep the previous patch (v4) with "debugfs_*", then. Is that fine? If so we can just ignore this version. Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 2/2] drm/i915/gt: Move power management debug files into a gt aware debugfs
Quoting Andi Shyti (2019-12-13 21:00:50) > From: Andi Shyti > > The GT system is becoming more and more a stand-alone system in > i915 and it's fair to assign it its own debugfs directory. > > rc6, rps and llc debugfs files are gt related, move them into the > gt debugfs directory. > > Signed-off-by: Andi Shyti > --- > drivers/gpu/drm/i915/Makefile | 2 + > drivers/gpu/drm/i915/gt/intel_debugfs_gt.c | 23 + > drivers/gpu/drm/i915/gt/intel_debugfs_gt.h | 27 + > drivers/gpu/drm/i915/gt/intel_debugfs_pm.c | 623 + > drivers/gpu/drm/i915/gt/intel_debugfs_pm.h | 16 + That's the worst of all worlds. debugfs is not a piece of intel hw. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset
On Fri, Dec 13, 2019 at 10:05:49PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 11, 2019 at 01:14:23PM -0800, Manasi Navare wrote:
> > In case of tiled displays, all the tiles are linke dto each other
> > for transcoder port sync. So in intel_atomic_check() we need to make
> > sure that we add all the tiles to the modeset and if one of the
> > tiles needs a full modeset then mark all other tiles for a full modeset.
> >
> > Suggested-by: Ville Syrjälä
> > Cc: Ville Syrjälä
> > Cc: José Roberto de Souza
> > Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 78
> > 1 file changed, 78 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 803993a01ca7..7263eaa66cda 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14066,6 +14066,80 @@ static int intel_atomic_check_crtcs(struct
> > intel_atomic_state *state)
> > return 0;
> > }
> >
> > +static int
> > +intel_dp_modeset_all_tiles(struct drm_i915_private *dev_priv,
> > + struct intel_atomic_state *state, int tile_grp_id)
> > +{
> > + struct drm_connector *conn_iter;
> 'connector'
Ok
> > + struct drm_connector_list_iter conn_list_iter;
> > + struct drm_crtc_state *crtc_state;
>
> crtc_state has needlessly wide scope.
Ok will add it inside the loop
>
> > +
> > + drm_connector_list_iter_begin(_priv->drm, _list_iter);
> > + drm_for_each_connector_iter(conn_iter, _list_iter) {
> > + struct drm_connector_state *conn_iter_state;
>
> 'conn_state' is the most popular name.
>
> > +
> > + if (!conn_iter->has_tile)
> > + continue;
> > + conn_iter_state = drm_atomic_get_connector_state(>base,
> > +conn_iter);
> > + if (IS_ERR(conn_iter_state)) {
> > + drm_connector_list_iter_end(_list_iter);
> > + return PTR_ERR(conn_iter_state);
> > + }
> > +
> > + if (!conn_iter_state->crtc)
> > + continue;
> > +
> > + if (conn_iter->tile_group->id != tile_grp_id)
> > + continue;
>
> The tile group check should be part of the same if with the has_tile
> check.
Ok yes. So not pass the tile grp id at all just compare with current
connector's tile_grp_id ?
>
> > +
> > + crtc_state = drm_atomic_get_crtc_state(>base,
> > conn_iter_state->crtc);
> > + if (IS_ERR(crtc_state)) {
> > + drm_connector_list_iter_end(_list_iter);
> > + return PTR_ERR(conn_iter_state);
> > + }
> > + crtc_state->mode_changed = true;
> > + }
> > + drm_connector_list_iter_end(_list_iter);
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +intel_dp_atomic_trans_port_sync_check(struct drm_i915_private *dev_priv,
>
> Pointless variable. Can be extracted from the atomic state.
>
> > + struct intel_atomic_state *state)
> > +{
> > + struct drm_connector *connector;
> > + struct drm_crtc_state *crtc_state;
> > + struct drm_connector_state *connector_state;
> > + int i, ret, tile_grp_id = 0;
>
> tile_grp_id is rather pointless. crtc_state and ret can move into
> tighter scope. And the next suggestion allows you to kill crtc_state
> entirely...
tile_grp_id is useless because I should just use it from current connector
obtained from state?
>
> > +
> > + if (INTEL_GEN(dev_priv) < 11)
> > + return 0;
> > +
> > + /* Is tiled, mark all other tiled CRTCs as needing a modeset */
> > + for_each_new_connector_in_state(>base, connector,
> > connector_state, i) {
> > + if (!connector->has_tile)
> > + continue;
> > + if (connector_state->crtc &&
> > + tile_grp_id != connector->tile_group->id) {
> > + crtc_state = drm_atomic_get_new_crtc_state(>base,
> > +
> > connector_state->crtc);
> > + if (!drm_atomic_crtc_needs_modeset(crtc_state))
> > + continue;
>
> This should to be able to be shortened to just
> intel_connector_needs_modeset().
Ok will use that instead.
>
> > +
> > + tile_grp_id = connector->tile_group->id;
> > + } else
> > + continue;
> > +
> > + ret = intel_dp_modeset_all_tiles(dev_priv, state, tile_grp_id);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > /**
> > * intel_atomic_check - validate state object
> > * @dev: drm device
> > @@ -14093,6 +14167,10 @@ static int intel_atomic_check(struct drm_device
> > *dev,
> > if (ret)
>
[Intel-gfx] [PATCH v5 0/2] Some debugfs enhancements
From: Andi Shyti Hi, this two patches are few debugfs improvements. The first adds some helpers for reading the GT frequency, while the second patch moves all the power management debufs functions into gt/ Thanks Chris and Michal for the reviews. Thanks, Andi Changelog: == v4-v5: (v4: https://lists.freedesktop.org/archives/intel-gfx/2019-December/223431.html) - renamed files: renamed:drivers/gpu/drm/i915/gt/debugfs_gt.c -> drivers/gpu/drm/i915/gt/intel_debugfs_gt.c renamed:drivers/gpu/drm/i915/gt/debugfs_gt.h -> drivers/gpu/drm/i915/gt/intel_debugfs_gt.h renamed:drivers/gpu/drm/i915/gt/debugfs_pm.c -> drivers/gpu/drm/i915/gt/intel_debugfs_pm.c renamed:drivers/gpu/drm/i915/gt/debugfs_pm.h -> drivers/gpu/drm/i915/gt/intel_debugfs_pm.h - change the spdx identifier's comment from the /* */ to the // style. v3-v4: (v3: https://lists.freedesktop.org/archives/intel-gfx/2019-December/223368.html) - added wakeref in frequency reading (patch 1) - added Chris reviewed-by in patch 1 - sorted in alphabetical order the debugfs functions - removed dentry reference in the gt structure, because it's useless. v2-v3: (v2: https://lists.freedesktop.org/archives/intel-gfx/2019-December/223277.html) Fixed the three reviews from Chris - removed the 'i915' prefix from the gt pm debugfs files - fixed my laziness and made the debugfs pm files more gt oriented. Now the only dependency remaining from the 'drm_i915_private' structure is for platform generation check. - restored the 'node_to_i915' to its original position, as it's not needed anymore. v1-v2: (v1: https://lists.freedesktop.org/archives/intel-gfx/2019-December/222758.html) - renamed functions from intel_cagf_freq_read to intel_rps_read_actual_frequency intel_cagf_read to intel_rps_read_cagf - created an independent gt/ directory in debugfs Andi Shyti (2): drm/i915/rps: Add frequency translation helpers drm/i915/gt: Move power management debug files into a gt aware debugfs drivers/gpu/drm/i915/Makefile | 2 + drivers/gpu/drm/i915/gt/intel_debugfs_gt.c | 23 + drivers/gpu/drm/i915/gt/intel_debugfs_gt.h | 27 + drivers/gpu/drm/i915/gt/intel_debugfs_pm.c | 623 + drivers/gpu/drm/i915/gt/intel_debugfs_pm.h | 16 + drivers/gpu/drm/i915/gt/intel_rps.c| 30 + drivers/gpu/drm/i915/gt/intel_rps.h| 2 + drivers/gpu/drm/i915/i915_debugfs.c| 590 +-- drivers/gpu/drm/i915/i915_sysfs.c | 14 +- 9 files changed, 734 insertions(+), 593 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_debugfs_gt.c create mode 100644 drivers/gpu/drm/i915/gt/intel_debugfs_gt.h create mode 100644 drivers/gpu/drm/i915/gt/intel_debugfs_pm.c create mode 100644 drivers/gpu/drm/i915/gt/intel_debugfs_pm.h -- 2.24.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 2/2] drm/i915/gt: Move power management debug files into a gt aware debugfs
From: Andi Shyti
The GT system is becoming more and more a stand-alone system in
i915 and it's fair to assign it its own debugfs directory.
rc6, rps and llc debugfs files are gt related, move them into the
gt debugfs directory.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/gt/intel_debugfs_gt.c | 23 +
drivers/gpu/drm/i915/gt/intel_debugfs_gt.h | 27 +
drivers/gpu/drm/i915/gt/intel_debugfs_pm.c | 623 +
drivers/gpu/drm/i915/gt/intel_debugfs_pm.h | 16 +
drivers/gpu/drm/i915/i915_debugfs.c| 579 +--
6 files changed, 700 insertions(+), 570 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_debugfs_gt.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_debugfs_gt.h
create mode 100644 drivers/gpu/drm/i915/gt/intel_debugfs_pm.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_debugfs_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e0fd10c0cfb8..61e4102ea626 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -77,6 +77,8 @@ obj-y += gt/
gt-y += \
gt/intel_breadcrumbs.o \
gt/intel_context.o \
+ gt/intel_debugfs_gt.o \
+ gt/intel_debugfs_pm.o \
gt/intel_engine_cs.o \
gt/intel_engine_heartbeat.o \
gt/intel_engine_pm.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_debugfs_gt.c
b/drivers/gpu/drm/i915/gt/intel_debugfs_gt.c
new file mode 100644
index ..f866a3bc4aa9
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_debugfs_gt.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: MIT
+
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_trace.h"
+#include "intel_debugfs_pm.h"
+
+int debugfs_gt_init(struct intel_gt *gt)
+{
+ struct dentry *debugfs_root = gt->i915->drm.primary->debugfs_root;
+ struct dentry *gt_root;
+
+ if (!debugfs_root)
+ return -ENODEV;
+
+ gt_root = debugfs_create_dir("gt", debugfs_root);
+ if (IS_ERR(gt_root))
+ return PTR_ERR(gt_root);
+
+ return intel_gt_pm_debugfs_register(gt, gt_root);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_debugfs_gt.h
b/drivers/gpu/drm/i915/gt/intel_debugfs_gt.h
new file mode 100644
index ..31e6b4b5861e
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_debugfs_gt.h
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: MIT
+
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef DEBUGFS_GT
+#define DEBUGFS_GT
+
+#include "intel_gt_types.h"
+
+#define DEFINE_GT_DEBUGFS_ATTRIBUTE(__name)\
+static int __name ## _open(struct inode *inode, struct file *file) \
+{ \
+ return single_open(file, __name ## _show, inode->i_private);\
+} \
+static const struct file_operations __name ## _fops = {
\
+ .owner = THIS_MODULE, \
+ .open = __name ## _open,\
+ .read = seq_read, \
+ .llseek = seq_lseek,\
+ .release = single_release, \
+}
+
+int debugfs_gt_init(struct intel_gt *gt);
+
+#endif /* DEBUGFS_GT */
diff --git a/drivers/gpu/drm/i915/gt/intel_debugfs_pm.c
b/drivers/gpu/drm/i915/gt/intel_debugfs_pm.c
new file mode 100644
index ..3248b041bb53
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_debugfs_pm.c
@@ -0,0 +1,623 @@
+// SPDX-License-Identifier: MIT
+
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_debugfs.h"
+#include "i915_trace.h"
+#include "intel_debugfs_pm.h"
+#include "intel_debugfs_gt.h"
+#include "intel_rc6.h"
+#include "intel_rps.h"
+#include "intel_sideband.h"
+
+static int forcewake_domains_show(struct seq_file *m, void *data)
+{
+ struct intel_gt *gt = m->private;
+ struct intel_uncore *uncore = gt->uncore;
+ struct intel_uncore_forcewake_domain *fw_domain;
+ unsigned int tmp;
+
+ seq_printf(m, "user.bypass_count = %u\n",
+ uncore->user_forcewake_count);
+
+ for_each_fw_domain(fw_domain, uncore, tmp)
+ seq_printf(m, "%s.wake_count = %u\n",
+ intel_uncore_forcewake_domain_to_str(fw_domain->id),
+ READ_ONCE(fw_domain->wake_count));
+
+ return 0;
+}
+DEFINE_GT_DEBUGFS_ATTRIBUTE(forcewake_domains);
+
+static void print_rc6_res(struct seq_file *m,
+ const char *title,
+ const i915_reg_t reg)
+{
+ struct intel_gt *gt = m->private;
+ intel_wakeref_t wakeref;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ seq_printf(m, "%s %u (%llu us)\n", title,
+
Re: [Intel-gfx] [PATCH 2/3] drm/i915/dp: Make port sync mode assignments only if all tiles present
On Fri, Dec 13, 2019 at 10:28:49PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 11, 2019 at 01:14:24PM -0800, Manasi Navare wrote:
> > Add an extra check before making master slave assignments for tiled
> > displays to make sure we make these assignments only if all tiled
> > connectors are present. If not then initialize the state to defaults
> > so it does a normal non tiled modeset without transcoder port sync.
> >
> > Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5
> > Cc: Ville Syrjälä
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 28 ++--
> > 1 file changed, 26 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 7263eaa66cda..c0a2dab3fe67 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -12048,6 +12048,12 @@ static bool c8_planes_changed(const struct
> > intel_crtc_state *new_crtc_state)
> > return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
> > }
> >
> > +static void initialize_trans_port_sync_mode_state(struct intel_crtc_state
> > *crtc_state)
> > +{
> > + crtc_state->master_transcoder = INVALID_TRANSCODER;
> > + crtc_state->sync_mode_slaves_mask = 0;
> > +}
> > +
> > static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
> > {
> > struct drm_crtc *crtc = crtc_state->uapi.crtc;
> > @@ -12059,11 +12065,22 @@ static int icl_add_sync_mode_crtcs(struct
> > intel_crtc_state *crtc_state)
> > struct drm_crtc *master_crtc = NULL;
> > struct drm_crtc_state *master_crtc_state;
> > struct intel_crtc_state *master_pipe_config;
> > - int i, tile_group_id;
> > + int i, tile_group_id = 0, num_tiled_conns = 0;
> >
> > if (INTEL_GEN(dev_priv) < 11)
> > return 0;
> >
> > + /* If all tiles not present do not make master slave assignments
> > +* Here we assume all tiles belong to the same tile group for now.
> > +*/
> > + for_each_new_connector_in_state(>base, connector,
> > connector_state, i) {
> > + if (connector->has_tile) {
> > + if (!tile_group_id)
> > + tile_group_id = connector->tile_group->id;
>
> Isn't 0 a valid tile group id?
>
> > + num_tiled_conns++;
> > + }
>
> This whole thing looks confused. Should it not just look for the same
> tile group as what the current connector belongs to?
I was making sure that we dont count the connectors that dont belong to the
same tile grp id.
But yes I agree that the tile grp id can be assigned by current connector's
tile grp id
and add num_conns only if they are of the same tile grp id.
>
> > + }
> > +
> > /*
> > * In case of tiled displays there could be one or more slaves but
> > there is
> > * only one master. Lets make the CRTC used by the connector
> > corresponding
> > @@ -12077,8 +12094,15 @@ static int icl_add_sync_mode_crtcs(struct
> > intel_crtc_state *crtc_state)
> > if (!connector->has_tile)
> > continue;
> > if (crtc_state->hw.mode.hdisplay != connector->tile_h_size ||
> > - crtc_state->hw.mode.vdisplay != connector->tile_v_size)
> > + crtc_state->hw.mode.vdisplay != connector->tile_v_size) {
> > + initialize_trans_port_sync_mode_state(crtc_state);
> > return 0;
> > + }
> > + if (connector->tile_group->id == tile_group_id &&
> > + num_tiled_conns < connector->num_h_tile *
> > connector->num_v_tile) {
> > + initialize_trans_port_sync_mode_state(crtc_state);
> > + return 0;
> > + }
> > if (connector->tile_h_loc == connector->num_h_tile - 1 &&
> > connector->tile_v_loc == connector->num_v_tile - 1)
> > continue;
>
> This whole thing seems kinda overly complicated. I suggest it should
> just blindly go through all connectors of the same tile group and pick
> the lowest transcoder as the master, which is the logic Jose is using
> for MST. Except I guess we have to special case the EDP transcoder
> for port sync since it can't be a slave. So a simple numeric comparison
> won't quite do like used for MST.
>
> And then we should probably move this thing to the encoder
> .compute_config(). I suppose it should look in the end something like:
>
> compute_config() {
> ...
> crtc_state->master = compute_master_transcoder();
> crtc_state->slaves = 0;
> if (master_transcoder == cpu_transcoder)
> crtc_state->master = INVALID;
> crtc_state->slave = compute_slave_transcoders();
> }
> }
>
> That keeps it very readable and avoids the confusing stuff of
> comptue_config() for one pipe randomly mutating the states of
> the
Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/gt: Move power management debug files into a gt aware debugfs
Hi Michal, > > @@ -75,6 +75,8 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o > > # "Graphics Technology" (aka we talk to the gpu) > > obj-y += gt/ > > gt-y += \ > > + gt/debugfs_gt.o \ > > + gt/debugfs_pm.o \ > > hm, maybe this should be: > gt/intel_gt_debugfs.o > and > gt/intel_pm_debugfs.o this was actually the name I wanted to give it originally, but meantime I also wanted to have the debugfs files alphabetically sorted in sequence, like the selftest_* files (I can imagine in the future having more debugfs files). Maybe intel_debugfs_gt.c/intel_debugfs_pm.c would be a good compromise? > > @@ -0,0 +1,22 @@ > > +/* SPDX-License-Identifier: MIT */ > > in .c SPDX shall start with // I agree this is the "official" way of doing it, and I also read some discussions about it in this mailing list. But however I do it, I know someone won't like it. I checked the style in this directory and tried to keep it conform to the "gt way". If no one will reject it because of it, I will send a v5 with '//'. Thanks for the review, Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 rebased 07/11] drm/i915/tgl: Select master transcoder for MST stream
On Thu, Dec 12, 2019 at 10:44:29PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 11, 2019 at 10:45:22AM -0800, José Roberto de Souza wrote:
> > On TGL the blending of all the streams have moved from DDI to
> > transcoder, so now every transcoder working over the same MST port must
> > send its stream to a master transcoder and master will send to DDI
> > respecting the time slots.
> >
> > So here adding all the CRTCs that shares the same MST stream if
> > needed and computing their state again, it will pick the lowest
> > pipe/transcoder among the ones in the same stream to be master.
> >
> > Most of the time skl_commit_modeset_enables() enables pipes in a
> > crescent order but due DDB overlapping it might not happen, this
> > scenarios will be handled in the next patch.
> >
> > v2:
> > - Using recently added intel_crtc_state_reset() to set
> > mst_master_transcoder to invalid transcoder for all non gen12 & MST
> > code paths
> > - Setting lowest pipe/transcoder as master, previously it was the
> > first one but setting a predictable one will help in future MST e
> > port sync integration
> > - Moving to intel type as much as we can
> >
> > BSpec: 50493
> > BSpec: 49190
> > Cc: Ville Syrjälä
> > Cc: Lucas De Marchi
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/display/intel_atomic.c | 14 ++
> > drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
> > drivers/gpu/drm/i915/display/intel_ddi.c | 14 +-
> > drivers/gpu/drm/i915/display/intel_display.c | 13 +-
> > .../drm/i915/display/intel_display_types.h| 3 +
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 139 --
> > drivers/gpu/drm/i915/display/intel_dp_mst.h | 5 +
> > 7 files changed, 178 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> > b/drivers/gpu/drm/i915/display/intel_atomic.c
> > index 6e93a39a6fec..69a0430c4638 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > @@ -206,6 +206,20 @@ intel_digital_connector_needs_modeset(struct
> > intel_atomic_state *state,
> >(new_crtc &&
> > drm_atomic_crtc_needs_modeset(_crtc_state->uapi));
> > }
> >
> > +struct intel_digital_connector_state *
> > +intel_atomic_get_digital_connector_state(struct intel_atomic_state *state,
> > +struct intel_connector *connector)
> > +{
> > + struct drm_connector_state *connector_state;
> > +
> > + connector_state = drm_atomic_get_connector_state(>base,
> > +>base);
> > + if (IS_ERR(connector_state))
> > + return ERR_CAST(connector_state);
> > +
> > + return to_intel_digital_connector_state(connector_state);
> > +}
> > +
> > /**
> > * intel_crtc_duplicate_state - duplicate crtc state
> > * @crtc: drm crtc
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
> > b/drivers/gpu/drm/i915/display/intel_atomic.h
> > index ba9cc29a5865..6e8638d83d28 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> > @@ -35,6 +35,9 @@ struct drm_connector_state *
> > intel_digital_connector_duplicate_state(struct drm_connector *connector);
> > bool intel_digital_connector_needs_modeset(struct intel_atomic_state
> > *state,
> >struct intel_connector *connector);
> > +struct intel_digital_connector_state *
> > +intel_atomic_get_digital_connector_state(struct intel_atomic_state *state,
> > +struct intel_connector *connector);
> >
> > struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
> > void intel_crtc_destroy_state(struct drm_crtc *crtc,
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 5b6f32517c75..6ee5230045eb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1903,8 +1903,13 @@ intel_ddi_transcoder_func_reg_val_get(const struct
> > intel_crtc_state *crtc_state)
> > temp |= TRANS_DDI_MODE_SELECT_DP_MST;
> > temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> >
> > - if (INTEL_GEN(dev_priv) >= 12)
> > - temp |=
> > TRANS_DDI_MST_TRANSPORT_SELECT(crtc_state->cpu_transcoder);
> > + if (INTEL_GEN(dev_priv) >= 12) {
> > + enum transcoder master;
> > +
> > + master = crtc_state->mst_master_transcoder;
> > + WARN_ON(master == INVALID_TRANSCODER);
> > + temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
> > + }
> > } else {
> > temp |= TRANS_DDI_MODE_SELECT_DP_SST;
> > temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> > @@ -4377,6 +4382,11 @@ void intel_ddi_get_config(struct intel_encoder
> > *encoder,
> >
Re: [Intel-gfx] [PATCH 2/3] drm/i915/dp: Make port sync mode assignments only if all tiles present
On Fri, Dec 13, 2019 at 10:28:49PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 11, 2019 at 01:14:24PM -0800, Manasi Navare wrote:
> > Add an extra check before making master slave assignments for tiled
> > displays to make sure we make these assignments only if all tiled
> > connectors are present. If not then initialize the state to defaults
> > so it does a normal non tiled modeset without transcoder port sync.
> >
> > Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5
> > Cc: Ville Syrjälä
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 28 ++--
> > 1 file changed, 26 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 7263eaa66cda..c0a2dab3fe67 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -12048,6 +12048,12 @@ static bool c8_planes_changed(const struct
> > intel_crtc_state *new_crtc_state)
> > return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
> > }
> >
> > +static void initialize_trans_port_sync_mode_state(struct intel_crtc_state
> > *crtc_state)
> > +{
> > + crtc_state->master_transcoder = INVALID_TRANSCODER;
> > + crtc_state->sync_mode_slaves_mask = 0;
> > +}
> > +
> > static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
> > {
> > struct drm_crtc *crtc = crtc_state->uapi.crtc;
> > @@ -12059,11 +12065,22 @@ static int icl_add_sync_mode_crtcs(struct
> > intel_crtc_state *crtc_state)
> > struct drm_crtc *master_crtc = NULL;
> > struct drm_crtc_state *master_crtc_state;
> > struct intel_crtc_state *master_pipe_config;
> > - int i, tile_group_id;
> > + int i, tile_group_id = 0, num_tiled_conns = 0;
> >
> > if (INTEL_GEN(dev_priv) < 11)
> > return 0;
> >
> > + /* If all tiles not present do not make master slave assignments
> > +* Here we assume all tiles belong to the same tile group for now.
> > +*/
> > + for_each_new_connector_in_state(>base, connector,
> > connector_state, i) {
> > + if (connector->has_tile) {
> > + if (!tile_group_id)
> > + tile_group_id = connector->tile_group->id;
>
> Isn't 0 a valid tile group id?
>
> > + num_tiled_conns++;
> > + }
>
> This whole thing looks confused. Should it not just look for the same
> tile group as what the current connector belongs to?
>
> > + }
> > +
> > /*
> > * In case of tiled displays there could be one or more slaves but
> > there is
> > * only one master. Lets make the CRTC used by the connector
> > corresponding
> > @@ -12077,8 +12094,15 @@ static int icl_add_sync_mode_crtcs(struct
> > intel_crtc_state *crtc_state)
> > if (!connector->has_tile)
> > continue;
> > if (crtc_state->hw.mode.hdisplay != connector->tile_h_size ||
> > - crtc_state->hw.mode.vdisplay != connector->tile_v_size)
> > + crtc_state->hw.mode.vdisplay != connector->tile_v_size) {
> > + initialize_trans_port_sync_mode_state(crtc_state);
> > return 0;
> > + }
> > + if (connector->tile_group->id == tile_group_id &&
> > + num_tiled_conns < connector->num_h_tile *
> > connector->num_v_tile) {
> > + initialize_trans_port_sync_mode_state(crtc_state);
> > + return 0;
> > + }
> > if (connector->tile_h_loc == connector->num_h_tile - 1 &&
> > connector->tile_v_loc == connector->num_v_tile - 1)
> > continue;
>
> This whole thing seems kinda overly complicated. I suggest it should
> just blindly go through all connectors of the same tile group and pick
> the lowest transcoder as the master, which is the logic Jose is using
> for MST. Except I guess we have to special case the EDP transcoder
> for port sync since it can't be a slave. So a simple numeric comparison
> won't quite do like used for MST.
Hmm. Except that won't actually work since .cpu_transcoder won't have
been populated yet for the later pipes. So we can't use that in
.compute_config(). So either we do this after .compute_config()
is done for everyone or we just calculate the cpu_transcoder on the
spot (I mean it's just a trivial port==A->EDP else->pipe so no big deal).
>
> And then we should probably move this thing to the encoder
> .compute_config(). I suppose it should look in the end something like:
>
> compute_config() {
> ...
> crtc_state->master = compute_master_transcoder();
> crtc_state->slaves = 0;
> if (master_transcoder == cpu_transcoder)
> crtc_state->master = INVALID;
> crtc_state->slave = compute_slave_transcoders();
> }
> }
>
> That keeps it very readable and avoids
Re: [Intel-gfx] [PATCH 1/4] drm/etnaviv: Use dma_resv locking wrappers
>-Original Message-
>From: dri-devel On Behalf Of
>Daniel Vetter
>Sent: Friday, December 13, 2019 3:08 PM
>To: DRI Development
>Cc: Daniel Vetter ; Intel Graphics Development
>; etna...@lists.freedesktop.org; Russell
>King ; Vetter, Daniel
>
>Subject: Re: [PATCH 1/4] drm/etnaviv: Use dma_resv locking wrappers
>
>On Mon, Nov 25, 2019 at 10:43:53AM +0100, Daniel Vetter wrote:
>> I'll add more fancy logic to them soon, so everyone really has to use
>> them. Plus they already provide some nice additional debug
>> infrastructure on top of direct ww_mutex usage for the fences tracked
>> by dma_resv.
>>
>> Signed-off-by: Daniel Vetter
>> Cc: Lucas Stach
>> Cc: Russell King
>> Cc: Christian Gmeiner
>> Cc: etna...@lists.freedesktop.org
>
>Ping for some review/acks.
>
>Thanks, Daniel
>
>> ---
>> drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 8 +++-
>> 1 file changed, 3 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
>b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
>> index aa3e4c3b063a..947b21868e72 100644
>> --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
>> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
>> @@ -113,7 +113,7 @@ static void submit_unlock_object(struct
>etnaviv_gem_submit *submit, int i)
>> if (submit->bos[i].flags & BO_LOCKED) {
>> struct drm_gem_object *obj = >bos[i].obj->base;
>>
>> -ww_mutex_unlock(>resv->lock);
>> +dma_resv_unlock(obj->resv);
>> submit->bos[i].flags &= ~BO_LOCKED;
>> }
>> }
>> @@ -133,8 +133,7 @@ static int submit_lock_objects(struct
>etnaviv_gem_submit *submit,
>> contended = i;
>>
>> if (!(submit->bos[i].flags & BO_LOCKED)) {
>> -ret = ww_mutex_lock_interruptible(>resv-
>>lock,
>> - ticket);
>> +ret = dma_resv_lock(obj->resv, ticket);
Should this be dma_resv_lock_interruptible()?
Mike
>> if (ret == -EALREADY)
>> DRM_ERROR("BO at index %u already on
>submit list\n",
>>i);
>> @@ -161,8 +160,7 @@ static int submit_lock_objects(struct
>etnaviv_gem_submit *submit,
>> obj = >bos[contended].obj->base;
>>
>> /* we lost out in a seqno race, lock and retry.. */
>> -ret = ww_mutex_lock_slow_interruptible(>resv->lock,
>> - ticket);
>> +ret = dma_resv_lock_slow_interruptible(obj->resv, ticket);
>> if (!ret) {
>> submit->bos[contended].flags |= BO_LOCKED;
>> slow_locked = contended;
>> --
>> 2.24.0
>>
>
>--
>Daniel Vetter
>Software Engineer, Intel Corporation
>http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/dp: Disable Port sync mode correctly on teardown
On Fri, Dec 13, 2019 at 12:40:13PM -0800, Manasi Navare wrote:
> On Fri, Dec 13, 2019 at 10:06:37PM +0200, Ville Syrjälä wrote:
> > On Wed, Dec 11, 2019 at 01:14:25PM -0800, Manasi Navare wrote:
> > > While clearing the Ports ync mode enable and master select bits
> > > we need to make sure that we perform a RMW for disable else
> > > it sets the other bits casuing unwanted sideeffects.
> > >
> > > Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5
> > > Cc: Ville Syrjälä
> > > Cc: Jani Nikula
> > > Fixes: 51528afe7c5e ("drm/i915/display/icl: Disable transcoder port sync
> > > as part of crtc_disable() sequence")
> > > Signed-off-by: Manasi Navare
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
> > > 1 file changed, 2 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index c0a2dab3fe67..3fccda0f1f36 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -4599,7 +4599,8 @@ static void icl_disable_transcoder_port_sync(const
> > > struct intel_crtc_state *old_
> > > transcoder_name(old_crtc_state->cpu_transcoder));
> > >
> > > reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
> > > - trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
> > > + trans_ddi_func_ctl2_val = I915_READ(reg);
> > > + trans_ddi_func_ctl2_val &= ~(PORT_SYNC_MODE_ENABLE |
> > > PORT_SYNC_MODE_MASTER_SELECT_MASK);
> > > I915_WRITE(reg, trans_ddi_func_ctl2_val);
> >
> > I915_WRITE(TRANS_DDI_FUNC_CTL2, 0);
>
> So not even consider the other values that might have been set in this reg?
> You would prefer setting this to 0 directly?
> Right now i do see that no other bits are set, but things can change when we
> start using DSI port sync mode or genlock mode etc.
No point in making it more complicated than it has to be.
In fact after the series I just posted we should probably just
suck this whole thing into intel_ddi_{enable,disable}_transcoder_func()
since on older platforms these bits live in TRANS_DDI_FUNC_CTL itself.
>
> Manasi
>
> >
> > > }
> > > --
> > > 2.19.1
> >
> > --
> > Ville Syrjälä
> > Intel
--
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm: Handle connector tile support only for modes that match tile size
== Series Details == Series: series starting with [1/2] drm: Handle connector tile support only for modes that match tile size URL : https://patchwork.freedesktop.org/series/70790/ State : success == Summary == CI Bug Log - changes from CI_DRM_7545_full -> Patchwork_15701_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15701_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@extended-parallel-vcs1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-iclb2/igt@gem_b...@extended-parallel-vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15701/shard-iclb6/igt@gem_b...@extended-parallel-vcs1.html * igt@gem_ctx_persistence@vcs1-hostile-preempt: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-iclb1/igt@gem_ctx_persiste...@vcs1-hostile-preempt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15701/shard-iclb6/igt@gem_ctx_persiste...@vcs1-hostile-preempt.html * igt@gem_eio@reset-stress: - shard-snb: [PASS][5] -> [FAIL][6] ([i915#232]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-snb2/igt@gem_...@reset-stress.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15701/shard-snb2/igt@gem_...@reset-stress.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-iclb6/igt@gem_exec_sched...@preempt-other-chain-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15701/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +6 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-iclb2/igt@gem_exec_sched...@preempt-queue-bsd1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15701/shard-iclb6/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_exec_suspend@basic-s3: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-kbl2/igt@gem_exec_susp...@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15701/shard-kbl7/igt@gem_exec_susp...@basic-s3.html * igt@gem_persistent_relocs@forked-faulting-reloc-thrashing: - shard-iclb: [PASS][13] -> [TIMEOUT][14] ([i915#530]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-iclb8/igt@gem_persistent_rel...@forked-faulting-reloc-thrashing.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15701/shard-iclb8/igt@gem_persistent_rel...@forked-faulting-reloc-thrashing.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-tglb: [PASS][15] -> [TIMEOUT][16] ([fdo#112126] / [i915#530]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-tglb4/igt@gem_persistent_rel...@forked-interruptible-thrashing.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15701/shard-tglb5/igt@gem_persistent_rel...@forked-interruptible-thrashing.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#69]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-skl9/igt@gem_soft...@noreloc-s3.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15701/shard-skl2/igt@gem_soft...@noreloc-s3.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][19] -> [FAIL][20] ([i915#454]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-iclb1/igt@i915_pm...@dc6-psr.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15701/shard-iclb6/igt@i915_pm...@dc6-psr.html * igt@i915_pm_rps@waitboost: - shard-tglb: [PASS][21] -> [FAIL][22] ([i915#413]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-tglb3/igt@i915_pm_...@waitboost.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15701/shard-tglb8/igt@i915_pm_...@waitboost.html * igt@i915_suspend@sysfs-reader: - shard-tglb: [PASS][23] -> [INCOMPLETE][24] ([i915#456] / [i915#460]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/shard-tglb4/igt@i915_susp...@sysfs-reader.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15701/shard-tglb4/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#54]) +1 similar issue [25]:
Re: [Intel-gfx] [PATCH 3/3] drm/i915/dp: Disable Port sync mode correctly on teardown
On Fri, Dec 13, 2019 at 10:06:37PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 11, 2019 at 01:14:25PM -0800, Manasi Navare wrote:
> > While clearing the Ports ync mode enable and master select bits
> > we need to make sure that we perform a RMW for disable else
> > it sets the other bits casuing unwanted sideeffects.
> >
> > Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5
> > Cc: Ville Syrjälä
> > Cc: Jani Nikula
> > Fixes: 51528afe7c5e ("drm/i915/display/icl: Disable transcoder port sync as
> > part of crtc_disable() sequence")
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index c0a2dab3fe67..3fccda0f1f36 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -4599,7 +4599,8 @@ static void icl_disable_transcoder_port_sync(const
> > struct intel_crtc_state *old_
> > transcoder_name(old_crtc_state->cpu_transcoder));
> >
> > reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
> > - trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
> > + trans_ddi_func_ctl2_val = I915_READ(reg);
> > + trans_ddi_func_ctl2_val &= ~(PORT_SYNC_MODE_ENABLE |
> > PORT_SYNC_MODE_MASTER_SELECT_MASK);
> > I915_WRITE(reg, trans_ddi_func_ctl2_val);
>
> I915_WRITE(TRANS_DDI_FUNC_CTL2, 0);
So not even consider the other values that might have been set in this reg?
You would prefer setting this to 0 directly?
Right now i do see that no other bits are set, but things can change when we
start using DSI port sync mode or genlock mode etc.
Manasi
>
> > }
> > --
> > 2.19.1
>
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH 2/3] drm/i915/dp: Make port sync mode assignments only if all tiles present
On Wed, Dec 11, 2019 at 01:14:24PM -0800, Manasi Navare wrote:
> Add an extra check before making master slave assignments for tiled
> displays to make sure we make these assignments only if all tiled
> connectors are present. If not then initialize the state to defaults
> so it does a normal non tiled modeset without transcoder port sync.
>
> Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5
> Cc: Ville Syrjälä
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 28 ++--
> 1 file changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 7263eaa66cda..c0a2dab3fe67 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12048,6 +12048,12 @@ static bool c8_planes_changed(const struct
> intel_crtc_state *new_crtc_state)
> return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
> }
>
> +static void initialize_trans_port_sync_mode_state(struct intel_crtc_state
> *crtc_state)
> +{
> + crtc_state->master_transcoder = INVALID_TRANSCODER;
> + crtc_state->sync_mode_slaves_mask = 0;
> +}
> +
> static int icl_add_sync_mode_crtcs(struct intel_crtc_state *crtc_state)
> {
> struct drm_crtc *crtc = crtc_state->uapi.crtc;
> @@ -12059,11 +12065,22 @@ static int icl_add_sync_mode_crtcs(struct
> intel_crtc_state *crtc_state)
> struct drm_crtc *master_crtc = NULL;
> struct drm_crtc_state *master_crtc_state;
> struct intel_crtc_state *master_pipe_config;
> - int i, tile_group_id;
> + int i, tile_group_id = 0, num_tiled_conns = 0;
>
> if (INTEL_GEN(dev_priv) < 11)
> return 0;
>
> + /* If all tiles not present do not make master slave assignments
> + * Here we assume all tiles belong to the same tile group for now.
> + */
> + for_each_new_connector_in_state(>base, connector,
> connector_state, i) {
> + if (connector->has_tile) {
> + if (!tile_group_id)
> + tile_group_id = connector->tile_group->id;
Isn't 0 a valid tile group id?
> + num_tiled_conns++;
> + }
This whole thing looks confused. Should it not just look for the same
tile group as what the current connector belongs to?
> + }
> +
> /*
>* In case of tiled displays there could be one or more slaves but
> there is
>* only one master. Lets make the CRTC used by the connector
> corresponding
> @@ -12077,8 +12094,15 @@ static int icl_add_sync_mode_crtcs(struct
> intel_crtc_state *crtc_state)
> if (!connector->has_tile)
> continue;
> if (crtc_state->hw.mode.hdisplay != connector->tile_h_size ||
> - crtc_state->hw.mode.vdisplay != connector->tile_v_size)
> + crtc_state->hw.mode.vdisplay != connector->tile_v_size) {
> + initialize_trans_port_sync_mode_state(crtc_state);
> return 0;
> + }
> + if (connector->tile_group->id == tile_group_id &&
> + num_tiled_conns < connector->num_h_tile *
> connector->num_v_tile) {
> + initialize_trans_port_sync_mode_state(crtc_state);
> + return 0;
> + }
> if (connector->tile_h_loc == connector->num_h_tile - 1 &&
> connector->tile_v_loc == connector->num_v_tile - 1)
> continue;
This whole thing seems kinda overly complicated. I suggest it should
just blindly go through all connectors of the same tile group and pick
the lowest transcoder as the master, which is the logic Jose is using
for MST. Except I guess we have to special case the EDP transcoder
for port sync since it can't be a slave. So a simple numeric comparison
won't quite do like used for MST.
And then we should probably move this thing to the encoder
.compute_config(). I suppose it should look in the end something like:
compute_config() {
...
crtc_state->master = compute_master_transcoder();
crtc_state->slaves = 0;
if (master_transcoder == cpu_transcoder)
crtc_state->master = INVALID;
crtc_state->slave = compute_slave_transcoders();
}
}
That keeps it very readable and avoids the confusing stuff of
comptue_config() for one pipe randomly mutating the states of
the other pipes.
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/8] drm/print: introduce new struct drm_device based logging macros (rev3)
== Series Details ==
Series: series starting with [1/8] drm/print: introduce new struct drm_device
based logging macros (rev3)
URL : https://patchwork.freedesktop.org/series/70685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7561 -> Patchwork_15749
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15749/index.html
Known issues
Here are the changes found in Patchwork_15749 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] ([i915#62] / [i915#92])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7561/fi-kbl-x1275/igt@kms_setm...@basic-clone-single-crtc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15749/fi-kbl-x1275/igt@kms_setm...@basic-clone-single-crtc.html
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- {fi-tgl-u}: [INCOMPLETE][3] ([i915#460]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7561/fi-tgl-u/igt@gem_exec_susp...@basic-s4-devices.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15749/fi-tgl-u/igt@gem_exec_susp...@basic-s4-devices.html
* igt@gem_sync@basic-store-all:
- fi-tgl-y: [INCOMPLETE][5] -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7561/fi-tgl-y/igt@gem_s...@basic-store-all.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15749/fi-tgl-y/igt@gem_s...@basic-store-all.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [DMESG-FAIL][7] ([i915#553] / [i915#725]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7561/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15749/fi-hsw-4770r/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8700k: [DMESG-FAIL][9] ([i915#730]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7561/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15749/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
Warnings
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][12] ([i915#62] / [i915#92]) +4 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7561/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15749/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) ->
[DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +6 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7561/fi-kbl-x1275/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15749/fi-kbl-x1275/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#730]: https://gitlab.freedesktop.org/drm/intel/issues/730
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (55 -> 47)
--
Missing(8): fi-icl-1065g7 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7561 -> Patchwork_15749
CI-20190529: 20190529
CI_DRM_7561: defef87d82a872aa888a857583a2a9d7245661af @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5349: 048f58513d8b8ec6bb307a939f0ac959bc0f0e10 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15749: 97cb51cfd41213d708cbde41a42c1fd64d18aa88 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
97cb51cfd412 drm/i915/wopcm: convert to drm device based logging
39839157ae6f drm/i915/uc: convert to drm device based logging
dea0baf56927 drm/atomic: convert to drm device based logging
1ab5b849bf17 drm/mipi-dbi: convert to drm device based logging
82e3e24464fc drm/gem-fb-helper: convert to drm device based logging
bcf9d3cbc0bb drm/fb-helper: convert to drm device based logging
6e1203c54013
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for AUX power well fixes (rev4)
On Fri, Dec 13, 2019 at 06:55:06PM +, Patchwork wrote: > == Series Details == > > Series: AUX power well fixes (rev4) > URL : https://patchwork.freedesktop.org/series/70857/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_7554_full -> Patchwork_15737_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_15737_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_15737_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_15737_full: > > ### Piglit changes ### > > Possible regressions > > * spec@glsl-1.30@execution@texelfetch@fs-texelfetch-isampler1darray (NEW): > - pig-hsw-4770r: NOTRUN -> [FAIL][1] +1292 similar issues >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15737/pig-hsw-4770r/spec@glsl-1.30@execution@texelfe...@fs-texelfetch-isampler1darray.html Piglit (!!) failures. Definitely not caused by display power well changes and especially not on HSW. Applied to dinq; thanks Lucas for the reviews. Matt > > > New tests > - > > New tests have been introduced between CI_DRM_7554_full and > Patchwork_15737_full: > > ### New Piglit tests (1200) ### > > * hiz@hiz-depth-read-fbo-d24-s8: > - Statuses : 1 fail(s) > - Exec time: [0.10] s > > * object namespace pollution@texture with glclear: > - Statuses : 1 fail(s) > - Exec time: [0.16] s > > * object namespace pollution@texture with glgeneratemipmap: > - Statuses : 1 fail(s) > - Exec time: [0.13] s > > * object namespace pollution@texture with gltexsubimage2d: > - Statuses : 1 fail(s) > - Exec time: [0.25] s > > * spec@!opengl 1.1@teximage-colors gl_alpha: > - Statuses : 1 fail(s) > - Exec time: [0.25] s > > * spec@!opengl 1.1@teximage-colors gl_alpha12: > - Statuses : 1 fail(s) > - Exec time: [0.30] s > > * spec@!opengl 1.1@teximage-colors gl_alpha16: > - Statuses : 1 fail(s) > - Exec time: [0.31] s > > * spec@!opengl 1.1@teximage-colors gl_alpha4: > - Statuses : 1 fail(s) > - Exec time: [0.39] s > > * spec@!opengl 1.1@teximage-colors gl_alpha8: > - Statuses : 1 fail(s) > - Exec time: [0.34] s > > * spec@!opengl 1.1@teximage-colors gl_luminance: > - Statuses : 1 fail(s) > - Exec time: [0.32] s > > * spec@!opengl 1.1@teximage-colors gl_luminance12: > - Statuses : 1 fail(s) > - Exec time: [0.35] s > > * spec@!opengl 1.1@teximage-colors gl_luminance12_alpha12: > - Statuses : 1 fail(s) > - Exec time: [0.32] s > > * spec@!opengl 1.1@teximage-colors gl_luminance12_alpha4: > - Statuses : 1 fail(s) > - Exec time: [0.30] s > > * spec@!opengl 1.1@teximage-colors gl_luminance16: > - Statuses : 1 fail(s) > - Exec time: [0.28] s > > * spec@!opengl 1.1@teximage-colors gl_luminance16_alpha16: > - Statuses : 1 fail(s) > - Exec time: [0.28] s > > * spec@!opengl 1.1@teximage-colors gl_luminance4: > - Statuses : 1 fail(s) > - Exec time: [0.36] s > > * spec@!opengl 1.1@teximage-colors gl_luminance4_alpha4: > - Statuses : 1 fail(s) > - Exec time: [0.31] s > > * spec@!opengl 1.1@teximage-colors gl_luminance6_alpha2: > - Statuses : 1 fail(s) > - Exec time: [0.35] s > > * spec@!opengl 1.1@teximage-colors gl_luminance8: > - Statuses : 1 fail(s) > - Exec time: [0.34] s > > * spec@!opengl 1.1@teximage-colors gl_luminance8_alpha8: > - Statuses : 1 fail(s) > - Exec time: [0.36] s > > * spec@!opengl 1.1@teximage-colors gl_luminance_alpha: > - Statuses : 1 fail(s) > - Exec time: [0.34] s > > * spec@!opengl 1.1@teximage-colors gl_rgb10_a2: > - Statuses : 1 fail(s) > - Exec time: [0.31] s > > * spec@!opengl 1.1@teximage-colors gl_rgb16_snorm: > - Statuses : 1 fail(s) > - Exec time: [5.20] s > > * spec@!opengl 1.1@teximage-colors gl_rgb16f: > - Statuses : 1 fail(s) > - Exec time: [5.18] s > > * spec@!opengl 1.1@teximage-colors gl_rgb32f: > - Statuses : 1 fail(s) > - Exec time: [5.21] s > > * spec@!opengl 1.1@teximage-colors gl_rgb5_a1: > - Statuses : 1 fail(s) > - Exec time: [0.29] s > > * spec@!opengl 1.1@teximage-colors gl_rgba: > - Statuses : 1 fail(s) > - Exec time: [5.15] s > > * spec@!opengl 1.1@teximage-colors gl_rgba12: > - Statuses : 1 fail(s) > - Exec time: [0.34] s > > * spec@!opengl 1.1@teximage-colors gl_rgba16: > - Statuses : 1 fail(s) > - Exec time: [0.29] s > > * spec@!opengl 1.1@teximage-colors gl_rgba16_snorm: > - Statuses : 1 fail(s) > -
Re: [Intel-gfx] [PATCH 4/4] drm/vc4: Use dma_resv locking wrappers
On Mon, Nov 25, 2019 at 10:43:56AM +0100, Daniel Vetter wrote:
> I'll add more fancy logic to them soon, so everyone really has to use
> them. Plus they already provide some nice additional debug
> infrastructure on top of direct ww_mutex usage for the fences tracked
> by dma_resv.
>
> Signed-off-by: Daniel Vetter
Ping for some review/acks.
Thanks, Daniel
> ---
> drivers/gpu/drm/vc4/vc4_gem.c | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c
> index 7a06cb6e31c5..e1cfc3ccd05a 100644
> --- a/drivers/gpu/drm/vc4/vc4_gem.c
> +++ b/drivers/gpu/drm/vc4/vc4_gem.c
> @@ -568,7 +568,7 @@ vc4_unlock_bo_reservations(struct drm_device *dev,
> for (i = 0; i < exec->bo_count; i++) {
> struct drm_gem_object *bo = >bo[i]->base;
>
> - ww_mutex_unlock(>resv->lock);
> + dma_resv_unlock(bo->resv);
> }
>
> ww_acquire_fini(acquire_ctx);
> @@ -595,8 +595,7 @@ vc4_lock_bo_reservations(struct drm_device *dev,
> retry:
> if (contended_lock != -1) {
> bo = >bo[contended_lock]->base;
> - ret = ww_mutex_lock_slow_interruptible(>resv->lock,
> -acquire_ctx);
> + ret = dma_resv_lock_slow_interruptible(bo->resv, acquire_ctx);
> if (ret) {
> ww_acquire_done(acquire_ctx);
> return ret;
> @@ -609,19 +608,19 @@ vc4_lock_bo_reservations(struct drm_device *dev,
>
> bo = >bo[i]->base;
>
> - ret = ww_mutex_lock_interruptible(>resv->lock, acquire_ctx);
> + ret = dma_resv_lock_interruptible(bo->resv, acquire_ctx);
> if (ret) {
> int j;
>
> for (j = 0; j < i; j++) {
> bo = >bo[j]->base;
> - ww_mutex_unlock(>resv->lock);
> + dma_resv_unlock(bo->resv);
> }
>
> if (contended_lock != -1 && contended_lock >= i) {
> bo = >bo[contended_lock]->base;
>
> - ww_mutex_unlock(>resv->lock);
> + dma_resv_unlock(bo->resv);
> }
>
> if (ret == -EDEADLK) {
> --
> 2.24.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH v4 3/3] drm/i915/icl: Cleanup combo PHY aux power well handlers
On Fri, Dec 13, 2019 at 10:06:01AM -0800, Lucas De Marchi wrote:
> On Thu, Dec 12, 2019 at 05:06:00PM -0800, Matt Roper wrote:
> > Now that the combo PHY aux power well handlers are used exclusively on
> > Icelake, we can drop a bunch of the extra tests.
> >
> > v2: Don't try to use intel_uncore_rmw for register updates yet; there's
> >pending display uncore patches that need to land first. (Lucas)
> >
> > v3: Drop the combo phy assertion. It was backward before, but doesn't
> >seem terribly necessary. I'm keeping the IS_ICELAKE assertion
> >though since we often copy/paste/modify the power well tables when
> >defining new platforms and it's too easy to cargo cult the
> >ICL-specific handling to new platforms that shouldn't use it.
> >(Lucas)
> >
> > v4: Fix build; forgot to commit all the changes. (CI)
> >
> > Cc: Lucas De Marchi
> > Signed-off-by: Matt Roper
> > ---
> > .../drm/i915/display/intel_display_power.c| 20 +++
> > 1 file changed, 7 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 52f2332e0ab8..d59539002aaa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -418,7 +418,8 @@ icl_combo_phy_aux_power_well_enable(struct
> > drm_i915_private *dev_priv,
> > int pw_idx = power_well->desc->hsw.idx;
> > enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> > u32 val;
> > - int wa_idx_max;
> > +
> > + WARN_ON(!IS_ICELAKE(dev_priv));
> >
> > val = I915_READ(regs->driver);
> > I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
> > @@ -430,14 +431,7 @@ icl_combo_phy_aux_power_well_enable(struct
> > drm_i915_private *dev_priv,
> >
> > hsw_wait_for_power_well_enable(dev_priv, power_well);
> >
> > - /* Display WA #1178: icl, tgl */
>
> this comment must stay
Woops, yes. Re-added (minus the tgl) while applying. Thanks for the
reviews.
Matt
>
> Otherwise
>
>
> Reviewed-by: Lucas De Marchi
>
> Lucas De Marchi
>
> > - if (IS_TIGERLAKE(dev_priv))
> > - wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
> > - else
> > - wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
> > -
> > - if (!IS_ELKHARTLAKE(dev_priv) &&
> > - pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= wa_idx_max &&
> > + if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
> > !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
> > val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
> > val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
> > @@ -454,10 +448,10 @@ icl_combo_phy_aux_power_well_disable(struct
> > drm_i915_private *dev_priv,
> > enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> > u32 val;
> >
> > - if (INTEL_GEN(dev_priv) < 12) {
> > - val = I915_READ(ICL_PORT_CL_DW12(phy));
> > - I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
> > - }
> > + WARN_ON(!IS_ICELAKE(dev_priv));
> > +
> > + val = I915_READ(ICL_PORT_CL_DW12(phy));
> > + I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
> >
> > val = I915_READ(regs->driver);
> > I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
> > --
> > 2.23.0
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH 3/4] drm/msm: Use dma_resv locking wrappers
On Mon, Nov 25, 2019 at 10:43:55AM +0100, Daniel Vetter wrote:
> I'll add more fancy logic to them soon, so everyone really has to use
> them. Plus they already provide some nice additional debug
> infrastructure on top of direct ww_mutex usage for the fences tracked
> by dma_resv.
>
> Signed-off-by: Daniel Vetter
> Cc: Rob Clark
> Cc: Sean Paul
> Cc: linux-arm-...@vger.kernel.org
> Cc: freedr...@lists.freedesktop.org
Ping for some review/acks.
Thanks, Daniel
> ---
> drivers/gpu/drm/msm/msm_gem_submit.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
> b/drivers/gpu/drm/msm/msm_gem_submit.c
> index 7d04c47d0023..385d4965a8d0 100644
> --- a/drivers/gpu/drm/msm/msm_gem_submit.c
> +++ b/drivers/gpu/drm/msm/msm_gem_submit.c
> @@ -157,7 +157,7 @@ static void submit_unlock_unpin_bo(struct msm_gem_submit
> *submit,
> msm_gem_unpin_iova(_obj->base, submit->aspace);
>
> if (submit->bos[i].flags & BO_LOCKED)
> - ww_mutex_unlock(_obj->base.resv->lock);
> + dma_resv_unlock(msm_obj->base.resv);
>
> if (backoff && !(submit->bos[i].flags & BO_VALID))
> submit->bos[i].iova = 0;
> @@ -180,8 +180,8 @@ static int submit_lock_objects(struct msm_gem_submit
> *submit)
> contended = i;
>
> if (!(submit->bos[i].flags & BO_LOCKED)) {
> - ret =
> ww_mutex_lock_interruptible(_obj->base.resv->lock,
> - >ticket);
> + ret = dma_resv_lock_interruptible(msm_obj->base.resv,
> + >ticket);
> if (ret)
> goto fail;
> submit->bos[i].flags |= BO_LOCKED;
> @@ -202,8 +202,8 @@ static int submit_lock_objects(struct msm_gem_submit
> *submit)
> if (ret == -EDEADLK) {
> struct msm_gem_object *msm_obj = submit->bos[contended].obj;
> /* we lost out in a seqno race, lock and retry.. */
> - ret =
> ww_mutex_lock_slow_interruptible(_obj->base.resv->lock,
> - >ticket);
> + ret = dma_resv_lock_slow_interruptible(msm_obj->base.resv,
> +>ticket);
> if (!ret) {
> submit->bos[contended].flags |= BO_LOCKED;
> slow_locked = contended;
> --
> 2.24.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 1/4] drm/etnaviv: Use dma_resv locking wrappers
On Mon, Nov 25, 2019 at 10:43:53AM +0100, Daniel Vetter wrote:
> I'll add more fancy logic to them soon, so everyone really has to use
> them. Plus they already provide some nice additional debug
> infrastructure on top of direct ww_mutex usage for the fences tracked
> by dma_resv.
>
> Signed-off-by: Daniel Vetter
> Cc: Lucas Stach
> Cc: Russell King
> Cc: Christian Gmeiner
> Cc: etna...@lists.freedesktop.org
Ping for some review/acks.
Thanks, Daniel
> ---
> drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 8 +++-
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
> b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
> index aa3e4c3b063a..947b21868e72 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
> @@ -113,7 +113,7 @@ static void submit_unlock_object(struct
> etnaviv_gem_submit *submit, int i)
> if (submit->bos[i].flags & BO_LOCKED) {
> struct drm_gem_object *obj = >bos[i].obj->base;
>
> - ww_mutex_unlock(>resv->lock);
> + dma_resv_unlock(obj->resv);
> submit->bos[i].flags &= ~BO_LOCKED;
> }
> }
> @@ -133,8 +133,7 @@ static int submit_lock_objects(struct etnaviv_gem_submit
> *submit,
> contended = i;
>
> if (!(submit->bos[i].flags & BO_LOCKED)) {
> - ret = ww_mutex_lock_interruptible(>resv->lock,
> - ticket);
> + ret = dma_resv_lock(obj->resv, ticket);
> if (ret == -EALREADY)
> DRM_ERROR("BO at index %u already on submit
> list\n",
> i);
> @@ -161,8 +160,7 @@ static int submit_lock_objects(struct etnaviv_gem_submit
> *submit,
> obj = >bos[contended].obj->base;
>
> /* we lost out in a seqno race, lock and retry.. */
> - ret = ww_mutex_lock_slow_interruptible(>resv->lock,
> -ticket);
> + ret = dma_resv_lock_slow_interruptible(obj->resv, ticket);
> if (!ret) {
> submit->bos[contended].flags |= BO_LOCKED;
> slow_locked = contended;
> --
> 2.24.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/dp: Disable Port sync mode correctly on teardown
On Wed, Dec 11, 2019 at 01:14:25PM -0800, Manasi Navare wrote:
> While clearing the Ports ync mode enable and master select bits
> we need to make sure that we perform a RMW for disable else
> it sets the other bits casuing unwanted sideeffects.
>
> Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Fixes: 51528afe7c5e ("drm/i915/display/icl: Disable transcoder port sync as
> part of crtc_disable() sequence")
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index c0a2dab3fe67..3fccda0f1f36 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4599,7 +4599,8 @@ static void icl_disable_transcoder_port_sync(const
> struct intel_crtc_state *old_
> transcoder_name(old_crtc_state->cpu_transcoder));
>
> reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
> - trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
> + trans_ddi_func_ctl2_val = I915_READ(reg);
> + trans_ddi_func_ctl2_val &= ~(PORT_SYNC_MODE_ENABLE |
> PORT_SYNC_MODE_MASTER_SELECT_MASK);
> I915_WRITE(reg, trans_ddi_func_ctl2_val);
I915_WRITE(TRANS_DDI_FUNC_CTL2, 0);
> }
> --
> 2.19.1
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset
On Wed, Dec 11, 2019 at 01:14:23PM -0800, Manasi Navare wrote:
> In case of tiled displays, all the tiles are linke dto each other
> for transcoder port sync. So in intel_atomic_check() we need to make
> sure that we add all the tiles to the modeset and if one of the
> tiles needs a full modeset then mark all other tiles for a full modeset.
>
> Suggested-by: Ville Syrjälä
> Cc: Ville Syrjälä
> Cc: José Roberto de Souza
> Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 78
> 1 file changed, 78 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 803993a01ca7..7263eaa66cda 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14066,6 +14066,80 @@ static int intel_atomic_check_crtcs(struct
> intel_atomic_state *state)
> return 0;
> }
>
> +static int
> +intel_dp_modeset_all_tiles(struct drm_i915_private *dev_priv,
> +struct intel_atomic_state *state, int tile_grp_id)
> +{
> + struct drm_connector *conn_iter;
'connector'
> + struct drm_connector_list_iter conn_list_iter;
> + struct drm_crtc_state *crtc_state;
crtc_state has needlessly wide scope.
> +
> + drm_connector_list_iter_begin(_priv->drm, _list_iter);
> + drm_for_each_connector_iter(conn_iter, _list_iter) {
> + struct drm_connector_state *conn_iter_state;
'conn_state' is the most popular name.
> +
> + if (!conn_iter->has_tile)
> + continue;
> + conn_iter_state = drm_atomic_get_connector_state(>base,
> + conn_iter);
> + if (IS_ERR(conn_iter_state)) {
> + drm_connector_list_iter_end(_list_iter);
> + return PTR_ERR(conn_iter_state);
> + }
> +
> + if (!conn_iter_state->crtc)
> + continue;
> +
> + if (conn_iter->tile_group->id != tile_grp_id)
> + continue;
The tile group check should be part of the same if with the has_tile
check.
> +
> + crtc_state = drm_atomic_get_crtc_state(>base,
> conn_iter_state->crtc);
> + if (IS_ERR(crtc_state)) {
> + drm_connector_list_iter_end(_list_iter);
> + return PTR_ERR(conn_iter_state);
> + }
> + crtc_state->mode_changed = true;
> + }
> + drm_connector_list_iter_end(_list_iter);
> +
> + return 0;
> +}
> +
> +static int
> +intel_dp_atomic_trans_port_sync_check(struct drm_i915_private *dev_priv,
Pointless variable. Can be extracted from the atomic state.
> + struct intel_atomic_state *state)
> +{
> + struct drm_connector *connector;
> + struct drm_crtc_state *crtc_state;
> + struct drm_connector_state *connector_state;
> + int i, ret, tile_grp_id = 0;
tile_grp_id is rather pointless. crtc_state and ret can move into
tighter scope. And the next suggestion allows you to kill crtc_state
entirely...
> +
> + if (INTEL_GEN(dev_priv) < 11)
> + return 0;
> +
> + /* Is tiled, mark all other tiled CRTCs as needing a modeset */
> + for_each_new_connector_in_state(>base, connector,
> connector_state, i) {
> + if (!connector->has_tile)
> + continue;
> + if (connector_state->crtc &&
> + tile_grp_id != connector->tile_group->id) {
> + crtc_state = drm_atomic_get_new_crtc_state(>base,
> +
> connector_state->crtc);
> + if (!drm_atomic_crtc_needs_modeset(crtc_state))
> + continue;
This should to be able to be shortened to just intel_connector_needs_modeset().
> +
> + tile_grp_id = connector->tile_group->id;
> + } else
> + continue;
> +
> + ret = intel_dp_modeset_all_tiles(dev_priv, state, tile_grp_id);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> /**
> * intel_atomic_check - validate state object
> * @dev: drm device
> @@ -14093,6 +14167,10 @@ static int intel_atomic_check(struct drm_device *dev,
> if (ret)
> goto fail;
>
> + ret = intel_dp_atomic_trans_port_sync_check(dev_priv, state);
> + if (ret)
> + goto fail;
We should probably do this from the connector .atomic_check() hook if
Jose is going to do the MST thing that way. But no real problem doing
here I think.
> +
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> if
[Intel-gfx] [PATCH 1/2] drm/i915/perf: Register sysctl path globally
We do not require to register the sysctl paths per instance,
so making registration global.
v2: make sysctl path register and unregister function driver
specific (Tvrtko and Lucas).
v3: remove the NULL-check as unregister_sysctl_table is null
safe. (Chris and Lucas)
Cc: Sudeep Dutt
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Cc: Chris Wilson
Cc: Jani Nikula
Reviewed-by: Chris Wilson
Reviewed-by: Lucas De Marchi
Signed-off-by: Venkata Sandeep Dhanalakota
---
drivers/gpu/drm/i915/i915_pci.c| 9 -
drivers/gpu/drm/i915/i915_perf.c | 17 +
drivers/gpu/drm/i915/i915_perf.h | 2 ++
drivers/gpu/drm/i915/i915_perf_types.h | 1 -
4 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 877560b1031e..9571611b4b16 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -30,6 +30,7 @@
#include "display/intel_fbdev.h"
#include "i915_drv.h"
+#include "i915_perf.h"
#include "i915_globals.h"
#include "i915_selftest.h"
@@ -1053,7 +1054,12 @@ static int __init i915_init(void)
return 0;
}
- return pci_register_driver(_pci_driver);
+ err = pci_register_driver(_pci_driver);
+ if (err)
+ return err;
+
+ i915_perf_sysctl_register();
+ return 0;
}
static void __exit i915_exit(void)
@@ -1061,6 +1067,7 @@ static void __exit i915_exit(void)
if (!i915_pci_driver.driver.owner)
return;
+ i915_perf_sysctl_unregister();
pci_unregister_driver(_pci_driver);
i915_globals_exit();
}
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 8d2e37949f46..3c163a9d69a9 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -387,6 +387,8 @@ struct i915_oa_config_bo {
struct i915_vma *vma;
};
+static struct ctl_table_header *sysctl_header;
+
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
void i915_oa_config_release(struct kref *ref)
@@ -4228,7 +4230,7 @@ static struct ctl_table dev_root[] = {
};
/**
- * i915_perf_init - initialize i915-perf state on module load
+ * i915_perf_init - initialize i915-perf state on module bind
* @i915: i915 device instance
*
* Initializes i915-perf state without exposing anything to userspace.
@@ -4345,7 +4347,6 @@ void i915_perf_init(struct drm_i915_private *i915)
oa_sample_rate_hard_limit = 1000 *
(RUNTIME_INFO(i915)->cs_timestamp_frequency_khz / 2);
- perf->sysctl_header = register_sysctl_table(dev_root);
mutex_init(>metrics_lock);
idr_init(>metrics_idr);
@@ -4381,6 +4382,16 @@ static int destroy_config(int id, void *p, void *data)
return 0;
}
+void i915_perf_sysctl_register(void)
+{
+ sysctl_header = register_sysctl_table(dev_root);
+}
+
+void i915_perf_sysctl_unregister(void)
+{
+ unregister_sysctl_table(sysctl_header);
+}
+
/**
* i915_perf_fini - Counter part to i915_perf_init()
* @i915: i915 device instance
@@ -4395,8 +4406,6 @@ void i915_perf_fini(struct drm_i915_private *i915)
idr_for_each(>metrics_idr, destroy_config, perf);
idr_destroy(>metrics_idr);
- unregister_sysctl_table(perf->sysctl_header);
-
memset(>ops, 0, sizeof(perf->ops));
perf->i915 = NULL;
}
diff --git a/drivers/gpu/drm/i915/i915_perf.h b/drivers/gpu/drm/i915/i915_perf.h
index 4ceebce72060..882fdd0a7680 100644
--- a/drivers/gpu/drm/i915/i915_perf.h
+++ b/drivers/gpu/drm/i915/i915_perf.h
@@ -23,6 +23,8 @@ void i915_perf_fini(struct drm_i915_private *i915);
void i915_perf_register(struct drm_i915_private *i915);
void i915_perf_unregister(struct drm_i915_private *i915);
int i915_perf_ioctl_version(void);
+void i915_perf_sysctl_register(void);
+void i915_perf_sysctl_unregister(void);
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h
b/drivers/gpu/drm/i915/i915_perf_types.h
index 74ddc20a0d37..45e581455f5d 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -380,7 +380,6 @@ struct i915_perf {
struct drm_i915_private *i915;
struct kobject *metrics_kobj;
- struct ctl_table_header *sysctl_header;
/*
* Lock associated with adding/modifying/removing OA configs
--
2.21.0.5.gaeb582a983
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[Intel-gfx] [PATCH 2/2] drm/i915: Introduce new macros for tracing
New macros ENGINE_TRACE(), CE_TRACE(), RQ_TRACE() and
GT_TRACE() are introduce to tag device name and engine
name with contexts and requests tracing in i915.
v2: Addressed CI checkpatch issues.
Cc: Sudeep Dutt
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Cc: Chris Wilson
Cc: Jani Nikula
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Signed-off-by: Venkata Sandeep Dhanalakota
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 4 +-
drivers/gpu/drm/i915/gt/intel_context.c | 11 +-
drivers/gpu/drm/i915/gt/intel_context.h | 7 ++
drivers/gpu/drm/i915/gt/intel_engine.h| 8 ++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +-
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 6 +-
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 15 ++-
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 6 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 106 --
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 11 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +-
drivers/gpu/drm/i915/i915_request.c | 23 +---
drivers/gpu/drm/i915/i915_request.h | 8 ++
14 files changed, 111 insertions(+), 110 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index f88ee1317bb4..3671a4e7e1cb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -13,7 +13,7 @@
void i915_gem_suspend(struct drm_i915_private *i915)
{
- GEM_TRACE("\n");
+ GEM_TRACE("%s\n", dev_name(i915->drm.dev));
intel_wakeref_auto(>ggtt.userfault_wakeref, 0);
flush_workqueue(i915->wq);
@@ -99,7 +99,7 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
void i915_gem_resume(struct drm_i915_private *i915)
{
- GEM_TRACE("\n");
+ GEM_TRACE("%s\n", dev_name(i915->drm.dev));
intel_uncore_forcewake_get(>uncore, FORCEWAKE_ALL);
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 61c39e943f69..b1e346d2d35f 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -68,9 +68,8 @@ int __intel_context_do_pin(struct intel_context *ce)
if (err)
goto err;
- GEM_TRACE("%s context:%llx pin ring:{head:%04x, tail:%04x}\n",
- ce->engine->name, ce->timeline->fence_context,
- ce->ring->head, ce->ring->tail);
+ CE_TRACE(ce, "pin ring:{head:%04x, tail:%04x}\n",
+ce->ring->head, ce->ring->tail);
i915_gem_context_get(ce->gem_context); /* for ctx->ppgtt */
@@ -98,8 +97,7 @@ void intel_context_unpin(struct intel_context *ce)
mutex_lock_nested(>pin_mutex, SINGLE_DEPTH_NESTING);
if (likely(atomic_dec_and_test(>pin_count))) {
- GEM_TRACE("%s context:%llx retire\n",
- ce->engine->name, ce->timeline->fence_context);
+ CE_TRACE(ce, "retire\n");
ce->ops->unpin(ce);
@@ -141,8 +139,7 @@ static void __intel_context_retire(struct i915_active
*active)
{
struct intel_context *ce = container_of(active, typeof(*ce), active);
- GEM_TRACE("%s context:%llx retire\n",
- ce->engine->name, ce->timeline->fence_context);
+ CE_TRACE(ce, "retire\n");
set_bit(CONTEXT_VALID_BIT, >flags);
if (ce->state)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index 68b3d317d959..29771dd78e4a 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -15,6 +15,13 @@
#include "intel_ring_types.h"
#include "intel_timeline_types.h"
+#define CE_TRACE((ce__), fmt, ...) do {
\
+ typecheck(struct intel_context, *(ce__)); \
+ ENGINE_TRACE((ce__)->engine, "context:%llx" fmt,\
+(ce__)->timeline->fence_context, \
+##__VA_ARGS__);\
+} while (0)
+
void intel_context_init(struct intel_context *ce,
struct i915_gem_context *ctx,
struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index c294ea80605e..230b02774a4e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -29,6 +29,14 @@ struct intel_gt;
#define CACHELINE_BYTES 64
#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
+#define ENGINE_TRACE((e__), fmt, ...) do { \
+ typecheck(struct intel_engine_cs, *(e__)); \
+ GEM_TRACE("%s %s: " fmt,\
+
[Intel-gfx] [PATCH 1/5] drm/i915: Call hsw_fdi_link_train() directly()
From: Ville Syrjälä
Remove the pointless vfunc detour for hsw_fdi_link_train()
and just call it directly. Also pass the encoder in so we
can nuke the silly encoder loop within.
Cc: José Roberto de Souza
Cc: Manasi Navare
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crt.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 12
drivers/gpu/drm/i915/display/intel_ddi.h | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 --
4 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index 7a2d36905155..50624b8f064d 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -278,7 +278,7 @@ static void hsw_pre_enable_crt(struct intel_encoder
*encoder,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
- dev_priv->display.fdi_link_train(crtc, crtc_state);
+ hsw_fdi_link_train(encoder, crtc_state);
intel_ddi_enable_pipe_clock(crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5b6f32517c75..94f8bc4cd335 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1107,18 +1107,14 @@ static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder
*encoder,
* DDI A (which is used for eDP)
*/
-void hsw_fdi_link_train(struct intel_crtc *crtc,
+void hsw_fdi_link_train(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_encoder *encoder;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 temp, i, rx_ctl_val, ddi_pll_sel;
- for_each_encoder_on_crtc(dev, >base, encoder) {
- WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
- intel_prepare_dp_ddi_buffers(encoder, crtc_state);
- }
+ intel_prepare_dp_ddi_buffers(encoder, crtc_state);
/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
* mode set "sequence for CRT port" document:
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
b/drivers/gpu/drm/i915/display/intel_ddi.h
index 19aeab1246ee..167c6579d972 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -22,7 +22,7 @@ struct intel_encoder;
void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state
*old_conn_state);
-void hsw_fdi_link_train(struct intel_crtc *crtc,
+void hsw_fdi_link_train(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0f37f1d2026d..8aed67d2c105 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16673,8 +16673,6 @@ void intel_init_display_hooks(struct drm_i915_private
*dev_priv)
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
- } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- dev_priv->display.fdi_link_train = hsw_fdi_link_train;
}
if (INTEL_GEN(dev_priv) >= 9)
--
2.23.0
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[Intel-gfx] [PATCH 5/5] drm/i915: Move stuff from haswell_crtc_disable() into encoder .post_disable()
From: Ville Syrjälä
Move all of haswell_crtc_disable() into the encoder
.post_disable() hooks. Now we're left with just
calling the .disable() and .post_disable() hooks
back to back.
I chose to move the code into the .post_disable() hook instead
of the .enable() hook as most of the sequence is currently
implemented in the .post_enable() hook.
We should collapse it all down to just one hook and then the
encoders can drive the modeset sequence fully. But that may
need some further refactoring as we currently call the
ddi .post_disable() hook from mst code and we can't just
replace that with a call to the ddi .disable() hook.
Should also follow up with similar treatment for the enable
sequence but let's start here where it's easier.
Cc: José Roberto de Souza
Cc: Manasi Navare
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 12 +
drivers/gpu/drm/i915/display/intel_crt.c | 8 +++
drivers/gpu/drm/i915/display/intel_ddi.c | 35
drivers/gpu/drm/i915/display/intel_display.c | 57 +++-
drivers/gpu/drm/i915/display/intel_display.h | 4 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 11
drivers/gpu/drm/i915/display/vlv_dsi.c | 10 +++-
7 files changed, 86 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 03aa92d317a2..006b1a297e6f 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1251,6 +1251,17 @@ static void gen11_dsi_disable(struct intel_encoder
*encoder,
gen11_dsi_disable_io_power(encoder);
}
+static void gen11_dsi_post_disable(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*old_crtc_state,
+ const struct drm_connector_state
*old_conn_state)
+{
+ intel_crtc_vblank_off(old_crtc_state);
+
+ intel_dsc_disable(old_crtc_state);
+
+ skylake_scaler_disable(old_crtc_state);
+}
+
static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector
*connector,
struct drm_display_mode *mode)
{
@@ -1697,6 +1708,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
encoder->pre_enable = gen11_dsi_pre_enable;
encoder->disable = gen11_dsi_disable;
+ encoder->post_disable = gen11_dsi_post_disable;
encoder->port = port;
encoder->get_config = gen11_dsi_get_config;
encoder->update_pipe = intel_panel_update_backlight;
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index 50624b8f064d..b2b1336ecdb6 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -241,6 +241,14 @@ static void hsw_post_disable_crt(struct intel_encoder
*encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ intel_crtc_vblank_off(old_crtc_state);
+
+ intel_disable_pipe(old_crtc_state);
+
+ intel_ddi_disable_transcoder_func(old_crtc_state);
+
+ ironlake_pfit_disable(old_crtc_state);
+
intel_ddi_disable_pipe_clock(old_crtc_state);
pch_post_disable_crt(encoder, old_crtc_state, old_conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index cac0be47e500..fa40ba7cbcad 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3851,6 +3851,25 @@ static void intel_ddi_post_disable_hdmi(struct
intel_encoder *encoder,
intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
}
+static void icl_disable_transcoder_port_sync(const struct intel_crtc_state
*old_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ i915_reg_t reg;
+ u32 trans_ddi_func_ctl2_val;
+
+ if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
+ return;
+
+ DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
+ transcoder_name(old_crtc_state->cpu_transcoder));
+
+ reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
+ trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
+ PORT_SYNC_MODE_MASTER_SELECT_MASK);
+ I915_WRITE(reg, trans_ddi_func_ctl2_val);
+}
+
static void intel_ddi_post_disable(struct intel_encoder *encoder,
const struct intel_crtc_state
*old_crtc_state,
const struct drm_connector_state
*old_conn_state)
@@ -3860,6 +3879,22 @@ static void intel_ddi_post_disable(struct intel_encoder
*encoder,
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
bool is_tc_port =
[Intel-gfx] [PATCH 4/5] drm/i915: Pass old crtc state to intel_crtc_vblank_off()
From: Ville Syrjälä
To make life easier in the future let's pass the old crtc state
to intel_crtc_vblank_off() just like we already do for its
counterpart intel_crtc_vblank_on().
Cc: José Roberto de Souza
Cc: Manasi Navare
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 30f277aa228f..df69e4cd4707 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1825,8 +1825,10 @@ static void intel_crtc_vblank_on(const struct
intel_crtc_state *crtc_state)
drm_crtc_vblank_on(>base);
}
-static void intel_crtc_vblank_off(struct intel_crtc *crtc)
+static void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
drm_crtc_vblank_off(>base);
assert_vblank_disabled(>base);
}
@@ -6699,7 +6701,7 @@ static void ironlake_crtc_disable(struct
intel_atomic_state *state,
intel_encoders_disable(state, crtc);
- intel_crtc_vblank_off(crtc);
+ intel_crtc_vblank_off(old_crtc_state);
intel_disable_pipe(old_crtc_state);
@@ -6748,7 +6750,7 @@ static void haswell_crtc_disable(struct
intel_atomic_state *state,
intel_encoders_disable(state, crtc);
- intel_crtc_vblank_off(crtc);
+ intel_crtc_vblank_off(old_crtc_state);
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
@@ -7113,7 +7115,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state
*state,
intel_encoders_disable(state, crtc);
- intel_crtc_vblank_off(crtc);
+ intel_crtc_vblank_off(old_crtc_state);
intel_disable_pipe(old_crtc_state);
--
2.23.0
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[Intel-gfx] [PATCH 3/5] drm/i915: Pass old crtc state to skylake_scaler_disable()
From: Ville Syrjälä
To make life easier in the future let's pass the old crtc state
to skylake_scaler_disable() just like we already do for
for its ancestor ironlake_pfit_disable().
Cc: José Roberto de Souza
Cc: Manasi Navare
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 4adcd751384e..30f277aa228f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5769,8 +5769,9 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
return 0;
}
-static void skylake_scaler_disable(struct intel_crtc *crtc)
+static void skylake_scaler_disable(const struct intel_crtc_state
*old_crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
int i;
for (i = 0; i < crtc->num_scalers; i++)
@@ -6762,7 +6763,7 @@ static void haswell_crtc_disable(struct
intel_atomic_state *state,
intel_dsc_disable(old_crtc_state);
if (INTEL_GEN(dev_priv) >= 9)
- skylake_scaler_disable(crtc);
+ skylake_scaler_disable(old_crtc_state);
else
ironlake_pfit_disable(old_crtc_state);
--
2.23.0
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[Intel-gfx] [PATCH 2/5] drm/i915: Nuke .post_pll_disable() for DDI platforms
From: Ville Syrjälä
HSW+ platforms call encoder .post_disable() and .post_pll_disable()
back to back. And since we don't even disable the PLL in between
let's just move everything into .post_disable().
intel_dp_mst does forward the .post_disable() call to intel_ddi at
the very end of its own .post_disable() hook, so this time MST
I shouldn't even break MST by accident.
Cc: José Roberto de Souza
Cc: Manasi Navare
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 29 +++-
drivers/gpu/drm/i915/display/intel_display.c | 2 --
drivers/gpu/drm/i915/display/intel_dp_mst.c | 15 --
3 files changed, 10 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 94f8bc4cd335..cac0be47e500 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3856,6 +3856,9 @@ static void intel_ddi_post_disable(struct intel_encoder
*encoder,
const struct drm_connector_state
*old_conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(>base);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
/*
* When called from DP MST code:
@@ -3879,6 +3882,13 @@ static void intel_ddi_post_disable(struct intel_encoder
*encoder,
if (INTEL_GEN(dev_priv) >= 11)
icl_unmap_plls_to_ports(encoder);
+
+ if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
+ intel_display_power_put_unchecked(dev_priv,
+
intel_ddi_main_link_aux_domain(dig_port));
+
+ if (is_tc_port)
+ intel_tc_port_put_link(dig_port);
}
void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
@@ -4191,24 +4201,6 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
crtc_state->lane_lat_optim_mask);
}
-static void
-intel_ddi_post_pll_disable(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_digital_port *dig_port = enc_to_dig_port(>base);
- enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
-
- if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
- intel_display_power_put_unchecked(dev_priv,
-
intel_ddi_main_link_aux_domain(dig_port));
-
- if (is_tc_port)
- intel_tc_port_put_link(dig_port);
-}
-
static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
@@ -4795,7 +4787,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
encoder->compute_config = intel_ddi_compute_config;
encoder->enable = intel_enable_ddi;
encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
- encoder->post_pll_disable = intel_ddi_post_pll_disable;
encoder->pre_enable = intel_ddi_pre_enable;
encoder->disable = intel_disable_ddi;
encoder->post_disable = intel_ddi_post_disable;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8aed67d2c105..4adcd751384e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6767,8 +6767,6 @@ static void haswell_crtc_disable(struct
intel_atomic_state *state,
ironlake_pfit_disable(old_crtc_state);
intel_encoders_post_disable(state, crtc);
-
- intel_encoders_post_pll_disable(state, crtc);
}
static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 926e49f449a6..8bdbb15799ee 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -286,20 +286,6 @@ static void intel_mst_pre_pll_enable_dp(struct
intel_encoder *encoder,
pipe_config, NULL);
}
-static void intel_mst_post_pll_disable_dp(struct intel_encoder *encoder,
- const struct intel_crtc_state
*old_crtc_state,
- const struct drm_connector_state
*old_conn_state)
-{
- struct intel_dp_mst_encoder *intel_mst = enc_to_mst(>base);
- struct intel_digital_port *intel_dig_port = intel_mst->primary;
- struct intel_dp *intel_dp =
Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/gt: Move power management debug files into a gt aware debugfs
Quoting Andi Shyti (2019-12-13 19:41:29)
> Hi Michal,
>
> > > @@ -75,6 +75,8 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
> > > # "Graphics Technology" (aka we talk to the gpu)
> > > obj-y += gt/
> > > gt-y += \
> > > + gt/debugfs_gt.o \
> > > + gt/debugfs_pm.o \
> >
> > hm, maybe this should be:
> > gt/intel_gt_debugfs.o
> > and
> > gt/intel_pm_debugfs.o
>
> this was actually the name I wanted to give it originally, but
> meantime I also wanted to have the debugfs files alphabetically
> sorted in sequence, like the selftest_* files (I can imagine in
> the future having more debugfs files).
>
> Maybe intel_debugfs_gt.c/intel_debugfs_pm.c would be a good
> compromise?
I don't mind, your argument that we will partition these files off
under gt-${CONFIG_DEBUGFS} += gt/debugfs_*.o was convincing.
>
> > > @@ -0,0 +1,22 @@
> > > +/* SPDX-License-Identifier: MIT */
> >
> > in .c SPDX shall start with //
>
> I agree this is the "official" way of doing it, and I also read
> some discussions about it in this mailing list. But however I do
> it, I know someone won't like it. I checked the style in this
> directory and tried to keep it conform to the "gt way".
Shrug. I don't like the coding style violation, so leave it up to
someone who insists to do treewide changes.
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/8] drm/print: introduce new struct drm_device based logging macros (rev3)
== Series Details == Series: series starting with [1/8] drm/print: introduce new struct drm_device based logging macros (rev3) URL : https://patchwork.freedesktop.org/series/70685/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2ccbb2bd92a4 drm/print: introduce new struct drm_device based logging macros -:83: CHECK:LINE_SPACING: Please don't use multiple blank lines #83: FILE: include/drm/drm_print.h:432: + + -:85: ERROR:SPACING: space required after that ',' (ctx:VxO) #85: FILE: include/drm/drm_print.h:434: + __drm_printk((drm), info,, fmt, ##__VA_ARGS__) ^ -:88: ERROR:SPACING: space required after that ',' (ctx:VxO) #88: FILE: include/drm/drm_print.h:437: + __drm_printk((drm), notice,, fmt, ##__VA_ARGS__) ^ -:91: ERROR:SPACING: space required after that ',' (ctx:VxO) #91: FILE: include/drm/drm_print.h:440: + __drm_printk((drm), warn,, fmt, ##__VA_ARGS__) ^ -:94: ERROR:SPACING: space required after that ',' (ctx:VxO) #94: FILE: include/drm/drm_print.h:443: + __drm_printk((drm), err,, "*ERROR* " fmt, ##__VA_ARGS__) ^ -:96: CHECK:LINE_SPACING: Please don't use multiple blank lines #96: FILE: include/drm/drm_print.h:445: + + -:109: CHECK:LINE_SPACING: Please don't use multiple blank lines #109: FILE: include/drm/drm_print.h:458: + + -:113: CHECK:LINE_SPACING: Please don't use multiple blank lines #113: FILE: include/drm/drm_print.h:462: + + -:133: CHECK:LINE_SPACING: Please don't use multiple blank lines #133: FILE: include/drm/drm_print.h:482: + + total: 4 errors, 0 warnings, 5 checks, 79 lines checked 6e1203c54013 drm/client: convert to drm device based logging bcf9d3cbc0bb drm/fb-helper: convert to drm device based logging 82e3e24464fc drm/gem-fb-helper: convert to drm device based logging 1ab5b849bf17 drm/mipi-dbi: convert to drm device based logging dea0baf56927 drm/atomic: convert to drm device based logging 39839157ae6f drm/i915/uc: convert to drm device based logging 97cb51cfd412 drm/i915/wopcm: convert to drm device based logging ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 02/12] drm/i915: Clear the repeater bit on HDCP disable
On Fri, Dec 13, 2019 at 03:59:02PM +0530, Ramalingam C wrote:
> On 2019-12-12 at 14:02:20 -0500, Sean Paul wrote:
> > From: Sean Paul
> >
> > On HDCP disable, clear the repeater bit. This ensures if we connect a
> > non-repeater sink after a repeater, the bit is in the state we expect.
> >
> > Fixes: ee5e5e7a5e0f ("drm/i915: Add HDCP framework + base implementation")
> > Cc: Chris Wilson
> > Cc: Ramalingam C
> > Cc: Daniel Vetter
> > Cc: Sean Paul
> > Cc: Jani Nikula
> > Cc: Joonas Lahtinen
> > Cc: Rodrigo Vivi
> > Cc: intel-gfx@lists.freedesktop.org
> > Cc: # v4.17+
> > Signed-off-by: Sean Paul
> >
> > Changes in v2:
> > -Added to the set
> > ---
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 5 +
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index eaab9008feef..c4394c8e10eb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -773,6 +773,7 @@ static int _intel_hdcp_disable(struct intel_connector
> > *connector)
> > struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
> > enum port port = intel_dig_port->base.port;
> > enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
> > + u32 repeater_ctl;
> > int ret;
> >
> > DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n",
> > @@ -787,6 +788,10 @@ static int _intel_hdcp_disable(struct intel_connector
> > *connector)
> > return -ETIMEDOUT;
> > }
> >
> > + repeater_ctl = intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder,
> > + port);
> > + I915_WRITE(HDCP_REP_CTL, I915_READ(HDCP_REP_CTL) & ~repeater_ctl);
> Do you think it will help to (double) clear HDCP_REP_CTL when detect a
> sink which is non repeater!? But yes disable will be executed on all
> HDCP exits.
>
Yeah, that's probably a better idea. I was a little undecided on where to put it
and I think I settled on the disable path since that matches the way we handle
HDCP signalling. However if we always write REP_CTL, that cuts our callsites
back down to 1, which seems like a Good Thing.
Will revise.
Sean
> > +
> LGTM
>
> Reviewed-by: Ramalingam C
>
> > ret = hdcp->shim->toggle_signalling(intel_dig_port, false);
> > if (ret) {
> > DRM_ERROR("Failed to disable HDCP signalling\n");
> > --
> > Sean Paul, Software Engineer, Google / Chromium OS
> >
--
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/gt: Move power management debug files into a gt aware debugfs
On Fri, 13 Dec 2019 19:37:36 +0100, Andi Shyti wrote:
From: Andi Shyti
The GT system is becoming more and more a stand-alone system in
i915 and it's fair to assign it its own debugfs directory.
rc6, rps and llc debugfs files are gt related, move them into the
gt debugfs directory.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/Makefile| 2 +
drivers/gpu/drm/i915/gt/debugfs_gt.c | 22 +
drivers/gpu/drm/i915/gt/debugfs_gt.h | 26 ++
drivers/gpu/drm/i915/gt/debugfs_pm.c | 623 +++
drivers/gpu/drm/i915/gt/debugfs_pm.h | 16 +
drivers/gpu/drm/i915/i915_debugfs.c | 579 +
6 files changed, 698 insertions(+), 570 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt.c
create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt.h
create mode 100644 drivers/gpu/drm/i915/gt/debugfs_pm.c
create mode 100644 drivers/gpu/drm/i915/gt/debugfs_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile
b/drivers/gpu/drm/i915/Makefile
index e0fd10c0cfb8..8f6cdfd08ac8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -75,6 +75,8 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
# "Graphics Technology" (aka we talk to the gpu)
obj-y += gt/
gt-y += \
+ gt/debugfs_gt.o \
+ gt/debugfs_pm.o \
hm, maybe this should be:
gt/intel_gt_debugfs.o
and
gt/intel_pm_debugfs.o
gt/intel_breadcrumbs.o \
gt/intel_context.o \
gt/intel_engine_cs.o \
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c
b/drivers/gpu/drm/i915/gt/debugfs_gt.c
new file mode 100644
index ..3c9dce1cc212
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
in .c SPDX shall start with //
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "debugfs_pm.h"
+#include "i915_trace.h"
+
+int debugfs_gt_init(struct intel_gt *gt)
+{
+ struct dentry *debugfs_root = gt->i915->drm.primary->debugfs_root;
+ struct dentry *gt_root;
+
+ if (!debugfs_root)
+ return -ENODEV;
+
+ gt_root = debugfs_create_dir("gt", debugfs_root);
+ if (IS_ERR(gt_root))
+ return PTR_ERR(gt_root);
+
+ return intel_gt_pm_debugfs_register(gt, gt_root);
+}
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.h
b/drivers/gpu/drm/i915/gt/debugfs_gt.h
new file mode 100644
index ..cac5a3503459
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef DEBUGFS_GT
+#define DEBUGFS_GT
+
+#include "intel_gt_types.h"
+
+#define DEFINE_GT_DEBUGFS_ATTRIBUTE(__name)\
+static int __name ## _open(struct inode *inode, struct file *file) \
+{ \
+ return single_open(file, __name ## _show, inode->i_private); \
+} \
+static const struct file_operations __name ## _fops = {
\
+ .owner = THIS_MODULE, \
+ .open = __name ## _open,\
+ .read = seq_read, \
+ .llseek = seq_lseek,\
+ .release = single_release, \
+}
+
+int debugfs_gt_init(struct intel_gt *gt);
+
+#endif /* DEBUGFS_GT */
diff --git a/drivers/gpu/drm/i915/gt/debugfs_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_pm.c
new file mode 100644
index ..accf8234385c
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/debugfs_pm.c
@@ -0,0 +1,623 @@
+/*
+ * SPDX-License-Identifier: MIT
SPDX shall be in 1st line (starting with //)
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "debugfs_pm.h"
+#include "debugfs_gt.h"
+#include "i915_debugfs.h"
+#include "i915_trace.h"
+#include "intel_rc6.h"
+#include "intel_rps.h"
+#include "intel_sideband.h"
+
+static int forcewake_domains_show(struct seq_file *m, void *data)
+{
+ struct intel_gt *gt = m->private;
+ struct intel_uncore *uncore = gt->uncore;
+ struct intel_uncore_forcewake_domain *fw_domain;
+ unsigned int tmp;
+
+ seq_printf(m, "user.bypass_count = %u\n",
+ uncore->user_forcewake_count);
+
+ for_each_fw_domain(fw_domain, uncore, tmp)
+ seq_printf(m, "%s.wake_count = %u\n",
+ intel_uncore_forcewake_domain_to_str(fw_domain->id),
+ READ_ONCE(fw_domain->wake_count));
+
+ return 0;
+}
+DEFINE_GT_DEBUGFS_ATTRIBUTE(forcewake_domains);
+
+static void print_rc6_res(struct seq_file *m,
+ const char *title,
+ const i915_reg_t reg)
+{
+ struct intel_gt *gt = m->private;
+ intel_wakeref_t wakeref;
+
+
Re: [Intel-gfx] [PATCH v2 07/12] drm/i915: Protect workers against disappearing connectors
On Fri, Dec 13, 2019 at 04:40:33PM +0530, Ramalingam C wrote:
> On 2019-12-12 at 14:02:25 -0500, Sean Paul wrote:
> > From: Sean Paul
> >
> > This patch adds some protection against connectors being destroyed
> > before the HDCP workers are finished.
> >
> > For check_work, we do a synchronous cancel after the connector is
> > unregistered which will ensure that it is finished before destruction.
> >
> > In the case of prop_work, we can't do a synchronous wait since it needs
> > to take connection_mutex which could cause deadlock. Instead, we'll take
> > a reference on the connector when scheduling prop_work and give it up
> > once we're done.
> >
> > Signed-off-by: Sean Paul
> Will there be an instance where prop_work is scheduled but before
> execution cancelled from the queue itself? This will leak the connector
> reference.
No, prop_work is really quite simple, it just grabs some locks and updates the
property value.
>
> Atleast hdcp stack is not requesting for such action. So Looks good to me.
>
> Reviewed-by: Ramalingam C
Thanks, I'm going to dig into what we should do when hdcp_cleanup is called from
connector_init failure paths and revise this patch.
> >
> > Changes in v2:
> > - Added to the set
> > ---
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 38 ---
> > 1 file changed, 33 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 798e7e1a19fc..c79dca2c74d1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -863,8 +863,10 @@ static void intel_hdcp_update_value(struct
> > intel_connector *connector,
> > return;
> >
> > hdcp->value = value;
> > - if (update_property)
> > + if (update_property) {
> > + drm_connector_get(>base);
> > schedule_work(>prop_work);
> > + }
> > }
> >
> > /* Implements Part 3 of the HDCP authorization procedure */
> > @@ -954,6 +956,8 @@ static void intel_hdcp_prop_work(struct work_struct
> > *work)
> >
> > mutex_unlock(>mutex);
> > drm_modeset_unlock(>mode_config.connection_mutex);
> > +
> > + drm_connector_put(>base);
> > }
> >
> > bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
> > @@ -1802,6 +1806,9 @@ static void intel_hdcp_check_work(struct work_struct
> > *work)
> >check_work);
> > struct intel_connector *connector = intel_hdcp_to_connector(hdcp);
> >
> > + if (drm_connector_is_unregistered(>base))
> > + return;
> > +
> > if (!intel_hdcp2_check_link(connector))
> > schedule_delayed_work(>check_work,
> > DRM_HDCP2_CHECK_PERIOD_MS);
> > @@ -2076,12 +2083,33 @@ void intel_hdcp_component_fini(struct
> > drm_i915_private *dev_priv)
> >
> > void intel_hdcp_cleanup(struct intel_connector *connector)
> > {
> > - if (!connector->hdcp.shim)
> > + struct intel_hdcp *hdcp = >hdcp;
> > +
> > + if (!hdcp->shim)
> > return;
> >
> > - mutex_lock(>hdcp.mutex);
> > - kfree(connector->hdcp.port_data.streams);
> > - mutex_unlock(>hdcp.mutex);
> > + WARN_ON(!drm_connector_is_unregistered(>base));
> > +
> > + /*
> > +* Now that the connector is unregistered, check_work won't be run, but
> > +* cancel any outstanding instances of it
> > +*/
> > + cancel_delayed_work_sync(>check_work);
> > +
> > + /*
> > +* We don't cancel prop_work in the same way as check_work since it
> > +* requires connection_mutex which could be held while calling this
> > +* function. Instead, we rely on the connector references grabbed before
> > +* scheduling prop_work to ensure the connector is alive when prop_work
> > +* is run. So if we're in the destroy path (which is where this
> > +* function should be called), we're "guaranteed" that prop_work is not
> > +* active (tl;dr This Should Never Happen).
> > +*/
> > + WARN_ON(work_pending(>prop_work));
> > +
> > + mutex_lock(>mutex);
> > + kfree(hdcp->port_data.streams);
> > + mutex_unlock(>mutex);
> > }
> >
> > void intel_hdcp_atomic_check(struct drm_connector *connector,
> > --
> > Sean Paul, Software Engineer, Google / Chromium OS
> >
--
Sean Paul, Software Engineer, Google / Chromium OS
___
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Re: [Intel-gfx] [PATCH v2 08/12] drm/i915: Don't fully disable HDCP on a port if multiple pipes are using it
On Fri, Dec 13, 2019 at 05:28:25PM +0530, Ramalingam C wrote:
> On 2019-12-12 at 14:02:26 -0500, Sean Paul wrote:
> > From: Sean Paul
> >
> > This patch is required for HDCP over MST. If a port is being used for
> > multiple HDCP streams, we don't want to fully disable HDCP on a port if
> > one of them is disabled. Instead, we just disable the HDCP signalling on
> > that particular pipe and exit early. The last pipe to disable HDCP will
> > also bring down HDCP on the port.
> Sean,
Hey Ram,
Thanks for the quick reviews!
>
> We have a complication here. till ICL this will work as the HDCP
> instance is port based. But from TGL, HDCP is transcoder based.
>
> We need to handle MST HDCP enable and disable differently for <=gen11 and
> >gen11.
> >
> > In order to achieve this, we need to keep a refcount in intel_digital_port
> > and protect it using a new hdcp_mutex.
> >
> > Signed-off-by: Sean Paul
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-8-s...@poorly.run
> > #v1
> >
> > Changes in v2:
> > - Move the toggle_signalling call into _intel_hdcp_disable so it's called
> > from check_work
> > ---
/snip
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -7580,6 +7580,8 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> > intel_encoder = _dig_port->base;
> > encoder = _encoder->base;
> >
> > + mutex_init(_dig_port->hdcp_mutex);
> its initialized at ddi_init itself.
I thought it would be safer to initialize the mutex for non-ddi based DP and
HDMI encoders as well.
> > +
> > if (drm_encoder_init(_priv->drm, _encoder->base,
> > _dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
> > "DP %c", port_name(port)))
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index c79dca2c74d1..fbbd4da7c491 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -779,6 +779,19 @@ static int _intel_
> hdcp_disable(struct intel_connector *connector)
> > DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n",
> > connector->base.name, connector->base.base.id);
> >
> > + /*
> > +* If there are other connectors on this port using HDCP, don't disable
> > +* it. Instead, toggle the HDCP signalling off on that particular
> > +* connector/pipe and exit.
> > +*/
> > + if (intel_dig_port->num_hdcp_streams > 0) {
> > + ret = hdcp->shim->toggle_signalling(intel_dig_port,
> > + cpu_transcoder, false);
> > + if (ret)
> > + DRM_ERROR("Failed to disable HDCP signalling\n");
> > + return ret;
> > + }
> This wont work for TGL+, where HDCP instance is transcoder based. we
> need to disable the HDCP per stream for TGL+
Hmm, I'm not sure how that would work for MST. Presumably you would still have
one port, but multiple transcoders feeding into it? Any chance you could send
me a bspec for HDMI on TGL+ so I can make adjustments? :-)
I also don't have any TGL hardware at my disposal, but hopefully soon.
Sean
> > +
/snip
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index 5066efadca85..905b188782ed 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -3247,6 +3247,8 @@ void intel_hdmi_init(struct drm_i915_private
> > *dev_priv,
> >
> > intel_encoder = _dig_port->base;
> >
> > + mutex_init(_dig_port->hdcp_mutex);
> its initialized at ddi_init itself.
>
> -Ram
> > +
> > drm_encoder_init(_priv->drm, _encoder->base,
> > _hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
> > "HDMI %c", port_name(port));
> > --
> > Sean Paul, Software Engineer, Google / Chromium OS
> >
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Select arb on/off around batches based on preemption
== Series Details ==
Series: drm/i915/execlists: Select arb on/off around batches based on preemption
URL : https://patchwork.freedesktop.org/series/70885/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7560 -> Patchwork_15748
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15748/index.html
Known issues
Here are the changes found in Patchwork_15748 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_close_race@basic-threads:
- fi-byt-j1900: [PASS][1] -> [TIMEOUT][2] ([i915#816])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-byt-j1900/igt@gem_close_r...@basic-threads.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15748/fi-byt-j1900/igt@gem_close_r...@basic-threads.html
* igt@gem_exec_gttfill@basic:
- fi-tgl-y: [PASS][3] -> [INCOMPLETE][4] ([fdo#111593])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-tgl-y/igt@gem_exec_gttf...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15748/fi-tgl-y/igt@gem_exec_gttf...@basic.html
* igt@i915_module_load@reload-no-display:
- fi-skl-lmem:[PASS][5] -> [DMESG-WARN][6] ([i915#592])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-skl-lmem/igt@i915_module_l...@reload-no-display.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15748/fi-skl-lmem/igt@i915_module_l...@reload-no-display.html
Possible fixes
* igt@gem_close_race@basic-threads:
- fi-byt-n2820: [TIMEOUT][7] ([i915#816]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-byt-n2820/igt@gem_close_r...@basic-threads.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15748/fi-byt-n2820/igt@gem_close_r...@basic-threads.html
* igt@i915_selftest@live_blt:
- fi-bsw-n3050: [DMESG-FAIL][9] ([i915#723]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-bsw-n3050/igt@i915_selftest@live_blt.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15748/fi-bsw-n3050/igt@i915_selftest@live_blt.html
- fi-hsw-4770:[DMESG-FAIL][11] ([i915#725]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-hsw-4770/igt@i915_selftest@live_blt.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15748/fi-hsw-4770/igt@i915_selftest@live_blt.html
Warnings
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [DMESG-FAIL][13] -> [DMESG-FAIL][14] ([i915#563])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15748/fi-hsw-4770r/igt@i915_selftest@live_blt.html
* igt@kms_busy@basic-flip-pipe-b:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) ->
[DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +7 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-kbl-x1275/igt@kms_b...@basic-flip-pipe-b.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15748/fi-kbl-x1275/igt@kms_b...@basic-flip-pipe-b.html
* igt@kms_flip@basic-flip-vs-modeset:
- fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][18] ([i915#62] / [i915#92]) +3 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-kbl-x1275/igt@kms_f...@basic-flip-vs-modeset.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15748/fi-kbl-x1275/igt@kms_f...@basic-flip-vs-modeset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476
[i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
[i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#723]: https://gitlab.freedesktop.org/drm/intel/issues/723
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (55 -> 47)
--
Missing(8): fi-icl-1065g7 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7560 -> Patchwork_15748
CI-20190529: 20190529
CI_DRM_7560: c093691eb61cb4680e44a339660e9443e728ef67 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5349:
Re: [Intel-gfx] [PATCH v8 3/4] drm/i915: Manipulate DBuf slices properly
On Fri, Dec 13, 2019 at 03:02:27PM +0200, Stanislav Lisovskiy wrote:
> Start manipulating DBuf slices as a mask,
> but not as a total number, as current approach
> doesn't give us full control on all combinations
> of slices, which we might need(like enabling S2
> only can't enabled by setting enabled_slices=1).
>
> Removed wrong code from intel_get_ddb_size as
> it doesn't match to BSpec. For now still just
> use DBuf slice until proper algorithm is implemented.
>
> Other minor code refactoring to get prepared
> for major DBuf assignment changes landed:
> - As now enabled slices contain a mask
> we still need some value which should
> reflect how much DBuf slices are supported
> by the platform, now device info contains
> num_supported_dbuf_slices.
> - Removed unneeded assertion as we are now
> manipulating slices in a more proper way.
>
> v2: Start using enabled_slices in dev_priv
>
> v3: "enabled_slices" is now "enabled_dbuf_slices_mask",
> as this now sits in dev_priv independently.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 23 ++--
> .../drm/i915/display/intel_display_power.c| 100 --
> .../drm/i915/display/intel_display_power.h| 5 +
> .../drm/i915/display/intel_display_types.h| 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_pci.c | 6 +-
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 49 +++--
> drivers/gpu/drm/i915/intel_pm.h | 2 +-
> 9 files changed, 84 insertions(+), 106 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 0e09d0c23b1d..42a0ea540d4f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13359,12 +13359,12 @@ static void verify_wm_state(struct intel_crtc *crtc,
>
> skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
>
> - hw_enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
> + hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
>
> if (INTEL_GEN(dev_priv) >= 11 &&
> - hw_enabled_slices != dev_priv->enabled_dbuf_slices_num)
> - DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
> - dev_priv->enabled_dbuf_slices_num,
> + hw_enabled_slices != dev_priv->enabled_dbuf_slices_mask)
> + DRM_ERROR("mismatch in DBUF Slices (expected %x, got %x)\n",
Minor nitpick: I'd write these with "0x%x" to make it more obvious to
the person reading the message that the value is hex and thus a bitmask
rather than a count.
> + dev_priv->enabled_dbuf_slices_mask,
> hw_enabled_slices);
>
> /* planes */
> @@ -14549,22 +14549,23 @@ static void
> intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
> static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_num;
> - u8 required_slices = state->enabled_dbuf_slices_num;
> + u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_mask;
> + u8 required_slices = state->enabled_dbuf_slices_mask;
> + u8 slices_union = hw_enabled_slices | required_slices;
>
> /* If 2nd DBuf slice required, enable it here */
> - if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
> - icl_dbuf_slices_update(dev_priv, required_slices);
> + if (INTEL_GEN(dev_priv) >= 11 && required_slices != hw_enabled_slices)
Should this be hw_enabled_slices != slices_union so that we only process
it when we're adding new slices and not in cases where we're only going
to be taking slices away?
> + icl_dbuf_slices_update(dev_priv, slices_union);
> }
>
> static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_num;
> - u8 required_slices = state->enabled_dbuf_slices_num;
> + u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_mask;
> + u8 required_slices = state->enabled_dbuf_slices_mask;
>
> /* If 2nd DBuf slice is no more required disable it */
> - if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
> + if (INTEL_GEN(dev_priv) >= 11 && required_slices != hw_enabled_slices)
> icl_dbuf_slices_update(dev_priv, required_slices);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index b8983422a882..ba384a5315f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++
[Intel-gfx] ✗ Fi.CI.IGT: failure for AUX power well fixes (rev4)
== Series Details == Series: AUX power well fixes (rev4) URL : https://patchwork.freedesktop.org/series/70857/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7554_full -> Patchwork_15737_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15737_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15737_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15737_full: ### Piglit changes ### Possible regressions * spec@glsl-1.30@execution@texelfetch@fs-texelfetch-isampler1darray (NEW): - pig-hsw-4770r: NOTRUN -> [FAIL][1] +1292 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15737/pig-hsw-4770r/spec@glsl-1.30@execution@texelfe...@fs-texelfetch-isampler1darray.html New tests - New tests have been introduced between CI_DRM_7554_full and Patchwork_15737_full: ### New Piglit tests (1200) ### * hiz@hiz-depth-read-fbo-d24-s8: - Statuses : 1 fail(s) - Exec time: [0.10] s * object namespace pollution@texture with glclear: - Statuses : 1 fail(s) - Exec time: [0.16] s * object namespace pollution@texture with glgeneratemipmap: - Statuses : 1 fail(s) - Exec time: [0.13] s * object namespace pollution@texture with gltexsubimage2d: - Statuses : 1 fail(s) - Exec time: [0.25] s * spec@!opengl 1.1@teximage-colors gl_alpha: - Statuses : 1 fail(s) - Exec time: [0.25] s * spec@!opengl 1.1@teximage-colors gl_alpha12: - Statuses : 1 fail(s) - Exec time: [0.30] s * spec@!opengl 1.1@teximage-colors gl_alpha16: - Statuses : 1 fail(s) - Exec time: [0.31] s * spec@!opengl 1.1@teximage-colors gl_alpha4: - Statuses : 1 fail(s) - Exec time: [0.39] s * spec@!opengl 1.1@teximage-colors gl_alpha8: - Statuses : 1 fail(s) - Exec time: [0.34] s * spec@!opengl 1.1@teximage-colors gl_luminance: - Statuses : 1 fail(s) - Exec time: [0.32] s * spec@!opengl 1.1@teximage-colors gl_luminance12: - Statuses : 1 fail(s) - Exec time: [0.35] s * spec@!opengl 1.1@teximage-colors gl_luminance12_alpha12: - Statuses : 1 fail(s) - Exec time: [0.32] s * spec@!opengl 1.1@teximage-colors gl_luminance12_alpha4: - Statuses : 1 fail(s) - Exec time: [0.30] s * spec@!opengl 1.1@teximage-colors gl_luminance16: - Statuses : 1 fail(s) - Exec time: [0.28] s * spec@!opengl 1.1@teximage-colors gl_luminance16_alpha16: - Statuses : 1 fail(s) - Exec time: [0.28] s * spec@!opengl 1.1@teximage-colors gl_luminance4: - Statuses : 1 fail(s) - Exec time: [0.36] s * spec@!opengl 1.1@teximage-colors gl_luminance4_alpha4: - Statuses : 1 fail(s) - Exec time: [0.31] s * spec@!opengl 1.1@teximage-colors gl_luminance6_alpha2: - Statuses : 1 fail(s) - Exec time: [0.35] s * spec@!opengl 1.1@teximage-colors gl_luminance8: - Statuses : 1 fail(s) - Exec time: [0.34] s * spec@!opengl 1.1@teximage-colors gl_luminance8_alpha8: - Statuses : 1 fail(s) - Exec time: [0.36] s * spec@!opengl 1.1@teximage-colors gl_luminance_alpha: - Statuses : 1 fail(s) - Exec time: [0.34] s * spec@!opengl 1.1@teximage-colors gl_rgb10_a2: - Statuses : 1 fail(s) - Exec time: [0.31] s * spec@!opengl 1.1@teximage-colors gl_rgb16_snorm: - Statuses : 1 fail(s) - Exec time: [5.20] s * spec@!opengl 1.1@teximage-colors gl_rgb16f: - Statuses : 1 fail(s) - Exec time: [5.18] s * spec@!opengl 1.1@teximage-colors gl_rgb32f: - Statuses : 1 fail(s) - Exec time: [5.21] s * spec@!opengl 1.1@teximage-colors gl_rgb5_a1: - Statuses : 1 fail(s) - Exec time: [0.29] s * spec@!opengl 1.1@teximage-colors gl_rgba: - Statuses : 1 fail(s) - Exec time: [5.15] s * spec@!opengl 1.1@teximage-colors gl_rgba12: - Statuses : 1 fail(s) - Exec time: [0.34] s * spec@!opengl 1.1@teximage-colors gl_rgba16: - Statuses : 1 fail(s) - Exec time: [0.29] s * spec@!opengl 1.1@teximage-colors gl_rgba16_snorm: - Statuses : 1 fail(s) - Exec time: [0.26] s * spec@!opengl 1.1@teximage-colors gl_rgba2: - Statuses : 1 fail(s) - Exec time: [0.31] s * spec@!opengl 1.1@teximage-colors gl_rgba32f: - Statuses : 1 fail(s) - Exec time: [0.25] s * spec@!opengl 1.1@teximage-colors gl_rgba4: - Statuses : 1 fail(s) - Exec time: [0.33] s * spec@!opengl 1.1@teximage-colors gl_rgba8: - Statuses : 1 fail(s) - Exec time: [0.27] s * spec@!opengl 1.1@teximage-colors gl_rgba8_snorm: - Statuses : 1 fail(s) - Exec time: [0.30] s * spec@!opengl
[Intel-gfx] [PATCH v4 1/2] drm/i915/rps: Add frequency translation helpers
From: Andi Shyti
Add two helpers that for reading the actual GT's frequency. The
two helpers are:
- intel_rps_read_cagf: reads the frequency and returns it not
normalized
- intel_rps_read_actual_frequency: provides the frequency in Hz.
Use the above helpers in sysfs and debugfs.
Signed-off-by: Andi Shyti
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_rps.c | 30 +
drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++
drivers/gpu/drm/i915/i915_debugfs.c | 21 +---
drivers/gpu/drm/i915/i915_sysfs.c | 14 ++
4 files changed, 39 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 106c9fce9d6c..370a11819d6f 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1682,6 +1682,36 @@ u32 intel_get_cagf(struct intel_rps *rps, u32 rpstat)
return cagf;
}
+u32 intel_rps_read_cagf(struct intel_rps *rps)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ u32 freq;
+
+ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+ vlv_punit_get(i915);
+ freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
+ vlv_punit_put(i915);
+
+ return (freq >> 8) & 0xff;
+ }
+
+ return intel_get_cagf(rps, intel_uncore_read(rps_to_gt(rps)->uncore,
+GEN6_RPSTAT1));
+}
+
+u32 intel_rps_read_actual_frequency(struct intel_rps *rps)
+{
+ struct intel_runtime_pm *rpm = rps_to_gt(rps)->uncore->rpm;
+ intel_wakeref_t wakeref;
+ int freq;
+
+ wakeref = intel_runtime_pm_get(rpm);
+ freq = intel_gpu_freq(rps, intel_rps_read_cagf(rps));
+ intel_runtime_pm_put(rpm, wakeref);
+
+ return freq;
+}
+
/* External interface for intel_ips.ko */
static struct drm_i915_private __rcu *ips_mchdev;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h
b/drivers/gpu/drm/i915/gt/intel_rps.h
index 9518c66c9792..bd12a63ecd4a 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -30,6 +30,8 @@ void intel_rps_mark_interactive(struct intel_rps *rps, bool
interactive);
int intel_gpu_freq(struct intel_rps *rps, int val);
int intel_freq_opcode(struct intel_rps *rps, int val);
u32 intel_get_cagf(struct intel_rps *rps, u32 rpstat1);
+u32 intel_rps_read_cagf(struct intel_rps *rps);
+u32 intel_rps_read_actual_frequency(struct intel_rps *rps);
void gen5_rps_irq_handler(struct intel_rps *rps);
void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9cd5ce5bc93b..3ec26b6a48c1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -881,7 +881,7 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) &
GEN6_CURBSYTAVG_MASK;
- cagf = intel_gpu_freq(rps, intel_get_cagf(rps, rpstat));
+ cagf = intel_rps_read_actual_frequency(rps);
intel_uncore_forcewake_put(_priv->uncore, FORCEWAKE_ALL);
@@ -1623,21 +1623,11 @@ static int i915_rps_boost_info(struct seq_file *m, void
*data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_rps *rps = _priv->gt.rps;
- u32 act_freq = rps->cur_freq;
+ u32 act_freq;
intel_wakeref_t wakeref;
- with_intel_runtime_pm_if_in_use(_priv->runtime_pm, wakeref) {
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- vlv_punit_get(dev_priv);
- act_freq = vlv_punit_read(dev_priv,
- PUNIT_REG_GPU_FREQ_STS);
- vlv_punit_put(dev_priv);
- act_freq = (act_freq >> 8) & 0xff;
- } else {
- act_freq = intel_get_cagf(rps,
- I915_READ(GEN6_RPSTAT1));
- }
- }
+ with_intel_runtime_pm_if_in_use(_priv->runtime_pm, wakeref)
+ act_freq = intel_rps_read_actual_frequency(rps);
seq_printf(m, "RPS enabled? %d\n", rps->enabled);
seq_printf(m, "GPU busy? %s\n", yesno(dev_priv->gt.awake));
@@ -1645,8 +1635,7 @@ static int i915_rps_boost_info(struct seq_file *m, void
*data)
atomic_read(>num_waiters));
seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
seq_printf(m, "Frequency requested %d, actual %d\n",
- intel_gpu_freq(rps, rps->cur_freq),
- intel_gpu_freq(rps, act_freq));
+
[Intel-gfx] [PATCH v4 2/2] drm/i915/gt: Move power management debug files into a gt aware debugfs
From: Andi Shyti
The GT system is becoming more and more a stand-alone system in
i915 and it's fair to assign it its own debugfs directory.
rc6, rps and llc debugfs files are gt related, move them into the
gt debugfs directory.
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/Makefile| 2 +
drivers/gpu/drm/i915/gt/debugfs_gt.c | 22 +
drivers/gpu/drm/i915/gt/debugfs_gt.h | 26 ++
drivers/gpu/drm/i915/gt/debugfs_pm.c | 623 +++
drivers/gpu/drm/i915/gt/debugfs_pm.h | 16 +
drivers/gpu/drm/i915/i915_debugfs.c | 579 +
6 files changed, 698 insertions(+), 570 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt.c
create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt.h
create mode 100644 drivers/gpu/drm/i915/gt/debugfs_pm.c
create mode 100644 drivers/gpu/drm/i915/gt/debugfs_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e0fd10c0cfb8..8f6cdfd08ac8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -75,6 +75,8 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
# "Graphics Technology" (aka we talk to the gpu)
obj-y += gt/
gt-y += \
+ gt/debugfs_gt.o \
+ gt/debugfs_pm.o \
gt/intel_breadcrumbs.o \
gt/intel_context.o \
gt/intel_engine_cs.o \
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c
b/drivers/gpu/drm/i915/gt/debugfs_gt.c
new file mode 100644
index ..3c9dce1cc212
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "debugfs_pm.h"
+#include "i915_trace.h"
+
+int debugfs_gt_init(struct intel_gt *gt)
+{
+ struct dentry *debugfs_root = gt->i915->drm.primary->debugfs_root;
+ struct dentry *gt_root;
+
+ if (!debugfs_root)
+ return -ENODEV;
+
+ gt_root = debugfs_create_dir("gt", debugfs_root);
+ if (IS_ERR(gt_root))
+ return PTR_ERR(gt_root);
+
+ return intel_gt_pm_debugfs_register(gt, gt_root);
+}
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.h
b/drivers/gpu/drm/i915/gt/debugfs_gt.h
new file mode 100644
index ..cac5a3503459
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef DEBUGFS_GT
+#define DEBUGFS_GT
+
+#include "intel_gt_types.h"
+
+#define DEFINE_GT_DEBUGFS_ATTRIBUTE(__name)\
+static int __name ## _open(struct inode *inode, struct file *file) \
+{ \
+ return single_open(file, __name ## _show, inode->i_private);\
+} \
+static const struct file_operations __name ## _fops = {
\
+ .owner = THIS_MODULE, \
+ .open = __name ## _open,\
+ .read = seq_read, \
+ .llseek = seq_lseek,\
+ .release = single_release, \
+}
+
+int debugfs_gt_init(struct intel_gt *gt);
+
+#endif /* DEBUGFS_GT */
diff --git a/drivers/gpu/drm/i915/gt/debugfs_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_pm.c
new file mode 100644
index ..accf8234385c
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/debugfs_pm.c
@@ -0,0 +1,623 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "debugfs_pm.h"
+#include "debugfs_gt.h"
+#include "i915_debugfs.h"
+#include "i915_trace.h"
+#include "intel_rc6.h"
+#include "intel_rps.h"
+#include "intel_sideband.h"
+
+static int forcewake_domains_show(struct seq_file *m, void *data)
+{
+ struct intel_gt *gt = m->private;
+ struct intel_uncore *uncore = gt->uncore;
+ struct intel_uncore_forcewake_domain *fw_domain;
+ unsigned int tmp;
+
+ seq_printf(m, "user.bypass_count = %u\n",
+ uncore->user_forcewake_count);
+
+ for_each_fw_domain(fw_domain, uncore, tmp)
+ seq_printf(m, "%s.wake_count = %u\n",
+ intel_uncore_forcewake_domain_to_str(fw_domain->id),
+ READ_ONCE(fw_domain->wake_count));
+
+ return 0;
+}
+DEFINE_GT_DEBUGFS_ATTRIBUTE(forcewake_domains);
+
+static void print_rc6_res(struct seq_file *m,
+ const char *title,
+ const i915_reg_t reg)
+{
+ struct intel_gt *gt = m->private;
+ intel_wakeref_t wakeref;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ seq_printf(m, "%s %u (%llu us)\n", title,
+ intel_uncore_read(gt->uncore, reg),
+ intel_rc6_residency_us(>rc6, reg));
+}
+
[Intel-gfx] [PATCH v4 0/2] Some debugfs enhancements
From: Andi Shyti Hi, this two patches are few debugfs improvements. The first adds some helpers for reading the GT frequency, while the second patch moves all the power management debufs functions into gt/ Thanks Chris for the reviews. Thanks, Andi Changelog: == v3-v4: (v3: https://lists.freedesktop.org/archives/intel-gfx/2019-December/223368.html) - added wakeref in frequency reading (patch 1) - added Chris reviewed-by in patch 1 - sorted in alphabetical order the debugfs functions - removed dentry reference in the gt structure, because it's useless. v2-v3: (v2: https://lists.freedesktop.org/archives/intel-gfx/2019-December/223277.html) Fixed the three reviews from Chris - removed the 'i915' prefix from the gt pm debugfs files - fixed my laziness and made the debugfs pm files more gt oriented. Now the only dependency remaining from the 'drm_i915_private' structure is for platform generation check. - restored the 'node_to_i915' to its original position, as it's not needed anymore. v1-v2: (v1: https://lists.freedesktop.org/archives/intel-gfx/2019-December/222758.html) - renamed functions from intel_cagf_freq_read to intel_rps_read_actual_frequency intel_cagf_read to intel_rps_read_cagf - created an independent gt/ directory in debugfs Andi Shyti (2): drm/i915/rps: Add frequency translation helpers drm/i915/gt: Move power management debug files into a gt aware debugfs drivers/gpu/drm/i915/Makefile| 2 + drivers/gpu/drm/i915/gt/debugfs_gt.c | 22 + drivers/gpu/drm/i915/gt/debugfs_gt.h | 26 ++ drivers/gpu/drm/i915/gt/debugfs_pm.c | 623 +++ drivers/gpu/drm/i915/gt/debugfs_pm.h | 16 + drivers/gpu/drm/i915/gt/intel_rps.c | 30 ++ drivers/gpu/drm/i915/gt/intel_rps.h | 2 + drivers/gpu/drm/i915/i915_debugfs.c | 590 + drivers/gpu/drm/i915/i915_sysfs.c| 14 +- 9 files changed, 732 insertions(+), 593 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt.c create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt.h create mode 100644 drivers/gpu/drm/i915/gt/debugfs_pm.c create mode 100644 drivers/gpu/drm/i915/gt/debugfs_pm.h -- 2.24.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support (rev14)
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev14)
URL : https://patchwork.freedesktop.org/series/68028/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7560 -> Patchwork_15747
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15747/index.html
Known issues
Here are the changes found in Patchwork_15747 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_sync@basic-each:
- fi-tgl-y: [PASS][1] -> [INCOMPLETE][2] ([i915#707])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-tgl-y/igt@gem_s...@basic-each.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15747/fi-tgl-y/igt@gem_s...@basic-each.html
* igt@i915_selftest@live_blt:
- fi-ivb-3770:[PASS][3] -> [DMESG-FAIL][4] ([i915#563])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-ivb-3770/igt@i915_selftest@live_blt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15747/fi-ivb-3770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-byt-j1900: [PASS][5] -> [DMESG-FAIL][6] ([i915#722])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15747/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
- fi-cfl-8700k: [PASS][7] -> [DMESG-FAIL][8] ([i915#730])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15747/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
- fi-hsw-peppy: [PASS][9] -> [INCOMPLETE][10] ([i915#694])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15747/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-skl-6700k2: [PASS][11] -> [INCOMPLETE][12] ([i915#69])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15747/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][13] -> [FAIL][14] ([fdo#111096] / [i915#323])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15747/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@gem_close_race@basic-threads:
- fi-byt-n2820: [TIMEOUT][15] ([i915#816]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-byt-n2820/igt@gem_close_r...@basic-threads.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15747/fi-byt-n2820/igt@gem_close_r...@basic-threads.html
* igt@i915_selftest@live_blt:
- fi-bsw-n3050: [DMESG-FAIL][17] ([i915#723]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-bsw-n3050/igt@i915_selftest@live_blt.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15747/fi-bsw-n3050/igt@i915_selftest@live_blt.html
- fi-hsw-4770r: [DMESG-FAIL][19] -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15747/fi-hsw-4770r/igt@i915_selftest@live_blt.html
Warnings
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) ->
[DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +6 similar issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15747/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html
* igt@kms_flip@basic-flip-vs-modeset:
- fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][24] ([i915#62] / [i915#92]) +5 similar issues
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7560/fi-kbl-x1275/igt@kms_f...@basic-flip-vs-modeset.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15747/fi-kbl-x1275/igt@kms_f...@basic-flip-vs-modeset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[i915#323]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev14)
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev14)
URL : https://patchwork.freedesktop.org/series/68028/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
455914397efd drm/i915: Refactor intel_can_enable_sagv
-:728: WARNING:LONG_LINE: line over 100 characters
#728: FILE: drivers/gpu/drm/i915/intel_pm.c:5766:
+
_crtc_state->wm.skl.optimal.planes[plane_id])) {
total: 0 errors, 1 warnings, 0 checks, 674 lines checked
0da0e3056a02 drm/i915: Restrict qgv points which don't have enough bandwidth.
8a5a4b77d79a drm/i915: Enable SAGV support for Gen12
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Re: [Intel-gfx] [PATCH v4 3/3] drm/i915/icl: Cleanup combo PHY aux power well handlers
On Thu, Dec 12, 2019 at 05:06:00PM -0800, Matt Roper wrote:
Now that the combo PHY aux power well handlers are used exclusively on
Icelake, we can drop a bunch of the extra tests.
v2: Don't try to use intel_uncore_rmw for register updates yet; there's
pending display uncore patches that need to land first. (Lucas)
v3: Drop the combo phy assertion. It was backward before, but doesn't
seem terribly necessary. I'm keeping the IS_ICELAKE assertion
though since we often copy/paste/modify the power well tables when
defining new platforms and it's too easy to cargo cult the
ICL-specific handling to new platforms that shouldn't use it.
(Lucas)
v4: Fix build; forgot to commit all the changes. (CI)
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_power.c| 20 +++
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 52f2332e0ab8..d59539002aaa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -418,7 +418,8 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private
*dev_priv,
int pw_idx = power_well->desc->hsw.idx;
enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
u32 val;
- int wa_idx_max;
+
+ WARN_ON(!IS_ICELAKE(dev_priv));
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
@@ -430,14 +431,7 @@ icl_combo_phy_aux_power_well_enable(struct
drm_i915_private *dev_priv,
hsw_wait_for_power_well_enable(dev_priv, power_well);
- /* Display WA #1178: icl, tgl */
this comment must stay
Otherwise
Reviewed-by: Lucas De Marchi
Lucas De Marchi
- if (IS_TIGERLAKE(dev_priv))
- wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
- else
- wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
-
- if (!IS_ELKHARTLAKE(dev_priv) &&
- pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= wa_idx_max &&
+ if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
!intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
@@ -454,10 +448,10 @@ icl_combo_phy_aux_power_well_disable(struct
drm_i915_private *dev_priv,
enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
u32 val;
- if (INTEL_GEN(dev_priv) < 12) {
- val = I915_READ(ICL_PORT_CL_DW12(phy));
- I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
- }
+ WARN_ON(!IS_ICELAKE(dev_priv));
+
+ val = I915_READ(ICL_PORT_CL_DW12(phy));
+ I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
--
2.23.0
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Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/tgl: Drop Wa#1178
On Thu, Dec 12, 2019 at 04:15:10PM -0800, Matt Roper wrote:
The TGL workaround database no longer shows Wa #1178 (or anything
similar under different workaround names/numbers) so we should be able
to drop it. In fact Swati just discovered that applying this workaround
is the root cause of some power well enable failures we've been seeing
in CI (gitlab issue 498).
Once we stop applying this WA, TGL no longer utilizes any of the special
handling provided by icl_combo_phy_aux_power_well_ops so we can just
drop back to using the standard hsw-style power well ops instead.
v3: Drop now-unused _TGL_AUX_ANAOVRD1_C definition too. (Lucas)
Closes: https://gitlab.freedesktop.org/drm/intel/issues/498
Fixes: deea06b47574 ("drm/i915/tgl: apply Display WA #1178 to fix type C
dongles")
Cc: Lucas De Marchi
Cc: Swati Sharma
Cc: Imre Deak
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi # v1
still stands on this rev
Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
drivers/gpu/drm/i915/i915_reg.h| 4 +---
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index cf34427cc840..52f2332e0ab8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -3977,7 +3977,7 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
{
.name = "AUX A",
.domains = TGL_AUX_A_IO_POWER_DOMAINS,
- .ops = _combo_phy_aux_power_well_ops,
+ .ops = _power_well_ops,
.id = DISP_PW_ID_NONE,
{
.hsw.regs = _aux_power_well_regs,
@@ -3987,7 +3987,7 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
{
.name = "AUX B",
.domains = TGL_AUX_B_IO_POWER_DOMAINS,
- .ops = _combo_phy_aux_power_well_ops,
+ .ops = _power_well_ops,
.id = DISP_PW_ID_NONE,
{
.hsw.regs = _aux_power_well_regs,
@@ -3997,7 +3997,7 @@ static const struct i915_power_well_desc
tgl_power_wells[] = {
{
.name = "AUX C",
.domains = TGL_AUX_C_IO_POWER_DOMAINS,
- .ops = _combo_phy_aux_power_well_ops,
+ .ops = _power_well_ops,
.id = DISP_PW_ID_NONE,
{
.hsw.regs = _aux_power_well_regs,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 17f9dd3bda72..cbb4689af432 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9437,11 +9437,9 @@ enum skl_power_gate {
#define _ICL_AUX_REG_IDX(pw_idx)((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
#define _ICL_AUX_ANAOVRD1_A 0x162398
#define _ICL_AUX_ANAOVRD1_B 0x6C398
-#define _TGL_AUX_ANAOVRD1_C0x160398
#define ICL_AUX_ANAOVRD1(pw_idx)_MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
_ICL_AUX_ANAOVRD1_A, \
- _ICL_AUX_ANAOVRD1_B, \
- _TGL_AUX_ANAOVRD1_C))
+ _ICL_AUX_ANAOVRD1_B))
#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
--
2.23.0
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Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/ehl: Define EHL powerwells independently of ICL
On Thu, Dec 12, 2019 at 04:15:09PM -0800, Matt Roper wrote:
Outputs C and D on EHL are combo PHY outputs and thus should not be
using the same TC AUX power well handlers as ICL. And even though
icl_combo_phy_aux_power_well_ops works okay for EHL/JSL combo PHYs none
of its special handling is actually necessary for this platform:
* EHL/JSL don't actually need to program PORT_CL_DW12
* Display WA #1178 does not apply to EHL/JSL
Thus we can simply drop back to using our standard "hsw-style" power
well ops for EHL AUX power wells.
Bspec: 4301
Fixes: f722b8c1e2a2 ("drm/i915/ehl: All EHL ports are combo phys")
Cc: Jose Souza
Cc: Bob Paauwe
Cc: Vivek Kasireddy
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
I find it odd that ehl/jsl supposedly use the same combo phy as ICL. So
I would expect the same WA to apply there too. But if hw people (who
know more than me) disagree then
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
.../drm/i915/display/intel_display_power.c| 147 ++
1 file changed, 147 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0b3dd2a3b94d..cf34427cc840 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -3688,6 +3688,151 @@ static const struct i915_power_well_desc
icl_power_wells[] = {
},
};
+static const struct i915_power_well_desc ehl_power_wells[] = {
+ {
+ .name = "always-on",
+ .always_on = true,
+ .domains = POWER_DOMAIN_MASK,
+ .ops = _always_on_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ },
+ {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .always_on = true,
+ .domains = 0,
+ .ops = _power_well_ops,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.regs = _power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "DC off",
+ .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = _dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ },
+ {
+ .name = "power well 2",
+ .domains = ICL_PW_2_POWER_DOMAINS,
+ .ops = _power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.regs = _power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "power well 3",
+ .domains = ICL_PW_3_POWER_DOMAINS,
+ .ops = _power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = _power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ },
+ {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = _power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = _ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ },
+ },
+ {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = _power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = _ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ },
+ },
+ {
+ .name = "DDI C IO",
+ .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .ops = _power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = _ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
+ },
+ },
+ {
+ .name = "DDI D IO",
+ .domains = ICL_DDI_IO_D_POWER_DOMAINS,
+ .ops = _power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = _ddi_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
+ },
+ },
+ {
+ .name = "AUX A",
+ .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .ops = _power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.regs = _aux_power_well_regs,
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ },
+ },
+ {
+ .name = "AUX B",
+
[Intel-gfx] [PATCH v4 2/4] drm/edid: Add CTA-861-G modes with VIC >= 193
From: Ville Syrjälä
Add a second table to the cea modes with VIC >= 193.
v2: Improve the comment for cea_modes_*[] to indicate
that one should always use cea_mode_for_vic() (Tom)
Cc: Hans Verkuil
Reviewed-by: Manasi Navare
Reviewed-by: Thomas Anderson
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 151 -
1 file changed, 149 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 00a543b9daab..2787ad0ef881 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1379,6 +1379,149 @@ static const struct drm_display_mode edid_cea_modes_0[]
= {
.vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
};
+/*
+ * From CEA/CTA-861 spec.
+ *
+ * Do not access directly, instead always use cea_mode_for_vic().
+ */
+static const struct drm_display_mode edid_cea_modes_193[] = {
+ /* 193 - 5120x2160@120Hz 64:27 */
+ { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
+ 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+ /* 194 - 7680x4320@24Hz 16:9 */
+ { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
+ 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+ /* 195 - 7680x4320@25Hz 16:9 */
+ { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
+ 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+ /* 196 - 7680x4320@30Hz 16:9 */
+ { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
+ 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+ /* 197 - 7680x4320@48Hz 16:9 */
+ { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
+ 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+ /* 198 - 7680x4320@50Hz 16:9 */
+ { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
+ 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+ /* 199 - 7680x4320@60Hz 16:9 */
+ { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
+ 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+ /* 200 - 7680x4320@100Hz 16:9 */
+ { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
+ 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+ /* 201 - 7680x4320@120Hz 16:9 */
+ { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
+ 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+ /* 202 - 7680x4320@24Hz 64:27 */
+ { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
+ 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+ /* 203 - 7680x4320@25Hz 64:27 */
+ { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
+ 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+ /* 204 - 7680x4320@30Hz 64:27 */
+ { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
+ 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+ /* 205 - 7680x4320@48Hz 64:27 */
+ { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
+ 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
+
[Intel-gfx] [PATCH v4 0/4] drm/edid: Add new modes from CTA-861-G
From: Ville Syrjälä Review feedback addressed. I considered changing the approach based on Tom's comments but in the end decided that probably better to go with this for now. We can massage it later if required. Cc: Hans Verkuil Cc: Manasi Navare Cc: Thomas Anderson Ville Syrjälä (4): drm/edid: Abstract away cea_edid_modes[] drm/edid: Add CTA-861-G modes with VIC >= 193 drm/edid: Throw away the dummy VIC 0 cea mode drm/edid: Make sure the CEA mode arrays have the correct amount of modes drivers/gpu/drm/drm_edid.c | 217 + 1 file changed, 193 insertions(+), 24 deletions(-) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 3/4] drm/edid: Throw away the dummy VIC 0 cea mode
From: Ville Syrjälä
Now that the cea mode handling is not 100% tied to the single
array the dummy VIC 0 mode is pretty much pointles. Throw it
out.
v2: Rebase
Cc: Tom Anderson
Cc: Hans Verkuil
Cc: Manasi Navare
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 2787ad0ef881..8bc69da53c2e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -714,9 +714,7 @@ static const struct minimode extra_modes[] = {
*
* Do not access directly, instead always use cea_mode_for_vic().
*/
-static const struct drm_display_mode edid_cea_modes_0[] = {
- /* 0 - dummy, VICs start at 1 */
- { },
+static const struct drm_display_mode edid_cea_modes_1[] = {
/* 1 - 640x480@60Hz 4:3 */
{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
752, 800, 0, 480, 490, 492, 525, 0,
@@ -3215,10 +3213,8 @@ static u8 *drm_find_cea_extension(const struct edid
*edid)
static const struct drm_display_mode *cea_mode_for_vic(u8 vic)
{
- if (!vic)
- return NULL;
- if (vic < ARRAY_SIZE(edid_cea_modes_0))
- return _cea_modes_0[vic];
+ if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
+ return _cea_modes_1[vic - 1];
if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
return _cea_modes_193[vic - 193];
return NULL;
@@ -3231,7 +3227,7 @@ static u8 cea_num_vics(void)
static u8 cea_next_vic(u8 vic)
{
- if (++vic == ARRAY_SIZE(edid_cea_modes_0))
+ if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
vic = 193;
return vic;
}
--
2.23.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 4/4] drm/edid: Make sure the CEA mode arrays have the correct amount of modes
From: Ville Syrjälä
We depend on a specific relationship between the VIC number and the
index in the CEA mode arrays. Assert that the arrays have the expected
size to make sure we've not accidentally left holes in them.
v2: Pimp the BUILD_BUG_ON()s
v3: Fix typos (Manasi)
Cc: Hans Verkuil
Reviewed-by: Manasi Navare
Reviewed-by: Thomas Anderson
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 8bc69da53c2e..ec5b88120428 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3213,6 +3213,9 @@ static u8 *drm_find_cea_extension(const struct edid *edid)
static const struct drm_display_mode *cea_mode_for_vic(u8 vic)
{
+ BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
+ BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
+
if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
return _cea_modes_1[vic - 1];
if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
--
2.23.0
___
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[Intel-gfx] [PATCH v4 1/4] drm/edid: Abstract away cea_edid_modes[]
From: Ville Syrjälä
We're going to need two cea mode tables (one for VICs < 128,
another one for VICs >= 193). To that end replace the direct
edid_cea_modes[] lookups with a function call. And we'll rename
the array to edid_cea_modes_0[] to indicate how it's to be
indexed.
v2: Fix typos (Tom)
Drop the pointless NULL checks in the loops (Tom)
Assign when declaring (Tom)
Improve the comment for cea_modes_*[] to indicate
that one should always use cea_mode_for_vic() (Tom)
Cc: Tom Anderson
Cc: Hans Verkuil
Cc: Manasi Navare
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 67 +-
1 file changed, 45 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 5b33b7cfd645..00a543b9daab 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -710,12 +710,11 @@ static const struct minimode extra_modes[] = {
};
/*
- * Probably taken from CEA-861 spec.
- * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
+ * From CEA/CTA-861 spec.
*
- * Index using the VIC.
+ * Do not access directly, instead always use cea_mode_for_vic().
*/
-static const struct drm_display_mode edid_cea_modes[] = {
+static const struct drm_display_mode edid_cea_modes_0[] = {
/* 0 - dummy, VICs start at 1 */
{ },
/* 1 - 640x480@60Hz 4:3 */
@@ -3071,6 +3070,25 @@ static u8 *drm_find_cea_extension(const struct edid
*edid)
return cea;
}
+static const struct drm_display_mode *cea_mode_for_vic(u8 vic)
+{
+ if (!vic)
+ return NULL;
+ if (vic < ARRAY_SIZE(edid_cea_modes_0))
+ return _cea_modes_0[vic];
+ return NULL;
+}
+
+static u8 cea_num_vics(void)
+{
+ return ARRAY_SIZE(edid_cea_modes_0);
+}
+
+static u8 cea_next_vic(u8 vic)
+{
+ return vic + 1;
+}
+
/*
* Calculate the alternate clock for the CEA mode
* (60Hz vs. 59.94Hz etc.)
@@ -3108,14 +3126,14 @@ cea_mode_alternate_timings(u8 vic, struct
drm_display_mode *mode)
* get the other variants by simply increasing the
* vertical front porch length.
*/
- BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
-edid_cea_modes[9].vtotal != 262 ||
-edid_cea_modes[12].vtotal != 262 ||
-edid_cea_modes[13].vtotal != 262 ||
-edid_cea_modes[23].vtotal != 312 ||
-edid_cea_modes[24].vtotal != 312 ||
-edid_cea_modes[27].vtotal != 312 ||
-edid_cea_modes[28].vtotal != 312);
+ BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
+cea_mode_for_vic(9)->vtotal != 262 ||
+cea_mode_for_vic(12)->vtotal != 262 ||
+cea_mode_for_vic(13)->vtotal != 262 ||
+cea_mode_for_vic(23)->vtotal != 312 ||
+cea_mode_for_vic(24)->vtotal != 312 ||
+cea_mode_for_vic(27)->vtotal != 312 ||
+cea_mode_for_vic(28)->vtotal != 312);
if (((vic == 8 || vic == 9 ||
vic == 12 || vic == 13) && mode->vtotal < 263) ||
@@ -3143,8 +3161,8 @@ static u8 drm_match_cea_mode_clock_tolerance(const struct
drm_display_mode *to_m
if (to_match->picture_aspect_ratio)
match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
- for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
- struct drm_display_mode cea_mode = edid_cea_modes[vic];
+ for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
+ struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
unsigned int clock1, clock2;
/* Check both 60Hz and 59.94Hz */
@@ -3182,8 +3200,8 @@ u8 drm_match_cea_mode(const struct drm_display_mode
*to_match)
if (to_match->picture_aspect_ratio)
match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
- for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
- struct drm_display_mode cea_mode = edid_cea_modes[vic];
+ for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
+ struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
unsigned int clock1, clock2;
/* Check both 60Hz and 59.94Hz */
@@ -3206,12 +3224,17 @@ EXPORT_SYMBOL(drm_match_cea_mode);
static bool drm_valid_cea_vic(u8 vic)
{
- return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
+ return cea_mode_for_vic(vic) != NULL;
}
static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
{
- return edid_cea_modes[video_code].picture_aspect_ratio;
+ const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
+
+ if (mode)
+ return mode->picture_aspect_ratio;
+
+ return HDMI_PICTURE_ASPECT_NONE;
}
static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8
