[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for In order to readout DP SDPs, refactors the handling of DP SDPs (rev7)
== Series Details ==
Series: In order to readout DP SDPs, refactors the handling of DP SDPs (rev7)
URL : https://patchwork.freedesktop.org/series/72853/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1ec55bed0178 drm: Add DP1.4 VSC SDP Payload related Data Structures
af98f8569ec0 drm/i915/dp: Add compute routine for DP VSC SDP
716fa531cfc4 drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP
314cbcc618a4 drm/i915/dp: Add writing of DP SDPs
31791cfcf1fd video/hdmi: Add Unpack only function for DRM infoframe
e8ae4c96f04b drm/i915/dp: Read out DP SDPs
4984b40cd894 drm: Add logging function for DP VSC SDP
b5e53b152b57 drm/i915: Include HDMI DRM infoframe in the crtc state dump
bb7d7c0a22b5 drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state
dump
ff2f055f0051 drm/i915: Include DP VSC SDP in the crtc state dump
8b34cb1487f9 drm/i915: Program DP SDPs with computed configs
db92d92142fa drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
200d6124205f drm/i915: Add state readout for DP VSC SDP
-:82: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible
side-effects?
#82: FILE: drivers/gpu/drm/i915/display/intel_display.c:13895:
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+ if (!intel_compare_dp_vsc_sdp(_config->infoframes.name, \
+ _config->infoframes.name)) { \
+ pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset,
__stringify(name), \
+
_config->infoframes.name, \
+ _config->infoframes.name);
\
+ ret = false; \
+ } \
+} while (0)
total: 0 errors, 0 warnings, 1 checks, 74 lines checked
5607ed3e0895 drm/i915: Fix enabled infoframe states of lspcon
ccc1b44c6c82 drm/i915: Program DP SDPs on pipe updates
6413aa289f40 drm/i915: Stop sending DP SDPs on ddi disable
f6ab721ac385 drm/i915/dp: Add compute routine for DP PSR VSC SDP
290fe3c7dbc4 drm/i915/psr: Use new DP VSC SDP compute routine on PSR
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 06/18] drm/i915/dp: Read out DP SDPs
It adds code to read the DP SDPs from the video DIP and unpack them into
the crtc state.
It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP
In order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]
In order to unpack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].
A naming rule and style of intel_read_dp_sdp() function references
intel_read_infoframe() function of intel_hdmi.c
v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
v5: Addressed review comments from Uma
- Polish commit message and comments
- Combine the if checks of sdp.HB2 and sdp.HB3
- Add 6bpc to unpacking of VSC SDP
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 187
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
2 files changed, 190 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 5bbc55113325..3df3533a1768 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4940,6 +4940,193 @@ void intel_dp_set_infoframes(struct intel_encoder
*encoder,
intel_write_dp_sdp(encoder, crtc_state,
HDMI_PACKET_TYPE_GAMUT_METADATA);
}
+static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
+ const void *buffer, size_t size)
+{
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ memset(vsc, 0, size);
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != DP_SDP_VSC)
+ return -EINVAL;
+
+ vsc->sdp_type = sdp->sdp_header.HB1;
+ vsc->revision = sdp->sdp_header.HB2;
+ vsc->length = sdp->sdp_header.HB3;
+
+ if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
+ (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
+ /*
+* - HB2 = 0x2, HB3 = 0x8
+* VSC SDP supporting 3D stereo + PSR
+* - HB2 = 0x4, HB3 = 0xe
+* VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
+* first scan line of the SU region (applies to eDP v1.4b
+* and higher).
+*/
+ return 0;
+ } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
+ /*
+* - HB2 = 0x5, HB3 = 0x13
+* VSC SDP supporting 3D stereo + PSR2 + Pixel
Encoding/Colorimetry
+* Format.
+*/
+ vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
+ vsc->colorimetry = sdp->db[16] & 0xf;
+ vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
+
+ switch (sdp->db[17] & 0x7) {
+ case 0x0:
+ vsc->bpc = 6;
+ break;
+ case 0x1:
+ vsc->bpc = 8;
+ break;
+ case 0x2:
+ vsc->bpc = 10;
+ break;
+ case 0x3:
+ vsc->bpc = 12;
+ break;
+ case 0x4:
+ vsc->bpc = 16;
+ break;
+ default:
+ MISSING_CASE(sdp->db[17] & 0x7);
+ return -EINVAL;
+ }
+
+ vsc->content_type = sdp->db[18] & 0x7;
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int
+intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe
*drm_infoframe,
+ const void *buffer, size_t size)
+{
+ int ret;
+
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
+ return -EINVAL;
+
+ /*
+* Least Significant Eight Bits of (Data Byte Count – 1)
+* 1Dh (i.e., Data Byte Count = 30 bytes).
+*/
+ if (sdp->sdp_header.HB2 != 0x1D)
+ return -EINVAL;
+
+ /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
+ if ((sdp->sdp_header.HB3 & 0x3) != 0)
+ return -EINVAL;
+
+ /* INFOFRAME SDP Version Number */
+ if
[Intel-gfx] [PATCH v7 11/18] drm/i915: Program DP SDPs with computed configs
In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
Infoframe SDP), it replaces intel_dp_vsc_enable() function and
intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes()
function.
And it removes unused functions.
Before:
intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() compute sdp
configs and program sdp registers on enable callback of encoder.
After:
It separates computing of sdp configs and programming of sdp register.
The compute config callback of encoder calls computing sdp configs.
The enable callback of encoder calls programming sdp register.
v3: Rebased
v5: Polish commit message [Uma]
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/display/intel_dp.c | 226 ---
drivers/gpu/drm/i915/display/intel_dp.h | 6 -
3 files changed, 1 insertion(+), 234 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1ab638e17046..857014fe5880 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3902,8 +3902,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_backlight_on(crtc_state, conn_state);
intel_psr_enable(intel_dp, crtc_state);
- intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
- intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
+ intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 3df3533a1768..a824408b6e2a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5127,232 +5127,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
}
}
-static void
-intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct dp_sdp vsc_sdp = {};
-
- /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
- vsc_sdp.sdp_header.HB0 = 0;
- vsc_sdp.sdp_header.HB1 = 0x7;
-
- /*
-* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
-* Colorimetry Format indication.
-*/
- vsc_sdp.sdp_header.HB2 = 0x5;
-
- /*
-* VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
-* Colorimetry Format indication (HB2 = 05h).
-*/
- vsc_sdp.sdp_header.HB3 = 0x13;
-
- /* DP 1.4a spec, Table 2-120 */
- switch (crtc_state->output_format) {
- case INTEL_OUTPUT_FORMAT_YCBCR444:
- vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
- break;
- case INTEL_OUTPUT_FORMAT_YCBCR420:
- vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
- break;
- case INTEL_OUTPUT_FORMAT_RGB:
- default:
- /* RGB: DB16[7:4] = 0h */
- break;
- }
-
- switch (conn_state->colorspace) {
- case DRM_MODE_COLORIMETRY_BT709_YCC:
- vsc_sdp.db[16] |= 0x1;
- break;
- case DRM_MODE_COLORIMETRY_XVYCC_601:
- vsc_sdp.db[16] |= 0x2;
- break;
- case DRM_MODE_COLORIMETRY_XVYCC_709:
- vsc_sdp.db[16] |= 0x3;
- break;
- case DRM_MODE_COLORIMETRY_SYCC_601:
- vsc_sdp.db[16] |= 0x4;
- break;
- case DRM_MODE_COLORIMETRY_OPYCC_601:
- vsc_sdp.db[16] |= 0x5;
- break;
- case DRM_MODE_COLORIMETRY_BT2020_CYCC:
- case DRM_MODE_COLORIMETRY_BT2020_RGB:
- vsc_sdp.db[16] |= 0x6;
- break;
- case DRM_MODE_COLORIMETRY_BT2020_YCC:
- vsc_sdp.db[16] |= 0x7;
- break;
- case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
- case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
- vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
- break;
- default:
- /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
-
- /* RGB->YCBCR color conversion uses the BT.709 color space. */
- if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
- vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
- break;
- }
-
- /*
-* For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
-* the following Component Bit Depth values are defined:
-* 001b = 8bpc.
-* 010b = 10bpc.
-* 011b = 12bpc.
-* 100b = 16bpc.
-*/
- switch
[Intel-gfx] [PATCH v7 15/18] drm/i915: Program DP SDPs on pipe updates
Call intel_dp_set_infoframes() function on pipe updates to make sure that we send VSC SDP and HDR Metadata Infoframe SDP (when applicable) on fastsets. Signed-off-by: Gwan-gyeong Mun Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_ddi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 7f29b08ea202..99d3f011ed96 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4070,6 +4070,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder, intel_ddi_set_dp_msa(crtc_state, conn_state); intel_psr_update(intel_dp, crtc_state); + intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); intel_edp_drrs_enable(intel_dp, crtc_state); intel_panel_update_backlight(encoder, crtc_state, conn_state); -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 18/18] drm/i915/psr: Use new DP VSC SDP compute routine on PSR
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.
Because PSR routine has its own scenario and timings of writing a VSC SDP,
the current PSR routine needs to have its own drm_dp_vsc_sdp structure
member variable on struct i915_psr.
In order to calculate colorimetry information, intel_psr_update()
function and intel_psr_enable() function extend a drm_connector_state
argument.
There are no changes to PSR mechanism.
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Rebased
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
drivers/gpu/drm/i915/display/intel_psr.c | 54 +++-
drivers/gpu/drm/i915/display/intel_psr.h | 6 ++-
drivers/gpu/drm/i915/i915_drv.h | 1 +
4 files changed, 22 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index e21dfc0d926b..fd0e88566074 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3903,7 +3903,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
*encoder,
intel_dp_stop_link_train(intel_dp);
intel_edp_backlight_on(crtc_state, conn_state);
- intel_psr_enable(intel_dp, crtc_state);
+ intel_psr_enable(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
@@ -4071,7 +4071,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder
*encoder,
intel_ddi_set_dp_msa(crtc_state, conn_state);
- intel_psr_update(intel_dp, crtc_state);
+ intel_psr_update(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index db3d1561e9bf..953c0286307d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -335,39 +335,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
}
}
-static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct dp_sdp psr_vsc;
-
- if (dev_priv->psr.psr2_enabled) {
- /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
- memset(_vsc, 0, sizeof(psr_vsc));
- psr_vsc.sdp_header.HB0 = 0;
- psr_vsc.sdp_header.HB1 = 0x7;
- if (dev_priv->psr.colorimetry_support) {
- psr_vsc.sdp_header.HB2 = 0x5;
- psr_vsc.sdp_header.HB3 = 0x13;
- } else {
- psr_vsc.sdp_header.HB2 = 0x4;
- psr_vsc.sdp_header.HB3 = 0xe;
- }
- } else {
- /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
- memset(_vsc, 0, sizeof(psr_vsc));
- psr_vsc.sdp_header.HB0 = 0;
- psr_vsc.sdp_header.HB1 = 0x7;
- psr_vsc.sdp_header.HB2 = 0x2;
- psr_vsc.sdp_header.HB3 = 0x8;
- }
-
- intel_dig_port->write_infoframe(_dig_port->base,
- crtc_state,
- DP_SDP_VSC, _vsc, sizeof(psr_vsc));
-}
-
static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -859,9 +826,12 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *crtc_state)
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state
*conn_state)
{
struct intel_dp *intel_dp = dev_priv->psr.dp;
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = _dig_port->base;
u32 val;
drm_WARN_ON(_priv->drm, dev_priv->psr.enabled);
@@ -900,7 +870,9 @@ static void intel_psr_enable_locked(struct drm_i915_private
*dev_priv,
drm_dbg_kms(_priv->drm, "Enabling PSR%s\n",
dev_priv->psr.psr2_enabled ? "2" : "1");
- intel_psr_setup_vsc(intel_dp, crtc_state);
+ intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
+_priv->psr.vsc);
+ intel_write_dp_vsc_sdp(encoder, crtc_state, _priv->psr.vsc);
intel_psr_enable_sink(intel_dp);
[Intel-gfx] [PATCH v7 13/18] drm/i915: Add state readout for DP VSC SDP
Added state readout for DP VSC SDP and enabled state validation
for DP VSC SDP.
v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 43
2 files changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 55eacc4d75bb..7f29b08ea202 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4367,6 +4367,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
_config->infoframes.drm);
intel_read_dp_sdp(encoder, pipe_config,
HDMI_PACKET_TYPE_GAMUT_METADATA);
+ intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
static enum intel_output_type
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e3694e499b28..c11898cc1b50 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13634,6 +13634,13 @@ intel_compare_infoframe(const union hdmi_infoframe *a,
return memcmp(a, b, sizeof(*a)) == 0;
}
+static bool
+intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
+const struct drm_dp_vsc_sdp *b)
+{
+ return memcmp(a, b, sizeof(*a)) == 0;
+}
+
static void
pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
bool fastset, const char *name,
@@ -13659,6 +13666,31 @@ pipe_config_infoframe_mismatch(struct drm_i915_private
*dev_priv,
}
}
+static void
+pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
+ bool fastset, const char *name,
+ const struct drm_dp_vsc_sdp *a,
+ const struct drm_dp_vsc_sdp *b)
+{
+ if (fastset) {
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ drm_dbg_kms(_priv->drm,
+ "fastset mismatch in %s dp sdp\n", name);
+ drm_dbg_kms(_priv->drm, "expected:\n");
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
+ drm_dbg_kms(_priv->drm, "found:\n");
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
+ } else {
+ drm_err(_priv->drm, "mismatch in %s dp sdp\n", name);
+ drm_err(_priv->drm, "expected:\n");
+ drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
+ drm_err(_priv->drm, "found:\n");
+ drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
+ }
+}
+
static void __printf(4, 5)
pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
const char *name, const char *format, ...)
@@ -13860,6 +13892,16 @@ intel_pipe_config_compare(const struct
intel_crtc_state *current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+ if (!intel_compare_dp_vsc_sdp(_config->infoframes.name, \
+ _config->infoframes.name)) { \
+ pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset,
__stringify(name), \
+
_config->infoframes.name, \
+ _config->infoframes.name);
\
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
if (current_config->name1 != pipe_config->name1) { \
pipe_config_mismatch(fastset, crtc, __stringify(name1), \
@@ -14035,6 +14077,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_INFOFRAME(spd);
PIPE_CONF_CHECK_INFOFRAME(hdmi);
PIPE_CONF_CHECK_INFOFRAME(drm);
+ PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
--
2.25.0
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[Intel-gfx] [PATCH v7 10/18] drm/i915: Include DP VSC SDP in the crtc state dump
Dump out the DP VSC SDP in the normal crtc state dump
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Use drm core's DP VSC SDP logging function
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 440e2c1c855c..e3694e499b28 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13006,6 +13006,16 @@ intel_dump_infoframe(struct drm_i915_private *dev_priv,
hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
}
+static void
+intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
+ const struct drm_dp_vsc_sdp *vsc)
+{
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
+}
+
#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
static const char * const output_type_str[] = {
@@ -13164,6 +13174,9 @@ static void intel_dump_pipe_config(const struct
intel_crtc_state *pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
intel_dump_infoframe(dev_priv, _config->infoframes.drm);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(DP_SDP_VSC))
+ intel_dump_dp_vsc_sdp(dev_priv, _config->infoframes.vsc);
drm_dbg_kms(_priv->drm, "requested mode:\n");
drm_mode_debug_printmodeline(_config->hw.mode);
--
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[Intel-gfx] [PATCH v7 12/18] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
Added state readout for DP HDR Metadata Infoframe SDP. Signed-off-by: Gwan-gyeong Mun Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_ddi.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 857014fe5880..55eacc4d75bb 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4298,6 +4298,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder, pipe_config->fec_enable); } + pipe_config->infoframes.enable |= + intel_hdmi_infoframes_enabled(encoder, pipe_config); + break; case TRANS_DDI_MODE_SELECT_DP_MST: pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); @@ -4309,6 +4312,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder, REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); intel_dp_get_m_n(intel_crtc, pipe_config); + + pipe_config->infoframes.enable |= + intel_hdmi_infoframes_enabled(encoder, pipe_config); break; default: break; @@ -4359,6 +4365,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder, intel_read_infoframe(encoder, pipe_config, HDMI_INFOFRAME_TYPE_DRM, _config->infoframes.drm); + + intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); } static enum intel_output_type -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 07/18] drm: Add logging function for DP VSC SDP
When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.
v2: Minor style fix
v3: Move logging functions to drm core [Jani N]
v5: Rebased
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/drm_dp_helper.c | 174
include/drm/drm_dp_helper.h | 3 +
2 files changed, 177 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 5a103e9b3c86..17059ed4763b 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1395,3 +1395,177 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_S
return num_bpc;
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
+{
+ if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
+ return "Invalid";
+
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "RGB";
+ case DP_PIXELFORMAT_YUV444:
+ return "YUV444";
+ case DP_PIXELFORMAT_YUV422:
+ return "YUV422";
+ case DP_PIXELFORMAT_YUV420:
+ return "YUV420";
+ case DP_PIXELFORMAT_Y_ONLY:
+ return "Y_ONLY";
+ case DP_PIXELFORMAT_RAW:
+ return "RAW";
+ default:
+ return "Reserved";
+ }
+}
+
+static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
+ enum dp_colorimetry colorimetry)
+{
+ if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
+ return "Invalid";
+
+ switch (colorimetry) {
+ case DP_COLORIMETRY_DEFAULT:
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "sRGB";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "BT.601";
+ case DP_PIXELFORMAT_Y_ONLY:
+ return "DICOM PS3.14";
+ case DP_PIXELFORMAT_RAW:
+ return "Custom Color Profile";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "Wide Fixed";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "BT.709";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "Wide Float";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "xvYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "OpRGB";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "xvYCC 709";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "DCI-P3";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "sYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "Custom Profile";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "OpYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "BT.2020 RGB";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case
[Intel-gfx] [PATCH v7 04/18] drm/i915/dp: Add writing of DP SDPs
It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe SDP.
In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]
In order to pack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_pack() function.
And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].
A mechanism and a naming rule of intel_dp_set_infoframes() function
references intel_encoder->set_infoframes() of intel_hdmi.c .
VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats cases.
Because PSR routine has its own routine of writing a VSC SDP, when the PSR
is enabled, intel_dp_set_infoframes() does not write a VSC SDP.
v3:
- Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be
used for HDMI), when intel_dp_set_infoframes() function will be called.
- Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp.
v4: Use struct drm_device logging macros
v5:
- use intel_de_*() functions for register access
- Addressed review comments from Uma
Polish commit message and comments
Add 6bpc to packing of VSC SDP
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 199
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
2 files changed, 202 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index fb008168ca83..5bbc55113325 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4741,6 +4741,205 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state
*crtc_state,
return false;
}
+static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
+struct dp_sdp *sdp, size_t size)
+{
+ size_t length = sizeof(struct dp_sdp);
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(sdp, 0, size);
+
+ /*
+* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
+* VSC SDP Header Bytes
+*/
+ sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
+ sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
+ sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
+ sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
+
+ /* VSC SDP Payload for DB16 through DB18 */
+ /* Pixel Encoding and Colorimetry Formats */
+ sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
+ sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
+
+ switch (vsc->bpc) {
+ case 6:
+ /* 6bpc: 0x0 */
+ break;
+ case 8:
+ sdp->db[17] = 0x1; /* DB17[3:0] */
+ break;
+ case 10:
+ sdp->db[17] = 0x2;
+ break;
+ case 12:
+ sdp->db[17] = 0x3;
+ break;
+ case 16:
+ sdp->db[17] = 0x4;
+ break;
+ default:
+ MISSING_CASE(vsc->bpc);
+ break;
+ }
+ /* Dynamic Range and Component Bit Depth */
+ if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
+ sdp->db[17] |= 0x80; /* DB17[7] */
+
+ /* Content Type */
+ sdp->db[18] = vsc->content_type & 0x7;
+
+ return length;
+}
+
+static ssize_t
+intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe
*drm_infoframe,
+struct dp_sdp *sdp,
+size_t size)
+{
+ size_t length = sizeof(struct dp_sdp);
+ const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
HDMI_DRM_INFOFRAME_SIZE;
+ unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
+ ssize_t len;
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(sdp, 0, size);
+
+ len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
+ if (len < 0) {
+ DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
infoframe\n");
+ return -ENOSPC;
+ }
+
+ if (len != infoframe_size) {
+ DRM_DEBUG_KMS("wrong static hdr metadata size\n");
+ return -ENOSPC;
+ }
+
+ /*
+* Set up the infoframe sdp packet for HDR static metadata.
+* Prepare VSC Header for SU as per DP 1.4a spec,
+* Table 2-100 and Table 2-101
+*/
+
+ /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
+ sdp->sdp_header.HB0 = 0;
+ /*
+* Packet Type 80h + Non-audio INFOFRAME Type value
+* HDMI_INFOFRAME_TYPE_DRM: 0x87
+* - 80h + Non-audio
[Intel-gfx] [PATCH v7 08/18] drm/i915: Include HDMI DRM infoframe in the crtc state dump
Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the normal crtc state dump. Signed-off-by: Gwan-gyeong Mun Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 368e481d45ee..66dbaab5867e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13158,6 +13158,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, if (pipe_config->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) intel_dump_infoframe(dev_priv, _config->infoframes.hdmi); + if (pipe_config->infoframes.enable & + intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) + intel_dump_infoframe(dev_priv, _config->infoframes.drm); drm_dbg_kms(_priv->drm, "requested mode:\n"); drm_mode_debug_printmodeline(_config->hw.mode); -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 14/18] drm/i915: Fix enabled infoframe states of lspcon
Compared to implementation of DP and HDMI's encoder->infoframes_enabled,
the lspcon's implementation returns its active state. (we expect enabled
infoframe states of HW.) It leads to pipe state mismatch error
when ddi_get_config is called.
Because the current implementation of lspcon is not ready to support
readout infoframes, we need to return 0 here.
In order to support readout to lspcon, we need to implement read_infoframe
and infoframes_enabled. And set_infoframes also have to set an appropriate
bit on crtc_state->infoframes.enable
Cc: Ville Syrjälä
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index d807c5648c87..6ff7b226f0a1 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -522,7 +522,7 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
/* FIXME actually read this from the hw */
- return enc_to_intel_lspcon(encoder)->active;
+ return 0;
}
void lspcon_resume(struct intel_lspcon *lspcon)
--
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[Intel-gfx] [PATCH v7 03/18] drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP
It stores computed dp hdr metadata infoframe sdp to infoframes.drm of
crtc state. It referenced intel_hdmi_compute_drm_infoframe().
While computing, we'll also fill out the infoframes.enable bitmask
appropriately.
v2: Wrap a long line.
v4: Use struct drm_device logging macros
v5: Fix typo [Uma]
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index bab802a7b3f3..fb008168ca83 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2471,6 +2471,29 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
*intel_dp,
_state->infoframes.vsc);
}
+static void
+intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state
*conn_state)
+{
+ int ret;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct hdmi_drm_infoframe *drm_infoframe =
_state->infoframes.drm.drm;
+
+ if (!conn_state->hdr_output_metadata)
+ return;
+
+ ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
+
+ if (ret) {
+ drm_dbg_kms(_priv->drm, "couldn't set HDR metadata in
infoframe\n");
+ return;
+ }
+
+ crtc_state->infoframes.enable |=
+ intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
+}
+
int
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -2577,6 +2600,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_psr_compute_config(intel_dp, pipe_config);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
+ intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config,
conn_state);
return 0;
}
--
2.25.0
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[Intel-gfx] [PATCH v7 09/18] drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump. HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata Infoframe SDP use the same member variable in infoframes of crtc state. Signed-off-by: Gwan-gyeong Mun Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 66dbaab5867e..440e2c1c855c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13161,6 +13161,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, if (pipe_config->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) intel_dump_infoframe(dev_priv, _config->infoframes.drm); + if (pipe_config->infoframes.enable & + intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) + intel_dump_infoframe(dev_priv, _config->infoframes.drm); drm_dbg_kms(_priv->drm, "requested mode:\n"); drm_mode_debug_printmodeline(_config->hw.mode); -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 16/18] drm/i915: Stop sending DP SDPs on ddi disable
Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp() to make sure not to send VSC SDP and HDR Metadata Infoframe SDP. v5: Polish commit message [Uma] Signed-off-by: Gwan-gyeong Mun Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 99d3f011ed96..e21dfc0d926b 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3715,6 +3715,8 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, INTEL_OUTPUT_DP_MST); enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + intel_dp_set_infoframes(encoder, false, old_crtc_state, old_conn_state); + /* * Power down sink before disabling the port, otherwise we end * up getting interrupts from the sink on detecting link loss. -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 05/18] video/hdmi: Add Unpack only function for DRM infoframe
It adds an unpack only function for DRM infoframe for dynamic range and
mastering infoframe readout.
It unpacks the information data block contained in the binary buffer into
a structured frame of the HDMI Dynamic Range and Mastering (DRM)
information frame.
In contrast to hdmi_drm_infoframe_unpack() function, it does not verify
a checksum.
It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
DP HDR Metadata Infoframe SDP uses the same Dynamic Range and Mastering
(DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
But DP SDP header and payload structure are different from HDMI DRM
Infoframe. Therefore unpacking DRM infoframe for DP requires skipping of
a verifying checksum.
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/video/hdmi.c | 58 +++-
include/linux/hdmi.h | 2 ++
2 files changed, 43 insertions(+), 17 deletions(-)
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 9c82e2a0a411..9818836d82b7 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -1775,20 +1775,18 @@ hdmi_vendor_any_infoframe_unpack(union
hdmi_vendor_any_infoframe *frame,
}
/**
- * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * hdmi_drm_infoframe_unpack_only() - unpack binary buffer to a HDMI DRM
infoframe
* @frame: HDMI DRM infoframe
* @buffer: source buffer
* @size: size of buffer
*
- * Unpacks the information contained in binary @buffer into a structured
+ * Unpacks the information data block contained in binary @buffer into a
structured
* @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
- * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
- * specification.
*
* Returns 0 on success or a negative error code on failure.
*/
-static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
-const void *buffer, size_t size)
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size)
{
const u8 *ptr = buffer;
const u8 *temp;
@@ -1797,23 +1795,13 @@ static int hdmi_drm_infoframe_unpack(struct
hdmi_drm_infoframe *frame,
int ret;
int i;
- if (size < HDMI_INFOFRAME_SIZE(DRM))
- return -EINVAL;
-
- if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
- ptr[1] != 1 ||
- ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
- return -EINVAL;
-
- if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ if (size < HDMI_DRM_INFOFRAME_SIZE)
return -EINVAL;
ret = hdmi_drm_infoframe_init(frame);
if (ret)
return ret;
- ptr += HDMI_INFOFRAME_HEADER_SIZE;
-
frame->eotf = ptr[0] & 0x7;
frame->metadata_type = ptr[1] & 0x7;
@@ -1837,6 +1825,42 @@ static int hdmi_drm_infoframe_unpack(struct
hdmi_drm_infoframe *frame,
return 0;
}
+EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
+
+/**
+ * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * @frame: HDMI DRM infoframe
+ * @buffer: source buffer
+ * @size: size of buffer
+ *
+ * Unpacks the information contained in binary @buffer into a structured
+ * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
+ * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
+ * specification.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
+const void *buffer, size_t size)
+{
+ const u8 *ptr = buffer;
+ int ret;
+
+ if (size < HDMI_INFOFRAME_SIZE(DRM))
+ return -EINVAL;
+
+ if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
+ ptr[1] != 1 ||
+ ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
+ return -EINVAL;
+
+ if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ return -EINVAL;
+
+ ret = hdmi_drm_infoframe_unpack_only(frame, ptr +
HDMI_INFOFRAME_HEADER_SIZE,
+size - HDMI_INFOFRAME_HEADER_SIZE);
+ return ret;
+}
/**
* hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 9918a6c910c5..afb43efc03e0 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -219,6 +219,8 @@ ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe
*frame, void *buffer,
ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
void *buffer, size_t size);
int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size);
enum
[Intel-gfx] [PATCH v7 02/18] drm/i915/dp: Add compute routine for DP VSC SDP
In order to support state readout for DP VSC SDP, we need to have a
structure which holds DP VSC SDP payload data such as
"union hdmi_infoframe drm" which is used for DRM infoframe.
It adds a struct drm_dp_vsc_sdp vsc to intel_crtc_state.infoframes.
And it stores computed dp vsc sdp to infoframes.vsc of crtc state.
While computing we'll also fill out the inforames.enable bitmask
appropriately.
The compute routine follows DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v5:
- Rebased
- Add warning where a bpc is 6 and a pixel format is RGB.
v7: Fix the wrong check of combination bpc 6 and RGB pixelformat
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 100 ++
2 files changed, 101 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7ae0bc8b80d1..7997c307026d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -997,6 +997,7 @@ struct intel_crtc_state {
union hdmi_infoframe spd;
union hdmi_infoframe hdmi;
union hdmi_infoframe drm;
+ struct drm_dp_vsc_sdp vsc;
} infoframes;
/* HDMI scrambling status */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f4dede6253f8..bab802a7b3f3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2372,6 +2372,105 @@ static bool intel_dp_port_has_audio(struct
drm_i915_private *dev_priv,
return true;
}
+static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state
*crtc_state,
+const struct drm_connector_state
*conn_state,
+struct drm_dp_vsc_sdp *vsc)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ /*
+* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+* Colorimetry Format indication.
+*/
+ vsc->revision = 0x5;
+ vsc->length = 0x13;
+
+ /* DP 1.4a spec, Table 2-120 */
+ switch (crtc_state->output_format) {
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ vsc->pixelformat = DP_PIXELFORMAT_YUV444;
+ break;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ vsc->pixelformat = DP_PIXELFORMAT_YUV420;
+ break;
+ case INTEL_OUTPUT_FORMAT_RGB:
+ default:
+ vsc->pixelformat = DP_PIXELFORMAT_RGB;
+ }
+
+ switch (conn_state->colorspace) {
+ case DRM_MODE_COLORIMETRY_BT709_YCC:
+ vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
+ break;
+ case DRM_MODE_COLORIMETRY_XVYCC_601:
+ vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
+ break;
+ case DRM_MODE_COLORIMETRY_XVYCC_709:
+ vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
+ break;
+ case DRM_MODE_COLORIMETRY_SYCC_601:
+ vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
+ break;
+ case DRM_MODE_COLORIMETRY_OPYCC_601:
+ vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_CYCC:
+ vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_RGB:
+ vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_YCC:
+ vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
+ break;
+ case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
+ case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
+ vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
+ break;
+ default:
+ /*
+* RGB->YCBCR color conversion uses the BT.709
+* color space.
+*/
+ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
+ else
+ vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
+ break;
+ }
+
+ vsc->bpc = crtc_state->pipe_bpp / 3;
+
+ /* only RGB pixelformat supports 6 bpc */
+ drm_WARN_ON(_priv->drm,
+ vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
+
+ /* all YCbCr are always limited range */
+ vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
+ vsc->content_type =
[Intel-gfx] [PATCH v7 17/18] drm/i915/dp: Add compute routine for DP PSR VSC SDP
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it adds a compute routine for PSR VSC SDP.
As PSR routine can not use infoframes.vsc of crtc state, it also adds new
writing of DP SDPs (Secondary Data Packet) for PSR.
PSR routine has its own scenario and timings of writing a VSC SDP.
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 54 +
drivers/gpu/drm/i915/display/intel_dp.h | 8
2 files changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a824408b6e2a..7a82ce425aba 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2471,6 +2471,42 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
*intel_dp,
_state->infoframes.vsc);
}
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ vsc->sdp_type = DP_SDP_VSC;
+
+ if (dev_priv->psr.psr2_enabled) {
+ if (dev_priv->psr.colorimetry_support &&
+ intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+ /* [PSR2, +Colorimetry] */
+ intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+vsc);
+ } else {
+ /*
+* [PSR2, -Colorimetry]
+* Prepare VSC Header for SU as per eDP 1.4 spec, Table
6-11
+* 3D stereo + PSR/PSR2 + Y-coordinate.
+*/
+ vsc->revision = 0x4;
+ vsc->length = 0xe;
+ }
+ } else {
+ /*
+* [PSR1]
+* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+* VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
+* higher).
+*/
+ vsc->revision = 0x2;
+ vsc->length = 0x8;
+ }
+}
+
static void
intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
@@ -4904,6 +4940,24 @@ static void intel_write_dp_sdp(struct intel_encoder
*encoder,
intel_dig_port->write_infoframe(encoder, crtc_state, type, , len);
}
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct dp_sdp sdp = {};
+ ssize_t len;
+
+ len = intel_dp_vsc_sdp_pack(vsc, , sizeof(sdp));
+
+ if (drm_WARN_ON(_priv->drm, len < 0))
+ return;
+
+ intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
+ , len);
+}
+
void intel_dp_set_infoframes(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 6562bb8edeba..5074e52722c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -18,6 +18,7 @@ struct drm_connector_state;
struct drm_encoder;
struct drm_i915_private;
struct drm_modeset_acquire_ctx;
+struct drm_dp_vsc_sdp;
struct intel_connector;
struct intel_crtc_state;
struct intel_digital_port;
@@ -110,6 +111,13 @@ int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state,
+ struct drm_dp_vsc_sdp *vsc);
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc);
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
const
[Intel-gfx] [PATCH v7 01/18] drm: Add DP1.4 VSC SDP Payload related Data Structures
It adds new enumeration definitions for VSC SDP Payload for Pixel
Encoding/Colorimetry Format.
And it adds a new drm data structure for DP VSC SDP.
enum dp_colorspace and enum dp_colorimetry correspond "Pixel Encoding and
Colorimetry Formats". enum dp_dynamic_range corresponds "Dynamic Range".
And enum dp_content_type corresponds "Content Type"
All of them are based on DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].
v3: Add a new drm data structure for DP VSC SDP
v5: Addressed review comments from Uma
- Add kernel docs for added data structures
- Rename enum dp_colorspace to dp_pixelformat
- Polish commit message
- Fix typos
- Drop self-explanatory comments
Signed-off-by: Gwan-gyeong Mun
---
include/drm/drm_dp_helper.h | 130
1 file changed, 130 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 262faf9e5e94..e332f54013d7 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1209,6 +1209,136 @@ struct dp_sdp {
#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
+/**
+ * enum dp_pixelformat - drm DP Pixel encoding formats
+ *
+ * This enum is used to indicate DP VSC SDP Pixel encoding formats.
+ * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
+ * DB18]
+ *
+ * @DP_PIXELFORMAT_RGB: RGB pixel encoding format
+ * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format
+ * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format
+ * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format
+ * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format
+ * @DP_PIXELFORMAT_RAW: RAW pixel encoding format
+ * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format
+ */
+enum dp_pixelformat {
+ DP_PIXELFORMAT_RGB = 0,
+ DP_PIXELFORMAT_YUV444 = 0x1,
+ DP_PIXELFORMAT_YUV422 = 0x2,
+ DP_PIXELFORMAT_YUV420 = 0x3,
+ DP_PIXELFORMAT_Y_ONLY = 0x4,
+ DP_PIXELFORMAT_RAW = 0x5,
+ DP_PIXELFORMAT_RESERVED = 0x6,
+};
+
+/**
+ * enum dp_colorimetry - drm DP Colorimetry formats
+ *
+ * This enum is used to indicate DP VSC SDP Colorimetry formats.
+ * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
+ * DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition.
+ *
+ * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or
+ * ITU-R BT.601 colorimetry format
+ * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry
format
+ * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format
+ * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point
+ * (scRGB (IEC 61966-2-2)) colorimetry format
+ * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format
+ * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format
+ * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format
+ * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format
+ * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format
+ * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format
+ * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format
+ * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format
+ * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format
+ * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format
+ */
+enum dp_colorimetry {
+ DP_COLORIMETRY_DEFAULT = 0,
+ DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
+ DP_COLORIMETRY_BT709_YCC = 0x1,
+ DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
+ DP_COLORIMETRY_XVYCC_601 = 0x2,
+ DP_COLORIMETRY_OPRGB = 0x3,
+ DP_COLORIMETRY_XVYCC_709 = 0x3,
+ DP_COLORIMETRY_DCI_P3_RGB = 0x4,
+ DP_COLORIMETRY_SYCC_601 = 0x4,
+ DP_COLORIMETRY_RGB_CUSTOM = 0x5,
+ DP_COLORIMETRY_OPYCC_601 = 0x5,
+ DP_COLORIMETRY_BT2020_RGB = 0x6,
+ DP_COLORIMETRY_BT2020_CYCC = 0x6,
+ DP_COLORIMETRY_BT2020_YCC = 0x7,
+};
+
+/**
+ * enum dp_dynamic_range - drm DP Dynamic Range
+ *
+ * This enum is used to indicate DP VSC SDP Dynamic Range.
+ * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
+ * DB18]
+ *
+ * @DP_DYNAMIC_RANGE_VESA: VESA range
+ * @DP_DYNAMIC_RANGE_CTA: CTA range
+ */
+enum dp_dynamic_range {
+ DP_DYNAMIC_RANGE_VESA = 0,
+ DP_DYNAMIC_RANGE_CTA = 1,
+};
+
+/**
+ * enum dp_content_type - drm DP Content Type
+ *
+ * This enum is used to indicate DP VSC SDP Content Types.
+ * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
+ * DB18]
+ * CTA-861-G defines content types and expected processing by a sink device
+ *
+ * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type
+ * @DP_CONTENT_TYPE_GRAPHICS: Graphics type
+ * @DP_CONTENT_TYPE_PHOTO: Photo type
+ * @DP_CONTENT_TYPE_VIDEO: Video type
+ * @DP_CONTENT_TYPE_GAME: Game type
+ */
+enum dp_content_type {
+ DP_CONTENT_TYPE_NOT_DEFINED =
[Intel-gfx] [PATCH v7 00/18] In order to readout DP SDPs, refactors the handling of DP SDPs
In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes. It adds new compute routines for DP HDR Metadata Infoframe SDP and DP VSC SDP. And new writing routines of DP SDPs (Secondary Data Packet) that uses computed configs. New reading routines of DP SDPs are added for readout. It adds a logging function for DP VSC SDP. When receiving video it is very useful to be able to log DP VSC SDP. This greatly simplifies debugging. In order to use a common VSC SDP Colorimetry calculating code on PSR, it uses a new psr vsc sdp compute routine. v2: Minor style fix v3: - Add a new drm data structure for DP VSC SDP - Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp - Move logging functions to drm core [Jani N] And use drm core's DP VSC SDP logging function - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be used for HDMI), when intel_dp_set_infoframes() function will be called. v4: - Use struct drm_device logging macros - Rebased v5: - Use intel_de_*() functions for register access - Add warning where a bpc is 6 and a pixel format is RGB. - Addressed review comments from Uma Add kernel docs for added data structures Rename enum dp_colorspace to dp_pixelformat Polish commit message and comments Combine the if checks of sdp.HB2 and sdp.HB3 Add 6bpc to packining and unpacking of VSC SDP v6: Fix enabled infoframe states of lspcon v7: Fix the wrong check of combination bpc 6 and RGB pixelformat Gwan-gyeong Mun (18): drm: Add DP1.4 VSC SDP Payload related Data Structures drm/i915/dp: Add compute routine for DP VSC SDP drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP drm/i915/dp: Add writing of DP SDPs video/hdmi: Add Unpack only function for DRM infoframe drm/i915/dp: Read out DP SDPs drm: Add logging function for DP VSC SDP drm/i915: Include HDMI DRM infoframe in the crtc state dump drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump drm/i915: Include DP VSC SDP in the crtc state dump drm/i915: Program DP SDPs with computed configs drm/i915: Add state readout for DP HDR Metadata Infoframe SDP drm/i915: Add state readout for DP VSC SDP drm/i915: Fix enabled infoframe states of lspcon drm/i915: Program DP SDPs on pipe updates drm/i915: Stop sending DP SDPs on ddi disable drm/i915/dp: Add compute routine for DP PSR VSC SDP drm/i915/psr: Use new DP VSC SDP compute routine on PSR drivers/gpu/drm/drm_dp_helper.c | 174 + drivers/gpu/drm/i915/display/intel_ddi.c | 19 +- drivers/gpu/drm/i915/display/intel_display.c | 62 ++ .../drm/i915/display/intel_display_types.h| 1 + drivers/gpu/drm/i915/display/intel_dp.c | 638 ++ drivers/gpu/drm/i915/display/intel_dp.h | 18 +- drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 54 +- drivers/gpu/drm/i915/display/intel_psr.h | 6 +- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/video/hdmi.c | 58 +- include/drm/drm_dp_helper.h | 133 include/linux/hdmi.h | 2 + 13 files changed, 950 insertions(+), 218 deletions(-) -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Disable -Wtautological-constant-out-of-range-compare (rev2)
== Series Details == Series: drm/i915: Disable -Wtautological-constant-out-of-range-compare (rev2) URL : https://patchwork.freedesktop.org/series/73271/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7905 -> Patchwork_16515 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16515 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16515, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16515/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16515: ### IGT changes ### Possible regressions * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7905/fi-hsw-4770r/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16515/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_objects: - fi-bwr-2160:[PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7905/fi-bwr-2160/igt@i915_selftest@live_objects.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16515/fi-bwr-2160/igt@i915_selftest@live_objects.html Known issues Here are the changes found in Patchwork_16515 that come from known issues: ### IGT changes ### Possible fixes * igt@gem_close_race@basic-threads: - fi-hsw-peppy: [INCOMPLETE][5] ([i915#694] / [i915#816]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7905/fi-hsw-peppy/igt@gem_close_r...@basic-threads.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16515/fi-hsw-peppy/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-8700k: [INCOMPLETE][7] ([i915#424]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7905/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16515/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 Participating hosts (46 -> 40) -- Additional (4): fi-skl-lmem fi-glk-dsi fi-snb-2520m fi-kbl-r Missing(10): fi-ilk-m540 fi-bsw-n3050 fi-byt-j1900 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-gdg-551 fi-blb-e6850 fi-byt-clapper fi-bsw-nick Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7905 -> Patchwork_16515 CI-20190529: 20190529 CI_DRM_7905: db98da3dd757a19dbaaeaef8640276fe7be2fc4e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5433: 6a96c17f3a1b4e1f90b1a0b0ce42a7219875d1a4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16515: 2b06b9a9a6d6785235ca559832db83a0e69928ff @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2b06b9a9a6d6 drm/i915: Disable -Wtautological-constant-out-of-range-compare == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16515/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: terminate reauth at stream management failure
On 2020-02-10 at 22:19:50 +0530, Ramalingam C wrote:
> As per the HDCP2.2 compliance test 1B-10 expectation, when stream
> management for a repeater fails, HDCP2.2 reauthentication stops at
> kernel.
Shall i drop my patch now and continue with reviewing this patch.
one comment below.
>
> Signed-off-by: Ramalingam C
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 55 ++-
> 1 file changed, 34 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 4d1a33d13105..5ab35484da93 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -1380,7 +1380,7 @@ static int hdcp2_session_key_exchange(struct
> intel_connector *connector)
> }
>
> static
> -int hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> +int _hdcp2_propagate_stream_management_info(struct intel_connector
> *connector)
> {
> struct intel_digital_port *intel_dig_port =
> intel_attached_dig_port(connector);
> struct intel_hdcp *hdcp = >hdcp;
> @@ -1492,17 +1492,6 @@ int hdcp2_authenticate_repeater_topology(struct
> intel_connector *connector)
> return 0;
> }
>
> -static int hdcp2_authenticate_repeater(struct intel_connector *connector)
> -{
> - int ret;
> -
> - ret = hdcp2_authenticate_repeater_topology(connector);
> - if (ret < 0)
> - return ret;
> -
> - return hdcp2_propagate_stream_management_info(connector);
> -}
> -
> static int hdcp2_authenticate_sink(struct intel_connector *connector)
> {
> struct intel_digital_port *intel_dig_port =
> intel_attached_dig_port(connector);
> @@ -1537,18 +1526,13 @@ static int hdcp2_authenticate_sink(struct
> intel_connector *connector)
> }
>
> if (hdcp->is_repeater) {
> - ret = hdcp2_authenticate_repeater(connector);
> + ret = hdcp2_authenticate_repeater_topology(connector);
> if (ret < 0) {
> DRM_DEBUG_KMS("Repeater Auth Failed. Err: %d\n", ret);
> return ret;
> }
> }
>
> - hdcp->port_data.streams[0].stream_type = hdcp->content_type;
> - ret = hdcp2_authenticate_port(connector);
> - if (ret < 0)
> - return ret;
> -
> return ret;
> }
>
> @@ -1626,14 +1610,43 @@ static int hdcp2_disable_encryption(struct
> intel_connector *connector)
> return ret;
> }
>
> +static int
> +hdcp2_propagate_stream_management_info(struct intel_connector *connector)
> +{
> + int i, tries = 3, ret;
> +
> + if (!connector->hdcp.is_repeater)
> + return 0;
> +
> + for (i = 0; i < tries; i++) {
> + ret = _hdcp2_propagate_stream_management_info(connector);
> + if (!ret)
> + break;
> + }
> +
> + return ret;
> +}
> +
> static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
> {
> + struct intel_hdcp *hdcp = >hdcp;
> int ret, i, tries = 3;
>
> for (i = 0; i < tries; i++) {
> ret = hdcp2_authenticate_sink(connector);
> - if (!ret)
> - break;
> + if (!ret) {
> + ret = hdcp2_propagate_stream_management_info(connector);
we need to increment seq_num_m fo every retry of stream
management.
Thanks,
Anshuman Gupta.
> + if (!ret) {
> + hdcp->port_data.streams[0].stream_type =
> + hdcp->content_type;
> + ret = hdcp2_authenticate_port(connector);
> + if (!ret)
> + break;
> + } else {
> + DRM_DEBUG_KMS("HDCP2 stream management
> failed\n");
> + break;
> + }
> + }
>
> /* Clearing the mei hdcp session */
> DRM_DEBUG_KMS("HDCP2.2 Auth %d of %d Failed.(%d)\n",
> @@ -1642,7 +1655,7 @@ static int hdcp2_authenticate_and_encrypt(struct
> intel_connector *connector)
> DRM_DEBUG_KMS("Port deauth failed.\n");
> }
>
> - if (i != tries) {
> + if (!ret) {
> /*
>* Ensuring the required 200mSec min time interval between
>* Session Key Exchange and encryption.
> --
> 2.20.1
>
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[Intel-gfx] [PATCH v2] drm/i915: Disable -Wtautological-constant-out-of-range-compare
A recent commit in clang added -Wtautological-compare to -Wall, which is enabled for i915 so we see the following warning: ../drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1485:22: warning: result of comparison of constant 576460752303423487 with expression of type 'unsigned int' is always false [-Wtautological-constant-out-of-range-compare] if (unlikely(remain > N_RELOC(ULONG_MAX))) ^ This warning only happens on x86_64 but that check is relevant for 32-bit x86 so we cannot remove it. -Wtautological-compare on a whole has good warnings but this one is not really relevant for the kernel because of all of the different configurations that are used to build the kernel. When -Wtautological-compare is enabled for the kernel, this option will remain disabled so do that for i915 now. Link: https://github.com/ClangBuiltLinux/linux/issues/778 Signed-off-by: Nathan Chancellor --- v1 -> v2: https://lore.kernel.org/lkml/20200211050808.29463-1-natechancel...@gmail.com/ * Fix patch application due to basing on a local tree that had -Wuninitialized turned on. Can confirm that patch applies on latest -next now. drivers/gpu/drm/i915/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index b8c5f8934dbd..159355eb43a9 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -22,6 +22,7 @@ subdir-ccflags-y += $(call cc-disable-warning, sign-compare) subdir-ccflags-y += $(call cc-disable-warning, sometimes-uninitialized) subdir-ccflags-y += $(call cc-disable-warning, initializer-overrides) subdir-ccflags-y += $(call cc-disable-warning, uninitialized) +subdir-ccflags-y += $(call cc-disable-warning, tautological-constant-out-of-range-compare) subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror # Fine grained warnings disable -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Disable -Wtautological-constant-out-of-range-compare
== Series Details == Series: drm/i915: Disable -Wtautological-constant-out-of-range-compare URL : https://patchwork.freedesktop.org/series/73271/ State : failure == Summary == Applying: drm/i915: Disable -Wtautological-constant-out-of-range-compare error: sha1 information is lacking or useless (drivers/gpu/drm/i915/Makefile). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915: Disable -Wtautological-constant-out-of-range-compare When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Disable -Wtautological-constant-out-of-range-compare
A recent commit in clang added -Wtautological-compare to -Wall, which is enabled for i915 so we see the following warning: ../drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1485:22: warning: result of comparison of constant 576460752303423487 with expression of type 'unsigned int' is always false [-Wtautological-constant-out-of-range-compare] if (unlikely(remain > N_RELOC(ULONG_MAX))) ^ This warning only happens on x86_64 but that check is relevant for 32-bit x86 so we cannot remove it. -Wtautological-compare on a whole has good warnings but this one is not really relevant for the kernel because of all of the different configurations that are used to build the kernel. When -Wtautological-compare is enabled for the kernel, this option will remain disabled so do that for i915 now. Link: https://github.com/ClangBuiltLinux/linux/issues/778 Signed-off-by: Nathan Chancellor --- drivers/gpu/drm/i915/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 38df01c23176..55dbcca179c7 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -21,6 +21,7 @@ subdir-ccflags-y += $(call cc-disable-warning, unused-but-set-variable) subdir-ccflags-y += $(call cc-disable-warning, sign-compare) subdir-ccflags-y += $(call cc-disable-warning, sometimes-uninitialized) subdir-ccflags-y += $(call cc-disable-warning, initializer-overrides) +subdir-ccflags-y += $(call cc-disable-warning, tautological-constant-out-of-range-compare) subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror # Fine grained warnings disable -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/execlists: Always force a context reload when rewinding RING_TAIL
Hi,
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag,
fixing commit: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing").
The bot has tested the following trees: v5.5.2, v5.4.18.
v5.5.2: Failed to apply! Possible dependencies:
05975cd9eb84 ("drm/i915: Remove vestigal i915_gem_context locals from
cmdparser")
32d94048b988 ("drm/i915/gem: Prepare gen7 cmdparser for async execution")
3cd6e8860ecd ("drm/i915/gen7: Re-enable full-ppgtt for ivb & hsw")
51696691aba3 ("drm/i915/gem: Tidy up error handling for eb_parse()")
755bf8a8c985 ("drm/i915: Remove redundant parameters from
intel_engine_cmd_parser")
9f3ccd40acf4 ("drm/i915: Drop GEM context as a direct link from
i915_request")
b291ce0a168b ("drm/i915/gem: Purge the sudden reappearance of
i915_gem_object_pin()")
cd30a5031704 ("drm/i915/gem: Excise the per-batch whitelist from the
context")
f70de8d2ca6b ("drm/i915/gt: Track the context validity explicitly")
f997056d5b17 ("drm/i915/gt: Push the flush_pd before the set-context")
fc4f125d958f ("drm/i915/gem: Embed context/timeline name inside the GEM
context")
v5.4.18: Failed to apply! Possible dependencies:
08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340")
0b718ba1e884 ("drm/i915/gtt: Downgrade Cherryview back to aliasing-ppgtt")
253a774bb08b ("drm/i915/execlists: Don't merely skip submission if maybe
timeslicing")
3c00660db183 ("drm/i915/execlists: Assert tasklet is locked for
process_csb()")
42014f69bb23 ("drm/i915: Hook up GT power management")
5bf05dc58d65 ("drm/i915/tgl: Register state context definition for Gen12")
5d904e3c5d40 ("drm/i915: Pass in intel_gt at some for_each_engine sites")
7dc56af5260e ("drm/i915/selftests: Verify the LRC register layout between
init and HW")
82c69bf58650 ("drm/i915/gt: Detect if we miss WaIdleLiteRestore")
c113236718e8 ("drm/i915: Extract GT render sleep (rc6) management")
cdb736fa8b8b ("drm/i915: Use engine relative LRIs on context setup")
eaef5b3c4113 ("drm/i915: Refactor instdone loops on new subslice functions")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
--
Thanks,
Sasha
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/tgl: Enable hotplug detection in TC5 and TC6
== Series Details ==
Series: drm/i915/display/tgl: Enable hotplug detection in TC5 and TC6
URL : https://patchwork.freedesktop.org/series/73267/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7904 -> Patchwork_16513
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16513/index.html
Known issues
Here are the changes found in Patchwork_16513 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_parallel@fds:
- fi-byt-n2820: [PASS][1] -> [TIMEOUT][2] ([fdo#112271] / [i915#1084])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7904/fi-byt-n2820/igt@gem_exec_paral...@fds.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16513/fi-byt-n2820/igt@gem_exec_paral...@fds.html
* igt@i915_selftest@live_execlists:
- fi-icl-y: [PASS][3] -> [DMESG-FAIL][4] ([fdo#108569])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7904/fi-icl-y/igt@i915_selftest@live_execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16513/fi-icl-y/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_gem_contexts:
- fi-cml-s: [PASS][5] -> [DMESG-FAIL][6] ([i915#877])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7904/fi-cml-s/igt@i915_selftest@live_gem_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16513/fi-cml-s/igt@i915_selftest@live_gem_contexts.html
Possible fixes
* igt@gem_close_race@basic-threads:
- fi-byt-j1900: [INCOMPLETE][7] ([i915#45]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7904/fi-byt-j1900/igt@gem_close_r...@basic-threads.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16513/fi-byt-j1900/igt@gem_close_r...@basic-threads.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8700k: [INCOMPLETE][9] ([i915#424]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7904/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16513/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877
Participating hosts (46 -> 39)
--
Additional (5): fi-kbl-soraka fi-hsw-peppy fi-kbl-7500u fi-hsw-4770
fi-gdg-551
Missing(12): fi-ilk-m540 fi-hsw-4200u fi-glk-dsi fi-byt-squawks
fi-bsw-cyan fi-ilk-650 fi-cfl-8109u fi-skl-lmem fi-blb-e6850 fi-byt-clapper
fi-skl-6600u fi-snb-2600
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7904 -> Patchwork_16513
CI-20190529: 20190529
CI_DRM_7904: 5de757f49fb13a3c0e42626e7c4b47c2d82b14a1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5433: 6a96c17f3a1b4e1f90b1a0b0ce42a7219875d1a4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16513: 81bec0c3bfd641ddef37583c43242ab63e7a573a @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
81bec0c3bfd6 drm/i915/display/tgl: Enable hotplug detection in TC5 and TC6
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16513/index.html
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[Intel-gfx] [PATCH] drm/i915/display/tgl: Enable hotplug detection in TC5 and TC6
The hotplug interruption detection was not being enabled for TC5 and TC6 in the north detection side. Cc: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_irq.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 3d0cd0960bd2..abd979ef75ec 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3051,6 +3051,9 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) | GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) | GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4); + if (INTEL_GEN(dev_priv) >= 12) + hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) | + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6); I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug); hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL); @@ -3058,6 +3061,9 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) | GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) | GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4); + if (INTEL_GEN(dev_priv) >= 12) + hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) | + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6); I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug); } -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_nop: Keep a copy of the names
Hi Chris,
On Tue, Feb 11, 2020 at 12:37:42AM +, Chris Wilson wrote:
> The engine names are now stored inside the iterator and not as static
> strings. If we wish to use them later, we need to make a copy.
But we are not using them later. Your patch just copies and frees
an array.
Is there a follow-up?
Andi
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> ---
> tests/i915/gem_exec_nop.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/tests/i915/gem_exec_nop.c b/tests/i915/gem_exec_nop.c
> index ed9568e5a..fc7f11827 100644
> --- a/tests/i915/gem_exec_nop.c
> +++ b/tests/i915/gem_exec_nop.c
> @@ -436,7 +436,7 @@ static void parallel(int fd, uint32_t handle, int timeout)
> struct drm_i915_gem_execbuffer2 execbuf;
> struct drm_i915_gem_exec_object2 obj;
> unsigned engines[16];
> - const char *names[16];
> + char *names[16];
> unsigned nengine;
> unsigned long count;
> double time, sum;
> @@ -445,7 +445,7 @@ static void parallel(int fd, uint32_t handle, int timeout)
> nengine = 0;
> __for_each_physical_engine(fd, e) {
> engines[nengine] = e->flags;
> - names[nengine++] = e->name;
> + names[nengine++] = strdup(e->name);
>
> time = nop_on_ring(fd, handle, e, 1, ) / count;
> sum += time;
> @@ -485,10 +485,11 @@ static void parallel(int fd, uint32_t handle, int
> timeout)
> time = elapsed(, ) / count;
> igt_info("%s: %ld cycles, %.3fus\n", names[child], count,
> 1e6*time);
> }
> + while (nengine--)
> + free(names[nengine]);
>
> igt_waitchildren();
> igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> -
> }
>
> static void series(int fd, uint32_t handle, int timeout)
> --
> 2.25.0
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] [PATCH i-g-t 3/3] i915/gem_ctx_isolation: Check engine relative registers - Part 2
Modify previous i915/gem_ctx_isolation "Check engine relative registers"
for modified mmio_base infrastructure.
Signed-off-by: Dale B Stimson
---
tests/i915/gem_ctx_isolation.c | 87 +++---
1 file changed, 48 insertions(+), 39 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index eff4b1df2..eec78c729 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -233,12 +233,12 @@ static bool ignore_register(uint32_t offset, uint32_t
mmio_base)
static void tmpl_regs(int fd,
uint32_t ctx,
const struct intel_execution_engine2 *e,
+ uint32_t mmio_base,
uint32_t handle,
uint32_t value)
{
const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
const unsigned int engine_bit = ENGINE(e->class, e->instance);
- const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
unsigned int regs_size;
uint32_t *regs;
@@ -278,12 +278,12 @@ static void tmpl_regs(int fd,
static uint32_t read_regs(int fd,
uint32_t ctx,
const struct intel_execution_engine2 *e,
+ uint32_t mmio_base,
unsigned int flags)
{
const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
const unsigned int gen_bit = 1 << gen;
const unsigned int engine_bit = ENGINE(e->class, e->instance);
- const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
const bool r64b = gen >= 8;
struct drm_i915_gem_exec_object2 obj[2];
struct drm_i915_gem_relocation_entry *reloc;
@@ -359,12 +359,12 @@ static uint32_t read_regs(int fd,
static void write_regs(int fd,
uint32_t ctx,
const struct intel_execution_engine2 *e,
+ uint32_t mmio_base,
unsigned int flags,
uint32_t value)
{
const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
const unsigned int engine_bit = ENGINE(e->class, e->instance);
- const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
struct drm_i915_gem_exec_object2 obj;
struct drm_i915_gem_execbuffer2 execbuf;
unsigned int batch_size;
@@ -420,13 +420,13 @@ static void write_regs(int fd,
static void restore_regs(int fd,
uint32_t ctx,
const struct intel_execution_engine2 *e,
+uint32_t mmio_base,
unsigned int flags,
uint32_t regs)
{
const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
const unsigned int gen_bit = 1 << gen;
const unsigned int engine_bit = ENGINE(e->class, e->instance);
- const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
const bool r64b = gen >= 8;
struct drm_i915_gem_exec_object2 obj[2];
struct drm_i915_gem_execbuffer2 execbuf;
@@ -498,12 +498,12 @@ static void restore_regs(int fd,
__attribute__((unused))
static void dump_regs(int fd,
const struct intel_execution_engine2 *e,
+ uint32_t mmio_base,
unsigned int regs)
{
const int gen = intel_gen(intel_get_drm_devid(fd));
const unsigned int gen_bit = 1 << gen;
const unsigned int engine_bit = ENGINE(e->class, e->instance);
- const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
unsigned int regs_size;
uint32_t *out;
@@ -541,9 +541,9 @@ static void dump_regs(int fd,
}
static void compare_regs(int fd, const struct intel_execution_engine2 *e,
+uint32_t mmio_base,
uint32_t A, uint32_t B, const char *who)
{
- const uint32_t mmio_base = gem_engine_mmio_base(fd, e->name);
unsigned int num_errors;
unsigned int regs_size;
uint32_t *a, *b;
@@ -596,6 +596,7 @@ static void compare_regs(int fd, const struct
intel_execution_engine2 *e,
static void nonpriv(int fd,
const struct intel_execution_engine2 *e,
+ uint32_t mmio_base,
unsigned int flags)
{
static const uint32_t values[] = {
@@ -623,16 +624,16 @@ static void nonpriv(int fd,
ctx = gem_context_clone_with_engines(fd, 0);
- tmpl = read_regs(fd, ctx, e, flags);
- regs[0] = read_regs(fd, ctx, e, flags);
+ tmpl = read_regs(fd, ctx, e, mmio_base, flags);
+ regs[0] = read_regs(fd, ctx, e, mmio_base, flags);
- tmpl_regs(fd, ctx, e, tmpl, values[v]);
+ tmpl_regs(fd, ctx, e, mmio_base, tmpl, values[v]);
spin = igt_spin_new(fd, .ctx = ctx, .engine = e->flags);
[Intel-gfx] [PATCH i-g-t 2/3] i915/gem_ctx_isolation: Check engine relative registers
From: Chris Wilson
Some of the non-privileged registers are at the same offset on each
engine. We can improve our coverage for unknown HW layout by using the
reported engine->mmio_base for relative offsets.
Signed-off-by: Chris Wilson
---
tests/i915/gem_ctx_isolation.c | 164 -
1 file changed, 100 insertions(+), 64 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index 1b66fec11..eff4b1df2 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -70,6 +70,7 @@ static const struct named_register {
uint32_t ignore_bits;
uint32_t write_mask; /* some registers bits do not exist */
bool masked;
+ bool relative;
} nonpriv_registers[] = {
{ "NOPID", NOCTX, RCS0, 0x2094 },
{ "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
@@ -109,7 +110,6 @@ static const struct named_register {
{ "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
{ "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x7 },
{ "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
- { "CS_GPR", GEN8, RCS0, 0x2600, 32 },
{ "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
{ "OACTXID", GEN8, RCS0, 0x2364 },
{ "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
@@ -138,79 +138,56 @@ static const struct named_register {
{ "CTX_PREEMPT", NOCTX /* GEN10 */, RCS0, 0x2248 },
{ "CS_CHICKEN1", GEN11, RCS0, 0x2580, .masked = true },
- { "HDC_CHICKEN1", GEN_RANGE(10, 10), RCS0, 0x7304, .masked = true },
/* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
{ "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 },
{ "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
{ "COMMON_SLICE_CHICKEN2", GEN_RANGE(9, 9), RCS0, 0x7014, .masked =
true },
- { "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true },
+ { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
{ "SLICE_COMMON_ECO_CHICKEN1", GEN_RANGE(11, 11) /* + glk */, RCS0,
0x731c, .masked = true },
{ "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask =
~0x10 },
{ "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked =
true },
{ "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true },
- { "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
{ "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true
},
{ "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
{ "MFC_VDBOX2", NOCTX, VCS1, 0x1c800, 64 },
- { "VCS0_GPR", GEN_RANGE(9, 10), VCS0, 0x12600, 32 },
- { "VCS1_GPR", GEN_RANGE(9, 10), VCS1, 0x1c600, 32 },
- { "VECS_GPR", GEN_RANGE(9, 10), VECS0, 0x1a600, 32 },
-
- { "VCS0_GPR", GEN11, VCS0, 0x1c0600, 32 },
- { "VCS1_GPR", GEN11, VCS1, 0x1c4600, 32 },
- { "VCS2_GPR", GEN11, VCS2, 0x1d0600, 32 },
- { "VCS3_GPR", GEN11, VCS3, 0x1d4600, 32 },
- { "VECS_GPR", GEN11, VECS0, 0x1c8600, 32 },
+ { "xCS_GPR", GEN9, ALL, 0x600, 32, .relative = true },
{}
}, ignore_registers[] = {
{ "RCS timestamp", GEN6, ~0u, 0x2358 },
{ "BCS timestamp", GEN7, ~0u, 0x22358 },
- { "VCS0 timestamp", GEN_RANGE(7, 10), ~0u, 0x12358 },
- { "VCS1 timestamp", GEN_RANGE(7, 10), ~0u, 0x1c358 },
- { "VECS timestamp", GEN_RANGE(8, 10), ~0u, 0x1a358 },
-
- { "VCS0 timestamp", GEN11, ~0u, 0x1c0358 },
- { "VCS1 timestamp", GEN11, ~0u, 0x1c4358 },
- { "VCS2 timestamp", GEN11, ~0u, 0x1d0358 },
- { "VCS3 timestamp", GEN11, ~0u, 0x1d4358 },
- { "VECS timestamp", GEN11, ~0u, 0x1c8358 },
+ { "xCS timestamp", GEN8, ALL, 0x358, .relative = true },
/* huc read only */
- { "BSD0 0x2000", GEN11, ~0u, 0x1c + 0x2000 },
- { "BSD0 0x2000", GEN11, ~0u, 0x1c + 0x2014 },
- { "BSD0 0x2000", GEN11, ~0u, 0x1c + 0x23b0 },
-
- { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2000 },
- { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x2014 },
- { "BSD1 0x2000", GEN11, ~0u, 0x1c4000 + 0x23b0 },
-
- { "BSD2 0x2000", GEN11, ~0u, 0x1d + 0x2000 },
- { "BSD2 0x2000", GEN11, ~0u, 0x1d + 0x2014 },
- { "BSD2 0x2000", GEN11, ~0u, 0x1d + 0x23b0 },
-
- { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2000 },
- { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x2014 },
- { "BSD3 0x2000", GEN11, ~0u, 0x1d4000 + 0x23b0 },
+ { "BSD 0x2000", GEN11, ALL, 0x2000, .relative = true },
+ { "BSD 0x2014", GEN11, ALL, 0x2014, .relative = true },
+ { "BSD 0x23b0", GEN11, ALL, 0x23b0, .relative = true },
{}
};
-static const char *register_name(uint32_t offset, char *buf, size_t len)
+static const char *
+register_name(uint32_t offset, uint32_t mmio_base, char *buf, size_t len)
{
for (const struct named_register *r = nonpriv_registers; r->name; r++) {
[Intel-gfx] [PATCH i-g-t 1/3] i915/gem_mmio_base.c - get mmio_base from debugfs (if possible)
Signed-off-by: Dale B Stimson
---
lib/Makefile.sources | 2 +
lib/i915/gem_mmio_base.c | 346 +++
lib/i915/gem_mmio_base.h | 19 +++
lib/igt.h| 1 +
lib/meson.build | 1 +
5 files changed, 369 insertions(+)
create mode 100644 lib/i915/gem_mmio_base.c
create mode 100644 lib/i915/gem_mmio_base.h
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 3e573f267..4c5d50d5d 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -7,6 +7,8 @@ lib_source_list = \
i915/gem_context.h \
i915/gem_engine_topology.c \
i915/gem_engine_topology.h \
+ i915/gem_mmio_base.c\
+ i915/gem_mmio_base.h\
i915/gem_scheduler.c\
i915/gem_scheduler.h\
i915/gem_submission.c \
diff --git a/lib/i915/gem_mmio_base.c b/lib/i915/gem_mmio_base.c
new file mode 100644
index 0..8718c092f
--- /dev/null
+++ b/lib/i915/gem_mmio_base.c
@@ -0,0 +1,346 @@
+// Copyright (C) 2020 Intel Corporation
+//
+// SPDX-License-Identifier: MIT
+
+#include
+
+#include
+
+#include "igt.h"
+
+struct eng_mmio_base_s {
+ char name[8];
+ uint32_t mmio_base;
+};
+
+struct eng_mmio_base_table_s {
+ unsigned int mb_cnt;
+ struct eng_mmio_base_s mb_tab[GEM_MAX_ENGINES];
+};
+
+
+static struct eng_mmio_base_table_s *_gem_engine_mmio_info_dup(
+ const struct eng_mmio_base_table_s *mbpi)
+{
+ struct eng_mmio_base_table_s *mbpo;
+ size_t nbytes;
+
+ nbytes = offsetof(typeof(struct eng_mmio_base_table_s),
mb_tab[mbpi->mb_cnt]);
+ mbpo = malloc(nbytes);
+ igt_assert(mbpo);
+ memcpy(mbpo, mbpi, nbytes);
+
+ return mbpo;
+}
+
+void gem_engine_mmio_base_info_free(struct eng_mmio_base_table_s *mbp)
+{
+ free(mbp);
+}
+
+static void _gem_engine_mmio_info_legacy_add(struct eng_mmio_base_table_s *mbp,
+ const char *eng_name, uint32_t mmio_base)
+{
+ if (mmio_base) {
+ strncpy(mbp->mb_tab[mbp->mb_cnt].name, eng_name,
+ sizeof(mbp->mb_tab[0].name));
+ mbp->mb_tab[mbp->mb_cnt].mmio_base = mmio_base;
+ mbp->mb_cnt++;
+ }
+}
+
+/**
+ * _gem_engine_mmio_base_info_get_legacy:
+ * @fd_dev: file descriptor upon which device is open or -1 to use defaults.
+ *
+ * Provides per-engine mmio_base information from legacy built-in values
+ * for the case when the information is not otherwise available.
+ *
+ * Returns:
+ * Pointer to dynamically allocated struct eng_mmio_base_table_s describing
+ * engine config or NULL.
+ * The allocated size does not include unused engine entries.
+ * If non-NULL, it is caller's responsibility to free.
+ */
+static struct eng_mmio_base_table_s *_gem_engine_mmio_base_info_get_legacy(int
fd_dev)
+{
+ int gen;
+ uint32_t mmio_base;
+ struct eng_mmio_base_table_s mbt;
+ struct eng_mmio_base_table_s *mbp;
+
+ memset(, 0, sizeof(mbt));
+
+ gen = intel_gen(intel_get_drm_devid(fd_dev));
+
+ /* The mmio_base values for engine instances 1 and higher cannot
+* be reliability determinated a priori. */
+
+ _gem_engine_mmio_info_legacy_add(, "rcs0", 0x2000);
+ _gem_engine_mmio_info_legacy_add(, "bcs0", 0x22000);
+
+ if (gen < 6)
+ mmio_base = 0x4000;
+ else if (gen < 11)
+ mmio_base = 0x12000;
+ else
+ mmio_base = 0x1c;
+ _gem_engine_mmio_info_legacy_add(, "vcs0", mmio_base);
+
+ if (gen < 11)
+ mmio_base = 0x1a000;
+ else
+ mmio_base = 0x1c8000;
+ _gem_engine_mmio_info_legacy_add(, "vecs0", mmio_base);
+
+ if (mbt.mb_cnt <= 0)
+ return NULL;
+
+ mbp = _gem_engine_mmio_info_dup();
+
+ return mbp;
+}
+
+
+/**
+ * _gem_engine_mmio_base_info_get_debugfs:
+ * @fd_dev: file descriptor upon which device is open or -1 to use defaults.
+ *
+ * Obtains per-engine mmio_base information from debugfs.
+ *
+ * Returns:
+ * Pointer to dynamically allocated struct eng_mmio_base_table_s describing
+ * engine config or NULL.
+ * The allocated size does not include unused engine entries.
+ * If non-NULL, it is caller's responsibility to free.
+ *
+ * Looking in debugfs for per-engine instances of:
+ *
+ * ...
+ * MMIO base:
+ *
+ * Example of relevant lines from debugfs:
+ * vcs0
+ * MMIO base: 0x001c
+ * vcs1
+ * MMIO base: 0x001d
+ *
+ * In order to qualify as the introduction of a new per-engine section, an
+ * input line must consist solely of an engine name. An engine name must
+ * be 7 or fewer characters in length and must consist of an engine class
+ * name of 3 or more lower case characters followed by an instance number.
+ */
+static struct eng_mmio_base_table_s
*_gem_engine_mmio_base_info_get_debugfs(int fd_dev)
+{
+
[Intel-gfx] [PATCH i-g-t 0/3] mmio_base via debugfs infrastructure + gem_ctx_isolation
This patch series provides infrastructure to allow determination of i915 per-engine mmio_base (which is otherwise sometimes hard to get). The provided method uses debugfs mmio_base information if present. Otherwise, a default determination is provided when possible. Also, gem_ctx_isolation is modified to use the new infrastructure. For example, on TGL, gem_ctx_isolation (without these or similar changes) will fail for subtests that use engine vcs1. The patches in this series are as they are intended to be submitted (subject to comments), except I would like to squash the two gem_ctx_isolation "relative registers" patches into one (as discussed below). Also, function gem_engine_mmio_base_info_dump() could be removed. On 2020-01-27, Chris wilson sent to the ML: [igt-dev] [PATCH i-g-t 1/5] i915: Start putting the mmio_base to wider use [igt-dev] [PATCH i-g-t 2/5] i915/gem_ctx_isolation: Check engine relative registers plus the following, which are not addressed here: [igt-dev] [PATCH i-g-t 3/5] i915: Exercise preemption timeout controls in sysfs [igt-dev] [PATCH i-g-t 4/5] i915: Exercise sysfs heartbeat controls [igt-dev] [PATCH i-g-t 5/5] i915: Exercise timeslice sysfs property This patch list is: i915/gem_mmio_base.c - get mmio_base from debugfs (if possible) i915/gem_ctx_isolation: Check engine relative registers i915/gem_ctx_isolation: Check engine relative registers - Part 2 The first 2020-01-27 patch obtains mmio_base information via sysfs, and depends on a proposed kernel change that would provide the mmio_base information via sysfs. It is unclear when or whether that kernel change will progress. The mmio_base information used by this patch series is available through debugfs now (as of kernel 5.4). If the per-engine mmio_base information is ever added to sysfs, it would be easy to plug that into the infrastructure proposed here as an additional higher-priority source of that information. This submission replaces the first patch (switching from sysfs to debugfs), retains the second 2020-01-27 patch i915/gem_ctx_isolation: Check engine relative registers and has a third patch that modifies the original second patch to support the altered API: i915/gem_ctx_isolation: Check engine relative registers - Part 2 I propose squashing the two gem_ctx_isolation "relative registers" patches into one patch with author == "Chris Wilson" if Chris agrees. Some differences from the 2020-01-27 patches: The mmio_base information is fetched once into local data structures, and is obtained from them thereafter instead of being fetched from the kernel everytime it is wanted. The function that obtains the mmio_base information is called by a particular test that wants it, and returns a handle through which the mmio_base can be requested for any particular engine. These patches introduce new source files lib/i915/gem_mmio_base.c and lib/i915/gem_mmio_base.h. Should the code instead be placed into lib/i915/gem_engine_topology.c? Function gem_engine_mmio_base_info_dump presently exists to dump the mmio_base information to stdout for debugging or informational purposes. This function is not currently called. I presume this function should be removed. Is there any desire to keep it around for future use? The 2020-01-27 patches define function gem_engine_mmio_base() with its first parameter as "fd". The new patches replace the first parameter with the mmio_base object handle. Chris Wilson (1): i915/gem_ctx_isolation: Check engine relative registers Dale B Stimson (2): i915/gem_mmio_base.c - get mmio_base from debugfs (if possible) i915/gem_ctx_isolation: Check engine relative registers - Part 2 lib/Makefile.sources | 2 + lib/i915/gem_mmio_base.c | 346 + lib/i915/gem_mmio_base.h | 19 ++ lib/igt.h | 1 + lib/meson.build| 1 + tests/i915/gem_ctx_isolation.c | 229 +- 6 files changed, 506 insertions(+), 92 deletions(-) create mode 100644 lib/i915/gem_mmio_base.c create mode 100644 lib/i915/gem_mmio_base.h -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_nop: Keep a copy of the names
The engine names are now stored inside the iterator and not as static
strings. If we wish to use them later, we need to make a copy.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/i915/gem_exec_nop.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/tests/i915/gem_exec_nop.c b/tests/i915/gem_exec_nop.c
index ed9568e5a..fc7f11827 100644
--- a/tests/i915/gem_exec_nop.c
+++ b/tests/i915/gem_exec_nop.c
@@ -436,7 +436,7 @@ static void parallel(int fd, uint32_t handle, int timeout)
struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 obj;
unsigned engines[16];
- const char *names[16];
+ char *names[16];
unsigned nengine;
unsigned long count;
double time, sum;
@@ -445,7 +445,7 @@ static void parallel(int fd, uint32_t handle, int timeout)
nengine = 0;
__for_each_physical_engine(fd, e) {
engines[nengine] = e->flags;
- names[nengine++] = e->name;
+ names[nengine++] = strdup(e->name);
time = nop_on_ring(fd, handle, e, 1, ) / count;
sum += time;
@@ -485,10 +485,11 @@ static void parallel(int fd, uint32_t handle, int timeout)
time = elapsed(, ) / count;
igt_info("%s: %ld cycles, %.3fus\n", names[child], count,
1e6*time);
}
+ while (nengine--)
+ free(names[nengine]);
igt_waitchildren();
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
-
}
static void series(int fd, uint32_t handle, int timeout)
--
2.25.0
___
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Intel-gfx@lists.freedesktop.org
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Trim blitter block size (rev5)
== Series Details == Series: drm/i915/selftests: Trim blitter block size (rev5) URL : https://patchwork.freedesktop.org/series/73066/ State : success == Summary == CI Bug Log - changes from CI_DRM_7903 -> Patchwork_16512 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16512/index.html Known issues Here are the changes found in Patchwork_16512 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([fdo#111407]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16512/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@i915_selftest@live_blt: - fi-bsw-n3050: [INCOMPLETE][3] ([i915#392]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-bsw-n3050/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16512/fi-bsw-n3050/igt@i915_selftest@live_blt.html - fi-ivb-3770:[DMESG-FAIL][5] ([i915#725]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-ivb-3770/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16512/fi-ivb-3770/igt@i915_selftest@live_blt.html - fi-hsw-4770:[DMESG-FAIL][7] ([i915#553] / [i915#725]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-hsw-4770/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16512/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-8700k: [DMESG-FAIL][9] ([i915#623]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16512/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html - fi-byt-n2820: [DMESG-FAIL][11] ([i915#1052]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16512/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html - fi-cfl-guc: [INCOMPLETE][13] ([CI#80] / [fdo#106070] / [i915#424]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16512/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html - fi-cml-s: [DMESG-FAIL][15] ([i915#877]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cml-s/igt@i915_selftest@live_gem_contexts.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16512/fi-cml-s/igt@i915_selftest@live_gem_contexts.html Warnings * igt@gem_exec_parallel@fds: - fi-byt-n2820: [FAIL][17] ([i915#694]) -> [TIMEOUT][18] ([fdo#112271]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-byt-n2820/igt@gem_exec_paral...@fds.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16512/fi-byt-n2820/igt@gem_exec_paral...@fds.html [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1052]: https://gitlab.freedesktop.org/drm/intel/issues/1052 [i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#623]: https://gitlab.freedesktop.org/drm/intel/issues/623 [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877 Participating hosts (47 -> 43) -- Additional (4): fi-hsw-peppy fi-skl-lmem fi-gdg-551 fi-snb-2600 Missing(8): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-kbl-guc fi-byt-clapper fi-bsw-nick fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7903 -> Patchwork_16512 CI-20190529: 20190529 CI_DRM_7903: 47b768c475f4a11a48bc43e6228660f8b26a542b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5433: 6a96c17f3a1b4e1f90b1a0b0ce42a7219875d1a4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16512: 1b0c23fd95fa68e8be067333049dd94c47346579 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mst: Set intel_dp_set_m_n() for MST slaves (rev2)
== Series Details == Series: drm/i915/mst: Set intel_dp_set_m_n() for MST slaves (rev2) URL : https://patchwork.freedesktop.org/series/73252/ State : success == Summary == CI Bug Log - changes from CI_DRM_7903 -> Patchwork_16511 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16511/index.html Known issues Here are the changes found in Patchwork_16511 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2] ([i915#553] / [i915#725]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-hsw-4770r/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16511/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111407]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16511/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@gem_close_race@basic-threads: - fi-byt-j1900: [INCOMPLETE][5] ([i915#45]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16511/fi-byt-j1900/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][7] ([i915#553] / [i915#725]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-hsw-4770/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16511/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-8700k: [DMESG-FAIL][9] ([i915#623]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16511/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html - fi-cfl-guc: [INCOMPLETE][11] ([CI#80] / [fdo#106070] / [i915#424]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16511/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html Warnings * igt@runner@aborted: - fi-byt-j1900: [FAIL][13] ([i915#816]) -> [FAIL][14] ([i915#999]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-byt-j1900/igt@run...@aborted.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16511/fi-byt-j1900/igt@run...@aborted.html [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#623]: https://gitlab.freedesktop.org/drm/intel/issues/623 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 [i915#999]: https://gitlab.freedesktop.org/drm/intel/issues/999 Participating hosts (47 -> 39) -- Additional (3): fi-hsw-peppy fi-gdg-551 fi-snb-2600 Missing(11): fi-ilk-m540 fi-bdw-samus fi-bsw-n3050 fi-hsw-4200u fi-byt-squawks fi-snb-2520m fi-blb-e6850 fi-byt-n2820 fi-byt-clapper fi-bsw-nick fi-skl-6600u Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7903 -> Patchwork_16511 CI-20190529: 20190529 CI_DRM_7903: 47b768c475f4a11a48bc43e6228660f8b26a542b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5433: 6a96c17f3a1b4e1f90b1a0b0ce42a7219875d1a4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16511: 9d61ed99d6a150d1718d2f830438b92ba1ab4d87 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9d61ed99d6a1 drm/i915/mst: Set intel_dp_set_m_n() for MST slaves == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16511/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/7] drm/i915/gt: Avoid resetting ring->head outside of its timeline mutex
== Series Details == Series: series starting with [1/7] drm/i915/gt: Avoid resetting ring->head outside of its timeline mutex URL : https://patchwork.freedesktop.org/series/73256/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7903 -> Patchwork_16510 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16510 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16510, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16510/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16510: ### IGT changes ### Possible regressions * igt@i915_selftest@live_execlists: - fi-kbl-x1275: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-kbl-x1275/igt@i915_selftest@live_execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16510/fi-kbl-x1275/igt@i915_selftest@live_execlists.html - fi-kbl-8809g: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-kbl-8809g/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16510/fi-kbl-8809g/igt@i915_selftest@live_execlists.html Known issues Here are the changes found in Patchwork_16510 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-n2820: [PASS][5] -> [INCOMPLETE][6] ([i915#45]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16510/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_hangcheck: - fi-apl-guc: [PASS][7] -> [INCOMPLETE][8] ([fdo#103927]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-apl-guc/igt@i915_selftest@live_hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16510/fi-apl-guc/igt@i915_selftest@live_hangcheck.html - fi-glk-dsi: [PASS][9] -> [INCOMPLETE][10] ([i915#58] / [k.org#198133]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-glk-dsi/igt@i915_selftest@live_hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16510/fi-glk-dsi/igt@i915_selftest@live_hangcheck.html * igt@kms_chamelium@dp-crc-fast: - fi-cml-u2: [PASS][11] -> [FAIL][12] ([i915#262]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16510/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html Possible fixes * igt@i915_selftest@live_blt: - fi-bsw-n3050: [INCOMPLETE][13] ([i915#392]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-bsw-n3050/igt@i915_selftest@live_blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16510/fi-bsw-n3050/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-8700k: [DMESG-FAIL][15] ([i915#623]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16510/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gtt: - fi-bdw-5557u: [TIMEOUT][17] ([fdo#112271]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-bdw-5557u/igt@i915_selftest@live_gtt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16510/fi-bdw-5557u/igt@i915_selftest@live_gtt.html Warnings * igt@i915_selftest@live_gem_contexts: - fi-cfl-guc: [INCOMPLETE][19] ([CI#80] / [fdo#106070] / [i915#424]) -> [INCOMPLETE][20] ([fdo#106070] / [i915#424]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16510/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 [i915#45]:
[Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size
Reduce the amount of work we do to verify client blt correctness as
currently our 0.5s subtests takes about 15s on slower devices!
v2: Grow the maximum block size until we run out of time
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
.../i915/gem/selftests/i915_gem_object_blt.c | 72 ---
1 file changed, 46 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
index 62077fe46715..f29da4560dc0 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
@@ -210,6 +210,7 @@ static int igt_fill_blt_thread(void *arg)
struct intel_context *ce;
unsigned int prio;
IGT_TIMEOUT(end);
+ u64 total, max;
int err;
ctx = thread->ctx;
@@ -225,24 +226,28 @@ static int igt_fill_blt_thread(void *arg)
ce = i915_gem_context_get_engine(ctx, BCS0);
GEM_BUG_ON(IS_ERR(ce));
+ /*
+* If we have a tiny shared address space, like for the GGTT
+* then we can't be too greedy.
+*/
+ max = ce->vm->total;
+ if (i915_is_ggtt(ce->vm) || thread->ctx)
+ max = div_u64(max, thread->n_cpus);
+ max >>= 4;
+
+ total = PAGE_SIZE;
do {
- const u32 max_block_size = S16_MAX * PAGE_SIZE;
+ /* Aim to keep the runtime under reasonable bounds! */
+ const u32 max_phys_size = SZ_64K;
u32 val = prandom_u32_state(prng);
- u64 total = ce->vm->total;
u32 phys_sz;
u32 sz;
u32 *vaddr;
u32 i;
- /*
-* If we have a tiny shared address space, like for the GGTT
-* then we can't be too greedy.
-*/
- if (i915_is_ggtt(ce->vm))
- total = div64_u64(total, thread->n_cpus);
-
- sz = min_t(u64, total >> 4, prandom_u32_state(prng));
- phys_sz = sz % (max_block_size + 1);
+ total = min(total, max);
+ sz = i915_prandom_u32_max_state(total, prng) + 1;
+ phys_sz = sz % max_phys_size;
sz = round_up(sz, PAGE_SIZE);
phys_sz = round_up(phys_sz, PAGE_SIZE);
@@ -276,13 +281,14 @@ static int igt_fill_blt_thread(void *arg)
if (err)
goto err_unpin;
- i915_gem_object_lock(obj);
- err = i915_gem_object_set_to_cpu_domain(obj, false);
- i915_gem_object_unlock(obj);
+ err = i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT);
if (err)
goto err_unpin;
- for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32);
++i) {
+ for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32); i
+= 17) {
+ if (!(obj->cache_coherent &
I915_BO_CACHE_COHERENT_FOR_READ))
+ drm_clflush_virt_range([i],
sizeof(vaddr[i]));
+
if (vaddr[i] != val) {
pr_err("vaddr[%u]=%x, expected=%x\n", i,
vaddr[i], val);
@@ -293,6 +299,8 @@ static int igt_fill_blt_thread(void *arg)
i915_gem_object_unpin_map(obj);
i915_gem_object_put(obj);
+
+ total <<= 1;
} while (!time_after(jiffies, end));
goto err_flush;
@@ -319,6 +327,7 @@ static int igt_copy_blt_thread(void *arg)
struct intel_context *ce;
unsigned int prio;
IGT_TIMEOUT(end);
+ u64 total, max;
int err;
ctx = thread->ctx;
@@ -334,20 +343,28 @@ static int igt_copy_blt_thread(void *arg)
ce = i915_gem_context_get_engine(ctx, BCS0);
GEM_BUG_ON(IS_ERR(ce));
+ /*
+* If we have a tiny shared address space, like for the GGTT
+* then we can't be too greedy.
+*/
+ max = ce->vm->total;
+ if (i915_is_ggtt(ce->vm) || thread->ctx)
+ max = div_u64(max, thread->n_cpus);
+ max >>= 4;
+
+ total = PAGE_SIZE;
do {
- const u32 max_block_size = S16_MAX * PAGE_SIZE;
+ /* Aim to keep the runtime under reasonable bounds! */
+ const u32 max_phys_size = SZ_64K;
u32 val = prandom_u32_state(prng);
- u64 total = ce->vm->total;
u32 phys_sz;
u32 sz;
u32 *vaddr;
u32 i;
- if (i915_is_ggtt(ce->vm))
- total = div64_u64(total, thread->n_cpus);
-
- sz = min_t(u64, total >> 4, prandom_u32_state(prng));
- phys_sz = sz % (max_block_size + 1);
+ total = min(total, max);
+ sz =
Re: [Intel-gfx] [PATCH] drm/i915/selftests: Trim blitter block size
Quoting Chris Wilson (2020-02-10 12:52:26) > Quoting Matthew Auld (2020-02-10 12:47:35) > > On Thu, 6 Feb 2020 at 14:10, Chris Wilson wrote: > > > > > > Reduce the amount of work we do to verify client blt correctness as > > > currently our 0.5s subtests takes about 15s on slower devices! > > > > > > v2: Grow the maximum block size until we run out of time > > > > > > Signed-off-by: Chris Wilson > > > > Is that bsw-kefka issue(coherency?) something new? > > It's something to worry about. Oh, it's just the vlv/chv clflush bug. Nothing to see here... -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915/gt: Avoid resetting ring->head outside of its timeline mutex
== Series Details ==
Series: series starting with [1/7] drm/i915/gt: Avoid resetting ring->head
outside of its timeline mutex
URL : https://patchwork.freedesktop.org/series/73256/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1f4fe3bfcb66 drm/i915/gt: Avoid resetting ring->head outside of its timeline
mutex
-:15: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#15:
References: f3c0efc9fe7a ("drm/i915/execlists: Leave resetting ring to
intel_ring")
-:15: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit f3c0efc9fe7a
("drm/i915/execlists: Leave resetting ring to intel_ring")'
#15:
References: f3c0efc9fe7a ("drm/i915/execlists: Leave resetting ring to
intel_ring")
total: 1 errors, 1 warnings, 0 checks, 115 lines checked
5bf840c72399 drm/i915/selftests: Exercise timeslice rewinding
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#13:
References: 5ba32c7be81e ("drm/i915/execlists: Always force a context reload
when rewinding RING_TAIL")
-:13: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 5ba32c7be81e
("drm/i915/execlists: Always force a context reload when rewinding RING_TAIL")'
#13:
References: 5ba32c7be81e ("drm/i915/execlists: Always force a context reload
when rewinding RING_TAIL")
-:189: WARNING:MEMORY_BARRIER: memory barrier without comment
#189: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:929:
+ wmb();
-:219: WARNING:MEMORY_BARRIER: memory barrier without comment
#219: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:959:
+ wmb();
total: 1 errors, 3 warnings, 0 checks, 221 lines checked
2351ed092201 drm/i915/selftests: Relax timeout for error-interrupt reset
processing
6ad77fccd647 drm/i915/gem: Don't leak non-persistent requests on changing
engines
-:249: WARNING:USE_SPINLOCK_T: struct spinlock should be spinlock_t
#249: FILE: drivers/gpu/drm/i915/gem/i915_gem_context_types.h:184:
+ struct spinlock lock;
total: 0 errors, 1 warnings, 0 checks, 246 lines checked
e015db52f116 drm/i915: Disable use of hwsp_cacheline for kernel_context
49bdac891f25 drm/i915/gt: Yield the timeslice if caught waiting on a user
semaphore
034350519d42 drm/i915/execlists: Remove preempt-to-busy roundtrip delay
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Program MBUS with rmw during initialization (rev2)
== Series Details == Series: series starting with [1/2] drm/i915: Program MBUS with rmw during initialization (rev2) URL : https://patchwork.freedesktop.org/series/72950/ State : success == Summary == CI Bug Log - changes from CI_DRM_7903 -> Patchwork_16509 Summary --- **WARNING** Minor unknown changes coming with Patchwork_16509 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16509, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16509/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16509: ### IGT changes ### Warnings * igt@i915_pm_rpm@module-reload: - fi-ivb-3770:[SKIP][1] ([fdo#109271]) -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-ivb-3770/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16509/fi-ivb-3770/igt@i915_pm_...@module-reload.html Known issues Here are the changes found in Patchwork_16509 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_parallel@basic: - fi-byt-n2820: [PASS][3] -> [TIMEOUT][4] ([fdo#112271]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-byt-n2820/igt@gem_exec_paral...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16509/fi-byt-n2820/igt@gem_exec_paral...@basic.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][5] -> [DMESG-FAIL][6] ([i915#553] / [i915#725]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-hsw-4770r/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16509/fi-hsw-4770r/igt@i915_selftest@live_blt.html Possible fixes * igt@i915_selftest@live_blt: - fi-bsw-n3050: [INCOMPLETE][7] ([i915#392]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-bsw-n3050/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16509/fi-bsw-n3050/igt@i915_selftest@live_blt.html - fi-hsw-4770:[DMESG-FAIL][9] ([i915#553] / [i915#725]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-hsw-4770/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16509/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-8700k: [DMESG-FAIL][11] ([i915#623]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16509/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html - fi-byt-n2820: [DMESG-FAIL][13] ([i915#1052]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16509/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html - fi-cfl-guc: [INCOMPLETE][15] ([CI#80] / [fdo#106070] / [i915#424]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16509/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html - fi-cml-s: [DMESG-FAIL][17] ([i915#877]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cml-s/igt@i915_selftest@live_gem_contexts.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16509/fi-cml-s/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gtt: - fi-bdw-5557u: [TIMEOUT][19] ([fdo#112271]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-bdw-5557u/igt@i915_selftest@live_gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16509/fi-bdw-5557u/igt@i915_selftest@live_gtt.html [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1052]: https://gitlab.freedesktop.org/drm/intel/issues/1052 [i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#623]: https://gitlab.freedesktop.org/drm/intel/issues/623 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#877]:
Re: [Intel-gfx] [PATCH 3/3] drm/i915/gtt: Downgrade gen7 (ivb, byt, hsw) back to aliasing-ppgtt
On Sat, Feb 08, 2020 at 10:01:06PM +, Chris Wilson wrote:
> Full-ppgtt on gen7 is proving to be highly unstable and not robust.
>
> Fixes: 3cd6e8860ecd ("drm/i915/gen7: Re-enable full-ppgtt for ivb & hsw")
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> ---
Acked-by: Rodrigo Vivi
> drivers/gpu/drm/i915/i915_pci.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 24b1f0ce8743..1d678aa7d420 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -437,7 +437,7 @@ static const struct intel_device_info snb_m_gt2_info = {
> .has_rc6 = 1, \
> .has_rc6p = 1, \
> .has_rps = true, \
> - .ppgtt_type = INTEL_PPGTT_FULL, \
> + .ppgtt_type = INTEL_PPGTT_ALIASING, \
> .ppgtt_size = 31, \
> IVB_PIPE_OFFSETS, \
> IVB_CURSOR_OFFSETS, \
> @@ -494,7 +494,7 @@ static const struct intel_device_info vlv_info = {
> .has_rps = true,
> .display.has_gmch = 1,
> .display.has_hotplug = 1,
> - .ppgtt_type = INTEL_PPGTT_FULL,
> + .ppgtt_type = INTEL_PPGTT_ALIASING,
> .ppgtt_size = 31,
> .has_snoop = true,
> .has_coherent_ggtt = false,
> --
> 2.25.0
>
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Add Wa_22010178259:tgl
== Series Details == Series: drm/i915/tgl: Add Wa_22010178259:tgl URL : https://patchwork.freedesktop.org/series/73255/ State : success == Summary == CI Bug Log - changes from CI_DRM_7903 -> Patchwork_16508 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16508/index.html Known issues Here are the changes found in Patchwork_16508 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-bsw-nick:[PASS][1] -> [INCOMPLETE][2] ([i915#392]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-bsw-nick/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16508/fi-bsw-nick/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111096] / [i915#323]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16508/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@i915_selftest@live_blt: - fi-hsw-4770:[DMESG-FAIL][5] ([i915#553] / [i915#725]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-hsw-4770/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16508/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-8700k: [DMESG-FAIL][7] ([i915#623]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16508/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html - fi-cfl-guc: [INCOMPLETE][9] ([CI#80] / [fdo#106070] / [i915#424]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16508/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html - fi-cml-s: [DMESG-FAIL][11] ([i915#877]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cml-s/igt@i915_selftest@live_gem_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16508/fi-cml-s/igt@i915_selftest@live_gem_contexts.html [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#623]: https://gitlab.freedesktop.org/drm/intel/issues/623 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877 Participating hosts (47 -> 39) -- Additional (4): fi-hsw-peppy fi-skl-lmem fi-gdg-551 fi-snb-2600 Missing(12): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-glk-dsi fi-byt-squawks fi-ilk-650 fi-cfl-8109u fi-icl-u3 fi-bdw-samus fi-byt-n2820 fi-byt-clapper fi-skl-6600u Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7903 -> Patchwork_16508 CI-20190529: 20190529 CI_DRM_7903: 47b768c475f4a11a48bc43e6228660f8b26a542b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5433: 6a96c17f3a1b4e1f90b1a0b0ce42a7219875d1a4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16508: 70b7d6e6151834638f8d1158e993023e1daa5091 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 70b7d6e61518 drm/i915/tgl: Add Wa_22010178259:tgl == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16508/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/7] drm/i915/gt: Avoid resetting ring->head outside of its timeline mutex
We manipulate ring->head while active in i915_request_retire underneath
the timeline manipulation. We cannot rely on a stable ring->head outside
of the timeline->mutex, in particular while setting up the context for
resume and reset.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1126
Fixes: 0881954965e3 ("drm/i915: Introduce intel_context.pin_mutex for pin
management")
Fixes: e5dadff4b093 ("drm/i915: Protect request retirement with
timeline->mutex")
References: f3c0efc9fe7a ("drm/i915/execlists: Leave resetting ring to
intel_ring")
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c| 36 --
drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +-
2 files changed, 18 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 929be03bbe7e..70d91ad923ef 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -235,7 +235,8 @@ static void execlists_init_reg_state(u32 *reg_state,
bool close);
static void
__execlists_update_reg_state(const struct intel_context *ce,
-const struct intel_engine_cs *engine);
+const struct intel_engine_cs *engine,
+u32 head);
static void mark_eio(struct i915_request *rq)
{
@@ -1184,12 +1185,11 @@ static void reset_active(struct i915_request *rq,
head = rq->tail;
else
head = active_request(ce->timeline, rq)->head;
- ce->ring->head = intel_ring_wrap(ce->ring, head);
- intel_ring_update_space(ce->ring);
+ head = intel_ring_wrap(ce->ring, head);
/* Scrub the context image to prevent replaying the previous batch */
restore_default_state(ce, engine);
- __execlists_update_reg_state(ce, engine);
+ __execlists_update_reg_state(ce, engine, head);
/* We've switched away, so this should be a no-op, but intent matters */
ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
@@ -2878,16 +2878,17 @@ static void execlists_context_unpin(struct
intel_context *ce)
static void
__execlists_update_reg_state(const struct intel_context *ce,
-const struct intel_engine_cs *engine)
+const struct intel_engine_cs *engine,
+u32 head)
{
struct intel_ring *ring = ce->ring;
u32 *regs = ce->lrc_reg_state;
- GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
+ GEM_BUG_ON(!intel_ring_offset_valid(ring, head));
GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
- regs[CTX_RING_HEAD] = ring->head;
+ regs[CTX_RING_HEAD] = head;
regs[CTX_RING_TAIL] = ring->tail;
/* RPCS */
@@ -2916,7 +2917,7 @@ __execlists_context_pin(struct intel_context *ce,
ce->lrc_desc = lrc_descriptor(ce, engine) | CTX_DESC_FORCE_RESTORE;
ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
- __execlists_update_reg_state(ce, engine);
+ __execlists_update_reg_state(ce, engine, ce->ring->tail);
return 0;
}
@@ -2941,7 +2942,7 @@ static void execlists_context_reset(struct intel_context
*ce)
/* Scrub away the garbage */
execlists_init_reg_state(ce->lrc_reg_state,
ce, ce->engine, ce->ring, true);
- __execlists_update_reg_state(ce, ce->engine);
+ __execlists_update_reg_state(ce, ce->engine, ce->ring->tail);
ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
}
@@ -3538,6 +3539,7 @@ static void __execlists_reset(struct intel_engine_cs
*engine, bool stalled)
struct intel_engine_execlists * const execlists = >execlists;
struct intel_context *ce;
struct i915_request *rq;
+ u32 head;
mb(); /* paranoia: read the CSB pointers from after the reset */
clflush(execlists->csb_write);
@@ -3565,15 +3567,15 @@ static void __execlists_reset(struct intel_engine_cs
*engine, bool stalled)
if (i915_request_completed(rq)) {
/* Idle context; tidy up the ring so we can restart afresh */
- ce->ring->head = intel_ring_wrap(ce->ring, rq->tail);
+ head = intel_ring_wrap(ce->ring, rq->tail);
goto out_replay;
}
/* Context has requests still in-flight; it should not be idle! */
GEM_BUG_ON(i915_active_is_idle(>active));
rq = active_request(ce->timeline, rq);
- ce->ring->head = intel_ring_wrap(ce->ring, rq->head);
- GEM_BUG_ON(ce->ring->head == ce->ring->tail);
+ head = intel_ring_wrap(ce->ring, rq->head);
+ GEM_BUG_ON(head == ce->ring->tail);
/*
* If this request hasn't started yet, e.g. it is waiting on a
@@ -3618,10 +3620,9 @@ static void
[Intel-gfx] [PATCH 3/7] drm/i915/selftests: Relax timeout for error-interrupt reset processing
We can not require that the system process a tasklet in reasonable time
(thanks be to ksoftirqd), but we can insist that having waited
sufficiently for the error interrupt to have been raised and having
kicked the tasklet, the reset has begun and the request will be marked
as in error (if not already completed).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 8b7383f6d9b3..ccd4cd2c202d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -503,14 +503,21 @@ static int live_error_interrupt(void *arg)
}
for (i = 0; i < ARRAY_SIZE(client); i++) {
- if (i915_request_wait(client[i], 0, HZ / 5) <
0) {
- pr_err("%s: %s request still
executing!\n",
- engine->name,
- error_repr(p->error[i]));
+ if (i915_request_wait(client[i], 0, HZ / 5) < 0)
+ pr_debug("%s: %s request incomplete!\n",
+engine->name,
+error_repr(p->error[i]));
+
+ if (!i915_request_started(client[i])) {
+ pr_debug("%s: %s request not stated!\n",
+engine->name,
+error_repr(p->error[i]));
err = -ETIME;
goto out;
}
+ /* Kick the tasklet to process the error */
+ intel_engine_flush_submission(engine);
if (client[i]->fence.error != p->error[i]) {
pr_err("%s: %s request completed with
wrong error code: %d\n",
engine->name,
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/7] drm/i915/gem: Don't leak non-persistent requests on changing engines
If we have a set of active engines marked as being non-persistent, we
lose track of those if the user replaces those engines with
I915_CONTEXT_PARAM_ENGINES. As part of our uABI contract is that
non-persistent requests are terminated if they are no longer being
tracked by the user's context (in order to prevent a lost request
causing an untracked and so unstoppable GPU hang), we need to apply the
same context cancellation upon changing engines.
v2: Track stale engines[] so we only reap at context closure.
Fixes: a0e047156cde ("drm/i915/gem: Make context persistence optional")
Testcase: igt/gem_ctx_peristence/replace
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 118 --
.../gpu/drm/i915/gem/i915_gem_context_types.h | 13 +-
drivers/gpu/drm/i915/i915_sw_fence.c | 19 ++-
drivers/gpu/drm/i915/i915_sw_fence.h | 2 +-
4 files changed, 139 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index cfaf5bbdbcab..ba29462bd501 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -270,7 +270,8 @@ static struct i915_gem_engines *default_engines(struct
i915_gem_context *ctx)
if (!e)
return ERR_PTR(-ENOMEM);
- init_rcu_head(>rcu);
+ e->ctx = ctx;
+
for_each_engine(engine, gt, id) {
struct intel_context *ce;
@@ -450,7 +451,7 @@ static struct intel_engine_cs *active_engine(struct
intel_context *ce)
return engine;
}
-static void kill_context(struct i915_gem_context *ctx)
+static void kill_engines(struct i915_gem_engines *engines)
{
struct i915_gem_engines_iter it;
struct intel_context *ce;
@@ -462,7 +463,7 @@ static void kill_context(struct i915_gem_context *ctx)
* However, we only care about pending requests, so only include
* engines on which there are incomplete requests.
*/
- for_each_gem_engine(ce, __context_engines_static(ctx), it) {
+ for_each_gem_engine(ce, engines, it) {
struct intel_engine_cs *engine;
if (intel_context_set_banned(ce))
@@ -484,10 +485,41 @@ static void kill_context(struct i915_gem_context *ctx)
* the context from the GPU, we have to resort to a full
* reset. We hope the collateral damage is worth it.
*/
- __reset_context(ctx, engine);
+ __reset_context(engines->ctx, engine);
}
}
+static void kill_stale_engines(struct i915_gem_context *ctx)
+{
+ struct i915_gem_engines *pos, *next;
+ unsigned long flags;
+
+ spin_lock_irqsave(>stale.lock, flags);
+ list_for_each_entry_safe(pos, next, >stale.engines, link) {
+ if (!i915_sw_fence_await(>fence))
+ continue;
+
+ spin_unlock_irqrestore(>stale.lock, flags);
+
+ kill_engines(pos);
+
+ spin_lock_irqsave(>stale.lock, flags);
+ list_safe_reset_next(pos, next, link);
+ list_del_init(>link); /* decouple from FENCE_COMPLETE */
+
+ i915_sw_fence_complete(>fence);
+ }
+ spin_unlock_irqrestore(>stale.lock, flags);
+}
+
+static void kill_context(struct i915_gem_context *ctx)
+{
+ if (!list_empty(>stale.engines))
+ kill_stale_engines(ctx);
+
+ kill_engines(__context_engines_static(ctx));
+}
+
static void set_closed_name(struct i915_gem_context *ctx)
{
char *s;
@@ -602,6 +634,9 @@ __create_context(struct drm_i915_private *i915)
ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL);
mutex_init(>mutex);
+ spin_lock_init(>stale.lock);
+ INIT_LIST_HEAD(>stale.engines);
+
mutex_init(>engines_mutex);
e = default_engines(ctx);
if (IS_ERR(e)) {
@@ -1529,6 +1564,71 @@ static const i915_user_extension_fn
set_engines__extensions[] = {
[I915_CONTEXT_ENGINES_EXT_BOND] = set_engines__bond,
};
+static int engines_notify(struct i915_sw_fence *fence,
+ enum i915_sw_fence_notify state)
+{
+ struct i915_gem_engines *engines =
+ container_of(fence, typeof(*engines), fence);
+
+ switch (state) {
+ case FENCE_COMPLETE:
+ if (!list_empty(>link)) {
+ struct i915_gem_context *ctx = engines->ctx;
+ unsigned long flags;
+
+ spin_lock_irqsave(>stale.lock, flags);
+ list_del(>link);
+ spin_unlock_irqrestore(>stale.lock, flags);
+ }
+ break;
+
+ case FENCE_FREE:
+ init_rcu_head(>rcu);
+ call_rcu(>rcu, free_engines_rcu);
+ break;
+ }
+
+ return
[Intel-gfx] [PATCH 6/7] drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore
If we find ourselves waiting on a MI_SEMAPHORE_WAIT, either within the
user batch or in our own preamble, the engine raises a
GT_WAIT_ON_SEMAPHORE interrupt. We can unmask that interrupt and so
respond to a semaphore wait by yielding the timeslice, if we have
another context to yield to!
The only real complication is that the interrupt is only generated for
the start of the semaphore wait, and is asynchronous to our
process_csb() -- that is, we may not have registered the timeslice before
we see the interrupt. To ensure we don't miss a potential semaphore
blocking forward progress (e.g. selftests/live_timeslice_preempt) we mark
the interrupt and apply it to the next timeslice regardless of whether it
was active at the time.
v2: We use semaphores in preempt-to-busy, within the timeslicing
implementation itself! Ergo, when we do insert a preemption due to an
expired timeslice, the new context may start with the missed semaphore
flagged by the retired context and be yielded, ad infinitum. To avoid
this, read the context id at the time of the semaphore interrupt and
only yield if that context is still active.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6 +++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 ++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 40 +---
drivers/gpu/drm/i915/i915_reg.h | 1 +
5 files changed, 61 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f6f5e1ec48fc..89f201a5a219 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1288,6 +1288,12 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
+ if (HAS_EXECLISTS(dev_priv)) {
+ drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
+ ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
+ drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
+ ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
+ }
drm_printf(m, "\tRING_START: 0x%08x\n",
ENGINE_READ(engine, RING_START));
drm_printf(m, "\tRING_HEAD: 0x%08x\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index b23366a81048..24cff658e6e5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -156,6 +156,15 @@ struct intel_engine_execlists {
*/
struct i915_priolist default_priolist;
+ /**
+* @yield: CCID at the time of the last semaphore-wait interrupt.
+*
+* Instead of leaving a semaphore busy-spinning on an engine, we would
+* like to switch to another ready context, i.e. yielding the semaphore
+* timeslice.
+*/
+ u32 yield;
+
/**
* @error_interrupt: CS Master EIR
*
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index f0e7fd95165a..875bd0392ffc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -39,6 +39,13 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
}
}
+ if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) {
+ WRITE_ONCE(engine->execlists.yield,
+ ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI));
+ if (del_timer(>execlists.timer))
+ tasklet = true;
+ }
+
if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
tasklet = true;
@@ -228,7 +235,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
const u32 irqs =
GT_CS_MASTER_ERROR_INTERRUPT |
GT_RENDER_USER_INTERRUPT |
- GT_CONTEXT_SWITCH_INTERRUPT;
+ GT_CONTEXT_SWITCH_INTERRUPT |
+ GT_WAIT_SEMAPHORE_INTERRUPT;
struct intel_uncore *uncore = gt->uncore;
const u32 dmask = irqs << 16 | irqs;
const u32 smask = irqs << 16;
@@ -366,7 +374,8 @@ void gen8_gt_irq_postinstall(struct intel_gt *gt)
const u32 irqs =
GT_CS_MASTER_ERROR_INTERRUPT |
GT_RENDER_USER_INTERRUPT |
- GT_CONTEXT_SWITCH_INTERRUPT;
+ GT_CONTEXT_SWITCH_INTERRUPT |
+ GT_WAIT_SEMAPHORE_INTERRUPT;
const u32 gt_interrupts[] = {
irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT,
irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT,
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 902d440ef07d..696f0b6b223c 100644
---
[Intel-gfx] [PATCH 5/7] drm/i915: Disable use of hwsp_cacheline for kernel_context
Currently on execlists, we use a local hwsp for the kernel_context,
rather than the engine's HWSP, as this is the default for execlists.
However, seqno rollover requires allocating a new HWSP cachline, and may
require pinning a new HWSP page in the GTT. This operation requiring
pinning in the GGTT is not allowed within the kernel_context timeline,
as doing so may require re-entering the kernel_context in order to evict
from the GGTT. As we want to avoid requiring a new HWSP for the
kernel_context, we can use the permanently pinned engine's HWSP instead.
However to do so we must prevent the use of semaphores reading the
kernel_context's HWSP, as the use of semaphores do not support rollover
onto the same cacheline. Fortunately, the kernel_context is mostly
isolated, so unlikely to give benefit to semaphores.
Reported-by: Maarten Lankhorst
Signed-off-by: Chris Wilson
Cc: Maarten Lankhorst
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c| 14 --
drivers/gpu/drm/i915/gt/selftest_lrc.c | 12 +---
drivers/gpu/drm/i915/i915_request.c| 14 +-
3 files changed, 30 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 70d91ad923ef..902d440ef07d 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2964,7 +2964,8 @@ static int gen8_emit_init_breadcrumb(struct i915_request
*rq)
{
u32 *cs;
- GEM_BUG_ON(!i915_request_timeline(rq)->has_initial_breadcrumb);
+ if (!i915_request_timeline(rq)->has_initial_breadcrumb)
+ return 0;
cs = intel_ring_begin(rq, 6);
if (IS_ERR(cs))
@@ -4616,8 +4617,17 @@ static int __execlists_context_alloc(struct
intel_context *ce,
if (!ce->timeline) {
struct intel_timeline *tl;
+ struct i915_vma *hwsp;
+
+ /*
+* Use the static global HWSP for the kernel context, and
+* a dynamically allocated cacheline for everyone else.
+*/
+ hwsp = NULL;
+ if (unlikely(intel_context_is_barrier(ce)))
+ hwsp = engine->status_page.vma;
- tl = intel_timeline_create(engine->gt, NULL);
+ tl = intel_timeline_create(engine->gt, hwsp);
if (IS_ERR(tl)) {
ret = PTR_ERR(tl);
goto error_deref_obj;
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index ccd4cd2c202d..6f458f6d5523 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -3494,15 +3494,21 @@ static int bond_virtual_engine(struct intel_gt *gt,
rq[0] = ERR_PTR(-ENOMEM);
for_each_engine(master, gt, id) {
struct i915_sw_fence fence = {};
+ struct intel_context *ce;
if (master->class == class)
continue;
+ ce = intel_context_create(master);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ goto out;
+ }
+
memset_p((void *)rq, ERR_PTR(-EINVAL), ARRAY_SIZE(rq));
- rq[0] = igt_spinner_create_request(,
- master->kernel_context,
- MI_NOOP);
+ rq[0] = igt_spinner_create_request(, ce, MI_NOOP);
+ intel_context_put(ce);
if (IS_ERR(rq[0])) {
err = PTR_ERR(rq[0]);
goto out;
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 0ecc2cf64216..1adb8cf35f75 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -886,6 +886,12 @@ emit_semaphore_wait(struct i915_request *to,
struct i915_request *from,
gfp_t gfp)
{
+ if (!intel_context_use_semaphores(to->context))
+ goto await_fence;
+
+ if (!rcu_access_pointer(from->hwsp_cacheline))
+ goto await_fence;
+
/* Just emit the first semaphore we see as request space is limited. */
if (already_busywaiting(to) & from->engine->mask)
goto await_fence;
@@ -931,12 +937,8 @@ i915_request_await_request(struct i915_request *to, struct
i915_request *from)
ret = i915_sw_fence_await_sw_fence_gfp(>submit,
>submit,
I915_FENCE_GFP);
- else if (intel_context_use_semaphores(to->context))
- ret = emit_semaphore_wait(to, from, I915_FENCE_GFP);
else
- ret = i915_sw_fence_await_dma_fence(>submit,
- >fence, 0,
-
[Intel-gfx] [PATCH 7/7] drm/i915/execlists: Remove preempt-to-busy roundtrip delay
To prevent the context from proceeding past the end of the request as we
unwind, we embed a semaphore into the footer of each request. (If the
context were to skip past the end of the request as we perform the
preemption, next time we reload the context it's RING_HEAD would be past
the RING_TAIL and instead of replaying the commands it would read the
read of the uninitialised ringbuffer.)
However, this requires us to keep the ring paused at the end of the
request until we have a change to process the preemption ack and remove
the semaphore. Our processing of acks is at the whim of ksoftirqd, and
so it is entirely possible that the GPU has to wait for the tasklet
before it can proceed with the next request.
It was suggested that we could also embed a MI_LOAD_REGISTER_MEM into
the footer to read the current RING_TAIL from the context, which would
allow us to not only avoid this round trip (and so release the context
as soon as we had submitted the preemption request to in ELSP), but also
skip using ELSP for lite-restores entirely. That has the nice benefit of
dramatically reducing contention and the frequency of interrupts when a
client submits two or more execbufs in rapid succession.
However, mmio access to RING_TAIL was defeatured in gen11 so we can only
employ this handy trick for gen8/gen9.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 23 +++--
drivers/gpu/drm/i915/gt/intel_lrc.c | 99 +++-
2 files changed, 109 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 24cff658e6e5..ae8724915320 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -488,14 +488,15 @@ struct intel_engine_cs {
/* status_notifier: list of callbacks for context-switch changes */
struct atomic_notifier_head context_status_notifier;
-#define I915_ENGINE_USING_CMD_PARSER BIT(0)
-#define I915_ENGINE_SUPPORTS_STATS BIT(1)
-#define I915_ENGINE_HAS_PREEMPTION BIT(2)
-#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
-#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
-#define I915_ENGINE_IS_VIRTUAL BIT(5)
-#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
-#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
+#define I915_ENGINE_REQUIRES_CMD_PARSERBIT(0)
+#define I915_ENGINE_USING_CMD_PARSER BIT(1)
+#define I915_ENGINE_SUPPORTS_STATS BIT(2)
+#define I915_ENGINE_HAS_PREEMPTION BIT(3)
+#define I915_ENGINE_HAS_SEMAPHORES BIT(4)
+#define I915_ENGINE_HAS_TAIL_LRM BIT(5)
+#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(6)
+#define I915_ENGINE_IS_VIRTUAL BIT(7)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(8)
unsigned int flags;
/*
@@ -592,6 +593,12 @@ intel_engine_has_semaphores(const struct intel_engine_cs
*engine)
return engine->flags & I915_ENGINE_HAS_SEMAPHORES;
}
+static inline bool
+intel_engine_has_tail_lrm(const struct intel_engine_cs *engine)
+{
+ return engine->flags & I915_ENGINE_HAS_TAIL_LRM;
+}
+
static inline bool
intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 696f0b6b223c..5939672781fb 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1797,6 +1797,74 @@ static inline void clear_ports(struct i915_request
**ports, int count)
memset_p((void **)ports, NULL, count);
}
+static struct i915_request *
+skip_lite_restore(struct intel_engine_cs *const engine,
+ struct i915_request *first,
+ bool *submit)
+{
+ struct intel_engine_execlists *const execlists = >execlists;
+ struct i915_request *last = first;
+ struct rb_node *rb;
+
+ if (!intel_engine_has_tail_lrm(engine))
+ return last;
+
+ GEM_BUG_ON(*submit);
+ while ((rb = rb_first_cached(>queue))) {
+ struct i915_priolist *p = to_priolist(rb);
+ struct i915_request *rq, *rn;
+ int i;
+
+ priolist_for_each_request_consume(rq, rn, p, i) {
+ if (!can_merge_rq(last, rq))
+ goto out;
+
+ if (__i915_request_submit(rq)) {
+ *submit = true;
+ last = rq;
+ }
+ }
+
+ rb_erase_cached(>node, >queue);
+ i915_priolist_free(p);
+ }
+out:
+ if (*submit) {
+ ring_set_paused(engine, 1);
+
+ /*
+* If we are quick and the current context hasn't yet completed
+* its request, we can just tell it to extend the RING_TAIL
+
[Intel-gfx] [PATCH 2/7] drm/i915/selftests: Exercise timeslice rewinding
Originally, I did not expect having to rewind a context upon
timeslicing: the point was to replace the executing context with an idle
one! However, given a second context that depends on requests from the
first, we may have to split the requests along the first context to
execute the second, causing us to replay the first context and have to
rewind the RING_TAIL.
References: 5ba32c7be81e ("drm/i915/execlists: Always force a context reload
when rewinding RING_TAIL")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 202 -
1 file changed, 201 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 82fa0712808e..8b7383f6d9b3 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -76,8 +76,11 @@ static int wait_for_submit(struct intel_engine_cs *engine,
do {
cond_resched();
intel_engine_flush_submission(engine);
- if (i915_request_is_active(rq))
+ if (i915_request_is_active(rq) &&
+ !READ_ONCE(engine->execlists.pending[0])) {
+ tasklet_unlock_wait(>execlists.tasklet);
return 0;
+ }
} while (time_before(jiffies, timeout));
return -ETIME;
@@ -772,6 +775,202 @@ static int live_timeslice_preempt(void *arg)
return err;
}
+static struct i915_request *
+create_rewinder(struct intel_context *ce,
+ struct i915_request *wait,
+ int slot)
+{
+ struct i915_request *rq;
+ u32 offset = i915_ggtt_offset(ce->engine->status_page.vma) + 4000;
+ u32 *cs;
+ int err;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ return rq;
+
+ if (wait) {
+ err = i915_request_await_dma_fence(rq, >fence);
+ if (err)
+ goto err;
+ }
+
+ cs = intel_ring_begin(rq, 10);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err;
+ }
+
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+ *cs++ = MI_NOOP;
+
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_NEQ_SDD;
+ *cs++ = 0;
+ *cs++ = offset;
+ *cs++ = 0;
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));
+ *cs++ = offset + slot * sizeof(u32);
+ *cs++ = 0;
+
+ intel_ring_advance(rq, cs);
+
+ rq->sched.attr.priority = I915_PRIORITY_MASK;
+ err = 0;
+err:
+ i915_request_get(rq);
+ i915_request_add(rq);
+ if (err) {
+ i915_request_put(rq);
+ return ERR_PTR(err);
+ }
+
+ return rq;
+}
+
+static int live_timeslice_rewind(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ /*
+* The usual presumption on timeslice expiration is that we replace
+* the active context with another. However, given a chain of
+* dependencies we may end up with replacing the context with itself,
+* but only a few of those requests, forcing us to rewind the
+* RING_TAIL of the original request.
+*/
+ if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
+ return 0;
+
+ for_each_engine(engine, gt, id) {
+ struct i915_request *rq[3] = {};
+ struct intel_context *ce;
+ unsigned long heartbeat;
+ unsigned long timeslice;
+ int i, err = 0;
+ u32 *slot;
+
+ if (!intel_engine_has_timeslices(engine))
+ continue;
+
+ /*
+* A:rq1 -- semaphore wait, timestamp X
+* A:rq2 -- write timestamp Y
+*
+* B:rq1 [await A:rq1] -- write timestamp Z
+*
+* Force timeslice, release sempahore.
+*
+* Expect evaluation order XZY
+*/
+
+ engine_heartbeat_disable(engine, );
+ timeslice = xchg(>props.timeslice_duration_ms, 1);
+
+ slot = memset(engine->status_page.addr + 1000,
+ 0, 4 * sizeof(u32));
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ goto err;
+ }
+
+ rq[0] = create_rewinder(ce, NULL, 1);
+ if (IS_ERR(rq[0])) {
+ intel_context_put(ce);
+ goto err;
+ }
+
+ rq[1] = create_rewinder(ce, NULL, 2);
+
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mst: Set intel_dp_set_m_n() for MST slaves
== Series Details == Series: drm/i915/mst: Set intel_dp_set_m_n() for MST slaves URL : https://patchwork.freedesktop.org/series/73252/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7903 -> Patchwork_16507 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16507 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16507, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16507/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16507: ### IGT changes ### Possible regressions * igt@i915_selftest@live_gt_mocs: - fi-bwr-2160:[PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-bwr-2160/igt@i915_selftest@live_gt_mocs.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16507/fi-bwr-2160/igt@i915_selftest@live_gt_mocs.html Known issues Here are the changes found in Patchwork_16507 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_parallel@fds: - fi-hsw-4770r: [PASS][3] -> [INCOMPLETE][4] ([i915#694]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-hsw-4770r/igt@gem_exec_paral...@fds.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16507/fi-hsw-4770r/igt@gem_exec_paral...@fds.html * igt@i915_selftest@live_execlists: - fi-icl-y: [PASS][5] -> [DMESG-FAIL][6] ([fdo#108569]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-icl-y/igt@i915_selftest@live_execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16507/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#111096] / [i915#323]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16507/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@gem_exec_parallel@contexts: - fi-byt-n2820: [FAIL][9] ([i915#694]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-byt-n2820/igt@gem_exec_paral...@contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16507/fi-byt-n2820/igt@gem_exec_paral...@contexts.html * igt@i915_selftest@live_blt: - fi-bsw-n3050: [INCOMPLETE][11] ([i915#392]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-bsw-n3050/igt@i915_selftest@live_blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16507/fi-bsw-n3050/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-8700k: [DMESG-FAIL][13] ([i915#623]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16507/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html - fi-byt-n2820: [DMESG-FAIL][15] ([i915#1052]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16507/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html - fi-cfl-guc: [INCOMPLETE][17] ([CI#80] / [fdo#106070] / [i915#424]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16507/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gtt: - fi-bdw-5557u: [TIMEOUT][19] ([fdo#112271]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-bdw-5557u/igt@i915_selftest@live_gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16507/fi-bdw-5557u/igt@i915_selftest@live_gtt.html Warnings * igt@gem_close_race@basic-threads: - fi-byt-j1900: [INCOMPLETE][21] ([i915#45]) -> [TIMEOUT][22] ([fdo#112271] / [i915#1084] / [i915#816]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16507/fi-byt-j1900/igt@gem_close_r...@basic-threads.html [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#111096]:
Re: [Intel-gfx] [PATCH] drm/i915/mst: Set intel_dp_set_m_n() for MST slaves
On Mon, 10 Feb 2020, José Roberto de Souza wrote:
> Commit 1c9d2eb24153 ("drm/i915: move intel_dp_set_m_n() to encoder for
> DDI platforms") moved the intel_dp_set_m_n() from hsw_crtc_enable()
> to intel_ddi_pre_enable_dp() but it missed add it to
> intel_mst_pre_enable_dp() causing MST slaves to not work.
>
> Fixes: 1c9d2eb24153 ("drm/i915: move intel_dp_set_m_n() to encoder for DDI
> platforms")
> Cc: Vandita Kulkarni
> Cc: Jani Nikula
> Signed-off-by: José Roberto de Souza
Damn it, this is the second DP MST thing I missed in the same
series. *facepalm*. The first goof-up was fixed in commit 274959622017
("drm/i915/mst: fix pipe and vblank enable"). We really need more MST in
CI.
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 9cd59141953d..d7bfa7c350e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -480,6 +480,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder
> *encoder,
> intel_ddi_enable_pipe_clock(pipe_config);
>
> intel_ddi_set_dp_msa(pipe_config, conn_state);
> +
> + intel_dp_set_m_n(pipe_config, M1_N1);
> }
>
> static void intel_mst_enable_dp(struct intel_encoder *encoder,
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_22010178259:tgl
We need to explicitly set the TLB Request Timer initial value in the
BW_BUDDY registers to 0x8 rather than relying on the hardware default.
Bspec: 52890
Bspec: 50044
Cc: Stanislav Lisovskiy
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h| 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 6e55e88ca0d0..2ad2694a28e6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5001,6 +5001,12 @@ static void tgl_bw_buddy_init(struct drm_i915_private
*dev_priv)
table[i].page_mask);
intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK,
table[i].page_mask);
+
+ /* Wa_22010178259:tgl */
+ intel_de_rmw(dev_priv, BW_BUDDY1_CTL,
+BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8);
+ intel_de_rmw(dev_priv, BW_BUDDY2_CTL,
+BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8);
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a6847f26678c..d829b9ae8402 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7766,6 +7766,7 @@ enum {
#define BW_BUDDY1_CTL _MMIO(0x45140)
#define BW_BUDDY2_CTL _MMIO(0x45150)
#define BW_BUDDY_DISABLE REG_BIT(31)
+#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
#define BW_BUDDY1_PAGE_MASK_MMIO(0x45144)
#define BW_BUDDY2_PAGE_MASK_MMIO(0x45154)
--
2.24.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for In order to readout DP SDPs, refactors the handling of DP SDPs (rev6)
== Series Details == Series: In order to readout DP SDPs, refactors the handling of DP SDPs (rev6) URL : https://patchwork.freedesktop.org/series/72853/ State : success == Summary == CI Bug Log - changes from CI_DRM_7903 -> Patchwork_16506 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16506/index.html Known issues Here are the changes found in Patchwork_16506 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload: - fi-skl-6770hq: [PASS][1] -> [DMESG-WARN][2] ([i915#92]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-skl-6770hq/igt@i915_module_l...@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16506/fi-skl-6770hq/igt@i915_module_l...@reload.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][3] -> [DMESG-FAIL][4] ([i915#725]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-hsw-4770r/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16506/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-skl-6770hq: [PASS][5] -> [SKIP][6] ([fdo#109271]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16506/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html * igt@kms_pipe_crc_basic@read-crc-pipe-b: - fi-skl-6770hq: [PASS][7] -> [DMESG-WARN][8] ([i915#106] / [i915#188]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16506/fi-skl-6770hq/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html Possible fixes * igt@i915_selftest@live_blt: - fi-bsw-n3050: [INCOMPLETE][9] ([i915#392]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-bsw-n3050/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16506/fi-bsw-n3050/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-8700k: [DMESG-FAIL][11] ([i915#623]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16506/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html - fi-cfl-guc: [INCOMPLETE][13] ([CI#80] / [fdo#106070] / [i915#424]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16506/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gtt: - fi-bdw-5557u: [TIMEOUT][15] ([fdo#112271]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-bdw-5557u/igt@i915_selftest@live_gtt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16506/fi-bdw-5557u/igt@i915_selftest@live_gtt.html Warnings * igt@gem_exec_parallel@fds: - fi-byt-n2820: [FAIL][17] ([i915#694]) -> [TIMEOUT][18] ([fdo#112271] / [i915#1084]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-byt-n2820/igt@gem_exec_paral...@fds.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16506/fi-byt-n2820/igt@gem_exec_paral...@fds.html * igt@runner@aborted: - fi-kbl-soraka: [FAIL][19] ([fdo#109383] / [fdo#111012]) -> [FAIL][20] ([i915#192] / [i915#193] / [i915#194]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-kbl-soraka/igt@run...@aborted.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16506/fi-kbl-soraka/igt@run...@aborted.html [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109383]: https://bugs.freedesktop.org/show_bug.cgi?id=109383 [fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#106]: https://gitlab.freedesktop.org/drm/intel/issues/106 [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084 [i915#188]: https://gitlab.freedesktop.org/drm/intel/issues/188 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392
Re: [Intel-gfx] [PATCH] drm/i915: Skip CPU synchronisation on dmabuf attachments
The patch is here: https://lists.freedesktop.org/archives/intel-gfx/2017-November/148988.html On Mon, Feb 10, 2020 at 11:34:07AM -0800, Dongwon Kim wrote: > Acked-by: Dongwon Kim > > It makes lots of sense to make CPU cache operation done only when > needed. Similar change was already landed in drm-prime and other > vendor specific drivers. We are actually seeing huge performance > boost in a specific customer case where dmabuf was used between > camera driver (importer) and i915 after applying this patch. > > Please consider upstreaming this code change. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Skip CPU synchronisation on dmabuf attachments
(mistakenly put a wrong message id in "In-reply-To") Acked-by: Dongwon Kim It makes lots of sense to make CPU cache operation done only when needed. Similar change was already landed in drm-prime and other vendor specific drivers. We are actually seeing huge performance boost in a specific customer case where dmabuf was used between camera driver (importer) and i915 after applying this patch. Please consider upstreaming this code change. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Skip CPU synchronisation on dmabuf attachments
Acked-by: Dongwon Kim It makes lots of sense to make CPU cache operation done only when needed. Similar change was already landed in drm-prime and other vendor specific drivers. We are actually seeing huge performance boost in a specific customer case where dmabuf was used between camera driver (importer) and i915 after applying this patch. Please consider upstreaming this code change. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for In order to readout DP SDPs, refactors the handling of DP SDPs (rev6)
== Series Details ==
Series: In order to readout DP SDPs, refactors the handling of DP SDPs (rev6)
URL : https://patchwork.freedesktop.org/series/72853/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5b39096a6173 drm: Add DP1.4 VSC SDP Payload related Data Structures
7b89b55cb716 drm/i915/dp: Add compute routine for DP VSC SDP
-:117: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#117: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2446:
+ drm_WARN_ON(_priv->drm, vsc->bpc == 6 &&
+ vsc->pixelformat == DP_PIXELFORMAT_RGB);
total: 0 errors, 0 warnings, 1 checks, 117 lines checked
a58f9a4670d6 drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP
32e44c015776 drm/i915/dp: Add writing of DP SDPs
90baf15b2a24 video/hdmi: Add Unpack only function for DRM infoframe
4cfa92180bee drm/i915/dp: Read out DP SDPs
182c420ece15 drm: Add logging function for DP VSC SDP
26f915701b32 drm/i915: Include HDMI DRM infoframe in the crtc state dump
877860d453ef drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state
dump
940af0cd4b8b drm/i915: Include DP VSC SDP in the crtc state dump
97c094247cb2 drm/i915: Program DP SDPs with computed configs
ca9ed0ad09e1 drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
2f41984fb5fa drm/i915: Add state readout for DP VSC SDP
-:82: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible
side-effects?
#82: FILE: drivers/gpu/drm/i915/display/intel_display.c:13895:
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+ if (!intel_compare_dp_vsc_sdp(_config->infoframes.name, \
+ _config->infoframes.name)) { \
+ pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset,
__stringify(name), \
+
_config->infoframes.name, \
+ _config->infoframes.name);
\
+ ret = false; \
+ } \
+} while (0)
total: 0 errors, 0 warnings, 1 checks, 74 lines checked
d29ea7802a66 drm/i915: Fix enabled infoframe states of lspcon
c10b0ee50bbe drm/i915: Program DP SDPs on pipe updates
b38bdf2a11e4 drm/i915: Stop sending DP SDPs on ddi disable
7d2beb287e3d drm/i915/dp: Add compute routine for DP PSR VSC SDP
25336a0274e2 drm/i915/psr: Use new DP VSC SDP compute routine on PSR
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[Intel-gfx] ✓ Fi.CI.BAT: success for HDCP 2.2 Comp fixes (rev2)
== Series Details == Series: HDCP 2.2 Comp fixes (rev2) URL : https://patchwork.freedesktop.org/series/73101/ State : success == Summary == CI Bug Log - changes from CI_DRM_7903 -> Patchwork_16505 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16505/index.html Known issues Here are the changes found in Patchwork_16505 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-byt-n2820: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-byt-n2820/igt@gem_close_r...@basic-threads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16505/fi-byt-n2820/igt@gem_close_r...@basic-threads.html * igt@i915_pm_rpm@basic-rte: - fi-hsw-4770:[PASS][3] -> [SKIP][4] ([fdo#109271]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-hsw-4770/igt@i915_pm_...@basic-rte.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16505/fi-hsw-4770/igt@i915_pm_...@basic-rte.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#111096] / [i915#323]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16505/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@i915_selftest@live_blt: - fi-bsw-n3050: [INCOMPLETE][7] ([i915#392]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-bsw-n3050/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16505/fi-bsw-n3050/igt@i915_selftest@live_blt.html - fi-ivb-3770:[DMESG-FAIL][9] ([i915#725]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-ivb-3770/igt@i915_selftest@live_blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16505/fi-ivb-3770/igt@i915_selftest@live_blt.html - fi-hsw-4770:[DMESG-FAIL][11] ([i915#553] / [i915#725]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-hsw-4770/igt@i915_selftest@live_blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16505/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-8700k: [DMESG-FAIL][13] ([i915#623]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16505/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html - fi-cfl-guc: [INCOMPLETE][15] ([CI#80] / [fdo#106070] / [i915#424]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16505/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html - fi-cml-s: [DMESG-FAIL][17] ([i915#877]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cml-s/igt@i915_selftest@live_gem_contexts.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16505/fi-cml-s/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gtt: - fi-bdw-5557u: [TIMEOUT][19] ([fdo#112271]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-bdw-5557u/igt@i915_selftest@live_gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16505/fi-bdw-5557u/igt@i915_selftest@live_gtt.html [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#623]: https://gitlab.freedesktop.org/drm/intel/issues/623 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877 Participating hosts (47 -> 45) -- Additional (3): fi-hsw-peppy fi-skl-lmem fi-snb-2600 Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7903 -> Patchwork_16505 CI-20190529: 20190529
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Avoid resetting ring->head outside of its timeline mutex
== Series Details == Series: drm/i915/gt: Avoid resetting ring->head outside of its timeline mutex URL : https://patchwork.freedesktop.org/series/73248/ State : success == Summary == CI Bug Log - changes from CI_DRM_7903 -> Patchwork_16504 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16504/index.html Known issues Here are the changes found in Patchwork_16504 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-hsw-4770r: [PASS][1] -> [DMESG-FAIL][2] ([i915#725]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-hsw-4770r/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16504/fi-hsw-4770r/igt@i915_selftest@live_blt.html Possible fixes * igt@gem_exec_parallel@fds: - fi-byt-n2820: [FAIL][3] ([i915#694]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-byt-n2820/igt@gem_exec_paral...@fds.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16504/fi-byt-n2820/igt@gem_exec_paral...@fds.html * igt@i915_selftest@live_blt: - fi-ivb-3770:[DMESG-FAIL][5] ([i915#725]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-ivb-3770/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16504/fi-ivb-3770/igt@i915_selftest@live_blt.html - fi-hsw-4770:[DMESG-FAIL][7] ([i915#553] / [i915#725]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-hsw-4770/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16504/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-8700k: [DMESG-FAIL][9] ([i915#623]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16504/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html - fi-byt-n2820: [DMESG-FAIL][11] ([i915#1052]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16504/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html - fi-cfl-guc: [INCOMPLETE][13] ([CI#80] / [fdo#106070] / [i915#424]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16504/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html - fi-cml-s: [DMESG-FAIL][15] ([i915#877]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-cml-s/igt@i915_selftest@live_gem_contexts.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16504/fi-cml-s/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gtt: - fi-bdw-5557u: [TIMEOUT][17] ([fdo#112271]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7903/fi-bdw-5557u/igt@i915_selftest@live_gtt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16504/fi-bdw-5557u/igt@i915_selftest@live_gtt.html [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1052]: https://gitlab.freedesktop.org/drm/intel/issues/1052 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#623]: https://gitlab.freedesktop.org/drm/intel/issues/623 [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877 Participating hosts (47 -> 42) -- Additional (4): fi-hsw-peppy fi-skl-lmem fi-gdg-551 fi-snb-2600 Missing(9): fi-ilk-m540 fi-bdw-samus fi-bsw-n3050 fi-hsw-4200u fi-byt-squawks fi-ilk-650 fi-blb-e6850 fi-byt-clapper fi-skl-6600u Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7903 -> Patchwork_16504 CI-20190529: 20190529 CI_DRM_7903: 47b768c475f4a11a48bc43e6228660f8b26a542b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5433: 6a96c17f3a1b4e1f90b1a0b0ce42a7219875d1a4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16504: 3838891e9c6169eed76e9b91ad655d9f39e5595f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3838891e9c61 drm/i915/gt: Avoid resetting ring->head outside of its timeline mutex == Logs == For more details
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Avoid resetting ring->head outside of its timeline mutex
== Series Details ==
Series: drm/i915/gt: Avoid resetting ring->head outside of its timeline mutex
URL : https://patchwork.freedesktop.org/series/73248/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3838891e9c61 drm/i915/gt: Avoid resetting ring->head outside of its timeline
mutex
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#13:
References: f3c0efc9fe7a ("drm/i915/execlists: Leave resetting ring to
intel_ring")
-:13: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit f3c0efc9fe7a
("drm/i915/execlists: Leave resetting ring to intel_ring")'
#13:
References: f3c0efc9fe7a ("drm/i915/execlists: Leave resetting ring to
intel_ring")
total: 1 errors, 1 warnings, 0 checks, 115 lines checked
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[Intel-gfx] [PATCH] drm/i915/mst: Set intel_dp_set_m_n() for MST slaves
Commit 1c9d2eb24153 ("drm/i915: move intel_dp_set_m_n() to encoder for
DDI platforms") moved the intel_dp_set_m_n() from hsw_crtc_enable()
to intel_ddi_pre_enable_dp() but it missed add it to
intel_mst_pre_enable_dp() causing MST slaves to not work.
Fixes: 1c9d2eb24153 ("drm/i915: move intel_dp_set_m_n() to encoder for DDI
platforms")
Cc: Vandita Kulkarni
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 9cd59141953d..d7bfa7c350e9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -480,6 +480,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder
*encoder,
intel_ddi_enable_pipe_clock(pipe_config);
intel_ddi_set_dp_msa(pipe_config, conn_state);
+
+ intel_dp_set_m_n(pipe_config, M1_N1);
}
static void intel_mst_enable_dp(struct intel_encoder *encoder,
--
2.25.0
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/ehl: Update port clock voltage level requirements
On Mon, Feb 10, 2020 at 04:05:34AM +, Patchwork wrote: > == Series Details == > > Series: series starting with [1/2] drm/i915/ehl: Update port clock voltage > level requirements > URL : https://patchwork.freedesktop.org/series/73123/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_7881_full -> Patchwork_16474_full > > > Summary > --- > > **SUCCESS** > > No regressions found. Applied to dinq. Thanks Jose for the reviews. Matt > > > > Known issues > > > Here are the changes found in Patchwork_16474_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_exec_schedule@preempt-bsd: > - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112146]) +2 similar > issues >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7881/shard-iclb5/igt@gem_exec_sched...@preempt-bsd.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16474/shard-iclb4/igt@gem_exec_sched...@preempt-bsd.html > > * igt@gem_partial_pwrite_pread@writes-after-reads-uncached: > - shard-hsw: [PASS][3] -> [FAIL][4] ([i915#694]) +1 similar issue >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7881/shard-hsw7/igt@gem_partial_pwrite_pr...@writes-after-reads-uncached.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16474/shard-hsw2/igt@gem_partial_pwrite_pr...@writes-after-reads-uncached.html > > * igt@gem_ppgtt@flink-and-close-vma-leak: > - shard-apl: [PASS][5] -> [FAIL][6] ([i915#644]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7881/shard-apl8/igt@gem_pp...@flink-and-close-vma-leak.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16474/shard-apl4/igt@gem_pp...@flink-and-close-vma-leak.html > > * igt@gem_tiled_blits@normal: > - shard-hsw: [PASS][7] -> [FAIL][8] ([i915#818]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7881/shard-hsw6/igt@gem_tiled_bl...@normal.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16474/shard-hsw5/igt@gem_tiled_bl...@normal.html > > * igt@gem_workarounds@suspend-resume-context: > - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +2 > similar issues >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7881/shard-apl8/igt@gem_workarou...@suspend-resume-context.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16474/shard-apl4/igt@gem_workarou...@suspend-resume-context.html > > * igt@i915_pm_dc@dc5-dpms: > - shard-iclb: [PASS][11] -> [FAIL][12] ([i915#447]) >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7881/shard-iclb6/igt@i915_pm...@dc5-dpms.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16474/shard-iclb3/igt@i915_pm...@dc5-dpms.html > > * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic: > - shard-glk: [PASS][13] -> [FAIL][14] ([i915#72]) >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7881/shard-glk5/igt@kms_cursor_leg...@2x-flip-vs-cursor-atomic.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16474/shard-glk3/igt@kms_cursor_leg...@2x-flip-vs-cursor-atomic.html > > * igt@kms_cursor_legacy@cursor-vs-flip-toggle: > - shard-hsw: [PASS][15] -> [FAIL][16] ([i915#57]) >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7881/shard-hsw8/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16474/shard-hsw6/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html > > * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: > - shard-skl: [PASS][17] -> [FAIL][18] ([IGT#5]) >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7881/shard-skl7/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16474/shard-skl8/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html > > * igt@kms_frontbuffer_tracking@fbc-suspend: > - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +6 > similar issues >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7881/shard-kbl3/igt@kms_frontbuffer_track...@fbc-suspend.html >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16474/shard-kbl2/igt@kms_frontbuffer_track...@fbc-suspend.html > > * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: > - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145]) >[21]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7881/shard-skl8/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html >[22]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16474/shard-skl7/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html > > * igt@kms_psr@psr2_sprite_plane_move: > - shard-iclb:
Re: [Intel-gfx] [PATCH] drm/i915/gt: Avoid resetting ring->head outside of its timeline mutex
Quoting Chris Wilson (2020-02-10 16:42:15)
> We manipulate ring->head while active in i915_request_retire underneath
> the timeline manipulation. We cannot rely on a stable ring->head outside
> of the timeline->mutex, in particular while setting up the context for
> resume and reset.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/1126
Fixes: 0881954965e3 ("drm/i915: Introduce intel_context.pin_mutex for pin
management")
Fixes: e5dadff4b093 ("drm/i915: Protect request retirement with
timeline->mutex")
> References: f3c0efc9fe7a ("drm/i915/execlists: Leave resetting ring to
> intel_ring")
> Signed-off-by: Chris Wilson
> Cc: Matthew Auld
> Cc: Tvrtko Ursulin
> Cc: Mika Kuoppala
-Chris
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for Adding YUV444 packed format support for skl+ (rev2)
== Series Details == Series: Adding YUV444 packed format support for skl+ (rev2) URL : https://patchwork.freedesktop.org/series/73020/ State : success == Summary == CI Bug Log - changes from CI_DRM_7900 -> Patchwork_16502 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16502/index.html Known issues Here are the changes found in Patchwork_16502 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-ivb-3770:[PASS][1] -> [DMESG-FAIL][2] ([i915#725]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-ivb-3770/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16502/fi-ivb-3770/igt@i915_selftest@live_blt.html Possible fixes * igt@gem_close_race@basic-threads: - fi-hsw-peppy: [INCOMPLETE][3] ([i915#694] / [i915#816]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-hsw-peppy/igt@gem_close_r...@basic-threads.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16502/fi-hsw-peppy/igt@gem_close_r...@basic-threads.html * igt@i915_selftest@live_blt: - fi-hsw-4770r: [DMESG-FAIL][5] ([i915#553] / [i915#725]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-hsw-4770r/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16502/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_execlists: - fi-icl-y: [DMESG-FAIL][7] ([fdo#108569]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-icl-y/igt@i915_selftest@live_execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16502/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gem_contexts: - fi-cml-s: [DMESG-FAIL][9] ([i915#877]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-cml-s/igt@i915_selftest@live_gem_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16502/fi-cml-s/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gtt: - fi-skl-6770hq: [TIMEOUT][11] ([fdo#111732] / [fdo#112271]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-skl-6770hq/igt@i915_selftest@live_gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16502/fi-skl-6770hq/igt@i915_selftest@live_gtt.html - fi-skl-6600u: [TIMEOUT][13] ([fdo#111732] / [fdo#112271]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-skl-6600u/igt@i915_selftest@live_gtt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16502/fi-skl-6600u/igt@i915_selftest@live_gtt.html * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [FAIL][15] ([fdo#109635] / [i915#217]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16502/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html Warnings * igt@gem_ctx_create@basic-files: - fi-whl-u: [INCOMPLETE][17] ([i915#1194]) -> [INCOMPLETE][18] ([i915#1147]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-whl-u/igt@gem_ctx_cre...@basic-files.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16502/fi-whl-u/igt@gem_ctx_cre...@basic-files.html [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 [fdo#111732]: https://bugs.freedesktop.org/show_bug.cgi?id=111732 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1147]: https://gitlab.freedesktop.org/drm/intel/issues/1147 [i915#1194]: https://gitlab.freedesktop.org/drm/intel/issues/1194 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877 Participating hosts (51 -> 47) -- Additional (3): fi-kbl-7560u fi-byt-n2820 fi-bwr-2160 Missing(7): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * IGT: IGT_5432 -> IGTPW_4011 * Linux: CI_DRM_7900 -> Patchwork_16502 CI-20190529: 20190529 CI_DRM_7900: f4ab479a4e3c9e0bc9120f6618b9876bfdece9cc @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_4011:
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dc3co: Add description of how it works
On Sat, 2020-02-08 at 12:22 +, Patchwork wrote: > == Series Details == > > Series: drm/i915/dc3co: Add description of how it works > URL : https://patchwork.freedesktop.org/series/73058/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_7871_full -> Patchwork_16444_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_16444_full absolutely > need to be > verified manually. > > If you think the reported changes have nothing to do with the > changes > introduced in Patchwork_16444_full, please notify your bug team to > allow them > to document this new failure mode, which will reduce false > positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_16444_full: > > ### IGT changes ### > > Possible regressions > > * igt@runner@aborted: > - shard-apl: NOTRUN -> [FAIL][1] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/shard-apl8/igt@run...@aborted.html > No functional changes in this patch so this is not related. Pushed to dinq, thanks for the review Imre. > > Known issues > > > Here are the changes found in Patchwork_16444_full that come from > known issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_busy@busy-vcs1: > - shard-iclb: [PASS][2] -> [SKIP][3] ([fdo#112080]) +15 > similar issues >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-iclb1/igt@gem_b...@busy-vcs1.html >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/shard-iclb8/igt@gem_b...@busy-vcs1.html > > * igt@gem_ctx_exec@basic-nohangcheck: > - shard-apl: [PASS][4] -> [INCOMPLETE][5] ([fdo#103927]) >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-apl6/igt@gem_ctx_e...@basic-nohangcheck.html >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/shard-apl8/igt@gem_ctx_e...@basic-nohangcheck.html > > * igt@gem_ctx_isolation@rcs0-s3: > - shard-kbl: [PASS][6] -> [DMESG-WARN][7] ([i915#180]) > +6 similar issues >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-kbl1/igt@gem_ctx_isolat...@rcs0-s3.html >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/shard-kbl2/igt@gem_ctx_isolat...@rcs0-s3.html > > * igt@gem_exec_schedule@in-order-bsd: > - shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#112146]) +3 > similar issues >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-iclb6/igt@gem_exec_sched...@in-order-bsd.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/shard-iclb1/igt@gem_exec_sched...@in-order-bsd.html > > * igt@gem_exec_schedule@independent-bsd2: > - shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276]) +24 > similar issues >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-iclb4/igt@gem_exec_sched...@independent-bsd2.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/shard-iclb8/igt@gem_exec_sched...@independent-bsd2.html > > * igt@gem_partial_pwrite_pread@writes-after-reads-uncached: > - shard-hsw: [PASS][12] -> [FAIL][13] ([i915#694]) +2 > similar issues >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-hsw7/igt@gem_partial_pwrite_pr...@writes-after-reads-uncached.html >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/shard-hsw5/igt@gem_partial_pwrite_pr...@writes-after-reads-uncached.html > > * igt@gem_workarounds@suspend-resume-context: > - shard-apl: [PASS][14] -> [DMESG-WARN][15] ([i915#180]) > +2 similar issues >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-apl2/igt@gem_workarou...@suspend-resume-context.html >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/shard-apl6/igt@gem_workarou...@suspend-resume-context.html > > * igt@i915_pm_dc@dc6-dpms: > - shard-iclb: [PASS][16] -> [FAIL][17] ([i915#454]) >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-iclb2/igt@i915_pm...@dc6-dpms.html >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/shard-iclb3/igt@i915_pm...@dc6-dpms.html > > * igt@i915_selftest@live_execlists: > - shard-glk: [PASS][18] -> [INCOMPLETE][19] ([i915#529] > / [i915#58] / [k.org#198133]) >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-glk6/igt@i915_selftest@live_execlists.html >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16444/shard-glk3/igt@i915_selftest@live_execlists.html > > * igt@kms_flip@flip-vs-suspend-interruptible: > - shard-skl: [PASS][20] -> [INCOMPLETE][21] ([i915#221]) >[20]: >
[Intel-gfx] [PATCH v6 15/18] drm/i915: Program DP SDPs on pipe updates
Call intel_dp_set_infoframes() function on pipe updates to make sure that we send VSC SDP and HDR Metadata Infoframe SDP (when applicable) on fastsets. Signed-off-by: Gwan-gyeong Mun Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_ddi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 7f29b08ea202..99d3f011ed96 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4070,6 +4070,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder, intel_ddi_set_dp_msa(crtc_state, conn_state); intel_psr_update(intel_dp, crtc_state); + intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); intel_edp_drrs_enable(intel_dp, crtc_state); intel_panel_update_backlight(encoder, crtc_state, conn_state); -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 13/18] drm/i915: Add state readout for DP VSC SDP
Added state readout for DP VSC SDP and enabled state validation
for DP VSC SDP.
v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 43
2 files changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 55eacc4d75bb..7f29b08ea202 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4367,6 +4367,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
_config->infoframes.drm);
intel_read_dp_sdp(encoder, pipe_config,
HDMI_PACKET_TYPE_GAMUT_METADATA);
+ intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
static enum intel_output_type
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e3694e499b28..c11898cc1b50 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13634,6 +13634,13 @@ intel_compare_infoframe(const union hdmi_infoframe *a,
return memcmp(a, b, sizeof(*a)) == 0;
}
+static bool
+intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
+const struct drm_dp_vsc_sdp *b)
+{
+ return memcmp(a, b, sizeof(*a)) == 0;
+}
+
static void
pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
bool fastset, const char *name,
@@ -13659,6 +13666,31 @@ pipe_config_infoframe_mismatch(struct drm_i915_private
*dev_priv,
}
}
+static void
+pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
+ bool fastset, const char *name,
+ const struct drm_dp_vsc_sdp *a,
+ const struct drm_dp_vsc_sdp *b)
+{
+ if (fastset) {
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ drm_dbg_kms(_priv->drm,
+ "fastset mismatch in %s dp sdp\n", name);
+ drm_dbg_kms(_priv->drm, "expected:\n");
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
+ drm_dbg_kms(_priv->drm, "found:\n");
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
+ } else {
+ drm_err(_priv->drm, "mismatch in %s dp sdp\n", name);
+ drm_err(_priv->drm, "expected:\n");
+ drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
+ drm_err(_priv->drm, "found:\n");
+ drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
+ }
+}
+
static void __printf(4, 5)
pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
const char *name, const char *format, ...)
@@ -13860,6 +13892,16 @@ intel_pipe_config_compare(const struct
intel_crtc_state *current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+ if (!intel_compare_dp_vsc_sdp(_config->infoframes.name, \
+ _config->infoframes.name)) { \
+ pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset,
__stringify(name), \
+
_config->infoframes.name, \
+ _config->infoframes.name);
\
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
if (current_config->name1 != pipe_config->name1) { \
pipe_config_mismatch(fastset, crtc, __stringify(name1), \
@@ -14035,6 +14077,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_INFOFRAME(spd);
PIPE_CONF_CHECK_INFOFRAME(hdmi);
PIPE_CONF_CHECK_INFOFRAME(drm);
+ PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
PIPE_CONF_CHECK_I(master_transcoder);
--
2.25.0
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[Intel-gfx] [PATCH v6 18/18] drm/i915/psr: Use new DP VSC SDP compute routine on PSR
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.
Because PSR routine has its own scenario and timings of writing a VSC SDP,
the current PSR routine needs to have its own drm_dp_vsc_sdp structure
member variable on struct i915_psr.
In order to calculate colorimetry information, intel_psr_update()
function and intel_psr_enable() function extend a drm_connector_state
argument.
There are no changes to PSR mechanism.
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Rebased
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
drivers/gpu/drm/i915/display/intel_psr.c | 54 +++-
drivers/gpu/drm/i915/display/intel_psr.h | 6 ++-
drivers/gpu/drm/i915/i915_drv.h | 1 +
4 files changed, 22 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index e21dfc0d926b..fd0e88566074 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3903,7 +3903,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
*encoder,
intel_dp_stop_link_train(intel_dp);
intel_edp_backlight_on(crtc_state, conn_state);
- intel_psr_enable(intel_dp, crtc_state);
+ intel_psr_enable(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
@@ -4071,7 +4071,7 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder
*encoder,
intel_ddi_set_dp_msa(crtc_state, conn_state);
- intel_psr_update(intel_dp, crtc_state);
+ intel_psr_update(intel_dp, crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index db3d1561e9bf..953c0286307d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -335,39 +335,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
}
}
-static void intel_psr_setup_vsc(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct dp_sdp psr_vsc;
-
- if (dev_priv->psr.psr2_enabled) {
- /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
- memset(_vsc, 0, sizeof(psr_vsc));
- psr_vsc.sdp_header.HB0 = 0;
- psr_vsc.sdp_header.HB1 = 0x7;
- if (dev_priv->psr.colorimetry_support) {
- psr_vsc.sdp_header.HB2 = 0x5;
- psr_vsc.sdp_header.HB3 = 0x13;
- } else {
- psr_vsc.sdp_header.HB2 = 0x4;
- psr_vsc.sdp_header.HB3 = 0xe;
- }
- } else {
- /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
- memset(_vsc, 0, sizeof(psr_vsc));
- psr_vsc.sdp_header.HB0 = 0;
- psr_vsc.sdp_header.HB1 = 0x7;
- psr_vsc.sdp_header.HB2 = 0x2;
- psr_vsc.sdp_header.HB3 = 0x8;
- }
-
- intel_dig_port->write_infoframe(_dig_port->base,
- crtc_state,
- DP_SDP_VSC, _vsc, sizeof(psr_vsc));
-}
-
static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -859,9 +826,12 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *crtc_state)
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state
*conn_state)
{
struct intel_dp *intel_dp = dev_priv->psr.dp;
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = _dig_port->base;
u32 val;
drm_WARN_ON(_priv->drm, dev_priv->psr.enabled);
@@ -900,7 +870,9 @@ static void intel_psr_enable_locked(struct drm_i915_private
*dev_priv,
drm_dbg_kms(_priv->drm, "Enabling PSR%s\n",
dev_priv->psr.psr2_enabled ? "2" : "1");
- intel_psr_setup_vsc(intel_dp, crtc_state);
+ intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
+_priv->psr.vsc);
+ intel_write_dp_vsc_sdp(encoder, crtc_state, _priv->psr.vsc);
intel_psr_enable_sink(intel_dp);
[Intel-gfx] [PATCH v6 17/18] drm/i915/dp: Add compute routine for DP PSR VSC SDP
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it adds a compute routine for PSR VSC SDP.
As PSR routine can not use infoframes.vsc of crtc state, it also adds new
writing of DP SDPs (Secondary Data Packet) for PSR.
PSR routine has its own scenario and timings of writing a VSC SDP.
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 54 +
drivers/gpu/drm/i915/display/intel_dp.h | 8
2 files changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2d6001dd7975..bfc39fbc6534 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2469,6 +2469,42 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
*intel_dp,
_state->infoframes.vsc);
}
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ vsc->sdp_type = DP_SDP_VSC;
+
+ if (dev_priv->psr.psr2_enabled) {
+ if (dev_priv->psr.colorimetry_support &&
+ intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+ /* [PSR2, +Colorimetry] */
+ intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+vsc);
+ } else {
+ /*
+* [PSR2, -Colorimetry]
+* Prepare VSC Header for SU as per eDP 1.4 spec, Table
6-11
+* 3D stereo + PSR/PSR2 + Y-coordinate.
+*/
+ vsc->revision = 0x4;
+ vsc->length = 0xe;
+ }
+ } else {
+ /*
+* [PSR1]
+* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+* VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
+* higher).
+*/
+ vsc->revision = 0x2;
+ vsc->length = 0x8;
+ }
+}
+
static void
intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
@@ -4902,6 +4938,24 @@ static void intel_write_dp_sdp(struct intel_encoder
*encoder,
intel_dig_port->write_infoframe(encoder, crtc_state, type, , len);
}
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct dp_sdp sdp = {};
+ ssize_t len;
+
+ len = intel_dp_vsc_sdp_pack(vsc, , sizeof(sdp));
+
+ if (drm_WARN_ON(_priv->drm, len < 0))
+ return;
+
+ intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
+ , len);
+}
+
void intel_dp_set_infoframes(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 6562bb8edeba..5074e52722c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -18,6 +18,7 @@ struct drm_connector_state;
struct drm_encoder;
struct drm_i915_private;
struct drm_modeset_acquire_ctx;
+struct drm_dp_vsc_sdp;
struct intel_connector;
struct intel_crtc_state;
struct intel_digital_port;
@@ -110,6 +111,13 @@ int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
+void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state,
+ struct drm_dp_vsc_sdp *vsc);
+void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ struct drm_dp_vsc_sdp *vsc);
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
const
[Intel-gfx] [PATCH v6 14/18] drm/i915: Fix enabled infoframe states of lspcon
Compared to implementation of DP and HDMI's encoder->infoframes_enabled,
the lspcon's implementation returns its active state. (we expect enabled
infoframe states of HW.) It leads to pipe state mismatch error
when ddi_get_config is called.
Because the current implementation of lspcon is not ready to support
readout infoframes, we need to return 0 here.
In order to support readout to lspcon, we need to implement read_infoframe
and infoframes_enabled. And set_infoframes also have to set an appropriate
bit on crtc_state->infoframes.enable
Cc: Ville Syrjälä
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/intel_lspcon.c
index d807c5648c87..6ff7b226f0a1 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -522,7 +522,7 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
/* FIXME actually read this from the hw */
- return enc_to_intel_lspcon(encoder)->active;
+ return 0;
}
void lspcon_resume(struct intel_lspcon *lspcon)
--
2.25.0
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[Intel-gfx] [PATCH v6 10/18] drm/i915: Include DP VSC SDP in the crtc state dump
Dump out the DP VSC SDP in the normal crtc state dump
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
Use drm core's DP VSC SDP logging function
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 440e2c1c855c..e3694e499b28 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13006,6 +13006,16 @@ intel_dump_infoframe(struct drm_i915_private *dev_priv,
hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
}
+static void
+intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
+ const struct drm_dp_vsc_sdp *vsc)
+{
+ if (!drm_debug_enabled(DRM_UT_KMS))
+ return;
+
+ drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
+}
+
#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
static const char * const output_type_str[] = {
@@ -13164,6 +13174,9 @@ static void intel_dump_pipe_config(const struct
intel_crtc_state *pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
intel_dump_infoframe(dev_priv, _config->infoframes.drm);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(DP_SDP_VSC))
+ intel_dump_dp_vsc_sdp(dev_priv, _config->infoframes.vsc);
drm_dbg_kms(_priv->drm, "requested mode:\n");
drm_mode_debug_printmodeline(_config->hw.mode);
--
2.25.0
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[Intel-gfx] [PATCH v6 11/18] drm/i915: Program DP SDPs with computed configs
In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
Infoframe SDP), it replaces intel_dp_vsc_enable() function and
intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes()
function.
And it removes unused functions.
Before:
intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() compute sdp
configs and program sdp registers on enable callback of encoder.
After:
It separates computing of sdp configs and programming of sdp register.
The compute config callback of encoder calls computing sdp configs.
The enable callback of encoder calls programming sdp register.
v3: Rebased
v5: Polish commit message [Uma]
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
drivers/gpu/drm/i915/display/intel_dp.c | 226 ---
drivers/gpu/drm/i915/display/intel_dp.h | 6 -
3 files changed, 1 insertion(+), 234 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1ab638e17046..857014fe5880 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3902,8 +3902,7 @@ static void intel_enable_ddi_dp(struct intel_encoder
*encoder,
intel_edp_backlight_on(crtc_state, conn_state);
intel_psr_enable(intel_dp, crtc_state);
- intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
- intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
+ intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_edp_drrs_enable(intel_dp, crtc_state);
if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 5a3ea3527fc3..2d6001dd7975 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5125,232 +5125,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
}
}
-static void
-intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct dp_sdp vsc_sdp = {};
-
- /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
- vsc_sdp.sdp_header.HB0 = 0;
- vsc_sdp.sdp_header.HB1 = 0x7;
-
- /*
-* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
-* Colorimetry Format indication.
-*/
- vsc_sdp.sdp_header.HB2 = 0x5;
-
- /*
-* VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
-* Colorimetry Format indication (HB2 = 05h).
-*/
- vsc_sdp.sdp_header.HB3 = 0x13;
-
- /* DP 1.4a spec, Table 2-120 */
- switch (crtc_state->output_format) {
- case INTEL_OUTPUT_FORMAT_YCBCR444:
- vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
- break;
- case INTEL_OUTPUT_FORMAT_YCBCR420:
- vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
- break;
- case INTEL_OUTPUT_FORMAT_RGB:
- default:
- /* RGB: DB16[7:4] = 0h */
- break;
- }
-
- switch (conn_state->colorspace) {
- case DRM_MODE_COLORIMETRY_BT709_YCC:
- vsc_sdp.db[16] |= 0x1;
- break;
- case DRM_MODE_COLORIMETRY_XVYCC_601:
- vsc_sdp.db[16] |= 0x2;
- break;
- case DRM_MODE_COLORIMETRY_XVYCC_709:
- vsc_sdp.db[16] |= 0x3;
- break;
- case DRM_MODE_COLORIMETRY_SYCC_601:
- vsc_sdp.db[16] |= 0x4;
- break;
- case DRM_MODE_COLORIMETRY_OPYCC_601:
- vsc_sdp.db[16] |= 0x5;
- break;
- case DRM_MODE_COLORIMETRY_BT2020_CYCC:
- case DRM_MODE_COLORIMETRY_BT2020_RGB:
- vsc_sdp.db[16] |= 0x6;
- break;
- case DRM_MODE_COLORIMETRY_BT2020_YCC:
- vsc_sdp.db[16] |= 0x7;
- break;
- case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
- case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
- vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
- break;
- default:
- /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
-
- /* RGB->YCBCR color conversion uses the BT.709 color space. */
- if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
- vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
- break;
- }
-
- /*
-* For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
-* the following Component Bit Depth values are defined:
-* 001b = 8bpc.
-* 010b = 10bpc.
-* 011b = 12bpc.
-* 100b = 16bpc.
-*/
- switch
[Intel-gfx] [PATCH v6 12/18] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP
Added state readout for DP HDR Metadata Infoframe SDP. Signed-off-by: Gwan-gyeong Mun Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_ddi.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 857014fe5880..55eacc4d75bb 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4298,6 +4298,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder, pipe_config->fec_enable); } + pipe_config->infoframes.enable |= + intel_hdmi_infoframes_enabled(encoder, pipe_config); + break; case TRANS_DDI_MODE_SELECT_DP_MST: pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); @@ -4309,6 +4312,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder, REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); intel_dp_get_m_n(intel_crtc, pipe_config); + + pipe_config->infoframes.enable |= + intel_hdmi_infoframes_enabled(encoder, pipe_config); break; default: break; @@ -4359,6 +4365,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder, intel_read_infoframe(encoder, pipe_config, HDMI_INFOFRAME_TYPE_DRM, _config->infoframes.drm); + + intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); } static enum intel_output_type -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 16/18] drm/i915: Stop sending DP SDPs on ddi disable
Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp() to make sure not to send VSC SDP and HDR Metadata Infoframe SDP. v5: Polish commit message [Uma] Signed-off-by: Gwan-gyeong Mun Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 99d3f011ed96..e21dfc0d926b 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3715,6 +3715,8 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, INTEL_OUTPUT_DP_MST); enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + intel_dp_set_infoframes(encoder, false, old_crtc_state, old_conn_state); + /* * Power down sink before disabling the port, otherwise we end * up getting interrupts from the sink on detecting link loss. -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 09/18] drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump
Dump out the DP HDR Metadata Infoframe SDP in the normal crtc state dump. HDMI Dynamic Range and Mastering (DRM) infoframe and DP HDR Metadata Infoframe SDP use the same member variable in infoframes of crtc state. Signed-off-by: Gwan-gyeong Mun Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 66dbaab5867e..440e2c1c855c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13161,6 +13161,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, if (pipe_config->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) intel_dump_infoframe(dev_priv, _config->infoframes.drm); + if (pipe_config->infoframes.enable & + intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) + intel_dump_infoframe(dev_priv, _config->infoframes.drm); drm_dbg_kms(_priv->drm, "requested mode:\n"); drm_mode_debug_printmodeline(_config->hw.mode); -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 05/18] video/hdmi: Add Unpack only function for DRM infoframe
It adds an unpack only function for DRM infoframe for dynamic range and
mastering infoframe readout.
It unpacks the information data block contained in the binary buffer into
a structured frame of the HDMI Dynamic Range and Mastering (DRM)
information frame.
In contrast to hdmi_drm_infoframe_unpack() function, it does not verify
a checksum.
It can be used for unpacking a DP HDR Metadata Infoframe SDP case.
DP HDR Metadata Infoframe SDP uses the same Dynamic Range and Mastering
(DRM) information (CTA-861-G spec.) such as HDMI DRM infoframe.
But DP SDP header and payload structure are different from HDMI DRM
Infoframe. Therefore unpacking DRM infoframe for DP requires skipping of
a verifying checksum.
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/video/hdmi.c | 58 +++-
include/linux/hdmi.h | 2 ++
2 files changed, 43 insertions(+), 17 deletions(-)
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 9c82e2a0a411..9818836d82b7 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -1775,20 +1775,18 @@ hdmi_vendor_any_infoframe_unpack(union
hdmi_vendor_any_infoframe *frame,
}
/**
- * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * hdmi_drm_infoframe_unpack_only() - unpack binary buffer to a HDMI DRM
infoframe
* @frame: HDMI DRM infoframe
* @buffer: source buffer
* @size: size of buffer
*
- * Unpacks the information contained in binary @buffer into a structured
+ * Unpacks the information data block contained in binary @buffer into a
structured
* @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
- * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
- * specification.
*
* Returns 0 on success or a negative error code on failure.
*/
-static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
-const void *buffer, size_t size)
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size)
{
const u8 *ptr = buffer;
const u8 *temp;
@@ -1797,23 +1795,13 @@ static int hdmi_drm_infoframe_unpack(struct
hdmi_drm_infoframe *frame,
int ret;
int i;
- if (size < HDMI_INFOFRAME_SIZE(DRM))
- return -EINVAL;
-
- if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
- ptr[1] != 1 ||
- ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
- return -EINVAL;
-
- if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ if (size < HDMI_DRM_INFOFRAME_SIZE)
return -EINVAL;
ret = hdmi_drm_infoframe_init(frame);
if (ret)
return ret;
- ptr += HDMI_INFOFRAME_HEADER_SIZE;
-
frame->eotf = ptr[0] & 0x7;
frame->metadata_type = ptr[1] & 0x7;
@@ -1837,6 +1825,42 @@ static int hdmi_drm_infoframe_unpack(struct
hdmi_drm_infoframe *frame,
return 0;
}
+EXPORT_SYMBOL(hdmi_drm_infoframe_unpack_only);
+
+/**
+ * hdmi_drm_infoframe_unpack() - unpack binary buffer to a HDMI DRM infoframe
+ * @frame: HDMI DRM infoframe
+ * @buffer: source buffer
+ * @size: size of buffer
+ *
+ * Unpacks the information contained in binary @buffer into a structured
+ * @frame of the HDMI Dynamic Range and Mastering (DRM) information frame.
+ * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4
+ * specification.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+static int hdmi_drm_infoframe_unpack(struct hdmi_drm_infoframe *frame,
+const void *buffer, size_t size)
+{
+ const u8 *ptr = buffer;
+ int ret;
+
+ if (size < HDMI_INFOFRAME_SIZE(DRM))
+ return -EINVAL;
+
+ if (ptr[0] != HDMI_INFOFRAME_TYPE_DRM ||
+ ptr[1] != 1 ||
+ ptr[2] != HDMI_DRM_INFOFRAME_SIZE)
+ return -EINVAL;
+
+ if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(DRM)) != 0)
+ return -EINVAL;
+
+ ret = hdmi_drm_infoframe_unpack_only(frame, ptr +
HDMI_INFOFRAME_HEADER_SIZE,
+size - HDMI_INFOFRAME_HEADER_SIZE);
+ return ret;
+}
/**
* hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 9918a6c910c5..afb43efc03e0 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -219,6 +219,8 @@ ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe
*frame, void *buffer,
ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
void *buffer, size_t size);
int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
+int hdmi_drm_infoframe_unpack_only(struct hdmi_drm_infoframe *frame,
+ const void *buffer, size_t size);
enum
[Intel-gfx] [PATCH v6 06/18] drm/i915/dp: Read out DP SDPs
It adds code to read the DP SDPs from the video DIP and unpack them into
the crtc state.
It adds routines that read out DP VSC SDP and DP HDR Metadata Infoframe SDP
In order to unpack DP VSC SDP, it adds intel_dp_vsc_sdp_unpack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]
In order to unpack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_unpack(). And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].
A naming rule and style of intel_read_dp_sdp() function references
intel_read_infoframe() function of intel_hdmi.c
v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
v5: Addressed review comments from Uma
- Polish commit message and comments
- Combine the if checks of sdp.HB2 and sdp.HB3
- Add 6bpc to unpacking of VSC SDP
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 187
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
2 files changed, 190 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index bc532cca125f..5a3ea3527fc3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4938,6 +4938,193 @@ void intel_dp_set_infoframes(struct intel_encoder
*encoder,
intel_write_dp_sdp(encoder, crtc_state,
HDMI_PACKET_TYPE_GAMUT_METADATA);
}
+static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
+ const void *buffer, size_t size)
+{
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ memset(vsc, 0, size);
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != DP_SDP_VSC)
+ return -EINVAL;
+
+ vsc->sdp_type = sdp->sdp_header.HB1;
+ vsc->revision = sdp->sdp_header.HB2;
+ vsc->length = sdp->sdp_header.HB3;
+
+ if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
+ (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
+ /*
+* - HB2 = 0x2, HB3 = 0x8
+* VSC SDP supporting 3D stereo + PSR
+* - HB2 = 0x4, HB3 = 0xe
+* VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
+* first scan line of the SU region (applies to eDP v1.4b
+* and higher).
+*/
+ return 0;
+ } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
+ /*
+* - HB2 = 0x5, HB3 = 0x13
+* VSC SDP supporting 3D stereo + PSR2 + Pixel
Encoding/Colorimetry
+* Format.
+*/
+ vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
+ vsc->colorimetry = sdp->db[16] & 0xf;
+ vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
+
+ switch (sdp->db[17] & 0x7) {
+ case 0x0:
+ vsc->bpc = 6;
+ break;
+ case 0x1:
+ vsc->bpc = 8;
+ break;
+ case 0x2:
+ vsc->bpc = 10;
+ break;
+ case 0x3:
+ vsc->bpc = 12;
+ break;
+ case 0x4:
+ vsc->bpc = 16;
+ break;
+ default:
+ MISSING_CASE(sdp->db[17] & 0x7);
+ return -EINVAL;
+ }
+
+ vsc->content_type = sdp->db[18] & 0x7;
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int
+intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe
*drm_infoframe,
+ const void *buffer, size_t size)
+{
+ int ret;
+
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
+ return -EINVAL;
+
+ /*
+* Least Significant Eight Bits of (Data Byte Count – 1)
+* 1Dh (i.e., Data Byte Count = 30 bytes).
+*/
+ if (sdp->sdp_header.HB2 != 0x1D)
+ return -EINVAL;
+
+ /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
+ if ((sdp->sdp_header.HB3 & 0x3) != 0)
+ return -EINVAL;
+
+ /* INFOFRAME SDP Version Number */
+ if
[Intel-gfx] [PATCH v6 08/18] drm/i915: Include HDMI DRM infoframe in the crtc state dump
Dump out the HDMI Dynamic Range and Mastering (DRM) infoframe in the normal crtc state dump. Signed-off-by: Gwan-gyeong Mun Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 368e481d45ee..66dbaab5867e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13158,6 +13158,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, if (pipe_config->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) intel_dump_infoframe(dev_priv, _config->infoframes.hdmi); + if (pipe_config->infoframes.enable & + intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) + intel_dump_infoframe(dev_priv, _config->infoframes.drm); drm_dbg_kms(_priv->drm, "requested mode:\n"); drm_mode_debug_printmodeline(_config->hw.mode); -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 00/18] In order to readout DP SDPs, refactors the handling of DP SDPs
In order to readout DP SDPs (Secondary Data Packet: DP HDR Metadata Infoframe SDP, DP VSC SDP), it refactors handling DP SDPs codes. It adds new compute routines for DP HDR Metadata Infoframe SDP and DP VSC SDP. And new writing routines of DP SDPs (Secondary Data Packet) that uses computed configs. New reading routines of DP SDPs are added for readout. It adds a logging function for DP VSC SDP. When receiving video it is very useful to be able to log DP VSC SDP. This greatly simplifies debugging. In order to use a common VSC SDP Colorimetry calculating code on PSR, it uses a new psr vsc sdp compute routine. v2: Minor style fix v3: - Add a new drm data structure for DP VSC SDP - Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp - Move logging functions to drm core [Jani N] And use drm core's DP VSC SDP logging function - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be used for HDMI), when intel_dp_set_infoframes() function will be called. v4: - Use struct drm_device logging macros - Rebased v5: - Use intel_de_*() functions for register access - Add warning where a bpc is 6 and a pixel format is RGB. - Addressed review comments from Uma Add kernel docs for added data structures Rename enum dp_colorspace to dp_pixelformat Polish commit message and comments Combine the if checks of sdp.HB2 and sdp.HB3 Add 6bpc to packining and unpacking of VSC SDP v6: - Fix enabled infoframe states of lspcon Gwan-gyeong Mun (18): drm: Add DP1.4 VSC SDP Payload related Data Structures drm/i915/dp: Add compute routine for DP VSC SDP drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP drm/i915/dp: Add writing of DP SDPs video/hdmi: Add Unpack only function for DRM infoframe drm/i915/dp: Read out DP SDPs drm: Add logging function for DP VSC SDP drm/i915: Include HDMI DRM infoframe in the crtc state dump drm/i915: Include DP HDR Metadata Infoframe SDP in the crtc state dump drm/i915: Include DP VSC SDP in the crtc state dump drm/i915: Program DP SDPs with computed configs drm/i915: Add state readout for DP HDR Metadata Infoframe SDP drm/i915: Add state readout for DP VSC SDP drm/i915: Fix enabled infoframe states of lspcon drm/i915: Program DP SDPs on pipe updates drm/i915: Stop sending DP SDPs on ddi disable drm/i915/dp: Add compute routine for DP PSR VSC SDP drm/i915/psr: Use new DP VSC SDP compute routine on PSR drivers/gpu/drm/drm_dp_helper.c | 174 + drivers/gpu/drm/i915/display/intel_ddi.c | 19 +- drivers/gpu/drm/i915/display/intel_display.c | 62 ++ .../drm/i915/display/intel_display_types.h| 1 + drivers/gpu/drm/i915/display/intel_dp.c | 636 +- drivers/gpu/drm/i915/display/intel_dp.h | 18 +- drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 54 +- drivers/gpu/drm/i915/display/intel_psr.h | 6 +- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/video/hdmi.c | 58 +- include/drm/drm_dp_helper.h | 133 include/linux/hdmi.h | 2 + 13 files changed, 948 insertions(+), 218 deletions(-) -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 04/18] drm/i915/dp: Add writing of DP SDPs
It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe SDP.
In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack() function.
It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
[Table 2-117: VSC SDP Payload for DB16 through DB18]
In order to pack DP HDR Metadata Infoframe SDP, it adds
intel_dp_hdr_metadata_infoframe_sdp_pack() function.
And it follows DP 1.4a spec.
([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and
[Table 2-126: INFOFRAME SDP v1.2 Payload Data Bytes - DB0 through DB31])
and CTA-861-G spec. [Table-42 Dynamic Range and Mastering InfoFrame].
A mechanism and a naming rule of intel_dp_set_infoframes() function
references intel_encoder->set_infoframes() of intel_hdmi.c .
VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats cases.
Because PSR routine has its own routine of writing a VSC SDP, when the PSR
is enabled, intel_dp_set_infoframes() does not write a VSC SDP.
v3:
- Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They will be
used for HDMI), when intel_dp_set_infoframes() function will be called.
- Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp.
v4: Use struct drm_device logging macros
v5:
- use intel_de_*() functions for register access
- Addressed review comments from Uma
Polish commit message and comments
Add 6bpc to packing of VSC SDP
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 199
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
2 files changed, 202 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 472ce3203a09..bc532cca125f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4739,6 +4739,205 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state
*crtc_state,
return false;
}
+static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
+struct dp_sdp *sdp, size_t size)
+{
+ size_t length = sizeof(struct dp_sdp);
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(sdp, 0, size);
+
+ /*
+* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
+* VSC SDP Header Bytes
+*/
+ sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
+ sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
+ sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
+ sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
+
+ /* VSC SDP Payload for DB16 through DB18 */
+ /* Pixel Encoding and Colorimetry Formats */
+ sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
+ sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
+
+ switch (vsc->bpc) {
+ case 6:
+ /* 6bpc: 0x0 */
+ break;
+ case 8:
+ sdp->db[17] = 0x1; /* DB17[3:0] */
+ break;
+ case 10:
+ sdp->db[17] = 0x2;
+ break;
+ case 12:
+ sdp->db[17] = 0x3;
+ break;
+ case 16:
+ sdp->db[17] = 0x4;
+ break;
+ default:
+ MISSING_CASE(vsc->bpc);
+ break;
+ }
+ /* Dynamic Range and Component Bit Depth */
+ if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
+ sdp->db[17] |= 0x80; /* DB17[7] */
+
+ /* Content Type */
+ sdp->db[18] = vsc->content_type & 0x7;
+
+ return length;
+}
+
+static ssize_t
+intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe
*drm_infoframe,
+struct dp_sdp *sdp,
+size_t size)
+{
+ size_t length = sizeof(struct dp_sdp);
+ const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
HDMI_DRM_INFOFRAME_SIZE;
+ unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
+ ssize_t len;
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(sdp, 0, size);
+
+ len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
+ if (len < 0) {
+ DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
infoframe\n");
+ return -ENOSPC;
+ }
+
+ if (len != infoframe_size) {
+ DRM_DEBUG_KMS("wrong static hdr metadata size\n");
+ return -ENOSPC;
+ }
+
+ /*
+* Set up the infoframe sdp packet for HDR static metadata.
+* Prepare VSC Header for SU as per DP 1.4a spec,
+* Table 2-100 and Table 2-101
+*/
+
+ /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
+ sdp->sdp_header.HB0 = 0;
+ /*
+* Packet Type 80h + Non-audio INFOFRAME Type value
+* HDMI_INFOFRAME_TYPE_DRM: 0x87
+* - 80h + Non-audio
[Intel-gfx] [PATCH v6 03/18] drm/i915/dp: Add compute routine for DP HDR Metadata Infoframe SDP
It stores computed dp hdr metadata infoframe sdp to infoframes.drm of
crtc state. It referenced intel_hdmi_compute_drm_infoframe().
While computing, we'll also fill out the infoframes.enable bitmask
appropriately.
v2: Wrap a long line.
v4: Use struct drm_device logging macros
v5: Fix typo [Uma]
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 499377bf2891..472ce3203a09 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2469,6 +2469,29 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
*intel_dp,
_state->infoframes.vsc);
}
+static void
+intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state
*conn_state)
+{
+ int ret;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct hdmi_drm_infoframe *drm_infoframe =
_state->infoframes.drm.drm;
+
+ if (!conn_state->hdr_output_metadata)
+ return;
+
+ ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
+
+ if (ret) {
+ drm_dbg_kms(_priv->drm, "couldn't set HDR metadata in
infoframe\n");
+ return;
+ }
+
+ crtc_state->infoframes.enable |=
+ intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
+}
+
int
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -2575,6 +2598,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_psr_compute_config(intel_dp, pipe_config);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
+ intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config,
conn_state);
return 0;
}
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 01/18] drm: Add DP1.4 VSC SDP Payload related Data Structures
It adds new enumeration definitions for VSC SDP Payload for Pixel
Encoding/Colorimetry Format.
And it adds a new drm data structure for DP VSC SDP.
enum dp_colorspace and enum dp_colorimetry correspond "Pixel Encoding and
Colorimetry Formats". enum dp_dynamic_range corresponds "Dynamic Range".
And enum dp_content_type corresponds "Content Type"
All of them are based on DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].
v3: Add a new drm data structure for DP VSC SDP
v5: Addressed review comments from Uma
- Add kernel docs for added data structures
- Rename enum dp_colorspace to dp_pixelformat
- Polish commit message
- Fix typos
- Drop self-explanatory comments
Signed-off-by: Gwan-gyeong Mun
---
include/drm/drm_dp_helper.h | 130
1 file changed, 130 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 262faf9e5e94..e332f54013d7 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1209,6 +1209,136 @@ struct dp_sdp {
#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
+/**
+ * enum dp_pixelformat - drm DP Pixel encoding formats
+ *
+ * This enum is used to indicate DP VSC SDP Pixel encoding formats.
+ * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
+ * DB18]
+ *
+ * @DP_PIXELFORMAT_RGB: RGB pixel encoding format
+ * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format
+ * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format
+ * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format
+ * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format
+ * @DP_PIXELFORMAT_RAW: RAW pixel encoding format
+ * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format
+ */
+enum dp_pixelformat {
+ DP_PIXELFORMAT_RGB = 0,
+ DP_PIXELFORMAT_YUV444 = 0x1,
+ DP_PIXELFORMAT_YUV422 = 0x2,
+ DP_PIXELFORMAT_YUV420 = 0x3,
+ DP_PIXELFORMAT_Y_ONLY = 0x4,
+ DP_PIXELFORMAT_RAW = 0x5,
+ DP_PIXELFORMAT_RESERVED = 0x6,
+};
+
+/**
+ * enum dp_colorimetry - drm DP Colorimetry formats
+ *
+ * This enum is used to indicate DP VSC SDP Colorimetry formats.
+ * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
+ * DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition.
+ *
+ * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or
+ * ITU-R BT.601 colorimetry format
+ * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry
format
+ * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format
+ * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point
+ * (scRGB (IEC 61966-2-2)) colorimetry format
+ * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format
+ * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format
+ * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format
+ * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format
+ * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format
+ * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format
+ * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format
+ * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format
+ * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format
+ * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format
+ */
+enum dp_colorimetry {
+ DP_COLORIMETRY_DEFAULT = 0,
+ DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
+ DP_COLORIMETRY_BT709_YCC = 0x1,
+ DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
+ DP_COLORIMETRY_XVYCC_601 = 0x2,
+ DP_COLORIMETRY_OPRGB = 0x3,
+ DP_COLORIMETRY_XVYCC_709 = 0x3,
+ DP_COLORIMETRY_DCI_P3_RGB = 0x4,
+ DP_COLORIMETRY_SYCC_601 = 0x4,
+ DP_COLORIMETRY_RGB_CUSTOM = 0x5,
+ DP_COLORIMETRY_OPYCC_601 = 0x5,
+ DP_COLORIMETRY_BT2020_RGB = 0x6,
+ DP_COLORIMETRY_BT2020_CYCC = 0x6,
+ DP_COLORIMETRY_BT2020_YCC = 0x7,
+};
+
+/**
+ * enum dp_dynamic_range - drm DP Dynamic Range
+ *
+ * This enum is used to indicate DP VSC SDP Dynamic Range.
+ * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
+ * DB18]
+ *
+ * @DP_DYNAMIC_RANGE_VESA: VESA range
+ * @DP_DYNAMIC_RANGE_CTA: CTA range
+ */
+enum dp_dynamic_range {
+ DP_DYNAMIC_RANGE_VESA = 0,
+ DP_DYNAMIC_RANGE_CTA = 1,
+};
+
+/**
+ * enum dp_content_type - drm DP Content Type
+ *
+ * This enum is used to indicate DP VSC SDP Content Types.
+ * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
+ * DB18]
+ * CTA-861-G defines content types and expected processing by a sink device
+ *
+ * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type
+ * @DP_CONTENT_TYPE_GRAPHICS: Graphics type
+ * @DP_CONTENT_TYPE_PHOTO: Photo type
+ * @DP_CONTENT_TYPE_VIDEO: Video type
+ * @DP_CONTENT_TYPE_GAME: Game type
+ */
+enum dp_content_type {
+ DP_CONTENT_TYPE_NOT_DEFINED =
[Intel-gfx] [PATCH v6 02/18] drm/i915/dp: Add compute routine for DP VSC SDP
In order to support state readout for DP VSC SDP, we need to have a
structure which holds DP VSC SDP payload data such as
"union hdmi_infoframe drm" which is used for DRM infoframe.
It adds a struct drm_dp_vsc_sdp vsc to intel_crtc_state.infoframes.
And it stores computed dp vsc sdp to infoframes.vsc of crtc state.
While computing we'll also fill out the inforames.enable bitmask
appropriately.
The compute routine follows DP 1.4 spec [Table 2-117: VSC SDP Payload for
DB16 through DB18].
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v5:
- Rebased
- Add warning where a bpc is 6 and a pixel format is RGB.
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 98 +++
2 files changed, 99 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7ae0bc8b80d1..7997c307026d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -997,6 +997,7 @@ struct intel_crtc_state {
union hdmi_infoframe spd;
union hdmi_infoframe hdmi;
union hdmi_infoframe drm;
+ struct drm_dp_vsc_sdp vsc;
} infoframes;
/* HDMI scrambling status */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f4dede6253f8..499377bf2891 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2372,6 +2372,103 @@ static bool intel_dp_port_has_audio(struct
drm_i915_private *dev_priv,
return true;
}
+static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state
*crtc_state,
+const struct drm_connector_state
*conn_state,
+struct drm_dp_vsc_sdp *vsc)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ /*
+* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+* Colorimetry Format indication.
+*/
+ vsc->revision = 0x5;
+ vsc->length = 0x13;
+
+ /* DP 1.4a spec, Table 2-120 */
+ switch (crtc_state->output_format) {
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ vsc->pixelformat = DP_PIXELFORMAT_YUV444;
+ break;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ vsc->pixelformat = DP_PIXELFORMAT_YUV420;
+ break;
+ case INTEL_OUTPUT_FORMAT_RGB:
+ default:
+ vsc->pixelformat = DP_PIXELFORMAT_RGB;
+ }
+
+ switch (conn_state->colorspace) {
+ case DRM_MODE_COLORIMETRY_BT709_YCC:
+ vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
+ break;
+ case DRM_MODE_COLORIMETRY_XVYCC_601:
+ vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
+ break;
+ case DRM_MODE_COLORIMETRY_XVYCC_709:
+ vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
+ break;
+ case DRM_MODE_COLORIMETRY_SYCC_601:
+ vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
+ break;
+ case DRM_MODE_COLORIMETRY_OPYCC_601:
+ vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_CYCC:
+ vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_RGB:
+ vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
+ break;
+ case DRM_MODE_COLORIMETRY_BT2020_YCC:
+ vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
+ break;
+ case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
+ case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
+ vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
+ break;
+ default:
+ /*
+* RGB->YCBCR color conversion uses the BT.709
+* color space.
+*/
+ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
+ else
+ vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
+ break;
+ }
+
+ vsc->bpc = crtc_state->pipe_bpp / 3;
+ drm_WARN_ON(_priv->drm, vsc->bpc == 6 &&
+ vsc->pixelformat == DP_PIXELFORMAT_RGB);
+
+ /* all YCbCr are always limited range */
+ vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
+ vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
+}
+
+static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+
[Intel-gfx] [PATCH v6 07/18] drm: Add logging function for DP VSC SDP
When receiving video it is very useful to be able to log DP VSC SDP.
This greatly simplifies debugging.
v2: Minor style fix
v3: Move logging functions to drm core [Jani N]
v5: Rebased
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/drm_dp_helper.c | 174
include/drm/drm_dp_helper.h | 3 +
2 files changed, 177 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 5a103e9b3c86..17059ed4763b 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1395,3 +1395,177 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_S
return num_bpc;
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+
+static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
+{
+ if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
+ return "Invalid";
+
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "RGB";
+ case DP_PIXELFORMAT_YUV444:
+ return "YUV444";
+ case DP_PIXELFORMAT_YUV422:
+ return "YUV422";
+ case DP_PIXELFORMAT_YUV420:
+ return "YUV420";
+ case DP_PIXELFORMAT_Y_ONLY:
+ return "Y_ONLY";
+ case DP_PIXELFORMAT_RAW:
+ return "RAW";
+ default:
+ return "Reserved";
+ }
+}
+
+static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
+ enum dp_colorimetry colorimetry)
+{
+ if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
+ return "Invalid";
+
+ switch (colorimetry) {
+ case DP_COLORIMETRY_DEFAULT:
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "sRGB";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "BT.601";
+ case DP_PIXELFORMAT_Y_ONLY:
+ return "DICOM PS3.14";
+ case DP_PIXELFORMAT_RAW:
+ return "Custom Color Profile";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "Wide Fixed";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "BT.709";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "Wide Float";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "xvYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "OpRGB";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "xvYCC 709";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "DCI-P3";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "sYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "Custom Profile";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case DP_PIXELFORMAT_YUV420:
+ return "OpYCC 601";
+ default:
+ return "Reserved";
+ }
+ case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
+ switch (pixelformat) {
+ case DP_PIXELFORMAT_RGB:
+ return "BT.2020 RGB";
+ case DP_PIXELFORMAT_YUV444:
+ case DP_PIXELFORMAT_YUV422:
+ case
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display/ehl: Add HBR2 and HBR3 voltage swing table
On Sat, 2020-02-08 at 11:25 +, Patchwork wrote: > == Series Details == > > Series: drm/i915/display/ehl: Add HBR2 and HBR3 voltage swing table > URL : https://patchwork.freedesktop.org/series/73055/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_7871_full -> Patchwork_16443_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_16443_full absolutely > need to be > verified manually. > > If you think the reported changes have nothing to do with the > changes > introduced in Patchwork_16443_full, please notify your bug team to > allow them > to document this new failure mode, which will reduce false > positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_16443_full: > > ### IGT changes ### > > Possible regressions > > * igt@gem_ctx_exec@basic-nohangcheck: > - shard-skl: [PASS][1] -> [INCOMPLETE][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-skl1/igt@gem_ctx_e...@basic-nohangcheck.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/shard-skl8/igt@gem_ctx_e...@basic-nohangcheck.html Not related as this changes are on display and only related to GEN11. So pushed to dinq, thanks for the review Matt. > > > Known issues > > > Here are the changes found in Patchwork_16443_full that come from > known issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_busy@busy-vcs1: > - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112080]) +20 > similar issues >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-iclb1/igt@gem_b...@busy-vcs1.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/shard-iclb8/igt@gem_b...@busy-vcs1.html > > * igt@gem_exec_balancer@hang: > - shard-tglb: [PASS][5] -> [TIMEOUT][6] ([fdo#112271]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-tglb5/igt@gem_exec_balan...@hang.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/shard-tglb5/igt@gem_exec_balan...@hang.html > > * igt@gem_exec_schedule@in-order-bsd: > - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146]) +4 > similar issues >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-iclb6/igt@gem_exec_sched...@in-order-bsd.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/shard-iclb4/igt@gem_exec_sched...@in-order-bsd.html > > * igt@gem_exec_schedule@independent-bsd2: > - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +28 > similar issues >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-iclb4/igt@gem_exec_sched...@independent-bsd2.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/shard-iclb8/igt@gem_exec_sched...@independent-bsd2.html > > * igt@gem_partial_pwrite_pread@write-snoop: > - shard-hsw: [PASS][11] -> [FAIL][12] ([i915#694]) +2 > similar issues >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-hsw5/igt@gem_partial_pwrite_pr...@write-snoop.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/shard-hsw7/igt@gem_partial_pwrite_pr...@write-snoop.html > > * igt@gem_ppgtt@flink-and-close-vma-leak: > - shard-apl: [PASS][13] -> [FAIL][14] ([i915#644]) >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-apl8/igt@gem_pp...@flink-and-close-vma-leak.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/shard-apl4/igt@gem_pp...@flink-and-close-vma-leak.html > > * igt@i915_pm_rps@min-max-config-loaded: > - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#370]) >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-iclb4/igt@i915_pm_...@min-max-config-loaded.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/shard-iclb7/igt@i915_pm_...@min-max-config-loaded.html > > * igt@i915_suspend@fence-restore-tiled2untiled: > - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#69]) >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-skl8/igt@i915_susp...@fence-restore-tiled2untiled.html >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/shard-skl7/igt@i915_susp...@fence-restore-tiled2untiled.html > > * igt@kms_atomic_transition@plane-all-modeset-transition-fencing: > - shard-hsw: [PASS][19] -> [DMESG-WARN][20] ([i915#44]) >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7871/shard-hsw8/igt@kms_atomic_transit...@plane-all-modeset-transition-fencing.html >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16443/shard-hsw5/igt@kms_atomic_transit...@plane-all-modeset-transition-fencing.html > > *
[Intel-gfx] [PATCH] drm/i915: terminate reauth at stream management failure
As per the HDCP2.2 compliance test 1B-10 expectation, when stream
management for a repeater fails, HDCP2.2 reauthentication stops at
kernel.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 55 ++-
1 file changed, 34 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 4d1a33d13105..5ab35484da93 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1380,7 +1380,7 @@ static int hdcp2_session_key_exchange(struct
intel_connector *connector)
}
static
-int hdcp2_propagate_stream_management_info(struct intel_connector *connector)
+int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
{
struct intel_digital_port *intel_dig_port =
intel_attached_dig_port(connector);
struct intel_hdcp *hdcp = >hdcp;
@@ -1492,17 +1492,6 @@ int hdcp2_authenticate_repeater_topology(struct
intel_connector *connector)
return 0;
}
-static int hdcp2_authenticate_repeater(struct intel_connector *connector)
-{
- int ret;
-
- ret = hdcp2_authenticate_repeater_topology(connector);
- if (ret < 0)
- return ret;
-
- return hdcp2_propagate_stream_management_info(connector);
-}
-
static int hdcp2_authenticate_sink(struct intel_connector *connector)
{
struct intel_digital_port *intel_dig_port =
intel_attached_dig_port(connector);
@@ -1537,18 +1526,13 @@ static int hdcp2_authenticate_sink(struct
intel_connector *connector)
}
if (hdcp->is_repeater) {
- ret = hdcp2_authenticate_repeater(connector);
+ ret = hdcp2_authenticate_repeater_topology(connector);
if (ret < 0) {
DRM_DEBUG_KMS("Repeater Auth Failed. Err: %d\n", ret);
return ret;
}
}
- hdcp->port_data.streams[0].stream_type = hdcp->content_type;
- ret = hdcp2_authenticate_port(connector);
- if (ret < 0)
- return ret;
-
return ret;
}
@@ -1626,14 +1610,43 @@ static int hdcp2_disable_encryption(struct
intel_connector *connector)
return ret;
}
+static int
+hdcp2_propagate_stream_management_info(struct intel_connector *connector)
+{
+ int i, tries = 3, ret;
+
+ if (!connector->hdcp.is_repeater)
+ return 0;
+
+ for (i = 0; i < tries; i++) {
+ ret = _hdcp2_propagate_stream_management_info(connector);
+ if (!ret)
+ break;
+ }
+
+ return ret;
+}
+
static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
{
+ struct intel_hdcp *hdcp = >hdcp;
int ret, i, tries = 3;
for (i = 0; i < tries; i++) {
ret = hdcp2_authenticate_sink(connector);
- if (!ret)
- break;
+ if (!ret) {
+ ret = hdcp2_propagate_stream_management_info(connector);
+ if (!ret) {
+ hdcp->port_data.streams[0].stream_type =
+ hdcp->content_type;
+ ret = hdcp2_authenticate_port(connector);
+ if (!ret)
+ break;
+ } else {
+ DRM_DEBUG_KMS("HDCP2 stream management
failed\n");
+ break;
+ }
+ }
/* Clearing the mei hdcp session */
DRM_DEBUG_KMS("HDCP2.2 Auth %d of %d Failed.(%d)\n",
@@ -1642,7 +1655,7 @@ static int hdcp2_authenticate_and_encrypt(struct
intel_connector *connector)
DRM_DEBUG_KMS("Port deauth failed.\n");
}
- if (i != tries) {
+ if (!ret) {
/*
* Ensuring the required 200mSec min time interval between
* Session Key Exchange and encryption.
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gt: Avoid resetting ring->head outside of its timeline mutex
We manipulate ring->head while active in i915_request_retire underneath
the timeline manipulation. We cannot rely on a stable ring->head outside
of the timeline->mutex, in particular while setting up the context for
resume and reset.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1126
References: f3c0efc9fe7a ("drm/i915/execlists: Leave resetting ring to
intel_ring")
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c| 36 --
drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +-
2 files changed, 18 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 230470c58ec9..3f75861a53c6 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -235,7 +235,8 @@ static void execlists_init_reg_state(u32 *reg_state,
bool close);
static void
__execlists_update_reg_state(const struct intel_context *ce,
-const struct intel_engine_cs *engine);
+const struct intel_engine_cs *engine,
+u32 head);
static void mark_eio(struct i915_request *rq)
{
@@ -1184,12 +1185,11 @@ static void reset_active(struct i915_request *rq,
head = rq->tail;
else
head = active_request(ce->timeline, rq)->head;
- ce->ring->head = intel_ring_wrap(ce->ring, head);
- intel_ring_update_space(ce->ring);
+ head = intel_ring_wrap(ce->ring, head);
/* Scrub the context image to prevent replaying the previous batch */
restore_default_state(ce, engine);
- __execlists_update_reg_state(ce, engine);
+ __execlists_update_reg_state(ce, engine, head);
/* We've switched away, so this should be a no-op, but intent matters */
ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
@@ -2878,16 +2878,17 @@ static void execlists_context_unpin(struct
intel_context *ce)
static void
__execlists_update_reg_state(const struct intel_context *ce,
-const struct intel_engine_cs *engine)
+const struct intel_engine_cs *engine,
+u32 head)
{
struct intel_ring *ring = ce->ring;
u32 *regs = ce->lrc_reg_state;
- GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
+ GEM_BUG_ON(!intel_ring_offset_valid(ring, head));
GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
- regs[CTX_RING_HEAD] = ring->head;
+ regs[CTX_RING_HEAD] = head;
regs[CTX_RING_TAIL] = ring->tail;
/* RPCS */
@@ -2916,7 +2917,7 @@ __execlists_context_pin(struct intel_context *ce,
ce->lrc_desc = lrc_descriptor(ce, engine) | CTX_DESC_FORCE_RESTORE;
ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
- __execlists_update_reg_state(ce, engine);
+ __execlists_update_reg_state(ce, engine, ce->ring->tail);
return 0;
}
@@ -2941,7 +2942,7 @@ static void execlists_context_reset(struct intel_context
*ce)
/* Scrub away the garbage */
execlists_init_reg_state(ce->lrc_reg_state,
ce, ce->engine, ce->ring, true);
- __execlists_update_reg_state(ce, ce->engine);
+ __execlists_update_reg_state(ce, ce->engine, ce->ring->tail);
ce->lrc_desc |= CTX_DESC_FORCE_RESTORE;
}
@@ -3538,6 +3539,7 @@ static void __execlists_reset(struct intel_engine_cs
*engine, bool stalled)
struct intel_engine_execlists * const execlists = >execlists;
struct intel_context *ce;
struct i915_request *rq;
+ u32 head;
mb(); /* paranoia: read the CSB pointers from after the reset */
clflush(execlists->csb_write);
@@ -3565,15 +3567,15 @@ static void __execlists_reset(struct intel_engine_cs
*engine, bool stalled)
if (i915_request_completed(rq)) {
/* Idle context; tidy up the ring so we can restart afresh */
- ce->ring->head = intel_ring_wrap(ce->ring, rq->tail);
+ head = intel_ring_wrap(ce->ring, rq->tail);
goto out_replay;
}
/* Context has requests still in-flight; it should not be idle! */
GEM_BUG_ON(i915_active_is_idle(>active));
rq = active_request(ce->timeline, rq);
- ce->ring->head = intel_ring_wrap(ce->ring, rq->head);
- GEM_BUG_ON(ce->ring->head == ce->ring->tail);
+ head = intel_ring_wrap(ce->ring, rq->head);
+ GEM_BUG_ON(head == ce->ring->tail);
/*
* If this request hasn't started yet, e.g. it is waiting on a
@@ -3618,10 +3620,9 @@ static void __execlists_reset(struct intel_engine_cs
*engine, bool stalled)
out_replay:
ENGINE_TRACE(engine, "replay {head:%04x, tail:%04x}\n",
-
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: change prefix to debugfs functions
== Series Details == Series: drm/i915/gt: change prefix to debugfs functions URL : https://patchwork.freedesktop.org/series/73239/ State : success == Summary == CI Bug Log - changes from CI_DRM_7900 -> Patchwork_16503 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16503/index.html Known issues Here are the changes found in Patchwork_16503 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_blt: - fi-ivb-3770:[PASS][1] -> [DMESG-FAIL][2] ([i915#725]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-ivb-3770/igt@i915_selftest@live_blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16503/fi-ivb-3770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-8700k: [PASS][3] -> [INCOMPLETE][4] ([i915#424]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16503/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html * igt@kms_chamelium@dp-edid-read: - fi-cml-u2: [PASS][5] -> [FAIL][6] ([i915#217] / [i915#976]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16503/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html Possible fixes * igt@i915_selftest@live_execlists: - fi-icl-y: [DMESG-FAIL][7] ([fdo#108569]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-icl-y/igt@i915_selftest@live_execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16503/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gem_contexts: - fi-cml-s: [DMESG-FAIL][9] ([i915#877]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-cml-s/igt@i915_selftest@live_gem_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16503/fi-cml-s/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gtt: - fi-skl-6770hq: [TIMEOUT][11] ([fdo#111732] / [fdo#112271]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-skl-6770hq/igt@i915_selftest@live_gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16503/fi-skl-6770hq/igt@i915_selftest@live_gtt.html - fi-skl-6600u: [TIMEOUT][13] ([fdo#111732] / [fdo#112271]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-skl-6600u/igt@i915_selftest@live_gtt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16503/fi-skl-6600u/igt@i915_selftest@live_gtt.html * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [FAIL][15] ([fdo#109635] / [i915#217]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16503/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][17] ([fdo#111407]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16503/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Warnings * igt@gem_close_race@basic-threads: - fi-hsw-peppy: [INCOMPLETE][19] ([i915#694] / [i915#816]) -> [TIMEOUT][20] ([fdo#112271] / [i915#1084]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-hsw-peppy/igt@gem_close_r...@basic-threads.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16503/fi-hsw-peppy/igt@gem_close_r...@basic-threads.html [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#111732]: https://bugs.freedesktop.org/show_bug.cgi?id=111732 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877 [i915#976]: https://gitlab.freedesktop.org/drm/intel/issues/976 Participating hosts (51 -> 47) -- Additional (3): fi-kbl-7560u fi-byt-n2820 fi-bwr-2160
[Intel-gfx] ✓ Fi.CI.IGT: success for drm: Try to fix encoder possible_clones/crtc (rev2)
== Series Details == Series: drm: Try to fix encoder possible_clones/crtc (rev2) URL : https://patchwork.freedesktop.org/series/63399/ State : success == Summary == CI Bug Log - changes from CI_DRM_7886_full -> Patchwork_16482_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16482_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-kbl3/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16482/shard-kbl4/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb1/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16482/shard-iclb6/igt@gem_exec_balan...@smoke.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +13 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb4/igt@gem_exec_paral...@vcs1-fds.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16482/shard-iclb5/igt@gem_exec_paral...@vcs1-fds.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146]) +6 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb3/igt@gem_exec_sched...@reorder-wide-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16482/shard-iclb1/igt@gem_exec_sched...@reorder-wide-bsd.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-apl8/igt@gem_workarou...@suspend-resume-context.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16482/shard-apl6/igt@gem_workarou...@suspend-resume-context.html * igt@gen9_exec_parse@allowed-all: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#716]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-glk6/igt@gen9_exec_pa...@allowed-all.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16482/shard-glk4/igt@gen9_exec_pa...@allowed-all.html * igt@i915_pm_dc@dc5-dpms: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#447]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb4/igt@i915_pm...@dc5-dpms.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16482/shard-iclb3/igt@i915_pm...@dc5-dpms.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#454]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb1/igt@i915_pm...@dc6-psr.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16482/shard-iclb8/igt@i915_pm...@dc6-psr.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#899]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-glk2/igt@kms_plane_low...@pipe-a-tiling-x.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16482/shard-glk9/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16482/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@prime_vgem@fence-wait-bsd2: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109276]) +26 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb2/igt@prime_v...@fence-wait-bsd2.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16482/shard-iclb8/igt@prime_v...@fence-wait-bsd2.html Possible fixes * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [DMESG-WARN][23] ([i915#180]) -> [PASS][24] +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-apl1/igt@gem_ctx_isolat...@rcs0-s3.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16482/shard-apl6/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_balancer@hang: - shard-tglb: [TIMEOUT][25] ([fdo#112271]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-tglb8/igt@gem_exec_balan...@hang.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16482/shard-tglb5/igt@gem_exec_balan...@hang.html * igt@gem_exec_schedule@in-order-bsd: -
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix force-probe failure message
== Series Details == Series: drm/i915: Fix force-probe failure message URL : https://patchwork.freedesktop.org/series/73149/ State : success == Summary == CI Bug Log - changes from CI_DRM_7886_full -> Patchwork_16481_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16481_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +7 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb2/igt@gem_ctx_isolat...@vcs1-dirty-create.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16481/shard-iclb6/igt@gem_ctx_isolat...@vcs1-dirty-create.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16481/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb1/igt@gem_exec_balan...@smoke.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16481/shard-iclb5/igt@gem_exec_balan...@smoke.html * igt@gem_exec_params@invalid-bsd-ring: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +11 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb1/igt@gem_exec_par...@invalid-bsd-ring.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16481/shard-iclb5/igt@gem_exec_par...@invalid-bsd-ring.html * igt@gem_exec_schedule@pi-distinct-iova-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb6/igt@gem_exec_sched...@pi-distinct-iova-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16481/shard-iclb1/igt@gem_exec_sched...@pi-distinct-iova-bsd.html * igt@gem_exec_schedule@preempt-self-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb8/igt@gem_exec_sched...@preempt-self-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16481/shard-iclb4/igt@gem_exec_sched...@preempt-self-bsd.html * igt@gen9_exec_parse@allowed-all: - shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#716]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-glk6/igt@gen9_exec_pa...@allowed-all.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16481/shard-glk1/igt@gen9_exec_pa...@allowed-all.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#454]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb8/igt@i915_pm...@dc6-dpms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16481/shard-iclb3/igt@i915_pm...@dc6-dpms.html * igt@i915_selftest@live_gtt: - shard-apl: [PASS][17] -> [TIMEOUT][18] ([fdo#112271]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-apl2/igt@i915_selftest@live_gtt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16481/shard-apl3/igt@i915_selftest@live_gtt.html * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#79]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-glk6/igt@kms_f...@flip-vs-expired-vblank.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16481/shard-glk1/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@plain-flip-fb-recreate: - shard-kbl: [PASS][21] -> [FAIL][22] ([i915#34]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-kbl2/igt@kms_f...@plain-flip-fb-recreate.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16481/shard-kbl3/igt@kms_f...@plain-flip-fb-recreate.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite: - shard-tglb: [PASS][23] -> [SKIP][24] ([i915#668]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-tglb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16481/shard-tglb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][25] -> [DMESG-WARN][26] ([i915#180]) [25]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Make sure to sanitize CT status
== Series Details == Series: drm/i915/guc: Make sure to sanitize CT status URL : https://patchwork.freedesktop.org/series/73146/ State : success == Summary == CI Bug Log - changes from CI_DRM_7886_full -> Patchwork_16480_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16480_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@busy-vcs1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +8 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb2/igt@gem_b...@busy-vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16480/shard-iclb8/igt@gem_b...@busy-vcs1.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16480/shard-iclb4/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb1/igt@gem_exec_balan...@smoke.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16480/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +21 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb4/igt@gem_exec_sched...@independent-bsd2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16480/shard-iclb6/igt@gem_exec_sched...@independent-bsd2.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb7/igt@gem_exec_sched...@preemptive-hang-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16480/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#644]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-glk1/igt@gem_pp...@flink-and-close-vma-leak.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16480/shard-glk6/igt@gem_pp...@flink-and-close-vma-leak.html * igt@gem_softpin@noreloc-s3: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-kbl6/igt@gem_soft...@noreloc-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16480/shard-kbl7/igt@gem_soft...@noreloc-s3.html * igt@gen9_exec_parse@allowed-all: - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#716]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-glk6/igt@gen9_exec_pa...@allowed-all.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16480/shard-glk7/igt@gen9_exec_pa...@allowed-all.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-apl1/igt@kms_frontbuffer_track...@fbc-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16480/shard-apl1/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_psr@no_drrs: - shard-iclb: [PASS][19] -> [FAIL][20] ([i915#173]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb7/igt@kms_psr@no_drrs.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16480/shard-iclb1/igt@kms_psr@no_drrs.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16480/shard-iclb3/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_psr@psr2_suspend: - shard-tglb: [PASS][23] -> [INCOMPLETE][24] ([i915#460] / [i915#472]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-tglb6/igt@kms_psr@psr2_suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16480/shard-tglb6/igt@kms_psr@psr2_suspend.html * igt@kms_setmode@basic: - shard-apl: [PASS][25] -> [FAIL][26] ([i915#31]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-apl8/igt@kms_setm...@basic.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16480/shard-apl4/igt@kms_setm...@basic.html Possible fixes * igt@gem_ctx_isolation@rcs0-s3: -
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Use the kernel_context to measure the breadcrumb size
== Series Details == Series: drm/i915/gt: Use the kernel_context to measure the breadcrumb size URL : https://patchwork.freedesktop.org/series/73143/ State : success == Summary == CI Bug Log - changes from CI_DRM_7886_full -> Patchwork_16479_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16479_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb8/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16479/shard-iclb4/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb1/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16479/shard-iclb5/igt@gem_exec_balan...@smoke.html * igt@gem_exec_params@invalid-bsd-ring: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +11 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb1/igt@gem_exec_par...@invalid-bsd-ring.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16479/shard-iclb5/igt@gem_exec_par...@invalid-bsd-ring.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb7/igt@gem_exec_sched...@preemptive-hang-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16479/shard-iclb2/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#644]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-glk1/igt@gem_pp...@flink-and-close-vma-leak.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16479/shard-glk6/igt@gem_pp...@flink-and-close-vma-leak.html * igt@gen9_exec_parse@allowed-all: - shard-glk: [PASS][11] -> [INCOMPLETE][12] ([i915#58] / [k.org#198133]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-glk6/igt@gen9_exec_pa...@allowed-all.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16479/shard-glk2/igt@gen9_exec_pa...@allowed-all.html * igt@i915_suspend@fence-restore-untiled: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-apl3/igt@i915_susp...@fence-restore-untiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16479/shard-apl2/igt@i915_susp...@fence-restore-untiled.html * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#79]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-glk6/igt@kms_f...@flip-vs-expired-vblank.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16479/shard-glk3/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#899]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-glk5/igt@kms_plane_low...@pipe-a-tiling-y.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16479/shard-glk9/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16479/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-kbl6/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16479/shard-kbl7/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html * igt@perf_pmu@busy-check-all-vcs1: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#112080]) +8 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb1/igt@perf_...@busy-check-all-vcs1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16479/shard-iclb6/igt@perf_...@busy-check-all-vcs1.html Possible fixes * igt@gem_exec_balancer@hang: - shard-tglb: [TIMEOUT][25] ([fdo#112271]) -> [PASS][26] [25]:
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/gem: Don't leak non-persistent requests on changing engines
Quoting Patchwork (2020-02-10 16:00:41)
> Possible fixes
>
> * {igt@gem_ctx_persistence@replace-hostile@vcs0}:
> - shard-kbl: [FAIL][27] ([i915#1154]) -> [PASS][28] +9 similar
> issues
>[27]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-kbl1/igt@gem_ctx_persistence@replace-host...@vcs0.html
>[28]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-kbl1/igt@gem_ctx_persistence@replace-host...@vcs0.html
>
> * {igt@gem_ctx_persistence@replace@vcs0}:
> - shard-apl: [FAIL][29] ([i915#1154]) -> [PASS][30] +7 similar
> issues
>[29]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-apl4/igt@gem_ctx_persistence@repl...@vcs0.html
>[30]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-apl3/igt@gem_ctx_persistence@repl...@vcs0.html
> - shard-iclb: [FAIL][31] ([i915#1154]) -> [PASS][32] +7 similar
> issues
>[31]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb2/igt@gem_ctx_persistence@repl...@vcs0.html
>[32]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-iclb7/igt@gem_ctx_persistence@repl...@vcs0.html
> - shard-glk: [FAIL][33] ([i915#1154]) -> [PASS][34] +7 similar
> issues
>[33]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-glk9/igt@gem_ctx_persistence@repl...@vcs0.html
>[34]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-glk9/igt@gem_ctx_persistence@repl...@vcs0.html
>
> * {igt@gem_ctx_persistence@replace@vecs0}:
> - shard-tglb: [FAIL][35] ([i915#1154]) -> [PASS][36] +9 similar
> issues
>[35]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-tglb1/igt@gem_ctx_persistence@repl...@vecs0.html
>[36]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-tglb7/igt@gem_ctx_persistence@repl...@vecs0.html
Yay \o/
-Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/gem: Don't leak non-persistent requests on changing engines
== Series Details == Series: series starting with [1/3] drm/i915/gem: Don't leak non-persistent requests on changing engines URL : https://patchwork.freedesktop.org/series/73134/ State : success == Summary == CI Bug Log - changes from CI_DRM_7886_full -> Patchwork_16478_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16478_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +9 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb2/igt@gem_ctx_isolat...@vcs1-dirty-create.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-iclb7/igt@gem_ctx_isolat...@vcs1-dirty-create.html * igt@gem_exec_balancer@hang: - shard-iclb: [PASS][3] -> [TIMEOUT][4] ([fdo#112271]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb6/igt@gem_exec_balan...@hang.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-iclb1/igt@gem_exec_balan...@hang.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb1/igt@gem_exec_balan...@smoke.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-iclb6/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@pi-distinct-iova-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([i915#677]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb6/igt@gem_exec_sched...@pi-distinct-iova-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-iclb1/igt@gem_exec_sched...@pi-distinct-iova-bsd.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb7/igt@gem_exec_sched...@preemptive-hang-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-iclb4/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#644]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-glk1/igt@gem_pp...@flink-and-close-vma-leak.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-glk1/igt@gem_pp...@flink-and-close-vma-leak.html * igt@gen9_exec_parse@allowed-all: - shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#716]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-glk6/igt@gen9_exec_pa...@allowed-all.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-glk4/igt@gen9_exec_pa...@allowed-all.html * igt@i915_selftest@live_gt_heartbeat: - shard-kbl: [PASS][15] -> [DMESG-FAIL][16] ([i915#541]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-kbl6/igt@i915_selftest@live_gt_heartbeat.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-kbl7/igt@i915_selftest@live_gt_heartbeat.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-kbl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-kbl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#899]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-glk2/igt@kms_plane_low...@pipe-a-tiling-x.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-glk9/igt@kms_plane_low...@pipe-a-tiling-x.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@prime_vgem@fence-wait-bsd2: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109276]) +22 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7886/shard-iclb2/igt@prime_v...@fence-wait-bsd2.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16478/shard-iclb5/igt@prime_v...@fence-wait-bsd2.html Possible fixes * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [DMESG-WARN][25] ([i915#180]) -> [PASS][26] +1 similar issue [25]:
Re: [Intel-gfx] [PATCH] drm/i915/mst: fix pipe and vblank enable
On Mon, Feb 10, 2020 at 01:43:47PM +0200, Lisovskiy, Stanislav wrote:
> On Mon, 2020-02-10 at 13:32 +0200, Jani Nikula wrote:
> > On Wed, 05 Feb 2020, Jani Nikula wrote:
> > > Commit 21fd23ac222f ("drm/i915: move pipe, pch and vblank enable to
> > > encoders on DDI platforms") pushed pipe and vblank enable to
> > > encoders on
> > > DDI platforms, however it missed the DP MST encoder. Fix it.
> > >
> > > Fixes: 21fd23ac222f ("drm/i915: move pipe, pch and vblank enable to
> > > encoders on DDI platforms")
> > > Cc: Vandita Kulkarni
> > > Cc: Ville Syrjala
> > > Reported-by: Stanislav Lisovskiy
> > > Signed-off-by: Jani Nikula
> >
> > Thanks for the reviews and testing, pushed to dinq.
> >
> > I don't usually cut corners, but I've made an exception and pushed
> > this without full IGT results.
> >
> > It's been 5 days since the patch was posted, the sharded run has
> > fallen between the cracks, and the queue is currently about three
> > days. IMHO it's intolerable for any patch, but especially so for a
> > regression fix that was posted within hours of the bug report.
>
> Absolutely agree, since we already had a regression, it's pointless
> now to wait longer with such a trivial fix. We are anyway in a bad
> situation now, checking also some other MST issues and having to apply
> this patch manually first in order to get at least this issue ruled
> out.
>
> Stan
As of why it was silently dropped:
We poke patchwork to check whether there is a newer version of a given
series. If there is we won't waste time on running the older one through
shards.
This bit looks more or less like this:
RES="$(curl -q
https://patchwork.freedesktop.org/api/1.0/series/$SER/revisions/$(( $REV + 1
))/ 2>/dev/null)"
[[ "$RES" = "" || "$RES" = *"ot found"* ]] || exit 1
If there is a network issue and curl exits with non-zero exit status
this aborts the shards because of `set -e`, which is what has happened:
+++ curl -q
https://patchwork.freedesktop.org/api/1.0/series/73006/revisions/2/
++ RES=
Build step 'Execute shell' marked build as failure
So a network issue + not robust enough bash script is the cause.
I have fixed the logic there to account for this and in case of network
errors we just go ahead with testing. Thanks for rising this up.
As of the 3 days worth of queued shards:
I agree that this is unacceptable, but we can do only so much from the
CI/infra side. The time has been creeping up steadily over the last year
or so and the machines are not getting any faster.
We are currently sitting on ~58min for a run and Tomi has already done a
lot of in terms of optimization. The overhead is as minimal as it can be
and there is some logic tracking the test execution times and doing
random but balanced test distribution.
We are also considering introducing hard limits on subtest execution
times and hunting down the tests that are exceeding this.
On IGT side there was a recent introduction of dynamic subtest which
should help with time wasted on some of the skips, and I am working on a
more reliable skips for multiple mode testing (currently one subtest =
one execv) but without optimizing the test cases we won't shave off much
time.
--
Cheers,
Arek
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/selftests: Disable capturing forced error states
== Series Details == Series: series starting with [1/4] drm/i915/selftests: Disable capturing forced error states URL : https://patchwork.freedesktop.org/series/73221/ State : success == Summary == CI Bug Log - changes from CI_DRM_7900 -> Patchwork_16501 Summary --- **WARNING** Minor unknown changes coming with Patchwork_16501 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16501, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16501/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16501: ### IGT changes ### Warnings * igt@gem_ctx_create@basic-files: - fi-whl-u: [INCOMPLETE][1] ([i915#1194]) -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-whl-u/igt@gem_ctx_cre...@basic-files.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16501/fi-whl-u/igt@gem_ctx_cre...@basic-files.html Known issues Here are the changes found in Patchwork_16501 that come from known issues: ### IGT changes ### Possible fixes * igt@i915_selftest@live_execlists: - fi-icl-y: [DMESG-FAIL][3] ([fdo#108569]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-icl-y/igt@i915_selftest@live_execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16501/fi-icl-y/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gtt: - fi-skl-6770hq: [TIMEOUT][5] ([fdo#111732] / [fdo#112271]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-skl-6770hq/igt@i915_selftest@live_gtt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16501/fi-skl-6770hq/igt@i915_selftest@live_gtt.html - fi-skl-6600u: [TIMEOUT][7] ([fdo#111732] / [fdo#112271]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-skl-6600u/igt@i915_selftest@live_gtt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16501/fi-skl-6600u/igt@i915_selftest@live_gtt.html * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [FAIL][9] ([fdo#109635] / [i915#217]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16501/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][11] ([fdo#111407]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7900/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16501/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#111732]: https://bugs.freedesktop.org/show_bug.cgi?id=111732 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#1194]: https://gitlab.freedesktop.org/drm/intel/issues/1194 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 Participating hosts (51 -> 44) -- Additional (2): fi-kbl-7560u fi-byt-n2820 Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ivb-3770 fi-cfl-8109u fi-skl-lmem fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_7900 -> Patchwork_16501 CI-20190529: 20190529 CI_DRM_7900: f4ab479a4e3c9e0bc9120f6618b9876bfdece9cc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5432: 6677811be6e9be9000b3217e8862353b3945a4f3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16501: 793720a0bed295a9b3564ea372092d61a522ac62 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 793720a0bed2 drm/i915/selftests: Relax timeout for error-interrupt reset processing a25b770e208d drm/i915/selftests: Exercise timeslice rewinding e34be8809aed drm/i915/selftests: Drop live_preempt_hang c6407ea9ac72 drm/i915/selftests: Disable capturing forced error states == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16501/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/selftests: Disable capturing forced error states
== Series Details ==
Series: series starting with [1/4] drm/i915/selftests: Disable capturing forced
error states
URL : https://patchwork.freedesktop.org/series/73221/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c6407ea9ac72 drm/i915/selftests: Disable capturing forced error states
e34be8809aed drm/i915/selftests: Drop live_preempt_hang
-:7: WARNING:TYPO_SPELLING: 'preemptable' may be misspelled - perhaps
'preemptible'?
#7:
live_preempt_reset's use of an non-preemptable spinner. The latter does
total: 0 errors, 1 warnings, 0 checks, 190 lines checked
a25b770e208d drm/i915/selftests: Exercise timeslice rewinding
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#13:
References: 5ba32c7be81e ("drm/i915/execlists: Always force a context reload
when rewinding RING_TAIL")
-:13: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 5ba32c7be81e
("drm/i915/execlists: Always force a context reload when rewinding RING_TAIL")'
#13:
References: 5ba32c7be81e ("drm/i915/execlists: Always force a context reload
when rewinding RING_TAIL")
-:189: WARNING:MEMORY_BARRIER: memory barrier without comment
#189: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:929:
+ wmb();
-:219: WARNING:MEMORY_BARRIER: memory barrier without comment
#219: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:959:
+ wmb();
total: 1 errors, 3 warnings, 0 checks, 221 lines checked
793720a0bed2 drm/i915/selftests: Relax timeout for error-interrupt reset
processing
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Re: [Intel-gfx] [PATCH] drm/i915/gt: change prefix to debugfs functions
Quoting Andi Shyti (2020-02-10 13:58:08) > Hi Chris, > > > > "We don't own the debugfs 'namespace' prefix." (Jani Nikula [*]) > > > > > > I agree, change the functions name from "debugfs_*" to > > > "intel_gt_*" prefix. > > > > An alternate way of looking at it is that these are all dependent on > > CONFIG_DEBUGFS. So are they not the debugfs interface? > > this is a complete matter of taste, I might have a strong opinion > if the concept of name prefix was something respected all over > i915, but that's not always the case. It's an object prefix; here I'd like to argue that it is the global debugfs/ that is the 'owner' (or root?) for this interface. > If Jani feels like enforcing the idea of the function name > prefix, I basically agree with the style. > > With "debugfs_*" I understand all those functions that handle the > debugfs as framework. Exactly. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gt: change prefix to debugfs functions
Hi Chris, > > "We don't own the debugfs 'namespace' prefix." (Jani Nikula [*]) > > > > I agree, change the functions name from "debugfs_*" to > > "intel_gt_*" prefix. > > An alternate way of looking at it is that these are all dependent on > CONFIG_DEBUGFS. So are they not the debugfs interface? this is a complete matter of taste, I might have a strong opinion if the concept of name prefix was something respected all over i915, but that's not always the case. If Jani feels like enforcing the idea of the function name prefix, I basically agree with the style. With "debugfs_*" I understand all those functions that handle the debugfs as framework. Andi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
