[Intel-gfx] linux-next: manual merge of the drm-misc tree with the drm-misc-fixes tree

[Stephen Rothwell]

Hi all,

Today's linux-next merge of the drm-misc tree got a conflict in:

  drivers/gpu/drm/drm_gem.c

between commit:

  f49a51bfdc8e ("drm/shme-helpers: Fix dma_buf_mmap forwarding bug")

from the drm-misc-fixes tree and commit:

  d693def4fd1c ("drm: Remove obsolete GEM and PRIME callbacks from struct 
drm_driver")

from the drm-misc tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/gpu/drm/drm_gem.c
index 69c2c079d803,1da67d34e55d..
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@@ -1085,9 -1076,7 +1076,9 @@@ int drm_gem_mmap_obj(struct drm_gem_obj
 */
drm_gem_object_get(obj);
  
 +  vma->vm_private_data = obj;
 +
-   if (obj->funcs && obj->funcs->mmap) {
+   if (obj->funcs->mmap) {
ret = obj->funcs->mmap(obj, vma);
if (ret) {
drm_gem_object_put(obj);


pgpV1bXcZ19SO.pgp
Description: OpenPGP digital signature
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)
URL   : https://patchwork.freedesktop.org/series/82411/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9214_full -> Patchwork_18801_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_18801_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18801_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_18801_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_create@create-clear:
- shard-tglb: [PASS][1] -> [DMESG-FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-tglb3/igt@gem_cre...@create-clear.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-tglb6/igt@gem_cre...@create-clear.html

  * igt@gem_exec_whisper@basic-contexts-all:
- shard-iclb: [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-iclb5/igt@gem_exec_whis...@basic-contexts-all.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-iclb2/igt@gem_exec_whis...@basic-contexts-all.html

  
New tests
-

  New tests have been introduced between CI_DRM_9214_full and 
Patchwork_18801_full:

### New CI tests (1) ###

  * boot:
- Statuses : 200 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18801_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_read@empty-block:
- shard-glk:  [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-glk1/igt@drm_r...@empty-block.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-glk8/igt@drm_r...@empty-block.html

  * igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding:
- shard-skl:  [PASS][7] -> [FAIL][8] ([i915#54]) +1 similar issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-skl8/igt@kms_cursor_...@pipe-c-cursor-128x42-sliding.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-skl8/igt@kms_cursor_...@pipe-c-cursor-128x42-sliding.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl:  [PASS][9] -> [FAIL][10] ([i915#79])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-edp1.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp1:
- shard-apl:  [PASS][11] -> [DMESG-WARN][12] ([i915#1635] / 
[i915#1982]) +1 similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-apl2/igt@kms_flip@plain-flip-fb-recreate-interrupti...@a-dp1.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-apl3/igt@kms_flip@plain-flip-fb-recreate-interrupti...@a-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-iclb: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +2 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-iclb8/igt@kms_flip@plain-flip-fb-recreate-interrupti...@a-edp1.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-iclb5/igt@kms_flip@plain-flip-fb-recreate-interrupti...@a-edp1.html

  * igt@kms_flip_tiling@flip-y-tiled:
- shard-kbl:  [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +2 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-kbl2/igt@kms_flip_til...@flip-y-tiled.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-kbl4/igt@kms_flip_til...@flip-y-tiled.html

  * igt@kms_hdr@bpc-switch-dpms:
- shard-skl:  [PASS][17] -> [FAIL][18] ([i915#1188]) +2 similar 
issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-skl10/igt@kms_...@bpc-switch-dpms.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-skl1/igt@kms_...@bpc-switch-dpms.html

  * igt@kms_plane_cursor@pipe-c-primary-size-128:
- shard-skl:  [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +11 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-skl7/igt@kms_plane_cur...@pipe-c-primary-size-128.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/shard-skl6/igt@kms_plane_cur...@pipe-c-primary-size-128.html

  * igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][21] -> 

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/6] drm/i915/display/psr: Calculate selective fetch plane registers

[Souza, Jose]

On Wed, 2020-10-28 at 05:54 +, Patchwork wrote:
Patch Details
Series: series starting with [v2,1/6] drm/i915/display/psr: Calculate selective 
fetch plane registers
URL:https://patchwork.freedesktop.org/series/83119/
State:  failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/index.html
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18793
Summary

FAILURE

Serious unknown changes coming with Patchwork_18793 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18793, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/index.html

Possible new issues

Here are the unknown changes that may have been introduced in Patchwork_18793:

IGT changes
Possible regressions

  *   igt@i915_selftest@live@gt_lrc:

 *   fi-bsw-n3050: 
PASS
 -> 
DMESG-FAIL

Unrelated.

  *   igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:

 *   fi-tgl-y: 
PASS
 -> 
FAIL

This one will be a test that we need to fix, it is using legacy api that do not 
calls current PSR2 sel fetch functions.
But for the initial enabling of selective fetch when doing page flips it is out 
of scope.

Warnings

  *   igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:

 *   fi-tgl-y: 
DMESG-WARN
 (i915#1982) -> 
FAIL
  *   igt@runner@aborted:

 *   fi-cfl-8109u: 
FAIL
 (k.org#202107 / 
k.org#202109) -> 
FAIL

New tests

New tests have been introduced between CI_DRM_9206 and Patchwork_18793:

New CI tests (1)

  *   boot:
 *   Statuses : 41 pass(s)
 *   Exec time: [0.0] s

Known issues

Here are the changes found in Patchwork_18793 that come from known issues:

IGT changes
Issues hit

  *   igt@debugfs_test@read_all_entries:

 *   fi-tgl-u2: 
PASS
 -> 
DMESG-WARN
 (i915#402)
  *   igt@gem_ctx_create@basic-files:

 *   fi-apl-guc: 
PASS
 -> 
INCOMPLETE
 (i915#1635)
  *   igt@i915_module_load@reload:

 *   fi-byt-j1900: 
PASS
 -> 
DMESG-WARN
 (i915#1982)
  *   igt@kms_busy@basic@flip:

 *   fi-kbl-soraka: 
PASS
 -> 
DMESG-WARN
 (i915#1982)

 *   fi-tgl-y: 
PASS
 -> 
DMESG-WARN
 (i915#1982) +1 similar 
issue

  *   igt@kms_chamelium@dp-crc-fast:

 *   fi-cml-u2: 
PASS
 -> 
INCOMPLETE
 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Force initial atomic check in all eDP panels

[Patchwork]

== Series Details ==

Series: drm/i915: Force initial atomic check in all eDP panels
URL   : https://patchwork.freedesktop.org/series/83170/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9214_full -> Patchwork_18800_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_18800_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18800_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_18800_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-tglb: [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-tglb7/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/shard-tglb2/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html

  
New tests
-

  New tests have been introduced between CI_DRM_9214_full and 
Patchwork_18800_full:

### New CI tests (1) ###

  * boot:
- Statuses : 175 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18800_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_read@empty-block:
- shard-glk:  [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar 
issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-glk1/igt@drm_r...@empty-block.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/shard-glk9/igt@drm_r...@empty-block.html

  * igt@gem_eio@kms:
- shard-snb:  [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-snb5/igt@gem_...@kms.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/shard-snb7/igt@gem_...@kms.html

  * igt@gem_exec_create@basic:
- shard-glk:  [PASS][7] -> [FAIL][8] ([i915#1888])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-glk2/igt@gem_exec_cre...@basic.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/shard-glk2/igt@gem_exec_cre...@basic.html

  * igt@gem_exec_create@madvise:
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#1888] / [i915#2545])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-glk2/igt@gem_exec_cre...@madvise.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/shard-glk2/igt@gem_exec_cre...@madvise.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen:
- shard-skl:  [PASS][11] -> [FAIL][12] ([i915#54]) +5 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-skl2/igt@kms_cursor_...@pipe-b-cursor-128x128-onscreen.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/shard-skl6/igt@kms_cursor_...@pipe-b-cursor-128x128-onscreen.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled:
- shard-snb:  [PASS][13] -> [SKIP][14] ([fdo#109271]) +2 similar 
issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-snb7/igt@kms_draw_...@draw-method-xrgb2101010-mmap-gtt-xtiled.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/shard-snb2/igt@kms_draw_...@draw-method-xrgb2101010-mmap-gtt-xtiled.html

  * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
- shard-tglb: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 
similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-tglb1/igt@kms_frontbuffer_track...@fbc-1p-indfb-fliptrack.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/shard-tglb3/igt@kms_frontbuffer_track...@fbc-1p-indfb-fliptrack.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl:  [PASS][17] -> [DMESG-WARN][18] ([i915#1635] / 
[i915#1982]) +1 similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-apl6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/shard-apl1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/shard-iclb3/igt@kms_frontbuffer_track...@fbc-suspend.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/shard-iclb7/igt@kms_frontbuffer_track...@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes

[Navare, Manasi D]

I don’t see how these failures are related to the patch series

Manasi

From: Patchwork 
Sent: Wednesday, October 28, 2020 4:31 PM
To: Navare, Manasi D 
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: failure for series starting with [v3,1/6] drm/i915/dp: 
Some reshuffling in mode_valid as prep for bigjoiner modes

Patch Details
Series:

series starting with [v3,1/6] drm/i915/dp: Some reshuffling in mode_valid as 
prep for bigjoiner modes

URL:

https://patchwork.freedesktop.org/series/83173/

State:

failure

Details:

https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18802/index.html

CI Bug Log - changes from CI_DRM_9214 -> Patchwork_18802
Summary

FAILURE

Serious unknown changes coming with Patchwork_18802 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18802, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18802/index.html

Possible new issues

Here are the unknown changes that may have been introduced in Patchwork_18802:

IGT changes
Possible regressions

  *   igt@kms_force_connector_basic@force-load-detect:
 *   fi-hsw-4770: 
PASS
 -> 
FAIL
 *   fi-elk-e7500: 
PASS
 -> 
FAIL
 *   fi-ivb-3770: 
PASS
 -> 
FAIL
 *   fi-byt-j1900: 
PASS
 -> 
FAIL
 *   fi-blb-e6850: 
PASS
 -> 
INCOMPLETE
 *   fi-ilk-650: 
PASS
 -> 
FAIL
 *   fi-snb-2520m: 
PASS
 -> 
FAIL
 *   fi-bwr-2160: 
PASS
 -> 
INCOMPLETE
 *   fi-snb-2600: 
PASS
 -> 
FAIL
  *   igt@runner@aborted:
 *   fi-pnv-d510: NOTRUN -> 
FAIL
 *   fi-gdg-551: NOTRUN -> 
FAIL
 *   fi-bwr-2160: NOTRUN -> 
FAIL
 *   fi-blb-e6850: NOTRUN -> 
FAIL

New tests

New tests have been introduced between CI_DRM_9214 and Patchwork_18802:

New CI tests (1)

  *   boot:
 *   Statuses : 39 pass(s)
 *   Exec time: [0.0] s

Known issues

Here are the changes found in Patchwork_18802 that come from known issues:

IGT changes
Issues hit

  *   igt@i915_module_load@reload:
 *   fi-tgl-u2: 
PASS
 -> 
DMESG-WARN
 (i915#1982 / 

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/6] drm/i915/dp: Some reshuffling in 
mode_valid as prep for bigjoiner modes
URL   : https://patchwork.freedesktop.org/series/83173/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9214 -> Patchwork_18802


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_18802 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18802, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18802/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_18802:

### IGT changes ###

 Possible regressions 

  * igt@kms_force_connector_basic@force-load-detect:
- fi-hsw-4770:[PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-hsw-4770/igt@kms_force_connector_ba...@force-load-detect.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18802/fi-hsw-4770/igt@kms_force_connector_ba...@force-load-detect.html
- fi-elk-e7500:   [PASS][3] -> [FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-elk-e7500/igt@kms_force_connector_ba...@force-load-detect.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18802/fi-elk-e7500/igt@kms_force_connector_ba...@force-load-detect.html
- fi-ivb-3770:[PASS][5] -> [FAIL][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-ivb-3770/igt@kms_force_connector_ba...@force-load-detect.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18802/fi-ivb-3770/igt@kms_force_connector_ba...@force-load-detect.html
- fi-byt-j1900:   [PASS][7] -> [FAIL][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-byt-j1900/igt@kms_force_connector_ba...@force-load-detect.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18802/fi-byt-j1900/igt@kms_force_connector_ba...@force-load-detect.html
- fi-blb-e6850:   [PASS][9] -> [INCOMPLETE][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-blb-e6850/igt@kms_force_connector_ba...@force-load-detect.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18802/fi-blb-e6850/igt@kms_force_connector_ba...@force-load-detect.html
- fi-ilk-650: [PASS][11] -> [FAIL][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-ilk-650/igt@kms_force_connector_ba...@force-load-detect.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18802/fi-ilk-650/igt@kms_force_connector_ba...@force-load-detect.html
- fi-snb-2520m:   [PASS][13] -> [FAIL][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-snb-2520m/igt@kms_force_connector_ba...@force-load-detect.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18802/fi-snb-2520m/igt@kms_force_connector_ba...@force-load-detect.html
- fi-bwr-2160:[PASS][15] -> [INCOMPLETE][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-bwr-2160/igt@kms_force_connector_ba...@force-load-detect.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18802/fi-bwr-2160/igt@kms_force_connector_ba...@force-load-detect.html
- fi-snb-2600:[PASS][17] -> [FAIL][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-snb-2600/igt@kms_force_connector_ba...@force-load-detect.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18802/fi-snb-2600/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][19]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18802/fi-pnv-d510/igt@run...@aborted.html
- fi-gdg-551: NOTRUN -> [FAIL][20]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18802/fi-gdg-551/igt@run...@aborted.html
- fi-bwr-2160:NOTRUN -> [FAIL][21]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18802/fi-bwr-2160/igt@run...@aborted.html
- fi-blb-e6850:   NOTRUN -> [FAIL][22]
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18802/fi-blb-e6850/igt@run...@aborted.html

  
New tests
-

  New tests have been introduced between CI_DRM_9214 and Patchwork_18802:

### New CI tests (1) ###

  * boot:
- Statuses : 39 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18802 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_module_load@reload:
- fi-tgl-u2:  [PASS][23] -> [DMESG-WARN][24] ([i915#1982] / 
[k.org#205379])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-tgl-u2/igt@i915_module_l...@reload.html

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/6] drm/i915/dp: Some reshuffling in 
mode_valid as prep for bigjoiner modes
URL   : https://patchwork.freedesktop.org/series/83173/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
29b307e050f4 drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner 
modes
7b5090a4c566 drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split
-:141: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#141: FILE: drivers/gpu/drm/i915/display/intel_display.c:13460:
+   crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = 
crtc_state->uapi.adjusted_mode;

total: 0 errors, 0 warnings, 1 checks, 357 lines checked
f4900e21412a drm/i915: Add pipe_mode readout in verify_crtc_state
a5f14d0b240f drm/i915: Pass intel_atomic_state instead of drm_atomic_state
779bec036a45 drm/i915/dp: Prep for bigjoiner atomic check
1388a0c36ca0 drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.


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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)
URL   : https://patchwork.freedesktop.org/series/82411/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9214 -> Patchwork_18801


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/index.html

New tests
-

  New tests have been introduced between CI_DRM_9214 and Patchwork_18801:

### New CI tests (1) ###

  * boot:
- Statuses : 39 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18801 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-tgl-y:   [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +2 similar 
issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-tgl-y/igt@gem_exec_gttf...@basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-tgl-y/igt@gem_exec_gttf...@basic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-kefka:   [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2:  [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  
 Possible fixes 

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-tgl-y/igt@debugfs_test@read_all_entries.html
- {fi-kbl-7560u}: [INCOMPLETE][9] ([i915#2417]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka:   [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
- fi-apl-guc: [DMESG-WARN][13] ([i915#1635] / [i915#1982]) -> 
[PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-apl-guc/igt@i915_pm_...@basic-pci-d3-state.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-apl-guc/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@kms_busy@basic@flip:
- fi-kbl-soraka:  [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
- fi-tgl-y:   [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-tgl-y/igt@kms_busy@ba...@flip.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-tgl-y/igt@kms_busy@ba...@flip.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2:  [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html

  * igt@vgem_basic@unload:
- fi-skl-guc: [DMESG-WARN][21] ([i915#2203]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-skl-guc/igt@vgem_ba...@unload.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-skl-guc/igt@vgem_ba...@unload.html

  
 Warnings 

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-tgl-y:   [DMESG-WARN][23] ([i915#1982] / [i915#2411]) -> 
[DMESG-WARN][24] ([i915#2411])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-tgl-y/igt@i915_pm_...@basic-pci-d3-state.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18801/fi-tgl-y/igt@i915_pm_...@basic-pci-d3-state.html

  
  {name}: This element is suppressed. This means it is ignored when 

Re: [Intel-gfx] [PATCH v3 19/19] drm/i915: Get rid of ibx_irq_pre_postinstall()

[Lucas De Marchi]

On Wed, Oct 28, 2020 at 11:33:23PM +0200, Ville Syrjälä wrote:

From: Ville Syrjälä 

ibx_irq_pre_postinstall() looks totally pointless. We can just
init both SDEIMR and SDEIER at the same time before enabling the
master intererupt. It's equally racy as the other order due


master interrupt


to doing all of this from the postinstall stage with the interrupt
handler already in place. That is, safe with MSI but racy with
shared legacy interrupts. Fortunately we should have MSI on all ilk+.

Signed-off-by: Ville Syrjälä 


Reviewed-by: Lucas De Marchi 

Lucas De Marchi


---
drivers/gpu/drm/i915/i915_irq.c | 46 -
1 file changed, 17 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 95268fca2fbc..fdd132e2ec76 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2910,24 +2910,6 @@ static void ibx_irq_reset(struct drm_i915_private 
*dev_priv)
I915_WRITE(SERR_INT, 0x);
}

-/*
- * SDEIER is also touched by the interrupt handler to work around missed PCH
- * interrupts. Hence we can't update it after the interrupt handler is enabled 
-
- * instead we unconditionally enable all PCH interrupt sources here, but then
- * only unmask them as needed with SDEIMR.
- *
- * This function needs to be called before interrupts are enabled.
- */
-static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
-{
-   if (HAS_PCH_NOP(dev_priv))
-   return;
-
-   drm_WARN_ON(_priv->drm, I915_READ(SDEIER) != 0);
-   I915_WRITE(SDEIER, 0x);
-   POSTING_READ(SDEIER);
-}
-
static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = _priv->uncore;
@@ -3545,8 +3527,20 @@ static void bxt_hpd_irq_setup(struct drm_i915_private 
*dev_priv)
bxt_hpd_detection_setup(dev_priv);
}

+/*
+ * SDEIER is also touched by the interrupt handler to work around missed PCH
+ * interrupts. Hence we can't update it after the interrupt handler is enabled 
-
+ * instead we unconditionally enable all PCH interrupt sources here, but then
+ * only unmask them as needed with SDEIMR.
+ *
+ * Note that we currently do this after installing the interrupt handler,
+ * but before we enable the master interrupt. That should be sufficient
+ * to avoid races with the irq handler, assuming we have MSI. Shared legacy
+ * interrupts could still race.
+ */
static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
{
+   struct intel_uncore *uncore = _priv->uncore;
u32 mask;

if (HAS_PCH_NOP(dev_priv))
@@ -3559,8 +3553,7 @@ static void ibx_irq_postinstall(struct drm_i915_private 
*dev_priv)
else
mask = SDE_GMBUS_CPT;

-   gen3_assert_iir_is_zero(_priv->uncore, SDEIIR);
-   I915_WRITE(SDEIMR, ~mask);
+   GEN3_IRQ_INIT(uncore, SDE, ~mask, 0x);
}

static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3593,14 +3586,12 @@ static void ilk_irq_postinstall(struct drm_i915_private 
*dev_priv)

dev_priv->irq_mask = ~display_mask;

-   ibx_irq_pre_postinstall(dev_priv);
+   ibx_irq_postinstall(dev_priv);

gen5_gt_irq_postinstall(_priv->gt);

GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
  display_mask | extra_mask);
-
-   ibx_irq_postinstall(dev_priv);
}

void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
@@ -3725,15 +3716,12 @@ static void gen8_de_irq_postinstall(struct 
drm_i915_private *dev_priv)

static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
{
-   if (HAS_PCH_SPLIT(dev_priv))
-   ibx_irq_pre_postinstall(dev_priv);
-
-   gen8_gt_irq_postinstall(_priv->gt);
-   gen8_de_irq_postinstall(dev_priv);
-
if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev_priv);

+   gen8_gt_irq_postinstall(_priv->gt);
+   gen8_de_irq_postinstall(dev_priv);
+
gen8_master_intr_enable(dev_priv->uncore.regs);
}

--
2.26.2

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Re: [Intel-gfx] [PATCH v3 17/19] drm/i915: Enable hpd logic only for ports that are present

[Lucas De Marchi]

On Wed, Oct 28, 2020 at 11:33:21PM +0200, Ville Syrjälä wrote:

From: Ville Syrjälä 

Let's enable the hardware hpd logic only for the ports we
can actually use.

In theory this may save some miniscule amounts of power,
and more importantly it eliminates a lot if platform specific
codepaths since the generic thing can now deal with any
combination of ports being present on each SKU.

v2: Deal with DG1

Signed-off-by: Ville Syrjälä 



Reviewed-by: Lucas De Marchi 

Lucas De Marchi


---
drivers/gpu/drm/i915/i915_irq.c | 302 ++--
drivers/gpu/drm/i915/i915_reg.h |  17 --
2 files changed, 205 insertions(+), 114 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index fa8a07c2f82d..2337416e581c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -61,6 +61,8 @@
 */

typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
+typedef u32 (*hotplug_enables_func)(struct drm_i915_private *i915,
+   enum hpd_pin pin);

static const u32 hpd_ilk[HPD_NUM_PINS] = {
[HPD_PORT_A] = DE_DP_A_HOTPLUG,
@@ -1230,6 +1232,18 @@ static u32 intel_hpd_hotplug_irqs(struct 
drm_i915_private *dev_priv,
return hotplug_irqs;
}

+static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
+hotplug_enables_func hotplug_enables)
+{
+   struct intel_encoder *encoder;
+   u32 hotplug = 0;
+
+   for_each_intel_encoder(>drm, encoder)
+   hotplug |= hotplug_enables(i915, encoder->hpd_pin);
+
+   return hotplug;
+}
+
static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
{
wake_up_all(_priv->gmbus_wait_queue);
@@ -3152,6 +3166,31 @@ static void cherryview_irq_reset(struct drm_i915_private 
*dev_priv)
spin_unlock_irq(_priv->irq_lock);
}

+static u32 ibx_hotplug_enables(struct drm_i915_private *i915,
+  enum hpd_pin pin)
+{
+   switch (pin) {
+   case HPD_PORT_A:
+   /*
+* When CPU and PCH are on the same package, port A
+* HPD must be enabled in both north and south.
+*/
+   return HAS_PCH_LPT_LP(i915) ?
+   PORTA_HOTPLUG_ENABLE : 0;
+   case HPD_PORT_B:
+   return PORTB_HOTPLUG_ENABLE |
+   PORTB_PULSE_DURATION_2ms;
+   case HPD_PORT_C:
+   return PORTC_HOTPLUG_ENABLE |
+   PORTC_PULSE_DURATION_2ms;
+   case HPD_PORT_D:
+   return PORTD_HOTPLUG_ENABLE |
+   PORTD_PULSE_DURATION_2ms;
+   default:
+   return 0;
+   }
+}
+
static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug;
@@ -3162,18 +3201,14 @@ static void ibx_hpd_detection_setup(struct 
drm_i915_private *dev_priv)
 * The pulse duration bits are reserved on LPT+.
 */
hotplug = I915_READ(PCH_PORT_HOTPLUG);
-   hotplug &= ~(PORTB_PULSE_DURATION_MASK |
+   hotplug &= ~(PORTA_HOTPLUG_ENABLE |
+PORTB_HOTPLUG_ENABLE |
+PORTC_HOTPLUG_ENABLE |
+PORTD_HOTPLUG_ENABLE |
+PORTB_PULSE_DURATION_MASK |
 PORTC_PULSE_DURATION_MASK |
 PORTD_PULSE_DURATION_MASK);
-   hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
-   hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
-   hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
-   /*
-* When CPU and PCH are on the same package, port A
-* HPD must be enabled in both north and south.
-*/
-   if (HAS_PCH_LPT_LP(dev_priv))
-   hotplug |= PORTA_HOTPLUG_ENABLE;
+   hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables);
I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
}

@@ -3189,28 +3224,63 @@ static void ibx_hpd_irq_setup(struct drm_i915_private 
*dev_priv)
ibx_hpd_detection_setup(dev_priv);
}

-static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv,
-   u32 enable_mask)
+static u32 icp_ddi_hotplug_enables(struct drm_i915_private *i915,
+  enum hpd_pin pin)
+{
+   switch (pin) {
+   case HPD_PORT_A:
+   case HPD_PORT_B:
+   case HPD_PORT_C:
+   return SHOTPLUG_CTL_DDI_HPD_ENABLE(pin);
+   default:
+   return 0;
+   }
+}
+
+static u32 icp_tc_hotplug_enables(struct drm_i915_private *i915,
+ enum hpd_pin pin)
+{
+   switch (pin) {
+   case HPD_PORT_TC1:
+   case HPD_PORT_TC2:
+   case HPD_PORT_TC3:
+   case HPD_PORT_TC4:
+   case HPD_PORT_TC5:
+   case HPD_PORT_TC6:
+   return ICP_TC_HPD_ENABLE(pin);
+   default:
+   return 0;
+   }
+}
+
+static void 

Re: [Intel-gfx] [PATCH v11 10/12] drm/i915: Link planes in a bigjoiner configuration, v3.

[Navare, Manasi]

On Wed, Oct 28, 2020 at 03:04:37PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 28, 2020 at 01:26:27PM +0100, Maarten Lankhorst wrote:
> > Op 27-10-2020 om 20:11 schreef Ville Syrjälä:
> > > On Tue, Oct 27, 2020 at 11:19:16AM -0700, Navare, Manasi wrote:
> > >> On Tue, Oct 27, 2020 at 03:42:30PM +0200, Ville Syrjälä wrote:
> > >>> On Mon, Oct 26, 2020 at 03:41:48PM -0700, Navare, Manasi wrote:
> >  On Mon, Oct 26, 2020 at 10:18:54PM +0200, Ville Syrjälä wrote:
> > > On Wed, Oct 21, 2020 at 10:42:21PM -0700, Manasi Navare wrote:
> > >> From: Maarten Lankhorst 
> > >>
> > >>  Make sure that when a plane is set in a bigjoiner mode, we will add
> > >>  their counterpart to the atomic state as well. This will allow us to
> > >>  make sure all state is available when planes are checked.
> > >>
> > >> Because of the funny interactions with bigjoiner and planar YUV
> > >> formats, we may end up adding a lot of planes, so we have to keep
> > >> iterating until we no longer add any planes.
> > >>
> > >> Also fix the atomic intel plane iterator, so things watermarks start
> > >> working automagically.
> > >>
> > >> v6:
> > >> * Fix from_plane_state assignments (Manasi)
> > >> v5:
> > >> * Rebase after adding sagv support (Manasi)
> > >> v4:
> > >> * Manual rebase (Manasi)
> > >> Changes since v1:
> > >> - Rebase on top of plane_state split, cleaning up the code a lot.
> > >> - Make intel_atomic_crtc_state_for_each_plane_state() bigjoiner 
> > >> capable.
> > >> - Add iter macro to intel_atomic_crtc_state_for_each_plane_state() to
> > >>   keep iteration working.
> > >> Changes since v2:
> > >> - Add icl_(un)set_bigjoiner_plane_links, to make it more clear where
> > >>   links are made and broken.
> > >>
> > >> Signed-off-by: Maarten Lankhorst 
> > >> Signed-off-by: Manasi Navare 
> > >> ---
> > >>  .../gpu/drm/i915/display/intel_atomic_plane.c |  53 -
> > >>  .../gpu/drm/i915/display/intel_atomic_plane.h |   3 +-
> > >>  drivers/gpu/drm/i915/display/intel_display.c  | 207 
> > >> --
> > >>  drivers/gpu/drm/i915/display/intel_display.h  |  20 +-
> > >>  .../drm/i915/display/intel_display_types.h|  11 +
> > >>  drivers/gpu/drm/i915/intel_pm.c   |  20 +-
> > >>  6 files changed, 274 insertions(+), 40 deletions(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c 
> > >> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > >> index 3334ff253600..5df928f8f322 100644
> > >> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > >> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > >> @@ -246,12 +246,17 @@ static void intel_plane_clear_hw_state(struct 
> > >> intel_plane_state *plane_state)
> > >>  memset(_state->hw, 0, sizeof(plane_state->hw));
> > >>  }
> > >>  
> > >> -void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state 
> > >> *plane_state,
> > >> +void intel_plane_copy_uapi_to_hw_state(const struct 
> > >> intel_crtc_state *crtc_state,
> > >> +   struct intel_plane_state 
> > >> *plane_state,
> > >> const struct intel_plane_state 
> > >> *from_plane_state)
> > >>  {
> > >>  intel_plane_clear_hw_state(plane_state);
> > >>  
> > >> -plane_state->hw.crtc = from_plane_state->uapi.crtc;
> > >> +if (from_plane_state->uapi.crtc)
> > >> +plane_state->hw.crtc = crtc_state->uapi.crtc;
> > >> +else
> > >> +plane_state->hw.crtc = NULL;
> > >> +
> > >>  plane_state->hw.fb = from_plane_state->uapi.fb;
> > >>  if (plane_state->hw.fb)
> > >>  drm_framebuffer_get(plane_state->hw.fb);
> > >> @@ -320,15 +325,36 @@ int intel_plane_atomic_check_with_state(const 
> > >> struct intel_crtc_state *old_crtc_
> > >>  }
> > >>  
> > >>  static struct intel_crtc *
> > >> -get_crtc_from_states(const struct intel_plane_state 
> > >> *old_plane_state,
> > >> +get_crtc_from_states(struct intel_atomic_state *state,
> > >> + const struct intel_plane_state *old_plane_state,
> > >>   const struct intel_plane_state *new_plane_state)
> > >>  {
> > >> +struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > >> +struct intel_plane *plane = 
> > >> to_intel_plane(new_plane_state->uapi.plane);
> > >> +
> > >>  if (new_plane_state->uapi.crtc)
> > >>  return to_intel_crtc(new_plane_state->uapi.crtc);
> > >>  
> > >>  if (old_plane_state->uapi.crtc)
> > >>  return to_intel_crtc(old_plane_state->uapi.crtc);
> > >>  
> > >> +if (new_plane_state->bigjoiner_slave) {
> > >> +

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)
URL   : https://patchwork.freedesktop.org/series/82411/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem 
*[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in 
assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem 
*[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in 
argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem 
*[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in 
assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem 
*[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in 
argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int 
[usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem 
*[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in 
argument 1 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 
279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 
'wakeref_auto_timeout' - unexpected unlock
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev5)
URL   : https://patchwork.freedesktop.org/series/82411/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
ee08af3a4155 drm/i915: s/PORT_TC/TC_PORT_/
-:313: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible 
side-effects?
#313: FILE: drivers/gpu/drm/i915/i915_reg.h:10330:
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
   (tc_port) + 12 : \
+  (tc_port) - TC_PORT_4 + 
21))

total: 0 errors, 0 warnings, 1 checks, 269 lines checked
fe19b59abf59 drm/i915: Add PORT_TCn aliases to enum port
287c7226cbc0 drm/i915: Give DDI encoders even better names
-:44: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#44: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:5186:
+tc_port != TC_PORT_NONE ? phy_name(phy) : 
tc_port - TC_PORT_1 + '1');

-:54: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#54: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:5196:
+tc_port != TC_PORT_NONE ? phy_name(phy) : 
tc_port - TC_PORT_1 + '1');

total: 0 errors, 2 warnings, 0 checks, 33 lines checked
5b31fc7d2973 drm/i915: Introduce AUX_CH_USBCn
907a6f378413 drm/i915: Pimp AUX CH names
cb0bc14e42f1 drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup
00239142669f drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin
4a178195598a drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()
60ce87b4b638 drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits
6d636206aba9 drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG()
8b3e20e749bc drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits
15e7a4125c07 drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs()
2cecffb1a88e drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt 
variants
62b52af3a1fc drm/i915: Don't enable hpd detection logic from irq_postinstall()
567b2cbf4a84 drm/i915: Rename 'tmp_mask'
26e100e104d0 drm/i915: Remove the per-plaform IIR HPD masking
3059c7ee9196 drm/i915: Enable hpd logic only for ports that are present
f2def9dff59f drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+
bd3fd9cc28ab drm/i915: Get rid of ibx_irq_pre_postinstall()


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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Force initial atomic check in all eDP panels

[Patchwork]

== Series Details ==

Series: drm/i915: Force initial atomic check in all eDP panels
URL   : https://patchwork.freedesktop.org/series/83170/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9214 -> Patchwork_18800


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/index.html

New tests
-

  New tests have been introduced between CI_DRM_9214 and Patchwork_18800:

### New CI tests (1) ###

  * boot:
- Statuses : 39 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18800 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@core_hotunplug@unbind-rebind:
- fi-skl-lmem:[PASS][1] -> [DMESG-WARN][2] ([i915#2605])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-skl-lmem/igt@core_hotunp...@unbind-rebind.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/fi-skl-lmem/igt@core_hotunp...@unbind-rebind.html

  * igt@i915_pm_rpm@module-reload:
- fi-kbl-7500u:   [PASS][3] -> [DMESG-WARN][4] ([i915#203])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-kbl-7500u/igt@i915_pm_...@module-reload.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/fi-kbl-7500u/igt@i915_pm_...@module-reload.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900:   [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y:   [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar 
issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
 Possible fixes 

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +2 similar 
issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/fi-tgl-y/igt@debugfs_test@read_all_entries.html
- {fi-kbl-7560u}: [INCOMPLETE][11] ([i915#2417]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-apl-guc: [DMESG-WARN][13] ([i915#1635] / [i915#1982]) -> 
[PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-apl-guc/igt@i915_pm_...@basic-pci-d3-state.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/fi-apl-guc/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@kms_busy@basic@flip:
- fi-kbl-soraka:  [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
- fi-tgl-y:   [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-tgl-y/igt@kms_busy@ba...@flip.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/fi-tgl-y/igt@kms_busy@ba...@flip.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2:  [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html

  * igt@vgem_basic@unload:
- fi-skl-guc: [DMESG-WARN][21] ([i915#2203]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-skl-guc/igt@vgem_ba...@unload.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/fi-skl-guc/igt@vgem_ba...@unload.html

  
 Warnings 

  * igt@core_hotunplug@unbind-rebind:
- fi-icl-u2:  [DMESG-WARN][23] ([i915#289]) -> [DMESG-WARN][24] 
([i915#1982] / [i915#289])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9214/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18800/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-tgl-y:   

Re: [Intel-gfx] [PATCH v3 14/19] drm/i915: Don't enable hpd detection logic from irq_postinstall()

[Lucas De Marchi]

On Wed, Oct 28, 2020 at 11:33:18PM +0200, Ville Syrjälä wrote:

From: Ville Syrjälä 

No reason that I can see why we should enable the hpd detection logic
already during irq postinstall phase. We don't even do this on all
the platforms. We just need it before we actually enable the hotplug
interrupts in .hpd_irq_setup(), and in fact we already do it there as
well. Let's just eliminate the redundant early setup.


yep, it makes sense. If CI is happy and doesn't explode in something
neither of us antecipated, I'm happy too.


Reviewed-by: Lucas De Marchi 

Lucas De Marchi



Signed-off-by: Ville Syrjälä 
---
drivers/gpu/drm/i915/i915_irq.c | 40 +++--
1 file changed, 3 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 43e3e7f70c14..3ff5747e755d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3407,8 +3407,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private 
*dev_priv)
ibx_hpd_irq_setup(dev_priv);
}

-static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
- u32 enabled_irqs)
+static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
+   u32 enabled_irqs)
{
u32 hotplug;

@@ -3439,11 +3439,6 @@ static void __bxt_hpd_detection_setup(struct 
drm_i915_private *dev_priv,
I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
}

-static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
-{
-   __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
-}
-
static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug_irqs, enabled_irqs;
@@ -3453,7 +3448,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private 
*dev_priv)

bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);

-   __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
+   bxt_hpd_detection_setup(dev_priv, enabled_irqs);
}

static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3472,12 +3467,6 @@ static void ibx_irq_postinstall(struct drm_i915_private 
*dev_priv)

gen3_assert_iir_is_zero(_priv->uncore, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
-
-   if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
-   HAS_PCH_LPT(dev_priv))
-   ibx_hpd_detection_setup(dev_priv);
-   else
-   spt_hpd_detection_setup(dev_priv);
}

static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3517,8 +3506,6 @@ static void ilk_irq_postinstall(struct drm_i915_private 
*dev_priv)
GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
  display_mask | extra_mask);

-   ilk_hpd_detection_setup(dev_priv);
-
ibx_irq_postinstall(dev_priv);
}

@@ -3639,12 +3626,6 @@ static void gen8_de_irq_postinstall(struct 
drm_i915_private *dev_priv)

GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
  de_hpd_enables);
-   gen11_tc_hpd_detection_setup(dev_priv);
-   gen11_tbt_hpd_detection_setup(dev_priv);
-   } else if (IS_GEN9_LP(dev_priv)) {
-   bxt_hpd_detection_setup(dev_priv);
-   } else if (IS_BROADWELL(dev_priv)) {
-   ilk_hpd_detection_setup(dev_priv);
}
}

@@ -3672,21 +3653,6 @@ static void icp_irq_postinstall(struct drm_i915_private 
*dev_priv)

gen3_assert_iir_is_zero(_priv->uncore, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
-
-   if (HAS_PCH_DG1(dev_priv))
-   icp_ddi_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK);
-   else if (HAS_PCH_TGP(dev_priv)) {
-   icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
-   icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK);
-   } else if (HAS_PCH_JSP(dev_priv)) {
-   icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
-   } else if (HAS_PCH_MCC(dev_priv)) {
-   icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
-   icp_tc_hpd_detection_setup(dev_priv, 
ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
-   } else {
-   icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
-   icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
-   }
}

static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
--
2.26.2

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Re: [Intel-gfx] linux-next: Signed-off-by missing for commit in the drm-intel-fixes tree

[Chris Wilson]

Quoting Stephen Rothwell (2020-10-28 21:28:23)
> Hi all,
> 
> Commit
> 
>   d13208a88f41 ("lockdep: Fix nr_unused_locks")
> 
> is missing a Signed-off-by from its author.
> 
> Also, the author's email name is missing the leading 'P'.

And it shouldn't be in the drm-intel-fixes tree.
-Chris
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[Intel-gfx] [PATCH v3 5/6] drm/i915/dp: Prep for bigjoiner atomic check

[Manasi Navare]

No functional changes here. Just pass intel_atomic_state
along with crtc_state to certain atomic_check functions.
This will lay the foundation for adding bigjoiner master/slave
states in atomic check.

v2:
* More prep with intel_atomic_state (Ville)

Cc: Ville Syrjälä 
Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/i915/display/intel_atomic.c  |  9 +
 drivers/gpu/drm/i915/display/intel_atomic.h  |  3 ++-
 drivers/gpu/drm/i915/display/intel_display.c | 21 
 3 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c 
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 86be032bcf96..e243ce97b534 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -270,14 +270,15 @@ void intel_crtc_free_hw_state(struct intel_crtc_state 
*crtc_state)
intel_crtc_put_color_blobs(crtc_state);
 }
 
-void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
+const struct intel_crtc_state *from_crtc_state)
 {
drm_property_replace_blob(_state->hw.degamma_lut,
- crtc_state->uapi.degamma_lut);
+ from_crtc_state->uapi.degamma_lut);
drm_property_replace_blob(_state->hw.gamma_lut,
- crtc_state->uapi.gamma_lut);
+ from_crtc_state->uapi.gamma_lut);
drm_property_replace_blob(_state->hw.ctm,
- crtc_state->uapi.ctm);
+ from_crtc_state->uapi.ctm);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h 
b/drivers/gpu/drm/i915/display/intel_atomic.h
index 285de07011dc..62a3365ed5e6 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -43,7 +43,8 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct 
drm_crtc *crtc);
 void intel_crtc_destroy_state(struct drm_crtc *crtc,
   struct drm_crtc_state *state);
 void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
-void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
+const struct intel_crtc_state 
*from_crtc_state);
 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
 void intel_atomic_state_free(struct drm_atomic_state *state);
 void intel_atomic_state_clear(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 78708552095a..233bd894c5c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13456,13 +13456,17 @@ static bool check_digital_port_conflicts(struct 
intel_atomic_state *state)
 }
 
 static void
-intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
+intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
+  struct intel_crtc_state *crtc_state)
 {
-   intel_crtc_copy_color_blobs(crtc_state);
+   const struct intel_crtc_state *from_crtc_state = crtc_state;
+
+   intel_crtc_copy_color_blobs(crtc_state, from_crtc_state);
 }
 
 static void
-intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
+intel_crtc_copy_uapi_to_hw_state(struct intel_atomic_state *state,
+struct intel_crtc_state *crtc_state)
 {
crtc_state->hw.enable = crtc_state->uapi.enable;
crtc_state->hw.active = crtc_state->uapi.active;
@@ -13470,7 +13474,7 @@ intel_crtc_copy_uapi_to_hw_state(struct 
intel_crtc_state *crtc_state)
crtc_state->hw.pipe_mode = crtc_state->hw.adjusted_mode = 
crtc_state->uapi.adjusted_mode;
crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
 
-   intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
+   intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc_state);
 }
 
 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state 
*crtc_state)
@@ -13493,7 +13497,8 @@ static void intel_crtc_copy_hw_to_uapi_state(struct 
intel_crtc_state *crtc_state
 }
 
 static int
-intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
+intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
+struct intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -13525,7 +13530,7 @@ intel_crtc_prepare_cleared_state(struct 
intel_crtc_state *crtc_state)
memcpy(crtc_state, saved_state, sizeof(*crtc_state));
kfree(saved_state);
 
-   

[Intel-gfx] [PATCH v3 1/6] drm/i915/dp: Some reshuffling in mode_valid as prep for bigjoiner modes

[Manasi Navare]

No functional changes. This patch just moves some mode checks
around to prepare for adding bigjoiner related mode validation

Cc: Ville Syrjälä 
Signed-off-by: Manasi Navare 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 818daab252f3..2c29e7f5281b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -721,6 +721,9 @@ intel_dp_mode_valid(struct drm_connector *connector,
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
 
+   if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+   return MODE_H_ILLEGAL;
+
if (intel_dp_is_edp(intel_dp) && fixed_mode) {
if (mode->hdisplay > fixed_mode->hdisplay)
return MODE_PANEL;
@@ -731,6 +734,9 @@ intel_dp_mode_valid(struct drm_connector *connector,
target_clock = fixed_mode->clock;
}
 
+   if (mode->clock < 1)
+   return MODE_CLOCK_LOW;
+
max_link_clock = intel_dp_max_link_rate(intel_dp);
max_lanes = intel_dp_max_lane_count(intel_dp);
 
@@ -771,12 +777,6 @@ intel_dp_mode_valid(struct drm_connector *connector,
target_clock > max_dotclk)
return MODE_CLOCK_HIGH;
 
-   if (mode->clock < 1)
-   return MODE_CLOCK_LOW;
-
-   if (mode->flags & DRM_MODE_FLAG_DBLCLK)
-   return MODE_H_ILLEGAL;
-
status = intel_dp_mode_valid_downstream(intel_connector,
mode, target_clock);
if (status != MODE_OK)
-- 
2.19.1

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[Intel-gfx] [PATCH v3 2/6] drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder split

[Manasi Navare]

From: Maarten Lankhorst 

With bigjoiner, there will be 2 pipes driving 2 halves of 1 transcoder,
because of this, we need a pipe_mode for various calculations, including
for example watermarks, plane clipping, etc.

v7:
* Remove redundant comment (Ville)
* Just keep mode instead of pipe_mode (Ville)
v6:
* renaming in separate function, only pipe_mode here (Ville)
* Add description (Maarten)
v5:
* Rebase (Manasi)
v4:
* Manual rebase (Manasi)
v3:
* Change state to crtc_state, fix rebase err  (Manasi)
v2:
* Manual Rebase (Manasi)

Signed-off-by: Maarten Lankhorst 
Signed-off-by: Manasi Navare 
Reviewed-by: Animesh Manna 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c  | 38 +-
 .../drm/i915/display/intel_display_types.h| 11 ++-
 drivers/gpu/drm/i915/intel_pm.c   | 76 +--
 3 files changed, 68 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index f41b6f8b5618..756683b2a5be 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6167,18 +6167,16 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, 
bool force_detach,
 
 static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
 {
-   const struct drm_display_mode *adjusted_mode =
-   _state->hw.adjusted_mode;
+   const struct drm_display_mode *pipe_mode = _state->hw.pipe_mode;
int width, height;
 
if (crtc_state->pch_pfit.enabled) {
width = drm_rect_width(_state->pch_pfit.dst);
height = drm_rect_height(_state->pch_pfit.dst);
} else {
-   width = adjusted_mode->crtc_hdisplay;
-   height = adjusted_mode->crtc_vdisplay;
+   width = pipe_mode->crtc_hdisplay;
+   height = pipe_mode->crtc_vdisplay;
}
-
return skl_update_scaler(crtc_state, !crtc_state->hw.active,
 SKL_CRTC_INDEX,
 _state->scaler_state.scaler_id,
@@ -8192,7 +8190,7 @@ static bool intel_crtc_supports_double_wide(const struct 
intel_crtc *crtc)
 
 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
 {
-   u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock;
+   u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
 
/*
@@ -8229,7 +8227,7 @@ static void intel_crtc_compute_pixel_rate(struct 
intel_crtc_state *crtc_state)
if (HAS_GMCH(dev_priv))
/* FIXME calculate proper pipe pixel rate for GMCH pfit */
crtc_state->pixel_rate =
-   crtc_state->hw.adjusted_mode.crtc_clock;
+   crtc_state->hw.pipe_mode.crtc_clock;
else
crtc_state->pixel_rate =
ilk_pipe_pixel_rate(crtc_state);
@@ -8239,7 +8237,7 @@ static int intel_crtc_compute_config(struct intel_crtc 
*crtc,
 struct intel_crtc_state *pipe_config)
 {
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   const struct drm_display_mode *adjusted_mode = 
_config->hw.adjusted_mode;
+   const struct drm_display_mode *pipe_mode = _config->hw.pipe_mode;
int clock_limit = dev_priv->max_dotclk_freq;
 
if (INTEL_GEN(dev_priv) < 4) {
@@ -8250,16 +8248,16 @@ static int intel_crtc_compute_config(struct intel_crtc 
*crtc,
 * is > 90% of the (display) core speed.
 */
if (intel_crtc_supports_double_wide(crtc) &&
-   adjusted_mode->crtc_clock > clock_limit) {
+   pipe_mode->crtc_clock > clock_limit) {
clock_limit = dev_priv->max_dotclk_freq;
pipe_config->double_wide = true;
}
}
 
-   if (adjusted_mode->crtc_clock > clock_limit) {
+   if (pipe_mode->crtc_clock > clock_limit) {
drm_dbg_kms(_priv->drm,
"requested pixel clock (%d kHz) too high (max: %d 
kHz, double wide: %s)\n",
-   adjusted_mode->crtc_clock, clock_limit,
+   pipe_mode->crtc_clock, clock_limit,
yesno(pipe_config->double_wide));
return -EINVAL;
}
@@ -8302,7 +8300,7 @@ static int intel_crtc_compute_config(struct intel_crtc 
*crtc,
 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
 */
if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
-   adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
+   pipe_mode->crtc_hsync_start == pipe_mode->crtc_hdisplay)
return -EINVAL;
 
intel_crtc_compute_pixel_rate(pipe_config);
@@ -12821,15 +12819,15 @@ static bool c8_planes_changed(const struct 

[Intel-gfx] [PATCH v3 4/6] drm/i915: Pass intel_atomic_state instead of drm_atomic_state

[Manasi Navare]

No functional changes, to align with previous cleanups pass
intel_atomic_state instead of drm_atomic_state.
Also pass this intel_atomic_state with crtc_state to
some of the atomic_check functions.

Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/i915/display/intel_display.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 50522c8a6ff0..78708552095a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12671,7 +12671,7 @@ static bool encoders_cloneable(const struct 
intel_encoder *a,
  b->cloneable & (1 << a->type));
 }
 
-static bool check_single_encoder_cloning(struct drm_atomic_state *state,
+static bool check_single_encoder_cloning(struct intel_atomic_state *state,
 struct intel_crtc *crtc,
 struct intel_encoder *encoder)
 {
@@ -12680,7 +12680,7 @@ static bool check_single_encoder_cloning(struct 
drm_atomic_state *state,
struct drm_connector_state *connector_state;
int i;
 
-   for_each_new_connector_in_state(state, connector, connector_state, i) {
+   for_each_new_connector_in_state(>base, connector, 
connector_state, i) {
if (connector_state->crtc != >base)
continue;
 
@@ -13531,10 +13531,10 @@ intel_crtc_prepare_cleared_state(struct 
intel_crtc_state *crtc_state)
 }
 
 static int
-intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
+intel_modeset_pipe_config(struct intel_atomic_state *state,
+ struct intel_crtc_state *pipe_config)
 {
struct drm_crtc *crtc = pipe_config->uapi.crtc;
-   struct drm_atomic_state *state = pipe_config->uapi.state;
struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
struct drm_connector *connector;
struct drm_connector_state *connector_state;
@@ -13576,7 +13576,7 @@ intel_modeset_pipe_config(struct intel_crtc_state 
*pipe_config)
   _config->pipe_src_w,
   _config->pipe_src_h);
 
-   for_each_new_connector_in_state(state, connector, connector_state, i) {
+   for_each_new_connector_in_state(>base, connector, 
connector_state, i) {
struct intel_encoder *encoder =
to_intel_encoder(connector_state->best_encoder);
 
@@ -13614,7 +13614,7 @@ intel_modeset_pipe_config(struct intel_crtc_state 
*pipe_config)
 * adjust it according to limitations or connector properties, and also
 * a chance to reject the mode entirely.
 */
-   for_each_new_connector_in_state(state, connector, connector_state, i) {
+   for_each_new_connector_in_state(>base, connector, 
connector_state, i) {
struct intel_encoder *encoder =
to_intel_encoder(connector_state->best_encoder);
 
@@ -15238,7 +15238,7 @@ static int intel_atomic_check(struct drm_device *dev,
if (!new_crtc_state->hw.enable)
continue;
 
-   ret = intel_modeset_pipe_config(new_crtc_state);
+   ret = intel_modeset_pipe_config(state, new_crtc_state);
if (ret)
goto fail;
}
-- 
2.19.1

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[Intel-gfx] [PATCH v3 6/6] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid(), v3.

[Manasi Navare]

From: Maarten Lankhorst 

Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.

v12:
* slice_count logic simplify (Ville)
* Fix unnecessary changes in downstream_mode_valid (Ville)
v11:
* Make intel_dp_can_bigjoiner non static
so it can be used in intel_display (Manasi)
v10:
* Simplify logic (Ville)
* Allow bigjoiner on edp (Ville)
v9:
* Restric Bigjoiner on PORT A (Ville)
v8:
* use source dotclock for max dotclock (Manasi)
v7:
* Add can_bigjoiner() helper (Ville)
* Pass bigjoiner to plane_size validation (Ville)
v6:
* Rebase after dp_downstream mode valid changes (Manasi)
v5:
* Increase max plane width to support 8K with bigjoiner (Maarten)
v4:
* Rebase (Manasi)

Changes since v1:
- Disallow bigjoiner on eDP.
Changes since v2:
- Rename intel_dp_downstream_max_dotclock to intel_dp_max_dotclock,
  and split off the downstream and source checking to its own function.
  (Ville)
v3:
* Rebase (Manasi)

Signed-off-by: Manasi Navare 
Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/display/intel_display.c |  5 +-
 drivers/gpu/drm/i915/display/intel_display.h |  3 +-
 drivers/gpu/drm/i915/display/intel_dp.c  | 77 
 drivers/gpu/drm/i915/display/intel_dp.h  |  1 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_dsi.c |  2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c|  2 +-
 7 files changed, 72 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 233bd894c5c3..45d8deafe89a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17770,7 +17770,8 @@ intel_mode_valid(struct drm_device *dev,
 
 enum drm_mode_status
 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
-   const struct drm_display_mode *mode)
+   const struct drm_display_mode *mode,
+   bool bigjoiner)
 {
int plane_width_max, plane_height_max;
 
@@ -17787,7 +17788,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private 
*dev_priv,
 * too big for that.
 */
if (INTEL_GEN(dev_priv) >= 11) {
-   plane_width_max = 5120;
+   plane_width_max = 5120 << bigjoiner;
plane_height_max = 4320;
} else {
plane_width_max = 5120;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h 
b/drivers/gpu/drm/i915/display/intel_display.h
index 1b946209e06b..4f8dee9dfb4d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -497,7 +497,8 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private 
*dev_priv,
 bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
 enum drm_mode_status
 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
-   const struct drm_display_mode *mode);
+   const struct drm_display_mode *mode,
+   bool bigjoiner);
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2c29e7f5281b..2336b204a3e9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -254,6 +254,17 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
return max_link_clock * max_lanes;
 }
 
+bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
+{
+   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+   struct intel_encoder *encoder = _dig_port->base;
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+   return INTEL_GEN(dev_priv) >= 12 ||
+   (INTEL_GEN(dev_priv) == 11 &&
+encoder->port != PORT_A);
+}
+
 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 {
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -519,7 +530,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
 
 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
   u32 link_clock, u32 lane_count,
-  u32 mode_clock, u32 mode_hdisplay)
+  u32 mode_clock, u32 mode_hdisplay,
+  bool bigjoiner)
 {
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -537,6 +549,10 @@ static u16 intel_dp_dsc_get_output_bpp(struct 
drm_i915_private *i915,
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
  

[Intel-gfx] [PATCH v3 3/6] drm/i915: Add pipe_mode readout in verify_crtc_state

[Manasi Navare]

This adds new pipe_mode readout in verify_crtc_state()
Here it is just adjusted_mode without bigjoiner.
Bigjoiner pipe_mode readout will be added later.

While at it, create a separate intel_encoder_get_config()
function that calls encoder->get_config hook.
This is needed so that later we can add beigjoienr related
readout here.

Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/i915/display/intel_display.c | 16 +---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 756683b2a5be..50522c8a6ff0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8220,6 +8220,16 @@ static u32 ilk_pipe_pixel_rate(const struct 
intel_crtc_state *crtc_state)
   pfit_w * pfit_h);
 }
 
+static void intel_encoder_get_config(struct intel_encoder *encoder,
+struct intel_crtc_state *crtc_state)
+{
+   struct drm_display_mode *pipe_mode = _state->hw.pipe_mode;
+
+   encoder->get_config(encoder, crtc_state);
+
+   *pipe_mode = crtc_state->hw.adjusted_mode;
+}
+
 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
 {
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
@@ -12473,7 +12483,7 @@ intel_encoder_current_mode(struct intel_encoder 
*encoder)
return NULL;
}
 
-   encoder->get_config(encoder, crtc_state);
+   intel_encoder_get_config(encoder, crtc_state);
 
intel_mode_from_pipe_config(mode, crtc_state);
 
@@ -14522,7 +14532,7 @@ verify_crtc_state(struct intel_crtc *crtc,
pipe_name(pipe));
 
if (active)
-   encoder->get_config(encoder, pipe_config);
+   intel_encoder_get_config(encoder, pipe_config);
}
 
intel_crtc_compute_pixel_rate(pipe_config);
@@ -18837,7 +18847,7 @@ static void intel_modeset_readout_hw_state(struct 
drm_device *dev)
crtc_state = to_intel_crtc_state(crtc->base.state);
 
encoder->base.crtc = >base;
-   encoder->get_config(encoder, crtc_state);
+   intel_encoder_get_config(encoder, crtc_state);
if (encoder->sync_state)
encoder->sync_state(encoder, crtc_state);
} else {
-- 
2.19.1

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[Intel-gfx] [PATCH v3 12/19] drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs()

[Ville Syrjala]

From: Ville Syrjälä 

Move intel_hpd_{enabled,hotplug}_irqs() closes to the beginning of
the file so we can use them in more places. No functional changes.

Reviewed-by: Lucas De Marchi 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_irq.c | 50 -
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 70a37d4ca9e5..b355e0307a8a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1205,6 +1205,31 @@ static void intel_get_hpd_pins(struct drm_i915_private 
*dev_priv,
 
 }
 
+static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
+ const u32 hpd[HPD_NUM_PINS])
+{
+   struct intel_encoder *encoder;
+   u32 enabled_irqs = 0;
+
+   for_each_intel_encoder(_priv->drm, encoder)
+   if (dev_priv->hotplug.stats[encoder->hpd_pin].state == 
HPD_ENABLED)
+   enabled_irqs |= hpd[encoder->hpd_pin];
+
+   return enabled_irqs;
+}
+
+static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
+ const u32 hpd[HPD_NUM_PINS])
+{
+   struct intel_encoder *encoder;
+   u32 hotplug_irqs = 0;
+
+   for_each_intel_encoder(_priv->drm, encoder)
+   hotplug_irqs |= hpd[encoder->hpd_pin];
+
+   return hotplug_irqs;
+}
+
 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
 {
wake_up_all(_priv->gmbus_wait_queue);
@@ -3145,31 +3170,6 @@ static void cherryview_irq_reset(struct drm_i915_private 
*dev_priv)
spin_unlock_irq(_priv->irq_lock);
 }
 
-static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
- const u32 hpd[HPD_NUM_PINS])
-{
-   struct intel_encoder *encoder;
-   u32 enabled_irqs = 0;
-
-   for_each_intel_encoder(_priv->drm, encoder)
-   if (dev_priv->hotplug.stats[encoder->hpd_pin].state == 
HPD_ENABLED)
-   enabled_irqs |= hpd[encoder->hpd_pin];
-
-   return enabled_irqs;
-}
-
-static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
- const u32 hpd[HPD_NUM_PINS])
-{
-   struct intel_encoder *encoder;
-   u32 hotplug_irqs = 0;
-
-   for_each_intel_encoder(_priv->drm, encoder)
-   hotplug_irqs |= hpd[encoder->hpd_pin];
-
-   return hotplug_irqs;
-}
-
 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
u32 hotplug;
-- 
2.26.2

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[Intel-gfx] [PATCH v3 11/19] drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits

[Ville Syrjala]

From: Ville Syrjälä 

Parametrize the icp+ TC HPD bits using hpd_pin rather than
tc_port so it's clear what kind of an animal we're dealing
with.

Reviewed-by: Lucas De Marchi 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_irq.c | 30 -
 drivers/gpu/drm/i915/i915_reg.h | 40 -
 2 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d3f35d9a02dd..70a37d4ca9e5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -144,12 +144,12 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
-   [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_1),
-   [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_2),
-   [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_3),
-   [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(TC_PORT_4),
-   [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(TC_PORT_5),
-   [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(TC_PORT_6),
+   [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
+   [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
+   [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
+   [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
+   [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5),
+   [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6),
 };
 
 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
@@ -1092,17 +1092,17 @@ static bool icp_tc_port_hotplug_long_detect(enum 
hpd_pin pin, u32 val)
 {
switch (pin) {
case HPD_PORT_TC1:
-   return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_1);
+   return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC1);
case HPD_PORT_TC2:
-   return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_2);
+   return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC2);
case HPD_PORT_TC3:
-   return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_3);
+   return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC3);
case HPD_PORT_TC4:
-   return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_4);
+   return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC4);
case HPD_PORT_TC5:
-   return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_5);
+   return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC5);
case HPD_PORT_TC6:
-   return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_6);
+   return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC6);
default:
return false;
}
@@ -1884,7 +1884,7 @@ static void icp_irq_handler(struct drm_i915_private 
*dev_priv, u32 pch_iir)
tc_hotplug_trigger = 0;
} else if (HAS_PCH_MCC(dev_priv)) {
ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
-   tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(TC_PORT_1);
+   tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1);
} else {
drm_WARN(_priv->drm, !HAS_PCH_ICP(dev_priv),
 "Unrecognized PCH type 0x%x\n",
@@ -3252,7 +3252,7 @@ static void icp_hpd_irq_setup(struct drm_i915_private 
*dev_priv,
 static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
icp_hpd_irq_setup(dev_priv,
- ICP_DDI_HPD_ENABLE_MASK, 
ICP_TC_HPD_ENABLE(TC_PORT_1));
+ ICP_DDI_HPD_ENABLE_MASK, 
ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
 }
 
 /*
@@ -3675,7 +3675,7 @@ static void icp_irq_postinstall(struct drm_i915_private 
*dev_priv)
icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
} else if (HAS_PCH_MCC(dev_priv)) {
icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
-   icp_tc_hpd_detection_setup(dev_priv, 
ICP_TC_HPD_ENABLE(TC_PORT_1));
+   icp_tc_hpd_detection_setup(dev_priv, 
ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
} else {
icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cc43e2c5088b..9e68ba254d51 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8349,23 +8349,23 @@ enum {
 
 /* south display engine interrupt: ICP/TGP */
 #define SDE_GMBUS_ICP  (1 << 23)
-#define SDE_TC_HOTPLUG_ICP(tc_port)(1 << ((tc_port) + 24))
+#define SDE_TC_HOTPLUG_ICP(hpd_pin)REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
 #define SDE_DDI_HOTPLUG_ICP(hpd_pin)   REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
 #define SDE_DDI_MASK_ICP   (SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
-#define SDE_TC_MASK_ICP

[Intel-gfx] [PATCH v3 02/19] drm/i915: Add PORT_TCn aliases to enum port

[Ville Syrjala]

From: Ville Syrjälä 

Since tgl the DDIs have been named A,B,C,TC1,TC2,TC3...
Add the appropriate enum values for the TC DDIs to enum port.

v2: Deal with rkl and dg1

Reviewed-by: Lucas De Marchi 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_bios.c| 10 +++
 drivers/gpu/drm/i915/display/intel_ddi.c | 12 -
 drivers/gpu/drm/i915/display/intel_display.c | 28 ++--
 drivers/gpu/drm/i915/display/intel_display.h |  8 ++
 4 files changed, 32 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index 0a309645fe06..ff825be0ac88 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1688,17 +1688,15 @@ static enum port dvo_port_to_port(struct 
drm_i915_private *dev_priv,
[PORT_I] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },
};
/*
-* Bspec lists the ports as A, B, C, D - however internally in our
-* driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the
-* registers in Display Engine match the right offsets. Apply the
-* mapping here to translate from VBT to internal convention.
+* RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D
+* map to DDI A,B,TC1,TC2 respectively.
 */
static const int rkl_port_mapping[][3] = {
[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
[PORT_C] = { -1 },
-   [PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
-   [PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+   [PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+   [PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
};
 
if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 63380b166c25..24245157dcb9 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5069,8 +5069,8 @@ static bool hti_uses_phy(struct drm_i915_private *i915, 
enum phy phy)
 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
enum port port)
 {
-   if (port >= PORT_D)
-   return HPD_PORT_C + port - PORT_D;
+   if (port >= PORT_TC1)
+   return HPD_PORT_C + port - PORT_TC1;
else
return HPD_PORT_A + port - PORT_A;
 }
@@ -5078,8 +5078,8 @@ static enum hpd_pin dg1_hpd_pin(struct drm_i915_private 
*dev_priv,
 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
enum port port)
 {
-   if (port >= PORT_D)
-   return HPD_PORT_TC1 + port - PORT_D;
+   if (port >= PORT_TC1)
+   return HPD_PORT_TC1 + port - PORT_TC1;
else
return HPD_PORT_A + port - PORT_A;
 }
@@ -5090,8 +5090,8 @@ static enum hpd_pin rkl_hpd_pin(struct drm_i915_private 
*dev_priv,
if (HAS_PCH_TGP(dev_priv))
return tgl_hpd_pin(dev_priv, port);
 
-   if (port >= PORT_D)
-   return HPD_PORT_C + port - PORT_D;
+   if (port >= PORT_TC1)
+   return HPD_PORT_C + port - PORT_TC1;
else
return HPD_PORT_A + port - PORT_A;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index da2a91122d44..cddbda5303ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7463,12 +7463,12 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, 
enum phy phy)
 
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 {
-   if (IS_ROCKETLAKE(i915) && port >= PORT_D)
-   return (enum phy)port - 1;
+   if (IS_ROCKETLAKE(i915) && port >= PORT_TC1)
+   return PHY_C + port - PORT_TC1;
else if (IS_JSL_EHL(i915) && port == PORT_D)
return PHY_A;
 
-   return (enum phy)port;
+   return PHY_A + port - PORT_A;
 }
 
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port 
port)
@@ -7477,9 +7477,9 @@ enum tc_port intel_port_to_tc(struct drm_i915_private 
*dev_priv, enum port port)
return TC_PORT_NONE;
 
if (INTEL_GEN(dev_priv) >= 12)
-   return port - PORT_D;
-
-   return port - PORT_C;
+   return TC_PORT_1 + port - PORT_TC1;
+   else
+   return TC_PORT_1 + port - PORT_C;
 }
 
 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
@@ -17216,17 +17216,17 @@ static void intel_setup_outputs(struct 
drm_i915_private *dev_priv)
if (IS_ROCKETLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
-   

[Intel-gfx] [PATCH v3 15/19] drm/i915: Rename 'tmp_mask'

[Ville Syrjala]

From: Ville Syrjälä 

Replace this silly tmp_mask with hotplug_trigger/te_trigger
where appropriate.

Reviewed-by: Lucas De Marchi 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_irq.c | 22 --
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3ff5747e755d..788e32098d3a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2386,7 +2386,6 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, 
u32 master_ctl)
if (master_ctl & GEN8_DE_PORT_IRQ) {
iir = I915_READ(GEN8_DE_PORT_IIR);
if (iir) {
-   u32 tmp_mask;
bool found = false;
 
I915_WRITE(GEN8_DE_PORT_IIR, iir);
@@ -2398,15 +2397,17 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, 
u32 master_ctl)
}
 
if (IS_GEN9_LP(dev_priv)) {
-   tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
-   if (tmp_mask) {
-   bxt_hpd_irq_handler(dev_priv, tmp_mask);
+   u32 hotplug_trigger = iir & 
BXT_DE_PORT_HOTPLUG_MASK;
+
+   if (hotplug_trigger) {
+   bxt_hpd_irq_handler(dev_priv, 
hotplug_trigger);
found = true;
}
} else if (IS_BROADWELL(dev_priv)) {
-   tmp_mask = iir & BDW_DE_PORT_HOTPLUG_MASK;
-   if (tmp_mask) {
-   ilk_hpd_irq_handler(dev_priv, tmp_mask);
+   u32 hotplug_trigger = iir & 
BDW_DE_PORT_HOTPLUG_MASK;
+
+   if (hotplug_trigger) {
+   ilk_hpd_irq_handler(dev_priv, 
hotplug_trigger);
found = true;
}
}
@@ -2417,9 +2418,10 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, 
u32 master_ctl)
}
 
if (INTEL_GEN(dev_priv) >= 11) {
-   tmp_mask = iir & (DSI0_TE | DSI1_TE);
-   if (tmp_mask) {
-   
gen11_dsi_te_interrupt_handler(dev_priv, tmp_mask);
+   u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
+
+   if (te_trigger) {
+   
gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);
found = true;
}
}
-- 
2.26.2

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[Intel-gfx] [PATCH v3 06/19] drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup

[Ville Syrjala]

From: Ville Syrjälä 

As with the VBT DVO port, RKL uses PHY based mapping for the
VBT AUX CH. Adjust the code to use the new AUX_USBCn names
and add a comment to explain the situation.

Reviewed-by: Lucas De Marchi 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index ff825be0ac88..4cc949b228f2 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2664,12 +2664,16 @@ enum aux_ch intel_bios_port_aux_ch(struct 
drm_i915_private *dev_priv,
aux_ch = AUX_CH_B;
break;
case DP_AUX_C:
+   /*
+* RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
+* map to DDI A,B,TC1,TC2 respectively.
+*/
aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
-   AUX_CH_D : AUX_CH_C;
+   AUX_CH_USBC1 : AUX_CH_C;
break;
case DP_AUX_D:
aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
-   AUX_CH_E : AUX_CH_D;
+   AUX_CH_USBC2 : AUX_CH_D;
break;
case DP_AUX_E:
aux_ch = AUX_CH_E;
-- 
2.26.2

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[Intel-gfx] [PATCH v3 18/19] drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+

[Ville Syrjala]

From: Ville Syrjälä 

No reason not to use GEN3_IRQ_INIT() on icp+.

Reviewed-by: Lucas De Marchi 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_irq.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2337416e581c..95268fca2fbc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3739,14 +3739,10 @@ static void gen8_irq_postinstall(struct 
drm_i915_private *dev_priv)
 
 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
 {
+   struct intel_uncore *uncore = _priv->uncore;
u32 mask = SDE_GMBUS_ICP;
 
-   drm_WARN_ON(_priv->drm, I915_READ(SDEIER) != 0);
-   I915_WRITE(SDEIER, 0x);
-   POSTING_READ(SDEIER);
-
-   gen3_assert_iir_is_zero(_priv->uncore, SDEIIR);
-   I915_WRITE(SDEIMR, ~mask);
+   GEN3_IRQ_INIT(uncore, SDE, ~mask, 0x);
 }
 
 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
-- 
2.26.2

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[Intel-gfx] [PATCH v3 13/19] drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants

[Ville Syrjala]

From: Ville Syrjälä 

No reason to stuff both type-c and tbt into the same function.
Let's split this so we may more easily handle platforms that
lack the tbt spefific bits.

Reviewed-by: Lucas De Marchi 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_irq.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b355e0307a8a..43e3e7f70c14 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3281,7 +3281,7 @@ static void dg1_hpd_irq_setup(struct drm_i915_private 
*dev_priv)
  DG1_DDI_HPD_ENABLE_MASK, 0);
 }
 
-static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
+static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
u32 hotplug;
 
@@ -3293,6 +3293,11 @@ static void gen11_hpd_detection_setup(struct 
drm_i915_private *dev_priv)
   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
+}
+
+static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
+{
+   u32 hotplug;
 
hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
@@ -3318,7 +3323,8 @@ static void gen11_hpd_irq_setup(struct drm_i915_private 
*dev_priv)
I915_WRITE(GEN11_DE_HPD_IMR, val);
POSTING_READ(GEN11_DE_HPD_IMR);
 
-   gen11_hpd_detection_setup(dev_priv);
+   gen11_tc_hpd_detection_setup(dev_priv);
+   gen11_tbt_hpd_detection_setup(dev_priv);
 
if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
icp_hpd_irq_setup(dev_priv,
@@ -3633,7 +3639,8 @@ static void gen8_de_irq_postinstall(struct 
drm_i915_private *dev_priv)
 
GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
  de_hpd_enables);
-   gen11_hpd_detection_setup(dev_priv);
+   gen11_tc_hpd_detection_setup(dev_priv);
+   gen11_tbt_hpd_detection_setup(dev_priv);
} else if (IS_GEN9_LP(dev_priv)) {
bxt_hpd_detection_setup(dev_priv);
} else if (IS_BROADWELL(dev_priv)) {
-- 
2.26.2

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[Intel-gfx] [PATCH v3 05/19] drm/i915: Pimp AUX CH names

[Ville Syrjala]

From: Ville Syrjälä 

Let's make the AUX CH names match the spec (AUX A-F for pre-tgl,
AUX A-C or AUX USBC1-6 for tgl+). And while at it let's include
the full encoder name in the AUX CH name as well (as opposed to
just using port_name() which wouldn't give us the right thing on
tgl+).

Reviewed-by: Lucas De Marchi 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index b4f824383fe0..cf09aca7607b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1859,6 +1859,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *encoder = _port->base;
+   enum aux_ch aux_ch = dig_port->aux_ch;
 
if (INTEL_GEN(dev_priv) >= 12) {
intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
@@ -1891,9 +1892,15 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
drm_dp_aux_init(_dp->aux);
 
/* Failure to allocate our preferred name is not critical */
-   intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c",
-  aux_ch_name(dig_port->aux_ch),
-  port_name(encoder->port));
+   if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
+   intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
+  aux_ch - AUX_CH_USBC1 + '1',
+  encoder->base.name);
+   else
+   intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
+  aux_ch_name(aux_ch),
+  encoder->base.name);
+
intel_dp->aux.transfer = intel_dp_aux_transfer;
 }
 
-- 
2.26.2

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[Intel-gfx] [PATCH v3 16/19] drm/i915: Remove the per-plaform IIR HPD masking

[Ville Syrjala]

From: Ville Syrjälä 

We no longer unmask all HPD irqs, so we can drop the ugly per-platform
HPD IIR masking. IMR will prevent unsupported bits from appearing in
IIR.

v2: Deal with DG1
Include "HOTPLUG" in the mask names (Lucas)

Reviewed-by: Lucas De Marchi 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_irq.c | 24 ++--
 drivers/gpu/drm/i915/i915_reg.h | 15 +++
 2 files changed, 5 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 788e32098d3a..fa8a07c2f82d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1895,30 +1895,10 @@ static void cpt_irq_handler(struct drm_i915_private 
*dev_priv, u32 pch_iir)
 
 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 {
-   u32 ddi_hotplug_trigger, tc_hotplug_trigger;
+   u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
+   u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
u32 pin_mask = 0, long_mask = 0;
 
-   if (HAS_PCH_DG1(dev_priv)) {
-   ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
-   tc_hotplug_trigger = 0;
-   } else if (HAS_PCH_TGP(dev_priv)) {
-   ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
-   tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
-   } else if (HAS_PCH_JSP(dev_priv)) {
-   ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
-   tc_hotplug_trigger = 0;
-   } else if (HAS_PCH_MCC(dev_priv)) {
-   ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
-   tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1);
-   } else {
-   drm_WARN(_priv->drm, !HAS_PCH_ICP(dev_priv),
-"Unrecognized PCH type 0x%x\n",
-INTEL_PCH_TYPE(dev_priv));
-
-   ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
-   tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
-   }
-
if (ddi_hotplug_trigger) {
u32 dig_hotplug_reg;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9e68ba254d51..eacec3c46a4d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8351,25 +8351,16 @@ enum {
 #define SDE_GMBUS_ICP  (1 << 23)
 #define SDE_TC_HOTPLUG_ICP(hpd_pin)REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
 #define SDE_DDI_HOTPLUG_ICP(hpd_pin)   REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
-#define SDE_DDI_MASK_ICP   (SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
-SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
-#define SDE_TC_MASK_ICP
(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
-SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
-SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
-SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
-#define SDE_DDI_MASK_TGP   (SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
+#define SDE_DDI_HOTPLUG_MASK_ICP   (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
+SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
-#define SDE_TC_MASK_TGP
(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
+#define SDE_TC_HOTPLUG_MASK_ICP
(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
-#define SDE_DDI_MASK_DG1   (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
-SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
-SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
-SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
 
 #define SDEISR  _MMIO(0xc4000)
 #define SDEIMR  _MMIO(0xc4004)
-- 
2.26.2

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[Intel-gfx] [PATCH v3 07/19] drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin

[Ville Syrjala]

From: Ville Syrjälä 

Use hpd_pin to parametrize BXT_DE_PORT_HP_DDI() to make it clear
these have nothing to do with DDI ports or PHYs as such. The only
thing that matters is the HPD pin assignment.

v2: Remember the gvt

Reviewed-by: Lucas De Marchi 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/gvt/display.c | 13 +++--
 drivers/gpu/drm/i915/i915_irq.c| 12 ++--
 drivers/gpu/drm/i915/i915_reg.h| 12 ++--
 3 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/display.c 
b/drivers/gpu/drm/i915/gvt/display.c
index 7ba16ddfe75f..c124734e114c 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -173,23 +173,24 @@ static void emulate_monitor_status_change(struct 
intel_vgpu *vgpu)
int pipe;
 
if (IS_BROXTON(dev_priv)) {
-   vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
-   BXT_DE_PORT_HP_DDIB |
-   BXT_DE_PORT_HP_DDIC);
+   vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
+   ~(BXT_DE_PORT_HP_DDI(HPD_PORT_A) |
+ BXT_DE_PORT_HP_DDI(HPD_PORT_B) |
+ BXT_DE_PORT_HP_DDI(HPD_PORT_C));
 
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-   BXT_DE_PORT_HP_DDIA;
+   BXT_DE_PORT_HP_DDI(HPD_PORT_A);
}
 
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-   BXT_DE_PORT_HP_DDIB;
+   BXT_DE_PORT_HP_DDI(HPD_PORT_B);
}
 
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-   BXT_DE_PORT_HP_DDIC;
+   BXT_DE_PORT_HP_DDI(HPD_PORT_C);
}
 
return;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ffa191913139..252464d90575 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_bxt[HPD_NUM_PINS] = {
-   [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
-   [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
-   [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC,
+   [HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A),
+   [HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B),
+   [HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C),
 };
 
 static const u32 hpd_gen11[HPD_NUM_PINS] = {
@@ -3420,13 +3420,13 @@ static void __bxt_hpd_detection_setup(struct 
drm_i915_private *dev_priv,
 * For BXT invert bit has to be set based on AOB design
 * for HPD detection logic, update it based on VBT fields.
 */
-   if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
+   if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
hotplug |= BXT_DDIA_HPD_INVERT;
-   if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
+   if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
hotplug |= BXT_DDIB_HPD_INVERT;
-   if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
+   if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
hotplug |= BXT_DDIC_HPD_INVERT;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4066cc509f27..37038afd404f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7812,6 +7812,8 @@ enum {
(GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
 GEN11_PIPE_PLANE5_FAULT)
 
+#define _HPD_PIN_DDI(hpd_pin)  ((hpd_pin) - HPD_PORT_A)
+
 #define GEN8_DE_PORT_ISR _MMIO(0x0)
 #define GEN8_DE_PORT_IMR _MMIO(0x4)
 #define GEN8_DE_PORT_IIR _MMIO(0x8)
@@ -7825,12 +7827,10 @@ enum {
 #define  GEN9_AUX_CHANNEL_B(1 << 25)
 #define  DSI1_TE   (1 << 24)
 #define  DSI0_TE   (1 << 23)
-#define  BXT_DE_PORT_HP_DDIC   (1 << 5)
-#define  BXT_DE_PORT_HP_DDIB   (1 << 4)
-#define  BXT_DE_PORT_HP_DDIA   (1 << 3)
-#define  BXT_DE_PORT_HOTPLUG_MASK  (BXT_DE_PORT_HP_DDIA | \
-BXT_DE_PORT_HP_DDIB | \
-BXT_DE_PORT_HP_DDIC)
+#define  BXT_DE_PORT_HP_DDI(hpd_pin)   REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
+#define  BXT_DE_PORT_HOTPLUG_MASK  (BXT_DE_PORT_HP_DDI(HPD_PORT_A) | \
+BXT_DE_PORT_HP_DDI(HPD_PORT_B) | \
+BXT_DE_PORT_HP_DDI(HPD_PORT_C))
 #define  

[Intel-gfx] [PATCH v3 19/19] drm/i915: Get rid of ibx_irq_pre_postinstall()

[Ville Syrjala]

From: Ville Syrjälä 

ibx_irq_pre_postinstall() looks totally pointless. We can just
init both SDEIMR and SDEIER at the same time before enabling the
master intererupt. It's equally racy as the other order due
to doing all of this from the postinstall stage with the interrupt
handler already in place. That is, safe with MSI but racy with
shared legacy interrupts. Fortunately we should have MSI on all ilk+.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_irq.c | 46 -
 1 file changed, 17 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 95268fca2fbc..fdd132e2ec76 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2910,24 +2910,6 @@ static void ibx_irq_reset(struct drm_i915_private 
*dev_priv)
I915_WRITE(SERR_INT, 0x);
 }
 
-/*
- * SDEIER is also touched by the interrupt handler to work around missed PCH
- * interrupts. Hence we can't update it after the interrupt handler is enabled 
-
- * instead we unconditionally enable all PCH interrupt sources here, but then
- * only unmask them as needed with SDEIMR.
- *
- * This function needs to be called before interrupts are enabled.
- */
-static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
-{
-   if (HAS_PCH_NOP(dev_priv))
-   return;
-
-   drm_WARN_ON(_priv->drm, I915_READ(SDEIER) != 0);
-   I915_WRITE(SDEIER, 0x);
-   POSTING_READ(SDEIER);
-}
-
 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
 {
struct intel_uncore *uncore = _priv->uncore;
@@ -3545,8 +3527,20 @@ static void bxt_hpd_irq_setup(struct drm_i915_private 
*dev_priv)
bxt_hpd_detection_setup(dev_priv);
 }
 
+/*
+ * SDEIER is also touched by the interrupt handler to work around missed PCH
+ * interrupts. Hence we can't update it after the interrupt handler is enabled 
-
+ * instead we unconditionally enable all PCH interrupt sources here, but then
+ * only unmask them as needed with SDEIMR.
+ *
+ * Note that we currently do this after installing the interrupt handler,
+ * but before we enable the master interrupt. That should be sufficient
+ * to avoid races with the irq handler, assuming we have MSI. Shared legacy
+ * interrupts could still race.
+ */
 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
 {
+   struct intel_uncore *uncore = _priv->uncore;
u32 mask;
 
if (HAS_PCH_NOP(dev_priv))
@@ -3559,8 +3553,7 @@ static void ibx_irq_postinstall(struct drm_i915_private 
*dev_priv)
else
mask = SDE_GMBUS_CPT;
 
-   gen3_assert_iir_is_zero(_priv->uncore, SDEIIR);
-   I915_WRITE(SDEIMR, ~mask);
+   GEN3_IRQ_INIT(uncore, SDE, ~mask, 0x);
 }
 
 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3593,14 +3586,12 @@ static void ilk_irq_postinstall(struct drm_i915_private 
*dev_priv)
 
dev_priv->irq_mask = ~display_mask;
 
-   ibx_irq_pre_postinstall(dev_priv);
+   ibx_irq_postinstall(dev_priv);
 
gen5_gt_irq_postinstall(_priv->gt);
 
GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
  display_mask | extra_mask);
-
-   ibx_irq_postinstall(dev_priv);
 }
 
 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
@@ -3725,15 +3716,12 @@ static void gen8_de_irq_postinstall(struct 
drm_i915_private *dev_priv)
 
 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
 {
-   if (HAS_PCH_SPLIT(dev_priv))
-   ibx_irq_pre_postinstall(dev_priv);
-
-   gen8_gt_irq_postinstall(_priv->gt);
-   gen8_de_irq_postinstall(dev_priv);
-
if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev_priv);
 
+   gen8_gt_irq_postinstall(_priv->gt);
+   gen8_de_irq_postinstall(dev_priv);
+
gen8_master_intr_enable(dev_priv->uncore.regs);
 }
 
-- 
2.26.2

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[Intel-gfx] [PATCH v3 09/19] drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits

[Ville Syrjala]

From: Ville Syrjälä 

Use hpd_pin instead of port in the parametrized ICP+ DDI HPD
macros. Makes it clear what these refer to.

v2: Handle DG1

Reviewed-by: Lucas De Marchi 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_irq.c | 22 +++
 drivers/gpu/drm/i915/i915_reg.h | 50 -
 2 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 216d6247b30a..d98420b62107 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -141,9 +141,9 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_icp[HPD_NUM_PINS] = {
-   [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
-   [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
-   [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
+   [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
+   [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
+   [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_1),
[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_2),
[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_3),
@@ -153,10 +153,10 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
-   [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
-   [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
-   [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
-   [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PORT_D),
+   [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
+   [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
+   [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
+   [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
 };
 
 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
@@ -1076,13 +1076,13 @@ static bool icp_ddi_port_hotplug_long_detect(enum 
hpd_pin pin, u32 val)
 {
switch (pin) {
case HPD_PORT_A:
-   return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
+   return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_A);
case HPD_PORT_B:
-   return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
+   return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_B);
case HPD_PORT_C:
-   return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
+   return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_C);
case HPD_PORT_D:
-   return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D);
+   return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_D);
default:
return false;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 950d2bd7d7a8..eb36355ce913 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8349,26 +8349,26 @@ enum {
 /* south display engine interrupt: ICP/TGP */
 #define SDE_GMBUS_ICP  (1 << 23)
 #define SDE_TC_HOTPLUG_ICP(tc_port)(1 << ((tc_port) + 24))
-#define SDE_DDI_HOTPLUG_ICP(port)  (1 << ((port) + 16))
-#define SDE_DDI_MASK_ICP   (SDE_DDI_HOTPLUG_ICP(PORT_B) | \
-SDE_DDI_HOTPLUG_ICP(PORT_A))
+#define SDE_DDI_HOTPLUG_ICP(hpd_pin)   REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
+#define SDE_DDI_MASK_ICP   (SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
+SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
 #define SDE_TC_MASK_ICP(SDE_TC_HOTPLUG_ICP(TC_PORT_4) 
| \
 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
-#define SDE_DDI_MASK_TGP   (SDE_DDI_HOTPLUG_ICP(PORT_C) | \
-SDE_DDI_HOTPLUG_ICP(PORT_B) | \
-SDE_DDI_HOTPLUG_ICP(PORT_A))
+#define SDE_DDI_MASK_TGP   (SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
+SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
+SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
 #define SDE_TC_MASK_TGP(SDE_TC_HOTPLUG_ICP(TC_PORT_6) 
| \
 SDE_TC_HOTPLUG_ICP(TC_PORT_5) | \
 SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
-#define SDE_DDI_MASK_DG1   (SDE_DDI_HOTPLUG_ICP(PORT_D) | \
-SDE_DDI_HOTPLUG_ICP(PORT_C) | \
-SDE_DDI_HOTPLUG_ICP(PORT_B) | \
-SDE_DDI_HOTPLUG_ICP(PORT_A))

[Intel-gfx] [PATCH v3 10/19] drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG()

[Ville Syrjala]

From: Ville Syrjälä 

Use hpd_pin instead of tc_port in the GEN11_{TC,TBT}_HOTPLUG()
to make it clear what they refer to.

Reviewed-by: Lucas De Marchi 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_irq.c | 48 -
 drivers/gpu/drm/i915/i915_reg.h | 37 -
 2 files changed, 43 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d98420b62107..d3f35d9a02dd 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -132,12 +132,12 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_gen11[HPD_NUM_PINS] = {
-   [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(TC_PORT_1) | 
GEN11_TBT_HOTPLUG(TC_PORT_1),
-   [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(TC_PORT_2) | 
GEN11_TBT_HOTPLUG(TC_PORT_2),
-   [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(TC_PORT_3) | 
GEN11_TBT_HOTPLUG(TC_PORT_3),
-   [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(TC_PORT_4) | 
GEN11_TBT_HOTPLUG(TC_PORT_4),
-   [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(TC_PORT_5) | 
GEN11_TBT_HOTPLUG(TC_PORT_5),
-   [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(TC_PORT_6) | 
GEN11_TBT_HOTPLUG(TC_PORT_6),
+   [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | 
GEN11_TBT_HOTPLUG(HPD_PORT_TC1),
+   [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | 
GEN11_TBT_HOTPLUG(HPD_PORT_TC2),
+   [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | 
GEN11_TBT_HOTPLUG(HPD_PORT_TC3),
+   [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | 
GEN11_TBT_HOTPLUG(HPD_PORT_TC4),
+   [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | 
GEN11_TBT_HOTPLUG(HPD_PORT_TC5),
+   [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | 
GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
 };
 
 static const u32 hpd_icp[HPD_NUM_PINS] = {
@@ -1042,17 +1042,17 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin 
pin, u32 val)
 {
switch (pin) {
case HPD_PORT_TC1:
-   return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_1);
+   return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC1);
case HPD_PORT_TC2:
-   return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_2);
+   return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC2);
case HPD_PORT_TC3:
-   return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_3);
+   return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC3);
case HPD_PORT_TC4:
-   return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_4);
+   return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC4);
case HPD_PORT_TC5:
-   return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_5);
+   return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC5);
case HPD_PORT_TC6:
-   return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_6);
+   return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC6);
default:
return false;
}
@@ -3286,21 +3286,21 @@ static void gen11_hpd_detection_setup(struct 
drm_i915_private *dev_priv)
u32 hotplug;
 
hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
-   hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
-  GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
-  GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
-  GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
-  GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
-  GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
+   hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
+  GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
+  GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
+  GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
+  GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
+  GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
 
hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
-   hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
-  GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
-  GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
-  GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
-  GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
-  GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
+   hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
+  GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
+  GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
+  GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
+  GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
+  GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eb36355ce913..cc43e2c5088b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7813,6 +7813,7 @@ enum {
 

[Intel-gfx] [PATCH v3 17/19] drm/i915: Enable hpd logic only for ports that are present

[Ville Syrjala]

From: Ville Syrjälä 

Let's enable the hardware hpd logic only for the ports we
can actually use.

In theory this may save some miniscule amounts of power,
and more importantly it eliminates a lot if platform specific
codepaths since the generic thing can now deal with any
combination of ports being present on each SKU.

v2: Deal with DG1

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_irq.c | 302 ++--
 drivers/gpu/drm/i915/i915_reg.h |  17 --
 2 files changed, 205 insertions(+), 114 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index fa8a07c2f82d..2337416e581c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -61,6 +61,8 @@
  */
 
 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
+typedef u32 (*hotplug_enables_func)(struct drm_i915_private *i915,
+   enum hpd_pin pin);
 
 static const u32 hpd_ilk[HPD_NUM_PINS] = {
[HPD_PORT_A] = DE_DP_A_HOTPLUG,
@@ -1230,6 +1232,18 @@ static u32 intel_hpd_hotplug_irqs(struct 
drm_i915_private *dev_priv,
return hotplug_irqs;
 }
 
+static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
+hotplug_enables_func hotplug_enables)
+{
+   struct intel_encoder *encoder;
+   u32 hotplug = 0;
+
+   for_each_intel_encoder(>drm, encoder)
+   hotplug |= hotplug_enables(i915, encoder->hpd_pin);
+
+   return hotplug;
+}
+
 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
 {
wake_up_all(_priv->gmbus_wait_queue);
@@ -3152,6 +3166,31 @@ static void cherryview_irq_reset(struct drm_i915_private 
*dev_priv)
spin_unlock_irq(_priv->irq_lock);
 }
 
+static u32 ibx_hotplug_enables(struct drm_i915_private *i915,
+  enum hpd_pin pin)
+{
+   switch (pin) {
+   case HPD_PORT_A:
+   /*
+* When CPU and PCH are on the same package, port A
+* HPD must be enabled in both north and south.
+*/
+   return HAS_PCH_LPT_LP(i915) ?
+   PORTA_HOTPLUG_ENABLE : 0;
+   case HPD_PORT_B:
+   return PORTB_HOTPLUG_ENABLE |
+   PORTB_PULSE_DURATION_2ms;
+   case HPD_PORT_C:
+   return PORTC_HOTPLUG_ENABLE |
+   PORTC_PULSE_DURATION_2ms;
+   case HPD_PORT_D:
+   return PORTD_HOTPLUG_ENABLE |
+   PORTD_PULSE_DURATION_2ms;
+   default:
+   return 0;
+   }
+}
+
 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
u32 hotplug;
@@ -3162,18 +3201,14 @@ static void ibx_hpd_detection_setup(struct 
drm_i915_private *dev_priv)
 * The pulse duration bits are reserved on LPT+.
 */
hotplug = I915_READ(PCH_PORT_HOTPLUG);
-   hotplug &= ~(PORTB_PULSE_DURATION_MASK |
+   hotplug &= ~(PORTA_HOTPLUG_ENABLE |
+PORTB_HOTPLUG_ENABLE |
+PORTC_HOTPLUG_ENABLE |
+PORTD_HOTPLUG_ENABLE |
+PORTB_PULSE_DURATION_MASK |
 PORTC_PULSE_DURATION_MASK |
 PORTD_PULSE_DURATION_MASK);
-   hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
-   hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
-   hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
-   /*
-* When CPU and PCH are on the same package, port A
-* HPD must be enabled in both north and south.
-*/
-   if (HAS_PCH_LPT_LP(dev_priv))
-   hotplug |= PORTA_HOTPLUG_ENABLE;
+   hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables);
I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
 }
 
@@ -3189,28 +3224,63 @@ static void ibx_hpd_irq_setup(struct drm_i915_private 
*dev_priv)
ibx_hpd_detection_setup(dev_priv);
 }
 
-static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv,
-   u32 enable_mask)
+static u32 icp_ddi_hotplug_enables(struct drm_i915_private *i915,
+  enum hpd_pin pin)
+{
+   switch (pin) {
+   case HPD_PORT_A:
+   case HPD_PORT_B:
+   case HPD_PORT_C:
+   return SHOTPLUG_CTL_DDI_HPD_ENABLE(pin);
+   default:
+   return 0;
+   }
+}
+
+static u32 icp_tc_hotplug_enables(struct drm_i915_private *i915,
+ enum hpd_pin pin)
+{
+   switch (pin) {
+   case HPD_PORT_TC1:
+   case HPD_PORT_TC2:
+   case HPD_PORT_TC3:
+   case HPD_PORT_TC4:
+   case HPD_PORT_TC5:
+   case HPD_PORT_TC6:
+   return ICP_TC_HPD_ENABLE(pin);
+   default:
+   return 0;
+   }
+}
+
+static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
u32 hotplug;
 

[Intel-gfx] [PATCH v3 14/19] drm/i915: Don't enable hpd detection logic from irq_postinstall()

[Ville Syrjala]

From: Ville Syrjälä 

No reason that I can see why we should enable the hpd detection logic
already during irq postinstall phase. We don't even do this on all
the platforms. We just need it before we actually enable the hotplug
interrupts in .hpd_irq_setup(), and in fact we already do it there as
well. Let's just eliminate the redundant early setup.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_irq.c | 40 +++--
 1 file changed, 3 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 43e3e7f70c14..3ff5747e755d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3407,8 +3407,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private 
*dev_priv)
ibx_hpd_irq_setup(dev_priv);
 }
 
-static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
- u32 enabled_irqs)
+static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
+   u32 enabled_irqs)
 {
u32 hotplug;
 
@@ -3439,11 +3439,6 @@ static void __bxt_hpd_detection_setup(struct 
drm_i915_private *dev_priv,
I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
 }
 
-static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
-{
-   __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
-}
-
 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
u32 hotplug_irqs, enabled_irqs;
@@ -3453,7 +3448,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private 
*dev_priv)
 
bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
 
-   __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
+   bxt_hpd_detection_setup(dev_priv, enabled_irqs);
 }
 
 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3472,12 +3467,6 @@ static void ibx_irq_postinstall(struct drm_i915_private 
*dev_priv)
 
gen3_assert_iir_is_zero(_priv->uncore, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
-
-   if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
-   HAS_PCH_LPT(dev_priv))
-   ibx_hpd_detection_setup(dev_priv);
-   else
-   spt_hpd_detection_setup(dev_priv);
 }
 
 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3517,8 +3506,6 @@ static void ilk_irq_postinstall(struct drm_i915_private 
*dev_priv)
GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
  display_mask | extra_mask);
 
-   ilk_hpd_detection_setup(dev_priv);
-
ibx_irq_postinstall(dev_priv);
 }
 
@@ -3639,12 +3626,6 @@ static void gen8_de_irq_postinstall(struct 
drm_i915_private *dev_priv)
 
GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
  de_hpd_enables);
-   gen11_tc_hpd_detection_setup(dev_priv);
-   gen11_tbt_hpd_detection_setup(dev_priv);
-   } else if (IS_GEN9_LP(dev_priv)) {
-   bxt_hpd_detection_setup(dev_priv);
-   } else if (IS_BROADWELL(dev_priv)) {
-   ilk_hpd_detection_setup(dev_priv);
}
 }
 
@@ -3672,21 +3653,6 @@ static void icp_irq_postinstall(struct drm_i915_private 
*dev_priv)
 
gen3_assert_iir_is_zero(_priv->uncore, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
-
-   if (HAS_PCH_DG1(dev_priv))
-   icp_ddi_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK);
-   else if (HAS_PCH_TGP(dev_priv)) {
-   icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
-   icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK);
-   } else if (HAS_PCH_JSP(dev_priv)) {
-   icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
-   } else if (HAS_PCH_MCC(dev_priv)) {
-   icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
-   icp_tc_hpd_detection_setup(dev_priv, 
ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
-   } else {
-   icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
-   icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
-   }
 }
 
 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
-- 
2.26.2

___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v3 01/19] drm/i915: s/PORT_TC/TC_PORT_/

[Ville Syrjala]

From: Ville Syrjälä 

Make the namespacing for enum tc_port better by adding
the TC_ to the actual enum values.

v2: Drop the extra TC (Lucas)

Reviewed-by: Lucas De Marchi 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/display/intel_display.h | 14 ++--
 drivers/gpu/drm/i915/display/intel_tc.c  |  2 +-
 drivers/gpu/drm/i915/i915_irq.c  | 78 ++--
 drivers/gpu/drm/i915/i915_reg.h  | 60 +++
 5 files changed, 78 insertions(+), 78 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index f41b6f8b5618..da2a91122d44 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7474,7 +7474,7 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, 
enum port port)
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port 
port)
 {
if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
-   return PORT_TC_NONE;
+   return TC_PORT_NONE;
 
if (INTEL_GEN(dev_priv) >= 12)
return port - PORT_D;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h 
b/drivers/gpu/drm/i915/display/intel_display.h
index 1b946209e06b..1b7ae1d507f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -244,14 +244,14 @@ static inline const char *port_identifier(enum port port)
 }
 
 enum tc_port {
-   PORT_TC_NONE = -1,
+   TC_PORT_NONE = -1,
 
-   PORT_TC1 = 0,
-   PORT_TC2,
-   PORT_TC3,
-   PORT_TC4,
-   PORT_TC5,
-   PORT_TC6,
+   TC_PORT_1 = 0,
+   TC_PORT_2,
+   TC_PORT_3,
+   TC_PORT_4,
+   TC_PORT_5,
+   TC_PORT_6,
 
I915_MAX_TC_PORTS
 };
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c 
b/drivers/gpu/drm/i915/display/intel_tc.c
index 8f67aef18b2d..1cb548d757e1 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -652,7 +652,7 @@ void intel_tc_port_init(struct intel_digital_port 
*dig_port, bool is_legacy)
enum port port = dig_port->base.port;
enum tc_port tc_port = intel_port_to_tc(i915, port);
 
-   if (drm_WARN_ON(>drm, tc_port == PORT_TC_NONE))
+   if (drm_WARN_ON(>drm, tc_port == TC_PORT_NONE))
return;
 
snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name),
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dc33c96d741d..ffa191913139 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -132,24 +132,24 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_gen11[HPD_NUM_PINS] = {
-   [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(PORT_TC1) | 
GEN11_TBT_HOTPLUG(PORT_TC1),
-   [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(PORT_TC2) | 
GEN11_TBT_HOTPLUG(PORT_TC2),
-   [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(PORT_TC3) | 
GEN11_TBT_HOTPLUG(PORT_TC3),
-   [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(PORT_TC4) | 
GEN11_TBT_HOTPLUG(PORT_TC4),
-   [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(PORT_TC5) | 
GEN11_TBT_HOTPLUG(PORT_TC5),
-   [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(PORT_TC6) | 
GEN11_TBT_HOTPLUG(PORT_TC6),
+   [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(TC_PORT_1) | 
GEN11_TBT_HOTPLUG(TC_PORT_1),
+   [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(TC_PORT_2) | 
GEN11_TBT_HOTPLUG(TC_PORT_2),
+   [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(TC_PORT_3) | 
GEN11_TBT_HOTPLUG(TC_PORT_3),
+   [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(TC_PORT_4) | 
GEN11_TBT_HOTPLUG(TC_PORT_4),
+   [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(TC_PORT_5) | 
GEN11_TBT_HOTPLUG(TC_PORT_5),
+   [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(TC_PORT_6) | 
GEN11_TBT_HOTPLUG(TC_PORT_6),
 };
 
 static const u32 hpd_icp[HPD_NUM_PINS] = {
[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
-   [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
-   [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
-   [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
-   [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
-   [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
-   [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
+   [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_1),
+   [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_2),
+   [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_3),
+   [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(TC_PORT_4),
+   [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(TC_PORT_5),
+   [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(TC_PORT_6),
 };
 
 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
@@ -1042,17 +1042,17 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin 
pin, u32 val)
 {
switch (pin) {
case HPD_PORT_TC1:
-   return val & 

[Intel-gfx] [PATCH v3 04/19] drm/i915: Introduce AUX_CH_USBCn

[Ville Syrjala]

From: Ville Syrjälä 

Just like with the DDIs tgl+ renamed the AUX CHs to reflect
the type of the DDI. Let's add the aliasing enum values for
the type-C AUX CHs.

Reviewed-by: Lucas De Marchi 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_display.h |  8 +++
 drivers/gpu/drm/i915/display/intel_dp.c  | 53 ++--
 2 files changed, 58 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.h 
b/drivers/gpu/drm/i915/display/intel_display.h
index 747aec8e8580..be774f216065 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -291,6 +291,14 @@ enum aux_ch {
AUX_CH_G,
AUX_CH_H,
AUX_CH_I,
+
+   /* tgl+ */
+   AUX_CH_USBC1 = AUX_CH_D,
+   AUX_CH_USBC2,
+   AUX_CH_USBC3,
+   AUX_CH_USBC4,
+   AUX_CH_USBC5,
+   AUX_CH_USBC6,
 };
 
 #define aux_ch_name(a) ((a) + 'A')
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 818daab252f3..b4f824383fe0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1774,7 +1774,6 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp 
*intel_dp)
case AUX_CH_D:
case AUX_CH_E:
case AUX_CH_F:
-   case AUX_CH_G:
return DP_AUX_CH_CTL(aux_ch);
default:
MISSING_CASE(aux_ch);
@@ -1795,7 +1794,52 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp 
*intel_dp, int index)
case AUX_CH_D:
case AUX_CH_E:
case AUX_CH_F:
-   case AUX_CH_G:
+   return DP_AUX_CH_DATA(aux_ch, index);
+   default:
+   MISSING_CASE(aux_ch);
+   return DP_AUX_CH_DATA(AUX_CH_A, index);
+   }
+}
+
+static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+   enum aux_ch aux_ch = dig_port->aux_ch;
+
+   switch (aux_ch) {
+   case AUX_CH_A:
+   case AUX_CH_B:
+   case AUX_CH_C:
+   case AUX_CH_USBC1:
+   case AUX_CH_USBC2:
+   case AUX_CH_USBC3:
+   case AUX_CH_USBC4:
+   case AUX_CH_USBC5:
+   case AUX_CH_USBC6:
+   return DP_AUX_CH_CTL(aux_ch);
+   default:
+   MISSING_CASE(aux_ch);
+   return DP_AUX_CH_CTL(AUX_CH_A);
+   }
+}
+
+static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+   enum aux_ch aux_ch = dig_port->aux_ch;
+
+   switch (aux_ch) {
+   case AUX_CH_A:
+   case AUX_CH_B:
+   case AUX_CH_C:
+   case AUX_CH_USBC1:
+   case AUX_CH_USBC2:
+   case AUX_CH_USBC3:
+   case AUX_CH_USBC4:
+   case AUX_CH_USBC5:
+   case AUX_CH_USBC6:
return DP_AUX_CH_DATA(aux_ch, index);
default:
MISSING_CASE(aux_ch);
@@ -1816,7 +1860,10 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *encoder = _port->base;
 
-   if (INTEL_GEN(dev_priv) >= 9) {
+   if (INTEL_GEN(dev_priv) >= 12) {
+   intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
+   intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
+   } else if (INTEL_GEN(dev_priv) >= 9) {
intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
intel_dp->aux_ch_data_reg = skl_aux_data_reg;
} else if (HAS_PCH_SPLIT(dev_priv)) {
-- 
2.26.2

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[Intel-gfx] [PATCH v3 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers

[Ville Syrjala]

From: Ville Syrjälä 

Rebase of the remaining hpd cleanup series. Almost started
merging from the start but then realized some dg1 stuff landed
which needed some tweaking. So figured best repost the whole thing
one more time.

Only a few patches missing and r-b I think.

Main changes since last time:
- dg1 changes
- updated the rkl port->hpd pin function as well
- Lucas's HOTPLUG_MASK rename

Ville Syrjälä (19):
  drm/i915: s/PORT_TC/TC_PORT_/
  drm/i915: Add PORT_TCn aliases to enum port
  drm/i915: Give DDI encoders even better names
  drm/i915: Introduce AUX_CH_USBCn
  drm/i915: Pimp AUX CH names
  drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup
  drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin
  drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()
  drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits
  drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC,TBT}_HOTPLUG()
  drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits
  drm/i915: Relocate intel_hpd_{enabled,hotplug}_irqs()
  drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants
  drm/i915: Don't enable hpd detection logic from irq_postinstall()
  drm/i915: Rename 'tmp_mask'
  drm/i915: Remove the per-plaform IIR HPD masking
  drm/i915: Enable hpd logic only for ports that are present
  drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+
  drm/i915: Get rid of ibx_irq_pre_postinstall()

 drivers/gpu/drm/i915/display/intel_bios.c|  18 +-
 drivers/gpu/drm/i915/display/intel_ddi.c |  39 +-
 drivers/gpu/drm/i915/display/intel_display.c |  30 +-
 drivers/gpu/drm/i915/display/intel_display.h |  30 +-
 drivers/gpu/drm/i915/display/intel_dp.c  |  66 ++-
 drivers/gpu/drm/i915/display/intel_tc.c  |   2 +-
 drivers/gpu/drm/i915/gvt/display.c   |  15 +-
 drivers/gpu/drm/i915/i915_irq.c  | 565 ++-
 drivers/gpu/drm/i915/i915_reg.h  | 123 ++--
 9 files changed, 503 insertions(+), 385 deletions(-)

-- 
2.26.2

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[Intel-gfx] [PATCH v3 03/19] drm/i915: Give DDI encoders even better names

[Ville Syrjala]

From: Ville Syrjälä 

Let's pimp the DDI encoder->name to reflect what the spec calls them.
Ie. on pre-tgl DDI A-F, on tgl+ DDI A-C or DDI TC1-6.

Also since each encoder is really a combination of the DDI and the PHY
we include the PHY name as well.

ICL is a bit special since it already has the two different types
of DDIs (combo or TC) but it still calls them just DDI A-F regarless
of the type. For that let's add an extra "(TC)" note to remind
is which type of DDI it really is.

The code is darn ugly, but not sure there's much we can do about it.

Reviewed-by: Lucas De Marchi 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 24245157dcb9..19b16517a502 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5174,8 +5174,31 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
enum port port)
 
encoder = _port->base;
 
-   drm_encoder_init(_priv->drm, >base, _ddi_funcs,
-DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
+   if (INTEL_GEN(dev_priv) >= 12) {
+   enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+
+   drm_encoder_init(_priv->drm, >base, 
_ddi_funcs,
+DRM_MODE_ENCODER_TMDS,
+"DDI %s%c/PHY %s%c",
+port >= PORT_TC1 ? "TC" : "",
+port >= PORT_TC1 ? port_name(port) : port - 
PORT_TC1 + '1',
+tc_port != TC_PORT_NONE ? "TC" : "",
+tc_port != TC_PORT_NONE ? phy_name(phy) : 
tc_port - TC_PORT_1 + '1');
+   } else if (INTEL_GEN(dev_priv) >= 11) {
+   enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+
+   drm_encoder_init(_priv->drm, >base, 
_ddi_funcs,
+DRM_MODE_ENCODER_TMDS,
+"DDI %c%s/PHY %s%c",
+port_name(port),
+port >= PORT_C ? " (TC)" : "",
+tc_port != TC_PORT_NONE ? "TC" : "",
+tc_port != TC_PORT_NONE ? phy_name(phy) : 
tc_port - TC_PORT_1 + '1');
+   } else {
+   drm_encoder_init(_priv->drm, >base, 
_ddi_funcs,
+DRM_MODE_ENCODER_TMDS,
+"DDI %c/PHY %c", port_name(port),  
phy_name(phy));
+   }
 
mutex_init(_port->hdcp_mutex);
dig_port->num_hdcp_streams = 0;
-- 
2.26.2

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[Intel-gfx] [PATCH v3 08/19] drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()

[Ville Syrjala]

From: Ville Syrjälä 

Unify the BDW/BXT hotplug bits. BDW only has port A, but that
matches BXT port A so we can shar the same macro for both.

v2: Remember the gvt

Reviewed-by: Lucas De Marchi 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/gvt/display.c | 14 +++---
 drivers/gpu/drm/i915/i915_irq.c| 18 +-
 drivers/gpu/drm/i915/i915_reg.h| 10 +-
 3 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/display.c 
b/drivers/gpu/drm/i915/gvt/display.c
index c124734e114c..5b5c71a0b4af 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -174,23 +174,23 @@ static void emulate_monitor_status_change(struct 
intel_vgpu *vgpu)
 
if (IS_BROXTON(dev_priv)) {
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
-   ~(BXT_DE_PORT_HP_DDI(HPD_PORT_A) |
- BXT_DE_PORT_HP_DDI(HPD_PORT_B) |
- BXT_DE_PORT_HP_DDI(HPD_PORT_C));
+   ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |
+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |
+ GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
 
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-   BXT_DE_PORT_HP_DDI(HPD_PORT_A);
+   GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
}
 
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-   BXT_DE_PORT_HP_DDI(HPD_PORT_B);
+   GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
}
 
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-   BXT_DE_PORT_HP_DDI(HPD_PORT_C);
+   GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
}
 
return;
@@ -328,7 +328,7 @@ static void emulate_monitor_status_change(struct intel_vgpu 
*vgpu)
if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
if (IS_BROADWELL(dev_priv))
vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-   GEN8_PORT_DP_A_HOTPLUG;
+   GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
else
vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 252464d90575..216d6247b30a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -71,7 +71,7 @@ static const u32 hpd_ivb[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_bdw[HPD_NUM_PINS] = {
-   [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
+   [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
 };
 
 static const u32 hpd_ibx[HPD_NUM_PINS] = {
@@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_bxt[HPD_NUM_PINS] = {
-   [HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A),
-   [HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B),
-   [HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C),
+   [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
+   [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
+   [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
 };
 
 static const u32 hpd_gen11[HPD_NUM_PINS] = {
@@ -2379,7 +2379,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, 
u32 master_ctl)
found = true;
}
} else if (IS_BROADWELL(dev_priv)) {
-   tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
+   tmp_mask = iir & BDW_DE_PORT_HOTPLUG_MASK;
if (tmp_mask) {
ilk_hpd_irq_handler(dev_priv, tmp_mask);
found = true;
@@ -3420,13 +3420,13 @@ static void __bxt_hpd_detection_setup(struct 
drm_i915_private *dev_priv,
 * For BXT invert bit has to be set based on AOB design
 * for HPD detection logic, update it based on VBT fields.
 */
-   if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) &&
+   if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
hotplug |= BXT_DDIA_HPD_INVERT;
-   if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) &&
+   if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_B)) &&
intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
hotplug |= BXT_DDIB_HPD_INVERT;
-   if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) &&
+   if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) &&
intel_bios_is_port_hpd_inverted(dev_priv, 

[Intel-gfx] linux-next: Signed-off-by missing for commit in the drm-intel-fixes tree

[Stephen Rothwell]

Hi all,

Commit

  d13208a88f41 ("lockdep: Fix nr_unused_locks")

is missing a Signed-off-by from its author.

Also, the author's email name is missing the leading 'P'.

-- 
Cheers,
Stephen Rothwell


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[Intel-gfx] [PATCH] drm/i915: Force initial atomic check in all eDP panels

[José Roberto de Souza]

After commit 00e5deb5c4f5 ("drm/i915: Fix encoder lookup during PSR
atomic check") dig_port was not being used but while fixing it I
realized that would be better to mark all CRTCs that has a eDP
connector as needing to have their state computed.
The principal reason is that in future we will support PSR in
multiple panels.
And this is only forcing the state compute if no register change is
need our atomic handling will just ignore this CRTC + connector
during the atomic commit phase.

Cc: Imre Deak 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/display/intel_psr.c | 10 ++
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 1576c3722d0b..b5441f0b5b58 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1875,17 +1875,11 @@ void intel_psr_atomic_check(struct drm_connector 
*connector,
struct drm_connector_state *new_state)
 {
struct drm_i915_private *dev_priv = to_i915(connector->dev);
-   struct intel_connector *intel_connector;
-   struct intel_digital_port *dig_port;
struct drm_crtc_state *crtc_state;
 
if (!CAN_PSR(dev_priv) || !new_state->crtc ||
-   !dev_priv->psr.force_mode_changed)
-   return;
-
-   intel_connector = to_intel_connector(connector);
-   dig_port = enc_to_dig_port(to_intel_encoder(new_state->best_encoder));
-   if (dev_priv->psr.dp != _port->dp)
+   !dev_priv->psr.force_mode_changed ||
+   connector->connector_type != DRM_MODE_CONNECTOR_eDP)
return;
 
crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
-- 
2.29.1

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Re: [Intel-gfx] [PATCH] drm/i915: Fix error handling during DPRX link training

[Imre Deak]

On Tue, Oct 27, 2020 at 10:02:45AM -0400, Jason Andryuk wrote:
> On Tue, Oct 27, 2020 at 9:36 AM Imre Deak  wrote:
> >
> > Make sure to propagate the error result from the DPRX link training
> > phase. The lack of this broke the link training fall-back logic if the
> > link training failed during the DPRX phase.
> >
> > Fixes: b30edfd8d0b4 ("drm/i915: Switch to LTTPR non-transparent mode link 
> > training")
> > References: https://gitlab.freedesktop.org/drm/intel/-/issues/1378
> > Reported-by: Jason Andryuk 
> > Cc: Ville Syrjälä 
> > Signed-off-by: Imre Deak 
> 
> Reviewed-by: Jason Andryuk 

Thanks.

> I haven't tested, but I assume this will cause my 7200 to fail link
> training (channel equalization) and cause the flashing display.  Any
> suggestions there?  Would a quirk like
> https://lore.kernel.org/lkml/20201023124804.11457-1-jandr...@gmail.com/
> be acceptable?

I'd like to try finding the root cause, if you could provide some more
logs on the gitlab ticket (will follow-up there).

> 
> Regards,
> Jason
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Re: [Intel-gfx] [PATCH] drm: Remove SCATTERLIST_MAX_SEGMENT

[Daniel Vetter]

On Wed, Oct 28, 2020 at 04:15:26PM -0300, Jason Gunthorpe wrote:
> Since commit 9a40401cfa13 ("lib/scatterlist: Do not limit max_segment to
> PAGE_ALIGNED values") the max_segment input to sg_alloc_table_from_pages()
> does not have to be any special value. The new algorithm will always
> create something less than what the user provides. Thus eliminate this
> confusing constant.
> 
> - vmwgfx should use the HW capability, not mix in the OS page size for
>   calling dma_set_max_seg_size()
> 
> - i915 uses i915_sg_segment_size() both for sg_alloc_table_from_pages
>   and for some open coded sgl construction. This doesn't change the value
>   since rounddown(size, UINT_MAX) == SCATTERLIST_MAX_SEGMENT
> 
> - drm_prime_pages_to_sg uses it as a default if max_segment is zero,
>   UINT_MAX is fine to use directly.
> 
> Cc: Gerd Hoffmann 
> Cc: Daniel Vetter 
> Cc: Thomas Hellstrom 
> Cc: Qian Cai 
> Cc: "Ursulin, Tvrtko" 
> Suggested-by: Christoph Hellwig 
> Signed-off-by: Jason Gunthorpe 

lgtm. Do you want to push this through some other queue, or should I put
this into drm trees? Prefer 5.10 or 5.11?

If you want to merge this Acked-by: Daniel Vetter 
-Daniel

> ---
>  drivers/gpu/drm/drm_prime.c | 4 ++--
>  drivers/gpu/drm/i915/i915_scatterlist.h | 2 +-
>  drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 3 +--
>  include/linux/scatterlist.h | 6 --
>  tools/testing/scatterlist/main.c| 2 +-
>  5 files changed, 5 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
> index d6808f678db541..c3693e5e8b74b0 100644
> --- a/drivers/gpu/drm/drm_prime.c
> +++ b/drivers/gpu/drm/drm_prime.c
> @@ -816,8 +816,8 @@ struct sg_table *drm_prime_pages_to_sg(struct drm_device 
> *dev,
>  
>   if (dev)
>   max_segment = dma_max_mapping_size(dev->dev);
> - if (max_segment == 0 || max_segment > SCATTERLIST_MAX_SEGMENT)
> - max_segment = SCATTERLIST_MAX_SEGMENT;
> + if (max_segment == 0)
> + max_segment = UINT_MAX;
>   sge = __sg_alloc_table_from_pages(sg, pages, nr_pages, 0,
> nr_pages << PAGE_SHIFT,
> max_segment,
> diff --git a/drivers/gpu/drm/i915/i915_scatterlist.h 
> b/drivers/gpu/drm/i915/i915_scatterlist.h
> index b7b59328cb76ab..883dd8d09d6bf2 100644
> --- a/drivers/gpu/drm/i915/i915_scatterlist.h
> +++ b/drivers/gpu/drm/i915/i915_scatterlist.h
> @@ -112,7 +112,7 @@ static inline unsigned int i915_sg_segment_size(void)
>   unsigned int size = swiotlb_max_segment();
>  
>   if (size == 0)
> - return SCATTERLIST_MAX_SEGMENT;
> + size = UINT_MAX;
>  
>   size = rounddown(size, PAGE_SIZE);
>   /* swiotlb_max_segment_size can return 1 byte when it means one page. */
> diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c 
> b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
> index 31e3e5c9f36223..c1817f1a3006e0 100644
> --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
> +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
> @@ -792,8 +792,7 @@ static int vmw_driver_load(struct drm_device *dev, 
> unsigned long chipset)
>   if (unlikely(ret != 0))
>   goto out_err0;
>  
> - dma_set_max_seg_size(dev->dev, min_t(unsigned int, U32_MAX & PAGE_MASK,
> -  SCATTERLIST_MAX_SEGMENT));
> + dma_set_max_seg_size(dev->dev, U32_MAX);
>  
>   if (dev_priv->capabilities & SVGA_CAP_GMR2) {
>   DRM_INFO("Max GMR ids is %u\n",
> diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h
> index 36c47e7e66a203..6f70572b2938be 100644
> --- a/include/linux/scatterlist.h
> +++ b/include/linux/scatterlist.h
> @@ -18,12 +18,6 @@ struct scatterlist {
>  #endif
>  };
>  
> -/*
> - * Since the above length field is an unsigned int, below we define the 
> maximum
> - * length in bytes that can be stored in one scatterlist entry.
> - */
> -#define SCATTERLIST_MAX_SEGMENT (UINT_MAX & PAGE_MASK)
> -
>  /*
>   * These macros should be used after a dma_map_sg call has been done
>   * to get bus addresses of each of the SG entries and their lengths.
> diff --git a/tools/testing/scatterlist/main.c 
> b/tools/testing/scatterlist/main.c
> index b2c7e9f7b8d3dc..d264bf853034bd 100644
> --- a/tools/testing/scatterlist/main.c
> +++ b/tools/testing/scatterlist/main.c
> @@ -50,7 +50,7 @@ static void fail(struct test *test, struct sg_table *st, 
> const char *cond)
>  
>  int main(void)
>  {
> - const unsigned int sgmax = SCATTERLIST_MAX_SEGMENT;
> + const unsigned int sgmax = UINT_MAX;
>   struct test *test, tests[] = {
>   { -EINVAL, 1, pfn(0), PAGE_SIZE, PAGE_SIZE + 1, 1 },
>   { -EINVAL, 1, pfn(0), PAGE_SIZE, 0, 1 },
> -- 
> 2.28.0
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH] drm/i915/ehl: Implement W/A 22010492432

[Imre Deak]

On Wed, Oct 28, 2020 at 02:46:41PM +0530, Tejas Upadhyay wrote:
> As per W/A implemented for TGL to program half of the nominal
> DCO divider fraction value which is also applicable on EHL.
> 
> Cc: Deak Imre 
> Signed-off-by: Tejas Upadhyay 
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 12 +++-
>  1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index eaef7a2d041f..0f3208d3c083 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2636,13 +2636,15 @@ static bool cnl_ddi_hdmi_pll_dividers(struct 
> intel_crtc_state *crtc_state)
>  }
>  
>  /*
> - * Display WA #22010492432: tgl
> + * Display WA #22010492432: ehl, tgl
>   * Program half of the nominal DCO divider fraction value.
>   */
>  static bool
> -tgl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
> +combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)

The usual way is to prefix such function names with the earliest
relevant platform, so I'd use ehl_ here.

>  {
> - return IS_TIGERLAKE(i915) && i915->dpll.ref_clks.nssc == 38400;
> + return (IS_PLATFORM(i915, INTEL_ELKHARTLAKE) ||

On EHL the WA is needed only B stepping onwards.

> + IS_TIGERLAKE(i915)) &&
> + i915->dpll.ref_clks.nssc == 38400;
>  }
>  
>  static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> @@ -2696,7 +2698,7 @@ static int __cnl_ddi_wrpll_get_freq(struct 
> drm_i915_private *dev_priv,
>   dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
>  DPLL_CFGCR0_DCO_FRACTION_SHIFT;
>  
> - if (tgl_combo_pll_div_frac_wa_needed(dev_priv))
> + if (combo_pll_div_frac_wa_needed(dev_priv))
>   dco_fraction *= 2;
>  
>   dco_freq += (dco_fraction * ref_clock) / 0x8000;
> @@ -3086,7 +3088,7 @@ static void icl_calc_dpll_state(struct drm_i915_private 
> *i915,
>  
>   memset(pll_state, 0, sizeof(*pll_state));
>  
> - if (tgl_combo_pll_div_frac_wa_needed(i915))
> + if (combo_pll_div_frac_wa_needed(i915))
>   dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
>  
>   pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
> -- 
> 2.28.0
> 
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix encoder lookup during PSR atomic check

[Imre Deak]

On Wed, Oct 28, 2020 at 05:50:13AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Fix encoder lookup during PSR atomic check
> URL   : https://patchwork.freedesktop.org/series/83102/
> State : success

Thanks for the review, pushed to -dinq.

> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18787_full
> 
> 
> Summary
> ---
> 
>   **SUCCESS**
> 
>   No regressions found.
> 
>   
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_18787_full:
> 
> ### IGT changes ###
> 
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * {igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile}:
> - shard-skl:  NOTRUN -> [FAIL][1]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18787/shard-skl8/igt@kms_flip_scaled_...@flip-64bpp-ytile-to-32bpp-ytile.html
> 
>   
> 
> ### Piglit changes ###
> 
>  Possible regressions 
> 
>   * spec@glsl-4.00@execution@built-in-functions@fs-op-mult-double-dmat4 (NEW):
> - {pig-icl-1065g7}:   NOTRUN -> [INCOMPLETE][2] +3 similar issues
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18787/pig-icl-1065g7/spec@glsl-4.00@execution@built-in-functi...@fs-op-mult-double-dmat4.html
> 
>   
> New tests
> -
> 
>   New tests have been introduced between CI_DRM_9206_full and 
> Patchwork_18787_full:
> 
> ### New CI tests (1) ###
> 
>   * boot:
> - Statuses : 200 pass(s)
> - Exec time: [0.0] s
> 
>   
> 
> 
> ### New Piglit tests (4) ###
> 
>   * spec@glsl-4.00@execution@built-in-functions@fs-op-mult-dmat3x4-dmat3:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
> 
>   * spec@glsl-4.00@execution@built-in-functions@fs-op-mult-dmat4-dmat3x4:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
> 
>   * spec@glsl-4.00@execution@built-in-functions@fs-op-mult-double-dmat4:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
> 
>   * spec@glsl-4.00@execution@built-in-functions@gs-op-div-double-dmat3x4:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
> 
>   
> 
> Known issues
> 
> 
>   Here are the changes found in Patchwork_18787_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@core_hotunplug@hotrebind-lateclose:
> - shard-snb:  [PASS][3] -> [INCOMPLETE][4] ([i915#82])
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb2/igt@core_hotunp...@hotrebind-lateclose.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18787/shard-snb4/igt@core_hotunp...@hotrebind-lateclose.html
> 
>   * igt@drm_read@empty-block:
> - shard-glk:  [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk2/igt@drm_r...@empty-block.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18787/shard-glk6/igt@drm_r...@empty-block.html
> 
>   * igt@gen9_exec_parse@allowed-single:
> - shard-skl:  [PASS][7] -> [DMESG-WARN][8] ([i915#1436] / 
> [i915#716])
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl6/igt@gen9_exec_pa...@allowed-single.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18787/shard-skl7/igt@gen9_exec_pa...@allowed-single.html
> 
>   * igt@kms_big_fb@x-tiled-8bpp-rotate-0:
> - shard-apl:  [PASS][9] -> [DMESG-WARN][10] ([i915#1635] / 
> [i915#1982]) +1 similar issue
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl2/igt@kms_big...@x-tiled-8bpp-rotate-0.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18787/shard-apl7/igt@kms_big...@x-tiled-8bpp-rotate-0.html
> 
>   * igt@kms_cursor_edge_walk@pipe-b-64x64-left-edge:
> - shard-skl:  [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 
> similar issue
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@kms_cursor_edge_w...@pipe-b-64x64-left-edge.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18787/shard-skl3/igt@kms_cursor_edge_w...@pipe-b-64x64-left-edge.html
> 
>   * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
> - shard-glk:  [PASS][13] -> [FAIL][14] ([i915#2346])
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk4/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18787/shard-glk6/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html
> 
>   * igt@kms_cursor_legacy@short-flip-after-cursor-toggle:
> - shard-hsw:  [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +2 
> similar issues
>[15]: 
> 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/jsl: Disable cursor clock gating in HDR mode

[Patchwork]

== Series Details ==

Series: drm/i915/jsl: Disable cursor clock gating in HDR mode
URL   : https://patchwork.freedesktop.org/series/83142/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9209_full -> Patchwork_18797_full


Summary
---

  **SUCCESS**

  No regressions found.

  

New tests
-

  New tests have been introduced between CI_DRM_9209_full and 
Patchwork_18797_full:

### New CI tests (1) ###

  * boot:
- Statuses : 200 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18797_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_read@empty-block:
- shard-glk:  [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +1 similar 
issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/shard-glk9/igt@drm_r...@empty-block.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/shard-glk1/igt@drm_r...@empty-block.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl:  [PASS][3] -> [INCOMPLETE][4] ([i915#1635] / 
[i915#2606])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/shard-apl7/igt@gem_ctx_isolation@preservation...@rcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/shard-apl1/igt@gem_ctx_isolation@preservation...@rcs0.html

  * igt@gem_exec_create@basic:
- shard-hsw:  [PASS][5] -> [FAIL][6] ([i915#1888])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/shard-hsw2/igt@gem_exec_cre...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/shard-hsw4/igt@gem_exec_cre...@basic.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-skl:  [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +4 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/shard-skl7/igt@kms_big...@x-tiled-32bpp-rotate-180.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/shard-skl1/igt@kms_big...@x-tiled-32bpp-rotate-180.html

  * igt@kms_cursor_crc@pipe-c-cursor-alpha-transparent:
- shard-skl:  [PASS][9] -> [FAIL][10] ([i915#54])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/shard-skl10/igt@kms_cursor_...@pipe-c-cursor-alpha-transparent.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/shard-skl10/igt@kms_cursor_...@pipe-c-cursor-alpha-transparent.html

  * igt@kms_flip@2x-blocking-wf_vblank@ab-vga1-hdmi-a1:
- shard-hsw:  [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/shard-hsw4/igt@kms_flip@2x-blocking-wf_vbl...@ab-vga1-hdmi-a1.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/shard-hsw6/igt@kms_flip@2x-blocking-wf_vbl...@ab-vga1-hdmi-a1.html

  * igt@kms_flip@absolute-wf_vblank@a-dp1:
- shard-apl:  [PASS][13] -> [DMESG-WARN][14] ([i915#1635] / 
[i915#1982]) +1 similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/shard-apl2/igt@kms_flip@absolute-wf_vbl...@a-dp1.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/shard-apl4/igt@kms_flip@absolute-wf_vbl...@a-dp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
- shard-glk:  [PASS][15] -> [FAIL][16] ([i915#79])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a2.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a2.html

  * igt@kms_flip_tiling@flip-y-tiled:
- shard-kbl:  [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +2 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/shard-kbl7/igt@kms_flip_til...@flip-y-tiled.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/shard-kbl4/igt@kms_flip_til...@flip-y-tiled.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
- shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([i915#2606]) +2 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/shard-tglb6/igt@kms_frontbuffer_track...@fbcpsr-rgb101010-draw-blt.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/shard-tglb6/igt@kms_frontbuffer_track...@fbcpsr-rgb101010-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc:
- shard-skl:  [PASS][21] -> [INCOMPLETE][22] ([i915#123] / 
[i915#2606]) +5 similar issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/shard-skl3/igt@kms_frontbuffer_track...@psr-rgb565-draw-mmap-wc.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/shard-skl4/igt@kms_frontbuffer_track...@psr-rgb565-draw-mmap-wc.html
- shard-iclb: [PASS][23] -> [INCOMPLETE][24] ([i915#123] / 
[i915#2606])
   [23]: 

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/guc: Update to GuC v49

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Update to GuC v49
URL   : https://patchwork.freedesktop.org/series/83157/
State : failure

== Summary ==

Applying: drm/i915/guc: Update to use firmware v49.0.1
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/gt/intel_engine_cs.c
M   drivers/gpu/drm/i915/gt/uc/intel_guc.c
M   drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
Auto-merging drivers/gpu/drm/i915/gt/uc/intel_guc.c
Auto-merging drivers/gpu/drm/i915/gt/intel_engine_cs.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915/guc: Update to use firmware v49.0.1
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".


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[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/rkl: new rkl ddc map for different PCH

[Patchwork]

== Series Details ==

Series: drm/i915/rkl: new rkl ddc map for different PCH
URL   : https://patchwork.freedesktop.org/series/83154/
State : failure

== Summary ==

Applying: drm/i915/rkl: new rkl ddc map for different PCH
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/display/intel_bios.c
M   drivers/gpu/drm/i915/display/intel_vbt_defs.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/intel_vbt_defs.h
Auto-merging drivers/gpu/drm/i915/display/intel_bios.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_bios.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915/rkl: new rkl ddc map for different PCH
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".


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[Intel-gfx] [PATCH v3 1/3] drm/i915/guc: Update to use firmware v49.0.1

[John . C . Harrison]

From: John Harrison 

The latest GuC firmware includes a number of interface changes that
require driver updates to match.

* Starting from Gen11, the ID to be provided to GuC needs to contain
  the engine class in bits [0..2] and the instance in bits [3..6].

  NOTE: this patch breaks pointer dereferences in some existing GuC
  functions that use the guc_id to dereference arrays but these functions
  are not used for now as we have GuC submission disabled and we will
  update these functions in follow up patch which requires new IDs.

* The new GuC requires the additional data structure (ADS) and associated
  'private_data' pointer to be setup. This is basically a scratch area
  of memory that the GuC owns. The size is read from the CSS header.

* There is now a physical to logical engine mapping table in the ADS
  which needs to be configured in order for the firmware to load. For
  now, the table is initialised with a 1 to 1 mapping.

* GUC_CTL_CTXINFO has been removed from the initialization params.

* reg_state_buffer is maintained internally by the GuC as part of
  the private data.

* The ADS layout has changed significantly. This patch updates the
  shared structure and also adds better documentation of the layout.

* While i915 does not use GuC doorbells, the firmware now requires
  that some initialisation is done.

* The number of engine classes and instances supported in the ADS has
  been increased.

Signed-off-by: John Harrison 
Signed-off-by: Matthew Brost 
Signed-off-by: Daniele Ceraolo Spurio 
Signed-off-by: Oscar Mateo 
Signed-off-by: Michel Thierry 
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Michal Wajdeczko 
Cc: Michal Winiarski 
Cc: Tomasz Lis 
Cc: Joonas Lahtinen 
Reviewed-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c|   3 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc.c   |  18 ---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c   | 131 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h  |  80 +--
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h   |   5 +
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c |  27 ++--
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h |   2 +
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h |   6 +-
 8 files changed, 176 insertions(+), 96 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1579a80bc8cb..b80d7285db2f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -305,8 +305,9 @@ static int intel_engine_setup(struct intel_gt *gt, enum 
intel_engine_id id)
engine->i915 = i915;
engine->gt = gt;
engine->uncore = gt->uncore;
-   engine->hw_id = engine->guc_id = info->hw_id;
engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
+   engine->hw_id = info->hw_id;
+   engine->guc_id = MAKE_GUC_ID(info->class, info->instance);
 
engine->class = info->class;
engine->instance = info->instance;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 942c7c187adb..6909da1e1a73 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -213,23 +213,6 @@ static u32 guc_ctl_feature_flags(struct intel_guc *guc)
return flags;
 }
 
-static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
-{
-   u32 flags = 0;
-
-   if (intel_guc_submission_is_used(guc)) {
-   u32 ctxnum, base;
-
-   base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
-   ctxnum = GUC_MAX_STAGE_DESCRIPTORS / 16;
-
-   base >>= PAGE_SHIFT;
-   flags |= (base << GUC_CTL_BASE_ADDR_SHIFT) |
-   (ctxnum << GUC_CTL_CTXNUM_IN16_SHIFT);
-   }
-   return flags;
-}
-
 static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
 {
u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT;
@@ -291,7 +274,6 @@ static void guc_init_params(struct intel_guc *guc)
 
BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32));
 
-   params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index d44061033f23..7950d28beb8c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -10,11 +10,52 @@
 
 /*
  * The Additional Data Struct (ADS) has pointers for different buffers used by
- * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
- * scheduling policies (guc_policies), a structure describing a collection of
- * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
- * its internal state for 

[Intel-gfx] [PATCH v3 2/3] drm/i915/guc: Improved reporting when GuC fails to load

[John . C . Harrison]

From: John Harrison 

Rather than just saying 'GuC failed to load: -110', actually print out
the GuC status register and break it down into the individual fields.

Signed-off-by: John Harrison 
Reviewed-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 31 ---
 1 file changed, 22 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index d4a87f4c9421..f9d0907ea1a5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -76,6 +76,7 @@ static inline bool guc_ready(struct intel_uncore *uncore, u32 
*status)
 
 static int guc_wait_ucode(struct intel_uncore *uncore)
 {
+   struct drm_device *drm = >i915->drm;
u32 status;
int ret;
 
@@ -90,15 +91,27 @@ static int guc_wait_ucode(struct intel_uncore *uncore)
ret = wait_for(guc_ready(uncore, ), 100);
DRM_DEBUG_DRIVER("GuC status %#x\n", status);
 
-   if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
-   DRM_ERROR("GuC firmware signature verification failed\n");
-   ret = -ENOEXEC;
-   }
-
-   if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) {
-   DRM_ERROR("GuC firmware exception. EIP: %#x\n",
- intel_uncore_read(uncore, SOFT_SCRATCH(13)));
-   ret = -ENXIO;
+   if (ret) {
+   drm_err(drm, "GuC load failed: status = 0x%08X\n", status);
+   drm_err(drm, "GuC load failed: status: Reset = %d, "
+   "BootROM = 0x%02X, UKernel = 0x%02X, "
+   "MIA = 0x%02X, Auth = 0x%02X\n",
+   REG_FIELD_GET(GS_MIA_IN_RESET, status),
+   REG_FIELD_GET(GS_BOOTROM_MASK, status),
+   REG_FIELD_GET(GS_UKERNEL_MASK, status),
+   REG_FIELD_GET(GS_MIA_MASK, status),
+   REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
+
+   if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
+   drm_err(drm, "GuC firmware signature verification 
failed\n");
+   ret = -ENOEXEC;
+   }
+
+   if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) {
+   drm_err(drm, "GuC firmware exception. EIP: %#x\n",
+   intel_uncore_read(uncore, SOFT_SCRATCH(13)));
+   ret = -ENXIO;
+   }
}
 
return ret;
-- 
2.25.1

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[Intel-gfx] [PATCH v3 3/3] drm/i915/guc: Clear pointers on free

[John . C . Harrison]

From: John Harrison 

Clear out some pointers when objects have been de-allocated. This
makes it much easier to track down use-after-free type issues.

Signed-off-by: John Harrison 
Reviewed-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 7950d28beb8c..5212ff844292 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -220,6 +220,7 @@ int intel_guc_ads_create(struct intel_guc *guc)
 void intel_guc_ads_destroy(struct intel_guc *guc)
 {
i915_vma_unpin_and_release(>ads_vma, I915_VMA_RELEASE_MAP);
+   guc->ads_blob = NULL;
 }
 
 static void guc_ads_private_data_reset(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 11742fca0e9e..fa9e048cc65f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -210,6 +210,7 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct)
GEM_BUG_ON(ct->enabled);
 
i915_vma_unpin_and_release(>vma, I915_VMA_RELEASE_MAP);
+   memset(ct, 0, sizeof(*ct));
 }
 
 /**
-- 
2.25.1

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[Intel-gfx] [PATCH v3 0/3] drm/i915/guc: Update to GuC v49

[John . C . Harrison]

From: John Harrison 

Update to the latest GuC firmware

v2: Rebase to newer tree, updated a commit message (review feedback
from Daniele) and dropped the patch to enable GuC/HuC loading by
default as apparently this is not allowed.

v3: Rebase to drm-intel-gt-next which is apparently missing the
patch to explicitly add Jasperlake FW.

Signed-off-by: John Harrison 


John Harrison (3):
  drm/i915/guc: Update to use firmware v49.0.1
  drm/i915/guc: Improved reporting when GuC fails to load
  drm/i915/guc: Clear pointers on free

 drivers/gpu/drm/i915/gt/intel_engine_cs.c|   3 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc.c   |  18 ---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c   | 132 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c|   1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c|  31 +++--
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h  |  80 +--
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h   |   5 +
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c |  27 ++--
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h |   2 +
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h |   6 +-
 10 files changed, 200 insertions(+), 105 deletions(-)

-- 
2.25.1

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[Intel-gfx] [PATCH] drm/i915/rkl: new rkl ddc map for different PCH

[Lee Shawn C]

After boot into kernel. Driver configured ddc pin mapping based on
predefined table in parse_ddi_port(). Now driver configure rkl
ddc pin mapping depends on icp_ddc_pin_map[]. Then this table will
give incorrect gmbus port number to cause HDMI can't work.

Refer to commit d0a89527d06 ("drm/i915/rkl: Add DDC pin mapping").
Create two ddc pin table for rkl TGP and CMP pch. Then HDMI can
works properly on rkl.

Cc: Matt Roper 
Cc: Aditya Swarup 
Cc: Anusha Srivatsa 
Cc: Jani Nikula 
Cc: Cooper Chiou 
Cc: Khaled Almahallawy 
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2577
Signed-off-by: Lee Shawn C 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 22 ++-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  4 
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index a0a41ec5c341..f2c4772e4c7f 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1597,12 +1597,32 @@ static const u8 icp_ddc_pin_map[] = {
[TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
 };
 
+static const u8 rkl_pch_tgp_ddc_pin_map[] = {
+   [RKL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+   [RKL_DDC_BUS_DDI_D] = GMBUS_PIN_9_TC1_ICP,
+   [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP,
+};
+
+static const u8 rkl_pch_cmp_ddc_pin_map[] = {
+   [RKL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+   [RKL_DDC_BUS_DDI_D] = GMBUS_PIN_3_BXT,
+   [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_4_CNP,
+};
+
 static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 {
const u8 *ddc_pin_map;
int n_entries;
 
-   if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
+   if (IS_ROCKETLAKE(dev_priv)) {
+   if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP) {
+   ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
+   n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
+   } else {
+   ddc_pin_map = rkl_pch_cmp_ddc_pin_map;
+   n_entries = ARRAY_SIZE(rkl_pch_cmp_ddc_pin_map);
+   }
+   } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
ddc_pin_map = icp_ddc_pin_map;
n_entries = ARRAY_SIZE(icp_ddc_pin_map);
} else if (HAS_PCH_CNP(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 6faabd4f6d49..3418c00446c1 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -315,6 +315,10 @@ enum vbt_gmbus_ddi {
ICL_DDC_BUS_DDI_A = 0x1,
ICL_DDC_BUS_DDI_B,
TGL_DDC_BUS_DDI_C,
+   RKL_DDC_BUS_DDI_B = 0x1,
+   RKL_DDC_BUS_DDI_C,
+   RKL_DDC_BUS_DDI_D,
+   RKL_DDC_BUS_DDI_E,
ICL_DDC_BUS_PORT_1 = 0x4,
ICL_DDC_BUS_PORT_2,
ICL_DDC_BUS_PORT_3,
-- 
2.28.0

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Re: [Intel-gfx] [PATCH 10/65] drm/malidp: Annotate dma-fence critical section in commit path

[Liviu Dudau]

On Fri, Oct 23, 2020 at 02:21:21PM +0200, Daniel Vetter wrote:
> Again needs to be put right after the call to
> drm_atomic_helper_commit_hw_done(), since that's the last thing which
> can hold up a subsequent atomic commit.
> 
> No surprises here.
> 
> Signed-off-by: Daniel Vetter 
> Cc: "James (Qian) Wang" 
> Cc: Liviu Dudau 

Acked-by: Liviu Dudau 

Thanks for the patch!

Best regards,
Liviu

> Cc: Mihail Atanassov 
> ---
>  drivers/gpu/drm/arm/malidp_drv.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/arm/malidp_drv.c 
> b/drivers/gpu/drm/arm/malidp_drv.c
> index 69fee05c256c..26e60401a8e1 100644
> --- a/drivers/gpu/drm/arm/malidp_drv.c
> +++ b/drivers/gpu/drm/arm/malidp_drv.c
> @@ -234,6 +234,7 @@ static void malidp_atomic_commit_tail(struct 
> drm_atomic_state *state)
>   struct drm_crtc *crtc;
>   struct drm_crtc_state *old_crtc_state;
>   int i;
> + bool fence_cookie = dma_fence_begin_signalling();
>  
>   pm_runtime_get_sync(drm->dev);
>  
> @@ -260,6 +261,8 @@ static void malidp_atomic_commit_tail(struct 
> drm_atomic_state *state)
>  
>   malidp_atomic_commit_hw_done(state);
>  
> + dma_fence_end_signalling(fence_cookie);
> +
>   pm_runtime_put(drm->dev);
>  
>   drm_atomic_helper_cleanup_planes(drm, state);
> -- 
> 2.28.0
> 

-- 

| I would like to |
| fix the world,  |
| but they're not |
| giving me the   |
 \ source code!  /
  ---
¯\_(ツ)_/¯
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Re: [Intel-gfx] [PATCH v11 10/12] drm/i915: Link planes in a bigjoiner configuration, v3.

[Ville Syrjälä]

On Wed, Oct 28, 2020 at 01:26:27PM +0100, Maarten Lankhorst wrote:
> Op 27-10-2020 om 20:11 schreef Ville Syrjälä:
> > On Tue, Oct 27, 2020 at 11:19:16AM -0700, Navare, Manasi wrote:
> >> On Tue, Oct 27, 2020 at 03:42:30PM +0200, Ville Syrjälä wrote:
> >>> On Mon, Oct 26, 2020 at 03:41:48PM -0700, Navare, Manasi wrote:
>  On Mon, Oct 26, 2020 at 10:18:54PM +0200, Ville Syrjälä wrote:
> > On Wed, Oct 21, 2020 at 10:42:21PM -0700, Manasi Navare wrote:
> >> From: Maarten Lankhorst 
> >>
> >>  Make sure that when a plane is set in a bigjoiner mode, we will add
> >>  their counterpart to the atomic state as well. This will allow us to
> >>  make sure all state is available when planes are checked.
> >>
> >> Because of the funny interactions with bigjoiner and planar YUV
> >> formats, we may end up adding a lot of planes, so we have to keep
> >> iterating until we no longer add any planes.
> >>
> >> Also fix the atomic intel plane iterator, so things watermarks start
> >> working automagically.
> >>
> >> v6:
> >> * Fix from_plane_state assignments (Manasi)
> >> v5:
> >> * Rebase after adding sagv support (Manasi)
> >> v4:
> >> * Manual rebase (Manasi)
> >> Changes since v1:
> >> - Rebase on top of plane_state split, cleaning up the code a lot.
> >> - Make intel_atomic_crtc_state_for_each_plane_state() bigjoiner 
> >> capable.
> >> - Add iter macro to intel_atomic_crtc_state_for_each_plane_state() to
> >>   keep iteration working.
> >> Changes since v2:
> >> - Add icl_(un)set_bigjoiner_plane_links, to make it more clear where
> >>   links are made and broken.
> >>
> >> Signed-off-by: Maarten Lankhorst 
> >> Signed-off-by: Manasi Navare 
> >> ---
> >>  .../gpu/drm/i915/display/intel_atomic_plane.c |  53 -
> >>  .../gpu/drm/i915/display/intel_atomic_plane.h |   3 +-
> >>  drivers/gpu/drm/i915/display/intel_display.c  | 207 --
> >>  drivers/gpu/drm/i915/display/intel_display.h  |  20 +-
> >>  .../drm/i915/display/intel_display_types.h|  11 +
> >>  drivers/gpu/drm/i915/intel_pm.c   |  20 +-
> >>  6 files changed, 274 insertions(+), 40 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c 
> >> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >> index 3334ff253600..5df928f8f322 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >> @@ -246,12 +246,17 @@ static void intel_plane_clear_hw_state(struct 
> >> intel_plane_state *plane_state)
> >>memset(_state->hw, 0, sizeof(plane_state->hw));
> >>  }
> >>  
> >> -void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state 
> >> *plane_state,
> >> +void intel_plane_copy_uapi_to_hw_state(const struct intel_crtc_state 
> >> *crtc_state,
> >> + struct intel_plane_state 
> >> *plane_state,
> >>   const struct intel_plane_state 
> >> *from_plane_state)
> >>  {
> >>intel_plane_clear_hw_state(plane_state);
> >>  
> >> -  plane_state->hw.crtc = from_plane_state->uapi.crtc;
> >> +  if (from_plane_state->uapi.crtc)
> >> +  plane_state->hw.crtc = crtc_state->uapi.crtc;
> >> +  else
> >> +  plane_state->hw.crtc = NULL;
> >> +
> >>plane_state->hw.fb = from_plane_state->uapi.fb;
> >>if (plane_state->hw.fb)
> >>drm_framebuffer_get(plane_state->hw.fb);
> >> @@ -320,15 +325,36 @@ int intel_plane_atomic_check_with_state(const 
> >> struct intel_crtc_state *old_crtc_
> >>  }
> >>  
> >>  static struct intel_crtc *
> >> -get_crtc_from_states(const struct intel_plane_state *old_plane_state,
> >> +get_crtc_from_states(struct intel_atomic_state *state,
> >> +   const struct intel_plane_state *old_plane_state,
> >> const struct intel_plane_state *new_plane_state)
> >>  {
> >> +  struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> >> +  struct intel_plane *plane = 
> >> to_intel_plane(new_plane_state->uapi.plane);
> >> +
> >>if (new_plane_state->uapi.crtc)
> >>return to_intel_crtc(new_plane_state->uapi.crtc);
> >>  
> >>if (old_plane_state->uapi.crtc)
> >>return to_intel_crtc(old_plane_state->uapi.crtc);
> >>  
> >> +  if (new_plane_state->bigjoiner_slave) {
> >> +  const struct intel_plane_state *new_master_plane_state =
> >> +  intel_atomic_get_new_plane_state(state, 
> >> new_plane_state->bigjoiner_plane);
> >> +
> >> +  /* need to use uapi here, 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/ehl: Implement W/A 22010492432

[Patchwork]

== Series Details ==

Series: drm/i915/ehl: Implement W/A 22010492432
URL   : https://patchwork.freedesktop.org/series/83135/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9207_full -> Patchwork_18796_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_18796_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18796_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_18796_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_flip@blocking-wf_vblank@a-hdmi-a1:
- shard-hsw:  [PASS][1] -> [INCOMPLETE][2] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-hsw1/igt@kms_flip@blocking-wf_vbl...@a-hdmi-a1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/shard-hsw2/igt@kms_flip@blocking-wf_vbl...@a-hdmi-a1.html

  
 Warnings 

  * igt@gem_exec_create@basic:
- shard-hsw:  [FAIL][3] ([i915#1888]) -> [FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-hsw7/igt@gem_exec_cre...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/shard-hsw4/igt@gem_exec_cre...@basic.html

  * igt@runner@aborted:
- shard-skl:  ([FAIL][5], [FAIL][6], [FAIL][7], [FAIL][8], 
[FAIL][9], [FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14], 
[FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], 
[FAIL][21], [FAIL][22], [FAIL][23], [FAIL][24], [FAIL][25], [FAIL][26]) 
([i915#1436] / [i915#1814]) -> ([FAIL][27], [FAIL][28], [FAIL][29], [FAIL][30], 
[FAIL][31], [FAIL][32], [FAIL][33], [FAIL][34], [FAIL][35], [FAIL][36], 
[FAIL][37], [FAIL][38], [FAIL][39], [FAIL][40], [FAIL][41], [FAIL][42], 
[FAIL][43], [FAIL][44], [FAIL][45]) ([i915#1814] / [i915#2439])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl6/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl1/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl4/igt@run...@aborted.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl10/igt@run...@aborted.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl10/igt@run...@aborted.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl3/igt@run...@aborted.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl4/igt@run...@aborted.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl6/igt@run...@aborted.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl2/igt@run...@aborted.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl8/igt@run...@aborted.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl2/igt@run...@aborted.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl9/igt@run...@aborted.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl9/igt@run...@aborted.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl4/igt@run...@aborted.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl7/igt@run...@aborted.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl1/igt@run...@aborted.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl3/igt@run...@aborted.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl2/igt@run...@aborted.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl8/igt@run...@aborted.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl7/igt@run...@aborted.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl9/igt@run...@aborted.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/shard-skl3/igt@run...@aborted.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/shard-skl8/igt@run...@aborted.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/shard-skl9/igt@run...@aborted.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/shard-skl10/igt@run...@aborted.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/shard-skl10/igt@run...@aborted.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/shard-skl7/igt@run...@aborted.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/shard-skl1/igt@run...@aborted.html
   [33]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/jsl: Disable cursor clock gating in HDR mode

[Patchwork]

== Series Details ==

Series: drm/i915/jsl: Disable cursor clock gating in HDR mode
URL   : https://patchwork.freedesktop.org/series/83142/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9209 -> Patchwork_18797


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/index.html

New tests
-

  New tests have been introduced between CI_DRM_9209 and Patchwork_18797:

### New CI tests (1) ###

  * boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18797 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2:  [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_exec_create@basic:
- fi-tgl-y:   [PASS][3] -> [DMESG-WARN][4] ([i915#402])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/fi-tgl-y/igt@gem_exec_cre...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/fi-tgl-y/igt@gem_exec_cre...@basic.html

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2:  [PASS][5] -> [FAIL][6] ([i915#1888])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html

  * igt@i915_module_load@reload:
- fi-apl-guc: [PASS][7] -> [DMESG-WARN][8] ([i915#1635] / 
[i915#1982])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/fi-apl-guc/igt@i915_module_l...@reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/fi-apl-guc/igt@i915_module_l...@reload.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2:  [PASS][9] -> [FAIL][10] ([i915#1161] / [i915#262])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-kefka:   [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 
similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_psr@cursor_plane_move:
- fi-cml-u2:  [PASS][13] -> [INCOMPLETE][14] ([i915#2606])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/fi-cml-u2/igt@kms_psr@cursor_plane_move.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/fi-cml-u2/igt@kms_psr@cursor_plane_move.html

  * igt@kms_psr@primary_mmap_gtt:
- fi-cml-s:   [PASS][15] -> [INCOMPLETE][16] ([i915#2606])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/fi-cml-s/igt@kms_psr@primary_mmap_gtt.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/fi-cml-s/igt@kms_psr@primary_mmap_gtt.html

  * igt@vgem_basic@unload:
- fi-skl-guc: [PASS][17] -> [DMESG-WARN][18] ([i915#2203])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/fi-skl-guc/igt@vgem_ba...@unload.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/fi-skl-guc/igt@vgem_ba...@unload.html

  
 Possible fixes 

  * igt@debugfs_test@read_all_entries:
- {fi-kbl-7560u}: [INCOMPLETE][19] ([i915#2417]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2:  [INCOMPLETE][21] ([i915#2606]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900:   [DMESG-WARN][23] ([i915#1982]) -> [PASS][24]
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9209/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18797/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- fi-apl-guc: [DMESG-WARN][25] ([i915#1635] / [i915#1982]) -> 
[PASS][26]
   [25]: 

Re: [Intel-gfx] [PATCH v11 10/12] drm/i915: Link planes in a bigjoiner configuration, v3.

[Maarten Lankhorst]

Op 27-10-2020 om 20:11 schreef Ville Syrjälä:
> On Tue, Oct 27, 2020 at 11:19:16AM -0700, Navare, Manasi wrote:
>> On Tue, Oct 27, 2020 at 03:42:30PM +0200, Ville Syrjälä wrote:
>>> On Mon, Oct 26, 2020 at 03:41:48PM -0700, Navare, Manasi wrote:
 On Mon, Oct 26, 2020 at 10:18:54PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 21, 2020 at 10:42:21PM -0700, Manasi Navare wrote:
>> From: Maarten Lankhorst 
>>
>>  Make sure that when a plane is set in a bigjoiner mode, we will add
>>  their counterpart to the atomic state as well. This will allow us to
>>  make sure all state is available when planes are checked.
>>
>> Because of the funny interactions with bigjoiner and planar YUV
>> formats, we may end up adding a lot of planes, so we have to keep
>> iterating until we no longer add any planes.
>>
>> Also fix the atomic intel plane iterator, so things watermarks start
>> working automagically.
>>
>> v6:
>> * Fix from_plane_state assignments (Manasi)
>> v5:
>> * Rebase after adding sagv support (Manasi)
>> v4:
>> * Manual rebase (Manasi)
>> Changes since v1:
>> - Rebase on top of plane_state split, cleaning up the code a lot.
>> - Make intel_atomic_crtc_state_for_each_plane_state() bigjoiner capable.
>> - Add iter macro to intel_atomic_crtc_state_for_each_plane_state() to
>>   keep iteration working.
>> Changes since v2:
>> - Add icl_(un)set_bigjoiner_plane_links, to make it more clear where
>>   links are made and broken.
>>
>> Signed-off-by: Maarten Lankhorst 
>> Signed-off-by: Manasi Navare 
>> ---
>>  .../gpu/drm/i915/display/intel_atomic_plane.c |  53 -
>>  .../gpu/drm/i915/display/intel_atomic_plane.h |   3 +-
>>  drivers/gpu/drm/i915/display/intel_display.c  | 207 --
>>  drivers/gpu/drm/i915/display/intel_display.h  |  20 +-
>>  .../drm/i915/display/intel_display_types.h|  11 +
>>  drivers/gpu/drm/i915/intel_pm.c   |  20 +-
>>  6 files changed, 274 insertions(+), 40 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c 
>> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> index 3334ff253600..5df928f8f322 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>> @@ -246,12 +246,17 @@ static void intel_plane_clear_hw_state(struct 
>> intel_plane_state *plane_state)
>>  memset(_state->hw, 0, sizeof(plane_state->hw));
>>  }
>>  
>> -void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state 
>> *plane_state,
>> +void intel_plane_copy_uapi_to_hw_state(const struct intel_crtc_state 
>> *crtc_state,
>> +   struct intel_plane_state 
>> *plane_state,
>> const struct intel_plane_state 
>> *from_plane_state)
>>  {
>>  intel_plane_clear_hw_state(plane_state);
>>  
>> -plane_state->hw.crtc = from_plane_state->uapi.crtc;
>> +if (from_plane_state->uapi.crtc)
>> +plane_state->hw.crtc = crtc_state->uapi.crtc;
>> +else
>> +plane_state->hw.crtc = NULL;
>> +
>>  plane_state->hw.fb = from_plane_state->uapi.fb;
>>  if (plane_state->hw.fb)
>>  drm_framebuffer_get(plane_state->hw.fb);
>> @@ -320,15 +325,36 @@ int intel_plane_atomic_check_with_state(const 
>> struct intel_crtc_state *old_crtc_
>>  }
>>  
>>  static struct intel_crtc *
>> -get_crtc_from_states(const struct intel_plane_state *old_plane_state,
>> +get_crtc_from_states(struct intel_atomic_state *state,
>> + const struct intel_plane_state *old_plane_state,
>>   const struct intel_plane_state *new_plane_state)
>>  {
>> +struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>> +struct intel_plane *plane = 
>> to_intel_plane(new_plane_state->uapi.plane);
>> +
>>  if (new_plane_state->uapi.crtc)
>>  return to_intel_crtc(new_plane_state->uapi.crtc);
>>  
>>  if (old_plane_state->uapi.crtc)
>>  return to_intel_crtc(old_plane_state->uapi.crtc);
>>  
>> +if (new_plane_state->bigjoiner_slave) {
>> +const struct intel_plane_state *new_master_plane_state =
>> +intel_atomic_get_new_plane_state(state, 
>> new_plane_state->bigjoiner_plane);
>> +
>> +/* need to use uapi here, new_master_plane_state might 
>> not be copied to hw yet */
>> +if (new_master_plane_state->uapi.crtc)
>> +return intel_get_crtc_for_pipe(dev_priv, 
>> plane->pipe);
>> +}

Re: [Intel-gfx] [PATCH] drm/i915/jsl: Disable cursor clock gating in HDR mode

[Chris Wilson]

Quoting Tejas Upadhyay (2020-10-28 11:17:31)
> Display underrun in HDR mode when cursor is enabled.
> RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
> As per W/A 1604331009, Disable cursor clock gating in HDR mode.
> 
> Bspec : 33451
> 
> Cc: Souza Jose 
> Signed-off-by: Tejas Upadhyay 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 32 
>  drivers/gpu/drm/i915/i915_reg.h  |  5 +++
>  2 files changed, 37 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f41b6f8b5618..73c4a43e6e31 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -541,6 +541,19 @@ icl_wa_scalerclkgating(struct drm_i915_private 
> *dev_priv, enum pipe pipe,
>intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) 
> & ~DPFR_GATING_DIS);
>  }
>  
> +/* Wa_1604331009:jsl */
> +static void
> +jsl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
> +  bool enable)
> +{
> +   if (enable)
> +   intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
> +  intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) 
> | CURSOR_GATING_DIS);
> +   else
> +   intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
> +  intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) 
> & ~CURSOR_GATING_DIS);

intel_de_rmw(i915, CLKGATE_DIS_PSL(pipe),
CURSOR_GATING_DIS, enable ? CURSOR_GATING_DIS : 0);
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/ehl: Remove require_force_probe protection

[Pandey, Hariom]

Ok, I have initiated the steps to upgrade the CI machine's silicon & BIOS.

Thanks
Hariom Pandey

> -Original Message-
> From: Vivi, Rodrigo 
> Sent: Wednesday, October 28, 2020 5:24 PM
> To: Pandey, Hariom ; Szwichtenberg, Radoslaw
> 
> Cc: Chris Wilson ; Ausmus, James
> ; Nikula, Jani ; intel-
> g...@lists.freedesktop.org; Souza, Jose ; dri-devel
> ; Surendrakumar Upadhyay, TejaskumarX
> ; K, SrinivasX
> ; Meena, Mahesh 
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/ehl: Remove require_force_probe
> protection
> 
> 
> 
> > On Oct 27, 2020, at 11:49 PM, Pandey, Hariom
>  wrote:
> >
> > Hi Chris,
> >
> > Awaiting your kind response here…
> 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9208/fi-ehl-
> 1/igt@i915_selftest@live@gt_pm.html
> "Did not enter RC6!"
> 
> Chris already told that we need to get RC6 working on CI.
> If we need BIOS update or machine replacement there we need to work with
> CI team to make that happen.
> 
> >
> > Thanks
> > Hariom Pandey
> >
> > From: Pandey, Hariom
> > Sent: Tuesday, October 20, 2020 9:28 PM
> > To: Chris Wilson 
> > Cc: Ausmus, James ; Nikula, Jani
> > ; intel-gfx@  > intel-gfx@lists.freedesktop.org>; Souza, Jose ;
> > dri-devel@ ;
> > Surendrakumar Upadhyay, TejaskumarX
> > ; K, SrinivasX
> > ; Vivi, Rodrigo ;
> > Meena, Mahesh 
> > Subject: RE: [Intel-gfx] [PATCH] drm/i915/ehl: Remove
> > require_force_probe protection
> >
> > Hi Chris,
> >
> > We have run RC6 test cases as recently as 4 days ago on EHL and they have
> passed. Below are the pass log links & attached email has the DRM/IGT tag
> where they have passed. We are finding that the “EHL BAT setup” is not upto
> date in terms of Silicon & BIOS which we are working to upgrade. But just for
> that, should we block this patch? Just trying to understand as there is no
> inherent or latent RC6 issue anymore.
> >
> > • igt@i915_pm_rc6_residency@rc6-accuracy --- PASS - Log •
> > igt@i915_pm_rc6_residency@rc6-fence --- PASS – Log •
> > igt@i915_pm_rc6_residency@rc6-idle --- PASS - Log •
> > igt@perf@rc6-disable --- PASS - Log • igt@perf_pmu@rc6 --- PASS - Log
> > • igt@perf_pmu@rc6-runtime-pm --- PASS - Log •
> > igt@perf_pmu@rc6-runtime-pm-long --- PASS – Log
> >
> >
> > Thanks
> > Hariom Pandey
> >
> > > -Original Message-
> > > From: Chris Wilson 
> > > Sent: Tuesday, October 20, 2020 12:04 AM
> > > To: K, SrinivasX ; Vivi, Rodrigo
> > > 
> > > Cc: Pandey, Hariom ; Ausmus, James
> > > ; Nikula, Jani ;
> > > intel-gfx@ ;
> > > Souza, Jose ; dri-devel@
> > > ;
> > > Surendrakumar Upadhyay, TejaskumarX
> > > 
> > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/ehl: Remove
> > > require_force_probe protection
> > >
> > > Quoting Rodrigo Vivi (2020-10-19 19:29:36)
> > > >
> > > > I just checked the CI picture and it looks much better indeed.
> > > >
> > > > Only bad case being the gt_pm, which is also failing on other platforms.
> > >
> > > Not nearly in the same manner. CI is indicating that there is no RC6
> > > entry and no power saving at all; neither in the selftests nor visible 
> > > from
> userspace.
> > > That is a critical battery eating bug.
> > >
> > > If there's a patch to fix it for ehl and jsl, send it to CI for proving.
> > > -Chris
> > 
> 

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Re: [Intel-gfx] [PATCH] drm/i915/ehl: Remove require_force_probe protection

[Vivi, Rodrigo]

> On Oct 27, 2020, at 11:49 PM, Pandey, Hariom  wrote:
> 
> Hi Chris,
>  
> Awaiting your kind response here…

https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9208/fi-ehl-1/igt@i915_selftest@live@gt_pm.html
"Did not enter RC6!"

Chris already told that we need to get RC6 working on CI.
If we need BIOS update or machine replacement there we need to work with CI 
team to make that happen.

>  
> Thanks
> Hariom Pandey
>  
> From: Pandey, Hariom 
> Sent: Tuesday, October 20, 2020 9:28 PM
> To: Chris Wilson 
> Cc: Ausmus, James ; Nikula, Jani 
> ; intel-gfx@  intel-gfx@lists.freedesktop.org>; Souza, Jose ; 
> dri-devel@ ; 
> Surendrakumar Upadhyay, TejaskumarX 
> ; K, SrinivasX 
> ; Vivi, Rodrigo ; Meena, 
> Mahesh 
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/ehl: Remove require_force_probe 
> protection
>  
> Hi Chris,
>  
> We have run RC6 test cases as recently as 4 days ago on EHL and they have 
> passed. Below are the pass log links & attached email has the DRM/IGT tag 
> where they have passed. We are finding that the “EHL BAT setup” is not upto 
> date in terms of Silicon & BIOS which we are working to upgrade. But just for 
> that, should we block this patch? Just trying to understand as there is no 
> inherent or latent RC6 issue anymore.
>  
>   • igt@i915_pm_rc6_residency@rc6-accuracy --- PASS - Log
>   • igt@i915_pm_rc6_residency@rc6-fence --- PASS – Log
>   • igt@i915_pm_rc6_residency@rc6-idle --- PASS - Log
>   • igt@perf@rc6-disable --- PASS - Log
>   • igt@perf_pmu@rc6 --- PASS - Log
>   • igt@perf_pmu@rc6-runtime-pm --- PASS - Log
>   • igt@perf_pmu@rc6-runtime-pm-long --- PASS – Log
>  
>  
> Thanks
> Hariom Pandey
>  
> > -Original Message-
> > From: Chris Wilson 
> > Sent: Tuesday, October 20, 2020 12:04 AM
> > To: K, SrinivasX ; Vivi, Rodrigo
> > 
> > Cc: Pandey, Hariom ; Ausmus, James
> > ; Nikula, Jani ; intel-gfx@
> > ; Souza, Jose
> > ; dri-devel@  > de...@lists.freedesktop.org>; Surendrakumar Upadhyay, TejaskumarX
> > 
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/ehl: Remove require_force_probe
> > protection
> > 
> > Quoting Rodrigo Vivi (2020-10-19 19:29:36)
> > >
> > > I just checked the CI picture and it looks much better indeed.
> > >
> > > Only bad case being the gt_pm, which is also failing on other platforms.
> > 
> > Not nearly in the same manner. CI is indicating that there is no RC6 entry 
> > and
> > no power saving at all; neither in the selftests nor visible from userspace.
> > That is a critical battery eating bug.
> > 
> > If there's a patch to fix it for ehl and jsl, send it to CI for proving.
> > -Chris
> 

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[Intel-gfx] [PATCH] drm/i915/jsl: Disable cursor clock gating in HDR mode

[Tejas Upadhyay]

Display underrun in HDR mode when cursor is enabled.
RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
As per W/A 1604331009, Disable cursor clock gating in HDR mode.

Bspec : 33451

Cc: Souza Jose 
Signed-off-by: Tejas Upadhyay 
---
 drivers/gpu/drm/i915/display/intel_display.c | 32 
 drivers/gpu/drm/i915/i915_reg.h  |  5 +++
 2 files changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index f41b6f8b5618..73c4a43e6e31 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -541,6 +541,19 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, 
enum pipe pipe,
   intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & 
~DPFR_GATING_DIS);
 }
 
+/* Wa_1604331009:jsl */
+static void
+jsl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
+  bool enable)
+{
+   if (enable)
+   intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
+  intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | 
CURSOR_GATING_DIS);
+   else
+   intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
+  intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & 
~CURSOR_GATING_DIS);
+}
+
 static bool
 needs_modeset(const struct intel_crtc_state *state)
 {
@@ -6637,6 +6650,16 @@ static bool needs_scalerclk_wa(const struct 
intel_crtc_state *crtc_state)
return false;
 }
 
+static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
+{
+   struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+   /* Wa_1604331009:jsl */
+   if (crtc_state->active_planes & icl_hdr_plane_mask() &&
+   IS_GEN(dev_priv, 11))
+   return true;
+   return false;
+}
+
 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
 {
@@ -6678,6 +6701,10 @@ static void intel_post_plane_update(struct 
intel_atomic_state *state,
if (needs_scalerclk_wa(old_crtc_state) &&
!needs_scalerclk_wa(new_crtc_state))
icl_wa_scalerclkgating(dev_priv, pipe, false);
+
+   if (needs_cursorclk_wa(old_crtc_state) &&
+   !needs_cursorclk_wa(new_crtc_state))
+   jsl_wa_cursorclkgating(dev_priv, pipe, false);
 }
 
 static void skl_disable_async_flip_wa(struct intel_atomic_state *state,
@@ -6743,6 +6770,11 @@ static void intel_pre_plane_update(struct 
intel_atomic_state *state,
needs_scalerclk_wa(new_crtc_state))
icl_wa_scalerclkgating(dev_priv, pipe, true);
 
+   /* Wa_1604331009:jsl */
+   if (!needs_cursorclk_wa(old_crtc_state) &&
+   needs_cursorclk_wa(new_crtc_state))
+   jsl_wa_cursorclkgating(dev_priv, pipe, true);
+
/*
 * Vblank time updates from the shadow to live plane control register
 * are blocked if the memory self-refresh mode is active at that
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b021f77cb1f..0434cab4bebb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4194,6 +4194,11 @@ enum {
 #define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
 #define   CGPSF_CLKGATE_DIS(1 << 3)
 
+/*
+ * GEN11 clock gating regs
+ */
+#define   CURSOR_GATING_DISBIT(28)
+
 /*
  * Display engine regs
  */
-- 
2.28.0

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Re: [Intel-gfx] [PULL] gvt-fixes

[Vivi, Rodrigo]

On Oct 27, 2020, at 1:46 PM, Rodrigo Vivi 
mailto:rodrigo.v...@intel.com>> wrote:

On Tue, Oct 27, 2020 at 11:17:40AM +0800, Zhenyu Wang wrote:

Hi,

Here's first gvt fixes for 5.10 which includes more vGPU
suspend/resume fix in HWSP reset handling, and also fix for host i915
suspend regression when vGPU is created (not need to be active), and
one workaround for APL guest hang issue.

pulled to drm-intel-fixes

I'm actually pulling it off. I had bypassed dim, considering this was an old 
issue with our email decoder,
but it happens that

$ git show 401ccfa87856 | grep Fixes
Fixes: e6ba76480299 (drm/i915: Remove i915->kernel_context)

And this is what it should have:

$ dim fixes e6ba76480299 | grep Fixes
Fixes: e6ba76480299 ("drm/i915: Remove i915->kernel_context")

Sorry for the trouble.
Let's fix this in place so we don't propagate bad tag that might break other 
scripts on the way

Sorry,
Rodrigo.

thanks


Thanks
--
The following changes since commit 16cce04cdb200ba905d1241b425ac48da5a9ace5:

 drm/i915/selftests: Push the fake iommu device from the stack to data 
(2020-09-23 10:15:46 +0300)

are available in the Git repository at:

 https://github.com/intel/gvt-linux tags/gvt-fixes-2020-10-27

for you to fetch changes up to 401ccfa87856656b874c737522ea92721394a348:

 drm/i915/gvt: Only pin/unpin intel_context along with workload (2020-10-19 
16:54:28 +0800)


gvt-fixes-2020-10-27

- Fix HWSP reset handling during vGPU suspend/resume (Colin)
- Apply flush workaround on APL now for possible guest hang (Colin)
- Fix vGPU context pin/unpin also for host suspend regression with
 vGPU created (Colin)


Colin Xu (3):
 drm/i915/gvt: Allow zero out HWSP addr on hws_pga_write
 drm/i915/gvt: Set SNOOP for PAT3 on BXT/APL to workaround GPU BB hang
 drm/i915/gvt: Only pin/unpin intel_context along with workload

drivers/gpu/drm/i915/gvt/handlers.c  | 35 +--
drivers/gpu/drm/i915/gvt/scheduler.c | 15 ---
2 files changed, 41 insertions(+), 9 deletions(-)


--

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827


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Re: [Intel-gfx] [PATCH 03/65] mm: Track mmu notifiers in fs_reclaim_acquire/release

[Christoph Hellwig]

Is there a list that has the cover letter and the whole series?
I've only found fragments (and mostly the same fragments) while
wading through my backlog in various list folders..
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ehl: Implement W/A 22010492432

[Patchwork]

== Series Details ==

Series: drm/i915/ehl: Implement W/A 22010492432
URL   : https://patchwork.freedesktop.org/series/83135/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9207 -> Patchwork_18796


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/index.html

New tests
-

  New tests have been introduced between CI_DRM_9207 and Patchwork_18796:

### New CI tests (1) ###

  * boot:
- Statuses : 39 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18796 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900:   [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/fi-byt-j1900/igt@i915_pm_...@basic-pci-d3-state.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/fi-byt-j1900/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2:  [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@vgem_basic@dmabuf-fence:
- fi-tgl-y:   [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar 
issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/fi-tgl-y/igt@vgem_ba...@dmabuf-fence.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/fi-tgl-y/igt@vgem_ba...@dmabuf-fence.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2:  [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html

  * igt@debugfs_test@read_all_entries:
- {fi-kbl-7560u}: [INCOMPLETE][9] ([i915#2417]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html

  * igt@i915_module_load@reload:
- {fi-tgl-dsi}:   [DMESG-WARN][11] ([i915#1982] / [k.org#205379]) -> 
[PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/fi-tgl-dsi/igt@i915_module_l...@reload.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/fi-tgl-dsi/igt@i915_module_l...@reload.html
- fi-tgl-u2:  [DMESG-WARN][13] ([i915#1982] / [k.org#205379]) -> 
[PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/fi-tgl-u2/igt@i915_module_l...@reload.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/fi-tgl-u2/igt@i915_module_l...@reload.html
- fi-icl-y:   [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/fi-icl-y/igt@i915_module_l...@reload.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/fi-icl-y/igt@i915_module_l...@reload.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka:   [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka:  [DMESG-FAIL][19] ([i915#541]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_busy@basic@flip:
- fi-kbl-soraka:  [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/fi-kbl-soraka/igt@kms_busy@ba...@flip.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u:   [INCOMPLETE][23] ([i915#2606]) -> [PASS][24]
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9207/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18796/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- {fi-tgl-dsi}:   [DMESG-WARN][25] ([i915#1982]) -> [PASS][26] +2 
similar issues
   [25]: 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg1: Fix unbalanced braces

[Patchwork]

== Series Details ==

Series: drm/i915/dg1: Fix unbalanced braces
URL   : https://patchwork.freedesktop.org/series/83120/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18794_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_18794_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile}:
- shard-skl:  NOTRUN -> [FAIL][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/shard-skl2/igt@kms_flip_scaled_...@flip-64bpp-ytile-to-32bpp-ytile.html

  
New tests
-

  New tests have been introduced between CI_DRM_9206_full and 
Patchwork_18794_full:

### New CI tests (1) ###

  * boot:
- Statuses : 200 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18794_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl:  [PASS][2] -> [DMESG-WARN][3] ([i915#180]) +1 similar 
issue
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@gem_ctx_isolation@preservation...@vcs0.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html

  * igt@kms_cursor_edge_walk@pipe-b-64x64-left-edge:
- shard-skl:  [PASS][4] -> [DMESG-WARN][5] ([i915#1982])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl1/igt@kms_cursor_edge_w...@pipe-b-64x64-left-edge.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/shard-skl7/igt@kms_cursor_edge_w...@pipe-b-64x64-left-edge.html

  * igt@kms_flip@flip-vs-suspend@b-vga1:
- shard-snb:  [PASS][6] -> [DMESG-WARN][7] ([i915#42])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb6/igt@kms_flip@flip-vs-susp...@b-vga1.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/shard-snb7/igt@kms_flip@flip-vs-susp...@b-vga1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
- shard-tglb: [PASS][8] -> [INCOMPLETE][9] ([i915#2606]) +2 similar 
issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@kms_frontbuffer_track...@fbc-1p-indfb-fliptrack.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/shard-tglb3/igt@kms_frontbuffer_track...@fbc-1p-indfb-fliptrack.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-kbl:  [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +3 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/shard-kbl7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-glk:  [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) +1 
similar issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk9/igt@kms_frontbuffer_track...@fbc-suspend.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/shard-glk3/igt@kms_frontbuffer_track...@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt:
- shard-skl:  [PASS][14] -> [INCOMPLETE][15] ([i915#123]) +2 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl10/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-indfb-draw-blt.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/shard-skl6/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc:
- shard-skl:  [PASS][16] -> [INCOMPLETE][17] ([i915#123] / 
[i915#2606])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@kms_frontbuffer_track...@psr-rgb565-draw-mmap-wc.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/shard-skl2/igt@kms_frontbuffer_track...@psr-rgb565-draw-mmap-wc.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl:  [PASS][18] -> [DMESG-FAIL][19] ([fdo#108145] / 
[i915#1982])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl6/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/shard-skl3/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html

  * igt@kms_psr@sprite_plane_onoff:
- shard-iclb: [PASS][20] -> [INCOMPLETE][21] ([i915#2606]) +1 
similar issue
   [20]: 

[Intel-gfx] [PATCH] drm/i915/ehl: Implement W/A 22010492432

[Tejas Upadhyay]

As per W/A implemented for TGL to program half of the nominal
DCO divider fraction value which is also applicable on EHL.

Cc: Deak Imre 
Signed-off-by: Tejas Upadhyay 
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index eaef7a2d041f..0f3208d3c083 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2636,13 +2636,15 @@ static bool cnl_ddi_hdmi_pll_dividers(struct 
intel_crtc_state *crtc_state)
 }
 
 /*
- * Display WA #22010492432: tgl
+ * Display WA #22010492432: ehl, tgl
  * Program half of the nominal DCO divider fraction value.
  */
 static bool
-tgl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
+combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
 {
-   return IS_TIGERLAKE(i915) && i915->dpll.ref_clks.nssc == 38400;
+   return (IS_PLATFORM(i915, INTEL_ELKHARTLAKE) ||
+   IS_TIGERLAKE(i915)) &&
+   i915->dpll.ref_clks.nssc == 38400;
 }
 
 static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
@@ -2696,7 +2698,7 @@ static int __cnl_ddi_wrpll_get_freq(struct 
drm_i915_private *dev_priv,
dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
   DPLL_CFGCR0_DCO_FRACTION_SHIFT;
 
-   if (tgl_combo_pll_div_frac_wa_needed(dev_priv))
+   if (combo_pll_div_frac_wa_needed(dev_priv))
dco_fraction *= 2;
 
dco_freq += (dco_fraction * ref_clock) / 0x8000;
@@ -3086,7 +3088,7 @@ static void icl_calc_dpll_state(struct drm_i915_private 
*i915,
 
memset(pll_state, 0, sizeof(*pll_state));
 
-   if (tgl_combo_pll_div_frac_wa_needed(i915))
+   if (combo_pll_div_frac_wa_needed(i915))
dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
 
pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
-- 
2.28.0

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Re: [Intel-gfx] drm/i915: Acquire connector reference before prop_work

[K, SrinivasX]

++Tejas

-Original Message-
From: Anshuman Gupta  
Sent: 28 October 2020 14:35
To: K, SrinivasX 
Cc: intel-gfx@lists.freedesktop.org; seanp...@chromium.org; Pandey, Hariom 

Subject: Re: [Intel-gfx] drm/i915: Acquire connector reference before prop_work

On 2020-10-27 at 16:03:35 +0530, Kamati Srinivas wrote:
> From: Srinivas Kamati 
> 
> "Content protection type change" igt test results in kernel taint. 
> Everytime after prop_work is done we are also giving up connector 
> reference, which is resulting in ref count underrun.
> 
> Before scheduling prop_work acquire connector reference.
I has been alreayd taken care at
https://patchwork.freedesktop.org/patch/397215/?series=82998=2
> 
> Cc: Sean Paul 
> Cc: Ramalingam C 
> Signed-off-by: Srinivas Kamati 
> ---
>  drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c 
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index b2a4bbcfdcd2..beedd672b21e 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2210,6 +2210,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state 
> *state,
>   if (content_protection_type_changed) {
>   mutex_lock(>mutex);
>   hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
> + drm_connector_get(>base);
>   schedule_work(>prop_work);
>   mutex_unlock(>mutex);
>   }
> --
> 2.25.1
> 
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Re: [Intel-gfx] drm/i915: Acquire connector reference before prop_work

[Anshuman Gupta]

On 2020-10-27 at 16:03:35 +0530, Kamati Srinivas wrote:
> From: Srinivas Kamati 
> 
> "Content protection type change" igt test results in kernel
> taint. Everytime after prop_work is done we are also
> giving up connector reference, which is resulting in ref
> count underrun.
> 
> Before scheduling prop_work acquire connector reference.
I has been alreayd taken care at 
https://patchwork.freedesktop.org/patch/397215/?series=82998=2
> 
> Cc: Sean Paul 
> Cc: Ramalingam C 
> Signed-off-by: Srinivas Kamati 
> ---
>  drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c 
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index b2a4bbcfdcd2..beedd672b21e 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2210,6 +2210,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state 
> *state,
>   if (content_protection_type_changed) {
>   mutex_lock(>mutex);
>   hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
> + drm_connector_get(>base);
>   schedule_work(>prop_work);
>   mutex_unlock(>mutex);
>   }
> -- 
> 2.25.1
> 
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Re: [Intel-gfx] [PATCH] drm/i915: Fix encoder lookup during PSR atomic check

[Anshuman Gupta]

On 2020-10-27 at 21:39:28 +0530, Imre Deak wrote:
> The atomic check hooks must look up the encoder to be used with a
> connector from the connector's atomic state, and not assume that it's
> the connector's current attached encoder. The latter one can change
> under the atomic check func, or can be unset yet as in the case of MST
> connectors.
I have also observed the similar crash while using DP-MST setup.
Looks good to me.
Reviewed-by: Anshuman Gupta 
> 
> This fixes
> [7.940719] Oops:  [#1] SMP NOPTI
> [7.944407] CPU: 2 PID: 143 Comm: kworker/2:2 Not tainted 5.6.0-1023-oem 
> #23-Ubuntu
> [7.952102] Hardware name: Dell Inc. Latitude 7320/, BIOS 88.87.11 
> 09/07/2020
> [7.959278] Workqueue: events output_poll_execute [drm_kms_helper]
> [7.965511] RIP: 0010:intel_psr_atomic_check+0x37/0xa0 [i915]
> [7.971327] Code: 80 2d 06 00 00 20 74 42 80 b8 34 71 00 00 00 74 39 48 8b 
> 72 08 48 85 f6 74 30 80 b8 f8 71 00 00 00 74 27 4c 8b 87 80 04 00 00 <41> 8b 
> 78 78 83 ff 08 77 19 31 c9 83 ff 05 77 19 48 81 c1 20 01 00
> [7.977541] input: PS/2 Generic Mouse as 
> /devices/platform/i8042/serio1/input/input5
> [7.990154] RSP: 0018:b864c073fac8 EFLAGS: 00010202
> [7.990155] RAX: 8c5d55ce RBX: 8c5d54519000 RCX: 
> 
> [7.990155] RDX: 8c5d55cb30c0 RSI: 8c5d89a0c800 RDI: 
> 8c5d55fcf800
> [7.990156] RBP: b864c073fac8 R08:  R09: 
> 8c5d55d9f3a0
> [7.990156] R10: 8c5d55cb30c0 R11: 0009 R12: 
> 8c5d55fcf800
> [7.990156] R13: 8c5d55cb30c0 R14: 8c5d56989cc0 R15: 
> 8c5d56989cc0
> [7.990158] FS:  () GS:8c5d8e48() 
> knlGS:
> [8.047193] CS:  0010 DS:  ES:  CR0: 80050033
> [8.052970] CR2: 0078 CR3: 00085655 CR4: 
> 00760ee0
> [8.060137] PKRU: 5554
> [8.062867] Call Trace:
> [8.065361]  intel_digital_connector_atomic_check+0x53/0x130 [i915]
> [8.071703]  intel_dp_mst_atomic_check+0x5b/0x200 [i915]
> [8.077074]  drm_atomic_helper_check_modeset+0x1db/0x790 [drm_kms_helper]
> [8.083942]  intel_atomic_check+0x92/0xc50 [i915]
> [8.088705]  ? drm_plane_check_pixel_format+0x4f/0xb0 [drm]
> [8.094345]  ? drm_atomic_plane_check+0x7a/0x3a0 [drm]
> [8.099548]  drm_atomic_check_only+0x2b1/0x450 [drm]
> [8.104573]  drm_atomic_commit+0x18/0x50 [drm]
> [8.109070]  drm_client_modeset_commit_atomic+0x1c9/0x200 [drm]
> [8.115056]  drm_client_modeset_commit_force+0x55/0x160 [drm]
> [8.120866]  drm_fb_helper_restore_fbdev_mode_unlocked+0x54/0xb0 
> [drm_kms_helper]
> [8.128415]  drm_fb_helper_set_par+0x34/0x50 [drm_kms_helper]
> [8.134225]  drm_fb_helper_hotplug_event.part.0+0xb4/0xe0 [drm_kms_helper]
> [8.141150]  drm_fb_helper_hotplug_event+0x1c/0x30 [drm_kms_helper]
> [8.147481]  intel_fbdev_output_poll_changed+0x6f/0xa0 [i915]
> [8.153287]  drm_kms_helper_hotplug_event+0x2c/0x40 [drm_kms_helper]
> [8.159709]  output_poll_execute+0x1aa/0x1c0 [drm_kms_helper]
> [8.165506]  process_one_work+0x1e8/0x3b0
> [8.169561]  worker_thread+0x4d/0x400
> [8.173249]  kthread+0x104/0x140
> [8.176515]  ? process_one_work+0x3b0/0x3b0
> [8.180726]  ? kthread_park+0x90/0x90
> [8.184416]  ret_from_fork+0x1f/0x40
> 
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2361
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/2486
> Reported-by: William Tseng 
> Reported-by: Cooper Chiou 
> Cc: 
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b2544102e7b1..1576c3722d0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1884,7 +1884,7 @@ void intel_psr_atomic_check(struct drm_connector 
> *connector,
>   return;
>  
>   intel_connector = to_intel_connector(connector);
> - dig_port = enc_to_dig_port(intel_attached_encoder(intel_connector));
> + dig_port = enc_to_dig_port(to_intel_encoder(new_state->best_encoder));
>   if (dev_priv->psr.dp != _port->dp)
>   return;
>  
> -- 
> 2.25.1
> 
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Remainder of dbuf state stuff

[Patchwork]

== Series Details ==

Series: drm/i915: Remainder of dbuf state stuff
URL   : https://patchwork.freedesktop.org/series/83114/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18791_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_18791_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18791_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_18791_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rpm@gem-mmap-type@uc:
- shard-glk:  [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk9/igt@i915_pm_rpm@gem-mmap-t...@uc.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18791/shard-glk8/igt@i915_pm_rpm@gem-mmap-t...@uc.html

  * igt@kms_psr@sprite_blt:
- shard-skl:  NOTRUN -> [INCOMPLETE][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18791/shard-skl2/igt@kms_psr@sprite_blt.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-glk:  [PASS][4] -> [INCOMPLETE][5] +1 similar issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk5/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18791/shard-glk8/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html

  
 Warnings 

  * igt@kms_psr@psr2_dpms:
- shard-iclb: [SKIP][6] ([fdo#109441]) -> [INCOMPLETE][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-iclb7/igt@kms_psr@psr2_dpms.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18791/shard-iclb2/igt@kms_psr@psr2_dpms.html

  
New tests
-

  New tests have been introduced between CI_DRM_9206_full and 
Patchwork_18791_full:

### New CI tests (1) ###

  * boot:
- Statuses : 174 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18791_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_read@empty-block:
- shard-glk:  [PASS][8] -> [DMESG-WARN][9] ([i915#1982])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk2/igt@drm_r...@empty-block.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18791/shard-glk9/igt@drm_r...@empty-block.html

  * igt@gem_exec_schedule@timeslicing@vecs0:
- shard-skl:  [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +2 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@gem_exec_schedule@timeslic...@vecs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18791/shard-skl3/igt@gem_exec_schedule@timeslic...@vecs0.html

  * igt@gem_exec_whisper@basic-fds-forked-all:
- shard-glk:  [PASS][12] -> [DMESG-WARN][13] ([i915#118] / 
[i915#95])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk4/igt@gem_exec_whis...@basic-fds-forked-all.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18791/shard-glk1/igt@gem_exec_whis...@basic-fds-forked-all.html

  * igt@gen9_exec_parse@allowed-single:
- shard-skl:  [PASS][14] -> [DMESG-WARN][15] ([i915#1436] / 
[i915#716])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl6/igt@gen9_exec_pa...@allowed-single.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18791/shard-skl7/igt@gen9_exec_pa...@allowed-single.html

  * igt@kms_flip@absolute-wf_vblank@a-dp1:
- shard-apl:  [PASS][16] -> [DMESG-WARN][17] ([i915#1635] / 
[i915#1982]) +1 similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl2/igt@kms_flip@absolute-wf_vbl...@a-dp1.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18791/shard-apl7/igt@kms_flip@absolute-wf_vbl...@a-dp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-kbl:  [PASS][18] -> [DMESG-WARN][19] ([i915#180])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-kbl1/igt@kms_flip@flip-vs-suspend-interrupti...@b-dp1.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18791/shard-kbl4/igt@kms_flip@flip-vs-suspend-interrupti...@b-dp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
- shard-tglb: [PASS][20] -> [INCOMPLETE][21] ([i915#2606]) +2 
similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@kms_frontbuffer_track...@fbc-1p-indfb-fliptrack.html
   [21]: 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Guard debugfs against invalid access without display

[Lucas De Marchi]

On Wed, Oct 28, 2020 at 03:17:45AM +, Patchwork wrote:

== Series Details ==

Series: series starting with [1/3] drm/i915: Guard debugfs against invalid 
access without display
URL   : https://patchwork.freedesktop.org/series/83070/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18782_full


Summary
---

 **FAILURE**

 Serious unknown changes coming with Patchwork_18782_full absolutely need to be
 verified manually.

 If you think the reported changes have nothing to do with the changes
 introduced in Patchwork_18782_full, please notify your bug team to allow them
 to document this new failure mode, which will reduce false positives in CI.



Possible new issues
---

 Here are the unknown changes that may have been introduced in 
Patchwork_18782_full:

### IGT changes ###

 Possible regressions 

 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render:
   - shard-skl:  [PASS][1] -> [DMESG-WARN][2]
  [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl10/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-draw-render.html
  [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl3/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-draw-render.html


same signature as recent runs on skl, e.g.
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9202/shard-skl8/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-draw-render.html#dmesg-warnings518

Lucas De Marchi




 Suppressed 

 The following results come from untrusted machines, tests, or statuses.
 They do not affect the overall result.

 * {igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile}:
   - shard-skl:  NOTRUN -> [FAIL][3]
  [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-skl10/igt@kms_flip_scaled_...@flip-64bpp-ytile-to-32bpp-ytile.html


New tests
-

 New tests have been introduced between CI_DRM_9206_full and 
Patchwork_18782_full:

### New CI tests (1) ###

 * boot:
   - Statuses : 175 pass(s)
   - Exec time: [0.0] s



Known issues


 Here are the changes found in Patchwork_18782_full that come from known issues:

### IGT changes ###

 Issues hit 

 * igt@drm_read@empty-block:
   - shard-glk:  [PASS][4] -> [DMESG-WARN][5] ([i915#1982])
  [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk2/igt@drm_r...@empty-block.html
  [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-glk4/igt@drm_r...@empty-block.html

 * igt@gem_softpin@noreloc-s3:
   - shard-apl:  [PASS][6] -> [INCOMPLETE][7] ([i915#1635])
  [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl2/igt@gem_soft...@noreloc-s3.html
  [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-apl6/igt@gem_soft...@noreloc-s3.html

 * igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge:
   - shard-apl:  [PASS][8] -> [DMESG-WARN][9] ([i915#1635] / 
[i915#1982]) +3 similar issues
  [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl8/igt@kms_cursor_edge_w...@pipe-b-256x256-left-edge.html
  [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-apl4/igt@kms_cursor_edge_w...@pipe-b-256x256-left-edge.html

 * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
   - shard-glk:  [PASS][10] -> [FAIL][11] ([i915#79])
  [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@ac-hdmi-a1-hdmi-a2.html
  [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@ac-hdmi-a1-hdmi-a2.html

 * igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
   - shard-tglb: [PASS][12] -> [INCOMPLETE][13] ([i915#2606]) +2 
similar issues
  [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@kms_frontbuffer_track...@fbc-1p-indfb-fliptrack.html
  [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb1/igt@kms_frontbuffer_track...@fbc-1p-indfb-fliptrack.html

 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
   - shard-tglb: [PASS][14] -> [DMESG-WARN][15] ([i915#2606])
  [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
  [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-tglb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html

 * igt@kms_frontbuffer_tracking@fbcpsr-tiling-linear:
   - shard-iclb: [PASS][16] -> [INCOMPLETE][17] ([i915#2606])
  [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-tiling-linear.html
  [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18782/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-tiling-linear.html

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: Avoid synchronous binds deep within locks

[Patchwork]

== Series Details ==

Series: drm/i915/gem: Avoid synchronous binds deep within locks
URL   : https://patchwork.freedesktop.org/series/83108/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18789_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_18789_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18789_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_18789_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_create@madvise:
- shard-hsw:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@gem_exec_cre...@madvise.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18789/shard-hsw6/igt@gem_exec_cre...@madvise.html

  * igt@i915_pm_rc6_residency@rc6-idle:
- shard-hsw:  [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@i915_pm_rc6_reside...@rc6-idle.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18789/shard-hsw2/igt@i915_pm_rc6_reside...@rc6-idle.html

  
 Warnings 

  * igt@kms_frontbuffer_tracking@fbc-farfromfence:
- shard-tglb: [INCOMPLETE][5] -> [DMESG-WARN][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-tglb2/igt@kms_frontbuffer_track...@fbc-farfromfence.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18789/shard-tglb2/igt@kms_frontbuffer_track...@fbc-farfromfence.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs}:
- shard-skl:  NOTRUN -> [FAIL][7]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18789/shard-skl8/igt@kms_flip_scaled_...@flip-32bpp-ytile-to-32bpp-ytileccs.html

  
New tests
-

  New tests have been introduced between CI_DRM_9206_full and 
Patchwork_18789_full:

### New CI tests (1) ###

  * boot:
- Statuses : 200 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18789_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_read@empty-block:
- shard-glk:  [PASS][8] -> [DMESG-WARN][9] ([i915#1982])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk2/igt@drm_r...@empty-block.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18789/shard-glk2/igt@drm_r...@empty-block.html

  * igt@gem_exec_create@basic:
- shard-hsw:  [PASS][10] -> [FAIL][11] ([i915#1888])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@gem_exec_cre...@basic.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18789/shard-hsw6/igt@gem_exec_cre...@basic.html

  * igt@gem_exec_schedule@timeslicing@vecs0:
- shard-skl:  [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) +1 
similar issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl7/igt@gem_exec_schedule@timeslic...@vecs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18789/shard-skl4/igt@gem_exec_schedule@timeslic...@vecs0.html

  * igt@gem_exec_whisper@basic-fds-forked-all:
- shard-glk:  [PASS][14] -> [DMESG-WARN][15] ([i915#118] / 
[i915#95])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk4/igt@gem_exec_whis...@basic-fds-forked-all.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18789/shard-glk6/igt@gem_exec_whis...@basic-fds-forked-all.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl:  [PASS][16] -> [INCOMPLETE][17] ([i915#300])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl4/igt@kms_cursor_...@pipe-c-cursor-suspend.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18789/shard-skl6/igt@kms_cursor_...@pipe-c-cursor-suspend.html

  * igt@kms_flip@absolute-wf_vblank@a-dp1:
- shard-apl:  [PASS][18] -> [DMESG-WARN][19] ([i915#1635] / 
[i915#1982])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl2/igt@kms_flip@absolute-wf_vbl...@a-dp1.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18789/shard-apl7/igt@kms_flip@absolute-wf_vbl...@a-dp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl:  [PASS][20] -> [INCOMPLETE][21] ([i915#1635])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-apl1/igt@kms_flip@flip-vs-suspend-interrupti...@a-dp1.html
   [21]: 

[Intel-gfx] ✗ Fi.CI.IGT: failure for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)

[Patchwork]

== Series Details ==

Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
URL   : https://patchwork.freedesktop.org/series/82998/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18788_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_18788_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18788_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_18788_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@evict:
- shard-skl:  [PASS][1] -> [INCOMPLETE][2] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl9/igt@i915_selftest@l...@evict.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl3/igt@i915_selftest@l...@evict.html

  * igt@kms_big_fb@linear-32bpp-rotate-180:
- shard-glk:  [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk8/igt@kms_big...@linear-32bpp-rotate-180.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk2/igt@kms_big...@linear-32bpp-rotate-180.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: NOTRUN -> [INCOMPLETE][5] +2 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
- shard-tglb: NOTRUN -> [DMESG-WARN][6]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-iclb: NOTRUN -> [DMESG-WARN][7] +1 similar issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-iclb8/igt@kms_frontbuffer_track...@fbc-rgb565-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- shard-tglb: NOTRUN -> [INCOMPLETE][8] +11 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@kms_frontbuffer_track...@fbcpsr-indfb-scaledprimary.html

  * igt@perf_pmu@busy-idle-no-semaphores@rcs0:
- shard-hsw:  [PASS][9] -> [FAIL][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@perf_pmu@busy-idle-no-semapho...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@perf_pmu@busy-idle-no-semapho...@rcs0.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_exec_parallel@engines@userptr}:
- shard-hsw:  [PASS][11] -> [FAIL][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw6/igt@gem_exec_parallel@engi...@userptr.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@gem_exec_parallel@engi...@userptr.html

  

### Piglit changes ###

 Possible regressions 

  * spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3 (NEW):
- {pig-icl-1065g7}:   NOTRUN -> [INCOMPLETE][13] +2 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/pig-icl-1065g7/spec@glsl-4.00@execution@built-in-functi...@gs-op-mult-dmat3-dmat3.html

  
New tests
-

  New tests have been introduced between CI_DRM_9206_full and 
Patchwork_18788_full:

### New CI tests (1) ###

  * boot:
- Statuses : 200 pass(s)
- Exec time: [0.0] s

  


### New IGT tests (4) ###

  * igt@kms_content_protection@dp-mst-lic-type-0:
- Statuses : 5 skip(s)
- Exec time: [0.0] s

  * igt@kms_content_protection@dp-mst-lic-type-1:
- Statuses : 5 skip(s)
- Exec time: [0.0] s

  * igt@kms_content_protection@dp-mst-type-0:
- Statuses : 6 skip(s)
- Exec time: [0.0, 0.00] s

  * igt@kms_content_protection@dp-mst-type-1:
- Statuses : 5 skip(s)
- Exec time: [0.0] s

  


### New Piglit tests (3) ###

  * spec@glsl-4.00@execution@built-in-functions@fs-op-mult-dmat4-dmat2x4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s

  * spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s

  * spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat4x3-double:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18788_full that come from known 
issues:

### IGT changes ###

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg1: Fix unbalanced braces

[Patchwork]

== Series Details ==

Series: drm/i915/dg1: Fix unbalanced braces
URL   : https://patchwork.freedesktop.org/series/83120/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18794


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/index.html

New tests
-

  New tests have been introduced between CI_DRM_9206 and Patchwork_18794:

### New CI tests (1) ###

  * boot:
- Statuses : 41 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_18794 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@core_hotunplug@unbind-rebind:
- fi-skl-lmem:[PASS][1] -> [DMESG-WARN][2] ([i915#2605])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-skl-lmem/igt@core_hotunp...@unbind-rebind.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/fi-skl-lmem/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_exec_parallel@engines@fds:
- fi-apl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#1635])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-apl-guc/igt@gem_exec_parallel@engi...@fds.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/fi-apl-guc/igt@gem_exec_parallel@engi...@fds.html

  * igt@gem_flink_basic@double-flink:
- fi-tgl-y:   [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar 
issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@gem_flink_ba...@double-flink.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/fi-tgl-y/igt@gem_flink_ba...@double-flink.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-n3050:   [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-bsw-n3050/igt@i915_pm_...@basic-pci-d3-state.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/fi-bsw-n3050/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_pm_rpm@module-reload:
- fi-byt-j1900:   [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-byt-j1900/igt@i915_pm_...@module-reload.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/fi-byt-j1900/igt@i915_pm_...@module-reload.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u:   [PASS][11] -> [INCOMPLETE][12] ([i915#2606])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_psr@primary_page_flip:
- fi-tgl-y:   [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +3 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@kms_psr@primary_page_flip.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/fi-tgl-y/igt@kms_psr@primary_page_flip.html
- fi-cml-u2:  [PASS][15] -> [INCOMPLETE][16] ([i915#2606])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-cml-u2/igt@kms_psr@primary_page_flip.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/fi-cml-u2/igt@kms_psr@primary_page_flip.html

  
 Possible fixes 

  * igt@i915_module_load@reload:
- fi-kbl-soraka:  [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-kbl-soraka/igt@i915_module_l...@reload.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/fi-kbl-soraka/igt@i915_module_l...@reload.html
- {fi-ehl-1}: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-ehl-1/igt@i915_module_l...@reload.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/fi-ehl-1/igt@i915_module_l...@reload.html
- fi-skl-lmem:[DMESG-WARN][21] ([i915#2605]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-skl-lmem/igt@i915_module_l...@reload.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/fi-skl-lmem/igt@i915_module_l...@reload.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka:   [DMESG-WARN][23] ([i915#1982]) -> [PASS][24]
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18794/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@kms_busy@basic@flip:
- {fi-tgl-dsi}:   [DMESG-WARN][25] ([i915#1982]) -> [PASS][26]
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-dsi/igt@kms_busy@ba...@flip.html
   [26]: 

[Intel-gfx] ✗ Fi.CI.BUILD: failure for linux-next: manual merge of the drm-misc tree with the amdgpu tree

[Patchwork]

== Series Details ==

Series: linux-next: manual merge of the drm-misc tree with the amdgpu tree
URL   : https://patchwork.freedesktop.org/series/83122/
State : failure

== Summary ==

Applying: linux-next: manual merge of the drm-misc tree with the amdgpu tree
error: sha1 information is lacking or useless 
(drivers/gpu/drm/amd/amdgpu/amdgpu_object.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 linux-next: manual merge of the drm-misc tree with the 
amdgpu tree
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".


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