[Intel-gfx] ✗ Fi.CI.BAT: failure for Introduce Intel PXP component
== Series Details ==
Series: Introduce Intel PXP component
URL : https://patchwork.freedesktop.org/series/84136/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9373 -> Patchwork_18954
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_18954 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18954, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18954/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_18954:
### IGT changes ###
Possible regressions
* igt@gem_exec_suspend@basic-s3:
- fi-ilk-650: [PASS][1] -> [FAIL][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-ilk-650/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18954/fi-ilk-650/igt@gem_exec_susp...@basic-s3.html
- fi-elk-e7500: [PASS][3] -> [FAIL][4] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-elk-e7500/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18954/fi-elk-e7500/igt@gem_exec_susp...@basic-s3.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-pnv-d510:[PASS][5] -> [DMESG-WARN][6] +2 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-pnv-d510/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18954/fi-pnv-d510/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
- fi-blb-e6850: [PASS][7] -> [DMESG-WARN][8] +2 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18954/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
- fi-bwr-2160:[PASS][9] -> [DMESG-WARN][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-bwr-2160/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18954/fi-bwr-2160/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
New tests
-
New tests have been introduced between CI_DRM_9373 and Patchwork_18954:
### New CI tests (1) ###
* boot:
- Statuses : 41 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18954 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-blb-e6850: [PASS][11] -> [INCOMPLETE][12] ([i915#2540])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18954/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-icl-u2: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-icl-u2/igt@i915_module_l...@reload.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18954/fi-icl-u2/igt@i915_module_l...@reload.html
* igt@kms_busy@basic@flip:
- fi-kbl-soraka: [PASS][15] -> [DMESG-WARN][16] ([i915#1982])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18954/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-skl-lmem:[DMESG-WARN][17] ([i915#2605]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-skl-lmem/igt@core_hotunp...@unbind-rebind.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18954/fi-skl-lmem/igt@core_hotunp...@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-bsw-kefka: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-bsw-kefka/igt@i915_module_l...@reload.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18954/fi-bsw-kefka/igt@i915_module_l...@reload.html
* igt@i915_selftest@live@execlists:
- fi-kbl-guc: [INCOMPLETE][21] ([i915#1037] / [i915#794]) ->
[PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-kbl-guc/igt@i915_selftest@l...@execlists.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18954/fi-kbl-guc/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component
== Series Details ==
Series: Introduce Intel PXP component
URL : https://patchwork.freedesktop.org/series/84136/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
66b76da7fe5d drm/i915/pxp: Introduce Intel PXP component
-:78: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 82 lines checked
7df24529d3bb drm/i915/pxp: Enable PXP irq worker and callback stub
a901ec3e7f21 drm/i915/pxp: Add PXP context for logical hardware states.
-:103: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#103:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 162 lines checked
d4b812189d1a drm/i915/pxp: set KCR reg init during the boot time
-:67: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#67:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 100 lines checked
988e5cd6442d drm/i915/pxp: Implement ioctl action to set the user space context
-:108: WARNING:PREFER_PACKED: __packed is preferred over __attribute__((packed))
#108: FILE: drivers/gpu/drm/i915/pxp/intel_pxp.h:40:
+} __attribute__((packed));
total: 0 errors, 1 warnings, 0 checks, 135 lines checked
0a0399386f35 drm/i915/pxp: Add PXP-related registers into allowlist
30b4635f97f3 drm/i915/pxp: Read register to check hardware session state
-:19: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible
side-effects?
#19: FILE: drivers/gpu/drm/i915/pxp/intel_pxp.h:15:
+#define pxp_session_list(i915, session_type) (((session_type) ==
SESSION_TYPE_TYPE0) ? \
+ &(i915)->pxp.ctx->active_pxp_type0_sessions :
&(i915)->pxp.ctx->active_pxp_type1_sessions)
total: 0 errors, 0 warnings, 1 checks, 255 lines checked
73fd2ab098a8 drm/i915/pxp: Implement funcs to get/set PXP tag
51b583b84185 drm/i915/pxp: Implement ioctl action to reserve session slot
815493587215 drm/i915/pxp: Implement ioctl action to set session in play
494076c52cd8 drm/i915/pxp: Func to send hardware session termination
9f49e0a6312c drm/i915/pxp: Implement ioctl action to terminate the session
8e1b6914f853 drm/i915/pxp: Enable ioctl action to query PXP tag
118c80a692a7 drm/i915/pxp: Destroy all type0 sessions upon teardown
8080d375bd2a drm/i915/pxp: Termiante the session upon app crash
9f5a2c10293e drm/i915/pxp: Enable PXP power management
-:69: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#69:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 129 lines checked
e12ec2580683 drm/i915/pxp: Implement funcs to create the TEE channel
-:85: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#85:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 242 lines checked
8fd3a79e52de drm/i915/pxp: Implement ioctl action to send TEE commands
cf85826129cb drm/i915/pxp: Create the arbitrary session after boot
328cdbf8a20f drm/i915/pxp: Add i915 trace logs for PXP operations
-:11: WARNING:TYPO_SPELLING: 'trun' may be misspelled - perhaps 'turn'?
#11:
To trun on this feature, we need to set
-:29: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#29: FILE: drivers/gpu/drm/i915/i915_trace.h:1038:
+ TP_STRUCT__entry(
-:36: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#36: FILE: drivers/gpu/drm/i915/i915_trace.h:1045:
+ TP_fast_assign(
total: 0 errors, 1 warnings, 2 checks, 80 lines checked
a0f54901f637 drm/i915/pxp: Expose session state for display protection flip
dd4a59bc3c5e mei: pxp: export pavp client to me client bus
-:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#32:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 277 lines checked
2c36a9443162 drm/i915/uapi: introduce drm_i915_gem_create_ext
-:12: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Joonas Lahtinen
joonas.lahti...@linux.intel.com'
#12:
Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com
-:13: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Matthew Auld
matthew.a...@intel.com'
#13:
Cc: Matthew Auld matthew.a...@intel.com
-:46: ERROR:CODE_INDENT: code indent should use tabs where possible
#46: FILE: drivers/gpu/drm/i915/i915_gem.c:265:
+struct drm_i915_private *i915;$
-:46: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#46: FILE: drivers/gpu/drm/i915/i915_gem.c:265:
+struct drm_i915_private *i915;$
-:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#50: FILE: drivers/gpu/drm/i915/i915_gem.c:269:
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext
*ext_data)
-:95: CHECK:LINE_SPACING: Please don't use multiple blank lines
#95: FILE: drivers/gpu/drm/i915/i915_gem.c:317:
+
+
-:107: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#107:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Warn about types of backlight not handled
== Series Details == Series: drm/i915/display: Warn about types of backlight not handled URL : https://patchwork.freedesktop.org/series/84125/ State : success == Summary == CI Bug Log - changes from CI_DRM_9373_full -> Patchwork_18953_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_9373_full and Patchwork_18953_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18953_full that come from known issues: ### IGT changes ### Issues hit * igt@core_hotunplug@unbind-rebind: - shard-tglb: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-tglb1/igt@core_hotunp...@unbind-rebind.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/shard-tglb7/igt@core_hotunp...@unbind-rebind.html * igt@gem_exec_gttfill@engines@rcs0: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-glk7/igt@gem_exec_gttfill@engi...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/shard-glk8/igt@gem_exec_gttfill@engi...@rcs0.html * igt@gen9_exec_parse@allowed-all: - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1436] / [i915#716]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-skl7/igt@gen9_exec_pa...@allowed-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/shard-skl2/igt@gen9_exec_pa...@allowed-all.html * igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#54]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-skl9/igt@kms_cursor_...@pipe-b-cursor-128x42-offscreen.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/shard-skl4/igt@kms_cursor_...@pipe-b-cursor-128x42-offscreen.html * igt@kms_cursor_edge_walk@pipe-a-128x128-top-edge: - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-skl1/igt@kms_cursor_edge_w...@pipe-a-128x128-top-edge.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/shard-skl3/igt@kms_cursor_edge_w...@pipe-a-128x128-top-edge.html * igt@kms_cursor_legacy@cursor-vs-flip-toggle: - shard-hsw: [PASS][11] -> [FAIL][12] ([i915#2370]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-hsw2/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/shard-hsw6/igt@kms_cursor_leg...@cursor-vs-flip-toggle.html * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#79]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-glk1/igt@kms_flip@flip-vs-expired-vbl...@b-hdmi-a1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/shard-glk8/igt@kms_flip@flip-vs-expired-vbl...@b-hdmi-a1.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt: - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-glk6/igt@kms_frontbuffer_track...@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/shard-glk5/igt@kms_frontbuffer_track...@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#198]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-skl10/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/shard-skl5/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][19] -> [DMESG-FAIL][20] ([fdo#108145] / [i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-skl9/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/shard-iclb4/igt@kms_psr@psr2_sprite_plane_move.html *
[Intel-gfx] [RFC-v2 08/26] drm/i915/pxp: Implement funcs to get/set PXP tag
Implement the functions to get/set the PXP tag, which is 32-bit
bitwise value containing the hardware session info, such as its
session id, protection mode or whether it's enabled.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 95 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 18 +
2 files changed, 113 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 6413f401d939..469810390c9b 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -41,6 +41,16 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32
offset, u32 regval)
return 0;
}
+static u8 pxp_get_session_id(int session_index, int session_type)
+{
+ u8 session_id = session_index & SESSION_ID_MASK;
+
+ if (session_type == SESSION_TYPE_TYPE1)
+ session_id |= SESSION_TYPE_MASK;
+
+ return session_id;
+}
+
/**
* is_sw_session_active - Check if the given sw session id is active.
* @i915: i915 device handle.
@@ -78,6 +88,91 @@ static bool is_sw_session_active(struct drm_i915_private
*i915, int session_type
return false;
}
+static int pxp_set_pxp_tag(struct drm_i915_private *i915, int session_type,
+ int session_idx, int protection_mode)
+{
+ struct pxp_tag *pxp_tag;
+
+ if (!i915 || session_type >= SESSION_TYPE_MAX)
+ return -EINVAL;
+
+ if (session_type == SESSION_TYPE_TYPE0 && session_idx <
MAX_TYPE0_SESSIONS) {
+ pxp_tag = (struct pxp_tag
*)>pxp.ctx->type0_session_pxp_tag[session_idx];
+ } else if (session_type == SESSION_TYPE_TYPE1 && session_idx <
MAX_TYPE1_SESSIONS) {
+ pxp_tag = (struct pxp_tag
*)>pxp.ctx->type1_session_pxp_tag[session_idx];
+ } else {
+ drm_err(>drm, "Failed to %s, bad params
session_type=[%d], session_idx=[%d]\n",
+ __func__, session_type, session_idx);
+ return -EINVAL;
+ }
+
+ switch (protection_mode) {
+ case PROTECTION_MODE_NONE:
+ {
+ pxp_tag->enable = false;
+ pxp_tag->hm = false;
+ pxp_tag->sm = false;
+ break;
+ }
+ case PROTECTION_MODE_LM:
+ {
+ pxp_tag->enable = true;
+ pxp_tag->hm = false;
+ pxp_tag->sm = false;
+ pxp_tag->instance_id++;
+ break;
+ }
+ case PROTECTION_MODE_HM:
+ {
+ pxp_tag->enable = true;
+ pxp_tag->hm = true;
+ pxp_tag->sm = false;
+ pxp_tag->instance_id++;
+ break;
+ }
+ case PROTECTION_MODE_SM:
+ {
+ pxp_tag->enable = true;
+ pxp_tag->hm = true;
+ pxp_tag->sm = true;
+ pxp_tag->instance_id++;
+ break;
+ }
+ default:
+ drm_err(>drm, "Failed to %s, bad params
protection_mode=[%d]\n",
+ __func__, protection_mode);
+ return -EINVAL;
+ }
+
+ pxp_tag->session_id = pxp_get_session_id(session_idx, session_type);
+end:
+ return 0;
+}
+
+u32 intel_pxp_get_pxp_tag(struct drm_i915_private *i915, int session_idx,
+ int session_type, u32 *session_is_alive)
+{
+ struct pxp_tag *pxp_tag;
+
+ if (!i915 || session_type >= SESSION_TYPE_MAX)
+ return -EINVAL;
+
+ if (session_type == SESSION_TYPE_TYPE0 && session_idx <
MAX_TYPE0_SESSIONS) {
+ pxp_tag = (struct pxp_tag
*)>pxp.ctx->type0_session_pxp_tag[session_idx];
+ } else if (session_type == SESSION_TYPE_TYPE1 && session_idx <
MAX_TYPE1_SESSIONS) {
+ pxp_tag = (struct pxp_tag
*)>pxp.ctx->type1_session_pxp_tag[session_idx];
+ } else {
+ drm_err(>drm, "Failed to %s, bad params
session_type=[%d], session_idx=[%d]\n",
+ __func__, session_type, session_idx);
+ return -EINVAL;
+ }
+
+ if (session_is_alive)
+ *session_is_alive = pxp_tag->enable;
+
+ return pxp_tag->value;
+}
+
static bool is_hw_type0_session_in_play(struct drm_i915_private *i915, int
session_index)
{
u32 regval_sip = 0;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index 222a879be96d..b5012948f971 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -20,6 +20,9 @@
#define GEN12_KCR_TSIP_LOW _MMIO(0x32264) /* KCR type1 session in play 0-31
*/
#define GEN12_KCR_TSIP_HIGH _MMIO(0x32268) /* KCR type1 session in play
32-63 */
+#define SESSION_TYPE_MASK BIT(7)
+#define SESSION_ID_MASK (BIT(7) - 1)
+
enum pxp_session_types {
SESSION_TYPE_TYPE0 = 0,
SESSION_TYPE_TYPE1 = 1,
@@ -36,6 +39,21 @@ enum
[Intel-gfx] [RFC-v2 23/26] drm/i915/uapi: introduce drm_i915_gem_create_ext
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen joonas.lahti...@linux.intel.com
Cc: Matthew Auld matthew.a...@intel.com
Cc: Telukuntla Sreedhar
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 42 -
include/uapi/drm/i915_drm.h | 47 +
3 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 453bb5222e99..e513fa359fe2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1742,7 +1742,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 58276694c848..41698a823737 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -53,6 +53,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "i915_user_extensions.h"
#include "intel_pm.h"
@@ -260,6 +261,35 @@ i915_gem_dumb_create(struct drm_file *file,
>size, >handle);
}
+struct create_ext {
+struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext
*ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -271,10 +301,20 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ _data);
+ if (ret)
+ return ret;
+
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index fa1f3d62f9a6..2c1ce2761d55 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -391,6 +391,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAPDRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -728,6 +729,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+* Requested size for the object.
+*
+
[Intel-gfx] [RFC-v2 22/26] mei: pxp: export pavp client to me client bus
From: Vitaly Lubart
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 +
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 271 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index c06581ffa7bd..36884b0a6395 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -57,3 +57,5 @@ config INTEL_MEI_VIRTIO
device over virtio.
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index 52aefaab5c1b..cab19c96ba7a 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -29,3 +29,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index ..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index ..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index ..5bd61fe445e3
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .receive = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_master->ops = _pxp_ops;
+
[Intel-gfx] [RFC-v2 10/26] drm/i915/pxp: Implement ioctl action to set session in play
With this ioctl action, user space driver can set the session in
state "session in play", after dirver reserved the session slot/id
from driver, and sent the TEE commands to activate the
corresponding hardware session. Session state "session in play"
means this session is ready for secure playback.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 4 ++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 69 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 2 +
3 files changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 5f13a44fe548..30bdbcf543e0 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -52,6 +52,10 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
pxp_info.sm_status = ret;
ret = 0;
}
+ } else if (params->req_session_state ==
PXP_SM_REQ_SESSION_IN_PLAY) {
+ ret = pxp_sm_mark_protected_session_in_play(i915,
params->session_type,
+
params->pxp_tag);
+
} else {
ret = -EINVAL;
goto end;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index e4218083f7ec..b69f5f8bf238 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -41,6 +41,18 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32
offset, u32 regval)
return 0;
}
+static int pxp_get_session_index(struct drm_i915_private *i915, u32 pxp_tag,
+int *session_index_out, int *session_type_out)
+{
+ if (!session_index_out || !session_type_out)
+ return -EINVAL;
+
+ *session_type_out = (pxp_tag & SESSION_TYPE_MASK) ? SESSION_TYPE_TYPE1
: SESSION_TYPE_TYPE0;
+ *session_index_out = pxp_tag & SESSION_ID_MASK;
+
+ return 0;
+}
+
static u8 pxp_get_session_id(int session_index, int session_type)
{
u8 session_id = session_index & SESSION_ID_MASK;
@@ -445,6 +457,63 @@ int intel_pxp_sm_reserve_session(struct drm_i915_private
*i915, struct drm_file
return ret;
}
+/**
+ * pxp_sm_mark_protected_session_in_play - To put an reserved protected
session to "in_play" state
+ * @i915: i915 device handle.
+ * @session_type: Type of the session to be updated. One of enum
pxp_session_types.
+ * @session_id: Session id identifier of the protected session.
+ *
+ * Return: status. 0 means update is successful.
+ */
+int pxp_sm_mark_protected_session_in_play(struct drm_i915_private *i915, int
session_type,
+ u32 session_id)
+{
+ int ret;
+ int session_index;
+ int session_type_in_id;
+ struct pxp_protected_session *current_session;
+
+ ret = pxp_get_session_index(i915, session_id, _index,
_type_in_id);
+ if (ret) {
+ drm_err(>drm, "Failed to pxp_get_session_index\n");
+ return ret;
+ }
+
+ if (session_type != session_type_in_id) {
+ drm_err(>drm, "Failed to session_type and
session_type_in_id don't match\n");
+ return -EINVAL;
+ }
+
+ lockdep_assert_held(>pxp.ctx->ctx_mutex);
+
+ switch (session_type) {
+ case SESSION_TYPE_TYPE0:
+ list_for_each_entry(current_session,
>pxp.ctx->active_pxp_type0_sessions,
+ session_list) {
+ if (current_session->session_index == session_index) {
+ current_session->session_is_in_play = true;
+ return 0;
+ }
+ }
+ break;
+ case SESSION_TYPE_TYPE1:
+ list_for_each_entry(current_session,
>pxp.ctx->active_pxp_type1_sessions,
+ session_list) {
+ if (current_session->session_index == session_index) {
+ current_session->session_is_in_play = true;
+ return 0;
+ }
+ }
+ break;
+ default:
+ /* invalid session type */
+ return -EINVAL;
+ }
+
+ drm_err(>drm, "Failed to %s couldn't find active session\n",
__func__);
+ return -EINVAL;
+}
+
int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915)
{
int ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index 5fcf63f804f8..90f7d74cacdf 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -87,6 +87,8 @@ struct pxp_protected_session {
int intel_pxp_sm_reserve_session(struct
[Intel-gfx] [RFC-v2 12/26] drm/i915/pxp: Implement ioctl action to terminate the session
Implement the PXP ioctl action to allow user space driver to
terminate the hardware session and cleanup its software session
state. PXP sends the session termination command to GPU once
receves this ioctl action.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 7 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 190
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 5 +
3 files changed, 202 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 30bdbcf543e0..91164005e0ff 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -56,6 +56,13 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
ret = pxp_sm_mark_protected_session_in_play(i915,
params->session_type,
params->pxp_tag);
+ } else if (params->req_session_state ==
PXP_SM_REQ_SESSION_TERMINATE) {
+ ret = pxp_sm_terminate_protected_session_safe(i915, 0,
+
params->session_type,
+
params->pxp_tag);
+
+ if (!intel_pxp_sm_is_any_type0_session_in_play(i915,
PROTECTION_MODE_ALL))
+ intel_pxp_destroy_user_ctx_list(i915);
} else {
ret = -EINVAL;
goto end;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index f41e50911688..65b89728251d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -802,6 +802,174 @@ static int issue_hw_terminate_for_session(struct
drm_i915_private *i915, int ses
return ret;
}
+/**
+ * terminate_protected_session - To terminate an active HW session and free
its entry.
+ * @i915: i915 device handle.
+ * @context_id: context identifier of the requestor. only relevant if
do_safety_check is true.
+ * @session_type: type of the session to be terminated. One of enum
pxp_session_types.
+ * @session_index: session index of the session to be terminated.
+ * @do_safety_check: if enabled the context Id sent by the caller is
+ * matched with the one associated with the terminated
+ * session entry.
+ *
+ * Return: 0 means terminate is successful, or didn't find the desired session.
+ */
+static int terminate_protected_session(struct drm_i915_private *i915, int
context_id,
+ int session_type, int session_index,
+ bool do_safety_check)
+{
+ int ret;
+ struct pxp_protected_session *current_session, *n;
+
+ lockdep_assert_held(>pxp.ctx->ctx_mutex);
+
+ switch (session_type) {
+ case SESSION_TYPE_TYPE0:
+ list_for_each_entry_safe(current_session, n,
+pxp_session_list(i915,
SESSION_TYPE_TYPE0),
+session_list) {
+ if (current_session->session_index == session_index) {
+ if (do_safety_check &&
current_session->context_id != context_id) {
+ ret = -EPERM;
+ drm_err(>drm, "Failed to %s due
to invalid context_id=[%d]\n",
+ __func__, context_id);
+ goto end;
+ }
+
+ ret = issue_hw_terminate_for_session(i915,
session_type,
+
session_index);
+ if (ret) {
+ drm_err(>drm, "Failed to
issue_hw_terminate_for_session()\n");
+ goto end;
+ }
+
+ ret = pxp_set_pxp_tag(i915, session_type,
session_index,
+ PROTECTION_MODE_NONE);
+ if (ret) {
+ drm_err(>drm, "Failed to
pxp_set_pxp_tag()\n");
+ goto end;
+ }
+
+ list_del(_session->session_list);
+ kfree(current_session);
+ return 0;
+ }
+ }
+ return 0;
+
+ case SESSION_TYPE_TYPE1:
+ list_for_each_entry_safe(current_session, n,
+pxp_session_list(i915,
SESSION_TYPE_TYPE1),
+session_list) {
+
[Intel-gfx] [RFC-v2 16/26] drm/i915/pxp: Enable PXP power management
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after the power cycle.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.c | 8 +++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 72 +
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 16 ++
4 files changed, 98 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 81432a9f44d6..6858392c1ef2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,7 +258,8 @@ i915-y += i915_perf.o
i915-y += \
pxp/intel_pxp.o \
pxp/intel_pxp_context.o \
- pxp/intel_pxp_sm.o
+ pxp/intel_pxp_sm.o \
+ pxp/intel_pxp_pm.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index dec3bb96d238..2eab12b5d964 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
@@ -1094,6 +1096,8 @@ static int i915_drm_prepare(struct drm_device *dev)
*/
i915_gem_suspend(i915);
+ intel_pxp_pm_prepare_suspend(i915);
+
return 0;
}
@@ -1277,6 +1281,8 @@ static int i915_drm_resume(struct drm_device *dev)
intel_power_domains_enable(dev_priv);
+ intel_pxp_pm_resume(dev_priv);
+
enable_rpm_wakeref_asserts(_priv->runtime_pm);
return 0;
@@ -1348,6 +1354,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_power_domains_resume(dev_priv);
+ intel_pxp_pm_resume_early(dev_priv);
+
enable_rpm_wakeref_asserts(_priv->runtime_pm);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index ..59847e0ed2e3
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "intel_pxp_context.h"
+#include "intel_pxp_sm.h"
+#include "intel_pxp_pm.h"
+
+void intel_pxp_pm_prepare_suspend(struct drm_i915_private *i915)
+{
+ if (!i915->pxp.ctx)
+ return;
+
+ mutex_lock(>pxp.ctx->ctx_mutex);
+
+ /* Disable PXP-IOCTLs */
+ i915->pxp.ctx->global_state_in_suspend = true;
+
+ mutex_unlock(>pxp.ctx->ctx_mutex);
+}
+
+void intel_pxp_pm_resume_early(struct drm_i915_private *i915)
+{
+ if (!i915->pxp.ctx)
+ return;
+
+ mutex_lock(>pxp.ctx->ctx_mutex);
+
+ if (i915->pxp.ctx->global_state_in_suspend) {
+ /* reset the attacked flag even there was a pending */
+ i915->pxp.ctx->global_state_attacked = false;
+
+ i915->pxp.ctx->flag_display_hm_surface_keys = false;
+ }
+
+ mutex_unlock(>pxp.ctx->ctx_mutex);
+}
+
+int intel_pxp_pm_resume(struct drm_i915_private *i915)
+{
+ int ret = 0;
+
+ if (!i915->pxp.ctx)
+ return 0;
+
+ mutex_lock(>pxp.ctx->ctx_mutex);
+
+ /* Re-enable PXP-IOCTLs */
+ if (i915->pxp.ctx->global_state_in_suspend) {
+ intel_pxp_destroy_user_ctx_list(i915);
+
+ ret = intel_pxp_sm_terminate_all_active_sessions(i915,
SESSION_TYPE_TYPE0);
+ if (ret) {
+ drm_err(>drm, "Failed to
intel_pxp_sm_terminate_all_active_sessions with type0\n");
+ goto end;
+ }
+
+ ret = intel_pxp_sm_terminate_all_active_sessions(i915,
SESSION_TYPE_TYPE1);
+ if (ret) {
+ drm_err(>drm, "Failed to
intel_pxp_sm_terminate_all_active_sessions with type1\n");
+ goto end;
+ }
+
+ i915->pxp.ctx->global_state_in_suspend = false;
+ }
+
+end:
+ mutex_unlock(>pxp.ctx->ctx_mutex);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
new file mode 100644
index ..d2af781c3de1
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_PM_H__
+#define __INTEL_PXP_PM_H__
+
+#include "i915_drv.h"
+
+void intel_pxp_pm_prepare_suspend(struct
[Intel-gfx] [RFC-v2 07/26] drm/i915/pxp: Read register to check hardware session state
Implement the functions to check the hardware protected session
state via reading the hardware register session in play.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.h| 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 177
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 51 +++
3 files changed, 231 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index a1e83bbeafb7..c9d19d3ee0e7 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -12,6 +12,9 @@
#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+#define pxp_session_list(i915, session_type) (((session_type) ==
SESSION_TYPE_TYPE0) ? \
+ &(i915)->pxp.ctx->active_pxp_type0_sessions :
&(i915)->pxp.ctx->active_pxp_type1_sessions)
+
#define MAX_TYPE0_SESSIONS 16
#define MAX_TYPE1_SESSIONS 6
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index a2c9c71d2372..6413f401d939 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -10,6 +10,21 @@
#include "intel_pxp_sm.h"
#include "intel_pxp_context.h"
+static int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32
*regval)
+{
+ intel_wakeref_t wakeref;
+
+ if (!i915 || !regval)
+ return -EINVAL;
+
+ with_intel_runtime_pm(>runtime_pm, wakeref) {
+ i915_reg_t reg_offset = {offset};
+ *regval = intel_uncore_read(>uncore, reg_offset);
+ }
+
+ return 0;
+}
+
static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
{
intel_wakeref_t wakeref;
@@ -26,6 +41,168 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32
offset, u32 regval)
return 0;
}
+/**
+ * is_sw_session_active - Check if the given sw session id is active.
+ * @i915: i915 device handle.
+ * @session_type: Specified session type
+ * @session_index: Numeric session identifier.
+ * @is_in_play: Set false to return true if the specified session is active.
+ * Set true to also check if the session is active and in_play.
+ * @protection_mode: get the protection mode of specified session.
+ *
+ * The caller needs to use ctx_mutex lock to protect the session_list
+ * inside this function.
+ *
+ * Return : true if session with the same identifier is active (and in_play).
+ */
+static bool is_sw_session_active(struct drm_i915_private *i915, int
session_type,
+int session_index, bool is_in_play, int
*protection_mode)
+{
+ struct pxp_protected_session *current_session;
+
+ lockdep_assert_held(>pxp.ctx->ctx_mutex);
+
+ list_for_each_entry(current_session, pxp_session_list(i915,
session_type), session_list) {
+ if (current_session->session_index == session_index) {
+ if (protection_mode)
+ *protection_mode =
current_session->protection_mode;
+
+ if (is_in_play && !current_session->session_is_in_play)
+ return false;
+
+ return true;
+ }
+ }
+
+ /* session id not found. return false */
+ return false;
+}
+
+static bool is_hw_type0_session_in_play(struct drm_i915_private *i915, int
session_index)
+{
+ u32 regval_sip = 0;
+ u32 reg_session_id_mask;
+ bool hw_session_is_in_play = false;
+ int ret = 0;
+
+ if (!i915 || session_index < 0 || session_index >= MAX_TYPE0_SESSIONS)
+ goto end;
+
+ ret = pxp_sm_reg_read(i915, GEN12_KCR_SIP.reg, _sip);
+ if (ret) {
+ drm_err(>drm, "Failed to read()\n");
+ goto end;
+ }
+
+ reg_session_id_mask = (1 << session_index);
+ hw_session_is_in_play = (bool)(regval_sip & reg_session_id_mask);
+end:
+ return hw_session_is_in_play;
+}
+
+static bool is_hw_type1_session_in_play(struct drm_i915_private *i915, int
session_index)
+{
+ int ret = 0;
+ u32 regval_tsip_low = 0;
+ u32 regval_tsip_high = 0;
+ u64 reg_session_id_mask;
+ u64 regval_tsip;
+ bool hw_session_is_in_play = false;
+
+ if (!i915 || session_index < 0 || session_index >= MAX_TYPE1_SESSIONS)
+ goto end;
+
+ ret = pxp_sm_reg_read(i915, GEN12_KCR_TSIP_LOW.reg, _tsip_low);
+ if (ret) {
+ drm_err(>drm, "Failed to pxp_sm_reg_read()\n");
+ goto end;
+ }
+
+ ret = pxp_sm_reg_read(i915, GEN12_KCR_TSIP_HIGH.reg, _tsip_high);
+ if (ret) {
+ drm_err(>drm, "Failed to pxp_sm_reg_read()\n");
+ goto end;
+ }
+
+ reg_session_id_mask = (1 << session_index);
+ regval_tsip = ((u64)regval_tsip_high << 32) | regval_tsip_low;
+
[Intel-gfx] [RFC-v2 21/26] drm/i915/pxp: Expose session state for display protection flip
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8
drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 ++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index d5e79beca0d3..45db4fb50507 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -312,3 +312,11 @@ void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir)
end:
return;
}
+
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ if (i915->pxp.ctx && i915->pxp.ctx->flag_display_hm_surface_keys)
+ return true;
+ else
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 96664d71cf0c..6cbe7164ac7a 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -116,4 +116,6 @@ int i915_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915);
int intel_pxp_init(struct drm_i915_private *i915);
void intel_pxp_uninit(struct drm_i915_private *i915);
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915);
+
#endif
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v2 14/26] drm/i915/pxp: Destroy all type0 sessions upon teardown
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate all the type0 sessions.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 6 +-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 112 +++-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 1 +
3 files changed, 117 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index c4e287f34588..ff6941cd3d83 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -124,16 +124,20 @@ static void intel_pxp_mask_irq(struct intel_gt *gt, u32
mask)
static int intel_pxp_teardown_required_callback(struct drm_i915_private *i915)
{
+ int ret;
+
mutex_lock(>pxp.ctx->ctx_mutex);
i915->pxp.ctx->global_state_attacked = true;
i915->pxp.ctx->flag_display_hm_surface_keys = false;
+ ret = intel_pxp_sm_terminate_all_active_sessions(i915,
SESSION_TYPE_TYPE0);
+
intel_pxp_destroy_user_ctx_list(i915);
mutex_unlock(>pxp.ctx->ctx_mutex);
- return 0;
+ return ret;
}
static int intel_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index fdfb366d7472..32eebdc380e5 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -802,6 +802,64 @@ static int issue_hw_terminate_for_session(struct
drm_i915_private *i915, int ses
return ret;
}
+static int terminate_all_hw_sessions_with_global_termination(struct
drm_i915_private *i915,
+int session_type)
+{
+ u32 *cmd = NULL;
+ u32 *cmd_ptr = NULL;
+ int cmd_size_in_dw = 0;
+ int ret;
+ int session_index;
+ const int session_num_max = pxp_session_max(session_type);
+
+ if (!i915)
+ return -EINVAL;
+
+ /* Calculate how many bytes need to be alloc */
+ for (session_index = 0; session_index < session_num_max;
session_index++) {
+ if (is_hw_session_in_play(i915, session_type, session_index)) {
+ cmd_size_in_dw += add_pxp_prolog(i915, NULL,
session_type, session_index);
+ cmd_size_in_dw += add_pxp_inline_termination(NULL);
+ }
+ }
+ cmd_size_in_dw += add_pxp_epilog(NULL);
+
+ cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ /* Program the command */
+ cmd_ptr = cmd;
+ for (session_index = 0; session_index < session_num_max;
session_index++) {
+ if (is_hw_session_in_play(i915, session_type, session_index)) {
+ cmd_ptr += add_pxp_prolog(i915, cmd_ptr, session_type,
session_index);
+ cmd_ptr += add_pxp_inline_termination(cmd_ptr);
+ }
+ }
+ cmd_ptr += add_pxp_epilog(cmd_ptr);
+
+ if (cmd_size_in_dw != (cmd_ptr - cmd)) {
+ ret = -EINVAL;
+ drm_err(>drm, "Failed to %s\n", __func__);
+ goto end;
+ }
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "global termination cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ ret = pxp_submit_cmd(i915, cmd, cmd_size_in_dw);
+ if (ret) {
+ drm_err(>drm, "Failed to pxp_submit_cmd()\n");
+ goto end;
+ }
+
+end:
+ kfree(cmd);
+ return ret;
+}
+
/**
* terminate_protected_session - To terminate an active HW session and free
its entry.
* @i915: i915 device handle.
@@ -970,6 +1028,58 @@ int pxp_sm_terminate_protected_session_unsafe(struct
drm_i915_private *i915, int
return ret;
}
+static int intel_pxp_sm_destroy_all_sw_sessions(struct drm_i915_private *i915,
int session_type)
+{
+ int ret = 0;
+ struct pxp_protected_session *current_session, *n;
+
+ list_for_each_entry_safe(current_session, n, pxp_session_list(i915,
session_type),
+session_list) {
+ ret = pxp_set_pxp_tag(i915, session_type,
current_session->session_index,
+ PROTECTION_MODE_NONE);
+ if (ret)
+ drm_err(>drm, "Failed to pxp_set_pxp_tag()\n");
+
+ list_del(_session->session_list);
+ kfree(current_session);
+ }
+
+ return ret;
+}
+
+/**
+ * intel_pxp_sm_terminate_all_active_sessions - Terminate all active HW
sessions and their entries.
+ * @i915: i915 device handle.
+ * @session_type: Type of the sessions to be
[Intel-gfx] [RFC-v2 18/26] drm/i915/pxp: Implement ioctl action to send TEE commands
Implement the ioctl action to allow user space driver sends TEE
commands via PXP ioctl, instead of TEE iotcl. So we can
centralize those protection operations at PXP.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 14 ++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 18
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 55
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 5 +++
4 files changed, 92 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 441e57d6c58f..bf95c63e52ff 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -77,6 +77,20 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
ret = pxp_sm_ioctl_query_pxp_tag(i915,
>session_is_alive, >pxp_tag);
break;
}
+ case PXP_ACTION_TEE_IO_MESSAGE:
+ {
+ struct pxp_tee_io_message_params *params =
_info.tee_io_message;
+
+ ret = pxp_tee_ioctl_io_message(i915,
+ params->msg_in,
params->msg_in_size,
+ params->msg_out,
>msg_out_size,
+ params->msg_out_buf_size);
+ if (ret) {
+ drm_err(>drm, "Failed to send TEE IO message\n");
+ ret = -EFAULT;
+ }
+ break;
+ }
case PXP_ACTION_SET_USER_CONTEXT:
{
ret = intel_pxp_set_user_ctx(i915, pxp_info.set_user_ctx);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index a3a0cf1f12e9..f24e6109eae6 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -33,6 +33,7 @@ enum pxp_sm_session_req {
enum pxp_ioctl_action {
PXP_ACTION_QUERY_PXP_TAG = 0,
PXP_ACTION_SET_SESSION_STATUS = 1,
+ PXP_ACTION_TEE_IO_MESSAGE = 4,
PXP_ACTION_SET_USER_CONTEXT = 5,
};
@@ -59,12 +60,29 @@ struct pxp_sm_set_session_status_params {
u32 req_session_state;
};
+/**
+ * struct pxp_tee_io_message_params - Params to send/receive message to/from
TEE.
+ */
+struct pxp_tee_io_message_params {
+ /** @msg_in: in - message input from UMD */
+ u8 __user *msg_in;
+ /** @msg_in_size: in - message input size from UMD */
+ u32 msg_in_size;
+ /** @msg_out: in - message output buffer from UMD */
+ u8 __user *msg_out;
+ /** @msg_out_size: out- message output size from TEE */
+ u32 msg_out_size;
+ /** @msg_out_buf_size: in - message output buffer size from UMD */
+ u32 msg_out_buf_size;
+};
+
struct pxp_info {
u32 action;
u32 sm_status;
union {
struct pxp_sm_query_pxp_tag query_pxp_tag;
struct pxp_sm_set_session_status_params set_session_status;
+ struct pxp_tee_io_message_paramstee_io_message;
u32 set_user_ctx;
};
} __attribute__((packed));
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index fa617546bdd4..2a28478b092d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -54,6 +54,61 @@ static int intel_pxp_tee_io_message(struct drm_i915_private
*i915,
return ret;
}
+int pxp_tee_ioctl_io_message(struct drm_i915_private *i915,
+void __user *msg_in_user_ptr, u32 msg_in_size,
+void __user *msg_out_user_ptr, u32
*msg_out_size_ptr,
+u32 msg_out_buf_size)
+{
+ int ret;
+ void *msg_in = NULL;
+ void *msg_out = NULL;
+
+ if (!msg_in_user_ptr || !msg_out_user_ptr || msg_out_buf_size == 0 ||
+ msg_in_size == 0 || !msg_out_size_ptr)
+ return -EINVAL;
+
+ msg_in = kzalloc(msg_in_size, GFP_KERNEL);
+ if (!msg_in)
+ return -ENOMEM;
+
+ msg_out = kzalloc(msg_out_buf_size, GFP_KERNEL);
+ if (!msg_out) {
+ ret = -ENOMEM;
+ goto end;
+ }
+
+ if (copy_from_user(msg_in, msg_in_user_ptr, msg_in_size) != 0) {
+ ret = -EFAULT;
+ drm_err(>drm, "Failed to copy_from_user for TEE
message\n");
+ goto end;
+ }
+
+ mutex_lock(>pxp_tee_comp_mutex);
+
+ ret = intel_pxp_tee_io_message(i915,
+ msg_in, msg_in_size,
+ msg_out, msg_out_size_ptr,
+ msg_out_buf_size);
+
+ mutex_unlock(>pxp_tee_comp_mutex);
+
+ if (ret) {
+ drm_err(>drm, "Failed to send/receive tee message\n");
+ goto end;
+ }
+
+ if (copy_to_user(msg_out_user_ptr, msg_out,
[Intel-gfx] [RFC-v2 25/26] drm/i915/pxp: Add plane decryption support
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
Cc: Bommu Krishnaiah
Cc: Huang, Sean Z
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 019a2d6d807a..158c8dea0930 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -39,6 +39,8 @@
#include
#include
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -752,6 +754,11 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
+{
+ return obj->user_flags & I915_BO_PROTECTED ? true : false;
+}
+
static void
skl_plane_async_flip(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -788,6 +795,7 @@ skl_program_plane(struct intel_plane *plane,
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int aux_plane = intel_main_to_aux_plane(fb, color_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -798,7 +806,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -874,8 +882,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_gem_object_status(dev_priv) &&
+ intel_fb_obj_protected(obj))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 69758935abb8..63d370c38ecd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7208,6 +7208,7 @@ enum {
#define _PLANE_SURF_3(pipe)_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane)\
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLEDREG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v2 06/26] drm/i915/pxp: Add PXP-related registers into allowlist
Add several PXP-related reg into allowlist to allow user space
driver to read the those register values.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_reg.h | 6
drivers/gpu/drm/i915/intel_uncore.c | 50 -
2 files changed, 41 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3b9ca142539..69758935abb8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12421,4 +12421,10 @@ enum skl_power_gate {
#define TGL_ROOT_DEVICE_SKU_ULX0x2
#define TGL_ROOT_DEVICE_SKU_ULT0x4
+/* Registers for allowlist check */
+#define PXP_REG_01_LOWERBOUND _MMIO(0x32260)
+#define PXP_REG_01_UPPERBOUND _MMIO(0x32268)
+#define PXP_REG_02_LOWERBOUND _MMIO(0x32670)
+#define PXP_REG_02_UPPERBOUND _MMIO(0x32678)
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 1c14a07eba7d..8206da8c51a9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1990,16 +1990,34 @@ void intel_uncore_fini_mmio(struct intel_uncore *uncore)
}
static const struct reg_whitelist {
- i915_reg_t offset_ldw;
+ i915_reg_t offset_ldw_lowerbound;
+ i915_reg_t offset_ldw_upperbound;
i915_reg_t offset_udw;
u16 gen_mask;
u8 size;
-} reg_read_whitelist[] = { {
- .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
+} reg_read_whitelist[] = {
+ {
+ .offset_ldw_lowerbound = RING_TIMESTAMP(RENDER_RING_BASE),
+ .offset_ldw_upperbound = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
.gen_mask = INTEL_GEN_MASK(4, 12),
.size = 8
-} };
+ },
+ {
+ .offset_ldw_lowerbound = PXP_REG_01_LOWERBOUND,
+ .offset_ldw_upperbound = PXP_REG_01_UPPERBOUND,
+ .offset_udw = {0},
+ .gen_mask = INTEL_GEN_MASK(4, 12),
+ .size = 4
+ },
+ {
+ .offset_ldw_lowerbound = PXP_REG_02_LOWERBOUND,
+ .offset_ldw_upperbound = PXP_REG_02_UPPERBOUND,
+ .offset_udw = {0},
+ .gen_mask = INTEL_GEN_MASK(4, 12),
+ .size = 4
+ }
+};
int i915_reg_read_ioctl(struct drm_device *dev,
void *data, struct drm_file *file)
@@ -2012,18 +2030,22 @@ int i915_reg_read_ioctl(struct drm_device *dev,
unsigned int flags;
int remain;
int ret = 0;
+ i915_reg_t offset_ldw;
entry = reg_read_whitelist;
remain = ARRAY_SIZE(reg_read_whitelist);
while (remain) {
- u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
+ u32 entry_offset_lb =
i915_mmio_reg_offset(entry->offset_ldw_lowerbound);
+ u32 entry_offset_ub =
i915_mmio_reg_offset(entry->offset_ldw_upperbound);
GEM_BUG_ON(!is_power_of_2(entry->size));
GEM_BUG_ON(entry->size > 8);
- GEM_BUG_ON(entry_offset & (entry->size - 1));
+ GEM_BUG_ON(entry_offset_lb & (entry->size - 1));
+ GEM_BUG_ON(entry_offset_ub & (entry->size - 1));
if (INTEL_INFO(i915)->gen_mask & entry->gen_mask &&
- entry_offset == (reg->offset & -entry->size))
+ entry_offset_lb <= (reg->offset & -entry->size) &&
+ (reg->offset & -entry->size) <= entry_offset_ub)
break;
entry++;
remain--;
@@ -2033,23 +2055,21 @@ int i915_reg_read_ioctl(struct drm_device *dev,
return -EINVAL;
flags = reg->offset & (entry->size - 1);
+ offset_ldw = _MMIO(reg->offset - flags);
with_intel_runtime_pm(>runtime_pm, wakeref) {
if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
reg->val = intel_uncore_read64_2x32(uncore,
- entry->offset_ldw,
+ offset_ldw,
entry->offset_udw);
else if (entry->size == 8 && flags == 0)
- reg->val = intel_uncore_read64(uncore,
- entry->offset_ldw);
+ reg->val = intel_uncore_read64(uncore, offset_ldw);
else if (entry->size == 4 && flags == 0)
- reg->val = intel_uncore_read(uncore, entry->offset_ldw);
+ reg->val = intel_uncore_read(uncore, offset_ldw);
else if (entry->size == 2 && flags == 0)
- reg->val = intel_uncore_read16(uncore,
- entry->offset_ldw);
+ reg->val = intel_uncore_read16(uncore, offset_ldw);
[Intel-gfx] [RFC-v2 04/26] drm/i915/pxp: set KCR reg init during the boot time
Set the KCR init during the boot time, which is required by
hardware, to allow us doing further protection operation such
as sending commands to GPU or TEE
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c| 11 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 38 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 20 +
4 files changed, 69 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 831e8ad57560..81432a9f44d6 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,6 +258,7 @@ i915-y += i915_perf.o
i915-y += \
pxp/intel_pxp.o \
pxp/intel_pxp_context.o \
+ pxp/intel_pxp_sm.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index b6c44b196e9a..f6b7297ee045 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+#include "intel_pxp_sm.h"
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
@@ -79,6 +80,8 @@ static void intel_pxp_irq_work(struct work_struct *work)
int intel_pxp_init(struct drm_i915_private *i915)
{
+ int ret;
+
drm_info(>drm, "i915 PXP is inited with i915=[%p]\n", i915);
i915->pxp.ctx = intel_pxp_create_ctx(i915);
@@ -87,13 +90,19 @@ int intel_pxp_init(struct drm_i915_private *i915)
return -EFAULT;
}
+ ret = pxp_sm_set_kcr_init_reg(i915);
+ if (ret) {
+ drm_err(>drm, "Failed to set kcr init reg\n");
+ return ret;
+ }
+
INIT_WORK(>pxp.irq_work, intel_pxp_irq_work);
i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
- return 0;
+ return ret;
}
void intel_pxp_uninit(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
new file mode 100644
index ..a2c9c71d2372
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+#include "intel_pxp.h"
+#include "intel_pxp_sm.h"
+#include "intel_pxp_context.h"
+
+static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
+{
+ intel_wakeref_t wakeref;
+
+ if (!i915)
+ return -EINVAL;
+
+ with_intel_runtime_pm(>runtime_pm, wakeref) {
+ i915_reg_t reg_offset = {offset};
+
+ intel_uncore_write(>uncore, reg_offset, regval);
+ }
+
+ return 0;
+}
+
+int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915)
+{
+ int ret;
+
+ ret = pxp_reg_write(i915, KCR_INIT.reg,
KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+ if (ret)
+ drm_err(>drm, "Failed to write()\n");
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
new file mode 100644
index ..d061f395aa16
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_SM_H__
+#define __INTEL_PXP_SM_H__
+
+#include "i915_drv.h"
+#include "i915_reg.h"
+
+/* KCR register definitions */
+#define KCR_INIT_MMIO(0x320f0)
+#define KCR_INIT_MASK_SHIFT (16)
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
KCR_INIT_MASK_SHIFT))
+
+int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915);
+
+#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v2 20/26] drm/i915/pxp: Add i915 trace logs for PXP operations
Add several i915 trace logs for PXP calls for debugging or
performance measurement, including:
(1) PXP ioctl
(2) PXP teardown callbacks
To trun on this feature, we need to set
"CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS=y" in .config for compiling
the Linux kernel.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_trace.h| 44
drivers/gpu/drm/i915/pxp/intel_pxp.c | 6
2 files changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_trace.h
b/drivers/gpu/drm/i915/i915_trace.h
index a4addcc64978..36470e20dc61 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -1031,6 +1031,50 @@ DEFINE_EVENT(i915_context, i915_context_free,
TP_ARGS(ctx)
);
+TRACE_EVENT(i915_pxp_ops_ioctl,
+ TP_PROTO(struct drm_device *dev, void *data, struct drm_file *file,
u32 action),
+ TP_ARGS(dev, data, file, action),
+
+ TP_STRUCT__entry(
+__field(struct drm_device *, dev)
+__field(void *, data)
+__field(struct drm_file *, file)
+__field(u32, action)
+ ),
+
+ TP_fast_assign(
+ __entry->dev = dev;
+ __entry->data = data;
+ __entry->file = file;
+ __entry->action = action;
+ ),
+
+ TP_printk("dev=%p, data=%p, file=%p, action=%u",
+ __entry->dev, __entry->data, __entry->file,
__entry->action)
+);
+
+TRACE_EVENT(i915_pxp_teardown_required_callback,
+ TP_PROTO(bool global_state_attacked),
+ TP_ARGS(global_state_attacked),
+
+ TP_STRUCT__entry(__field(bool, global_state_attacked)),
+
+ TP_fast_assign(__entry->global_state_attacked =
global_state_attacked;),
+
+ TP_printk("global_state_attacked=%s",
yesno(__entry->global_state_attacked))
+);
+
+TRACE_EVENT(i915_pxp_global_terminate_complete_callback,
+ TP_PROTO(bool global_state_attacked),
+ TP_ARGS(global_state_attacked),
+
+ TP_STRUCT__entry(__field(bool, global_state_attacked)),
+
+ TP_fast_assign(__entry->global_state_attacked =
global_state_attacked;),
+
+ TP_printk("global_state_attacked=%s",
yesno(__entry->global_state_attacked))
+);
+
#endif /* _I915_TRACE_H_ */
/* This part must be outside protection */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 80949f1bbe59..d5e79beca0d3 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -8,6 +8,7 @@
#include "intel_pxp_context.h"
#include "intel_pxp_sm.h"
#include "intel_pxp_tee.h"
+#include "i915_trace.h"
int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile)
{
@@ -22,6 +23,8 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
if (copy_from_user(_info, pxp_ops->info_ptr, sizeof(pxp_info)) != 0)
return -EFAULT;
+ trace_i915_pxp_ops_ioctl(dev, data, drmfile, pxp_info.action);
+
mutex_lock(>pxp.ctx->ctx_mutex);
if (i915->pxp.ctx->global_state_in_suspend) {
@@ -197,6 +200,8 @@ static int intel_pxp_teardown_required_callback(struct
drm_i915_private *i915)
mutex_unlock(>pxp.ctx->ctx_mutex);
+
trace_i915_pxp_teardown_required_callback(i915->pxp.ctx->global_state_attacked);
+
return ret;
}
@@ -219,6 +224,7 @@ static int
intel_pxp_global_terminate_complete_callback(struct drm_i915_private
end:
mutex_unlock(>pxp.ctx->ctx_mutex);
+
trace_i915_pxp_global_terminate_complete_callback(i915->pxp.ctx->global_state_attacked);
return ret;
}
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v2 11/26] drm/i915/pxp: Func to send hardware session termination
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 288
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 16 ++
2 files changed, 304 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index b69f5f8bf238..f41e50911688 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -3,13 +3,163 @@
* Copyright(c) 2020, Intel Corporation. All rights reserved.
*/
+#include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt.h"
#include "gt/intel_context.h"
+#include "gt/intel_gt_buffer_pool.h"
#include "gt/intel_engine_pm.h"
#include "intel_pxp.h"
#include "intel_pxp_sm.h"
#include "intel_pxp_context.h"
+static struct i915_vma *pxp_get_batch(struct drm_i915_private *i915,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw)
+{
+ struct i915_vma *batch = ERR_PTR(-EINVAL);
+ u32 *cmd;
+
+ if (!ce || !ce->engine || !cmd_buf)
+ return ERR_PTR(-EINVAL);
+
+ if (cmd_size_in_dw * 4 > PAGE_SIZE) {
+ drm_err(>drm, "Failed to %s, invalid
cmd_size_id_dw=[%d]\n",
+ __func__, cmd_size_in_dw);
+ return ERR_PTR(-EINVAL);
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
+ if (IS_ERR(cmd)) {
+ drm_err(>drm, "Failed to i915_gem_object_pin_map()\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw *
4, true);
+ }
+
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ drm_err(>drm, "Failed to i915_vma_instance()\n");
+ return batch;
+ }
+
+ return batch;
+}
+
+static int pxp_submit_cmd(struct drm_i915_private *i915, u32 *cmd, int
cmd_size_in_dw)
+{
+ int err = -EINVAL;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ struct intel_context *ce = NULL;
+ bool is_engine_pm_get = false;
+ bool is_batch_vma_pin = false;
+ bool is_skip_req_on_err = false;
+ bool is_engine_get_pool = false;
+ struct intel_gt_buffer_pool_node *pool = NULL;
+ struct intel_gt *gt = NULL;
+
+ if (!i915 || !HAS_ENGINE(>gt, VCS0) ||
+ !i915->gt.engine[VCS0]->kernel_context) {
+ err = -EINVAL;
+ goto end;
+ }
+
+ if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
+ drm_err(>drm, "Failed to %s bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ gt = >gt;
+ ce = i915->gt.engine[VCS0]->kernel_context;
+
+ intel_engine_pm_get(ce->engine);
+ is_engine_pm_get = true;
+
+ pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE);
+ if (IS_ERR(pool)) {
+ drm_err(>drm, "Failed to intel_engine_get_pool()\n");
+ goto end;
+ }
+ is_engine_get_pool = true;
+
+ batch = pxp_get_batch(i915, ce, pool, cmd, cmd_size_in_dw);
+ if (IS_ERR(batch)) {
+ drm_err(>drm, "Failed to pxp_get_batch()\n");
+ goto end;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err) {
+ drm_err(>drm, "Failed to i915_vma_pin()\n");
+ goto end;
+ }
+ is_batch_vma_pin = true;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ drm_err(>drm, "Failed to
intel_context_create_request()\n");
+ goto end;
+ }
+ is_skip_req_on_err = true;
+
+ err = intel_gt_buffer_pool_mark_active(pool, rq);
+ if (err) {
+ drm_err(>drm, "Failed to
intel_engine_pool_mark_active()\n");
+ goto end;
+ }
+
+ i915_vma_lock(batch);
+ err = i915_request_await_object(rq, batch->obj, false);
+ if (!err)
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (err) {
+ drm_err(>drm, "Failed to i915_request_await_object()\n");
+ goto end;
+ }
+
+ if (ce->engine->emit_init_breadcrumb) {
+ err = ce->engine->emit_init_breadcrumb(rq);
+ if (err) {
+ drm_err(>drm, "Failed to
emit_init_breadcrumb()\n");
+ goto end;
+ }
+ }
+
+ err =
[Intel-gfx] [RFC-v2 24/26] drm/i915/pxp: User interface for Protected buffer
From: Bommu Krishnaiah
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 10
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5
drivers/gpu/drm/i915/i915_gem.c | 23 +++
include/uapi/drm/i915_drm.h | 19 +++
6 files changed, 67 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index a6299da64de4..dd5d24a13cb9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -2060,12 +2060,23 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
+ else if (args->value) {
+ if (!i915_gem_context_is_protected(ctx))
+ i915_gem_context_set_recoverable(ctx);
+ else
+ ret = -EPERM;
+ }
else
i915_gem_context_clear_recoverable(ctx);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ if (args->size)
+ ret = -EINVAL;
+ else if (args->value)
+ i915_gem_context_set_protected(ctx);
+ break;
+
case I915_CONTEXT_PARAM_PRIORITY:
ret = set_priority(ctx, args);
break;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index a133f92bbedb..5897e7ca11a8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -70,6 +70,16 @@ static inline void i915_gem_context_set_recoverable(struct
i915_gem_context *ctx
set_bit(UCONTEXT_RECOVERABLE, >user_flags);
}
+static inline void i915_gem_context_set_protected(struct i915_gem_context *ctx)
+{
+ set_bit(UCONTEXT_PROTECTED, >user_flags);
+}
+
+static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, >user_flags);
+}
+
static inline void i915_gem_context_clear_recoverable(struct i915_gem_context
*ctx)
{
clear_bit(UCONTEXT_RECOVERABLE, >user_flags);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index ae14ca24a11f..81ae94c2be86 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -135,7 +135,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
-
+#define UCONTEXT_PROTECTED 5
/**
* @flags: small set of booleans
*/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e2d9b7e1e152..90ac955463f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -161,6 +161,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+* @user_flags: small set of booleans set by the user
+*/
+ unsigned long user_flags;
+#define I915_BO_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 41698a823737..6a791fd24eaa 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -184,7 +184,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, >base, );
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
@@ -258,11 +261,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
[Intel-gfx] [RFC-v2 19/26] drm/i915/pxp: Create the arbitrary session after boot
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session needs to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 47 +++-
drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 27 ++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 6 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 34 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 6 +++
6 files changed, 121 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index bf95c63e52ff..80949f1bbe59 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -125,6 +125,43 @@ void intel_pxp_close(struct drm_i915_private *i915, struct
drm_file *drmfile)
mutex_unlock(>pxp.ctx->ctx_mutex);
}
+int intel_pxp_create_arb_session(struct drm_i915_private *i915)
+{
+ struct pxp_tag pxptag;
+ int ret;
+
+ lockdep_assert_held(>pxp.ctx->ctx_mutex);
+
+ if (i915->pxp.ctx->flag_display_hm_surface_keys) {
+ drm_err(>drm, "%s: arb session is alive so skipping the
creation\n",
+ __func__);
+ return 0;
+ }
+
+ ret = intel_pxp_sm_reserve_arb_session(i915, );
+ if (ret) {
+ drm_err(>drm, "Failed to reserve session\n");
+ goto end;
+ }
+
+ ret = intel_pxp_tee_cmd_create_arb_session(i915);
+ if (ret) {
+ drm_err(>drm, "Failed to send tee cmd for arb session
creation\n");
+ goto end;
+ }
+
+ ret = pxp_sm_mark_protected_session_in_play(i915, ARB_SESSION_TYPE,
pxptag.session_id);
+ if (ret) {
+ drm_err(>drm, "Failed to mark session status in play\n");
+ goto end;
+ }
+
+ i915->pxp.ctx->flag_display_hm_surface_keys = true;
+
+end:
+ return ret;
+}
+
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
/* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
@@ -169,9 +206,17 @@ static int
intel_pxp_global_terminate_complete_callback(struct drm_i915_private
mutex_lock(>pxp.ctx->ctx_mutex);
- if (i915->pxp.ctx->global_state_attacked)
+ if (i915->pxp.ctx->global_state_attacked) {
i915->pxp.ctx->global_state_attacked = false;
+ /* Re-create the arb session after teardown handle complete */
+ ret = intel_pxp_create_arb_session(i915);
+ if (ret) {
+ drm_err(>drm, "Failed to create arb session\n");
+ goto end;
+ }
+ }
+end:
mutex_unlock(>pxp.ctx->ctx_mutex);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index f24e6109eae6..96664d71cf0c 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -107,6 +107,8 @@ struct drm_i915_private;
int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile);
void intel_pxp_close(struct drm_i915_private *i915, struct drm_file *drmfile);
+int intel_pxp_create_arb_session(struct drm_i915_private *i915);
+
void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir);
int i915_pxp_teardown_required_callback(struct drm_i915_private *i915);
int i915_pxp_global_terminate_complete_callback(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 6ff347b7b72b..31eaec25a85f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -607,6 +607,33 @@ int intel_pxp_sm_reserve_session(struct drm_i915_private
*i915, struct drm_file
return ret;
}
+int intel_pxp_sm_reserve_arb_session(struct drm_i915_private *i915, u32
*pxp_tag)
+{
+ int ret;
+
+ lockdep_assert_held(>pxp.ctx->ctx_mutex);
+
+ if (!pxp_tag || !i915)
+ return -EINVAL;
+
+ ret = sync_hw_sw_state(i915, ARB_SESSION_INDEX, ARB_SESSION_TYPE);
+ if (unlikely(ret))
+ goto end;
+
+ ret = create_new_session_entry(i915, NULL, 0, ARB_SESSION_TYPE,
+ ARB_PROTECTION_MODE, ARB_SESSION_INDEX);
+ if (unlikely(ret))
+ goto end;
+
+ ret = pxp_set_pxp_tag(i915, ARB_SESSION_TYPE, ARB_SESSION_INDEX,
ARB_PROTECTION_MODE);
+
+end:
+ if (ret == 0)
+ *pxp_tag = intel_pxp_get_pxp_tag(i915, ARB_SESSION_INDEX,
ARB_SESSION_TYPE, NULL);
+
+
[Intel-gfx] [RFC-v2 15/26] drm/i915/pxp: Termiante the session upon app crash
PXP should terminate the hardware session and cleanup the software
state gracefully when the application has established the
protection session, but doesn't close the session correctly due to
some cases like application crash.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c| 12 ++--
drivers/gpu/drm/i915/pxp/intel_pxp.h| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 19 +++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 1 +
5 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c8b9c42fcbd6..dec3bb96d238 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1028,6 +1028,8 @@ static void i915_driver_postclose(struct drm_device *dev,
struct drm_file *file)
/* Catch up with all the deferred frees from "this" client */
i915_gem_flush_free_objects(to_i915(dev));
+
+ intel_pxp_close(to_i915(dev), file);
}
static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index ff6941cd3d83..846d94d90861 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -100,10 +100,18 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void
*data, struct drm_file *drmf
return ret;
}
-static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
+void intel_pxp_close(struct drm_i915_private *i915, struct drm_file *drmfile)
{
- WARN_ON(INTEL_GEN(i915) < 11);
+ if (!i915 || !i915->pxp.ctx || !drmfile)
+ return;
+ mutex_lock(>pxp.ctx->ctx_mutex);
+ intel_pxp_sm_close(i915, drmfile);
+ mutex_unlock(>pxp.ctx->ctx_mutex);
+}
+
+static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
+{
/* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
intel_uncore_write(>uncore, GEN11_CRYPTO_RSVD_INTR_MASK, mask <<
16);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 6f29a409c124..a3a0cf1f12e9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -88,6 +88,7 @@ struct intel_gt;
struct drm_i915_private;
int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile);
+void intel_pxp_close(struct drm_i915_private *i915, struct drm_file *drmfile);
void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir);
int i915_pxp_teardown_required_callback(struct drm_i915_private *i915);
int i915_pxp_global_terminate_complete_callback(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 32eebdc380e5..6ff347b7b72b 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -1132,3 +1132,22 @@ bool intel_pxp_sm_is_any_type0_session_in_play(struct
drm_i915_private *i915, in
return false;
}
+
+int intel_pxp_sm_close(struct drm_i915_private *i915, struct drm_file *drmfile)
+{
+ struct pxp_protected_session *s, *n;
+ int ret = 0;
+
+ list_for_each_entry_safe(s, n, pxp_session_list(i915,
SESSION_TYPE_TYPE0), session_list) {
+ if (s->drmfile && s->drmfile == drmfile && s->pid ==
pid_nr(drmfile->pid)) {
+ ret = terminate_protected_session(i915, 0,
s->session_type,
+ s->session_index,
false);
+ if (ret) {
+ drm_err(>drm, "Failed to
terminate_protected_session()\n");
+ return ret;
+ }
+ }
+ }
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index aee638e70be6..143f024bb0d2 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -115,5 +115,6 @@ int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915);
u32 intel_pxp_get_pxp_tag(struct drm_i915_private *i915, int session_idx,
int session_type, u32 *session_is_alive);
bool intel_pxp_sm_is_any_type0_session_in_play(struct drm_i915_private *i915,
int protection_mode);
+int intel_pxp_sm_close(struct drm_i915_private *i915, struct drm_file
*drmfile);
#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v2 03/26] drm/i915/pxp: Add PXP context for logical hardware states.
Add PXP context which represents combined view
of driver and logical HW states.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 26 ++-
drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 45
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 44 +++
5 files changed, 119 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8274fea96009..831e8ad57560 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -256,7 +256,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-y += \
- pxp/intel_pxp.o
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_context.o \
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 6ee0814f0d09..b6c44b196e9a 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
+#include "intel_pxp_context.h"
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
@@ -30,12 +31,28 @@ static void intel_pxp_mask_irq(struct intel_gt *gt, u32
mask)
static int intel_pxp_teardown_required_callback(struct drm_i915_private *i915)
{
+ mutex_lock(>pxp.ctx->ctx_mutex);
+
+ i915->pxp.ctx->global_state_attacked = true;
+ i915->pxp.ctx->flag_display_hm_surface_keys = false;
+
+ mutex_unlock(>pxp.ctx->ctx_mutex);
+
return 0;
}
static int intel_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915)
{
- return 0;
+ int ret = 0;
+
+ mutex_lock(>pxp.ctx->ctx_mutex);
+
+ if (i915->pxp.ctx->global_state_attacked)
+ i915->pxp.ctx->global_state_attacked = false;
+
+ mutex_unlock(>pxp.ctx->ctx_mutex);
+
+ return ret;
}
static void intel_pxp_irq_work(struct work_struct *work)
@@ -64,6 +81,12 @@ int intel_pxp_init(struct drm_i915_private *i915)
{
drm_info(>drm, "i915 PXP is inited with i915=[%p]\n", i915);
+ i915->pxp.ctx = intel_pxp_create_ctx(i915);
+ if (!i915->pxp.ctx) {
+ drm_err(>drm, "Failed to create pxp ctx\n");
+ return -EFAULT;
+ }
+
INIT_WORK(>pxp.irq_work, intel_pxp_irq_work);
i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
@@ -75,6 +98,7 @@ int intel_pxp_init(struct drm_i915_private *i915)
void intel_pxp_uninit(struct drm_i915_private *i915)
{
+ intel_pxp_destroy_ctx(i915);
}
/**
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index b17f4153f470..9db4bf6fd3f8 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -12,6 +12,9 @@
#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+#define MAX_TYPE0_SESSIONS 16
+#define MAX_TYPE1_SESSIONS 6
+
enum pxp_sm_session_req {
/* Request KMD to allocate session id and move it to IN INIT */
PXP_SM_REQ_SESSION_ID_INIT = 0x0,
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
new file mode 100644
index ..c340c375daac
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_context.h"
+
+/**
+ * intel_pxp_create_ctx - To create a new pxp context.
+ * @i915: i915 device handle.
+ *
+ * Return: pointer to new_ctx, NULL for failure
+ */
+struct pxp_context *intel_pxp_create_ctx(struct drm_i915_private *i915)
+{
+ struct pxp_context *new_ctx = NULL;
+
+ new_ctx = kzalloc(sizeof(*new_ctx), GFP_KERNEL);
+ if (!new_ctx)
+ return NULL;
+
+ get_random_bytes(_ctx->ctx_id, sizeof(new_ctx->ctx_id));
+
+ new_ctx->global_state_attacked = false;
+
+ mutex_init(_ctx->ctx_mutex);
+
+ INIT_LIST_HEAD(_ctx->active_pxp_type0_sessions);
+ INIT_LIST_HEAD(_ctx->active_pxp_type1_sessions);
+ INIT_LIST_HEAD(_ctx->user_ctx_list);
+
+ return new_ctx;
+}
+
+/**
+ * intel_pxp_destroy_ctx - To destroy the pxp context.
+ * @i915: i915 device handle.
+ *
+ * Return: return 0 for success, failure otherwise.
+ */
+void intel_pxp_destroy_ctx(struct drm_i915_private *i915)
+{
+ kfree(i915->pxp.ctx);
+ i915->pxp.ctx = NULL;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
[Intel-gfx] [RFC-v2 02/26] drm/i915/pxp: Enable PXP irq worker and callback stub
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 ++
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 87 ++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 22 +++
4 files changed, 114 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 257063a57101..d64013d0afb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -13,6 +13,7 @@
#include "intel_gt_irq.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -106,6 +107,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(gt, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5375b219cc3b..c3b9ca142539 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7943,6 +7943,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index bc19024e43f0..6ee0814f0d09 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,13 +6,100 @@
#include "i915_drv.h"
#include "intel_pxp.h"
+static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
+{
+ WARN_ON(INTEL_GEN(i915) < 11);
+
+ /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
+ intel_uncore_write(>uncore, GEN11_CRYPTO_RSVD_INTR_MASK, mask <<
16);
+}
+
+static void intel_pxp_unmask_irq(struct intel_gt *gt)
+{
+ lockdep_assert_held(>irq_lock);
+
+ intel_pxp_write_irq_mask_reg(gt->i915, 0);
+}
+
+static void intel_pxp_mask_irq(struct intel_gt *gt, u32 mask)
+{
+ lockdep_assert_held(>irq_lock);
+
+ intel_pxp_write_irq_mask_reg(gt->i915, mask);
+}
+
+static int intel_pxp_teardown_required_callback(struct drm_i915_private *i915)
+{
+ return 0;
+}
+
+static int intel_pxp_global_terminate_complete_callback(struct
drm_i915_private *i915)
+{
+ return 0;
+}
+
+static void intel_pxp_irq_work(struct work_struct *work)
+{
+ struct intel_pxp *pxp_ptr = container_of(work, typeof(*pxp_ptr),
irq_work);
+ struct drm_i915_private *i915 = container_of(pxp_ptr, typeof(*i915),
pxp);
+ u32 events = 0;
+
+ spin_lock_irq(>gt.irq_lock);
+ events = fetch_and_zero(_ptr->current_events);
+ spin_unlock_irq(>gt.irq_lock);
+
+ if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
+ events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
+ intel_pxp_teardown_required_callback(i915);
+
+ if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
+ intel_pxp_global_terminate_complete_callback(i915);
+
+ spin_lock_irq(>gt.irq_lock);
+ intel_pxp_unmask_irq(>gt);
+ spin_unlock_irq(>gt.irq_lock);
+}
+
int intel_pxp_init(struct drm_i915_private *i915)
{
drm_info(>drm, "i915 PXP is inited with i915=[%p]\n", i915);
+ INIT_WORK(>pxp.irq_work, intel_pxp_irq_work);
+
+ i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
+PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
+PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
+
return 0;
}
void intel_pxp_uninit(struct drm_i915_private *i915)
{
}
+
+/**
+ * intel_pxp_irq_handler - Proxies KCR interrupts to PXP.
+ * @gt: valid GT instance
+ * @iir: GT interrupt vector associated with the interrupt
+ *
+ * Dispatches each vector element into an IRQ to PXP.
+ */
+void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ const u32 events = iir & i915->pxp.handled_irr;
+
+ lockdep_assert_held(>irq_lock);
+
+ if (unlikely(!events)) {
+ drm_err(>drm, "%s returned due to iir=[0x%04x]\n",
__func__, iir);
+ goto end;
+ }
+
+ intel_pxp_mask_irq(gt, i915->pxp.handled_irr);
+
+ i915->pxp.current_events |= events;
+ schedule_work(>pxp.irq_work);
+end:
+ return;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index d92b9bbcef2e..b17f4153f470
[Intel-gfx] [RFC-v2 13/26] drm/i915/pxp: Enable ioctl action to query PXP tag
Enable the PXP ioctl action to allow user space driver to query the
PXP tag, which is a 32-bit bitwise value indicating the current
session info, including protection type, session id, and whether
the session is enabled.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 7 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h| 7 +++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 20
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 3 +++
4 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 91164005e0ff..c4e287f34588 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -69,6 +69,13 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
}
break;
}
+ case PXP_ACTION_QUERY_PXP_TAG:
+ {
+ struct pxp_sm_query_pxp_tag *params = _info.query_pxp_tag;
+
+ ret = pxp_sm_ioctl_query_pxp_tag(i915,
>session_is_alive, >pxp_tag);
+ break;
+ }
case PXP_ACTION_SET_USER_CONTEXT:
{
ret = intel_pxp_set_user_ctx(i915, pxp_info.set_user_ctx);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 1ed433b04943..6f29a409c124 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -31,6 +31,7 @@ enum pxp_sm_session_req {
};
enum pxp_ioctl_action {
+ PXP_ACTION_QUERY_PXP_TAG = 0,
PXP_ACTION_SET_SESSION_STATUS = 1,
PXP_ACTION_SET_USER_CONTEXT = 5,
};
@@ -42,6 +43,11 @@ enum pxp_sm_status {
PXP_SM_STATUS_ERROR_UNKNOWN
};
+struct pxp_sm_query_pxp_tag {
+ u32 session_is_alive;
+ u32 pxp_tag; /* in - Session ID, out pxp tag */
+};
+
struct pxp_sm_set_session_status_params {
/** @pxp_tag: in [optional], for Arbitrator session, out pxp tag */
u32 pxp_tag;
@@ -57,6 +63,7 @@ struct pxp_info {
u32 action;
u32 sm_status;
union {
+ struct pxp_sm_query_pxp_tag query_pxp_tag;
struct pxp_sm_set_session_status_params set_session_status;
u32 set_user_ctx;
};
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 65b89728251d..fdfb366d7472 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -970,6 +970,26 @@ int pxp_sm_terminate_protected_session_unsafe(struct
drm_i915_private *i915, int
return ret;
}
+int pxp_sm_ioctl_query_pxp_tag(struct drm_i915_private *i915, u32
*session_is_alive, u32 *pxp_tag)
+{
+ int session_type = 0;
+ int session_index = 0;
+ int ret;
+
+ if (!session_is_alive || !pxp_tag)
+ return -EINVAL;
+
+ ret = pxp_get_session_index(i915, *pxp_tag, _index,
_type);
+ if (ret) {
+ drm_err(>drm, "Failed to __pxpsessionid_to_sessionid\n");
+ return ret;
+ }
+
+ *pxp_tag = intel_pxp_get_pxp_tag(i915, session_index, session_type,
session_is_alive);
+end:
+ return 0;
+}
+
int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915)
{
int ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index a68e1d109437..7ae001ccb60f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -109,7 +109,10 @@ int pxp_sm_terminate_protected_session_safe(struct
drm_i915_private *i915, int c
int session_type, int session_id);
int pxp_sm_terminate_protected_session_unsafe(struct drm_i915_private *i915,
int session_type,
int session_id);
+int pxp_sm_ioctl_query_pxp_tag(struct drm_i915_private *i915, u32
*session_is_alive, u32 *pxp_tag);
int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915);
+u32 intel_pxp_get_pxp_tag(struct drm_i915_private *i915, int session_idx,
+ int session_type, u32 *session_is_alive);
bool intel_pxp_sm_is_any_type0_session_in_play(struct drm_i915_private *i915,
int protection_mode);
#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v2 26/26] drm/i915/pxp: Enable the PXP ioctl for protected session
In the previous commits, we have implemented the PXP ioctl
functions. Now we enable those handlers and expose them as PXP
ioctl, so allow the user space driver can establish, set, or
destory the protected session via this ioctl.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 48 --
include/uapi/drm/i915_drm.h | 75
3 files changed, 76 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e513fa359fe2..a2b5b6f2723f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1772,6 +1772,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_PXP_OPS, i915_pxp_ops_ioctl, DRM_RENDER_ALLOW),
};
static const struct drm_driver driver = {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 6cbe7164ac7a..06608617c318 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -44,54 +44,6 @@ enum pxp_sm_status {
PXP_SM_STATUS_ERROR_UNKNOWN
};
-struct pxp_sm_query_pxp_tag {
- u32 session_is_alive;
- u32 pxp_tag; /* in - Session ID, out pxp tag */
-};
-
-struct pxp_sm_set_session_status_params {
- /** @pxp_tag: in [optional], for Arbitrator session, out pxp tag */
- u32 pxp_tag;
- /** @session_type: in, session type */
- u32 session_type;
- /** @session_mode: in, session mode */
- u32 session_mode;
- /** @req_session_state: in, new session state */
- u32 req_session_state;
-};
-
-/**
- * struct pxp_tee_io_message_params - Params to send/receive message to/from
TEE.
- */
-struct pxp_tee_io_message_params {
- /** @msg_in: in - message input from UMD */
- u8 __user *msg_in;
- /** @msg_in_size: in - message input size from UMD */
- u32 msg_in_size;
- /** @msg_out: in - message output buffer from UMD */
- u8 __user *msg_out;
- /** @msg_out_size: out- message output size from TEE */
- u32 msg_out_size;
- /** @msg_out_buf_size: in - message output buffer size from UMD */
- u32 msg_out_buf_size;
-};
-
-struct pxp_info {
- u32 action;
- u32 sm_status;
- union {
- struct pxp_sm_query_pxp_tag query_pxp_tag;
- struct pxp_sm_set_session_status_params set_session_status;
- struct pxp_tee_io_message_paramstee_io_message;
- u32 set_user_ctx;
- };
-} __attribute__((packed));
-
-struct drm_i915_pxp_ops {
- struct pxp_info __user *info_ptr;
- __u32 info_size;
-};
-
struct pxp_context;
struct intel_pxp {
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index fab00bfbbdee..83044309708d 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -359,6 +359,7 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_QUERY 0x39
#define DRM_I915_GEM_VM_CREATE 0x3a
#define DRM_I915_GEM_VM_DESTROY0x3b
+#define DRM_I915_PXP_OPS 0x3c
/* Must be kept compact -- no holes */
#define DRM_IOCTL_I915_INITDRM_IOW( DRM_COMMAND_BASE +
DRM_I915_INIT, drm_i915_init_t)
@@ -423,6 +424,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_QUERY, struct drm_i915_query)
#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
+#define DRM_IOCTL_I915_PXP_OPS DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_PXP_OPS, struct drm_i915_pxp_ops)
/* Allow drivers to submit batchbuffers directly to hardware, relying
* on the security mechanisms provided by hardware.
@@ -1964,6 +1966,79 @@ struct drm_i915_gem_vm_control {
__u32 vm_id;
};
+/*
+ * struct pxp_sm_query_pxp_tag - Params to query the PXP tag of specified
+ * session id and whether the session is alive from PXP state machine.
+ */
+struct pxp_sm_query_pxp_tag {
+ u32 session_is_alive;
+ u32 pxp_tag; /* in - Session ID, out pxp tag */
+};
+
+/*
+ * struct pxp_sm_set_session_status_params - Params to reserved, set or destroy
+ * the session from the PXP state machine.
+ */
+struct pxp_sm_set_session_status_params {
+ u32 pxp_tag; /* in [optional], for Arbitrator session, out pxp tag */
+ u32 session_type; /* in, session type */
+ u32 session_mode; /* in, session mode */
+
[Intel-gfx] [RFC-v2 17/26] drm/i915/pxp: Implement funcs to create the TEE channel
Currently ring3 driver sends the TEE commands directly to TEE, but
later, as our design, we would like to make ring3 sending the TEE
commands via the ring0 PXP ioctl action instead of TEE ioctl, so
we can centralize those protection operations at ring0 PXP.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 127 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45
8 files changed, 200 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6858392c1ef2..1f3e0b89ae42 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -259,6 +259,7 @@ i915-y += \
pxp/intel_pxp.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_sm.o \
+ pxp/intel_pxp_tee.o \
pxp/intel_pxp_pm.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2eab12b5d964..453bb5222e99 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -324,6 +324,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
mutex_init(_priv->wm.wm_mutex);
mutex_init(_priv->pps_mutex);
mutex_init(_priv->hdcp_comp_mutex);
+ mutex_init(_priv->pxp_tee_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f34ed07a68ee..9ba6eada4f84 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1219,6 +1219,12 @@ struct drm_i915_private {
struct intel_pxp pxp;
+ struct i915_pxp_comp_master *pxp_tee_master;
+ bool pxp_tee_comp_added;
+
+ /* Mutex to protect the above pxp_tee component related values. */
+ struct mutex pxp_tee_comp_mutex;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 846d94d90861..441e57d6c58f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -7,6 +7,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_sm.h"
+#include "intel_pxp_tee.h"
int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile)
{
@@ -202,6 +203,8 @@ int intel_pxp_init(struct drm_i915_private *i915)
return ret;
}
+ intel_pxp_tee_component_init(i915);
+
INIT_WORK(>pxp.irq_work, intel_pxp_irq_work);
i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
@@ -213,6 +216,8 @@ int intel_pxp_init(struct drm_i915_private *i915)
void intel_pxp_uninit(struct drm_i915_private *i915)
{
+ intel_pxp_tee_component_fini(i915);
+
intel_pxp_destroy_ctx(i915);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index ..fa617546bdd4
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+static int intel_pxp_tee_io_message(struct drm_i915_private *i915,
+ void *msg_in, u32 msg_in_size,
+ void *msg_out, u32 *msg_out_size_ptr,
+ u32 msg_out_buf_size)
+{
+ int ret;
+ struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
+
+ if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr)
+ return -EINVAL;
+
+ lockdep_assert_held(>pxp_tee_comp_mutex);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER))
+ print_hex_dump(KERN_DEBUG, "TEE input message binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, msg_in, msg_in_size,
true);
+
+ ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in,
msg_in_size);
+ if (ret) {
+ drm_err(>drm, "Failed to send TEE message\n");
+ return -EFAULT;
+ }
+
+ ret = pxp_tee_master->ops->receive(pxp_tee_master->tee_dev, msg_out,
msg_out_buf_size);
+ if (ret < 0) {
+
[Intel-gfx] [RFC-v2 09/26] drm/i915/pxp: Implement ioctl action to reserve session slot
With this ioctl action, user space driver can reserve a specific
session slot/id assigned by PXP, as the first step of PXP session
establishment flow. The session info is stored in the session list
structure.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c| 20
drivers/gpu/drm/i915/pxp/intel_pxp.h| 24 +++-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 149 +++-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 3 +
4 files changed, 193 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 34f6db3f8bd6..5f13a44fe548 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -38,6 +38,26 @@ int i915_pxp_ops_ioctl(struct drm_device *dev, void *data,
struct drm_file *drmf
}
switch (pxp_info.action) {
+ case PXP_ACTION_SET_SESSION_STATUS:
+ {
+ struct pxp_sm_set_session_status_params *params =
_info.set_session_status;
+
+ if (params->req_session_state == PXP_SM_REQ_SESSION_ID_INIT) {
+ ret = intel_pxp_sm_reserve_session(i915, drmfile, 0,
+ params->session_type,
+ params->session_mode,
+ >pxp_tag);
+ if (ret == PXP_SM_STATUS_RETRY_REQUIRED ||
+ ret == PXP_SM_STATUS_SESSION_NOT_AVAILABLE) {
+ pxp_info.sm_status = ret;
+ ret = 0;
+ }
+ } else {
+ ret = -EINVAL;
+ goto end;
+ }
+ break;
+ }
case PXP_ACTION_SET_USER_CONTEXT:
{
ret = intel_pxp_set_user_ctx(i915, pxp_info.set_user_ctx);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index c9d19d3ee0e7..1ed433b04943 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -15,6 +15,9 @@
#define pxp_session_list(i915, session_type) (((session_type) ==
SESSION_TYPE_TYPE0) ? \
&(i915)->pxp.ctx->active_pxp_type0_sessions :
&(i915)->pxp.ctx->active_pxp_type1_sessions)
+#define pxp_session_max(session_type) (((session_type) == SESSION_TYPE_TYPE0)
? \
+ MAX_TYPE0_SESSIONS : MAX_TYPE1_SESSIONS)
+
#define MAX_TYPE0_SESSIONS 16
#define MAX_TYPE1_SESSIONS 6
@@ -27,7 +30,10 @@ enum pxp_sm_session_req {
PXP_SM_REQ_SESSION_TERMINATE
};
-#define PXP_ACTION_SET_USER_CONTEXT 5
+enum pxp_ioctl_action {
+ PXP_ACTION_SET_SESSION_STATUS = 1,
+ PXP_ACTION_SET_USER_CONTEXT = 5,
+};
enum pxp_sm_status {
PXP_SM_STATUS_SUCCESS,
@@ -36,10 +42,24 @@ enum pxp_sm_status {
PXP_SM_STATUS_ERROR_UNKNOWN
};
+struct pxp_sm_set_session_status_params {
+ /** @pxp_tag: in [optional], for Arbitrator session, out pxp tag */
+ u32 pxp_tag;
+ /** @session_type: in, session type */
+ u32 session_type;
+ /** @session_mode: in, session mode */
+ u32 session_mode;
+ /** @req_session_state: in, new session state */
+ u32 req_session_state;
+};
+
struct pxp_info {
u32 action;
u32 sm_status;
- u32 set_user_ctx;
+ union {
+ struct pxp_sm_set_session_status_params set_session_status;
+ u32 set_user_ctx;
+ };
} __attribute__((packed));
struct drm_i915_pxp_ops {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 469810390c9b..e4218083f7ec 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -145,7 +145,7 @@ static int pxp_set_pxp_tag(struct drm_i915_private *i915,
int session_type,
}
pxp_tag->session_id = pxp_get_session_id(session_idx, session_type);
-end:
+
return 0;
}
@@ -298,6 +298,153 @@ static bool
check_if_protected_type0_sessions_are_attacked(struct drm_i915_priva
return false;
}
+/**
+ * create_new_session_entry - Create a new session entry with provided info.
+ * @i915: i915 device handle.
+ * @drmfile: pointer to drm_file
+ * @context_id: Numeric identifier of the context created by the caller.
+ * @session_type: Type of the session requested. One of enum pxp_session_types.
+ * @protection_mode: Type of protection requested for the session.
+ * One of the enum pxp_protection_modes.
+ * @session_index: Numeric session identifier.
+ *
+ * Return: status. 0 means creation is successful.
+ */
+static int create_new_session_entry(struct drm_i915_private *i915, struct
drm_file *drmfile,
+ int context_id, int session_type, int
protection_mode,
+ int session_index)
+{
+
[Intel-gfx] [RFC-v2 01/26] drm/i915/pxp: Introduce Intel PXP component
PXP (Protected Xe Path) is an i915 componment, that
helps user space to establish the hardware protected session and
manage the status of each alive software session, as well as
the life cycle of each session.
By design PXP will expose ioctl so allow user space to create, set,
and destroy each session. It will also provide the communication
chanel to TEE (Trusted Execution Environment) for the protected
hardware session creation.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 4
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/pxp/intel_pxp.c | 18 ++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 22 ++
5 files changed, 52 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e5574e506a5c..8274fea96009 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -254,6 +254,10 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-y += \
+ pxp/intel_pxp.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f2389ba49c69..c8b9c42fcbd6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -889,6 +889,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (ret)
goto out_cleanup_gem;
+ intel_pxp_init(i915);
+
i915_driver_register(i915);
enable_rpm_wakeref_asserts(>runtime_pm);
@@ -938,6 +940,8 @@ void i915_driver_remove(struct drm_i915_private *i915)
/* Flush any external code that still may be under the RCU lock */
synchronize_rcu();
+ intel_pxp_uninit(i915);
+
i915_gem_suspend(i915);
drm_atomic_helper_shutdown(>drm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 15be8debae54..f34ed07a68ee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -105,6 +105,8 @@
#include "intel_region_lmem.h"
+#include "pxp/intel_pxp.h"
+
/* General customization:
*/
@@ -1215,6 +1217,8 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct intel_pxp pxp;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index ..bc19024e43f0
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "i915_drv.h"
+#include "intel_pxp.h"
+
+int intel_pxp_init(struct drm_i915_private *i915)
+{
+ drm_info(>drm, "i915 PXP is inited with i915=[%p]\n", i915);
+
+ return 0;
+}
+
+void intel_pxp_uninit(struct drm_i915_private *i915)
+{
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
new file mode 100644
index ..d92b9bbcef2e
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_H__
+#define __INTEL_PXP_H__
+
+#include
+
+struct pxp_context;
+
+struct intel_pxp {
+ struct pxp_context *ctx;
+};
+
+struct drm_i915_private;
+
+int intel_pxp_init(struct drm_i915_private *i915);
+void intel_pxp_uninit(struct drm_i915_private *i915);
+
+#endif
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC-v2 05/26] drm/i915/pxp: Implement ioctl action to set the user space context
Implement one ioctl action to allow user space driver to set its
user space context, so PXP can track the context id through this
user space context list.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 56
drivers/gpu/drm/i915/pxp/intel_pxp.h | 21
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 24 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 3 ++
4 files changed, 104 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index f6b7297ee045..34f6db3f8bd6 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -8,6 +8,60 @@
#include "intel_pxp_context.h"
#include "intel_pxp_sm.h"
+int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile)
+{
+ int ret;
+ struct pxp_info pxp_info = {0};
+ struct drm_i915_pxp_ops *pxp_ops = data;
+ struct drm_i915_private *i915 = to_i915(dev);
+
+ if (!i915 || !drmfile || !pxp_ops || pxp_ops->info_size !=
sizeof(pxp_info))
+ return -EINVAL;
+
+ if (copy_from_user(_info, pxp_ops->info_ptr, sizeof(pxp_info)) != 0)
+ return -EFAULT;
+
+ mutex_lock(>pxp.ctx->ctx_mutex);
+
+ if (i915->pxp.ctx->global_state_in_suspend) {
+ drm_err(>drm, "Return failure due to state in suspend\n");
+ pxp_info.sm_status = PXP_SM_STATUS_SESSION_NOT_AVAILABLE;
+ ret = 0;
+ goto end;
+ }
+
+ if (i915->pxp.ctx->global_state_attacked) {
+ drm_err(>drm, "Retry required due to state attacked\n");
+ pxp_info.sm_status = PXP_SM_STATUS_RETRY_REQUIRED;
+ ret = 0;
+ goto end;
+ }
+
+ switch (pxp_info.action) {
+ case PXP_ACTION_SET_USER_CONTEXT:
+ {
+ ret = intel_pxp_set_user_ctx(i915, pxp_info.set_user_ctx);
+ break;
+ }
+ default:
+ drm_err(>drm, "Failed to %s due to bad params\n",
__func__);
+ ret = -EINVAL;
+ goto end;
+ }
+
+end:
+ mutex_unlock(>pxp.ctx->ctx_mutex);
+
+ if (ret == 0)
+ if (copy_to_user(pxp_ops->info_ptr, _info,
sizeof(pxp_info)) != 0)
+ ret = -EFAULT;
+
+ if (ret)
+ dev_err(>pdev->dev, "pid=%d, ret = %d\n",
task_pid_nr(current), ret);
+
+ return ret;
+}
+
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32
mask)
{
WARN_ON(INTEL_GEN(i915) < 11);
@@ -37,6 +91,8 @@ static int intel_pxp_teardown_required_callback(struct
drm_i915_private *i915)
i915->pxp.ctx->global_state_attacked = true;
i915->pxp.ctx->flag_display_hm_surface_keys = false;
+ intel_pxp_destroy_user_ctx_list(i915);
+
mutex_unlock(>pxp.ctx->ctx_mutex);
return 0;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 9db4bf6fd3f8..a1e83bbeafb7 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -24,6 +24,26 @@ enum pxp_sm_session_req {
PXP_SM_REQ_SESSION_TERMINATE
};
+#define PXP_ACTION_SET_USER_CONTEXT 5
+
+enum pxp_sm_status {
+ PXP_SM_STATUS_SUCCESS,
+ PXP_SM_STATUS_RETRY_REQUIRED,
+ PXP_SM_STATUS_SESSION_NOT_AVAILABLE,
+ PXP_SM_STATUS_ERROR_UNKNOWN
+};
+
+struct pxp_info {
+ u32 action;
+ u32 sm_status;
+ u32 set_user_ctx;
+} __attribute__((packed));
+
+struct drm_i915_pxp_ops {
+ struct pxp_info __user *info_ptr;
+ __u32 info_size;
+};
+
struct pxp_context;
struct intel_pxp {
@@ -37,6 +57,7 @@ struct intel_pxp {
struct intel_gt;
struct drm_i915_private;
+int i915_pxp_ops_ioctl(struct drm_device *dev, void *data, struct drm_file
*drmfile);
void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir);
int i915_pxp_teardown_required_callback(struct drm_i915_private *i915);
int i915_pxp_global_terminate_complete_callback(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
index c340c375daac..7fc99567b3ac 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
@@ -43,3 +43,27 @@ void intel_pxp_destroy_ctx(struct drm_i915_private *i915)
kfree(i915->pxp.ctx);
i915->pxp.ctx = NULL;
}
+
+int intel_pxp_set_user_ctx(struct drm_i915_private *i915, u32 user_ctx_in)
+{
+ struct pxp_user_ctx *user_ctx;
+
+ user_ctx = kzalloc(sizeof(*user_ctx), GFP_KERNEL);
+ if (!user_ctx)
+ return -ENOMEM;
+
+ user_ctx->user_ctx = user_ctx_in;
+
+ list_add(_ctx->listhead, >pxp.ctx->user_ctx_list);
+ return 0;
+}
+
+void intel_pxp_destroy_user_ctx_list(struct drm_i915_private *i915)
+{
+ struct pxp_user_ctx *user_ctx, *n;
+
+
[Intel-gfx] [RFC-v2 00/26] Introduce Intel PXP component
PXP is an i915 componment, that helps user space to establish the hardware protected session and manage the status of each alive software session, as well as the life cycle of each session. This ioctl is to allow user space driver to create, set, and destroy each session. It also provides the communication chanel to TEE (Trusted Execution Environment) for the protected hardware session creation. Anshuman Gupta (1): drm/i915/pxp: Add plane decryption support Bommu Krishnaiah (2): drm/i915/uapi: introduce drm_i915_gem_create_ext drm/i915/pxp: User interface for Protected buffer Huang, Sean Z (22): drm/i915/pxp: Introduce Intel PXP component drm/i915/pxp: Enable PXP irq worker and callback stub drm/i915/pxp: Add PXP context for logical hardware states. drm/i915/pxp: set KCR reg init during the boot time drm/i915/pxp: Implement ioctl action to set the user space context drm/i915/pxp: Add PXP-related registers into allowlist drm/i915/pxp: Read register to check hardware session state drm/i915/pxp: Implement funcs to get/set PXP tag drm/i915/pxp: Implement ioctl action to reserve session slot drm/i915/pxp: Implement ioctl action to set session in play drm/i915/pxp: Func to send hardware session termination drm/i915/pxp: Implement ioctl action to terminate the session drm/i915/pxp: Enable ioctl action to query PXP tag drm/i915/pxp: Destroy all type0 sessions upon teardown drm/i915/pxp: Termiante the session upon app crash drm/i915/pxp: Enable PXP power management drm/i915/pxp: Implement funcs to create the TEE channel drm/i915/pxp: Implement ioctl action to send TEE commands drm/i915/pxp: Create the arbitrary session after boot drm/i915/pxp: Add i915 trace logs for PXP operations drm/i915/pxp: Expose session state for display protection flip drm/i915/pxp: Enable the PXP ioctl for protected session Vitaly Lubart (1): mei: pxp: export pavp client to me client bus drivers/gpu/drm/i915/Makefile |8 + drivers/gpu/drm/i915/display/intel_sprite.c | 21 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 +- drivers/gpu/drm/i915/gem/i915_gem_context.h | 10 + .../gpu/drm/i915/gem/i915_gem_context_types.h |2 +- .../gpu/drm/i915/gem/i915_gem_object_types.h |5 + drivers/gpu/drm/i915/gt/intel_gt_irq.c|4 + drivers/gpu/drm/i915/i915_drv.c | 18 +- drivers/gpu/drm/i915/i915_drv.h | 10 + drivers/gpu/drm/i915/i915_gem.c | 63 +- drivers/gpu/drm/i915/i915_reg.h |8 + drivers/gpu/drm/i915/i915_trace.h | 44 + drivers/gpu/drm/i915/intel_uncore.c | 50 +- drivers/gpu/drm/i915/pxp/intel_pxp.c | 322 + drivers/gpu/drm/i915/pxp/intel_pxp.h | 73 + drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 69 + drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 47 + drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 72 + drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 16 + drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 1180 + drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 126 ++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 216 +++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 25 + drivers/misc/mei/Kconfig |2 + drivers/misc/mei/Makefile |1 + drivers/misc/mei/pxp/Kconfig | 13 + drivers/misc/mei/pxp/Makefile |7 + drivers/misc/mei/pxp/mei_pxp.c| 230 drivers/misc/mei/pxp/mei_pxp.h| 18 + include/drm/i915_component.h |1 + include/drm/i915_pxp_tee_interface.h | 45 + include/uapi/drm/i915_drm.h | 141 ++ 32 files changed, 2836 insertions(+), 26 deletions(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.h create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h create mode 100644 drivers/misc/mei/pxp/Kconfig create mode 100644 drivers/misc/mei/pxp/Makefile create mode 100644 drivers/misc/mei/pxp/mei_pxp.c create mode 100644 drivers/misc/mei/pxp/mei_pxp.h create mode 100644 include/drm/i915_pxp_tee_interface.h -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Properly flag modesets for all bigjoiner pipes
On Fri, Nov 20, 2020 at 06:01:35PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> If either of the bigjoiner pipes needs a modeset then we need
> a modeset on both pipes. Make it so.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 40
> 1 file changed, 24 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 595183f7b60f..321321230a55 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15355,21 +15355,16 @@ static int intel_atomic_check_bigjoiner(struct
> intel_atomic_state *state,
> return -EINVAL;
> }
>
> -static int kill_bigjoiner_slave(struct intel_atomic_state *state,
> - struct intel_crtc_state *master_crtc_state)
> +static void kill_bigjoiner_slave(struct intel_atomic_state *state,
> + struct intel_crtc_state *master_crtc_state)
> {
> struct intel_crtc_state *slave_crtc_state =
> - intel_atomic_get_crtc_state(>base,
> -
> master_crtc_state->bigjoiner_linked_crtc);
> -
> - if (IS_ERR(slave_crtc_state))
> - return PTR_ERR(slave_crtc_state);
> + intel_atomic_get_new_crtc_state(state,
> master_crtc_state->bigjoiner_linked_crtc);
Isnt this just a cleanup, doesnt relate to adding linked bigjoiner
pipe to the modeset.
Split this in a separate patch? Or atleast mention this in the commit message
Other than that looks good to me
Manasi
>
> slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
> slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave
> = false;
> slave_crtc_state->bigjoiner_linked_crtc =
> master_crtc_state->bigjoiner_linked_crtc = NULL;
> intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
> - return 0;
> }
>
> /**
> @@ -15507,7 +15502,7 @@ static int intel_atomic_check_async(struct
> intel_atomic_state *state)
>
> static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state
> *state)
> {
> - const struct intel_crtc_state *crtc_state;
> + struct intel_crtc_state *crtc_state;
> struct intel_crtc *crtc;
> int i;
>
> @@ -15521,6 +15516,16 @@ static int intel_bigjoiner_add_affected_crtcs(struct
> intel_atomic_state *state)
>
> crtc_state->bigjoiner_linked_crtc);
> if (IS_ERR(linked_crtc_state))
> return PTR_ERR(linked_crtc_state);
> +
> + if (needs_modeset(crtc_state))
> + linked_crtc_state->uapi.mode_changed = true;
> + }
> +
> + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> + /* Kill old bigjoiner link, we may re-establish afterwards */
> + if (needs_modeset(crtc_state) &&
> + crtc_state->bigjoiner && !crtc_state->bigjoiner_slave)
> + kill_bigjoiner_slave(state, crtc_state);
> }
>
> return 0;
> @@ -15564,13 +15569,6 @@ static int intel_atomic_check(struct drm_device *dev,
> continue;
> }
>
> - /* Kill old bigjoiner link, we may re-establish afterwards */
> - if (old_crtc_state->bigjoiner &&
> !old_crtc_state->bigjoiner_slave) {
> - ret = kill_bigjoiner_slave(state, new_crtc_state);
> - if (ret)
> - goto fail;
> - }
> -
> if (!new_crtc_state->uapi.enable) {
> if (!new_crtc_state->bigjoiner_slave) {
> intel_crtc_copy_uapi_to_hw_state(state,
> new_crtc_state);
> @@ -15640,6 +15638,16 @@ static int intel_atomic_check(struct drm_device *dev,
> new_crtc_state->update_pipe = false;
> }
> }
> +
> + if (new_crtc_state->bigjoiner) {
> + struct intel_crtc_state *linked_crtc_state =
> + intel_atomic_get_new_crtc_state(state,
> new_crtc_state->bigjoiner_linked_crtc);
> +
> + if (needs_modeset(linked_crtc_state)) {
> + new_crtc_state->uapi.mode_changed = true;
> + new_crtc_state->update_pipe = false;
> + }
> + }
> }
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> --
> 2.26.2
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Properly flag modesets for all bigjoiner pipes
== Series Details == Series: drm/i915: Properly flag modesets for all bigjoiner pipes URL : https://patchwork.freedesktop.org/series/84118/ State : success == Summary == CI Bug Log - changes from CI_DRM_9373_full -> Patchwork_18952_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_9373_full and Patchwork_18952_full: ### New CI tests (1) ### * boot: - Statuses : 199 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18952_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_whisper@basic-queues-forked-all: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-glk8/igt@gem_exec_whis...@basic-queues-forked-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/shard-glk3/igt@gem_exec_whis...@basic-queues-forked-all.html * igt@i915_pm_rc6_residency@rc6-fence: - shard-hsw: [PASS][3] -> [WARN][4] ([i915#1519]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-hsw1/igt@i915_pm_rc6_reside...@rc6-fence.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/shard-hsw1/igt@i915_pm_rc6_reside...@rc6-fence.html * igt@kms_cursor_crc@pipe-c-cursor-64x21-random: - shard-skl: [PASS][5] -> [FAIL][6] ([i915#54]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-skl6/igt@kms_cursor_...@pipe-c-cursor-64x21-random.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/shard-skl1/igt@kms_cursor_...@pipe-c-cursor-64x21-random.html * igt@kms_cursor_edge_walk@pipe-b-256x256-top-edge: - shard-hsw: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-hsw6/igt@kms_cursor_edge_w...@pipe-b-256x256-top-edge.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/shard-hsw6/igt@kms_cursor_edge_w...@pipe-b-256x256-top-edge.html * igt@kms_dp_aux_dev: - shard-iclb: [PASS][9] -> [DMESG-WARN][10] ([i915#262]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-iclb4/igt@kms_dp_aux_dev.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/shard-iclb7/igt@kms_dp_aux_dev.html * igt@kms_flip@basic-plain-flip@a-dp1: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1635] / [i915#1982]) +7 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-apl1/igt@kms_flip@basic-plain-f...@a-dp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/shard-apl6/igt@kms_flip@basic-plain-f...@a-dp1.html * igt@kms_flip@dpms-vs-vblank-race-interruptible@a-dp1: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-kbl4/igt@kms_flip@dpms-vs-vblank-race-interrupti...@a-dp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/shard-kbl6/igt@kms_flip@dpms-vs-vblank-race-interrupti...@a-dp1.html * igt@kms_flip@flip-vs-expired-vblank@c-edp1: - shard-skl: [PASS][15] -> [DMESG-FAIL][16] ([i915#1982]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-skl3/igt@kms_flip@flip-vs-expired-vbl...@c-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/shard-skl6/igt@kms_flip@flip-vs-expired-vbl...@c-edp1.html * igt@kms_flip@flip-vs-suspend@b-dp1: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-kbl3/igt@kms_flip@flip-vs-susp...@b-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/shard-kbl7/igt@kms_flip@flip-vs-susp...@b-dp1.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt: - shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-glk6/igt@kms_frontbuffer_track...@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/shard-glk6/igt@kms_frontbuffer_track...@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt: - shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/shard-tglb5/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-draw-mmap-gtt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/shard-tglb8/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-draw-mmap-gtt.html * igt@kms_plane_cursor@pipe-a-viewport-size-128: - shard-skl:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Warn about types of backlight not handled
== Series Details ==
Series: drm/i915/display: Warn about types of backlight not handled
URL : https://patchwork.freedesktop.org/series/84125/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9373 -> Patchwork_18953
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/index.html
New tests
-
New tests have been introduced between CI_DRM_9373 and Patchwork_18953:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18953 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([i915#2540])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-icl-u2/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/fi-icl-u2/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-skl-lmem:[DMESG-WARN][7] ([i915#2605]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-skl-lmem/igt@core_hotunp...@unbind-rebind.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/fi-skl-lmem/igt@core_hotunp...@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-bsw-kefka: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-bsw-kefka/igt@i915_module_l...@reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/fi-bsw-kefka/igt@i915_module_l...@reload.html
* igt@i915_selftest@live@execlists:
- fi-kbl-guc: [INCOMPLETE][11] ([i915#1037] / [i915#794]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-kbl-guc/igt@i915_selftest@l...@execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/fi-kbl-guc/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2540]: https://gitlab.freedesktop.org/drm/intel/issues/2540
[i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
[i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
Participating hosts (45 -> 40)
--
Additional (1): fi-tgl-y
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-bsw-cyan
fi-ctg-p8600 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9373 -> Patchwork_18953
CI-20190529: 20190529
CI_DRM_9373: 9cdf0261b50968252f7775f0de5d34ab8f8b4892 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5864: afc0e559615b791d229ba977f792d04de13a37f7 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18953: 4f6b5a7cfc45ad8d923cbeba0e1ad7579ac7e47b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4f6b5a7cfc45 drm/i915/display: Warn about types of backlight not handled
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18953/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 000/141] Fix fall-through warnings for Clang
On Fri, Nov 20, 2020 at 11:51:42AM -0800, Jakub Kicinski wrote: > On Fri, 20 Nov 2020 11:30:40 -0800 Kees Cook wrote: > > On Fri, Nov 20, 2020 at 10:53:44AM -0800, Jakub Kicinski wrote: > > > On Fri, 20 Nov 2020 12:21:39 -0600 Gustavo A. R. Silva wrote: > > > > This series aims to fix almost all remaining fall-through warnings in > > > > order to enable -Wimplicit-fallthrough for Clang. > > > > > > > > In preparation to enable -Wimplicit-fallthrough for Clang, explicitly > > > > add multiple break/goto/return/fallthrough statements instead of just > > > > letting the code fall through to the next case. > > > > > > > > Notice that in order to enable -Wimplicit-fallthrough for Clang, this > > > > change[1] is meant to be reverted at some point. So, this patch helps > > > > to move in that direction. > > > > > > > > Something important to mention is that there is currently a discrepancy > > > > between GCC and Clang when dealing with switch fall-through to empty > > > > case > > > > statements or to cases that only contain a break/continue/return > > > > statement[2][3][4]. > > > > > > Are we sure we want to make this change? Was it discussed before? > > > > > > Are there any bugs Clangs puritanical definition of fallthrough helped > > > find? > > > > > > IMVHO compiler warnings are supposed to warn about issues that could > > > be bugs. Falling through to default: break; can hardly be a bug?! > > > > It's certainly a place where the intent is not always clear. I think > > this makes all the cases unambiguous, and doesn't impact the machine > > code, since the compiler will happily optimize away any behavioral > > redundancy. > > If none of the 140 patches here fix a real bug, and there is no change > to machine code then it sounds to me like a W=2 kind of a warning. I'd like to avoid splitting common -W options between default and W=2 just based on the compiler. Getting -Wimplicit-fallthrough enabled found plenty of bugs, so making sure it works correctly for both compilers feels justified to me. (This is just a subset of the same C language short-coming.) > I think clang is just being annoying here, but if I'm the only one who > feels this way chances are I'm wrong :) It's being pretty pedantic, but I don't think it's unreasonable to explicitly state how every case ends. GCC's silence for the case of "fall through to a break" doesn't really seem justified. -- Kees Cook ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 16/21] drm/i915/adl_s: MCHBAR memory info registers are moved
On Fri, 2020-11-20 at 12:18 -0800, Lucas De Marchi wrote:
> On Tue, Nov 17, 2020 at 10:50:24AM -0800, Aditya Swarup wrote:
> > From: Caz Yokoyama
> >
> > The crwebview indicates on ADL-S that some of our MCHBAR
> > registers have moved from their traditional 0x50XX offsets to
> > new locations. The meaning and bit layout of the registers
> > remain same.
> >
> > Cc: Lucas De Marchi
> > Cc: Jani Nikula
> > Cc: Ville Syrjälä
> > Cc: Imre Deak
> > Cc: Matt Roper
> > Signed-off-by: Yokoyama, Caz
> > Signed-off-by: Aditya Swarup
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 5 +
> > drivers/gpu/drm/i915/intel_dram.c | 18 +++---
> > 2 files changed, 20 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 4c8d0d84af6a..6abba59592f7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10863,6 +10863,8 @@ enum skl_power_gate {
> > #define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
> > #define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
> >
> > +#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR
> > _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x6048)
> > +
> > #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN_MMIO(MCHBAR_MI
> > RROR_BASE_SNB + 0x500C)
> > #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN_MMIO(MCHBAR_MI
> > RROR_BASE_SNB + 0x5010)
> > #define SKL_DRAM_S_SHIFT 16
> > @@ -10890,6 +10892,9 @@ enum skl_power_gate {
> > #define CNL_DRAM_RANK_3(0x2 << 9)
> > #define CNL_DRAM_RANK_4(0x3 << 9)
> >
> > +#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR _MMIO(MCHBAR_MI
> > RROR_BASE_SNB + 0x6054)
> > +#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR _MMIO(MCHBAR_MI
> > RROR_BASE_SNB + 0x6058)
> > +
> > /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using
> > this register,
> > * since on HSW we can't write to it using I915_WRITE. */
> > #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB +
> > 0x5F0C)
> > diff --git a/drivers/gpu/drm/i915/intel_dram.c
> > b/drivers/gpu/drm/i915/intel_dram.c
> > index 4754296a250e..e7427e5f4130 100644
> > --- a/drivers/gpu/drm/i915/intel_dram.c
> > +++ b/drivers/gpu/drm/i915/intel_dram.c
> > @@ -184,13 +184,21 @@ skl_dram_get_channels_info(struct
> > drm_i915_private *i915)
> > u32 val;
> > int ret;
> >
> > - val = intel_uncore_read(>uncore,
> > + if (IS_ALDERLAKE_S(i915))
> > + val = intel_uncore_read(>uncore,
> > + ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR);
> > + else
> > + val = intel_uncore_read(>uncore,
> > SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
> > ret = skl_dram_get_channel_info(i915, , 0, val);
> > if (ret == 0)
> > dram_info->num_channels++;
> >
> > - val = intel_uncore_read(>uncore,
> > + if (IS_ALDERLAKE_S(i915))
> > + val = intel_uncore_read(>uncore,
> > + ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR);
> > + else
> > + val = intel_uncore_read(>uncore,
> > SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
>
> probably better to:
>
> u32 ch0, ch1;
>
> and then keep the reads together in a single if/else chain.
> Or use i915_reg_t ch0_reg, ch1_reg
Agree/Better idea. When I worked for, I only concerned how to minimize
my patch and not think about whether the code is simple and readable.
-caz
>
> Lucas De Marchi
>
> > ret = skl_dram_get_channel_info(i915, , 1, val);
> > if (ret == 0)
> > @@ -231,7 +239,11 @@ skl_get_dram_type(struct drm_i915_private
> > *i915)
> > {
> > u32 val;
> >
> > - val = intel_uncore_read(>uncore,
> > + if (IS_ALDERLAKE_S(i915))
> > + val = intel_uncore_read(>uncore,
> > + ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR);
> > + else
> > + val = intel_uncore_read(>uncore,
> > SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMA
> > IN);
> >
> > switch (val & SKL_DRAM_DDR_TYPE_MASK) {
> > --
> > 2.27.0
> >
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 16/21] drm/i915/adl_s: MCHBAR memory info registers are moved
On Tue, Nov 17, 2020 at 10:50:24AM -0800, Aditya Swarup wrote:
From: Caz Yokoyama
The crwebview indicates on ADL-S that some of our MCHBAR
registers have moved from their traditional 0x50XX offsets to
new locations. The meaning and bit layout of the registers
remain same.
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Yokoyama, Caz
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_dram.c | 18 +++---
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4c8d0d84af6a..6abba59592f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10863,6 +10863,8 @@ enum skl_power_gate {
#define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
#define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
+#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB +
0x6048)
+
#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN_MMIO(MCHBAR_MIRROR_BASE_SNB +
0x500C)
#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN_MMIO(MCHBAR_MIRROR_BASE_SNB +
0x5010)
#define SKL_DRAM_S_SHIFT 16
@@ -10890,6 +10892,9 @@ enum skl_power_gate {
#define CNL_DRAM_RANK_3(0x2 << 9)
#define CNL_DRAM_RANK_4(0x3 << 9)
+#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB +
0x6054)
+#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB +
0x6058)
+
/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
* since on HSW we can't write to it using I915_WRITE. */
#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
diff --git a/drivers/gpu/drm/i915/intel_dram.c
b/drivers/gpu/drm/i915/intel_dram.c
index 4754296a250e..e7427e5f4130 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -184,13 +184,21 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
u32 val;
int ret;
- val = intel_uncore_read(>uncore,
+ if (IS_ALDERLAKE_S(i915))
+ val = intel_uncore_read(>uncore,
+ ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR);
+ else
+ val = intel_uncore_read(>uncore,
SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
ret = skl_dram_get_channel_info(i915, , 0, val);
if (ret == 0)
dram_info->num_channels++;
- val = intel_uncore_read(>uncore,
+ if (IS_ALDERLAKE_S(i915))
+ val = intel_uncore_read(>uncore,
+ ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR);
+ else
+ val = intel_uncore_read(>uncore,
SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
probably better to:
u32 ch0, ch1;
and then keep the reads together in a single if/else chain.
Or use i915_reg_t ch0_reg, ch1_reg
Lucas De Marchi
ret = skl_dram_get_channel_info(i915, , 1, val);
if (ret == 0)
@@ -231,7 +239,11 @@ skl_get_dram_type(struct drm_i915_private *i915)
{
u32 val;
- val = intel_uncore_read(>uncore,
+ if (IS_ALDERLAKE_S(i915))
+ val = intel_uncore_read(>uncore,
+ ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR);
+ else
+ val = intel_uncore_read(>uncore,
SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
switch (val & SKL_DRAM_DDR_TYPE_MASK) {
--
2.27.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/display: Warn about types of backlight not handled
Right now we are only explicitly handling the backlight of types INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE, INTEL_BACKLIGHT_DSI_DCS and INTEL_BACKLIGHT_DISPLAY_DDI all others are being handled as INTEL_BACKLIGHT_DISPLAY_DDI(south display engine PWM) but that might not be the intended HW usage, so lets warn to identify those systems and implement it properly if needed. Cc: Imre Deak Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_panel.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 9f23bac0d792..368722536462 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -2023,6 +2023,21 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel) struct intel_connector *connector = container_of(panel, struct intel_connector, panel); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + enum intel_backlight_type type = dev_priv->vbt.backlight.type; + + if (dev_priv->params.enable_dpcd_backlight) + type = INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE; + + drm_dbg_kms(_priv->drm, + "Connector %s backlight type %u controller %u\n", + connector->base.name, type, + dev_priv->vbt.backlight.controller); + + if (type != INTEL_BACKLIGHT_DISPLAY_DDI && + type != INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE && + type != INTEL_BACKLIGHT_DSI_DCS) + drm_warn(_priv->drm, "Backlight type %i not properly handled\n", +type); if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP && intel_dp_aux_init_backlight_funcs(connector) == 0) -- 2.29.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 000/141] Fix fall-through warnings for Clang
On 11/20/20 12:28, Joe Perches wrote: > On Fri, 2020-11-20 at 12:21 -0600, Gustavo A. R. Silva wrote: >> Hi all, >> >> This series aims to fix almost all remaining fall-through warnings in >> order to enable -Wimplicit-fallthrough for Clang. >> >> In preparation to enable -Wimplicit-fallthrough for Clang, explicitly >> add multiple break/goto/return/fallthrough statements instead of just >> letting the code fall through to the next case. >> >> Notice that in order to enable -Wimplicit-fallthrough for Clang, this >> change[1] is meant to be reverted at some point. So, this patch helps >> to move in that direction. > > This was a bit hard to parse for a second or three. > > Thanks Gustavo. > > How was this change done? I audited case by case in order to determine the best fit for each situation. Depending on the surrounding logic, sometimes it makes more sense a goto or a fallthrough rather than merely a break. Thanks -- Gustavo ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 000/141] Fix fall-through warnings for Clang
On Fri, Nov 20, 2020 at 10:53:44AM -0800, Jakub Kicinski wrote: > On Fri, 20 Nov 2020 12:21:39 -0600 Gustavo A. R. Silva wrote: > > This series aims to fix almost all remaining fall-through warnings in > > order to enable -Wimplicit-fallthrough for Clang. > > > > In preparation to enable -Wimplicit-fallthrough for Clang, explicitly > > add multiple break/goto/return/fallthrough statements instead of just > > letting the code fall through to the next case. > > > > Notice that in order to enable -Wimplicit-fallthrough for Clang, this > > change[1] is meant to be reverted at some point. So, this patch helps > > to move in that direction. > > > > Something important to mention is that there is currently a discrepancy > > between GCC and Clang when dealing with switch fall-through to empty case > > statements or to cases that only contain a break/continue/return > > statement[2][3][4]. > > Are we sure we want to make this change? Was it discussed before? > > Are there any bugs Clangs puritanical definition of fallthrough helped > find? > > IMVHO compiler warnings are supposed to warn about issues that could > be bugs. Falling through to default: break; can hardly be a bug?! It's certainly a place where the intent is not always clear. I think this makes all the cases unambiguous, and doesn't impact the machine code, since the compiler will happily optimize away any behavioral redundancy. -- Kees Cook ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 000/141] Fix fall-through warnings for Clang
Hi,
On 11/20/20 12:53, Jakub Kicinski wrote:
> On Fri, 20 Nov 2020 12:21:39 -0600 Gustavo A. R. Silva wrote:
>> This series aims to fix almost all remaining fall-through warnings in
>> order to enable -Wimplicit-fallthrough for Clang.
>>
>> In preparation to enable -Wimplicit-fallthrough for Clang, explicitly
>> add multiple break/goto/return/fallthrough statements instead of just
>> letting the code fall through to the next case.
>>
>> Notice that in order to enable -Wimplicit-fallthrough for Clang, this
>> change[1] is meant to be reverted at some point. So, this patch helps
>> to move in that direction.
>>
>> Something important to mention is that there is currently a discrepancy
>> between GCC and Clang when dealing with switch fall-through to empty case
>> statements or to cases that only contain a break/continue/return
>> statement[2][3][4].
>
> Are we sure we want to make this change? Was it discussed before?
>
> Are there any bugs Clangs puritanical definition of fallthrough helped
> find?
>
> IMVHO compiler warnings are supposed to warn about issues that could
> be bugs. Falling through to default: break; can hardly be a bug?!
The justification for this is explained in this same changelog text:
Now that the -Wimplicit-fallthrough option has been globally enabled[5],
any compiler should really warn on missing either a fallthrough annotation
or any of the other case-terminating statements (break/continue/return/
goto) when falling through to the next case statement. Making exceptions
to this introduces variation in case handling which may continue to lead
to bugs, misunderstandings, and a general lack of robustness. The point
of enabling options like -Wimplicit-fallthrough is to prevent human error
and aid developers in spotting bugs before their code is even built/
submitted/committed, therefore eliminating classes of bugs. So, in order
to really accomplish this, we should, and can, move in the direction of
addressing any error-prone scenarios and get rid of the unintentional
fallthrough bug-class in the kernel, entirely, even if there is some minor
redundancy. Better to have explicit case-ending statements than continue to
have exceptions where one must guess as to the right result. The compiler
will eliminate any actual redundancy.
Note that there is already a patch in mainline that addresses almost
40,000 of these issues[6].
[1] commit e2079e93f562c ("kbuild: Do not enable -Wimplicit-fallthrough for
clang for now")
[2] ClangBuiltLinux#636
[3] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91432
[4] https://godbolt.org/z/xgkvIh
[5] commit a035d552a93b ("Makefile: Globally enable fall-through warning")
[6] commit 4169e889e588 ("include: jhash/signal: Fix fall-through warnings for
Clang")
Thanks
--
Gustavo
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 000/141] Fix fall-through warnings for Clang
On Fri, 2020-11-20 at 12:21 -0600, Gustavo A. R. Silva wrote: > Hi all, > > This series aims to fix almost all remaining fall-through warnings in > order to enable -Wimplicit-fallthrough for Clang. > > In preparation to enable -Wimplicit-fallthrough for Clang, explicitly > add multiple break/goto/return/fallthrough statements instead of just > letting the code fall through to the next case. > > Notice that in order to enable -Wimplicit-fallthrough for Clang, this > change[1] is meant to be reverted at some point. So, this patch helps > to move in that direction. This was a bit hard to parse for a second or three. Thanks Gustavo. How was this change done? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/3] drm/i915/gem: Remove incorrect early dbg print
== Series Details == Series: series starting with [CI,1/3] drm/i915/gem: Remove incorrect early dbg print URL : https://patchwork.freedesktop.org/series/84110/ State : success == Summary == CI Bug Log - changes from CI_DRM_9371_full -> Patchwork_18951_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_9371_full and Patchwork_18951_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18951_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-suspend: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#1037] / [i915#198]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/shard-skl7/igt@gem_...@in-flight-suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/shard-skl3/igt@gem_...@in-flight-suspend.html * igt@gem_eio@kms: - shard-snb: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/shard-snb4/igt@gem_...@kms.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/shard-snb7/igt@gem_...@kms.html * igt@i915_module_load@reload: - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/shard-tglb5/igt@i915_module_l...@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/shard-tglb3/igt@i915_module_l...@reload.html * igt@i915_pm_rpm@i2c: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/shard-glk5/igt@i915_pm_...@i2c.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/shard-glk4/igt@i915_pm_...@i2c.html * igt@kms_cursor_crc@pipe-b-cursor-64x64-random: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/shard-skl9/igt@kms_cursor_...@pipe-b-cursor-64x64-random.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/shard-skl8/igt@kms_cursor_...@pipe-b-cursor-64x64-random.html * igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge: - shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/shard-hsw2/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/shard-hsw6/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html * igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1635] / [i915#1982]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/shard-apl8/igt@kms_cursor_edge_w...@pipe-c-256x256-left-edge.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/shard-apl1/igt@kms_cursor_edge_w...@pipe-c-256x256-left-edge.html * igt@kms_cursor_legacy@flip-vs-cursor-legacy: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#2346]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/shard-skl6/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/shard-skl2/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#79]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-edp1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/shard-kbl3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/shard-kbl4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html * igt@kms_getfb@getfb-addfb-different-handles: - shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +8 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/shard-skl10/igt@kms_ge...@getfb-addfb-different-handles.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/shard-skl9/igt@kms_ge...@getfb-addfb-different-handles.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([i915#198]) [23]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Properly flag modesets for all bigjoiner pipes
== Series Details ==
Series: drm/i915: Properly flag modesets for all bigjoiner pipes
URL : https://patchwork.freedesktop.org/series/84118/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9373 -> Patchwork_18952
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_18952:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-dg1-1}: [FAIL][1] ([i915#2292] / [k.org#204565]) -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-dg1-1/igt@run...@aborted.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/fi-dg1-1/igt@run...@aborted.html
New tests
-
New tests have been introduced between CI_DRM_9373 and Patchwork_18952:
### New CI tests (1) ###
* boot:
- Statuses : 41 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18952 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_hotunplug@unbind-rebind:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([i915#2540])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-tgl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982] /
[k.org#205379])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-tgl-u2/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/fi-tgl-u2/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@module-reload:
- fi-bsw-kefka: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar
issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-bsw-kefka/igt@i915_pm_...@module-reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/fi-bsw-kefka/igt@i915_pm_...@module-reload.html
* igt@kms_busy@basic@flip:
- fi-kbl-soraka: [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/fi-kbl-soraka/igt@kms_busy@ba...@flip.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-skl-lmem:[DMESG-WARN][13] ([i915#2605]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-skl-lmem/igt@core_hotunp...@unbind-rebind.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/fi-skl-lmem/igt@core_hotunp...@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-bsw-kefka: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-bsw-kefka/igt@i915_module_l...@reload.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/fi-bsw-kefka/igt@i915_module_l...@reload.html
* igt@i915_selftest@live@execlists:
- fi-kbl-guc: [INCOMPLETE][17] ([i915#1037] / [i915#794]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9373/fi-kbl-guc/igt@i915_selftest@l...@execlists.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18952/fi-kbl-guc/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2292]: https://gitlab.freedesktop.org/drm/intel/issues/2292
[i915#2540]: https://gitlab.freedesktop.org/drm/intel/issues/2540
[i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
[i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
[k.org#204565]: https://bugzilla.kernel.org/show_bug.cgi?id=204565
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (45 -> 41)
--
Additional (1): fi-tgl-y
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan
Re: [Intel-gfx] [PATCH 4/6] ath11k: make relay callbacks const
Jani Nikula writes: > On Wed, 18 Nov 2020, Jani Nikula wrote: >> Now that relay_open() accepts const callbacks, make relay callbacks >> const. >> >> Cc: Kalle Valo >> Cc: ath...@lists.infradead.org >> Signed-off-by: Jani Nikula > > Kalle, thanks for the acks on the other two ath patches - can I have > your ack on this one too please? Oops, missed that: Acked-by: Kalle Valo -- https://patchwork.kernel.org/project/linux-wireless/list/ https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/6] relay: allow the use of const callback structs
> +/* > + * rchan_callback wrappers. Call the callbacks if available, otherwise fall > back > + * to default behaviour. > + */ This adds an overly long line. That being said this behavior is pretty normal for kernel APIs, so I'm not even sure we need it at all. > + > +/* > + * subbuf_start() callback. > + */ and this one is for sure completley useless. Same for all the other similar ones. But taking one step back: All instances implement create_buf_file and remove_buf_file, which makes sense as that is the prime aim of these methods. So there is no point in making those optional. subbuf_start_callback is overriden by two instances, so making that optional totally makes sense. buf_mapped and buf_unmapped are never overriden, so they should be removed entirely. More importantly there is no case that passes a NULL rchan_callbacks, which makes complete sense as it wouldn't even create a file. So remove that case as well and just replace it with a sanity check in relay_open(). Please also add a patch to mark all rchan_callbacks instances const while you're at it. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Properly flag modesets for all bigjoiner pipes
== Series Details == Series: drm/i915: Properly flag modesets for all bigjoiner pipes URL : https://patchwork.freedesktop.org/series/84118/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2bed74690121 drm/i915: Properly flag modesets for all bigjoiner pipes -:90: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #90: FILE: drivers/gpu/drm/i915/display/intel_display.c:15644: + intel_atomic_get_new_crtc_state(state, new_crtc_state->bigjoiner_linked_crtc); total: 0 errors, 1 warnings, 0 checks, 77 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/6] relay: allow the use of const callback structs
On Thu, Nov 19, 2020 at 08:11:20AM +, Christoph Hellwig wrote: > Please also add a patch to mark all rchan_callbacks instances const > while you're at it. Oops, I just noticed you actually sent that one. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] mm: Extract might_alloc() debug check
On Fri, Nov 20, 2020 at 6:20 PM Randy Dunlap wrote:
>
> Hi,
>
> On 11/20/20 1:54 AM, Daniel Vetter wrote:
> > diff --git a/include/linux/sched/mm.h b/include/linux/sched/mm.h
> > index d5ece7a9a403..f94405d43fd1 100644
> > --- a/include/linux/sched/mm.h
> > +++ b/include/linux/sched/mm.h
> > @@ -180,6 +180,22 @@ static inline void fs_reclaim_acquire(gfp_t gfp_mask)
> > { }
> > static inline void fs_reclaim_release(gfp_t gfp_mask) { }
> > #endif
> >
> > +/**
> > + * might_alloc - Marks possible allocation sites
>
> Mark
>
> > + * @gfp_mask: gfp_t flags that would be use to allocate
>
>used
>
> > + *
> > + * Similar to might_sleep() and other annotations this can be used in
> > functions
>
> annotations,
>
> > + * that might allocate, but often dont. Compiles to nothing without
>
> don't.
>
> > + * CONFIG_LOCKDEP. Includes a conditional might_sleep() if @gfp allows
> > blocking.
>
> ?might_sleep_if() if
That's one if too many, I'll do the others for next round. Thanks for
taking a look.
-Daniel
>
> > + */
> > +static inline void might_alloc(gfp_t gfp_mask)
> > +{
> > + fs_reclaim_acquire(gfp_mask);
> > + fs_reclaim_release(gfp_mask);
> > +
> > + might_sleep_if(gfpflags_allow_blocking(gfp_mask));
> > +}
>
>
> --
> ~Randy
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] mm: Extract might_alloc() debug check
Hi,
On 11/20/20 1:54 AM, Daniel Vetter wrote:
> diff --git a/include/linux/sched/mm.h b/include/linux/sched/mm.h
> index d5ece7a9a403..f94405d43fd1 100644
> --- a/include/linux/sched/mm.h
> +++ b/include/linux/sched/mm.h
> @@ -180,6 +180,22 @@ static inline void fs_reclaim_acquire(gfp_t gfp_mask) { }
> static inline void fs_reclaim_release(gfp_t gfp_mask) { }
> #endif
>
> +/**
> + * might_alloc - Marks possible allocation sites
Mark
> + * @gfp_mask: gfp_t flags that would be use to allocate
used
> + *
> + * Similar to might_sleep() and other annotations this can be used in
> functions
annotations,
> + * that might allocate, but often dont. Compiles to nothing without
don't.
> + * CONFIG_LOCKDEP. Includes a conditional might_sleep() if @gfp allows
> blocking.
?might_sleep_if() if
> + */
> +static inline void might_alloc(gfp_t gfp_mask)
> +{
> + fs_reclaim_acquire(gfp_mask);
> + fs_reclaim_release(gfp_mask);
> +
> + might_sleep_if(gfpflags_allow_blocking(gfp_mask));
> +}
--
~Randy
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/guc: Use correct lock for CT event handler
On 11/20/2020 6:43 AM, Tvrtko Ursulin wrote:
On 20/11/2020 14:32, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-11-20 09:56:36)
From: Tvrtko Ursulin
CT event handler is called under the gt->irq_lock from the interrupt
handling paths so make it the same from the init path. I don't think
this
mismatch caused any functional issue but we need to wean the code of
the
global i915->irq_lock.
ct_read definitely wants to be serialised. Is guc->irq_lock the right
choice?
Not under my understanding and also confirmed by Daniele off line.
Signed-off-by: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 220626c3ad81..6a0452815c41 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -203,7 +203,8 @@ static void guc_disable_interrupts(struct
intel_guc *guc)
static int guc_enable_communication(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct drm_i915_private *i915 = gt->i915;
int ret;
GEM_BUG_ON(guc_communication_enabled(guc));
@@ -223,9 +224,9 @@ static int guc_enable_communication(struct
intel_guc *guc)
guc_enable_interrupts(guc);
/* check for CT messages received before we enabled
interrupts */
- spin_lock_irq(>irq_lock);
+ spin_lock_irq(>irq_lock);
intel_guc_ct_event_handler(>ct);
- spin_unlock_irq(>irq_lock);
+ spin_unlock_irq(>irq_lock);
You used guc->irq_lock in the previous patch. I suggest
intel_guc_ct_event_handler() should specify what lock it requires.
There are indeed too many locks and too little asserts to help the
reader.
But the other end of the state ct_read needs is updated from the GuC
firmware itself, which then send the interrupt, which we process in:
guc_irq_handler
-> intel_guc_to_host_event_handler
-> intel_guc_ct_event_handler
And this side runs under the gt->irq_lock.
guc->irq_lock is not very aptly named, as it is used to protect access
to the guc interrupt state variables (msg_enabled_mask, mmio_msg) and
has nothing to do with protecting the interrupt handler. For that, as
Tvrtko said, the GuC code can use the same lock the rest of the GT uses,
i.e. gt->irq_lock. Maybe we can rename guc->irq_lock to
guc->msg_state_lock for clarity?
Anyway, this is:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/guc: Use correct lock for accessing guc->mmio_msg
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: Use correct lock for accessing
guc->mmio_msg
URL : https://patchwork.freedesktop.org/series/84100/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9370_full -> Patchwork_18950_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_18950_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_userptr_blits@vma-merge}:
- shard-hsw: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/shard-hsw5/igt@gem_userptr_bl...@vma-merge.html
New tests
-
New tests have been introduced between CI_DRM_9370_full and
Patchwork_18950_full:
### New CI tests (1) ###
* boot:
- Statuses : 200 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18950_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@i2c:
- shard-glk: [PASS][2] -> [DMESG-WARN][3] ([i915#1982]) +2 similar
issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/shard-glk7/igt@i915_pm_...@i2c.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/shard-glk9/igt@i915_pm_...@i2c.html
* igt@kms_cursor_crc@pipe-c-cursor-64x21-random:
- shard-skl: [PASS][4] -> [FAIL][5] ([i915#54]) +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/shard-skl5/igt@kms_cursor_...@pipe-c-cursor-64x21-random.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/shard-skl1/igt@kms_cursor_...@pipe-c-cursor-64x21-random.html
* igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge:
- shard-apl: [PASS][6] -> [DMESG-WARN][7] ([i915#1635] /
[i915#1982]) +1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/shard-apl2/igt@kms_cursor_edge_w...@pipe-c-256x256-left-edge.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/shard-apl7/igt@kms_cursor_edge_w...@pipe-c-256x256-left-edge.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [PASS][8] -> [FAIL][9] ([i915#96])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/shard-hsw2/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
- shard-skl: [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +9
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/shard-skl3/igt@kms_flip@flip-vs-blocking-wf-vbl...@a-edp1.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/shard-skl2/igt@kms_flip@flip-vs-blocking-wf-vbl...@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][12] -> [FAIL][13] ([i915#79])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2598])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/shard-tglb1/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a1:
- shard-glk: [PASS][16] -> [FAIL][17] ([i915#79]) +1 similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-hdmi-a1.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-hdmi-a1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][18] -> [FAIL][19] ([i915#2122]) +1 similar
issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interrupti...@b-edp1.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interrupti...@b-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-kbl: [PASS][20] -> [DMESG-WARN][21] ([i915#1982]) +2
similar issues
[20]:
[Intel-gfx] [PATCH] drm/i915: Properly flag modesets for all bigjoiner pipes
From: Ville Syrjälä
If either of the bigjoiner pipes needs a modeset then we need
a modeset on both pipes. Make it so.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 40
1 file changed, 24 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 595183f7b60f..321321230a55 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15355,21 +15355,16 @@ static int intel_atomic_check_bigjoiner(struct
intel_atomic_state *state,
return -EINVAL;
}
-static int kill_bigjoiner_slave(struct intel_atomic_state *state,
- struct intel_crtc_state *master_crtc_state)
+static void kill_bigjoiner_slave(struct intel_atomic_state *state,
+struct intel_crtc_state *master_crtc_state)
{
struct intel_crtc_state *slave_crtc_state =
- intel_atomic_get_crtc_state(>base,
-
master_crtc_state->bigjoiner_linked_crtc);
-
- if (IS_ERR(slave_crtc_state))
- return PTR_ERR(slave_crtc_state);
+ intel_atomic_get_new_crtc_state(state,
master_crtc_state->bigjoiner_linked_crtc);
slave_crtc_state->bigjoiner = master_crtc_state->bigjoiner = false;
slave_crtc_state->bigjoiner_slave = master_crtc_state->bigjoiner_slave
= false;
slave_crtc_state->bigjoiner_linked_crtc =
master_crtc_state->bigjoiner_linked_crtc = NULL;
intel_crtc_copy_uapi_to_hw_state(state, slave_crtc_state);
- return 0;
}
/**
@@ -15507,7 +15502,7 @@ static int intel_atomic_check_async(struct
intel_atomic_state *state)
static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
{
- const struct intel_crtc_state *crtc_state;
+ struct intel_crtc_state *crtc_state;
struct intel_crtc *crtc;
int i;
@@ -15521,6 +15516,16 @@ static int intel_bigjoiner_add_affected_crtcs(struct
intel_atomic_state *state)
crtc_state->bigjoiner_linked_crtc);
if (IS_ERR(linked_crtc_state))
return PTR_ERR(linked_crtc_state);
+
+ if (needs_modeset(crtc_state))
+ linked_crtc_state->uapi.mode_changed = true;
+ }
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ /* Kill old bigjoiner link, we may re-establish afterwards */
+ if (needs_modeset(crtc_state) &&
+ crtc_state->bigjoiner && !crtc_state->bigjoiner_slave)
+ kill_bigjoiner_slave(state, crtc_state);
}
return 0;
@@ -15564,13 +15569,6 @@ static int intel_atomic_check(struct drm_device *dev,
continue;
}
- /* Kill old bigjoiner link, we may re-establish afterwards */
- if (old_crtc_state->bigjoiner &&
!old_crtc_state->bigjoiner_slave) {
- ret = kill_bigjoiner_slave(state, new_crtc_state);
- if (ret)
- goto fail;
- }
-
if (!new_crtc_state->uapi.enable) {
if (!new_crtc_state->bigjoiner_slave) {
intel_crtc_copy_uapi_to_hw_state(state,
new_crtc_state);
@@ -15640,6 +15638,16 @@ static int intel_atomic_check(struct drm_device *dev,
new_crtc_state->update_pipe = false;
}
}
+
+ if (new_crtc_state->bigjoiner) {
+ struct intel_crtc_state *linked_crtc_state =
+ intel_atomic_get_new_crtc_state(state,
new_crtc_state->bigjoiner_linked_crtc);
+
+ if (needs_modeset(linked_crtc_state)) {
+ new_crtc_state->uapi.mode_changed = true;
+ new_crtc_state->update_pipe = false;
+ }
+ }
}
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915/gem: Remove incorrect early dbg print
== Series Details == Series: series starting with [CI,1/3] drm/i915/gem: Remove incorrect early dbg print URL : https://patchwork.freedesktop.org/series/84110/ State : success == Summary == CI Bug Log - changes from CI_DRM_9371 -> Patchwork_18951 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/index.html New tests - New tests have been introduced between CI_DRM_9371 and Patchwork_18951: ### New CI tests (1) ### * boot: - Statuses : 41 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18951 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_create@basic: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/fi-tgl-y/igt@gem_exec_cre...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/fi-tgl-y/igt@gem_exec_cre...@basic.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/fi-byt-j1900/igt@i915_pm_...@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/fi-byt-j1900/igt@i915_pm_...@basic-pci-d3-state.html * igt@kms_busy@basic@flip: - fi-kbl-soraka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/fi-kbl-soraka/igt@kms_busy@ba...@flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/fi-kbl-soraka/igt@kms_busy@ba...@flip.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html * igt@kms_flip@basic-flip-vs-modeset@a-edp1: - fi-tgl-y: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/fi-tgl-y/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/fi-tgl-y/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html Possible fixes * igt@i915_module_load@reload: - fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/fi-icl-u2/igt@i915_module_l...@reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/fi-icl-u2/igt@i915_module_l...@reload.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_selftest@live@execlists: - fi-cml-s: [INCOMPLETE][17] ([i915#1037]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/fi-cml-s/igt@i915_selftest@l...@execlists.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/fi-cml-s/igt@i915_selftest@l...@execlists.html * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [FAIL][19] -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-kbl-soraka: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/fi-kbl-soraka/igt@kms_frontbuffer_track...@basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18951/fi-kbl-soraka/igt@kms_frontbuffer_track...@basic.html * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [DMESG-WARN][23] ([i915#402]) -> [PASS][24] +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9371/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [24]:
Re: [Intel-gfx] [PATCH] drm/ttm: don't set page->mapping
On Fri, Nov 20, 2020 at 11:08:31AM +0100, Christian König wrote:
> Am 20.11.20 um 11:05 schrieb Daniel Vetter:
> > On Fri, Nov 20, 2020 at 11:04 AM Christian König
> > wrote:
> > > Am 20.11.20 um 10:54 schrieb Daniel Vetter:
> > > > Random observation while trying to review Christian's patch series to
> > > > stop looking at struct page for dma-buf imports.
> > > >
> > > > This was originally added in
> > > >
> > > > commit 58aa6622d32af7d2c08d45085f44c54554a16ed7
> > > > Author: Thomas Hellstrom
> > > > Date: Fri Jan 3 11:47:23 2014 +0100
> > > >
> > > > drm/ttm: Correctly set page mapping and -index members
> > > >
> > > > Needed for some vm operations; most notably unmap_mapping_range()
> > > > with
> > > > even_cows = 0.
> > > >
> > > > Signed-off-by: Thomas Hellstrom
> > > > Reviewed-by: Brian Paul
> > > >
> > > > but we do not have a single caller of unmap_mapping_range with
> > > > even_cows == 0. And all the gem drivers don't do this, so another
> > > > small thing we could standardize between drm and ttm drivers.
> > > >
> > > > Plus I don't really see a need for unamp_mapping_range where we don't
> > > > want to indiscriminately shoot down all ptes.
> > > >
> > > > Cc: Thomas Hellstrom
> > > > Cc: Brian Paul
> > > > Signed-off-by: Daniel Vetter
> > > > Cc: Christian Koenig
> > > > Cc: Huang Rui
> > > This is still a NAK as long as we can't come up with a better way to
> > > track TTMs page allocations.
> > >
> > > Additional to that page_mapping() is used quite extensively in the mm
> > > code and I'm not sure if that isn't needed for other stuff as well.
> > Apologies, I'm honestly not quite sure how this lone patch here ended
> > up in this submission. I didn't want to send it out.
>
> No problem.
>
> But looking a bit deeper into the mm code that other drm drivers don't set
> this correctly and still use unmap_mapping_range() sounds like quite a bug
> to me.
>
> Going to track down what exactly that is used for.
Pagecache shootdown. unmap_mapping_range only shoots down from the virtual
side. Since that's all we care about, we don't need to set up the
address_space in the page.
-Daniel
>
> Christian.
>
> > -Daniel
> >
> > > Regards,
> > > Christian.
> > >
> > > > ---
> > > >drivers/gpu/drm/ttm/ttm_tt.c | 12
> > > >1 file changed, 12 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
> > > > index da9eeffe0c6d..5b2eb6d58bb7 100644
> > > > --- a/drivers/gpu/drm/ttm/ttm_tt.c
> > > > +++ b/drivers/gpu/drm/ttm/ttm_tt.c
> > > > @@ -284,17 +284,6 @@ int ttm_tt_swapout(struct ttm_bo_device *bdev,
> > > > struct ttm_tt *ttm)
> > > >return ret;
> > > >}
> > > >
> > > > -static void ttm_tt_add_mapping(struct ttm_bo_device *bdev, struct
> > > > ttm_tt *ttm)
> > > > -{
> > > > - pgoff_t i;
> > > > -
> > > > - if (ttm->page_flags & TTM_PAGE_FLAG_SG)
> > > > - return;
> > > > -
> > > > - for (i = 0; i < ttm->num_pages; ++i)
> > > > - ttm->pages[i]->mapping = bdev->dev_mapping;
> > > > -}
> > > > -
> > > >int ttm_tt_populate(struct ttm_bo_device *bdev,
> > > >struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
> > > >{
> > > > @@ -313,7 +302,6 @@ int ttm_tt_populate(struct ttm_bo_device *bdev,
> > > >if (ret)
> > > >return ret;
> > > >
> > > > - ttm_tt_add_mapping(bdev, ttm);
> > > >ttm->page_flags |= TTM_PAGE_FLAG_PRIV_POPULATED;
> > > >if (unlikely(ttm->page_flags & TTM_PAGE_FLAG_SWAPPED)) {
> > > >ret = ttm_tt_swapin(ttm);
> >
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI 1/3] drm/i915/gem: Remove incorrect early dbg print
Quoting Tvrtko Ursulin (2020-11-20 14:49:16) > > On 20/11/2020 14:03, Chris Wilson wrote: > > We print out the "logical" context support before we discover whether or > > not the engines have logical contexts. No one seems to have noticed the > > error, so the debug message must not be useful to anyone. > > I have, many months ago! :) No one, except Tvrtko, seems to have noticed... -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI 1/3] drm/i915/gem: Remove incorrect early dbg print
On 20/11/2020 14:03, Chris Wilson wrote:
We print out the "logical" context support before we discover whether or
not the engines have logical contexts. No one seems to have noticed the
error, so the debug message must not be useful to anyone.
I have, many months ago! :)
Regards,
Tvrtko
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 4fd38101bb56..a6299da64de4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -904,9 +904,6 @@ static void init_contexts(struct i915_gem_contexts *gc)
void i915_gem_init__contexts(struct drm_i915_private *i915)
{
init_contexts(>gem.contexts);
- drm_dbg(>drm, "%s context support initialized\n",
- DRIVER_CAPS(i915)->has_logical_contexts ?
- "logical" : "fake");
}
void i915_gem_driver_release__contexts(struct drm_i915_private *i915)
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Use correct lock for accessing guc->mmio_msg
On 20/11/2020 14:26, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2020-11-20 09:56:35)
>> From: Tvrtko Ursulin
>>
>> Guc->mmio_msg is set under the guc->irq_lock in guc_get_mmio_msg so it
>> should be consumed under the same lock from guc_handle_mmio_msg.
>>
>> I am not sure if the overall flow here makes complete sense but at least
>> the correct lock is now used.
>>
>> Signed-off-by: Tvrtko Ursulin
>> Cc: Daniele Ceraolo Spurio
>> ---
>> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 16 ++--
>> 1 file changed, 6 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> index 4e6070e95fe9..220626c3ad81 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> @@ -175,19 +175,15 @@ static void guc_get_mmio_msg(struct intel_guc *guc)
>>
>> static void guc_handle_mmio_msg(struct intel_guc *guc)
>> {
>> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>> -
>> /* we need communication to be enabled to reply to GuC */
>> GEM_BUG_ON(!guc_communication_enabled(guc));
>>
>> - if (!guc->mmio_msg)
>> - return;
>> -
>> - spin_lock_irq(>irq_lock);
>> - intel_guc_to_host_process_recv_msg(guc, >mmio_msg, 1);
>> - spin_unlock_irq(>irq_lock);
>> -
>> - guc->mmio_msg = 0;
>> + spin_lock_irq(>irq_lock);
>> + if (guc->mmio_msg) {
>> + intel_guc_to_host_process_recv_msg(guc, >mmio_msg, 1);
>> + guc->mmio_msg = 0;
>> + }
>> + spin_unlock_irq(>irq_lock);
>
> Based on just looking at mmio_msg, the locking should be guc->irq_lock, and
> guc->mmio_msg = 0 should be pulled under the lock.
>
> Reviewed-by: Chris Wilson
Thanks, the thing which made me say that I am not sure it completely makes
sense is that the mmio_msg appears to only be used from
guc_enable_communication and
guc_disable_communication, which I would assume should be mutually exclusive by
itself already. So I was not sure what value is there in the locking around
mmio_msg access.
And even in guc_enable_communication we have a sequence of:
guc_get_mmio_msg(guc);
guc_handle_mmio_msg(guc);
Which expands to:
static void guc_get_mmio_msg(struct intel_guc *guc)
{
u32 val;
spin_lock_irq(>irq_lock);
val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15));
guc->mmio_msg |= val & guc->msg_enabled_mask;
/*
* clear all events, including the ones we're not currently servicing,
* to make sure we don't try to process a stale message if we enable
* handling of more events later.
*/
guc_clear_mmio_msg(guc);
spin_unlock_irq(>irq_lock);
}
static void guc_handle_mmio_msg(struct intel_guc *guc)
{
/* we need communication to be enabled to reply to GuC */
GEM_BUG_ON(!guc_communication_enabled(guc));
spin_lock_irq(>irq_lock);
if (guc->mmio_msg) {
intel_guc_to_host_process_recv_msg(guc, >mmio_msg, 1);
guc->mmio_msg = 0;
}
spin_unlock_irq(>irq_lock);
}
So it seems a bit pointless. Nevertheless I only wanted to remove usage of
i915->irq_lock.
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/guc: Use correct lock for CT event handler
On 20/11/2020 14:32, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2020-11-20 09:56:36)
From: Tvrtko Ursulin
CT event handler is called under the gt->irq_lock from the interrupt
handling paths so make it the same from the init path. I don't think this
mismatch caused any functional issue but we need to wean the code of the
global i915->irq_lock.
ct_read definitely wants to be serialised. Is guc->irq_lock the right
choice?
Not under my understanding and also confirmed by Daniele off line.
Signed-off-by: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 220626c3ad81..6a0452815c41 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -203,7 +203,8 @@ static void guc_disable_interrupts(struct intel_guc *guc)
static int guc_enable_communication(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct drm_i915_private *i915 = gt->i915;
int ret;
GEM_BUG_ON(guc_communication_enabled(guc));
@@ -223,9 +224,9 @@ static int guc_enable_communication(struct intel_guc *guc)
guc_enable_interrupts(guc);
/* check for CT messages received before we enabled interrupts */
- spin_lock_irq(>irq_lock);
+ spin_lock_irq(>irq_lock);
intel_guc_ct_event_handler(>ct);
- spin_unlock_irq(>irq_lock);
+ spin_unlock_irq(>irq_lock);
You used guc->irq_lock in the previous patch. I suggest
intel_guc_ct_event_handler() should specify what lock it requires.
There are indeed too many locks and too little asserts to help the reader.
But the other end of the state ct_read needs is updated from the GuC
firmware itself, which then send the interrupt, which we process in:
guc_irq_handler
-> intel_guc_to_host_event_handler
-> intel_guc_ct_event_handler
And this side runs under the gt->irq_lock.
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/guc: Use correct lock for CT event handler
Quoting Tvrtko Ursulin (2020-11-20 09:56:36)
> From: Tvrtko Ursulin
>
> CT event handler is called under the gt->irq_lock from the interrupt
> handling paths so make it the same from the init path. I don't think this
> mismatch caused any functional issue but we need to wean the code of the
> global i915->irq_lock.
ct_read definitely wants to be serialised. Is guc->irq_lock the right
choice?
> Signed-off-by: Tvrtko Ursulin
> Cc: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 220626c3ad81..6a0452815c41 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -203,7 +203,8 @@ static void guc_disable_interrupts(struct intel_guc *guc)
>
> static int guc_enable_communication(struct intel_guc *guc)
> {
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> + struct intel_gt *gt = guc_to_gt(guc);
> + struct drm_i915_private *i915 = gt->i915;
> int ret;
>
> GEM_BUG_ON(guc_communication_enabled(guc));
> @@ -223,9 +224,9 @@ static int guc_enable_communication(struct intel_guc *guc)
> guc_enable_interrupts(guc);
>
> /* check for CT messages received before we enabled interrupts */
> - spin_lock_irq(>irq_lock);
> + spin_lock_irq(>irq_lock);
> intel_guc_ct_event_handler(>ct);
> - spin_unlock_irq(>irq_lock);
> + spin_unlock_irq(>irq_lock);
You used guc->irq_lock in the previous patch. I suggest
intel_guc_ct_event_handler() should specify what lock it requires.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Use correct lock for accessing guc->mmio_msg
Quoting Tvrtko Ursulin (2020-11-20 09:56:35)
> From: Tvrtko Ursulin
>
> Guc->mmio_msg is set under the guc->irq_lock in guc_get_mmio_msg so it
> should be consumed under the same lock from guc_handle_mmio_msg.
>
> I am not sure if the overall flow here makes complete sense but at least
> the correct lock is now used.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 16 ++--
> 1 file changed, 6 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 4e6070e95fe9..220626c3ad81 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -175,19 +175,15 @@ static void guc_get_mmio_msg(struct intel_guc *guc)
>
> static void guc_handle_mmio_msg(struct intel_guc *guc)
> {
> - struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> -
> /* we need communication to be enabled to reply to GuC */
> GEM_BUG_ON(!guc_communication_enabled(guc));
>
> - if (!guc->mmio_msg)
> - return;
> -
> - spin_lock_irq(>irq_lock);
> - intel_guc_to_host_process_recv_msg(guc, >mmio_msg, 1);
> - spin_unlock_irq(>irq_lock);
> -
> - guc->mmio_msg = 0;
> + spin_lock_irq(>irq_lock);
> + if (guc->mmio_msg) {
> + intel_guc_to_host_process_recv_msg(guc, >mmio_msg, 1);
> + guc->mmio_msg = 0;
> + }
> + spin_unlock_irq(>irq_lock);
Based on just looking at mmio_msg, the locking should be guc->irq_lock, and
guc->mmio_msg = 0 should be pulled under the lock.
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/guc: Use correct lock for accessing guc->mmio_msg
== Series Details == Series: series starting with [1/2] drm/i915/guc: Use correct lock for accessing guc->mmio_msg URL : https://patchwork.freedesktop.org/series/84100/ State : success == Summary == CI Bug Log - changes from CI_DRM_9370 -> Patchwork_18950 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/index.html New tests - New tests have been introduced between CI_DRM_9370 and Patchwork_18950: ### New CI tests (1) ### * boot: - Statuses : 41 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18950 that come from known issues: ### IGT changes ### Issues hit * igt@core_hotunplug@unbind-rebind: - fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html * igt@i915_module_load@reload: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/fi-icl-u2/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/fi-icl-u2/igt@i915_module_l...@reload.html - fi-icl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/fi-icl-y/igt@i915_module_l...@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/fi-icl-y/igt@i915_module_l...@reload.html * igt@i915_selftest@live@execlists: - fi-cml-s: [PASS][7] -> [INCOMPLETE][8] ([i915#1037]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/fi-cml-s/igt@i915_selftest@l...@execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/fi-cml-s/igt@i915_selftest@l...@execlists.html Possible fixes * igt@i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [DMESG-WARN][11] ([i915#1982] / [i915#262]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-apl-guc: [DMESG-WARN][13] ([i915#1635] / [i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/fi-apl-guc/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/fi-apl-guc/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9370/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html [i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 Participating hosts (45 -> 41) -- Additional (1): fi-tgl-y Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_9370 -> Patchwork_18950 CI-20190529: 20190529 CI_DRM_9370: e74e64a27fb256d20dc574e0eb741ca59630747d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5863: 849de1780d33c6749e0a26dc3c642eb9b3d6cd42 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18950: cd580a4110745957039f7da8f13ac93093f9d681 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == cd580a411074 drm/i915/guc: Use correct lock for CT event handler 19ea2e77b317 drm/i915/guc: Use correct lock for accessing guc->mmio_msg == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18950/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/3] drm/i915/gem: Remove incorrect early dbg print
We print out the "logical" context support before we discover whether or
not the engines have logical contexts. No one seems to have noticed the
error, so the debug message must not be useful to anyone.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 4fd38101bb56..a6299da64de4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -904,9 +904,6 @@ static void init_contexts(struct i915_gem_contexts *gc)
void i915_gem_init__contexts(struct drm_i915_private *i915)
{
init_contexts(>gem.contexts);
- drm_dbg(>drm, "%s context support initialized\n",
- DRIVER_CAPS(i915)->has_logical_contexts ?
- "logical" : "fake");
}
void i915_gem_driver_release__contexts(struct drm_i915_private *i915)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/3] drm/i915/selftests: Improve granularity for mocs reset checks
Allow us to validate mocs configurations after reset if we have either
engine or global reset.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/selftest_mocs.c | 40 +
1 file changed, 21 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c
b/drivers/gpu/drm/i915/gt/selftest_mocs.c
index b25eba50c88e..21dcd91cbd62 100644
--- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -361,29 +361,34 @@ static int active_engine_reset(struct intel_context *ce,
static int __live_mocs_reset(struct live_mocs *mocs,
struct intel_context *ce)
{
+ struct intel_gt *gt = ce->engine->gt;
int err;
- err = intel_engine_reset(ce->engine, "mocs");
- if (err)
- return err;
+ if (intel_has_reset_engine(gt)) {
+ err = intel_engine_reset(ce->engine, "mocs");
+ if (err)
+ return err;
- err = check_mocs_engine(mocs, ce);
- if (err)
- return err;
+ err = check_mocs_engine(mocs, ce);
+ if (err)
+ return err;
- err = active_engine_reset(ce, "mocs");
- if (err)
- return err;
+ err = active_engine_reset(ce, "mocs");
+ if (err)
+ return err;
- err = check_mocs_engine(mocs, ce);
- if (err)
- return err;
+ err = check_mocs_engine(mocs, ce);
+ if (err)
+ return err;
+ }
- intel_gt_reset(ce->engine->gt, ce->engine->mask, "mocs");
+ if (intel_has_gpu_reset(gt)) {
+ intel_gt_reset(gt, ce->engine->mask, "mocs");
- err = check_mocs_engine(mocs, ce);
- if (err)
- return err;
+ err = check_mocs_engine(mocs, ce);
+ if (err)
+ return err;
+ }
return 0;
}
@@ -398,9 +403,6 @@ static int live_mocs_reset(void *arg)
/* Check the mocs setup is retained over per-engine and global resets */
- if (!intel_has_reset_engine(gt))
- return 0;
-
err = live_mocs_init(, gt);
if (err)
return err;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 3/3] drm/i915/selftests: Small tweak to put the termination conditions together
If we run out of ring space, or exceed the desired runtime, we wish to
stop the subtest. Put these checks together, so that we always keep the
requests flushed on completion.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c
b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index 2edf2b15885f..ef7e3ce8c60c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -1090,12 +1090,6 @@ static int live_hwsp_read(void *arg)
}
count++;
- if (8 * watcher[1].rq->ring->emit >
- 3 * watcher[1].rq->ring->size) {
- i915_request_put(rq);
- break;
- }
-
/* Flush the timeline before manually wrapping again */
if (i915_request_wait(rq,
I915_WAIT_INTERRUPTIBLE,
@@ -1104,9 +1098,13 @@ static int live_hwsp_read(void *arg)
i915_request_put(rq);
goto out;
}
-
retire_requests(tl);
i915_request_put(rq);
+
+ if (8 * watcher[1].rq->ring->emit >
+ 3 * watcher[1].rq->ring->size)
+ break;
+
} while (!__igt_timeout(end_time, NULL));
WRITE_ONCE(*(u32 *)tl->hwsp_seqno, 0xdeadbeef);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] locking/selftests: Add testcases for fs_reclaim
On Fri, Nov 20, 2020 at 10:54:44AM +0100, Daniel Vetter wrote: > Since I butchered this I figured better to make sure we have testcases > for this now. Since we only have a locking context for __GFP_FS that's > the only thing we're testing right now. > > Cc: linux-fsde...@vger.kernel.org > Cc: Dave Chinner > Cc: Qian Cai > Cc: linux-...@vger.kernel.org > Cc: Thomas Hellström (Intel) > Cc: Andrew Morton > Cc: Jason Gunthorpe > Cc: linux...@kvack.org > Cc: linux-r...@vger.kernel.org > Cc: Maarten Lankhorst > Cc: Christian König > Cc: "Matthew Wilcox (Oracle)" > Signed-off-by: Daniel Vetter > Cc: Peter Zijlstra > Cc: Ingo Molnar > Cc: Will Deacon > Cc: linux-ker...@vger.kernel.org > --- > lib/locking-selftest.c | 47 ++ > 1 file changed, 47 insertions(+) I have a few changes pending for this file, I don't think the conflicts will be bad, but.. In any case: Acked-by: Peter Zijlstra (Intel) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gt: Plug IPS into intel_rps_set
Chris Wilson writes:
> The old IPS interface did not match the RPS interface that we tried to
> plug it into (bool vs int return). Once repaired, our minimal
> selftesting is finally happy!
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 34 +++--
> 1 file changed, 22 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 0d88f17799ff..b13e7845d483 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -400,7 +400,7 @@ static unsigned int gen5_invert_freq(struct intel_rps
> *rps,
> return val;
> }
>
> -static bool gen5_rps_set(struct intel_rps *rps, u8 val)
> +static int __gen5_rps_set(struct intel_rps *rps, u8 val)
> {
> struct intel_uncore *uncore = rps_to_uncore(rps);
> u16 rgvswctl;
> @@ -410,7 +410,7 @@ static bool gen5_rps_set(struct intel_rps *rps, u8 val)
> rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
> if (rgvswctl & MEMCTL_CMD_STS) {
> DRM_DEBUG("gpu busy, RCS change rejected\n");
> - return false; /* still busy with another command */
> + return -EBUSY; /* still busy with another command */
> }
>
> /* Invert the frequency bin into an ips delay */
> @@ -426,7 +426,18 @@ static bool gen5_rps_set(struct intel_rps *rps, u8 val)
> rgvswctl |= MEMCTL_CMD_STS;
> intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);
>
> - return true;
> + return 0;
> +}
> +
> +static int gen5_rps_set(struct intel_rps *rps, u8 val)
> +{
> + int err;
> +
> + spin_lock_irq(_lock);
> + err = __gen5_rps_set(rps, val);
> + spin_unlock_irq(_lock);
> +
> + return err;
> }
>
> static unsigned long intel_pxfreq(u32 vidfreq)
> @@ -557,7 +568,7 @@ static bool gen5_rps_enable(struct intel_rps *rps)
> "stuck trying to change perf mode\n");
> mdelay(1);
>
> - gen5_rps_set(rps, rps->cur_freq);
> + __gen5_rps_set(rps, rps->cur_freq);
>
> rps->ips.last_count1 = intel_uncore_read(uncore, DMIEC);
> rps->ips.last_count1 += intel_uncore_read(uncore, DDREC);
> @@ -599,7 +610,7 @@ static void gen5_rps_disable(struct intel_rps *rps)
> intel_uncore_write(uncore, MEMINTRSTS, MEMINT_EVAL_CHG);
>
> /* Go back to the starting frequency */
> - gen5_rps_set(rps, rps->idle_freq);
> + __gen5_rps_set(rps, rps->idle_freq);
> mdelay(1);
> rgvswctl |= MEMCTL_CMD_STS;
> intel_uncore_write(uncore, MEMSWCTL, rgvswctl);
> @@ -797,20 +808,19 @@ static int rps_set(struct intel_rps *rps, u8 val, bool
> update)
> struct drm_i915_private *i915 = rps_to_i915(rps);
> int err;
>
> - if (INTEL_GEN(i915) < 6)
> - return 0;
> -
> if (val == rps->last_freq)
> return 0;
>
> if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> err = vlv_rps_set(rps, val);
> - else
> + else if (INTEL_GEN(i915) >= 6)
> err = gen6_rps_set(rps, val);
> + else
> + err = gen5_rps_set(rps, val);
> if (err)
> return err;
>
> - if (update)
> + if (update && INTEL_GEN(i915) >= 6)
> gen6_rps_set_thresholds(rps, val);
> rps->last_freq = val;
>
> @@ -1794,7 +1804,7 @@ void gen5_rps_irq_handler(struct intel_rps *rps)
>rps->min_freq_softlimit,
>rps->max_freq_softlimit);
>
> - if (new_freq != rps->cur_freq && gen5_rps_set(rps, new_freq))
> + if (new_freq != rps->cur_freq && !__gen5_rps_set(rps, new_freq))
> rps->cur_freq = new_freq;
>
> spin_unlock(_lock);
> @@ -2105,7 +2115,7 @@ bool i915_gpu_turbo_disable(void)
>
> spin_lock_irq(_lock);
> rps->max_freq_softlimit = rps->min_freq;
> - ret = gen5_rps_set(>gt.rps, rps->min_freq);
> + ret = !__gen5_rps_set(>gt.rps, rps->min_freq);
> spin_unlock_irq(_lock);
>
> drm_dev_put(>drm);
> --
> 2.20.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/ttm: don't set page->mapping
== Series Details == Series: drm/ttm: don't set page->mapping URL : https://patchwork.freedesktop.org/series/84098/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9367 -> Patchwork_18949 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18949 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18949, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18949/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18949: ### IGT changes ### Possible regressions * igt@i915_selftest@live@hangcheck: - fi-bsw-nick:[PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-bsw-nick/igt@i915_selftest@l...@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18949/fi-bsw-nick/igt@i915_selftest@l...@hangcheck.html New tests - New tests have been introduced between CI_DRM_9367 and Patchwork_18949: ### New CI tests (1) ### * boot: - Statuses : 41 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_18949 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@basic-pci-d3-state: - fi-glk-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-glk-dsi/igt@i915_pm_...@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18949/fi-glk-dsi/igt@i915_pm_...@basic-pci-d3-state.html - fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-byt-j1900/igt@i915_pm_...@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18949/fi-byt-j1900/igt@i915_pm_...@basic-pci-d3-state.html * igt@kms_busy@basic@flip: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-tgl-y/igt@kms_busy@ba...@flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18949/fi-tgl-y/igt@kms_busy@ba...@flip.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18949/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@prime_vgem@basic-read: - fi-tgl-y: [PASS][11] -> [DMESG-WARN][12] ([i915#402]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-tgl-y/igt@prime_v...@basic-read.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18949/fi-tgl-y/igt@prime_v...@basic-read.html Possible fixes * igt@core_hotunplug@unbind-rebind: - fi-tgl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18949/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html * igt@i915_module_load@reload: - fi-icl-y: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-icl-y/igt@i915_module_l...@reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18949/fi-icl-y/igt@i915_module_l...@reload.html * igt@kms_chamelium@dp-crc-fast: - fi-cml-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18949/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-j1900: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18949/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_psr@primary_page_flip: - fi-tgl-y: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9367/fi-tgl-y/igt@kms_psr@primary_page_flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18949/fi-tgl-y/igt@kms_psr@primary_page_flip.html *
Re: [Intel-gfx] [PATCH v4 0/7] Convert the intel iommu driver to the dma-iommu api
On 2020/11/3 18:54, Joerg Roedel wrote: Hi, On Tue, Nov 03, 2020 at 11:58:26AM +0200, Joonas Lahtinen wrote: Would that work for you? We intend to send the feature pull requests to DRM for 5.11 in the upcoming weeks. For the IOMMU side it is best to include the workaround for now. When the DRM fixes are merged into v5.11-rc1 together with this conversion, it can be reverted and will not be in 5.11-final. Okay! So I will keep the workaround and send a new version (mostly rebase) to Will. Best regards, baolu ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/ttm: don't set page->mapping
== Series Details == Series: drm/ttm: don't set page->mapping URL : https://patchwork.freedesktop.org/series/84098/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/ttm: don't set page->mapping
== Series Details ==
Series: drm/ttm: don't set page->mapping
URL : https://patchwork.freedesktop.org/series/84098/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cd6a3ea2fee2 mm: Track mmu notifiers in fs_reclaim_acquire/release
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 23b68395c7c7 ("mm/mmu_notifiers:
add a lockdep map for invalidate_range_start/end")'
#12:
recursions we do have lockdep annotations since 23b68395c7c7
-:41: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 66204f1d2d1b ("mm/mmu_notifiers:
prime lockdep")'
#41:
With this we can also remove the lockdep priming added in 66204f1d2d1b
-:57: WARNING:BAD_SIGN_OFF: email address 'Thomas Hellström (Intel)
' might be better as '"Thomas Hellström"(Intel)
'
#57:
Cc: Thomas Hellström (Intel)
-:137: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#137: FILE: mm/page_alloc.c:4307:
+
+ }
-:153: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by:
Daniel Vetter '
total: 2 errors, 2 warnings, 1 checks, 74 lines checked
6b4f92676139 mm: Extract might_alloc() debug check
-:122: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by:
Daniel Vetter '
total: 0 errors, 1 warnings, 0 checks, 51 lines checked
872ca8a3a4ac locking/selftests: Add testcases for fs_reclaim
-:17: WARNING:BAD_SIGN_OFF: email address 'Thomas Hellström (Intel)
' might be better as '"Thomas Hellström"(Intel)
'
#17:
Cc: Thomas Hellström (Intel)
-:74: WARNING:PRINTK_WITHOUT_KERN_LEVEL: printk() should include KERN_
facility level
#74: FILE: lib/locking-selftest.c:2388:
+ printk(" \n");
-:75: WARNING:PRINTK_WITHOUT_KERN_LEVEL: printk() should include KERN_
facility level
#75: FILE: lib/locking-selftest.c:2389:
+ printk(" | fs_reclaim tests |\n");
-:76: WARNING:PRINTK_WITHOUT_KERN_LEVEL: printk() should include KERN_
facility level
#76: FILE: lib/locking-selftest.c:2390:
+ printk(" \n");
-:80: WARNING:LOGGING_CONTINUATION: Avoid logging continuation uses where
feasible
#80: FILE: lib/locking-selftest.c:2394:
+ pr_cont("\n");
-:84: WARNING:LOGGING_CONTINUATION: Avoid logging continuation uses where
feasible
#84: FILE: lib/locking-selftest.c:2398:
+ pr_cont("\n");
-:88: WARNING:LOGGING_CONTINUATION: Avoid logging continuation uses where
feasible
#88: FILE: lib/locking-selftest.c:2402:
+ pr_cont("\n");
-:102: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by:
Daniel Vetter '
total: 0 errors, 8 warnings, 0 checks, 65 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/ttm: don't set page->mapping
Am 20.11.20 um 11:05 schrieb Daniel Vetter:
On Fri, Nov 20, 2020 at 11:04 AM Christian König
wrote:
Am 20.11.20 um 10:54 schrieb Daniel Vetter:
Random observation while trying to review Christian's patch series to
stop looking at struct page for dma-buf imports.
This was originally added in
commit 58aa6622d32af7d2c08d45085f44c54554a16ed7
Author: Thomas Hellstrom
Date: Fri Jan 3 11:47:23 2014 +0100
drm/ttm: Correctly set page mapping and -index members
Needed for some vm operations; most notably unmap_mapping_range() with
even_cows = 0.
Signed-off-by: Thomas Hellstrom
Reviewed-by: Brian Paul
but we do not have a single caller of unmap_mapping_range with
even_cows == 0. And all the gem drivers don't do this, so another
small thing we could standardize between drm and ttm drivers.
Plus I don't really see a need for unamp_mapping_range where we don't
want to indiscriminately shoot down all ptes.
Cc: Thomas Hellstrom
Cc: Brian Paul
Signed-off-by: Daniel Vetter
Cc: Christian Koenig
Cc: Huang Rui
This is still a NAK as long as we can't come up with a better way to
track TTMs page allocations.
Additional to that page_mapping() is used quite extensively in the mm
code and I'm not sure if that isn't needed for other stuff as well.
Apologies, I'm honestly not quite sure how this lone patch here ended
up in this submission. I didn't want to send it out.
No problem.
But looking a bit deeper into the mm code that other drm drivers don't
set this correctly and still use unmap_mapping_range() sounds like quite
a bug to me.
Going to track down what exactly that is used for.
Christian.
-Daniel
Regards,
Christian.
---
drivers/gpu/drm/ttm/ttm_tt.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index da9eeffe0c6d..5b2eb6d58bb7 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -284,17 +284,6 @@ int ttm_tt_swapout(struct ttm_bo_device *bdev, struct
ttm_tt *ttm)
return ret;
}
-static void ttm_tt_add_mapping(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
-{
- pgoff_t i;
-
- if (ttm->page_flags & TTM_PAGE_FLAG_SG)
- return;
-
- for (i = 0; i < ttm->num_pages; ++i)
- ttm->pages[i]->mapping = bdev->dev_mapping;
-}
-
int ttm_tt_populate(struct ttm_bo_device *bdev,
struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
{
@@ -313,7 +302,6 @@ int ttm_tt_populate(struct ttm_bo_device *bdev,
if (ret)
return ret;
- ttm_tt_add_mapping(bdev, ttm);
ttm->page_flags |= TTM_PAGE_FLAG_PRIV_POPULATED;
if (unlikely(ttm->page_flags & TTM_PAGE_FLAG_SWAPPED)) {
ret = ttm_tt_swapin(ttm);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/ttm: don't set page->mapping
On Fri, Nov 20, 2020 at 11:04 AM Christian König
wrote:
>
> Am 20.11.20 um 10:54 schrieb Daniel Vetter:
> > Random observation while trying to review Christian's patch series to
> > stop looking at struct page for dma-buf imports.
> >
> > This was originally added in
> >
> > commit 58aa6622d32af7d2c08d45085f44c54554a16ed7
> > Author: Thomas Hellstrom
> > Date: Fri Jan 3 11:47:23 2014 +0100
> >
> > drm/ttm: Correctly set page mapping and -index members
> >
> > Needed for some vm operations; most notably unmap_mapping_range() with
> > even_cows = 0.
> >
> > Signed-off-by: Thomas Hellstrom
> > Reviewed-by: Brian Paul
> >
> > but we do not have a single caller of unmap_mapping_range with
> > even_cows == 0. And all the gem drivers don't do this, so another
> > small thing we could standardize between drm and ttm drivers.
> >
> > Plus I don't really see a need for unamp_mapping_range where we don't
> > want to indiscriminately shoot down all ptes.
> >
> > Cc: Thomas Hellstrom
> > Cc: Brian Paul
> > Signed-off-by: Daniel Vetter
> > Cc: Christian Koenig
> > Cc: Huang Rui
>
> This is still a NAK as long as we can't come up with a better way to
> track TTMs page allocations.
>
> Additional to that page_mapping() is used quite extensively in the mm
> code and I'm not sure if that isn't needed for other stuff as well.
Apologies, I'm honestly not quite sure how this lone patch here ended
up in this submission. I didn't want to send it out.
-Daniel
>
> Regards,
> Christian.
>
> > ---
> > drivers/gpu/drm/ttm/ttm_tt.c | 12
> > 1 file changed, 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
> > index da9eeffe0c6d..5b2eb6d58bb7 100644
> > --- a/drivers/gpu/drm/ttm/ttm_tt.c
> > +++ b/drivers/gpu/drm/ttm/ttm_tt.c
> > @@ -284,17 +284,6 @@ int ttm_tt_swapout(struct ttm_bo_device *bdev, struct
> > ttm_tt *ttm)
> > return ret;
> > }
> >
> > -static void ttm_tt_add_mapping(struct ttm_bo_device *bdev, struct ttm_tt
> > *ttm)
> > -{
> > - pgoff_t i;
> > -
> > - if (ttm->page_flags & TTM_PAGE_FLAG_SG)
> > - return;
> > -
> > - for (i = 0; i < ttm->num_pages; ++i)
> > - ttm->pages[i]->mapping = bdev->dev_mapping;
> > -}
> > -
> > int ttm_tt_populate(struct ttm_bo_device *bdev,
> > struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
> > {
> > @@ -313,7 +302,6 @@ int ttm_tt_populate(struct ttm_bo_device *bdev,
> > if (ret)
> > return ret;
> >
> > - ttm_tt_add_mapping(bdev, ttm);
> > ttm->page_flags |= TTM_PAGE_FLAG_PRIV_POPULATED;
> > if (unlikely(ttm->page_flags & TTM_PAGE_FLAG_SWAPPED)) {
> > ret = ttm_tt_swapin(ttm);
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/ttm: don't set page->mapping
Am 20.11.20 um 10:54 schrieb Daniel Vetter:
Random observation while trying to review Christian's patch series to
stop looking at struct page for dma-buf imports.
This was originally added in
commit 58aa6622d32af7d2c08d45085f44c54554a16ed7
Author: Thomas Hellstrom
Date: Fri Jan 3 11:47:23 2014 +0100
drm/ttm: Correctly set page mapping and -index members
Needed for some vm operations; most notably unmap_mapping_range() with
even_cows = 0.
Signed-off-by: Thomas Hellstrom
Reviewed-by: Brian Paul
but we do not have a single caller of unmap_mapping_range with
even_cows == 0. And all the gem drivers don't do this, so another
small thing we could standardize between drm and ttm drivers.
Plus I don't really see a need for unamp_mapping_range where we don't
want to indiscriminately shoot down all ptes.
Cc: Thomas Hellstrom
Cc: Brian Paul
Signed-off-by: Daniel Vetter
Cc: Christian Koenig
Cc: Huang Rui
This is still a NAK as long as we can't come up with a better way to
track TTMs page allocations.
Additional to that page_mapping() is used quite extensively in the mm
code and I'm not sure if that isn't needed for other stuff as well.
Regards,
Christian.
---
drivers/gpu/drm/ttm/ttm_tt.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index da9eeffe0c6d..5b2eb6d58bb7 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -284,17 +284,6 @@ int ttm_tt_swapout(struct ttm_bo_device *bdev, struct
ttm_tt *ttm)
return ret;
}
-static void ttm_tt_add_mapping(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
-{
- pgoff_t i;
-
- if (ttm->page_flags & TTM_PAGE_FLAG_SG)
- return;
-
- for (i = 0; i < ttm->num_pages; ++i)
- ttm->pages[i]->mapping = bdev->dev_mapping;
-}
-
int ttm_tt_populate(struct ttm_bo_device *bdev,
struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
{
@@ -313,7 +302,6 @@ int ttm_tt_populate(struct ttm_bo_device *bdev,
if (ret)
return ret;
- ttm_tt_add_mapping(bdev, ttm);
ttm->page_flags |= TTM_PAGE_FLAG_PRIV_POPULATED;
if (unlikely(ttm->page_flags & TTM_PAGE_FLAG_SWAPPED)) {
ret = ttm_tt_swapin(ttm);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/guc: Use correct lock for CT event handler
From: Tvrtko Ursulin
CT event handler is called under the gt->irq_lock from the interrupt
handling paths so make it the same from the init path. I don't think this
mismatch caused any functional issue but we need to wean the code of the
global i915->irq_lock.
Signed-off-by: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 220626c3ad81..6a0452815c41 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -203,7 +203,8 @@ static void guc_disable_interrupts(struct intel_guc *guc)
static int guc_enable_communication(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct drm_i915_private *i915 = gt->i915;
int ret;
GEM_BUG_ON(guc_communication_enabled(guc));
@@ -223,9 +224,9 @@ static int guc_enable_communication(struct intel_guc *guc)
guc_enable_interrupts(guc);
/* check for CT messages received before we enabled interrupts */
- spin_lock_irq(>irq_lock);
+ spin_lock_irq(>irq_lock);
intel_guc_ct_event_handler(>ct);
- spin_unlock_irq(>irq_lock);
+ spin_unlock_irq(>irq_lock);
drm_dbg(>drm, "GuC communication enabled\n");
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/guc: Use correct lock for accessing guc->mmio_msg
From: Tvrtko Ursulin
Guc->mmio_msg is set under the guc->irq_lock in guc_get_mmio_msg so it
should be consumed under the same lock from guc_handle_mmio_msg.
I am not sure if the overall flow here makes complete sense but at least
the correct lock is now used.
Signed-off-by: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 4e6070e95fe9..220626c3ad81 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -175,19 +175,15 @@ static void guc_get_mmio_msg(struct intel_guc *guc)
static void guc_handle_mmio_msg(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
-
/* we need communication to be enabled to reply to GuC */
GEM_BUG_ON(!guc_communication_enabled(guc));
- if (!guc->mmio_msg)
- return;
-
- spin_lock_irq(>irq_lock);
- intel_guc_to_host_process_recv_msg(guc, >mmio_msg, 1);
- spin_unlock_irq(>irq_lock);
-
- guc->mmio_msg = 0;
+ spin_lock_irq(>irq_lock);
+ if (guc->mmio_msg) {
+ intel_guc_to_host_process_recv_msg(guc, >mmio_msg, 1);
+ guc->mmio_msg = 0;
+ }
+ spin_unlock_irq(>irq_lock);
}
static void guc_reset_interrupts(struct intel_guc *guc)
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/ttm: don't set page->mapping
Random observation while trying to review Christian's patch series to
stop looking at struct page for dma-buf imports.
This was originally added in
commit 58aa6622d32af7d2c08d45085f44c54554a16ed7
Author: Thomas Hellstrom
Date: Fri Jan 3 11:47:23 2014 +0100
drm/ttm: Correctly set page mapping and -index members
Needed for some vm operations; most notably unmap_mapping_range() with
even_cows = 0.
Signed-off-by: Thomas Hellstrom
Reviewed-by: Brian Paul
but we do not have a single caller of unmap_mapping_range with
even_cows == 0. And all the gem drivers don't do this, so another
small thing we could standardize between drm and ttm drivers.
Plus I don't really see a need for unamp_mapping_range where we don't
want to indiscriminately shoot down all ptes.
Cc: Thomas Hellstrom
Cc: Brian Paul
Signed-off-by: Daniel Vetter
Cc: Christian Koenig
Cc: Huang Rui
---
drivers/gpu/drm/ttm/ttm_tt.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index da9eeffe0c6d..5b2eb6d58bb7 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -284,17 +284,6 @@ int ttm_tt_swapout(struct ttm_bo_device *bdev, struct
ttm_tt *ttm)
return ret;
}
-static void ttm_tt_add_mapping(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
-{
- pgoff_t i;
-
- if (ttm->page_flags & TTM_PAGE_FLAG_SG)
- return;
-
- for (i = 0; i < ttm->num_pages; ++i)
- ttm->pages[i]->mapping = bdev->dev_mapping;
-}
-
int ttm_tt_populate(struct ttm_bo_device *bdev,
struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
{
@@ -313,7 +302,6 @@ int ttm_tt_populate(struct ttm_bo_device *bdev,
if (ret)
return ret;
- ttm_tt_add_mapping(bdev, ttm);
ttm->page_flags |= TTM_PAGE_FLAG_PRIV_POPULATED;
if (unlikely(ttm->page_flags & TTM_PAGE_FLAG_SWAPPED)) {
ret = ttm_tt_swapin(ttm);
--
2.29.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] locking/selftests: Add testcases for fs_reclaim
Since I butchered this I figured better to make sure we have testcases
for this now. Since we only have a locking context for __GFP_FS that's
the only thing we're testing right now.
Cc: linux-fsde...@vger.kernel.org
Cc: Dave Chinner
Cc: Qian Cai
Cc: linux-...@vger.kernel.org
Cc: Thomas Hellström (Intel)
Cc: Andrew Morton
Cc: Jason Gunthorpe
Cc: linux...@kvack.org
Cc: linux-r...@vger.kernel.org
Cc: Maarten Lankhorst
Cc: Christian König
Cc: "Matthew Wilcox (Oracle)"
Signed-off-by: Daniel Vetter
Cc: Peter Zijlstra
Cc: Ingo Molnar
Cc: Will Deacon
Cc: linux-ker...@vger.kernel.org
---
lib/locking-selftest.c | 47 ++
1 file changed, 47 insertions(+)
diff --git a/lib/locking-selftest.c b/lib/locking-selftest.c
index a899b3f0e2e5..ad47c3358e30 100644
--- a/lib/locking-selftest.c
+++ b/lib/locking-selftest.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2357,6 +2358,50 @@ static void queued_read_lock_tests(void)
pr_cont("\n");
}
+static void fs_reclaim_correct_nesting(void)
+{
+ fs_reclaim_acquire(GFP_KERNEL);
+ might_alloc(GFP_NOFS);
+ fs_reclaim_release(GFP_KERNEL);
+}
+
+static void fs_reclaim_wrong_nesting(void)
+{
+ fs_reclaim_acquire(GFP_KERNEL);
+ might_alloc(GFP_KERNEL);
+ fs_reclaim_release(GFP_KERNEL);
+}
+
+static void fs_reclaim_protected_nesting(void)
+{
+ unsigned int flags;
+
+ fs_reclaim_acquire(GFP_KERNEL);
+ flags = memalloc_nofs_save();
+ might_alloc(GFP_KERNEL);
+ memalloc_nofs_restore(flags);
+ fs_reclaim_release(GFP_KERNEL);
+}
+
+static void fs_reclaim_tests(void)
+{
+ printk(" \n");
+ printk(" | fs_reclaim tests |\n");
+ printk(" \n");
+
+ print_testname("correct nesting");
+ dotest(fs_reclaim_correct_nesting, SUCCESS, 0);
+ pr_cont("\n");
+
+ print_testname("wrong nesting");
+ dotest(fs_reclaim_wrong_nesting, FAILURE, 0);
+ pr_cont("\n");
+
+ print_testname("protected nesting");
+ dotest(fs_reclaim_protected_nesting, SUCCESS, 0);
+ pr_cont("\n");
+}
+
void locking_selftest(void)
{
/*
@@ -2478,6 +2523,8 @@ void locking_selftest(void)
if (IS_ENABLED(CONFIG_QUEUED_RWLOCKS))
queued_read_lock_tests();
+ fs_reclaim_tests();
+
if (unexpected_testcase_failures) {
printk("-\n");
debug_locks = 0;
--
2.29.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] mm: Extract might_alloc() debug check
Extracted from slab.h, which seems to have the most complete version
including the correct might_sleep() check. Roll it out to slob.c.
Motivated by a discussion with Paul about possibly changing call_rcu
behaviour to allocate memory, but only roughly every 500th call.
There are a lot fewer places in the kernel that care about whether
allocating memory is allowed or not (due to deadlocks with reclaim
code) than places that care whether sleeping is allowed. But debugging
these also tends to be a lot harder, so nice descriptive checks could
come in handy. I might have some use eventually for annotations in
drivers/gpu.
Note that unlike fs_reclaim_acquire/release gfpflags_allow_blocking
does not consult the PF_MEMALLOC flags. But there is no flag
equivalent for GFP_NOWAIT, hence this check can't go wrong due to
memalloc_no*_save/restore contexts. Willy is working on a patch series
which might change this:
https://lore.kernel.org/linux-mm/20200625113122.7540-7-wi...@infradead.org/
I think best would be if that updates gfpflags_allow_blocking(), since
there's a ton of callers all over the place for that already.
Acked-by: Vlastimil Babka
Acked-by: Paul E. McKenney
Cc: Paul E. McKenney
Cc: Christoph Lameter
Cc: Pekka Enberg
Cc: David Rientjes
Cc: Joonsoo Kim
Cc: Andrew Morton
Cc: Peter Zijlstra
Cc: Ingo Molnar
Cc: Vlastimil Babka
Cc: Mathieu Desnoyers
Cc: Sebastian Andrzej Siewior
Cc: Michel Lespinasse
Cc: Daniel Vetter
Cc: Waiman Long
Cc: Thomas Gleixner
Cc: Randy Dunlap
Cc: linux...@kvack.org
Cc: linux-fsde...@vger.kernel.org
Cc: Dave Chinner
Cc: Qian Cai
Cc: linux-...@vger.kernel.org
Cc: "Matthew Wilcox (Oracle)"
Signed-off-by: Daniel Vetter
---
include/linux/sched/mm.h | 16
mm/slab.h| 5 +
mm/slob.c| 6 ++
3 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/include/linux/sched/mm.h b/include/linux/sched/mm.h
index d5ece7a9a403..f94405d43fd1 100644
--- a/include/linux/sched/mm.h
+++ b/include/linux/sched/mm.h
@@ -180,6 +180,22 @@ static inline void fs_reclaim_acquire(gfp_t gfp_mask) { }
static inline void fs_reclaim_release(gfp_t gfp_mask) { }
#endif
+/**
+ * might_alloc - Marks possible allocation sites
+ * @gfp_mask: gfp_t flags that would be use to allocate
+ *
+ * Similar to might_sleep() and other annotations this can be used in functions
+ * that might allocate, but often dont. Compiles to nothing without
+ * CONFIG_LOCKDEP. Includes a conditional might_sleep() if @gfp allows
blocking.
+ */
+static inline void might_alloc(gfp_t gfp_mask)
+{
+ fs_reclaim_acquire(gfp_mask);
+ fs_reclaim_release(gfp_mask);
+
+ might_sleep_if(gfpflags_allow_blocking(gfp_mask));
+}
+
/**
* memalloc_noio_save - Marks implicit GFP_NOIO allocation scope.
*
diff --git a/mm/slab.h b/mm/slab.h
index 6d7c6a5056ba..37b981247e5d 100644
--- a/mm/slab.h
+++ b/mm/slab.h
@@ -500,10 +500,7 @@ static inline struct kmem_cache
*slab_pre_alloc_hook(struct kmem_cache *s,
{
flags &= gfp_allowed_mask;
- fs_reclaim_acquire(flags);
- fs_reclaim_release(flags);
-
- might_sleep_if(gfpflags_allow_blocking(flags));
+ might_alloc(flags);
if (should_failslab(s, flags))
return NULL;
diff --git a/mm/slob.c b/mm/slob.c
index 7cc9805c8091..8d4bfa46247f 100644
--- a/mm/slob.c
+++ b/mm/slob.c
@@ -474,8 +474,7 @@ __do_kmalloc_node(size_t size, gfp_t gfp, int node,
unsigned long caller)
gfp &= gfp_allowed_mask;
- fs_reclaim_acquire(gfp);
- fs_reclaim_release(gfp);
+ might_alloc(gfp);
if (size < PAGE_SIZE - minalign) {
int align = minalign;
@@ -597,8 +596,7 @@ static void *slob_alloc_node(struct kmem_cache *c, gfp_t
flags, int node)
flags &= gfp_allowed_mask;
- fs_reclaim_acquire(flags);
- fs_reclaim_release(flags);
+ might_alloc(flags);
if (c->size < PAGE_SIZE) {
b = slob_alloc(c->size, flags, c->align, node, 0);
--
2.29.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] mm: Track mmu notifiers in fs_reclaim_acquire/release
fs_reclaim_acquire/release nicely catch recursion issues when
allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend
to use to keep the excessive caches in check). For mmu notifier
recursions we do have lockdep annotations since 23b68395c7c7
("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end").
But these only fire if a path actually results in some pte
invalidation - for most small allocations that's very rarely the case.
The other trouble is that pte invalidation can happen any time when
__GFP_RECLAIM is set. Which means only really GFP_ATOMIC is a safe
choice, GFP_NOIO isn't good enough to avoid potential mmu notifier
recursion.
I was pondering whether we should just do the general annotation, but
there's always the risk for false positives. Plus I'm assuming that
the core fs and io code is a lot better reviewed and tested than
random mmu notifier code in drivers. Hence why I decide to only
annotate for that specific case.
Furthermore even if we'd create a lockdep map for direct reclaim, we'd
still need to explicit pull in the mmu notifier map - there's a lot
more places that do pte invalidation than just direct reclaim, these
two contexts arent the same.
Note that the mmu notifiers needing their own independent lockdep map
is also the reason we can't hold them from fs_reclaim_acquire to
fs_reclaim_release - it would nest with the acquistion in the pte
invalidation code, causing a lockdep splat. And we can't remove the
annotations from pte invalidation and all the other places since
they're called from many other places than page reclaim. Hence we can
only do the equivalent of might_lock, but on the raw lockdep map.
With this we can also remove the lockdep priming added in 66204f1d2d1b
("mm/mmu_notifiers: prime lockdep") since the new annotations are
strictly more powerful.
v2: Review from Thomas Hellstrom:
- unbotch the fs_reclaim context check, I accidentally inverted it,
but it didn't blow up because I inverted it immediately
- fix compiling for !CONFIG_MMU_NOTIFIER
v3: Unbreak the PF_MEMALLOC_ context flags. Thanks to Qian for the
report and Dave for explaining what I failed to see.
Cc: linux-fsde...@vger.kernel.org
Cc: Dave Chinner
Cc: Qian Cai
Cc: linux-...@vger.kernel.org
Cc: Thomas Hellström (Intel)
Cc: Andrew Morton
Cc: Jason Gunthorpe
Cc: linux...@kvack.org
Cc: linux-r...@vger.kernel.org
Cc: Maarten Lankhorst
Cc: Christian König
Cc: "Matthew Wilcox (Oracle)"
Signed-off-by: Daniel Vetter
---
mm/mmu_notifier.c | 7 ---
mm/page_alloc.c | 31 ---
2 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c
index 5654dd19addc..61ee40ed804e 100644
--- a/mm/mmu_notifier.c
+++ b/mm/mmu_notifier.c
@@ -612,13 +612,6 @@ int __mmu_notifier_register(struct mmu_notifier
*subscription,
mmap_assert_write_locked(mm);
BUG_ON(atomic_read(>mm_users) <= 0);
- if (IS_ENABLED(CONFIG_LOCKDEP)) {
- fs_reclaim_acquire(GFP_KERNEL);
- lock_map_acquire(&__mmu_notifier_invalidate_range_start_map);
- lock_map_release(&__mmu_notifier_invalidate_range_start_map);
- fs_reclaim_release(GFP_KERNEL);
- }
-
if (!mm->notifier_subscriptions) {
/*
* kmalloc cannot be called under mm_take_all_locks(), but we
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 23f5066bd4a5..ff0f9a84b8de 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -57,6 +57,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -4264,10 +4265,8 @@ should_compact_retry(struct alloc_context *ac, unsigned
int order, int alloc_fla
static struct lockdep_map __fs_reclaim_map =
STATIC_LOCKDEP_MAP_INIT("fs_reclaim", &__fs_reclaim_map);
-static bool __need_fs_reclaim(gfp_t gfp_mask)
+static bool __need_reclaim(gfp_t gfp_mask)
{
- gfp_mask = current_gfp_context(gfp_mask);
-
/* no reclaim without waiting on it */
if (!(gfp_mask & __GFP_DIRECT_RECLAIM))
return false;
@@ -4276,10 +4275,6 @@ static bool __need_fs_reclaim(gfp_t gfp_mask)
if (current->flags & PF_MEMALLOC)
return false;
- /* We're only interested __GFP_FS allocations for now */
- if (!(gfp_mask & __GFP_FS))
- return false;
-
if (gfp_mask & __GFP_NOLOCKDEP)
return false;
@@ -4298,15 +4293,29 @@ void __fs_reclaim_release(void)
void fs_reclaim_acquire(gfp_t gfp_mask)
{
- if (__need_fs_reclaim(gfp_mask))
- __fs_reclaim_acquire();
+ gfp_mask = current_gfp_context(gfp_mask);
+
+ if (__need_reclaim(gfp_mask)) {
+ if (gfp_mask & __GFP_FS)
+ __fs_reclaim_acquire();
+
+#ifdef CONFIG_MMU_NOTIFIER
+ lock_map_acquire(&__mmu_notifier_invalidate_range_start_map);
+
[Intel-gfx] [PATCH 0/3] mmu_notifier fs fs_reclaim lockdep annotations
Hi all, I've finally gotten around to polish of my lockdep anntotation patches from a while ago: https://lore.kernel.org/dri-devel/20200610194101.1668038-1-daniel.vet...@ffwll.ch/ That patch has been in -mm for a few days already, but it immediately hit some issues with xfs. Changes since v2: - Now hopefully the bug that bombed xfs fixed. - With unit-tests (that's the part I really wanted and never got to) - might_alloc() helper thrown in for good. The unit test stuff was the major drag until I figured out how to make this very easy with the locking selftests. Comments, review, testing all very much welcome. Cheers, Daniel Daniel Vetter (3): mm: Track mmu notifiers in fs_reclaim_acquire/release mm: Extract might_alloc() debug check locking/selftests: Add testcases for fs_reclaim include/linux/sched/mm.h | 16 ++ lib/locking-selftest.c | 47 mm/mmu_notifier.c| 7 -- mm/page_alloc.c | 31 -- mm/slab.h| 5 + mm/slob.c| 6 ++--- 6 files changed, 86 insertions(+), 26 deletions(-) -- 2.29.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
