[Intel-gfx] ✓ Fi.CI.IGT: success for tpm_tis: Detect interrupt storms
== Series Details ==
Series: tpm_tis: Detect interrupt storms
URL : https://patchwork.freedesktop.org/series/84608/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9445_full -> Patchwork_19068_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19068_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_ctx_exec@basic-close-race}:
- shard-apl: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-apl3/igt@gem_ctx_e...@basic-close-race.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/shard-apl1/igt@gem_ctx_e...@basic-close-race.html
- shard-kbl: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-kbl3/igt@gem_ctx_e...@basic-close-race.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/shard-kbl4/igt@gem_ctx_e...@basic-close-race.html
New tests
-
New tests have been introduced between CI_DRM_9445_full and
Patchwork_19068_full:
### New CI tests (1) ###
* boot:
- Statuses : 174 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_19068_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_softpin@noreloc-s3:
- shard-apl: [PASS][5] -> [INCOMPLETE][6] ([i915#2405])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-apl4/igt@gem_soft...@noreloc-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/shard-apl4/igt@gem_soft...@noreloc-s3.html
* igt@i915_suspend@forcewake:
- shard-kbl: [PASS][7] -> [INCOMPLETE][8] ([i915#155] / [i915#180]
/ [i915#636])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-kbl7/igt@i915_susp...@forcewake.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/shard-kbl7/igt@i915_susp...@forcewake.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) +2 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl8/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/shard-skl3/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [PASS][11] -> [FAIL][12] ([i915#79])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-edp1.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-edp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#2122])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl4/igt@kms_flip@plain-flip-ts-check-interrupti...@a-edp1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/shard-skl4/igt@kms_flip@plain-flip-ts-check-interrupti...@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
- shard-apl: [PASS][15] -> [FAIL][16] ([i915#49])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-apl7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/shard-apl2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#49])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-glk2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/shard-glk8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
- shard-kbl: [PASS][19] -> [FAIL][20] ([i915#49])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-kbl1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/shard-kbl6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][21] -> [FAIL][22] ([i915#1188])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl4/igt@kms_...@bpc-switch-suspend.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/shard-skl7/igt@kms_...@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i9
[Intel-gfx] ✓ Fi.CI.IGT: success for Introduce Alderlake-S (rev3)
== Series Details ==
Series: Introduce Alderlake-S (rev3)
URL : https://patchwork.freedesktop.org/series/82917/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9445_full -> Patchwork_19067_full
Summary
---
**SUCCESS**
No regressions found.
New tests
-
New tests have been introduced between CI_DRM_9445_full and
Patchwork_19067_full:
### New CI tests (1) ###
* boot:
- Statuses : 173 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_19067_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_softpin@noreloc-s3:
- shard-apl: [PASS][1] -> [INCOMPLETE][2] ([i915#2405])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-apl4/igt@gem_soft...@noreloc-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-apl6/igt@gem_soft...@noreloc-s3.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [PASS][3] -> [FAIL][4] ([i915#2521])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl2/igt@kms_async_fl...@alternate-sync-async-flip.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-skl5/igt@kms_async_fl...@alternate-sync-async-flip.html
* igt@kms_cursor_crc@pipe-c-cursor-64x21-offscreen:
- shard-skl: [PASS][5] -> [FAIL][6] ([i915#54]) +2 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl5/igt@kms_cursor_...@pipe-c-cursor-64x21-offscreen.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-skl4/igt@kms_cursor_...@pipe-c-cursor-64x21-offscreen.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-kbl: [PASS][7] -> [INCOMPLETE][8] ([i915#155] / [i915#180])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-kbl2/igt@kms_flip@flip-vs-susp...@a-dp1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-kbl3/igt@kms_flip@flip-vs-susp...@a-dp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
- shard-apl: [PASS][9] -> [FAIL][10] ([i915#49])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-apl7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-apl3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#49])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-glk2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-glk9/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
- shard-kbl: [PASS][13] -> [FAIL][14] ([i915#49])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-kbl1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-kbl7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][15] -> [FAIL][16] ([i915#1188])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl4/igt@kms_...@bpc-switch-suspend.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-skl5/igt@kms_...@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265])
+1 similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl10/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-skl8/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@perf@polling-parameterized:
- shard-iclb: [PASS][21] -> [FAIL][22] ([i915#1542])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-iclb1/igt@p...@polling-parameterized.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-iclb3/igt@p...@polling-parameterized.html
Possible fixes
* {igt@gem_ctx_exec@basic-close-race}:
- shard-skl: [INCOMPLETE][23] -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/shard-skl1/igt@gem_ctx_e...@basic-close-race.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/shard-skl3/igt@gem_ctx_e...@basic-close-race.html
* igt@gem_exec_
[Intel-gfx] ✓ Fi.CI.BAT: success for tpm_tis: Detect interrupt storms
== Series Details == Series: tpm_tis: Detect interrupt storms URL : https://patchwork.freedesktop.org/series/84608/ State : success == Summary == CI Bug Log - changes from CI_DRM_9445 -> Patchwork_19068 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/index.html New tests - New tests have been introduced between CI_DRM_9445 and Patchwork_19068: ### New CI tests (1) ### * boot: - Statuses : 1 fail(s) 37 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19068 that come from known issues: ### IGT changes ### Issues hit * igt@gem_basic@create-close: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/fi-tgl-y/igt@gem_ba...@create-close.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/fi-tgl-y/igt@gem_ba...@create-close.html * igt@i915_selftest@live@gt_heartbeat: - fi-tgl-y: [PASS][3] -> [DMESG-FAIL][4] ([i915#2601]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html Possible fixes * igt@gem_basic@create-fd-close: - fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/fi-tgl-y/igt@gem_ba...@create-fd-close.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/fi-tgl-y/igt@gem_ba...@create-fd-close.html * igt@gem_exec_suspend@basic-s3: - fi-snb-2600:[INCOMPLETE][7] -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html [i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 38) -- Missing(5): fi-ilk-m540 fi-cml-s fi-hsw-4200u fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9445 -> Patchwork_19068 CI-20190529: 20190529 CI_DRM_9445: 2e3d245730b4ce190e96d9731a2a6f06bb0ec57a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5881: 10d4e2e9177eb747b9f2ab9122e3ab60e91654fb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19068: 6c83347a790e974258695626a9027419c62e5a76 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6c83347a790e tpm_tis: Disable Interrupts on the ThinkPad L490 d3237e7109ec tpm_tis: Disable interrupts if interrupt storm detected f747809abcdd drm/i915/pmu: Use kstat_irqs to get interrupt count 2ce4abcffe25 irq: export kstat_irqs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19068/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for tpm_tis: Detect interrupt storms
== Series Details == Series: tpm_tis: Detect interrupt storms URL : https://patchwork.freedesktop.org/series/84608/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add support for Intel's eDP backlight controls (rev3)
== Series Details ==
Series: drm/i915: Add support for Intel's eDP backlight controls (rev3)
URL : https://patchwork.freedesktop.org/series/81702/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9444_full -> Patchwork_19066_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19066_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19066_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19066_full:
### IGT changes ###
Possible regressions
* igt@kms_flip_tiling@flip-to-yf-tiled@edp-1-pipe-c:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl4/igt@kms_flip_tiling@flip-to-yf-ti...@edp-1-pipe-c.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19066/shard-skl9/igt@kms_flip_tiling@flip-to-yf-ti...@edp-1-pipe-c.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_ctx_exec@basic-close-race}:
- shard-glk: [DMESG-FAIL][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-glk7/igt@gem_ctx_e...@basic-close-race.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19066/shard-glk1/igt@gem_ctx_e...@basic-close-race.html
New tests
-
New tests have been introduced between CI_DRM_9444_full and
Patchwork_19066_full:
### New CI tests (1) ###
* boot:
- Statuses : 174 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_19066_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@api_intel_bb@render-ccs:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#2405] /
[i915#2499])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl4/igt@api_intel...@render-ccs.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19066/shard-skl8/igt@api_intel...@render-ccs.html
* igt@gem_exec_whisper@basic-fds-priority:
- shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-glk2/igt@gem_exec_whis...@basic-fds-priority.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19066/shard-glk2/igt@gem_exec_whis...@basic-fds-priority.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [PASS][9] -> [INCOMPLETE][10] ([i915#2405])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-apl8/igt@gem_soft...@noreloc-s3.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19066/shard-apl3/igt@gem_soft...@noreloc-s3.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1436] /
[i915#716])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl8/igt@gen9_exec_pa...@allowed-single.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19066/shard-skl4/igt@gen9_exec_pa...@allowed-single.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#54]) +1 similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl4/igt@kms_cursor_...@pipe-b-cursor-128x42-sliding.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19066/shard-skl8/igt@kms_cursor_...@pipe-b-cursor-128x42-sliding.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2598])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19066/shard-tglb3/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#79])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-glk2/igt@kms_flip@flip-vs-expired-vbl...@c-hdmi-a2.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19066/shard-glk5/igt@kms_flip@flip-vs-expired-vbl...@c-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
- shard-apl: [PASS][19] -> [FAIL][20] ([i915#49])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-apl2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19066/shard-apl7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plf
[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Alderlake-S (rev3)
== Series Details == Series: Introduce Alderlake-S (rev3) URL : https://patchwork.freedesktop.org/series/82917/ State : success == Summary == CI Bug Log - changes from CI_DRM_9445 -> Patchwork_19067 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/index.html New tests - New tests have been introduced between CI_DRM_9445 and Patchwork_19067: ### New CI tests (1) ### * boot: - Statuses : 1 fail(s) 38 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19067 that come from known issues: ### IGT changes ### Issues hit * igt@gem_render_linear_blits@basic: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/fi-tgl-y/igt@gem_render_linear_bl...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/fi-tgl-y/igt@gem_render_linear_bl...@basic.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-skl-6700k2: [PASS][3] -> [INCOMPLETE][4] ([i915#146] / [i915#2405]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html * igt@prime_vgem@basic-fence-flip: - fi-cml-s: [PASS][5] -> [INCOMPLETE][6] ([i915#2377]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/fi-cml-s/igt@prime_v...@basic-fence-flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/fi-cml-s/igt@prime_v...@basic-fence-flip.html Possible fixes * igt@gem_basic@create-fd-close: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/fi-tgl-y/igt@gem_ba...@create-fd-close.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/fi-tgl-y/igt@gem_ba...@create-fd-close.html * igt@gem_exec_suspend@basic-s3: - fi-snb-2600:[INCOMPLETE][9] -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9445/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#2377]: https://gitlab.freedesktop.org/drm/intel/issues/2377 [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 39) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9445 -> Patchwork_19067 CI-20190529: 20190529 CI_DRM_9445: 2e3d245730b4ce190e96d9731a2a6f06bb0ec57a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5881: 10d4e2e9177eb747b9f2ab9122e3ab60e91654fb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19067: 4550beb694af36a8cea5bfd14dc1353644abd1ed @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4550beb694af drm/i915/adl_s: Update memory bandwidth parameters fceb5bcdc2e0 drm/i915/adl_s: Load DMC 75bb40138464 drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION e234d322b07f drm/i915/adl_s: Re-use TGL GuC/HuC firmware 3c42824c88e1 drm/i915/adl_s: Add power wells 7363cd5f8d3f drm/i915/adl_s: MCHBAR memory info registers are moved ea3c5de02c7f drm/i915/adl_s: Add GT and CTX WAs for ADL-S b2ac95cad0d1 drm/i915/adl_s: Add display WAs for ADL-S cc24f634335a drm/i915/adl_s: Update PHY_MISC programming b3310f98c834 drm/i915/adl_s: Update combo PHY master/slave relationships fbd148aa96fd drm/i915/adl_s: Add vbt port and aux channel settings for adls 241ce3db14df drm/i915/adl_s: Add adl-s ddc pin mapping 8982e3cd419c drm/i915/adl_s: Initialize display for ADL-S 2591c7399649 drm/i915/adl_s: Configure Port clock registers for ADL-S 114e7efe0b1a drm/i915/adl_s: Configure DPLL for ADL-S d1bd8b907825 drm/i915/adl_s: Add PHYs for Alderlake S ca0a9e7d58c5 drm/i915/adl_s: Add Interrupt Support 130950398722 drm/i915/adl_s: Add PCH support 150a0b30604f x86/gpu: add ADL_S stolen memory support 75d8d0e1ed7d drm/i915/adl_s: Add ADL-S platform info and PCI ids deb53d194dbb drm/i915/tgl: Add bound checks and simplify TGL REVID macros d90e9bb9cd0e drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19067/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gem: Drop false !i915_vma_is_closed assertion
== Series Details == Series: drm/i915/gem: Drop false !i915_vma_is_closed assertion URL : https://patchwork.freedesktop.org/series/84602/ State : success == Summary == CI Bug Log - changes from CI_DRM_9444_full -> Patchwork_19065_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_9444_full and Patchwork_19065_full: ### New CI tests (1) ### * boot: - Statuses : 200 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19065_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#2369]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl3/igt@gem_exec_capture@p...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/shard-skl9/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_whisper@basic-fds-priority: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-glk2/igt@gem_exec_whis...@basic-fds-priority.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/shard-glk9/igt@gem_exec_whis...@basic-fds-priority.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: [PASS][5] -> [FAIL][6] ([i915#79]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1: - shard-apl: [PASS][7] -> [FAIL][8] ([i915#79]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-dp1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/shard-apl1/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-dp1.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-kbl: [PASS][9] -> [INCOMPLETE][10] ([i915#155] / [i915#180]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-kbl7/igt@kms_flip@flip-vs-suspend-interrupti...@a-dp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/shard-kbl7/igt@kms_flip@flip-vs-suspend-interrupti...@a-dp1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: - shard-apl: [PASS][11] -> [FAIL][12] ([i915#49]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-apl2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/shard-apl8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html - shard-glk: [PASS][13] -> [FAIL][14] ([i915#49]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-glk2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/shard-glk8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html - shard-kbl: [PASS][15] -> [FAIL][16] ([i915#49]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-kbl7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/shard-kbl7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#1188]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl4/igt@kms_...@bpc-switch-dpms.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/shard-skl10/igt@kms_...@bpc-switch-dpms.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl9/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/shard-skl2/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/shard-iclb5/igt@kms_psr@psr2_cursor_plane_move.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([i915#198] / [i915#2295]) [23]: https://intel-gfx-ci.01.o
[Intel-gfx] [PATCH v3 3/4] tpm_tis: Disable interrupts if interrupt storm detected
When enabling the interrupt code for the tpm_tis driver we have
noticed some systems have a bios issue causing an interrupt storm to
occur. The issue isn't limited to a single tpm or system manufacturer
so keeping a denylist of systems with the issue isn't optimal. Instead
try to detect the problem occurring, disable interrupts, and revert to
polling when it happens.
Cc: Jarkko Sakkinen
Cc: Jason Gunthorpe
Cc: Peter Huewe
Cc: James Bottomley
Cc: Matthew Garrett
Cc: Hans de Goede
Signed-off-by: Jerry Snitselaar
---
v3: - Change include from linux/kernel_stat.h to linux/irq.h
v2: - drop tpm_tis specific workqueue and use just system_w
drivers/char/tpm/tpm_tis_core.c | 27 +++
drivers/char/tpm/tpm_tis_core.h | 2 ++
2 files changed, 29 insertions(+)
diff --git a/drivers/char/tpm/tpm_tis_core.c b/drivers/char/tpm/tpm_tis_core.c
index 92c51c6cfd1b..d817ff5664d1 100644
--- a/drivers/char/tpm/tpm_tis_core.c
+++ b/drivers/char/tpm/tpm_tis_core.c
@@ -24,6 +24,8 @@
#include
#include
#include
+#include
+#include
#include "tpm.h"
#include "tpm_tis_core.h"
@@ -715,9 +717,23 @@ static irqreturn_t tis_int_handler(int dummy, void *dev_id)
{
struct tpm_chip *chip = dev_id;
struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+ static bool check_storm = true;
+ static unsigned int check_start;
u32 interrupt;
int i, rc;
+ if (unlikely(check_storm)) {
+ if (!check_start) {
+ check_start = jiffies_to_msecs(jiffies);
+ } else if ((kstat_irqs(priv->irq) > 1000) &&
+ (jiffies_to_msecs(jiffies) - check_start < 500)) {
+ check_storm = false;
+ schedule_work(&priv->storm_work);
+ } else if (jiffies_to_msecs(jiffies) - check_start >= 500) {
+ check_storm = false;
+ }
+ }
+
rc = tpm_tis_read32(priv, TPM_INT_STATUS(priv->locality), &interrupt);
if (rc < 0)
return IRQ_NONE;
@@ -943,6 +959,14 @@ static const struct tpm_class_ops tpm_tis = {
.clk_enable = tpm_tis_clkrun_enable,
};
+static void tpm_tis_storm_work(struct work_struct *work)
+{
+ struct tpm_tis_data *priv = container_of(work, struct tpm_tis_data,
storm_work);
+
+ disable_interrupts(priv->chip);
+ dev_warn(&priv->chip->dev, "Interrupt storm detected, using
polling.\n");
+}
+
int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq,
const struct tpm_tis_phy_ops *phy_ops,
acpi_handle acpi_dev_handle)
@@ -959,6 +983,9 @@ int tpm_tis_core_init(struct device *dev, struct
tpm_tis_data *priv, int irq,
if (IS_ERR(chip))
return PTR_ERR(chip);
+ priv->chip = chip;
+ INIT_WORK(&priv->storm_work, tpm_tis_storm_work);
+
#ifdef CONFIG_ACPI
chip->acpi_dev_handle = acpi_dev_handle;
#endif
diff --git a/drivers/char/tpm/tpm_tis_core.h b/drivers/char/tpm/tpm_tis_core.h
index 9b2d32a59f67..973297ee2e16 100644
--- a/drivers/char/tpm/tpm_tis_core.h
+++ b/drivers/char/tpm/tpm_tis_core.h
@@ -95,6 +95,8 @@ struct tpm_tis_data {
u16 clkrun_enabled;
wait_queue_head_t int_queue;
wait_queue_head_t read_queue;
+ struct work_struct storm_work;
+ struct tpm_chip *chip;
const struct tpm_tis_phy_ops *phy_ops;
unsigned short rng_quality;
};
--
2.27.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/4] drm/i915/pmu: Use kstat_irqs to get interrupt count
Now that kstat_irqs is exported, get rid of count_interrupts in
i915_pmu.c
Cc: Thomas Gleixner
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: David Airlie
Cc: Daniel Vetter
Cc: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Cc: Jarkko Sakkinen
Cc: Jason Gunthorpe
Cc: Peter Huewe
Cc: James Bottomley
Cc: Matthew Garrett
Cc: Hans de Goede
Signed-off-by: Jerry Snitselaar
---
drivers/gpu/drm/i915/i915_pmu.c | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 69c0fa20eba1..a3e63f03da8c 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -423,22 +423,6 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
return HRTIMER_RESTART;
}
-static u64 count_interrupts(struct drm_i915_private *i915)
-{
- /* open-coded kstat_irqs() */
- struct irq_desc *desc = irq_to_desc(i915->drm.pdev->irq);
- u64 sum = 0;
- int cpu;
-
- if (!desc || !desc->kstat_irqs)
- return 0;
-
- for_each_possible_cpu(cpu)
- sum += *per_cpu_ptr(desc->kstat_irqs, cpu);
-
- return sum;
-}
-
static void i915_pmu_event_destroy(struct perf_event *event)
{
struct drm_i915_private *i915 =
@@ -581,7 +565,7 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
USEC_PER_SEC /* to MHz */);
break;
case I915_PMU_INTERRUPTS:
- val = count_interrupts(i915);
+ val = kstat_irqs(i915->drm.pdev->irq);
break;
case I915_PMU_RC6_RESIDENCY:
val = get_rc6(&i915->gt);
--
2.27.0
___
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[Intel-gfx] [PATCH v3 4/4] tpm_tis: Disable Interrupts on the ThinkPad L490
The interrupt storm detection code detects the issue on the ThinkPad
T490s, but the L490 still hangs at initialization. So swap out the
T490s for the L490 in the dmi check.
Cc: Jarkko Sakkinen
Cc: Jason Gunthorpe
Cc: Peter Huewe
Cc: James Bottomley
Cc: Matthew Garrett
Cc: Hans de Goede
Signed-off-by: Jerry Snitselaar
---
drivers/char/tpm/tpm_tis.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/char/tpm/tpm_tis.c b/drivers/char/tpm/tpm_tis.c
index 4ed6e660273a..7322e0986a83 100644
--- a/drivers/char/tpm/tpm_tis.c
+++ b/drivers/char/tpm/tpm_tis.c
@@ -77,10 +77,10 @@ static int tpm_tis_disable_irq(const struct dmi_system_id
*d)
static const struct dmi_system_id tpm_tis_dmi_table[] = {
{
.callback = tpm_tis_disable_irq,
- .ident = "ThinkPad T490s",
+ .ident = "ThinkPad L490",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
- DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T490s"),
+ DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L490"),
},
},
{}
--
2.27.0
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[Intel-gfx] [PATCH v3 1/4] irq: export kstat_irqs
To try and detect potential interrupt storms that have been occurring with tpm_tis devices it was suggested to use kstat_irqs() to get the number of interrupts. Since tpm_tis can be built as a module it needs kstat_irqs exported. Reported-by: kernel test robot Cc: Thomas Gleixner Cc: Jarkko Sakkinen Cc: Jason Gunthorpe Cc: Peter Huewe Cc: James Bottomley Cc: Matthew Garrett Cc: Hans de Goede Signed-off-by: Jerry Snitselaar --- include/linux/irqdesc.h | 1 + kernel/irq/irqdesc.c| 1 + 2 files changed, 2 insertions(+) diff --git a/include/linux/irqdesc.h b/include/linux/irqdesc.h index 5745491303e0..fff88c1f1ac6 100644 --- a/include/linux/irqdesc.h +++ b/include/linux/irqdesc.h @@ -153,6 +153,7 @@ static inline void generic_handle_irq_desc(struct irq_desc *desc) } int generic_handle_irq(unsigned int irq); +unsigned int kstat_irqs(unsigned int irq); #ifdef CONFIG_HANDLE_DOMAIN_IRQ /* diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index 1a7723604399..12398ef1796b 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -1000,6 +1000,7 @@ unsigned int kstat_irqs(unsigned int irq) sum += *per_cpu_ptr(desc->kstat_irqs, cpu); return sum; } +EXPORT_SYMBOL_GPL(kstat_irqs); /** * kstat_irqs_usr - Get the statistics for an interrupt -- 2.27.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 0/4] tpm_tis: Detect interrupt storms
This patchset is an attempt to try and catch tpm_tis devices that have interrupt storm issues, disable the interrupt, and use polling. In 2016 the tpm_tis interrupt code was accidently disabled, and polling was just being used. When we initially tried to enable interrupts again there were some reports of systems being hit with interrupt storms. It turned out that the ThinkPad T490s had misconfigured a gpio pin being used for the interrupt. The problem is more widespread though, with interrupt storms also being seen on other platforms and different TPM vendors. With the L490 the system hangs at tpm_tis initialization even with the detection code, so change the earlier detection code that used dmi to look for the T490s to instead look for the L490 and disable interrupts. Since kstat_irqs needs to be exported to allow building of tpm_tis as a module, I've included a patch to change the i915_pmu code to use kstat_irqs where before it was using its own version. If this isn't desired it can be dropped. I've been testing this on top of James' proposed patchset which re-enables interrupts for tpm_tis. With the patchsets applied it detects the problem on the T490s and on the Ice Lake development system where I found the issue. I have Lenovo verifying that the dmi detection code will now detect the L490 and avoid the hang it experiences. I'm also working on getting access to an L490 to see if I can figure out what the underlying issue is. Changes from v2: - Export kstat_irqs to allow building tpm_tis as a module. - Change i915_pmu.c to use kstat_irqs instead of it's own version count_interrupts. - Change include from linux/kernel_stat.h to linux/irq.h. - Change dmi checking code to now look for L490 instead of T490s. Changes from v1: - drop tpm_tis specific workqueue and use just system_w. Jerry Snitselaar (4): irq: export kstat_irqs drm/i915/pmu: Use kstat_irqs to get interrupt count tpm_tis: Disable interrupts if interrupt storm detected tpm_tis: Disable Interrupts on the ThinkPad L490 Cc: Thomas Gleixner Cc: Jani Nikula Cc: Rodrigo Vivi Cc: David Airlie Cc: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Cc: Jarkko Sakkinen Cc: Jason Gunthorpe Cc: Peter Huewe Cc: James Bottomley Cc: Matthew Garrett Cc: Hans de Goede Cc: linux-integr...@vger.kernel.org drivers/char/tpm/tpm_tis.c | 4 ++-- drivers/char/tpm/tpm_tis_core.c | 27 +++ drivers/char/tpm/tpm_tis_core.h | 2 ++ drivers/gpu/drm/i915/i915_pmu.c | 18 +- include/linux/irqdesc.h | 1 + kernel/irq/irqdesc.c| 1 + 6 files changed, 34 insertions(+), 19 deletions(-) -- 2.27.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce Alderlake-S (rev3)
== Series Details == Series: Introduce Alderlake-S (rev3) URL : https://patchwork.freedesktop.org/series/82917/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1447:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1501:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fw
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alderlake-S (rev3)
== Series Details == Series: Introduce Alderlake-S (rev3) URL : https://patchwork.freedesktop.org/series/82917/ State : warning == Summary == $ dim checkpatch origin/drm-tip d90e9bb9cd0e drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping deb53d194dbb drm/i915/tgl: Add bound checks and simplify TGL REVID macros 75d8d0e1ed7d drm/i915/adl_s: Add ADL-S platform info and PCI ids -:239: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects? #239: FILE: drivers/gpu/drm/i915/i915_drv.h:1646: +#define IS_ADLS_DISP_REVID(p, since, until) \ + (IS_ALDERLAKE_S(p) && \ +tgl_revids_get(p)->disp_stepping >= (since) && \ +tgl_revids_get(p)->disp_stepping <= (until)) -:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects? #244: FILE: drivers/gpu/drm/i915/i915_drv.h:1651: +#define IS_ADLS_GT_REVID(p, since, until) \ + (IS_ALDERLAKE_S(p) && \ +tgl_revids_get(p)->gt_stepping >= (since) && \ +tgl_revids_get(p)->gt_stepping <= (until)) -:329: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #329: FILE: include/drm/i915_pciids.h:638: +#define INTEL_ADLS_IDS(info) \ + INTEL_VGA_DEVICE(0x4680, info), \ + INTEL_VGA_DEVICE(0x4681, info), \ + INTEL_VGA_DEVICE(0x4682, info), \ + INTEL_VGA_DEVICE(0x4683, info), \ + INTEL_VGA_DEVICE(0x4690, info), \ + INTEL_VGA_DEVICE(0x4691, info), \ + INTEL_VGA_DEVICE(0x4692, info), \ + INTEL_VGA_DEVICE(0x4693, info), \ + INTEL_VGA_DEVICE(0x4698, info), \ + INTEL_VGA_DEVICE(0x4699, info) -:329: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #329: FILE: include/drm/i915_pciids.h:638: +#define INTEL_ADLS_IDS(info) \ + INTEL_VGA_DEVICE(0x4680, info), \ + INTEL_VGA_DEVICE(0x4681, info), \ + INTEL_VGA_DEVICE(0x4682, info), \ + INTEL_VGA_DEVICE(0x4683, info), \ + INTEL_VGA_DEVICE(0x4690, info), \ + INTEL_VGA_DEVICE(0x4691, info), \ + INTEL_VGA_DEVICE(0x4692, info), \ + INTEL_VGA_DEVICE(0x4693, info), \ + INTEL_VGA_DEVICE(0x4698, info), \ + INTEL_VGA_DEVICE(0x4699, info) total: 1 errors, 0 warnings, 3 checks, 241 lines checked 150a0b30604f x86/gpu: add ADL_S stolen memory support 130950398722 drm/i915/adl_s: Add PCH support ca0a9e7d58c5 drm/i915/adl_s: Add Interrupt Support d1bd8b907825 drm/i915/adl_s: Add PHYs for Alderlake S 114e7efe0b1a drm/i915/adl_s: Configure DPLL for ADL-S 2591c7399649 drm/i915/adl_s: Configure Port clock registers for ADL-S 8982e3cd419c drm/i915/adl_s: Initialize display for ADL-S 241ce3db14df drm/i915/adl_s: Add adl-s ddc pin mapping fbd148aa96fd drm/i915/adl_s: Add vbt port and aux channel settings for adls -:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #10: - ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E. total: 0 errors, 1 warnings, 0 checks, 81 lines checked b3310f98c834 drm/i915/adl_s: Update combo PHY master/slave relationships cc24f634335a drm/i915/adl_s: Update PHY_MISC programming b2ac95cad0d1 drm/i915/adl_s: Add display WAs for ADL-S ea3c5de02c7f drm/i915/adl_s: Add GT and CTX WAs for ADL-S 7363cd5f8d3f drm/i915/adl_s: MCHBAR memory info registers are moved 3c42824c88e1 drm/i915/adl_s: Add power wells e234d322b07f drm/i915/adl_s: Re-use TGL GuC/HuC firmware 75bb40138464 drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION -:45: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #45: FILE: drivers/gpu/drm/i915/i915_drv.h:1799: +#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \ + IS_ALDERLAKE_S(dev_priv)) total: 0 errors, 0 warnings, 1 checks, 33 lines checked fceb5bcdc2e0 drm/i915/adl_s: Load DMC 4550beb694af drm/i915/adl_s: Update memory bandwidth parameters ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 22/22] drm/i915/adl_s: Update memory bandwidth parameters
From: Tejas Upadhyay
Just like RKL, the ADL_S platform also has different memory
characteristics from past platforms. Update the values used
by our memory bandwidth calculations accordingly.
Bspec: 64631
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Signed-off-by: Tejas Upadhyay
Signed-off-by: Aditya Swarup
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_bw.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index bd060404d249..32522ec1ffb9 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -205,6 +205,12 @@ static const struct intel_sa_info rkl_sa_info = {
.displayrtids = 128,
};
+static const struct intel_sa_info adls_sa_info = {
+ .deburst = 16,
+ .deprogbwlimit = 38, /* GB/s */
+ .displayrtids = 256,
+};
+
static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct
intel_sa_info *sa)
{
struct intel_qgv_info qi = {};
@@ -317,6 +323,8 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
if (IS_ROCKETLAKE(dev_priv))
icl_get_bw_info(dev_priv, &rkl_sa_info);
+ else if (IS_ALDERLAKE_S(dev_priv))
+ icl_get_bw_info(dev_priv, &adls_sa_info);
else if (IS_GEN(dev_priv, 12))
icl_get_bw_info(dev_priv, &tgl_sa_info);
else if (IS_GEN(dev_priv, 11))
--
2.27.0
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[Intel-gfx] [PATCH 21/22] drm/i915/adl_s: Load DMC
From: Anusha Srivatsa
Load DMC on ADL_S v2.01. This is the first offcial
release of DMC for ADL_S.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Aditya Swarup
Signed-off-by: Anusha Srivatsa
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/display/intel_csr.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c
b/drivers/gpu/drm/i915/display/intel_csr.c
index 67dc64df78a5..db9f219c4b5a 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -40,6 +40,10 @@
#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
+#define ADLS_CSR_PATH "i915/adls_dmc_ver2_01.bin"
+#define ADLS_CSR_VERSION_REQUIRED CSR_VERSION(2, 1)
+MODULE_FIRMWARE(ADLS_CSR_PATH);
+
#define DG1_CSR_PATH "i915/dg1_dmc_ver2_02.bin"
#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
MODULE_FIRMWARE(DG1_CSR_PATH);
@@ -689,7 +693,11 @@ void intel_csr_ucode_init(struct drm_i915_private
*dev_priv)
*/
intel_csr_runtime_pm_get(dev_priv);
- if (IS_DG1(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ csr->fw_path = ADLS_CSR_PATH;
+ csr->required_version = ADLS_CSR_VERSION_REQUIRED;
+ csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+ } else if (IS_DG1(dev_priv)) {
csr->fw_path = DG1_CSR_PATH;
csr->required_version = DG1_CSR_VERSION_REQUIRED;
csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
--
2.27.0
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[Intel-gfx] [PATCH 20/22] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
From: José Roberto de Souza
- As RKL and ADL-S only have 5 planes, primary and 4 sprites and
the cursor plane, let's group the handling together under
HAS_D12_PLANE_MINIMIZATION.
- Also use macro to select pipe irq fault error mask.
BSpec: 49251
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: José Roberto de Souza
Signed-off-by: Aditya Swarup
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c| 2 +-
4 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 2d820ff2b236..10176b174e50 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -366,7 +366,7 @@ int intel_plane_check_src_coordinates(struct
intel_plane_state *plane_state)
static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
{
- if (IS_ROCKETLAKE(i915))
+ if (HAS_D12_PLANE_MINIMIZATION(i915))
return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
else
return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91bd262dd871..1d710d9d8dee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1796,6 +1796,9 @@ extern const struct i915_rev_steppings adls_revids[];
#define INTEL_DISPLAY_ENABLED(dev_priv) \
(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),
!(dev_priv)->params.disable_display)
+#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
+ IS_ALDERLAKE_S(dev_priv))
+
static inline bool intel_vtd_active(void)
{
#ifdef CONFIG_INTEL_IOMMU
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d1b4893d6c92..bcb0f7c96c65 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2246,7 +2246,7 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private
*dev_priv)
static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
{
- if (IS_ROCKETLAKE(dev_priv))
+ if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
else if (INTEL_GEN(dev_priv) >= 11)
return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index da651ef10014..c94a52642f32 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -409,7 +409,7 @@ void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv)
BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
- if (IS_ROCKETLAKE(dev_priv))
+ if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 4;
else if (INTEL_GEN(dev_priv) >= 11)
--
2.27.0
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[Intel-gfx] [PATCH 18/22] drm/i915/adl_s: Add power wells
From: Lucas De Marchi
TGL power wells can be re-used for ADL-S with the exception of the fake
power well for TC_COLD, just like DG-1.
Bspec: 53597
Cc: Imre Deak
Cc: Matt Roper
Cc: Aditya Swarup
Signed-off-by: Lucas De Marchi
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 8b163d804a41..152cf4a6826d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4632,7 +4632,7 @@ int intel_power_domains_init(struct drm_i915_private
*dev_priv)
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
*/
- if (IS_DG1(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
err = set_power_wells_mask(power_domains, tgl_power_wells,
BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
} else if (IS_ROCKETLAKE(dev_priv)) {
--
2.27.0
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[Intel-gfx] [PATCH 14/22] drm/i915/adl_s: Update PHY_MISC programming
From: Matt Roper ADL-S switches up which PHYs are considered a master to other PHYs; PHY-C is no longer a master, but PHY-D is now. Bspec: 49291 Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Lucas De Marchi Signed-off-by: Matt Roper Signed-off-by: Aditya Swarup --- drivers/gpu/drm/i915/display/intel_combo_phy.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index dd45cbafcf42..c55813c6194a 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -187,10 +187,16 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) * Some platforms only expect PHY_MISC to be programmed for PHY-A and * PHY-B and may not even have instances of the register for the * other combo PHY's. +* +* ADL-S technically has three instances of PHY_MISC, but only requires +* that we program it for PHY A. */ - if (IS_JSL_EHL(i915) || - IS_ROCKETLAKE(i915) || - IS_DG1(i915)) + + if (IS_ALDERLAKE_S(i915)) + return phy == PHY_A; + else if (IS_JSL_EHL(i915) || +IS_ROCKETLAKE(i915) || +IS_DG1(i915)) return phy < PHY_C; return true; -- 2.27.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 19/22] drm/i915/adl_s: Re-use TGL GuC/HuC firmware
From: Matt Roper ADL-S, like RKL, uses the same internal device ID for the GuC and HuC as TGL did, making them all firmware-compatible. Let's re-use TGL's firmware for ADL-S. Bspec: 50668 Cc: John Harrison Cc: Lucas De Marchi Signed-off-by: Matt Roper Signed-off-by: Aditya Swarup Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 180c23e2e25e..2d123158df0d 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -44,9 +44,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, * List of required GuC and HuC binaries per-platform. * Must be ordered based on platform + revid, from newer to older. * - * Note that RKL uses the same firmware as TGL. + * Note that RKL and ADL-S have the same GuC/HuC device ID's and use the same + * firmware as TGL. */ #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \ + fw_def(ALDERLAKE_S, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \ fw_def(ROCKETLAKE, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \ fw_def(TIGERLAKE, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl, 7, 5, 0)) \ fw_def(JASPERLAKE, 0, guc_def(ehl, 49, 0, 1), huc_def(ehl, 9, 0, 0)) \ -- 2.27.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 17/22] drm/i915/adl_s: MCHBAR memory info registers are moved
From: Caz Yokoyama
The crwebview indicates on ADL-S that some of our MCHBAR
registers have moved from their traditional 0x50XX offsets to
new locations. The meaning and bit layout of the registers
remain same.
v2: Simplify logic to a single if else chain and fix indents.(Lucas)
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Caz Yokoyama
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_dram.c | 23 +--
2 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ce4ef7fa4000..55e186293fbb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10865,6 +10865,8 @@ enum skl_power_gate {
#define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
#define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
+#define ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB +
0x6048)
+
#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB +
0x500C)
#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB +
0x5010)
#define SKL_DRAM_S_SHIFT 16
@@ -10892,6 +10894,9 @@ enum skl_power_gate {
#define CNL_DRAM_RANK_3 (0x2 << 9)
#define CNL_DRAM_RANK_4 (0x3 << 9)
+#define ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB +
0x6054)
+#define ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB +
0x6058)
+
/*
* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this
register,
* since on HSW we can't write to it using intel_uncore_write.
diff --git a/drivers/gpu/drm/i915/intel_dram.c
b/drivers/gpu/drm/i915/intel_dram.c
index 4754296a250e..fc9942139ccc 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -181,17 +181,24 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
{
struct dram_info *dram_info = &i915->dram_info;
struct dram_channel_info ch0 = {}, ch1 = {};
+ i915_reg_t ch0_reg, ch1_reg;
u32 val;
int ret;
- val = intel_uncore_read(&i915->uncore,
- SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
+ if (IS_ALDERLAKE_S(i915)) {
+ ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
+ ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;
+ } else {
+ ch0_reg = ADLS_MAD_DIMM_CH0_0_0_0_MCHBAR;
+ ch1_reg = ADLS_MAD_DIMM_CH1_0_0_0_MCHBAR;
+ }
+
+ val = intel_uncore_read(&i915->uncore, ch0_reg);
ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
if (ret == 0)
dram_info->num_channels++;
- val = intel_uncore_read(&i915->uncore,
- SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
+ val = intel_uncore_read(&i915->uncore, ch1_reg);
ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
if (ret == 0)
dram_info->num_channels++;
@@ -231,8 +238,12 @@ skl_get_dram_type(struct drm_i915_private *i915)
{
u32 val;
- val = intel_uncore_read(&i915->uncore,
- SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
+ if (IS_ALDERLAKE_S(i915))
+ val = intel_uncore_read(&i915->uncore,
+ ADLS_MAD_INTER_CHANNEL_0_0_0_MCHBAR);
+ else
+ val = intel_uncore_read(&i915->uncore,
+
SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
switch (val & SKL_DRAM_DDR_TYPE_MASK) {
case SKL_DRAM_DDR_TYPE_DDR3:
--
2.27.0
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[Intel-gfx] [PATCH 16/22] drm/i915/adl_s: Add GT and CTX WAs for ADL-S
- Add placeholders for gt and ctx WAs for ADL-S
- Extend Wa_1606931601 and Wa_1409804808 to ADL-S.
- Extend Wa_14010919138 and Wa_14010229206 to ADL-S (Madhumitha)
- Extend Wa_22010271021 to ADLS (cyokoyam)
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Madhumitha Tolakanahalli Pradeep
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 91 ++---
1 file changed, 61 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3db57b577a79..1a1958d3e617 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -664,22 +664,6 @@ static void tgl_ctx_workarounds_init(struct
intel_engine_cs *engine,
struct i915_wa_list *wal)
{
gen12_ctx_workarounds_init(engine, wal);
-
- /*
-* Wa_1604555607:tgl,rkl
-*
-* Note that the implementation of this workaround is further modified
-* according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
-* FF_MODE2 register will return the wrong value when read. The default
-* value for this register is zero for all fields and there are no bit
-* masks. So instead of doing a RMW we should just write the GS Timer
-* and TDS timer values for Wa_1604555607 and Wa_16011163337.
-*/
- wa_add(wal,
- FF_MODE2,
- FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
- FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128,
- 0);
}
static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
@@ -696,6 +680,12 @@ static void dg1_ctx_workarounds_init(struct
intel_engine_cs *engine,
DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
}
+static void adls_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
+{
+ gen12_ctx_workarounds_init(engine, wal);
+}
+
static void
__intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
struct i915_wa_list *wal,
@@ -708,7 +698,31 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_DG1(i915))
+ if (INTEL_GEN(i915) >= 12) {
+ /*
+* This setting isn't actually a workaround, but is a general
+* tuning setting that needs to be programmed on all platforms
+* gen12+. Although some platforms also refer to this setting
+* as Wa_1604555607, we need to program it even on platforms
that
+* don't explicitly list that workaround.
+*
+* Note that the implementation is further modified according
+* to the FF_MODE2 guidance given by Wa_1608008084:gen12.
+* FF_MODE2 register will return the wrong value when read.
+* The default value for this register is zero for all fields
+* and there are no bit masks. So instead of doing a RMW, we
+* should just write the value directly.
+*/
+ wa_add(wal,
+ FF_MODE2,
+ FF_MODE2_TDS_TIMER_MASK,
+ FF_MODE2_TDS_TIMER_128,
+ 0);
+ }
+
+ if (IS_ALDERLAKE_S(i915))
+ adls_ctx_workarounds_init(engine, wal);
+ else if (IS_DG1(i915))
dg1_ctx_workarounds_init(engine, wal);
else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
tgl_ctx_workarounds_init(engine, wal);
@@ -1294,10 +1308,18 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
VSUNIT_CLKGATE_DIS_TGL);
}
+static void
+adls_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
+{
+ gen12_gt_workarounds_init(i915, wal);
+}
+
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_DG1(i915))
+ if (IS_ALDERLAKE_S(i915))
+ adls_gt_workarounds_init(i915, wal);
+ else if (IS_DG1(i915))
dg1_gt_workarounds_init(i915, wal);
else if (IS_TIGERLAKE(i915))
tgl_gt_workarounds_init(i915, wal);
@@ -1678,6 +1700,11 @@ static void dg1_whitelist_build(struct intel_engine_cs
*engine)
RING_FORCE_TO_NONPRIV_ACCESS_RD);
}
+static void adls_whitelist_build(struct intel_engine_cs *engine)
+{
+ tgl_whitelist_build(engine);
+}
+
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
@@ -1685,7 +1712,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs
*engine)
wa_init_start(w,
[Intel-gfx] [PATCH 15/22] drm/i915/adl_s: Add display WAs for ADL-S
- Extend permanent driver WA Wa_1409767108, Wa_14010685332
and Wa_14011294188 to adl-s.
- Extend permanent driver WA Wa_1606054188 to adl-s.
- Add Wa_14011765242 for adl-s A0 stepping.
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/display/intel_display_power.c | 7 ---
drivers/gpu/drm/i915/display/intel_sprite.c| 4 ++--
drivers/gpu/drm/i915/intel_device_info.c | 6 +-
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 06c036e2092c..8b163d804a41 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5282,9 +5282,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private
*dev_priv)
unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
int config, i;
- if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+ if (IS_ALDERLAKE_S(dev_priv) ||
+ IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0))
- /* Wa_1409767108:tgl,dg1 */
+ /* Wa_1409767108:tgl,dg1,adl-s */
table = wa_1409767108_buddy_page_masks;
else
table = tgl_buddy_page_masks;
@@ -5322,7 +5323,7 @@ static void icl_display_core_init(struct drm_i915_private
*dev_priv,
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
- /* Wa_14011294188:ehl,jsl,tgl,rkl */
+ /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index e19d4f873b94..2d820ff2b236 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2371,8 +2371,8 @@ static int skl_plane_check_fb(const struct
intel_crtc_state *crtc_state,
return -EINVAL;
}
- /* Wa_1606054188:tgl */
- if (IS_TIGERLAKE(dev_priv) &&
+ /* Wa_1606054188:tgl,adl-s */
+ if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
intel_format_is_p01x(fb->format->format)) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index ce8c69c17b8e..da651ef10014 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -394,7 +394,11 @@ void intel_device_info_runtime_init(struct
drm_i915_private *dev_priv)
struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
enum pipe pipe;
- if (INTEL_GEN(dev_priv) >= 10) {
+ /* Wa_14011765242: adl-s A0 */
+ if (IS_ADLS_DISP_REVID(dev_priv, REVID_A0, REVID_A0))
+ for_each_pipe(dev_priv, pipe)
+ runtime->num_scalers[pipe] = 0;
+ else if (INTEL_GEN(dev_priv) >= 10) {
for_each_pipe(dev_priv, pipe)
runtime->num_scalers[pipe] = 2;
} else if (IS_GEN(dev_priv, 9)) {
--
2.27.0
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[Intel-gfx] [PATCH 12/22] drm/i915/adl_s: Add vbt port and aux channel settings for adls
- ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and
E.
- Add ADLS specific port mappings for vbt port dvo settings.
- Select appropriate AUX CH specific to ADLS based on port mapping.
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/display/intel_bios.c | 57 ++-
1 file changed, 46 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 9dc67c03ffc0..8f166f49b6cc 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1709,8 +1709,26 @@ static enum port dvo_port_to_port(struct
drm_i915_private *dev_priv,
[PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
[PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
};
+ /*
+* Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E,
+* PORT_F and PORT_G, we need to map that to correct VBT sections.
+*/
+ static const int adls_port_mapping[][3] = {
+ [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
+ [PORT_B] = { -1 },
+ [PORT_C] = { -1 },
+ [PORT_TC1] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
+ [PORT_TC2] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+ [PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+ [PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 },
+ };
- if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv))
+ return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping),
+ ARRAY_SIZE(adls_port_mapping[0]),
+ adls_port_mapping,
+ dvo_port);
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
ARRAY_SIZE(rkl_port_mapping[0]),
rkl_port_mapping,
@@ -2667,27 +2685,44 @@ enum aux_ch intel_bios_port_aux_ch(struct
drm_i915_private *dev_priv,
return aux_ch;
}
+ /*
+* RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
+* map to DDI A,B,TC1,TC2 respectively.
+*
+* ADL-S VBT uses PHY based mapping. Combo PHYs A,B,C,D,E
+* map to DDI A,TC1,TC2,TC3,TC4 respectively.
+*/
switch (info->alternate_aux_channel) {
case DP_AUX_A:
aux_ch = AUX_CH_A;
break;
case DP_AUX_B:
- aux_ch = AUX_CH_B;
+ if (IS_ALDERLAKE_S(dev_priv))
+ aux_ch = AUX_CH_USBC1;
+ else
+ aux_ch = AUX_CH_B;
break;
case DP_AUX_C:
- /*
-* RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
-* map to DDI A,B,TC1,TC2 respectively.
-*/
- aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
- AUX_CH_USBC1 : AUX_CH_C;
+ if (IS_ALDERLAKE_S(dev_priv))
+ aux_ch = AUX_CH_USBC2;
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ aux_ch = AUX_CH_USBC1;
+ else
+ aux_ch = AUX_CH_C;
break;
case DP_AUX_D:
- aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
- AUX_CH_USBC2 : AUX_CH_D;
+ if (IS_ALDERLAKE_S(dev_priv))
+ aux_ch = AUX_CH_USBC3;
+ else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ aux_ch = AUX_CH_USBC2;
+ else
+ aux_ch = AUX_CH_D;
break;
case DP_AUX_E:
- aux_ch = AUX_CH_E;
+ if (IS_ALDERLAKE_S(dev_priv))
+ aux_ch = AUX_CH_USBC4;
+ else
+ aux_ch = AUX_CH_E;
break;
case DP_AUX_F:
aux_ch = AUX_CH_F;
--
2.27.0
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[Intel-gfx] [PATCH 13/22] drm/i915/adl_s: Update combo PHY master/slave relationships
From: Matt Roper ADL-S switches up which PHYs are considered a master to other PHYs; PHY-C is no longer a master, but PHY-D is now. Bspec: 49291 Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Lucas De Marchi Signed-off-by: Matt Roper Signed-off-by: Aditya Swarup Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_combo_phy.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 996ae0608a62..dd45cbafcf42 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -246,14 +246,21 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) * RKL,DG1: * A(master) -> B(slave) * C(master) -> D(slave) +* ADL-S: +* A(master) -> B(slave), C(slave) +* D(master) -> E(slave) * * We must set the IREFGEN bit for any PHY acting as a master * to another PHY. */ - if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy == PHY_C) + if (phy == PHY_A) return true; + else if (IS_ALDERLAKE_S(dev_priv)) + return phy == PHY_D; + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) + return phy == PHY_C; - return phy == PHY_A; + return false; } static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, -- 2.27.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/22] drm/i915/adl_s: Add adl-s ddc pin mapping
ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E.
Combo PHY A still uses the old ddc pin mapping.
From VBT, ddc pin info suggests the following mapping:
VBTDRIVER
DDI B->ddc_pin=2 should translate to PORT_D->0x9
DDI C->ddc_pin=3 should translate to PORT_E->0xa
DDI D->ddc_pin=4 should translate to PORT_F->0xb
DDI E->ddc_pin=5 should translate to PORT_G->0xc
Adding pin map to facilitate this translation as we cannot use existing
icl ddc pin map due to conflict with DDI B and DDI C info.
Bspec:20124
v2: Replace IS_ALDERLAKE_S() with HAS_PCH_ADP() as the pin map pairing
depends on the PCH being used rather than the platform.(mdroper)
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/display/intel_bios.c | 13 +++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4
3 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 4cc949b228f2..9dc67c03ffc0 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1623,12 +1623,23 @@ static const u8 icp_ddc_pin_map[] = {
[TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
};
+static const u8 adls_ddc_pin_map[] = {
+ [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+ [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
+ [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP,
+ [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP,
+ [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,
+};
+
static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
{
const u8 *ddc_pin_map;
int n_entries;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
+ if (HAS_PCH_ADP(dev_priv)) {
+ ddc_pin_map = adls_ddc_pin_map;
+ n_entries = ARRAY_SIZE(adls_ddc_pin_map);
+ } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
return vbt_pin;
} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
ddc_pin_map = icp_ddc_pin_map;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index e10fdb369daa..060a13b63aa9 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3135,6 +3135,22 @@ static u8 dg1_port_to_ddc_pin(struct drm_i915_private
*dev_priv, enum port port)
return intel_port_to_phy(dev_priv, port) + 1;
}
+static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port
port)
+{
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+
+ WARN_ON(port == PORT_B || port == PORT_C);
+
+ /*
+* Pin mapping for ADL-S requires TC pins for all combo phy outputs
+* except first combo output.
+*/
+ if (IS_ALDERLAKE_S(dev_priv) && phy >= PHY_B)
+ return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
+
+ return GMBUS_PIN_1_BXT + phy;
+}
+
static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
enum port port)
{
@@ -3172,7 +3188,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder
*encoder)
return ddc_pin;
}
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ if (IS_ALDERLAKE_S(dev_priv))
+ ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
else if (IS_ROCKETLAKE(dev_priv))
ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 49b4b5fca941..32d1b4f05760 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -325,6 +325,10 @@ enum vbt_gmbus_ddi {
ICL_DDC_BUS_PORT_4,
TGL_DDC_BUS_PORT_5,
TGL_DDC_BUS_PORT_6,
+ ADLS_DDC_BUS_PORT_TC1 = 0x2,
+ ADLS_DDC_BUS_PORT_TC2,
+ ADLS_DDC_BUS_PORT_TC3,
+ ADLS_DDC_BUS_PORT_TC4
};
#define DP_AUX_A 0x40
--
2.27.0
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[Intel-gfx] [PATCH 10/22] drm/i915/adl_s: Initialize display for ADL-S
Initialize display outputs for ADL-S. ADL-S has 5 display
outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs.
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/display/intel_display.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0ff0eeabab8c..19ed51e6c647 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17627,7 +17627,13 @@ static void intel_setup_outputs(struct
drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */
+ intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */
+ intel_ddi_init(dev_priv, PORT_F); /* DDI TC3 */
+ intel_ddi_init(dev_priv, PORT_G); /* DDI TC4 */
+ } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_TC1);
--
2.27.0
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[Intel-gfx] [PATCH 09/22] drm/i915/adl_s: Configure Port clock registers for ADL-S
Add changes to configure port clock registers for ADL-S. Combo phy port
clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers.
The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S
translates to
DDI A -> DDIA
DDI B -> USBC1
DDI I -> USBC2
For DPCLKA_CFGCR1
DDI J -> USBC3
DDI K -> USBC4
Bspec: 50287
Bspec: 53812
Bspec: 53723
v2: Replace I915_READ() with intel_de_read().(Jani)
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/display/intel_ddi.c | 64 +---
drivers/gpu/drm/i915/display/intel_display.c | 18 +-
drivers/gpu/drm/i915/i915_reg.h | 23 ++-
3 files changed, 82 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 76e975b4765b..fdf692be2bc3 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3088,25 +3088,30 @@ static void icl_map_plls_to_ports(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- u32 val;
+ u32 val, mask, sel;
+ i915_reg_t reg;
+
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ reg = ADLS_DPCLKA_CFGCR(phy);
+ mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
+ sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
+ } else if (IS_ROCKETLAKE(dev_priv)) {
+ reg = ICL_DPCLKA_CFGCR0;
+ mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ } else {
+ reg = ICL_DPCLKA_CFGCR0;
+ mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+ }
mutex_lock(&dev_priv->dpll.lock);
- val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ val = intel_de_read(dev_priv, reg);
drm_WARN_ON(&dev_priv->drm,
(val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
if (intel_phy_is_combo(dev_priv, phy)) {
- u32 mask, sel;
-
- if (IS_ROCKETLAKE(dev_priv)) {
- mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
- } else {
- mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
- }
-
/*
* Even though this register references DDIs, note that we
* want to pass the PHY rather than the port (DDI). For
@@ -3119,12 +3124,12 @@ static void icl_map_plls_to_ports(struct intel_encoder
*encoder,
*/
val &= ~mask;
val |= sel;
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
- intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ intel_de_write(dev_priv, reg, val);
+ intel_de_posting_read(dev_priv, reg);
}
val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+ intel_de_write(dev_priv, reg, val);
mutex_unlock(&dev_priv->dpll.lock);
}
@@ -3150,9 +3155,17 @@ static void icl_unmap_plls_to_ports(struct intel_encoder
*encoder)
mutex_lock(&dev_priv->dpll.lock);
- val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ if (IS_ALDERLAKE_S(dev_priv))
+ val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy));
+ else
+ val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+
val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+
+ if (IS_ALDERLAKE_S(dev_priv))
+ intel_de_write(dev_priv, ADLS_DPCLKA_CFGCR(phy), val);
+ else
+ intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
mutex_unlock(&dev_priv->dpll.lock);
}
@@ -3192,13 +3205,19 @@ static void icl_sanitize_port_clk_off(struct
drm_i915_private *dev_priv,
u32 port_mask, bool ddi_clk_needed)
{
enum port port;
+ bool ddi_clk_off;
u32 val;
- val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
for_each_port_masked(port, port_mask) {
enum phy phy = intel_port_to_phy(dev_priv, port);
- bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
- phy);
+
+ if (IS_ALDERLAKE_S(dev_priv))
+ val = intel_de_read(dev_priv, ADLS_DPCLKA_CFGCR(phy));
[Intel-gfx] [PATCH 06/22] drm/i915/adl_s: Add Interrupt Support
From: Anusha Srivatsa ADLS follows ICP/TGP like interrupts. v2: Use "INTEL_PCH_TYPE(dev_priv) >= PCH_ICP" of hpd_icp (Lucas) Cc: Lucas De Marchi Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: José Roberto de Souza Signed-off-by: Anusha Srivatsa Signed-off-by: Lucas De Marchi Signed-off-by: Aditya Swarup Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/i915_irq.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b245109f73e3..d1b4893d6c92 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -191,8 +191,7 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) if (HAS_PCH_DG1(dev_priv)) hpd->pch_hpd = hpd_sde_dg1; - else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) || -HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) hpd->pch_hpd = hpd_icp; else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv)) hpd->pch_hpd = hpd_spt; -- 2.27.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 00/22] Introduce Alderlake-S
Rev 3 with all the comments addressed from Rev 2: https://patchwork.freedesktop.org/series/82917/ Aditya Swarup (9): drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping drm/i915/tgl: Add bound checks and simplify TGL REVID macros drm/i915/adl_s: Configure DPLL for ADL-S drm/i915/adl_s: Configure Port clock registers for ADL-S drm/i915/adl_s: Initialize display for ADL-S drm/i915/adl_s: Add adl-s ddc pin mapping drm/i915/adl_s: Add vbt port and aux channel settings for adls drm/i915/adl_s: Add display WAs for ADL-S drm/i915/adl_s: Add GT and CTX WAs for ADL-S Anusha Srivatsa (4): drm/i915/adl_s: Add PCH support drm/i915/adl_s: Add Interrupt Support drm/i915/adl_s: Add PHYs for Alderlake S drm/i915/adl_s: Load DMC Caz Yokoyama (3): drm/i915/adl_s: Add ADL-S platform info and PCI ids x86/gpu: add ADL_S stolen memory support drm/i915/adl_s: MCHBAR memory info registers are moved José Roberto de Souza (1): drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION Lucas De Marchi (1): drm/i915/adl_s: Add power wells Matt Roper (3): drm/i915/adl_s: Update combo PHY master/slave relationships drm/i915/adl_s: Update PHY_MISC programming drm/i915/adl_s: Re-use TGL GuC/HuC firmware Tejas Upadhyay (1): drm/i915/adl_s: Update memory bandwidth parameters arch/x86/kernel/early-quirks.c| 1 + drivers/gpu/drm/i915/display/intel_bios.c | 70 +-- drivers/gpu/drm/i915/display/intel_bw.c | 8 ++ .../gpu/drm/i915/display/intel_combo_phy.c| 23 +++- drivers/gpu/drm/i915/display/intel_csr.c | 10 +- drivers/gpu/drm/i915/display/intel_ddi.c | 64 ++ drivers/gpu/drm/i915/display/intel_display.c | 36 +- .../drm/i915/display/intel_display_power.c| 11 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++- drivers/gpu/drm/i915/display/intel_psr.c | 4 +- drivers/gpu/drm/i915/display/intel_sprite.c | 8 +- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 119 -- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +- drivers/gpu/drm/i915/i915_drv.h | 72 --- drivers/gpu/drm/i915/i915_irq.c | 5 +- drivers/gpu/drm/i915/i915_pci.c | 13 ++ drivers/gpu/drm/i915/i915_reg.h | 54 +++- drivers/gpu/drm/i915/intel_device_info.c | 9 +- drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_dram.c | 23 +++- drivers/gpu/drm/i915/intel_pch.c | 8 +- drivers/gpu/drm/i915/intel_pch.h | 3 + drivers/gpu/drm/i915/intel_pm.c | 2 +- include/drm/i915_pciids.h | 13 ++ 26 files changed, 489 insertions(+), 134 deletions(-) -- 2.27.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/22] drm/i915/adl_s: Add PHYs for Alderlake S
From: Anusha Srivatsa
Alderlake-S has 5 combo phys, add reg definitions for
combo phys and update the port to phy helper for ADL-S.
v2:
- Change IS_GEN() >= 12 to IS_TIGERLAKE() in intel_phy_is_tc()
and return false for platforms RKL,DG1 and ADLS.(mdroper)
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++
drivers/gpu/drm/i915/i915_reg.h | 5 -
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9187a20a8aca..2d1c5bfe4032 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7397,6 +7397,8 @@ bool intel_phy_is_combo(struct drm_i915_private
*dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
return false;
+ else if (IS_ALDERLAKE_S(dev_priv))
+ return phy <= PHY_E;
else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
return phy <= PHY_D;
else if (IS_JSL_EHL(dev_priv))
@@ -7409,9 +7411,7 @@ bool intel_phy_is_combo(struct drm_i915_private
*dev_priv, enum phy phy)
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
- if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
- return false;
- else if (INTEL_GEN(dev_priv) >= 12)
+ if (IS_TIGERLAKE(dev_priv))
return phy >= PHY_D && phy <= PHY_I;
else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv))
return phy >= PHY_C && phy <= PHY_F;
@@ -7421,7 +7421,9 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv,
enum phy phy)
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
- if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
+ if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
+ return PHY_B + port - PORT_TC1;
+ else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
return PHY_C + port - PORT_TC1;
else if (IS_JSL_EHL(i915) && port == PORT_D)
return PHY_A;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cdc67f583a9c..60a0d4c35cae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1874,10 +1874,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _ICL_COMBOPHY_B0x6C000
#define _EHL_COMBOPHY_C0x16
#define _RKL_COMBOPHY_D0x161000
+#define _ADL_COMBOPHY_E0x16B000
+
#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
_ICL_COMBOPHY_B, \
_EHL_COMBOPHY_C, \
- _RKL_COMBOPHY_D)
+ _RKL_COMBOPHY_D, \
+ _ADL_COMBOPHY_E)
/* CNL/ICL Port CL_DW registers */
#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
--
2.27.0
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[Intel-gfx] [PATCH 08/22] drm/i915/adl_s: Configure DPLL for ADL-S
Add changes for configuring DPLL for ADL-S
- Reusing DG1 DPLL 2 & DPLL 3 for ADL-S
- Extend CNL macro to choose DPLL_ENABLE
for ADL-S.
- Select CFGCR0 and CFGCR1 for ADL-S plls.
On BSpec: 53720 PLL arrangement dig for adls:
DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1)
DPLL3 cfgcr is programmed using _ADLS_DPLL4_CFGCR(0/1)
v2 (Lucas): add missing update_ref_clks
Bspec: 50288
Bspec: 50289
Bspec: 49443
v3 : Adding another bit to HDPORT_DPLL_USED_MASK bitfield
for DPLL3_USED.(mdroper)
Bspec: 53707
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 +--
drivers/gpu/drm/i915/i915_reg.h | 21 +-
2 files changed, 53 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f6ad257a260e..529b1d569af2 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3559,7 +3559,13 @@ static bool icl_get_combo_phy_dpll(struct
intel_atomic_state *state,
icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
- if (IS_DG1(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ dpll_mask =
+ BIT(DPLL_ID_DG1_DPLL3) |
+ BIT(DPLL_ID_DG1_DPLL2) |
+ BIT(DPLL_ID_ICL_DPLL1) |
+ BIT(DPLL_ID_ICL_DPLL0);
+ } else if (IS_DG1(dev_priv)) {
if (port == PORT_D || port == PORT_E) {
dpll_mask =
BIT(DPLL_ID_DG1_DPLL2) |
@@ -3865,7 +3871,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private
*dev_priv,
if (!(val & PLL_ENABLE))
goto out;
- if (IS_DG1(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ hw_state->cfgcr0 = intel_de_read(dev_priv,
ADLS_DPLL_CFGCR0(id));
+ hw_state->cfgcr1 = intel_de_read(dev_priv,
ADLS_DPLL_CFGCR1(id));
+ } else if (IS_DG1(dev_priv)) {
hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
} else if (IS_ROCKETLAKE(dev_priv)) {
@@ -3921,7 +3930,10 @@ static void icl_dpll_write(struct drm_i915_private
*dev_priv,
const enum intel_dpll_id id = pll->info->id;
i915_reg_t cfgcr0_reg, cfgcr1_reg;
- if (IS_DG1(dev_priv)) {
+ if (IS_ALDERLAKE_S(dev_priv)) {
+ cfgcr0_reg = ADLS_DPLL_CFGCR0(id);
+ cfgcr1_reg = ADLS_DPLL_CFGCR1(id);
+ } else if (IS_DG1(dev_priv)) {
cfgcr0_reg = DG1_DPLL_CFGCR0(id);
cfgcr1_reg = DG1_DPLL_CFGCR1(id);
} else if (IS_ROCKETLAKE(dev_priv)) {
@@ -4384,6 +4396,22 @@ static const struct intel_dpll_mgr dg1_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info adls_plls[] = {
+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
+ { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr adls_pll_mgr = {
+ .dpll_info = adls_plls,
+ .get_dplls = icl_get_dplls,
+ .put_dplls = icl_put_dplls,
+ .update_ref_clks = icl_update_dpll_ref_clks,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -4397,7 +4425,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (IS_DG1(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv))
+ dpll_mgr = &adls_pll_mgr;
+ else if (IS_DG1(dev_priv))
dpll_mgr = &dg1_pll_mgr;
else if (IS_ROCKETLAKE(dev_priv))
dpll_mgr = &rkl_pll_mgr;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 60a0d4c35cae..999b4eb422db 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2930,7 +2930,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
#define HDPORT_STATE _MMIO(0x45050)
-#define HDPORT_DPLL_USED_MASKREG_GENMASK(14, 12)
+#define HDPORT_DPLL_USED_MASKREG_GENMASK(15, 12)
#define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2)
#define HDPORT_PHY_USED_HDMI(phy)REG_BIT(2 * (phy) + 1)
#define HDPORT_ENABLED REG_BIT(0)
@@ -10345,11 +10345,14 @@ enum skl_power_gate {
/* CNL PLL */
#define DPLL0_ENABLE 0x46010
#define DPLL1_ENABLE 0x46014
+#define _ADLS_DPLL2_ENABLE 0x
[Intel-gfx] [PATCH 01/22] drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping
Fix TGL REVID macros to fetch correct display/gt stepping based
on SOC rev id from INTEL_REVID() macro. Previously, we were just
returning the first element of the revid array instead of using
the correct index based on SOC rev id.
Fixes: ("drm/i915/tgl: Fix stepping WA matching")
Cc: José Roberto de Souza
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Aditya Swarup
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_drv.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fc1090c6889c..2e2149c9a2f4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1580,9 +1580,9 @@ static inline const struct i915_rev_steppings *
tgl_revids_get(struct drm_i915_private *dev_priv)
{
if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
- return tgl_uy_revids;
+ return &tgl_uy_revids[INTEL_REVID(dev_priv)];
else
- return tgl_revids;
+ return &tgl_revids[INTEL_REVID(dev_priv)];
}
#define IS_TGL_DISP_REVID(p, since, until) \
@@ -1592,14 +1592,14 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
#define IS_TGL_UY_GT_REVID(p, since, until) \
((IS_TGL_U(p) || IS_TGL_Y(p)) && \
-tgl_uy_revids->gt_stepping >= (since) && \
-tgl_uy_revids->gt_stepping <= (until))
+tgl_uy_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
+tgl_uy_revids[INTEL_REVID(p)].gt_stepping <= (until))
#define IS_TGL_GT_REVID(p, since, until) \
(IS_TIGERLAKE(p) && \
!(IS_TGL_U(p) || IS_TGL_Y(p)) && \
-tgl_revids->gt_stepping >= (since) && \
-tgl_revids->gt_stepping <= (until))
+tgl_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
+tgl_revids[INTEL_REVID(p)].gt_stepping <= (until))
#define RKL_REVID_A0 0x0
#define RKL_REVID_B0 0x1
--
2.27.0
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[Intel-gfx] [PATCH 05/22] drm/i915/adl_s: Add PCH support
From: Anusha Srivatsa
Add support for Alderpoint(ADP) PCH used with Alderlake-S.
v2:
- Use drm_dbg_kms and drm_WARN_ON based on Jani's feedback.(aswarup)
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Caz Yokoyama
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Signed-off-by: Anusha Srivatsa
Signed-off-by: Aditya Swarup
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/intel_pch.c | 8 +++-
drivers/gpu/drm/i915/intel_pch.h | 3 +++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index f31c0dabd0cc..2a6d70f247e8 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -128,6 +128,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
unsigned short id)
drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
return PCH_JSP;
+ case INTEL_PCH_ADP_DEVICE_ID_TYPE:
+ drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
+ drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv));
+ return PCH_ADP;
default:
return PCH_NONE;
}
@@ -155,7 +159,9 @@ intel_virt_detect_pch(const struct drm_i915_private
*dev_priv)
* make an educated guess as to which PCH is really there.
*/
- if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
+ if (IS_ALDERLAKE_S(dev_priv))
+ id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
+ else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
else if (IS_JSL_EHL(dev_priv))
id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 06d2cd50af0b..7318377503b0 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -26,6 +26,7 @@ enum intel_pch {
PCH_JSP,/* Jasper Lake PCH */
PCH_MCC,/* Mule Creek Canyon PCH */
PCH_TGP,/* Tiger Lake PCH */
+ PCH_ADP,/* Alder Lake PCH */
/* Fake PCHs, functionality handled on the same PCI dev */
PCH_DG1 = 1024,
@@ -53,12 +54,14 @@ enum intel_pch {
#define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380
#define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
#define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880
+#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
+#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_ADP)
#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_DG1)
#define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_JSP)
#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_MCC)
--
2.27.0
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[Intel-gfx] [PATCH 02/22] drm/i915/tgl: Add bound checks and simplify TGL REVID macros
Add bound checks for TGL REV ID array. Since, there might
be a possibility of using older kernels on latest platform
revisions, resulting in out of bounds access for rev ID array.
In this scenario, use the latest rev ID available and apply
those WAs.
Also, simplify GT macros for TGL rev ID to reuse tgl_revids_get().
Cc: José Roberto de Souza
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Aditya Swarup
---
drivers/gpu/drm/i915/i915_drv.h | 34 +++--
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2e2149c9a2f4..37c2df19ce52 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1573,16 +1573,30 @@ enum {
TGL_REVID_D0,
};
-extern const struct i915_rev_steppings tgl_uy_revids[];
-extern const struct i915_rev_steppings tgl_revids[];
+#define TGL_UY_REVIDS_SIZE 4
+#define TGL_REVIDS_SIZE2
+
+extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
+extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
static inline const struct i915_rev_steppings *
tgl_revids_get(struct drm_i915_private *dev_priv)
{
- if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))
- return &tgl_uy_revids[INTEL_REVID(dev_priv)];
- else
- return &tgl_revids[INTEL_REVID(dev_priv)];
+ u8 revid = INTEL_REVID(dev_priv);
+ u8 size;
+ const struct i915_rev_steppings *tgl_revid_tbl;
+
+ if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
+ tgl_revid_tbl = tgl_uy_revids;
+ size = ARRAY_SIZE(tgl_uy_revids);
+ } else {
+ tgl_revid_tbl = tgl_revids;
+ size = ARRAY_SIZE(tgl_revids);
+ }
+
+ revid = min_t(u8, revid, size - 1);
+
+ return &tgl_revid_tbl[revid];
}
#define IS_TGL_DISP_REVID(p, since, until) \
@@ -1592,14 +1606,14 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
#define IS_TGL_UY_GT_REVID(p, since, until) \
((IS_TGL_U(p) || IS_TGL_Y(p)) && \
-tgl_uy_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
-tgl_uy_revids[INTEL_REVID(p)].gt_stepping <= (until))
+tgl_revids_get(p)->gt_stepping >= (since) && \
+tgl_revids_get(p)->gt_stepping <= (until))
#define IS_TGL_GT_REVID(p, since, until) \
(IS_TIGERLAKE(p) && \
!(IS_TGL_U(p) || IS_TGL_Y(p)) && \
-tgl_revids[INTEL_REVID(p)].gt_stepping >= (since) && \
-tgl_revids[INTEL_REVID(p)].gt_stepping <= (until))
+tgl_revids_get(p)->gt_stepping >= (since) && \
+tgl_revids_get(p)->gt_stepping <= (until))
#define RKL_REVID_A0 0x0
#define RKL_REVID_B0 0x1
--
2.27.0
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[Intel-gfx] [PATCH 04/22] x86/gpu: add ADL_S stolen memory support
From: Caz Yokoyama
ADL_S re-uses the same stolen memory registers as TGL and ICL.
This patch has a dependency on:
("drm/i915/adl_s: Add ADL-S platform info and PCI ids")
Bspec: 52055
Bspec: 49589
Bspec: 49636
Cc: Lucas De Marchi
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: x...@kernel.org
Cc: Ingo Molnar ,
Cc: Thomas Gleixner ,
Cc: Borislav Petkov
Signed-off-by: Caz Yokoyama
Signed-off-by: Aditya Swarup
Reviewed-by: Lucas De Marchi
---
arch/x86/kernel/early-quirks.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index a4b5af03dcc1..6edd1e2ee8af 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -551,6 +551,7 @@ static const struct pci_device_id intel_early_ids[]
__initconst = {
INTEL_EHL_IDS(&gen11_early_ops),
INTEL_TGL_12_IDS(&gen11_early_ops),
INTEL_RKL_IDS(&gen11_early_ops),
+ INTEL_ADLS_IDS(&gen11_early_ops),
};
struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0,
0);
--
2.27.0
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[Intel-gfx] [PATCH 03/22] drm/i915/adl_s: Add ADL-S platform info and PCI ids
From: Caz Yokoyama
- Add the initial platform information for Alderlake-S.
- Specify ppgtt_size value
- Add dma_mask_size
- Add ADLS REVIDs
- HW tracking(Selective Update Tracking Enable) has been
removed from ADLS. Disable PSR2 till we enable software/
manual tracking.
v2:
- Add support for different ADLS SOC steppings to select
correct GT/DISP stepping based on Bspec 53655 based on
feedback from Matt Roper.(aswarup)
v3:
- Make display/gt steppings info generic for reuse with TGL and ADLS.
- Modify the macros to reuse tgl_revids_get()
- Add HTI support to adls device info.(mdroper)
Bspec: 53597
Bspec: 53648
Bspec: 53655
Bspec: 48028
Bspec: 53650
BSpec: 50422
Cc: José Roberto de Souza
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Imre Deak
Signed-off-by: Caz Yokoyama
Signed-off-by: Aditya Swarup
---
.../drm/i915/display/intel_display_power.c| 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 4 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 28 +++-
drivers/gpu/drm/i915/i915_drv.h | 45 ++-
drivers/gpu/drm/i915/i915_pci.c | 13 ++
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 +-
include/drm/i915_pciids.h | 13 ++
10 files changed, 86 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index fe2d90bba536..06c036e2092c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5283,7 +5283,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private
*dev_priv)
int config, i;
if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
- IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
+ IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0))
/* Wa_1409767108:tgl,dg1 */
table = wa_1409767108_buddy_page_masks;
else
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index d9a395c486d3..1771f5000a45 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
if (dev_priv->psr.psr2_sel_fetch_enabled) {
/* WA 1408330847 */
- if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+ if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK,
@@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
/* WA 1408330847 */
if (dev_priv->psr.psr2_sel_fetch_enabled &&
- (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+ (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index b7e208816074..e19d4f873b94 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -3032,7 +3032,7 @@ static bool gen12_plane_supports_mc_ccs(struct
drm_i915_private *dev_priv,
{
/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
- IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
+ IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_C0))
return false;
return plane_id < PLANE_SPRITE4;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 7c6b21ced56f..3db57b577a79 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -71,16 +71,24 @@ const struct i915_rev_steppings kbl_revids[] = {
};
const struct i915_rev_steppings tgl_uy_revids[] = {
- [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
- [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
- [2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
- [3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
+ [0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 },
+ [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_C0 },
+ [2] = { .gt_stepping = REVID_B1, .disp_stepping
Re: [Intel-gfx] [PATCH] drm/i915: Reduce duplicated switch cases in hpd code
On Fri, Dec 4, 2020 at 10:23 AM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> With GEN11_HOTPLUG_CTL_LONG_DETECT(), SHOTPLUG_CTL_DDI_HPD_LONG_DETECT()
> and ICP_TC_HPD_LONG_DETECT() taking the hpd_pin as their argument
> we can remove some duplication in the long_detect() switch statements.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_irq.c | 19 +++
> 1 file changed, 3 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b245109f73e3..491f82500d68 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1044,17 +1044,12 @@ static bool gen11_port_hotplug_long_detect(enum
> hpd_pin pin, u32 val)
> {
> switch (pin) {
> case HPD_PORT_TC1:
case HPD_PORT_TC1 ... HPD_PORT_TC6
?
in any case,
Reviewed-by: Lucas De Marchi
Lucas De Marchi
> - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC1);
> case HPD_PORT_TC2:
> - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC2);
> case HPD_PORT_TC3:
> - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC3);
> case HPD_PORT_TC4:
> - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC4);
> case HPD_PORT_TC5:
> - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC5);
> case HPD_PORT_TC6:
> - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC6);
> + return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin);
> default:
> return false;
> }
> @@ -1078,13 +1073,10 @@ static bool icp_ddi_port_hotplug_long_detect(enum
> hpd_pin pin, u32 val)
> {
> switch (pin) {
> case HPD_PORT_A:
> - return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_A);
> case HPD_PORT_B:
> - return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_B);
> case HPD_PORT_C:
> - return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_C);
> case HPD_PORT_D:
> - return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_D);
> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin);
> default:
> return false;
> }
> @@ -1094,17 +1086,12 @@ static bool icp_tc_port_hotplug_long_detect(enum
> hpd_pin pin, u32 val)
> {
> switch (pin) {
> case HPD_PORT_TC1:
> - return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC1);
> case HPD_PORT_TC2:
> - return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC2);
> case HPD_PORT_TC3:
> - return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC3);
> case HPD_PORT_TC4:
> - return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC4);
> case HPD_PORT_TC5:
> - return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC5);
> case HPD_PORT_TC6:
> - return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC6);
> + return val & ICP_TC_HPD_LONG_DETECT(pin);
> default:
> return false;
> }
> --
> 2.26.2
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/dp: Compute the correct slice count for VDSC on DP
== Series Details ==
Series: drm/i915/display/dp: Compute the correct slice count for VDSC on DP
URL : https://patchwork.freedesktop.org/series/84599/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9444_full -> Patchwork_19064_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19064_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_ctx_exec@basic-close-race}:
- shard-glk: [DMESG-FAIL][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-glk7/igt@gem_ctx_e...@basic-close-race.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19064/shard-glk2/igt@gem_ctx_e...@basic-close-race.html
New tests
-
New tests have been introduced between CI_DRM_9444_full and
Patchwork_19064_full:
### New CI tests (1) ###
* boot:
- Statuses : 175 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_19064_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_whisper@basic-fds-priority:
- shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95])
+1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-glk2/igt@gem_exec_whis...@basic-fds-priority.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19064/shard-glk3/igt@gem_exec_whis...@basic-fds-priority.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#198] /
[i915#2405])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl6/igt@gem_workarou...@suspend-resume-fd.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19064/shard-skl9/igt@gem_workarou...@suspend-resume-fd.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding:
- shard-skl: [PASS][7] -> [FAIL][8] ([i915#54]) +2 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl4/igt@kms_cursor_...@pipe-b-cursor-128x42-sliding.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19064/shard-skl6/igt@kms_cursor_...@pipe-b-cursor-128x42-sliding.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#79])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl5/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19064/shard-skl4/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-dp1:
- shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2122])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-kbl7/igt@kms_flip@plain-flip-fb-recreate-interrupti...@b-dp1.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19064/shard-kbl7/igt@kms_flip@plain-flip-fb-recreate-interrupti...@b-dp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
- shard-apl: [PASS][13] -> [FAIL][14] ([i915#49])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-apl2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19064/shard-apl2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#49])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-glk2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19064/shard-glk4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
- shard-kbl: [PASS][17] -> [FAIL][18] ([i915#49])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-kbl7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19064/shard-kbl3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl2/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19064/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +2 similar
issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Inject a failure into the initial modeset (rev2)
== Series Details == Series: drm/i915/display: Inject a failure into the initial modeset (rev2) URL : https://patchwork.freedesktop.org/series/84592/ State : success == Summary == CI Bug Log - changes from CI_DRM_9444_full -> Patchwork_19062_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_9444_full and Patchwork_19062_full: ### New CI tests (1) ### * boot: - Statuses : 174 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19062_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#2369]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl3/igt@gem_exec_capture@p...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/shard-skl1/igt@gem_exec_capture@p...@rcs0.html * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][3] -> [INCOMPLETE][4] ([i915#2405]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-apl8/igt@gem_soft...@noreloc-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/shard-apl2/igt@gem_soft...@noreloc-s3.html * igt@gem_userptr_blits@huge-split: - shard-apl: [PASS][5] -> [INCOMPLETE][6] ([i915#2502]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-apl7/igt@gem_userptr_bl...@huge-split.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/shard-apl7/igt@gem_userptr_bl...@huge-split.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][7] -> [FAIL][8] ([i915#454]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-iclb5/igt@i915_pm...@dc6-psr.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/shard-iclb6/igt@i915_pm...@dc6-psr.html * igt@i915_selftest@live@execlists: - shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([i915#1037] / [i915#2268]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-tglb7/igt@i915_selftest@l...@execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/shard-tglb1/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_heartbeat: - shard-skl: [PASS][11] -> [DMESG-FAIL][12] ([i915#2291] / [i915#541]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl7/igt@i915_selftest@live@gt_heartbeat.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/shard-skl3/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2574]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-tglb2/igt@kms_async_fl...@test-time-stamp.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/shard-tglb1/igt@kms_async_fl...@test-time-stamp.html * igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#54]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl9/igt@kms_cursor_...@pipe-b-cursor-128x128-sliding.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/shard-skl10/igt@kms_cursor_...@pipe-b-cursor-128x128-sliding.html * igt@kms_cursor_legacy@flip-vs-cursor-legacy: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#2346]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl6/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/shard-skl6/igt@kms_cursor_leg...@flip-vs-cursor-legacy.html * igt@kms_flip@flip-vs-expired-vblank@b-edp1: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#79]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl5/igt@kms_flip@flip-vs-expired-vbl...@b-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/shard-skl10/igt@kms_flip@flip-vs-expired-vbl...@b-edp1.html * igt@kms_flip@plain-flip-ts-check@a-edp1: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#2122]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl4/igt@kms_flip@plain-flip-ts-ch...@a-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/shard-skl4/igt@kms_flip@plain-flip-ts-ch...@a-edp1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: - shard-apl: [PASS][23] -> [FAIL][24] ([i915#49]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-apl2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/shard-apl8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html - shard-glk: [PASS][25] -> [FAIL][26] ([i915#49]) [25]
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add support for Intel's eDP backlight controls (rev3)
== Series Details == Series: drm/i915: Add support for Intel's eDP backlight controls (rev3) URL : https://patchwork.freedesktop.org/series/81702/ State : success == Summary == CI Bug Log - changes from CI_DRM_9444 -> Patchwork_19066 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19066/index.html New tests - New tests have been introduced between CI_DRM_9444 and Patchwork_19066: ### New CI tests (1) ### * boot: - Statuses : 1 fail(s) 38 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19066 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19066/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#2411] / [i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19066/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@prime_vgem@basic-write: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@prime_v...@basic-write.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19066/fi-tgl-y/igt@prime_v...@basic-write.html Possible fixes * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19066/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 39) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9444 -> Patchwork_19066 CI-20190529: 20190529 CI_DRM_9444: cee8f6ace633b555c64b14938577e6da02710a0b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5881: 10d4e2e9177eb747b9f2ab9122e3ab60e91654fb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19066: 0246c3bf43a014e16ba421f18a17c4e17898cdd3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0246c3bf43a0 drm/dp: Revert "drm/dp: Introduce EDID-based quirks" 1cd0fee4656f drm/i915/dp: Allow forcing specific interfaces through enable_dpcd_backlight 0f59b8d11611 drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now) e013bc041067 drm/i915/dp: Add register definitions for Intel HDR backlight interface 9af1a6377bd0 drm/i915/dp: Rename eDP VESA backlight interface functions ae85f27764dd drm/i915: Keep track of pwm-related backlight hooks separately f6028d739181 drm/i915: Pass down brightness values to enable/disable backlight callbacks 9233620226ff drm/i915: Rename pwm_* backlight callbacks to ext_pwm_* f28a72ff60f8 drm/i915/dp: Program source OUI on eDP panels == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19066/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Disable outputs during unregister (rev2)
== Series Details == Series: drm/i915: Disable outputs during unregister (rev2) URL : https://patchwork.freedesktop.org/series/84371/ State : success == Summary == CI Bug Log - changes from CI_DRM_9444_full -> Patchwork_19060_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_9444_full and Patchwork_19060_full: ### New CI tests (1) ### * boot: - Statuses : 173 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19060_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_whisper@basic-contexts-all: - shard-glk: [PASS][1] -> [INCOMPLETE][2] ([i915#2405]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-glk5/igt@gem_exec_whis...@basic-contexts-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/shard-glk3/igt@gem_exec_whis...@basic-contexts-all.html * igt@i915_selftest@live@gt_heartbeat: - shard-skl: [PASS][3] -> [DMESG-FAIL][4] ([i915#2291] / [i915#541]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl7/igt@i915_selftest@live@gt_heartbeat.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/shard-skl3/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding: - shard-skl: [PASS][5] -> [FAIL][6] ([i915#54]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl7/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/shard-skl3/igt@kms_cursor_...@pipe-a-cursor-64x64-sliding.html * igt@kms_flip@flip-vs-expired-vblank@a-dp1: - shard-apl: [PASS][7] -> [FAIL][8] ([i915#79]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-apl1/igt@kms_flip@flip-vs-expired-vbl...@a-dp1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/shard-apl3/igt@kms_flip@flip-vs-expired-vbl...@a-dp1.html * igt@kms_flip@wf_vblank-ts-check@a-edp1: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#2122]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl1/igt@kms_flip@wf_vblank-ts-ch...@a-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/shard-skl2/igt@kms_flip@wf_vblank-ts-ch...@a-edp1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#49]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-glk2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/shard-glk9/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#49]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-kbl7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/shard-kbl6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1188]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl4/igt@kms_...@bpc-switch-dpms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/shard-skl2/igt@kms_...@bpc-switch-dpms.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl9/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/shard-skl8/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/shard-iclb8/igt@kms_psr@psr2_cursor_plane_move.html * igt@perf@blocking: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#1542]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl9/igt@p...@blocking.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/shard-skl4/igt@p...@blocking.html * igt@sysfs_heartbeat_interval@mixed@vecs0: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([i915#1731]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/shard-skl10/igt@sysfs_heartbeat_interval@mi...@vecs0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/shard-skl1/igt@sysfs_heartbeat_interval@mi...@vecs0.html Possi
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add support for Intel's eDP backlight controls (rev3)
== Series Details ==
Series: drm/i915: Add support for Intel's eDP backlight controls (rev3)
URL : https://patchwork.freedesktop.org/series/81702/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f28a72ff60f8 drm/i915/dp: Program source OUI on eDP panels
9233620226ff drm/i915: Rename pwm_* backlight callbacks to ext_pwm_*
f6028d739181 drm/i915: Pass down brightness values to enable/disable backlight
callbacks
ae85f27764dd drm/i915: Keep track of pwm-related backlight hooks separately
9af1a6377bd0 drm/i915/dp: Rename eDP VESA backlight interface functions
e013bc041067 drm/i915/dp: Add register definitions for Intel HDR backlight
interface
0f59b8d11611 drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for
now)
-:151: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#151: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:147:
+ return panel->backlight.max;
+ } else {
-:172: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u8' over 'uint8_t'
#172: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:168:
+ uint8_t buf[4] = { 0 };
-:191: WARNING:LINE_SPACING: Missing a blank line after declarations
#191: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:187:
+ const u32 pwm_level =
intel_panel_backlight_level_to_pwm(connector, level);
+ intel_panel_set_pwm_level(conn_state, pwm_level);
-:218: WARNING:LINE_SPACING: Missing a blank line after declarations
#218: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c:214:
+ u32 pwm_level = intel_panel_backlight_level_to_pwm(connector,
level);
+ panel->backlight.pwm_funcs->enable(crtc_state, conn_state,
pwm_level);
total: 0 errors, 3 warnings, 1 checks, 379 lines checked
1cd0fee4656f drm/i915/dp: Allow forcing specific interfaces through
enable_dpcd_backlight
0246c3bf43a0 drm/dp: Revert "drm/dp: Introduce EDID-based quirks"
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Drop false !i915_vma_is_closed assertion
== Series Details == Series: drm/i915/gem: Drop false !i915_vma_is_closed assertion URL : https://patchwork.freedesktop.org/series/84602/ State : success == Summary == CI Bug Log - changes from CI_DRM_9444 -> Patchwork_19065 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/index.html New tests - New tests have been introduced between CI_DRM_9444 and Patchwork_19065: ### New CI tests (1) ### * boot: - Statuses : 1 fail(s) 38 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19065 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#2411] / [i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@i915_hangman@error-state-basic: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@i915_hang...@error-state-basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/fi-tgl-y/igt@i915_hang...@error-state-basic.html * igt@i915_selftest@live@active: - fi-kbl-soraka: [PASS][7] -> [DMESG-FAIL][8] ([i915#2291] / [i915#666]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-kbl-soraka/igt@i915_selftest@l...@active.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/fi-kbl-soraka/igt@i915_selftest@l...@active.html Possible fixes * igt@gem_ctx_create@basic: - fi-tgl-y: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@gem_ctx_cre...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/fi-tgl-y/igt@gem_ctx_cre...@basic.html Warnings * igt@amdgpu/amd_prime@i915-to-amd: - fi-gdg-551: [SKIP][11] ([fdo#109271]) -> [INCOMPLETE][12] ([i915#172]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-gdg-551/igt@amdgpu/amd_pr...@i915-to-amd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/fi-gdg-551/igt@amdgpu/amd_pr...@i915-to-amd.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#172]: https://gitlab.freedesktop.org/drm/intel/issues/172 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666 Participating hosts (43 -> 39) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9444 -> Patchwork_19065 CI-20190529: 20190529 CI_DRM_9444: cee8f6ace633b555c64b14938577e6da02710a0b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5881: 10d4e2e9177eb747b9f2ab9122e3ab60e91654fb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19065: 2f09abf79c2fed8ccad82374dfadbc36ca35ac77 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2f09abf79c2f drm/i915/gem: Drop false !i915_vma_is_closed assertion == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19065/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 9/9] drm/dp: Revert "drm/dp: Introduce EDID-based quirks"
This reverts commit 0883ce8146ed6074c76399f4e70dbed788582e12. Originally
these quirks were added because of the issues with using the eDP
backlight interfaces on certain laptop panels, which made it impossible
to properly probe for DPCD backlight support without having a whitelist
for panels that we know have working VESA backlight control interfaces
over DPCD. As well, it should be noted it was impossible to use the
normal sink OUI for recognizing these panels as none of them actually
filled out their OUIs, hence needing to resort to checking EDIDs.
At the time we weren't really sure why certain panels had issues with
DPCD backlight controls, but we eventually figured out that there was a
second interface that these problematic laptop panels actually did work
with and advertise properly: Intel's proprietary backlight interface for
HDR panels. So far the testing we've done hasn't brought any panels to
light that advertise this interface and don't support it properly, which
means we finally have a real solution to this problem.
As a result, we now have no need for the force DPCD backlight quirk, and
furthermore this also removes the need for any kind of EDID quirk
checking in DRM. So, let's just revert it for now since we were the only
driver using this.
v3:
* Rebase
v2:
* Fix indenting error picked up by checkpatch in
intel_edp_init_connector()
Signed-off-by: Lyude Paul
Acked-by: Jani Nikula
Cc: thay...@noraisin.net
Cc: Vasily Khoruzhick
---
drivers/gpu/drm/drm_dp_helper.c | 83 +--
drivers/gpu/drm/drm_dp_mst_topology.c | 3 +-
.../drm/i915/display/intel_display_types.h| 1 -
drivers/gpu/drm/i915/display/intel_dp.c | 9 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +-
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
include/drm/drm_dp_helper.h | 21 +
7 files changed, 9 insertions(+), 113 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 5bd0934004e3..62f696fe511e 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1204,7 +1204,7 @@ bool drm_dp_read_sink_count_cap(struct drm_connector
*connector,
return connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
- !drm_dp_has_quirk(desc, 0, DP_DPCD_QUIRK_NO_SINK_COUNT);
+ !drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT);
}
EXPORT_SYMBOL(drm_dp_read_sink_count_cap);
@@ -1925,87 +1925,6 @@ drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident,
bool is_branch)
#undef DEVICE_ID_ANY
#undef DEVICE_ID
-struct edid_quirk {
- u8 mfg_id[2];
- u8 prod_id[2];
- u32 quirks;
-};
-
-#define MFG(first, second) { (first), (second) }
-#define PROD_ID(first, second) { (first), (second) }
-
-/*
- * Some devices have unreliable OUIDs where they don't set the device ID
- * correctly, and as a result we need to use the EDID for finding additional
- * DP quirks in such cases.
- */
-static const struct edid_quirk edid_quirk_list[] = {
- /* Optional 4K AMOLED panel in the ThinkPad X1 Extreme 2nd Generation
-* only supports DPCD backlight controls
-*/
- { MFG(0x4c, 0x83), PROD_ID(0x41, 0x41),
BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
- /*
-* Some Dell CML 2020 systems have panels support both AUX and PWM
-* backlight control, and some only support AUX backlight control. All
-* said panels start up in AUX mode by default, and we don't have any
-* support for disabling HDR mode on these panels which would be
-* required to switch to PWM backlight control mode (plus, I'm not
-* even sure we want PWM backlight controls over DPCD backlight
-* controls anyway...). Until we have a better way of detecting these,
-* force DPCD backlight mode on all of them.
-*/
- { MFG(0x06, 0xaf), PROD_ID(0x9b, 0x32),
BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
- { MFG(0x06, 0xaf), PROD_ID(0xeb, 0x41),
BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
- { MFG(0x4d, 0x10), PROD_ID(0xc7, 0x14),
BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
- { MFG(0x4d, 0x10), PROD_ID(0xe6, 0x14),
BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
- { MFG(0x4c, 0x83), PROD_ID(0x47, 0x41),
BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
- { MFG(0x09, 0xe5), PROD_ID(0xde, 0x08),
BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
-};
-
-#undef MFG
-#undef PROD_ID
-
-/**
- * drm_dp_get_edid_quirks() - Check the EDID of a DP device to find additional
- * DP-specific quirks
- * @edid: The EDID to check
- *
- * While OUIDs are meant to be used to recognize a DisplayPort device, a lot
- * of manufacturers don't seem to like following standards and neglect to fill
- * the dev-ID in, making it impossible to only use OUIDs for determining
- * quirks in some cases. This function can
[Intel-gfx] [PATCH v3 8/9] drm/i915/dp: Allow forcing specific interfaces through enable_dpcd_backlight
Since we now support controlling panel backlights through DPCD using
both the standard VESA interface, and Intel's proprietary HDR backlight
interface, we should allow the user to be able to explicitly choose
between one or the other in the event that we're wrong about panels
reliably reporting support for the Intel HDR interface.
So, this commit adds support for this by introducing two new
enable_dpcd_backlight options: 2 which forces i915 to only probe for the
VESA interface, and 3 which forces i915 to only probe for the Intel
backlight interface (might be useful if we find panels in the wild that
report the VESA interface in their VBT, but actually only support the
Intel backlight interface).
v3:
* Rebase
Signed-off-by: Lyude Paul
Cc: thay...@noraisin.net
Cc: Vasily Khoruzhick
---
.../drm/i915/display/intel_dp_aux_backlight.c | 45 +--
drivers/gpu/drm/i915/i915_params.c| 2 +-
2 files changed, 43 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 9a3ff3ffc158..eef14ab6bddc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -609,15 +609,54 @@ static const struct intel_panel_bl_funcs
intel_dp_vesa_bl_funcs = {
.get = intel_dp_aux_vesa_get_backlight,
};
+enum intel_dp_aux_backlight_modparam {
+ INTEL_DP_AUX_BACKLIGHT_AUTO = -1,
+ INTEL_DP_AUX_BACKLIGHT_OFF = 0,
+ INTEL_DP_AUX_BACKLIGHT_ON = 1,
+ INTEL_DP_AUX_BACKLIGHT_FORCE_VESA = 2,
+ INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL = 3,
+};
+
int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector)
{
struct drm_device *dev = connector->base.dev;
struct intel_panel *panel = &connector->panel;
struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ bool try_intel_interface = false, try_vesa_interface = false;
- if (i915->params.enable_dpcd_backlight == 0)
+ /* Check the VBT and user's module parameters to figure out which
+* interfaces to probe
+*/
+ switch (i915->params.enable_dpcd_backlight) {
+ case INTEL_DP_AUX_BACKLIGHT_OFF:
return -ENODEV;
+ case INTEL_DP_AUX_BACKLIGHT_AUTO:
+ switch (i915->vbt.backlight.type) {
+ case INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE:
+ try_vesa_interface = true;
+ break;
+ case INTEL_BACKLIGHT_DISPLAY_DDI:
+ try_intel_interface = true;
+ try_vesa_interface = true;
+ break;
+ default:
+ return -ENODEV;
+ }
+ break;
+ case INTEL_DP_AUX_BACKLIGHT_ON:
+ if (i915->vbt.backlight.type !=
INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE)
+ try_intel_interface = true;
+
+ try_vesa_interface = true;
+ break;
+ case INTEL_DP_AUX_BACKLIGHT_FORCE_VESA:
+ try_vesa_interface = true;
+ break;
+ case INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL:
+ try_intel_interface = true;
+ break;
+ }
/*
* A lot of eDP panels in the wild will report supporting both the
@@ -626,13 +665,13 @@ int intel_dp_aux_init_backlight_funcs(struct
intel_connector *connector)
* and will only work with the Intel interface. So, always probe for
* that first.
*/
- if (intel_dp_aux_supports_hdr_backlight(connector)) {
+ if (try_intel_interface &&
intel_dp_aux_supports_hdr_backlight(connector)) {
drm_dbg(dev, "Using Intel proprietary eDP backlight
controls\n");
panel->backlight.funcs = &intel_dp_hdr_bl_funcs;
return 0;
}
- if (intel_dp_aux_supports_vesa_backlight(connector)) {
+ if (try_vesa_interface &&
intel_dp_aux_supports_vesa_backlight(connector)) {
drm_dbg(dev, "Using VESA eDP backlight controls\n");
panel->backlight.funcs = &intel_dp_vesa_bl_funcs;
return 0;
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 7f139ea4a90b..6939634e56ed 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -185,7 +185,7 @@ i915_param_named_unsafe(inject_probe_failure, uint, 0400,
i915_param_named(enable_dpcd_backlight, int, 0400,
"Enable support for DPCD backlight control"
- "(-1=use per-VBT LFP backlight type setting [default], 0=disabled,
1=enabled)");
+ "(-1=use per-VBT LFP backlight type setting [default], 0=disabled,
1=enable, 2=force VESA interface, 3=force Intel interface)");
#if IS_ENABLED(CONFIG_DRM_I915_GVT)
i915_param_named(enable
[Intel-gfx] [PATCH v3 7/9] drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now)
So-recently a bunch of laptops on the market have started using DPCD
backlight controls instead of the traditional DDI backlight controls.
Originally we thought we had this handled by adding VESA backlight
control support to i915, but the story ended up being a lot more
complicated then that.
Simply put-there's two main backlight interfaces Intel can see in the
wild. Intel's proprietary HDR backlight interface, and the standard VESA
backlight interface. Note that many panels have been observed to report
support for both backlight interfaces, but testing has shown far more
panels work with the Intel HDR backlight interface at the moment.
Additionally, the VBT appears to be capable of reporting support for the
VESA backlight interface but not the Intel HDR interface which needs to
be probed by setting the right magic OUI.
On top of that however, there's also actually two different variants of
the Intel HDR backlight interface. The first uses the AUX channel for
controlling the brightness of the screen in both SDR and HDR mode, and
the second only uses the AUX channel for setting the brightness level in
HDR mode - relying on PWM for setting the brightness level in SDR mode.
For the time being we've been using EDIDs to maintain a list of quirks
for panels that safely do support the VESA backlight interface. Adding
support for Intel's HDR backlight interface in addition however, should
finally allow us to auto-detect eDP backlight controls properly so long
as we probe like so:
* If the panel's VBT reports VESA backlight support, assume it really
does support it
* If the panel's VBT reports DDI backlight controls:
* First probe for Intel's HDR backlight interface
* If that fails, probe for VESA's backlight interface
* If that fails, assume no DPCD backlight control
* If the panel's VBT reports any other backlight type: just assume it
doesn't have DPCD backlight controls
Signed-off-by: Lyude Paul
Cc: thay...@noraisin.net
Cc: Vasily Khoruzhick
---
.../drm/i915/display/intel_display_types.h| 9 +-
.../drm/i915/display/intel_dp_aux_backlight.c | 244 --
drivers/gpu/drm/i915/display/intel_panel.c| 34 ++-
drivers/gpu/drm/i915/display/intel_panel.h| 4 +
4 files changed, 263 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 47ee565c49a2..889b6f9c1aa9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -261,7 +261,14 @@ struct intel_panel {
struct pwm_state pwm_state;
/* DPCD backlight */
- u8 pwmgen_bit_count;
+ union {
+ struct {
+ u8 pwmgen_bit_count;
+ } vesa;
+ struct {
+ bool sdr_uses_aux;
+ } intel;
+ } edp;
struct backlight_device *device;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 9775f33d1aac..9a3ff3ffc158 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -22,8 +22,26 @@
*
*/
+/*
+ * Laptops with Intel GPUs which have panels that support controlling the
+ * backlight through DP AUX can actually use two different interfaces: Intel's
+ * proprietary DP AUX backlight interface, and the standard VESA backlight
+ * interface. Unfortunately, at the time of writing this a lot of laptops will
+ * advertise support for the standard VESA backlight interface when they
+ * don't properly support it. However, on these systems the Intel backlight
+ * interface generally does work properly. Additionally, these systems will
+ * usually just indicate that they use PWM backlight controls in their VBIOS
+ * for some reason.
+ */
+
#include "intel_display_types.h"
#include "intel_dp_aux_backlight.h"
+#include "intel_panel.h"
+
+/* TODO:
+ * Implement HDR, right now we just implement the bare minimum to bring us
back into SDR mode so we
+ * can make people's backlights work in the mean time
+ */
/*
* DP AUX registers for Intel's proprietary HDR backlight interface. We define
@@ -77,6 +95,175 @@
#define INTEL_EDP_BRIGHTNESS_OPTIMIZATION_10x359
+/* Intel EDP backlight callbacks */
+static bool
+intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector)
+{
+ struct drm_device *dev = connector->base.dev;
+ struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
+ struct drm_dp_aux *aux = &intel_dp->aux;
+ struct intel_panel *panel = &connector->panel;
+ int ret;
+ u8 tcon_cap[4];
+
+ ret = drm_dp_dpcd_read(aux, INTEL_EDP_HDR_TCON_CAP0, tcon_cap,
sizeof(tcon_cap));
+ if (ret < 0)
+
[Intel-gfx] [PATCH v3 4/9] drm/i915: Keep track of pwm-related backlight hooks separately
Currently, every different type of backlight hook that i915 supports is
pretty straight forward - you have a backlight, probably through PWM
(but maybe DPCD), with a single set of platform-specific hooks that are
used for controlling it.
HDR backlights, in particular VESA and Intel's HDR backlight
implementations, can end up being more complicated. With Intel's
proprietary interface, HDR backlight controls always run through the
DPCD. When the backlight is in SDR backlight mode however, the driver
may need to bypass the TCON and control the backlight directly through
PWM.
So, in order to support this we'll need to split our backlight callbacks
into two groups: a set of high-level backlight control callbacks in
intel_panel, and an additional set of pwm-specific backlight control
callbacks. This also implies a functional changes for how these
callbacks are used:
* We now keep track of two separate backlight level ranges, one for the
high-level backlight, and one for the pwm backlight range
* We also keep track of backlight enablement and PWM backlight
enablement separately
* Since the currently set backlight level might not be the same as the
currently programmed PWM backlight level, we stop setting
panel->backlight.level with the currently programmed PWM backlight
level in panel->backlight.pwm_funcs->setup(). Instead, we rely
on the higher level backlight control functions to retrieve the
current PWM backlight level (in this case, intel_pwm_get_backlight()).
Note that there are still a few PWM backlight setup callbacks that
do actually need to retrieve the current PWM backlight level, although
we no longer save this value in panel->backlight.level like before.
Additionally, we drop the call to lpt_get_backlight() in
lpt_setup_backlight(), and avoid unconditionally writing the PWM value that
we get from it and only write it back if we're in PCH mode. The reason for
this is because in the original codepath for this, it was expected that the
intel_panel_bl_funcs->setup() hook would be responsible for fetching the
initial backlight level. On lpt systems, the only time we could ever be in
PCH backlight mode is during the initial driver load - meaning that outside
of the setup() hook, lpt_get_backlight() will always be the callback used
for retrieving the current backlight level. After this patch we still need
to fetch and write-back the PCH backlight value if we're in PCH mode, but
because intel_pwm_setup_backlight() will retrieve the backlight level after
setup() using the get() hook, which always ends up being
lpt_get_backlight(). Thus - an additional call to lpt_get_backlight() in
lpt_setup_backlight() is made redundant.
v3:
* Reuse intel_panel_bl_funcs() for pwm_funcs
* Explain why we drop lpt_get_backlight()
Signed-off-by: Lyude Paul
Cc: thay...@noraisin.net
Cc: Vasily Khoruzhick
---
.../drm/i915/display/intel_display_types.h| 4 +
drivers/gpu/drm/i915/display/intel_panel.c| 344 ++
2 files changed, 194 insertions(+), 154 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index a70d1bf29aa5..47ee565c49a2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -252,6 +252,9 @@ struct intel_panel {
bool alternate_pwm_increment; /* lpt+ */
/* PWM chip */
+ u32 pwm_min;
+ u32 pwm_max;
+ bool pwm_enabled;
bool util_pin_active_low; /* bxt+ */
u8 controller; /* bxt+ only */
struct pwm_device *pwm;
@@ -263,6 +266,7 @@ struct intel_panel {
struct backlight_device *device;
const struct intel_panel_bl_funcs *funcs;
+ const struct intel_panel_bl_funcs *pwm_funcs;
void (*power)(struct intel_connector *, bool enable);
} backlight;
};
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
b/drivers/gpu/drm/i915/display/intel_panel.c
index 67f81ae995c4..41f0d2b2c627 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -511,25 +511,34 @@ static u32 scale_hw_to_user(struct intel_connector
*connector,
0, user_max);
}
-static u32 intel_panel_compute_brightness(struct intel_connector *connector,
- u32 val)
+static u32 intel_panel_sanitize_pwm_level(struct intel_connector *connector,
u32 val)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_panel *panel = &connector->panel;
- drm_WARN_ON(&dev_priv->drm, panel->backlight.max == 0);
+ drm_WARN_ON(&dev_priv->drm, panel->backlight.pwm_max == 0);
if (dev_priv->params.invert_brightness < 0)
return val;
if (dev_priv->params.invert_brightness > 0 ||
[Intel-gfx] [PATCH v3 3/9] drm/i915: Pass down brightness values to enable/disable backlight callbacks
Instead of using intel_panel->backlight.level, have the caller provide us
with the current panel backlight value. We'll need this for when we
separate PWM-related backlight callbacks from other means of backlight
control (like DPCD backlight controls), as the caller of each PWM callback
will be responsible for converting the current brightness value to it's
respective PWM level.
Signed-off-by: Lyude Paul
---
.../drm/i915/display/intel_display_types.h| 4 +-
.../drm/i915/display/intel_dp_aux_backlight.c | 8 +--
.../i915/display/intel_dsi_dcs_backlight.c| 7 +-
drivers/gpu/drm/i915/display/intel_panel.c| 67 +--
4 files changed, 42 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1fa0246b3a82..a70d1bf29aa5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -230,9 +230,9 @@ struct intel_panel_bl_funcs {
int (*setup)(struct intel_connector *connector, enum pipe pipe);
u32 (*get)(struct intel_connector *connector);
void (*set)(const struct drm_connector_state *conn_state, u32 level);
- void (*disable)(const struct drm_connector_state *conn_state);
+ void (*disable)(const struct drm_connector_state *conn_state, u32
level);
void (*enable)(const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state);
+ const struct drm_connector_state *conn_state, u32 level);
u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
};
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 4fd536801b14..c76287e9e91e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -174,7 +174,7 @@ static bool intel_dp_aux_set_pwm_freq(struct
intel_connector *connector)
}
static void intel_dp_aux_enable_backlight(const struct intel_crtc_state
*crtc_state,
- const struct drm_connector_state
*conn_state)
+ const struct drm_connector_state
*conn_state, u32 level)
{
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct intel_dp *intel_dp = intel_attached_dp(connector);
@@ -225,12 +225,12 @@ static void intel_dp_aux_enable_backlight(const struct
intel_crtc_state *crtc_st
}
}
- intel_dp_aux_set_backlight(conn_state,
- connector->panel.backlight.level);
+ intel_dp_aux_set_backlight(conn_state, level);
set_aux_backlight_enable(intel_dp, true);
}
-static void intel_dp_aux_disable_backlight(const struct drm_connector_state
*old_conn_state)
+static void intel_dp_aux_disable_backlight(const struct drm_connector_state
*old_conn_state,
+ u32 level)
{
set_aux_backlight_enable(enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)),
false);
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
index 5c508d51f526..88628764956d 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
@@ -77,7 +77,7 @@ static void dcs_set_backlight(const struct
drm_connector_state *conn_state, u32
}
}
-static void dcs_disable_backlight(const struct drm_connector_state *conn_state)
+static void dcs_disable_backlight(const struct drm_connector_state
*conn_state, u32 level)
{
struct intel_dsi *intel_dsi =
enc_to_intel_dsi(to_intel_encoder(conn_state->best_encoder));
struct mipi_dsi_device *dsi_device;
@@ -111,10 +111,9 @@ static void dcs_disable_backlight(const struct
drm_connector_state *conn_state)
}
static void dcs_enable_backlight(const struct intel_crtc_state *crtc_state,
-const struct drm_connector_state *conn_state)
+const struct drm_connector_state *conn_state,
u32 level)
{
struct intel_dsi *intel_dsi =
enc_to_intel_dsi(to_intel_encoder(conn_state->best_encoder));
- struct intel_panel *panel =
&to_intel_connector(conn_state->connector)->panel;
struct mipi_dsi_device *dsi_device;
enum port port;
@@ -142,7 +141,7 @@ static void dcs_enable_backlight(const struct
intel_crtc_state *crtc_state,
&cabc, sizeof(cabc));
}
- dcs_set_backlight(conn_state, panel->backlight.level);
+ dcs_set_backlight(conn_state, level);
}
static int dcs_setup_backlight(struct intel_connector *connector,
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
b/drivers/gp
[Intel-gfx] [PATCH v3 5/9] drm/i915/dp: Rename eDP VESA backlight interface functions
Since we're about to add support for a second type of backlight control
interface over DP AUX (specifically, Intel's proprietary HDR backlight
controls) let's rename all of the current backlight hooks we have for
vesa to make it clear that they're specific to the VESA interface and
not Intel's.
v3:
* Rebase
Signed-off-by: Lyude Paul
Reviewed-by: Rodrigo Vivi
Cc: thay...@noraisin.net
Cc: Vasily Khoruzhick
---
.../drm/i915/display/intel_dp_aux_backlight.c | 62 ++-
1 file changed, 32 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index c76287e9e91e..b102692a659d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -25,7 +25,7 @@
#include "intel_display_types.h"
#include "intel_dp_aux_backlight.h"
-static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)
+static void set_vesa_backlight_enable(struct intel_dp *intel_dp, bool enable)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 reg_val = 0;
@@ -52,7 +52,7 @@ static void set_aux_backlight_enable(struct intel_dp
*intel_dp, bool enable)
}
}
-static bool intel_dp_aux_backlight_dpcd_mode(struct intel_connector *connector)
+static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector
*connector)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -75,7 +75,7 @@ static bool intel_dp_aux_backlight_dpcd_mode(struct
intel_connector *connector)
* Read the current backlight value from DPCD register(s) based
* on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
*/
-static u32 intel_dp_aux_get_backlight(struct intel_connector *connector)
+static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -86,7 +86,7 @@ static u32 intel_dp_aux_get_backlight(struct intel_connector
*connector)
* If we're not in DPCD control mode yet, the programmed brightness
* value is meaningless and we should assume max brightness
*/
- if (!intel_dp_aux_backlight_dpcd_mode(connector))
+ if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
return connector->panel.backlight.max;
if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
@@ -107,7 +107,8 @@ static u32 intel_dp_aux_get_backlight(struct
intel_connector *connector)
* 8-bit or 16 bit value (MSB and LSB)
*/
static void
-intel_dp_aux_set_backlight(const struct drm_connector_state *conn_state, u32
level)
+intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
+ u32 level)
{
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct intel_dp *intel_dp = intel_attached_dp(connector);
@@ -137,7 +138,7 @@ intel_dp_aux_set_backlight(const struct drm_connector_state
*conn_state, u32 lev
* - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
* EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
*/
-static bool intel_dp_aux_set_pwm_freq(struct intel_connector *connector)
+static bool intel_dp_aux_vesa_set_pwm_freq(struct intel_connector *connector)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_dp *intel_dp = intel_attached_dp(connector);
@@ -173,8 +174,9 @@ static bool intel_dp_aux_set_pwm_freq(struct
intel_connector *connector)
return true;
}
-static void intel_dp_aux_enable_backlight(const struct intel_crtc_state
*crtc_state,
- const struct drm_connector_state
*conn_state, u32 level)
+static void
+intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state
*conn_state, u32 level)
{
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct intel_dp *intel_dp = intel_attached_dp(connector);
@@ -214,7 +216,7 @@ static void intel_dp_aux_enable_backlight(const struct
intel_crtc_state *crtc_st
}
if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
- if (intel_dp_aux_set_pwm_freq(connector))
+ if (intel_dp_aux_vesa_set_pwm_freq(connector))
new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
if (new_dpcd_buf != dpcd_buf) {
@@ -225,18 +227,18 @@ static void intel_dp_aux_enable_backlight(const struct
intel_crtc_state *crtc_st
}
}
- intel_dp_aux_set_backlight(conn_state, level);
- set_aux_backlight_enable(intel_dp, true);
+ intel_dp_aux_vesa_se
[Intel-gfx] [PATCH v3 6/9] drm/i915/dp: Add register definitions for Intel HDR backlight interface
No functional changes yet, this just adds definitions for all of the
known DPCD registers used by Intel's HDR backlight interface. Since
we'll only ever use this in i915, we just define them in
intel_dp_aux_backlight.c
Reviewed-by: Rodrigo Vivi
Signed-off-by: Lyude Paul
Cc: thay...@noraisin.net
Cc: Vasily Khoruzhick
---
.../drm/i915/display/intel_dp_aux_backlight.c | 53 +++
1 file changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index b102692a659d..9775f33d1aac 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -25,6 +25,59 @@
#include "intel_display_types.h"
#include "intel_dp_aux_backlight.h"
+/*
+ * DP AUX registers for Intel's proprietary HDR backlight interface. We define
+ * them here since we'll likely be the only driver to ever use these.
+ */
+#define INTEL_EDP_HDR_TCON_CAP00x340
+
+#define INTEL_EDP_HDR_TCON_CAP10x341
+# define INTEL_EDP_HDR_TCON_2084_DECODE_CAP BIT(0)
+# define INTEL_EDP_HDR_TCON_2020_GAMUT_CAPBIT(1)
+# define INTEL_EDP_HDR_TCON_TONE_MAPPING_CAP BIT(2)
+# define INTEL_EDP_HDR_TCON_SEGMENTED_BACKLIGHT_CAP BIT(3)
+# define INTEL_EDP_HDR_TCON_BRIGHTNESS_NITS_CAP BIT(4)
+# define INTEL_EDP_HDR_TCON_OPTIMIZATION_CAP BIT(5)
+# define INTEL_EDP_HDR_TCON_SDP_COLORIMETRY_CAP BIT(6)
+# define INTEL_EDP_HDR_TCON_SRGB_TO_PANEL_GAMUT_CONVERSION_CAPBIT(7)
+
+#define INTEL_EDP_HDR_TCON_CAP20x342
+# define INTEL_EDP_SDR_TCON_BRIGHTNESS_AUX_CAPBIT(0)
+
+#define INTEL_EDP_HDR_TCON_CAP30x343
+
+#define INTEL_EDP_HDR_GETSET_CTRL_PARAMS 0x344
+# define INTEL_EDP_HDR_TCON_2084_DECODE_ENABLEBIT(0)
+# define INTEL_EDP_HDR_TCON_2020_GAMUT_ENABLE BIT(1)
+# define INTEL_EDP_HDR_TCON_TONE_MAPPING_ENABLE BIT(2)
/* Pre-TGL+ */
+# define INTEL_EDP_HDR_TCON_SEGMENTED_BACKLIGHT_ENABLEBIT(3)
+# define INTEL_EDP_HDR_TCON_BRIGHTNESS_AUX_ENABLE BIT(4)
+# define INTEL_EDP_HDR_TCON_SRGB_TO_PANEL_GAMUT_ENABLEBIT(5)
+/* Bit 6 is reserved */
+# define INTEL_EDP_HDR_TCON_SDP_COLORIMETRY_ENABLEBIT(7)
+
+#define INTEL_EDP_HDR_CONTENT_LUMINANCE0x346
/* Pre-TGL+ */
+#define INTEL_EDP_HDR_PANEL_LUMINANCE_OVERRIDE 0x34A
+#define INTEL_EDP_SDR_LUMINANCE_LEVEL 0x352
+#define INTEL_EDP_BRIGHTNESS_NITS_LSB 0x354
+#define INTEL_EDP_BRIGHTNESS_NITS_MSB 0x355
+#define INTEL_EDP_BRIGHTNESS_DELAY_FRAMES 0x356
+#define INTEL_EDP_BRIGHTNESS_PER_FRAME_STEPS 0x357
+
+#define INTEL_EDP_BRIGHTNESS_OPTIMIZATION_00x358
+# define INTEL_EDP_TCON_USAGE_MASK GENMASK(0, 3)
+# define INTEL_EDP_TCON_USAGE_UNKNOWN0x0
+# define INTEL_EDP_TCON_USAGE_DESKTOP0x1
+# define INTEL_EDP_TCON_USAGE_FULL_SCREEN_MEDIA 0x2
+# define INTEL_EDP_TCON_USAGE_FULL_SCREEN_GAMING 0x3
+# define INTEL_EDP_TCON_POWER_MASKBIT(4)
+# define INTEL_EDP_TCON_POWER_DC(0 << 4)
+# define INTEL_EDP_TCON_POWER_AC(1 << 4)
+# define INTEL_EDP_TCON_OPTIMIZATION_STRENGTH_MASK GENMASK(5, 7)
+
+#define INTEL_EDP_BRIGHTNESS_OPTIMIZATION_10x359
+
+/* VESA backlight callbacks */
static void set_vesa_backlight_enable(struct intel_dp *intel_dp, bool enable)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
--
2.28.0
___
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[Intel-gfx] [PATCH v3 2/9] drm/i915: Rename pwm_* backlight callbacks to ext_pwm_*
Since we're going to need to add a set of lower-level PWM backlight
control hooks to be shared by normal backlight controls and HDR
backlight controls in SDR mode, let's add a prefix to the external PWM
backlight functions so that the difference between them and the high
level PWM-only backlight functions is a bit more obvious.
This introduces no functional changes.
Signed-off-by: Lyude Paul
Reviewed-by: Rodrigo Vivi
Reviewed-by: Jani Nikula
Cc: thay...@noraisin.net
Cc: Vasily Khoruzhick
---
drivers/gpu/drm/i915/display/intel_panel.c | 28 +++---
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
b/drivers/gpu/drm/i915/display/intel_panel.c
index 36b7693453ae..da8f7c12ae22 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -589,7 +589,7 @@ static u32 bxt_get_backlight(struct intel_connector
*connector)
BXT_BLC_PWM_DUTY(panel->backlight.controller));
}
-static u32 pwm_get_backlight(struct intel_connector *connector)
+static u32 ext_pwm_get_backlight(struct intel_connector *connector)
{
struct intel_panel *panel = &connector->panel;
struct pwm_state state;
@@ -666,7 +666,7 @@ static void bxt_set_backlight(const struct
drm_connector_state *conn_state, u32
BXT_BLC_PWM_DUTY(panel->backlight.controller), level);
}
-static void pwm_set_backlight(const struct drm_connector_state *conn_state,
u32 level)
+static void ext_pwm_set_backlight(const struct drm_connector_state
*conn_state, u32 level)
{
struct intel_panel *panel =
&to_intel_connector(conn_state->connector)->panel;
@@ -835,7 +835,7 @@ static void cnp_disable_backlight(const struct
drm_connector_state *old_conn_sta
tmp & ~BXT_BLC_PWM_ENABLE);
}
-static void pwm_disable_backlight(const struct drm_connector_state
*old_conn_state)
+static void ext_pwm_disable_backlight(const struct drm_connector_state
*old_conn_state)
{
struct intel_connector *connector =
to_intel_connector(old_conn_state->connector);
struct intel_panel *panel = &connector->panel;
@@ -1168,8 +1168,8 @@ static void cnp_enable_backlight(const struct
intel_crtc_state *crtc_state,
pwm_ctl | BXT_BLC_PWM_ENABLE);
}
-static void pwm_enable_backlight(const struct intel_crtc_state *crtc_state,
-const struct drm_connector_state *conn_state)
+static void ext_pwm_enable_backlight(const struct intel_crtc_state *crtc_state,
+const struct drm_connector_state
*conn_state)
{
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct intel_panel *panel = &connector->panel;
@@ -1890,8 +1890,8 @@ cnp_setup_backlight(struct intel_connector *connector,
enum pipe unused)
return 0;
}
-static int pwm_setup_backlight(struct intel_connector *connector,
- enum pipe pipe)
+static int ext_pwm_setup_backlight(struct intel_connector *connector,
+ enum pipe pipe)
{
struct drm_device *dev = connector->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -2061,12 +2061,12 @@ static const struct intel_panel_bl_funcs pch_funcs = {
.hz_to_pwm = pch_hz_to_pwm,
};
-static const struct intel_panel_bl_funcs pwm_funcs = {
- .setup = pwm_setup_backlight,
- .enable = pwm_enable_backlight,
- .disable = pwm_disable_backlight,
- .set = pwm_set_backlight,
- .get = pwm_get_backlight,
+static const struct intel_panel_bl_funcs ext_pwm_funcs = {
+ .setup = ext_pwm_setup_backlight,
+ .enable = ext_pwm_enable_backlight,
+ .disable = ext_pwm_disable_backlight,
+ .set = ext_pwm_set_backlight,
+ .get = ext_pwm_get_backlight,
};
static const struct intel_panel_bl_funcs vlv_funcs = {
@@ -2125,7 +2125,7 @@ intel_panel_init_backlight_funcs(struct intel_panel
*panel)
panel->backlight.funcs = &pch_funcs;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI) {
- panel->backlight.funcs = &pwm_funcs;
+ panel->backlight.funcs = &ext_pwm_funcs;
} else {
panel->backlight.funcs = &vlv_funcs;
}
--
2.28.0
___
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[Intel-gfx] [PATCH v3 1/9] drm/i915/dp: Program source OUI on eDP panels
Since we're about to start adding support for Intel's magic HDR
backlight interface over DPCD, we need to ensure we're properly
programming this field so that Intel specific sink services are exposed.
Otherwise, 0x300-0x3ff will just read zeroes.
We also take care not to reprogram the source OUI if it already matches
what we expect. This is just to be careful so that we don't accidentally
take the panel out of any backlight control modes we found it in.
v2:
* Add careful parameter to intel_edp_init_source_oui() to avoid
re-writing the source OUI if it's already been set during driver
initialization
Signed-off-by: Lyude Paul
Reviewed-by: Rodrigo Vivi
Cc: thay...@noraisin.net
Cc: Vasily Khoruzhick
---
drivers/gpu/drm/i915/display/intel_dp.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2d4d5e95af84..4cb2bfee9c40 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3583,6 +3583,29 @@ void intel_dp_sink_set_decompression_state(struct
intel_dp *intel_dp,
enable ? "enable" : "disable");
}
+static void
+intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u8 oui[] = { 0x00, 0xaa, 0x01 };
+ u8 buf[3] = { 0 };
+
+ /*
+* During driver init, we want to be careful and avoid changing the
source OUI if it's
+* already set to what we want, so as to avoid clearing any state by
accident
+*/
+ if (careful) {
+ if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf,
sizeof(buf)) < 0)
+ drm_err(&i915->drm, "Failed to read source OUI\n");
+
+ if (memcmp(oui, buf, sizeof(oui)) == 0)
+ return;
+ }
+
+ if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui))
< 0)
+ drm_err(&i915->drm, "Failed to write source OUI\n");
+}
+
/* If the device supports it, try to set the power state appropriately */
void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
{
@@ -3604,6 +3627,10 @@ void intel_dp_set_power(struct intel_dp *intel_dp, u8
mode)
lspcon_resume(dp_to_dig_port(intel_dp));
+ /* Write the source OUI as early as possible */
+ if (intel_dp_is_edp(intel_dp))
+ intel_edp_init_source_oui(intel_dp, false);
+
/*
* When turning on, we need to retry for 1ms to give the sink
* time to wake up.
@@ -4869,6 +4896,12 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
intel_dp_get_dsc_sink_cap(intel_dp);
+ /*
+* If needed, program our source OUI so we can make various
Intel-specific AUX services
+* available (such as HDR backlight controls)
+*/
+ intel_edp_init_source_oui(intel_dp, true);
+
return true;
}
--
2.28.0
___
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[Intel-gfx] [PATCH v3 0/9] drm/i915: Add support for Intel's eDP backlight controls
A while ago we ran into issues while trying to enable the eDP backlight control interface as defined by VESA, in order to make the DPCD backlight controls on newer laptop panels work. The issue ended up being much more complicated however, as we also apparently needed to add support for an Intel-specific DPCD backlight control interface as the VESA interface is broken on many laptop panels. For lack of a better name, we just call this the Intel HDR backlight interface. While this only adds support for the SDR backlight mode (I think), this will fix a lot of user's laptop panels that we weren't able to properly automatically detect DPCD backlight controls on previously. Series-wide changes in v3: * Pass down brightness values to enable/disable backlight callbacks in a separate patch * Rebase Lyude Paul (9): drm/i915/dp: Program source OUI on eDP panels drm/i915: Rename pwm_* backlight callbacks to ext_pwm_* drm/i915: Pass down brightness values to enable/disable backlight callbacks drm/i915: Keep track of pwm-related backlight hooks separately drm/i915/dp: Rename eDP VESA backlight interface functions drm/i915/dp: Add register definitions for Intel HDR backlight interface drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now) drm/i915/dp: Allow forcing specific interfaces through enable_dpcd_backlight drm/dp: Revert "drm/dp: Introduce EDID-based quirks" drivers/gpu/drm/drm_dp_helper.c | 83 +--- drivers/gpu/drm/drm_dp_mst_topology.c | 3 +- .../drm/i915/display/intel_display_types.h| 18 +- drivers/gpu/drm/i915/display/intel_dp.c | 42 +- .../drm/i915/display/intel_dp_aux_backlight.c | 394 +--- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +- .../i915/display/intel_dsi_dcs_backlight.c| 7 +- drivers/gpu/drm/i915/display/intel_panel.c| 435 ++ drivers/gpu/drm/i915/display/intel_panel.h| 4 + drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/i915_params.c| 2 +- include/drm/drm_dp_helper.h | 21 +- 12 files changed, 655 insertions(+), 359 deletions(-) -- 2.28.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/17] drivers/gpu: Convert to mem*_page()
On Fri, Dec 04 2020 at 08:05, Ira Weiny wrote: > So I think I'm going to submit the base patch to Andrew today (with some > cleanups per the comments in this thread). Could you please base that on tip core/mm where the kmap_local() muck is and use kmap_local() right away? Thanks, tglx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/dp: Compute the correct slice count for VDSC on DP
== Series Details == Series: drm/i915/display/dp: Compute the correct slice count for VDSC on DP URL : https://patchwork.freedesktop.org/series/84599/ State : success == Summary == CI Bug Log - changes from CI_DRM_9444 -> Patchwork_19064 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19064/index.html New tests - New tests have been introduced between CI_DRM_9444 and Patchwork_19064: ### New CI tests (1) ### * boot: - Statuses : 1 fail(s) 38 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19064 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s0: - fi-ilk-650: [PASS][1] -> [DMESG-WARN][2] ([i915#164]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-ilk-650/igt@gem_exec_susp...@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19064/fi-ilk-650/igt@gem_exec_susp...@basic-s0.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#2411] / [i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19064/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@gem_flink_basic@flink-lifetime: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@gem_flink_ba...@flink-lifetime.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19064/fi-tgl-y/igt@gem_flink_ba...@flink-lifetime.html Possible fixes * igt@gem_ctx_create@basic: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@gem_ctx_cre...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19064/fi-tgl-y/igt@gem_ctx_cre...@basic.html [i915#164]: https://gitlab.freedesktop.org/drm/intel/issues/164 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 39) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9444 -> Patchwork_19064 CI-20190529: 20190529 CI_DRM_9444: cee8f6ace633b555c64b14938577e6da02710a0b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5881: 10d4e2e9177eb747b9f2ab9122e3ab60e91654fb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19064: 5568af5a0e7f9131540b9eff4633b76e69259fe8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5568af5a0e7f drm/i915/display/dp: Compute the correct slice count for VDSC on DP == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19064/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gem: Drop false !i915_vma_is_closed assertion
Closed vma are protected by the GT wakeref held as we lookup the vma, so we know that the vma will not be freed as we process it for the execbuf. Instead we expect to catch the closed status of the context, and simply allow the close-race on an individual vma to be washed away. Longer term, the GT wakeref protection will be removed by explicit vma.kref tracking. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2245 Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index b07dc1156a0e..193996144c84 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -534,8 +534,6 @@ eb_add_vma(struct i915_execbuffer *eb, struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; struct eb_vma *ev = &eb->vma[i]; - GEM_BUG_ON(i915_vma_is_closed(vma)); - ev->vma = vma; ev->exec = entry; ev->flags = entry->flags; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Reduce duplicated switch cases in hpd code
== Series Details == Series: drm/i915: Reduce duplicated switch cases in hpd code URL : https://patchwork.freedesktop.org/series/84593/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9444 -> Patchwork_19063 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19063 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19063, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19063/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19063: ### IGT changes ### Possible regressions * igt@i915_pm_backlight@basic-brightness: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-bsw-kefka/igt@i915_pm_backli...@basic-brightness.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19063/fi-bsw-kefka/igt@i915_pm_backli...@basic-brightness.html New tests - New tests have been introduced between CI_DRM_9444 and Patchwork_19063: ### New CI tests (1) ### * boot: - Statuses : 1 fail(s) 38 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19063 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-icl-y: [PASS][3] -> [INCOMPLETE][4] ([i915#1037] / [i915#2276]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-icl-y/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19063/fi-icl-y/igt@i915_selftest@l...@execlists.html * igt@vgem_basic@setversion: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@vgem_ba...@setversion.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19063/fi-tgl-y/igt@vgem_ba...@setversion.html Possible fixes * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19063/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037 [i915#2276]: https://gitlab.freedesktop.org/drm/intel/issues/2276 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 39) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9444 -> Patchwork_19063 CI-20190529: 20190529 CI_DRM_9444: cee8f6ace633b555c64b14938577e6da02710a0b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5881: 10d4e2e9177eb747b9f2ab9122e3ab60e91654fb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19063: ea2f55cba539f1e9f1a54279904d7392351f6dc8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ea2f55cba539 drm/i915: Reduce duplicated switch cases in hpd code == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19063/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/display/dp: Compute the correct slice count for VDSC on DP
This patch fixes the slice count computation algorithm
for calculating the slice count based on Peak pixel rate
and the max slice width allowed on the DSC engines.
We need to ensure slice count > min slice count req
as per DP spec based on peak pixel rate and that it is
greater than min slice count based on the max slice width
advertised by DPCD. So use max of these two.
In the prev patch we were using min of these 2 causing it
to violate the max slice width limitation causing a blank
screen on 8K@60.
Fixes: d9218c8f6cf4 ("drm/i915/dp: Add helpers for Compressed BPP and Slice
Count for DSC")
Cc: Ankit Nautiyal
Cc: Jani Nikula
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2d4d5e95af84..cb5e42c3ecd5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -615,7 +615,7 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp
*intel_dp,
return 0;
}
/* Also take into account max slice width */
- min_slice_count = min_t(u8, min_slice_count,
+ min_slice_count = max_t(u8, min_slice_count,
DIV_ROUND_UP(mode_hdisplay,
max_slice_width));
--
2.19.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Inject a failure into the initial modeset (rev2)
== Series Details == Series: drm/i915/display: Inject a failure into the initial modeset (rev2) URL : https://patchwork.freedesktop.org/series/84592/ State : success == Summary == CI Bug Log - changes from CI_DRM_9444 -> Patchwork_19062 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/index.html New tests - New tests have been introduced between CI_DRM_9444 and Patchwork_19062: ### New CI tests (1) ### * boot: - Statuses : 1 fail(s) 38 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19062 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@active: - fi-bsw-nick:[PASS][1] -> [DMESG-FAIL][2] ([i915#2675] / [i915#541]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-bsw-nick/igt@i915_selftest@l...@active.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/fi-bsw-nick/igt@i915_selftest@l...@active.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [PASS][3] -> [DMESG-FAIL][4] ([i915#2291] / [i915#541]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@prime_vgem@basic-fence-flip: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@prime_v...@basic-fence-flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/fi-tgl-y/igt@prime_v...@basic-fence-flip.html Possible fixes * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2675]: https://gitlab.freedesktop.org/drm/intel/issues/2675 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 Participating hosts (43 -> 39) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9444 -> Patchwork_19062 CI-20190529: 20190529 CI_DRM_9444: cee8f6ace633b555c64b14938577e6da02710a0b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5881: 10d4e2e9177eb747b9f2ab9122e3ab60e91654fb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19062: 203678a9c9abfca010dfbc6ff60977c5d8c652d5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 203678a9c9ab drm/i915/display: Inject a failure into the initial modeset == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19062/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for dma-buf: Fix kerneldoc formatting
== Series Details == Series: dma-buf: Fix kerneldoc formatting URL : https://patchwork.freedesktop.org/series/84585/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9444 -> Patchwork_19061 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19061 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19061, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19061/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19061: ### IGT changes ### Possible regressions * igt@gem_exec_suspend@basic-s3: - fi-snb-2600:[PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19061/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html New tests - New tests have been introduced between CI_DRM_9444 and Patchwork_19061: ### New CI tests (1) ### * boot: - Statuses : 1 fail(s) 38 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19061 that come from known issues: ### IGT changes ### Issues hit * igt@gem_linear_blits@basic: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@gem_linear_bl...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19061/fi-tgl-y/igt@gem_linear_bl...@basic.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][5] -> [DMESG-FAIL][6] ([i915#165]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19061/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@gem_ctx_create@basic: - fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@gem_ctx_cre...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19061/fi-tgl-y/igt@gem_ctx_cre...@basic.html [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 39) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9444 -> Patchwork_19061 CI-20190529: 20190529 CI_DRM_9444: cee8f6ace633b555c64b14938577e6da02710a0b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5881: 10d4e2e9177eb747b9f2ab9122e3ab60e91654fb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19061: f9918c0f7808f8648b0069498199177bef3b9ac8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f9918c0f7808 dma-buf: Fix kerneldoc formatting == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19061/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v2] runner: Don't kill a test on taint if watching timeouts
We may still be interested in results of a test even if it has tainted
the kernel. On the other hand, we need to kill the test on taint if no
other means of killing it on a jam is active.
If abort on both kernel taint or a timeout is requested, decrease all
potential timeouts significantly while the taint is detected instead of
aborting immediately. However, report the taint as the reason of the
abort if a timeout decreased by the taint expires.
v2: Fix missing show_kernel_task_state() lost on rebase conflict
resolution (Chris - thanks!)
Signed-off-by: Janusz Krzysztofik
---
runner/executor.c | 26 --
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/runner/executor.c b/runner/executor.c
index 1688ae41d..faf272d85 100644
--- a/runner/executor.c
+++ b/runner/executor.c
@@ -726,6 +726,8 @@ static const char *need_to_timeout(struct settings
*settings,
double time_since_kill,
size_t disk_usage)
{
+ int decrease = 1;
+
if (killed) {
/*
* Timeout after being killed is a hardcoded amount
@@ -753,20 +755,32 @@ static const char *need_to_timeout(struct settings
*settings,
}
/*
-* If we're configured to care about taints, kill the
-* test if there's a taint.
+* If we're configured to care about taints,
+* decrease timeouts in use if there's a taint,
+* or kill the test if no timeouts have been requested.
*/
if (settings->abort_mask & ABORT_TAINT &&
- is_tainted(taints))
- return "Killing the test because the kernel is tainted.\n";
+ is_tainted(taints)) {
+ /* list of timeouts that may postpone immediate kill on taint */
+ if (settings->per_test_timeout || settings->inactivity_timeout)
+ decrease = 10;
+ else
+ return "Killing the test because the kernel is
tainted.\n";
+ }
if (settings->per_test_timeout != 0 &&
- time_since_subtest > settings->per_test_timeout)
+ time_since_subtest > settings->per_test_timeout / decrease) {
+ if (decrease > 1)
+ return "Killing the test because the kernel is
tainted.\n";
return show_kernel_task_state("Per-test timeout exceeded.
Killing the current test with SIGQUIT.\n");
+ }
if (settings->inactivity_timeout != 0 &&
- time_since_activity > settings->inactivity_timeout)
+ time_since_activity > settings->inactivity_timeout / decrease ) {
+ if (decrease > 1)
+ return "Killing the test because the kernel is
tainted.\n";
return show_kernel_task_state("Inactivity timeout exceeded.
Killing the current test with SIGQUIT.\n");
+ }
if (disk_usage_limit_exceeded(settings, disk_usage))
return "Disk usage limit exceeded.\n";
--
2.21.1
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-buf: Fix kerneldoc formatting
== Series Details == Series: dma-buf: Fix kerneldoc formatting URL : https://patchwork.freedesktop.org/series/84585/ State : warning == Summary == $ dim checkpatch origin/drm-tip f9918c0f7808 dma-buf: Fix kerneldoc formatting -:37: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 16 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable outputs during unregister (rev2)
== Series Details == Series: drm/i915: Disable outputs during unregister (rev2) URL : https://patchwork.freedesktop.org/series/84371/ State : success == Summary == CI Bug Log - changes from CI_DRM_9444 -> Patchwork_19060 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/index.html New tests - New tests have been introduced between CI_DRM_9444 and Patchwork_19060: ### New CI tests (1) ### * boot: - Statuses : 1 fail(s) 38 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19060 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@read_all_entries: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@i915_selftest@live@execlists: - fi-cfl-8109u: [PASS][3] -> [INCOMPLETE][4] ([i915#1037] / [i915#2089]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [PASS][5] -> [DMESG-FAIL][6] ([i915#2291] / [i915#541]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html - fi-skl-guc: [PASS][7] -> [DMESG-FAIL][8] ([i915#2291] / [i915#541]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-skl-guc/igt@i915_selftest@live@gt_heartbeat.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/fi-skl-guc/igt@i915_selftest@live@gt_heartbeat.html Possible fixes * igt@core_hotunplug@unbind-rebind: - fi-blb-e6850: [INCOMPLETE][9] ([i915#2540]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html * igt@gem_ctx_create@basic: - fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9444/fi-tgl-y/igt@gem_ctx_cre...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/fi-tgl-y/igt@gem_ctx_cre...@basic.html [i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037 [i915#2089]: https://gitlab.freedesktop.org/drm/intel/issues/2089 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2540]: https://gitlab.freedesktop.org/drm/intel/issues/2540 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 Participating hosts (43 -> 39) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9444 -> Patchwork_19060 CI-20190529: 20190529 CI_DRM_9444: cee8f6ace633b555c64b14938577e6da02710a0b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5881: 10d4e2e9177eb747b9f2ab9122e3ab60e91654fb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19060: 8e64d87e1fce88cb5bd14be2f81a7862d7d8dff9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8e64d87e1fce drm/i915: Disable outputs during unregister == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19060/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC-v4 24/26] drm/i915/pxp: User interface for Protected buffer
Hi Landwerlin,
Thanks for your feedback, Let me check with the commit owner. And I will upload
another reversion once it's done.
Hi Krishnaiah,
May I have your comment for this? Please let me know if there is new revision
path thanks.
Best regards,
Sean
-Original Message-
From: Lionel Landwerlin
Sent: Friday, December 4, 2020 6:24 AM
To: Huang, Sean Z ; Intel-gfx@lists.freedesktop.org
Cc: Bommu, Krishnaiah ; Kondapally, Kalyan
Subject: Re: [Intel-gfx] [RFC-v4 24/26] drm/i915/pxp: User interface for
Protected buffer
On 02/12/2020 06:03, Huang, Sean Z wrote:
> From: Bommu Krishnaiah
>
> This api allow user mode to create Protected buffer and context creation.
>
> Signed-off-by: Bommu Krishnaiah
> Cc: Telukuntla Sreedhar
> Cc: Kondapally Kalyan
> Cc: Gupta Anshuman
> Cc: Huang Sean Z
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++--
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 10
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 5
> drivers/gpu/drm/i915/i915_gem.c | 23 +++
> include/uapi/drm/i915_drm.h | 19 +++
> 6 files changed, 67 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index a6299da64de4..dd5d24a13cb9 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -2060,12 +2060,23 @@ static int ctx_setparam(struct drm_i915_file_private
> *fpriv,
> case I915_CONTEXT_PARAM_RECOVERABLE:
> if (args->size)
> ret = -EINVAL;
> - else if (args->value)
> - i915_gem_context_set_recoverable(ctx);
> + else if (args->value) {
> + if (!i915_gem_context_is_protected(ctx))
> + i915_gem_context_set_recoverable(ctx);
> + else
> + ret = -EPERM;
> + }
> else
> i915_gem_context_clear_recoverable(ctx);
> break;
>
> + case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + if (args->size)
> + ret = -EINVAL;
> + else if (args->value)
> + i915_gem_context_set_protected(ctx);
> + break;
> +
> case I915_CONTEXT_PARAM_PRIORITY:
> ret = set_priority(ctx, args);
> break;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> index a133f92bbedb..5897e7ca11a8 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> @@ -70,6 +70,16 @@ static inline void i915_gem_context_set_recoverable(struct
> i915_gem_context *ctx
> set_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
> }
>
> +static inline void i915_gem_context_set_protected(struct
> +i915_gem_context *ctx) {
> + set_bit(UCONTEXT_PROTECTED, &ctx->user_flags); }
> +
> +static inline bool i915_gem_context_is_protected(struct
> +i915_gem_context *ctx) {
> + return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags); }
> +
> static inline void i915_gem_context_clear_recoverable(struct
> i915_gem_context *ctx)
> {
> clear_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags); diff --git
> a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> index ae14ca24a11f..81ae94c2be86 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> @@ -135,7 +135,7 @@ struct i915_gem_context {
> #define UCONTEXT_BANNABLE 2
> #define UCONTEXT_RECOVERABLE3
> #define UCONTEXT_PERSISTENCE4
> -
> +#define UCONTEXT_PROTECTED 5
> /**
>* @flags: small set of booleans
>*/
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index e2d9b7e1e152..90ac955463f4 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -161,6 +161,11 @@ struct drm_i915_gem_object {
> } mmo;
>
> I915_SELFTEST_DECLARE(struct list_head st_link);
> + /**
> + * @user_flags: small set of booleans set by the user
> + */
> + unsigned long user_flags;
> +#define I915_BO_PROTECTED BIT(0)
>
> unsigned long flags;
> #define I915_BO_ALLOC_CONTIGUOUS BIT(0) diff --git
> a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 41698a823737..6a791fd24eaa 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -184,7 +184,8 @@ static int
> i915_gem_create(struct drm_file *file,
>
[Intel-gfx] [PATCH] drm/i915: Reduce duplicated switch cases in hpd code
From: Ville Syrjälä
With GEN11_HOTPLUG_CTL_LONG_DETECT(), SHOTPLUG_CTL_DDI_HPD_LONG_DETECT()
and ICP_TC_HPD_LONG_DETECT() taking the hpd_pin as their argument
we can remove some duplication in the long_detect() switch statements.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 19 +++
1 file changed, 3 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b245109f73e3..491f82500d68 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1044,17 +1044,12 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin
pin, u32 val)
{
switch (pin) {
case HPD_PORT_TC1:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC1);
case HPD_PORT_TC2:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC2);
case HPD_PORT_TC3:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC3);
case HPD_PORT_TC4:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC4);
case HPD_PORT_TC5:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC5);
case HPD_PORT_TC6:
- return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC6);
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin);
default:
return false;
}
@@ -1078,13 +1073,10 @@ static bool icp_ddi_port_hotplug_long_detect(enum
hpd_pin pin, u32 val)
{
switch (pin) {
case HPD_PORT_A:
- return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_A);
case HPD_PORT_B:
- return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_B);
case HPD_PORT_C:
- return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_C);
case HPD_PORT_D:
- return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_D);
+ return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin);
default:
return false;
}
@@ -1094,17 +1086,12 @@ static bool icp_tc_port_hotplug_long_detect(enum
hpd_pin pin, u32 val)
{
switch (pin) {
case HPD_PORT_TC1:
- return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC1);
case HPD_PORT_TC2:
- return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC2);
case HPD_PORT_TC3:
- return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC3);
case HPD_PORT_TC4:
- return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC4);
case HPD_PORT_TC5:
- return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC5);
case HPD_PORT_TC6:
- return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC6);
+ return val & ICP_TC_HPD_LONG_DETECT(pin);
default:
return false;
}
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Add a comment about how to use udev for configuring engines
== Series Details ==
Series: drm/i915/gt: Add a comment about how to use udev for configuring engines
URL : https://patchwork.freedesktop.org/series/84578/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9442_full -> Patchwork_19057_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19057_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_ctx_exec@basic-close-race}:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/shard-iclb6/igt@gem_ctx_e...@basic-close-race.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19057/shard-iclb3/igt@gem_ctx_e...@basic-close-race.html
New tests
-
New tests have been introduced between CI_DRM_9442_full and
Patchwork_19057_full:
### New CI tests (1) ###
* boot:
- Statuses : 199 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_19057_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_whisper@basic-fds-priority:
- shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/shard-glk3/igt@gem_exec_whis...@basic-fds-priority.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19057/shard-glk8/igt@gem_exec_whis...@basic-fds-priority.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-skl: [PASS][5] -> [DMESG-FAIL][6] ([i915#2291] /
[i915#541])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/shard-skl10/igt@i915_selftest@live@gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19057/shard-skl2/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [PASS][7] -> [FAIL][8] ([i915#2521])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/shard-skl5/igt@kms_async_fl...@alternate-sync-async-flip.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19057/shard-skl6/igt@kms_async_fl...@alternate-sync-async-flip.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) +2 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/shard-skl5/igt@kms_cursor_...@pipe-b-cursor-256x256-offscreen.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19057/shard-skl6/igt@kms_cursor_...@pipe-b-cursor-256x256-offscreen.html
* igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
- shard-hsw: [PASS][11] -> [INCOMPLETE][12] ([i915#2055])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/shard-hsw6/igt@kms_flip@flip-vs-susp...@c-hdmi-a1.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19057/shard-hsw1/igt@kms_flip@flip-vs-susp...@c-hdmi-a1.html
* igt@kms_flip@plain-flip-ts-check@b-edp1:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#2122])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/shard-skl8/igt@kms_flip@plain-flip-ts-ch...@b-edp1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19057/shard-skl3/igt@kms_flip@plain-flip-ts-ch...@b-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
- shard-apl: [PASS][15] -> [FAIL][16] ([i915#49])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/shard-apl3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19057/shard-apl2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#49])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/shard-glk3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19057/shard-glk5/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
- shard-kbl: [PASS][19] -> [FAIL][20] ([i915#49])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/shard-kbl7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19057/shard-kbl7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/shard-skl6/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19057/shard-skl7/ig
[Intel-gfx] [PATCH] drm/i915/display: Inject a failure into the initial modeset
Experiment with how fault tolerant we are if the initial modeset fails
and we need to abort the driver load.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 6e5b93f6a25e..86124b8d156d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -18456,7 +18456,9 @@ static int intel_initial_commit(struct drm_device *dev)
}
}
- ret = drm_atomic_commit(state);
+ ret = -ENODEV;
+ if (!i915_inject_probe_failure(to_i915(dev)))
+ ret = drm_atomic_commit(state);
out:
if (ret == -EDEADLK) {
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/display: Inject a failure into the initial modeset
Experiment with how fault tolerant we are if the initial modeset fails
and we need to abort the driver load.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 6e5b93f6a25e..c76c34e2c77a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -18456,7 +18456,9 @@ static int intel_initial_commit(struct drm_device *dev)
}
}
- ret = drm_atomic_commit(state);
+ ret = -ENODEV;
+ if (i915_inject_probe_failure(to_i915(dev)))
+ ret = drm_atomic_commit(state);
out:
if (ret == -EDEADLK) {
--
2.20.1
___
Intel-gfx mailing list
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/4] drm/i915/gt: Ignore repeated attempts to suspend request flow across reset
== Series Details == Series: series starting with [CI,1/4] drm/i915/gt: Ignore repeated attempts to suspend request flow across reset URL : https://patchwork.freedesktop.org/series/84582/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9442 -> Patchwork_19059 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19059 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19059, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19059/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19059: ### IGT changes ### Possible regressions * igt@gem_exec_suspend@basic-s0: - fi-snb-2600:[PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-snb-2600/igt@gem_exec_susp...@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19059/fi-snb-2600/igt@gem_exec_susp...@basic-s0.html * igt@i915_selftest@live@blt: - fi-snb-2520m: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-snb-2520m/igt@i915_selftest@l...@blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19059/fi-snb-2520m/igt@i915_selftest@l...@blt.html New tests - New tests have been introduced between CI_DRM_9442 and Patchwork_19059: ### New CI tests (1) ### * boot: - Statuses : 1 fail(s) 38 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19059 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#2411] / [i915#402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19059/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19059/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html Possible fixes * igt@gem_exec_create@basic: - fi-tgl-y: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-tgl-y/igt@gem_exec_cre...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19059/fi-tgl-y/igt@gem_exec_cre...@basic.html * igt@i915_selftest@live@sanitycheck: - fi-kbl-7500u: [DMESG-WARN][11] -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19059/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 39) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_9442 -> Patchwork_19059 CI-20190529: 20190529 CI_DRM_9442: 02c9a02a342173bd38a6c5210f1b047741a1b294 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5881: 10d4e2e9177eb747b9f2ab9122e3ab60e91654fb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19059: 1ba31db544dff75c78d363f66b8eed7f52ccb35d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1ba31db544df drm/i915/gt: Clear the execlists timers upon reset 87c6bc8c0e91 drm/i915/gt: Include reset failures in the trace 5f2a756cbc91 drm/i915/gt: Cancel the preemption timeout on responding to it 6784cc924e25 drm/i915/gt: Ignore repeated attempts to suspend request flow across reset == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19059/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/display: Support PSR Multiple Transcoders
On 2020-11-06 at 15:44:42 +0530, Gwan-gyeong Mun wrote:
> It is a preliminary work for supporting multiple EDP PSR and
> DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
> supportable PSR.
> And this moves and renames the i915_psr structure of drm_i915_private's to
> intel_dp's intel_psr structure.
> It also causes changes in PSR interrupt handling routine for supporting
> multiple transcoders. But it does not change the scenario and timing of
> enabling and disabling PSR.
Could you please break this patch, it can be break in following parts.
1. psr init path
2. atomic commit path
3. irq path
3. debugfs path
There are couple of comments, see below.
>
> v2: Fix indentation and add comments
> v3: Remove Blank line
> v4: Rebased
>
> Signed-off-by: Gwan-gyeong Mun
> Cc: José Roberto de Souza
> Cc: Juha-Pekka Heikkila
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 5 +
> drivers/gpu/drm/i915/display/intel_display.c | 4 -
> .../drm/i915/display/intel_display_debugfs.c | 111 ++--
> .../drm/i915/display/intel_display_types.h| 38 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 23 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 585 ++
> drivers/gpu/drm/i915/display/intel_psr.h | 14 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-
> drivers/gpu/drm/i915/i915_drv.h | 38 --
> drivers/gpu/drm/i915/i915_irq.c | 47 +-
> 10 files changed, 491 insertions(+), 380 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 19b16517a502..983781ce3683 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4127,7 +4127,10 @@ static void intel_ddi_update_pipe_dp(struct
> intel_atomic_state *state,
>
> intel_ddi_set_dp_msa(crtc_state, conn_state);
>
> + //TODO: move PSR related functions into intel_psr_update()
> + intel_psr2_program_trans_man_trk_ctl(intel_dp, crtc_state);
> intel_psr_update(intel_dp, crtc_state, conn_state);
> +
> intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> intel_edp_drrs_update(intel_dp, crtc_state);
>
> @@ -5275,6 +5278,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> goto err;
>
> dig_port->hpd_pulse = intel_dp_hpd_pulse;
> +
> + intel_psr_init(&dig_port->dp);
IMHO this should be called from intel_dp_init_connector.
> }
>
> /* In theory we don't need the encoder->type check, but leave it just in
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8c4687b19814..466923a54370 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15506,8 +15506,6 @@ static void commit_pipe_config(struct
> intel_atomic_state *state,
>
> if (new_crtc_state->update_pipe)
> intel_pipe_fastset(old_crtc_state, new_crtc_state);
> -
> - intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
> }
>
> if (dev_priv->display.atomic_update_watermarks)
> @@ -17435,8 +17433,6 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> intel_dvo_init(dev_priv);
> }
>
> - intel_psr_init(dev_priv);
> -
> for_each_intel_encoder(&dev_priv->drm, encoder) {
> encoder->base.possible_crtcs =
> intel_encoder_possible_crtcs(encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index cfb4c1474982..8402e6ac9f76 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -248,18 +248,17 @@ static int i915_psr_sink_status_show(struct seq_file
> *m, void *data)
> "sink internal error",
> };
> struct drm_connector *connector = m->private;
> - struct drm_i915_private *dev_priv = to_i915(connector->dev);
> struct intel_dp *intel_dp =
> intel_attached_dp(to_intel_connector(connector));
> int ret;
>
> - if (!CAN_PSR(dev_priv)) {
> - seq_puts(m, "PSR Unsupported\n");
> + if (connector->status != connector_status_connected)
> return -ENODEV;
> - }
>
> - if (connector->status != connector_status_connected)
> + if (!CAN_PSR(intel_dp)) {
> + seq_puts(m, "PSR Unsupported\n");
> return -ENODEV;
> + }
>
> ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
>
> @@ -279,12 +278,13 @@ static int i915_psr_sink_status_show(struct seq_file
> *m, void *data)
> DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
>
> static void
> -psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m
[Intel-gfx] [PATCH] dma-buf: Fix kerneldoc formatting
I wanted to look up something and noticed the hyperlink doesn't work.
While fixing that also noticed a trivial kerneldoc comment typo in the
same section, fix that too.
Signed-off-by: Daniel Vetter
---
Documentation/driver-api/dma-buf.rst | 2 +-
include/linux/dma-buf-map.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/driver-api/dma-buf.rst
b/Documentation/driver-api/dma-buf.rst
index d6b2a195dbed..a2133d69872c 100644
--- a/Documentation/driver-api/dma-buf.rst
+++ b/Documentation/driver-api/dma-buf.rst
@@ -190,7 +190,7 @@ DMA Fence uABI/Sync File
Indefinite DMA Fences
~
-At various times &dma_fence with an indefinite time until dma_fence_wait()
+At various times struct dma_fence with an indefinite time until
dma_fence_wait()
finishes have been proposed. Examples include:
* Future fences, used in HWC1 to signal when a buffer isn't used by the display
diff --git a/include/linux/dma-buf-map.h b/include/linux/dma-buf-map.h
index 583a3a1f9447..278d489e4bdd 100644
--- a/include/linux/dma-buf-map.h
+++ b/include/linux/dma-buf-map.h
@@ -122,7 +122,7 @@ struct dma_buf_map {
/**
* DMA_BUF_MAP_INIT_VADDR - Initializes struct dma_buf_map to an address in
system memory
- * @vaddr: A system-memory address
+ * @vaddr_:A system-memory address
*/
#define DMA_BUF_MAP_INIT_VADDR(vaddr_) \
{ \
--
2.29.2
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/4] drm/i915/gt: Ignore repeated attempts to suspend request flow across reset
== Series Details == Series: series starting with [CI,1/4] drm/i915/gt: Ignore repeated attempts to suspend request flow across reset URL : https://patchwork.freedesktop.org/series/84582/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/24] drm/i915: Disable outputs during unregister
== Series Details == Series: series starting with [01/24] drm/i915: Disable outputs during unregister URL : https://patchwork.freedesktop.org/series/84579/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9442 -> Patchwork_19058 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19058 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19058, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19058/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19058: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_timelines: - fi-skl-6600u: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-skl-6600u/igt@i915_selftest@live@gt_timelines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19058/fi-skl-6600u/igt@i915_selftest@live@gt_timelines.html - fi-bdw-5557u: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-bdw-5557u/igt@i915_selftest@live@gt_timelines.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19058/fi-bdw-5557u/igt@i915_selftest@live@gt_timelines.html - fi-cfl-8109u: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-cfl-8109u/igt@i915_selftest@live@gt_timelines.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19058/fi-cfl-8109u/igt@i915_selftest@live@gt_timelines.html - fi-glk-dsi: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-glk-dsi/igt@i915_selftest@live@gt_timelines.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19058/fi-glk-dsi/igt@i915_selftest@live@gt_timelines.html - fi-bsw-nick:[PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-bsw-nick/igt@i915_selftest@live@gt_timelines.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19058/fi-bsw-nick/igt@i915_selftest@live@gt_timelines.html - fi-tgl-y: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-tgl-y/igt@i915_selftest@live@gt_timelines.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19058/fi-tgl-y/igt@i915_selftest@live@gt_timelines.html - fi-bsw-kefka: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-bsw-kefka/igt@i915_selftest@live@gt_timelines.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19058/fi-bsw-kefka/igt@i915_selftest@live@gt_timelines.html - fi-cml-s: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-cml-s/igt@i915_selftest@live@gt_timelines.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19058/fi-cml-s/igt@i915_selftest@live@gt_timelines.html - fi-kbl-soraka: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-kbl-soraka/igt@i915_selftest@live@gt_timelines.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19058/fi-kbl-soraka/igt@i915_selftest@live@gt_timelines.html - fi-bxt-dsi: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-bxt-dsi/igt@i915_selftest@live@gt_timelines.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19058/fi-bxt-dsi/igt@i915_selftest@live@gt_timelines.html New tests - New tests have been introduced between CI_DRM_9442 and Patchwork_19058: ### New CI tests (1) ### * boot: - Statuses : 1 fail(s) 38 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19058 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gt_timelines: - fi-apl-guc: [PASS][21] -> [INCOMPLETE][22] ([i915#2750]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19058/fi-apl-guc/igt@i915_selftest@live@gt_timelines.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [PASS][23] -> [DMESG-WARN][24] ([i915#165]) +27 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19058/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html * i
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/4] drm/i915/gt: Ignore repeated attempts to suspend request flow across reset
== Series Details == Series: series starting with [CI,1/4] drm/i915/gt: Ignore repeated attempts to suspend request flow across reset URL : https://patchwork.freedesktop.org/series/84582/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6784cc924e25 drm/i915/gt: Ignore repeated attempts to suspend request flow across reset -:7: WARNING:TYPO_SPELLING: 'reseting' may be misspelled - perhaps 'resetting'? #7: Before reseting the engine, we suspend the execution of the guilty -:17: WARNING:BAD_SIGN_OFF: email address ' # v5.7+' might be better as 'sta...@vger.kernel.org# v5.7+' #17: Cc: # v5.7+ total: 0 errors, 2 warnings, 0 checks, 9 lines checked 5f2a756cbc91 drm/i915/gt: Cancel the preemption timeout on responding to it -:17: WARNING:BAD_SIGN_OFF: email address ' # v5.5+' might be better as 'sta...@vger.kernel.org# v5.5+' #17: Cc: # v5.5+ total: 0 errors, 1 warnings, 0 checks, 11 lines checked 87c6bc8c0e91 drm/i915/gt: Include reset failures in the trace 1ba31db544df drm/i915/gt: Clear the execlists timers upon reset ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
On 2020-11-18 at 16:42:29 +0530, Jani Nikula wrote:
> On Fri, 06 Nov 2020, Gwan-gyeong Mun wrote:
> > In order to support the PSR state of each transcoder, it adds
> > i915_psr_status to sub-directory of each transcoder.
> >
> > v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
> > permissions '0444'
> >
> > Signed-off-by: Gwan-gyeong Mun
> > Cc: José Roberto de Souza
> > ---
> > .../drm/i915/display/intel_display_debugfs.c | 23 +++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index 8402e6ac9f76..37805615a221 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -2093,6 +2093,23 @@ static int i915_hdcp_sink_capability_show(struct
> > seq_file *m, void *data)
> > }
> > DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
> >
> > +static int i915_psr_status_show(struct seq_file *m, void *data)
> > +{
> > + struct drm_connector *connector = m->private;
> > + struct intel_dp *intel_dp =
> > + intel_attached_dp(to_intel_connector(connector));
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + if (connector->status != connector_status_connected)
>
> How's this possible for eDP, btw?
>
> BR,
> Jani.
>
> > + return -ENODEV;
> > +
> > + if (!HAS_PSR(dev_priv))
> > + return -ENODEV;
> > +
> > + return intel_psr_status(m, intel_dp);
> > +}
> > +DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
> > +
> > #define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
> > seq_puts(m, "LPSP: incapable\n"))
> >
> > @@ -2268,6 +2285,12 @@ int intel_connector_debugfs_add(struct drm_connector
> > *connector)
> > connector, &i915_psr_sink_status_fops);
> > }
> >
> > + if (INTEL_GEN(dev_priv) >= 12 &&
> > + connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
Hi GG
IMHO this should connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
connector->connector_type == DRM_MODE_SUBCONNECTOR_DisplayPort
to support DP Panel Reply, i read somewere DP panel reply is PSR with Link Full
ON ?
I believe this would be the reason to keep file name as "i915_psr_status"
instead of i915_edp_psr_status?
Thanks,
Anshuman.
> > + debugfs_create_file("i915_psr_status", 0444, root,
> > + connector, &i915_psr_status_fops);
> > + }
> > +
> > if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> > connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
> > connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
>
> --
> Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] [CI] drm/i915: Disable outputs during unregister
Switch off the scanout during driver unregister, so we can shutdown the HW immediately for unbind. v2: Remove the old shutdown from remove, it should now be redundant. Signed-off-by: Chris Wilson Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 320856b665a1..5708e11d917b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -738,6 +738,7 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) * events. */ drm_kms_helper_poll_fini(&dev_priv->drm); + drm_atomic_helper_shutdown(&dev_priv->drm); intel_gt_driver_unregister(&dev_priv->gt); acpi_video_unregister(); @@ -940,8 +941,6 @@ void i915_driver_remove(struct drm_i915_private *i915) i915_gem_suspend(i915); - drm_atomic_helper_shutdown(&i915->drm); - intel_gvt_driver_remove(i915); intel_modeset_driver_remove(i915); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Disable outputs during unregister
Quoting Ville Syrjälä (2020-12-04 16:01:11) > On Tue, Dec 01, 2020 at 10:38:57PM +, Chris Wilson wrote: > > Quoting Ville Syrjälä (2020-12-01 16:05:17) > > > On Fri, Nov 27, 2020 at 10:05:48PM +, Chris Wilson wrote: > > > > Switch off the scanout during driver unregister, so we can shutdown the > > > > HW immediately for unbind. > > > > > > > > Signed-off-by: Chris Wilson > > > > --- > > > > drivers/gpu/drm/i915/i915_drv.c | 1 + > > > > 1 file changed, 1 insertion(+) > > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c > > > > b/drivers/gpu/drm/i915/i915_drv.c > > > > index 320856b665a1..62d188e5cb8d 100644 > > > > --- a/drivers/gpu/drm/i915/i915_drv.c > > > > +++ b/drivers/gpu/drm/i915/i915_drv.c > > > > @@ -738,6 +738,7 @@ static void i915_driver_unregister(struct > > > > drm_i915_private *dev_priv) > > > >* events. > > > >*/ > > > > drm_kms_helper_poll_fini(&dev_priv->drm); > > > > + drm_atomic_helper_shutdown(&dev_priv->drm); > > > > > > Looks like we already have this in remove(). Is that too late? > > > > For the operations we do during unbind, yes. > > > > For the core_hotplug/rebind dance, we have to reset the GPU while we > > still have runtime-pm operational and have pushed the reset to > > unregister (from experimentation that's as late as we can put it where > > the GPU works after rebinding and we don't corrupt the system on unbind, > > with the current hooks). You can guess how well gen3 likes that. > > > > But I don't think the right answer is to skip the reset for gen3. > > Suppose we enable context support for gen3, then the reset would be > > required as well, and so we would still need the whole display > > shenanigans to turn it off. Moving the modeset to turn the display off > > to the end of userspace seems reasonable. > > Yeah, just a bit odd to have the same call twice in the > sequence. Can we remove the second call at least? I think we can, but I am sufficiently paranoid to leave it. I presume if it is a no-op, it will return without touching HW? > Also a bit annoying the unload sequence no longer matches the > suspend sequence. Well, I guess it was never 100% anyway but > I think it was a bit closer before this patch. But the whole > thing is rather messy anyway so I guess t's not significantly > worse after this. Yes, I feel things have been thrown into a bit of disarray by haphazardly fixing unbind. The last* remaining fly in the ointment is rebinding iommu. Once we have that solid (and the system stops randomly eating itself 1-10 minutes after the test passes), we should be in a much better spot to safely remove duplication and refine the flow. * that I am aware of. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/17] drivers/gpu: Convert to mem*_page()
On Fri, Nov 27, 2020 at 03:01:56PM +0200, Joonas Lahtinen wrote:
> + intel-gfx mailing list
>
> Quoting ira.we...@intel.com (2020-11-24 08:07:41)
> > From: Ira Weiny
> >
> > The pattern of kmap/mem*/kunmap is repeated. Use the new mem*_page()
> > calls instead.
> >
> > Cc: Patrik Jakobsson
> > Cc: Jani Nikula
> > Cc: Joonas Lahtinen
> > Cc: Rodrigo Vivi
> > Signed-off-by: Ira Weiny
> > ---
> > drivers/gpu/drm/gma500/gma_display.c | 7 +++
> > drivers/gpu/drm/gma500/mmu.c | 4 ++--
> > drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 6 ++
> > drivers/gpu/drm/i915/gt/intel_gtt.c | 9 ++---
> > drivers/gpu/drm/i915/gt/shmem_utils.c | 8 +++-
>
> Are you looking to merge all these from the same tree, or first merge
> the first patch and then trickle the rest through their own trees?
I was thinking that they would go through Andrew's tree in bulk. But as I go
through all the 'variants' including adding any kmap_atomic() variants it is
getting to be a pretty big change. I'm trying to use Coccinelle but I'm not
100% confident in it working, more precisely in my skill to make it work.
So I think I'm going to submit the base patch to Andrew today (with some
cleanups per the comments in this thread).
If Andrew could land that then I will can submit separate patches to each
subsystem which would get full testing... :-(
That is best.
Thanks for making me think on this,
Ira
> Our last -next PR was already sent for i915, so I would queue this
> only for 5.12.
>
> In any case, if you could split the i915 changes to a separate patch
> (we have multiple sub-trees in drm), those are:
>
> Reviewed-by: Joonas Lahtinen
>
> The gma500 changes also appear correct, so feel free to apply the
> R-b for those, too.
>
> Regards, Joonas
>
> > 5 files changed, 12 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/gma500/gma_display.c
> > b/drivers/gpu/drm/gma500/gma_display.c
> > index 3df6d6e850f5..f81114594211 100644
> > --- a/drivers/gpu/drm/gma500/gma_display.c
> > +++ b/drivers/gpu/drm/gma500/gma_display.c
> > @@ -9,6 +9,7 @@
> >
> > #include
> > #include
> > +#include
> >
> > #include
> > #include
> > @@ -334,7 +335,7 @@ int gma_crtc_cursor_set(struct drm_crtc *crtc,
> > struct gtt_range *gt;
> > struct gtt_range *cursor_gt = gma_crtc->cursor_gt;
> > struct drm_gem_object *obj;
> > - void *tmp_dst, *tmp_src;
> > + void *tmp_dst;
> > int ret = 0, i, cursor_pages;
> >
> > /* If we didn't get a handle then turn the cursor off */
> > @@ -400,9 +401,7 @@ int gma_crtc_cursor_set(struct drm_crtc *crtc,
> > /* Copy the cursor to cursor mem */
> > tmp_dst = dev_priv->vram_addr + cursor_gt->offset;
> > for (i = 0; i < cursor_pages; i++) {
> > - tmp_src = kmap(gt->pages[i]);
> > - memcpy(tmp_dst, tmp_src, PAGE_SIZE);
> > - kunmap(gt->pages[i]);
> > + memcpy_from_page(tmp_dst, gt->pages[i], 0,
> > PAGE_SIZE);
> > tmp_dst += PAGE_SIZE;
> > }
> >
> > diff --git a/drivers/gpu/drm/gma500/mmu.c b/drivers/gpu/drm/gma500/mmu.c
> > index 505044c9a673..8a0856c7f439 100644
> > --- a/drivers/gpu/drm/gma500/mmu.c
> > +++ b/drivers/gpu/drm/gma500/mmu.c
> > @@ -5,6 +5,7 @@
> >
> > **/
> >
> > #include
> > +#include
> >
> > #include "mmu.h"
> > #include "psb_drv.h"
> > @@ -204,8 +205,7 @@ struct psb_mmu_pd *psb_mmu_alloc_pd(struct
> > psb_mmu_driver *driver,
> >
> > kunmap(pd->p);
> >
> > - clear_page(kmap(pd->dummy_page));
> > - kunmap(pd->dummy_page);
> > + memzero_page(pd->dummy_page, 0, PAGE_SIZE);
> >
> > pd->tables = vmalloc_user(sizeof(struct psb_mmu_pt *) * 1024);
> > if (!pd->tables)
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> > index 75e8b71c18b9..8a25e08edd18 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> > @@ -558,7 +558,7 @@ i915_gem_object_create_shmem_from_data(struct
> > drm_i915_private *dev_priv,
> > do {
> > unsigned int len = min_t(typeof(size), size, PAGE_SIZE);
> > struct page *page;
> > - void *pgdata, *vaddr;
> > + void *pgdata;
> >
> > err = pagecache_write_begin(file, file->f_mapping,
> > offset, len, 0,
> > @@ -566,9 +566,7 @@ i915_gem_object_create_shmem_from_data(struct
> > drm_i915_private *dev_priv,
> > if (err < 0)
> > goto fail;
> >
> > - vaddr = kmap(page);
> > - memcpy(vaddr, data, len);
> > - kunmap(page);
> > +
Re: [Intel-gfx] [PATCH] drm/i915: Disable outputs during unregister
On Tue, Dec 01, 2020 at 10:38:57PM +, Chris Wilson wrote: > Quoting Ville Syrjälä (2020-12-01 16:05:17) > > On Fri, Nov 27, 2020 at 10:05:48PM +, Chris Wilson wrote: > > > Switch off the scanout during driver unregister, so we can shutdown the > > > HW immediately for unbind. > > > > > > Signed-off-by: Chris Wilson > > > --- > > > drivers/gpu/drm/i915/i915_drv.c | 1 + > > > 1 file changed, 1 insertion(+) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c > > > b/drivers/gpu/drm/i915/i915_drv.c > > > index 320856b665a1..62d188e5cb8d 100644 > > > --- a/drivers/gpu/drm/i915/i915_drv.c > > > +++ b/drivers/gpu/drm/i915/i915_drv.c > > > @@ -738,6 +738,7 @@ static void i915_driver_unregister(struct > > > drm_i915_private *dev_priv) > > >* events. > > >*/ > > > drm_kms_helper_poll_fini(&dev_priv->drm); > > > + drm_atomic_helper_shutdown(&dev_priv->drm); > > > > Looks like we already have this in remove(). Is that too late? > > For the operations we do during unbind, yes. > > For the core_hotplug/rebind dance, we have to reset the GPU while we > still have runtime-pm operational and have pushed the reset to > unregister (from experimentation that's as late as we can put it where > the GPU works after rebinding and we don't corrupt the system on unbind, > with the current hooks). You can guess how well gen3 likes that. > > But I don't think the right answer is to skip the reset for gen3. > Suppose we enable context support for gen3, then the reset would be > required as well, and so we would still need the whole display > shenanigans to turn it off. Moving the modeset to turn the display off > to the end of userspace seems reasonable. Yeah, just a bit odd to have the same call twice in the sequence. Can we remove the second call at least? Also a bit annoying the unload sequence no longer matches the suspend sequence. Well, I guess it was never 100% anyway but I think it was a bit closer before this patch. But the whole thing is rather messy anyway so I guess t's not significantly worse after this. Reviewed-by: Ville Syrjälä -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/24] drm/i915: Disable outputs during unregister
== Series Details == Series: series starting with [01/24] drm/i915: Disable outputs during unregister URL : https://patchwork.freedesktop.org/series/84579/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1326:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:expected void *in +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:expected void const *src +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:expected unsigned int [usertype] *s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:got void [noderef] __iomem *[assigned] s +drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1447:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1501:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:838:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:864:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/24] drm/i915: Disable outputs during unregister
== Series Details == Series: series starting with [01/24] drm/i915: Disable outputs during unregister URL : https://patchwork.freedesktop.org/series/84579/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2bae8f3c30a7 drm/i915: Disable outputs during unregister 363bb75548d1 drm/i915/gt: Ignore repeated attempts to suspend request flow across reset -:7: WARNING:TYPO_SPELLING: 'reseting' may be misspelled - perhaps 'resetting'? #7: Before reseting the engine, we suspend the execution of the guilty -:17: WARNING:BAD_SIGN_OFF: email address ' # v5.7+' might be better as 'sta...@vger.kernel.org# v5.7+' #17: Cc: # v5.7+ total: 0 errors, 2 warnings, 0 checks, 9 lines checked 5f68e7fe001d drm/i915/gt: Cancel the preemption timeout on responding to it -:17: WARNING:BAD_SIGN_OFF: email address ' # v5.5+' might be better as 'sta...@vger.kernel.org# v5.5+' #17: Cc: # v5.5+ total: 0 errors, 1 warnings, 0 checks, 11 lines checked 4aec48d111f4 drm/i915/gt: Include reset failures in the trace dbc53514f4b6 drm/i915/gt: Clear the execlists timers upon reset 44f085d92e2c drm/i915/gt: Replace direct submit with direct call to tasklet ea79baee80ce drm/i915/gt: Use virtual_engine during execlists_dequeue 49b88baf972d drm/i915/gt: Decouple inflight virtual engines 22ca745b6b71 drm/i915/gt: Defer schedule_out until after the next dequeue bfc60ea87a1f drm/i915/gt: Remove virtual breadcrumb before transfer 44173d41aef0 drm/i915/gt: Shrink the critical section for irq signaling 2553339dfe7a drm/i915/gt: Resubmit the virtual engine on schedule-out 66f9cbe3938f drm/i915/gt: Simplify virtual engine handling for execlists_hold() 7693cd2d83df drm/i915/gt: ce->inflight updates are now serialised 68b8f9056a58 drm/i915/gem: Drop free_work for GEM contexts 794eff00db39 drm/i915/gt: Track the overall awake/busy time a38be5734e47 drm/i915: Encode fence specific waitqueue behaviour into the wait.flags 81943438c451 drm/i915/gt: Track all timelines created using the HWSP 476117c64cb4 drm/i915/gt: Wrap intel_timeline.has_initial_breadcrumb a4ec0db74fea drm/i915/gt: Track timeline GGTT offset separately from subpage offset 6d370b2a6ce1 drm/i915/gt: Add timeline "mode" 612cd1428563 drm/i915/gt: Use indices for writing into relative timelines 17d6ab1a040c drm/i915/selftests: Exercise relative timeline modes 9b4381eeec21 drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Protect pipe_update against dc3co exit
On Fri, Dec 04, 2020 at 01:40:03PM +0530, Anshuman Gupta wrote:
> On 2020-11-30 at 17:28:32 +0200, Imre Deak wrote:
> > On Mon, Nov 30, 2020 at 02:46:46PM +0530, Anshuman Gupta wrote:
> > > At usual case DC3CO exit happen automatically by DMC f/w whenever
> > > PSR2 clears idle. This happens smoothly by DMC f/w to work with flips.
> > > But there are certain scenario where DC3CO Disallowed by driver
> > > asynchronous with flips. In such scenario display engine could
> > > be already in DC3CO state and driver has disallowed it,
> > > It initiates DC3CO exit sequence in DMC f/w which requires a
> > > dc3co exit delay of 200us in driver.
> > > It requires to protect intel_pipe_update_{update_end} with
> > > dc3co exit delay.
> > >
> > > Cc: Imre Deak
> > > Cc:
> > > Signed-off-by: Anshuman Gupta
> >
> > To make sure that it doesn't hide the root cause (or affects unrelated
> > platforms), I'd only add locking around DC3co changes with a new lock,
> > using lock/unlock helpers in intel_display_power.c called from
> > intel_pipe_update_start/end.
> >
> > Also please submit this patch separately, w/o the optimization in patch
> > 1/2, so we know that this change fixes the problem.
> This patch doesn't seems to fix the issue.
> Looks like there is some other set of display register updates before
> completing the dc3co exit delay beyond intel_pipe_update_start/end causing
> this issue.
Not really sure I understand the DC3CO issue here, nor how grabbing a
mutex across the update could help.
But anyways, maybe we should just:
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 2e2dd746921f..96276f0feddc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16268,8 +16268,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
drm_atomic_helper_wait_for_dependencies(&state->base);
- if (state->modeset)
- wakeref = intel_display_power_get(dev_priv,
POWER_DOMAIN_MODESET);
+ wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
@@ -16415,8 +16414,8 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
* the culprit.
*/
intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
- intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET,
wakeref);
}
+ intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
/*
To get the DMC out of equation entirely for all plane updates?
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add a comment about how to use udev for configuring engines
== Series Details == Series: drm/i915/gt: Add a comment about how to use udev for configuring engines URL : https://patchwork.freedesktop.org/series/84578/ State : success == Summary == CI Bug Log - changes from CI_DRM_9442 -> Patchwork_19057 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19057/index.html New tests - New tests have been introduced between CI_DRM_9442 and Patchwork_19057: ### New CI tests (1) ### * boot: - Statuses : 1 fail(s) 37 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_19057 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@read_all_entries: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-tgl-y/igt@debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19057/fi-tgl-y/igt@debugfs_test@read_all_entries.html Possible fixes * igt@gem_exec_create@basic: - fi-tgl-y: [DMESG-WARN][3] ([i915#402]) -> [PASS][4] +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-tgl-y/igt@gem_exec_cre...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19057/fi-tgl-y/igt@gem_exec_cre...@basic.html * igt@i915_selftest@live@sanitycheck: - fi-kbl-7500u: [DMESG-WARN][5] -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9442/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19057/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 38) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-blb-e6850 fi-bdw-samus Build changes - * Linux: CI_DRM_9442 -> Patchwork_19057 CI-20190529: 20190529 CI_DRM_9442: 02c9a02a342173bd38a6c5210f1b047741a1b294 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5881: 10d4e2e9177eb747b9f2ab9122e3ab60e91654fb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19057: c1053d20241bf75db6af0f8e74b0511266ecb80c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c1053d20241b drm/i915/gt: Add a comment about how to use udev for configuring engines == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19057/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 3/4] drm/i915/gt: Include reset failures in the trace
The GT and engine reset failures are completely invisible when looking at
a trace for a bug, but are vital to understanding the incomplete flow.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_reset.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 3654c955e6be..000d63588e9e 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -231,7 +231,7 @@ static int g4x_do_reset(struct intel_gt *gt,
GRDOM_MEDIA | GRDOM_RESET_ENABLE);
ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
if (ret) {
- drm_dbg(>->i915->drm, "Wait for media reset failed\n");
+ GT_TRACE(gt, "Wait for media reset failed\n");
goto out;
}
@@ -239,7 +239,7 @@ static int g4x_do_reset(struct intel_gt *gt,
GRDOM_RENDER | GRDOM_RESET_ENABLE);
ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
if (ret) {
- drm_dbg(>->i915->drm, "Wait for render reset failed\n");
+ GT_TRACE(gt, "Wait for render reset failed\n");
goto out;
}
@@ -265,7 +265,7 @@ static int ilk_do_reset(struct intel_gt *gt,
intel_engine_mask_t engine_mask,
5000, 0,
NULL);
if (ret) {
- drm_dbg(>->i915->drm, "Wait for render reset failed\n");
+ GT_TRACE(gt, "Wait for render reset failed\n");
goto out;
}
@@ -276,7 +276,7 @@ static int ilk_do_reset(struct intel_gt *gt,
intel_engine_mask_t engine_mask,
5000, 0,
NULL);
if (ret) {
- drm_dbg(>->i915->drm, "Wait for media reset failed\n");
+ GT_TRACE(gt, "Wait for media reset failed\n");
goto out;
}
@@ -305,9 +305,9 @@ static int gen6_hw_domain_reset(struct intel_gt *gt, u32
hw_domain_mask)
500, 0,
NULL);
if (err)
- drm_dbg(>->i915->drm,
- "Wait for 0x%08x engines reset failed\n",
- hw_domain_mask);
+ GT_TRACE(gt,
+"Wait for 0x%08x engines reset failed\n",
+hw_domain_mask);
return err;
}
@@ -407,8 +407,7 @@ static int gen11_lock_sfc(struct intel_engine_cs *engine,
u32 *hw_mask)
return 0;
if (ret) {
- drm_dbg(&engine->i915->drm,
- "Wait for SFC forced lock ack failed\n");
+ ENGINE_TRACE(engine, "Wait for SFC forced lock ack failed\n");
return ret;
}
@@ -1148,8 +1147,7 @@ int intel_engine_reset(struct intel_engine_cs *engine,
const char *msg)
ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine);
if (ret) {
/* If we fail here, we expect to fallback to a global reset */
- drm_dbg(>->i915->drm, "%sFailed to reset %s, ret=%d\n",
- uses_guc ? "GuC " : "", engine->name, ret);
+ ENGINE_TRACE(engine, "Failed to reset, err: %d\n", ret);
goto out;
}
@@ -1186,7 +1184,7 @@ static void intel_gt_reset_global(struct intel_gt *gt,
kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
- drm_dbg(>->i915->drm, "resetting chip, engines=%x\n", engine_mask);
+ GT_TRACE(gt, "resetting chip, engines=%x\n", engine_mask);
kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
/* Use a watchdog to ensure that our reset completes */
--
2.20.1
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[Intel-gfx] [CI 4/4] drm/i915/gt: Clear the execlists timers upon reset
Across a reset, we stop the engine but not the timers. This leaves a window where the timers have inconsistent state with the engine, but should only result in a spurious timeout. As we cancel the outstanding events, also cancel their timers. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_lrc.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 7f25894e41d5..0c7f1e3dee5c 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2450,6 +2450,11 @@ cancel_port_requests(struct intel_engine_execlists * const execlists) smp_wmb(); /* complete the seqlock for execlists_active() */ WRITE_ONCE(execlists->active, execlists->inflight); + + /* Having cancelled all outstanding process_csb(), stop their timers */ + GEM_BUG_ON(execlists->pending[0]); + cancel_timer(&execlists->timer); + cancel_timer(&execlists->preempt); } static inline void -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/4] drm/i915/gt: Cancel the preemption timeout on responding to it
We currently presume that the engine reset is successful, cancelling the
expired preemption timer in the process. However, engine resets can
fail, leaving the timeout still pending and we will then respond to the
timeout again next time the tasklet fires. What we want is for the
failed engine reset to be promoted to a full device reset, which is
kicked by the heartbeat once the engine stops processing events.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1168
Fixes: 3a7a92aba8fb ("drm/i915/execlists: Force preemption")
Signed-off-by: Chris Wilson
Cc: # v5.5+
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 1d209a8a95e8..7f25894e41d5 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3209,8 +3209,10 @@ static void execlists_submission_tasklet(unsigned long
data)
spin_unlock_irqrestore(&engine->active.lock, flags);
/* Recheck after serialising with direct-submission */
- if (unlikely(timeout && preempt_timeout(engine)))
+ if (unlikely(timeout && preempt_timeout(engine))) {
+ cancel_timer(&engine->execlists.preempt);
execlists_reset(engine, "preemption time out");
+ }
}
}
--
2.20.1
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[Intel-gfx] [CI 1/4] drm/i915/gt: Ignore repeated attempts to suspend request flow across reset
Before reseting the engine, we suspend the execution of the guilty
request, so that we can continue execution with a new context while we
slowly compress the captured error state for the guilty context. However,
if the reset fails, we will promptly attempt to reset the same request
again, and discover the ongoing capture. Ignore the second attempt to
suspend and capture the same request.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1168
Fixes: 32ff621fd744 ("drm/i915/gt: Allow temporary suspension of inflight
requests")
Signed-off-by: Chris Wilson
Cc: # v5.7+
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 43703efb36d1..1d209a8a95e8 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2823,6 +2823,9 @@ static void __execlists_hold(struct i915_request *rq)
static bool execlists_hold(struct intel_engine_cs *engine,
struct i915_request *rq)
{
+ if (i915_request_on_hold(rq))
+ return false;
+
spin_lock_irq(&engine->active.lock);
if (i915_request_completed(rq)) { /* too late! */
--
2.20.1
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Re: [Intel-gfx] [PATCH 03/24] drm/i915/gt: Cancel the preemption timeout on responding to it
Chris Wilson writes:
> We currently presume that the engine reset is successful, cancelling the
> expired preemption timer in the process. However, engine resets can
> fail, leaving the timeout still pending and we will then respond to the
> timeout again next time the tasklet fires. What we want is for the
> failed engine reset to be promoted to a full device reset, which is
> kicked by the heartbeat once the engine stops processing events.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1168
> Fixes: 3a7a92aba8fb ("drm/i915/execlists: Force preemption")
> Signed-off-by: Chris Wilson
> Cc: # v5.5+
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 1d209a8a95e8..7f25894e41d5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -3209,8 +3209,10 @@ static void execlists_submission_tasklet(unsigned long
> data)
> spin_unlock_irqrestore(&engine->active.lock, flags);
>
> /* Recheck after serialising with direct-submission */
> - if (unlikely(timeout && preempt_timeout(engine)))
> + if (unlikely(timeout && preempt_timeout(engine))) {
> + cancel_timer(&engine->execlists.preempt);
> execlists_reset(engine, "preemption time out");
> + }
> }
> }
>
> --
> 2.20.1
>
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Re: [Intel-gfx] [PATCH 02/24] drm/i915/gt: Ignore repeated attempts to suspend request flow across reset
Chris Wilson writes:
> Before reseting the engine, we suspend the execution of the guilty
> request, so that we can continue execution with a new context while we
> slowly compress the captured error state for the guilty context. However,
> if the reset fails, we will promptly attempt to reset the same request
> again, and discover the ongoing capture. Ignore the second attempt to
> suspend and capture the same request.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1168
> Fixes: 32ff621fd744 ("drm/i915/gt: Allow temporary suspension of inflight
> requests")
> Signed-off-by: Chris Wilson
> Cc: # v5.7+
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 43703efb36d1..1d209a8a95e8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2823,6 +2823,9 @@ static void __execlists_hold(struct i915_request *rq)
> static bool execlists_hold(struct intel_engine_cs *engine,
> struct i915_request *rq)
> {
> + if (i915_request_on_hold(rq))
> + return false;
> +
> spin_lock_irq(&engine->active.lock);
>
> if (i915_request_completed(rq)) { /* too late! */
> --
> 2.20.1
>
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Re: [Intel-gfx] [RFC-v4 24/26] drm/i915/pxp: User interface for Protected buffer
On 02/12/2020 06:03, Huang, Sean Z wrote:
From: Bommu Krishnaiah
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 10
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5
drivers/gpu/drm/i915/i915_gem.c | 23 +++
include/uapi/drm/i915_drm.h | 19 +++
6 files changed, 67 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index a6299da64de4..dd5d24a13cb9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -2060,12 +2060,23 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
+ else if (args->value) {
+ if (!i915_gem_context_is_protected(ctx))
+ i915_gem_context_set_recoverable(ctx);
+ else
+ ret = -EPERM;
+ }
else
i915_gem_context_clear_recoverable(ctx);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ if (args->size)
+ ret = -EINVAL;
+ else if (args->value)
+ i915_gem_context_set_protected(ctx);
+ break;
+
case I915_CONTEXT_PARAM_PRIORITY:
ret = set_priority(ctx, args);
break;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index a133f92bbedb..5897e7ca11a8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -70,6 +70,16 @@ static inline void i915_gem_context_set_recoverable(struct
i915_gem_context *ctx
set_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
}
+static inline void i915_gem_context_set_protected(struct i915_gem_context *ctx)
+{
+ set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
+static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
static inline void i915_gem_context_clear_recoverable(struct i915_gem_context
*ctx)
{
clear_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index ae14ca24a11f..81ae94c2be86 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -135,7 +135,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
-
+#define UCONTEXT_PROTECTED 5
/**
* @flags: small set of booleans
*/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e2d9b7e1e152..90ac955463f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -161,6 +161,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+* @user_flags: small set of booleans set by the user
+*/
+ unsigned long user_flags;
+#define I915_BO_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 41698a823737..6a791fd24eaa 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -184,7 +184,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
@@ -258,11 +261,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to
[Intel-gfx] [RFC PATCH 2/2] i915: POC use dynamic_debug_exec_queries to control pr_debugs in gvt
The gvt component of this driver has ~120 pr_debugs, in 9 "classes".
Following model of drm.debug, add a parameter to map bits to these
classes.
In Makefile, add DYNAMIC_DEBUG_MODULE. This converts gvt's pr_debugs,
even if the rest of drm is not using CONFIG_DRM_USE_DYNAMIC_DEBUG.
Signed-off-by: Jim Cromie
---
drivers/gpu/drm/i915/gvt/Makefile | 1 +
drivers/gpu/drm/i915/i915_params.c | 74 ++
2 files changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/i915/gvt/Makefile
b/drivers/gpu/drm/i915/gvt/Makefile
index ea8324abc784..e38a1eb618bd 100644
--- a/drivers/gpu/drm/i915/gvt/Makefile
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -6,4 +6,5 @@ GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o
trace_points.o firmware.o \
fb_decoder.o dmabuf.o page_track.o
ccflags-y += -I $(srctree)/$(src) -I
$(srctree)/$(src)/$(GVT_DIR)/
+ccflags-y += -DDYNAMIC_DEBUG_MODULE
i915-y += $(addprefix $(GVT_DIR)/,
$(GVT_SOURCE))
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 7f139ea4a90b..ecc825558e00 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -260,3 +260,77 @@ void i915_params_free(struct i915_params *params)
I915_PARAMS_FOR_EACH(FREE);
#undef FREE
}
+
+/* POC for callback -> dynamic_debug_exec_queries */
+unsigned long __gvt_debug;
+EXPORT_SYMBOL(__gvt_debug);
+
+static char *format_prefix_classes[] = {
+ "gvt: cmd: ",
+ "gvt: core: ",
+ "gvt: dpy: ",
+ "gvt: el: ",
+ "gvt: irq: ",
+ "gvt: mm: ",
+ "gvt: mmio: ",
+ "gvt: render: ",
+ "gvt: sched: "
+};
+#define NUM_CLASSESARRAY_SIZE(format_prefix_classes)
+#define OUR_QUERY_SIZE 128 /* we need about 20 */
+
+#include
+
+static int param_set_dyndbg(const char *instr, const struct kernel_param *kp)
+{
+ unsigned int val;
+ unsigned long changes, result;
+ int rc, chgct = 0, totct = 0, bitpos;
+ char query[OUR_QUERY_SIZE];
+
+ rc = kstrtouint(instr, 0, &val);
+ if (rc) {
+ pr_err("set_dyndbg: failed\n");
+ return -EINVAL;
+ }
+ result = val;
+ pr_info("set_dyndbg: result:0x%lx from %s\n", result, instr);
+
+ changes = result ^ __gvt_debug;
+
+ for_each_set_bit(bitpos, &changes, NUM_CLASSES) {
+
+ sprintf(query, "format '^%s' %cp",
format_prefix_classes[bitpos],
+ test_bit(bitpos, &result) ? '+' : '-');
+
+ chgct = dynamic_debug_exec_queries(query, "i915");
+
+ pr_info("%d changes on: %s\n", chgct, query);
+ totct += chgct;
+ }
+ pr_info("total changes: %d\n", totct);
+ __gvt_debug = result;
+ return 0;
+}
+static int param_get_dyndbg(char *buffer, const struct kernel_param *kp)
+{
+ return scnprintf(buffer, PAGE_SIZE, "%u\n",
+*((unsigned int *)kp->arg));
+}
+static const struct kernel_param_ops param_ops_dyndbg = {
+ .set = param_set_dyndbg,
+ .get = param_get_dyndbg,
+};
+
+MODULE_PARM_DESC(debug_gvt, " gvt debug categories:"
+"\n\t0x1\t gvt: cmd:"
+"\n\t0x2\t gvt: core:"
+"\n\t0x4\t gvt: dpy:"
+"\n\t0x8\t gvt: el:"
+"\n\t0x10\t gvt: irq:"
+"\n\t0x20\t gvt: mm:"
+"\n\t0x40\t gvt: mmio:"
+"\n\t0x80\t gvt: render:"
+"\n\t0x100\t gvt: sched:" "\n");
+
+module_param_cb(debug_gvt, ¶m_ops_dyndbg, &__gvt_debug, 0644);
--
2.28.0
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[Intel-gfx] [PATCH 02/24] drm/i915/gt: Ignore repeated attempts to suspend request flow across reset
Before reseting the engine, we suspend the execution of the guilty
request, so that we can continue execution with a new context while we
slowly compress the captured error state for the guilty context. However,
if the reset fails, we will promptly attempt to reset the same request
again, and discover the ongoing capture. Ignore the second attempt to
suspend and capture the same request.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1168
Fixes: 32ff621fd744 ("drm/i915/gt: Allow temporary suspension of inflight
requests")
Signed-off-by: Chris Wilson
Cc: # v5.7+
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 43703efb36d1..1d209a8a95e8 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2823,6 +2823,9 @@ static void __execlists_hold(struct i915_request *rq)
static bool execlists_hold(struct intel_engine_cs *engine,
struct i915_request *rq)
{
+ if (i915_request_on_hold(rq))
+ return false;
+
spin_lock_irq(&engine->active.lock);
if (i915_request_completed(rq)) { /* too late! */
--
2.20.1
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[Intel-gfx] [PATCH 03/24] drm/i915/gt: Cancel the preemption timeout on responding to it
We currently presume that the engine reset is successful, cancelling the
expired preemption timer in the process. However, engine resets can
fail, leaving the timeout still pending and we will then respond to the
timeout again next time the tasklet fires. What we want is for the
failed engine reset to be promoted to a full device reset, which is
kicked by the heartbeat once the engine stops processing events.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1168
Fixes: 3a7a92aba8fb ("drm/i915/execlists: Force preemption")
Signed-off-by: Chris Wilson
Cc: # v5.5+
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 1d209a8a95e8..7f25894e41d5 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3209,8 +3209,10 @@ static void execlists_submission_tasklet(unsigned long
data)
spin_unlock_irqrestore(&engine->active.lock, flags);
/* Recheck after serialising with direct-submission */
- if (unlikely(timeout && preempt_timeout(engine)))
+ if (unlikely(timeout && preempt_timeout(engine))) {
+ cancel_timer(&engine->execlists.preempt);
execlists_reset(engine, "preemption time out");
+ }
}
}
--
2.20.1
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[Intel-gfx] [PATCH 16/24] drm/i915/gt: Track the overall awake/busy time
Since we wake the GT up before executing a request, and go to sleep as
soon as it is retired, the GT wake time not only represents how long the
device is powered up, but also provides a summary, albeit an overestimate,
of the device runtime (i.e. the rc0 time to compare against rc6 time).
v2: s/busy/awake/
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 5 ++-
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 49
drivers/gpu/drm/i915/gt/intel_gt_pm.h| 2 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 24
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++-
drivers/gpu/drm/i915/i915_pmu.c | 6 +++
include/uapi/drm/i915_drm.h | 1 +
7 files changed, 89 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index 174a24553322..8975717ace06 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -11,6 +11,7 @@
#include "i915_drv.h"
#include "intel_gt.h"
#include "intel_gt_clock_utils.h"
+#include "intel_gt_pm.h"
#include "intel_llc.h"
#include "intel_rc6.h"
#include "intel_rps.h"
@@ -558,7 +559,9 @@ static int rps_boost_show(struct seq_file *m, void *data)
seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps)));
seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps)));
- seq_printf(m, "GPU busy? %s\n", yesno(gt->awake));
+ seq_printf(m, "GPU busy? %s, %llums\n",
+ yesno(gt->awake),
+ ktime_to_ms(intel_gt_get_awake_time(gt)));
seq_printf(m, "Boosts outstanding? %d\n",
atomic_read(&rps->num_waiters));
seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 274aa0dd7050..c94e8ac884eb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -39,6 +39,28 @@ static void user_forcewake(struct intel_gt *gt, bool suspend)
intel_gt_pm_put(gt);
}
+static void runtime_begin(struct intel_gt *gt)
+{
+ local_irq_disable();
+ write_seqcount_begin(>->stats.lock);
+ gt->stats.start = ktime_get();
+ gt->stats.active = true;
+ write_seqcount_end(>->stats.lock);
+ local_irq_enable();
+}
+
+static void runtime_end(struct intel_gt *gt)
+{
+ local_irq_disable();
+ write_seqcount_begin(>->stats.lock);
+ gt->stats.active = false;
+ gt->stats.total =
+ ktime_add(gt->stats.total,
+ ktime_sub(ktime_get(), gt->stats.start));
+ write_seqcount_end(>->stats.lock);
+ local_irq_enable();
+}
+
static int __gt_unpark(struct intel_wakeref *wf)
{
struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref);
@@ -67,6 +89,7 @@ static int __gt_unpark(struct intel_wakeref *wf)
i915_pmu_gt_unparked(i915);
intel_gt_unpark_requests(gt);
+ runtime_begin(gt);
return 0;
}
@@ -79,6 +102,7 @@ static int __gt_park(struct intel_wakeref *wf)
GT_TRACE(gt, "\n");
+ runtime_end(gt);
intel_gt_park_requests(gt);
i915_vma_parked(gt);
@@ -106,6 +130,7 @@ static const struct intel_wakeref_ops wf_ops = {
void intel_gt_pm_init_early(struct intel_gt *gt)
{
intel_wakeref_init(>->wakeref, gt->uncore->rpm, &wf_ops);
+ seqcount_mutex_init(>->stats.lock, >->wakeref.mutex);
}
void intel_gt_pm_init(struct intel_gt *gt)
@@ -339,6 +364,30 @@ int intel_gt_runtime_resume(struct intel_gt *gt)
return intel_uc_runtime_resume(>->uc);
}
+static ktime_t __intel_gt_get_awake_time(const struct intel_gt *gt)
+{
+ ktime_t total = gt->stats.total;
+
+ if (gt->stats.active)
+ total = ktime_add(total,
+ ktime_sub(ktime_get(), gt->stats.start));
+
+ return total;
+}
+
+ktime_t intel_gt_get_awake_time(const struct intel_gt *gt)
+{
+ unsigned int seq;
+ ktime_t total;
+
+ do {
+ seq = read_seqcount_begin(>->stats.lock);
+ total = __intel_gt_get_awake_time(gt);
+ } while (read_seqcount_retry(>->stats.lock, seq));
+
+ return total;
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_gt_pm.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index 60f0e2fbe55c..63846a856e7e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -58,6 +58,8 @@ int intel_gt_resume(struct intel_gt *gt);
void intel_gt_runtime_suspend(struct intel_gt *gt);
int intel_gt_runtime_resume(struct intel_gt *gt);
+ktime_t intel_gt_get_awake_time(const struct intel_gt *gt);
+
static inline bool is_mock_gt(const struct intel_gt *gt)
{
return I915_SELFTEST_ONLY(gt->awake == -ENODEV);
diff
[Intel-gfx] [PATCH 05/24] drm/i915/gt: Clear the execlists timers upon reset
Across a reset, we stop the engine but not the timers. This leaves a window where the timers have inconsistent state with the engine, but should only result in a spurious timeout. As we cancel the outstanding events, also cancel their timers. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_lrc.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 7f25894e41d5..0c7f1e3dee5c 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2450,6 +2450,11 @@ cancel_port_requests(struct intel_engine_execlists * const execlists) smp_wmb(); /* complete the seqlock for execlists_active() */ WRITE_ONCE(execlists->active, execlists->inflight); + + /* Having cancelled all outstanding process_csb(), stop their timers */ + GEM_BUG_ON(execlists->pending[0]); + cancel_timer(&execlists->timer); + cancel_timer(&execlists->preempt); } static inline void -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 23/24] drm/i915/selftests: Exercise relative timeline modes
A quick test to verify that the backend accepts each type of timeline
and can use them to track and control request emission.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 93 +
1 file changed, 93 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c
b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index 6f355c8a4f81..0d7576953c6d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -1364,9 +1364,102 @@ static int live_hwsp_recycle(void *arg)
return err;
}
+static int live_hwsp_relative(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ /*
+* Check backend support for different timeline modes.
+*/
+
+ for_each_engine(engine, gt, id) {
+ enum intel_timeline_mode mode;
+
+ if (!engine->schedule)
+ continue;
+
+ for (mode = INTEL_TIMELINE_ABSOLUTE;
+mode <= INTEL_TIMELINE_GLOBAL;
+mode++) {
+ struct intel_timeline *tl;
+ struct i915_request *rq;
+ struct intel_context *ce;
+ const char *msg;
+ int err;
+
+ if (mode == INTEL_TIMELINE_CONTEXT &&
+ INTEL_GEN(gt->i915) < 8)
+ continue;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ err = intel_context_alloc_state(ce);
+ if (err) {
+ intel_context_put(ce);
+ return err;
+ }
+
+ switch (mode) {
+ case INTEL_TIMELINE_ABSOLUTE:
+ tl = intel_timeline_create(gt);
+ msg = "local";
+ break;
+
+ case INTEL_TIMELINE_CONTEXT:
+ tl = __intel_timeline_create(gt,
+ce->state,
+256 |
INTEL_TIMELINE_CONTEXT);
+ msg = "ppHWSP";
+ break;
+
+ case INTEL_TIMELINE_GLOBAL:
+ tl = __intel_timeline_create(gt,
+
engine->status_page.vma,
+256);
+ msg = "HWSP";
+ break;
+ }
+ if (IS_ERR(tl)) {
+ intel_context_put(ce);
+ return PTR_ERR(tl);
+ }
+
+ pr_info("Testing %s timeline on %s\n",
+ msg, engine->name);
+
+ intel_timeline_put(ce->timeline);
+ ce->timeline = tl;
+
+ rq = intel_context_create_request(ce);
+ intel_context_put(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ GEM_BUG_ON(rcu_access_pointer(rq->timeline) != tl);
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0) {
+ i915_request_put(rq);
+ return -EIO;
+ }
+
+ i915_request_put(rq);
+ }
+ }
+
+ return 0;
+}
+
int intel_timeline_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
+ SUBTEST(live_hwsp_relative),
SUBTEST(live_hwsp_recycle),
SUBTEST(live_hwsp_engine),
SUBTEST(live_hwsp_alternate),
--
2.20.1
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[Intel-gfx] [PATCH 13/24] drm/i915/gt: Simplify virtual engine handling for execlists_hold()
Now that the tasklet completely controls scheduling of the requests, and
we postpone scheduling out the old requests, we can keep a hanging
virtual request bound to the engine on which it hung, and remove it from
te queue. On release, it will be returned to the same engine and remain
in its queue until it is scheduled; after which point it will become
eligible for transfer to a sibling. Instead, we could opt to resubmit the
request along the virtual engine on unhold, making it eligible for load
balancing immediately -- but that seems like a pointless optimisation
for a hanging context.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 29 -
1 file changed, 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index efc8edd9e219..5f90ecacc22b 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2862,35 +2862,6 @@ static bool execlists_hold(struct intel_engine_cs
*engine,
goto unlock;
}
- if (rq->engine != engine) { /* preempted virtual engine */
- struct virtual_engine *ve = to_virtual_engine(rq->engine);
-
- /*
-* intel_context_inflight() is only protected by virtue
-* of process_csb() being called only by the tasklet (or
-* directly from inside reset while the tasklet is suspended).
-* Assert that neither of those are allowed to run while we
-* poke at the request queues.
-*/
- GEM_BUG_ON(!reset_in_progress(&engine->execlists));
-
- /*
-* An unsubmitted request along a virtual engine will
-* remain on the active (this) engine until we are able
-* to process the context switch away (and so mark the
-* context as no longer in flight). That cannot have happened
-* yet, otherwise we would not be hanging!
-*/
- spin_lock(&ve->base.active.lock);
- GEM_BUG_ON(intel_context_inflight(rq->context) != engine);
- GEM_BUG_ON(ve->request != rq);
- ve->request = NULL;
- spin_unlock(&ve->base.active.lock);
- i915_request_put(rq);
-
- rq->engine = engine;
- }
-
/*
* Transfer this request onto the hold queue to prevent it
* being resumbitted to HW (and potentially completed) before we have
--
2.20.1
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[Intel-gfx] [PATCH 07/24] drm/i915/gt: Use virtual_engine during execlists_dequeue
Rather than going back and forth between the rb_node entry and the
virtual_engine type, store the ve local and reuse it. As the
container_of conversion from rb_node to virtual_engine requires a
variable offset, performing that conversion just once shaves off a bit
of code.
v2: Keep a single virtual engine lookup, for typical use.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 239
1 file changed, 105 insertions(+), 134 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index c8c0493cb0b1..372b008364cf 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -454,9 +454,15 @@ static int queue_prio(const struct intel_engine_execlists
*execlists)
return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used);
}
+static int virtual_prio(const struct intel_engine_execlists *el)
+{
+ struct rb_node *rb = rb_first_cached(&el->virtual);
+
+ return rb ? rb_entry(rb, struct ve_node, rb)->prio : INT_MIN;
+}
+
static inline bool need_preempt(const struct intel_engine_cs *engine,
- const struct i915_request *rq,
- struct rb_node *rb)
+ const struct i915_request *rq)
{
int last_prio;
@@ -493,25 +499,6 @@ static inline bool need_preempt(const struct
intel_engine_cs *engine,
rq_prio(list_next_entry(rq, sched.link)) > last_prio)
return true;
- if (rb) {
- struct virtual_engine *ve =
- rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
- bool preempt = false;
-
- if (engine == ve->siblings[0]) { /* only preempt one sibling */
- struct i915_request *next;
-
- rcu_read_lock();
- next = READ_ONCE(ve->request);
- if (next)
- preempt = rq_prio(next) > last_prio;
- rcu_read_unlock();
- }
-
- if (preempt)
- return preempt;
- }
-
/*
* If the inflight context did not trigger the preemption, then maybe
* it was the set of queued requests? Pick the highest priority in
@@ -522,7 +509,8 @@ static inline bool need_preempt(const struct
intel_engine_cs *engine,
* ELSP[0] or ELSP[1] as, thanks again to PI, if it was the same
* context, it's priority would not exceed ELSP[0] aka last_prio.
*/
- return queue_prio(&engine->execlists) > last_prio;
+ return max(virtual_prio(&engine->execlists),
+ queue_prio(&engine->execlists)) > last_prio;
}
__maybe_unused static inline bool
@@ -1810,6 +1798,35 @@ static bool virtual_matches(const struct virtual_engine
*ve,
return true;
}
+static struct virtual_engine *
+first_virtual_engine(struct intel_engine_cs *engine)
+{
+ struct intel_engine_execlists *el = &engine->execlists;
+ struct rb_node *rb = rb_first_cached(&el->virtual);
+
+ while (rb) {
+ struct virtual_engine *ve =
+ rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
+ struct i915_request *rq = READ_ONCE(ve->request);
+
+ /* lazily cleanup after another engine handled rq */
+ if (!rq) {
+ rb_erase_cached(rb, &el->virtual);
+ RB_CLEAR_NODE(rb);
+ rb = rb_first_cached(&el->virtual);
+ continue;
+ }
+
+ if (!virtual_matches(ve, rq, engine)) {
+ rb = rb_next(rb);
+ continue;
+ }
+ return ve;
+ }
+
+ return NULL;
+}
+
static void virtual_xfer_context(struct virtual_engine *ve,
struct intel_engine_cs *engine)
{
@@ -1898,32 +1915,15 @@ static void defer_active(struct intel_engine_cs *engine)
static bool
need_timeslice(const struct intel_engine_cs *engine,
- const struct i915_request *rq,
- const struct rb_node *rb)
+ const struct i915_request *rq)
{
int hint;
if (!intel_engine_has_timeslices(engine))
return false;
- hint = engine->execlists.queue_priority_hint;
-
- if (rb) {
- const struct virtual_engine *ve =
- rb_entry(rb, typeof(*ve), nodes[engine->id].rb);
- const struct intel_engine_cs *inflight =
- intel_context_inflight(&ve->context);
-
- if (!inflight || inflight == engine) {
- struct i915_request *next;
-
- rcu_read_lock();
- next = READ_ONCE(ve->request);
- if (next)
-
[Intel-gfx] [PATCH 11/24] drm/i915/gt: Shrink the critical section for irq signaling
Let's only wait for the list iterator when decoupling the virtual
breadcrumb, as the signaling of all the requests may take a long time,
during which we do not want to keep the tasklet spinning.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 2 ++
drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 ++-
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index 63900edbde88..ac1e5f6c3c2c 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -239,6 +239,7 @@ static void signal_irq_work(struct irq_work *work)
intel_breadcrumbs_disarm_irq(b);
rcu_read_lock();
+ atomic_inc(&b->signaler_active);
list_for_each_entry_rcu(ce, &b->signalers, signal_link) {
struct i915_request *rq;
@@ -274,6 +275,7 @@ static void signal_irq_work(struct irq_work *work)
}
}
}
+ atomic_dec(&b->signaler_active);
rcu_read_unlock();
llist_for_each_safe(signal, sn, signal) {
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
index a74bb3062bd8..f672053d694d 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h
@@ -35,6 +35,7 @@ struct intel_breadcrumbs {
spinlock_t signalers_lock; /* protects the list of signalers */
struct list_head signalers;
struct llist_head signaled_requests;
+ atomic_t signaler_active;
spinlock_t irq_lock; /* protects the interrupt from hardirq context */
struct irq_work irq_work; /* for use from inside irq_lock */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b3db16b2a5a4..35cded25c6c1 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1401,7 +1401,8 @@ static void kick_siblings(struct i915_request *rq, struct
intel_context *ce)
* ce->signal_link.
*/
i915_request_cancel_breadcrumb(rq);
- irq_work_sync(&engine->breadcrumbs->irq_work);
+ while (atomic_read(&engine->breadcrumbs->signaler_active))
+ cpu_relax();
}
if (READ_ONCE(ve->request))
--
2.20.1
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