[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/8] drm/i915: refactor ddi translations into a separate file
== Series Details == Series: series starting with [1/8] drm/i915: refactor ddi translations into a separate file URL : https://patchwork.freedesktop.org/series/86110/ State : success == Summary == CI Bug Log - changes from CI_DRM_9650_full -> Patchwork_19436_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19436_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-mixed-process: - shard-hsw: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/shard-hsw4/igt@gem_ctx_persiste...@legacy-engines-mixed-process.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][2] -> [FAIL][3] ([i915#2842]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][4] ([i915#2842]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_render_copy@y-tiled-to-vebox-linear: - shard-hsw: NOTRUN -> [SKIP][5] ([fdo#109271]) +222 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/shard-hsw4/igt@gem_render_c...@y-tiled-to-vebox-linear.html * igt@gen3_mixed_blits: - shard-kbl: NOTRUN -> [SKIP][6] ([fdo#109271]) +10 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/shard-kbl7/igt@gen3_mixed_blits.html * igt@i915_pm_rps@reset: - shard-hsw: [PASS][7] -> [FAIL][8] ([i915#39]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-hsw6/igt@i915_pm_...@reset.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/shard-hsw4/igt@i915_pm_...@reset.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2597]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb2/igt@kms_async_fl...@test-time-stamp.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/shard-tglb1/igt@kms_async_fl...@test-time-stamp.html * igt@kms_chamelium@common-hpd-after-suspend: - shard-hsw: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +18 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/shard-hsw4/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-with-enabled-mode: - shard-kbl: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/shard-kbl7/igt@kms_chamel...@hdmi-hpd-with-enabled-mode.html * igt@kms_chamelium@vga-frame-dump: - shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/shard-snb6/igt@kms_chamel...@vga-frame-dump.html * igt@kms_color_chamelium@pipe-a-ctm-green-to-red: - shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/shard-glk5/igt@kms_color_chamel...@pipe-a-ctm-green-to-red.html * igt@kms_color_chamelium@pipe-d-ctm-green-to-red: - shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/shard-skl10/igt@kms_color_chamel...@pipe-d-ctm-green-to-red.html * igt@kms_cursor_crc@pipe-c-cursor-64x21-random: - shard-skl: [PASS][16] -> [FAIL][17] ([i915#54]) +4 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl6/igt@kms_cursor_...@pipe-c-cursor-64x21-random.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/shard-skl5/igt@kms_cursor_...@pipe-c-cursor-64x21-random.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: NOTRUN -> [DMESG-WARN][18] ([i915#180]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/shard-kbl7/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][19] -> [FAIL][20] ([i915#96]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-hsw7/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/shard-hsw8/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2598]) [21]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dp: Fix a logical vs bitwise OR bug
== Series Details == Series: drm/i915/dp: Fix a logical vs bitwise OR bug URL : https://patchwork.freedesktop.org/series/86114/ State : failure == Summary == Applying: drm/i915/dp: Fix a logical vs bitwise OR bug Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_dp.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_dp.c No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/dp: Fix a logical vs bitwise OR bug
This was supposed to be | instead of ||.
Fixes: 522508b665df ("drm/i915/display: Let PCON convert from RGB to YCbCr if
it can")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 8a00e609085f..9c6f427b2703 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6955,8 +6955,8 @@ intel_dp_update_420(struct intel_dp *intel_dp)
intel_dp->downstream_ports);
rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
intel_dp->downstream_ports,
-
DP_DS_HDMI_BT601_RGB_YCBCR_CONV ||
-
DP_DS_HDMI_BT709_RGB_YCBCR_CONV ||
+
DP_DS_HDMI_BT601_RGB_YCBCR_CONV |
+
DP_DS_HDMI_BT709_RGB_YCBCR_CONV |
DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
if (INTEL_GEN(i915) >= 11) {
--
2.29.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/8] drm/i915: refactor ddi translations into a separate file
== Series Details ==
Series: series starting with [1/8] drm/i915: refactor ddi translations into a
separate file
URL : https://patchwork.freedesktop.org/series/86110/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19436
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/index.html
Known issues
Here are the changes found in Patchwork_19436 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/fi-snb-2520m/igt@amdgpu/amd_pr...@i915-to-amd.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#2411] /
[i915#402])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271]) +30 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html
* igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y: [PASS][6] -> [DMESG-WARN][7] ([i915#402]) +1 similar
issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-snb-2600:[DMESG-WARN][8] ([i915#2772]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2520m: [INCOMPLETE][10] -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][12] ([i915#402]) -> [PASS][13] +1
similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9650 -> Patchwork_19436
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19436: 26c4525e26a4289c6b6846cd8c02c5c28cccd5a1 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
26c4525e26a4 drm/i915: migrate i9xx plane get config
28a3e3bd2878 drm/i915: migrate pll enable/disable code to intel_dpll.[ch]
6de2a1874b9d drm/i915: move is_ccs_modifier to an inline
ceac7e29dced drm/i915: split fb scalable checks into g4x and skl versions
1f21c6b8bcc4 drm/i915: move pipe update code into crtc.
630ae9723fa6 drm/i915: migrate skl planes code new file (v4)
4208556348c8 drm/i915: migrate hsw fdi code to new file.
8977ebfa68d5 drm/i915: refactor ddi translations into a separate file
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19436/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/8] drm/i915: refactor ddi translations into a separate file
== Series Details == Series: series starting with [1/8] drm/i915: refactor ddi translations into a separate file URL : https://patchwork.freedesktop.org/series/86110/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:714:28: warning: symbol 'bdw_get_buf_trans_edp' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:728:28: warning: symbol 'skl_get_buf_trans_dp' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:745:28: warning: symbol 'kbl_get_buf_trans_dp' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:766:28: warning: symbol 'skl_get_buf_trans_edp' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:798:28: warning: symbol 'skl_get_buf_trans_hdmi' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:813:5: warning: symbol 'skl_buf_trans_num_entries' was not declared. Should it be static? +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1328:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/8] drm/i915: refactor ddi translations into a separate file
== Series Details ==
Series: series starting with [1/8] drm/i915: refactor ddi translations into a
separate file
URL : https://patchwork.freedesktop.org/series/86110/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8977ebfa68d5 drm/i915: refactor ddi translations into a separate file
-:1523: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#1523:
new file mode 100644
-:1791: CHECK:LINE_SPACING: Please don't use multiple blank lines
#1791: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:264:
+
+
-:2249: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2249: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:722:
+ return bdw_ddi_translations_edp;
+ } else {
-:2266: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2266: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:739:
+ return skl_u_ddi_translations_dp;
+ } else {
-:2287: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2287: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:760:
+ return kbl_u_ddi_translations_dp;
+ } else {
-:2311: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2311: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:784:
+ return skl_u_ddi_translations_edp;
+ } else {
-:2334: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2334: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:807:
+ return skl_y_ddi_translations_hdmi;
+ } else {
-:2489: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2489: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:962:
+ return cnl_ddi_translations_hdmi_1_05V;
+ } else {
-:2511: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2511: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:984:
+ return cnl_ddi_translations_dp_1_05V;
+ } else {
-:2534: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2534: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1007:
+ return cnl_ddi_translations_edp_1_05V;
+ } else {
-:2628: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2628: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1101:
+ return icl_mg_phy_ddi_translations_hbr2_hbr3;
+ } else {
-:2720: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2720: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1193:
+ return jsl_combo_phy_ddi_translations_edp_hbr2;
+ } else {
-:2762: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2762: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1235:
+ return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
+ } else {
-:2824: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2824: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1297:
+ return tgl_dkl_phy_dp_ddi_trans_hbr2;
+ } else {
total: 0 errors, 13 warnings, 1 checks, 2944 lines checked
4208556348c8 drm/i915: migrate hsw fdi code to new file.
-:293: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#293: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:583:
+ FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) |
FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
-:301: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see
Documentation/timers/timers-howto.rst
#301: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:591:
+ udelay(220);
-:313: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a
separate line
#313: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:603:
+* testing each value twice. */
-:325: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a
separate line
#325: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:615:
+* port reversal bit */
-:327: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#327: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:617:
+ DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes -
1) << 1) | DDI_BUF_TRANS_SELECT(i / 2));
-:330: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see
Documentation/timers/timers-howto.rst
#330: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:620:
+ udelay(600);
-:341: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see
Documentation/timers/timers-howto.rst
#341: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:631:
+ udelay(30);
total: 0 errors, 4
[Intel-gfx] [PATCH 7/8] drm/i915: migrate pll enable/disable code to intel_dpll.[ch]
From: Dave Airlie
This moves the older i9xx/vlv/chv enable/disable to dpll file.
Signed-off-by: Dave Airlie
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 512 ---
drivers/gpu/drm/i915/display/intel_display.h | 3 -
drivers/gpu/drm/i915/display/intel_dp.c | 1 +
drivers/gpu/drm/i915/display/intel_dpll.c| 509 ++
drivers/gpu/drm/i915/display/intel_dpll.h| 18 +
drivers/gpu/drm/i915/display/intel_pps.c | 1 +
6 files changed, 529 insertions(+), 515 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 56ca70228886..7a84e19bc8c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -109,10 +109,6 @@ static void i9xx_set_pipeconf(const struct
intel_crtc_state *crtc_state);
static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
-static void vlv_prepare_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config);
-static void chv_prepare_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config);
static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
static void intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx);
@@ -565,224 +561,6 @@ static void assert_pch_ports_disabled(struct
drm_i915_private *dev_priv,
assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
}
-static void _vlv_enable_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
-
- intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
- intel_de_posting_read(dev_priv, DPLL(pipe));
- udelay(150);
-
- if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
- drm_err(_priv->drm, "DPLL %d failed to lock\n", pipe);
-}
-
-static void vlv_enable_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
-
- assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
-
- /* PLL is protected by panel, make sure we can write it */
- assert_panel_unlocked(dev_priv, pipe);
-
- if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
- _vlv_enable_pll(crtc, pipe_config);
-
- intel_de_write(dev_priv, DPLL_MD(pipe),
- pipe_config->dpll_hw_state.dpll_md);
- intel_de_posting_read(dev_priv, DPLL_MD(pipe));
-}
-
-
-static void _chv_enable_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
- enum dpio_channel port = vlv_pipe_to_channel(pipe);
- u32 tmp;
-
- vlv_dpio_get(dev_priv);
-
- /* Enable back the 10bit clock to display controller */
- tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
- tmp |= DPIO_DCLKP_EN;
- vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
-
- vlv_dpio_put(dev_priv);
-
- /*
-* Need to wait > 100ns between dclkp clock enable bit and PLL enable.
-*/
- udelay(1);
-
- /* Enable PLL */
- intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
-
- /* Check PLL is locked */
- if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
- drm_err(_priv->drm, "PLL %d failed to lock\n", pipe);
-}
-
-static void chv_enable_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
-
- assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
-
- /* PLL is protected by panel, make sure we can write it */
- assert_panel_unlocked(dev_priv, pipe);
-
- if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
- _chv_enable_pll(crtc, pipe_config);
-
- if (pipe != PIPE_A) {
- /*
-* WaPixelRepeatModeFixForC0:chv
-*
-* DPLLCMD is AWOL. Use chicken bits to propagate
-* the value from DPLLBMD to either pipe B or C.
-*/
- intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
- intel_de_write(dev_priv, DPLL_MD(PIPE_B),
-
[Intel-gfx] [PATCH 8/8] drm/i915: migrate i9xx plane get config
From: Dave Airlie
Migrate this code out like the skylake code.
Signed-off-by: Dave Airlie
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c| 119 +++
drivers/gpu/drm/i915/display/i9xx_plane.h| 4 +
drivers/gpu/drm/i915/display/intel_display.c | 119 ---
3 files changed, 123 insertions(+), 119 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 6c568079f492..a063a92f04dc 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -698,3 +698,122 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
return ERR_PTR(ret);
}
+static int i9xx_format_to_fourcc(int format)
+{
+ switch (format) {
+ case DISPPLANE_8BPP:
+ return DRM_FORMAT_C8;
+ case DISPPLANE_BGRA555:
+ return DRM_FORMAT_ARGB1555;
+ case DISPPLANE_BGRX555:
+ return DRM_FORMAT_XRGB1555;
+ case DISPPLANE_BGRX565:
+ return DRM_FORMAT_RGB565;
+ default:
+ case DISPPLANE_BGRX888:
+ return DRM_FORMAT_XRGB;
+ case DISPPLANE_RGBX888:
+ return DRM_FORMAT_XBGR;
+ case DISPPLANE_BGRA888:
+ return DRM_FORMAT_ARGB;
+ case DISPPLANE_RGBA888:
+ return DRM_FORMAT_ABGR;
+ case DISPPLANE_BGRX101010:
+ return DRM_FORMAT_XRGB2101010;
+ case DISPPLANE_RGBX101010:
+ return DRM_FORMAT_XBGR2101010;
+ case DISPPLANE_BGRA101010:
+ return DRM_FORMAT_ARGB2101010;
+ case DISPPLANE_RGBA101010:
+ return DRM_FORMAT_ABGR2101010;
+ case DISPPLANE_RGBX161616:
+ return DRM_FORMAT_XBGR16161616F;
+ }
+}
+
+void
+i9xx_get_initial_plane_config(struct intel_crtc *crtc,
+ struct intel_initial_plane_config *plane_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+ enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
+ enum pipe pipe;
+ u32 val, base, offset;
+ int fourcc, pixel_format;
+ unsigned int aligned_height;
+ struct drm_framebuffer *fb;
+ struct intel_framebuffer *intel_fb;
+
+ if (!plane->get_hw_state(plane, ))
+ return;
+
+ drm_WARN_ON(dev, pipe != crtc->pipe);
+
+ intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
+ if (!intel_fb) {
+ drm_dbg_kms(_priv->drm, "failed to alloc fb\n");
+ return;
+ }
+
+ fb = _fb->base;
+
+ fb->dev = dev;
+
+ val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
+
+ if (INTEL_GEN(dev_priv) >= 4) {
+ if (val & DISPPLANE_TILED) {
+ plane_config->tiling = I915_TILING_X;
+ fb->modifier = I915_FORMAT_MOD_X_TILED;
+ }
+
+ if (val & DISPPLANE_ROTATE_180)
+ plane_config->rotation = DRM_MODE_ROTATE_180;
+ }
+
+ if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
+ val & DISPPLANE_MIRROR)
+ plane_config->rotation |= DRM_MODE_REFLECT_X;
+
+ pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
+ fourcc = i9xx_format_to_fourcc(pixel_format);
+ fb->format = drm_format_info(fourcc);
+
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+ offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
+ base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) &
0xf000;
+ } else if (INTEL_GEN(dev_priv) >= 4) {
+ if (plane_config->tiling)
+ offset = intel_de_read(dev_priv,
+ DSPTILEOFF(i9xx_plane));
+ else
+ offset = intel_de_read(dev_priv,
+ DSPLINOFF(i9xx_plane));
+ base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) &
0xf000;
+ } else {
+ base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
+ }
+ plane_config->base = base;
+
+ val = intel_de_read(dev_priv, PIPESRC(pipe));
+ fb->width = ((val >> 16) & 0xfff) + 1;
+ fb->height = ((val >> 0) & 0xfff) + 1;
+
+ val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
+ fb->pitches[0] = val & 0xffc0;
+
+ aligned_height = intel_fb_align_height(fb, 0, fb->height);
+
+ plane_config->size = fb->pitches[0] * aligned_height;
+
+ drm_dbg_kms(_priv->drm,
+ "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size
0x%x\n",
+ crtc->base.name, plane->base.name, fb->width, fb->height,
+ fb->format->cpp[0] * 8, base,
[Intel-gfx] [PATCH 6/8] drm/i915: move is_ccs_modifier to an inline
From: Dave Airlie
There is no need for this to be out of line.
Reviewed-by: Ville Syrjälä
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 8
drivers/gpu/drm/i915/display/intel_display.h | 1 -
drivers/gpu/drm/i915/display/intel_display_types.h | 8
3 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 6d2978179ac0..56ca70228886 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1791,14 +1791,6 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
}
}
-bool is_ccs_modifier(u64 modifier)
-{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
- modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
-}
-
static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
{
return DIV_ROUND_UP(fb->pitches[skl_ccs_to_main_plane(fb, ccs_plane)],
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 0b2fed58badf..f4214e161a9d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -508,7 +508,6 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n, bool fec_enable);
-bool is_ccs_modifier(u64 modifier);
void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 58cec59fd4f7..ed06e7e6a634 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1876,6 +1876,14 @@ static inline u32 intel_fdi_link_freq(struct
drm_i915_private *dev_priv,
return dev_priv->fdi_pll_freq;
}
+static inline bool is_ccs_modifier(u64 modifier)
+{
+ return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+ modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+}
+
static inline bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
{
if (!is_ccs_modifier(fb->modifier))
--
2.27.0
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[Intel-gfx] [PATCH 4/8] drm/i915: move pipe update code into crtc.
From: Dave Airlie
Daniel suggested this should move here.
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crtc.c | 230
drivers/gpu/drm/i915/display/intel_sprite.c | 228 ---
2 files changed, 230 insertions(+), 228 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index eb478712c381..8825f960a121 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -10,6 +10,9 @@
#include
#include
+#include "i915_trace.h"
+#include "i915_vgpu.h"
+
#include "intel_atomic.h"
#include "intel_atomic_plane.h"
#include "intel_color.h"
@@ -17,7 +20,9 @@
#include "intel_cursor.h"
#include "intel_display_debugfs.h"
#include "intel_display_types.h"
+#include "intel_dsi.h"
#include "intel_pipe_crc.h"
+#include "intel_psr.h"
#include "intel_sprite.h"
#include "i9xx_plane.h"
#include "skl_universal_plane.h"
@@ -332,3 +337,228 @@ int intel_crtc_init(struct drm_i915_private *dev_priv,
enum pipe pipe)
return ret;
}
+
+int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
+int usecs)
+{
+ /* paranoia */
+ if (!adjusted_mode->crtc_htotal)
+ return 1;
+
+ return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
+ 1000 * adjusted_mode->crtc_htotal);
+}
+
+/**
+ * intel_pipe_update_start() - start update of a set of display registers
+ * @new_crtc_state: the new crtc state
+ *
+ * Mark the start of an update to pipe registers that should be updated
+ * atomically regarding vblank. If the next vblank will happens within
+ * the next 100 us, this function waits until the vblank passes.
+ *
+ * After a successful call to this function, interrupts will be disabled
+ * until a subsequent call to intel_pipe_update_end(). That is done to
+ * avoid random delays.
+ */
+void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_display_mode *adjusted_mode =
_crtc_state->hw.adjusted_mode;
+ long timeout = msecs_to_jiffies_timeout(1);
+ int scanline, min, max, vblank_start;
+ wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(>base);
+ bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) ||
IS_CHERRYVIEW(dev_priv)) &&
+ intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
+ DEFINE_WAIT(wait);
+ u32 psr_status;
+
+ if (new_crtc_state->uapi.async_flip)
+ return;
+
+ vblank_start = adjusted_mode->crtc_vblank_start;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
+ vblank_start = DIV_ROUND_UP(vblank_start, 2);
+
+ /* FIXME needs to be calibrated sensibly */
+ min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
+ VBLANK_EVASION_TIME_US);
+ max = vblank_start - 1;
+
+ if (min <= 0 || max <= 0)
+ goto irq_disable;
+
+ if (drm_WARN_ON(_priv->drm, drm_crtc_vblank_get(>base)))
+ goto irq_disable;
+
+ /*
+* Wait for psr to idle out after enabling the VBL interrupts
+* VBL interrupts will start the PSR exit and prevent a PSR
+* re-entry as well.
+*/
+ if (intel_psr_wait_for_idle(new_crtc_state, _status))
+ drm_err(_priv->drm,
+ "PSR idle timed out 0x%x, atomic update may fail\n",
+ psr_status);
+
+ local_irq_disable();
+
+ crtc->debug.min_vbl = min;
+ crtc->debug.max_vbl = max;
+ trace_intel_pipe_update_start(crtc);
+
+ for (;;) {
+ /*
+* prepare_to_wait() has a memory barrier, which guarantees
+* other CPUs can see the task state update by the time we
+* read the scanline.
+*/
+ prepare_to_wait(wq, , TASK_UNINTERRUPTIBLE);
+
+ scanline = intel_get_crtc_scanline(crtc);
+ if (scanline < min || scanline > max)
+ break;
+
+ if (!timeout) {
+ drm_err(_priv->drm,
+ "Potential atomic update failure on pipe %c\n",
+ pipe_name(crtc->pipe));
+ break;
+ }
+
+ local_irq_enable();
+
+ timeout = schedule_timeout(timeout);
+
+ local_irq_disable();
+ }
+
+ finish_wait(wq, );
+
+ drm_crtc_vblank_put(>base);
+
+ /*
+* On VLV/CHV DSI the scanline counter would appear to
+* increment approx. 1/3 of a scanline before start of vblank.
+*
[Intel-gfx] [PATCH 5/8] drm/i915: split fb scalable checks into g4x and skl versions
From: Dave Airlie
This just cleans these up a bit.
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c| 7 +++
drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 7d779402cef7..9995bf6c39b9 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1345,19 +1345,18 @@ g4x_plane_get_hw_state(struct intel_plane *plane,
return ret;
}
-static bool intel_fb_scalable(const struct drm_framebuffer *fb)
+static bool g4x_fb_scalable(const struct drm_framebuffer *fb)
{
if (!fb)
return false;
switch (fb->format->format) {
case DRM_FORMAT_C8:
- return false;
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
case DRM_FORMAT_XBGR16161616F:
case DRM_FORMAT_ABGR16161616F:
- return INTEL_GEN(to_i915(fb->dev)) >= 11;
+ return false;
default:
return true;
}
@@ -1434,7 +1433,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
int max_scale = DRM_PLANE_HELPER_NO_SCALING;
int ret;
- if (intel_fb_scalable(plane_state->hw.fb)) {
+ if (g4x_fb_scalable(plane_state->hw.fb)) {
if (INTEL_GEN(dev_priv) < 7) {
min_scale = 1;
max_scale = 16 << 16;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 98d31bdc93ba..493bff4d8982 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1646,7 +1646,7 @@ static int skl_check_plane_surface(struct
intel_plane_state *plane_state)
return 0;
}
-static bool intel_fb_scalable(const struct drm_framebuffer *fb)
+static bool skl_fb_scalable(const struct drm_framebuffer *fb)
{
if (!fb)
return false;
@@ -1679,7 +1679,7 @@ static int skl_plane_check(struct intel_crtc_state
*crtc_state,
return ret;
/* use scaler when colorkey is not required */
- if (!plane_state->ckey.flags && intel_fb_scalable(fb)) {
+ if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
min_scale = 1;
max_scale = skl_plane_max_scale(dev_priv, fb);
}
--
2.27.0
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[Intel-gfx] [PATCH 2/8] drm/i915: migrate hsw fdi code to new file.
From: Dave Airlie
Daniel asked for this, but it's a bit messy and I'm not sure
how best to clean it up yet.
Signed-off-by: Dave Airlie
[Jani: also moved fdi buf trans to intel_fdi.c.]
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_crt.c | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 151 ++-
drivers/gpu/drm/i915/display/intel_ddi.h | 8 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 139 +
drivers/gpu/drm/i915/display/intel_fdi.h | 3 +
5 files changed, 156 insertions(+), 146 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index 4934edd51cb0..077ebc7e6396 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -38,6 +38,7 @@
#include "intel_crt.h"
#include "intel_ddi.h"
#include "intel_display_types.h"
+#include "intel_fdi.h"
#include "intel_fifo_underrun.h"
#include "intel_gmbus.h"
#include "intel_hotplug.h"
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6ccf2e75b58b..5bed6fa1ff57 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -36,10 +36,11 @@
#include "intel_ddi_buf_trans.h"
#include "intel_display_types.h"
#include "intel_dp.h"
-#include "intel_dp_mst.h"
#include "intel_dp_link_training.h"
+#include "intel_dp_mst.h"
#include "intel_dpio_phy.h"
#include "intel_dsi.h"
+#include "intel_fdi.h"
#include "intel_fifo_underrun.h"
#include "intel_gmbus.h"
#include "intel_hdcp.h"
@@ -90,8 +91,8 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
* values in advance. This function programs the correct values for
* DP/eDP/FDI use cases.
*/
-static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
-const struct intel_crtc_state
*crtc_state)
+void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 iboost_bit = 0;
@@ -153,8 +154,8 @@ static void intel_prepare_hdmi_ddi_buffers(struct
intel_encoder *encoder,
ddi_translations[level].trans2);
}
-static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
- enum port port)
+void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
+enum port port)
{
if (IS_BROXTON(dev_priv)) {
udelay(16);
@@ -182,7 +183,7 @@ static void intel_wait_ddi_buf_active(struct
drm_i915_private *dev_priv,
port_name(port));
}
-static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
+u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
{
switch (pll->info->id) {
case DPLL_ID_WRPLL1:
@@ -242,144 +243,6 @@ static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder
*encoder,
}
}
-/* Starting with Haswell, different DDI ports can work in FDI mode for
- * connection to the PCH-located connectors. For this, it is necessary to train
- * both the DDI port and PCH receiver for the desired DDI buffer settings.
- *
- * The recommended port to work in FDI mode is DDI E, which we use here. Also,
- * please note that when FDI mode is active on DDI E, it shares 2 lines with
- * DDI A (which is used for eDP)
- */
-
-void hsw_fdi_link_train(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 temp, i, rx_ctl_val, ddi_pll_sel;
- int n_entries;
-
- intel_ddi_get_buf_trans_fdi(dev_priv, _entries);
-
- intel_prepare_dp_ddi_buffers(encoder, crtc_state);
-
- /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
-* mode set "sequence for CRT port" document:
-* - TP1 to TP2 time with the default value
-* - FDI delay to 90h
-*
-* WaFDIAutoLinkSetTimingOverrride:hsw
-*/
- intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
- FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) |
FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
-
- /* Enable the PCH Receiver FDI PLL */
- rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
-FDI_RX_PLL_ENABLE |
-FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
- intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
- intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
- udelay(220);
-
- /* Switch from Rawclk to PCDclk */
- rx_ctl_val |= FDI_PCDCLK;
- intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A),
[Intel-gfx] [rfc v8] remaining intel_display.c refactors
This rebases, fixes up the headers (thanks Jani, for pointing that out), and adds missing tags and review tags. I think only patch 3 is missing an r-b, I've fixed the header issues he pointed out. Dave. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] gvt-gt-next
On 2021.01.20 14:21:53 +0200, Joonas Lahtinen wrote: > Quoting Zhenyu Wang (2021-01-18 07:07:39) > > > > Hi, > > > > This is GVT next for 5.12 against drm-intel-gt-next which is mostly > > for cmd parser enhancement which adds extra check on register load > > depending on initial context and handles vGPU register state > > accordingly. > > I think we were bit inconclusive on this last time. > Sorry about that, I was thinking we might just follow your previous idea. > Even if this does not have any dependency to drm-intel-gt-next I can > pull this to drm-intel-gt-next. The only caveat is that for any -fixes, > there needs to be a backmerge to drm-intel-next. > > Not sure if this is a problem. Do we want to make it a recurring practice > to backmerge drm-intel-gt-next into drm-intel-next after it lands in > drm-next? > So -gt-next won't do -gt-next-fixes, right? For -next-fixes, we always do drm-next backmerge, right? > So to recap: Do we want to pull to drm-intel-next whenever there are no > dependencies to drm-intel-gt-next, to avoid a backmerge? yeah, that's fine to me. But for this time gvt-next pull, it's really targeting for -gt-next which has some dependency, I can double check to confirm. Thanks. > Or do we want > to always do a backmerge in anticipation of -fixes. > > Regards, Joonas > > > Thanks. > > -- > > The following changes since commit fe7bcfaeb2b775f257348dc7b935f8e80eef3e7d: > > > > drm/i915/gt: Refactor heartbeat request construction and submission > > (2020-12-24 18:07:26 +) > > > > are available in the Git repository at: > > > > https://github.com/intel/gvt-linux tags/gvt-gt-next-2021-01-18 > > > > for you to fetch changes up to 02dd2b12a685944c4d52c569d05f636372a7b6c7: > > > > drm/i915/gvt: unify lri cmd handler and mmio handlers (2020-12-25 > > 11:16:32 +0800) > > > > > > gvt-gt-next-2021-01-18 > > > > - GVT cmd parser enhancement against guest context (Yan) > > > > > > Yan Zhao (11): > > drm/i915/gvt: parse init context to update cmd accessible reg > > whitelist > > drm/i915/gvt: scan VM ctx pages > > drm/i915/gvt: filter cmds "srm" and "lrm" in cmd_handler > > drm/i915/gvt: filter cmds "lrr-src" and "lrr-dst" in cmd_handler > > drm/i915/gvt: filter cmd "pipe-ctrl" in cmd_handler > > drm/i915/gvt: export find_mmio_info > > drm/i915/gvt: make width of mmio_attribute bigger > > drm/i915/gvt: introduce a new flag F_CMD_WRITE_PATCH > > drm/i915/gvt: statically set F_CMD_WRITE_PATCH flag > > drm/i915/gvt: update F_CMD_WRITE_PATCH flag when parsing init ctx > > drm/i915/gvt: unify lri cmd handler and mmio handlers > > > > drivers/gpu/drm/i915/gvt/cmd_parser.c | 335 > > +++--- > > drivers/gpu/drm/i915/gvt/cmd_parser.h | 4 + > > drivers/gpu/drm/i915/gvt/gvt.h| 37 +++- > > drivers/gpu/drm/i915/gvt/handlers.c | 15 +- > > drivers/gpu/drm/i915/gvt/mmio.h | 3 + > > drivers/gpu/drm/i915/gvt/reg.h| 2 + > > drivers/gpu/drm/i915/gvt/scheduler.c | 22 ++- > > drivers/gpu/drm/i915/gvt/vgpu.c | 4 +- > > 8 files changed, 339 insertions(+), 83 deletions(-) signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Move execlists_reset() out of line
== Series Details == Series: drm/i915/gt: Move execlists_reset() out of line URL : https://patchwork.freedesktop.org/series/86106/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9650_full -> Patchwork_19435_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19435_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19435_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19435_full: ### IGT changes ### Possible regressions * igt@i915_pm_rps@reset: - shard-snb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-snb5/igt@i915_pm_...@reset.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/shard-snb2/igt@i915_pm_...@reset.html * igt@sysfs_timeslice_duration@timeout@vcs0: - shard-skl: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/shard-skl7/igt@sysfs_timeslice_duration@time...@vcs0.html Known issues Here are the changes found in Patchwork_19435_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@close-replace-race: - shard-glk: [PASS][4] -> [TIMEOUT][5] ([i915#2918]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk6/igt@gem_ctx_persiste...@close-replace-race.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/shard-glk4/igt@gem_ctx_persiste...@close-replace-race.html * igt@gem_ctx_persistence@engines-mixed: - shard-hsw: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/shard-hsw8/igt@gem_ctx_persiste...@engines-mixed.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb8/igt@gem_exec_fair@basic-p...@vecs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/shard-tglb6/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][13] ([i915#2389]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/shard-iclb1/igt@gem_exec_reloc@basic-wide-act...@vcs1.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-apl: [PASS][14] -> [DMESG-WARN][15] ([i915#1610]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-apl2/igt@gem_exec_schedule@u-fairsl...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/shard-apl8/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][16] -> [SKIP][17] ([i915#2190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb8/igt@gem_huc_c...@huc-copy.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@gem_render_copy@y-tiled-to-vebox-linear: - shard-hsw: NOTRUN -> [SKIP][18] ([fdo#109271]) +114 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/shard-hsw8/igt@gem_render_c...@y-tiled-to-vebox-linear.html * igt@gen3_mixed_blits: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271]) +29 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/shard-kbl1/igt@gen3_mixed_blits.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#658]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/shard-kbl1/igt@i915_pm...@dc3co-vpb-simulation.html * igt@i915_selftest@live@hangcheck: - shard-hsw: NOTRUN -> [INCOMPLETE][21] ([i915#2782]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/shard-hsw4/igt@i915_selftest@l...@hangcheck.html *
Re: [Intel-gfx] [PATCH 06/11] drm/i915: migrate skl planes code new file (v3)
On Fri, 15 Jan 2021 at 01:57, Ville Syrjälä
wrote:
>
> On Thu, Jan 14, 2021 at 01:13:50PM +0200, Jani Nikula wrote:
> > From: Dave Airlie
> >
> > Rework the plane init calls to do the gen test one level higher.
> >
> > Rework some of the plane helpers so they can live in new file,
> > there is still some scope to clean up the plane/fb interactions
> > later.
> >
> > v2: drop atomic code back, rename file to Ville suggestions,
> > add header file.
> > v3: move scaler bits back
> >
> > Signed-off-by: Dave Airlie
> > [Jani: fixed up sparse warnings.]
> > Signed-off-by: Jani Nikula
> > Reported-by: kernel test robot
> > Reported-by: Dan Carpenter
> > ---
>
> > -unsigned int
> > -intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
> > -{
> > - int x = 0, y = 0;
> > -
> > - intel_plane_adjust_aligned_offset(, , plane_state, 0,
> > - plane_state->color_plane[0].offset,
> > 0);
> > -
> > - return y;
> > -}
>
> This getting moved around is messing up the diff.
>
>
> > @@ -4386,15 +3633,6 @@ static int skl_update_scaler_plane(struct
> > intel_crtc_state *crtc_state,
> > return 0;
> > }
> >
> > -void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
> > -{
> > - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> > - int i;
> > -
> > - for (i = 0; i < crtc->num_scalers; i++)
> > - skl_detach_scaler(crtc, i);
> > -}
>
> Same here.
Wierd not sure how to generate it better.
>
>
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index f76e2c2a83b8..8e4b6647752f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -39,6 +39,7 @@
> > #include "intel_dp_mst.h"
> > #include "intel_dpio_phy.h"
> > #include "intel_hdcp.h"
> > +#include "skl_universal_plane.h"
>
> Why is this here?
Not sure, probably left over from moving scaler, dropped it now.
>
> >
> > static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> > struct intel_crtc_state
> > *crtc_state,
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index c24ae69426cf..0d0b0d3c52a1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -31,6 +31,7 @@
> > #include "intel_psr.h"
> > #include "intel_sprite.h"
> > #include "intel_hdmi.h"
> > +#include "skl_universal_plane.h"
>
> Is this due to the psr damage stuff?
intel_psr2_program_plane_sel_fetch calls skl_calc_main_surface_offset
>
>
> > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
> > b/drivers/gpu/drm/i915/display/vlv_dsi.c
> > index f94025ec603a..ebf266457518 100644
> > --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> > @@ -38,6 +38,7 @@
> > #include "intel_fifo_underrun.h"
> > #include "intel_panel.h"
> > #include "intel_sideband.h"
> > +#include "skl_universal_plane.h"
>
> Why do we need this here?
>
Oops as well, dropped it.
Dave.
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Call stop_ring() from ring resume, again
== Series Details == Series: drm/i915/gt: Call stop_ring() from ring resume, again URL : https://patchwork.freedesktop.org/series/86103/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9650_full -> Patchwork_19434_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19434_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19434_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19434_full: ### IGT changes ### Possible regressions * igt@kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb6/igt@kms_plane_alpha_bl...@pipe-b-alpha-basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/shard-tglb6/igt@kms_plane_alpha_bl...@pipe-b-alpha-basic.html Known issues Here are the changes found in Patchwork_19434_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_param@root-set-no-zeromap-enabled: - shard-skl: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl3/igt@gem_ctx_pa...@root-set-no-zeromap-enabled.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/shard-skl2/igt@gem_ctx_pa...@root-set-no-zeromap-enabled.html * igt@gem_ctx_persistence@engines-mixed: - shard-hsw: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/shard-hsw8/igt@gem_ctx_persiste...@engines-mixed.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2846]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl4/igt@gem_exec_f...@basic-deadline.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/shard-kbl3/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/shard-iclb1/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/shard-kbl2/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb8/igt@gem_exec_fair@basic-p...@vecs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/shard-tglb6/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][13] -> [SKIP][14] ([i915#2190]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb8/igt@gem_huc_c...@huc-copy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@gem_render_copy@y-tiled-to-vebox-linear: - shard-hsw: NOTRUN -> [SKIP][15] ([fdo#109271]) +114 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/shard-hsw8/igt@gem_render_c...@y-tiled-to-vebox-linear.html * igt@gen3_mixed_blits: - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271]) +29 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/shard-kbl1/igt@gen3_mixed_blits.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#658]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/shard-kbl1/igt@i915_pm...@dc3co-vpb-simulation.html * igt@i915_selftest@live@hangcheck: - shard-hsw: NOTRUN -> [INCOMPLETE][18] ([i915#2782]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/shard-hsw4/igt@i915_selftest@l...@hangcheck.html - shard-snb: [PASS][19] -> [INCOMPLETE][20] ([i915#2782]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-snb5/igt@i915_selftest@l...@hangcheck.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/shard-snb6/igt@i915_selftest@l...@hangcheck.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2597]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb2/igt@kms_async_fl...@test-time-stamp.html [22]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Move execlists_reset() out of line
== Series Details ==
Series: drm/i915/gt: Move execlists_reset() out of line
URL : https://patchwork.freedesktop.org/series/86106/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19435
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/index.html
Known issues
Here are the changes found in Patchwork_19435 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/fi-snb-2520m/igt@amdgpu/amd_pr...@i915-to-amd.html
* igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +1 similar
issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][4] -> [SKIP][5] ([fdo#109271])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-kbl-guc/igt@i915_pm_...@module-reload.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/fi-kbl-guc/igt@i915_pm_...@module-reload.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-snb-2520m: [INCOMPLETE][6] -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][8] ([i915#402]) -> [PASS][9] +1 similar
issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9650 -> Patchwork_19435
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19435: 090d023d9910db877bc24ec559e856e5b1e9aa43 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
090d023d9910 drm/i915/gt: Move execlists_reset() out of line
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19435/index.html
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/uc: Use platform specific defaults for GuC/HuC enabling
== Series Details == Series: drm/i915/uc: Use platform specific defaults for GuC/HuC enabling URL : https://patchwork.freedesktop.org/series/86100/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9650_full -> Patchwork_19432_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19432_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19432_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19432_full: ### IGT changes ### Possible regressions * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/shard-kbl3/igt@gem_exec_fair@basic-p...@vcs0.html * igt@kms_atomic@plane-immutable-zpos: - shard-iclb: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb4/igt@kms_ato...@plane-immutable-zpos.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/shard-iclb1/igt@kms_ato...@plane-immutable-zpos.html Known issues Here are the changes found in Patchwork_19432_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-hostile-preempt: - shard-hsw: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/shard-hsw8/igt@gem_ctx_persiste...@legacy-engines-hostile-preempt.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb2/igt@gem_exec_fair@basic-none-sh...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/shard-tglb1/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl4/igt@gem_exec_fair@basic-n...@vecs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/shard-kbl1/igt@gem_exec_fair@basic-n...@vecs0.html - shard-apl: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-apl2/igt@gem_exec_fair@basic-n...@vecs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/shard-apl7/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][12] ([i915#2389]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/shard-iclb4/igt@gem_exec_reloc@basic-wide-act...@vcs1.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1610] / [i915#2803]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl10/igt@gem_exec_schedule@u-fairsl...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/shard-skl7/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_exec_whisper@basic-queues-priority-all: - shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([i915#1895]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb4/igt@gem_exec_whis...@basic-queues-priority-all.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/shard-iclb2/igt@gem_exec_whis...@basic-queues-priority-all.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][17] -> [SKIP][18] ([i915#2190]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb8/igt@gem_huc_c...@huc-copy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@gen3_mixed_blits: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271]) +29 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/shard-kbl6/igt@gen3_mixed_blits.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#658]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/shard-kbl6/igt@i915_pm...@dc3co-vpb-simulation.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-hsw: [PASS][21] -> [FAIL][22] ([i915#1860]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-hsw6/igt@i915_pm_rc6_reside...@rc6-idle.html [22]:
[Intel-gfx] linux-next: manual merge of the drm-misc tree with Linus' tree
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/ttm/ttm_pool.c
between commit:
bb52cb0dec8d ("drm/ttm: make the pool shrinker lock a mutex")
from Linus' tree and commits:
ba051901d10f ("drm/ttm: add a debugfs file for the global page pools")
f987c9e0f537 ("drm/ttm: optimize ttm pool shrinker a bit")
from the drm-misc tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/gpu/drm/ttm/ttm_pool.c
index 11e0313db0ea,e0617717113f..
--- a/drivers/gpu/drm/ttm/ttm_pool.c
+++ b/drivers/gpu/drm/ttm/ttm_pool.c
@@@ -503,11 -505,14 +506,13 @@@ void ttm_pool_init(struct ttm_pool *poo
pool->use_dma_alloc = use_dma_alloc;
pool->use_dma32 = use_dma32;
- for (i = 0; i < TTM_NUM_CACHING_TYPES; ++i)
- for (j = 0; j < MAX_ORDER; ++j)
- ttm_pool_type_init(>caching[i].orders[j],
- pool, i, j);
+ if (use_dma_alloc) {
+ for (i = 0; i < TTM_NUM_CACHING_TYPES; ++i)
+ for (j = 0; j < MAX_ORDER; ++j)
+ ttm_pool_type_init(>caching[i].orders[j],
+ pool, i, j);
+ }
}
-EXPORT_SYMBOL(ttm_pool_init);
/**
* ttm_pool_fini - Cleanup a pool
@@@ -521,9 -526,34 +526,33 @@@ void ttm_pool_fini(struct ttm_pool *poo
{
unsigned int i, j;
- for (i = 0; i < TTM_NUM_CACHING_TYPES; ++i)
- for (j = 0; j < MAX_ORDER; ++j)
- ttm_pool_type_fini(>caching[i].orders[j]);
+ if (pool->use_dma_alloc) {
+ for (i = 0; i < TTM_NUM_CACHING_TYPES; ++i)
+ for (j = 0; j < MAX_ORDER; ++j)
+ ttm_pool_type_fini(>caching[i].orders[j]);
+ }
+ }
-EXPORT_SYMBOL(ttm_pool_fini);
+
+ /* As long as pages are available make sure to release at least one */
+ static unsigned long ttm_pool_shrinker_scan(struct shrinker *shrink,
+ struct shrink_control *sc)
+ {
+ unsigned long num_freed = 0;
+
+ do
+ num_freed += ttm_pool_shrink();
+ while (!num_freed && atomic_long_read(_pages));
+
+ return num_freed;
+ }
+
+ /* Return the number of pages available or SHRINK_EMPTY if we have none */
+ static unsigned long ttm_pool_shrinker_count(struct shrinker *shrink,
+struct shrink_control *sc)
+ {
+ unsigned long num_pages = atomic_long_read(_pages);
+
+ return num_pages ? num_pages : SHRINK_EMPTY;
}
#ifdef CONFIG_DEBUG_FS
@@@ -553,6 -594,35 +593,35 @@@ static void ttm_pool_debugfs_orders(str
seq_puts(m, "\n");
}
+ /* Dump the total amount of allocated pages */
+ static void ttm_pool_debugfs_footer(struct seq_file *m)
+ {
+ seq_printf(m, "\ntotal\t: %8lu of %8lu\n",
+ atomic_long_read(_pages), page_pool_size);
+ }
+
+ /* Dump the information for the global pools */
+ static int ttm_pool_debugfs_globals_show(struct seq_file *m, void *data)
+ {
+ ttm_pool_debugfs_header(m);
+
- spin_lock(_lock);
++ mutex_lock(_lock);
+ seq_puts(m, "wc\t:");
+ ttm_pool_debugfs_orders(global_write_combined, m);
+ seq_puts(m, "uc\t:");
+ ttm_pool_debugfs_orders(global_uncached, m);
+ seq_puts(m, "wc 32\t:");
+ ttm_pool_debugfs_orders(global_dma32_write_combined, m);
+ seq_puts(m, "uc 32\t:");
+ ttm_pool_debugfs_orders(global_dma32_uncached, m);
- spin_unlock(_lock);
++ mutex_unlock(_lock);
+
+ ttm_pool_debugfs_footer(m);
+
+ return 0;
+ }
+ DEFINE_SHOW_ATTRIBUTE(ttm_pool_debugfs_globals);
+
/**
* ttm_pool_debugfs - Debugfs dump function for a pool
*
@@@ -565,23 -635,14 +634,14 @@@ int ttm_pool_debugfs(struct ttm_pool *p
{
unsigned int i;
- mutex_lock(_lock);
-
- seq_puts(m, "\t ");
- for (i = 0; i < MAX_ORDER; ++i)
- seq_printf(m, " ---%2u---", i);
- seq_puts(m, "\n");
-
- seq_puts(m, "wc\t:");
- ttm_pool_debugfs_orders(global_write_combined, m);
- seq_puts(m, "uc\t:");
- ttm_pool_debugfs_orders(global_uncached, m);
+ if (!pool->use_dma_alloc) {
+ seq_puts(m, "unused\n");
+ return 0;
+ }
- seq_puts(m, "wc 32\t:");
- ttm_pool_debugfs_orders(global_dma32_write_combined, m);
- seq_puts(m, "uc 32\t:");
- ttm_pool_debugfs_orders(global_dma32_uncached, m);
+ ttm_pool_debugfs_header(m);
-
Re: [Intel-gfx] linux-next: build failure after merge of the drm-intel tree
Hi all,
On Wed, 20 Jan 2021 10:57:15 +1100 Stephen Rothwell
wrote:
>
> After merging the drm-intel tree, today's linux-next build (arm
> multi_v7_defconfig) failed like this:
>
> drivers/gpu/drm/msm/dp/dp_ctrl.c: In function 'dp_ctrl_use_fixed_nvid':
> drivers/gpu/drm/msm/dp/dp_ctrl.c:1425:16: error: implicit declaration of
> function 'drm_dp_get_edid_quirks'; did you mean 'drm_do_get_edid'?
> [-Werror=implicit-function-declaration]
> 1425 | edid_quirks = drm_dp_get_edid_quirks(ctrl->panel->edid);
> |^~
> |drm_do_get_edid
> drivers/gpu/drm/msm/dp/dp_ctrl.c:1431:11: error: too many arguments to
> function 'drm_dp_has_quirk'
> 1431 | return (drm_dp_has_quirk(>panel->desc, edid_quirks,
> | ^~~~
> In file included from drivers/gpu/drm/msm/dp/dp_ctrl.c:15:
> include/drm/drm_dp_helper.h:2087:1: note: declared here
> 2087 | drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk
> quirk)
> | ^~~~
>
> Caused by commit
>
> 7c553f8b5a7d ("drm/dp: Revert "drm/dp: Introduce EDID-based quirks"")
>
> Since the drm-intel tree still has its other build failure, I used the
> version from next-20210108 again today.
I still get this failure, but not the one from the drm tree, so I have
used the drm-intel tree from next-20210119 for today.
--
Cheers,
Stephen Rothwell
pgpBlpaqoIsSK.pgp
Description: OpenPGP digital signature
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[Intel-gfx] [PATCH] drm/i915/gt: Move execlists_reset() out of line
Reduce the bulk of execlists_submission_tasklet by moving the unlikely
reset function out of line.
add/remove: 1/0 grow/shrink: 0/1 up/down: 960/-935 (25)
Function old new delta
execlists_reset- 960+960
execlists_submission_tasklet66295694-935
Signed-off-by: Chris Wilson
---
.../drm/i915/gt/intel_execlists_submission.c | 36 +--
1 file changed, 17 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 740ff05fd692..43cc85241886 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2299,10 +2299,13 @@ static void execlists_capture(struct intel_engine_cs
*engine)
kfree(cap);
}
-static void execlists_reset(struct intel_engine_cs *engine, const char *msg)
+static noinline void execlists_reset(struct intel_engine_cs *engine)
{
+ struct intel_engine_execlists *el = >execlists;
const unsigned int bit = I915_RESET_ENGINE + engine->id;
unsigned long *lock = >gt->reset.flags;
+ unsigned long eir = fetch_and_zero(>error_interrupt);
+ const char *msg;
if (!intel_has_reset_engine(engine->gt))
return;
@@ -2310,16 +2313,25 @@ static void execlists_reset(struct intel_engine_cs
*engine, const char *msg)
if (test_and_set_bit(bit, lock))
return;
+ /* Generate the error message in priority wrt to the user! */
+ if (eir & GENMASK(15, 0))
+ msg = "CS error"; /* thrown by a user payload */
+ else if (eir & ERROR_CSB)
+ msg = "invalid CSB event";
+ else if (eir & ERROR_PREEMPT)
+ msg = "preemption time out";
+ else
+ msg = "internal error";
ENGINE_TRACE(engine, "reset for %s\n", msg);
/* Mark this tasklet as disabled to avoid waiting for it to complete */
- tasklet_disable_nosync(>execlists.tasklet);
+ tasklet_disable_nosync(>tasklet);
ring_set_paused(engine, 1); /* Freeze the current request in place */
execlists_capture(engine);
intel_engine_reset(engine, msg);
- tasklet_enable(>execlists.tasklet);
+ tasklet_enable(>tasklet);
clear_and_wake_up_bit(bit, lock);
}
@@ -2355,22 +2367,8 @@ static void execlists_submission_tasklet(unsigned long
data)
engine->execlists.error_interrupt |= ERROR_PREEMPT;
}
- if (unlikely(READ_ONCE(engine->execlists.error_interrupt))) {
- const char *msg;
-
- /* Generate the error message in priority wrt to the user! */
- if (engine->execlists.error_interrupt & GENMASK(15, 0))
- msg = "CS error"; /* thrown by a user payload */
- else if (engine->execlists.error_interrupt & ERROR_CSB)
- msg = "invalid CSB event";
- else if (engine->execlists.error_interrupt & ERROR_PREEMPT)
- msg = "preemption time out";
- else
- msg = "internal error";
-
- engine->execlists.error_interrupt = 0;
- execlists_reset(engine, msg);
- }
+ if (unlikely(READ_ONCE(engine->execlists.error_interrupt)))
+ execlists_reset(engine);
if (!engine->execlists.pending[0]) {
execlists_dequeue_irq(engine);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Call stop_ring() from ring resume, again
== Series Details ==
Series: drm/i915/gt: Call stop_ring() from ring resume, again
URL : https://patchwork.freedesktop.org/series/86103/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19434
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/index.html
Known issues
Here are the changes found in Patchwork_19434 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/fi-snb-2520m/igt@amdgpu/amd_pr...@i915-to-amd.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [PASS][2] -> [INCOMPLETE][3] ([i915#142] /
[i915#2405])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-byt-j1900/igt@i915_pm_...@module-reload.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/fi-byt-j1900/igt@i915_pm_...@module-reload.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271]) +30 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html
* igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y: [PASS][6] -> [DMESG-WARN][7] ([i915#402]) +1 similar
issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][8] ([i915#1602] / [i915#2029] /
[i915#2369])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/fi-bdw-5557u/igt@run...@aborted.html
- fi-byt-j1900: NOTRUN -> [FAIL][9] ([i915#1814] / [i915#2505])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/fi-byt-j1900/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-snb-2600:[DMESG-WARN][10] ([i915#2772]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2520m: [INCOMPLETE][12] -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][14] ([i915#402]) -> [PASS][15] +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19434/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9650 -> Patchwork_19434
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v12,1/2] drm/i915/display: Support PSR Multiple Instances
== Series Details == Series: series starting with [v12,1/2] drm/i915/display: Support PSR Multiple Instances URL : https://patchwork.freedesktop.org/series/86091/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9650_full -> Patchwork_19428_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19428_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19428_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19428_full: ### IGT changes ### Possible regressions * igt@i915_module_load@reload-with-fault-injection: - shard-hsw: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-hsw6/igt@i915_module_l...@reload-with-fault-injection.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/shard-hsw4/igt@i915_module_l...@reload-with-fault-injection.html Known issues Here are the changes found in Patchwork_19428_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_exec@basic-close-race: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([i915#1895]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb3/igt@gem_ctx_e...@basic-close-race.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/shard-iclb7/igt@gem_ctx_e...@basic-close-race.html * igt@gem_ctx_persistence@legacy-engines-mixed-process: - shard-hsw: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/shard-hsw8/igt@gem_ctx_persiste...@legacy-engines-mixed-process.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb8/igt@gem_exec_fair@basic-p...@vecs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/shard-tglb1/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][11] ([i915#2389]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/shard-iclb1/igt@gem_exec_reloc@basic-wide-act...@vcs1.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-tglb: [PASS][12] -> [DMESG-WARN][13] ([i915#2803]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb8/igt@gem_exec_schedule@u-fairsl...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/shard-tglb1/igt@gem_exec_schedule@u-fairsl...@rcs0.html - shard-skl: [PASS][14] -> [DMESG-WARN][15] ([i915#1610] / [i915#2803]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl10/igt@gem_exec_schedule@u-fairsl...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/shard-skl3/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_render_copy@y-tiled-to-vebox-linear: - shard-hsw: NOTRUN -> [SKIP][16] ([fdo#109271]) +212 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/shard-hsw4/igt@gem_render_c...@y-tiled-to-vebox-linear.html * igt@gen3_mixed_blits: - shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271]) +29 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/shard-kbl2/igt@gen3_mixed_blits.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#658]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/shard-kbl2/igt@i915_pm...@dc3co-vpb-simulation.html * igt@i915_selftest@live@hangcheck: - shard-snb: [PASS][19] -> [INCOMPLETE][20] ([i915#2782]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-snb5/igt@i915_selftest@l...@hangcheck.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/shard-snb6/igt@i915_selftest@l...@hangcheck.html * igt@i915_suspend@forcewake: - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#636])
[Intel-gfx] [PATCH] drm/i915/gt: Call stop_ring() from ring resume, again
For reasons I cannot explain, except to say this is Sandybridge after
all, call stop_ring() again dring ring resume in order to prevent
mysterious hard hangs.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
If this survives the night on my snb-2500, I declare victory.
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 107 +-
1 file changed, 55 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 4984ff565424..7eef2c6c1ed0 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -183,15 +183,35 @@ static void set_pp_dir(struct intel_engine_cs *engine)
}
}
+static bool stop_ring(struct intel_engine_cs *engine)
+{
+ /* Empty the ring by skipping to the end */
+ ENGINE_WRITE_FW(engine, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL));
+ ENGINE_POSTING_READ(engine, RING_HEAD);
+
+ /* The ring must be empty before it is disabled */
+ ENGINE_WRITE_FW(engine, RING_CTL, 0);
+ ENGINE_POSTING_READ(engine, RING_CTL);
+
+ /* Then reset the disabled ring */
+ ENGINE_WRITE_FW(engine, RING_HEAD, 0);
+ ENGINE_WRITE_FW(engine, RING_TAIL, 0);
+
+ return (ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) == 0;
+}
+
static int xcs_resume(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
struct intel_ring *ring = engine->legacy.ring;
ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n",
ring->head, ring->tail);
- if (HWS_NEEDS_PHYSICAL(dev_priv))
+ /* Double check the ring is empty & disabled before we resume */
+ if (!stop_ring(engine))
+ goto err;
+
+ if (HWS_NEEDS_PHYSICAL(engine->i915))
ring_setup_phys_status_page(engine);
else
ring_setup_status_page(engine);
@@ -228,21 +248,10 @@ static int xcs_resume(struct intel_engine_cs *engine)
if (__intel_wait_for_register_fw(engine->uncore,
RING_CTL(engine->mmio_base),
RING_VALID, RING_VALID,
-5000, 0, NULL)) {
- drm_err(_priv->drm,
- "%s initialization failed; "
- "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x]
start %08x [expected %08x]\n",
- engine->name,
- ENGINE_READ(engine, RING_CTL),
- ENGINE_READ(engine, RING_CTL) & RING_VALID,
- ENGINE_READ(engine, RING_HEAD), ring->head,
- ENGINE_READ(engine, RING_TAIL), ring->tail,
- ENGINE_READ(engine, RING_START),
- i915_ggtt_offset(ring->vma));
- return -EIO;
- }
+5000, 0, NULL))
+ goto err;
- if (INTEL_GEN(dev_priv) > 2)
+ if (INTEL_GEN(engine->i915) > 2)
ENGINE_WRITE_FW(engine,
RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
@@ -255,6 +264,19 @@ static int xcs_resume(struct intel_engine_cs *engine)
/* Papering over lost _interrupts_ immediately following the restart */
intel_engine_signal_breadcrumbs(engine);
return 0;
+
+err:
+ drm_err(>i915->drm,
+ "%s initialization failed; "
+ "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start
%08x [expected %08x]\n",
+ engine->name,
+ ENGINE_READ(engine, RING_CTL),
+ ENGINE_READ(engine, RING_CTL) & RING_VALID,
+ ENGINE_READ(engine, RING_HEAD), ring->head,
+ ENGINE_READ(engine, RING_TAIL), ring->tail,
+ ENGINE_READ(engine, RING_START),
+ i915_ggtt_offset(ring->vma));
+ return -EIO;
}
static void sanitize_hwsp(struct intel_engine_cs *engine)
@@ -290,23 +312,6 @@ static void xcs_sanitize(struct intel_engine_cs *engine)
clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
}
-static bool stop_ring(struct intel_engine_cs *engine)
-{
- /* Empty the ring by skipping to the end */
- ENGINE_WRITE_FW(engine, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL));
- ENGINE_POSTING_READ(engine, RING_HEAD);
-
- /* The ring must be empty before it is disabled */
- ENGINE_WRITE_FW(engine, RING_CTL, 0);
- ENGINE_POSTING_READ(engine, RING_CTL);
-
- /* Then reset the disabled ring */
- ENGINE_WRITE_FW(engine, RING_HEAD, 0);
- ENGINE_WRITE_FW(engine, RING_TAIL, 0);
-
- return (ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) == 0;
-}
-
static void reset_prepare(struct intel_engine_cs *engine)
{
/*
@@ -329,25 +334,23 @@ static void reset_prepare(struct intel_engine_cs *engine)
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gen12: Add display render clear color decompression support (rev5)
== Series Details ==
Series: drm/i915/gen12: Add display render clear color decompression support
(rev5)
URL : https://patchwork.freedesktop.org/series/85877/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19433
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19433 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19433, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19433/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19433:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@hangcheck:
- fi-bsw-nick:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-bsw-nick/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19433/fi-bsw-nick/igt@i915_selftest@l...@hangcheck.html
Known issues
Here are the changes found in Patchwork_19433 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@memory-alloc:
- fi-tgl-y: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +2
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19433/fi-tgl-y/igt@amdgpu/amd_ba...@memory-alloc.html
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19433/fi-snb-2520m/igt@amdgpu/amd_pr...@i915-to-amd.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#2411] /
[i915#402])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19433/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [PASS][7] -> [DMESG-WARN][8] ([i915#2868])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19433/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
* igt@prime_self_import@basic-with_one_bo:
- fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#402])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_one_bo.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19433/fi-tgl-y/igt@prime_self_import@basic-with_one_bo.html
* igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][11] ([i915#1436])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19433/fi-bsw-nick/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-snb-2520m: [INCOMPLETE][12] -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19433/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][14] ([i915#402]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19433/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9650 -> Patchwork_19433
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19433: 34cda0c7d54c4ab10b167f9003b18f6183849b85 @
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [01/10] drm/i915/gt: Do not suspend bonded requests if one hangs
== Series Details == Series: series starting with [01/10] drm/i915/gt: Do not suspend bonded requests if one hangs URL : https://patchwork.freedesktop.org/series/86088/ State : success == Summary == CI Bug Log - changes from CI_DRM_9650_full -> Patchwork_19427_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_9650_full and Patchwork_19427_full: ### New IGT tests (2) ### * igt@i915_selftest@live@scheduler: - Statuses : 8 pass(s) - Exec time: [0.47, 6.58] s * igt@i915_selftest@perf@scheduler: - Statuses : 8 pass(s) - Exec time: [0.62, 10.95] s Known issues Here are the changes found in Patchwork_19427_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-hostile-preempt: - shard-hsw: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-hsw4/igt@gem_ctx_persiste...@legacy-engines-hostile-preempt.html * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][2] -> [INCOMPLETE][3] ([i915#2369]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl3/igt@gem_exec_capture@p...@rcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl5/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][4] ([i915#2842]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl4/igt@gem_exec_fair@basic-n...@vecs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-kbl4/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [PASS][7] -> [SKIP][8] ([fdo#109271]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb8/igt@gem_exec_fair@basic-p...@vecs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-tglb7/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][11] ([i915#2389]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-iclb4/igt@gem_exec_reloc@basic-wide-act...@vcs1.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-apl: [PASS][12] -> [DMESG-WARN][13] ([i915#1610]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-apl2/igt@gem_exec_schedule@u-fairsl...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-apl8/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-skl: [PASS][14] -> [FAIL][15] ([i915#644]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl5/igt@gem_pp...@flink-and-close-vma-leak.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl2/igt@gem_pp...@flink-and-close-vma-leak.html * igt@gen3_mixed_blits: - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271]) +29 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-kbl3/igt@gen3_mixed_blits.html * igt@gen9_exec_parse@allowed-all: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1436] / [i915#716]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl6/igt@gen9_exec_pa...@allowed-all.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-skl10/igt@gen9_exec_pa...@allowed-all.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#658]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-kbl3/igt@i915_pm...@dc3co-vpb-simulation.html * igt@i915_selftest@live@hangcheck: - shard-hsw: NOTRUN -> [INCOMPLETE][20] ([i915#2782]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/shard-hsw2/igt@i915_selftest@l...@hangcheck.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2574]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb2/igt@kms_async_fl...@test-time-stamp.html [22]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gen12: Add display render clear color decompression support (rev5)
== Series Details == Series: drm/i915/gen12: Add display render clear color decompression support (rev5) URL : https://patchwork.freedesktop.org/series/85877/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gen12: Add display render clear color decompression support (rev5)
== Series Details == Series: drm/i915/gen12: Add display render clear color decompression support (rev5) URL : https://patchwork.freedesktop.org/series/85877/ State : warning == Summary == $ dim checkpatch origin/drm-tip 249da006ed76 drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color 8815035bf706 drm/i915/gem: Add a helper to read data from a GEM object page -:48: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #48: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.c:341: +i915_gem_object_read_from_page_kmap(struct drm_i915_gem_object *obj, u64 offset, void *dst, int size) -:64: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #64: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.c:357: +i915_gem_object_read_from_page_iomap(struct drm_i915_gem_object *obj, u64 offset, void *dst, int size) -:92: WARNING:TYPO_SPELLING: 'sucess' may be misspelled - perhaps 'success'? #92: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.c:385: + * Returns 0 on sucess or -ENODEV if the type of @obj's backing store is ^^ -:135: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #135: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.h:540: +int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, u64 offset, void *dst, int size); total: 0 errors, 4 warnings, 0 checks, 95 lines checked 34cda0c7d54c drm/i915/tgl: Add Clear Color support for TGL Render Decompression -:360: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #360: FILE: drivers/gpu/drm/i915/i915_reg.h:7120: +#define PLANE_CC_VAL(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe)) total: 0 errors, 0 warnings, 1 checks, 272 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/uc: Use platform specific defaults for GuC/HuC enabling
== Series Details ==
Series: drm/i915/uc: Use platform specific defaults for GuC/HuC enabling
URL : https://patchwork.freedesktop.org/series/86100/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19432
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/index.html
Known issues
Here are the changes found in Patchwork_19432 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/fi-snb-2520m/igt@amdgpu/amd_pr...@i915-to-amd.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][2] ([fdo#109271]) +30 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html
* igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y: [PASS][4] -> [DMESG-WARN][5] ([i915#402]) +1 similar
issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-snb-2600:[DMESG-WARN][6] ([i915#2772]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2520m: [INCOMPLETE][8] -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][10] ([i915#402]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 37)
--
Missing(6): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-bsw-cyan
fi-ctg-p8600 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9650 -> Patchwork_19432
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19432: 626023209159fa1c8d61d7237297c7260a804916 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
626023209159 drm/i915/uc: Use platform specific defaults for GuC/HuC enabling
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19432/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/gt: Do not suspend bonded requests if one hangs
== Series Details == Series: series starting with [1/2] drm/i915/gt: Do not suspend bonded requests if one hangs URL : https://patchwork.freedesktop.org/series/86087/ State : success == Summary == CI Bug Log - changes from CI_DRM_9650_full -> Patchwork_19426_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19426_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@engines-mixed: - shard-hsw: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/shard-hsw6/igt@gem_ctx_persiste...@engines-mixed.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [PASS][2] -> [FAIL][3] ([i915#2842]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-apl2/igt@gem_exec_fair@basic-n...@vecs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2842]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb8/igt@gem_exec_fair@basic-p...@vecs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/shard-tglb8/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-apl: [PASS][6] -> [FAIL][7] ([i915#2389]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-apl3/igt@gem_exec_reloc@basic-many-act...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/shard-apl4/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_render_copy@y-tiled-to-vebox-linear: - shard-hsw: NOTRUN -> [SKIP][8] ([fdo#109271]) +160 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/shard-hsw6/igt@gem_render_c...@y-tiled-to-vebox-linear.html * igt@gen3_mixed_blits: - shard-kbl: NOTRUN -> [SKIP][9] ([fdo#109271]) +29 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/shard-kbl6/igt@gen3_mixed_blits.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-kbl: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#658]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/shard-kbl6/igt@i915_pm...@dc3co-vpb-simulation.html * igt@i915_selftest@live@hangcheck: - shard-hsw: NOTRUN -> [INCOMPLETE][11] ([i915#2782]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/shard-hsw7/igt@i915_selftest@l...@hangcheck.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [PASS][12] -> [FAIL][13] ([i915#2521]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl3/igt@kms_async_fl...@alternate-sync-async-flip.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/shard-skl10/igt@kms_async_fl...@alternate-sync-async-flip.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2597]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb2/igt@kms_async_fl...@test-time-stamp.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/shard-tglb2/igt@kms_async_fl...@test-time-stamp.html * igt@kms_atomic_transition@plane-all-transition-nonblocking-fencing: - shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/shard-snb2/igt@kms_atomic_transit...@plane-all-transition-nonblocking-fencing.html * igt@kms_chamelium@hdmi-hpd-with-enabled-mode: - shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/shard-kbl6/igt@kms_chamel...@hdmi-hpd-with-enabled-mode.html * igt@kms_chamelium@vga-frame-dump: - shard-snb: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/shard-snb4/igt@kms_chamel...@vga-frame-dump.html * igt@kms_color_chamelium@pipe-a-ctm-green-to-red: - shard-glk: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/shard-glk2/igt@kms_color_chamel...@pipe-a-ctm-green-to-red.html * igt@kms_color_chamelium@pipe-c-ctm-limited-range: - shard-hsw: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +10 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/shard-hsw2/igt@kms_color_chamel...@pipe-c-ctm-limited-range.html * igt@kms_color_chamelium@pipe-d-ctm-green-to-red: - shard-skl: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +3 similar issues [21]:
[Intel-gfx] ✗ Fi.CI.BUILD: failure for kbuild: use always-y instead of extra-y
== Series Details == Series: kbuild: use always-y instead of extra-y URL : https://patchwork.freedesktop.org/series/86094/ State : failure == Summary == Applying: kbuild: use always-y instead of extra-y error: sha1 information is lacking or useless (scripts/Makefile.lib). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 kbuild: use always-y instead of extra-y When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] kbuild: use always-y instead of extra-y
On Wed, Jan 20, 2021 at 03:23:51PM +0900, Masahiro Yamada wrote:
> As commit d0e628cd817f ("kbuild: doc: clarify the difference between
> extra-y and always-y") explained, extra-y should be used for listing
> the prerequsites of vmlinux. always-y is a better fix here.
prerequisites
Glad to see this clarified. I think just tried both and picked one.
Reviewed-by: Rob Herring
>
> Signed-off-by: Masahiro Yamada
> ---
>
> Documentation/devicetree/bindings/Makefile | 8
> drivers/gpu/drm/i915/Makefile | 2 +-
> scripts/Makefile.lib | 10 +-
> scripts/gdb/linux/Makefile | 2 +-
> 4 files changed, 11 insertions(+), 11 deletions(-)
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 2/3] drm/i915/gem: Add a helper to read data from a GEM object page
Add a simple helper to read data with the CPU from the page of a GEM
object. Do the read either via a kmap if the object has struct pages
or an iomap otherwise. This is needed by the next patch, reading a u64
value from the object (w/o requiring the obj to be mapped to the GPU).
Suggested by Chris.
v2 (Chris):
- Sanitize the type and order of func params.
- Avoid consts requiring too many casts.
- Use BUG_ON instead of WARN_ON, simplify the conditions.
- Fix __iomem sparse errors.
- Leave locking/syncing/pinning up to the caller, require only that the
caller has pinned the object pages.
- Check for iomem backing store before reading via an iomap.
v3:
- Fix offset passed to io_mapping_map_wc() missing a mem.region.start
delta. (Chris, Matthew)
Cc: Chris Wilson
Cc: Matthew Auld
Signed-off-by: Imre Deak
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 65 ++
drivers/gpu/drm/i915/gem/i915_gem_object.h | 8 +++
2 files changed, 73 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 83c6ee6a509a..ad90a43a1c8c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -31,6 +31,7 @@
#include "i915_gem_mman.h"
#include "i915_gem_object.h"
#include "i915_globals.h"
+#include "i915_memcpy.h"
#include "i915_trace.h"
static struct i915_global_object {
@@ -336,6 +337,70 @@ void __i915_gem_object_invalidate_frontbuffer(struct
drm_i915_gem_object *obj,
}
}
+static void
+i915_gem_object_read_from_page_kmap(struct drm_i915_gem_object *obj, u64
offset, void *dst, int size)
+{
+ void *src_map;
+ void *src_ptr;
+
+ src_map = kmap_atomic(i915_gem_object_get_page(obj, offset >>
PAGE_SHIFT));
+
+ src_ptr = src_map + offset_in_page(offset);
+ if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ))
+ drm_clflush_virt_range(src_ptr, size);
+ memcpy(dst, src_ptr, size);
+
+ kunmap_atomic(src_map);
+}
+
+static void
+i915_gem_object_read_from_page_iomap(struct drm_i915_gem_object *obj, u64
offset, void *dst, int size)
+{
+ void __iomem *src_map;
+ void __iomem *src_ptr;
+ dma_addr_t dma = i915_gem_object_get_dma_address(obj, offset >>
PAGE_SHIFT);
+
+ src_map = io_mapping_map_wc(>mm.region->iomap,
+ dma - obj->mm.region->region.start,
+ PAGE_SIZE);
+
+ src_ptr = src_map + offset_in_page(offset);
+ if (!i915_memcpy_from_wc(dst, (void __force *)src_ptr, size))
+ memcpy_fromio(dst, src_ptr, size);
+
+ io_mapping_unmap(src_map);
+}
+
+/**
+ * i915_gem_object_read_from_page - read data from the page of a GEM object
+ * @obj: GEM object to read from
+ * @offset: offset within the object
+ * @dst: buffer to store the read data
+ * @size: size to read
+ *
+ * Reads data from @obj at the specified offset. The requested region to read
+ * from can't cross a page boundary. The caller must ensure that @obj pages
+ * are pinned and that @obj is synced wrt. any related writes.
+ *
+ * Returns 0 on sucess or -ENODEV if the type of @obj's backing store is
+ * unsupported.
+ */
+int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, u64
offset, void *dst, int size)
+{
+ GEM_BUG_ON(offset >= obj->base.size);
+ GEM_BUG_ON(offset_in_page(offset) > PAGE_SIZE - size);
+ GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
+
+ if (i915_gem_object_has_struct_page(obj))
+ i915_gem_object_read_from_page_kmap(obj, offset, dst, size);
+ else if (i915_gem_object_has_iomem(obj))
+ i915_gem_object_read_from_page_iomap(obj, offset, dst, size);
+ else
+ return -ENODEV;
+
+ return 0;
+}
+
void i915_gem_init__objects(struct drm_i915_private *i915)
{
INIT_WORK(>mm.free_work, __i915_gem_free_work);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index b6a16ab85956..bb8aea75c3fd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -200,6 +200,12 @@ i915_gem_object_has_struct_page(const struct
drm_i915_gem_object *obj)
return i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_STRUCT_PAGE);
}
+static inline bool
+i915_gem_object_has_iomem(const struct drm_i915_gem_object *obj)
+{
+ return i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_IOMEM);
+}
+
static inline bool
i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
{
@@ -531,4 +537,6 @@ i915_gem_object_invalidate_frontbuffer(struct
drm_i915_gem_object *obj,
__i915_gem_object_invalidate_frontbuffer(obj, origin);
}
+int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, u64
offset, void *dst, int size);
+
#endif
--
2.25.1
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915: Nuke not needed members of dram_info
== Series Details ==
Series: series starting with [1/4] drm/i915: Nuke not needed members of
dram_info
URL : https://patchwork.freedesktop.org/series/86092/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19429
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19429 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19429, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19429/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19429:
### IGT changes ###
Possible regressions
* igt@i915_module_load@reload:
- fi-glk-dsi: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-glk-dsi/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19429/fi-glk-dsi/igt@i915_module_l...@reload.html
Known issues
Here are the changes found in Patchwork_19429 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19429/fi-snb-2520m/igt@amdgpu/amd_pr...@i915-to-amd.html
* igt@gem_exec_fence@basic-busy:
- fi-glk-dsi: NOTRUN -> [SKIP][4] ([fdo#109271]) +13 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19429/fi-glk-dsi/igt@gem_exec_fe...@basic-busy.html
* igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar
issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19429/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
* igt@kms_addfb_basic@invalid-set-prop-any:
- fi-glk-dsi: [PASS][7] -> [SKIP][8] ([fdo#109271]) +116 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-glk-dsi/igt@kms_addfb_ba...@invalid-set-prop-any.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19429/fi-glk-dsi/igt@kms_addfb_ba...@invalid-set-prop-any.html
* igt@runner@aborted:
- fi-glk-dsi: NOTRUN -> [FAIL][9] ([i915#2292] / [i915#2295] /
[k.org#202321] / [k.org#204565])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19429/fi-glk-dsi/igt@run...@aborted.html
Possible fixes
* igt@gem_render_tiled_blits@basic:
- fi-tgl-y: [DMESG-WARN][10] ([i915#402]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@gem_render_tiled_bl...@basic.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19429/fi-tgl-y/igt@gem_render_tiled_bl...@basic.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2520m: [INCOMPLETE][12] -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19429/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
Warnings
* igt@gem_huc_copy@huc-copy:
- fi-glk-dsi: [SKIP][14] ([fdo#109271] / [i915#2190]) -> [SKIP][15]
([fdo#109271])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-glk-dsi/igt@gem_huc_c...@huc-copy.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19429/fi-glk-dsi/igt@gem_huc_c...@huc-copy.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-glk-dsi: [SKIP][16] ([fdo#109271] / [fdo#111827]) ->
[SKIP][17] ([fdo#109271]) +8 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-glk-dsi/igt@kms_chamel...@hdmi-hpd-fast.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19429/fi-glk-dsi/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-glk-dsi: [SKIP][18] ([fdo#109271] / [i915#533]) -> [SKIP][19]
([fdo#109271])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-glk-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19429/fi-glk-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gem: Allow importing of shmemfs objects into any device
== Series Details == Series: drm/i915/gem: Allow importing of shmemfs objects into any device URL : https://patchwork.freedesktop.org/series/86093/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c: In function ‘i915_gem_prime_import’: drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c:250:7: error: implicit declaration of function ‘i915_gem_object_is_shmem’; did you mean ‘i915_gem_object_is_tiled’? [-Werror=implicit-function-declaration] if (i915_gem_object_is_shmem(obj)) ^~~~ i915_gem_object_is_tiled cc1: all warnings being treated as errors scripts/Makefile.build:279: recipe for target 'drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o' failed make[4]: *** [drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o] Error 1 scripts/Makefile.build:496: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:496: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:496: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1805: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gem: Allow importing of shmemfs objects into any device
Quoting Chris Wilson (2021-01-20 18:06:08) > Quoting Matthew Auld (2021-01-20 17:46:10) > > On Wed, 20 Jan 2021 at 15:40, Chris Wilson wrote: > > > > > > If we import a shmemfs object between devices, for example from > > > Tigerlake to DG1, we can simply reuse the native object and its backing > > > store. > > > > Hmmm interesting, so does that include re-using the actual sg mapping > > for the backing pages? Does that work out-of-the-box between different > > devices assuming we have iommu enabled? > > Indeed interesting; the dma_addr_t are supposed to be local to a device. On reflection, we are expected to use cross-device dma_addr_t with dma-buf. It's the exporter who assigns the dma_addr_t for the importer to use, and they are always given from the original device. Maybe not so bad. Definitely needs testing to see what happens in practice. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v12,1/2] drm/i915/display: Support PSR Multiple Instances
== Series Details ==
Series: series starting with [v12,1/2] drm/i915/display: Support PSR Multiple
Instances
URL : https://patchwork.freedesktop.org/series/86091/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19428
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19428:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_psr@primary_mmap_gtt:
- {fi-tgl-dsi}: [SKIP][1] ([fdo#110189]) -> [SKIP][2] +3 similar
issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
Known issues
Here are the changes found in Patchwork_19428 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/fi-snb-2520m/igt@amdgpu/amd_pr...@i915-to-amd.html
* igt@i915_selftest@live@client:
- fi-kbl-soraka: [PASS][4] -> [INCOMPLETE][5] ([i915#2295])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-kbl-soraka/igt@i915_selftest@l...@client.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/fi-kbl-soraka/igt@i915_selftest@l...@client.html
* igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y: [PASS][6] -> [DMESG-WARN][7] ([i915#402]) +1 similar
issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
* igt@runner@aborted:
- fi-kbl-soraka: NOTRUN -> [FAIL][8] ([i915#1436] / [i915#2722])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/fi-kbl-soraka/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-snb-2520m: [INCOMPLETE][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9650 -> Patchwork_19428
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19428: d3cae8cfe173bf0155edf3e67453ace6c47d2191 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d3cae8cfe173 drm/i915/display: Support Multiple Transcoders' PSR status on
debugfs
ca6ecae10b15 drm/i915/display: Support PSR Multiple Instances
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19428/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gem: Allow importing of shmemfs objects into any device
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip v5.11-rc4 next-20210120]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-gem-Allow-importing-of-shmemfs-objects-into-any-device/20210120-234237
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-a013-20210120 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/ce377384dec1c18f1af3558d5d4624d300d160c4
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Chris-Wilson/drm-i915-gem-Allow-importing-of-shmemfs-objects-into-any-device/20210120-234237
git checkout ce377384dec1c18f1af3558d5d4624d300d160c4
# save the attached .config to linux build tree
make W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c: In function
'i915_gem_prime_import':
>> drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c:250:7: error: implicit
>> declaration of function 'i915_gem_object_is_shmem'; did you mean
>> 'i915_gem_object_is_tiled'? [-Werror=implicit-function-declaration]
250 | if (i915_gem_object_is_shmem(obj))
| ^~~~
| i915_gem_object_is_tiled
cc1: some warnings being treated as errors
vim +250 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
225
226 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
227 struct dma_buf *dma_buf)
228 {
229 static struct lock_class_key lock_class;
230 struct dma_buf_attachment *attach;
231 struct drm_i915_gem_object *obj;
232 int ret;
233
234 /* is this one of own objects? */
235 if (dma_buf->ops == _dmabuf_ops) {
236 obj = dma_buf_to_obj(dma_buf);
237 /* is it from our device? */
238 if (obj->base.dev == dev) {
239 /*
240 * Importing dmabuf exported from out own gem
increases
241 * refcount on gem itself instead of f_count of
dmabuf.
242 */
243 return _gem_object_get(obj)->base;
244 }
245
246 /*
247 * If the object is in plain system memory, we can
reuse the
248 * same backing store in any device.
249 */
> 250 if (i915_gem_object_is_shmem(obj))
251 return _gem_object_get(obj)->base;
252 }
253
254 /* need to attach */
255 attach = dma_buf_attach(dma_buf, dev->dev);
256 if (IS_ERR(attach))
257 return ERR_CAST(attach);
258
259 get_dma_buf(dma_buf);
260
261 obj = i915_gem_object_alloc();
262 if (obj == NULL) {
263 ret = -ENOMEM;
264 goto fail_detach;
265 }
266
267 drm_gem_private_object_init(dev, >base, dma_buf->size);
268 i915_gem_object_init(obj, _gem_object_dmabuf_ops,
_class);
269 obj->base.import_attach = attach;
270 obj->base.resv = dma_buf->resv;
271
272 /* We use GTT as shorthand for a coherent domain, one that is
273 * neither in the GPU cache nor in the CPU cache, where all
274 * writes are immediately visible in memory. (That's not
strictly
275 * true, but it's close! There are internal buffers such as the
276 * write-combined buffer or a delay through the chipset for GTT
277 * writes that do require us to treat GTT as a separate cache
domain.)
278 */
279 obj->read_domains = I915_GEM_DOMAIN_GTT;
280 obj->write_domain = 0;
281
282 return >base;
283
284 fail_detach:
285 dma_buf_detach(dma_buf, attach);
286 dma_buf_put(dma_buf);
287
288 return ERR_PTR(ret);
289 }
290
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] linux-next: build failure after merge of the drm tree
Hi Daniel, On Wed, 20 Jan 2021 13:12:21 +0100 Daniel Vetter wrote: > > I've pulled drm-misc-next into drm-next now, so as long as all other > drm trees are merged after drm, this should be solved now. > drm-intel-next also has their msm build breakage fixed (I acked the > patch already), so hopefully we should be all clean again. Thanks. -- Cheers, Stephen Rothwell pgpnUv51MUYI_.pgp Description: OpenPGP digital signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/msm/dp: fix build after dp quirk helper change
== Series Details == Series: drm/msm/dp: fix build after dp quirk helper change URL : https://patchwork.freedesktop.org/series/86079/ State : success == Summary == CI Bug Log - changes from CI_DRM_9650_full -> Patchwork_19424_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19424_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@close-replace-race: - shard-glk: [PASS][1] -> [TIMEOUT][2] ([i915#2918]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk6/igt@gem_ctx_persiste...@close-replace-race.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/shard-glk3/igt@gem_ctx_persiste...@close-replace-race.html * igt@gem_ctx_persistence@engines-mixed: - shard-hsw: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/shard-hsw6/igt@gem_ctx_persiste...@engines-mixed.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2842]) +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/shard-tglb6/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-apl2/igt@gem_exec_fair@basic-n...@vecs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/shard-apl3/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_reloc@basic-many-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][10] ([i915#2389]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/shard-iclb1/igt@gem_exec_reloc@basic-many-act...@vcs1.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1610] / [i915#2803]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl10/igt@gem_exec_schedule@u-fairsl...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/shard-skl6/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_render_copy@y-tiled-to-vebox-linear: - shard-hsw: NOTRUN -> [SKIP][13] ([fdo#109271]) +170 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/shard-hsw6/igt@gem_render_c...@y-tiled-to-vebox-linear.html * igt@gen3_mixed_blits: - shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271]) +29 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/shard-kbl3/igt@gen3_mixed_blits.html * igt@i915_pm_backlight@fade_with_suspend: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#198]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl4/igt@i915_pm_backlight@fade_with_suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/shard-skl7/igt@i915_pm_backlight@fade_with_suspend.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#658]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/shard-kbl3/igt@i915_pm...@dc3co-vpb-simulation.html * igt@i915_selftest@live@hangcheck: - shard-hsw: NOTRUN -> [INCOMPLETE][18] ([i915#2782]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/shard-hsw4/igt@i915_selftest@l...@hangcheck.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#2521]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl3/igt@kms_async_fl...@alternate-sync-async-flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/shard-skl1/igt@kms_async_fl...@alternate-sync-async-flip.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2574]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb2/igt@kms_async_fl...@test-time-stamp.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/shard-tglb8/igt@kms_async_fl...@test-time-stamp.html * igt@kms_ccs@pipe-c-crc-primary-rotation-180: - shard-skl: NOTRUN -> [SKIP][23] ([fdo#109271] / [fdo#111304]) [23]:
[Intel-gfx] [PATCH] drm/i915/uc: Use platform specific defaults for GuC/HuC enabling
From: John Harrison The meaning of 'default' for the enable_guc module parameter has been updated to accurately reflect what is supported on current platforms. So start using the defaults instead of forcing everything off. Signed-off-by: John Harrison CC: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_params.c | 2 +- drivers/gpu/drm/i915/i915_params.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 6939634e56ed..ec1561f5b051 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -160,7 +160,7 @@ i915_param_named_unsafe(edp_vswing, int, 0400, i915_param_named_unsafe(enable_guc, int, 0400, "Enable GuC load for GuC submission and/or HuC load. " "Required functionality can be selected using bitmask values. " - "(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load)"); + "(-1=auto [default], 0=disable, 1=GuC submission, 2=HuC load)"); i915_param_named(guc_log_level, int, 0400, "GuC firmware logging level. Requires GuC to be loaded. " diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index f031966af5b7..3f1b4ad6abdf 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -59,7 +59,7 @@ struct drm_printer; param(int, disable_power_well, -1, 0400) \ param(int, enable_ips, 1, 0600) \ param(int, invert_brightness, 0, 0600) \ - param(int, enable_guc, 0, 0400) \ + param(int, enable_guc, -1, 0400) \ param(int, guc_log_level, -1, 0400) \ param(char *, guc_firmware_path, NULL, 0400) \ param(char *, huc_firmware_path, NULL, 0400) \ -- 2.25.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v12,1/2] drm/i915/display: Support PSR Multiple Instances
== Series Details == Series: series starting with [v12,1/2] drm/i915/display: Support PSR Multiple Instances URL : https://patchwork.freedesktop.org/series/86091/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1328:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v12,1/2] drm/i915/display: Support PSR Multiple Instances
== Series Details == Series: series starting with [v12,1/2] drm/i915/display: Support PSR Multiple Instances URL : https://patchwork.freedesktop.org/series/86091/ State : warning == Summary == $ dim checkpatch origin/drm-tip ca6ecae10b15 drm/i915/display: Support PSR Multiple Instances -:1682: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible side-effects? #1682: FILE: drivers/gpu/drm/i915/display/intel_psr.h:21: +#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && intel_dp->psr.sink_support) total: 0 errors, 0 warnings, 1 checks, 1692 lines checked d3cae8cfe173 drm/i915/display: Support Multiple Transcoders' PSR status on debugfs ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] drm/i915/dp: abstract struct intel_dp pps members to a sub-struct
On Wed, Jan 20, 2021 at 09:25:10PM +0200, Jani Nikula wrote:
> On Wed, 20 Jan 2021, Rodrigo Vivi wrote:
> > On Wed, Jan 20, 2021 at 12:18:33PM +0200, Jani Nikula wrote:
> >> Add some namespacing to highlight what belongs where. No functional
> >> changes.
> >>
> >> Cc: Anshuman Gupta
> >> Signed-off-by: Jani Nikula
> >> ---
> >> .../drm/i915/display/intel_display_debugfs.c | 8 +-
> >> .../drm/i915/display/intel_display_types.h| 61 +++---
> >> drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
> >> drivers/gpu/drm/i915/display/intel_pps.c | 192 +-
> >> 4 files changed, 140 insertions(+), 135 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >> index cd7e5519ee7d..885d2d3c91a3 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >> @@ -2155,13 +2155,13 @@ static int i915_panel_show(struct seq_file *m,
> >> void *data)
> >>return -ENODEV;
> >>
> >>seq_printf(m, "Panel power up delay: %d\n",
> >> - intel_dp->panel_power_up_delay);
> >> + intel_dp->pps.panel_power_up_delay);
> >>seq_printf(m, "Panel power down delay: %d\n",
> >> - intel_dp->panel_power_down_delay);
> >> + intel_dp->pps.panel_power_down_delay);
> >>seq_printf(m, "Backlight on delay: %d\n",
> >> - intel_dp->backlight_on_delay);
> >> + intel_dp->pps.backlight_on_delay);
> >>seq_printf(m, "Backlight off delay: %d\n",
> >> - intel_dp->backlight_off_delay);
> >> + intel_dp->pps.backlight_off_delay);
> >>
> >>return 0;
> >> }
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> >> b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> index b601e804f854..1a9243426a25 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >> @@ -1369,6 +1369,38 @@ struct intel_dp_pcon_frl {
> >>int trained_rate_gbps;
> >> };
> >>
> >> +struct intel_pps {
> >
> > PPS for Panel Power Something (Sequence? Struct?)
>
> Panel Power Sequencer.
7>
> >
> >> + int panel_power_up_delay;
> >
> > if we have panel power already could we remove panel_power_ from
> > here to simply use pps.up_delay ?
>
> IIRC that's the name used in the specs.
>
> Also didn't want to rename any of the fields in this patch because it's
> much easier to review. Can be renamed afterwards.
That's very true.
Reviewed-by: Rodrigo Vivi
>
> BR,
> Jani.
>
> >
> >> + int panel_power_down_delay;
> >> + int panel_power_cycle_delay;
> >> + int backlight_on_delay;
> >> + int backlight_off_delay;
> >> + struct delayed_work panel_vdd_work;
> >> + bool want_panel_vdd;
> >> + unsigned long last_power_on;
> >> + unsigned long last_backlight_off;
> >> + ktime_t panel_power_off_time;
> >> + intel_wakeref_t vdd_wakeref;
> >> +
> >> + /*
> >> + * Pipe whose power sequencer is currently locked into
> >> + * this port. Only relevant on VLV/CHV.
> >> + */
> >> + enum pipe pps_pipe;
> >
> > and pps.pipe
> >
> >> + /*
> >> + * Pipe currently driving the port. Used for preventing
> >> + * the use of the PPS for any pipe currentrly driving
> >> + * external DP as that will mess things up on VLV.
> >> + */
> >> + enum pipe active_pipe;
> >> + /*
> >> + * Set if the sequencer may be reset due to a power transition,
> >> + * requiring a reinitialization. Only relevant on BXT.
> >> + */
> >> + bool pps_reset;
> >
> > and pps.reset ?
> >
> >> + struct edp_power_seq pps_delays;
> >> +};
> >> +
> >> struct intel_dp {
> >>i915_reg_t output_reg;
> >>u32 DP;
> >> @@ -1408,35 +1440,8 @@ struct intel_dp {
> >>struct drm_dp_aux aux;
> >>u32 aux_busy_last_status;
> >>u8 train_set[4];
> >> - int panel_power_up_delay;
> >> - int panel_power_down_delay;
> >> - int panel_power_cycle_delay;
> >> - int backlight_on_delay;
> >> - int backlight_off_delay;
> >> - struct delayed_work panel_vdd_work;
> >> - bool want_panel_vdd;
> >> - unsigned long last_power_on;
> >> - unsigned long last_backlight_off;
> >> - ktime_t panel_power_off_time;
> >> - intel_wakeref_t vdd_wakeref;
> >>
> >> - /*
> >> - * Pipe whose power sequencer is currently locked into
> >> - * this port. Only relevant on VLV/CHV.
> >> - */
> >> - enum pipe pps_pipe;
> >> - /*
> >> - * Pipe currently driving the port. Used for preventing
> >> - * the use of the PPS for any pipe currentrly driving
> >> - * external DP as that will mess things up on VLV.
> >> - */
> >> - enum pipe active_pipe;
> >> - /*
> >> - * Set if the sequencer may be reset due to a power transition,
> >> - * requiring a reinitialization. Only relevant on BXT.
> >> - */
> >> - bool pps_reset;
> >> - struct edp_power_seq pps_delays;
> >> + struct
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915/gt: Do not suspend bonded requests if one hangs
== Series Details ==
Series: series starting with [01/10] drm/i915/gt: Do not suspend bonded
requests if one hangs
URL : https://patchwork.freedesktop.org/series/86088/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19427
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/index.html
New tests
-
New tests have been introduced between CI_DRM_9650 and Patchwork_19427:
### New IGT tests (1) ###
* igt@i915_selftest@live@scheduler:
- Statuses : 32 pass(s)
- Exec time: [0.56, 7.42] s
Known issues
Here are the changes found in Patchwork_19427 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/fi-snb-2520m/igt@amdgpu/amd_pr...@i915-to-amd.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][2] ([fdo#109271]) +30 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html
* igt@prime_self_import@basic-with_one_bo:
- fi-tgl-y: [PASS][4] -> [DMESG-WARN][5] ([i915#402]) +1 similar
issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_one_bo.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/fi-tgl-y/igt@prime_self_import@basic-with_one_bo.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][6] ([i915#1602] / [i915#2029] /
[i915#2369])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/fi-bdw-5557u/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-snb-2600:[DMESG-WARN][7] ([i915#2772]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2520m: [INCOMPLETE][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19427/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9650 -> Patchwork_19427
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19427: 9bf36381a2f6b8f0a1ed4b4955b3a6970d2d94bc @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9bf36381a2f6 drm/i915: Improve DFS for priority inheritance
242ea7da8ef4 drm/i915/selftests: Exercise priority inheritance around an engine
loop
d1f21b1a4125 drm/i915/selftests: Measure set-priority duration
a440718dfe78 drm/i915: Restructure priority inheritance
af4debc42274 drm/i915: Teach the i915_dependency to use a double-lock
d02f5b7f8431 drm/i915: Replace engine->schedule() with a
Re: [Intel-gfx] [PATCH v8 2/3] drm/i915/gem: Add a helper to read data from a GEM object page
On Wed, Jan 20, 2021 at 12:02:49PM +, Chris Wilson wrote:
> Quoting Imre Deak (2021-01-15 19:41:00)
> > Add a simple helper to read data with the CPU from the page of a GEM
> > object. Do the read either via a kmap if the object has struct pages
> > or an iomap otherwise. This is needed by the next patch, reading a u64
> > value from the object (w/o requiring the obj to be mapped to the GPU).
> >
> > Suggested by Chris.
> >
> > v2 (Chris):
> > - Sanitize the type and order of func params.
> > - Avoid consts requiring too many casts.
> > - Use BUG_ON instead of WARN_ON, simplify the conditions.
> > - Fix __iomem sparse errors.
> > - Leave locking/syncing/pinning up to the caller, require only that the
> > caller has pinned the object pages.
> > - Check for iomem backing store before reading via an iomap.
> >
> > Cc: Chris Wilson
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_object.c | 64 ++
> > drivers/gpu/drm/i915/gem/i915_gem_object.h | 8 +++
> > 2 files changed, 72 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> > index 00d24000b5e8..67956a5f5fe3 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> > @@ -32,6 +32,7 @@
> > #include "i915_gem_mman.h"
> > #include "i915_gem_object.h"
> > #include "i915_globals.h"
> > +#include "i915_memcpy.h"
> > #include "i915_trace.h"
> >
> > static struct i915_global_object {
> > @@ -383,6 +384,69 @@ void __i915_gem_object_invalidate_frontbuffer(struct
> > drm_i915_gem_object *obj,
> > }
> > }
> >
> > +static void
> > +i915_gem_object_read_from_page_kmap(struct drm_i915_gem_object *obj, u64
> > offset, void *dst, int size)
> > +{
> > + void *src_map;
> > + void *src_ptr;
> > +
> > + src_map = kmap_atomic(i915_gem_object_get_page(obj, offset >>
> > PAGE_SHIFT));
> > +
> > + src_ptr = src_map + offset_in_page(offset);
> > + if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ))
> > + drm_clflush_virt_range(src_ptr, size);
> > + memcpy(dst, src_ptr, size);
> > +
> > + kunmap_atomic(src_map);
> > +}
> > +
> > +static void
> > +i915_gem_object_read_from_page_iomap(struct drm_i915_gem_object *obj, u64
> > offset, void *dst, int size)
> > +{
> > + void __iomem *src_map;
> > + void __iomem *src_ptr;
> > +
> > + src_map = io_mapping_map_wc(>mm.region->iomap,
> > + i915_gem_object_get_dma_address(obj,
> > offset >> PAGE_SHIFT),
>
> I've been corrected in that one needs to use
>
> dma_addr_t dma =
> i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT);
>
> src_map = io_mapping_map_wc(>mm.region->iomap,
> dma - obj->mm.region->region.start,
Thanks, will fix this. It happened to work on DG1, where region.start is
always 0.
>
> > + PAGE_SIZE);
> > +
> > + src_ptr = src_map + offset_in_page(offset);
> > + if (!i915_memcpy_from_wc(dst, (void __force *)src_ptr, size))
> > + memcpy_fromio(dst, src_ptr, size);
> > +
> > + io_mapping_unmap(src_map);
> > +}
> > +
> > +/**
> > + * i915_gem_object_read_from_page - read data from the page of a GEM object
> > + * @obj: GEM object to read from
> > + * @offset: offset within the object
> > + * @dst: buffer to store the read data
> > + * @size: size to read
> > + *
> > + * Reads data from @obj at the specified offset. The requested region to
> > read
> > + * from can't cross a page boundary. The caller must ensure that @obj pages
> > + * are pinned and that @obj is synced wrt. any related writes.
> > + *
> > + * Returns 0 on sucess or -ENODEV if the type of @obj's backing store is
> > + * unsupported.
> > + */
> > +int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, u64
> > offset, void *dst, int size)
> > +{
> > + GEM_BUG_ON(offset >= obj->base.size);
> > + GEM_BUG_ON(offset_in_page(offset) > PAGE_SIZE - size);
> > + GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
> > +
> > + if (i915_gem_object_has_struct_page(obj))
> > + i915_gem_object_read_from_page_kmap(obj, offset, dst, size);
> > + else if (i915_gem_object_has_iomem(obj))
> > + i915_gem_object_read_from_page_iomap(obj, offset, dst,
> > size);
> > + else
> > + return -ENODEV;
>
> Otherwise, that looks to be as simple as possible (offloading the setup
> to the caller where it is already done), so
>
> Reviewed-by: Chris Wilson
>
> with the dma offset before Matthew corrects me, again.
> -Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/region: don't leak the object on error
== Series Details == Series: drm/i915/region: don't leak the object on error URL : https://patchwork.freedesktop.org/series/86077/ State : success == Summary == CI Bug Log - changes from CI_DRM_9650_full -> Patchwork_19423_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19423_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([i915#1373]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb8/igt@gem_ctx_isolation@preservation...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/shard-iclb3/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_persistence@engines-mixed: - shard-hsw: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/shard-hsw5/igt@gem_ctx_persiste...@engines-mixed.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-kbl: [PASS][4] -> [SKIP][5] ([fdo#109271]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl6/igt@gem_exec_fair@basic-f...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/shard-kbl7/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb8/igt@gem_exec_fair@basic-p...@vecs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/shard-tglb7/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][9] ([i915#2389]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/shard-iclb4/igt@gem_exec_reloc@basic-wide-act...@vcs1.html * igt@gem_exec_schedule@u-fairslice@vcs0: - shard-skl: [PASS][10] -> [DMESG-WARN][11] ([i915#1610] / [i915#2803]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl10/igt@gem_exec_schedule@u-fairsl...@vcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/shard-skl3/igt@gem_exec_schedule@u-fairsl...@vcs0.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-skl: [PASS][12] -> [FAIL][13] ([i915#644]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl5/igt@gem_pp...@flink-and-close-vma-leak.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/shard-skl5/igt@gem_pp...@flink-and-close-vma-leak.html * igt@gem_render_copy@y-tiled-to-vebox-linear: - shard-hsw: NOTRUN -> [SKIP][14] ([fdo#109271]) +124 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/shard-hsw5/igt@gem_render_c...@y-tiled-to-vebox-linear.html * igt@gen3_mixed_blits: - shard-kbl: NOTRUN -> [SKIP][15] ([fdo#109271]) +29 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/shard-kbl3/igt@gen3_mixed_blits.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#658]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/shard-kbl3/igt@i915_pm...@dc3co-vpb-simulation.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][17] -> [FAIL][18] ([i915#2597]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb2/igt@kms_async_fl...@test-time-stamp.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/shard-tglb5/igt@kms_async_fl...@test-time-stamp.html * igt@kms_chamelium@hdmi-hpd-with-enabled-mode: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/shard-kbl3/igt@kms_chamel...@hdmi-hpd-with-enabled-mode.html * igt@kms_chamelium@vga-frame-dump: - shard-snb: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/shard-snb6/igt@kms_chamel...@vga-frame-dump.html * igt@kms_color_chamelium@pipe-a-ctm-green-to-red: - shard-glk: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/shard-glk9/igt@kms_color_chamel...@pipe-a-ctm-green-to-red.html * igt@kms_color_chamelium@pipe-d-ctm-green-to-red: - shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827]) +3 similar issues [22]:
Re: [Intel-gfx] [PATCH 1/4] drm/i915: Nuke not needed members of dram_info
On Wed, 2021-01-20 at 10:52 -0800, Lucas De Marchi wrote:
> On Wed, Jan 20, 2021 at 10:42:46AM -0800, Jose Souza wrote:
> > On Wed, 2021-01-20 at 10:31 -0800, Lucas De Marchi wrote:
> > > On Wed, Jan 20, 2021 at 07:16:08AM -0800, Jose Souza wrote:
> > > > Valid, ranks and bandwidth_kbps are set into dram_info but are not
> > > > used anywhere else so nuking it.
> > > >
> > > > Signed-off-by: José Roberto de Souza
> > > > ---
> > > > drivers/gpu/drm/i915/i915_drv.c | 4 +--
> > > > drivers/gpu/drm/i915/i915_drv.h | 3 --
> > > > drivers/gpu/drm/i915/intel_dram.c | 47 +++
> > > > 3 files changed, 12 insertions(+), 42 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > > b/drivers/gpu/drm/i915/i915_drv.c
> > > > index f5666b44ea9d..a1cc60de99f0 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > @@ -609,8 +609,8 @@ static int i915_driver_hw_probe(struct
> > > > drm_i915_private *dev_priv)
> > > >
> > > > intel_opregion_setup(dev_priv);
> > > > /*
> > > > -* Fill the dram structure to get the system raw bandwidth and
> > > > -* dram info. This will be used for memory latency calculation.
> > > > +* Fill the dram structure to get the system dram info. This
> > > > will be
> > > > +* used for memory latency calculation.
> > > > */
> > > > intel_dram_detect(dev_priv);
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > > b/drivers/gpu/drm/i915/i915_drv.h
> > > > index 8376cff5ba86..250e92910fa1 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > @@ -1134,11 +1134,8 @@ struct drm_i915_private {
> > > > } wm;
> > > >
> > > > struct dram_info {
> > > > - bool valid;
> > > > bool is_16gb_dimm;
> > > > u8 num_channels;
> > > > - u8 ranks;
> > > > - u32 bandwidth_kbps;
> > > > bool symmetric_memory;
> > > > enum intel_dram_type {
> > > > INTEL_DRAM_UNKNOWN,
> > > > diff --git a/drivers/gpu/drm/i915/intel_dram.c
> > > > b/drivers/gpu/drm/i915/intel_dram.c
> > > > index 4754296a250e..694fbd8c9cd4 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dram.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dram.c
> > > > @@ -201,17 +201,7 @@ skl_dram_get_channels_info(struct drm_i915_private
> > > > *i915)
> > > > return -EINVAL;
> > > > }
> > > >
> > > > - /*
> > > > -* If any of the channel is single rank channel, worst case
> > > > output
> > > > -* will be same as if single rank memory, so consider single
> > > > rank
> > > > -* memory.
> > > > -*/
> > > > - if (ch0.ranks == 1 || ch1.ranks == 1)
> > > > - dram_info->ranks = 1;
> > > > - else
> > > > - dram_info->ranks = max(ch0.ranks, ch1.ranks);
> > > > -
> > > > - if (dram_info->ranks == 0) {
> > > > + if (ch0.ranks == 0 && ch1.ranks == 0) {
> > >
> > > previously if any of them were != 0, we would not fall here.
> >
> > This is the same behavior.
>
> indeed, I misread the condition
>
> >
> > >
> > >
> > > > drm_info(>drm, "couldn't get memory rank
> > > > information\n");
> > > > return -EINVAL;
> > > > }
> > > > @@ -269,16 +259,12 @@ skl_get_dram_info(struct drm_i915_private *i915)
> > > > mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
> > > > SKL_MEMORY_FREQ_MULTIPLIER_HZ,
> > > > 1000);
> > > >
> > > > - dram_info->bandwidth_kbps = dram_info->num_channels *
> > > > - mem_freq_khz * 8;
> > > > -
> > > > - if (dram_info->bandwidth_kbps == 0) {
> > > > + if (dram_info->num_channels * mem_freq_khz == 0) {
> > > > drm_info(>drm,
> > > > "Couldn't get system memory bandwidth\n");
> > > > return -EINVAL;
> > > > }
> > > >
> > > > - dram_info->valid = true;
> > > > return 0;
> > > > }
> > > >
> > > > @@ -365,7 +351,7 @@ static int bxt_get_dram_info(struct
> > > > drm_i915_private *i915)
> > > > struct dram_info *dram_info = >dram_info;
> > > > u32 dram_channels;
> > > > u32 mem_freq_khz, val;
> > > > - u8 num_active_channels;
> > > > + u8 num_active_channels, valid_ranks = 0;
> > > > int i;
> > > >
> > > > val = intel_uncore_read(>uncore,
> > > > BXT_P_CR_MC_BIOS_REQ_0_0_0);
> > > > @@ -375,10 +361,7 @@ static int bxt_get_dram_info(struct
> > > > drm_i915_private *i915)
> > > > dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
> > > > num_active_channels = hweight32(dram_channels);
> > > >
> > > > - /* Each active bit represents 4-byte channel */
> > > > -
Re: [Intel-gfx] [PATCH 3/4] drm/i915/dp: abstract struct intel_dp pps members to a sub-struct
On Wed, 20 Jan 2021, Rodrigo Vivi wrote:
> On Wed, Jan 20, 2021 at 12:18:33PM +0200, Jani Nikula wrote:
>> Add some namespacing to highlight what belongs where. No functional
>> changes.
>>
>> Cc: Anshuman Gupta
>> Signed-off-by: Jani Nikula
>> ---
>> .../drm/i915/display/intel_display_debugfs.c | 8 +-
>> .../drm/i915/display/intel_display_types.h| 61 +++---
>> drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
>> drivers/gpu/drm/i915/display/intel_pps.c | 192 +-
>> 4 files changed, 140 insertions(+), 135 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index cd7e5519ee7d..885d2d3c91a3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -2155,13 +2155,13 @@ static int i915_panel_show(struct seq_file *m, void
>> *data)
>> return -ENODEV;
>>
>> seq_printf(m, "Panel power up delay: %d\n",
>> - intel_dp->panel_power_up_delay);
>> + intel_dp->pps.panel_power_up_delay);
>> seq_printf(m, "Panel power down delay: %d\n",
>> - intel_dp->panel_power_down_delay);
>> + intel_dp->pps.panel_power_down_delay);
>> seq_printf(m, "Backlight on delay: %d\n",
>> - intel_dp->backlight_on_delay);
>> + intel_dp->pps.backlight_on_delay);
>> seq_printf(m, "Backlight off delay: %d\n",
>> - intel_dp->backlight_off_delay);
>> + intel_dp->pps.backlight_off_delay);
>>
>> return 0;
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index b601e804f854..1a9243426a25 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1369,6 +1369,38 @@ struct intel_dp_pcon_frl {
>> int trained_rate_gbps;
>> };
>>
>> +struct intel_pps {
>
> PPS for Panel Power Something (Sequence? Struct?)
Panel Power Sequencer.
>
>> +int panel_power_up_delay;
>
> if we have panel power already could we remove panel_power_ from
> here to simply use pps.up_delay ?
IIRC that's the name used in the specs.
Also didn't want to rename any of the fields in this patch because it's
much easier to review. Can be renamed afterwards.
BR,
Jani.
>
>> +int panel_power_down_delay;
>> +int panel_power_cycle_delay;
>> +int backlight_on_delay;
>> +int backlight_off_delay;
>> +struct delayed_work panel_vdd_work;
>> +bool want_panel_vdd;
>> +unsigned long last_power_on;
>> +unsigned long last_backlight_off;
>> +ktime_t panel_power_off_time;
>> +intel_wakeref_t vdd_wakeref;
>> +
>> +/*
>> + * Pipe whose power sequencer is currently locked into
>> + * this port. Only relevant on VLV/CHV.
>> + */
>> +enum pipe pps_pipe;
>
> and pps.pipe
>
>> +/*
>> + * Pipe currently driving the port. Used for preventing
>> + * the use of the PPS for any pipe currentrly driving
>> + * external DP as that will mess things up on VLV.
>> + */
>> +enum pipe active_pipe;
>> +/*
>> + * Set if the sequencer may be reset due to a power transition,
>> + * requiring a reinitialization. Only relevant on BXT.
>> + */
>> +bool pps_reset;
>
> and pps.reset ?
>
>> +struct edp_power_seq pps_delays;
>> +};
>> +
>> struct intel_dp {
>> i915_reg_t output_reg;
>> u32 DP;
>> @@ -1408,35 +1440,8 @@ struct intel_dp {
>> struct drm_dp_aux aux;
>> u32 aux_busy_last_status;
>> u8 train_set[4];
>> -int panel_power_up_delay;
>> -int panel_power_down_delay;
>> -int panel_power_cycle_delay;
>> -int backlight_on_delay;
>> -int backlight_off_delay;
>> -struct delayed_work panel_vdd_work;
>> -bool want_panel_vdd;
>> -unsigned long last_power_on;
>> -unsigned long last_backlight_off;
>> -ktime_t panel_power_off_time;
>> -intel_wakeref_t vdd_wakeref;
>>
>> -/*
>> - * Pipe whose power sequencer is currently locked into
>> - * this port. Only relevant on VLV/CHV.
>> - */
>> -enum pipe pps_pipe;
>> -/*
>> - * Pipe currently driving the port. Used for preventing
>> - * the use of the PPS for any pipe currentrly driving
>> - * external DP as that will mess things up on VLV.
>> - */
>> -enum pipe active_pipe;
>> -/*
>> - * Set if the sequencer may be reset due to a power transition,
>> - * requiring a reinitialization. Only relevant on BXT.
>> - */
>> -bool pps_reset;
>> -struct edp_power_seq pps_delays;
>> +struct intel_pps pps;
>>
>> bool can_mst; /* this port supports mst */
>> bool is_mst;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 8b9c20555f0e..d815087a26aa 100644
>> ---
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/10] drm/i915/gt: Do not suspend bonded requests if one hangs
== Series Details == Series: series starting with [01/10] drm/i915/gt: Do not suspend bonded requests if one hangs URL : https://patchwork.freedesktop.org/series/86088/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1328:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Unify the sanity checks for the buf trans tables
On Mon, 2020-12-07 at 22:35 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Get rid of the "I like my random new style best" approach and unify
> the handling for the DDI buf trans table sanity checks once again.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 23 ++-
> 1 file changed, 10 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c3a15ce66478..68693d4538e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2631,15 +2631,11 @@ static void icl_ddi_combo_vswing_program(struct
> intel_encoder *encoder,
> ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state,
> _entries);
> else
> ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state,
> _entries);
> - if (!ddi_translations)
> - return;
>
>
>
>
> - if (level >= n_entries) {
> - drm_dbg_kms(_priv->drm,
> - "DDI translation not found for level %d. Using %d
> instead.",
> - level, n_entries - 1);
> + if (drm_WARN_ON_ONCE(_priv->drm, !ddi_translations))
> + return;
> + if (drm_WARN_ON_ONCE(_priv->drm, level >= n_entries))
> level = n_entries - 1;
> - }
>
>
>
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> @@ -2760,12 +2756,11 @@ static void icl_mg_phy_ddi_vswing_sequence(struct
> intel_encoder *encoder,
> u32 val;
>
>
>
>
> ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state,
> _entries);
> - if (level >= n_entries) {
> - drm_dbg_kms(_priv->drm,
> - "DDI translation not found for level %d. Using %d
> instead.",
> - level, n_entries - 1);
> +
> + if (drm_WARN_ON_ONCE(_priv->drm, !ddi_translations))
> + return;
> + if (drm_WARN_ON_ONCE(_priv->drm, level >= n_entries))
> level = n_entries - 1;
> - }
>
>
>
>
> /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
> for (ln = 0; ln < 2; ln++) {
> @@ -2897,7 +2892,9 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder
> *encoder,
>
>
>
>
> ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state,
> _entries);
>
>
>
>
> - if (level >= n_entries)
> + if (drm_WARN_ON_ONCE(_priv->drm, !ddi_translations))
> + return;
> + if (drm_WARN_ON_ONCE(_priv->drm, level >= n_entries))
> level = n_entries - 1;
>
>
>
>
> dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915/gt: Do not suspend bonded requests if one hangs
== Series Details ==
Series: series starting with [01/10] drm/i915/gt: Do not suspend bonded
requests if one hangs
URL : https://patchwork.freedesktop.org/series/86088/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ed0915405628 drm/i915/gt: Do not suspend bonded requests if one hangs
89f5522aeb8f drm/i915/gt: Skip over completed active execlists, again
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#10:
Referenecs: 35f3fd8182ba ("drm/i915/execlists: Workaround switching back to a
completed context")
-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 35f3fd8182ba
("drm/i915/execlists: Workaround switching back to a completed context")'
#10:
Referenecs: 35f3fd8182ba ("drm/i915/execlists: Workaround switching back to a
completed context")
-:11: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 8ab3a3812aa9 ("drm/i915/gt:
Incrementally check for rewinding")'
#11:
References: 8ab3a3812aa9 ("drm/i915/gt: Incrementally check for rewinding")
total: 2 errors, 1 warnings, 0 checks, 72 lines checked
7e2e3df4ad78 drm/i915: Strip out internal priorities
ab6bc4b70663 drm/i915: Remove I915_USER_PRIORITY_SHIFT
d02f5b7f8431 drm/i915: Replace engine->schedule() with a known request operation
af4debc42274 drm/i915: Teach the i915_dependency to use a double-lock
a440718dfe78 drm/i915: Restructure priority inheritance
d1f21b1a4125 drm/i915/selftests: Measure set-priority duration
-:52: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#52:
new file mode 100644
-:434: WARNING:LINE_SPACING: Missing a blank line after declarations
#434: FILE: drivers/gpu/drm/i915/selftests/i915_scheduler.c:378:
+ struct igt_spinner spin;
+ I915_RND_STATE(prng);
total: 0 errors, 2 warnings, 0 checks, 702 lines checked
242ea7da8ef4 drm/i915/selftests: Exercise priority inheritance around an engine
loop
9bf36381a2f6 drm/i915: Improve DFS for priority inheritance
___
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix ICL MG PHY vswing handling
On Mon, 2020-12-07 at 22:35 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The MH PHY vswing table does have all the entries these days. Get
> rid of the old hacks in the code which claim otherwise.
>
> This hack was totally bogus anyway. The correct way to handle the
> lack of those two entries would have been to declare our max
> vswing and pre-emph to both be level 2.
Reviewed-by: José Roberto de Souza
>
> Cc: José Roberto de Souza
> Cc: Clinton Taylor
> Fixes: 9f7ffa297978 ("drm/i915/tc/icl: Update TC vswing tables")
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 5193473c838c..c3a15ce66478 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2760,12 +2760,11 @@ static void icl_mg_phy_ddi_vswing_sequence(struct
> intel_encoder *encoder,
> u32 val;
>
>
>
>
> ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state,
> _entries);
> - /* The table does not have values for level 3 and level 9. */
> - if (level >= n_entries || level == 3 || level == 9) {
> + if (level >= n_entries) {
> drm_dbg_kms(_priv->drm,
> "DDI translation not found for level %d. Using %d
> instead.",
> - level, n_entries - 2);
> - level = n_entries - 2;
> + level, n_entries - 1);
> + level = n_entries - 1;
> }
>
>
>
>
> /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Do not suspend bonded requests if one hangs
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Do not suspend bonded requests
if one hangs
URL : https://patchwork.freedesktop.org/series/86087/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19426
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/index.html
Known issues
Here are the changes found in Patchwork_19426 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/fi-snb-2520m/igt@amdgpu/amd_pr...@i915-to-amd.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][2] ([fdo#109271]) +30 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html
* igt@vgem_basic@create:
- fi-tgl-y: [PASS][4] -> [DMESG-WARN][5] ([i915#402])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@vgem_ba...@create.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/fi-tgl-y/igt@vgem_ba...@create.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-snb-2600:[DMESG-WARN][6] ([i915#2772]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2520m: [INCOMPLETE][8] -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][10] ([i915#402]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9650 -> Patchwork_19426
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19426: 63e0ca6b8dc8f97bb9e2509ce1f4d091c3985cde @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
63e0ca6b8dc8 drm/i915/gt: Skip over completed active execlists, again
69e82f4a4b40 drm/i915/gt: Do not suspend bonded requests if one hangs
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19426/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/6] drm/i915/gem: Almagamate clflushes on suspend (rev2)
== Series Details == Series: series starting with [CI,1/6] drm/i915/gem: Almagamate clflushes on suspend (rev2) URL : https://patchwork.freedesktop.org/series/86058/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9650_full -> Patchwork_19421_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19421_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19421_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19421_full: ### IGT changes ### Possible regressions * igt@sysfs_timeslice_duration@timeout@bcs0: - shard-skl: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/shard-skl6/igt@sysfs_timeslice_duration@time...@bcs0.html Known issues Here are the changes found in Patchwork_19421_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@close-replace-race: - shard-glk: [PASS][2] -> [TIMEOUT][3] ([i915#2918]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk6/igt@gem_ctx_persiste...@close-replace-race.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/shard-glk4/igt@gem_ctx_persiste...@close-replace-race.html * igt@gem_ctx_persistence@legacy-engines-mixed-process: - shard-hsw: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/shard-hsw6/igt@gem_ctx_persiste...@legacy-engines-mixed-process.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl4/igt@gem_exec_fair@basic-n...@vecs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/shard-kbl2/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][7] ([i915#2842]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb8/igt@gem_exec_fair@basic-p...@vecs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/shard-tglb1/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_schedule@u-fairslice-all: - shard-iclb: [PASS][10] -> [DMESG-WARN][11] ([i915#2803]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb4/igt@gem_exec_sched...@u-fairslice-all.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/shard-iclb3/igt@gem_exec_sched...@u-fairslice-all.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-skl: [PASS][12] -> [DMESG-WARN][13] ([i915#1610] / [i915#2803]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl10/igt@gem_exec_schedule@u-fairsl...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/shard-skl8/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_render_copy@y-tiled-to-vebox-linear: - shard-hsw: NOTRUN -> [SKIP][14] ([fdo#109271]) +222 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/shard-hsw6/igt@gem_render_c...@y-tiled-to-vebox-linear.html * igt@gen3_mixed_blits: - shard-kbl: NOTRUN -> [SKIP][15] ([fdo#109271]) +29 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/shard-kbl4/igt@gen3_mixed_blits.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#658]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/shard-kbl4/igt@i915_pm...@dc3co-vpb-simulation.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#2521]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl3/igt@kms_async_fl...@alternate-sync-async-flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/shard-skl5/igt@kms_async_fl...@alternate-sync-async-flip.html * igt@kms_chamelium@common-hpd-after-suspend: - shard-hsw: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +18 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/shard-hsw6/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-with-enabled-mode: - shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] /
Re: [Intel-gfx] [PATCH] drm/i915/gem: Allow importing of shmemfs objects into any device
On Wed, 20 Jan 2021 at 15:40, Chris Wilson wrote: > > If we import a shmemfs object between devices, for example from > Tigerlake to DG1, we can simply reuse the native object and its backing > store. Hmmm interesting, so does that include re-using the actual sg mapping for the backing pages? Does that work out-of-the-box between different devices assuming we have iommu enabled? > > Suggested-by: Imre Deak > Signed-off-by: Chris Wilson > Cc: Matthew Auld > Cc: Imre Deak > --- > drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c > b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c > index 04e9c04545ad..4816f08c4009 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c > @@ -242,6 +242,13 @@ struct drm_gem_object *i915_gem_prime_import(struct > drm_device *dev, > */ > return _gem_object_get(obj)->base; > } > + > + /* > +* If the object is in plain system memory, we can reuse the > +* same backing store in any device. > +*/ > + if (i915_gem_object_is_shmem(obj)) > + return _gem_object_get(obj)->base; > } > > /* need to attach */ > -- > 2.20.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/msm/dp: fix build after dp quirk helper change
== Series Details ==
Series: drm/msm/dp: fix build after dp quirk helper change
URL : https://patchwork.freedesktop.org/series/86079/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19424
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/index.html
Known issues
Here are the changes found in Patchwork_19424 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@requests:
- fi-kbl-soraka: [PASS][1] -> [INCOMPLETE][2] ([i915#2782])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-kbl-soraka/igt@i915_selftest@l...@requests.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/fi-kbl-soraka/igt@i915_selftest@l...@requests.html
* igt@prime_vgem@basic-fence-flip:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar
issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_v...@basic-fence-flip.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/fi-tgl-y/igt@prime_v...@basic-fence-flip.html
* igt@runner@aborted:
- fi-kbl-soraka: NOTRUN -> [FAIL][5] ([i915#1436] / [i915#2295])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/fi-kbl-soraka/igt@run...@aborted.html
Possible fixes
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][6] ([i915#402]) -> [PASS][7] +1 similar
issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9650 -> Patchwork_19424
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19424: 85c10923c0f6e8422213191d2d877615c0a65fe8 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
85c10923c0f6 drm/msm/dp: fix build after dp quirk helper change
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19424/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/i915/dp: split out aux functionality to intel_dp_aux.c
On Wed, Jan 20, 2021 at 12:18:34PM +0200, Jani Nikula wrote:
> Split out the DP aux functionality to a new intel_dp_aux.[ch]. This is a
> surprisingly clean cut.
I had wondered about this split in the past... surprisingly clean cut indeed...
>
> v2:
> - Remove intel_dp_pack_aux declaration from intel_dp.h (Anshuman)
> - Fixed some whitespace/comment checkpatch warnings
>
> Cc: Anshuman Gupta
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 680 +--
> drivers/gpu/drm/i915/display/intel_dp.h | 1 -
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 692
> drivers/gpu/drm/i915/display/intel_dp_aux.h | 18 +
> drivers/gpu/drm/i915/display/intel_psr.c| 3 +-
> 6 files changed, 714 insertions(+), 681 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 006dec54408d..ea1cc5736049 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -243,6 +243,7 @@ i915-y += \
> display/intel_crt.o \
> display/intel_ddi.o \
> display/intel_dp.o \
> + display/intel_dp_aux.o \
> display/intel_dp_aux_backlight.o \
> display/intel_dp_hdcp.o \
> display/intel_dp_link_training.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index d815087a26aa..8979996f1747 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -41,13 +41,13 @@
>
> #include "i915_debugfs.h"
> #include "i915_drv.h"
> -#include "i915_trace.h"
> #include "intel_atomic.h"
> #include "intel_audio.h"
> #include "intel_connector.h"
> #include "intel_ddi.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> +#include "intel_dp_aux.h"
> #include "intel_dp_link_training.h"
> #include "intel_dp_mst.h"
> #include "intel_dpio_phy.h"
> @@ -862,684 +862,6 @@ intel_dp_mode_valid(struct drm_connector *connector,
> return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
> }
>
> -u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
> -{
> - int i;
> - u32 v = 0;
> -
> - if (src_bytes > 4)
> - src_bytes = 4;
> - for (i = 0; i < src_bytes; i++)
> - v |= ((u32)src[i]) << ((3 - i) * 8);
> - return v;
> -}
> -
> -static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
> -{
> - int i;
> - if (dst_bytes > 4)
> - dst_bytes = 4;
> - for (i = 0; i < dst_bytes; i++)
> - dst[i] = src >> ((3-i) * 8);
> -}
> -
> -static u32
> -intel_dp_aux_wait_done(struct intel_dp *intel_dp)
> -{
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
> - const unsigned int timeout_ms = 10;
> - u32 status;
> - bool done;
> -
> -#define C (((status = intel_uncore_read_notrace(>uncore, ch_ctl)) &
> DP_AUX_CH_CTL_SEND_BUSY) == 0)
> - done = wait_event_timeout(i915->gmbus_wait_queue, C,
> - msecs_to_jiffies_timeout(timeout_ms));
> -
> - /* just trace the final value */
> - trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
> -
> - if (!done)
> - drm_err(>drm,
> - "%s: did not complete or timeout within %ums (status
> 0x%08x)\n",
> - intel_dp->aux.name, timeout_ms, status);
> -#undef C
> -
> - return status;
> -}
> -
> -static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -
> - if (index)
> - return 0;
> -
> - /*
> - * The clock divider is based off the hrawclk, and would like to run at
> - * 2MHz. So, take the hrawclk value and divide by 2000 and use that
> - */
> - return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
> -}
> -
> -static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> -{
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - u32 freq;
> -
> - if (index)
> - return 0;
> -
> - /*
> - * The clock divider is based off the cdclk or PCH rawclk, and would
> - * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
> - * divide by 2000 and use that
> - */
> - if (dig_port->aux_ch == AUX_CH_A)
> - freq = dev_priv->cdclk.hw.cdclk;
> - else
> - freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
> - return DIV_ROUND_CLOSEST(freq, 2000);
> -}
> -
> -static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> -{
> - struct
Re: [Intel-gfx] [PATCH 3/4] drm/i915/dp: abstract struct intel_dp pps members to a sub-struct
On Wed, Jan 20, 2021 at 12:18:33PM +0200, Jani Nikula wrote:
> Add some namespacing to highlight what belongs where. No functional
> changes.
>
> Cc: Anshuman Gupta
> Signed-off-by: Jani Nikula
> ---
> .../drm/i915/display/intel_display_debugfs.c | 8 +-
> .../drm/i915/display/intel_display_types.h| 61 +++---
> drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
> drivers/gpu/drm/i915/display/intel_pps.c | 192 +-
> 4 files changed, 140 insertions(+), 135 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index cd7e5519ee7d..885d2d3c91a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2155,13 +2155,13 @@ static int i915_panel_show(struct seq_file *m, void
> *data)
> return -ENODEV;
>
> seq_printf(m, "Panel power up delay: %d\n",
> -intel_dp->panel_power_up_delay);
> +intel_dp->pps.panel_power_up_delay);
> seq_printf(m, "Panel power down delay: %d\n",
> -intel_dp->panel_power_down_delay);
> +intel_dp->pps.panel_power_down_delay);
> seq_printf(m, "Backlight on delay: %d\n",
> -intel_dp->backlight_on_delay);
> +intel_dp->pps.backlight_on_delay);
> seq_printf(m, "Backlight off delay: %d\n",
> -intel_dp->backlight_off_delay);
> +intel_dp->pps.backlight_off_delay);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b601e804f854..1a9243426a25 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1369,6 +1369,38 @@ struct intel_dp_pcon_frl {
> int trained_rate_gbps;
> };
>
> +struct intel_pps {
PPS for Panel Power Something (Sequence? Struct?)
> + int panel_power_up_delay;
if we have panel power already could we remove panel_power_ from
here to simply use pps.up_delay ?
> + int panel_power_down_delay;
> + int panel_power_cycle_delay;
> + int backlight_on_delay;
> + int backlight_off_delay;
> + struct delayed_work panel_vdd_work;
> + bool want_panel_vdd;
> + unsigned long last_power_on;
> + unsigned long last_backlight_off;
> + ktime_t panel_power_off_time;
> + intel_wakeref_t vdd_wakeref;
> +
> + /*
> + * Pipe whose power sequencer is currently locked into
> + * this port. Only relevant on VLV/CHV.
> + */
> + enum pipe pps_pipe;
and pps.pipe
> + /*
> + * Pipe currently driving the port. Used for preventing
> + * the use of the PPS for any pipe currentrly driving
> + * external DP as that will mess things up on VLV.
> + */
> + enum pipe active_pipe;
> + /*
> + * Set if the sequencer may be reset due to a power transition,
> + * requiring a reinitialization. Only relevant on BXT.
> + */
> + bool pps_reset;
and pps.reset ?
> + struct edp_power_seq pps_delays;
> +};
> +
> struct intel_dp {
> i915_reg_t output_reg;
> u32 DP;
> @@ -1408,35 +1440,8 @@ struct intel_dp {
> struct drm_dp_aux aux;
> u32 aux_busy_last_status;
> u8 train_set[4];
> - int panel_power_up_delay;
> - int panel_power_down_delay;
> - int panel_power_cycle_delay;
> - int backlight_on_delay;
> - int backlight_off_delay;
> - struct delayed_work panel_vdd_work;
> - bool want_panel_vdd;
> - unsigned long last_power_on;
> - unsigned long last_backlight_off;
> - ktime_t panel_power_off_time;
> - intel_wakeref_t vdd_wakeref;
>
> - /*
> - * Pipe whose power sequencer is currently locked into
> - * this port. Only relevant on VLV/CHV.
> - */
> - enum pipe pps_pipe;
> - /*
> - * Pipe currently driving the port. Used for preventing
> - * the use of the PPS for any pipe currentrly driving
> - * external DP as that will mess things up on VLV.
> - */
> - enum pipe active_pipe;
> - /*
> - * Set if the sequencer may be reset due to a power transition,
> - * requiring a reinitialization. Only relevant on BXT.
> - */
> - bool pps_reset;
> - struct edp_power_seq pps_delays;
> + struct intel_pps pps;
>
> bool can_mst; /* this port supports mst */
> bool is_mst;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8b9c20555f0e..d815087a26aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4129,7 +4129,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
> intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
> }
>
> -
Re: [Intel-gfx] [PATCH] drm/msm/dp: fix build after dp quirk helper change
Reviewed-by: Lyude Paul
On Wed, 2021-01-20 at 13:07 +0200, Jani Nikula wrote:
> Commit 7c553f8b5a7d ("drm/dp: Revert "drm/dp: Introduce EDID-based
> quirks"") removed drm_dp_get_edid_quirks() and changed the signature of
> drm_dp_has_quirk() while they were still being used in msm. Fix the
> breakage. Functionally, removing the EDID-based quirks has no impact on
> msm.
>
> [The above commit was merged to drm-intel-next; make two wrongs a right
> by merging this fix through drm-intel-next as well.]
>
> Reported-by: Stephen Rothwell
> References:
> http://lore.kernel.org/r/20210120105715.4391d...@canb.auug.org.au
> Fixes: 7c553f8b5a7d ("drm/dp: Revert "drm/dp: Introduce EDID-based quirks"")
> Cc: Lyude Paul
> Acked-by: Daniel Vetter
> Cc: Rob Clark
> Cc: Sean Paul
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Jani Nikula
>
> ---
>
> Note: I admit to not even build testing this one. I'd need a config,
> possibly also a toolchain setup for that.
> ---
> drivers/gpu/drm/msm/dp/dp_ctrl.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> index e3462f5d96d7..36b39c381b3f 100644
> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> @@ -1420,16 +1420,14 @@ void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl)
> static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl)
> {
> u8 *dpcd = ctrl->panel->dpcd;
> - u32 edid_quirks = 0;
>
> - edid_quirks = drm_dp_get_edid_quirks(ctrl->panel->edid);
> /*
> * For better interop experience, used a fixed NVID=0x8000
> * whenever connected to a VGA dongle downstream.
> */
> if (drm_dp_is_branch(dpcd))
> - return (drm_dp_has_quirk(>panel->desc, edid_quirks,
> - DP_DPCD_QUIRK_CONSTANT_N));
> + return (drm_dp_has_quirk(>panel->desc,
> + DP_DPCD_QUIRK_CONSTANT_N));
>
> return false;
> }
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
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Re: [Intel-gfx] [CI 1/2] drm/i915/tgl: Use TGL stepping info for applying WAs
Both patches applied to topic/adl-s-enabling branch.
Lucas De Marchi
On Tue, Jan 19, 2021 at 11:29:30AM -0800, Lucas De Marchi wrote:
From: Aditya Swarup
TGL adds another level of indirection for applying WA based on stepping
information rather than PCI REVID. So change TGL_REVID enum into
stepping enum and use PCI REVID as index into revid to stepping table to
fetch correct display and GT stepping for application of WAs as
suggested by Matt Roper.
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: José Roberto de Souza
Signed-off-by: Aditya Swarup
Reviewed-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
.../drm/i915/display/intel_display_power.c| 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 4 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 +-
drivers/gpu/drm/i915/i915_drv.h | 50 +--
drivers/gpu/drm/i915/intel_pm.c | 2 +-
6 files changed, 43 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index c11c37c65d86..708f0b7e0990 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5340,7 +5340,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private
*dev_priv)
int config, i;
if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
- IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
+ IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
/* Wa_1409767108:tgl,dg1 */
table = wa_1409767108_buddy_page_masks;
else
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 1e6c1fa59d4a..909bdd7ff4ff 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
if (dev_priv->psr.psr2_sel_fetch_enabled) {
/* WA 1408330847 */
- if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+ if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK,
@@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
/* WA 1408330847 */
if (dev_priv->psr.psr2_sel_fetch_enabled &&
- (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
+ (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index adc5f088d458..ff7c6203eaf9 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -3059,7 +3059,7 @@ static bool gen12_plane_supports_mc_ccs(struct
drm_i915_private *dev_priv,
{
/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
- IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
+ IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
return false;
return plane_id < PLANE_SPRITE4;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3fdcd5ff71dd..c7420a2d2ca3 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -71,17 +71,17 @@ const struct i915_rev_steppings kbl_revids[] = {
[7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
};
-const struct i915_rev_steppings tgl_uy_revids[] = {
- [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
- [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
- [2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
- [3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
+const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
+ [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
+ [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
+ [2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
+ [3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 },
};
/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW
*/
-const struct i915_rev_steppings tgl_revids[] = {
- [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
- [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping =
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/msm/dp: fix build after dp quirk helper change
== Series Details ==
Series: drm/msm/dp: fix build after dp quirk helper change
URL : https://patchwork.freedesktop.org/series/86079/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
85c10923c0f6 drm/msm/dp: fix build after dp quirk helper change
-:6: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'Commit 7c553f8b5a7d ("drm/dp: Revert
"drm/dp: Introduce EDID-based quirks"")'
#6:
Commit 7c553f8b5a7d ("drm/dp: Revert "drm/dp: Introduce EDID-based
-:16: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#16:
References: http://lore.kernel.org/r/20210120105715.4391d...@canb.auug.org.au
total: 1 errors, 1 warnings, 0 checks, 18 lines checked
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/region: don't leak the object on error
== Series Details ==
Series: drm/i915/region: don't leak the object on error
URL : https://patchwork.freedesktop.org/series/86077/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19423
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/index.html
Known issues
Here are the changes found in Patchwork_19423 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/fi-snb-2520m/igt@amdgpu/amd_pr...@i915-to-amd.html
* igt@fbdev@read:
- fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +2 similar
issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@fb...@read.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/fi-tgl-y/igt@fb...@read.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271]) +30 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][5] -> [DMESG-WARN][6] ([i915#1982] /
[i915#262])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
- fi-cml-u2: [PASS][7] -> [FAIL][8] ([i915#1161] / [i915#262])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][10] ([i915#1602] / [i915#2029] /
[i915#2369])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/fi-bdw-5557u/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-snb-2600:[DMESG-WARN][11] ([i915#2772]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2520m: [INCOMPLETE][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][15] ([i915#402]) -> [PASS][16] +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19423/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9650 -> Patchwork_19423
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
[Intel-gfx] ✓ Fi.CI.BAT: success for HDCP misc fixes (rev2)
== Series Details ==
Series: HDCP misc fixes (rev2)
URL : https://patchwork.freedesktop.org/series/86025/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19422
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19422/index.html
Known issues
Here are the changes found in Patchwork_19422 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@memory-alloc:
- fi-tgl-y: NOTRUN -> [SKIP][1] ([fdo#109315] / [i915#2575]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19422/fi-tgl-y/igt@amdgpu/amd_ba...@memory-alloc.html
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19422/fi-snb-2520m/igt@amdgpu/amd_pr...@i915-to-amd.html
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +2 similar
issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19422/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][5] -> [FAIL][6] ([i915#2203] / [i915#579])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-kbl-guc/igt@i915_pm_...@module-reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19422/fi-kbl-guc/igt@i915_pm_...@module-reload.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][7] ([fdo#109271]) +30 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19422/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19422/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-snb-2600:[DMESG-WARN][9] ([i915#2772]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19422/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2520m: [INCOMPLETE][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19422/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][13] ([i915#402]) -> [PASS][14] +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19422/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9650 -> Patchwork_19422
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19422: e03462940f0c1769c2f0adaf2e31a5d71667ecbe @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e03462940f0c drm/i915/hdcp: Fix uninitialized symbol
84fcb9750e20 drm/i915/hdcp: Fix WARN_ON(data->k > INTEL_NUM_PIPES)
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19422/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915/pps: refactor init abstractions
== Series Details == Series: series starting with [1/4] drm/i915/pps: refactor init abstractions URL : https://patchwork.freedesktop.org/series/86076/ State : success == Summary == CI Bug Log - changes from CI_DRM_9650_full -> Patchwork_19420_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19420_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@close-replace-race: - shard-glk: [PASS][1] -> [TIMEOUT][2] ([i915#2918]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk6/igt@gem_ctx_persiste...@close-replace-race.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-glk5/igt@gem_ctx_persiste...@close-replace-race.html * igt@gem_ctx_persistence@engines-mixed: - shard-hsw: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-hsw6/igt@gem_ctx_persiste...@engines-mixed.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2842]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_reloc@basic-many-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][9] ([i915#2389]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-iclb2/igt@gem_exec_reloc@basic-many-act...@vcs1.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-skl: [PASS][10] -> [DMESG-WARN][11] ([i915#1610] / [i915#2803]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl10/igt@gem_exec_schedule@u-fairsl...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl7/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-skl: [PASS][12] -> [FAIL][13] ([i915#644]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl5/igt@gem_pp...@flink-and-close-vma-leak.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl4/igt@gem_pp...@flink-and-close-vma-leak.html * igt@gem_render_copy@y-tiled-to-vebox-linear: - shard-hsw: NOTRUN -> [SKIP][14] ([fdo#109271]) +124 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-hsw6/igt@gem_render_c...@y-tiled-to-vebox-linear.html * igt@gem_vm_create@destroy-race: - shard-tglb: [PASS][15] -> [TIMEOUT][16] ([i915#2795]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb5/igt@gem_vm_cre...@destroy-race.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-tglb7/igt@gem_vm_cre...@destroy-race.html * igt@gen3_mixed_blits: - shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271]) +29 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-kbl1/igt@gen3_mixed_blits.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#658]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-kbl1/igt@i915_pm...@dc3co-vpb-simulation.html * igt@kms_chamelium@hdmi-hpd-with-enabled-mode: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-kbl1/igt@kms_chamel...@hdmi-hpd-with-enabled-mode.html * igt@kms_chamelium@vga-frame-dump: - shard-snb: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-snb4/igt@kms_chamel...@vga-frame-dump.html * igt@kms_color@pipe-b-ctm-0-5: - shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl6/igt@kms_co...@pipe-b-ctm-0-5.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/shard-skl9/igt@kms_co...@pipe-b-ctm-0-5.html * igt@kms_color_chamelium@pipe-a-ctm-green-to-red: - shard-glk: NOTRUN -> [SKIP][23] ([fdo#109271] /
[Intel-gfx] [PATCH] kbuild: use always-y instead of extra-y
As commit d0e628cd817f ("kbuild: doc: clarify the difference between
extra-y and always-y") explained, extra-y should be used for listing
the prerequsites of vmlinux. always-y is a better fix here.
Signed-off-by: Masahiro Yamada
---
Documentation/devicetree/bindings/Makefile | 8
drivers/gpu/drm/i915/Makefile | 2 +-
scripts/Makefile.lib | 10 +-
scripts/gdb/linux/Makefile | 2 +-
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/Makefile
b/Documentation/devicetree/bindings/Makefile
index 8f2b054bec5a..90fcad98984d 100644
--- a/Documentation/devicetree/bindings/Makefile
+++ b/Documentation/devicetree/bindings/Makefile
@@ -78,10 +78,10 @@ $(obj)/processed-schema.json: $(DT_SCHEMA_FILES)
check_dtschema_version FORCE
endif
-extra-$(CHECK_DT_BINDING) += processed-schema-examples.json
-extra-$(CHECK_DTBS) += processed-schema.json
-extra-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dts,
$(DT_SCHEMA_FILES))
-extra-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dt.yaml,
$(DT_SCHEMA_FILES))
+always-$(CHECK_DT_BINDING) += processed-schema-examples.json
+always-$(CHECK_DTBS) += processed-schema.json
+always-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dts,
$(DT_SCHEMA_FILES))
+always-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dt.yaml,
$(DT_SCHEMA_FILES))
# Hack: avoid 'Argument list too long' error for 'make clean'. Remove most of
# build artifacts here before they are processed by scripts/Makefile.clean
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6d9e81ea67f4..938221894d0c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -294,7 +294,7 @@ no-header-test := \
gvt/mpt.h \
gvt/scheduler.h
-extra-$(CONFIG_DRM_I915_WERROR) += \
+always-$(CONFIG_DRM_I915_WERROR) += \
$(patsubst %.h,%.hdrtest, $(filter-out $(no-header-test), \
$(shell cd $(srctree)/$(src) && find * -name '*.h')))
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 4612a887f28e..b8e587a17dcc 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -64,12 +64,12 @@ always-y += $(userprogs-always-y) $(userprogs-always-m)
# DTB
# If CONFIG_OF_ALL_DTBS is enabled, all DT blobs are built
-extra-y+= $(dtb-y)
-extra-$(CONFIG_OF_ALL_DTBS)+= $(dtb-)
+always-y += $(dtb-y)
+always-$(CONFIG_OF_ALL_DTBS) += $(dtb-)
ifneq ($(CHECK_DTBS),)
-extra-y += $(patsubst %.dtb,%.dt.yaml, $(dtb-y))
-extra-$(CONFIG_OF_ALL_DTBS) += $(patsubst %.dtb,%.dt.yaml, $(dtb-))
+always-y += $(patsubst %.dtb,%.dt.yaml, $(dtb-y))
+always-$(CONFIG_OF_ALL_DTBS) += $(patsubst %.dtb,%.dt.yaml, $(dtb-))
endif
# Add subdir path
@@ -230,7 +230,7 @@ $(obj)/%: $(src)/%_shipped
# target: source(s) FORCE
# $(if_changed,ld/objcopy/gzip)
#
-# and add target to extra-y so that we know we have to
+# and add target to 'targets' so that we know we have to
# read in the saved command line
# Linking
diff --git a/scripts/gdb/linux/Makefile b/scripts/gdb/linux/Makefile
index 124755087510..13903073cbff 100644
--- a/scripts/gdb/linux/Makefile
+++ b/scripts/gdb/linux/Makefile
@@ -18,7 +18,7 @@ quiet_cmd_gen_constants_py = GEN $@
$(CPP) -E -x c -P $(c_flags) $< > $@ ;\
sed -i '1,//d;' $@
-extra-y += constants.py
+always-y += constants.py
$(obj)/constants.py: $(src)/constants.py.in FORCE
$(call if_changed_dep,gen_constants_py)
--
2.27.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] gvt-gt-next
On Wed, 2021-01-20 at 14:21 +0200, Joonas Lahtinen wrote: > Quoting Zhenyu Wang (2021-01-18 07:07:39) > > > > Hi, > > > > This is GVT next for 5.12 against drm-intel-gt-next which is mostly > > for cmd parser enhancement which adds extra check on register load > > depending on initial context and handles vGPU register state > > accordingly. > > I think we were bit inconclusive on this last time. > > Even if this does not have any dependency to drm-intel-gt-next I can > pull this to drm-intel-gt-next. The only caveat is that for any - > fixes, > there needs to be a backmerge to drm-intel-next. > > Not sure if this is a problem. Do we want to make it a recurring > practice > to backmerge drm-intel-gt-next into drm-intel-next after it lands in > drm-next? > > So to recap: Do we want to pull to drm-intel-next whenever there are > no > dependencies to drm-intel-gt-next, to avoid a backmerge? It looks better indeed... but how to proceed when we have dependencies? merge on both sides like the topic branches? > Or do we want > to always do a backmerge in anticipation of -fixes. > > Regards, Joonas > > > Thanks. > > -- > > The following changes since commit > > fe7bcfaeb2b775f257348dc7b935f8e80eef3e7d: > > > > drm/i915/gt: Refactor heartbeat request construction and > > submission (2020-12-24 18:07:26 +) > > > > are available in the Git repository at: > > > > https://github.com/intel/gvt-linux tags/gvt-gt-next-2021-01-18 > > > > for you to fetch changes up to > > 02dd2b12a685944c4d52c569d05f636372a7b6c7: > > > > drm/i915/gvt: unify lri cmd handler and mmio handlers (2020-12-25 > > 11:16:32 +0800) > > > > > > gvt-gt-next-2021-01-18 > > > > - GVT cmd parser enhancement against guest context (Yan) > > > > > > Yan Zhao (11): > > drm/i915/gvt: parse init context to update cmd accessible reg > > whitelist > > drm/i915/gvt: scan VM ctx pages > > drm/i915/gvt: filter cmds "srm" and "lrm" in cmd_handler > > drm/i915/gvt: filter cmds "lrr-src" and "lrr-dst" in > > cmd_handler > > drm/i915/gvt: filter cmd "pipe-ctrl" in cmd_handler > > drm/i915/gvt: export find_mmio_info > > drm/i915/gvt: make width of mmio_attribute bigger > > drm/i915/gvt: introduce a new flag F_CMD_WRITE_PATCH > > drm/i915/gvt: statically set F_CMD_WRITE_PATCH flag > > drm/i915/gvt: update F_CMD_WRITE_PATCH flag when parsing init > > ctx > > drm/i915/gvt: unify lri cmd handler and mmio handlers > > > > drivers/gpu/drm/i915/gvt/cmd_parser.c | 335 > > +++--- > > drivers/gpu/drm/i915/gvt/cmd_parser.h | 4 + > > drivers/gpu/drm/i915/gvt/gvt.h | 37 +++- > > drivers/gpu/drm/i915/gvt/handlers.c | 15 +- > > drivers/gpu/drm/i915/gvt/mmio.h | 3 + > > drivers/gpu/drm/i915/gvt/reg.h | 2 + > > drivers/gpu/drm/i915/gvt/scheduler.c | 22 ++- > > drivers/gpu/drm/i915/gvt/vgpu.c | 4 +- > > 8 files changed, 339 insertions(+), 83 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/6] drm/i915/gem: Almagamate clflushes on suspend (rev2)
== Series Details ==
Series: series starting with [CI,1/6] drm/i915/gem: Almagamate clflushes on
suspend (rev2)
URL : https://patchwork.freedesktop.org/series/86058/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19421
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/index.html
Known issues
Here are the changes found in Patchwork_19421 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/fi-snb-2520m/igt@amdgpu/amd_pr...@i915-to-amd.html
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +2 similar
issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271]) +30 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-snb-2600:[DMESG-WARN][6] ([i915#2772]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2520m: [INCOMPLETE][8] -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [DMESG-WARN][10] ([i915#402]) -> [PASS][11] +1
similar issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9650 -> Patchwork_19421
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19421: 1f9edc822fe4456ce4f480af732f9011435da3e0 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1f9edc822fe4 drm/i915/gem: Drop lru bumping on display unpinning
afb981966ab6 drm/i915/gem: Protect used framebuffers from casual eviction
3b52d3cc067b drm/i915/gem: Use shrinkable status for unknown swizzle quirks
daadc72e5f33 drm/i915/gem: Move stolen node into GEM object union
4af3d682302e drm/i915/gem: Almagamate clflushes on freeze
12342e09d0d8 drm/i915/gem: Almagamate clflushes on suspend
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19421/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gem: Allow importing of shmemfs objects into any device
If we import a shmemfs object between devices, for example from Tigerlake to DG1, we can simply reuse the native object and its backing store. Suggested-by: Imre Deak Signed-off-by: Chris Wilson Cc: Matthew Auld Cc: Imre Deak --- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c index 04e9c04545ad..4816f08c4009 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c @@ -242,6 +242,13 @@ struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, */ return _gem_object_get(obj)->base; } + + /* +* If the object is in plain system memory, we can reuse the +* same backing store in any device. +*/ + if (i915_gem_object_is_shmem(obj)) + return _gem_object_get(obj)->base; } /* need to attach */ -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/6] drm/i915/gem: Almagamate clflushes on suspend (rev2)
== Series Details == Series: series starting with [CI,1/6] drm/i915/gem: Almagamate clflushes on suspend (rev2) URL : https://patchwork.freedesktop.org/series/86058/ State : warning == Summary == $ dim checkpatch origin/drm-tip 12342e09d0d8 drm/i915/gem: Almagamate clflushes on suspend -:24: WARNING:INCLUDE_LINUX: Use #include instead of #24: FILE: drivers/gpu/drm/i915/gem/i915_gem_pm.c:15: +#include total: 0 errors, 1 warnings, 0 checks, 68 lines checked 4af3d682302e drm/i915/gem: Almagamate clflushes on freeze daadc72e5f33 drm/i915/gem: Move stolen node into GEM object union 3b52d3cc067b drm/i915/gem: Use shrinkable status for unknown swizzle quirks afb981966ab6 drm/i915/gem: Protect used framebuffers from casual eviction 1f9edc822fe4 drm/i915/gem: Drop lru bumping on display unpinning ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v12,1/2] drm/i915/display: Support PSR Multiple Instances
== Series Details == Series: series starting with [v12,1/2] drm/i915/display: Support PSR Multiple Instances URL : https://patchwork.freedesktop.org/series/86072/ State : success == Summary == CI Bug Log - changes from CI_DRM_9650_full -> Patchwork_19419_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19419_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@close-replace-race: - shard-glk: [PASS][1] -> [TIMEOUT][2] ([i915#2918]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk6/igt@gem_ctx_persiste...@close-replace-race.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/shard-glk5/igt@gem_ctx_persiste...@close-replace-race.html * igt@gem_ctx_persistence@legacy-engines-hostile-preempt: - shard-hsw: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/shard-hsw5/igt@gem_ctx_persiste...@legacy-engines-hostile-preempt.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-kbl: [PASS][4] -> [FAIL][5] ([i915#2842]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl1/igt@gem_exec_fair@basic-none-...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/shard-kbl2/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [PASS][7] -> [SKIP][8] ([fdo#109271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-tglb8/igt@gem_exec_fair@basic-p...@vecs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/shard-tglb3/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_schedule@u-fairslice-all: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1610]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-apl6/igt@gem_exec_sched...@u-fairslice-all.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/shard-apl6/igt@gem_exec_sched...@u-fairslice-all.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1610] / [i915#2803]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl10/igt@gem_exec_schedule@u-fairsl...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/shard-skl7/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_exec_whisper@basic-normal: - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#118] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-glk9/igt@gem_exec_whis...@basic-normal.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/shard-glk9/igt@gem_exec_whis...@basic-normal.html * igt@gem_exec_whisper@basic-queues-forked: - shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([i915#1895] / [i915#2405]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-iclb3/igt@gem_exec_whis...@basic-queues-forked.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/shard-iclb3/igt@gem_exec_whis...@basic-queues-forked.html * igt@gen3_mixed_blits: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271]) +29 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/shard-kbl7/igt@gen3_mixed_blits.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#658]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/shard-kbl7/igt@i915_pm...@dc3co-vpb-simulation.html * igt@i915_selftest@live@hangcheck: - shard-hsw: NOTRUN -> [INCOMPLETE][21] ([i915#2782]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/shard-hsw4/igt@i915_selftest@l...@hangcheck.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [PASS][22] -> [FAIL][23] ([i915#2521]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/shard-skl3/igt@kms_async_fl...@alternate-sync-async-flip.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/shard-skl2/igt@kms_async_fl...@alternate-sync-async-flip.html * igt@kms_chamelium@hdmi-hpd-with-enabled-mode: - shard-kbl: NOTRUN
[Intel-gfx] [PATCH 4/4] drm/i915: Rename is_16gb_dimm to wm_lv_0_adjust_needed
As it now it is always required for GEN12+ the is_16gb_dimm name
do not make sense for GEN12+.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_dram.c | 10 +-
drivers/gpu/drm/i915/intel_pm.c | 2 +-
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a2ae21082b34..adc008c65b14 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1134,7 +1134,7 @@ struct drm_i915_private {
} wm;
struct dram_info {
- bool is_16gb_dimm;
+ bool wm_lv_0_adjust_needed;
u8 num_channels;
bool symmetric_memory;
enum intel_dram_type {
diff --git a/drivers/gpu/drm/i915/intel_dram.c
b/drivers/gpu/drm/i915/intel_dram.c
index 4871d48589f9..a5850f0f25aa 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -207,7 +207,7 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
return -EINVAL;
}
- dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
+ dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
dram_info->symmetric_memory = intel_is_dram_symmetric(, );
@@ -475,7 +475,7 @@ static int gen11_get_dram_info(struct drm_i915_private
*i915)
return ret;
} else {
/* Always needed for GEN12+ */
- i915->dram_info.is_16gb_dimm = true;
+ i915->dram_info.wm_lv_0_adjust_needed = true;
}
return icl_pcode_read_mem_global_info(i915);
@@ -491,7 +491,7 @@ int intel_dram_detect(struct drm_i915_private *i915)
* This is only used for the level 0 watermark latency
* w/a which does not apply to bxt/glk.
*/
- dram_info->is_16gb_dimm = !IS_GEN9_LP(i915);
+ dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);
if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915))
return 0;
@@ -510,8 +510,8 @@ int intel_dram_detect(struct drm_i915_private *i915)
drm_dbg_kms(>drm, "DRAM channels: %u\n", dram_info->num_channels);
- drm_dbg_kms(>drm, "DRAM 16Gb DIMMs: %s\n",
- yesno(dram_info->is_16gb_dimm));
+ drm_dbg_kms(>drm, "Watermark level 0 adjustment needed: %s\n",
+ yesno(dram_info->wm_lv_0_adjust_needed));
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 992fce8b8d13..f778aae19f82 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2930,7 +2930,7 @@ static void intel_read_wm_latency(struct drm_i915_private
*dev_priv,
* any underrun. If not able to get Dimm info assume 16GB dimm
* to avoid any underrun.
*/
- if (dev_priv->dram_info.is_16gb_dimm)
+ if (dev_priv->dram_info.wm_lv_0_adjust_needed)
wm[0] += 1;
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
--
2.30.0
___
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[Intel-gfx] [PATCH 3/4] drm/i915: Fail driver probe when unable to load DRAM information
DRAM information is required to properly program display.
Before "drm/i915/gen11+: Only load DRAM information from pcode" we
were failing driver load if unable to fetch DRAM information from
pcode form GEN11+ but we should also extend it to GEN9 plaforms.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 6 +-
drivers/gpu/drm/i915/intel_dram.c | 13 +
drivers/gpu/drm/i915/intel_dram.h | 2 +-
3 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 66f763fe7a83..6bfcd3ee6c66 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -615,12 +615,16 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
* Fill the dram structure to get the system dram info. This will be
* used for memory latency calculation.
*/
- intel_dram_detect(dev_priv);
+ ret = intel_dram_detect(dev_priv);
+ if (ret)
+ goto err_dram;
intel_bw_init_hw(dev_priv);
return 0;
+err_dram:
+ intel_gvt_driver_remove(dev_priv);
err_msi:
if (pdev->msi_enabled)
pci_disable_msi(pdev);
diff --git a/drivers/gpu/drm/i915/intel_dram.c
b/drivers/gpu/drm/i915/intel_dram.c
index 1298823c957c..4871d48589f9 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -481,7 +481,7 @@ static int gen11_get_dram_info(struct drm_i915_private
*i915)
return icl_pcode_read_mem_global_info(i915);
}
-void intel_dram_detect(struct drm_i915_private *i915)
+int intel_dram_detect(struct drm_i915_private *i915)
{
struct dram_info *dram_info = >dram_info;
int ret;
@@ -494,7 +494,7 @@ void intel_dram_detect(struct drm_i915_private *i915)
dram_info->is_16gb_dimm = !IS_GEN9_LP(i915);
if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915))
- return;
+ return 0;
if (INTEL_GEN(i915) >= 11)
ret = gen11_get_dram_info(i915);
@@ -502,13 +502,18 @@ void intel_dram_detect(struct drm_i915_private *i915)
ret = bxt_get_dram_info(i915);
else
ret = skl_get_dram_info(i915);
- if (ret)
- return;
+
+ if (ret) {
+ drm_warn(>drm, "Unable to load dram information\n");
+ return ret;
+ }
drm_dbg_kms(>drm, "DRAM channels: %u\n", dram_info->num_channels);
drm_dbg_kms(>drm, "DRAM 16Gb DIMMs: %s\n",
yesno(dram_info->is_16gb_dimm));
+
+ return 0;
}
static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
diff --git a/drivers/gpu/drm/i915/intel_dram.h
b/drivers/gpu/drm/i915/intel_dram.h
index 4ba13c13162c..2a0f283b1a1d 100644
--- a/drivers/gpu/drm/i915/intel_dram.h
+++ b/drivers/gpu/drm/i915/intel_dram.h
@@ -9,6 +9,6 @@
struct drm_i915_private;
void intel_dram_edram_detect(struct drm_i915_private *i915);
-void intel_dram_detect(struct drm_i915_private *i915);
+int intel_dram_detect(struct drm_i915_private *i915);
#endif /* __INTEL_DRAM_H__ */
--
2.30.0
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[Intel-gfx] [PATCH 2/4] drm/i915/gen11+: Only load DRAM information from pcode
Up to now we were reading some DRAM information from MCHBAR register
and from pcode what is already not good but some GEN12(TGL-H and ADL-S)
platforms have MCHBAR DRAM information in different offsets.
This was notified to HW team that decided that the best alternative is
always apply the 16gb_dimm watermark adjustment for GEN12+ platforms
and read the remaning DRAM information needed to other display
programming from pcode.
So here moving the DRAM pcode function to intel_dram.c, removing
the duplicated fields from intel_qgv_info, setting and using
information from dram_info.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bw.c | 98 +
drivers/gpu/drm/i915/i915_drv.c | 5 +-
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_dram.c | 77 ++-
4 files changed, 97 insertions(+), 84 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index bd060404d249..1368bd96ed73 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -19,77 +19,9 @@ struct intel_qgv_point {
struct intel_qgv_info {
struct intel_qgv_point points[I915_NUM_QGV_POINTS];
- u8 num_points;
- u8 num_channels;
u8 t_bl;
- enum intel_dram_type dram_type;
};
-static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv,
- struct intel_qgv_info *qi)
-{
- u32 val = 0;
- int ret;
-
- ret = sandybridge_pcode_read(dev_priv,
-ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
-ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
-, NULL);
- if (ret)
- return ret;
-
- if (IS_GEN(dev_priv, 12)) {
- switch (val & 0xf) {
- case 0:
- qi->dram_type = INTEL_DRAM_DDR4;
- break;
- case 3:
- qi->dram_type = INTEL_DRAM_LPDDR4;
- break;
- case 4:
- qi->dram_type = INTEL_DRAM_DDR3;
- break;
- case 5:
- qi->dram_type = INTEL_DRAM_LPDDR3;
- break;
- default:
- MISSING_CASE(val & 0xf);
- break;
- }
- } else if (IS_GEN(dev_priv, 11)) {
- switch (val & 0xf) {
- case 0:
- qi->dram_type = INTEL_DRAM_DDR4;
- break;
- case 1:
- qi->dram_type = INTEL_DRAM_DDR3;
- break;
- case 2:
- qi->dram_type = INTEL_DRAM_LPDDR3;
- break;
- case 3:
- qi->dram_type = INTEL_DRAM_LPDDR4;
- break;
- default:
- MISSING_CASE(val & 0xf);
- break;
- }
- } else {
- MISSING_CASE(INTEL_GEN(dev_priv));
- qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */
- }
-
- qi->num_channels = (val & 0xf0) >> 4;
- qi->num_points = (val & 0xf00) >> 8;
-
- if (IS_GEN(dev_priv, 12))
- qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16;
- else if (IS_GEN(dev_priv, 11))
- qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
-
- return 0;
-}
-
static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
struct intel_qgv_point *sp,
int point)
@@ -139,17 +71,19 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private
*dev_priv,
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi)
{
+ struct dram_info *dram_info = _priv->dram_info;
int i, ret;
- ret = icl_pcode_read_mem_global_info(dev_priv, qi);
- if (ret)
- return ret;
+ if (IS_GEN(dev_priv, 12))
+ qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 16;
+ else if (IS_GEN(dev_priv, 11))
+ qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
if (drm_WARN_ON(_priv->drm,
- qi->num_points > ARRAY_SIZE(qi->points)))
- qi->num_points = ARRAY_SIZE(qi->points);
+ dram_info->qgv_points > ARRAY_SIZE(qi->points)))
+ dram_info->qgv_points = ARRAY_SIZE(qi->points);
- for (i = 0; i < qi->num_points; i++) {
+ for (i = 0; i < dram_info->qgv_points; i++) {
struct intel_qgv_point *sp = >points[i];
ret =
[Intel-gfx] [PATCH 1/4] drm/i915: Nuke not needed members of dram_info
Valid, ranks and bandwidth_kbps are set into dram_info but are not
used anywhere else so nuking it.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 4 +--
drivers/gpu/drm/i915/i915_drv.h | 3 --
drivers/gpu/drm/i915/intel_dram.c | 47 +++
3 files changed, 12 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f5666b44ea9d..a1cc60de99f0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -609,8 +609,8 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
intel_opregion_setup(dev_priv);
/*
-* Fill the dram structure to get the system raw bandwidth and
-* dram info. This will be used for memory latency calculation.
+* Fill the dram structure to get the system dram info. This will be
+* used for memory latency calculation.
*/
intel_dram_detect(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8376cff5ba86..250e92910fa1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1134,11 +1134,8 @@ struct drm_i915_private {
} wm;
struct dram_info {
- bool valid;
bool is_16gb_dimm;
u8 num_channels;
- u8 ranks;
- u32 bandwidth_kbps;
bool symmetric_memory;
enum intel_dram_type {
INTEL_DRAM_UNKNOWN,
diff --git a/drivers/gpu/drm/i915/intel_dram.c
b/drivers/gpu/drm/i915/intel_dram.c
index 4754296a250e..694fbd8c9cd4 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -201,17 +201,7 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
return -EINVAL;
}
- /*
-* If any of the channel is single rank channel, worst case output
-* will be same as if single rank memory, so consider single rank
-* memory.
-*/
- if (ch0.ranks == 1 || ch1.ranks == 1)
- dram_info->ranks = 1;
- else
- dram_info->ranks = max(ch0.ranks, ch1.ranks);
-
- if (dram_info->ranks == 0) {
+ if (ch0.ranks == 0 && ch1.ranks == 0) {
drm_info(>drm, "couldn't get memory rank information\n");
return -EINVAL;
}
@@ -269,16 +259,12 @@ skl_get_dram_info(struct drm_i915_private *i915)
mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
- dram_info->bandwidth_kbps = dram_info->num_channels *
- mem_freq_khz * 8;
-
- if (dram_info->bandwidth_kbps == 0) {
+ if (dram_info->num_channels * mem_freq_khz == 0) {
drm_info(>drm,
"Couldn't get system memory bandwidth\n");
return -EINVAL;
}
- dram_info->valid = true;
return 0;
}
@@ -365,7 +351,7 @@ static int bxt_get_dram_info(struct drm_i915_private *i915)
struct dram_info *dram_info = >dram_info;
u32 dram_channels;
u32 mem_freq_khz, val;
- u8 num_active_channels;
+ u8 num_active_channels, valid_ranks = 0;
int i;
val = intel_uncore_read(>uncore, BXT_P_CR_MC_BIOS_REQ_0_0_0);
@@ -375,10 +361,7 @@ static int bxt_get_dram_info(struct drm_i915_private *i915)
dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
num_active_channels = hweight32(dram_channels);
- /* Each active bit represents 4-byte channel */
- dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
-
- if (dram_info->bandwidth_kbps == 0) {
+ if (mem_freq_khz * num_active_channels == 0) {
drm_info(>drm,
"Couldn't get system memory bandwidth\n");
return -EINVAL;
@@ -410,27 +393,18 @@ static int bxt_get_dram_info(struct drm_i915_private
*i915)
dimm.size, dimm.width, dimm.ranks,
intel_dram_type_str(type));
- /*
-* If any of the channel is single rank channel,
-* worst case output will be same as if single rank
-* memory, so consider single rank memory.
-*/
- if (dram_info->ranks == 0)
- dram_info->ranks = dimm.ranks;
- else if (dimm.ranks == 1)
- dram_info->ranks = 1;
+ if (valid_ranks == 0)
+ valid_ranks = dimm.ranks;
if (type != INTEL_DRAM_UNKNOWN)
dram_info->type = type;
}
- if (dram_info->type == INTEL_DRAM_UNKNOWN || dram_info->ranks == 0) {
+ if (dram_info->type == INTEL_DRAM_UNKNOWN || valid_ranks == 0) {
drm_info(>drm,
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/pps: refactor init abstractions
== Series Details ==
Series: series starting with [1/4] drm/i915/pps: refactor init abstractions
URL : https://patchwork.freedesktop.org/series/86076/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19420
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/index.html
Known issues
Here are the changes found in Patchwork_19420 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/fi-snb-2520m/igt@amdgpu/amd_pr...@i915-to-amd.html
* igt@fbdev@read:
- fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +1 similar
issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@fb...@read.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/fi-tgl-y/igt@fb...@read.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][4] -> [FAIL][5] ([i915#2203] / [i915#579])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-kbl-guc/igt@i915_pm_...@module-reload.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/fi-kbl-guc/igt@i915_pm_...@module-reload.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][6] ([fdo#109271]) +30 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-snb-2600:[DMESG-WARN][8] ([i915#2772]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
* igt@gem_render_tiled_blits@basic:
- fi-tgl-y: [DMESG-WARN][10] ([i915#402]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@gem_render_tiled_bl...@basic.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/fi-tgl-y/igt@gem_render_tiled_bl...@basic.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2520m: [INCOMPLETE][12] -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9650 -> Patchwork_19420
CI-20190529: 20190529
CI_DRM_9650: 3f989d1bb4cfd91e25549f9fd7a750412581dcc4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5960: ace82fcd5f3623f8dde7c220a825873dc53dfae4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19420: c56c8a0d76770a79728ee5f8fb534cc88d3070e9 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c56c8a0d7677 drm/i915/dp: split out aux functionality to intel_dp_aux.c
6c274e339aa3 drm/i915/dp: abstract struct intel_dp pps members to a sub-struct
b59f412b98d3 drm/i915/pps: move pps code over from intel_display.c and refactor
3210f99b0871 drm/i915/pps: refactor init abstractions
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19420/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v12 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
In order to support the PSR state of each transcoder, it adds
i915_psr_status to sub-directory of each transcoder.
v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
permissions '0444'
v5: Addressed JJani Nikula's review comments
- Remove checking of Gen12 for i915_psr_status.
- Add check of HAS_PSR()
- Remove meaningless check routine.
Signed-off-by: Gwan-gyeong Mun
Cc: José Roberto de Souza
Cc: Jani Nikula
Cc: Anshuman Gupta
Reviewed-by: Anshuman Gupta
---
.../gpu/drm/i915/display/intel_display_debugfs.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 2b1708e13cbc..100c4519925e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -2224,6 +2224,16 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
+static int i915_psr_status_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct intel_dp *intel_dp =
+ intel_attached_dp(to_intel_connector(connector));
+
+ return intel_psr_status(m, intel_dp);
+}
+DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
+
#define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
seq_puts(m, "LPSP: incapable\n"))
@@ -2399,6 +2409,12 @@ int intel_connector_debugfs_add(struct drm_connector
*connector)
connector, _psr_sink_status_fops);
}
+ if (HAS_PSR(dev_priv) &&
+ connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+ debugfs_create_file("i915_psr_status", 0444, root,
+ connector, _psr_status_fops);
+ }
+
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v12 1/2] drm/i915/display: Support PSR Multiple Instances
It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt handling routine for supporting
multiple transcoders. But it does not change the scenario and timing of
enabling and disabling PSR. And it not support multiple pipes with
a single transcoder PSR case yet.
v2: Fix indentation and add comments
v3: Remove Blank line
v4: Rebased
v5: Rebased and Addressed Anshuman's review comment.
- Move calling of intel_psr_init() to intel_dp_init_connector()
v6: Address Anshuman's review comments
- Remove wrong comments and add comments for a limit of supporting of
a single pipe PSR
v7: Update intel_psr_compute_config() for supporting multiple transcoder
PSR on BDW+
v8: Address Anshuman's review comments
- Replace DRM_DEBUG_KMS with drm_dbg_kms() / DRM_WARN with drm_warn()
v9: Fix commit message
v10: Rebased
v11: Address Jose's review comment.
- Reorder calling order of intel_psr2_program_trans_man_trk_ctl().
- In order to reduce changes keep the old name for drm_i915_private.
- Change restrictions of multiple instances of PSR.
v12: Address Jose's review comment.
- Change the calling of intel_psr2_program_trans_man_trk_ctl() into
commit_pipe_config().
- Change a checking order of CAN_PSR() and connector_status to original
on i915_psr_sink_status_show().
- Drop unneeded intel_dp_update_pipe() function.
- In order to wait a specific encoder which belong to crtc_state on
intel_psr_wait_for_idle(), add checking of encoder.
- Add an whitespace to comments.
Signed-off-by: Gwan-gyeong Mun
Cc: José Roberto de Souza
Cc: Juha-Pekka Heikkila
Cc: Anshuman Gupta
Reviewed-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 2 -
.../drm/i915/display/intel_display_debugfs.c | 105 +++-
.../drm/i915/display/intel_display_types.h| 38 ++
drivers/gpu/drm/i915/display/intel_dp.c | 10 +-
drivers/gpu/drm/i915/display/intel_psr.c | 584 ++
drivers/gpu/drm/i915/display/intel_psr.h | 11 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 38 --
drivers/gpu/drm/i915/i915_irq.c | 49 +-
9 files changed, 476 insertions(+), 367 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 7373f54b216e..75c1c5139965 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14059,8 +14059,6 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_dvo_init(dev_priv);
}
- intel_psr_init(dev_priv);
-
for_each_intel_encoder(_priv->drm, encoder) {
encoder->base.possible_crtcs =
intel_encoder_possible_crtcs(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cd7e5519ee7d..2b1708e13cbc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -249,12 +249,11 @@ static int i915_psr_sink_status_show(struct seq_file *m,
void *data)
"sink internal error",
};
struct drm_connector *connector = m->private;
- struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_dp *intel_dp =
intel_attached_dp(to_intel_connector(connector));
int ret;
- if (!CAN_PSR(dev_priv)) {
+ if (!CAN_PSR(intel_dp)) {
seq_puts(m, "PSR Unsupported\n");
return -ENODEV;
}
@@ -280,12 +279,13 @@ static int i915_psr_sink_status_show(struct seq_file *m,
void *data)
DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
static void
-psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
+psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
{
u32 val, status_val;
const char *status = "unknown";
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- if (dev_priv->psr.psr2_enabled) {
+ if (intel_dp->psr.psr2_enabled) {
static const char * const live_status[] = {
"IDLE",
"CAPTURE",
@@ -300,7 +300,7 @@ psr_source_status(struct drm_i915_private *dev_priv, struct
seq_file *m)
"TG_ON"
};
val = intel_de_read(dev_priv,
- EDP_PSR2_STATUS(dev_priv->psr.transcoder));
+ EDP_PSR2_STATUS(intel_dp->psr.transcoder));
status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/i915/pps: refactor init abstractions
== Series Details == Series: series starting with [1/4] drm/i915/pps: refactor init abstractions URL : https://patchwork.freedesktop.org/series/86076/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1328:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/pps: refactor init abstractions
== Series Details == Series: series starting with [1/4] drm/i915/pps: refactor init abstractions URL : https://patchwork.freedesktop.org/series/86076/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3210f99b0871 drm/i915/pps: refactor init abstractions b59f412b98d3 drm/i915/pps: move pps code over from intel_display.c and refactor 6c274e339aa3 drm/i915/dp: abstract struct intel_dp pps members to a sub-struct -:347: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #347: FILE: drivers/gpu/drm/i915/display/intel_pps.c:509: + panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time); -:355: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #355: FILE: drivers/gpu/drm/i915/display/intel_pps.c:515: + intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration); total: 0 errors, 2 warnings, 0 checks, 632 lines checked c56c8a0d7677 drm/i915/dp: split out aux functionality to intel_dp_aux.c -:745: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #745: new file mode 100644 -:793: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #793: FILE: drivers/gpu/drm/i915/display/intel_dp_aux.c:44: +#define C (((status = intel_uncore_read_notrace(>uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) -:984: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst #984: FILE: drivers/gpu/drm/i915/display/intel_dp_aux.c:235: + msleep(1); total: 0 errors, 3 warnings, 0 checks, 1433 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v12,1/2] drm/i915/display: Support PSR Multiple Instances
== Series Details ==
Series: series starting with [v12,1/2] drm/i915/display: Support PSR Multiple
Instances
URL : https://patchwork.freedesktop.org/series/86072/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9650 -> Patchwork_19419
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19419:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_lrc:
- {fi-tgl-dsi}: [DMESG-FAIL][1] ([i915#2373]) -> [SKIP][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-dsi/igt@i915_selftest@live@gt_lrc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/fi-tgl-dsi/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_pm:
- {fi-tgl-dsi}: [DMESG-FAIL][3] ([i915#1759]) -> [SKIP][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-dsi/igt@i915_selftest@live@gt_pm.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/fi-tgl-dsi/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@gt_timelines:
- {fi-tgl-dsi}: [PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-dsi/igt@i915_selftest@live@gt_timelines.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/fi-tgl-dsi/igt@i915_selftest@live@gt_timelines.html
* igt@i915_selftest@live@perf:
- {fi-tgl-dsi}: [PASS][7] -> [SKIP][8] +24 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-dsi/igt@i915_selftest@l...@perf.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/fi-tgl-dsi/igt@i915_selftest@l...@perf.html
* igt@kms_psr@primary_mmap_gtt:
- {fi-tgl-dsi}: [SKIP][9] ([fdo#110189]) -> [SKIP][10] +3 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
Known issues
Here are the changes found in Patchwork_19419 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][11] ([fdo#109271]) +17 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/fi-snb-2520m/igt@amdgpu/amd_pr...@i915-to-amd.html
* igt@fbdev@read:
- fi-tgl-y: [PASS][12] -> [DMESG-WARN][13] ([i915#402])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-tgl-y/igt@fb...@read.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/fi-tgl-y/igt@fb...@read.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][14] ([fdo#109271]) +30 similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-snb-2600:[DMESG-WARN][16] ([i915#2772]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/fi-snb-2600/igt@gem_exec_susp...@basic-s3.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2520m: [INCOMPLETE][18] -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9650/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19419/fi-snb-2520m/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#2772]: https://gitlab.freedesktop.org/drm/intel/issues/2772
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan
Re: [Intel-gfx] [PATCH v6 16/64] drm/i915: Fix userptr so we do not have to worry about obj->mm.lock, v5.
On 1/18/21 1:55 PM, Thomas Hellström (Intel) wrote:
On 1/18/21 1:43 PM, Maarten Lankhorst wrote:
Op 18-01-2021 om 12:30 schreef Thomas Hellström (Intel):
Hi,
On 1/5/21 4:35 PM, Maarten Lankhorst wrote:
Instead of doing what we do currently, which will never work with
PROVE_LOCKING, do the same as AMD does, and something similar to
relocation slowpath. When all locks are dropped, we acquire the
pages for pinning. When the locks are taken, we transfer those
pages in .get_pages() to the bo. As a final check before installing
the fences, we ensure that the mmu notifier was not called; if it is,
we return -EAGAIN to userspace to signal it has to start over.
Changes since v1:
- Unbinding is done in submit_init only. submit_begin() removed.
- MMU_NOTFIER -> MMU_NOTIFIER
Changes since v2:
- Make i915->mm.notifier a spinlock.
Changes since v3:
- Add WARN_ON if there are any page references left, should have
been 0.
- Return 0 on success in submit_init(), bug from spinlock conversion.
- Release pvec outside of notifier_lock (Thomas).
Changes since v4:
- Mention why we're clearing eb->[i + 1].vma in the code. (Thomas)
- Actually check all invalidations in eb_move_to_gpu. (Thomas)
- Do not wait when process is exiting to fix
gem_ctx_persistence.userptr.
Signed-off-by: Maarten Lankhorst
...
-static int
-userptr_mn_invalidate_range_start(struct mmu_notifier *_mn,
- const struct mmu_notifier_range *range)
-{
- struct i915_mmu_notifier *mn =
- container_of(_mn, struct i915_mmu_notifier, mn);
- struct interval_tree_node *it;
- unsigned long end;
- int ret = 0;
-
- if (RB_EMPTY_ROOT(>objects.rb_root))
- return 0;
-
- /* interval ranges are inclusive, but invalidate range is
exclusive */
- end = range->end - 1;
-
- spin_lock(>lock);
- it = interval_tree_iter_first(>objects, range->start, end);
- while (it) {
- struct drm_i915_gem_object *obj;
-
- if (!mmu_notifier_range_blockable(range)) {
- ret = -EAGAIN;
- break;
- }
+ spin_lock(>mm.notifier_lock);
- /*
- * The mmu_object is released late when destroying the
- * GEM object so it is entirely possible to gain a
- * reference on an object in the process of being freed
- * since our serialisation is via the spinlock and not
- * the struct_mutex - and consequently use it after it
- * is freed and then double free it. To prevent that
- * use-after-free we only acquire a reference on the
- * object if it is not in the process of being destroyed.
- */
- obj = container_of(it, struct i915_mmu_object, it)->obj;
- if (!kref_get_unless_zero(>base.refcount)) {
- it = interval_tree_iter_next(it, range->start, end);
- continue;
- }
- spin_unlock(>lock);
+ mmu_interval_set_seq(mni, cur_seq);
- ret = i915_gem_object_unbind(obj,
- I915_GEM_OBJECT_UNBIND_ACTIVE |
- I915_GEM_OBJECT_UNBIND_BARRIER);
- if (ret == 0)
- ret = __i915_gem_object_put_pages(obj);
- i915_gem_object_put(obj);
- if (ret)
- return ret;
+ spin_unlock(>mm.notifier_lock);
- spin_lock(>lock);
+ /* During exit there's no need to wait */
+ if (current->flags & PF_EXITING)
+ return true;
Did we ever find out why this is needed, that is why the old userptr
invalidation called doesn't hang here in a similar way?
It's an optimization for teardown because userptr will be invalidated
anyway, but also for gem_ctx_persistence.userptr, although
with ulls that test may stop working anyway because it takes an
out_fence.
Sure, but what I meant was: Did we find out what's different in the
new code compared to the old one? Because the old code also waits for
gpu when unbinding in the mmu_notifier, but it appears like in the old
code, the mmu notifier is never called here. At least to me it seems
it would be good if we understand what that difference is.
/Thomas
IIRC I did some investigation here as well and from what I could tell,
the notifier was not called at all for the old code. I don't really feel
comfortable with an R-B until we've really understood why.
Also there was a discussion with you, Sudeep and Chris about whether
user-space was actually not comfortable with this, you saying it worked,
Chris said tests were showing otherwise. What were those tests?
Thanks,
Thomas
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v12,1/2] drm/i915/display: Support PSR Multiple Instances
== Series Details == Series: series starting with [v12,1/2] drm/i915/display: Support PSR Multiple Instances URL : https://patchwork.freedesktop.org/series/86072/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1328:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v12,1/2] drm/i915/display: Support PSR Multiple Instances
== Series Details == Series: series starting with [v12,1/2] drm/i915/display: Support PSR Multiple Instances URL : https://patchwork.freedesktop.org/series/86072/ State : warning == Summary == $ dim checkpatch origin/drm-tip 25db9a3ad7a1 drm/i915/display: Support PSR Multiple Instances -:1259: CHECK:LINE_SPACING: Please don't use multiple blank lines #1259: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1519: + + -:1683: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible side-effects? #1683: FILE: drivers/gpu/drm/i915/display/intel_psr.h:21: +#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && intel_dp->psr.sink_support) total: 0 errors, 0 warnings, 2 checks, 1693 lines checked a15e8e858ac9 drm/i915/display: Support Multiple Transcoders' PSR status on debugfs ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/10] drm/i915/gt: Skip over completed active execlists, again
Now that we are careful to always force-restore contexts upon rewinding
(where necessary), we can restore our optimisation to skip over
completed active execlists when dequeuing.
Referenecs: 35f3fd8182ba ("drm/i915/execlists: Workaround switching back to a
completed context")
References: 8ab3a3812aa9 ("drm/i915/gt: Incrementally check for rewinding")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
.../drm/i915/gt/intel_execlists_submission.c | 34 +--
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 524c8b54d220..ac1be7a632d3 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1224,12 +1224,20 @@ static void set_preempt_timeout(struct intel_engine_cs
*engine,
active_preempt_timeout(engine, rq));
}
+static bool completed(const struct i915_request *rq)
+{
+ if (i915_request_has_sentinel(rq))
+ return false;
+
+ return __i915_request_is_complete(rq);
+}
+
static void execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = >execlists;
struct i915_request **port = execlists->pending;
struct i915_request ** const last_port = port + execlists->port_mask;
- struct i915_request *last = *execlists->active;
+ struct i915_request *last, * const *active;
struct virtual_engine *ve;
struct rb_node *rb;
bool submit = false;
@@ -1266,21 +1274,13 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* i.e. we will retrigger preemption following the ack in case
* of trouble.
*
-* In theory we can skip over completed contexts that have not
-* yet been processed by events (as those events are in flight):
-*
-* while ((last = *active) && i915_request_completed(last))
-* active++;
-*
-* However, the GPU cannot handle this as it will ultimately
-* find itself trying to jump back into a context it has just
-* completed and barf.
*/
+ active = execlists->active;
+ while ((last = *active) && completed(last))
+ active++;
if (last) {
- if (__i915_request_is_complete(last)) {
- goto check_secondary;
- } else if (need_preempt(engine, last)) {
+ if (need_preempt(engine, last)) {
ENGINE_TRACE(engine,
"preempting last=%llx:%lld, prio=%d,
hint=%d\n",
last->fence.context,
@@ -1359,9 +1359,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* we hopefully coalesce several updates into a single
* submission.
*/
-check_secondary:
- if (!list_is_last(>sched.link,
- >active.requests)) {
+ if (active[1]) {
/*
* Even if ELSP[1] is occupied and not worthy
* of timeslices, our queue might be.
@@ -1562,7 +1560,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* of ordered contexts.
*/
if (submit &&
- memcmp(execlists->active,
+ memcmp(active,
execlists->pending,
(port - execlists->pending) * sizeof(*port))) {
*port = NULL;
@@ -1570,7 +1568,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
execlists_schedule_in(*port, port - execlists->pending);
WRITE_ONCE(execlists->yield, -1);
- set_preempt_timeout(engine, *execlists->active);
+ set_preempt_timeout(engine, *active);
execlists_submit_ports(engine);
} else {
ring_set_paused(engine, 0);
--
2.20.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/10] drm/i915/selftests: Exercise priority inheritance around an engine loop
Exercise rescheduling priority inheritance around a sequence of requests
that wrap around all the engines.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/selftests/i915_scheduler.c | 219 ++
1 file changed, 219 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
index cb67de304aeb..e6910f4c429d 100644
--- a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
@@ -7,6 +7,7 @@
#include "gt/intel_context.h"
#include "gt/intel_gpu_commands.h"
+#include "gt/intel_ring.h"
#include "gt/selftest_engine_heartbeat.h"
#include "selftests/igt_spinner.h"
#include "selftests/i915_random.h"
@@ -512,10 +513,228 @@ static int igt_priority_chains(void *arg)
return igt_schedule_chains(arg, igt_priority);
}
+static struct i915_request *
+__write_timestamp(struct intel_engine_cs *engine,
+ struct drm_i915_gem_object *obj,
+ int slot,
+ struct i915_request *prev)
+{
+ struct i915_request *rq = ERR_PTR(-EINVAL);
+ struct intel_context *ce;
+ struct i915_vma *vma;
+ int err = 0;
+ u32 *cs;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return ERR_CAST(ce);
+
+ vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_ce;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto out_ce;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_unpin;
+ }
+
+ i915_vma_lock(vma);
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ i915_vma_unlock(vma);
+ if (err)
+ goto out_request;
+
+ if (prev) {
+ err = i915_request_await_dma_fence(rq, >fence);
+ if (err)
+ goto out_request;
+ }
+
+ if (engine->emit_init_breadcrumb) {
+ err = engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_request;
+ }
+
+ cs = intel_ring_begin(rq, 4);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto out_request;
+ }
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8;
+ *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base));
+ *cs++ = lower_32_bits(vma->node.start) + sizeof(u32) * slot;
+ *cs++ = upper_32_bits(vma->node.start);
+ intel_ring_advance(rq, cs);
+
+ i915_request_get(rq);
+out_request:
+ i915_request_add(rq);
+out_unpin:
+ i915_vma_unpin(vma);
+out_ce:
+ intel_context_put(ce);
+ i915_request_put(prev);
+ return err ? ERR_PTR(err) : rq;
+}
+
+static struct i915_request *create_spinner(struct drm_i915_private *i915,
+ struct igt_spinner *spin)
+{
+ struct intel_engine_cs *engine;
+
+ for_each_uabi_engine(engine, i915) {
+ struct intel_context *ce;
+ struct i915_request *rq;
+
+ if (igt_spinner_init(spin, engine->gt))
+ return ERR_PTR(-ENOMEM);
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return ERR_CAST(ce);
+
+ rq = igt_spinner_create_request(spin, ce, MI_NOOP);
+ intel_context_put(ce);
+ if (rq == ERR_PTR(-ENODEV))
+ continue;
+ if (IS_ERR(rq))
+ return rq;
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ return rq;
+ }
+
+ return ERR_PTR(-ENODEV);
+}
+
+static int __igt_schedule_cycle(struct drm_i915_private *i915,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_engine_cs *engine;
+ struct drm_i915_gem_object *obj;
+ struct igt_spinner spin;
+ struct i915_request *rq;
+ unsigned long count, n;
+ u32 *time, last;
+ int err;
+
+ /*
+* Queue a bunch of ordered requests (each waiting on the previous)
+* around the engines a couple of times. Each request will write
+* the timestamp it executes at into the scratch, with the expectation
+* that the timestamp will be in our desired execution order.
+*/
+
+ if (INTEL_GEN(i915) < 8)
+ return 0;
+
+ obj = i915_gem_object_create_internal(i915, SZ_64K);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ time = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(time)) {
+ err = PTR_ERR(time);
+ goto out_obj;
+ }
+
+ rq =
[Intel-gfx] [PATCH 06/10] drm/i915: Teach the i915_dependency to use a double-lock
Currently, we construct and teardown the i915_dependency chains using a
global spinlock. As the lists are entirely local, it should be possible
to use an double-lock with an explicit nesting [signaler -> waiter,
always] and so avoid the costly convenience of a global spinlock.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 2 +-
drivers/gpu/drm/i915/i915_scheduler.c | 65 +
drivers/gpu/drm/i915/i915_scheduler.h | 2 +-
drivers/gpu/drm/i915/i915_scheduler_types.h | 2 +
4 files changed, 46 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index abda565dfe62..df2ab39b394d 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -330,7 +330,7 @@ bool i915_request_retire(struct i915_request *rq)
intel_context_unpin(rq->context);
free_capture_list(rq);
- i915_sched_node_fini(>sched);
+ i915_sched_node_retire(>sched);
i915_request_put(rq);
return true;
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index dbdd4128f13d..96fe1e22dad7 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -19,6 +19,17 @@ static struct i915_global_scheduler {
static DEFINE_SPINLOCK(schedule_lock);
+static struct i915_sched_node *node_get(struct i915_sched_node *node)
+{
+ i915_request_get(container_of(node, struct i915_request, sched));
+ return node;
+}
+
+static void node_put(struct i915_sched_node *node)
+{
+ i915_request_put(container_of(node, struct i915_request, sched));
+}
+
static const struct i915_request *
node_to_request(const struct i915_sched_node *node)
{
@@ -353,6 +364,8 @@ void i915_request_set_priority(struct i915_request *rq, int
prio)
void i915_sched_node_init(struct i915_sched_node *node)
{
+ spin_lock_init(>lock);
+
INIT_LIST_HEAD(>signalers_list);
INIT_LIST_HEAD(>waiters_list);
INIT_LIST_HEAD(>link);
@@ -377,10 +390,17 @@ i915_dependency_alloc(void)
return kmem_cache_alloc(global.slab_dependencies, GFP_KERNEL);
}
+static void
+rcu_dependency_free(struct rcu_head *rcu)
+{
+ kmem_cache_free(global.slab_dependencies,
+ container_of(rcu, typeof(struct i915_dependency), rcu));
+}
+
static void
i915_dependency_free(struct i915_dependency *dep)
{
- kmem_cache_free(global.slab_dependencies, dep);
+ call_rcu(>rcu, rcu_dependency_free);
}
bool __i915_sched_node_add_dependency(struct i915_sched_node *node,
@@ -390,24 +410,27 @@ bool __i915_sched_node_add_dependency(struct
i915_sched_node *node,
{
bool ret = false;
- spin_lock_irq(_lock);
+ /* The signal->lock is always the outer lock in this double-lock. */
+ spin_lock(>lock);
if (!node_signaled(signal)) {
INIT_LIST_HEAD(>dfs_link);
dep->signaler = signal;
- dep->waiter = node;
+ dep->waiter = node_get(node);
dep->flags = flags;
/* All set, now publish. Beware the lockless walkers. */
+ spin_lock_nested(>lock, SINGLE_DEPTH_NESTING);
list_add_rcu(>signal_link, >signalers_list);
list_add_rcu(>wait_link, >waiters_list);
+ spin_unlock(>lock);
/* Propagate the chains */
node->flags |= signal->flags;
ret = true;
}
- spin_unlock_irq(_lock);
+ spin_unlock(>lock);
return ret;
}
@@ -429,39 +452,36 @@ int i915_sched_node_add_dependency(struct i915_sched_node
*node,
return 0;
}
-void i915_sched_node_fini(struct i915_sched_node *node)
+void i915_sched_node_retire(struct i915_sched_node *node)
{
struct i915_dependency *dep, *tmp;
- spin_lock_irq(_lock);
-
/*
* Everyone we depended upon (the fences we wait to be signaled)
* should retire before us and remove themselves from our list.
* However, retirement is run independently on each timeline and
-* so we may be called out-of-order.
+* so we may be called out-of-order. As we need to avoid taking
+* the signaler's lock, just mark up our completion and be wary
+* in traversing the signalers->waiters_list.
*/
- list_for_each_entry_safe(dep, tmp, >signalers_list, signal_link) {
- GEM_BUG_ON(!list_empty(>dfs_link));
-
- list_del_rcu(>wait_link);
- if (dep->flags & I915_DEPENDENCY_ALLOC)
- i915_dependency_free(dep);
- }
- INIT_LIST_HEAD(>signalers_list);
/* Remove ourselves from everyone who depends upon us */
+ spin_lock(>lock);
list_for_each_entry_safe(dep, tmp, >waiters_list, wait_link) {
- GEM_BUG_ON(dep->signaler != node);
[Intel-gfx] [PATCH 05/10] drm/i915: Replace engine->schedule() with a known request operation
Looking to the future, we want to set the scheduling attributes
explicitly and so replace the generic engine->schedule() with the more
direct i915_request_set_priority()
What it loses in removing the 'schedule' name from the function, it
gains in having an explicit entry point with a stated goal.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_display.c | 5 ++-
drivers/gpu/drm/i915/gem/i915_gem_object.h| 5 ++-
drivers/gpu/drm/i915/gem/i915_gem_wait.c | 29 +---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 --
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 4 +--
drivers/gpu/drm/i915/gt/intel_engine_types.h | 29
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 3 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 33 +--
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 11 +++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 -
drivers/gpu/drm/i915/i915_request.c | 10 +++---
drivers/gpu/drm/i915/i915_scheduler.c | 15 +
drivers/gpu/drm/i915/i915_scheduler.h | 3 +-
14 files changed, 59 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 6f04f85812fe..265344d98cbb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13543,7 +13543,6 @@ int
intel_prepare_plane_fb(struct drm_plane *_plane,
struct drm_plane_state *_new_plane_state)
{
- struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
struct intel_plane *plane = to_intel_plane(_plane);
struct intel_plane_state *new_plane_state =
to_intel_plane_state(_new_plane_state);
@@ -13584,7 +13583,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
if (new_plane_state->uapi.fence) { /* explicit fencing */
i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
-);
+I915_PRIORITY_DISPLAY);
ret = i915_sw_fence_await_dma_fence(>commit_ready,
new_plane_state->uapi.fence,
i915_fence_timeout(dev_priv),
@@ -13606,7 +13605,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
if (ret)
return ret;
- i915_gem_object_wait_priority(obj, 0, );
+ i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
if (!new_plane_state->uapi.fence) { /* implicit fencing */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index b6a16ab85956..92d174017dbf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -500,15 +500,14 @@ static inline void __start_cpu_write(struct
drm_i915_gem_object *obj)
obj->cache_dirty = true;
}
-void i915_gem_fence_wait_priority(struct dma_fence *fence,
- const struct i915_sched_attr *attr);
+void i915_gem_fence_wait_priority(struct dma_fence *fence, int prio);
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
unsigned int flags,
long timeout);
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
unsigned int flags,
- const struct i915_sched_attr *attr);
+ int prio);
void __i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj,
enum fb_op_origin origin);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
index 4b9856d5ba14..d79bf16083bd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
@@ -91,22 +91,12 @@ i915_gem_object_wait_reservation(struct dma_resv *resv,
return timeout;
}
-static void fence_set_priority(struct dma_fence *fence,
- const struct i915_sched_attr *attr)
+static void fence_set_priority(struct dma_fence *fence, int prio)
{
- struct i915_request *rq;
- struct intel_engine_cs *engine;
-
if (dma_fence_is_signaled(fence) || !dma_fence_is_i915(fence))
return;
- rq = to_request(fence);
- engine = rq->engine;
-
- rcu_read_lock(); /* RCU serialisation for set-wedged protection */
- if (engine->schedule)
- engine->schedule(rq, attr);
- rcu_read_unlock();
+ i915_request_set_priority(to_request(fence), prio);
}
static inline bool __dma_fence_is_chain(const struct dma_fence *fence)
@@ -114,8
Re: [Intel-gfx] [PULL] gvt-gt-next
Quoting Zhenyu Wang (2021-01-18 07:07:39) > > Hi, > > This is GVT next for 5.12 against drm-intel-gt-next which is mostly > for cmd parser enhancement which adds extra check on register load > depending on initial context and handles vGPU register state > accordingly. I think we were bit inconclusive on this last time. Even if this does not have any dependency to drm-intel-gt-next I can pull this to drm-intel-gt-next. The only caveat is that for any -fixes, there needs to be a backmerge to drm-intel-next. Not sure if this is a problem. Do we want to make it a recurring practice to backmerge drm-intel-gt-next into drm-intel-next after it lands in drm-next? So to recap: Do we want to pull to drm-intel-next whenever there are no dependencies to drm-intel-gt-next, to avoid a backmerge? Or do we want to always do a backmerge in anticipation of -fixes. Regards, Joonas > Thanks. > -- > The following changes since commit fe7bcfaeb2b775f257348dc7b935f8e80eef3e7d: > > drm/i915/gt: Refactor heartbeat request construction and submission > (2020-12-24 18:07:26 +) > > are available in the Git repository at: > > https://github.com/intel/gvt-linux tags/gvt-gt-next-2021-01-18 > > for you to fetch changes up to 02dd2b12a685944c4d52c569d05f636372a7b6c7: > > drm/i915/gvt: unify lri cmd handler and mmio handlers (2020-12-25 11:16:32 > +0800) > > > gvt-gt-next-2021-01-18 > > - GVT cmd parser enhancement against guest context (Yan) > > > Yan Zhao (11): > drm/i915/gvt: parse init context to update cmd accessible reg whitelist > drm/i915/gvt: scan VM ctx pages > drm/i915/gvt: filter cmds "srm" and "lrm" in cmd_handler > drm/i915/gvt: filter cmds "lrr-src" and "lrr-dst" in cmd_handler > drm/i915/gvt: filter cmd "pipe-ctrl" in cmd_handler > drm/i915/gvt: export find_mmio_info > drm/i915/gvt: make width of mmio_attribute bigger > drm/i915/gvt: introduce a new flag F_CMD_WRITE_PATCH > drm/i915/gvt: statically set F_CMD_WRITE_PATCH flag > drm/i915/gvt: update F_CMD_WRITE_PATCH flag when parsing init ctx > drm/i915/gvt: unify lri cmd handler and mmio handlers > > drivers/gpu/drm/i915/gvt/cmd_parser.c | 335 > +++--- > drivers/gpu/drm/i915/gvt/cmd_parser.h | 4 + > drivers/gpu/drm/i915/gvt/gvt.h| 37 +++- > drivers/gpu/drm/i915/gvt/handlers.c | 15 +- > drivers/gpu/drm/i915/gvt/mmio.h | 3 + > drivers/gpu/drm/i915/gvt/reg.h| 2 + > drivers/gpu/drm/i915/gvt/scheduler.c | 22 ++- > drivers/gpu/drm/i915/gvt/vgpu.c | 4 +- > 8 files changed, 339 insertions(+), 83 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/10] drm/i915: Restructure priority inheritance
In anticipation of wanting to be able to call pi from underneath an
engine's active.lock, rework the priority inheritance to primarily work
along an engine's priority queue, delegating any other engine that the
chain may traverse to a worker. This reduces the global spinlock from
governing the multi-entire priority inheritance depth-first search, to a
smaller lock on each engine around a single list on that engine.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +
drivers/gpu/drm/i915/i915_scheduler.c| 346 ---
drivers/gpu/drm/i915/i915_scheduler.h| 2 +
drivers/gpu/drm/i915/i915_scheduler_types.h | 19 +-
5 files changed, 234 insertions(+), 138 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index af4f90be39cd..8e7bc0c28af2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -595,6 +595,8 @@ void intel_engine_init_execlists(struct intel_engine_cs
*engine)
execlists->queue_priority_hint = INT_MIN;
execlists->queue = RB_ROOT_CACHED;
+
+ i915_sched_init_ipi(>ipi);
}
static void cleanup_status_page(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index d482674ceb60..1258b1f795a7 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -21,6 +21,7 @@
#include "i915_gem.h"
#include "i915_pmu.h"
#include "i915_priolist_types.h"
+#include "i915_scheduler_types.h"
#include "i915_selftest.h"
#include "intel_breadcrumbs_types.h"
#include "intel_sseu.h"
@@ -258,6 +259,8 @@ struct intel_engine_execlists {
struct rb_root_cached queue;
struct rb_root_cached virtual;
+ struct i915_sched_ipi ipi;
+
/**
* @csb_write: control register for Context Switch buffer
*
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 96fe1e22dad7..0ecf71a6afd4 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -17,8 +17,6 @@ static struct i915_global_scheduler {
struct kmem_cache *slab_priorities;
} global;
-static DEFINE_SPINLOCK(schedule_lock);
-
static struct i915_sched_node *node_get(struct i915_sched_node *node)
{
i915_request_get(container_of(node, struct i915_request, sched));
@@ -30,17 +28,116 @@ static void node_put(struct i915_sched_node *node)
i915_request_put(container_of(node, struct i915_request, sched));
}
+static inline int rq_prio(const struct i915_request *rq)
+{
+ return READ_ONCE(rq->sched.attr.priority);
+}
+
+static int ipi_get_prio(struct i915_request *rq)
+{
+ if (READ_ONCE(rq->sched.ipi_priority) == I915_PRIORITY_INVALID)
+ return I915_PRIORITY_INVALID;
+
+ return xchg(>sched.ipi_priority, I915_PRIORITY_INVALID);
+}
+
+static void ipi_schedule(struct work_struct *wrk)
+{
+ struct i915_sched_ipi *ipi = container_of(wrk, typeof(*ipi), work);
+ struct i915_request *rq = xchg(>list, NULL);
+
+ do {
+ struct i915_request *rn = xchg(>sched.ipi_link, NULL);
+ int prio;
+
+ prio = ipi_get_prio(rq);
+
+ /*
+* For cross-engine scheduling to work we rely on one of two
+* things:
+*
+* a) The requests are using dma-fence fences and so will not
+* be scheduled until the previous engine is completed, and
+* so we cannot cross back onto the original engine and end up
+* queuing an earlier request after the first (due to the
+* interrupted DFS).
+*
+* b) The requests are using semaphores and so may be already
+* be in flight, in which case if we cross back onto the same
+* engine, we will already have put the interrupted DFS into
+* the priolist, and the continuation will now be queued
+* afterwards [out-of-order]. However, since we are using
+* semaphores in this case, we also perform yield on semaphore
+* waits and so will reorder the requests back into the correct
+* sequence. This occurrence (of promoting a request chain
+* that crosses the engines using semaphores back unto itself)
+* should be unlikely enough that it probably does not matter...
+*/
+ local_bh_disable();
+ i915_request_set_priority(rq, prio);
+ local_bh_enable();
+
+ i915_request_put(rq);
+ rq = ptr_mask_bits(rn, 1);
+ } while (rq);
+}
+
+void i915_sched_init_ipi(struct
[Intel-gfx] [PATCH 10/10] drm/i915: Improve DFS for priority inheritance
The core of the scheduling algorithm is that we compute the topological
order of the fence DAG. Knowing that we have a DAG, we should be able to
use a DFS to compute the topological sort in linear time. However,
during the conversion of the recursive algorithm into an iterative one,
the memoization of how far we had progressed down a branch was
forgotten. The result was that instead of running in linear time, it was
running in geometric time and could easily run for a few hundred
milliseconds given a wide enough graph, not the microseconds as required.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_scheduler.c | 58 ---
1 file changed, 34 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 4802c9b1081d..9139a91f0aa3 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -234,6 +234,26 @@ void __i915_priolist_free(struct i915_priolist *p)
kmem_cache_free(global.slab_priorities, p);
}
+static struct i915_request *
+stack_push(struct i915_request *rq,
+ struct i915_request *stack,
+ struct list_head *pos)
+{
+ stack->sched.dfs.prev = pos;
+ rq->sched.dfs.next = (struct list_head *)stack;
+ return rq;
+}
+
+static struct i915_request *
+stack_pop(struct i915_request *rq,
+ struct list_head **pos)
+{
+ rq = (struct i915_request *)rq->sched.dfs.next;
+ if (rq)
+ *pos = rq->sched.dfs.prev;
+ return rq;
+}
+
static inline bool need_preempt(int prio, int active)
{
/*
@@ -298,11 +318,10 @@ static void ipi_priority(struct i915_request *rq, int
prio)
static void __i915_request_set_priority(struct i915_request *rq, int prio)
{
struct intel_engine_cs *engine = rq->engine;
- struct i915_request *rn;
+ struct list_head *pos = >sched.signalers_list;
struct list_head *plist;
- LIST_HEAD(dfs);
- list_add(>sched.dfs, );
+ plist = i915_sched_lookup_priolist(engine, prio);
/*
* Recursively bump all dependent priorities to match the new request.
@@ -322,40 +341,31 @@ static void __i915_request_set_priority(struct
i915_request *rq, int prio)
* end result is a topological list of requests in reverse order, the
* last element in the list is the request we must execute first.
*/
- list_for_each_entry(rq, , sched.dfs) {
- struct i915_dependency *p;
-
- /* Also release any children on this engine that are ready */
- GEM_BUG_ON(rq->engine != engine);
-
- for_each_signaler(p, rq) {
+ rq->sched.dfs.next = NULL;
+ do {
+ list_for_each_continue(pos, >sched.signalers_list) {
+ struct i915_dependency *p =
+ list_entry(pos, typeof(*p), signal_link);
struct i915_request *s =
container_of(p->signaler, typeof(*s), sched);
- GEM_BUG_ON(s == rq);
-
if (rq_prio(s) >= prio)
continue;
if (__i915_request_is_complete(s))
continue;
- if (s->engine != rq->engine) {
+ if (s->engine != engine) {
ipi_priority(s, prio);
continue;
}
- list_move_tail(>sched.dfs, );
+ /* Remember our position along this branch */
+ rq = stack_push(s, rq, pos);
+ pos = >sched.signalers_list;
}
- }
- plist = i915_sched_lookup_priolist(engine, prio);
-
- /* Fifo and depth-first replacement ensure our deps execute first */
- list_for_each_entry_safe_reverse(rq, rn, , sched.dfs) {
- GEM_BUG_ON(rq->engine != engine);
-
- INIT_LIST_HEAD(>sched.dfs);
+ RQ_TRACE(rq, "set-priority:%d\n", prio);
WRITE_ONCE(rq->sched.attr.priority, prio);
/*
@@ -369,12 +379,13 @@ static void __i915_request_set_priority(struct
i915_request *rq, int prio)
if (!i915_request_is_ready(rq))
continue;
+ GEM_BUG_ON(rq->engine != engine);
if (i915_request_in_priority_queue(rq))
list_move_tail(>sched.link, plist);
/* Defer (tasklet) submission until after all updates. */
kick_submission(engine, rq, prio);
- }
+ } while ((rq = stack_pop(rq, )));
}
void i915_request_set_priority(struct i915_request *rq, int prio)
@@ -444,7 +455,6 @@ void i915_sched_node_init(struct i915_sched_node *node)
INIT_LIST_HEAD(>signalers_list);
[Intel-gfx] [PATCH 08/10] drm/i915/selftests: Measure set-priority duration
As a topological sort, we expect it to run in linear graph time,
O(V+E). In removing the recursion, it is no longer a DFS but rather a
BFS, and performs as O(VE). Let's demonstrate how bad this is with a few
examples, and build a few test cases to verify a potential fix.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_scheduler.c | 4 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../drm/i915/selftests/i915_perf_selftests.h | 1 +
.../gpu/drm/i915/selftests/i915_scheduler.c | 679 ++
4 files changed, 685 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_scheduler.c
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 0ecf71a6afd4..4802c9b1081d 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -592,6 +592,10 @@ void i915_request_show_with_schedule(struct drm_printer *m,
rcu_read_unlock();
}
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/i915_scheduler.c"
+#endif
+
static void i915_global_scheduler_shrink(void)
{
kmem_cache_shrink(global.slab_dependencies);
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index a92c0e9b7e6b..2200a5baa68e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -26,6 +26,7 @@ selftest(gt_mocs, intel_mocs_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
selftest(gt_heartbeat, intel_heartbeat_live_selftests)
selftest(requests, i915_request_live_selftests)
+selftest(scheduler, i915_scheduler_live_selftests)
selftest(active, i915_active_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
selftest(mman, i915_gem_mman_live_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
index c2389f8a257d..137e35283fee 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
@@ -17,5 +17,6 @@
*/
selftest(engine_cs, intel_engine_cs_perf_selftests)
selftest(request, i915_request_perf_selftests)
+selftest(scheduler, i915_scheduler_perf_selftests)
selftest(blt, i915_gem_object_blt_perf_selftests)
selftest(region, intel_memory_region_perf_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
new file mode 100644
index ..cb67de304aeb
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
@@ -0,0 +1,679 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_selftest.h"
+
+#include "gt/intel_context.h"
+#include "gt/intel_gpu_commands.h"
+#include "gt/selftest_engine_heartbeat.h"
+#include "selftests/igt_spinner.h"
+#include "selftests/i915_random.h"
+
+static void scheduling_disable(struct intel_engine_cs *engine)
+{
+ engine->props.preempt_timeout_ms = 0;
+ engine->props.timeslice_duration_ms = 0;
+
+ st_engine_heartbeat_disable(engine);
+}
+
+static void scheduling_enable(struct intel_engine_cs *engine)
+{
+ st_engine_heartbeat_enable(engine);
+
+ engine->props.preempt_timeout_ms =
+ engine->defaults.preempt_timeout_ms;
+ engine->props.timeslice_duration_ms =
+ engine->defaults.timeslice_duration_ms;
+}
+
+static int first_engine(struct drm_i915_private *i915,
+ int (*chain)(struct intel_engine_cs *engine,
+unsigned long param,
+bool (*fn)(struct i915_request *rq,
+ unsigned long v,
+ unsigned long e)),
+ unsigned long param,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_engine_cs *engine;
+
+ for_each_uabi_engine(engine, i915) {
+ if (!intel_engine_has_scheduler(engine))
+ continue;
+
+ return chain(engine, param, fn);
+ }
+
+ return 0;
+}
+
+static int all_engines(struct drm_i915_private *i915,
+ int (*chain)(struct intel_engine_cs *engine,
+ unsigned long param,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v,
+ unsigned long e)),
+ unsigned long param,
+ bool (*fn)(struct i915_request *rq,
+ unsigned long v, unsigned long e))
+{
+ struct intel_engine_cs *engine;
+ int err;
+
+ for_each_uabi_engine(engine, i915) {
+
[Intel-gfx] [PATCH 04/10] drm/i915: Remove I915_USER_PRIORITY_SHIFT
As we do not have any internal priority levels, the priority can be set
directed from the user values.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +--
.../i915/gem/selftests/i915_gem_object_blt.c | 4 +-
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 10 ++---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 44 +++
drivers/gpu/drm/i915/i915_priolist_types.h| 3 --
drivers/gpu/drm/i915/i915_scheduler.c | 1 -
7 files changed, 24 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 7373f54b216e..6f04f85812fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13543,9 +13543,7 @@ int
intel_prepare_plane_fb(struct drm_plane *_plane,
struct drm_plane_state *_new_plane_state)
{
- struct i915_sched_attr attr = {
- .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
- };
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
struct intel_plane *plane = to_intel_plane(_plane);
struct intel_plane_state *new_plane_state =
to_intel_plane_state(_new_plane_state);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 4d2f40cf237b..61a7360c4d9a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -679,7 +679,7 @@ __create_context(struct drm_i915_private *i915)
kref_init(>ref);
ctx->i915 = i915;
- ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL);
+ ctx->sched.priority = I915_PRIORITY_NORMAL;
mutex_init(>mutex);
INIT_LIST_HEAD(>link);
@@ -1959,7 +1959,7 @@ static int set_priority(struct i915_gem_context *ctx,
!capable(CAP_SYS_NICE))
return -EPERM;
- ctx->sched.priority = I915_USER_PRIORITY(priority);
+ ctx->sched.priority = priority;
context_apply_all(ctx, __apply_priority, ctx);
return 0;
@@ -2463,7 +2463,7 @@ int i915_gem_context_getparam_ioctl(struct drm_device
*dev, void *data,
case I915_CONTEXT_PARAM_PRIORITY:
args->size = 0;
- args->value = ctx->sched.priority >> I915_USER_PRIORITY_SHIFT;
+ args->value = ctx->sched.priority;
break;
case I915_CONTEXT_PARAM_SSEU:
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
index 23b6e11bbc3e..c4c04fb97d14 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
@@ -220,7 +220,7 @@ static int igt_fill_blt_thread(void *arg)
return PTR_ERR(ctx);
prio = i915_prandom_u32_max_state(I915_PRIORITY_MAX, prng);
- ctx->sched.priority = I915_USER_PRIORITY(prio);
+ ctx->sched.priority = prio;
}
ce = i915_gem_context_get_engine(ctx, 0);
@@ -338,7 +338,7 @@ static int igt_copy_blt_thread(void *arg)
return PTR_ERR(ctx);
prio = i915_prandom_u32_max_state(I915_PRIORITY_MAX, prng);
- ctx->sched.priority = I915_USER_PRIORITY(prio);
+ ctx->sched.priority = prio;
}
ce = i915_gem_context_get_engine(ctx, 0);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index 1732a42e9075..ed03c08737f5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -81,9 +81,7 @@ static void show_heartbeat(const struct i915_request *rq,
static void heartbeat(struct work_struct *wrk)
{
- struct i915_sched_attr attr = {
- .priority = I915_USER_PRIORITY(I915_PRIORITY_MIN),
- };
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_MIN };
struct intel_engine_cs *engine =
container_of(wrk, typeof(*engine), heartbeat.work.work);
struct intel_context *ce = engine->kernel_context;
@@ -127,7 +125,7 @@ static void heartbeat(struct work_struct *wrk)
*/
attr.priority = 0;
if (rq->sched.attr.priority >= attr.priority)
- attr.priority |=
I915_USER_PRIORITY(I915_PRIORITY_HEARTBEAT);
+ attr.priority = I915_PRIORITY_HEARTBEAT;
if (rq->sched.attr.priority >= attr.priority)
attr.priority = I915_PRIORITY_BARRIER;
@@ -285,9 +283,7 @@ int intel_engine_pulse(struct intel_engine_cs *engine)
int intel_engine_flush_barriers(struct
[Intel-gfx] [PATCH 03/10] drm/i915: Strip out internal priorities
Since we are not using any internal priority levels, and in the next few
patches will introduce a new index for which the optimisation is not so
lear cut, discard the small table within the priolist.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 22 ++--
drivers/gpu/drm/i915/gt/selftest_execlists.c | 1 -
drivers/gpu/drm/i915/gt/selftest_lrc.c| 1 -
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +--
drivers/gpu/drm/i915/i915_priolist_types.h| 8 +--
drivers/gpu/drm/i915/i915_scheduler.c | 51 +++
drivers/gpu/drm/i915/i915_scheduler.h | 16 ++
8 files changed, 20 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index d7be2b9339f9..1732a42e9075 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -125,7 +125,7 @@ static void heartbeat(struct work_struct *wrk)
* low latency and no jitter] the chance to naturally
* complete before being preempted.
*/
- attr.priority = I915_PRIORITY_MASK;
+ attr.priority = 0;
if (rq->sched.attr.priority >= attr.priority)
attr.priority |=
I915_USER_PRIORITY(I915_PRIORITY_HEARTBEAT);
if (rq->sched.attr.priority >= attr.priority)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index ac1be7a632d3..b31ce0d60028 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -274,22 +274,13 @@ static int effective_prio(const struct i915_request *rq)
static int queue_prio(const struct intel_engine_execlists *execlists)
{
- struct i915_priolist *p;
struct rb_node *rb;
rb = rb_first_cached(>queue);
if (!rb)
return INT_MIN;
- /*
-* As the priolist[] are inverted, with the highest priority in [0],
-* we have to flip the index value to become priority.
-*/
- p = to_priolist(rb);
- if (!I915_USER_PRIORITY_SHIFT)
- return p->priority;
-
- return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used);
+ return to_priolist(rb)->priority;
}
static int virtual_prio(const struct intel_engine_execlists *el)
@@ -1452,9 +1443,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
while ((rb = rb_first_cached(>queue))) {
struct i915_priolist *p = to_priolist(rb);
struct i915_request *rq, *rn;
- int i;
- priolist_for_each_request_consume(rq, rn, p, i) {
+ priolist_for_each_request_consume(rq, rn, p) {
bool merge = true;
/*
@@ -2968,9 +2958,8 @@ static void execlists_reset_cancel(struct intel_engine_cs
*engine)
/* Flush the queued requests to the timeline list (for retiring). */
while ((rb = rb_first_cached(>queue))) {
struct i915_priolist *p = to_priolist(rb);
- int i;
- priolist_for_each_request_consume(rq, rn, p, i) {
+ priolist_for_each_request_consume(rq, rn, p) {
i915_request_mark_eio(rq);
__i915_request_submit(rq);
}
@@ -3244,7 +3233,7 @@ int intel_execlists_submission_setup(struct
intel_engine_cs *engine)
static struct list_head *virtual_queue(struct virtual_engine *ve)
{
- return >base.execlists.default_priolist.requests[0];
+ return >base.execlists.default_priolist.requests;
}
static void rcu_virtual_context_destroy(struct work_struct *wrk)
@@ -3840,9 +3829,8 @@ void intel_execlists_show_requests(struct intel_engine_cs
*engine,
count = 0;
for (rb = rb_first_cached(>queue); rb; rb = rb_next(rb)) {
struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
- int i;
- priolist_for_each_request(rq, p, i) {
+ priolist_for_each_request(rq, p) {
if (count++ < max - 1)
show_request(m, rq, "\t\t", 0);
else
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 264b5ebdb021..6bce45f63f37 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -1081,7 +1081,6 @@ create_rewinder(struct intel_context *ce,
intel_ring_advance(rq, cs);
- rq->sched.attr.priority = I915_PRIORITY_MASK;
err = 0;
err:
i915_request_get(rq);
diff --git
[Intel-gfx] [PATCH 01/10] drm/i915/gt: Do not suspend bonded requests if one hangs
Treat the dependency between bonded requests as weak and leave the remainder of the pair on the GPU if one hangs. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 740ff05fd692..524c8b54d220 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -1990,6 +1990,9 @@ static void __execlists_hold(struct i915_request *rq) struct i915_request *w = container_of(p->waiter, typeof(*w), sched); + if (p->flags & I915_DEPENDENCY_WEAK) + continue; + /* Leave semaphores spinning on the other engines */ if (w->engine != rq->engine) continue; @@ -2088,6 +2091,9 @@ static void __execlists_unhold(struct i915_request *rq) struct i915_request *w = container_of(p->waiter, typeof(*w), sched); + if (p->flags & I915_DEPENDENCY_WEAK) + continue; + /* Propagate any change in error status */ if (rq->fence.error) i915_request_set_error_once(w, rq->fence.error); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/gt: Skip over completed active execlists, again
Now that we are careful to always force-restore contexts upon rewinding
(where necessary), we can restore our optimisation to skip over
completed active execlists when dequeuing.
Referenecs: 35f3fd8182ba ("drm/i915/execlists: Workaround switching back to a
completed context")
References: 8ab3a3812aa9 ("drm/i915/gt: Incrementally check for rewinding")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
.../drm/i915/gt/intel_execlists_submission.c | 34 +--
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 524c8b54d220..ac1be7a632d3 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1224,12 +1224,20 @@ static void set_preempt_timeout(struct intel_engine_cs
*engine,
active_preempt_timeout(engine, rq));
}
+static bool completed(const struct i915_request *rq)
+{
+ if (i915_request_has_sentinel(rq))
+ return false;
+
+ return __i915_request_is_complete(rq);
+}
+
static void execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = >execlists;
struct i915_request **port = execlists->pending;
struct i915_request ** const last_port = port + execlists->port_mask;
- struct i915_request *last = *execlists->active;
+ struct i915_request *last, * const *active;
struct virtual_engine *ve;
struct rb_node *rb;
bool submit = false;
@@ -1266,21 +1274,13 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* i.e. we will retrigger preemption following the ack in case
* of trouble.
*
-* In theory we can skip over completed contexts that have not
-* yet been processed by events (as those events are in flight):
-*
-* while ((last = *active) && i915_request_completed(last))
-* active++;
-*
-* However, the GPU cannot handle this as it will ultimately
-* find itself trying to jump back into a context it has just
-* completed and barf.
*/
+ active = execlists->active;
+ while ((last = *active) && completed(last))
+ active++;
if (last) {
- if (__i915_request_is_complete(last)) {
- goto check_secondary;
- } else if (need_preempt(engine, last)) {
+ if (need_preempt(engine, last)) {
ENGINE_TRACE(engine,
"preempting last=%llx:%lld, prio=%d,
hint=%d\n",
last->fence.context,
@@ -1359,9 +1359,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* we hopefully coalesce several updates into a single
* submission.
*/
-check_secondary:
- if (!list_is_last(>sched.link,
- >active.requests)) {
+ if (active[1]) {
/*
* Even if ELSP[1] is occupied and not worthy
* of timeslices, our queue might be.
@@ -1562,7 +1560,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* of ordered contexts.
*/
if (submit &&
- memcmp(execlists->active,
+ memcmp(active,
execlists->pending,
(port - execlists->pending) * sizeof(*port))) {
*port = NULL;
@@ -1570,7 +1568,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
execlists_schedule_in(*port, port - execlists->pending);
WRITE_ONCE(execlists->yield, -1);
- set_preempt_timeout(engine, *execlists->active);
+ set_preempt_timeout(engine, *active);
execlists_submit_ports(engine);
} else {
ring_set_paused(engine, 0);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/gt: Do not suspend bonded requests if one hangs
Treat the dependency between bonded requests as weak and leave the remainder of the pair on the GPU if one hangs. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 740ff05fd692..524c8b54d220 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -1990,6 +1990,9 @@ static void __execlists_hold(struct i915_request *rq) struct i915_request *w = container_of(p->waiter, typeof(*w), sched); + if (p->flags & I915_DEPENDENCY_WEAK) + continue; + /* Leave semaphores spinning on the other engines */ if (w->engine != rq->engine) continue; @@ -2088,6 +2091,9 @@ static void __execlists_unhold(struct i915_request *rq) struct i915_request *w = container_of(p->waiter, typeof(*w), sched); + if (p->flags & I915_DEPENDENCY_WEAK) + continue; + /* Propagate any change in error status */ if (rq->fence.error) i915_request_set_error_once(w, rq->fence.error); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Strip out internal priorities
Since we are not using any internal priority levels, and in the next few
patches will introduce a new index for which the optimisation is not so
lear cut, discard the small table within the priolist.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 22 ++--
drivers/gpu/drm/i915/gt/selftest_execlists.c | 1 -
drivers/gpu/drm/i915/gt/selftest_lrc.c| 1 -
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +--
drivers/gpu/drm/i915/i915_priolist_types.h| 8 +--
drivers/gpu/drm/i915/i915_scheduler.c | 51 +++
drivers/gpu/drm/i915/i915_scheduler.h | 16 ++
8 files changed, 20 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index d7be2b9339f9..1732a42e9075 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -125,7 +125,7 @@ static void heartbeat(struct work_struct *wrk)
* low latency and no jitter] the chance to naturally
* complete before being preempted.
*/
- attr.priority = I915_PRIORITY_MASK;
+ attr.priority = 0;
if (rq->sched.attr.priority >= attr.priority)
attr.priority |=
I915_USER_PRIORITY(I915_PRIORITY_HEARTBEAT);
if (rq->sched.attr.priority >= attr.priority)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 740ff05fd692..39c31f95d4dc 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -274,22 +274,13 @@ static int effective_prio(const struct i915_request *rq)
static int queue_prio(const struct intel_engine_execlists *execlists)
{
- struct i915_priolist *p;
struct rb_node *rb;
rb = rb_first_cached(>queue);
if (!rb)
return INT_MIN;
- /*
-* As the priolist[] are inverted, with the highest priority in [0],
-* we have to flip the index value to become priority.
-*/
- p = to_priolist(rb);
- if (!I915_USER_PRIORITY_SHIFT)
- return p->priority;
-
- return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used);
+ return to_priolist(rb)->priority;
}
static int virtual_prio(const struct intel_engine_execlists *el)
@@ -1454,9 +1445,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
while ((rb = rb_first_cached(>queue))) {
struct i915_priolist *p = to_priolist(rb);
struct i915_request *rq, *rn;
- int i;
- priolist_for_each_request_consume(rq, rn, p, i) {
+ priolist_for_each_request_consume(rq, rn, p) {
bool merge = true;
/*
@@ -2964,9 +2954,8 @@ static void execlists_reset_cancel(struct intel_engine_cs
*engine)
/* Flush the queued requests to the timeline list (for retiring). */
while ((rb = rb_first_cached(>queue))) {
struct i915_priolist *p = to_priolist(rb);
- int i;
- priolist_for_each_request_consume(rq, rn, p, i) {
+ priolist_for_each_request_consume(rq, rn, p) {
i915_request_mark_eio(rq);
__i915_request_submit(rq);
}
@@ -3240,7 +3229,7 @@ int intel_execlists_submission_setup(struct
intel_engine_cs *engine)
static struct list_head *virtual_queue(struct virtual_engine *ve)
{
- return >base.execlists.default_priolist.requests[0];
+ return >base.execlists.default_priolist.requests;
}
static void rcu_virtual_context_destroy(struct work_struct *wrk)
@@ -3836,9 +3825,8 @@ void intel_execlists_show_requests(struct intel_engine_cs
*engine,
count = 0;
for (rb = rb_first_cached(>queue); rb; rb = rb_next(rb)) {
struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
- int i;
- priolist_for_each_request(rq, p, i) {
+ priolist_for_each_request(rq, p) {
if (count++ < max - 1)
show_request(m, rq, "\t\t", 0);
else
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 264b5ebdb021..6bce45f63f37 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -1081,7 +1081,6 @@ create_rewinder(struct intel_context *ce,
intel_ring_advance(rq, cs);
- rq->sched.attr.priority = I915_PRIORITY_MASK;
err = 0;
err:
i915_request_get(rq);
diff --git
[Intel-gfx] [PATCH 2/2] drm/i915: Remove I915_USER_PRIORITY_SHIFT
As we do not have any internal priority levels, the priority can be set
directed from the user values.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +--
.../i915/gem/selftests/i915_gem_object_blt.c | 4 +-
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 10 ++---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 44 +++
drivers/gpu/drm/i915/i915_priolist_types.h| 3 --
drivers/gpu/drm/i915/i915_scheduler.c | 1 -
7 files changed, 24 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 7373f54b216e..6f04f85812fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13543,9 +13543,7 @@ int
intel_prepare_plane_fb(struct drm_plane *_plane,
struct drm_plane_state *_new_plane_state)
{
- struct i915_sched_attr attr = {
- .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
- };
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
struct intel_plane *plane = to_intel_plane(_plane);
struct intel_plane_state *new_plane_state =
to_intel_plane_state(_new_plane_state);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 4d2f40cf237b..61a7360c4d9a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -679,7 +679,7 @@ __create_context(struct drm_i915_private *i915)
kref_init(>ref);
ctx->i915 = i915;
- ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL);
+ ctx->sched.priority = I915_PRIORITY_NORMAL;
mutex_init(>mutex);
INIT_LIST_HEAD(>link);
@@ -1959,7 +1959,7 @@ static int set_priority(struct i915_gem_context *ctx,
!capable(CAP_SYS_NICE))
return -EPERM;
- ctx->sched.priority = I915_USER_PRIORITY(priority);
+ ctx->sched.priority = priority;
context_apply_all(ctx, __apply_priority, ctx);
return 0;
@@ -2463,7 +2463,7 @@ int i915_gem_context_getparam_ioctl(struct drm_device
*dev, void *data,
case I915_CONTEXT_PARAM_PRIORITY:
args->size = 0;
- args->value = ctx->sched.priority >> I915_USER_PRIORITY_SHIFT;
+ args->value = ctx->sched.priority;
break;
case I915_CONTEXT_PARAM_SSEU:
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
index 23b6e11bbc3e..c4c04fb97d14 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
@@ -220,7 +220,7 @@ static int igt_fill_blt_thread(void *arg)
return PTR_ERR(ctx);
prio = i915_prandom_u32_max_state(I915_PRIORITY_MAX, prng);
- ctx->sched.priority = I915_USER_PRIORITY(prio);
+ ctx->sched.priority = prio;
}
ce = i915_gem_context_get_engine(ctx, 0);
@@ -338,7 +338,7 @@ static int igt_copy_blt_thread(void *arg)
return PTR_ERR(ctx);
prio = i915_prandom_u32_max_state(I915_PRIORITY_MAX, prng);
- ctx->sched.priority = I915_USER_PRIORITY(prio);
+ ctx->sched.priority = prio;
}
ce = i915_gem_context_get_engine(ctx, 0);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index 1732a42e9075..ed03c08737f5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -81,9 +81,7 @@ static void show_heartbeat(const struct i915_request *rq,
static void heartbeat(struct work_struct *wrk)
{
- struct i915_sched_attr attr = {
- .priority = I915_USER_PRIORITY(I915_PRIORITY_MIN),
- };
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_MIN };
struct intel_engine_cs *engine =
container_of(wrk, typeof(*engine), heartbeat.work.work);
struct intel_context *ce = engine->kernel_context;
@@ -127,7 +125,7 @@ static void heartbeat(struct work_struct *wrk)
*/
attr.priority = 0;
if (rq->sched.attr.priority >= attr.priority)
- attr.priority |=
I915_USER_PRIORITY(I915_PRIORITY_HEARTBEAT);
+ attr.priority = I915_PRIORITY_HEARTBEAT;
if (rq->sched.attr.priority >= attr.priority)
attr.priority = I915_PRIORITY_BARRIER;
@@ -285,9 +283,7 @@ int intel_engine_pulse(struct intel_engine_cs *engine)
int intel_engine_flush_barriers(struct
