[Intel-gfx] [PATCH v14 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs
In order to support the PSR state of each transcoder, it adds
i915_psr_status to sub-directory of each transcoder.
v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
permissions '0444'
v5: Addressed JJani Nikula's review comments
- Remove checking of Gen12 for i915_psr_status.
- Add check of HAS_PSR()
- Remove meaningless check routine.
Signed-off-by: Gwan-gyeong Mun
Cc: José Roberto de Souza
Cc: Jani Nikula
Cc: Anshuman Gupta
Reviewed-by: Anshuman Gupta
---
.../gpu/drm/i915/display/intel_display_debugfs.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index b1bda1f5ef16..d6e4a9237bda 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -2211,6 +2211,16 @@ static int i915_hdcp_sink_capability_show(struct
seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
+static int i915_psr_status_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct intel_dp *intel_dp =
+ intel_attached_dp(to_intel_connector(connector));
+
+ return intel_psr_status(m, intel_dp);
+}
+DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
+
#define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
seq_puts(m, "LPSP: incapable\n"))
@@ -2386,6 +2396,12 @@ int intel_connector_debugfs_add(struct drm_connector
*connector)
connector, _psr_sink_status_fops);
}
+ if (HAS_PSR(dev_priv) &&
+ connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+ debugfs_create_file("i915_psr_status", 0444, root,
+ connector, _psr_status_fops);
+ }
+
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v14 1/2] drm/i915/display: Support PSR Multiple Instances
It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt handling routine for supporting
multiple transcoders. But it does not change the scenario and timing of
enabling and disabling PSR. And it not support multiple pipes with
a single transcoder PSR case yet.
v2: Fix indentation and add comments
v3: Remove Blank line
v4: Rebased
v5: Rebased and Addressed Anshuman's review comment.
- Move calling of intel_psr_init() to intel_dp_init_connector()
v6: Address Anshuman's review comments
- Remove wrong comments and add comments for a limit of supporting of
a single pipe PSR
v7: Update intel_psr_compute_config() for supporting multiple transcoder
PSR on BDW+
v8: Address Anshuman's review comments
- Replace DRM_DEBUG_KMS with drm_dbg_kms() / DRM_WARN with drm_warn()
v9: Fix commit message
v10: Rebased
v11: Address Jose's review comment.
- Reorder calling order of intel_psr2_program_trans_man_trk_ctl().
- In order to reduce changes keep the old name for drm_i915_private.
- Change restrictions of multiple instances of PSR.
v12: Address Jose's review comment.
- Change the calling of intel_psr2_program_trans_man_trk_ctl() into
commit_pipe_config().
- Change a checking order of CAN_PSR() and connector_status to original
on i915_psr_sink_status_show().
- Drop unneeded intel_dp_update_pipe() function.
- In order to wait a specific encoder which belong to crtc_state on
intel_psr_wait_for_idle(), add checking of encoder.
- Add an whitespace to comments.
v13: Rebased and Address Jose's review comment.
- Add and use for_each_intel_psr_enabled_encoder() macro.
- In order to use correct frontbuffer_bit for each pipe,
fix intel_psr_invalidate() and intel_psr_flush().
- Remove redundant or unneeded codes.
- Update comments.
v14: Address Jose's review comment
- Add and use for_each_intel_encoder_can_psr() macro and
for_each_intel_encoder_mask_can_psr() macro.
- Add source_support member variable into intel_psr structure.
- Update CAN_PSR() macro that checks source_support.
- Move encoder's PSR availity check to psr_init() from
psr_compute_config().
- Remove redundant or unneeded codes.
Signed-off-by: Gwan-gyeong Mun
Cc: José Roberto de Souza
Cc: Juha-Pekka Heikkila
Cc: Anshuman Gupta
Reviewed-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 2 -
drivers/gpu/drm/i915/display/intel_display.h | 9 +
.../drm/i915/display/intel_display_debugfs.c | 95 ++-
.../drm/i915/display/intel_display_types.h| 51 ++
drivers/gpu/drm/i915/display/intel_dp.c | 10 +-
drivers/gpu/drm/i915/display/intel_psr.c | 605 ++
drivers/gpu/drm/i915/display/intel_psr.h | 10 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 38 --
drivers/gpu/drm/i915/i915_irq.c | 42 +-
10 files changed, 492 insertions(+), 376 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d013b0fab128..163a2c4eb313 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14141,8 +14141,6 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_dvo_init(dev_priv);
}
- intel_psr_init(dev_priv);
-
for_each_intel_encoder(_priv->drm, encoder) {
encoder->base.possible_crtcs =
intel_encoder_possible_crtcs(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 64ffa34544a7..c72e41b61349 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -417,10 +417,19 @@ enum phy_fia {
for_each_if((encoder_mask) &\
drm_encoder_mask(_encoder->base))
+#define for_each_intel_encoder_mask_can_psr(dev, intel_encoder, encoder_mask) \
+ list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list,
base.head) \
+ for_each_if(((encoder_mask) &
drm_encoder_mask(&(intel_encoder)->base)) && \
+ intel_encoder_can_psr(intel_encoder))
+
#define for_each_intel_dp(dev, intel_encoder) \
for_each_intel_encoder(dev, intel_encoder) \
for_each_if(intel_encoder_is_dp(intel_encoder))
+#define for_each_intel_encoder_can_psr(dev, intel_encoder) \
+ for_each_intel_encoder((dev), (intel_encoder)) \
+ for_each_if(intel_encoder_can_psr(intel_encoder))
+
#define for_each_intel_connector_iter(intel_connector, iter) \
while
[Intel-gfx] ✓ Fi.CI.BAT: success for disable the QSES check for HDCP2.2 over MST (rev2)
== Series Details == Series: disable the QSES check for HDCP2.2 over MST (rev2) URL : https://patchwork.freedesktop.org/series/86375/ State : success == Summary == CI Bug Log - changes from CI_DRM_9697 -> Patchwork_19536 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19536/index.html Known issues Here are the changes found in Patchwork_19536 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@sanitycheck: - fi-kbl-7500u: [PASS][1] -> [DMESG-WARN][2] ([i915#2605]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9697/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19536/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9697/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19536/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9697/fi-tgl-y/igt@debugfs_test@read_all_entries.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19536/fi-tgl-y/igt@debugfs_test@read_all_entries.html [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 38) -- Missing(5): fi-kbl-soraka fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan Build changes - * Linux: CI_DRM_9697 -> Patchwork_19536 CI-20190529: 20190529 CI_DRM_9697: f4f5294bd767b553ae354d78607c530049351b0b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5978: e1e5b3fea2baafdae0160940ecb8bf0242703840 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19536: 603c4c91a321e4333e408ea1bef5224c99838441 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 603c4c91a321 drm/i915/hdcp: disable the QSES check for HDCP2.2 over MST == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19536/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/gvt: Parse default state to update reg whitelist
On 2021.01.29 00:49:32 +, Chris Wilson wrote:
> Rather than break existing context objects by incorrectly forcing them
> to rogue cache coherency and trying to assert a new mapping, read the
> reg whitelist from the default context image.
>
So this work actually lived within internal for some time, previously
we found that i915 didn't guarantee each engine's default_state would
be always valid, e.g for media engines if I remember correctly...so we
tried to get init hw state then. Currently looks i915 always ensure
default state for each engine, otherwise it would claim gt wedged, so
it's fine that we switch to i915 default state now.
Acked-by: Zhenyu Wang
I'd like to queue this through gvt tree, so we could get regression test
with VM before merging.
Thanks!
> And use gvt->gt, never _priv->gt.
>
> Fixes: 493f30cd086e ("drm/i915/gvt: parse init context to update cmd
> accessible reg whitelist")
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Kevin Tian
> Cc: Wang Zhi
> Cc: Yan Zhao
> Cc: Zhenyu Wang
> Cc: Zhi Wang
> ---
> drivers/gpu/drm/i915/gvt/cmd_parser.c | 93 ++-
> 1 file changed, 20 insertions(+), 73 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index 9a7087830cc2..ec6ea11d747f 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -41,6 +41,7 @@
> #include "gt/intel_lrc.h"
> #include "gt/intel_ring.h"
> #include "gt/intel_gt_requests.h"
> +#include "gt/shmem_utils.h"
> #include "gvt.h"
> #include "i915_pvinfo.h"
> #include "trace.h"
> @@ -3087,71 +3088,28 @@ int intel_gvt_scan_and_shadow_wa_ctx(struct
> intel_shadow_wa_ctx *wa_ctx)
> */
> void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu)
> {
> + const unsigned long start = LRC_STATE_PN * PAGE_SIZE;
> struct intel_gvt *gvt = vgpu->gvt;
> - struct drm_i915_private *dev_priv = gvt->gt->i915;
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
> - const unsigned long start = LRC_STATE_PN * PAGE_SIZE;
> - struct i915_request *rq;
> - struct intel_vgpu_submission *s = >submission;
> - struct i915_request *requests[I915_NUM_ENGINES] = {};
> - bool is_ctx_pinned[I915_NUM_ENGINES] = {};
> - int ret = 0;
>
> if (gvt->is_reg_whitelist_updated)
> return;
>
> - for_each_engine(engine, _priv->gt, id) {
> - ret = intel_context_pin(s->shadow[id]);
> - if (ret) {
> - gvt_vgpu_err("fail to pin shadow ctx\n");
> - goto out;
> - }
> - is_ctx_pinned[id] = true;
> -
> - rq = i915_request_create(s->shadow[id]);
> - if (IS_ERR(rq)) {
> - gvt_vgpu_err("fail to alloc default request\n");
> - ret = -EIO;
> - goto out;
> - }
> - requests[id] = i915_request_get(rq);
> - i915_request_add(rq);
> - }
> -
> - if (intel_gt_wait_for_idle(_priv->gt,
> - I915_GEM_IDLE_TIMEOUT) == -ETIME) {
> - ret = -EIO;
> - goto out;
> - }
> -
> /* scan init ctx to update cmd accessible list */
> - for_each_engine(engine, _priv->gt, id) {
> - int size = engine->context_size - PAGE_SIZE;
> - void *vaddr;
> + for_each_engine(engine, gvt->gt, id) {
> struct parser_exec_state s;
> - struct drm_i915_gem_object *obj;
> - struct i915_request *rq;
> + void *vaddr;
> + int ret;
>
> - rq = requests[id];
> - GEM_BUG_ON(!i915_request_completed(rq));
> - GEM_BUG_ON(!intel_context_is_pinned(rq->context));
> - obj = rq->context->state->obj;
> + if (!engine->default_state)
> + continue;
>
> - if (!obj) {
> - ret = -EIO;
> - goto out;
> - }
> -
> - i915_gem_object_set_cache_coherency(obj,
> - I915_CACHE_LLC);
> -
> - vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
> + vaddr = shmem_pin_map(engine->default_state);
> if (IS_ERR(vaddr)) {
> - gvt_err("failed to pin init ctx obj, ring=%d,
> err=%lx\n",
> - id, PTR_ERR(vaddr));
> - ret = PTR_ERR(vaddr);
> - goto out;
> + gvt_err("failed to map %s->default state, err:%zd\n",
> + engine->name, PTR_ERR(vaddr));
> + return;
> }
>
> s.buf_type = RING_BUFFER_CTX;
> @@ -3159,9 +3117,9 @@ void intel_gvt_update_reg_whitelist(struct intel_vgpu
> *vgpu)
> s.vgpu = vgpu;
> s.engine =
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm: Move struct drm_device.pdev to legacy (rev6)
== Series Details == Series: drm: Move struct drm_device.pdev to legacy (rev6) URL : https://patchwork.freedesktop.org/series/84205/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9693_full -> Patchwork_19528_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19528_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19528_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19528_full: ### IGT changes ### Possible regressions * igt@kms_lease@page_flip_implicit_plane: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-tglb1/igt@kms_lease@page_flip_implicit_plane.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19528/shard-tglb5/igt@kms_lease@page_flip_implicit_plane.html Known issues Here are the changes found in Patchwork_19528_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@idempotent: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19528/shard-snb2/igt@gem_ctx_persiste...@idempotent.html * igt@gem_exec_fair@basic-none@vcs1: - shard-kbl: [PASS][4] -> [FAIL][5] ([i915#2842]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs1.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19528/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19528/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-tglb5/igt@gem_exec_fair@basic-p...@vecs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19528/shard-tglb6/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-apl: [PASS][10] -> [FAIL][11] ([i915#2389]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-apl2/igt@gem_exec_reloc@basic-many-act...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19528/shard-apl2/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_exec_schedule@u-fairslice@vecs0: - shard-skl: [PASS][12] -> [DMESG-WARN][13] ([i915#1610] / [i915#2803]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-skl3/igt@gem_exec_schedule@u-fairsl...@vecs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19528/shard-skl8/igt@gem_exec_schedule@u-fairsl...@vecs0.html * igt@gen7_exec_parse@basic-offset: - shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271]) +9 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19528/shard-glk6/igt@gen7_exec_pa...@basic-offset.html * igt@gen9_exec_parse@allowed-all: - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#1436] / [i915#716]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-glk8/igt@gen9_exec_pa...@allowed-all.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19528/shard-glk6/igt@gen9_exec_pa...@allowed-all.html * igt@i915_pm_lpsp@screens-disabled: - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271]) +32 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19528/shard-skl2/igt@i915_pm_l...@screens-disabled.html * igt@i915_pm_rpm@system-suspend-modeset: - shard-skl: [PASS][18] -> [INCOMPLETE][19] ([i915#151]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-skl2/igt@i915_pm_...@system-suspend-modeset.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19528/shard-skl5/igt@i915_pm_...@system-suspend-modeset.html * igt@kms_chamelium@vga-hpd: - shard-snb: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +2 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19528/shard-snb2/igt@kms_chamel...@vga-hpd.html * igt@kms_color@pipe-c-ctm-0-5: - shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-skl2/igt@kms_co...@pipe-c-ctm-0-5.html [22]:
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v5,1/8] drm/i915: make local-memory probing a GT operation (rev2)
== Series Details ==
Series: series starting with [v5,1/8] drm/i915: make local-memory probing a GT
operation (rev2)
URL : https://patchwork.freedesktop.org/series/86355/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9693_full -> Patchwork_19527_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19527_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@sysfs_clients@busy@vcs0}:
- shard-iclb: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-iclb5/igt@sysfs_clients@b...@vcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19527/shard-iclb6/igt@sysfs_clients@b...@vcs0.html
Known issues
Here are the changes found in Patchwork_19527_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@idempotent:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19527/shard-snb6/igt@gem_ctx_persiste...@idempotent.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [PASS][4] -> [INCOMPLETE][5] ([i915#2369])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-skl1/igt@gem_exec_capture@p...@rcs0.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19527/shard-skl6/igt@gem_exec_capture@p...@rcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2846])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-kbl4/igt@gem_exec_f...@basic-deadline.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19527/shard-kbl4/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-apl: [PASS][8] -> [SKIP][9] ([fdo#109271])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-apl7/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19527/shard-apl2/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-kbl7/igt@gem_exec_fair@basic-none-...@rcs0.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19527/shard-kbl7/igt@gem_exec_fair@basic-none-...@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19527/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: NOTRUN -> [FAIL][14] ([i915#2842])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19527/shard-iclb4/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar
issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-tglb5/igt@gem_exec_fair@basic-p...@vcs1.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19527/shard-tglb6/igt@gem_exec_fair@basic-p...@vcs1.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-iclb: NOTRUN -> [SKIP][17] ([fdo#109313])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19527/shard-iclb4/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html
* igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][18] ([fdo#112283])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19527/shard-iclb4/igt@gem_exec_par...@secure-non-root.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#1610] /
[i915#2803])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-glk4/igt@gem_exec_schedule@u-fairsl...@rcs0.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19527/shard-glk2/igt@gem_exec_schedule@u-fairsl...@rcs0.html
* igt@gem_exec_schedule@u-fairslice@vcs0:
- shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1610] /
[i915#2803])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9693/shard-skl3/igt@gem_exec_schedule@u-fairsl...@vcs0.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19527/shard-skl10/igt@gem_exec_schedule@u-fairsl...@vcs0.html
- shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#1610] /
[i915#2803])
[23]:
Re: [Intel-gfx] [RFC PATCH 0/9] cgroup support for GPU devices
On 2021/1/27 上午5:46, Brian Welty wrote: > We'd like to revisit the proposal of a GPU cgroup controller for managing > GPU devices but with just a basic set of controls. This series is based on > the prior patch series from Kenny Ho [1]. We take Kenny's base patches > which implement the basic framework for the controller, but we propose an > alternate set of control files. Here we've taken a subset of the controls > proposed in earlier discussion on ML here [2]. > > This series proposes a set of device memory controls (gpu.memory.current, > gpu.memory.max, and gpu.memory.total) and accounting of GPU time usage > (gpu.sched.runtime). GPU time sharing controls are left as future work. > These are implemented within the GPU controller along with integration/usage > of the device memory controls by the i915 device driver. > > As an accelerator or GPU device is similar in many respects to a CPU with > (or without) attached system memory, the basic principle here is try to > copy the semantics of existing controls from other controllers when possible > and where these controls serve the same underlying purpose. > For example, the memory.max and memory.current controls are based on > same controls from MEMCG controller. It seems not to be DRM specific, or even GPU specific. Would we have an universal control group for any accelerator, GPGPU device etc, that hold sharable resources like device memory, compute utility, bandwidth, with extra control file to select between devices(or vendors)? e.g. /cgname.device that stores PCI BDF， or enum(intel, amdgpu, nvidia, ...), defaults to none, means not enabled. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 0/9] cgroup support for GPU devices
On 2021/1/27 上午5:46, Brian Welty wrote: > We'd like to revisit the proposal of a GPU cgroup controller for managing > GPU devices but with just a basic set of controls. This series is based on > the prior patch series from Kenny Ho [1]. We take Kenny's base patches > which implement the basic framework for the controller, but we propose an > alternate set of control files. Here we've taken a subset of the controls > proposed in earlier discussion on ML here [2]. > > This series proposes a set of device memory controls (gpu.memory.current, > gpu.memory.max, and gpu.memory.total) and accounting of GPU time usage > (gpu.sched.runtime). GPU time sharing controls are left as future work. > These are implemented within the GPU controller along with integration/usage > of the device memory controls by the i915 device driver. > > As an accelerator or GPU device is similar in many respects to a CPU with > (or without) attached system memory, the basic principle here is try to > copy the semantics of existing controls from other controllers when possible > and where these controls serve the same underlying purpose. > For example, the memory.max and memory.current controls are based on > same controls from MEMCG controller. It seems not to be DRM specific, or even GPU specific. Would we have an universal control group for any accelerator, GPGPU device etc, that hold sharable resources like device memory, compute utility, bandwidth, with extra control file to select between devices(or vendors)? e.g. /cgname.device that stores PCI BDF， or enum(intel, amdgpu, nvidia, ...), defaults to none, means not enabled. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gvt: Parse default state to update reg whitelist
== Series Details == Series: series starting with [1/2] drm/i915/gvt: Parse default state to update reg whitelist URL : https://patchwork.freedesktop.org/series/86425/ State : success == Summary == CI Bug Log - changes from CI_DRM_9696 -> Patchwork_19535 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/index.html Known issues Here are the changes found in Patchwork_19535 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@debugfs_test@read_all_entries: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/fi-tgl-y/igt@debugfs_test@read_all_entries.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@kms_chamelium@dp-crc-fast: - fi-cml-u2: [PASS][4] -> [FAIL][5] ([i915#1161] / [i915#262]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html Possible fixes * igt@i915_selftest@live@execlists: - fi-bsw-nick:[INCOMPLETE][6] ([i915#2940]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling: - fi-tgl-y: [DMESG-WARN][8] ([i915#402]) -> [PASS][9] +2 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/fi-tgl-y/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/fi-tgl-y/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (44 -> 39) -- Missing(5): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9696 -> Patchwork_19535 CI-20190529: 20190529 CI_DRM_9696: 9fee71c4c03d8101401b895315a97f970036c6a0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5977: 0b6967520b15e73773eace7937ed8c17ba411bc0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19535: 31e991c6343c14920a80bccd776d828805bc8ebf @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 31e991c6343c drm/i915/gvt: Purge dev_priv->gt d6ae99d96b25 drm/i915/gvt: Parse default state to update reg whitelist == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/gvt: Parse default state to update reg whitelist
Rather than break existing context objects by incorrectly forcing them
to rogue cache coherency and trying to assert a new mapping, read the
reg whitelist from the default context image.
And use gvt->gt, never _priv->gt.
Fixes: 493f30cd086e ("drm/i915/gvt: parse init context to update cmd accessible
reg whitelist")
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Kevin Tian
Cc: Wang Zhi
Cc: Yan Zhao
Cc: Zhenyu Wang
Cc: Zhi Wang
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 93 ++-
1 file changed, 20 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 9a7087830cc2..ec6ea11d747f 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -41,6 +41,7 @@
#include "gt/intel_lrc.h"
#include "gt/intel_ring.h"
#include "gt/intel_gt_requests.h"
+#include "gt/shmem_utils.h"
#include "gvt.h"
#include "i915_pvinfo.h"
#include "trace.h"
@@ -3087,71 +3088,28 @@ int intel_gvt_scan_and_shadow_wa_ctx(struct
intel_shadow_wa_ctx *wa_ctx)
*/
void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu)
{
+ const unsigned long start = LRC_STATE_PN * PAGE_SIZE;
struct intel_gvt *gvt = vgpu->gvt;
- struct drm_i915_private *dev_priv = gvt->gt->i915;
struct intel_engine_cs *engine;
enum intel_engine_id id;
- const unsigned long start = LRC_STATE_PN * PAGE_SIZE;
- struct i915_request *rq;
- struct intel_vgpu_submission *s = >submission;
- struct i915_request *requests[I915_NUM_ENGINES] = {};
- bool is_ctx_pinned[I915_NUM_ENGINES] = {};
- int ret = 0;
if (gvt->is_reg_whitelist_updated)
return;
- for_each_engine(engine, _priv->gt, id) {
- ret = intel_context_pin(s->shadow[id]);
- if (ret) {
- gvt_vgpu_err("fail to pin shadow ctx\n");
- goto out;
- }
- is_ctx_pinned[id] = true;
-
- rq = i915_request_create(s->shadow[id]);
- if (IS_ERR(rq)) {
- gvt_vgpu_err("fail to alloc default request\n");
- ret = -EIO;
- goto out;
- }
- requests[id] = i915_request_get(rq);
- i915_request_add(rq);
- }
-
- if (intel_gt_wait_for_idle(_priv->gt,
- I915_GEM_IDLE_TIMEOUT) == -ETIME) {
- ret = -EIO;
- goto out;
- }
-
/* scan init ctx to update cmd accessible list */
- for_each_engine(engine, _priv->gt, id) {
- int size = engine->context_size - PAGE_SIZE;
- void *vaddr;
+ for_each_engine(engine, gvt->gt, id) {
struct parser_exec_state s;
- struct drm_i915_gem_object *obj;
- struct i915_request *rq;
+ void *vaddr;
+ int ret;
- rq = requests[id];
- GEM_BUG_ON(!i915_request_completed(rq));
- GEM_BUG_ON(!intel_context_is_pinned(rq->context));
- obj = rq->context->state->obj;
+ if (!engine->default_state)
+ continue;
- if (!obj) {
- ret = -EIO;
- goto out;
- }
-
- i915_gem_object_set_cache_coherency(obj,
- I915_CACHE_LLC);
-
- vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ vaddr = shmem_pin_map(engine->default_state);
if (IS_ERR(vaddr)) {
- gvt_err("failed to pin init ctx obj, ring=%d,
err=%lx\n",
- id, PTR_ERR(vaddr));
- ret = PTR_ERR(vaddr);
- goto out;
+ gvt_err("failed to map %s->default state, err:%zd\n",
+ engine->name, PTR_ERR(vaddr));
+ return;
}
s.buf_type = RING_BUFFER_CTX;
@@ -3159,9 +3117,9 @@ void intel_gvt_update_reg_whitelist(struct intel_vgpu
*vgpu)
s.vgpu = vgpu;
s.engine = engine;
s.ring_start = 0;
- s.ring_size = size;
+ s.ring_size = engine->context_size - start;
s.ring_head = 0;
- s.ring_tail = size;
+ s.ring_tail = s.ring_size;
s.rb_va = vaddr + start;
s.workload = NULL;
s.is_ctx_wa = false;
@@ -3169,29 +3127,18 @@ void intel_gvt_update_reg_whitelist(struct intel_vgpu
*vgpu)
/* skipping the first RING_CTX_SIZE(0x50) dwords */
ret = ip_gma_set(, RING_CTX_SIZE);
- if (ret) {
- i915_gem_object_unpin_map(obj);
- goto out;
[Intel-gfx] [PATCH 2/2] drm/i915/gvt: Purge dev_priv->gt
Use the right intel_gt stored as a backpointer in intel_vgpu.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gvt/execlist.c | 8 +++-
drivers/gpu/drm/i915/gvt/scheduler.c | 3 +--
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c
b/drivers/gpu/drm/i915/gvt/execlist.c
index 158873f269b1..c8dcda6d4f0d 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.c
+++ b/drivers/gpu/drm/i915/gvt/execlist.c
@@ -522,12 +522,11 @@ static void init_vgpu_execlist(struct intel_vgpu *vgpu,
static void clean_execlist(struct intel_vgpu *vgpu,
intel_engine_mask_t engine_mask)
{
- struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
- struct intel_engine_cs *engine;
struct intel_vgpu_submission *s = >submission;
+ struct intel_engine_cs *engine;
intel_engine_mask_t tmp;
- for_each_engine_masked(engine, _priv->gt, engine_mask, tmp) {
+ for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) {
kfree(s->ring_scan_buffer[engine->id]);
s->ring_scan_buffer[engine->id] = NULL;
s->ring_scan_buffer_size[engine->id] = 0;
@@ -537,11 +536,10 @@ static void clean_execlist(struct intel_vgpu *vgpu,
static void reset_execlist(struct intel_vgpu *vgpu,
intel_engine_mask_t engine_mask)
{
- struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
struct intel_engine_cs *engine;
intel_engine_mask_t tmp;
- for_each_engine_masked(engine, _priv->gt, engine_mask, tmp)
+ for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp)
init_vgpu_execlist(vgpu, engine);
}
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c
b/drivers/gpu/drm/i915/gvt/scheduler.c
index 43f31c2eab14..a55ae50dbbe1 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1015,13 +1015,12 @@ void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
intel_engine_mask_t engine_mask)
{
struct intel_vgpu_submission *s = >submission;
- struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
struct intel_engine_cs *engine;
struct intel_vgpu_workload *pos, *n;
intel_engine_mask_t tmp;
/* free the unsubmited workloads in the queues. */
- for_each_engine_masked(engine, _priv->gt, engine_mask, tmp) {
+ for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) {
list_for_each_entry_safe(pos, n,
>workload_q_head[engine->id], list) {
list_del_init(>list);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 20/41] drm/i915: Replace priolist rbtree with a skiplist
On Mon, Jan 25, 2021 at 02:01:15PM +, Chris Wilson wrote:
> Replace the priolist rbtree with a skiplist. The crucial difference is
> that walking and removing the first element of a skiplist is O(1), but
> O(lgN) for an rbtree, as we need to rebalance on remove. This is a
> hindrance for submission latency as it occurs between picking a request
> for the priolist and submitting it to hardware, as well effectively
> trippling the number of O(lgN) operations required under the irqoff lock.
> This is critical to reducing the latency jitter with multiple clients.
>
> The downsides to skiplists are that lookup/insertion is only
> probablistically O(lgN) and there is a significant memory penalty to
> as each skip node is larger than the rbtree equivalent. Furthermore, we
> don't use dynamic arrays for the skiplist, so the allocation is fixed,
> and imposes an upper bound on the scalability wrt to the number of
> inflight requests.
>
This is a fun data structure but IMO might be overkill to maintain this
code in the i915. The UMDs have effectively agreed to use only 3 levels,
is O(lgN) where N == 3 really a big deal? With GuC submission we will
statically map all user levels into 3 buckets. If we are doing that, do
we even need a complex data structure? i.e. Could use just use can
array of linked lists?
Also BTW, seems like people are having a hard time understanding what a
skip list is, might have just started with the below link which explains
it quite nicely:
https://en.wikipedia.org/wiki/Skip_list
Matt
> Signed-off-by: Chris Wilson
> ---
> .../drm/i915/gt/intel_execlists_submission.c | 63 +++--
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 30 +--
> drivers/gpu/drm/i915/i915_priolist_types.h| 28 +-
> drivers/gpu/drm/i915/i915_scheduler.c | 244 ++
> drivers/gpu/drm/i915/i915_scheduler.h | 11 +-
> drivers/gpu/drm/i915/i915_scheduler_types.h | 2 +-
> .../drm/i915/selftests/i915_mock_selftests.h | 1 +
> .../gpu/drm/i915/selftests/i915_scheduler.c | 53 +++-
> 8 files changed, 316 insertions(+), 116 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 1103c8a00af1..129144dd86b0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -244,11 +244,6 @@ static void ring_set_paused(const struct intel_engine_cs
> *engine, int state)
> wmb();
> }
>
> -static struct i915_priolist *to_priolist(struct rb_node *rb)
> -{
> - return rb_entry(rb, struct i915_priolist, node);
> -}
> -
> static int rq_prio(const struct i915_request *rq)
> {
> return READ_ONCE(rq->sched.attr.priority);
> @@ -272,15 +267,31 @@ static int effective_prio(const struct i915_request *rq)
> return prio;
> }
>
> -static int queue_prio(const struct i915_sched_engine *se)
> +static struct i915_request *first_request(struct i915_sched_engine *se)
> {
> - struct rb_node *rb;
> + struct i915_priolist *pl;
>
> - rb = rb_first_cached(>queue);
> - if (!rb)
> + for_each_priolist(pl, >queue) {
> + if (likely(!list_empty(>requests)))
> + return list_first_entry(>requests,
> + struct i915_request,
> + sched.link);
> +
> + i915_priolist_advance(>queue, pl);
> + }
> +
> + return NULL;
> +}
> +
> +static int queue_prio(struct i915_sched_engine *se)
> +{
> + struct i915_request *rq;
> +
> + rq = first_request(se);
> + if (!rq)
> return INT_MIN;
>
> - return to_priolist(rb)->priority;
> + return rq_prio(rq);
> }
>
> static int virtual_prio(const struct intel_engine_execlists *el)
> @@ -290,7 +301,7 @@ static int virtual_prio(const struct
> intel_engine_execlists *el)
> return rb ? rb_entry(rb, struct ve_node, rb)->prio : INT_MIN;
> }
>
> -static bool need_preempt(const struct intel_engine_cs *engine,
> +static bool need_preempt(struct intel_engine_cs *engine,
>const struct i915_request *rq)
> {
> int last_prio;
> @@ -1136,6 +1147,7 @@ static void execlists_dequeue(struct intel_engine_cs
> *engine)
> struct i915_request ** const last_port = port + execlists->port_mask;
> struct i915_request *last, * const *active;
> struct virtual_engine *ve;
> + struct i915_priolist *pl;
> struct rb_node *rb;
> bool submit = false;
>
> @@ -1346,11 +1358,10 @@ static void execlists_dequeue(struct intel_engine_cs
> *engine)
> break;
> }
>
> - while ((rb = rb_first_cached(>active.queue))) {
> - struct i915_priolist *p = to_priolist(rb);
> + for_each_priolist(pl, >active.queue) {
> struct i915_request *rq, *rn;
>
> - priolist_for_each_request_consume(rq,
Re: [Intel-gfx] [PATCH 20/41] drm/i915: Replace priolist rbtree with a skiplist
Quoting Tvrtko Ursulin (2021-01-28 16:42:44)
>
> On 28/01/2021 16:26, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2021-01-28 15:56:19)
> >> On 25/01/2021 14:01, Chris Wilson wrote:
> >>> diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h
> >>> b/drivers/gpu/drm/i915/i915_priolist_types.h
> >>> index bc2fa84f98a8..1200c3df6a4a 100644
> >>> --- a/drivers/gpu/drm/i915/i915_priolist_types.h
> >>> +++ b/drivers/gpu/drm/i915/i915_priolist_types.h
> >>> @@ -38,10 +38,36 @@ enum {
> >>>#define I915_PRIORITY_UNPREEMPTABLE INT_MAX
> >>>#define I915_PRIORITY_BARRIER (I915_PRIORITY_UNPREEMPTABLE - 1)
> >>>
> >>> +#ifdef CONFIG_64BIT
> >>> +#define I915_PRIOLIST_HEIGHT 12
> >>> +#else
> >>> +#define I915_PRIOLIST_HEIGHT 11
> >>> +#endif
> >>
> >> I did not get this. On one hand I could think pointers are larger on
> >> 64-bit so go for fewer levels, if size was a concern. But on the other
> >> hand 32-bit is less important these days, definitely much less as a
> >> performance platform. So going for less memory use => worse performance
> >> on a less important platform, which typically could be more memory
> >> constrained? Not sure I see it as that important either way to be
> >> distinctive but a comment would satisfy me.
> >
> > Just aligned to the cacheline. The struct is 128B on 64b and 64B on 32b.
> > On 64B, we will scale to around 16 million requests in flight and 4
> > million on 32b. Which should be enough.
> >
> > If we shrunk 64b to a 64B node, we would only scale to 256 requests
> > which limit we definitely will exceed.
>
> Ok thanks, pouring it into a comment is implied.
>
> >
> >>>struct i915_priolist {
> >>>struct list_head requests;
> >>
> >> What would be on this list? Request can only be on one at a time, so I
> >> was thinking these nodes would have pointers to list of that priority,
> >> rather than lists themselves. Assuming there can be multiple nodes of
> >> the same priority in the 2d hierarcy. Possibly I don't understand the
> >> layout.
> >
> > A request is only on one list (queue, active, hold). But we may still
> > have more than one request at the same deadline, though that will likely
> > be limited to priority-inheritance and timeslice deferrals.
> >
> > Since we would need pointer to the request, we could only reclaim a
> > single pointer here, which is not enough to warrant reducing the overall
> > node size. And while there is at least one user of request->sched.link,
> > the list maintenance will still be incurred. Using request->sched.link
> > remains a convenient interface.
>
> Lost you.
/*
* i915_priolist forms a skiplist. The skiplist is built in layers,
* starting at the base [0] is a singly linked list of all i915_priolist.
* Each higher layer contains a fraction of the i915_priolist from the
* previous layer:
*
* S[0] 0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF S
* E[1] >1>3>5>7>9>B>D>F>1>3>5>7>9>B>D>F>1>3>5>7>9>B>D>F>1>3>5>7>9>B>D>F E
* N[2] -->3-->7-->B-->F-->3-->7-->B-->F-->3-->7-->B-->F-->3-->7-->B-->F N
* T[3] --->7->F---7-->F-->7-->F-->7-->F T
* I[4] -->F-->F-->F-->F I
* N[5] -->F-->F N
* E[6] -->F---> E
* L[7] ---> L
*
* To iterate through all active i915_priolist, we only need to follow
* the chain in i915_priolist.next[0] (see for_each_priolist).
*
* To quickly find a specific key (or insert point), we can perform a binary
* search by starting at the highest level and following the linked list
* at that level until we either find the node, or have gone passed the key.
* Then we descend a level, and start walking the list again starting from
* the current position, until eventually we find our key, or we run out of
* levels.
*/
-Chris
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Re: [Intel-gfx] [PATCH 20/41] drm/i915: Replace priolist rbtree with a skiplist
Quoting Tvrtko Ursulin (2021-01-28 16:42:44)
>
> On 28/01/2021 16:26, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2021-01-28 15:56:19)
> >> On 25/01/2021 14:01, Chris Wilson wrote:
> >>>struct i915_priolist {
> >>>struct list_head requests;
> >>
> >> What would be on this list? Request can only be on one at a time, so I
> >> was thinking these nodes would have pointers to list of that priority,
> >> rather than lists themselves. Assuming there can be multiple nodes of
> >> the same priority in the 2d hierarcy. Possibly I don't understand the
> >> layout.
> >
> > A request is only on one list (queue, active, hold). But we may still
> > have more than one request at the same deadline, though that will likely
> > be limited to priority-inheritance and timeslice deferrals.
> >
> > Since we would need pointer to the request, we could only reclaim a
> > single pointer here, which is not enough to warrant reducing the overall
> > node size. And while there is at least one user of request->sched.link,
> > the list maintenance will still be incurred. Using request->sched.link
> > remains a convenient interface.
>
> Lost you.
>
> Is the data structure like this and I will limit to priorities for
> simplicity:
>
> Level1: [-1]->[1]
> Level0: [-1]>[0]->[1]
> [SENTINEL]
>
> Each of the boxes is struct i915_priolist?
Although each level is circular.
1: SENTINEL -> [-1] > [1] -> SENTINEL
0: SENTINEL -> [-1] -> [0] -> [1] -> SENTINEL
Ah. I think I see the cause of confusion here. Each column, not each
box, is a i915_priolist.
So the skiplist is really a set of [HEIGHT] singly linked lists, with
each list containing a sorted subset of the whole. And each descending
level includes every member from the level above, until we reach a
linked list of all i915_priolist in [0].
[skip, hopefully I caught the central point]
SENTINEL[2] is a list of all i915_priolist of level >= 2
SENTINEL[1] is a list of all i915_priolist of level >= 1
SENTINEL[0] is a list of all i915_priolist.
As we randomly assign i915_priolist.level, SENTINEL[1] should have half
the elements of SENTINEL[0], and SENTINEL[2] should have half again the
elements of SENTINEL[1] (hence its ability to do a binary/lgN search for
a key, each level is a bisection of the last).
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915/hdcp: update cp_irq_count_cached in intel_dp_hdcp2_read_msg()
== Series Details == Series: series starting with [v3,1/2] drm/i915/hdcp: update cp_irq_count_cached in intel_dp_hdcp2_read_msg() URL : https://patchwork.freedesktop.org/series/86424/ State : success == Summary == CI Bug Log - changes from CI_DRM_9696 -> Patchwork_19534 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/index.html Known issues Here are the changes found in Patchwork_19534 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@debugfs_test@read_all_entries: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/fi-tgl-y/igt@debugfs_test@read_all_entries.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@i915_selftest@live@gt_heartbeat: - fi-tgl-y: [PASS][4] -> [DMESG-FAIL][5] ([i915#2601]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html Possible fixes * igt@i915_selftest@live@execlists: - fi-bsw-nick:[INCOMPLETE][6] ([i915#2940]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling: - fi-tgl-y: [DMESG-WARN][8] ([i915#402]) -> [PASS][9] +2 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/fi-tgl-y/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/fi-tgl-y/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (44 -> 39) -- Missing(5): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9696 -> Patchwork_19534 CI-20190529: 20190529 CI_DRM_9696: 9fee71c4c03d8101401b895315a97f970036c6a0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5977: 0b6967520b15e73773eace7937ed8c17ba411bc0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19534: f7a01e50b5f5e0f475825d4cda20541d4db36e5c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f7a01e50b5f5 drm/i915/hdcp: read RxInfo once when reading Send_Pairing_Info 70e5f3b9f8ad drm/i915/hdcp: update cp_irq_count_cached in intel_dp_hdcp2_read_msg() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/2] drm/i915/hdcp: update cp_irq_count_cached in intel_dp_hdcp2_read_msg()
Update cp_irq_count_cached when we handle reading the messages rather
than writing a message to make sure the value is up to date and not
stale from a previously handled CP_IRQ. AKE flow doesn't always respond
to a read with a write msg.
E.g. currently AKE_Send_Pairing_Info will "timeout" because we received
a CP_IRQ for reading AKE_Send_H_Prime but no write occurred between that
and reading AKE_Send_Pairing_Info so cp_irq_count_cached is stale
causing the wait to return right away rather than waiting for a new
CP_IRQ.
Signed-off-by: Juston Li
Acked-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 4dba5bb15af5..d1397af97f69 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -442,8 +442,6 @@ static
int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port,
void *buf, size_t size)
{
- struct intel_dp *dp = _port->dp;
- struct intel_hdcp *hdcp = >attached_connector->hdcp;
unsigned int offset;
u8 *byte = buf;
ssize_t ret, bytes_to_write, len;
@@ -459,8 +457,6 @@ int intel_dp_hdcp2_write_msg(struct intel_digital_port
*dig_port,
bytes_to_write = size - 1;
byte++;
- hdcp->cp_irq_count_cached = atomic_read(>cp_irq_count);
-
while (bytes_to_write) {
len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
@@ -509,6 +505,8 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port
*dig_port,
u8 msg_id, void *buf, size_t size)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_dp *dp = _port->dp;
+ struct intel_hdcp *hdcp = >attached_connector->hdcp;
unsigned int offset;
u8 *byte = buf;
ssize_t ret, bytes_to_recv, len;
@@ -523,6 +521,8 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port
*dig_port,
if (ret < 0)
return ret;
+ hdcp->cp_irq_count_cached = atomic_read(>cp_irq_count);
+
if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
ret = get_receiver_id_list_size(dig_port);
if (ret < 0)
--
2.29.2
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[Intel-gfx] [PATCH v3 2/2] drm/i915/hdcp: read RxInfo once when reading Send_Pairing_Info
Previously when reading Send_Pairing_Info, RxInfo by itself was read
once to retrieve the DEVICE_COUNT and then a second time when reading
the RepeaterAuth_Send_ReceiverID_List which contains RxInfo.
On a couple HDCP 2.2 docks, this second read attempt on RxInfo fails
due to no Ack response. This behavior doesn't seem to be defined but
regardless we can fix it by reading RxInfo once and storing it before
reading the rest of RepeaterAuth_Send_ReceiverID_List once we know the
size.
Modify get_receiver_id_list_size() to read and store RxInfo in the
message buffer and also parse DEVICE_COUNT so we know the size of
RepeaterAuth_Send_ReceiverID_List.
Afterwards, retrieve the rest of the message at the offset for
seq_num_V.
Changes in v3:
- remove comment
Changes in v2:
- remove unnecessary moving of drm_i915_private from patch 1
Signed-off-by: Juston Li
Acked-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 30 ++--
include/drm/drm_dp_helper.h | 2 +-
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index d1397af97f69..3c04576681b9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -475,11 +475,10 @@ int intel_dp_hdcp2_write_msg(struct intel_digital_port
*dig_port,
}
static
-ssize_t get_receiver_id_list_size(struct intel_digital_port *dig_port)
+ssize_t get_receiver_id_list_rx_info(struct intel_digital_port *dig_port, u32
*dev_cnt, u8 *byte)
{
- u8 rx_info[HDCP_2_2_RXINFO_LEN];
- u32 dev_cnt;
ssize_t ret;
+ u8 *rx_info = byte;
ret = drm_dp_dpcd_read(_port->dp.aux,
DP_HDCP_2_2_REG_RXINFO_OFFSET,
@@ -487,15 +486,11 @@ ssize_t get_receiver_id_list_size(struct
intel_digital_port *dig_port)
if (ret != HDCP_2_2_RXINFO_LEN)
return ret >= 0 ? -EIO : ret;
- dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
+ *dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
- if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
- dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
-
- ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
- HDCP_2_2_RECEIVER_IDS_MAX_LEN +
- (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
+ if (*dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
+ *dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
return ret;
}
@@ -511,6 +506,7 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port
*dig_port,
u8 *byte = buf;
ssize_t ret, bytes_to_recv, len;
const struct hdcp2_dp_msg_data *hdcp2_msg_data;
+ u32 dev_cnt;
hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
if (!hdcp2_msg_data)
@@ -523,17 +519,21 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port
*dig_port,
hdcp->cp_irq_count_cached = atomic_read(>cp_irq_count);
+ /* DP adaptation msgs has no msg_id */
+ byte++;
+
if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
- ret = get_receiver_id_list_size(dig_port);
+ ret = get_receiver_id_list_rx_info(dig_port, _cnt, byte);
if (ret < 0)
return ret;
- size = ret;
+ byte += ret;
+ size = sizeof(struct hdcp2_rep_send_receiverid_list) -
+ HDCP_2_2_RXINFO_LEN - HDCP_2_2_RECEIVER_IDS_MAX_LEN +
+ (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
}
- bytes_to_recv = size - 1;
- /* DP adaptation msgs has no msg_id */
- byte++;
+ bytes_to_recv = size - 1;
while (bytes_to_recv) {
len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index edffd1dcca3e..3b42392394ba 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1388,7 +1388,7 @@ enum drm_dp_phy {
#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET
#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET
DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
-#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET
DP_HDCP_2_2_REG_RXINFO_OFFSET
+#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET
DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET
#define DP_HDCP_2_2_REP_SEND_ACK_OFFSETDP_HDCP_2_2_REG_V_OFFSET
#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
#define DP_HDCP_2_2_REP_STREAM_READY_OFFSETDP_HDCP_2_2_REG_MPRIME_OFFSET
--
2.29.2
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Re: [Intel-gfx] [PATCH] drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are detected
On Thu, 2021-01-21 at 15:15 +0200, Imre Deak wrote:
> On Tue, Jan 19, 2021 at 08:47:25AM +0200, Almahallawy, Khaled wrote:
> > On Mon, 2021-01-18 at 20:31 +0200, Imre Deak wrote:
> > > Atm, the driver programs explicitly the default transparent link
> > > training mode (0x55) to DP_PHY_REPEATER_MODE even if no LTTPRs
> > > are
> > > detected.
> > >
> > > This conforms to the spec (3.6.6.1):
> > > "DP upstream devices that do not enable the Non-transparent mode
> > > of
> > > LTTPRs shall program the PHY_REPEATER_MODE register (DPCD
> > > Address
> > > F0003h) to 55h (default) prior to link training"
> > >
> > > however writing the default value to this DPCD register seems to
> > > cause
> > > occasional link training errors at least for a DELL WD19TB TBT
> > > dock,
> > > when
> > > no LTTPRs are detected.
> >
> > I think this patch is more aligned with: DP v2.0 SCR on 8b/10b DPTX
> > and
> > LTTPR Requirements Update to Section 3.6
> >
> > The SCR made it clear that we only need to program
> > PHY_REPEATER_MODE to
> > transparent mode if we detect LTTPR.
>
> Yes, the updated version is clearer in this. In any case I don't see
> any
> reason now to set the default mode if there's no LTTPR on the link.
>
> > Quoting from SCR:
> > “A DPTX supporting 3.2-ms AUX Reply Timeout shall issue AUX read
> > transaction to LTTPR DPCD Capability and ID Field at DPCD Fh ~
> > F0007 (refer to Section 3.6.4.1) as the first AUX transaction upon
> > HPD
> > signal assertion detection (1) to determine whether LTTPR’s are
> > present
> > in the link between itself and the downstream DPRX and (2) to put
> > the
> > LTTPR’s, if present, in LTTPR Transparent Mode.”
> >
> > Also section 3.6.6 title is updated as the following “Section 3.6.6
> > Link Training in LTTPR Non-transparent Mode”. This reflects it only
> > relevant after we detect LTTPR.
> >
> > However it is still interesting that Dell Dock failed after setting
> > LTTPR to transparent mode.
>
> Yes, sinks should handle writing to this DPCD register regardless if
> there's any LTTPR on the link or not.
>
> > Thank You for your effort to enable LTTPR.
> > Khaled
> > > Writing to DP_PHY_REPEATER_MODE will also cause an unnecessary
> > > timeout
> > > on systems without any LTTPR.
> > >
> > > To fix the above two issues let's assume that setting the default
> > > mode
> > > is redundant when no LTTPRs are detected. Keep the existing
> > > behavior
> > > and
> > > program the default mode if more than 8 LTTPRs are detected or in
> > > case
> > > the read from DP_PHY_REPEATER_CNT returns an invalid value.
> > >
> > > References:
> > > https://gitlab.freedesktop.org/drm/intel/-/issues/2801
> > > Signed-off-by: Imre Deak
> > > ---
> > > .../drm/i915/display/intel_dp_link_training.c | 36 -
> > >
> > > --
> > > 1 file changed, 15 insertions(+), 21 deletions(-)
> > >
> > > diff --git
> > > a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > index d8c6d7054d11..fad9e9874c7b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > @@ -34,18 +34,6 @@ intel_dp_dump_link_status(const u8
> > > link_status[DP_LINK_STATUS_SIZE])
> > >link_status[3], link_status[4], link_status[5]);
> > > }
> > >
> > > -static int intel_dp_lttpr_count(struct intel_dp *intel_dp)
> > > -{
> > > -int count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
> > > -
> > > -/*
> > > - * Pretend no LTTPRs in case of LTTPR detection error, or
> > > - * if too many (>8) LTTPRs are detected. This translates to
> > > link
> > > - * training in transparent mode.
> > > - */
> > > -return count <= 0 ? 0 : count;
> > > -}
> > > -
> > > static void intel_dp_reset_lttpr_count(struct intel_dp
> > > *intel_dp)
> > > {
> > > intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -
> > > @@ -142,6 +130,17 @@ int intel_dp_lttpr_init(struct intel_dp
> > > *intel_dp)
> > > return 0;
> > >
> > > ret = intel_dp_read_lttpr_common_caps(intel_dp);
> > > +if (!ret)
> > > +return 0;
> > > +
> > > +lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
> > > +/*
> > > + * Prevent setting LTTPR transparent mode explicitly if no
> > > LTTPRs are
> > > + * detected as this breaks link training at least on the Dell
> > > WD19TB
> > > + * dock.
> > > + */
> > > +if (lttpr_count == 0)
> > > +return 0;
> > >
> > > /*
> > > * See DP Standard v2.0 3.6.6.1. about the explicit disabling
> > > of
> > > @@ -150,17 +149,12 @@ int intel_dp_lttpr_init(struct intel_dp
> > > *intel_dp)
> > > */
> > > intel_dp_set_lttpr_transparent_mode(intel_dp, true);
> > >
> > > -if (!ret)
> > > -return 0;
> > > -
> > > -lttpr_count = intel_dp_lttpr_count(intel_dp);
> > > -
> > > /*
> > > * In case of unsupported number of LTTPRs or failing to switch
> > > to
> > > * non-transparent mode fall-back to transparent link training
> > > mode,
> >
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/dp/mst: Export drm_dp_get_vc_payload_bw()
On Tue, Jan 26, 2021 at 01:28:09AM +, Patchwork wrote: > == Series Details == > > Series: series starting with [1/2] drm/dp/mst: Export > drm_dp_get_vc_payload_bw() > URL : https://patchwork.freedesktop.org/series/86267/ > State : success Patchset pushed to -din with the docbook fix, thanks for the review. > > == Summary == > > CI Bug Log - changes from CI_DRM_9680_full -> Patchwork_19491_full > > > Summary > --- > > **SUCCESS** > > No regressions found. > > > > New tests > - > > New tests have been introduced between CI_DRM_9680_full and > Patchwork_19491_full: > > ### New IGT tests (1749) ### > > * igt@core_auth@many-magics: > - Statuses : 6 pass(s) > - Exec time: [0.15, 0.85] s > > * igt@core_getclient: > - Statuses : 7 pass(s) > - Exec time: [0.07, 0.18] s > > * igt@core_getstats: > - Statuses : 6 pass(s) > - Exec time: [0.07, 0.19] s > > * igt@core_getversion: > - Statuses : 7 pass(s) > - Exec time: [0.07, 0.18] s > > * igt@core_setmaster_vs_auth: > - Statuses : 7 pass(s) > - Exec time: [0.06, 0.18] s > > * igt@debugfs_test@read_all_entries_display_off: > - Statuses : 7 pass(s) > - Exec time: [0.07, 1.13] s > > * igt@debugfs_test@read_all_entries_display_on: > - Statuses : > - Exec time: [None] s > > * igt@drm_import_export@flink: > - Statuses : 7 pass(s) > - Exec time: [10.74, 10.75] s > > * igt@drm_import_export@import-close-race-flink: > - Statuses : 7 pass(s) > - Exec time: [10.74, 10.75] s > > * igt@drm_import_export@import-close-race-prime: > - Statuses : 7 pass(s) > - Exec time: [10.74] s > > * igt@drm_import_export@prime: > - Statuses : 7 pass(s) > - Exec time: [10.74] s > > * igt@drm_read@empty-block: > - Statuses : 2 pass(s) > - Exec time: [1.0] s > > * igt@drm_read@empty-nonblock: > - Statuses : 7 pass(s) > - Exec time: [0.0] s > > * igt@drm_read@fault-buffer: > - Statuses : 7 pass(s) > - Exec time: [0.0, 0.00] s > > * igt@drm_read@invalid-buffer: > - Statuses : 7 pass(s) > - Exec time: [0.0] s > > * igt@drm_read@short-buffer-block: > - Statuses : 7 pass(s) > - Exec time: [0.0] s > > * igt@drm_read@short-buffer-nonblock: > - Statuses : 7 pass(s) > - Exec time: [0.0] s > > * igt@dumb_buffer@create-clear: > - Statuses : 7 pass(s) > - Exec time: [37.43, 47.67] s > > * igt@dumb_buffer@create-valid-dumb: > - Statuses : 7 pass(s) > - Exec time: [0.0] s > > * igt@dumb_buffer@invalid-bpp: > - Statuses : 7 pass(s) > - Exec time: [0.0] s > > * igt@dumb_buffer@map-invalid-size: > - Statuses : 7 pass(s) > - Exec time: [0.0, 0.00] s > > * igt@dumb_buffer@map-uaf: > - Statuses : 7 pass(s) > - Exec time: [0.02, 0.10] s > > * igt@dumb_buffer@map-valid: > - Statuses : 7 pass(s) > - Exec time: [0.0] s > > * igt@gem_bad_reloc@negative-reloc-bltcopy: > - Statuses : 7 pass(s) > - Exec time: [0.36, 4.37] s > > * igt@gem_blits@basic: > - Statuses : 7 pass(s) > - Exec time: [1.44, 14.28] s > > * igt@gem_busy@close-race: > - Statuses : 7 pass(s) > - Exec time: [21.71, 22.45] s > > * igt@gem_caching@read-writes: > - Statuses : 7 pass(s) > - Exec time: [4.43, 22.74] s > > * igt@gem_caching@reads: > - Statuses : 7 pass(s) > - Exec time: [0.66, 5.61] s > > * igt@gem_caching@writes: > - Statuses : 7 pass(s) > - Exec time: [2.31, 13.42] s > > * igt@gem_close@basic: > - Statuses : 7 pass(s) > - Exec time: [0.0] s > > * igt@gem_close@many-handles-one-vma: > - Statuses : 7 pass(s) > - Exec time: [0.02, 0.10] s > > * igt@gem_create@create-invalid-size: > - Statuses : 7 pass(s) > - Exec time: [0.0] s > > * igt@gem_create@create-valid-nonaligned: > - Statuses : 7 pass(s) > - Exec time: [0.0, 0.00] s > > * igt@gem_ctx_bad_destroy@double-destroy: > - Statuses : 7 pass(s) > - Exec time: [0.0, 0.00] s > > * igt@gem_ctx_bad_destroy@invalid-ctx: > - Statuses : 7 pass(s) > - Exec time: [0.0] s > > * igt@gem_ctx_bad_destroy@invalid-default-ctx: > - Statuses : 7 pass(s) > - Exec time: [0.0] s > > * igt@gem_ctx_bad_destroy@invalid-pad: > - Statuses : 7 pass(s) > - Exec time: [0.0, 0.00] s > > * igt@gem_ctx_exec@basic-invalid-context: > - Statuses : 7 pass(s) > - Exec time: [0.00, 0.01] s > > * igt@gem_ctx_freq@sysfs: > - Statuses : 7 pass(s) > - Exec time: [4.80, 4.99] s > > * igt@gem_ctx_param@basic: > - Statuses : 7 pass(s) > - Exec time: [0.0] s > > * igt@gem_ctx_param@basic-default: > - Statuses : 7 pass(s) > - Exec time: [0.0] s > > * igt@gem_ctx_param@get-priority-new-ctx: > - Statuses : 5 pass(s) 2 skip(s) > - Exec time: [0.0, 0.00] s > > * igt@gem_ctx_param@invalid-ctx-get: >
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Skip vswing programming for TBT (rev2)
== Series Details == Series: series starting with [1/5] drm/i915: Skip vswing programming for TBT (rev2) URL : https://patchwork.freedesktop.org/series/86402/ State : success == Summary == CI Bug Log - changes from CI_DRM_9695 -> Patchwork_19532 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/index.html Known issues Here are the changes found in Patchwork_19532 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ringfill@basic-all: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-tgl-y/igt@gem_ringf...@basic-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/fi-tgl-y/igt@gem_ringf...@basic-all.html * igt@i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][3] -> [INCOMPLETE][4] ([i915#142] / [i915#2405]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-byt-j1900/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/fi-byt-j1900/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [PASS][5] -> [DMESG-FAIL][6] ([i915#2291] / [i915#541]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@runner@aborted: - fi-byt-j1900: NOTRUN -> [FAIL][7] ([i915#1814] / [i915#2505]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/fi-byt-j1900/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [DMESG-WARN][8] ([i915#2411] / [i915#402]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@gem_render_tiled_blits@basic: - fi-tgl-y: [DMESG-WARN][10] ([i915#402]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-tgl-y/igt@gem_render_tiled_bl...@basic.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/fi-tgl-y/igt@gem_render_tiled_bl...@basic.html [i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 Participating hosts (44 -> 39) -- Missing(5): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9695 -> Patchwork_19532 CI-20190529: 20190529 CI_DRM_9695: 67e514b158700703fcaaed71c3fb1eea8b2e645c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5977: 0b6967520b15e73773eace7937ed8c17ba411bc0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19532: 18f6d51d713ef8dde42136c1543072ced16a9f00 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 18f6d51d713e drm/i915: Don't check tc_mode unless dealing with a TC PHY c3e4b48fa88a drm/i915: Move HDMI vswing programming to the right place 1051a47e74bb drm/i915: Power up combo PHY lanes for for HDMI as well b6261fb8ce40 drm/i915: Extract intel_ddi_power_up_lanes() 86b6011d3fe6 drm/i915: Skip vswing programming for TBT == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Preliminary Display13 support
== Series Details == Series: Preliminary Display13 support URL : https://patchwork.freedesktop.org/series/86409/ State : failure == Summary == Applying: drm/i915/display13: add Display13 characteristics Applying: drm/i915/display13: Handle proper AUX interrupt bits Applying: drm/i915/display13: Enhanced pipe underrun reporting Applying: drm/i915/display13: Define plane capabilities error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_irq.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0004 drm/i915/display13: Define plane capabilities When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/18] drm/i915/display13: Increase maximum watermark lines to 255
Display13 continues to use the same "skylake-style" watermark
programming as other recent platforms. The only change to the watermark
calculations compared to Display12 is that Display13 now allows a
maximum of 255 lines vs the old limit of 31.
Due to the larger possible lines value, the corresponding bits
representing the value in PLANE_WM are also extended, so make sure we
read/write enough bits. Let's also take this opportunity to switch over
to the REG_FIELD notation.
Bspec: 49325
Bspec: 50419
Cc: Ville Syrjälä
Cc: Anshuman Gupta
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_reg.h | 3 +--
drivers/gpu/drm/i915/intel_pm.c | 15 +++
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ec7bda22f4f3..03711ba05bf5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6424,8 +6424,7 @@ enum {
#define _CUR_WM_TRANS_B_0 0x71168
#define PLANE_WM_EN (1 << 31)
#define PLANE_WM_IGNORE_LINES(1 << 30)
-#define PLANE_WM_LINES_SHIFT 14
-#define PLANE_WM_LINES_MASK 0x1f
+#define PLANE_WM_LINES_MASK REG_GENMASK(21, 14)
#define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */
#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6e9678bd0597..696ee3a1c28c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5160,6 +5160,14 @@ static bool skl_wm_has_lines(struct drm_i915_private
*dev_priv, int level)
return level > 0;
}
+static int skl_wm_max_lines(struct drm_i915_private *dev_priv)
+{
+ if (HAS_DISPLAY13(dev_priv))
+ return 255;
+ else
+ return 31;
+}
+
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
int level,
unsigned int latency,
@@ -5268,7 +5276,7 @@ static void skl_compute_plane_wm(const struct
intel_crtc_state *crtc_state,
if (!skl_wm_has_lines(dev_priv, level))
res_lines = 0;
- if (res_lines > 31) {
+ if (res_lines > skl_wm_max_lines(dev_priv)) {
/* reject it */
result->min_ddb_alloc = U16_MAX;
return;
@@ -5559,7 +5567,7 @@ static void skl_write_wm_level(struct drm_i915_private
*dev_priv,
if (level->ignore_lines)
val |= PLANE_WM_IGNORE_LINES;
val |= level->plane_res_b;
- val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
+ val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->plane_res_l);
intel_de_write_fw(dev_priv, reg, val);
}
@@ -6144,8 +6152,7 @@ static void skl_wm_level_from_reg_val(u32 val, struct
skl_wm_level *level)
level->plane_en = val & PLANE_WM_EN;
level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
- level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
- PLANE_WM_LINES_MASK;
+ level->plane_res_l = REG_FIELD_GET(PLANE_WM_LINES_MASK, val);
}
void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
--
2.25.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/18] drm/i915/display13: Add Wa_14011503030:d13
Cc: Aditya Swarup
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4
drivers/gpu/drm/i915/i915_reg.h| 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7dd12fe9137e..f5a268e81024 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5844,6 +5844,10 @@ static void icl_display_core_init(struct
drm_i915_private *dev_priv,
DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR;
intel_uncore_rmw(_priv->uncore, GEN11_CHICKEN_DCPR_2, 0,
val);
}
+
+ /* Wa_14011503030:d13 */
+ if (HAS_DISPLAY13(dev_priv))
+ intel_de_write(dev_priv, D13_DISPLAY_ERR_FATAL_MASK, ~0);
}
static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 03711ba05bf5..128b835c0adb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7776,6 +7776,8 @@ enum {
#define GEN8_GT_BCS_IRQ (1 << 1)
#define GEN8_GT_RCS_IRQ (1 << 0)
+#define D13_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
+
#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
--
2.25.4
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/18] drm/i915/display13: Handle new location of outputs D and E
The DDI naming template for Display12 went A-C, TC1-TC6. With
Display13, that naming scheme for DDI's has now changed to A-E, TC1-TC4.
The Display13 design keeps the register offsets and bitfields relating
to the TC outputs in the same location they were on Display12. The new
"D" and "E" outputs now take the locations that were previously used by
Display12's TC5 and TC6 outputs, or what we would have considered to be
outputs "H" and "I" under the legacy lettering scheme.
For the most part everything will just work as long as we initialize the
output with the proper 'enum port' value. However we do need to take
care to pick the correct AUX channel when parsing the VBT (e.g., a
reference to 'AUX D' is actually asking us to use the 8th aux channel,
not the fourth). We should also make sure that our encoders and aux
channels are named appropriately so that it's easier to correlate driver
debug messages with the bspec instructions.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bios.c| 8 ++--
drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++-
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
drivers/gpu/drm/i915/display/intel_display.h | 8
drivers/gpu/drm/i915/display/intel_dp_aux.c | 14 +-
5 files changed, 35 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 04337ac6f8c4..b9e00fc3715d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2716,7 +2716,9 @@ enum aux_ch intel_bios_port_aux_ch(struct
drm_i915_private *dev_priv,
aux_ch = AUX_CH_C;
break;
case DP_AUX_D:
- if (IS_ALDERLAKE_S(dev_priv))
+ if (HAS_DISPLAY13(dev_priv))
+ aux_ch = AUX_CH_D_D13;
+ else if (IS_ALDERLAKE_S(dev_priv))
aux_ch = AUX_CH_USBC3;
else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
aux_ch = AUX_CH_USBC2;
@@ -2724,7 +2726,9 @@ enum aux_ch intel_bios_port_aux_ch(struct
drm_i915_private *dev_priv,
aux_ch = AUX_CH_D;
break;
case DP_AUX_E:
- if (IS_ALDERLAKE_S(dev_priv))
+ if (HAS_DISPLAY13(dev_priv))
+ aux_ch = AUX_CH_E_D13;
+ else if (IS_ALDERLAKE_S(dev_priv))
aux_ch = AUX_CH_USBC4;
else
aux_ch = AUX_CH_E;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9506b8048530..68e58e94f2a5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5520,7 +5520,13 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
encoder = _port->base;
- if (INTEL_GEN(dev_priv) >= 12) {
+ if (HAS_DISPLAY13(dev_priv) && port >= PORT_D_D13) {
+ drm_encoder_init(_priv->drm, >base,
_ddi_funcs,
+DRM_MODE_ENCODER_TMDS,
+"DDI %c/PHY %c",
+port_name(port - PORT_D_D13 + PORT_D),
+phy_name(phy));
+ } else if (INTEL_GEN(dev_priv) >= 12) {
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
drm_encoder_init(_priv->drm, >base,
_ddi_funcs,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f56237aaa7b5..4dc4b1be0809 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5699,7 +5699,11 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv,
enum phy phy)
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
- if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
+ if (HAS_DISPLAY13(i915) && port >= PORT_D_D13)
+ return PHY_D + port - PORT_D_D13;
+ else if (HAS_DISPLAY13(i915) && port >= PORT_TC1)
+ return PHY_F + port - PORT_TC1;
+ else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
return PHY_B + port - PORT_TC1;
else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
return PHY_C + port - PORT_TC1;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 64ffa34544a7..b102ec0d5390 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -216,6 +216,10 @@ enum port {
PORT_TC5,
PORT_TC6,
+ /* Display13 repositions D/E offsets and bitfields */
+ PORT_D_D13 = PORT_TC5,
+ PORT_E_D13,
+
I915_MAX_PORTS
};
@@ -299,6 +303,10 @@ enum aux_ch {
AUX_CH_USBC4,
[Intel-gfx] [PATCH 14/18] drm/i915/display13: Support DP1.4 compression BPPs
From: Vandita Kulkarni
Support compression BPPs from bpc to uncompressed BPP -1.
So far we have 8,10,12 as valid compressed BPPS now the
support is extended.
Cc: Manasi Navare
Signed-off-by: Vandita Kulkarni
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 32 ++---
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a531103fb0b5..1feafd038db1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -153,6 +153,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
static void intel_dp_link_down(struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state);
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
/* update sink rates from dpcd */
static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
@@ -538,7 +539,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner)
+ bool bigjoiner,
+ u32 pipe_bpp)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -563,6 +565,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
drm_dbg_kms(>drm, "Max small joiner bpp: %u\n",
max_bpp_small_joiner_ram);
+
/*
* Greatest allowed DSC BPP = MIN (output BPP from available Link BW
* check, output bpp from small joiner RAM check)
@@ -585,12 +588,17 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
return 0;
}
- /* Find the nearest match in the array of known BPPs from VESA */
- for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
- if (bits_per_pixel < valid_dsc_bpp[i + 1])
- break;
+ /* From Display13 onwards we support from bpc upto uncompressed bpp-1
BPPs */
+ if (HAS_DISPLAY13(i915)) {
+ bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
+ } else {
+ /* Find the nearest match in the array of known BPPs from VESA
*/
+ for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
+ if (bits_per_pixel < valid_dsc_bpp[i + 1])
+ break;
+ }
+ bits_per_pixel = valid_dsc_bpp[i];
}
- bits_per_pixel = valid_dsc_bpp[i];
/*
* Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
@@ -824,6 +832,12 @@ intel_dp_mode_valid(struct drm_connector *connector,
*/
if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ /*
+* TBD pass the connector BPC,
+* for now U8_MAX so that max BPC on that platform would be
picked
+*/
+ int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+
if (intel_dp_is_edp(intel_dp)) {
dsc_max_output_bpp =
drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd)
>> 4;
@@ -837,7 +851,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
max_lanes,
target_clock,
mode->hdisplay,
- bigjoiner) >> 4;
+ bigjoiner,
+ pipe_bpp) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1355,7 +1370,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner);
+ pipe_config->bigjoiner,
+ pipe_bpp);
dsc_dp_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
[Intel-gfx] [PATCH 11/18] drm/i915/display13: Required bandwidth increases when VT-d is active
If VT-d is active, the memory bandwidth usage of the display is 5% higher. Take this into account when determining whether we can support a display configuration. Bspec: 64631 Cc: Matt Atwood Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_bw.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 32522ec1ffb9..14cb3fbf0039 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -398,6 +398,9 @@ static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv, for_each_pipe(dev_priv, pipe) data_rate += bw_state->data_rate[pipe]; + if (HAS_DISPLAY13(dev_priv) && intel_vtd_active()) + data_rate = data_rate * 105 / 100; + return data_rate; } -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/18] drm/i915/display13: Add Display13 power wells
Aside from the hardware-managed PG0, Display13 has power wells 1-2 and
A-D. These power wells should be enabled/disabled according to the
following dependency tree (enable top to bottom, disable bottom to top):
PG0
|
--PG1--
/ \
PGA --PG2--
/ | \
PGB PGC PGD
PWR_WELL_CTL follows the general ICL/TGL design and places PG A-D in the
bits that would have been PG 6-9 under the old scheme.
PWR_WELL_CTL_{DDI,AUX}'s bit indexing for DDI's A-C and TC1 is the same
as TGL, but DDI-D is placed at index 7 (bits 14 & 15).
Bspec: 49233
Bspec: 49503
Bspec: 49504
Bspec: 49505
Bspec: 49296
Bspec: 50090
Bspec: 53920
Cc: Anshuman Gupta
Cc: Imre Deak
Cc: Anshuman Gupta
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_power.c| 422 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 5 +-
drivers/gpu/drm/i915/i915_reg.h | 10 +
3 files changed, 433 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index e17b1ca356c3..7dd12fe9137e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1035,7 +1035,7 @@ static void assert_can_enable_dc5(struct drm_i915_private
*dev_priv)
enum i915_power_well_id high_pg;
/* Power wells at this level and above must be disabled for DC5 entry */
- if (INTEL_GEN(dev_priv) >= 12)
+ if (INTEL_GEN(dev_priv) >= 12 && !HAS_DISPLAY13(dev_priv))
high_pg = ICL_DISP_PW_3;
else
high_pg = SKL_DISP_PW_2;
@@ -3028,6 +3028,109 @@ intel_display_power_put_mask_in_set(struct
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
+/*
+ * Display13 Power Domains
+ *
+ * Previous platforms required that PG(n-1) be enabled before PG(n). That
+ * dependency chain turns into a dependency tree on Display13:
+ *
+ * PG0
+ *|
+ * --PG1--
+ */ \
+ * PGA --PG2--
+ * / | \
+ * PGB PGC PGD
+ *
+ * Power wells must be enabled from top to bottom and disabled from bottom
+ * to top. This allows pipes to be power gated independently.
+ */
+
+#define D13_PW_D_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |\
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define D13_PW_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define D13_PW_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define D13_PW_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define D13_PW_2_POWER_DOMAINS ( \
+ D13_PW_B_POWER_DOMAINS |\
+ D13_PW_C_POWER_DOMAINS |\
+ D13_PW_D_POWER_DOMAINS |\
+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_G_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_H_LANES) |\
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_I_LANES) |\
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E) | \
+ BIT_ULL(POWER_DOMAIN_AUX_F) | \
+ BIT_ULL(POWER_DOMAIN_AUX_G) | \
+ BIT_ULL(POWER_DOMAIN_AUX_H) | \
+ BIT_ULL(POWER_DOMAIN_AUX_I) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+/*
+ * D13 PW_1/PG_1 domains (under HW/DMC control):
+ * - DBUF function (registers are in PW0)
+ * - Transcoder A
+ * - DDI_A and DDI_B
+ *
+ * D13 PW_0/PW_1 domains (under HW/DMC control):
+ * - PCI
+ * - Clocks except port PLL
+ * - Shared functions:
+ * * interrupts except pipe interrupts
+ * * MBus except PIPE_MBUS_DBOX_CTL
+ * * DBUF registers
[Intel-gfx] [PATCH 13/18] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp
From: Vandita Kulkarni
Move the platform specific max bpc calculation into
intel_dp_dsc_compute_bpp function
Cc: Manasi Navare
Signed-off-by: Vandita Kulkarni
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 8c12d5375607..a531103fb0b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1212,10 +1212,18 @@ intel_dp_compute_link_config_fast(struct intel_dp
*intel_dp,
return -EINVAL;
}
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
u8 dsc_bpc[3] = {0};
+ u8 dsc_max_bpc;
+
+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+ if (INTEL_GEN(i915) >= 12)
+ dsc_max_bpc = min_t(u8, 12, max_req_bpc);
+ else
+ dsc_max_bpc = min_t(u8, 10, max_req_bpc);
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
dsc_bpc);
@@ -1303,7 +1311,6 @@ static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
_config->hw.adjusted_mode;
- u8 dsc_max_bpc;
int pipe_bpp;
int ret;
@@ -1313,14 +1320,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
- if (INTEL_GEN(dev_priv) >= 12)
- dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
- else
- dsc_max_bpc = min_t(u8, 10,
- conn_state->max_requested_bpc);
-
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
conn_state->max_requested_bpc);
/* Min Input BPC for ICL+ is 8 */
if (pipe_bpp < 8 * 3) {
--
2.25.4
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[Intel-gfx] [PATCH 18/18] drm/i915/display13: Enabling dithering after the CC1 pipe
From: Nischal Varide
If the panel is 12bpc then Dithering is not enabled in the Legacy
dithering block , instead its Enabled after the C1 CC1 pipe post
color space conversion.For a 6bpc pannel Dithering is enabled in
Legacy block.
Cc: Uma Shankar
Signed-off-by: Nischal Varide
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_color.c | 16
drivers/gpu/drm/i915/display/intel_display.c | 9 -
drivers/gpu/drm/i915/i915_reg.h | 3 ++-
3 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index ff7dcb7088bf..9a0572bbc5db 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1604,6 +1604,20 @@ static u32 icl_csc_mode(const struct intel_crtc_state
*crtc_state)
return csc_mode;
}
+static u32 dither_after_cc1_12bpc(const struct intel_crtc_state *crtc_state)
+{
+ u32 gamma_mode = crtc_state->gamma_mode;
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+
+ if (HAS_DISPLAY13(i915)) {
+ if (!crtc_state->dither_force_disable &&
+ (crtc_state->pipe_bpp == 36))
+ gamma_mode |= GAMMA_MODE_DITHER_AFTER_CC1;
+ }
+
+ return gamma_mode;
+}
+
static int icl_color_check(struct intel_crtc_state *crtc_state)
{
int ret;
@@ -1614,6 +1628,8 @@ static int icl_color_check(struct intel_crtc_state
*crtc_state)
crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
+ crtc_state->gamma_mode = dither_after_cc1_12bpc(crtc_state);
+
crtc_state->csc_mode = icl_csc_mode(crtc_state);
crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 4dc4b1be0809..e3dbcd956fc6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8098,9 +8098,15 @@ static void bdw_set_pipemisc(const struct
intel_crtc_state *crtc_state)
break;
}
- if (crtc_state->dither)
+ /*
+* If 12bpc panel then, Enables dithering after the CC1 pipe
+* post color space conversion and not here
+*/
+
+ if (crtc_state->dither && (crtc_state->pipe_bpp != 36))
val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
+
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
@@ -10760,6 +10766,7 @@ intel_modeset_pipe_config(struct intel_atomic_state
*state,
*/
pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
!pipe_config->dither_force_disable;
+
drm_dbg_kms(>drm,
"hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 128b835c0adb..27f25214a839 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6132,7 +6132,7 @@ enum {
#define PIPEMISC_DITHER_8_BPC(0 << 5)
#define PIPEMISC_DITHER_10_BPC (1 << 5)
#define PIPEMISC_DITHER_6_BPC(2 << 5)
-#define PIPEMISC_DITHER_12_BPC (3 << 5)
+#define PIPEMISC_DITHER_12_BPC (4 << 5)
#define PIPEMISC_DITHER_ENABLE (1 << 4)
#define PIPEMISC_DITHER_TYPE_MASK(3 << 2)
#define PIPEMISC_DITHER_TYPE_SP (0 << 2)
@@ -7668,6 +7668,7 @@ enum {
#define GAMMA_MODE_MODE_12BIT (2 << 0)
#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
+#define GAMMA_MODE_DITHER_AFTER_CC1 (1 << 26)
/* DMC/CSR */
#define CSR_PROGRAM(i) _MMIO(0x8 + (i) * 4)
--
2.25.4
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[Intel-gfx] [PATCH 08/18] drm/i915/display13: Handle LPSP for Display 13
From: Uma Shankar
Enable LPSP for Display13 and get the proper power well
enable check in place. For Display13 it is PW2 which
need to check for LPSP.
Cc: Anshuman Gupta
Cc: Animesh Manna
Cc: Matt Roper
Suggested-by: Matt Roper
Signed-off-by: Uma Shankar
Signed-off-by: Anshuman Gupta
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index d62b18d5ecd8..2af7d74d5960 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1316,6 +1316,13 @@ static int i915_lpsp_status(struct seq_file *m, void
*unused)
switch (INTEL_GEN(i915)) {
case 12:
+ if (HAS_DISPLAY13(i915)) {
+ LPSP_STATUS(!intel_lpsp_power_well_enabled(i915,
+
SKL_DISP_PW_2));
+ break;
+ }
+
+ fallthrough;
case 11:
LPSP_STATUS(!intel_lpsp_power_well_enabled(i915,
ICL_DISP_PW_3));
break;
--
2.25.4
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[Intel-gfx] [PATCH 05/18] drm/i915/display13: Support 128k plane stride
From: Juha-Pekka Heikkilä
Display13 supports plane strides up to 128KB.
Cc: Vandita Kulkarni
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 6 -
drivers/gpu/drm/i915/display/intel_sprite.c | 24 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 ++
3 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d013b0fab128..f56237aaa7b5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8396,7 +8396,11 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
- fb->pitches[0] = (val & 0x3ff) * stride_mult;
+
+ if (HAS_DISPLAY13(dev_priv))
+ fb->pitches[0] = (val & PLANE_STRIDE_MASK_D13) * stride_mult;
+ else
+ fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
aligned_height = intel_fb_align_height(fb, 0, fb->height);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 81bb5eb1cd15..c858ba6dc026 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -572,17 +572,37 @@ skl_plane_max_stride(struct intel_plane *plane,
u32 pixel_format, u64 modifier,
unsigned int rotation)
{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
const struct drm_format_info *info = drm_format_info(pixel_format);
int cpp = info->cpp[0];
+ int max_horizontal_pixels = 8192;
+ int max_stride_bytes;
+
+ if (HAS_DISPLAY13(i915)) {
+ /*
+* The stride in bytes must not exceed of the size
+* of 128K bytes. For pixel formats of 64bpp will allow
+* for a 16K pixel surface.
+*/
+ max_stride_bytes = 131072;
+ if (cpp == 8)
+ max_horizontal_pixels = 16384;
+ } else {
+ /*
+* "The stride in bytes must not exceed the
+* of the size of 8K pixels and 32K bytes."
+*/
+ max_stride_bytes = 32768;
+ }
/*
* "The stride in bytes must not exceed the
* of the size of 8K pixels and 32K bytes."
*/
if (drm_rotation_90_or_270(rotation))
- return min(8192, 32768 / cpp);
+ return min(max_horizontal_pixels, max_stride_bytes / cpp);
else
- return min(8192 * cpp, 32768);
+ return min(max_horizontal_pixels * cpp, max_stride_bytes);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a57593f7d7b1..9dfa4d711d6f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7198,6 +7198,8 @@ enum {
_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
#define PLANE_STRIDE(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
+#define PLANE_STRIDE_MASK REG_GENMASK(10, 0)
+#define PLANE_STRIDE_MASK_D13 REG_GENMASK(11, 0)
#define _PLANE_POS_1_B 0x7118c
#define _PLANE_POS_2_B 0x7128c
--
2.25.4
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[Intel-gfx] [PATCH 15/18] drm/i915/display13: Get slice height before computing rc params
From: Vandita Kulkarni We need slice height to calculate few RC parameters hence assign slice height first. Cc: Manasi Navare Signed-off-by: Vandita Kulkarni Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_dp.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1feafd038db1..d8ae4bbf0c15 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1269,10 +1269,6 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, */ vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; - ret = intel_dsc_compute_params(encoder, crtc_state); - if (ret) - return ret; - /* * Slice Height of 8 works for all currently available panels. So start * with that if pic_height is an integral multiple of 8. Eventually add @@ -1285,6 +1281,10 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, else vdsc_cfg->slice_height = 2; + ret = intel_dsc_compute_params(encoder, crtc_state); + if (ret) + return ret; + vdsc_cfg->dsc_version_major = (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/18] drm/i915/display13: add Display13 characteristics
Let's start preparing for upcoming platforms that will use a Display13
design.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 11 +++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
3 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9713ab963122..1c0fdbf800ac 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1778,6 +1778,7 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
+#define HAS_DISPLAY13(dev_priv) (INTEL_INFO(dev_priv)->has_display13)
#define HAS_VRR(i915) (INTEL_GEN(i915) >= 12)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 6cff7cf0f17b..e5e10484bf8d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -936,6 +936,17 @@ static const struct intel_device_info adl_s_info = {
.dma_mask_size = 46,
};
+#define DISPLAY13_FEATURES \
+ .has_display13 = 1, \
+ .display.has_psr_hw_tracking = 0, \
+ .abox_mask = GENMASK(1, 0), \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
+ .ddb_size = 4096, \
+ .mbus_size = 2048, \
+ .num_supported_dbuf_slices = 4,
+
#undef GEN
#undef PLATFORM
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index e6ca1023ffcf..ba44c2c10ad8 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -116,6 +116,7 @@ enum intel_ppgtt_type {
func(is_dgfx); \
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
+ func(has_display13); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_fpga_dbg); \
@@ -193,6 +194,7 @@ struct intel_device_info {
} display;
u16 ddb_size; /* in blocks */
+ u16 mbus_size; /* total ddb size on one mbus */
u8 num_supported_dbuf_slices; /* number of DBuf slices */
/* Register offsets for the various display pipes and transcoders */
--
2.25.4
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[Intel-gfx] [PATCH 03/18] drm/i915/display13: Enhanced pipe underrun reporting
Display13 brings enhanced underrun recovery: the hardware can somewhat
mitigate underruns by using an interpolated replacement pixel (soft
underrun) or the previous pixel (hard underrun). Furthermore, underruns
can now be caused downstream by the port, even if the pipe itself is
operating properly. The interrupt register gives us extra bits to
determine hard/soft underruns and whether the underrun was caused by the
port, so let's pass the iir down to the underrun handler and print some
more descriptive errors on Display13 platforms.
The context of the underrun is also available via PIPE_STATUS, but since
we have the same information in the IIR we don't have a need to read
from there. PIPE_STATUS might be useful in debugfs in the future
though.
Bspec: 50335
Bspec: 50366
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_fifo_underrun.c| 55 ++-
drivers/gpu/drm/i915/i915_irq.c | 14 -
drivers/gpu/drm/i915/i915_reg.h | 7 +++
3 files changed, 73 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index 813a4f7033e1..6c377f0fc1b3 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -359,6 +359,39 @@ bool intel_set_pch_fifo_underrun_reporting(struct
drm_i915_private *dev_priv,
return old;
}
+static u32
+underrun_pipestat_mask(struct drm_i915_private *dev_priv)
+{
+ u32 mask = PIPE_FIFO_UNDERRUN_STATUS;
+
+ if (HAS_DISPLAY13(dev_priv))
+ mask |= PIPE_STAT_SOFT_UNDERRUN_D13 |
+ PIPE_STAT_HARD_UNDERRUN_D13 |
+ PIPE_STAT_PORT_UNDERRUN_D13;
+
+ return mask;
+}
+
+static const char *
+pipe_underrun_reason(u32 pipestat_underruns)
+{
+ if (pipestat_underruns & PIPE_STAT_SOFT_UNDERRUN_D13)
+ /*
+* Hardware used replacement/interpolated pixels at
+* underrun locations.
+*/
+ return "soft";
+ else if (pipestat_underruns & PIPE_STAT_HARD_UNDERRUN_D13)
+ /*
+* Hardware used previous pixel value at underrun
+* locations.
+*/
+ return "hard";
+ else
+ /* Old platform or no extra soft/hard bit set */
+ return "FIFO";
+}
+
/**
* intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
* @dev_priv: i915 device instance
@@ -372,6 +405,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct
drm_i915_private *dev_priv,
enum pipe pipe)
{
struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+ u32 underruns = 0;
/* We may be called too early in init, thanks BIOS! */
if (crtc == NULL)
@@ -382,10 +416,27 @@ void intel_cpu_fifo_underrun_irq_handler(struct
drm_i915_private *dev_priv,
crtc->cpu_fifo_underrun_disabled)
return;
+ /*
+* On Display13, we can find out whether an underrun is soft/hard from
+* either the iir or PIPE_STAT, but we can only determine if underruns
+* were due to downstream port logic from PIPE_STAT.
+*/
+ underruns = intel_uncore_read(_priv->uncore, ICL_PIPESTAT(pipe)) &
+ underrun_pipestat_mask(dev_priv);
+ intel_uncore_write(_priv->uncore, ICL_PIPESTAT(pipe), underruns);
+
if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
trace_intel_cpu_fifo_underrun(dev_priv, pipe);
- drm_err(_priv->drm, "CPU pipe %c FIFO underrun\n",
- pipe_name(pipe));
+
+ if (underruns & PIPE_STAT_PORT_UNDERRUN_D13)
+ /* Underrun was caused downstream from the pipes */
+ drm_err(_priv->drm, "Port triggered a %s underrun
on pipe %c\n",
+ pipe_underrun_reason(underruns),
+ pipe_name(pipe));
+ else
+ drm_err(_priv->drm, "CPU pipe %c %s underrun\n",
+ pipe_name(pipe),
+ pipe_underrun_reason(underruns));
}
intel_fbc_handle_fifo_underrun_irq(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1bced71470a5..407b42706a14 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2389,6 +2389,18 @@ static void gen11_dsi_te_interrupt_handler(struct
drm_i915_private *dev_priv,
intel_uncore_write(_priv->uncore, DSI_INTR_IDENT_REG(port), tmp);
}
+static u32
+underrun_iir_mask(struct drm_i915_private *dev_priv)
+{
+ u32 mask = GEN8_PIPE_FIFO_UNDERRUN;
+
+ if (HAS_DISPLAY13(dev_priv))
+ mask |=
[Intel-gfx] [PATCH 16/18] drm/i915/display13: Calculate VDSC RC parameters
From: Vandita Kulkarni
Add methods to calculate rc parameters for all bpps, against the fixed
arrays that we already have for 8,10,12 valid o/p bpps, to cover RGB 444
formats. Our hw doesnt support YUV compression yet. The calculations
used here are from VESA C model for DSC 1.1
Cc: Manasi Navare
Cc: Juha-Pekka Heikkil
Signed-off-by: Vandita Kulkarni
Signed-off-by: Mohammed Khajapasha
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 98 ---
1 file changed, 88 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 8d8be0a006c7..41edcb7fdb47 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -5,7 +5,7 @@
* Author: Gaurav K Singh
* Manasi Navare
*/
-
+#include
#include "i915_drv.h"
#include "intel_display_types.h"
#include "intel_dsi.h"
@@ -376,12 +376,74 @@ static bool is_pipe_dsc(const struct intel_crtc_state
*crtc_state)
return true;
}
+static void
+calculate_rc_params(struct rc_parameters *rc,
+ struct drm_dsc_config *vdsc_cfg)
+{
+ int bpc = vdsc_cfg->bits_per_component;
+ int bpp = vdsc_cfg->bits_per_pixel >> 4;
+ int ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12,
-12, -12, -12 };
+ int ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12,
-12, -12 };
+ int ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10,
-12, -12, -12 };
+ int ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12,
-12, -12 };
+ int qp_bpc_modifier = (bpc - 8) * 2;
+ u32 res, buf_i;
+
+ if (vdsc_cfg->slice_height >= 8)
+ rc->first_line_bpg_offset = 12 + DIV_ROUND_UP((9 * min(34,
vdsc_cfg->slice_height - 8)), 100);
+ else
+ rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
+
+ /* Our hw supports only 444 modes as of today */
+ if (bpp >= 12)
+ rc->initial_offset = 2048;
+ else if (bpp >= 10)
+ rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584),
2);
+ else if (bpp >= 8)
+ rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
+ else
+ rc->initial_offset = 6144;
+
+ /* initial_xmit_delay = rc_model_size/2/compression_bpp */
+ rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
+
+ rc->flatness_min_qp = 3 + qp_bpc_modifier;
+ rc->flatness_max_qp = 12 + qp_bpc_modifier;
+
+ rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
+ rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
+
+ for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
+ /* Calculate range_bgp_offset */
+ if (bpp <= 6) {
+ rc->rc_range_params[buf_i].range_bpg_offset =
ofs_und6[buf_i];
+ } else if (bpp <= 8) {
+ res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] -
ofs_und6[buf_i])), 2);
+ rc->rc_range_params[buf_i].range_bpg_offset =
+ ofs_und6[buf_i]
+ res;
+ } else if (bpp <= 12) {
+ rc->rc_range_params[buf_i].range_bpg_offset =
+ ofs_und8[buf_i];
+ } else if (bpp <= 15) {
+ res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] -
ofs_und12[buf_i])), 3);
+ rc->rc_range_params[buf_i].range_bpg_offset =
+
ofs_und12[buf_i] + res;
+ } else {
+ rc->rc_range_params[buf_i].range_bpg_offset =
+
ofs_und15[buf_i];
+ }
+ }
+ return;
+}
+
int intel_dsc_compute_params(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_dsc_config *vdsc_cfg = _config->dsc.config;
u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
const struct rc_parameters *rc_params;
+ struct rc_parameters *rc = NULL;
u8 i = 0;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
@@ -416,9 +478,24 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
vdsc_cfg->rc_buf_thresh[13] = 0x7D;
}
- rc_params = get_rc_params(compressed_bpp, vdsc_cfg->bits_per_component);
- if (!rc_params)
- return -EINVAL;
+ /*
+* From Display13 onwards we supports compression bpps in steps of 1
+* upto uncompressed bpp-1, hence add calculations for all the rc
+* parameters
+*/
+ if
[Intel-gfx] [PATCH 17/18] drm/i915/display13: Add rc_qp_table for rcparams calculation
From: Vandita Kulkarni
Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by
the VESA C model for DSC 1.1
Cc: Manasi Navare
Signed-off-by: Vandita Kulkarni
Signed-off-by: Matt Roper
---
.../gpu/drm/i915/display/intel_qp_tables.h| 294 ++
drivers/gpu/drm/i915/display/intel_vdsc.c | 22 +-
2 files changed, 315 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.h
diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.h
b/drivers/gpu/drm/i915/display/intel_qp_tables.h
new file mode 100644
index ..13694d5220d4
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.h
@@ -0,0 +1,294 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include
+
+#define RC_RANGE_QP(min_max, bpp, row, col) \
+ rc_range_##min_max##qp444_##bpp##bpc[row][col]
+
+#ifndef DSC_NUM_BUF_RANGES
+#define DSC_NUM_BUF_RANGES 15
+#endif
+
+/* from BPP 6 to 24 in steps of 0.5 */
+#define RC_RANGE_QP444_8BPC_MAX_NUM_BPP37
+
+/* from BPP 6 to 30 in steps of 0.5 */
+#define RC_RANGE_QP444_10BPC_MAX_NUM_BPP 49
+
+/* from BPP 6 to 36 in steps of 0.5 */
+#define RC_RANGE_QP444_12BPC_MAX_NUM_BPP 61
+
+/*
+ * These qp tables are as per the C model
+ * and it has the rows pointing to bpps which increment
+ * in steps of 0.5
+ * We do not support fractional bpps as of today,
+ * hence we would skip the fractional bpps during
+ * our references for qp calclulations.
+ */
+__maybe_unused
+static const u8
rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
+ { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
+ { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+ { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+ { 6, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+ { 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3,
+ 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 0 },
+ { 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 0 },
+ { 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4,
+ 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 0 },
+ { 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5,
+ 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 1, 1, 1 },
+ { 14, 14, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 9, 9, 9, 8, 8,
+ 8, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3 }
+};
+
+__maybe_unused
+static const u8
rc_range_maxqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
+ { 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 6, 6, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+ { 8, 7, 7, 6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 2, 2, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+ { 8, 8, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 4, 3, 3, 2, 2, 2, 2, 2,
+ 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 },
+ { 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 4, 4, 3, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 0 },
+ { 9, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 5, 4, 4, 3, 3, 3, 3, 3,
+ 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1 },
+ { 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 4, 4, 3, 3, 3, 3, 3,
+ 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1 },
+ { 10, 10, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 6, 5, 5, 4, 4, 4, 4, 3,
+ 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1 },
+ { 11, 11, 10, 10, 9, 9, 9, 9, 9, 9, 8, 8, 8, 7, 7, 6, 6, 5, 5, 5, 5, 5,
+ 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 1,
[Intel-gfx] [PATCH 04/18] drm/i915/display13: Define plane capabilities
Display13's plane support is identical to RKL --- 5 universal + 1 cursor
with NV12 UV support on planes 1-3 and NV12 Y support on planes 4-5.
Bspec: 53657
Bspec: 49251
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_sprite.c | 16
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c| 2 +-
3 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index ec931a08ff28..81bb5eb1cd15 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -382,7 +382,7 @@ int intel_plane_check_src_coordinates(struct
intel_plane_state *plane_state)
static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
{
- if (HAS_D12_PLANE_MINIMIZATION(i915))
+ if (HAS_DISPLAY13(i915) || HAS_D12_PLANE_MINIMIZATION(i915))
return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
else
return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
@@ -2322,6 +2322,11 @@ static int skl_plane_check_fb(const struct
intel_crtc_state *crtc_state,
}
if (drm_rotation_90_or_270(rotation)) {
+ if (HAS_DISPLAY13(dev_priv)) {
+ DRM_DEBUG_KMS("90/270 rotation not supported on this
platform\n");
+ return -EINVAL;
+ }
+
if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
drm_dbg_kms(_priv->drm,
@@ -3338,9 +3343,12 @@ skl_universal_plane_create(struct drm_i915_private
*dev_priv,
if (ret)
goto fail;
- supported_rotations =
- DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
- DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
+ if (HAS_DISPLAY13(dev_priv))
+ supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
+ else
+ supported_rotations =
+ DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
+ DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
if (INTEL_GEN(dev_priv) >= 10)
supported_rotations |= DRM_MODE_REFLECT_X;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 407b42706a14..bb4fad71c429 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2290,7 +2290,7 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private
*dev_priv)
static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
{
- if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
+ if (HAS_DISPLAY13(dev_priv) || HAS_D12_PLANE_MINIMIZATION(dev_priv))
return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
else if (INTEL_GEN(dev_priv) >= 11)
return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 92ad3e7d1f6f..200d4eceaa4e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -265,7 +265,7 @@ void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv)
BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
- if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
+ if (HAS_DISPLAY13(dev_priv) || HAS_D12_PLANE_MINIMIZATION(dev_priv))
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 4;
else if (INTEL_GEN(dev_priv) >= 11)
--
2.25.4
___
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[Intel-gfx] [PATCH 02/18] drm/i915/display13: Handle proper AUX interrupt bits
Display13 has new AUX interrupt bits for DDI-D and DDI-E.
Bspec: 50064
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 12 +++-
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 06937a2d2714..1bced71470a5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2251,7 +2251,17 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private
*dev_priv)
{
u32 mask;
- if (INTEL_GEN(dev_priv) >= 12)
+ if (HAS_DISPLAY13(dev_priv))
+ return TGL_DE_PORT_AUX_DDIA |
+ TGL_DE_PORT_AUX_DDIB |
+ TGL_DE_PORT_AUX_DDIC |
+ D13_DE_PORT_AUX_DDID |
+ D13_DE_PORT_AUX_DDIE |
+ TGL_DE_PORT_AUX_USBC1 |
+ TGL_DE_PORT_AUX_USBC2 |
+ TGL_DE_PORT_AUX_USBC3 |
+ TGL_DE_PORT_AUX_USBC4;
+ else if (INTEL_GEN(dev_priv) >= 12)
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB |
TGL_DE_PORT_AUX_DDIC |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3031897239a0..10fd0e3af2d4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7858,6 +7858,8 @@ enum {
#define TGL_DE_PORT_AUX_USBC3 (1 << 10)
#define TGL_DE_PORT_AUX_USBC2 (1 << 9)
#define TGL_DE_PORT_AUX_USBC1 (1 << 8)
+#define D13_DE_PORT_AUX_DDIE (1 << 13)
+#define D13_DE_PORT_AUX_DDID (1 << 12)
#define TGL_DE_PORT_AUX_DDIC (1 << 2)
#define TGL_DE_PORT_AUX_DDIB (1 << 1)
#define TGL_DE_PORT_AUX_DDIA (1 << 0)
--
2.25.4
___
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[Intel-gfx] [PATCH 06/18] drm/i915/display13: Only enable legacy gamma for now
The multi-segment gamma used on past platforms is gone and replaced by a
logarithmic LUT. Until logarithmic LUT is enabled, let's just turn off
uapi color management (aside from legacy gamma) since it doesn't really
make sense to expose the full degamma and CTM when we only have limited
legacy gamma support to go with them. Note that the hardware
programming of the degamma and CTM is unchanged except that the degamma
table now has 128 entries instead of just 33.
The output CSC used implicitly for RGB->YUV conversions is also
unchanged and will continue to function as expected.
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_pci.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e5e10484bf8d..fb28f3b24dd8 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -945,7 +945,18 @@ static const struct intel_device_info adl_s_info = {
BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
.ddb_size = 4096, \
.mbus_size = 2048, \
- .num_supported_dbuf_slices = 4,
+ .num_supported_dbuf_slices = 4, \
+ /* \
+* FIXME: Just enable legacy gamma (and no degamma/csc) until \
+* logarithmic LUT is implemented. \
+* \
+* LEGACY_LUT_LENGTH = 256 entries \
+* \
+* Note that once logarithmic LUT is enabled and we re-enable \
+* real color management, degamma_lut_size here should be set \
+* to 128. \
+*/ \
+ .color = { .degamma_lut_size = 0, .gamma_lut_size = 256 }
#undef GEN
#undef PLATFORM
--
2.25.4
___
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[Intel-gfx] [PATCH 00/18] Preliminary Display13 support
Upcoming platforms will be using a "Display13" design. Despite the version number bump, Display13 is a pretty natural evolution from Display12 (which we've been using on TGL, RKL, DG1, and ADL-S). This series provides the basic Display13 support that isn't tied to a specific platform; any platforms incorporating the Display13 IP will have additional platform-specific display patches as well. Note that there are a few general Display13 changes that aren't included in this series and will be sent separately: * Tiled surfaces need to be mapped into the GGTT in a special way (using "Display Page Tables"). * Color management is programmed differently on Display13 (using a logarithmic scheme). Since this relates to some new DRM property uapi, we'll just leave color management mostly disabled in this series and enable the new logarithmic color management later. The changes for Display13 have some minor contextual conflicts with the ADL-S series that Aditya currently has in flight. Since the ADL-S patches will be landing any time now, I've based the patches here on top of the in-flight ADL-S patches. Juha-Pekka Heikkilä (1): drm/i915/display13: Support 128k plane stride Matt Roper (10): drm/i915/display13: add Display13 characteristics drm/i915/display13: Handle proper AUX interrupt bits drm/i915/display13: Enhanced pipe underrun reporting drm/i915/display13: Define plane capabilities drm/i915/display13: Only enable legacy gamma for now drm/i915/display13: Add Display13 power wells drm/i915/display13: Handle new location of outputs D and E drm/i915/display13: Increase maximum watermark lines to 255 drm/i915/display13: Required bandwidth increases when VT-d is active drm/i915/display13: Add Wa_14011503030:d13 Nischal Varide (1): drm/i915/display13: Enabling dithering after the CC1 pipe Uma Shankar (1): drm/i915/display13: Handle LPSP for Display 13 Vandita Kulkarni (5): drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp drm/i915/display13: Support DP1.4 compression BPPs drm/i915/display13: Get slice height before computing rc params drm/i915/display13: Calculate VDSC RC parameters drm/i915/display13: Add rc_qp_table for rcparams calculation drivers/gpu/drm/i915/display/intel_bios.c | 8 +- drivers/gpu/drm/i915/display/intel_bw.c | 3 + drivers/gpu/drm/i915/display/intel_color.c| 16 + drivers/gpu/drm/i915/display/intel_ddi.c | 8 +- drivers/gpu/drm/i915/display/intel_display.c | 21 +- drivers/gpu/drm/i915/display/intel_display.h | 8 + .../drm/i915/display/intel_display_debugfs.c | 7 + .../drm/i915/display/intel_display_power.c| 426 +- drivers/gpu/drm/i915/display/intel_dp.c | 60 ++- drivers/gpu/drm/i915/display/intel_dp_aux.c | 14 +- .../drm/i915/display/intel_fifo_underrun.c| 55 ++- .../gpu/drm/i915/display/intel_qp_tables.h| 294 drivers/gpu/drm/i915/display/intel_sprite.c | 40 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 123 - drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_irq.c | 28 +- drivers/gpu/drm/i915/i915_pci.c | 22 + drivers/gpu/drm/i915/i915_reg.h | 29 +- drivers/gpu/drm/i915/intel_device_info.c | 2 +- drivers/gpu/drm/i915/intel_device_info.h | 2 + drivers/gpu/drm/i915/intel_pm.c | 15 +- 21 files changed, 1116 insertions(+), 66 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.h -- 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Disable runtime power management during shutdown
On Wed, Jan 27, 2021 at 08:19:09PM +0200, Imre Deak wrote:
> At least on some TGL platforms PUNIT wants to access some display HW
> registers, but it doesn't handle display power managment (disabling DC
> states as required) and so this register access will lead to a hang. To
> prevent this disable runtime power management for poweroff and reboot.
>
> Reported-and-tested-by: Khaled Almahallawy
> Signed-off-by: Imre Deak
Chris or Ville, could you ack if you see no problem with this?
> ---
> drivers/gpu/drm/i915/i915_drv.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 0037b81d991e..6f83cca8e27b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1054,6 +1054,8 @@ static void intel_shutdown_encoders(struct
> drm_i915_private *dev_priv)
> void i915_driver_shutdown(struct drm_i915_private *i915)
> {
> disable_rpm_wakeref_asserts(>runtime_pm);
> + intel_runtime_pm_disable(>runtime_pm);
> + intel_power_domains_disable(i915);
>
> i915_gem_suspend(i915);
>
> @@ -1069,7 +1071,10 @@ void i915_driver_shutdown(struct drm_i915_private
> *i915)
> intel_suspend_encoders(i915);
> intel_shutdown_encoders(i915);
>
> + intel_power_domains_driver_remove(i915);
> enable_rpm_wakeref_asserts(>runtime_pm);
> +
> + intel_runtime_pm_driver_release(>runtime_pm);
> }
>
> static bool suspend_to_idle(struct drm_i915_private *dev_priv)
> --
> 2.25.1
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915: Nuke not needed members of dram_info
== Series Details == Series: series starting with [CI,1/3] drm/i915: Nuke not needed members of dram_info URL : https://patchwork.freedesktop.org/series/86404/ State : success == Summary == CI Bug Log - changes from CI_DRM_9695 -> Patchwork_19531 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/index.html Known issues Here are the changes found in Patchwork_19531 that come from known issues: ### IGT changes ### Issues hit * igt@fbdev@read: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-tgl-y/igt@fb...@read.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/fi-tgl-y/igt@fb...@read.html [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (44 -> 39) -- Missing(5): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9695 -> Patchwork_19531 CI-20190529: 20190529 CI_DRM_9695: 67e514b158700703fcaaed71c3fb1eea8b2e645c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5977: 0b6967520b15e73773eace7937ed8c17ba411bc0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19531: 8e4dd2f243e2cc51d43e6b67f2a9d6d2ce5c45a3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8e4dd2f243e2 drm/i915: Rename is_16gb_dimm to wm_lv_0_adjust_needed 287b939f58f6 drm/i915/gen11+: Only load DRAM information from pcode 0373afb0d1b9 drm/i915: Nuke not needed members of dram_info == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Remove obj->mm.lock! (rev14)
== Series Details ==
Series: drm/i915: Remove obj->mm.lock! (rev14)
URL : https://patchwork.freedesktop.org/series/82337/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9695 -> Patchwork_19530
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19530 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19530, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19530:
### IGT changes ###
Possible regressions
* igt@gem_busy@busy@all:
- fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-bsw-kefka/igt@gem_busy@b...@all.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/fi-bsw-kefka/igt@gem_busy@b...@all.html
- fi-bsw-n3050: [PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-bsw-n3050/igt@gem_busy@b...@all.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/fi-bsw-n3050/igt@gem_busy@b...@all.html
* igt@gem_exec_fence@basic-await@vecs0:
- fi-bsw-nick:[PASS][5] -> [DMESG-WARN][6] +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-bsw-nick/igt@gem_exec_fence@basic-aw...@vecs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/fi-bsw-nick/igt@gem_exec_fence@basic-aw...@vecs0.html
* igt@gem_exec_fence@nb-await@vecs0:
- fi-apl-guc: [PASS][7] -> [DMESG-WARN][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-apl-guc/igt@gem_exec_fence@nb-aw...@vecs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/fi-apl-guc/igt@gem_exec_fence@nb-aw...@vecs0.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-y: [PASS][9] -> [SKIP][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-tgl-y/igt@prime_v...@basic-userptr.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/fi-tgl-y/igt@prime_v...@basic-userptr.html
- fi-icl-u2: [PASS][11] -> [SKIP][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-icl-u2/igt@prime_v...@basic-userptr.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/fi-icl-u2/igt@prime_v...@basic-userptr.html
- fi-tgl-u2: [PASS][13] -> [SKIP][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-tgl-u2/igt@prime_v...@basic-userptr.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/fi-tgl-u2/igt@prime_v...@basic-userptr.html
- fi-cml-s: [PASS][15] -> [SKIP][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-cml-s/igt@prime_v...@basic-userptr.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/fi-cml-s/igt@prime_v...@basic-userptr.html
- fi-icl-y: [PASS][17] -> [SKIP][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-icl-y/igt@prime_v...@basic-userptr.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/fi-icl-y/igt@prime_v...@basic-userptr.html
- fi-cml-u2: [PASS][19] -> [SKIP][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-cml-u2/igt@prime_v...@basic-userptr.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/fi-cml-u2/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> [FAIL][21]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/fi-bsw-kefka/igt@run...@aborted.html
- fi-bsw-nick:NOTRUN -> [FAIL][22]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/fi-bsw-nick/igt@run...@aborted.html
- fi-bsw-n3050: NOTRUN -> [FAIL][23]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/fi-bsw-n3050/igt@run...@aborted.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_parallel@engines@userptr:
- {fi-tgl-dsi}: [PASS][24] -> [FAIL][25] +1 similar issue
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-tgl-dsi/igt@gem_exec_parallel@engi...@userptr.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/fi-tgl-dsi/igt@gem_exec_parallel@engi...@userptr.html
* igt@prime_vgem@basic-userptr:
- {fi-ehl-1}: [PASS][26] -> [SKIP][27]
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/fi-ehl-1/igt@prime_v...@basic-userptr.html
[27]:
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Remove obj->mm.lock! (rev14)
== Series Details == Series: drm/i915: Remove obj->mm.lock! (rev14) URL : https://patchwork.freedesktop.org/series/82337/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1413: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1413: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1413: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1413: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1413: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Remove obj->mm.lock! (rev14)
== Series Details == Series: drm/i915: Remove obj->mm.lock! (rev14) URL : https://patchwork.freedesktop.org/series/82337/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1192:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Remove obj->mm.lock! (rev14)
== Series Details ==
Series: drm/i915: Remove obj->mm.lock! (rev14)
URL : https://patchwork.freedesktop.org/series/82337/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f0caa76735a7 drm/i915: Do not share hwsp across contexts any more, v7.
-:562: WARNING:CONSTANT_COMPARISON: Comparisons should place the constant on
the right side of the test
#562: FILE: drivers/gpu/drm/i915/gt/intel_timeline.c:286:
+ if (TIMELINE_SEQNO_BYTES <= BIT(5) && (next_ofs & BIT(5)))
total: 0 errors, 1 warnings, 0 checks, 954 lines checked
2e13b870eff3 drm/i915: Pin timeline map after first timeline pin, v3.
-:16: WARNING:TYPO_SPELLING: 'arithmatic' may be misspelled - perhaps
'arithmetic'?
#16:
- Fix NULL + XX arithmatic, use casts. (kbuild)
^^
total: 0 errors, 1 warnings, 0 checks, 296 lines checked
cfa8d0589b53 drm/i915: Move cmd parser pinning to execbuffer
8b3ce40a27dc drm/i915: Add missing -EDEADLK handling to execbuf pinning, v2.
-:59: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#59: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:452:
+ err = i915_vma_pin_ww(vma, >ww,
entry->pad_to_size,
total: 0 errors, 0 warnings, 1 checks, 75 lines checked
e74b81617eb0 drm/i915: Ensure we hold the object mutex in pin correctly.
13b9209c078e drm/i915: Add gem object locking to madvise.
e4fe993ac962 drm/i915: Move HAS_STRUCT_PAGE to obj->flags
-:110: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#110: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.c:63:
+ struct lock_class_key *key, unsigned flags)
-:133: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#133: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.h:53:
+ unsigned alloc_flags);
total: 0 errors, 2 warnings, 0 checks, 350 lines checked
0f0d96bdbcb2 drm/i915: Rework struct phys attachment handling
ba20fbbe4737 drm/i915: Convert i915_gem_object_attach_phys() to ww locking, v2.
372b944d10b8 drm/i915: make lockdep slightly happier about execbuf.
0cbd23b2d726 drm/i915: Disable userptr pread/pwrite support.
c973c01f3065 drm/i915: No longer allow exporting userptr through dma-buf
e06a0adf3a6f drm/i915: Reject more ioctls for userptr
229733dcc336 drm/i915: Reject UNSYNCHRONIZED for userptr, v2.
4acda00724a9 drm/i915: Make compilation of userptr code depend on MMU_NOTIFIER.
a653a892ff43 drm/i915: Fix userptr so we do not have to worry about
obj->mm.lock, v6.
-:294: WARNING:LONG_LINE: line length of 121 exceeds 100 columns
#294: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.h:605:
+static inline int i915_gem_object_userptr_submit_init(struct
drm_i915_gem_object *obj) { GEM_BUG_ON(1); return -ENODEV; }
-:295: WARNING:LONG_LINE: line length of 121 exceeds 100 columns
#295: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.h:606:
+static inline int i915_gem_object_userptr_submit_done(struct
drm_i915_gem_object *obj) { GEM_BUG_ON(1); return -ENODEV; }
-:296: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#296: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.h:607:
+static inline void i915_gem_object_userptr_submit_fini(struct
drm_i915_gem_object *obj) { GEM_BUG_ON(1); }
-:354: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#354: FILE: drivers/gpu/drm/i915/gem/i915_gem_userptr.c:2:
* SPDX-License-Identifier: MIT
-:358: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each
line
#358: FILE: drivers/gpu/drm/i915/gem/i915_gem_userptr.c:6:
+ *
+ * Based on amdgpu_mn, which bears the following notice:
-:359: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each
line
#359: FILE: drivers/gpu/drm/i915/gem/i915_gem_userptr.c:7:
+ * Based on amdgpu_mn, which bears the following notice:
+ *
-:444: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#444: FILE: drivers/gpu/drm/i915/gem/i915_gem_userptr.c:63:
+ struct drm_i915_gem_object *obj = container_of(mni, struct
drm_i915_gem_object, userptr.notifier);
-:1132: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#1132: FILE: drivers/gpu/drm/i915/gem/i915_gem_userptr.c:300:
+ pinned = ret = 0;
-:1147: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1147: FILE: drivers/gpu/drm/i915/gem/i915_gem_userptr.c:315:
+ if (mmu_interval_read_retry(>userptr.notifier,
+ !obj->userptr.page_ref ? notifier_seq :
-:1268: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#1268: FILE: drivers/gpu/drm/i915/i915_drv.h:601:
+ spinlock_t notifier_lock;
total: 0 errors, 7 warnings, 3 checks, 1208 lines checked
1d108228e705 drm/i915: Flatten obj->mm.lock
6fb47c6d71c7 drm/i915: Populate logical context during first pin.
01ca4854c93e drm/i915: Make ring submission compatible with obj->mm.lock
removal, v2.
3abcb0076a68 drm/i915: Handle ww
Re: [Intel-gfx] [PATCH v7 01/63] drm/i915: Do not share hwsp across contexts any more, v7.
This series still willfully breaks ABI resulting in iris aborting among others, introduces an unrecoverable dos, despite knowing how to avoid both.It is unconscionable that this design was not revised to avoid such breakage, after being rejected. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 14/63] drm/i915: Reject UNSYNCHRONIZED for userptr, v2.
We've never used this bit in mesa.
Acked-by: Jason Ekstrand
On Thu, Jan 28, 2021 at 10:26 AM Maarten Lankhorst
wrote:
>
> We should not allow this any more, as it will break with the new userptr
> implementation, it could still be made to work, but there's no point in
> doing so.
>
> Inspection of the beignet opencl driver shows that it's only used
> when normal userptr is not available, which means for new kernels
> you will need CONFIG_I915_USERPTR.
>
> Signed-off-by: Maarten Lankhorst
> Acked-by: Dave Airlie
> Reviewed-by: Thomas Hellström
> Cc: Jason Ekstrand
> ---
> drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 10 ++
> 1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> index c89cf911fb29..80bc10b4ac74 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> @@ -224,7 +224,7 @@ i915_gem_userptr_init__mmu_notifier(struct
> drm_i915_gem_object *obj,
> struct i915_mmu_object *mo;
>
> if (flags & I915_USERPTR_UNSYNCHRONIZED)
> - return capable(CAP_SYS_ADMIN) ? 0 : -EPERM;
> + return -ENODEV;
>
> if (GEM_WARN_ON(!obj->userptr.mm))
> return -EINVAL;
> @@ -274,13 +274,7 @@ static int
> i915_gem_userptr_init__mmu_notifier(struct drm_i915_gem_object *obj,
> unsigned flags)
> {
> - if ((flags & I915_USERPTR_UNSYNCHRONIZED) == 0)
> - return -ENODEV;
> -
> - if (!capable(CAP_SYS_ADMIN))
> - return -EPERM;
> -
> - return 0;
> + return -ENODEV;
> }
>
> static void
> --
> 2.30.0
>
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Re: [Intel-gfx] [PATCH v7 13/63] drm/i915: Reject more ioctls for userptr
On Thu, Jan 28, 2021 at 10:26 AM Maarten Lankhorst
wrote:
>
> There are a couple of ioctl's related to tiling and cache placement,
> that make no sense for userptr, reject those:
> - i915_gem_set_tiling_ioctl()
> Tiling should always be linear for userptr. Changing placement will
> fail with -ENXIO.
> - i915_gem_set_caching_ioctl()
> Userptr memory should always be cached. Changing caching mode will
> fail with -ENXIO.
> - i915_gem_set_domain_ioctl()
> Changed to be equivalent to gem_wait, which is correct for the
> cached linear userptr pointers. This is required because we
> cannot grab a reference to the pages in the rework, but waiting
> for idle will do the same.
>
> This plus the previous changes have been tested against beignet
> by using its own unit tests, and intel-video-compute by using
> piglit's opencl tests.
Did you test against mesa at all?
>
> Signed-off-by: Maarten Lankhorst
> Reviewed-by: Thomas Hellström
> Cc: Jason Ekstrand
>
> -- Still needs an ack from relevant userspace that it won't break, but should
> be good.
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/gem/i915_gem_domain.c | 12 ++--
> drivers/gpu/drm/i915/gem/i915_gem_object.h | 6 ++
> drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 ++-
> 4 files changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d013b0fab128..3e24db8b9ad6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14172,7 +14172,7 @@ static int
> intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
>
> - if (obj->userptr.mm) {
> + if (i915_gem_object_is_userptr(obj)) {
> drm_dbg(>drm,
> "attempting to use a userptr for a framebuffer,
> denied\n");
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> index 36f54cedaaeb..3078e9a09f70 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> @@ -335,7 +335,13 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev,
> void *data,
> * not allowed to be changed by userspace.
> */
> if (i915_gem_object_is_proxy(obj)) {
> - ret = -ENXIO;
> + /*
> +* Silently allow cached for userptr; the vulkan driver
> +* sets all objects to cached
> +*/
> + if (!i915_gem_object_is_userptr(obj) ||
> + args->caching != I915_CACHING_CACHED)
Thanks for looking out for this case. I just double-checked and, yes,
we set caching on userptr but we always set it to CACHED so this
should take care of us, assuming it does what it looks like it does.
Acked-by: Jason Ekstrand
> + ret = -ENXIO;
> goto out;
> }
>
> @@ -533,7 +539,9 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void
> *data,
> * considered to be outside of any cache domain.
> */
> if (i915_gem_object_is_proxy(obj)) {
> - err = -ENXIO;
> + /* silently allow userptr to complete */
> + if (!i915_gem_object_is_userptr(obj))
> + err = -ENXIO;
> goto out;
> }
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> index e9a8ee96d64c..3f300a1d27ba 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> @@ -574,6 +574,12 @@ void __i915_gem_object_flush_frontbuffer(struct
> drm_i915_gem_object *obj,
> void __i915_gem_object_invalidate_frontbuffer(struct drm_i915_gem_object
> *obj,
> enum fb_op_origin origin);
>
> +static inline bool
> +i915_gem_object_is_userptr(struct drm_i915_gem_object *obj)
> +{
> + return obj->userptr.mm;
> +}
> +
> static inline void
> i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj,
> enum fb_op_origin origin)
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> index 0c30ca52dee3..c89cf911fb29 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> @@ -721,7 +721,8 @@ static const struct drm_i915_gem_object_ops
> i915_gem_userptr_ops = {
> .name = "i915_gem_object_userptr",
> .flags = I915_GEM_OBJECT_IS_SHRINKABLE |
> I915_GEM_OBJECT_NO_MMAP |
> -I915_GEM_OBJECT_ASYNC_CANCEL,
> +
Re: [Intel-gfx] [PATCH v7 12/63] drm/i915: No longer allow exporting userptr through dma-buf
I double-checked and Vulkan doesn't do/allow this.
Acked-by: Jason Ekstrand
On Thu, Jan 28, 2021 at 10:26 AM Maarten Lankhorst
wrote:
>
> It doesn't make sense to export a memory address, we will prevent
> allowing access this way to different address spaces when we
> rework userptr handling, so best to explicitly disable it.
>
> Signed-off-by: Maarten Lankhorst
> Reviewed-by: Thomas Hellström
> Cc: Jason Ekstrand
>
> -- Still needs an ack from relevant userspace that it won't break, but should
> be good.
> ---
> drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> index 5a19699c2d7e..0c30ca52dee3 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> @@ -694,10 +694,9 @@ i915_gem_userptr_release(struct drm_i915_gem_object *obj)
> static int
> i915_gem_userptr_dmabuf_export(struct drm_i915_gem_object *obj)
> {
> - if (obj->userptr.mmu_object)
> - return 0;
> + drm_dbg(obj->base.dev, "Exporting userptr no longer allowed\n");
>
> - return i915_gem_userptr_init__mmu_notifier(obj, 0);
> + return -EINVAL;
> }
>
> static int
> --
> 2.30.0
>
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Re: [Intel-gfx] [PATCH v2 3/4] drm/i915: Fail driver probe when unable to load DRAM information
On Wed, 2021-01-27 at 20:21 -0800, Lucas De Marchi wrote:
> On Wed, Jan 27, 2021 at 08:54:01AM -0800, Jose Souza wrote:
> > DRAM information is required to properly program display.
> > Before "drm/i915/gen11+: Only load DRAM information from pcode" we
> > were failing driver load if unable to fetch DRAM information from
> > pcode form GEN11+ but we should also extend it to GEN9 plaforms.
> >
> > Signed-off-by: José Roberto de Souza
>
> makes sense and seems correct. But this needs to be tested on DG1 that
> is not on CI and AFAIR misbehaved when trying to get this info from
> pcode. If that is passing now,
Okay, will send the 3 other and merge as soon as I get CI results.
Will do some more testing with this one before merging it, it might be causing
some regression in fi-glk-dsi.
thanks for the reviews.
>
>
> Reviewed-by: Lucas De Marchi
>
> Lucas De Marchi
>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 6 +-
> > drivers/gpu/drm/i915/intel_dram.c | 13 +
> > drivers/gpu/drm/i915/intel_dram.h | 2 +-
> > 3 files changed, 15 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index aec0e870dc25..7ff58ea30c7c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -622,12 +622,16 @@ static int i915_driver_hw_probe(struct
> > drm_i915_private *dev_priv)
> > * Fill the dram structure to get the system dram info. This will be
> > * used for memory latency calculation.
> > */
> > - intel_dram_detect(dev_priv);
> > + ret = intel_dram_detect(dev_priv);
> > + if (ret)
> > + goto err_dram;
> >
> > intel_bw_init_hw(dev_priv);
> >
> > return 0;
> >
> > +err_dram:
> > + intel_gvt_driver_remove(dev_priv);
> > err_msi:
> > if (pdev->msi_enabled)
> > pci_disable_msi(pdev);
> > diff --git a/drivers/gpu/drm/i915/intel_dram.c
> > b/drivers/gpu/drm/i915/intel_dram.c
> > index 4d5ab206eacb..6ce56eedaf12 100644
> > --- a/drivers/gpu/drm/i915/intel_dram.c
> > +++ b/drivers/gpu/drm/i915/intel_dram.c
> > @@ -484,7 +484,7 @@ static int gen12_get_dram_info(struct drm_i915_private
> > *i915)
> > return icl_pcode_read_mem_global_info(i915);
> > }
> >
> > -void intel_dram_detect(struct drm_i915_private *i915)
> > +int intel_dram_detect(struct drm_i915_private *i915)
> > {
> > struct dram_info *dram_info = >dram_info;
> > int ret;
> > @@ -497,7 +497,7 @@ void intel_dram_detect(struct drm_i915_private *i915)
> > dram_info->is_16gb_dimm = !IS_GEN9_LP(i915);
> >
> > if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915))
> > - return;
> > + return 0;
> >
> > if (INTEL_GEN(i915) >= 12)
> > ret = gen12_get_dram_info(i915);
> > @@ -507,13 +507,18 @@ void intel_dram_detect(struct drm_i915_private *i915)
> > ret = bxt_get_dram_info(i915);
> > else
> > ret = skl_get_dram_info(i915);
> > - if (ret)
> > - return;
> > +
> > + if (ret) {
> > + drm_warn(>drm, "Unable to load dram information\n");
> > + return ret;
> > + }
> >
> > drm_dbg_kms(>drm, "DRAM channels: %u\n", dram_info->num_channels);
> >
> > drm_dbg_kms(>drm, "DRAM 16Gb DIMMs: %s\n",
> > yesno(dram_info->is_16gb_dimm));
> > +
> > + return 0;
> > }
> >
> > static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
> > diff --git a/drivers/gpu/drm/i915/intel_dram.h
> > b/drivers/gpu/drm/i915/intel_dram.h
> > index 4ba13c13162c..2a0f283b1a1d 100644
> > --- a/drivers/gpu/drm/i915/intel_dram.h
> > +++ b/drivers/gpu/drm/i915/intel_dram.h
> > @@ -9,6 +9,6 @@
> > struct drm_i915_private;
> >
> > void intel_dram_edram_detect(struct drm_i915_private *i915);
> > -void intel_dram_detect(struct drm_i915_private *i915);
> > +int intel_dram_detect(struct drm_i915_private *i915);
> >
> > #endif /* __INTEL_DRAM_H__ */
> > --
> > 2.30.0
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 20/41] drm/i915: Replace priolist rbtree with a skiplist
On 28/01/2021 16:26, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2021-01-28 15:56:19)
On 25/01/2021 14:01, Chris Wilson wrote:
diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h
b/drivers/gpu/drm/i915/i915_priolist_types.h
index bc2fa84f98a8..1200c3df6a4a 100644
--- a/drivers/gpu/drm/i915/i915_priolist_types.h
+++ b/drivers/gpu/drm/i915/i915_priolist_types.h
@@ -38,10 +38,36 @@ enum {
#define I915_PRIORITY_UNPREEMPTABLE INT_MAX
#define I915_PRIORITY_BARRIER (I915_PRIORITY_UNPREEMPTABLE - 1)
+#ifdef CONFIG_64BIT
+#define I915_PRIOLIST_HEIGHT 12
+#else
+#define I915_PRIOLIST_HEIGHT 11
+#endif
I did not get this. On one hand I could think pointers are larger on
64-bit so go for fewer levels, if size was a concern. But on the other
hand 32-bit is less important these days, definitely much less as a
performance platform. So going for less memory use => worse performance
on a less important platform, which typically could be more memory
constrained? Not sure I see it as that important either way to be
distinctive but a comment would satisfy me.
Just aligned to the cacheline. The struct is 128B on 64b and 64B on 32b.
On 64B, we will scale to around 16 million requests in flight and 4
million on 32b. Which should be enough.
If we shrunk 64b to a 64B node, we would only scale to 256 requests
which limit we definitely will exceed.
Ok thanks, pouring it into a comment is implied.
struct i915_priolist {
struct list_head requests;
What would be on this list? Request can only be on one at a time, so I
was thinking these nodes would have pointers to list of that priority,
rather than lists themselves. Assuming there can be multiple nodes of
the same priority in the 2d hierarcy. Possibly I don't understand the
layout.
A request is only on one list (queue, active, hold). But we may still
have more than one request at the same deadline, though that will likely
be limited to priority-inheritance and timeslice deferrals.
Since we would need pointer to the request, we could only reclaim a
single pointer here, which is not enough to warrant reducing the overall
node size. And while there is at least one user of request->sched.link,
the list maintenance will still be incurred. Using request->sched.link
remains a convenient interface.
Lost you.
Is the data structure like this and I will limit to priorities for
simplicity:
Level1: [-1]->[1]
Level0: [-1]>[0]->[1]
[SENTINEL]
Each of the boxes is struct i915_priolist?
Sentinel contains pointers to first i915_priolist for each level. Or
maybe it could contain just a single pointer to highest level (most
sparse) list.
And then each box is i915_priolist, single linked to next, in order.
But it should also have a single pointer for down, or up (or both)? I
don't understand why you have up to "max levels" pointers in each.
And each box should then contain a pointer to a list of requests. I
cannot each have it's own list since there are duplicates.
But obviously I am understanding something way wrong.
- struct rb_node node;
int priority;
+
+ int level;
+ struct i915_priolist *next[I915_PRIOLIST_HEIGHT];
Does every node need maximum height or you could allocated depending on
current height?
Every slab allocation here is a power of 2, so there are only a few
different options that are worthwhile (on 64b the only other choice is
[4], unless you want to go larger to [28]). It did not feel like enough
benefit to justify the extra code.
-static void assert_priolists(struct i915_sched_engine * const se)
-{
- struct rb_node *rb;
- long last_prio;
-
- if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
- return;
-
- GEM_BUG_ON(rb_first_cached(>queue) !=
-rb_first(>queue.rb_root));
-
- last_prio = INT_MAX;
- for (rb = rb_first_cached(>queue); rb; rb = rb_next(rb)) {
- const struct i915_priolist *p = to_priolist(rb);
-
- GEM_BUG_ON(p->priority > last_prio);
- last_prio = p->priority;
- }
+ root->prng = next_pseudo_random32(root->prng);
+ return __ffs(root->prng) / 2;
Where is the relationship to I915_PRIOLIST_HEIGHT? Feels root->prng %
I915_PRIOLIST_HEIGHT would be more obvious here unless I am terribly
mistaken. Or at least put a comment saying why the hack.
HEIGHT is the maximum possible for our struct. skiplists only want to
increment the height of the tree one step at a time. So we choose a level
with decreasing probability, and then limit that to the maximum height of
the current tree + 1, clamped to HEIGHT.
You might notice that unlike traditional skiplists, this uses a
That's optimistic, that I would notice that. I'll stick to the basics
for now. :)
Regards,
Tvrtko
probability of 0.25 for each additional level. A neat trick discovered by
Con Kolivas (I haven't found it mentioned elsewhere) as the cost of the
extra level (using P=.5) is the same as the
[Intel-gfx] [PATCH CI 2/3] drm/i915/gen11+: Only load DRAM information from pcode
Up to now we were reading some DRAM information from MCHBAR register
and from pcode what is already not good but some GEN12(TGL-H and ADL-S)
platforms have MCHBAR DRAM information in different offsets.
This was notified to HW team that decided that the best alternative is
always apply the 16gb_dimm watermark adjustment for GEN12+ platforms
and read the remaning DRAM information needed to other display
programming from pcode.
So here moving the DRAM pcode function to intel_dram.c, removing
the duplicated fields from intel_qgv_info, setting and using
information from dram_info.
v2:
- bring back num_points to intel_qgv_info as num_qgv_point can be
overwritten in icl_get_qgv_points()
- add gen12_get_dram_info() and simplify gen11_get_dram_info()
Reviewed-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bw.c | 80 +++-
drivers/gpu/drm/i915/i915_drv.c | 5 +-
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_dram.c | 82 -
4 files changed, 93 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index bd060404d249..4b5a30ac84bc 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -20,76 +20,9 @@ struct intel_qgv_point {
struct intel_qgv_info {
struct intel_qgv_point points[I915_NUM_QGV_POINTS];
u8 num_points;
- u8 num_channels;
u8 t_bl;
- enum intel_dram_type dram_type;
};
-static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv,
- struct intel_qgv_info *qi)
-{
- u32 val = 0;
- int ret;
-
- ret = sandybridge_pcode_read(dev_priv,
-ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
-ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
-, NULL);
- if (ret)
- return ret;
-
- if (IS_GEN(dev_priv, 12)) {
- switch (val & 0xf) {
- case 0:
- qi->dram_type = INTEL_DRAM_DDR4;
- break;
- case 3:
- qi->dram_type = INTEL_DRAM_LPDDR4;
- break;
- case 4:
- qi->dram_type = INTEL_DRAM_DDR3;
- break;
- case 5:
- qi->dram_type = INTEL_DRAM_LPDDR3;
- break;
- default:
- MISSING_CASE(val & 0xf);
- break;
- }
- } else if (IS_GEN(dev_priv, 11)) {
- switch (val & 0xf) {
- case 0:
- qi->dram_type = INTEL_DRAM_DDR4;
- break;
- case 1:
- qi->dram_type = INTEL_DRAM_DDR3;
- break;
- case 2:
- qi->dram_type = INTEL_DRAM_LPDDR3;
- break;
- case 3:
- qi->dram_type = INTEL_DRAM_LPDDR4;
- break;
- default:
- MISSING_CASE(val & 0xf);
- break;
- }
- } else {
- MISSING_CASE(INTEL_GEN(dev_priv));
- qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */
- }
-
- qi->num_channels = (val & 0xf0) >> 4;
- qi->num_points = (val & 0xf00) >> 8;
-
- if (IS_GEN(dev_priv, 12))
- qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16;
- else if (IS_GEN(dev_priv, 11))
- qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
-
- return 0;
-}
-
static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
struct intel_qgv_point *sp,
int point)
@@ -139,11 +72,15 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private
*dev_priv,
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi)
{
+ const struct dram_info *dram_info = _priv->dram_info;
int i, ret;
- ret = icl_pcode_read_mem_global_info(dev_priv, qi);
- if (ret)
- return ret;
+ qi->num_points = dram_info->num_qgv_points;
+
+ if (IS_GEN(dev_priv, 12))
+ qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 16;
+ else if (IS_GEN(dev_priv, 11))
+ qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
if (drm_WARN_ON(_priv->drm,
qi->num_points > ARRAY_SIZE(qi->points)))
@@ -209,7 +146,7 @@ static int icl_get_bw_info(struct drm_i915_private
*dev_priv, const struct intel
{
struct intel_qgv_info qi = {};
[Intel-gfx] [PATCH CI 3/3] drm/i915: Rename is_16gb_dimm to wm_lv_0_adjust_needed
As it now it is always required for GEN12+ the is_16gb_dimm name
do not make sense for GEN12+.
v2:
- Updated comment on top of "dram_info->wm_lv_0_adjust_needed =
!IS_GEN9_LP(i915);"
Reviewed-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_dram.c | 15 +++
drivers/gpu/drm/i915/intel_pm.c | 2 +-
3 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 80227d47b5cb..f684147290cb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1128,7 +1128,7 @@ struct drm_i915_private {
} wm;
struct dram_info {
- bool is_16gb_dimm;
+ bool wm_lv_0_adjust_needed;
u8 num_channels;
bool symmetric_memory;
enum intel_dram_type {
diff --git a/drivers/gpu/drm/i915/intel_dram.c
b/drivers/gpu/drm/i915/intel_dram.c
index 4d5ab206eacb..73d256fc6830 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -207,7 +207,7 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
return -EINVAL;
}
- dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
+ dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
dram_info->symmetric_memory = intel_is_dram_symmetric(, );
@@ -479,7 +479,7 @@ static int gen11_get_dram_info(struct drm_i915_private
*i915)
static int gen12_get_dram_info(struct drm_i915_private *i915)
{
/* Always needed for GEN12+ */
- i915->dram_info.is_16gb_dimm = true;
+ i915->dram_info.wm_lv_0_adjust_needed = true;
return icl_pcode_read_mem_global_info(i915);
}
@@ -490,11 +490,10 @@ void intel_dram_detect(struct drm_i915_private *i915)
int ret;
/*
-* Assume 16Gb DIMMs are present until proven otherwise.
-* This is only used for the level 0 watermark latency
-* w/a which does not apply to bxt/glk.
+* Assume level 0 watermark latency adjustment is needed until proven
+* otherwise, this w/a is not needed by bxt/glk.
*/
- dram_info->is_16gb_dimm = !IS_GEN9_LP(i915);
+ dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);
if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915))
return;
@@ -512,8 +511,8 @@ void intel_dram_detect(struct drm_i915_private *i915)
drm_dbg_kms(>drm, "DRAM channels: %u\n", dram_info->num_channels);
- drm_dbg_kms(>drm, "DRAM 16Gb DIMMs: %s\n",
- yesno(dram_info->is_16gb_dimm));
+ drm_dbg_kms(>drm, "Watermark level 0 adjustment needed: %s\n",
+ yesno(dram_info->wm_lv_0_adjust_needed));
}
static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6e9678bd0597..c58e5077590d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2930,7 +2930,7 @@ static void intel_read_wm_latency(struct drm_i915_private
*dev_priv,
* any underrun. If not able to get Dimm info assume 16GB dimm
* to avoid any underrun.
*/
- if (dev_priv->dram_info.is_16gb_dimm)
+ if (dev_priv->dram_info.wm_lv_0_adjust_needed)
wm[0] += 1;
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
--
2.30.0
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[Intel-gfx] [PATCH CI 1/3] drm/i915: Nuke not needed members of dram_info
Valid, ranks and bandwidth_kbps are set into dram_info but are not
used anywhere else so nuking it.
Reviewed-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 4 +--
drivers/gpu/drm/i915/i915_drv.h | 3 --
drivers/gpu/drm/i915/intel_dram.c | 47 +++
3 files changed, 12 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 49d94ffe4796..f2aa7275055b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -620,8 +620,8 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
intel_opregion_setup(dev_priv);
/*
-* Fill the dram structure to get the system raw bandwidth and
-* dram info. This will be used for memory latency calculation.
+* Fill the dram structure to get the system dram info. This will be
+* used for memory latency calculation.
*/
intel_dram_detect(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3edc9c4f2d21..4e8e151c7ade 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1128,11 +1128,8 @@ struct drm_i915_private {
} wm;
struct dram_info {
- bool valid;
bool is_16gb_dimm;
u8 num_channels;
- u8 ranks;
- u32 bandwidth_kbps;
bool symmetric_memory;
enum intel_dram_type {
INTEL_DRAM_UNKNOWN,
diff --git a/drivers/gpu/drm/i915/intel_dram.c
b/drivers/gpu/drm/i915/intel_dram.c
index 4754296a250e..694fbd8c9cd4 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -201,17 +201,7 @@ skl_dram_get_channels_info(struct drm_i915_private *i915)
return -EINVAL;
}
- /*
-* If any of the channel is single rank channel, worst case output
-* will be same as if single rank memory, so consider single rank
-* memory.
-*/
- if (ch0.ranks == 1 || ch1.ranks == 1)
- dram_info->ranks = 1;
- else
- dram_info->ranks = max(ch0.ranks, ch1.ranks);
-
- if (dram_info->ranks == 0) {
+ if (ch0.ranks == 0 && ch1.ranks == 0) {
drm_info(>drm, "couldn't get memory rank information\n");
return -EINVAL;
}
@@ -269,16 +259,12 @@ skl_get_dram_info(struct drm_i915_private *i915)
mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
- dram_info->bandwidth_kbps = dram_info->num_channels *
- mem_freq_khz * 8;
-
- if (dram_info->bandwidth_kbps == 0) {
+ if (dram_info->num_channels * mem_freq_khz == 0) {
drm_info(>drm,
"Couldn't get system memory bandwidth\n");
return -EINVAL;
}
- dram_info->valid = true;
return 0;
}
@@ -365,7 +351,7 @@ static int bxt_get_dram_info(struct drm_i915_private *i915)
struct dram_info *dram_info = >dram_info;
u32 dram_channels;
u32 mem_freq_khz, val;
- u8 num_active_channels;
+ u8 num_active_channels, valid_ranks = 0;
int i;
val = intel_uncore_read(>uncore, BXT_P_CR_MC_BIOS_REQ_0_0_0);
@@ -375,10 +361,7 @@ static int bxt_get_dram_info(struct drm_i915_private *i915)
dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
num_active_channels = hweight32(dram_channels);
- /* Each active bit represents 4-byte channel */
- dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
-
- if (dram_info->bandwidth_kbps == 0) {
+ if (mem_freq_khz * num_active_channels == 0) {
drm_info(>drm,
"Couldn't get system memory bandwidth\n");
return -EINVAL;
@@ -410,27 +393,18 @@ static int bxt_get_dram_info(struct drm_i915_private
*i915)
dimm.size, dimm.width, dimm.ranks,
intel_dram_type_str(type));
- /*
-* If any of the channel is single rank channel,
-* worst case output will be same as if single rank
-* memory, so consider single rank memory.
-*/
- if (dram_info->ranks == 0)
- dram_info->ranks = dimm.ranks;
- else if (dimm.ranks == 1)
- dram_info->ranks = 1;
+ if (valid_ranks == 0)
+ valid_ranks = dimm.ranks;
if (type != INTEL_DRAM_UNKNOWN)
dram_info->type = type;
}
- if (dram_info->type == INTEL_DRAM_UNKNOWN || dram_info->ranks == 0) {
+ if (dram_info->type == INTEL_DRAM_UNKNOWN || valid_ranks == 0) {
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915: Skip vswing programming for TBT
== Series Details ==
Series: series starting with [1/5] drm/i915: Skip vswing programming for TBT
URL : https://patchwork.freedesktop.org/series/86402/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9694 -> Patchwork_19529
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19529 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19529, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19529/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19529:
### IGT changes ###
Possible regressions
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9694/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19529/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
Known issues
Here are the changes found in Patchwork_19529 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_linear_blits@basic:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9694/fi-tgl-y/igt@gem_linear_bl...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19529/fi-tgl-y/igt@gem_linear_bl...@basic.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-tgl-y: [PASS][5] -> [DMESG-FAIL][6] ([i915#2601])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9694/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19529/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
Possible fixes
* igt@gem_ringfill@basic-all:
- fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9694/fi-tgl-y/igt@gem_ringf...@basic-all.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19529/fi-tgl-y/igt@gem_ringf...@basic-all.html
* igt@i915_module_load@reload:
- fi-kbl-7500u: [DMESG-WARN][9] ([i915#2605]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9694/fi-kbl-7500u/igt@i915_module_l...@reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19529/fi-kbl-7500u/igt@i915_module_l...@reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601
[i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
[i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
[i915#3014]: https://gitlab.freedesktop.org/drm/intel/issues/3014
[i915#3015]: https://gitlab.freedesktop.org/drm/intel/issues/3015
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (44 -> 39)
--
Missing(5): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9694 -> Patchwork_19529
CI-20190529: 20190529
CI_DRM_9694: 5f3b05c083d511d2d9e2b6a27eaec6a7cd1df842 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5976: 1d3b7bde430dd7ea946682d1df46a483b6a93272 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19529: 36dc93369a4c35ad575002de267bae94ec22154d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
36dc93369a4c drm/i915: Don't check tc_mode unless dealing with a TC PHY
a0d3bbb9ac43 drm/i915: Move HDMI vswing programming to the right place
eedf3240b968 drm/i915: Power up combo PHY lanes for for HDMI as well
bd419ba25d70 drm/i915: Extract intel_ddi_power_up_lanes()
d44689e35b85 drm/i915: Skip vswing programming for TBT
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19529/index.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 18/63] drm/i915: Populate logical context during first pin.
This allows us to remove pin_map from state allocation, which saves
us a few retry loops. We won't need this until first pin, anyway.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
.../drm/i915/gt/intel_execlists_submission.c | 26 ---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index e20ab2eab3a8..13e1876a6b6c 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2456,11 +2456,31 @@ static void execlists_submit_request(struct
i915_request *request)
spin_unlock_irqrestore(>active.lock, flags);
}
+static int
+__execlists_context_pre_pin(struct intel_context *ce,
+ struct intel_engine_cs *engine,
+ struct i915_gem_ww_ctx *ww, void **vaddr)
+{
+ int err;
+
+ err = lrc_pre_pin(ce, engine, ww, vaddr);
+ if (err)
+ return err;
+
+ if (!__test_and_set_bit(CONTEXT_INIT_BIT, >flags)) {
+ lrc_init_state(ce, engine, *vaddr);
+
+__i915_gem_object_flush_map(ce->state->obj, 0,
engine->context_size);
+ }
+
+ return 0;
+}
+
static int execlists_context_pre_pin(struct intel_context *ce,
struct i915_gem_ww_ctx *ww,
void **vaddr)
{
- return lrc_pre_pin(ce, ce->engine, ww, vaddr);
+ return __execlists_context_pre_pin(ce, ce->engine, ww, vaddr);
}
static int execlists_context_pin(struct intel_context *ce, void *vaddr)
@@ -3366,8 +3386,8 @@ static int virtual_context_pre_pin(struct intel_context
*ce,
{
struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
- /* Note: we must use a real engine class for setting up reg state */
- return lrc_pre_pin(ce, ve->siblings[0], ww, vaddr);
+/* Note: we must use a real engine class for setting up reg state */
+ return __execlists_context_pre_pin(ce, ve->siblings[0], ww, vaddr);
}
static int virtual_context_pin(struct intel_context *ce, void *vaddr)
--
2.30.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 60/63] drm/i915/selftests: Prepare gtt tests for obj->mm.lock removal
We need to lock the global gtt dma_resv, use i915_vm_lock_objects
to handle this correctly. Add ww handling for this where required.
Add the object lock around unpin/put pages, and use the unlocked
versions of pin_pages and pin_map where required.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 92 ++-
1 file changed, 67 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 5be6dcf4357e..2e4f06eaacc1 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -130,7 +130,7 @@ fake_dma_object(struct drm_i915_private *i915, u64 size)
obj->cache_level = I915_CACHE_NONE;
/* Preallocate the "backing storage" */
- if (i915_gem_object_pin_pages(obj))
+ if (i915_gem_object_pin_pages_unlocked(obj))
goto err_obj;
i915_gem_object_unpin_pages(obj);
@@ -146,6 +146,7 @@ static int igt_ppgtt_alloc(void *arg)
{
struct drm_i915_private *dev_priv = arg;
struct i915_ppgtt *ppgtt;
+ struct i915_gem_ww_ctx ww;
u64 size, last, limit;
int err = 0;
@@ -171,6 +172,12 @@ static int igt_ppgtt_alloc(void *arg)
limit = totalram_pages() << PAGE_SHIFT;
limit = min(ppgtt->vm.total, limit);
+ i915_gem_ww_ctx_init(, false);
+retry:
+ err = i915_vm_lock_objects(>vm, );
+ if (err)
+ goto err_ppgtt_cleanup;
+
/* Check we can allocate the entire range */
for (size = 4096; size <= limit; size <<= 2) {
struct i915_vm_pt_stash stash = {};
@@ -215,6 +222,13 @@ static int igt_ppgtt_alloc(void *arg)
}
err_ppgtt_cleanup:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+
i915_vm_put(>vm);
return err;
}
@@ -276,7 +290,7 @@ static int lowlevel_hole(struct i915_address_space *vm,
GEM_BUG_ON(obj->base.size != BIT_ULL(size));
- if (i915_gem_object_pin_pages(obj)) {
+ if (i915_gem_object_pin_pages_unlocked(obj)) {
i915_gem_object_put(obj);
kfree(order);
break;
@@ -297,20 +311,36 @@ static int lowlevel_hole(struct i915_address_space *vm,
if (vm->allocate_va_range) {
struct i915_vm_pt_stash stash = {};
+ struct i915_gem_ww_ctx ww;
+ int err;
+
+ i915_gem_ww_ctx_init(, false);
+retry:
+ err = i915_vm_lock_objects(vm, );
+ if (err)
+ goto alloc_vm_end;
+ err = -ENOMEM;
if (i915_vm_alloc_pt_stash(vm, ,
BIT_ULL(size)))
- break;
-
- if (i915_vm_pin_pt_stash(vm, )) {
- i915_vm_free_pt_stash(vm, );
- break;
- }
+ goto alloc_vm_end;
- vm->allocate_va_range(vm, ,
- addr, BIT_ULL(size));
+ err = i915_vm_pin_pt_stash(vm, );
+ if (!err)
+ vm->allocate_va_range(vm, ,
+ addr,
BIT_ULL(size));
i915_vm_free_pt_stash(vm, );
+alloc_vm_end:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+
+ if (err)
+ break;
}
mock_vma->pages = obj->mm.pages;
@@ -1166,7 +1196,7 @@ static int igt_ggtt_page(void *arg)
if (IS_ERR(obj))
return PTR_ERR(obj);
- err = i915_gem_object_pin_pages(obj);
+ err = i915_gem_object_pin_pages_unlocked(obj);
if (err)
goto out_free;
@@ -1333,7 +1363,7 @@ static int igt_gtt_reserve(void *arg)
goto out;
}
- err = i915_gem_object_pin_pages(obj);
+ err = i915_gem_object_pin_pages_unlocked(obj);
if (err)
[Intel-gfx] [PATCH v7 02/63] drm/i915: Pin timeline map after first timeline pin, v3.
We're starting to require the reservation lock for pinning,
so wait until we have that.
Update the selftests to handle this correctly, and ensure pin is
called in live_hwsp_rollover_user() and mock_hwsp_freelist().
Changes since v1:
- Fix NULL + XX arithmatic, use casts. (kbuild)
Changes since v2:
- Clear entire cacheline when pinning.
Signed-off-by: Maarten Lankhorst
Reported-by: kernel test robot
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/intel_timeline.c| 40 +
drivers/gpu/drm/i915/gt/intel_timeline.h| 2 +
drivers/gpu/drm/i915/gt/mock_engine.c | 22 ++-
drivers/gpu/drm/i915/gt/selftest_timeline.c | 63 +++--
drivers/gpu/drm/i915/i915_selftest.h| 2 +
5 files changed, 84 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index efe2030cfe5e..032e1d1b4c5e 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -52,14 +52,29 @@ static int __timeline_active(struct i915_active *active)
return 0;
}
+I915_SELFTEST_EXPORT int
+intel_timeline_pin_map(struct intel_timeline *timeline)
+{
+ struct drm_i915_gem_object *obj = timeline->hwsp_ggtt->obj;
+ u32 ofs = offset_in_page(timeline->hwsp_offset);
+ void *vaddr;
+
+ vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(vaddr))
+ return PTR_ERR(vaddr);
+
+ timeline->hwsp_map = vaddr;
+ timeline->hwsp_seqno = memset(vaddr + ofs, 0, CACHELINE_BYTES);
+ clflush(vaddr + ofs);
+
+ return 0;
+}
+
static int intel_timeline_init(struct intel_timeline *timeline,
struct intel_gt *gt,
struct i915_vma *hwsp,
unsigned int offset)
{
- void *vaddr;
- u32 *seqno;
-
kref_init(>kref);
atomic_set(>pin_count, 0);
@@ -76,14 +91,8 @@ static int intel_timeline_init(struct intel_timeline
*timeline,
timeline->hwsp_ggtt = hwsp;
}
- vaddr = i915_gem_object_pin_map(hwsp->obj, I915_MAP_WB);
- if (IS_ERR(vaddr))
- return PTR_ERR(vaddr);
-
- timeline->hwsp_map = vaddr;
- seqno = vaddr + timeline->hwsp_offset;
- WRITE_ONCE(*seqno, 0);
- timeline->hwsp_seqno = seqno;
+ timeline->hwsp_map = NULL;
+ timeline->hwsp_seqno = (void *)(long)timeline->hwsp_offset;
GEM_BUG_ON(timeline->hwsp_offset >= hwsp->size);
@@ -113,7 +122,8 @@ static void intel_timeline_fini(struct rcu_head *rcu)
struct intel_timeline *timeline =
container_of(rcu, struct intel_timeline, rcu);
- i915_gem_object_unpin_map(timeline->hwsp_ggtt->obj);
+ if (timeline->hwsp_map)
+ i915_gem_object_unpin_map(timeline->hwsp_ggtt->obj);
i915_vma_put(timeline->hwsp_ggtt);
i915_active_fini(>active);
@@ -173,6 +183,12 @@ int intel_timeline_pin(struct intel_timeline *tl, struct
i915_gem_ww_ctx *ww)
if (atomic_add_unless(>pin_count, 1, 0))
return 0;
+ if (!tl->hwsp_map) {
+ err = intel_timeline_pin_map(tl);
+ if (err)
+ return err;
+ }
+
err = i915_ggtt_pin(tl->hwsp_ggtt, ww, 0, PIN_HIGH);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h
b/drivers/gpu/drm/i915/gt/intel_timeline.h
index b1f81d947f8d..57308c4d664a 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
@@ -98,4 +98,6 @@ intel_timeline_is_last(const struct intel_timeline *tl,
return list_is_last_rcu(>link, >requests);
}
+I915_SELFTEST_DECLARE(int intel_timeline_pin_map(struct intel_timeline *tl));
+
#endif
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c
b/drivers/gpu/drm/i915/gt/mock_engine.c
index df7c1b1acc32..5097b5548ca9 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -13,9 +13,20 @@
#include "mock_engine.h"
#include "selftests/mock_request.h"
-static void mock_timeline_pin(struct intel_timeline *tl)
+static int mock_timeline_pin(struct intel_timeline *tl)
{
+ int err;
+
+ if (WARN_ON(!i915_gem_object_trylock(tl->hwsp_ggtt->obj)))
+ return -EBUSY;
+
+ err = intel_timeline_pin_map(tl);
+ i915_gem_object_unlock(tl->hwsp_ggtt->obj);
+ if (err)
+ return err;
+
atomic_inc(>pin_count);
+ return 0;
}
static void mock_timeline_unpin(struct intel_timeline *tl)
@@ -133,6 +144,8 @@ static void mock_context_destroy(struct kref *ref)
static int mock_context_alloc(struct intel_context *ce)
{
+ int err;
+
ce->ring = mock_ring(ce->engine);
if (!ce->ring)
return -ENOMEM;
@@ -143,7 +156,12 @@ static int mock_context_alloc(struct intel_context
[Intel-gfx] [PATCH v7 46/63] drm/i915/selftests: Prepare execbuf tests for obj->mm.lock removal.
Also quite simple, a single call needs to use the unlocked version.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c
index e1d50a5a1477..4df505e4c53a 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c
@@ -116,7 +116,7 @@ static int igt_gpu_reloc(void *arg)
if (IS_ERR(scratch))
return PTR_ERR(scratch);
- map = i915_gem_object_pin_map(scratch, I915_MAP_WC);
+ map = i915_gem_object_pin_map_unlocked(scratch, I915_MAP_WC);
if (IS_ERR(map)) {
err = PTR_ERR(map);
goto err_scratch;
--
2.30.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 20/63] drm/i915: Handle ww locking in init_status_page
Try to pin to ggtt first, and use a full ww loop to handle
eviction correctly.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 37 +++
1 file changed, 24 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 73d84e08422a..34490ed35cce 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -600,6 +600,7 @@ static void cleanup_status_page(struct intel_engine_cs
*engine)
}
static int pin_ggtt_status_page(struct intel_engine_cs *engine,
+ struct i915_gem_ww_ctx *ww,
struct i915_vma *vma)
{
unsigned int flags;
@@ -620,12 +621,13 @@ static int pin_ggtt_status_page(struct intel_engine_cs
*engine,
else
flags = PIN_HIGH;
- return i915_ggtt_pin(vma, NULL, 0, flags);
+ return i915_ggtt_pin(vma, ww, 0, flags);
}
static int init_status_page(struct intel_engine_cs *engine)
{
struct drm_i915_gem_object *obj;
+ struct i915_gem_ww_ctx ww;
struct i915_vma *vma;
void *vaddr;
int ret;
@@ -651,30 +653,39 @@ static int init_status_page(struct intel_engine_cs
*engine)
vma = i915_vma_instance(obj, >gt->ggtt->vm, NULL);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
- goto err;
+ goto err_put;
}
+ i915_gem_ww_ctx_init(, true);
+retry:
+ ret = i915_gem_object_lock(obj, );
+ if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915))
+ ret = pin_ggtt_status_page(engine, , vma);
+ if (ret)
+ goto err;
+
vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
if (IS_ERR(vaddr)) {
ret = PTR_ERR(vaddr);
- goto err;
+ goto err_unpin;
}
engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
engine->status_page.vma = vma;
- if (!HWS_NEEDS_PHYSICAL(engine->i915)) {
- ret = pin_ggtt_status_page(engine, vma);
- if (ret)
- goto err_unpin;
- }
-
- return 0;
-
err_unpin:
- i915_gem_object_unpin_map(obj);
+ if (ret)
+ i915_vma_unpin(vma);
err:
- i915_gem_object_put(obj);
+ if (ret == -EDEADLK) {
+ ret = i915_gem_ww_ctx_backoff();
+ if (!ret)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+err_put:
+ if (ret)
+ i915_gem_object_put(obj);
return ret;
}
--
2.30.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 19/63] drm/i915: Make ring submission compatible with obj->mm.lock removal, v2.
We map the initial context during first pin.
This allows us to remove pin_map from state allocation, which saves
us a few retry loops. We won't need this until first pin anyway.
intel_ring_submission_setup() is also reworked slightly to do all
pinning in a single ww loop.
Changes since v1:
- Handle -EDEADLK backoff in intel_ring_submission_setup() better.
- Handle smatch errors reported by Dan and testbot.
Signed-off-by: Maarten Lankhorst
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Reviewed-by: Thomas Hellström
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 184 +++---
1 file changed, 118 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 8b7cc637c432..5a128b8b55e4 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -435,6 +435,26 @@ static void ring_context_destroy(struct kref *ref)
intel_context_free(ce);
}
+static int ring_context_init_default_state(struct intel_context *ce,
+ struct i915_gem_ww_ctx *ww)
+{
+ struct drm_i915_gem_object *obj = ce->state->obj;
+ void *vaddr;
+
+ vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(vaddr))
+ return PTR_ERR(vaddr);
+
+ shmem_read(ce->engine->default_state, 0,
+ vaddr, ce->engine->context_size);
+
+ i915_gem_object_flush_map(obj);
+ __i915_gem_object_release_map(obj);
+
+ __set_bit(CONTEXT_VALID_BIT, >flags);
+ return 0;
+}
+
static int ring_context_pre_pin(struct intel_context *ce,
struct i915_gem_ww_ctx *ww,
void **unused)
@@ -442,6 +462,13 @@ static int ring_context_pre_pin(struct intel_context *ce,
struct i915_address_space *vm;
int err = 0;
+ if (ce->engine->default_state &&
+ !test_bit(CONTEXT_VALID_BIT, >flags)) {
+ err = ring_context_init_default_state(ce, ww);
+ if (err)
+ return err;
+ }
+
vm = vm_alias(ce->vm);
if (vm)
err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)), ww);
@@ -497,22 +524,6 @@ alloc_context_vma(struct intel_engine_cs *engine)
if (IS_IVYBRIDGE(i915))
i915_gem_object_set_cache_coherency(obj, I915_CACHE_L3_LLC);
- if (engine->default_state) {
- void *vaddr;
-
- vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
- if (IS_ERR(vaddr)) {
- err = PTR_ERR(vaddr);
- goto err_obj;
- }
-
- shmem_read(engine->default_state, 0,
- vaddr, engine->context_size);
-
- i915_gem_object_flush_map(obj);
- __i915_gem_object_release_map(obj);
- }
-
vma = i915_vma_instance(obj, >gt->ggtt->vm, NULL);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
@@ -544,8 +555,6 @@ static int ring_context_alloc(struct intel_context *ce)
return PTR_ERR(vma);
ce->state = vma;
- if (engine->default_state)
- __set_bit(CONTEXT_VALID_BIT, >flags);
}
return 0;
@@ -1147,37 +1156,15 @@ static int gen7_ctx_switch_bb_setup(struct
intel_engine_cs * const engine,
return gen7_setup_clear_gpr_bb(engine, vma);
}
-static int gen7_ctx_switch_bb_init(struct intel_engine_cs *engine)
+static int gen7_ctx_switch_bb_init(struct intel_engine_cs *engine,
+ struct i915_gem_ww_ctx *ww,
+ struct i915_vma *vma)
{
- struct drm_i915_gem_object *obj;
- struct i915_vma *vma;
- int size;
int err;
- size = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */);
- if (size <= 0)
- return size;
-
- size = ALIGN(size, PAGE_SIZE);
- obj = i915_gem_object_create_internal(engine->i915, size);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
-
- vma = i915_vma_instance(obj, engine->gt->vm, NULL);
- if (IS_ERR(vma)) {
- err = PTR_ERR(vma);
- goto err_obj;
- }
-
- vma->private = intel_context_create(engine); /* dummy residuals */
- if (IS_ERR(vma->private)) {
- err = PTR_ERR(vma->private);
- goto err_obj;
- }
-
- err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH);
+ err = i915_vma_pin_ww(vma, ww, 0, 0, PIN_USER | PIN_HIGH);
if (err)
- goto err_private;
+ return err;
err = i915_vma_sync(vma);
if (err)
@@ -1192,17 +1179,53 @@ static int gen7_ctx_switch_bb_init(struct
intel_engine_cs *engine)
err_unpin:
i915_vma_unpin(vma);
-err_private:
-
[Intel-gfx] [PATCH v7 23/63] drm/i915: Add object locking to vm_fault_cpu
Take a simple lock so we hold ww around (un)pin_pages as needed. Signed-off-by: Maarten Lankhorst Reviewed-by: Thomas Hellström --- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c index c0034d811e50..163208a6260d 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c @@ -246,6 +246,9 @@ static vm_fault_t vm_fault_cpu(struct vm_fault *vmf) area->vm_flags & VM_WRITE)) return VM_FAULT_SIGBUS; + if (i915_gem_object_lock_interruptible(obj, NULL)) + return VM_FAULT_NOPAGE; + err = i915_gem_object_pin_pages(obj); if (err) goto out; @@ -269,6 +272,7 @@ static vm_fault_t vm_fault_cpu(struct vm_fault *vmf) i915_gem_object_unpin_pages(obj); out: + i915_gem_object_unlock(obj); return i915_error_to_vmf_fault(err); } -- 2.30.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 51/63] drm/i915/selftests: Prepare context selftest for obj->mm.lock removal
Only needs to convert a single call to the unlocked version.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/selftest_context.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c
b/drivers/gpu/drm/i915/gt/selftest_context.c
index a02fd70644e2..b9bdd1d23243 100644
--- a/drivers/gpu/drm/i915/gt/selftest_context.c
+++ b/drivers/gpu/drm/i915/gt/selftest_context.c
@@ -87,8 +87,8 @@ static int __live_context_size(struct intel_engine_cs *engine)
if (err)
goto err;
- vaddr = i915_gem_object_pin_map(ce->state->obj,
- i915_coherent_map_type(engine->i915));
+ vaddr = i915_gem_object_pin_map_unlocked(ce->state->obj,
+
i915_coherent_map_type(engine->i915));
if (IS_ERR(vaddr)) {
err = PTR_ERR(vaddr);
intel_context_unpin(ce);
--
2.30.0
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[Intel-gfx] [PATCH v7 49/63] drm/i915/selftests: Prepare object blit tests for obj->mm.lock removal.
Use some unlocked versions where we're not holding the ww lock.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
index c4c04fb97d14..8c335d1a8406 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
@@ -262,7 +262,7 @@ static int igt_fill_blt_thread(void *arg)
goto err_flush;
}
- vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
if (IS_ERR(vaddr)) {
err = PTR_ERR(vaddr);
goto err_put;
@@ -380,7 +380,7 @@ static int igt_copy_blt_thread(void *arg)
goto err_flush;
}
- vaddr = i915_gem_object_pin_map(src, I915_MAP_WB);
+ vaddr = i915_gem_object_pin_map_unlocked(src, I915_MAP_WB);
if (IS_ERR(vaddr)) {
err = PTR_ERR(vaddr);
goto err_put_src;
@@ -400,7 +400,7 @@ static int igt_copy_blt_thread(void *arg)
goto err_put_src;
}
- vaddr = i915_gem_object_pin_map(dst, I915_MAP_WB);
+ vaddr = i915_gem_object_pin_map_unlocked(dst, I915_MAP_WB);
if (IS_ERR(vaddr)) {
err = PTR_ERR(vaddr);
goto err_put_dst;
--
2.30.0
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[Intel-gfx] [PATCH v7 32/63] drm/i915: Prepare for obj->mm.lock removal, v2.
From: Thomas Hellström
Stolen objects need to lock, and we may call put_pages when
refcount drops to 0, ensure all calls are handled correctly.
Changes since v1:
- Rebase on top of upstream changes.
Idea-from: Thomas Hellström
Signed-off-by: Maarten Lankhorst
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_object.h | 14 ++
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 14 --
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 12 +++-
3 files changed, 33 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 9d51164bf6f2..919dd668944c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -144,6 +144,20 @@ i915_gem_object_put(struct drm_i915_gem_object *obj)
#define assert_object_held(obj) dma_resv_assert_held((obj)->base.resv)
+/*
+ * If more than one potential simultaneous locker, assert held.
+ */
+static inline void assert_object_held_shared(struct drm_i915_gem_object *obj)
+{
+ /*
+* Note mm list lookup is protected by
+* kref_get_unless_zero().
+*/
+ if (IS_ENABLED(CONFIG_LOCKDEP) &&
+ kref_read(>base.refcount) > 0)
+ lockdep_assert_held(>mm.lock);
+}
+
static inline int __i915_gem_object_lock(struct drm_i915_gem_object *obj,
struct i915_gem_ww_ctx *ww,
bool intr)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index a24617af3c93..2d0065fa6e80 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -19,7 +19,7 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj,
bool shrinkable;
int i;
- lockdep_assert_held(>mm.lock);
+ assert_object_held_shared(obj);
if (i915_gem_object_is_volatile(obj))
obj->mm.madv = I915_MADV_DONTNEED;
@@ -70,6 +70,7 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj,
struct list_head *list;
unsigned long flags;
+ lockdep_assert_held(>mm.lock);
spin_lock_irqsave(>mm.obj_lock, flags);
i915->mm.shrink_count++;
@@ -91,6 +92,8 @@ int i915_gem_object_get_pages(struct drm_i915_gem_object
*obj)
struct drm_i915_private *i915 = to_i915(obj->base.dev);
int err;
+ assert_object_held_shared(obj);
+
if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
drm_dbg(>drm,
"Attempting to obtain a purgeable object\n");
@@ -118,6 +121,8 @@ int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj)
if (err)
return err;
+ assert_object_held_shared(obj);
+
if (unlikely(!i915_gem_object_has_pages(obj))) {
GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
@@ -145,7 +150,7 @@ void i915_gem_object_truncate(struct drm_i915_gem_object
*obj)
/* Try to discard unwanted pages */
void i915_gem_object_writeback(struct drm_i915_gem_object *obj)
{
- lockdep_assert_held(>mm.lock);
+ assert_object_held_shared(obj);
GEM_BUG_ON(i915_gem_object_has_pages(obj));
if (obj->ops->writeback)
@@ -176,6 +181,8 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object
*obj)
{
struct sg_table *pages;
+ assert_object_held_shared(obj);
+
pages = fetch_and_zero(>mm.pages);
if (IS_ERR_OR_NULL(pages))
return pages;
@@ -203,6 +210,9 @@ int __i915_gem_object_put_pages_locked(struct
drm_i915_gem_object *obj)
if (i915_gem_object_has_pinned_pages(obj))
return -EBUSY;
+ /* May be called by shrinker from within get_pages() (on another bo) */
+ assert_object_held_shared(obj);
+
i915_gem_object_release_mmap_offset(obj);
/*
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 51c2ef6bd8ac..2f2c7f6242dc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -637,13 +637,15 @@ static int __i915_gem_object_create_stolen(struct
intel_memory_region *mem,
cache_level = HAS_LLC(mem->i915) ? I915_CACHE_LLC : I915_CACHE_NONE;
i915_gem_object_set_cache_coherency(obj, cache_level);
- err = i915_gem_object_pin_pages(obj);
- if (err)
- return err;
+ if (WARN_ON(!i915_gem_object_trylock(obj)))
+ return -EBUSY;
- i915_gem_object_init_memory_region(obj, mem);
+ err = i915_gem_object_pin_pages(obj);
+ if (!err)
+ i915_gem_object_init_memory_region(obj, mem);
+ i915_gem_object_unlock(obj);
- return 0;
+ return err;
}
static int
[Intel-gfx] [PATCH v7 24/63] drm/i915: Move pinning to inside engine_wa_list_verify()
This should be done as part of the ww loop, in order to remove a
i915_vma_pin that needs ww held.
Now only i915_ggtt_pin() callers remaining.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/intel_gtt.c| 14 +-
drivers/gpu/drm/i915/gt/intel_gtt.h| 3 +++
drivers/gpu/drm/i915/gt/intel_workarounds.c| 10 --
drivers/gpu/drm/i915/gt/selftest_execlists.c | 5 +++--
drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_mocs.c| 3 ++-
drivers/gpu/drm/i915/gt/selftest_workarounds.c | 6 +++---
7 files changed, 33 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 04aa6601e984..444d9bacfafd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -427,7 +427,6 @@ __vm_create_scratch_for_read(struct i915_address_space *vm,
unsigned long size)
{
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
- int err;
obj = i915_gem_object_create_internal(vm->i915, PAGE_ALIGN(size));
if (IS_ERR(obj))
@@ -441,6 +440,19 @@ __vm_create_scratch_for_read(struct i915_address_space
*vm, unsigned long size)
return vma;
}
+ return vma;
+}
+
+struct i915_vma *
+__vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned
long size)
+{
+ struct i915_vma *vma;
+ int err;
+
+ vma = __vm_create_scratch_for_read(vm, size);
+ if (IS_ERR(vma))
+ return vma;
+
err = i915_vma_pin(vma, 0, 0,
i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER);
if (err) {
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 29c10fde8ce3..af90090c3d18 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -576,6 +576,9 @@ void i915_vm_free_pt_stash(struct i915_address_space *vm,
struct i915_vma *
__vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long
size);
+struct i915_vma *
+__vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned
long size);
+
static inline struct sgt_dma {
struct scatterlist *sg;
dma_addr_t dma, max;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 71d1c19c868b..720508337dc5 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2203,10 +2203,15 @@ static int engine_wa_list_verify(struct intel_context
*ce,
if (err)
goto err_pm;
+ err = i915_vma_pin_ww(vma, , 0, 0,
+ i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER);
+ if (err)
+ goto err_unpin;
+
rq = i915_request_create(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
- goto err_unpin;
+ goto err_vma;
}
err = i915_request_await_object(rq, vma->obj, true);
@@ -2247,6 +2252,8 @@ static int engine_wa_list_verify(struct intel_context *ce,
err_rq:
i915_request_put(rq);
+err_vma:
+ i915_vma_unpin(vma);
err_unpin:
intel_context_unpin(ce);
err_pm:
@@ -2257,7 +2264,6 @@ static int engine_wa_list_verify(struct intel_context *ce,
}
i915_gem_ww_ctx_fini();
intel_engine_pm_put(ce->engine);
- i915_vma_unpin(vma);
i915_vma_put(vma);
return err;
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 5d7fac383add..9deed904371d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -4181,8 +4181,9 @@ static int preserved_virtual_engine(struct intel_gt *gt,
int err = 0;
u32 *cs;
- scratch = __vm_create_scratch_for_read([0]->gt->ggtt->vm,
- PAGE_SIZE);
+ scratch =
+ __vm_create_scratch_for_read_pinned([0]->gt->ggtt->vm,
+ PAGE_SIZE);
if (IS_ERR(scratch))
return PTR_ERR(scratch);
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 7bf34c439876..f74addad98ac 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -27,7 +27,7 @@
static struct i915_vma *create_scratch(struct intel_gt *gt)
{
- return __vm_create_scratch_for_read(>ggtt->vm, PAGE_SIZE);
+ return __vm_create_scratch_for_read_pinned(>ggtt->vm, PAGE_SIZE);
}
static bool is_active(struct i915_request *rq)
diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c
b/drivers/gpu/drm/i915/gt/selftest_mocs.c
index e6f6807487d4..5d2e515f4e2d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
[Intel-gfx] [PATCH v7 62/63] drm/i915: Keep userpointer bindings if seqcount is unchanged, v2.
Instead of force unbinding and rebinding every time, we try to check
if our notifier seqcount is still correct when pages are bound. This
way we only rebind userptr when we need to, and prevent stalls.
Changes since v1:
- Missing mutex_unlock, reported by kbuild.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Reviewed-by: Thomas Hellström
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 27 ++---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index cd6ef29a18a5..63c5c862a846 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -281,12 +281,33 @@ int i915_gem_object_userptr_submit_init(struct
drm_i915_gem_object *obj)
if (ret)
return ret;
- /* Make sure userptr is unbound for next attempt, so we don't use stale
pages. */
- ret = i915_gem_object_userptr_unbind(obj, false);
+ /* optimistically try to preserve current pages while unlocked */
+ if (i915_gem_object_has_pages(obj) &&
+ !mmu_interval_check_retry(>userptr.notifier,
+ obj->userptr.notifier_seq)) {
+ spin_lock(>mm.notifier_lock);
+ if (obj->userptr.pvec &&
+ !mmu_interval_read_retry(>userptr.notifier,
+obj->userptr.notifier_seq)) {
+ obj->userptr.page_ref++;
+
+ /* We can keep using the current binding, this is the
fastpath */
+ ret = 1;
+ }
+ spin_unlock(>mm.notifier_lock);
+ }
+
+ if (!ret) {
+ /* Make sure userptr is unbound for next attempt, so we don't
use stale pages. */
+ ret = i915_gem_object_userptr_unbind(obj, false);
+ }
i915_gem_object_unlock(obj);
- if (ret)
+ if (ret < 0)
return ret;
+ if (ret > 0)
+ return 0;
+
notifier_seq = mmu_interval_read_begin(>userptr.notifier);
pvec = kvmalloc_array(num_pages, sizeof(struct page *), GFP_KERNEL);
--
2.30.0
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[Intel-gfx] [PATCH v7 56/63] drm/i915/selftests: Prepare timeline tests for obj->mm.lock removal
We can no longer call intel_timeline_pin with a null argument,
so add a ww loop that locks the backing object.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 30 +
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c
b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index 31b492eb2982..d20f9301a459 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -37,6 +37,26 @@ static unsigned long hwsp_cacheline(struct intel_timeline
*tl)
return (address + offset_in_page(tl->hwsp_offset)) / CACHELINE_BYTES;
}
+static int selftest_tl_pin(struct intel_timeline *tl)
+{
+ struct i915_gem_ww_ctx ww;
+ int err;
+
+ i915_gem_ww_ctx_init(, false);
+retry:
+ err = i915_gem_object_lock(tl->hwsp_ggtt->obj, );
+ if (!err)
+ err = intel_timeline_pin(tl, );
+
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+ return err;
+}
+
#define CACHELINES_PER_PAGE (PAGE_SIZE / CACHELINE_BYTES)
struct mock_hwsp_freelist {
@@ -78,7 +98,7 @@ static int __mock_hwsp_timeline(struct mock_hwsp_freelist
*state,
if (IS_ERR(tl))
return PTR_ERR(tl);
- err = intel_timeline_pin(tl, NULL);
+ err = selftest_tl_pin(tl);
if (err) {
intel_timeline_put(tl);
return err;
@@ -464,7 +484,7 @@ checked_tl_write(struct intel_timeline *tl, struct
intel_engine_cs *engine, u32
struct i915_request *rq;
int err;
- err = intel_timeline_pin(tl, NULL);
+ err = selftest_tl_pin(tl);
if (err) {
rq = ERR_PTR(err);
goto out;
@@ -664,7 +684,7 @@ static int live_hwsp_wrap(void *arg)
if (!tl->has_initial_breadcrumb)
goto out_free;
- err = intel_timeline_pin(tl, NULL);
+ err = selftest_tl_pin(tl);
if (err)
goto out_free;
@@ -811,13 +831,13 @@ static int setup_watcher(struct hwsp_watcher *w, struct
intel_gt *gt)
if (IS_ERR(obj))
return PTR_ERR(obj);
- w->map = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ w->map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
if (IS_ERR(w->map)) {
i915_gem_object_put(obj);
return PTR_ERR(w->map);
}
- vma = i915_gem_object_ggtt_pin_ww(obj, NULL, NULL, 0, 0, 0);
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
if (IS_ERR(vma)) {
i915_gem_object_put(obj);
return PTR_ERR(vma);
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 08/63] drm/i915: Rework struct phys attachment handling
Instead of creating a separate object type, we make changes to
the shmem type, to clear struct page backing. This will allow us to
ensure we never run into a race when we exchange obj->ops with other
function pointers.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_object.h| 8 ++
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 102 +-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 22 +++-
.../drm/i915/gem/selftests/i915_gem_phys.c| 6 --
4 files changed, 78 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 32d62f5dc42e..c1d7de6ebd4f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -63,7 +63,15 @@ void __i915_gem_object_release_shmem(struct
drm_i915_gem_object *obj,
struct sg_table *pages,
bool needs_clflush);
+int i915_gem_object_pwrite_phys(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pwrite *args);
+int i915_gem_object_pread_phys(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pread *args);
+
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align);
+void i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
+ struct sg_table *pages);
+
void i915_gem_flush_free_objects(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index d1d9a824c46f..99ab42380826 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -76,6 +76,8 @@ static int i915_gem_object_get_pages_phys(struct
drm_i915_gem_object *obj)
intel_gt_chipset_flush(_i915(obj->base.dev)->gt);
+ /* We're no longer struct page backed */
+ obj->flags &= ~I915_BO_ALLOC_STRUCT_PAGE;
__i915_gem_object_set_pages(obj, st, sg->length);
return 0;
@@ -89,7 +91,7 @@ static int i915_gem_object_get_pages_phys(struct
drm_i915_gem_object *obj)
return -ENOMEM;
}
-static void
+void
i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
struct sg_table *pages)
{
@@ -134,9 +136,8 @@ i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj,
vaddr, dma);
}
-static int
-phys_pwrite(struct drm_i915_gem_object *obj,
- const struct drm_i915_gem_pwrite *args)
+int i915_gem_object_pwrite_phys(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pwrite *args)
{
void *vaddr = sg_page(obj->mm.pages->sgl) + args->offset;
char __user *user_data = u64_to_user_ptr(args->data_ptr);
@@ -165,9 +166,8 @@ phys_pwrite(struct drm_i915_gem_object *obj,
return 0;
}
-static int
-phys_pread(struct drm_i915_gem_object *obj,
- const struct drm_i915_gem_pread *args)
+int i915_gem_object_pread_phys(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pread *args)
{
void *vaddr = sg_page(obj->mm.pages->sgl) + args->offset;
char __user *user_data = u64_to_user_ptr(args->data_ptr);
@@ -186,86 +186,82 @@ phys_pread(struct drm_i915_gem_object *obj,
return 0;
}
-static void phys_release(struct drm_i915_gem_object *obj)
+static int i915_gem_object_shmem_to_phys(struct drm_i915_gem_object *obj)
{
- fput(obj->base.filp);
-}
+ struct sg_table *pages;
+ int err;
-static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
- .name = "i915_gem_object_phys",
- .get_pages = i915_gem_object_get_pages_phys,
- .put_pages = i915_gem_object_put_pages_phys,
+ pages = __i915_gem_object_unset_pages(obj);
+
+ err = i915_gem_object_get_pages_phys(obj);
+ if (err)
+ goto err_xfer;
- .pread = phys_pread,
- .pwrite = phys_pwrite,
+ /* Perma-pin (until release) the physical set of pages */
+ __i915_gem_object_pin_pages(obj);
- .release = phys_release,
-};
+ if (!IS_ERR_OR_NULL(pages))
+ i915_gem_shmem_ops.put_pages(obj, pages);
+
+ i915_gem_object_release_memory_region(obj);
+ return 0;
+
+err_xfer:
+ if (!IS_ERR_OR_NULL(pages)) {
+ unsigned int sg_page_sizes = i915_sg_page_sizes(pages->sgl);
+
+ __i915_gem_object_set_pages(obj, pages, sg_page_sizes);
+ }
+ return err;
+}
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align)
{
- struct sg_table *pages;
int err;
if (align > obj->base.size)
return -EINVAL;
- if (obj->ops == _gem_phys_ops)
- return 0;
-
if
[Intel-gfx] [PATCH v7 37/63] drm/i915: Add ww locking to dma-buf ops.
vmap is using pin_pages, but needs to use ww locking,
add pin_pages_unlocked to correctly lock the mapping.
Also add ww locking to begin/end cpu access.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 60 --
1 file changed, 33 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index 194d8bb9d718..ed6ca054eb63 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -82,7 +82,7 @@ static int i915_gem_dmabuf_vmap(struct dma_buf *dma_buf,
struct dma_buf_map *map
struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
void *vaddr;
- vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
if (IS_ERR(vaddr))
return PTR_ERR(vaddr);
@@ -123,42 +123,48 @@ static int i915_gem_begin_cpu_access(struct dma_buf
*dma_buf, enum dma_data_dire
{
struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
bool write = (direction == DMA_BIDIRECTIONAL || direction ==
DMA_TO_DEVICE);
+ struct i915_gem_ww_ctx ww;
int err;
- err = i915_gem_object_pin_pages(obj);
- if (err)
- return err;
-
- err = i915_gem_object_lock_interruptible(obj, NULL);
- if (err)
- goto out;
-
- err = i915_gem_object_set_to_cpu_domain(obj, write);
- i915_gem_object_unlock(obj);
-
-out:
- i915_gem_object_unpin_pages(obj);
+ i915_gem_ww_ctx_init(, true);
+retry:
+ err = i915_gem_object_lock(obj, );
+ if (!err)
+ err = i915_gem_object_pin_pages(obj);
+ if (!err) {
+ err = i915_gem_object_set_to_cpu_domain(obj, write);
+ i915_gem_object_unpin_pages(obj);
+ }
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
return err;
}
static int i915_gem_end_cpu_access(struct dma_buf *dma_buf, enum
dma_data_direction direction)
{
struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
+ struct i915_gem_ww_ctx ww;
int err;
- err = i915_gem_object_pin_pages(obj);
- if (err)
- return err;
-
- err = i915_gem_object_lock_interruptible(obj, NULL);
- if (err)
- goto out;
-
- err = i915_gem_object_set_to_gtt_domain(obj, false);
- i915_gem_object_unlock(obj);
-
-out:
- i915_gem_object_unpin_pages(obj);
+ i915_gem_ww_ctx_init(, true);
+retry:
+ err = i915_gem_object_lock(obj, );
+ if (!err)
+ err = i915_gem_object_pin_pages(obj);
+ if (!err) {
+ err = i915_gem_object_set_to_gtt_domain(obj, false);
+ i915_gem_object_unpin_pages(obj);
+ }
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
return err;
}
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 45/63] drm/i915/selftests: Prepare dma-buf tests for obj->mm.lock removal.
Use pin_pages_unlocked() where we don't have a lock.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
index b6d43880b0c1..dd74bc09ec88 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
@@ -194,7 +194,7 @@ static int igt_dmabuf_import_ownership(void *arg)
dma_buf_put(dmabuf);
- err = i915_gem_object_pin_pages(obj);
+ err = i915_gem_object_pin_pages_unlocked(obj);
if (err) {
pr_err("i915_gem_object_pin_pages failed with err=%d\n", err);
goto out_obj;
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 42/63] drm/i915/selftests: Prepare client blit for obj->mm.lock removal.
Straightforward conversion, just convert a bunch of calls to
unlocked versions.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 6a674a7994df..d36873885cc1 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -45,7 +45,7 @@ static int __igt_client_fill(struct intel_engine_cs *engine)
goto err_flush;
}
- vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
if (IS_ERR(vaddr)) {
err = PTR_ERR(vaddr);
goto err_put;
@@ -157,7 +157,7 @@ static int prepare_blit(const struct tiled_blits *t,
u32 src_pitch, dst_pitch;
u32 cmd, *cs;
- cs = i915_gem_object_pin_map(batch, I915_MAP_WC);
+ cs = i915_gem_object_pin_map_unlocked(batch, I915_MAP_WC);
if (IS_ERR(cs))
return PTR_ERR(cs);
@@ -377,7 +377,7 @@ static int verify_buffer(const struct tiled_blits *t,
y = i915_prandom_u32_max_state(t->height, prng);
p = y * t->width + x;
- vaddr = i915_gem_object_pin_map(buf->vma->obj, I915_MAP_WC);
+ vaddr = i915_gem_object_pin_map_unlocked(buf->vma->obj, I915_MAP_WC);
if (IS_ERR(vaddr))
return PTR_ERR(vaddr);
@@ -564,7 +564,7 @@ static int tiled_blits_prepare(struct tiled_blits *t,
int err;
int i;
- map = i915_gem_object_pin_map(t->scratch.vma->obj, I915_MAP_WC);
+ map = i915_gem_object_pin_map_unlocked(t->scratch.vma->obj,
I915_MAP_WC);
if (IS_ERR(map))
return PTR_ERR(map);
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 29/63] drm/i915: Defer pin calls in buffer pool until first use by caller.
We need to take the obj lock to pin pages, so wait until the callers
have done so, before making the object unshrinkable.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +
.../gpu/drm/i915/gem/i915_gem_object_blt.c| 6 +++
.../gpu/drm/i915/gt/intel_gt_buffer_pool.c| 47 +--
.../gpu/drm/i915/gt/intel_gt_buffer_pool.h| 5 ++
.../drm/i915/gt/intel_gt_buffer_pool_types.h | 1 +
5 files changed, 35 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 64d0e5fccece..97b0d1134b66 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1335,6 +1335,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
err = PTR_ERR(cmd);
goto err_pool;
}
+ intel_gt_buffer_pool_mark_used(pool);
memset32(cmd, 0, pool->obj->base.size / sizeof(u32));
@@ -2630,6 +2631,7 @@ static int eb_parse(struct i915_execbuffer *eb)
err = PTR_ERR(shadow);
goto err;
}
+ intel_gt_buffer_pool_mark_used(pool);
i915_gem_object_set_readonly(shadow->obj);
shadow->private = pool;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index d6dac21fce0b..df8e8c18c6c9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -55,6 +55,9 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context
*ce,
if (unlikely(err))
goto out_put;
+ /* we pinned the pool, mark it as such */
+ intel_gt_buffer_pool_mark_used(pool);
+
cmd = i915_gem_object_pin_map(pool->obj, pool->type);
if (IS_ERR(cmd)) {
err = PTR_ERR(cmd);
@@ -277,6 +280,9 @@ struct i915_vma *intel_emit_vma_copy_blt(struct
intel_context *ce,
if (unlikely(err))
goto out_put;
+ /* we pinned the pool, mark it as such */
+ intel_gt_buffer_pool_mark_used(pool);
+
cmd = i915_gem_object_pin_map(pool->obj, pool->type);
if (IS_ERR(cmd)) {
err = PTR_ERR(cmd);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
b/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
index 06d84cf09570..c59468107598 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
@@ -98,28 +98,6 @@ static void pool_free_work(struct work_struct *wrk)
round_jiffies_up_relative(HZ));
}
-static int pool_active(struct i915_active *ref)
-{
- struct intel_gt_buffer_pool_node *node =
- container_of(ref, typeof(*node), active);
- struct dma_resv *resv = node->obj->base.resv;
- int err;
-
- if (dma_resv_trylock(resv)) {
- dma_resv_add_excl_fence(resv, NULL);
- dma_resv_unlock(resv);
- }
-
- err = i915_gem_object_pin_pages(node->obj);
- if (err)
- return err;
-
- /* Hide this pinned object from the shrinker until retired */
- i915_gem_object_make_unshrinkable(node->obj);
-
- return 0;
-}
-
__i915_active_call
static void pool_retire(struct i915_active *ref)
{
@@ -129,10 +107,13 @@ static void pool_retire(struct i915_active *ref)
struct list_head *list = bucket_for_size(pool, node->obj->base.size);
unsigned long flags;
- i915_gem_object_unpin_pages(node->obj);
+ if (node->pinned) {
+ i915_gem_object_unpin_pages(node->obj);
- /* Return this object to the shrinker pool */
- i915_gem_object_make_purgeable(node->obj);
+ /* Return this object to the shrinker pool */
+ i915_gem_object_make_purgeable(node->obj);
+ node->pinned = false;
+ }
GEM_BUG_ON(node->age);
spin_lock_irqsave(>lock, flags);
@@ -144,6 +125,19 @@ static void pool_retire(struct i915_active *ref)
round_jiffies_up_relative(HZ));
}
+void intel_gt_buffer_pool_mark_used(struct intel_gt_buffer_pool_node *node)
+{
+ assert_object_held(node->obj);
+
+ if (node->pinned)
+ return;
+
+ __i915_gem_object_pin_pages(node->obj);
+ /* Hide this pinned object from the shrinker until retired */
+ i915_gem_object_make_unshrinkable(node->obj);
+ node->pinned = true;
+}
+
static struct intel_gt_buffer_pool_node *
node_create(struct intel_gt_buffer_pool *pool, size_t sz,
enum i915_map_type type)
@@ -159,7 +153,8 @@ node_create(struct intel_gt_buffer_pool *pool, size_t sz,
node->age = 0;
node->pool = pool;
- i915_active_init(>active, pool_active, pool_retire);
+ node->pinned = false;
+ i915_active_init(>active,
[Intel-gfx] [PATCH v7 33/63] drm/i915: Add igt_spinner_pin() to allow for ww locking around spinner.
By default, we assume that it's called inside igt_create_request
to keep existing selftests working, but allow for manual pinning
when passing a ww context.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/selftests/igt_spinner.c | 136 ---
drivers/gpu/drm/i915/selftests/igt_spinner.h | 5 +
2 files changed, 95 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c
b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index 83f6e5f31fb3..cfbbe415b57c 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -12,8 +12,6 @@
int igt_spinner_init(struct igt_spinner *spin, struct intel_gt *gt)
{
- unsigned int mode;
- void *vaddr;
int err;
memset(spin, 0, sizeof(*spin));
@@ -24,6 +22,7 @@ int igt_spinner_init(struct igt_spinner *spin, struct
intel_gt *gt)
err = PTR_ERR(spin->hws);
goto err;
}
+ i915_gem_object_set_cache_coherency(spin->hws, I915_CACHE_LLC);
spin->obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
if (IS_ERR(spin->obj)) {
@@ -31,34 +30,83 @@ int igt_spinner_init(struct igt_spinner *spin, struct
intel_gt *gt)
goto err_hws;
}
- i915_gem_object_set_cache_coherency(spin->hws, I915_CACHE_LLC);
- vaddr = i915_gem_object_pin_map(spin->hws, I915_MAP_WB);
- if (IS_ERR(vaddr)) {
- err = PTR_ERR(vaddr);
- goto err_obj;
- }
- spin->seqno = memset(vaddr, 0xff, PAGE_SIZE);
-
- mode = i915_coherent_map_type(gt->i915);
- vaddr = i915_gem_object_pin_map(spin->obj, mode);
- if (IS_ERR(vaddr)) {
- err = PTR_ERR(vaddr);
- goto err_unpin_hws;
- }
- spin->batch = vaddr;
-
return 0;
-err_unpin_hws:
- i915_gem_object_unpin_map(spin->hws);
-err_obj:
- i915_gem_object_put(spin->obj);
err_hws:
i915_gem_object_put(spin->hws);
err:
return err;
}
+static void *igt_spinner_pin_obj(struct intel_context *ce,
+struct i915_gem_ww_ctx *ww,
+struct drm_i915_gem_object *obj,
+unsigned int mode, struct i915_vma **vma)
+{
+ void *vaddr;
+ int ret;
+
+ *vma = i915_vma_instance(obj, ce->vm, NULL);
+ if (IS_ERR(*vma))
+ return ERR_CAST(*vma);
+
+ ret = i915_gem_object_lock(obj, ww);
+ if (ret)
+ return ERR_PTR(ret);
+
+ vaddr = i915_gem_object_pin_map(obj, mode);
+
+ if (!ww)
+ i915_gem_object_unlock(obj);
+
+ if (IS_ERR(vaddr))
+ return vaddr;
+
+ if (ww)
+ ret = i915_vma_pin_ww(*vma, ww, 0, 0, PIN_USER);
+ else
+ ret = i915_vma_pin(*vma, 0, 0, PIN_USER);
+
+ if (ret) {
+ i915_gem_object_unpin_map(obj);
+ return ERR_PTR(ret);
+ }
+
+ return vaddr;
+}
+
+int igt_spinner_pin(struct igt_spinner *spin,
+ struct intel_context *ce,
+ struct i915_gem_ww_ctx *ww)
+{
+ void *vaddr;
+
+ if (spin->ce && WARN_ON(spin->ce != ce))
+ return -ENODEV;
+ spin->ce = ce;
+
+ if (!spin->seqno) {
+ vaddr = igt_spinner_pin_obj(ce, ww, spin->hws, I915_MAP_WB,
>hws_vma);
+ if (IS_ERR(vaddr))
+ return PTR_ERR(vaddr);
+
+ spin->seqno = memset(vaddr, 0xff, PAGE_SIZE);
+ }
+
+ if (!spin->batch) {
+ unsigned int mode =
+ i915_coherent_map_type(spin->gt->i915);
+
+ vaddr = igt_spinner_pin_obj(ce, ww, spin->obj, mode,
>batch_vma);
+ if (IS_ERR(vaddr))
+ return PTR_ERR(vaddr);
+
+ spin->batch = vaddr;
+ }
+
+ return 0;
+}
+
static unsigned int seqno_offset(u64 fence)
{
return offset_in_page(sizeof(u32) * fence);
@@ -103,27 +151,18 @@ igt_spinner_create_request(struct igt_spinner *spin,
if (!intel_engine_can_store_dword(ce->engine))
return ERR_PTR(-ENODEV);
- vma = i915_vma_instance(spin->obj, ce->vm, NULL);
- if (IS_ERR(vma))
- return ERR_CAST(vma);
-
- hws = i915_vma_instance(spin->hws, ce->vm, NULL);
- if (IS_ERR(hws))
- return ERR_CAST(hws);
+ if (!spin->batch) {
+ err = igt_spinner_pin(spin, ce, NULL);
+ if (err)
+ return ERR_PTR(err);
+ }
- err = i915_vma_pin(vma, 0, 0, PIN_USER);
- if (err)
- return ERR_PTR(err);
-
- err = i915_vma_pin(hws, 0, 0, PIN_USER);
- if (err)
- goto unpin_vma;
+ hws = spin->hws_vma;
+ vma = spin->batch_vma;
rq =
[Intel-gfx] [PATCH v7 38/63] drm/i915: Add missing ww lock in intel_dsb_prepare.
Because of the long lifetime of the mapping, we cannot wrap this in a
simple limited ww lock. Just use the unlocked version of pin_map,
because we'll likely release the mapping a lot later, in a different
thread.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/display/intel_dsb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 566fa72427b3..857126822a88 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -293,7 +293,7 @@ void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
goto out;
}
- buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
+ buf = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WC);
if (IS_ERR(buf)) {
drm_err(>drm, "Command buffer creation failed\n");
i915_vma_unpin_and_release(, I915_VMA_RELEASE_MAP);
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 52/63] drm/i915/selftests: Prepare hangcheck for obj->mm.lock removal
Convert a few calls to use the unlocked versions.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index d6ce4075602c..746985971c3a 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -61,15 +61,15 @@ static int hang_init(struct hang *h, struct intel_gt *gt)
}
i915_gem_object_set_cache_coherency(h->hws, I915_CACHE_LLC);
- vaddr = i915_gem_object_pin_map(h->hws, I915_MAP_WB);
+ vaddr = i915_gem_object_pin_map_unlocked(h->hws, I915_MAP_WB);
if (IS_ERR(vaddr)) {
err = PTR_ERR(vaddr);
goto err_obj;
}
h->seqno = memset(vaddr, 0xff, PAGE_SIZE);
- vaddr = i915_gem_object_pin_map(h->obj,
- i915_coherent_map_type(gt->i915));
+ vaddr = i915_gem_object_pin_map_unlocked(h->obj,
+
i915_coherent_map_type(gt->i915));
if (IS_ERR(vaddr)) {
err = PTR_ERR(vaddr);
goto err_unpin_hws;
@@ -130,7 +130,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs
*engine)
return ERR_CAST(obj);
}
- vaddr = i915_gem_object_pin_map(obj, i915_coherent_map_type(gt->i915));
+ vaddr = i915_gem_object_pin_map_unlocked(obj,
i915_coherent_map_type(gt->i915));
if (IS_ERR(vaddr)) {
i915_gem_object_put(obj);
i915_vm_put(vm);
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 13/63] drm/i915: Reject more ioctls for userptr
There are a couple of ioctl's related to tiling and cache placement,
that make no sense for userptr, reject those:
- i915_gem_set_tiling_ioctl()
Tiling should always be linear for userptr. Changing placement will
fail with -ENXIO.
- i915_gem_set_caching_ioctl()
Userptr memory should always be cached. Changing caching mode will
fail with -ENXIO.
- i915_gem_set_domain_ioctl()
Changed to be equivalent to gem_wait, which is correct for the
cached linear userptr pointers. This is required because we
cannot grab a reference to the pages in the rework, but waiting
for idle will do the same.
This plus the previous changes have been tested against beignet
by using its own unit tests, and intel-video-compute by using
piglit's opencl tests.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
Cc: Jason Ekstrand
-- Still needs an ack from relevant userspace that it won't break, but should
be good.
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 12 ++--
drivers/gpu/drm/i915/gem/i915_gem_object.h | 6 ++
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 ++-
4 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d013b0fab128..3e24db8b9ad6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14172,7 +14172,7 @@ static int intel_user_framebuffer_create_handle(struct
drm_framebuffer *fb,
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
struct drm_i915_private *i915 = to_i915(obj->base.dev);
- if (obj->userptr.mm) {
+ if (i915_gem_object_is_userptr(obj)) {
drm_dbg(>drm,
"attempting to use a userptr for a framebuffer,
denied\n");
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 36f54cedaaeb..3078e9a09f70 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -335,7 +335,13 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev,
void *data,
* not allowed to be changed by userspace.
*/
if (i915_gem_object_is_proxy(obj)) {
- ret = -ENXIO;
+ /*
+* Silently allow cached for userptr; the vulkan driver
+* sets all objects to cached
+*/
+ if (!i915_gem_object_is_userptr(obj) ||
+ args->caching != I915_CACHING_CACHED)
+ ret = -ENXIO;
goto out;
}
@@ -533,7 +539,9 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void
*data,
* considered to be outside of any cache domain.
*/
if (i915_gem_object_is_proxy(obj)) {
- err = -ENXIO;
+ /* silently allow userptr to complete */
+ if (!i915_gem_object_is_userptr(obj))
+ err = -ENXIO;
goto out;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index e9a8ee96d64c..3f300a1d27ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -574,6 +574,12 @@ void __i915_gem_object_flush_frontbuffer(struct
drm_i915_gem_object *obj,
void __i915_gem_object_invalidate_frontbuffer(struct drm_i915_gem_object *obj,
enum fb_op_origin origin);
+static inline bool
+i915_gem_object_is_userptr(struct drm_i915_gem_object *obj)
+{
+ return obj->userptr.mm;
+}
+
static inline void
i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj,
enum fb_op_origin origin)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 0c30ca52dee3..c89cf911fb29 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -721,7 +721,8 @@ static const struct drm_i915_gem_object_ops
i915_gem_userptr_ops = {
.name = "i915_gem_object_userptr",
.flags = I915_GEM_OBJECT_IS_SHRINKABLE |
I915_GEM_OBJECT_NO_MMAP |
-I915_GEM_OBJECT_ASYNC_CANCEL,
+I915_GEM_OBJECT_ASYNC_CANCEL |
+I915_GEM_OBJECT_IS_PROXY,
.get_pages = i915_gem_userptr_get_pages,
.put_pages = i915_gem_userptr_put_pages,
.dmabuf_export = i915_gem_userptr_dmabuf_export,
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 44/63] drm/i915/selftests: Prepare context tests for obj->mm.lock removal.
Straightforward conversion, just convert a bunch of calls to
unlocked versions.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index d3f87dc4eda3..5fef592390cb 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1094,7 +1094,7 @@ __read_slice_count(struct intel_context *ce,
if (ret < 0)
return ret;
- buf = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ buf = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
if (IS_ERR(buf)) {
ret = PTR_ERR(buf);
return ret;
@@ -1511,7 +1511,7 @@ static int write_to_scratch(struct i915_gem_context *ctx,
if (IS_ERR(obj))
return PTR_ERR(obj);
- cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ cmd = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
if (IS_ERR(cmd)) {
err = PTR_ERR(cmd);
goto out;
@@ -1622,7 +1622,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
if (err)
goto out_vm;
- cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ cmd = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
if (IS_ERR(cmd)) {
err = PTR_ERR(cmd);
goto out;
@@ -1658,7 +1658,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
if (err)
goto out_vm;
- cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ cmd = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
if (IS_ERR(cmd)) {
err = PTR_ERR(cmd);
goto out;
@@ -1715,7 +1715,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
if (err)
goto out_vm;
- cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ cmd = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
if (IS_ERR(cmd)) {
err = PTR_ERR(cmd);
goto out_vm;
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 12/63] drm/i915: No longer allow exporting userptr through dma-buf
It doesn't make sense to export a memory address, we will prevent
allowing access this way to different address spaces when we
rework userptr handling, so best to explicitly disable it.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
Cc: Jason Ekstrand
-- Still needs an ack from relevant userspace that it won't break, but should
be good.
---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 5a19699c2d7e..0c30ca52dee3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -694,10 +694,9 @@ i915_gem_userptr_release(struct drm_i915_gem_object *obj)
static int
i915_gem_userptr_dmabuf_export(struct drm_i915_gem_object *obj)
{
- if (obj->userptr.mmu_object)
- return 0;
+ drm_dbg(obj->base.dev, "Exporting userptr no longer allowed\n");
- return i915_gem_userptr_init__mmu_notifier(obj, 0);
+ return -EINVAL;
}
static int
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 47/63] drm/i915/selftests: Prepare mman testcases for obj->mm.lock removal.
Ensure we hold the lock around put_pages, and use the unlocked wrappers
for pinning pages and mappings.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 44908c68e331..5cf6df49c333 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -322,7 +322,7 @@ static int igt_partial_tiling(void *arg)
if (IS_ERR(obj))
return PTR_ERR(obj);
- err = i915_gem_object_pin_pages(obj);
+ err = i915_gem_object_pin_pages_unlocked(obj);
if (err) {
pr_err("Failed to allocate %u pages (%lu total), err=%d\n",
nreal, obj->base.size / PAGE_SIZE, err);
@@ -459,7 +459,7 @@ static int igt_smoke_tiling(void *arg)
if (IS_ERR(obj))
return PTR_ERR(obj);
- err = i915_gem_object_pin_pages(obj);
+ err = i915_gem_object_pin_pages_unlocked(obj);
if (err) {
pr_err("Failed to allocate %u pages (%lu total), err=%d\n",
nreal, obj->base.size / PAGE_SIZE, err);
@@ -798,7 +798,7 @@ static int wc_set(struct drm_i915_gem_object *obj)
{
void *vaddr;
- vaddr = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
if (IS_ERR(vaddr))
return PTR_ERR(vaddr);
@@ -814,7 +814,7 @@ static int wc_check(struct drm_i915_gem_object *obj)
void *vaddr;
int err = 0;
- vaddr = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
if (IS_ERR(vaddr))
return PTR_ERR(vaddr);
@@ -1316,7 +1316,9 @@ static int __igt_mmap_revoke(struct drm_i915_private
*i915,
}
if (type != I915_MMAP_TYPE_GTT) {
+ i915_gem_object_lock(obj, NULL);
__i915_gem_object_put_pages(obj);
+ i915_gem_object_unlock(obj);
if (i915_gem_object_has_pages(obj)) {
pr_err("Failed to put-pages object!\n");
err = -EINVAL;
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 36/63] drm/i915: Lock ww in ucode objects correctly
In the ucode functions, the calls are done before userspace runs,
when debugging using debugfs, or when creating semi-permanent mappings;
we can safely use the unlocked versions that does the ww dance for us.
Because there is no pin_pages_unlocked yet, add it as convenience function.
This removes possible lockdep splats about missing resv lock for ucode.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_object.h | 2 ++
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 20
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
6 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 919dd668944c..0acdd08934da 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -392,6 +392,8 @@ i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
return __i915_gem_object_get_pages(obj);
}
+int i915_gem_object_pin_pages_unlocked(struct drm_i915_gem_object *obj);
+
static inline bool
i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 2d0065fa6e80..5b8af8f83ee3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -139,6 +139,26 @@ int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj)
return err;
}
+int i915_gem_object_pin_pages_unlocked(struct drm_i915_gem_object *obj)
+{
+ struct i915_gem_ww_ctx ww;
+ int err;
+
+ i915_gem_ww_ctx_init(, true);
+retry:
+ err = i915_gem_object_lock(obj, );
+ if (!err)
+ err = i915_gem_object_pin_pages(obj);
+
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+ return err;
+}
+
/* Immediately discard the backing storage */
void i915_gem_object_truncate(struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 4545e90e3bf1..78305b2ec89d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -682,7 +682,7 @@ int intel_guc_allocate_and_map_vma(struct intel_guc *guc,
u32 size,
if (IS_ERR(vma))
return PTR_ERR(vma);
- vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
+ vaddr = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WB);
if (IS_ERR(vaddr)) {
i915_vma_unpin_and_release(, 0);
return PTR_ERR(vaddr);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index c92f2c056db4..c36d5eb5bbb9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -335,7 +335,7 @@ static int guc_log_map(struct intel_guc_log *log)
* buffer pages, so that we can directly get the data
* (up-to-date) from memory.
*/
- vaddr = i915_gem_object_pin_map(log->vma->obj, I915_MAP_WC);
+ vaddr = i915_gem_object_pin_map_unlocked(log->vma->obj, I915_MAP_WC);
if (IS_ERR(vaddr))
return PTR_ERR(vaddr);
@@ -744,7 +744,7 @@ int intel_guc_log_dump(struct intel_guc_log *log, struct
drm_printer *p,
if (!obj)
return 0;
- map = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ map = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
if (IS_ERR(map)) {
DRM_DEBUG("Failed to pin object\n");
drm_puts(p, "(log data unaccessible)\n");
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 65eeb44b397d..2126dd81ac38 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -82,7 +82,7 @@ static int intel_huc_rsa_data_create(struct intel_huc *huc)
if (IS_ERR(vma))
return PTR_ERR(vma);
- vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
+ vaddr = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WB);
if (IS_ERR(vaddr)) {
i915_vma_unpin_and_release(, 0);
return PTR_ERR(vaddr);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 67b06fde1225..370a4ef8e33d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -537,7 +537,7 @@ int intel_uc_fw_init(struct intel_uc_fw *uc_fw)
if (!intel_uc_fw_is_available(uc_fw))
return -ENOEXEC;
- err =
[Intel-gfx] [PATCH v7 28/63] drm/i915: Take obj lock around set_domain ioctl
We need to lock the object to move it to the correct domain, add the missing lock. Signed-off-by: Maarten Lankhorst Reviewed-by: Thomas Hellström --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index 1a788d1f1f1b..a3d5a46e815f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -527,6 +527,10 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, goto out; } + err = i915_gem_object_lock_interruptible(obj, NULL); + if (err) + goto out; + /* * Flush and acquire obj->pages so that we are coherent through * direct access in memory with previous cached writes through @@ -538,7 +542,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, */ err = i915_gem_object_pin_pages(obj); if (err) - goto out; + goto out_unlock; /* * Already in the desired write domain? Nothing for us to do! @@ -553,10 +557,6 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, if (READ_ONCE(obj->write_domain) == read_domains) goto out_unpin; - err = i915_gem_object_lock_interruptible(obj, NULL); - if (err) - goto out_unpin; - if (read_domains & I915_GEM_DOMAIN_WC) err = i915_gem_object_set_to_wc_domain(obj, write_domain); else if (read_domains & I915_GEM_DOMAIN_GTT) @@ -564,13 +564,15 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, else err = i915_gem_object_set_to_cpu_domain(obj, write_domain); +out_unpin: + i915_gem_object_unpin_pages(obj); + +out_unlock: i915_gem_object_unlock(obj); - if (write_domain) + if (!err && write_domain) i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU); -out_unpin: - i915_gem_object_unpin_pages(obj); out: i915_gem_object_put(obj); return err; -- 2.30.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 22/63] drm/i915: Pass ww ctx to intel_pin_to_display_plane
Instead of multiple lockings, lock the object once,
and perform the ww dance around attach_phys and pin_pages.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/display/intel_display.c | 69 ---
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
drivers/gpu/drm/i915/display/intel_fbdev.c| 2 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 34 +++--
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 30 ++--
drivers/gpu/drm/i915/gem/i915_gem_object.h| 1 +
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 10 +--
.../drm/i915/gem/selftests/i915_gem_phys.c| 2 +
8 files changed, 86 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 3e24db8b9ad6..8a0af26bcce2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1368,6 +1368,7 @@ static bool intel_plane_uses_fence(const struct
intel_plane_state *plane_state)
struct i915_vma *
intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
+ bool phys_cursor,
const struct i915_ggtt_view *view,
bool uses_fence,
unsigned long *out_flags)
@@ -1376,14 +1377,19 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
intel_wakeref_t wakeref;
+ struct i915_gem_ww_ctx ww;
struct i915_vma *vma;
unsigned int pinctl;
u32 alignment;
+ int ret;
if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
return ERR_PTR(-EINVAL);
- alignment = intel_surf_alignment(fb, 0);
+ if (phys_cursor)
+ alignment = intel_cursor_alignment(dev_priv);
+ else
+ alignment = intel_surf_alignment(fb, 0);
if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
return ERR_PTR(-EINVAL);
@@ -1418,14 +1424,26 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
if (HAS_GMCH(dev_priv))
pinctl |= PIN_MAPPABLE;
- vma = i915_gem_object_pin_to_display_plane(obj,
- alignment, view, pinctl);
- if (IS_ERR(vma))
+ i915_gem_ww_ctx_init(, true);
+retry:
+ ret = i915_gem_object_lock(obj, );
+ if (!ret && phys_cursor)
+ ret = i915_gem_object_attach_phys(obj, alignment);
+ if (!ret)
+ ret = i915_gem_object_pin_pages(obj);
+ if (ret)
goto err;
- if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
- int ret;
+ if (!ret) {
+ vma = i915_gem_object_pin_to_display_plane(obj, , alignment,
+ view, pinctl);
+ if (IS_ERR(vma)) {
+ ret = PTR_ERR(vma);
+ goto err_unpin;
+ }
+ }
+ if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
/*
* Install a fence for tiled scan-out. Pre-i965 always needs a
* fence, whereas 965+ only requires a fence if using
@@ -1446,16 +1464,28 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
ret = i915_vma_pin_fence(vma);
if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
i915_vma_unpin(vma);
- vma = ERR_PTR(ret);
- goto err;
+ goto err_unpin;
}
+ ret = 0;
- if (ret == 0 && vma->fence)
+ if (vma->fence)
*out_flags |= PLANE_HAS_FENCE;
}
i915_vma_get(vma);
+
+err_unpin:
+ i915_gem_object_unpin_pages(obj);
err:
+ if (ret == -EDEADLK) {
+ ret = i915_gem_ww_ctx_backoff();
+ if (!ret)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+ if (ret)
+ vma = ERR_PTR(ret);
+
atomic_dec(_priv->gpu_error.pending_fb_pin);
intel_runtime_pm_put(_priv->runtime_pm, wakeref);
return vma;
@@ -13608,19 +13638,11 @@ int intel_plane_pin_fb(struct intel_plane_state
*plane_state)
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct drm_framebuffer *fb = plane_state->hw.fb;
struct i915_vma *vma;
+ bool phys_cursor =
+ plane->id == PLANE_CURSOR &&
+ INTEL_INFO(dev_priv)->display.cursor_needs_physical;
- if (plane->id == PLANE_CURSOR &&
- INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
- struct drm_i915_gem_object *obj = intel_fb_obj(fb);
- const int align =
[Intel-gfx] [PATCH v7 40/63] drm/i915: Use a single page table lock for each gtt.
We may create page table objects on the fly, but we may need to
wait with the ww lock held. Instead of waiting on a freed obj
lock, ensure we have the same lock for each object to keep
-EDEADLK working. This ensures that i915_vma_pin_ww can lock
the page tables when required.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 8 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 38 ++-
drivers/gpu/drm/i915/gt/intel_gtt.h | 5
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 3 ++-
drivers/gpu/drm/i915/i915_vma.c | 5
5 files changed, 56 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 2b273652b0f0..4bb6197be9e2 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -647,7 +647,9 @@ static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
if (err)
goto err_ppgtt;
+ i915_gem_object_lock(ppgtt->vm.scratch[0], NULL);
err = i915_vm_pin_pt_stash(>vm, );
+ i915_gem_object_unlock(ppgtt->vm.scratch[0]);
if (err)
goto err_stash;
@@ -734,6 +736,7 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
mutex_unlock(>vm.mutex);
i915_address_space_fini(>vm);
+ dma_resv_fini(>vm.resv);
arch_phys_wc_del(ggtt->mtrr);
@@ -1115,6 +1118,7 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct
intel_gt *gt)
ggtt->vm.gt = gt;
ggtt->vm.i915 = i915;
ggtt->vm.dma = >drm.pdev->dev;
+ dma_resv_init(>vm.resv);
if (INTEL_GEN(i915) <= 5)
ret = i915_gmch_probe(ggtt);
@@ -1122,8 +1126,10 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct
intel_gt *gt)
ret = gen6_gmch_probe(ggtt);
else
ret = gen8_gmch_probe(ggtt);
- if (ret)
+ if (ret) {
+ dma_resv_fini(>vm.resv);
return ret;
+ }
if ((ggtt->vm.total - 1) >> 32) {
drm_err(>drm,
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 444d9bacfafd..941f8af016d6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -13,16 +13,36 @@
struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz)
{
+ struct drm_i915_gem_object *obj;
+
if (I915_SELFTEST_ONLY(should_fail(>fault_attr, 1)))
i915_gem_shrink_all(vm->i915);
- return i915_gem_object_create_internal(vm->i915, sz);
+ obj = i915_gem_object_create_internal(vm->i915, sz);
+ /* ensure all dma objects have the same reservation class */
+ if (!IS_ERR(obj))
+ obj->base.resv = >resv;
+ return obj;
}
int pin_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj)
{
int err;
+ i915_gem_object_lock(obj, NULL);
+ err = i915_gem_object_pin_pages(obj);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ i915_gem_object_make_unshrinkable(obj);
+ return 0;
+}
+
+int pin_pt_dma_locked(struct i915_address_space *vm, struct
drm_i915_gem_object *obj)
+{
+ int err;
+
err = i915_gem_object_pin_pages(obj);
if (err)
return err;
@@ -56,6 +76,20 @@ void __i915_vm_close(struct i915_address_space *vm)
mutex_unlock(>mutex);
}
+/* lock the vm into the current ww, if we lock one, we lock all */
+int i915_vm_lock_objects(struct i915_address_space *vm,
+struct i915_gem_ww_ctx *ww)
+{
+ if (vm->scratch[0]->base.resv == >resv) {
+ return i915_gem_object_lock(vm->scratch[0], ww);
+ } else {
+ struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+
+ /* We borrowed the scratch page from ggtt, take the top level
object */
+ return i915_gem_object_lock(ppgtt->pd->pt.base, ww);
+ }
+}
+
void i915_address_space_fini(struct i915_address_space *vm)
{
drm_mm_takedown(>mm);
@@ -69,6 +103,7 @@ static void __i915_vm_release(struct work_struct *work)
vm->cleanup(vm);
i915_address_space_fini(vm);
+ dma_resv_fini(>resv);
kfree(vm);
}
@@ -98,6 +133,7 @@ void i915_address_space_init(struct i915_address_space *vm,
int subclass)
mutex_init(>mutex);
lockdep_set_subclass(>mutex, subclass);
i915_gem_shrinker_taints_mutex(vm->i915, >mutex);
+ dma_resv_init(>resv);
GEM_BUG_ON(!vm->total);
drm_mm_init(>mm, 0, vm->total);
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index af90090c3d18..8f7c49efa190 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -238,6 +238,7 @@ struct i915_address_space {
atomic_t open;
[Intel-gfx] [PATCH v7 11/63] drm/i915: Disable userptr pread/pwrite support.
Userptr should not need the kernel for a userspace memcpy, userspace
needs to call memcpy directly.
Specifically, disable i915_gem_pwrite_ioctl() and i915_gem_pread_ioctl().
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
-- Still needs an ack from relevant userspace that it won't break, but should
be good.
---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 20
drivers/gpu/drm/i915/i915_gem.c | 5 +
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 0f9024c62c06..5a19699c2d7e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -700,6 +700,24 @@ i915_gem_userptr_dmabuf_export(struct drm_i915_gem_object
*obj)
return i915_gem_userptr_init__mmu_notifier(obj, 0);
}
+static int
+i915_gem_userptr_pwrite(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pwrite *args)
+{
+ drm_dbg(obj->base.dev, "pwrite to userptr no longer allowed\n");
+
+ return -EINVAL;
+}
+
+static int
+i915_gem_userptr_pread(struct drm_i915_gem_object *obj,
+ const struct drm_i915_gem_pread *args)
+{
+ drm_dbg(obj->base.dev, "pread from userptr no longer allowed\n");
+
+ return -EINVAL;
+}
+
static const struct drm_i915_gem_object_ops i915_gem_userptr_ops = {
.name = "i915_gem_object_userptr",
.flags = I915_GEM_OBJECT_IS_SHRINKABLE |
@@ -708,6 +726,8 @@ static const struct drm_i915_gem_object_ops
i915_gem_userptr_ops = {
.get_pages = i915_gem_userptr_get_pages,
.put_pages = i915_gem_userptr_put_pages,
.dmabuf_export = i915_gem_userptr_dmabuf_export,
+ .pwrite = i915_gem_userptr_pwrite,
+ .pread = i915_gem_userptr_pread,
.release = i915_gem_userptr_release,
};
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f713299dd84d..993d26597707 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -400,6 +400,11 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
}
trace_i915_gem_object_pread(obj, args->offset, args->size);
+ ret = -ENODEV;
+ if (obj->ops->pread)
+ ret = obj->ops->pread(obj, args);
+ if (ret != -ENODEV)
+ goto out;
ret = -ENODEV;
if (obj->ops->pread)
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 43/63] drm/i915/selftests: Prepare coherency tests for obj->mm.lock removal.
Straightforward conversion, just convert a bunch of calls to unlocked versions. Signed-off-by: Maarten Lankhorst Reviewed-by: Thomas Hellström --- drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c index 654912abaeb4..7da9f1a53ab5 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c @@ -160,7 +160,7 @@ static int wc_set(struct context *ctx, unsigned long offset, u32 v) if (err) return err; - map = i915_gem_object_pin_map(ctx->obj, I915_MAP_WC); + map = i915_gem_object_pin_map_unlocked(ctx->obj, I915_MAP_WC); if (IS_ERR(map)) return PTR_ERR(map); @@ -183,7 +183,7 @@ static int wc_get(struct context *ctx, unsigned long offset, u32 *v) if (err) return err; - map = i915_gem_object_pin_map(ctx->obj, I915_MAP_WC); + map = i915_gem_object_pin_map_unlocked(ctx->obj, I915_MAP_WC); if (IS_ERR(map)) return PTR_ERR(map); -- 2.30.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 25/63] drm/i915: Take reservation lock around i915_vma_pin.
We previously complained when ww == NULL.
This function is now only used in selftests to pin an object,
and ww locking is now fixed.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
.../i915/gem/selftests/i915_gem_coherency.c | 14 +
drivers/gpu/drm/i915/i915_gem.c | 6 +-
drivers/gpu/drm/i915/i915_vma.c | 4 +---
drivers/gpu/drm/i915/i915_vma.h | 20 +++
4 files changed, 27 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
index 1117d2a44518..654912abaeb4 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
@@ -200,16 +200,14 @@ static int gpu_set(struct context *ctx, unsigned long
offset, u32 v)
u32 *cs;
int err;
+ vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, 0);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
i915_gem_object_lock(ctx->obj, NULL);
err = i915_gem_object_set_to_gtt_domain(ctx->obj, true);
if (err)
- goto out_unlock;
-
- vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, 0);
- if (IS_ERR(vma)) {
- err = PTR_ERR(vma);
- goto out_unlock;
- }
+ goto out_unpin;
rq = intel_engine_create_kernel_request(ctx->engine);
if (IS_ERR(rq)) {
@@ -249,9 +247,7 @@ static int gpu_set(struct context *ctx, unsigned long
offset, u32 v)
i915_request_add(rq);
out_unpin:
i915_vma_unpin(vma);
-out_unlock:
i915_gem_object_unlock(ctx->obj);
-
return err;
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c69fb95f7ac8..6bd8929587f3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -914,7 +914,11 @@ i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object
*obj,
return ERR_PTR(ret);
}
- ret = i915_vma_pin_ww(vma, ww, size, alignment, flags | PIN_GLOBAL);
+ if (ww)
+ ret = i915_vma_pin_ww(vma, ww, size, alignment, flags |
PIN_GLOBAL);
+ else
+ ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
+
if (ret)
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 1ffda2aaa7a0..265e3a3079e2 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -863,9 +863,7 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
int err;
#ifdef CONFIG_PROVE_LOCKING
- if (debug_locks && lockdep_is_held(>vm->i915->drm.struct_mutex))
- WARN_ON(!ww);
- if (debug_locks && ww && vma->resv)
+ if (debug_locks && !WARN_ON(!ww) && vma->resv)
assert_vma_held(vma);
#endif
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 6b48f5c42488..8df784a026d2 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -246,10 +246,22 @@ i915_vma_pin_ww(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
static inline int __must_check
i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
{
-#ifdef CONFIG_LOCKDEP
- WARN_ON_ONCE(vma->resv && dma_resv_held(vma->resv));
-#endif
- return i915_vma_pin_ww(vma, NULL, size, alignment, flags);
+ struct i915_gem_ww_ctx ww;
+ int err;
+
+ i915_gem_ww_ctx_init(, true);
+retry:
+ err = i915_gem_object_lock(vma->obj, );
+ if (!err)
+ err = i915_vma_pin_ww(vma, , size, alignment, flags);
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+
+ return err;
}
int i915_ggtt_pin(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 57/63] drm/i915/selftests: Prepare i915_request tests for obj->mm.lock removal
Straightforward conversion by using unlocked versions.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/selftests/i915_request.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index d2a678a2497e..9a9e92a775c8 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -620,7 +620,7 @@ static struct i915_vma *empty_batch(struct drm_i915_private
*i915)
if (IS_ERR(obj))
return ERR_CAST(obj);
- cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ cmd = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
if (IS_ERR(cmd)) {
err = PTR_ERR(cmd);
goto err;
@@ -782,7 +782,7 @@ static struct i915_vma *recursive_batch(struct
drm_i915_private *i915)
if (err)
goto err;
- cmd = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ cmd = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
if (IS_ERR(cmd)) {
err = PTR_ERR(cmd);
goto err;
@@ -817,7 +817,7 @@ static int recursive_batch_resolve(struct i915_vma *batch)
{
u32 *cmd;
- cmd = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
+ cmd = i915_gem_object_pin_map_unlocked(batch->obj, I915_MAP_WC);
if (IS_ERR(cmd))
return PTR_ERR(cmd);
@@ -1070,8 +1070,8 @@ static int live_sequential_engines(void *arg)
if (!request[idx])
break;
- cmd = i915_gem_object_pin_map(request[idx]->batch->obj,
- I915_MAP_WC);
+ cmd = i915_gem_object_pin_map_unlocked(request[idx]->batch->obj,
+ I915_MAP_WC);
if (!IS_ERR(cmd)) {
*cmd = MI_BATCH_BUFFER_END;
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 17/63] drm/i915: Flatten obj->mm.lock
With userptr fixed, there is no need for all separate lockdep classes
now, and we can remove all lockdep tricks used. A trylock in the
shrinker is all we need now to flatten the locking hierarchy.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 +---
drivers/gpu/drm/i915/gem/i915_gem_object.h | 20 ++--
drivers/gpu/drm/i915/gem/i915_gem_pages.c| 34 ++--
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 10 +++---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 2 +-
6 files changed, 27 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index b7fe7e4f69e4..821cb40f8d73 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -62,7 +62,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_object_ops *ops,
struct lock_class_key *key, unsigned flags)
{
- __mutex_init(>mm.lock, ops->name ?: "obj->mm.lock", key);
+ mutex_init(>mm.lock);
spin_lock_init(>vma.lock);
INIT_LIST_HEAD(>vma.list);
@@ -86,10 +86,6 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
mutex_init(>mm.get_page.lock);
INIT_RADIX_TREE(>mm.get_dma_page.radix, GFP_KERNEL | __GFP_NOWARN);
mutex_init(>mm.get_dma_page.lock);
-
- if (IS_ENABLED(CONFIG_LOCKDEP) && i915_gem_object_is_shrinkable(obj))
- i915_gem_shrinker_taints_mutex(to_i915(obj->base.dev),
- >mm.lock);
}
/**
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index d40a8e457163..425bc68c1c2d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -372,27 +372,10 @@ void __i915_gem_object_set_pages(struct
drm_i915_gem_object *obj,
int i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
-enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock/struct_mutex */
- I915_MM_NORMAL = 0,
- /*
-* Only used by struct_mutex, when called "recursively" from
-* direct-reclaim-esque. Safe because there is only every one
-* struct_mutex in the entire system.
-*/
- I915_MM_SHRINKER = 1,
- /*
-* Used for obj->mm.lock when allocating pages. Safe because the object
-* isn't yet on any LRU, and therefore the shrinker can't deadlock on
-* it. As soon as the object has pages, obj->mm.lock nests within
-* fs_reclaim.
-*/
- I915_MM_GET_PAGES = 1,
-};
-
static inline int __must_check
i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
- might_lock_nested(>mm.lock, I915_MM_GET_PAGES);
+ might_lock(>mm.lock);
if (atomic_inc_not_zero(>mm.pages_pin_count))
return 0;
@@ -436,6 +419,7 @@ i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
}
int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
+int __i915_gem_object_put_pages_locked(struct drm_i915_gem_object *obj);
void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
void i915_gem_object_writeback(struct drm_i915_gem_object *obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index e7d7650072c5..e947d4c0da1f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -114,7 +114,7 @@ int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj)
{
int err;
- err = mutex_lock_interruptible_nested(>mm.lock, I915_MM_GET_PAGES);
+ err = mutex_lock_interruptible(>mm.lock);
if (err)
return err;
@@ -196,21 +196,13 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object
*obj)
return pages;
}
-int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
+int __i915_gem_object_put_pages_locked(struct drm_i915_gem_object *obj)
{
struct sg_table *pages;
- int err;
if (i915_gem_object_has_pinned_pages(obj))
return -EBUSY;
- /* May be called by shrinker from within get_pages() (on another bo) */
- mutex_lock(>mm.lock);
- if (unlikely(atomic_read(>mm.pages_pin_count))) {
- err = -EBUSY;
- goto unlock;
- }
-
i915_gem_object_release_mmap_offset(obj);
/*
@@ -226,14 +218,22 @@ int __i915_gem_object_put_pages(struct
drm_i915_gem_object *obj)
* get_pages backends we should be better able to handle the
* cancellation of the async task in a more uniform manner.
*/
- if (!pages)
- pages =
[Intel-gfx] [PATCH v7 50/63] drm/i915/selftests: Prepare igt_gem_utils for obj->mm.lock removal
igt_emit_store_dw needs to use the unlocked version, as it's not
holding a lock. This fixes igt_gpu_fill_dw() which is used by
some other selftests.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
index d6783061bc72..0b092c62bb34 100644
--- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
+++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
@@ -55,7 +55,7 @@ igt_emit_store_dw(struct i915_vma *vma,
if (IS_ERR(obj))
return ERR_CAST(obj);
- cmd = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ cmd = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
if (IS_ERR(cmd)) {
err = PTR_ERR(cmd);
goto err;
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 41/63] drm/i915/selftests: Prepare huge_pages testcases for obj->mm.lock removal.
Straightforward conversion, just convert a bunch of calls to
unlocked versions.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 28 ++-
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 6c2241b7387b..dadd485bc52f 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -589,7 +589,7 @@ static int igt_mock_ppgtt_misaligned_dma(void *arg)
goto out_put;
}
- err = i915_gem_object_pin_pages(obj);
+ err = i915_gem_object_pin_pages_unlocked(obj);
if (err)
goto out_put;
@@ -653,15 +653,19 @@ static int igt_mock_ppgtt_misaligned_dma(void *arg)
break;
}
+ i915_gem_object_lock(obj, NULL);
i915_gem_object_unpin_pages(obj);
__i915_gem_object_put_pages(obj);
+ i915_gem_object_unlock(obj);
i915_gem_object_put(obj);
}
return 0;
out_unpin:
+ i915_gem_object_lock(obj, NULL);
i915_gem_object_unpin_pages(obj);
+ i915_gem_object_unlock(obj);
out_put:
i915_gem_object_put(obj);
@@ -675,8 +679,10 @@ static void close_object_list(struct list_head *objects,
list_for_each_entry_safe(obj, on, objects, st_link) {
list_del(>st_link);
+ i915_gem_object_lock(obj, NULL);
i915_gem_object_unpin_pages(obj);
__i915_gem_object_put_pages(obj);
+ i915_gem_object_unlock(obj);
i915_gem_object_put(obj);
}
}
@@ -713,7 +719,7 @@ static int igt_mock_ppgtt_huge_fill(void *arg)
break;
}
- err = i915_gem_object_pin_pages(obj);
+ err = i915_gem_object_pin_pages_unlocked(obj);
if (err) {
i915_gem_object_put(obj);
break;
@@ -889,7 +895,7 @@ static int igt_mock_ppgtt_64K(void *arg)
if (IS_ERR(obj))
return PTR_ERR(obj);
- err = i915_gem_object_pin_pages(obj);
+ err = i915_gem_object_pin_pages_unlocked(obj);
if (err)
goto out_object_put;
@@ -943,8 +949,10 @@ static int igt_mock_ppgtt_64K(void *arg)
}
i915_vma_unpin(vma);
+ i915_gem_object_lock(obj, NULL);
i915_gem_object_unpin_pages(obj);
__i915_gem_object_put_pages(obj);
+ i915_gem_object_unlock(obj);
i915_gem_object_put(obj);
}
}
@@ -954,7 +962,9 @@ static int igt_mock_ppgtt_64K(void *arg)
out_vma_unpin:
i915_vma_unpin(vma);
out_object_unpin:
+ i915_gem_object_lock(obj, NULL);
i915_gem_object_unpin_pages(obj);
+ i915_gem_object_unlock(obj);
out_object_put:
i915_gem_object_put(obj);
@@ -1024,7 +1034,7 @@ static int __cpu_check_vmap(struct drm_i915_gem_object
*obj, u32 dword, u32 val)
if (err)
return err;
- ptr = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ ptr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
if (IS_ERR(ptr))
return PTR_ERR(ptr);
@@ -1304,7 +1314,7 @@ static int igt_ppgtt_smoke_huge(void *arg)
return err;
}
- err = i915_gem_object_pin_pages(obj);
+ err = i915_gem_object_pin_pages_unlocked(obj);
if (err) {
if (err == -ENXIO || err == -E2BIG) {
i915_gem_object_put(obj);
@@ -1327,8 +1337,10 @@ static int igt_ppgtt_smoke_huge(void *arg)
__func__, size, i);
}
out_unpin:
+ i915_gem_object_lock(obj, NULL);
i915_gem_object_unpin_pages(obj);
__i915_gem_object_put_pages(obj);
+ i915_gem_object_unlock(obj);
out_put:
i915_gem_object_put(obj);
@@ -1402,7 +1414,7 @@ static int igt_ppgtt_sanity_check(void *arg)
return err;
}
- err = i915_gem_object_pin_pages(obj);
+ err = i915_gem_object_pin_pages_unlocked(obj);
if (err) {
i915_gem_object_put(obj);
goto out;
@@ -1416,8 +1428,10 @@ static int igt_ppgtt_sanity_check(void *arg)
err = igt_write_huge(ctx, obj);
+
[Intel-gfx] [PATCH v7 55/63] drm/i915/selftests: Prepare ring submission for obj->mm.lock removal
Use unlocked versions when the ww lock is not held.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/selftest_ring_submission.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
index 3350e7c995bc..99609271c3a7 100644
--- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
@@ -35,7 +35,7 @@ static struct i915_vma *create_wally(struct intel_engine_cs
*engine)
return ERR_PTR(err);
}
- cs = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ cs = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC);
if (IS_ERR(cs)) {
i915_gem_object_put(obj);
return ERR_CAST(cs);
@@ -212,7 +212,7 @@ static int __live_ctx_switch_wa(struct intel_engine_cs
*engine)
if (IS_ERR(bb))
return PTR_ERR(bb);
- result = i915_gem_object_pin_map(bb->obj, I915_MAP_WC);
+ result = i915_gem_object_pin_map_unlocked(bb->obj, I915_MAP_WC);
if (IS_ERR(result)) {
intel_context_put(bb->private);
i915_vma_unpin_and_release(, 0);
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 30/63] drm/i915: Fix pread/pwrite to work with new locking rules.
We are removing obj->mm.lock, and need to take the reservation lock
before we can pin pages. Move the pinning pages into the helper, and
merge gtt pwrite/pread preparation and cleanup paths.
The fence lock is also removed; it will conflict with fence annotations,
because of memory allocations done when pagefaulting inside copy_*_user.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/Makefile | 1 -
drivers/gpu/drm/i915/gem/i915_gem_fence.c | 95 -
drivers/gpu/drm/i915/gem/i915_gem_object.h | 5 -
drivers/gpu/drm/i915/i915_gem.c| 224 +++--
4 files changed, 114 insertions(+), 211 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/gem/i915_gem_fence.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index ce01634d4ea7..a5f377703980 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -141,7 +141,6 @@ gem-y += \
gem/i915_gem_dmabuf.o \
gem/i915_gem_domain.o \
gem/i915_gem_execbuffer.o \
- gem/i915_gem_fence.o \
gem/i915_gem_internal.o \
gem/i915_gem_object.o \
gem/i915_gem_object_blt.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_fence.c
b/drivers/gpu/drm/i915/gem/i915_gem_fence.c
deleted file mode 100644
index 8ab842c80f99..
--- a/drivers/gpu/drm/i915/gem/i915_gem_fence.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * SPDX-License-Identifier: MIT
- *
- * Copyright © 2019 Intel Corporation
- */
-
-#include "i915_drv.h"
-#include "i915_gem_object.h"
-
-struct stub_fence {
- struct dma_fence dma;
- struct i915_sw_fence chain;
-};
-
-static int __i915_sw_fence_call
-stub_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
-{
- struct stub_fence *stub = container_of(fence, typeof(*stub), chain);
-
- switch (state) {
- case FENCE_COMPLETE:
- dma_fence_signal(>dma);
- break;
-
- case FENCE_FREE:
- dma_fence_put(>dma);
- break;
- }
-
- return NOTIFY_DONE;
-}
-
-static const char *stub_driver_name(struct dma_fence *fence)
-{
- return DRIVER_NAME;
-}
-
-static const char *stub_timeline_name(struct dma_fence *fence)
-{
- return "object";
-}
-
-static void stub_release(struct dma_fence *fence)
-{
- struct stub_fence *stub = container_of(fence, typeof(*stub), dma);
-
- i915_sw_fence_fini(>chain);
-
- BUILD_BUG_ON(offsetof(typeof(*stub), dma));
- dma_fence_free(>dma);
-}
-
-static const struct dma_fence_ops stub_fence_ops = {
- .get_driver_name = stub_driver_name,
- .get_timeline_name = stub_timeline_name,
- .release = stub_release,
-};
-
-struct dma_fence *
-i915_gem_object_lock_fence(struct drm_i915_gem_object *obj)
-{
- struct stub_fence *stub;
-
- assert_object_held(obj);
-
- stub = kmalloc(sizeof(*stub), GFP_KERNEL);
- if (!stub)
- return NULL;
-
- i915_sw_fence_init(>chain, stub_notify);
- dma_fence_init(>dma, _fence_ops, >chain.wait.lock,
- 0, 0);
-
- if (i915_sw_fence_await_reservation(>chain,
- obj->base.resv, NULL, true,
-
i915_fence_timeout(to_i915(obj->base.dev)),
- I915_FENCE_GFP) < 0)
- goto err;
-
- dma_resv_add_excl_fence(obj->base.resv, >dma);
-
- return >dma;
-
-err:
- stub_release(>dma);
- return NULL;
-}
-
-void i915_gem_object_unlock_fence(struct drm_i915_gem_object *obj,
- struct dma_fence *fence)
-{
- struct stub_fence *stub = container_of(fence, typeof(*stub), dma);
-
- i915_sw_fence_commit(>chain);
-}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index b22dc3d2f3b7..807798080884 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -189,11 +189,6 @@ static inline void i915_gem_object_unlock(struct
drm_i915_gem_object *obj)
dma_resv_unlock(obj->base.resv);
}
-struct dma_fence *
-i915_gem_object_lock_fence(struct drm_i915_gem_object *obj);
-void i915_gem_object_unlock_fence(struct drm_i915_gem_object *obj,
- struct dma_fence *fence);
-
static inline void
i915_gem_object_set_readonly(struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6bd8929587f3..29e6c9dc92e0 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -204,7 +204,6 @@ i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
{
unsigned int needs_clflush;
unsigned int idx, offset;
- struct dma_fence *fence;
char __user *user_data;
u64 remain;
int ret;
@@ -213,19 +212,17 @@
[Intel-gfx] [PATCH v7 35/63] drm/i915: Increase ww locking for perf.
We need to lock a few more objects, some temporarily,
add ww lock where needed.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/i915_perf.c | 56
1 file changed, 43 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 112ba5f2ce90..aac614204fc0 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1589,7 +1589,7 @@ static int alloc_oa_buffer(struct i915_perf_stream
*stream)
stream->oa_buffer.vma = vma;
stream->oa_buffer.vaddr =
- i915_gem_object_pin_map(bo, I915_MAP_WB);
+ i915_gem_object_pin_map_unlocked(bo, I915_MAP_WB);
if (IS_ERR(stream->oa_buffer.vaddr)) {
ret = PTR_ERR(stream->oa_buffer.vaddr);
goto err_unpin;
@@ -1643,6 +1643,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
const u32 base = stream->engine->mmio_base;
#define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
u32 *batch, *ts0, *cs, *jump;
+ struct i915_gem_ww_ctx ww;
int ret, i;
enum {
START_TS,
@@ -1660,15 +1661,21 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
return PTR_ERR(bo);
}
+ i915_gem_ww_ctx_init(, true);
+retry:
+ ret = i915_gem_object_lock(bo, );
+ if (ret)
+ goto out_ww;
+
/*
* We pin in GGTT because we jump into this buffer now because
* multiple OA config BOs will have a jump to this address and it
* needs to be fixed during the lifetime of the i915/perf stream.
*/
- vma = i915_gem_object_ggtt_pin(bo, NULL, 0, 0, PIN_HIGH);
+ vma = i915_gem_object_ggtt_pin_ww(bo, , NULL, 0, 0, PIN_HIGH);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
- goto err_unref;
+ goto out_ww;
}
batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
@@ -1802,12 +1809,19 @@ static int alloc_noa_wait(struct i915_perf_stream
*stream)
__i915_gem_object_release_map(bo);
stream->noa_wait = vma;
- return 0;
+ goto out_ww;
err_unpin:
i915_vma_unpin_and_release(, 0);
-err_unref:
- i915_gem_object_put(bo);
+out_ww:
+ if (ret == -EDEADLK) {
+ ret = i915_gem_ww_ctx_backoff();
+ if (!ret)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
+ if (ret)
+ i915_gem_object_put(bo);
return ret;
}
@@ -1850,6 +1864,7 @@ alloc_oa_config_buffer(struct i915_perf_stream *stream,
{
struct drm_i915_gem_object *obj;
struct i915_oa_config_bo *oa_bo;
+ struct i915_gem_ww_ctx ww;
size_t config_length = 0;
u32 *cs;
int err;
@@ -1870,10 +1885,16 @@ alloc_oa_config_buffer(struct i915_perf_stream *stream,
goto err_free;
}
+ i915_gem_ww_ctx_init(, true);
+retry:
+ err = i915_gem_object_lock(obj, );
+ if (err)
+ goto out_ww;
+
cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
if (IS_ERR(cs)) {
err = PTR_ERR(cs);
- goto err_oa_bo;
+ goto out_ww;
}
cs = write_cs_mi_lri(cs,
@@ -1901,19 +1922,28 @@ alloc_oa_config_buffer(struct i915_perf_stream *stream,
NULL);
if (IS_ERR(oa_bo->vma)) {
err = PTR_ERR(oa_bo->vma);
- goto err_oa_bo;
+ goto out_ww;
}
oa_bo->oa_config = i915_oa_config_get(oa_config);
llist_add(_bo->node, >oa_config_bos);
- return oa_bo;
+out_ww:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff();
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini();
-err_oa_bo:
- i915_gem_object_put(obj);
+ if (err)
+ i915_gem_object_put(obj);
err_free:
- kfree(oa_bo);
- return ERR_PTR(err);
+ if (err) {
+ kfree(oa_bo);
+ return ERR_PTR(err);
+ }
+ return oa_bo;
}
static struct i915_vma *
--
2.30.0
___
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[Intel-gfx] [PATCH v7 48/63] drm/i915/selftests: Prepare object tests for obj->mm.lock removal.
Convert a single pin_pages call to use the unlocked version.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
index bf853c40ec65..740ee8086a27 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
@@ -47,7 +47,7 @@ static int igt_gem_huge(void *arg)
if (IS_ERR(obj))
return PTR_ERR(obj);
- err = i915_gem_object_pin_pages(obj);
+ err = i915_gem_object_pin_pages_unlocked(obj);
if (err) {
pr_err("Failed to allocate %u pages (%lu total), err=%d\n",
nreal, obj->base.size / PAGE_SIZE, err);
--
2.30.0
___
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[Intel-gfx] [PATCH v7 15/63] drm/i915: Make compilation of userptr code depend on MMU_NOTIFIER.
Now that unsynchronized mappings are removed, the only time userptr
works is when the MMU notifier is enabled. Put all of the userptr
code behind a mmu notifier ifdef.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +
drivers/gpu/drm/i915/gem/i915_gem_object.h| 4 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 58 +++
drivers/gpu/drm/i915/i915_drv.h | 2 +
5 files changed, 31 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index b5056bd80464..c72440c10876 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1964,8 +1964,10 @@ static noinline int eb_relocate_parse_slow(struct
i915_execbuffer *eb,
err = 0;
}
+#ifdef CONFIG_MMU_NOTIFIER
if (!err)
flush_workqueue(eb->i915->mm.userptr_wq);
+#endif
err_relock:
i915_gem_ww_ctx_init(>ww, true);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 3f300a1d27ba..7b83ce5e38c3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -577,7 +577,11 @@ void __i915_gem_object_invalidate_frontbuffer(struct
drm_i915_gem_object *obj,
static inline bool
i915_gem_object_is_userptr(struct drm_i915_gem_object *obj)
{
+#ifdef CONFIG_MMU_NOTIFIER
return obj->userptr.mm;
+#else
+ return false;
+#endif
}
static inline void
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 33b54727e306..7423f622cba3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -290,6 +290,7 @@ struct drm_i915_gem_object {
unsigned long *bit_17;
union {
+#ifdef CONFIG_MMU_NOTIFIER
struct i915_gem_userptr {
uintptr_t ptr;
@@ -297,6 +298,7 @@ struct drm_i915_gem_object {
struct i915_mmu_object *mmu_object;
struct work_struct *work;
} userptr;
+#endif
struct drm_mm_node *stolen;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 80bc10b4ac74..b466ab2def4d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -15,6 +15,8 @@
#include "i915_gem_object.h"
#include "i915_scatterlist.h"
+#if defined(CONFIG_MMU_NOTIFIER)
+
struct i915_mm_struct {
struct mm_struct *mm;
struct drm_i915_private *i915;
@@ -24,7 +26,6 @@ struct i915_mm_struct {
struct rcu_work work;
};
-#if defined(CONFIG_MMU_NOTIFIER)
#include
struct i915_mmu_notifier {
@@ -217,15 +218,11 @@ i915_mmu_notifier_find(struct i915_mm_struct *mm)
}
static int
-i915_gem_userptr_init__mmu_notifier(struct drm_i915_gem_object *obj,
- unsigned flags)
+i915_gem_userptr_init__mmu_notifier(struct drm_i915_gem_object *obj)
{
struct i915_mmu_notifier *mn;
struct i915_mmu_object *mo;
- if (flags & I915_USERPTR_UNSYNCHRONIZED)
- return -ENODEV;
-
if (GEM_WARN_ON(!obj->userptr.mm))
return -EINVAL;
@@ -258,32 +255,6 @@ i915_mmu_notifier_free(struct i915_mmu_notifier *mn,
kfree(mn);
}
-#else
-
-static void
-__i915_gem_userptr_set_active(struct drm_i915_gem_object *obj, bool value)
-{
-}
-
-static void
-i915_gem_userptr_release__mmu_notifier(struct drm_i915_gem_object *obj)
-{
-}
-
-static int
-i915_gem_userptr_init__mmu_notifier(struct drm_i915_gem_object *obj,
- unsigned flags)
-{
- return -ENODEV;
-}
-
-static void
-i915_mmu_notifier_free(struct i915_mmu_notifier *mn,
- struct mm_struct *mm)
-{
-}
-
-#endif
static struct i915_mm_struct *
__i915_mm_struct_find(struct drm_i915_private *i915, struct mm_struct *real)
@@ -725,6 +696,8 @@ static const struct drm_i915_gem_object_ops
i915_gem_userptr_ops = {
.release = i915_gem_userptr_release,
};
+#endif
+
/*
* Creates a new mm object that wraps some normal memory from the process
* context - user memory.
@@ -765,12 +738,12 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
void *data,
struct drm_file *file)
{
- static struct lock_class_key lock_class;
+ static struct lock_class_key __maybe_unused lock_class;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_gem_userptr *args = data;
- struct drm_i915_gem_object *obj;
- int ret;
- u32 handle;
+ struct drm_i915_gem_object __maybe_unused *obj;
+
[Intel-gfx] [PATCH v7 05/63] drm/i915: Ensure we hold the object mutex in pin correctly.
Currently we have a lot of places where we hold the gem object lock,
but haven't yet been converted to the ww dance. Complain loudly about
those places.
i915_vma_pin shouldn't have the obj lock held, so we can do a ww dance,
while i915_vma_pin_ww should.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström #irc
---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 11 ++-
drivers/gpu/drm/i915/i915_vma.h | 3 +++
3 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c
b/drivers/gpu/drm/i915/gt/intel_renderstate.c
index 0f7c0a148b80..b03e197b1d99 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
@@ -176,7 +176,7 @@ int intel_renderstate_init(struct intel_renderstate *so,
if (err)
goto err_context;
- err = i915_vma_pin(so->vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
+ err = i915_vma_pin_ww(so->vma, >ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
if (err)
goto err_context;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index caa9b041616b..7310893086f7 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -865,6 +865,8 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
#ifdef CONFIG_PROVE_LOCKING
if (debug_locks && lockdep_is_held(>vm->i915->drm.struct_mutex))
WARN_ON(!ww);
+ if (debug_locks && ww && vma->resv)
+ assert_vma_held(vma);
#endif
BUILD_BUG_ON(PIN_GLOBAL != I915_VMA_GLOBAL_BIND);
@@ -1020,8 +1022,15 @@ int i915_ggtt_pin(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
+#ifdef CONFIG_LOCKDEP
+ WARN_ON(!ww && vma->resv && dma_resv_held(vma->resv));
+#endif
+
do {
- err = i915_vma_pin_ww(vma, ww, 0, align, flags | PIN_GLOBAL);
+ if (ww)
+ err = i915_vma_pin_ww(vma, ww, 0, align, flags |
PIN_GLOBAL);
+ else
+ err = i915_vma_pin(vma, 0, align, flags | PIN_GLOBAL);
if (err != -ENOSPC) {
if (!err) {
err = i915_vma_wait_for_bind(vma);
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index a64adc8c883b..3c914c9de9a9 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -243,6 +243,9 @@ i915_vma_pin_ww(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
static inline int __must_check
i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
{
+#ifdef CONFIG_LOCKDEP
+ WARN_ON_ONCE(vma->resv && dma_resv_held(vma->resv));
+#endif
return i915_vma_pin_ww(vma, NULL, size, alignment, flags);
}
--
2.30.0
___
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[Intel-gfx] [PATCH v7 61/63] drm/i915: Finally remove obj->mm.lock.
With all callers and selftests fixed to use ww locking, we can now
finally remove this lock.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_object.c| 2 -
drivers/gpu/drm/i915/gem/i915_gem_object.h| 5 +--
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 -
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 43 ---
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 34 ---
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 37 +++-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.h | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_tiling.c| 2 -
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 +-
drivers/gpu/drm/i915/i915_debugfs.c | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 6 ---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
14 files changed, 55 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 821cb40f8d73..ea74cbca95be 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -62,8 +62,6 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_object_ops *ops,
struct lock_class_key *key, unsigned flags)
{
- mutex_init(>mm.lock);
-
spin_lock_init(>vma.lock);
INIT_LIST_HEAD(>vma.list);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 0acdd08934da..32a701b9329c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -155,7 +155,7 @@ static inline void assert_object_held_shared(struct
drm_i915_gem_object *obj)
*/
if (IS_ENABLED(CONFIG_LOCKDEP) &&
kref_read(>base.refcount) > 0)
- lockdep_assert_held(>mm.lock);
+ assert_object_held(obj);
}
static inline int __i915_gem_object_lock(struct drm_i915_gem_object *obj,
@@ -384,7 +384,7 @@ int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj);
static inline int __must_check
i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
- might_lock(>mm.lock);
+ assert_object_held(obj);
if (atomic_inc_not_zero(>mm.pages_pin_count))
return 0;
@@ -430,7 +430,6 @@ i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
}
int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
-int __i915_gem_object_put_pages_locked(struct drm_i915_gem_object *obj);
void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
void i915_gem_object_writeback(struct drm_i915_gem_object *obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index dbe12951fa1c..8e485cb3343c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -216,7 +216,6 @@ struct drm_i915_gem_object {
* Protects the pages and their use. Do not use directly, but
* instead go through the pin/unpin interfaces.
*/
- struct mutex lock;
atomic_t pages_pin_count;
atomic_t shrink_pin;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 5b8af8f83ee3..aed8a37ccdc9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -70,7 +70,7 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object
*obj,
struct list_head *list;
unsigned long flags;
- lockdep_assert_held(>mm.lock);
+ assert_object_held(obj);
spin_lock_irqsave(>mm.obj_lock, flags);
i915->mm.shrink_count++;
@@ -117,9 +117,7 @@ int __i915_gem_object_get_pages(struct drm_i915_gem_object
*obj)
{
int err;
- err = mutex_lock_interruptible(>mm.lock);
- if (err)
- return err;
+ assert_object_held(obj);
assert_object_held_shared(obj);
@@ -128,15 +126,13 @@ int __i915_gem_object_get_pages(struct
drm_i915_gem_object *obj)
err = i915_gem_object_get_pages(obj);
if (err)
- goto unlock;
+ return err;
smp_mb__before_atomic();
}
atomic_inc(>mm.pages_pin_count);
-unlock:
- mutex_unlock(>mm.lock);
- return err;
+ return 0;
}
int i915_gem_object_pin_pages_unlocked(struct drm_i915_gem_object *obj)
@@ -223,7 +219,7 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object
*obj)
return pages;
}
-int __i915_gem_object_put_pages_locked(struct
[Intel-gfx] [PATCH v7 39/63] drm/i915: Fix ww locking in shmem_create_from_object
Quick fix, just use the unlocked version. Signed-off-by: Maarten Lankhorst Reviewed-by: Thomas Hellström --- drivers/gpu/drm/i915/gt/shmem_utils.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/shmem_utils.c b/drivers/gpu/drm/i915/gt/shmem_utils.c index a4d8fc9e2374..f8f02aab842b 100644 --- a/drivers/gpu/drm/i915/gt/shmem_utils.c +++ b/drivers/gpu/drm/i915/gt/shmem_utils.c @@ -39,7 +39,7 @@ struct file *shmem_create_from_object(struct drm_i915_gem_object *obj) return file; } - ptr = i915_gem_object_pin_map(obj, I915_MAP_WB); + ptr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB); if (IS_ERR(ptr)) return ERR_CAST(ptr); -- 2.30.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
