[Intel-gfx] [PULL] gvt-gt-next
Hi, Here's more gvt next changes including ww locking fix from Zhi, and replace to use i915 engine default state for GVT cmd parser init. Those have all been verified without regression. Details below. Thanks. -- The following changes since commit 69b4b99842201bc24c98ba66b922d8879e190483: drm/i915/gvt: Add missing forward decl of intel_vgpu for HDRTEST (2021-01-21 15:51:21 +0200) are available in the Git repository at: https://github.com/intel/gvt-linux tags/gvt-gt-next-2020-02-05 for you to fetch changes up to e156285b120feaac6207e6bd3fa31d9ae8ffd80d: drm/i915/gvt: Purge dev_priv->gt (2021-02-05 15:28:36 +0800) gvt-gt-next-2020-02-05 - GVT object ww locking fix (Zhi) - One smatch fix for uninitialized return value (Dan) - Use i915 engine's default state for GVT cmd parser init (Chris) - Purge dev_priv->gt (Chris) Chris Wilson (2): drm/i915/gvt: Parse default state to update reg whitelist drm/i915/gvt: Purge dev_priv->gt Dan Carpenter (1): drm/i915/gvt: fix uninitialized return in intel_gvt_update_reg_whitelist() Zhenyu Wang (1): Merge tag 'drm-intel-gt-next-2021-01-21-1' into gvt-gt-next Zhi Wang (1): drm/i915/gvt: Introduce per object locking in GVT scheduler. drivers/gpu/drm/i915/gvt/cmd_parser.c | 92 --- drivers/gpu/drm/i915/gvt/execlist.c | 8 ++- drivers/gpu/drm/i915/gvt/scheduler.c | 52 +++- 3 files changed, 64 insertions(+), 88 deletions(-) signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: support ddr5 mem types
== Series Details == Series: drm/i915/display: support ddr5 mem types URL : https://patchwork.freedesktop.org/series/86726/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9732_full -> Patchwork_19595_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19595_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19595_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19595_full: ### IGT changes ### Possible regressions * igt@kms_flip_tiling@flip-yf-tiled@edp-1-pipe-c: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-skl4/igt@kms_flip_tiling@flip-yf-ti...@edp-1-pipe-c.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/shard-skl7/igt@kms_flip_tiling@flip-yf-ti...@edp-1-pipe-c.html Known issues Here are the changes found in Patchwork_19595_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-tglb: NOTRUN -> [DMESG-WARN][3] ([i915#3002]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/shard-tglb2/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@replace@vecs0: - shard-iclb: [PASS][4] -> [FAIL][5] ([i915#2410]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-iclb7/igt@gem_ctx_persistence@repl...@vecs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/shard-iclb7/igt@gem_ctx_persistence@repl...@vecs0.html * igt@gem_exec_balancer@hang: - shard-iclb: [PASS][6] -> [INCOMPLETE][7] ([i915#1895] / [i915#2295]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-iclb8/igt@gem_exec_balan...@hang.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/shard-iclb1/igt@gem_exec_balan...@hang.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/shard-iclb1/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-apl1/igt@gem_exec_fair@basic-n...@vecs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-kbl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_params@secure-non-root: - shard-tglb: NOTRUN -> [SKIP][15] ([fdo#112283]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/shard-tglb3/igt@gem_exec_par...@secure-non-root.html * igt@gem_exec_reloc@basic-parallel: - shard-tglb: NOTRUN -> [TIMEOUT][16] ([i915#1729]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/shard-tglb3/igt@gem_exec_re...@basic-parallel.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#1610] / [i915#2803]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-glk9/igt@gem_exec_schedule@u-fairsl...@rcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/shard-glk4/igt@gem_exec_schedule@u-fairsl...@rcs0.html - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1610] / [i915#2803]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-skl6/igt@gem_exec_schedule@u-fairsl...@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/shard-skl2/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_exec_schedule@u-semaphore-codependency: - shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1610]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-skl8/igt@gem_exec_sched...@u-semaphore-codependency.html [22]:
[Intel-gfx] [PATCH] drm/i915/hdcp: Show connector hdcp capability
Show only connector hdcp capability in i915_display_info
instead of platform and sink.
There are some platforms which don't support HDCP 2.2
yet, those are not HDCP 2.2 capable but those platform
should show up the connector capability in i915_display_info.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index d62b18d5ecd8..8a028f943da5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -605,6 +605,7 @@ static void intel_panel_info(struct seq_file *m, struct
intel_panel *panel)
static void intel_hdcp_info(struct seq_file *m,
struct intel_connector *intel_connector)
{
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(intel_connector);
bool hdcp_cap, hdcp2_cap;
if (!intel_connector->hdcp.shim) {
@@ -613,7 +614,8 @@ static void intel_hdcp_info(struct seq_file *m,
}
hdcp_cap = intel_hdcp_capable(intel_connector);
- hdcp2_cap = intel_hdcp2_capable(intel_connector);
+ /* Sink's capability for HDCP2.2 */
+ intel_connector->hdcp.shim->hdcp_2_2_capable(dig_port, _cap);
if (hdcp_cap)
seq_puts(m, "HDCP1.4 ");
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add link rate and lane count to i915_display_info
== Series Details ==
Series: drm/i915: Add link rate and lane count to i915_display_info
URL : https://patchwork.freedesktop.org/series/86738/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9735 -> Patchwork_19600
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19600/index.html
Known issues
Here are the changes found in Patchwork_19600 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@sanitycheck:
- fi-kbl-7500u: [PASS][1] -> [DMESG-WARN][2] ([i915#2605])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19600/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar
issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19600/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
Possible fixes
* igt@fbdev@write:
- fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +2 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-tgl-y/igt@fb...@write.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19600/fi-tgl-y/igt@fb...@write.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-cfl-8700k: [DMESG-FAIL][7] ([i915#2291] / [i915#541]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-cfl-8700k/igt@i915_selftest@live@gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19600/fi-cfl-8700k/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@late_gt_pm:
- {fi-ehl-1}: [DMESG-FAIL][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-ehl-1/igt@i915_selftest@live@late_gt_pm.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19600/fi-ehl-1/igt@i915_selftest@live@late_gt_pm.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (42 -> 38)
--
Missing(4): fi-jsl-1 fi-ilk-m540 fi-bsw-cyan fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9735 -> Patchwork_19600
CI-20190529: 20190529
CI_DRM_9735: 186ea69ad1d026d004fbd64457fb576ab86556eb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5991: a2d9c45fca85918ecf4776120aade64b9220 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19600: affe26105adb63ca89125b501edad1ec70ea43a2 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
affe26105adb drm/i915: Add link rate and lane count to i915_display_info
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19600/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add link rate and lane count to i915_display_info
== Series Details == Series: drm/i915: Add link rate and lane count to i915_display_info URL : https://patchwork.freedesktop.org/series/86738/ State : warning == Summary == $ dim checkpatch origin/drm-tip affe26105adb drm/i915: Add link rate and lane count to i915_display_info -:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #9: Link rate and lane count information are more easier and faster to check in i915_display_info total: 0 errors, 1 warnings, 0 checks, 12 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: refactor intel_display.c + a bit more
== Series Details == Series: drm/i915: refactor intel_display.c + a bit more URL : https://patchwork.freedesktop.org/series/86723/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9732_full -> Patchwork_19594_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19594_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19594_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19594_full: ### IGT changes ### Possible regressions * igt@sysfs_clients@fair-1@vcs: - shard-kbl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-kbl2/igt@sysfs_clients@fai...@vcs.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/shard-kbl6/igt@sysfs_clients@fai...@vcs.html Known issues Here are the changes found in Patchwork_19594_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-tglb: NOTRUN -> [DMESG-WARN][3] ([i915#3002]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/shard-tglb1/igt@gem_cre...@create-massive.html * igt@gem_exec_balancer@hang: - shard-iclb: [PASS][4] -> [INCOMPLETE][5] ([i915#1895] / [i915#2295]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-iclb8/igt@gem_exec_balan...@hang.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/shard-iclb2/igt@gem_exec_balan...@hang.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-apl1/igt@gem_exec_fair@basic-n...@vecs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_params@secure-non-root: - shard-tglb: NOTRUN -> [SKIP][11] ([fdo#112283]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/shard-tglb5/igt@gem_exec_par...@secure-non-root.html * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-glk: [PASS][12] -> [FAIL][13] ([i915#2389]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-glk9/igt@gem_exec_reloc@basic-many-act...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/shard-glk4/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_exec_reloc@basic-parallel: - shard-tglb: NOTRUN -> [TIMEOUT][14] ([i915#1729]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/shard-tglb5/igt@gem_exec_re...@basic-parallel.html * igt@gem_exec_schedule@u-fairslice@bcs0: - shard-tglb: [PASS][15] -> [DMESG-WARN][16] ([i915#2803]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-tglb5/igt@gem_exec_schedule@u-fairsl...@bcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/shard-tglb7/igt@gem_exec_schedule@u-fairsl...@bcs0.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#1610]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-apl4/igt@gem_exec_schedule@u-fairsl...@rcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/shard-apl8/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_userptr_blits@readonly-mmap-unsync@wb: - shard-tglb: NOTRUN -> [SKIP][19] ([i915#1704]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/shard-tglb1/igt@gem_userptr_blits@readonly-mmap-uns...@wb.html * igt@gem_userptr_blits@readonly-unsync: - shard-tglb: NOTRUN -> [SKIP][20] ([fdo#110426] / [i915#1704]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/shard-tglb5/igt@gem_userptr_bl...@readonly-unsync.html * igt@gen3_render_mixed_blits: - shard-tglb: NOTRUN -> [SKIP][21] ([fdo#109289]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/shard-tglb5/igt@gen3_render_mixed_blits.html *
[Intel-gfx] [PATCH] drm/i915: Add link rate and lane count to i915_display_info
Link rate and lane count information are more easier and faster to check in i915_display_info than checking kernel logs for people not familiar with i915 in the following scenarios: * Debugging DP tunnel bandwidth usage in Thunderbolt driver. * In USB4 certification, it is a requirement to know which link rate used by monitor to prove that DP tunnel handle up to HBR3 * In PHY Compliance, when the connector propes are not mounted correctly, some display lanes will not show up in the DP Oscilloscope and will fail CTS. Just give the tester an easy way to identify where the problem is. Cc: Imre Deak Cc: Ville Syrjälä CC: José Roberto de Souza Signed-off-by: Khaled Almahallawy --- drivers/gpu/drm/i915/display/intel_display_debugfs.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index d62b18d5ecd8..c6161c1e87e9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -990,9 +990,10 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) yesno(crtc_state->hw.active), DRM_MODE_ARG(_state->hw.adjusted_mode)); - seq_printf(m, "\tpipe src size=%dx%d, dither=%s, bpp=%d\n", + seq_printf(m, "\tpipe src size=%dx%d, dither=%s, bpp=%d, link rate = %d, lane count = %d\n", crtc_state->pipe_src_w, crtc_state->pipe_src_h, - yesno(crtc_state->dither), crtc_state->pipe_bpp); + yesno(crtc_state->dither), crtc_state->pipe_bpp, + crtc_state->port_clock, crtc_state->lane_count); intel_scaler_info(m, crtc); } -- 2.25.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Reject 446-480MHz HDMI clock on GLK
> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, February 3, 2021 11:31 AM > To: intel-gfx@lists.freedesktop.org > Cc: sta...@vger.kernel.org > Subject: [Intel-gfx] [PATCH] drm/i915: Reject 446-480MHz HDMI clock on GLK > > From: Ville Syrjälä > > The BXT/GLK DPLL can't generate certain frequencies. We already reject the > 233-240MHz range on both. But on GLK the DPLL max frequency was > bumped from 300MHz to 594MHz, so now we get to also worry about the > 446-480MHz range (double the original problem range). Reject any frequency > within the higher problematic range as well. > > Cc: sta...@vger.kernel.org > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3000 > Signed-off-by: Ville Syrjälä Reviewed-by: Mika Kahola > --- > drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c > b/drivers/gpu/drm/i915/display/intel_hdmi.c > index 66e1ac3887c6..b593a71e6517 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c > @@ -2218,7 +2218,11 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, > has_hdmi_sink)) > return MODE_CLOCK_HIGH; > > - /* BXT DPLL can't generate 223-240 MHz */ > + /* GLK DPLL can't generate 446-480 MHz */ > + if (IS_GEMINILAKE(dev_priv) && clock > 44 && clock < 48) > + return MODE_CLOCK_RANGE; > + > + /* BXT/GLK DPLL can't generate 223-240 MHz */ > if (IS_GEN9_LP(dev_priv) && clock > 22 && clock < 24) > return MODE_CLOCK_RANGE; > > -- > 2.26.2 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Clean up the DDI clock routing mess (rev2)
== Series Details == Series: drm/i915: Clean up the DDI clock routing mess (rev2) URL : https://patchwork.freedesktop.org/series/86544/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9732_full -> Patchwork_19593_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19593_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19593_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19593_full: ### IGT changes ### Possible regressions * igt@kms_flip_tiling@flip-yf-tiled@edp-1-pipe-c: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-skl4/igt@kms_flip_tiling@flip-yf-ti...@edp-1-pipe-c.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/shard-skl2/igt@kms_flip_tiling@flip-yf-ti...@edp-1-pipe-c.html Known issues Here are the changes found in Patchwork_19593_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-apl7/igt@gem_ctx_isolation@preservation...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/shard-apl4/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][5] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_params@secure-non-root: - shard-tglb: NOTRUN -> [SKIP][6] ([fdo#112283]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/shard-tglb8/igt@gem_exec_par...@secure-non-root.html * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2389]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-glk9/igt@gem_exec_reloc@basic-many-act...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/shard-glk4/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_exec_reloc@basic-parallel: - shard-tglb: NOTRUN -> [TIMEOUT][9] ([i915#1729]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/shard-tglb8/igt@gem_exec_re...@basic-parallel.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#1610]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-apl4/igt@gem_exec_schedule@u-fairsl...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/shard-apl3/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_userptr_blits@readonly-unsync: - shard-tglb: NOTRUN -> [SKIP][12] ([fdo#110426] / [i915#1704]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/shard-tglb8/igt@gem_userptr_bl...@readonly-unsync.html * igt@gen3_render_mixed_blits: - shard-tglb: NOTRUN -> [SKIP][13] ([fdo#109289]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/shard-tglb8/igt@gen3_render_mixed_blits.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][14] -> [DMESG-WARN][15] ([i915#1436] / [i915#716]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-skl2/igt@gen9_exec_pa...@allowed-single.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/shard-skl9/igt@gen9_exec_pa...@allowed-single.html * igt@gen9_exec_parse@bb-chained: - shard-tglb: NOTRUN -> [SKIP][16] ([fdo#112306]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/shard-tglb8/igt@gen9_exec_pa...@bb-chained.html * igt@i915_pm_backlight@bad-brightness: - shard-glk: NOTRUN -> [SKIP][17] ([fdo#109271]) +50 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/shard-glk6/igt@i915_pm_backli...@bad-brightness.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [PASS][18] -> [FAIL][19] ([i915#2521]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-skl1/igt@kms_async_fl...@alternate-sync-async-flip.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/shard-skl2/igt@kms_async_fl...@alternate-sync-async-flip.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: NOTRUN -> [FAIL][20] ([i915#2597]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/shard-tglb8/igt@kms_async_fl...@test-time-stamp.html *
Re: [Intel-gfx] [PATCH] drm/i915: Make psr_safest_params and enable_psr2_sel_fetch parameters read only
Reviewed-by: Gwan-gyeong Mun On Thu, 2021-02-04 at 07:33 -0800, José Roberto de Souza wrote: > By mistake those 2 parameters were defined as read and write in the > .h file while in the .c file it is read only. > The intention here was to be read only to avoid the need of > additional > handling. > > Cc: Gwan-gyeong Mun > Cc: Petri Latvala > Signed-off-by: José Roberto de Souza > --- > drivers/gpu/drm/i915/i915_params.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_params.h > b/drivers/gpu/drm/i915/i915_params.h > index f031966af5b7..48f47e44e848 100644 > --- a/drivers/gpu/drm/i915/i915_params.h > +++ b/drivers/gpu/drm/i915/i915_params.h > @@ -54,8 +54,8 @@ struct drm_printer; > param(int, enable_dc, -1, 0400) \ > param(int, enable_fbc, -1, 0600) \ > param(int, enable_psr, -1, 0600) \ > - param(bool, psr_safest_params, false, 0600) \ > - param(bool, enable_psr2_sel_fetch, false, 0600) \ > + param(bool, psr_safest_params, false, 0400) \ > + param(bool, enable_psr2_sel_fetch, false, 0400) \ > param(int, disable_power_well, -1, 0400) \ > param(int, enable_ips, 1, 0600) \ > param(int, invert_brightness, 0, 0600) \ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Remove PSR2 on JSL and EHL
== Series Details == Series: drm/i915/display: Remove PSR2 on JSL and EHL URL : https://patchwork.freedesktop.org/series/86714/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9732_full -> Patchwork_19592_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19592_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19592_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19592_full: ### IGT changes ### Possible regressions * igt@kms_flip@2x-flip-vs-suspend@bc-vga1-hdmi-a1: - shard-hsw: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-hsw7/igt@kms_flip@2x-flip-vs-susp...@bc-vga1-hdmi-a1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/shard-hsw2/igt@kms_flip@2x-flip-vs-susp...@bc-vga1-hdmi-a1.html * igt@kms_flip_tiling@flip-yf-tiled@edp-1-pipe-c: - shard-skl: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-skl4/igt@kms_flip_tiling@flip-yf-ti...@edp-1-pipe-c.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/shard-skl4/igt@kms_flip_tiling@flip-yf-ti...@edp-1-pipe-c.html Known issues Here are the changes found in Patchwork_19592_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-tglb: NOTRUN -> [DMESG-WARN][5] ([i915#3002]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/shard-tglb2/igt@gem_cre...@create-massive.html * igt@gem_exec_fair@basic-none@rcs0: - shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-kbl7/igt@gem_exec_fair@basic-n...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/shard-kbl6/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_params@secure-non-root: - shard-tglb: NOTRUN -> [SKIP][10] ([fdo#112283]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/shard-tglb3/igt@gem_exec_par...@secure-non-root.html * igt@gem_exec_reloc@basic-parallel: - shard-tglb: NOTRUN -> [TIMEOUT][11] ([i915#1729]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/shard-tglb3/igt@gem_exec_re...@basic-parallel.html * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][12] ([i915#2389]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/shard-iclb1/igt@gem_exec_reloc@basic-wide-act...@vcs1.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#1610] / [i915#2803]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-kbl1/igt@gem_exec_schedule@u-fairsl...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/shard-kbl2/igt@gem_exec_schedule@u-fairsl...@rcs0.html - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#1610] / [i915#2803]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-glk9/igt@gem_exec_schedule@u-fairsl...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/shard-glk3/igt@gem_exec_schedule@u-fairsl...@rcs0.html - shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([i915#2803]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-iclb8/igt@gem_exec_schedule@u-fairsl...@rcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/shard-iclb6/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_userptr_blits@readonly-mmap-unsync@wb: - shard-tglb: NOTRUN -> [SKIP][19] ([i915#1704]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/shard-tglb2/igt@gem_userptr_blits@readonly-mmap-uns...@wb.html * igt@gem_userptr_blits@readonly-unsync: - shard-tglb: NOTRUN -> [SKIP][20] ([fdo#110426] / [i915#1704]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/shard-tglb3/igt@gem_userptr_bl...@readonly-unsync.html * igt@gen3_render_mixed_blits: - shard-tglb: NOTRUN -> [SKIP][21] ([fdo#109289]) [21]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Ratelimit heartbeat completion probing (rev3)
== Series Details ==
Series: drm/i915/gt: Ratelimit heartbeat completion probing (rev3)
URL : https://patchwork.freedesktop.org/series/86665/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9735 -> Patchwork_19599
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19599 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19599, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19599/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19599:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gt_heartbeat:
- fi-hsw-4770:[PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-hsw-4770/igt@i915_selftest@live@gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19599/fi-hsw-4770/igt@i915_selftest@live@gt_heartbeat.html
- fi-snb-2600:[PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-snb-2600/igt@i915_selftest@live@gt_heartbeat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19599/fi-snb-2600/igt@i915_selftest@live@gt_heartbeat.html
- fi-ivb-3770:[PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-ivb-3770/igt@i915_selftest@live@gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19599/fi-ivb-3770/igt@i915_selftest@live@gt_heartbeat.html
- fi-snb-2520m: [PASS][7] -> [DMESG-FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-snb-2520m/igt@i915_selftest@live@gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19599/fi-snb-2520m/igt@i915_selftest@live@gt_heartbeat.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@execlists:
- {fi-rkl-11500t}:[PASS][9] -> [INCOMPLETE][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-rkl-11500t/igt@i915_selftest@l...@execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19599/fi-rkl-11500t/igt@i915_selftest@l...@execlists.html
- {fi-ehl-1}: [PASS][11] -> [INCOMPLETE][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-ehl-1/igt@i915_selftest@l...@execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19599/fi-ehl-1/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@gt_heartbeat:
- {fi-hsw-gt1}: [PASS][13] -> [DMESG-FAIL][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-hsw-gt1/igt@i915_selftest@live@gt_heartbeat.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19599/fi-hsw-gt1/igt@i915_selftest@live@gt_heartbeat.html
- {fi-ehl-1}: [PASS][15] -> [DMESG-FAIL][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-ehl-1/igt@i915_selftest@live@gt_heartbeat.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19599/fi-ehl-1/igt@i915_selftest@live@gt_heartbeat.html
- {fi-rkl-11500t}:[PASS][17] -> [DMESG-FAIL][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-rkl-11500t/igt@i915_selftest@live@gt_heartbeat.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19599/fi-rkl-11500t/igt@i915_selftest@live@gt_heartbeat.html
Known issues
Here are the changes found in Patchwork_19599 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-byt-j1900: NOTRUN -> [SKIP][19] ([fdo#109271]) +27 similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19599/fi-byt-j1900/igt@gem_huc_c...@huc-copy.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][20] -> [FAIL][21] ([i915#2203] / [i915#579])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-kbl-guc/igt@i915_pm_...@module-reload.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19599/fi-kbl-guc/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@execlists:
- fi-kbl-r: [PASS][22] -> [INCOMPLETE][23] ([i915#1037] /
[i915#794])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-kbl-r/igt@i915_selftest@l...@execlists.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19599/fi-kbl-r/igt@i915_selftest@l...@execlists.html
- fi-cfl-8109u: [PASS][24] -> [INCOMPLETE][25] ([i915#1037])
[24]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Make psr_safest_params and enable_psr2_sel_fetch parameters read only
== Series Details == Series: drm/i915: Make psr_safest_params and enable_psr2_sel_fetch parameters read only URL : https://patchwork.freedesktop.org/series/86710/ State : success == Summary == CI Bug Log - changes from CI_DRM_9732_full -> Patchwork_19591_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19591_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-tglb: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/shard-tglb3/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-apl: [PASS][2] -> [DMESG-WARN][3] ([i915#180]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-apl7/igt@gem_ctx_isolation@preservation...@bcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/shard-apl8/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_exec_balancer@hang: - shard-iclb: [PASS][4] -> [INCOMPLETE][5] ([i915#1895] / [i915#2295]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-iclb8/igt@gem_exec_balan...@hang.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/shard-iclb4/igt@gem_exec_balan...@hang.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/shard-tglb6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_params@secure-non-root: - shard-tglb: NOTRUN -> [SKIP][11] ([fdo#112283]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/shard-tglb5/igt@gem_exec_par...@secure-non-root.html * igt@gem_exec_reloc@basic-parallel: - shard-tglb: NOTRUN -> [TIMEOUT][12] ([i915#1729]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/shard-tglb5/igt@gem_exec_re...@basic-parallel.html * igt@gem_exec_whisper@basic-fds: - shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#118] / [i915#95]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-glk6/igt@gem_exec_whis...@basic-fds.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/shard-glk6/igt@gem_exec_whis...@basic-fds.html * igt@gem_userptr_blits@readonly-mmap-unsync@wb: - shard-tglb: NOTRUN -> [SKIP][15] ([i915#1704]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/shard-tglb3/igt@gem_userptr_blits@readonly-mmap-uns...@wb.html * igt@gem_userptr_blits@readonly-unsync: - shard-tglb: NOTRUN -> [SKIP][16] ([fdo#110426] / [i915#1704]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/shard-tglb5/igt@gem_userptr_bl...@readonly-unsync.html * igt@gen3_render_mixed_blits: - shard-tglb: NOTRUN -> [SKIP][17] ([fdo#109289]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/shard-tglb5/igt@gen3_render_mixed_blits.html * igt@gen9_exec_parse@allowed-all: - shard-skl: [PASS][18] -> [DMESG-WARN][19] ([i915#1436] / [i915#716]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-skl7/igt@gen9_exec_pa...@allowed-all.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/shard-skl6/igt@gen9_exec_pa...@allowed-all.html * igt@gen9_exec_parse@bb-chained: - shard-tglb: NOTRUN -> [SKIP][20] ([fdo#112306]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/shard-tglb5/igt@gen9_exec_pa...@bb-chained.html * igt@i915_pm_rc6_residency@rc6-fence: - shard-hsw: [PASS][21] -> [WARN][22] ([i915#1519]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-hsw7/igt@i915_pm_rc6_reside...@rc6-fence.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/shard-hsw8/igt@i915_pm_rc6_reside...@rc6-fence.html * igt@i915_selftest@live@hangcheck: - shard-hsw: [PASS][23] -> [INCOMPLETE][24] ([i915#2782]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-hsw8/igt@i915_selftest@l...@hangcheck.html [24]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl, tgl: whitelist COMMON_SLICE_CHICKEN3 register
== Series Details ==
Series: drm/i915/icl, tgl: whitelist COMMON_SLICE_CHICKEN3 register
URL : https://patchwork.freedesktop.org/series/86733/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9735 -> Patchwork_19598
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19598/index.html
Known issues
Here are the changes found in Patchwork_19598 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#2411] /
[i915#402])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19598/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
* igt@gem_mmap_gtt@basic:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar
issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-tgl-y/igt@gem_mmap_...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19598/fi-tgl-y/igt@gem_mmap_...@basic.html
Possible fixes
* igt@fbdev@write:
- fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +2 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-tgl-y/igt@fb...@write.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19598/fi-tgl-y/igt@fb...@write.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-cfl-8700k: [DMESG-FAIL][7] ([i915#2291] / [i915#541]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-cfl-8700k/igt@i915_selftest@live@gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19598/fi-cfl-8700k/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@late_gt_pm:
- {fi-ehl-1}: [DMESG-FAIL][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-ehl-1/igt@i915_selftest@live@late_gt_pm.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19598/fi-ehl-1/igt@i915_selftest@live@late_gt_pm.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (42 -> 38)
--
Missing(4): fi-jsl-1 fi-ilk-m540 fi-bsw-cyan fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9735 -> Patchwork_19598
CI-20190529: 20190529
CI_DRM_9735: 186ea69ad1d026d004fbd64457fb576ab86556eb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5991: a2d9c45fca85918ecf4776120aade64b9220 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19598: d11d4136e3d72e8f2fa870186d33a966996ac863 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d11d4136e3d7 drm/i915/icl, tgl: whitelist COMMON_SLICE_CHICKEN3 register
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19598/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftest: Synchronise with the GPU timestamp
== Series Details ==
Series: drm/i915/selftest: Synchronise with the GPU timestamp
URL : https://patchwork.freedesktop.org/series/86731/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9735 -> Patchwork_19597
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19597 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19597, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19597/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19597:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gt_engines:
- fi-bsw-nick:[PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-bsw-nick/igt@i915_selftest@live@gt_engines.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19597/fi-bsw-nick/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19597/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
Known issues
Here are the changes found in Patchwork_19597 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +2 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19597/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [PASS][7] -> [FAIL][8] ([i915#1888])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19597/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
* igt@gem_huc_copy@huc-copy:
- fi-byt-j1900: NOTRUN -> [SKIP][9] ([fdo#109271]) +9 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19597/fi-byt-j1900/igt@gem_huc_c...@huc-copy.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: NOTRUN -> [INCOMPLETE][10] ([i915#142] / [i915#2405])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19597/fi-byt-j1900/igt@i915_pm_...@module-reload.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-byt-j1900: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19597/fi-byt-j1900/igt@kms_chamel...@hdmi-crc-fast.html
* igt@runner@aborted:
- fi-kbl-guc: NOTRUN -> [FAIL][12] ([i915#2426])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19597/fi-kbl-guc/igt@run...@aborted.html
- fi-byt-j1900: NOTRUN -> [FAIL][13] ([i915#1814] / [i915#2505])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19597/fi-byt-j1900/igt@run...@aborted.html
- fi-bsw-n3050: NOTRUN -> [FAIL][14] ([i915#1436])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19597/fi-bsw-n3050/igt@run...@aborted.html
Possible fixes
* igt@fbdev@write:
- fi-tgl-y: [DMESG-WARN][15] ([i915#402]) -> [PASS][16] +2
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-tgl-y/igt@fb...@write.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19597/fi-tgl-y/igt@fb...@write.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-cfl-8700k: [DMESG-FAIL][17] ([i915#2291] / [i915#541]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-cfl-8700k/igt@i915_selftest@live@gt_heartbeat.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19597/fi-cfl-8700k/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@late_gt_pm:
- {fi-ehl-1}: [DMESG-FAIL][19] -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9735/fi-ehl-1/igt@i915_selftest@live@late_gt_pm.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19597/fi-ehl-1/igt@i915_selftest@live@late_gt_pm.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#142]:
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v15,1/2] drm/i915/display: Support PSR Multiple Instances
== Series Details ==
Series: series starting with [v15,1/2] drm/i915/display: Support PSR Multiple
Instances
URL : https://patchwork.freedesktop.org/series/86701/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9732_full -> Patchwork_19590_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19590_full:
### Piglit changes ###
Possible regressions
* spec@arb_tessellation_shader@execution@tcs-input@tcs-input-mat4x2_2 (NEW):
- {pig-icl-1065g7}: NOTRUN -> [CRASH][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/pig-icl-1065g7/spec@arb_tessellation_shader@execution@tcs-input@tcs-input-mat4x2_2.html
* spec@arb_tessellation_shader@execution@tcs-input@tcs-input-mat4x3 (NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][2] +7 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/pig-icl-1065g7/spec@arb_tessellation_shader@execution@tcs-in...@tcs-input-mat4x3.html
New tests
-
New tests have been introduced between CI_DRM_9732_full and
Patchwork_19590_full:
### New Piglit tests (9) ###
* spec@arb_tessellation_shader@execution@tcs-input@tcs-input-ivec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@tcs-input@tcs-input-mat2x4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@tcs-input@tcs-input-mat3_2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@tcs-input@tcs-input-mat4x2_2:
- Statuses : 1 crash(s)
- Exec time: [0.53] s
* spec@arb_tessellation_shader@execution@tcs-input@tcs-input-mat4x3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@tcs-input@tcs-input-uint:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@tcs-input@tcs-input-uvec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@tcs-input@tcs-input-uvec4_2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_tessellation_shader@execution@tcs-input@tcs-input-vec2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_19590_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_create@create-massive:
- shard-tglb: NOTRUN -> [DMESG-WARN][3] ([i915#3002])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/shard-tglb1/igt@gem_cre...@create-massive.html
* igt@gem_exec_balancer@hang:
- shard-iclb: [PASS][4] -> [INCOMPLETE][5] ([i915#1895] /
[i915#2295] / [i915#3031])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-iclb8/igt@gem_exec_balan...@hang.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/shard-iclb2/igt@gem_exec_balan...@hang.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_params@secure-non-root:
- shard-tglb: NOTRUN -> [SKIP][9] ([fdo#112283])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/shard-tglb7/igt@gem_exec_par...@secure-non-root.html
* igt@gem_exec_reloc@basic-parallel:
- shard-tglb: NOTRUN -> [TIMEOUT][10] ([i915#1729])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/shard-tglb7/igt@gem_exec_re...@basic-parallel.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#1610] /
[i915#2803])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-glk9/igt@gem_exec_schedule@u-fairsl...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/shard-glk4/igt@gem_exec_schedule@u-fairsl...@rcs0.html
* igt@gem_pipe_control_store_loop@reused-buffer:
- shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#118] /
[i915#95])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-glk7/igt@gem_pipe_control_store_l...@reused-buffer.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/shard-glk2/igt@gem_pipe_control_store_l...@reused-buffer.html
* igt@gem_userptr_blits@readonly-mmap-unsync@wb:
-
[Intel-gfx] ✗ Fi.CI.IGT: failure for swiotlb: 64-bit DMA buffer
== Series Details ==
Series: swiotlb: 64-bit DMA buffer
URL : https://patchwork.freedesktop.org/series/86700/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9732_full -> Patchwork_19589_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19589_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19589_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_19589_full:
### IGT changes ###
Possible regressions
* igt@kms_flip@2x-flip-vs-suspend@bc-vga1-hdmi-a1:
- shard-hsw: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-hsw7/igt@kms_flip@2x-flip-vs-susp...@bc-vga1-hdmi-a1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19589/shard-hsw4/igt@kms_flip@2x-flip-vs-susp...@bc-vga1-hdmi-a1.html
### Piglit changes ###
Possible regressions
* spec@glsl-4.30@execution@built-in-functions@cs-op-lshift-uvec4-int (NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][3] +7 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19589/pig-icl-1065g7/spec@glsl-4.30@execution@built-in-functi...@cs-op-lshift-uvec4-int.html
New tests
-
New tests have been introduced between CI_DRM_9732_full and
Patchwork_19589_full:
### New Piglit tests (8) ###
* spec@glsl-4.30@execution@built-in-functions@cs-mix-vec3-vec3-bvec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-4.30@execution@built-in-functions@cs-op-bitor-not-int-ivec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-4.30@execution@built-in-functions@cs-op-bitxor-neg-ivec3-ivec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-4.30@execution@built-in-functions@cs-op-div-mat4-mat4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-4.30@execution@built-in-functions@cs-op-lshift-uvec4-int:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-4.30@execution@built-in-functions@cs-op-mult-vec4-float:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@glsl-4.30@execution@built-in-functions@cs-op-selection-bool-float-float:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@glsl-4.30@execution@built-in-functions@cs-op-selection-bool-vec4-vec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_19589_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_create@create-massive:
- shard-tglb: NOTRUN -> [DMESG-WARN][4] ([i915#3002])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19589/shard-tglb3/igt@gem_cre...@create-massive.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-kbl: [PASS][5] -> [SKIP][6] ([fdo#109271])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-kbl1/igt@gem_exec_fair@basic-f...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19589/shard-kbl6/igt@gem_exec_fair@basic-f...@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19589/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_params@secure-non-root:
- shard-tglb: NOTRUN -> [SKIP][9] ([fdo#112283])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19589/shard-tglb7/igt@gem_exec_par...@secure-non-root.html
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-glk: [PASS][10] -> [FAIL][11] ([i915#2389])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/shard-glk9/igt@gem_exec_reloc@basic-many-act...@rcs0.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19589/shard-glk2/igt@gem_exec_reloc@basic-many-act...@rcs0.html
* igt@gem_exec_reloc@basic-parallel:
- shard-tglb: NOTRUN -> [TIMEOUT][12] ([i915#1729])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19589/shard-tglb7/igt@gem_exec_re...@basic-parallel.html
* igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2389])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19589/shard-iclb1/igt@gem_exec_reloc@basic-wide-act...@vcs1.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-tglb: [PASS][14] -> [DMESG-WARN][15] ([i915#2803])
[14]:
[Intel-gfx] [PATCH] drm/i915/gt: Ratelimit heartbeat completion probing
The heartbeat runs through a few phases that we expect to complete
within a certain number of heartbeat intervals. First we must submit the
heartbeat to the queue, and if the queue is occupied it may take a
couple of intervals before the heartbeat preempts the workload and is
submitted to HW. Once running on HW, completion is not instantaneous as
it may have to first reset the current workload before it itself runs
through the empty request and signals completion. As such, we know that
the heartbeat must take at least the preempt reset timeout and before we
have had a chance to reset the engine, we do not want to issue a global
reset ourselves (simply so that we only try to do one reset at a time
and not confuse ourselves by resetting twice and hitting an innocent.)
So by taking into consideration that once running the request must take
a finite amount of time, we can delay the final completion check to
accommodate that and avoid checking too early (before we've had a chance
to handle any engine resets required).
v2: Attach a callback to flush the work immediately upon the heartbeat
completion and insert the delay before the next.
Suggested-by: CQ Tang
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 85 +--
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
.../drm/i915/gt/selftest_engine_heartbeat.c | 30 +--
3 files changed, 99 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index 93741a65924a..3df10bfafb3b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -20,6 +20,18 @@
* issue a reset -- in the hope that restores progress.
*/
+#define HEARTBEAT_COMPLETION 50u /* milliseconds */
+
+static long completion_timeout(const struct intel_engine_cs *engine)
+{
+ long timeout = HEARTBEAT_COMPLETION;
+
+ if (intel_engine_has_preempt_reset(engine))
+ timeout += READ_ONCE(engine->props.preempt_timeout_ms);
+
+ return msecs_to_jiffies(timeout);
+}
+
static bool next_heartbeat(struct intel_engine_cs *engine)
{
long delay;
@@ -29,6 +41,28 @@ static bool next_heartbeat(struct intel_engine_cs *engine)
return false;
delay = msecs_to_jiffies_timeout(delay);
+
+ /*
+* Once we submit a heartbeat to the HW, we know that it will take
+* at least a certain amount of time to complete. On a hanging system
+* it will first have to wait for the preempt reset timeout, and
+* then it will take some time for the reset to resume with the
+* heartbeat and for it to complete. So once we have submitted the
+* heartbeat to HW, we can wait a while longer before declaring the
+* engine stuck and forcing a reset ourselves. If we do a reset
+* and the engine is also doing a reset, it is possible that we
+* reset the engine twice, harming an innocent.
+*
+* Before we have sumitted the heartbeat, we do not want to change
+* the interval as we to promote the heartbeat and trigger preemption
+* in a deterministic time frame.
+*/
+ if (engine->heartbeat.systole) {
+ intel_engine_flush_submission(engine);
+ if (i915_request_is_active(engine->heartbeat.systole))
+ delay = max(delay, completion_timeout(engine));
+ }
+
if (delay >= HZ)
delay = round_jiffies_up_relative(delay);
mod_delayed_work(system_highpri_wq, >heartbeat.work, delay + 1);
@@ -48,12 +82,44 @@ heartbeat_create(struct intel_context *ce, gfp_t gfp)
return rq;
}
+static void defibrillator(struct dma_fence *f, struct dma_fence_cb *cb)
+{
+ struct intel_engine_cs *engine =
+ container_of(cb, typeof(*engine), heartbeat.cb);
+
+ if (READ_ONCE(engine->heartbeat.systole))
+ mod_delayed_work(system_highpri_wq, >heartbeat.work, 0);
+}
+
+static void
+track_heartbeat(struct intel_engine_cs *engine, struct i915_request *rq)
+{
+ engine->heartbeat.systole = i915_request_get(rq);
+ if (dma_fence_add_callback(>fence,
+ >heartbeat.cb,
+ defibrillator))
+ mod_delayed_work(system_highpri_wq, >heartbeat.work, 0);
+}
+
+static void
+untrack_heartbeat(struct intel_engine_cs *engine)
+{
+ struct i915_request *rq;
+
+ rq = fetch_and_zero(>heartbeat.systole);
+ if (!rq)
+ return;
+
+ dma_fence_remove_callback(>fence, >heartbeat.cb);
+ i915_request_put(rq);
+}
+
static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq)
{
engine->wakeref_serial = READ_ONCE(engine->serial) + 1;
i915_request_add_active_barriers(rq);
if (!engine->heartbeat.systole &&
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/selftests: Restore previous heartbeat interval
== Series Details == Series: series starting with [CI,1/2] drm/i915/selftests: Restore previous heartbeat interval URL : https://patchwork.freedesktop.org/series/86727/ State : success == Summary == CI Bug Log - changes from CI_DRM_9733 -> Patchwork_19596 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19596/index.html Known issues Here are the changes found in Patchwork_19596 that come from known issues: ### IGT changes ### Issues hit * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9733/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19596/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][3] ([i915#402]) -> [PASS][4] +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9733/fi-tgl-y/igt@debugfs_test@read_all_entries.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19596/fi-tgl-y/igt@debugfs_test@read_all_entries.html [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 39) -- Missing(4): fi-jsl-1 fi-ilk-m540 fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9733 -> Patchwork_19596 CI-20190529: 20190529 CI_DRM_9733: 0f9f63f17287af66109d2a765ec810989b4ebe16 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5991: a2d9c45fca85918ecf4776120aade64b9220 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19596: a8f6d642536b2362f21f0dad075449fbb3c573b7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a8f6d642536b drm/i915/gt: Double check heartbeat timeout before resetting 9b100da03974 drm/i915/selftests: Restore previous heartbeat interval == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19596/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftest: Synchronise with the GPU timestamp
> Wait for the GPU to wake up from the semaphore before measuring the >time, so that we coordinate the sampling on both the CPU and GPU for > more accurate comparisons. > >Reported-by: Bruce Chang > Signed-off-by: Chris Wilson > Cc: CQ Tang > --- > drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c >index 3ce8cb3329f3..007a7c790778 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > @@ -111,8 +111,10 @@ static int __measure_timestamps(struct intel_context *ce, > > /* Run the request for a 100us, sampling timestamps before/after */ > preempt_disable(); > - *dt = local_clock(); > write_semaphore([2], 0); > + while (READ_ONCE(sema[1]) == 0) /* wait for the gpu to catch up */ > + cpu_relax(); > + *dt = local_clock(); > udelay(100); > *dt = local_clock() - *dt; > write_semaphore([2], 1); > -- >2.20.1 > This trick should work! Thanks! Reviewed-by: Bruce Chang ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/icl, tgl: whitelist COMMON_SLICE_CHICKEN3 register
Adding this register to whitelist will allow UMD to toggle State Cache Perf fix disable chicken bit. "If this bit is enabled, RCC uses BTP+BTI as address tag in its state cache instead of BTI only" which will lead to dropping unnecessary render target flushes and stall on scoreboard. Bspec: 11333 Bspec: 45829 Signed-off-by: Sagar Ghuge --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 53f7838bd3c4..318302475c28 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1473,6 +1473,9 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) /* WaEnableStateCacheRedirectToCS:icl */ whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); + /* WaAllowToDisableStateCachePerfFixFromUMD:icl */ + whitelist_reg(w, GEN11_COMMON_SLICE_CHICKEN3); + /* * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl * @@ -1533,6 +1536,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine) /* Wa_1808121037:tgl */ whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); + /* WaAllowToDisableStateCachePerfFixFromUMD:tgl */ + whitelist_reg(w, GEN11_COMMON_SLICE_CHICKEN3); + /* Wa_1806527549:tgl */ whitelist_reg(w, HIZ_CHICKEN); break; -- 2.29.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftest: Synchronise with the GPU timestamp
Wait for the GPU to wake up from the semaphore before measuring the time, so that we coordinate the sampling on both the CPU and GPU for more accurate comparisons. Reported-by: Bruce Chang Signed-off-by: Chris Wilson Cc: CQ Tang --- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index 3ce8cb3329f3..007a7c790778 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -111,8 +111,10 @@ static int __measure_timestamps(struct intel_context *ce, /* Run the request for a 100us, sampling timestamps before/after */ preempt_disable(); - *dt = local_clock(); write_semaphore([2], 0); + while (READ_ONCE(sema[1]) == 0) /* wait for the gpu to catch up */ + cpu_relax(); + *dt = local_clock(); udelay(100); *dt = local_clock() - *dt; write_semaphore([2], 1); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: support ddr5 mem types
== Series Details == Series: drm/i915/display: support ddr5 mem types URL : https://patchwork.freedesktop.org/series/86726/ State : success == Summary == CI Bug Log - changes from CI_DRM_9732 -> Patchwork_19595 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/index.html Known issues Here are the changes found in Patchwork_19595 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_flink_basic@bad-flink: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html Possible fixes * igt@i915_selftest@live@execlists: - fi-bsw-nick:[INCOMPLETE][4] ([i915#2940]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@prime_vgem@basic-read: - fi-tgl-y: [DMESG-WARN][6] ([i915#402]) -> [PASS][7] +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-y/igt@prime_v...@basic-read.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/fi-tgl-y/igt@prime_v...@basic-read.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 39) -- Missing(4): fi-jsl-1 fi-ilk-m540 fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9732 -> Patchwork_19595 CI-20190529: 20190529 CI_DRM_9732: adb75f6f105d29ef75c1c8547db6259cad2092df @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5991: a2d9c45fca85918ecf4776120aade64b9220 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19595: a83ab36bcc5af2cf1ddfd181707b0e6815473ed5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a83ab36bcc5a drm/i915/display: support ddr5 mem types == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19595/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: refactor intel_display.c + a bit more
== Series Details == Series: drm/i915: refactor intel_display.c + a bit more URL : https://patchwork.freedesktop.org/series/86723/ State : success == Summary == CI Bug Log - changes from CI_DRM_9732 -> Patchwork_19594 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/index.html Known issues Here are the changes found in Patchwork_19594 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_mmap_gtt@basic: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-y/igt@gem_mmap_...@basic.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/fi-tgl-y/igt@gem_mmap_...@basic.html Possible fixes * igt@i915_selftest@live@execlists: - fi-bsw-nick:[INCOMPLETE][4] ([i915#2940]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@prime_vgem@basic-read: - fi-tgl-y: [DMESG-WARN][6] ([i915#402]) -> [PASS][7] +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-y/igt@prime_v...@basic-read.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/fi-tgl-y/igt@prime_v...@basic-read.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 39) -- Missing(4): fi-jsl-1 fi-ilk-m540 fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9732 -> Patchwork_19594 CI-20190529: 20190529 CI_DRM_9732: adb75f6f105d29ef75c1c8547db6259cad2092df @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5991: a2d9c45fca85918ecf4776120aade64b9220 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19594: b222155f3f4eaeb6586e0ac52419cfd59fa2265a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b222155f3f4e drm/i915: move ddi pll state get to dpll mgr c29fac301e62 drm/i915: refactor skylake scaler code into new file. 44f33f127d85 drm/i915: migrate i9xx plane get config 95df1ee5c668 drm/i915: migrate pll enable/disable code to intel_dpll.[ch] 10dd41f58e61 drm/i915: move is_ccs_modifier to an inline ed9e74d3ed1e drm/i915: split fb scalable checks into g4x and skl versions d60dcb2389b8 drm/i915: move pipe update code into crtc. (v2) 73371d0509a6 drm/i915: migrate skl planes code new file (v5) dac5399f8947 drm/i915: migrate hsw fdi code to new file. 124144996ca6 drm/i915: refactor ddi translations into a separate file (v2) == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19594/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: refactor intel_display.c + a bit more
== Series Details == Series: drm/i915: refactor intel_display.c + a bit more URL : https://patchwork.freedesktop.org/series/86723/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:742:28: warning: symbol 'bdw_get_buf_trans_edp' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:756:28: warning: symbol 'skl_get_buf_trans_dp' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:773:28: warning: symbol 'kbl_get_buf_trans_dp' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:794:28: warning: symbol 'skl_get_buf_trans_edp' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:826:28: warning: symbol 'skl_get_buf_trans_hdmi' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:841:5: warning: symbol 'skl_buf_trans_num_entries' was not declared. Should it be static? +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: refactor intel_display.c + a bit more
== Series Details ==
Series: drm/i915: refactor intel_display.c + a bit more
URL : https://patchwork.freedesktop.org/series/86723/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
124144996ca6 drm/i915: refactor ddi translations into a separate file (v2)
-:1525: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#1525:
new file mode 100644
-:1793: CHECK:LINE_SPACING: Please don't use multiple blank lines
#1793: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:264:
+
+
-:2279: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2279: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:750:
+ return bdw_ddi_translations_edp;
+ } else {
-:2296: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2296: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:767:
+ return skl_u_ddi_translations_dp;
+ } else {
-:2317: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2317: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:788:
+ return kbl_u_ddi_translations_dp;
+ } else {
-:2341: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2341: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:812:
+ return skl_u_ddi_translations_edp;
+ } else {
-:2364: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2364: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:835:
+ return skl_y_ddi_translations_hdmi;
+ } else {
-:2519: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2519: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:990:
+ return cnl_ddi_translations_hdmi_1_05V;
+ } else {
-:2541: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2541: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1012:
+ return cnl_ddi_translations_dp_1_05V;
+ } else {
-:2564: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2564: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1035:
+ return cnl_ddi_translations_edp_1_05V;
+ } else {
-:2658: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2658: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1129:
+ return icl_mg_phy_ddi_translations_hbr2_hbr3;
+ } else {
-:2750: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2750: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1221:
+ return jsl_combo_phy_ddi_translations_edp_hbr2;
+ } else {
-:2795: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2795: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1266:
+ return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
+ } else {
-:2803: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2803: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1274:
+ return rkl_combo_phy_ddi_translations_dp_hbr;
+ } else {
-:2862: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#2862: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1333:
+ return tgl_dkl_phy_dp_ddi_trans_hbr2;
+ } else {
total: 0 errors, 14 warnings, 1 checks, 2980 lines checked
dac5399f8947 drm/i915: migrate hsw fdi code to new file.
-:293: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#293: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:583:
+ FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) |
FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
-:301: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see
Documentation/timers/timers-howto.rst
#301: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:591:
+ udelay(220);
-:313: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a
separate line
#313: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:603:
+* testing each value twice. */
-:325: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a
separate line
#325: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:615:
+* port reversal bit */
-:327: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#327: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:617:
+ DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes -
1) << 1) | DDI_BUF_TRANS_SELECT(i / 2));
-:330: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see
Documentation/timers/timers-howto.rst
#330: FILE: drivers/gpu/drm/i915/display/intel_fdi.c:620:
+
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Clean up the DDI clock routing mess (rev2)
== Series Details ==
Series: drm/i915: Clean up the DDI clock routing mess (rev2)
URL : https://patchwork.freedesktop.org/series/86544/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9732 -> Patchwork_19593
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/index.html
Known issues
Here are the changes found in Patchwork_19593 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-bsw-nick:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [PASS][2] -> [INCOMPLETE][3] ([i915#2940])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y: [PASS][4] -> [DMESG-WARN][5] ([i915#402])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
* igt@runner@aborted:
- fi-bsw-n3050: NOTRUN -> [FAIL][6] ([i915#1436] / [i915#2722])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/fi-bsw-n3050/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[INCOMPLETE][7] ([i915#2940]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@prime_vgem@basic-read:
- fi-tgl-y: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +1 similar
issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-y/igt@prime_v...@basic-read.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/fi-tgl-y/igt@prime_v...@basic-read.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 38)
--
Missing(5): fi-jsl-1 fi-ilk-m540 fi-byt-j1900 fi-bsw-cyan fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9732 -> Patchwork_19593
CI-20190529: 20190529
CI_DRM_9732: adb75f6f105d29ef75c1c8547db6259cad2092df @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5991: a2d9c45fca85918ecf4776120aade64b9220 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19593: 3042cc386f808b0fbaab79f4a1dc54f0f03d947b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3042cc386f80 drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routing
68c071acd87d drm/i915: Relocate icl_sanitize_encoder_pll_mapping()
43bdf3bff434 drm/i915: Use .disable_clock() for pll sanitation
ad2ff2024cda drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable,
disable}_clock()
2c2cbb342e26 drm/i915: Extract _cnl_ddi_{enable, disable}_clock()
da8fa7f178d4 drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()
955b034d57a3 drm/i915: Sprinkle a few missing locks around shared DDI clock
registers
05feedf13562 drm/i915: Use intel_de_rmw() for DDI clock routing
6556f08b6691 drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs
818ed01c5517 drm/i915: Convert DG1 over to .{enable, disable}_clock()
ff375afcdf02 drm/i195: Extract cnl_ddi_{enable, disable}_clock()
370fdbea29e2 drm/i915: Extract skl_ddi_{enable, disable}_clock()
104612889762 drm/i915: Extract hsw_ddi_{enable, disable}_clock()
7a9a433648ec drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19593/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [RFC,1/3] proc: Show GPU runtimes
== Series Details == Series: series starting with [RFC,1/3] proc: Show GPU runtimes URL : https://patchwork.freedesktop.org/series/86693/ State : success == Summary == CI Bug Log - changes from CI_DRM_9730_full -> Patchwork_19587_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19587_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-glk: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/shard-glk8/igt@gem_cre...@create-massive.html - shard-apl: NOTRUN -> [DMESG-WARN][2] ([i915#3002]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/shard-apl7/igt@gem_cre...@create-massive.html * igt@gem_exec_fair@basic-none@rcs0: - shard-kbl: [PASS][3] -> [FAIL][4] ([i915#2842]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/shard-kbl7/igt@gem_exec_fair@basic-n...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/shard-kbl1/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][5] -> [SKIP][6] ([fdo#109271]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/shard-kbl7/igt@gem_exec_fair@basic-p...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/shard-kbl6/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_reloc@basic-many-active@vcs0: - shard-kbl: NOTRUN -> [FAIL][7] ([i915#2389]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/shard-kbl7/igt@gem_exec_reloc@basic-many-act...@vcs0.html * igt@gem_exec_reloc@basic-many-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][8] ([i915#2389]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/shard-iclb4/igt@gem_exec_reloc@basic-many-act...@vcs1.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-tglb: [PASS][9] -> [DMESG-WARN][10] ([i915#2803]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/shard-tglb1/igt@gem_exec_schedule@u-fairsl...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/shard-tglb6/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/shard-apl3/igt@gem_huc_c...@huc-copy.html * igt@gem_pread@exhaustion: - shard-skl: NOTRUN -> [WARN][12] ([i915#2658]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/shard-skl9/igt@gem_pr...@exhaustion.html * igt@gem_render_copy@yf-tiled-to-vebox-x-tiled: - shard-iclb: NOTRUN -> [SKIP][13] ([i915#768]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/shard-iclb3/igt@gem_render_c...@yf-tiled-to-vebox-x-tiled.html * igt@i915_pm_rc6_residency@rc6-fence: - shard-iclb: [PASS][14] -> [WARN][15] ([i915#1804] / [i915#2684]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/shard-iclb8/igt@i915_pm_rc6_reside...@rc6-fence.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/shard-iclb3/igt@i915_pm_rc6_reside...@rc6-fence.html * igt@kms_async_flips@test-time-stamp: - shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2574]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/shard-tglb6/igt@kms_async_fl...@test-time-stamp.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/shard-tglb7/igt@kms_async_fl...@test-time-stamp.html * igt@kms_big_fb@x-tiled-8bpp-rotate-270: - shard-iclb: NOTRUN -> [SKIP][18] ([fdo#110725] / [fdo#111614]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/shard-iclb3/igt@kms_big...@x-tiled-8bpp-rotate-270.html * igt@kms_big_joiner@basic: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2705]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/shard-kbl6/igt@kms_big_joi...@basic.html * igt@kms_big_joiner@invalid-modeset: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#2705]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/shard-apl3/igt@kms_big_joi...@invalid-modeset.html * igt@kms_chamelium@dp-mode-timings: - shard-glk: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/shard-glk8/igt@kms_chamel...@dp-mode-timings.html * igt@kms_chamelium@hdmi-hpd-with-enabled-mode: - shard-kbl: NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827]) +5 similar issues [22]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Clean up the DDI clock routing mess (rev2)
== Series Details == Series: drm/i915: Clean up the DDI clock routing mess (rev2) URL : https://patchwork.freedesktop.org/series/86544/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1323:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up the DDI clock routing mess (rev2)
== Series Details ==
Series: drm/i915: Clean up the DDI clock routing mess (rev2)
URL : https://patchwork.freedesktop.org/series/86544/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7a9a433648ec drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs
104612889762 drm/i915: Extract hsw_ddi_{enable, disable}_clock()
370fdbea29e2 drm/i915: Extract skl_ddi_{enable, disable}_clock()
ff375afcdf02 drm/i195: Extract cnl_ddi_{enable, disable}_clock()
818ed01c5517 drm/i915: Convert DG1 over to .{enable, disable}_clock()
6556f08b6691 drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#12:
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
total: 0 errors, 1 warnings, 0 checks, 232 lines checked
05feedf13562 drm/i915: Use intel_de_rmw() for DDI clock routing
955b034d57a3 drm/i915: Sprinkle a few missing locks around shared DDI clock
registers
da8fa7f178d4 drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()
2c2cbb342e26 drm/i915: Extract _cnl_ddi_{enable, disable}_clock()
ad2ff2024cda drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable,
disable}_clock()
43bdf3bff434 drm/i915: Use .disable_clock() for pll sanitation
68c071acd87d drm/i915: Relocate icl_sanitize_encoder_pll_mapping()
3042cc386f80 drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routing
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Remove PSR2 on JSL and EHL
== Series Details == Series: drm/i915/display: Remove PSR2 on JSL and EHL URL : https://patchwork.freedesktop.org/series/86714/ State : success == Summary == CI Bug Log - changes from CI_DRM_9732 -> Patchwork_19592 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/index.html Known issues Here are the changes found in Patchwork_19592 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_exec_suspend@basic-s3: - fi-skl-6700k2: [PASS][2] -> [INCOMPLETE][3] ([i915#198]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-skl-6700k2/igt@gem_exec_susp...@basic-s3.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/fi-skl-6700k2/igt@gem_exec_susp...@basic-s3.html - fi-tgl-y: [PASS][4] -> [DMESG-WARN][5] ([i915#2411] / [i915#402]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][6] -> [INCOMPLETE][7] ([i915#142] / [i915#2405]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-byt-j1900/igt@i915_pm_...@module-reload.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/fi-byt-j1900/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@sanitycheck: - fi-kbl-7500u: [PASS][8] -> [DMESG-WARN][9] ([i915#2605]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [PASS][10] -> [DMESG-WARN][11] ([i915#402]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html * igt@runner@aborted: - fi-byt-j1900: NOTRUN -> [FAIL][12] ([i915#1814] / [i915#2505]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/fi-byt-j1900/igt@run...@aborted.html Possible fixes * igt@i915_selftest@live@execlists: - fi-bsw-nick:[INCOMPLETE][13] ([i915#2940]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@prime_vgem@basic-read: - fi-tgl-y: [DMESG-WARN][15] ([i915#402]) -> [PASS][16] +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-y/igt@prime_v...@basic-read.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/fi-tgl-y/igt@prime_v...@basic-read.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505 [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 38) -- Missing(5): fi-jsl-1 fi-ilk-m540 fi-bsw-cyan fi-bsw-kefka fi-bdw-samus Build changes - * Linux: CI_DRM_9732 -> Patchwork_19592 CI-20190529: 20190529 CI_DRM_9732: adb75f6f105d29ef75c1c8547db6259cad2092df @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5991: a2d9c45fca85918ecf4776120aade64b9220 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19592: 26994f547e3ad326b6303505e14e35a3120839cf @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 26994f547e3a drm/i915/display: Remove PSR2 on JSL and EHL == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19592/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Make psr_safest_params and enable_psr2_sel_fetch parameters read only
== Series Details == Series: drm/i915: Make psr_safest_params and enable_psr2_sel_fetch parameters read only URL : https://patchwork.freedesktop.org/series/86710/ State : success == Summary == CI Bug Log - changes from CI_DRM_9732 -> Patchwork_19591 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/index.html Known issues Here are the changes found in Patchwork_19591 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#2411] / [i915#402]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live@execlists: - fi-bsw-kefka: [PASS][4] -> [INCOMPLETE][5] ([i915#2940]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][6] -> [FAIL][7] ([i915#1372]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [PASS][8] -> [DMESG-WARN][9] ([i915#402]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html * igt@runner@aborted: - fi-bsw-kefka: NOTRUN -> [FAIL][10] ([i915#1436]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/fi-bsw-kefka/igt@run...@aborted.html Possible fixes * igt@i915_selftest@live@execlists: - fi-bsw-nick:[INCOMPLETE][11] ([i915#2940]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@prime_vgem@basic-read: - fi-tgl-y: [DMESG-WARN][13] ([i915#402]) -> [PASS][14] +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-y/igt@prime_v...@basic-read.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/fi-tgl-y/igt@prime_v...@basic-read.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 39) -- Missing(4): fi-jsl-1 fi-ilk-m540 fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9732 -> Patchwork_19591 CI-20190529: 20190529 CI_DRM_9732: adb75f6f105d29ef75c1c8547db6259cad2092df @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5991: a2d9c45fca85918ecf4776120aade64b9220 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19591: 40c071ccaac156b523d1435aac5faf05b715d143 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 40c071ccaac1 drm/i915: Make psr_safest_params and enable_psr2_sel_fetch parameters read only == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19591/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/2] drm/i915/gt: Double check heartbeat timeout before resetting
Check that we have actually passed the heartbeat interval since last
checking the request before resetting the device.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2780
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index 48a91c0dbad6..93741a65924a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -31,7 +31,7 @@ static bool next_heartbeat(struct intel_engine_cs *engine)
delay = msecs_to_jiffies_timeout(delay);
if (delay >= HZ)
delay = round_jiffies_up_relative(delay);
- mod_delayed_work(system_highpri_wq, >heartbeat.work, delay);
+ mod_delayed_work(system_highpri_wq, >heartbeat.work, delay + 1);
return true;
}
@@ -103,6 +103,13 @@ static void heartbeat(struct work_struct *wrk)
goto out;
if (engine->heartbeat.systole) {
+ long delay = READ_ONCE(engine->props.heartbeat_interval_ms);
+
+ /* Safeguard against too-fast worker invocations */
+ if (!time_after(jiffies,
+ rq->emitted_jiffies + msecs_to_jiffies(delay)))
+ goto out;
+
if (!i915_sw_fence_signaled(>submit)) {
/*
* Not yet submitted, system is stalled.
@@ -139,6 +146,8 @@ static void heartbeat(struct work_struct *wrk)
"stopped heartbeat on %s",
engine->name);
}
+
+ rq->emitted_jiffies = jiffies;
goto out;
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/2] drm/i915/selftests: Restore previous heartbeat interval
Use the defaults we store on the engine when resetting the heartbeat as
we may have had to adjust it from the config value during initialisation.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
.../gpu/drm/i915/gt/selftest_engine_heartbeat.c| 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
index b0bae6676140..b2c369317bf1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
@@ -11,6 +11,12 @@
#include "i915_selftest.h"
#include "selftest_engine_heartbeat.h"
+static void reset_heartbeat(struct intel_engine_cs *engine)
+{
+ intel_engine_set_heartbeat(engine,
+ engine->defaults.heartbeat_interval_ms);
+}
+
static int timeline_sync(struct intel_timeline *tl)
{
struct dma_fence *fence;
@@ -269,7 +275,7 @@ static int __live_heartbeat_fast(struct intel_engine_cs
*engine)
err = -EINVAL;
}
- intel_engine_set_heartbeat(engine, CONFIG_DRM_I915_HEARTBEAT_INTERVAL);
+ reset_heartbeat(engine);
err_pm:
intel_engine_pm_put(engine);
intel_context_put(ce);
@@ -284,7 +290,7 @@ static int live_heartbeat_fast(void *arg)
int err = 0;
/* Check that the heartbeat ticks at the desired rate. */
- if (!CONFIG_DRM_I915_HEARTBEAT_INTERVAL)
+ if (!IS_ACTIVE(CONFIG_DRM_I915_HEARTBEAT_INTERVAL))
return 0;
for_each_engine(engine, gt, id) {
@@ -332,7 +338,7 @@ static int __live_heartbeat_off(struct intel_engine_cs
*engine)
}
err_beat:
- intel_engine_set_heartbeat(engine, CONFIG_DRM_I915_HEARTBEAT_INTERVAL);
+ reset_heartbeat(engine);
err_pm:
intel_engine_pm_put(engine);
return err;
@@ -346,7 +352,7 @@ static int live_heartbeat_off(void *arg)
int err = 0;
/* Check that we can turn off heartbeat and not interrupt VIP */
- if (!CONFIG_DRM_I915_HEARTBEAT_INTERVAL)
+ if (!IS_ACTIVE(CONFIG_DRM_I915_HEARTBEAT_INTERVAL))
return 0;
for_each_engine(engine, gt, id) {
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v15,1/2] drm/i915/display: Support PSR Multiple Instances
== Series Details ==
Series: series starting with [v15,1/2] drm/i915/display: Support PSR Multiple
Instances
URL : https://patchwork.freedesktop.org/series/86701/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9732 -> Patchwork_19590
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_19590 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19590, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19590:
### IGT changes ###
Warnings
* igt@kms_psr@primary_mmap_gtt:
- fi-icl-y: [SKIP][1] ([fdo#110189]) -> [SKIP][2] +3 similar
issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-icl-y/igt@kms_psr@primary_mmap_gtt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/fi-icl-y/igt@kms_psr@primary_mmap_gtt.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_psr@cursor_plane_move:
- {fi-rkl-11500t}:[SKIP][3] ([i915#1072]) -> [SKIP][4] +3 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-rkl-11500t/igt@kms_psr@cursor_plane_move.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/fi-rkl-11500t/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@primary_mmap_gtt:
- {fi-tgl-dsi}: [SKIP][5] ([fdo#110189]) -> [SKIP][6] +3 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_psr@sprite_plane_onoff:
- {fi-ehl-1}: [SKIP][7] ([i915#1072]) -> [SKIP][8] +3 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-ehl-1/igt@kms_psr@sprite_plane_onoff.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/fi-ehl-1/igt@kms_psr@sprite_plane_onoff.html
Known issues
Here are the changes found in Patchwork_19590 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-bsw-nick:NOTRUN -> [SKIP][9] ([fdo#109271]) +17 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html
* igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y: [PASS][10] -> [DMESG-WARN][11] ([i915#402]) +1
similar issue
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
* igt@i915_selftest@live@blt:
- fi-hsw-4770:[PASS][12] -> [DMESG-FAIL][13] ([i915#1409])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-hsw-4770/igt@i915_selftest@l...@blt.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/fi-hsw-4770/igt@i915_selftest@l...@blt.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[INCOMPLETE][14] ([i915#2940]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@prime_vgem@basic-read:
- fi-tgl-y: [DMESG-WARN][16] ([i915#402]) -> [PASS][17] +2
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-y/igt@prime_v...@basic-read.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/fi-tgl-y/igt@prime_v...@basic-read.html
Warnings
* igt@kms_psr@primary_mmap_gtt:
- fi-hsw-4770:[SKIP][18] ([fdo#109271] / [i915#1072]) -> [SKIP][19]
([fdo#109271]) +3 similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19590/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1409]:
Re: [Intel-gfx] [PATCH v11 03/10] drm/i915: migrate skl planes code new file (v5)
On Thu, 04 Feb 2021, Ville Syrjälä wrote:
> On Thu, Feb 04, 2021 at 09:43:20PM +0200, Jani Nikula wrote:
>> -unsigned int
>> -intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
>> -{
>> -int x = 0, y = 0;
>> -
>> -intel_plane_adjust_aligned_offset(, , plane_state, 0,
>> - plane_state->color_plane[0].offset,
>> 0);
>> -
>> -return y;
>> -}
>
> This unrelated code motion is still here, messing up the diff.
Right. I wasn't looking to improve anything, I just wanted to rebase and
get test results.
BR,
Jani.
>
>
>> }
>>
>> -void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
>> -{
>> -struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>> -int i;
>> -
>> -for (i = 0; i < crtc->num_scalers; i++)
>> -skl_detach_scaler(crtc, i);
>> -}
>
> ditto
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v11 09/10] drm/i915: refactor skylake scaler code into new file.
On Thu, Feb 04, 2021 at 09:43:26PM +0200, Jani Nikula wrote:
> static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
Missed all the skl_pfit*().
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 46fcb5b9983f..4cbdb8fd4bb1 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -138,68 +138,6 @@ int intel_plane_check_src_coordinates(struct
> intel_plane_state *plane_state)
> return 0;
> }
>
> -void
> -skl_program_scaler(struct intel_plane *plane,
> -const struct intel_crtc_state *crtc_state,
> -const struct intel_plane_state *plane_state)
If we move this we should rename it to skl_program_plane_scaler() or
something along those lines. Ideally I'd like to have a single
function that works for both pipe and plane scaling but that might
require some actual thought so not going to be a trivial rename/move.
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/display: support ddr5 mem types
On Thu, 2021-02-04 at 12:04 -0800, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> Add DDR5 and LPDDR5 return values from punit fw.
>
Reviewed-by: José Roberto de Souza
> BSPEC: 54023
> Cc: Matt Roper
> Cc: José Roberto de Souza
> Signed-off-by: Clint Taylor
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 12 +++-
> drivers/gpu/drm/i915/i915_drv.h | 4 +++-
> drivers/gpu/drm/i915/intel_dram.c | 6 ++
> 3 files changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index ba9e713585e7..d122b9965532 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -78,7 +78,17 @@ static int icl_get_qgv_points(struct drm_i915_private
> *dev_priv,
> qi->num_points = dram_info->num_qgv_points;
>
>
>
>
> if (IS_GEN(dev_priv, 12))
> - qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 16;
> + switch (dram_info->type) {
> + case INTEL_DRAM_DDR4:
> + qi->t_bl = 4;
> + break;
> + case INTEL_DRAM_DDR5:
> + qi->t_bl = 8;
> + break;
> + default:
> + qi->t_bl = 16;
> + break;
> + }
> else if (IS_GEN(dev_priv, 11))
> qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
>
>
>
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a2fd7e5039b3..8083a50908bf 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1136,7 +1136,9 @@ struct drm_i915_private {
> INTEL_DRAM_DDR3,
> INTEL_DRAM_DDR4,
> INTEL_DRAM_LPDDR3,
> - INTEL_DRAM_LPDDR4
> + INTEL_DRAM_LPDDR4,
> + INTEL_DRAM_DDR5,
> + INTEL_DRAM_LPDDR5,
> } type;
> u8 num_qgv_points;
> } dram_info;
> diff --git a/drivers/gpu/drm/i915/intel_dram.c
> b/drivers/gpu/drm/i915/intel_dram.c
> index 73d256fc6830..1e53c017c30d 100644
> --- a/drivers/gpu/drm/i915/intel_dram.c
> +++ b/drivers/gpu/drm/i915/intel_dram.c
> @@ -427,6 +427,12 @@ static int icl_pcode_read_mem_global_info(struct
> drm_i915_private *dev_priv)
> case 0:
> dram_info->type = INTEL_DRAM_DDR4;
> break;
> + case 1:
> + dram_info->type = INTEL_DRAM_DDR5;
> + break;
> + case 2:
> + dram_info->type = INTEL_DRAM_LPDDR5;
> + break;
> case 3:
> dram_info->type = INTEL_DRAM_LPDDR4;
> break;
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v15,1/2] drm/i915/display: Support PSR Multiple Instances
== Series Details == Series: series starting with [v15,1/2] drm/i915/display: Support PSR Multiple Instances URL : https://patchwork.freedesktop.org/series/86701/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1323:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v11 03/10] drm/i915: migrate skl planes code new file (v5)
On Thu, Feb 04, 2021 at 09:43:20PM +0200, Jani Nikula wrote:
> -unsigned int
> -intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
> -{
> - int x = 0, y = 0;
> -
> - intel_plane_adjust_aligned_offset(, , plane_state, 0,
> - plane_state->color_plane[0].offset,
> 0);
> -
> - return y;
> -}
This unrelated code motion is still here, messing up the diff.
> }
>
> -void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
> -{
> - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> - int i;
> -
> - for (i = 0; i < crtc->num_scalers; i++)
> - skl_detach_scaler(crtc, i);
> -}
ditto
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v15,1/2] drm/i915/display: Support PSR Multiple Instances
== Series Details == Series: series starting with [v15,1/2] drm/i915/display: Support PSR Multiple Instances URL : https://patchwork.freedesktop.org/series/86701/ State : warning == Summary == $ dim checkpatch origin/drm-tip f7ac9079531d drm/i915/display: Support PSR Multiple Instances -:90: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #90: FILE: drivers/gpu/drm/i915/display/intel_display.h:420: +#define for_each_intel_encoder_mask_can_psr(dev, intel_encoder, encoder_mask) \ + list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ + for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \ + intel_encoder_can_psr(intel_encoder)) -:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_encoder' - possible side-effects? #90: FILE: drivers/gpu/drm/i915/display/intel_display.h:420: +#define for_each_intel_encoder_mask_can_psr(dev, intel_encoder, encoder_mask) \ + list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ + for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \ + intel_encoder_can_psr(intel_encoder)) -:99: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #99: FILE: drivers/gpu/drm/i915/display/intel_display.h:429: +#define for_each_intel_encoder_can_psr(dev, intel_encoder) \ + for_each_intel_encoder((dev), (intel_encoder)) \ + for_each_if(intel_encoder_can_psr(intel_encoder)) -:99: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_encoder' - possible side-effects? #99: FILE: drivers/gpu/drm/i915/display/intel_display.h:429: +#define for_each_intel_encoder_can_psr(dev, intel_encoder) \ + for_each_intel_encoder((dev), (intel_encoder)) \ + for_each_if(intel_encoder_can_psr(intel_encoder)) -:377: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible side-effects? #377: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:1795: +#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && \ +(intel_dp)->psr.sink_support && \ +(intel_dp)->psr.source_support) total: 2 errors, 0 warnings, 3 checks, 1726 lines checked 7a9ed6999675 drm/i915/display: Support Multiple Transcoders' PSR status on debugfs ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for swiotlb: 64-bit DMA buffer
== Series Details == Series: swiotlb: 64-bit DMA buffer URL : https://patchwork.freedesktop.org/series/86700/ State : success == Summary == CI Bug Log - changes from CI_DRM_9732 -> Patchwork_19589 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19589/index.html Known issues Here are the changes found in Patchwork_19589 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19589/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19589/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html Possible fixes * igt@i915_selftest@live@execlists: - fi-bsw-nick:[INCOMPLETE][4] ([i915#2940]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19589/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@prime_vgem@basic-read: - fi-tgl-y: [DMESG-WARN][6] ([i915#402]) -> [PASS][7] +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9732/fi-tgl-y/igt@prime_v...@basic-read.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19589/fi-tgl-y/igt@prime_v...@basic-read.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 39) -- Missing(4): fi-jsl-1 fi-ilk-m540 fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9732 -> Patchwork_19589 CI-20190529: 20190529 CI_DRM_9732: adb75f6f105d29ef75c1c8547db6259cad2092df @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5991: a2d9c45fca85918ecf4776120aade64b9220 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19589: 3a347e83afb9bd9f979e0b457114cbfaa2399154 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3a347e83afb9 xen-swiotlb: enable 64-bit xen-swiotlb 30d8a3cce117 xen-swiotlb: convert variables to arrays eb9848ac2c6c swiotlb: enable 64-bit swiotlb 7fe9ad150961 swiotlb: introduce swiotlb_get_type() to calculate swiotlb buffer type 50f74bc8af02 swiotlb: convert variables to arrays e188296818db swiotlb: define new enumerated type == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19589/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/display: Remove PSR2 on JSL and EHL
On Thu, 2021-02-04 at 09:58 -0800, José Roberto de Souza wrote:
> From: Edmund Dea
>
> While JSL and EHL eDP transcoder supports PSR2, the phy of this
> platforms only supports eDP 1.3, so removing PSR2 support as this
> feature was added in eDP 1.4.
Just sent a patch from Edmund with a minor commit message tweaks, so I guess my
rvb is valid if not please let me know.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Edmund Dea
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2c365b778f74..cccb8aff4336 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -718,6 +718,12 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> if (!dev_priv->psr.sink_psr2_support)
> return false;
>
>
>
>
> + /* JSL and EHL only supports eDP 1.3 */
> + if (IS_JSL_EHL(dev_priv)) {
> + drm_dbg_kms(_priv->drm, "PSR2 not supported by phy\n");
> + return false;
> + }
> +
> if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
> drm_dbg_kms(_priv->drm,
> "PSR2 not supported in transcoder %s\n",
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] RFC: dma-buf: Require VM_SPECIAL vma for mmap
On Thu, Feb 4, 2021 at 9:09 PM Jason Gunthorpe wrote: > > On Thu, Feb 04, 2021 at 08:59:59PM +0100, Daniel Vetter wrote: > > > So I think just checking for VM_PFNMAP after the vma is set up should > > be enough to guarantee we'll only have pte_special ptes in there, > > ever. But I'm not sure, this stuff all isn't really documented much > > and the code is sometimes a maze (to me at least). > > Yes, that makes sense. VM_PFNMAP and !VM_MIXEDMAP seems like the right > check after the VMA is populated > > But how do you stuff special pfns into a VMA outside the fault > handler? Many drivers we have don't have dynamic buffer management (kinda overkill for a few framebuffers on a display-only IP block), so the just remap_pfn_range on ->mmap, and don't have a fault handler at all. Or I'm not understanding what you're asking? -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/display: support ddr5 mem types
From: Clint Taylor
Add DDR5 and LPDDR5 return values from punit fw.
BSPEC: 54023
Cc: Matt Roper
Cc: José Roberto de Souza
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_bw.c | 12 +++-
drivers/gpu/drm/i915/i915_drv.h | 4 +++-
drivers/gpu/drm/i915/intel_dram.c | 6 ++
3 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index ba9e713585e7..d122b9965532 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -78,7 +78,17 @@ static int icl_get_qgv_points(struct drm_i915_private
*dev_priv,
qi->num_points = dram_info->num_qgv_points;
if (IS_GEN(dev_priv, 12))
- qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 16;
+ switch (dram_info->type) {
+ case INTEL_DRAM_DDR4:
+ qi->t_bl = 4;
+ break;
+ case INTEL_DRAM_DDR5:
+ qi->t_bl = 8;
+ break;
+ default:
+ qi->t_bl = 16;
+ break;
+ }
else if (IS_GEN(dev_priv, 11))
qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a2fd7e5039b3..8083a50908bf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1136,7 +1136,9 @@ struct drm_i915_private {
INTEL_DRAM_DDR3,
INTEL_DRAM_DDR4,
INTEL_DRAM_LPDDR3,
- INTEL_DRAM_LPDDR4
+ INTEL_DRAM_LPDDR4,
+ INTEL_DRAM_DDR5,
+ INTEL_DRAM_LPDDR5,
} type;
u8 num_qgv_points;
} dram_info;
diff --git a/drivers/gpu/drm/i915/intel_dram.c
b/drivers/gpu/drm/i915/intel_dram.c
index 73d256fc6830..1e53c017c30d 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -427,6 +427,12 @@ static int icl_pcode_read_mem_global_info(struct
drm_i915_private *dev_priv)
case 0:
dram_info->type = INTEL_DRAM_DDR4;
break;
+ case 1:
+ dram_info->type = INTEL_DRAM_DDR5;
+ break;
+ case 2:
+ dram_info->type = INTEL_DRAM_LPDDR5;
+ break;
case 3:
dram_info->type = INTEL_DRAM_LPDDR4;
break;
--
2.29.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] RFC: dma-buf: Require VM_SPECIAL vma for mmap
On Thu, Feb 4, 2021 at 7:38 PM Jason Gunthorpe wrote: > > On Thu, Feb 04, 2021 at 06:16:27PM +0100, Daniel Vetter wrote: > > On Thu, Feb 4, 2021 at 5:13 PM Jason Gunthorpe wrote: > > > On Wed, Feb 03, 2021 at 10:19:48PM +0100, Daniel Vetter wrote: > > > > tldr; DMA buffers aren't normal memory, expecting that you can use > > > > them like that (like calling get_user_pages works, or that they're > > > > accounting like any other normal memory) cannot be guaranteed. > > > > > > > > Since some userspace only runs on integrated devices, where all > > > > buffers are actually all resident system memory, there's a huge > > > > temptation to assume that a struct page is always present and useable > > > > like for any more pagecache backed mmap. This has the potential to > > > > result in a uapi nightmare. > > > > > > > > To stop this gap require that DMA buffer mmaps are VM_SPECIAL, which > > > > blocks get_user_pages and all the other struct page based > > > > infrastructure for everyone. In spirit this is the uapi counterpart to > > > > the kernel-internal CONFIG_DMABUF_DEBUG. > > > > > > Fast gup needs the special flag set on the PTE as well.. Feels weird > > > to have a special VMA without also having special PTEs? > > > > There's kinda no convenient & cheap way to check for the pte_special > > flag. This here should at least catch accidental misuse, people > > building their own ptes we can't stop. Maybe we should exclude > > VM_MIXEDMAP to catch vm_insert_page in one of these. > > > > Hm looking at code I think we need to require VM_PFNMAP here to stop > > vm_insert_page. And looking at the various functions, that seems to be > > required (and I guess VM_IO is more for really funky architectures > > where io-space is somewhere else?). I guess I should check for > > VM_PFNMAP instead of VM_SPECIAL? > > Well, you said the goal was to block GUP usage, that won't happen > without the PTE special flag, at least on x86 > > So, really, what you are saying is all dmabuf users should always use > vmf_insert_pfn_prot() or something similar - and never insert_page/etc? > > It might make sense to check the vma flags in all the insert paths, eg > vm_insert_page() can't work with VMAs that should not have struct > pages in them (eg VM_SPECIAl, VM_PFNMAP, !VM_MIXEMAP if I understand > it right) Well that's what I've done, and it /looks/ like all the checks are there already, as long as we use VM_PFNMAP. vm_insert_page tries to auto-add VM_MIXEDMAP, but bails out with a BUG_ON if VM_PFNMAP is set. And all the vm_insert_pfn_prot/remap_pfn_range functions require (or set) VM_PFNMAP. So I think just checking for VM_PFNMAP after the vma is set up should be enough to guarantee we'll only have pte_special ptes in there, ever. But I'm not sure, this stuff all isn't really documented much and the code is sometimes a maze (to me at least). > At least as some VM debug option Seems to be there already unconditionally. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for swiotlb: 64-bit DMA buffer
== Series Details == Series: swiotlb: 64-bit DMA buffer URL : https://patchwork.freedesktop.org/series/86700/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +drivers/gpu/drm/i915/gt/intel_reset.c:1323:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for swiotlb: 64-bit DMA buffer
== Series Details == Series: swiotlb: 64-bit DMA buffer URL : https://patchwork.freedesktop.org/series/86700/ State : warning == Summary == $ dim checkpatch origin/drm-tip e188296818db swiotlb: define new enumerated type 50f74bc8af02 swiotlb: convert variables to arrays -:130: WARNING:CONSIDER_KSTRTO: simple_strtoul is obsolete, use kstrtoul instead #130: FILE: kernel/dma/swiotlb.c:116: + io_tlb_nslabs[SWIOTLB_LO] = simple_strtoul(str, , 0); -:591: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV) #591: FILE: kernel/dma/swiotlb.c:589: + io_tlb_orig_addr[SWIOTLB_LO][index+i] = orig_addr + (i << IO_TLB_SHIFT); ^ total: 0 errors, 1 warnings, 1 checks, 602 lines checked 7fe9ad150961 swiotlb: introduce swiotlb_get_type() to calculate swiotlb buffer type eb9848ac2c6c swiotlb: enable 64-bit swiotlb -:227: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files #227: FILE: include/linux/swiotlb.h:48: +extern unsigned long swiotlb_nr_tbl(enum swiotlb_t type); -:231: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files #231: FILE: include/linux/swiotlb.h:50: +extern int swiotlb_late_init_with_tbl(char *tlb, unsigned long nslabs, -:233: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files #233: FILE: include/linux/swiotlb.h:52: +extern int swiotlb_late_init_with_default_size(size_t default_size, -:268: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #268: FILE: include/linux/swiotlb.h:123: } +static inline unsigned int swiotlb_max_segment(enum swiotlb_t type) -:278: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files #278: FILE: include/linux/swiotlb.h:142: +extern void swiotlb_print_info(enum swiotlb_t type); -:279: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files #279: FILE: include/linux/swiotlb.h:143: +extern void swiotlb_set_max_segment(unsigned int val, enum swiotlb_t type); -:304: WARNING:CONSIDER_KSTRTO: simple_strtoul is obsolete, use kstrtoul instead #304: FILE: kernel/dma/swiotlb.c:131: + io_tlb_nslabs[SWIOTLB_HI] = simple_strtoul(str, , 0); -:840: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV) #840: FILE: kernel/dma/swiotlb.c:641: + io_tlb_orig_addr[type][index+i] = orig_addr + (i << IO_TLB_SHIFT); ^ total: 0 errors, 1 warnings, 7 checks, 790 lines checked 30d8a3cce117 xen-swiotlb: convert variables to arrays -:110: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #110: FILE: drivers/xen/swiotlb-xen.c:208: + xen_io_tlb_start[SWIOTLB_LO] = memblock_alloc(PAGE_ALIGN(bytes), PAGE_SIZE); total: 0 errors, 0 warnings, 1 checks, 181 lines checked 3a347e83afb9 xen-swiotlb: enable 64-bit xen-swiotlb -:83: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #83: FILE: drivers/xen/swiotlb-xen.c:165: + xen_io_tlb_nslabs[type] = ALIGN(xen_io_tlb_nslabs[type], IO_TLB_SEGSIZE); -:130: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #130: FILE: drivers/xen/swiotlb-xen.c:219: + xen_io_tlb_start[type] = memblock_alloc(PAGE_ALIGN(bytes), PAGE_SIZE); total: 0 errors, 0 warnings, 2 checks, 235 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [rfc v10] refactor intel_display.c + a bit more
On Wed, 27 Jan 2021, Dave Airlie wrote: > This is a repost of the last series, rebased to include the VRR > and GEN12 CCS changes. > > It also has to scaler and ddi pll state movement patches that need > review, I think the rest should be pretty good to push sooner so > I don't fall into any more rebase traps. It started conflicting on day 1. :( Rebased and resent -> [1]. BR, Jani. [1] http://lore.kernel.org/r/cover.1612467466.git.jani.nik...@intel.com -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v11 10/10] drm/i915: move ddi pll state get to dpll mgr
From: Dave Airlie
This just migrates the hsw+ code to a better place.
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 219 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 223 ++
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 +
3 files changed, 226 insertions(+), 218 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d6046f2ab42e..7b7f4af701ac 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6579,212 +6579,6 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
return ret;
}
-static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
- struct intel_crtc_state *pipe_config)
-{
- enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
- enum phy phy = intel_port_to_phy(dev_priv, port);
- struct icl_port_dpll *port_dpll;
- struct intel_shared_dpll *pll;
- enum intel_dpll_id id;
- bool pll_active;
- u32 clk_sel;
-
- clk_sel = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)) &
DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- id = DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy);
-
- if (WARN_ON(id > DPLL_ID_DG1_DPLL3))
- return;
-
- pll = intel_get_shared_dpll_by_id(dev_priv, id);
- port_dpll = _config->icl_port_dplls[port_dpll_id];
-
- port_dpll->pll = pll;
- pll_active = intel_dpll_get_hw_state(dev_priv, pll,
-_dpll->hw_state);
- drm_WARN_ON(_priv->drm, !pll_active);
-
- icl_set_active_port_dpll(pipe_config, port_dpll_id);
-}
-
-static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
- struct intel_crtc_state *pipe_config)
-{
- enum phy phy = intel_port_to_phy(dev_priv, port);
- enum icl_port_dpll_id port_dpll_id;
- struct icl_port_dpll *port_dpll;
- struct intel_shared_dpll *pll;
- enum intel_dpll_id id;
- bool pll_active;
- i915_reg_t reg;
- u32 temp;
-
- if (intel_phy_is_combo(dev_priv, phy)) {
- u32 mask, shift;
-
- if (IS_ALDERLAKE_S(dev_priv)) {
- reg = ADLS_DPCLKA_CFGCR(phy);
- mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
- shift = ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy);
- } else if (IS_ROCKETLAKE(dev_priv)) {
- reg = ICL_DPCLKA_CFGCR0;
- mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
- } else {
- reg = ICL_DPCLKA_CFGCR0;
- mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
- }
-
- temp = intel_de_read(dev_priv, reg) & mask;
- id = temp >> shift;
- port_dpll_id = ICL_PORT_DPLL_DEFAULT;
- } else if (intel_phy_is_tc(dev_priv, phy)) {
- u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) &
DDI_CLK_SEL_MASK;
-
- if (clk_sel == DDI_CLK_SEL_MG) {
- id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
- port));
- port_dpll_id = ICL_PORT_DPLL_MG_PHY;
- } else {
- drm_WARN_ON(_priv->drm,
- clk_sel < DDI_CLK_SEL_TBT_162);
- id = DPLL_ID_ICL_TBTPLL;
- port_dpll_id = ICL_PORT_DPLL_DEFAULT;
- }
- } else {
- drm_WARN(_priv->drm, 1, "Invalid port %x\n", port);
- return;
- }
-
- pll = intel_get_shared_dpll_by_id(dev_priv, id);
- port_dpll = _config->icl_port_dplls[port_dpll_id];
-
- port_dpll->pll = pll;
- pll_active = intel_dpll_get_hw_state(dev_priv, pll,
-_dpll->hw_state);
- drm_WARN_ON(_priv->drm, !pll_active);
-
- icl_set_active_port_dpll(pipe_config, port_dpll_id);
-}
-
-static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
- struct intel_crtc_state *pipe_config)
-{
- struct intel_shared_dpll *pll;
- enum intel_dpll_id id;
- bool pll_active;
- u32 temp;
-
- temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) &
DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
- id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
-
- if (drm_WARN_ON(_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
- return;
-
- pll = intel_get_shared_dpll_by_id(dev_priv, id);
-
-
[Intel-gfx] [PATCH v11 09/10] drm/i915: refactor skylake scaler code into new file.
From: Dave Airlie
This moves the code from various places and consolidates it
into one new file.
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/icl_dsi.c| 1 +
drivers/gpu/drm/i915/display/intel_atomic.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 429 +--
drivers/gpu/drm/i915/display/intel_display.h | 6 -
drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
drivers/gpu/drm/i915/display/intel_sprite.c | 62 ---
drivers/gpu/drm/i915/display/intel_sprite.h | 7 -
drivers/gpu/drm/i915/display/skl_scaler.c | 497 ++
drivers/gpu/drm/i915/display/skl_scaler.h | 32 ++
.../drm/i915/display/skl_universal_plane.c| 1 +
.../drm/i915/display/skl_universal_plane.h| 4 +
drivers/gpu/drm/i915/display/vlv_dsi.c| 1 +
14 files changed, 541 insertions(+), 504 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/skl_scaler.c
create mode 100644 drivers/gpu/drm/i915/display/skl_scaler.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9388e09184fe..235679637d1c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -226,6 +226,7 @@ i915-y += \
display/intel_tc.o \
display/intel_vga.o \
display/i9xx_plane.o \
+ display/skl_scaler.o \
display/skl_universal_plane.o
i915-$(CONFIG_ACPI) += \
display/intel_acpi.o \
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 9eeec6fadec7..7ef6b89c79d9 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -35,6 +35,7 @@
#include "intel_dsi.h"
#include "intel_panel.h"
#include "intel_vdsc.h"
+#include "skl_scaler.h"
#include "skl_universal_plane.h"
static int header_credits_available(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index e00fdc47c0eb..27f7d7109ca3 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -40,7 +40,7 @@
#include "intel_global_state.h"
#include "intel_hdcp.h"
#include "intel_psr.h"
-#include "intel_sprite.h"
+#include "skl_universal_plane.h"
/**
* intel_digital_connector_atomic_get_property - hook for
connector->atomic_get_property.
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index f4746c1edabe..3c4003605f93 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -54,6 +54,7 @@
#include "intel_tc.h"
#include "intel_vdsc.h"
#include "intel_vrr.h"
+#include "skl_scaler.h"
#include "skl_universal_plane.h"
static const u8 index_to_dp_signal_levels[] = {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ef1e0f072d8f..d6046f2ab42e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -94,6 +94,7 @@
#include "intel_tc.h"
#include "intel_vga.h"
#include "i9xx_plane.h"
+#include "skl_scaler.h"
#include "skl_universal_plane.h"
static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
@@ -2510,47 +2511,6 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
_intel_frontbuffer(fb)->bits);
}
-static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
-{
- struct drm_device *dev = intel_crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- unsigned long irqflags;
-
- spin_lock_irqsave(_priv->uncore.lock, irqflags);
-
- intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
- intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
- intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
-
- spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
-}
-
-/*
- * This function detaches (aka. unbinds) unused scalers in hardware
- */
-static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
-{
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
- const struct intel_crtc_scaler_state *scaler_state =
- _state->scaler_state;
- int i;
-
- /* loop through and disable scalers that aren't in use */
- for (i = 0; i < intel_crtc->num_scalers; i++) {
- if (!scaler_state->scalers[i].in_use)
- skl_detach_scaler(intel_crtc, i);
- }
-}
-
-void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
- int i;
-
- for (i = 0; i < crtc->num_scalers; i++)
- skl_detach_scaler(crtc, i);
[Intel-gfx] [PATCH v11 08/10] drm/i915: migrate i9xx plane get config
From: Dave Airlie
Migrate this code out like the skylake code.
Signed-off-by: Dave Airlie
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c| 119 +++
drivers/gpu/drm/i915/display/i9xx_plane.h| 4 +
drivers/gpu/drm/i915/display/intel_display.c | 119 ---
3 files changed, 123 insertions(+), 119 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index d116dee201aa..0523e2c79d16 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -893,3 +893,122 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
return ERR_PTR(ret);
}
+static int i9xx_format_to_fourcc(int format)
+{
+ switch (format) {
+ case DISPPLANE_8BPP:
+ return DRM_FORMAT_C8;
+ case DISPPLANE_BGRA555:
+ return DRM_FORMAT_ARGB1555;
+ case DISPPLANE_BGRX555:
+ return DRM_FORMAT_XRGB1555;
+ case DISPPLANE_BGRX565:
+ return DRM_FORMAT_RGB565;
+ default:
+ case DISPPLANE_BGRX888:
+ return DRM_FORMAT_XRGB;
+ case DISPPLANE_RGBX888:
+ return DRM_FORMAT_XBGR;
+ case DISPPLANE_BGRA888:
+ return DRM_FORMAT_ARGB;
+ case DISPPLANE_RGBA888:
+ return DRM_FORMAT_ABGR;
+ case DISPPLANE_BGRX101010:
+ return DRM_FORMAT_XRGB2101010;
+ case DISPPLANE_RGBX101010:
+ return DRM_FORMAT_XBGR2101010;
+ case DISPPLANE_BGRA101010:
+ return DRM_FORMAT_ARGB2101010;
+ case DISPPLANE_RGBA101010:
+ return DRM_FORMAT_ABGR2101010;
+ case DISPPLANE_RGBX161616:
+ return DRM_FORMAT_XBGR16161616F;
+ }
+}
+
+void
+i9xx_get_initial_plane_config(struct intel_crtc *crtc,
+ struct intel_initial_plane_config *plane_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+ enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
+ enum pipe pipe;
+ u32 val, base, offset;
+ int fourcc, pixel_format;
+ unsigned int aligned_height;
+ struct drm_framebuffer *fb;
+ struct intel_framebuffer *intel_fb;
+
+ if (!plane->get_hw_state(plane, ))
+ return;
+
+ drm_WARN_ON(dev, pipe != crtc->pipe);
+
+ intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
+ if (!intel_fb) {
+ drm_dbg_kms(_priv->drm, "failed to alloc fb\n");
+ return;
+ }
+
+ fb = _fb->base;
+
+ fb->dev = dev;
+
+ val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
+
+ if (INTEL_GEN(dev_priv) >= 4) {
+ if (val & DISPPLANE_TILED) {
+ plane_config->tiling = I915_TILING_X;
+ fb->modifier = I915_FORMAT_MOD_X_TILED;
+ }
+
+ if (val & DISPPLANE_ROTATE_180)
+ plane_config->rotation = DRM_MODE_ROTATE_180;
+ }
+
+ if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
+ val & DISPPLANE_MIRROR)
+ plane_config->rotation |= DRM_MODE_REFLECT_X;
+
+ pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
+ fourcc = i9xx_format_to_fourcc(pixel_format);
+ fb->format = drm_format_info(fourcc);
+
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+ offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
+ base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) &
0xf000;
+ } else if (INTEL_GEN(dev_priv) >= 4) {
+ if (plane_config->tiling)
+ offset = intel_de_read(dev_priv,
+ DSPTILEOFF(i9xx_plane));
+ else
+ offset = intel_de_read(dev_priv,
+ DSPLINOFF(i9xx_plane));
+ base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) &
0xf000;
+ } else {
+ base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
+ }
+ plane_config->base = base;
+
+ val = intel_de_read(dev_priv, PIPESRC(pipe));
+ fb->width = ((val >> 16) & 0xfff) + 1;
+ fb->height = ((val >> 0) & 0xfff) + 1;
+
+ val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
+ fb->pitches[0] = val & 0xffc0;
+
+ aligned_height = intel_fb_align_height(fb, 0, fb->height);
+
+ plane_config->size = fb->pitches[0] * aligned_height;
+
+ drm_dbg_kms(_priv->drm,
+ "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size
0x%x\n",
+ crtc->base.name, plane->base.name, fb->width, fb->height,
+
[Intel-gfx] [PATCH v11 06/10] drm/i915: move is_ccs_modifier to an inline
From: Dave Airlie
There is no need for this to be out of line.
Reviewed-by: Ville Syrjälä
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 9 -
drivers/gpu/drm/i915/display/intel_display.h | 1 -
drivers/gpu/drm/i915/display/intel_display_types.h | 9 +
3 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8211cb40b5c6..3758627f0f7d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1823,15 +1823,6 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
}
}
-bool is_ccs_modifier(u64 modifier)
-{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
- modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
-}
-
static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
{
return DIV_ROUND_UP(fb->pitches[skl_ccs_to_main_plane(fb, ccs_plane)],
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 251398128349..c176c31c3ec2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -508,7 +508,6 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n, bool fec_enable);
-bool is_ccs_modifier(u64 modifier);
void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 23a74496c172..9222e4f9348f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1895,6 +1895,15 @@ static inline u32 intel_fdi_link_freq(struct
drm_i915_private *dev_priv,
return dev_priv->fdi_pll_freq;
}
+static inline bool is_ccs_modifier(u64 modifier)
+{
+ return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+ modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+}
+
static inline bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
{
if (!is_ccs_modifier(fb->modifier))
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v11 07/10] drm/i915: migrate pll enable/disable code to intel_dpll.[ch]
From: Dave Airlie
This moves the older i9xx/vlv/chv enable/disable to dpll file.
Signed-off-by: Dave Airlie
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 512 ---
drivers/gpu/drm/i915/display/intel_display.h | 3 -
drivers/gpu/drm/i915/display/intel_dp.c | 1 +
drivers/gpu/drm/i915/display/intel_dpll.c| 509 ++
drivers/gpu/drm/i915/display/intel_dpll.h| 18 +
drivers/gpu/drm/i915/display/intel_pps.c | 1 +
6 files changed, 529 insertions(+), 515 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 3758627f0f7d..009f38cbd3c5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -113,10 +113,6 @@ static void i9xx_set_pipeconf(const struct
intel_crtc_state *crtc_state);
static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
-static void vlv_prepare_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config);
-static void chv_prepare_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config);
static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
static void intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx);
@@ -569,224 +565,6 @@ static void assert_pch_ports_disabled(struct
drm_i915_private *dev_priv,
assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
}
-static void _vlv_enable_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
-
- intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
- intel_de_posting_read(dev_priv, DPLL(pipe));
- udelay(150);
-
- if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
- drm_err(_priv->drm, "DPLL %d failed to lock\n", pipe);
-}
-
-static void vlv_enable_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
-
- assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
-
- /* PLL is protected by panel, make sure we can write it */
- assert_panel_unlocked(dev_priv, pipe);
-
- if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
- _vlv_enable_pll(crtc, pipe_config);
-
- intel_de_write(dev_priv, DPLL_MD(pipe),
- pipe_config->dpll_hw_state.dpll_md);
- intel_de_posting_read(dev_priv, DPLL_MD(pipe));
-}
-
-
-static void _chv_enable_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
- enum dpio_channel port = vlv_pipe_to_channel(pipe);
- u32 tmp;
-
- vlv_dpio_get(dev_priv);
-
- /* Enable back the 10bit clock to display controller */
- tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
- tmp |= DPIO_DCLKP_EN;
- vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
-
- vlv_dpio_put(dev_priv);
-
- /*
-* Need to wait > 100ns between dclkp clock enable bit and PLL enable.
-*/
- udelay(1);
-
- /* Enable PLL */
- intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
-
- /* Check PLL is locked */
- if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
- drm_err(_priv->drm, "PLL %d failed to lock\n", pipe);
-}
-
-static void chv_enable_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
-
- assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
-
- /* PLL is protected by panel, make sure we can write it */
- assert_panel_unlocked(dev_priv, pipe);
-
- if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
- _chv_enable_pll(crtc, pipe_config);
-
- if (pipe != PIPE_A) {
- /*
-* WaPixelRepeatModeFixForC0:chv
-*
-* DPLLCMD is AWOL. Use chicken bits to propagate
-* the value from DPLLBMD to either pipe B or C.
-*/
- intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
- intel_de_write(dev_priv,
[Intel-gfx] [PATCH v11 05/10] drm/i915: split fb scalable checks into g4x and skl versions
From: Dave Airlie
This just cleans these up a bit.
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c| 7 +++
drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index b8288330dbc9..46fcb5b9983f 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1365,19 +1365,18 @@ g4x_plane_get_hw_state(struct intel_plane *plane,
return ret;
}
-static bool intel_fb_scalable(const struct drm_framebuffer *fb)
+static bool g4x_fb_scalable(const struct drm_framebuffer *fb)
{
if (!fb)
return false;
switch (fb->format->format) {
case DRM_FORMAT_C8:
- return false;
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
case DRM_FORMAT_XBGR16161616F:
case DRM_FORMAT_ABGR16161616F:
- return INTEL_GEN(to_i915(fb->dev)) >= 11;
+ return false;
default:
return true;
}
@@ -1454,7 +1453,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
int max_scale = DRM_PLANE_HELPER_NO_SCALING;
int ret;
- if (intel_fb_scalable(plane_state->hw.fb)) {
+ if (g4x_fb_scalable(plane_state->hw.fb)) {
if (INTEL_GEN(dev_priv) < 7) {
min_scale = 1;
max_scale = 16 << 16;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 29c2e3693e8b..4ae1a2ef29ec 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1618,7 +1618,7 @@ static int skl_check_plane_surface(struct
intel_plane_state *plane_state)
return 0;
}
-static bool intel_fb_scalable(const struct drm_framebuffer *fb)
+static bool skl_fb_scalable(const struct drm_framebuffer *fb)
{
if (!fb)
return false;
@@ -1651,7 +1651,7 @@ static int skl_plane_check(struct intel_crtc_state
*crtc_state,
return ret;
/* use scaler when colorkey is not required */
- if (!plane_state->ckey.flags && intel_fb_scalable(fb)) {
+ if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
min_scale = 1;
max_scale = skl_plane_max_scale(dev_priv, fb);
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v11 04/10] drm/i915: move pipe update code into crtc. (v2)
From: Dave Airlie
Daniel suggested this should move here.
v2: move vrr code.
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crtc.c | 245
drivers/gpu/drm/i915/display/intel_sprite.c | 242 ---
2 files changed, 245 insertions(+), 242 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index eb478712c381..fdc896c55179 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -10,6 +10,9 @@
#include
#include
+#include "i915_trace.h"
+#include "i915_vgpu.h"
+
#include "intel_atomic.h"
#include "intel_atomic_plane.h"
#include "intel_color.h"
@@ -17,8 +20,11 @@
#include "intel_cursor.h"
#include "intel_display_debugfs.h"
#include "intel_display_types.h"
+#include "intel_dsi.h"
#include "intel_pipe_crc.h"
+#include "intel_psr.h"
#include "intel_sprite.h"
+#include "intel_vrr.h"
#include "i9xx_plane.h"
#include "skl_universal_plane.h"
@@ -332,3 +338,242 @@ int intel_crtc_init(struct drm_i915_private *dev_priv,
enum pipe pipe)
return ret;
}
+
+int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
+int usecs)
+{
+ /* paranoia */
+ if (!adjusted_mode->crtc_htotal)
+ return 1;
+
+ return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
+ 1000 * adjusted_mode->crtc_htotal);
+}
+
+static int intel_mode_vblank_start(const struct drm_display_mode *mode)
+{
+ int vblank_start = mode->crtc_vblank_start;
+
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+ vblank_start = DIV_ROUND_UP(vblank_start, 2);
+
+ return vblank_start;
+}
+
+/**
+ * intel_pipe_update_start() - start update of a set of display registers
+ * @new_crtc_state: the new crtc state
+ *
+ * Mark the start of an update to pipe registers that should be updated
+ * atomically regarding vblank. If the next vblank will happens within
+ * the next 100 us, this function waits until the vblank passes.
+ *
+ * After a successful call to this function, interrupts will be disabled
+ * until a subsequent call to intel_pipe_update_end(). That is done to
+ * avoid random delays.
+ */
+void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_display_mode *adjusted_mode =
_crtc_state->hw.adjusted_mode;
+ long timeout = msecs_to_jiffies_timeout(1);
+ int scanline, min, max, vblank_start;
+ wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(>base);
+ bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) ||
IS_CHERRYVIEW(dev_priv)) &&
+ intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
+ DEFINE_WAIT(wait);
+ u32 psr_status;
+
+ if (new_crtc_state->uapi.async_flip)
+ return;
+
+ if (new_crtc_state->vrr.enable)
+ vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
+ else
+ vblank_start = intel_mode_vblank_start(adjusted_mode);
+
+ /* FIXME needs to be calibrated sensibly */
+ min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
+ VBLANK_EVASION_TIME_US);
+ max = vblank_start - 1;
+
+ if (min <= 0 || max <= 0)
+ goto irq_disable;
+
+ if (drm_WARN_ON(_priv->drm, drm_crtc_vblank_get(>base)))
+ goto irq_disable;
+
+ /*
+* Wait for psr to idle out after enabling the VBL interrupts
+* VBL interrupts will start the PSR exit and prevent a PSR
+* re-entry as well.
+*/
+ if (intel_psr_wait_for_idle(new_crtc_state, _status))
+ drm_err(_priv->drm,
+ "PSR idle timed out 0x%x, atomic update may fail\n",
+ psr_status);
+
+ local_irq_disable();
+
+ crtc->debug.min_vbl = min;
+ crtc->debug.max_vbl = max;
+ trace_intel_pipe_update_start(crtc);
+
+ for (;;) {
+ /*
+* prepare_to_wait() has a memory barrier, which guarantees
+* other CPUs can see the task state update by the time we
+* read the scanline.
+*/
+ prepare_to_wait(wq, , TASK_UNINTERRUPTIBLE);
+
+ scanline = intel_get_crtc_scanline(crtc);
+ if (scanline < min || scanline > max)
+ break;
+
+ if (!timeout) {
+ drm_err(_priv->drm,
+ "Potential atomic update failure on pipe %c\n",
+ pipe_name(crtc->pipe));
+ break;
+ }
+
+
[Intel-gfx] [PATCH v11 02/10] drm/i915: migrate hsw fdi code to new file.
From: Dave Airlie
Daniel asked for this, but it's a bit messy and I'm not sure
how best to clean it up yet.
Signed-off-by: Dave Airlie
[Jani: also moved fdi buf trans to intel_fdi.c.]
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_crt.c | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 151 ++-
drivers/gpu/drm/i915/display/intel_ddi.h | 8 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 139 +
drivers/gpu/drm/i915/display/intel_fdi.h | 3 +
5 files changed, 156 insertions(+), 146 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index 4934edd51cb0..077ebc7e6396 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -38,6 +38,7 @@
#include "intel_crt.h"
#include "intel_ddi.h"
#include "intel_display_types.h"
+#include "intel_fdi.h"
#include "intel_fifo_underrun.h"
#include "intel_gmbus.h"
#include "intel_hotplug.h"
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index e2b82e0557e7..28877a31adc0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -36,10 +36,11 @@
#include "intel_ddi_buf_trans.h"
#include "intel_display_types.h"
#include "intel_dp.h"
-#include "intel_dp_mst.h"
#include "intel_dp_link_training.h"
+#include "intel_dp_mst.h"
#include "intel_dpio_phy.h"
#include "intel_dsi.h"
+#include "intel_fdi.h"
#include "intel_fifo_underrun.h"
#include "intel_gmbus.h"
#include "intel_hdcp.h"
@@ -91,8 +92,8 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
* values in advance. This function programs the correct values for
* DP/eDP/FDI use cases.
*/
-static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
-const struct intel_crtc_state
*crtc_state)
+void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 iboost_bit = 0;
@@ -154,8 +155,8 @@ static void intel_prepare_hdmi_ddi_buffers(struct
intel_encoder *encoder,
ddi_translations[level].trans2);
}
-static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
- enum port port)
+void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
+enum port port)
{
if (IS_BROXTON(dev_priv)) {
udelay(16);
@@ -183,7 +184,7 @@ static void intel_wait_ddi_buf_active(struct
drm_i915_private *dev_priv,
port_name(port));
}
-static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
+u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
{
switch (pll->info->id) {
case DPLL_ID_WRPLL1:
@@ -243,144 +244,6 @@ static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder
*encoder,
}
}
-/* Starting with Haswell, different DDI ports can work in FDI mode for
- * connection to the PCH-located connectors. For this, it is necessary to train
- * both the DDI port and PCH receiver for the desired DDI buffer settings.
- *
- * The recommended port to work in FDI mode is DDI E, which we use here. Also,
- * please note that when FDI mode is active on DDI E, it shares 2 lines with
- * DDI A (which is used for eDP)
- */
-
-void hsw_fdi_link_train(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 temp, i, rx_ctl_val, ddi_pll_sel;
- int n_entries;
-
- intel_ddi_get_buf_trans_fdi(dev_priv, _entries);
-
- intel_prepare_dp_ddi_buffers(encoder, crtc_state);
-
- /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
-* mode set "sequence for CRT port" document:
-* - TP1 to TP2 time with the default value
-* - FDI delay to 90h
-*
-* WaFDIAutoLinkSetTimingOverrride:hsw
-*/
- intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
- FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) |
FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
-
- /* Enable the PCH Receiver FDI PLL */
- rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
-FDI_RX_PLL_ENABLE |
-FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
- intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
- intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
- udelay(220);
-
- /* Switch from Rawclk to PCDclk */
- rx_ctl_val |= FDI_PCDCLK;
- intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A),
[Intel-gfx] [PATCH v11 00/10] drm/i915: refactor intel_display.c + a bit more
Rebase of [1]. Please let's try to double check the rebase and review the patches and get this merged ASAP. Part of the reason we've always put this refactoring off in the first place has been that it's a PITA with the constant conflicts. Dave's last posting of the series started conflicting before CI even tried to build it... BR, Jani. [1] https://patchwork.freedesktop.org/series/86321/ Dave Airlie (10): drm/i915: refactor ddi translations into a separate file (v2) drm/i915: migrate hsw fdi code to new file. drm/i915: migrate skl planes code new file (v5) drm/i915: move pipe update code into crtc. (v2) drm/i915: split fb scalable checks into g4x and skl versions drm/i915: move is_ccs_modifier to an inline drm/i915: migrate pll enable/disable code to intel_dpll.[ch] drm/i915: migrate i9xx plane get config drm/i915: refactor skylake scaler code into new file. drm/i915: move ddi pll state get to dpll mgr drivers/gpu/drm/i915/Makefile |5 +- drivers/gpu/drm/i915/display/i9xx_plane.c | 123 +- drivers/gpu/drm/i915/display/i9xx_plane.h |4 + drivers/gpu/drm/i915/display/icl_dsi.c|2 + drivers/gpu/drm/i915/display/intel_atomic.c |2 +- drivers/gpu/drm/i915/display/intel_crt.c |1 + drivers/gpu/drm/i915/display/intel_crtc.c | 258 +- drivers/gpu/drm/i915/display/intel_ddi.c | 1560 +-- drivers/gpu/drm/i915/display/intel_ddi.h |8 +- .../drm/i915/display/intel_ddi_buf_trans.c| 1394 ++ .../drm/i915/display/intel_ddi_buf_trans.h| 100 + drivers/gpu/drm/i915/display/intel_display.c | 2372 + drivers/gpu/drm/i915/display/intel_display.h | 37 +- .../drm/i915/display/intel_display_types.h| 36 + drivers/gpu/drm/i915/display/intel_dp.c |1 + drivers/gpu/drm/i915/display/intel_dp_mst.c |1 + drivers/gpu/drm/i915/display/intel_dpll.c | 509 drivers/gpu/drm/i915/display/intel_dpll.h | 18 + drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 223 ++ drivers/gpu/drm/i915/display/intel_dpll_mgr.h |2 + drivers/gpu/drm/i915/display/intel_fdi.c | 139 + drivers/gpu/drm/i915/display/intel_fdi.h |3 + drivers/gpu/drm/i915/display/intel_pps.c |1 + drivers/gpu/drm/i915/display/intel_psr.c |1 + drivers/gpu/drm/i915/display/intel_sprite.c | 1718 +--- drivers/gpu/drm/i915/display/intel_sprite.h |7 - drivers/gpu/drm/i915/display/skl_scaler.c | 497 drivers/gpu/drm/i915/display/skl_scaler.h | 32 + .../drm/i915/display/skl_universal_plane.c| 2266 .../drm/i915/display/skl_universal_plane.h| 37 + drivers/gpu/drm/i915/display/vlv_dsi.c|1 + drivers/gpu/drm/i915/intel_pm.c |1 + 32 files changed, 5811 insertions(+), 5548 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c create mode 100644 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h create mode 100644 drivers/gpu/drm/i915/display/skl_scaler.c create mode 100644 drivers/gpu/drm/i915/display/skl_scaler.h create mode 100644 drivers/gpu/drm/i915/display/skl_universal_plane.c create mode 100644 drivers/gpu/drm/i915/display/skl_universal_plane.h -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH RFC v1 2/6] swiotlb: convert variables to arrays
On Thu, Feb 04, 2021 at 11:49:23AM +, Robin Murphy wrote: > On 2021-02-04 07:29, Christoph Hellwig wrote: > > On Wed, Feb 03, 2021 at 03:37:05PM -0800, Dongli Zhang wrote: > > > This patch converts several swiotlb related variables to arrays, in > > > order to maintain stat/status for different swiotlb buffers. Here are > > > variables involved: > > > > > > - io_tlb_start and io_tlb_end > > > - io_tlb_nslabs and io_tlb_used > > > - io_tlb_list > > > - io_tlb_index > > > - max_segment > > > - io_tlb_orig_addr > > > - no_iotlb_memory > > > > > > There is no functional change and this is to prepare to enable 64-bit > > > swiotlb. > > > > Claire Chang (on Cc) already posted a patch like this a month ago, > > which looks much better because it actually uses a struct instead > > of all the random variables. > > Indeed, I skimmed the cover letter and immediately thought that this whole > thing is just the restricted DMA pool concept[1] again, only from a slightly > different angle. Kind of. Let me lay out how some of these pieces are right now: +---+ +--+ | | | | | | | | | a)Xen-SWIOTLB | | b)SWIOTLB (for !Xen) | | | | | +---XX--+ +---X--+ X XX XXX X XX +--XX---+ | | | | | c) SWIOTLB generic | | | +---+ Dongli's patches modify the SWIOTLB generic c), and Xen-SWIOTLB a) parts. Also see the IOMMU_INIT logic which lays this a bit more deepth (for example how to enable SWIOTLB on AMD boxes, or IBM with Calgary IOMMU, etc - see iommu_table.h). Furtheremore it lays the groundwork to allocate AMD SEV SWIOTLB buffers later after boot (so that you can stich different pools together). All the bits are kind of inside of the SWIOTLB code. And also it changes the Xen-SWIOTLB to do something similar. The mempool did it similarly by taking the internal parts (aka the various io_tlb) of SWIOTLB and exposing them out and having other code: +---+ +--+ | | | | | | | | | a)Xen-SWIOTLB | | b)SWIOTLB (for !Xen) | | | | | +---XX--+ +---X--+ X XX XXX X XX +--XX---+ +--+ | | | Device tree | | +<+ enabling SWIOTLB | |c) SWIOTLB generic | | | | | | mempool | +---+ +--+ What I was suggesting to Clarie to follow Xen model, that is do something like this: +---+ +--+ ++ | | | | || | | | | || | a)Xen-SWIOTLB | | b)SWIOTLB (for !Xen) | | e) DT-SWIOTLB | | | | | || +---XX--+ +---X--+ +XX-X+ XXXX X X XX X XX XX XXX X XX X +--XXX--+ | | | | |c) SWIOTLB generic | | | +---+ so using the SWIOTLB generic parts, and then bolt on top of the device-tree logic, along with the mempool logic. But Christopher has an interesting suggestion which is to squash the all the existing code (a, b, c) all together and pepper it with various jump-tables. So: -+ | SWIOTLB: | || | a) SWIOTLB (for non-Xen) | | b) Xen-SWIOTLB| | c) DT-SWIOTLB | || || -+ with all the various bits (M2P/P2M for Xen, mempool for ARM, and normal allocation for BM) in one big file. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org
Re: [Intel-gfx] [PATCH] drm/i915/debugfs: HDCP capability enc NULL check
On Fri, Jan 29, 2021 at 01:30:43PM +0530, Anshuman Gupta wrote:
> DP-MST connector encoder initializes at modeset
> Adding a connector->encoder NULL check in order to
> avoid any NULL pointer dereference.
> intel_hdcp_enable() already handle this but debugfs
> can also invoke the intel_{hdcp,hdcp2_capable}.
> Handling it gracefully.
>
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 14 --
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index ae1371c36a32..58af323d189a 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -135,11 +135,16 @@ int intel_hdcp_read_valid_bksv(struct
> intel_digital_port *dig_port,
> /* Is HDCP1.4 capable on Platform and Sink */
> bool intel_hdcp_capable(struct intel_connector *connector)
> {
> - struct intel_digital_port *dig_port =
> intel_attached_dig_port(connector);
> + struct intel_digital_port *dig_port;
> const struct intel_hdcp_shim *shim = connector->hdcp.shim;
> bool capable = false;
> u8 bksv[5];
>
> + if (!connector->encoder)
> + return -ENODEV;
I assume this is needed when called from i915_hdcp_sink_capability
debugfs entry. That one is lacking the locking for the connector, but is
that entry really needed? We print the same info already from the
i915_display_info entry which has the proper locking and encoder check.
> +
> + dig_port = intel_attached_dig_port(connector);
> +
> if (!shim)
> return capable;
>
> @@ -156,11 +161,16 @@ bool intel_hdcp_capable(struct intel_connector
> *connector)
> /* Is HDCP2.2 capable on Platform and Sink */
> bool intel_hdcp2_capable(struct intel_connector *connector)
> {
> - struct intel_digital_port *dig_port =
> intel_attached_dig_port(connector);
> + struct intel_digital_port *dig_port;
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_hdcp *hdcp = >hdcp;
> bool capable = false;
>
> + if (!connector->encoder)
> + return -ENODEV;
> +
> + dig_port = intel_attached_dig_port(connector);
> +
> /* I915 support for HDCP2.2 */
> if (!hdcp->hdcp2_supported)
> return false;
> --
> 2.26.2
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Disable runtime power management during shutdown
On Thu, Jan 28, 2021 at 12:31:38AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915: Disable runtime power management during shutdown > URL : https://patchwork.freedesktop.org/series/86362/ > State : success Thanks for the review, pushed to -din with a code comment addition. > > == Summary == > > CI Bug Log - changes from CI_DRM_9688_full -> Patchwork_19524_full > > > Summary > --- > > **SUCCESS** > > No regressions found. > > > > Known issues > > > Here are the changes found in Patchwork_19524_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_ctx_persistence@close-replace-race: > - shard-glk: [PASS][1] -> [TIMEOUT][2] ([i915#2918]) >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk6/igt@gem_ctx_persiste...@close-replace-race.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-glk7/igt@gem_ctx_persiste...@close-replace-race.html > > * igt@gem_exec_fair@basic-deadline: > - shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2846]) >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-tglb5/igt@gem_exec_f...@basic-deadline.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-tglb6/igt@gem_exec_f...@basic-deadline.html > - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2846]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk7/igt@gem_exec_f...@basic-deadline.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-glk1/igt@gem_exec_f...@basic-deadline.html > > * igt@gem_exec_fair@basic-none-solo@rcs0: > - shard-apl: [PASS][7] -> [FAIL][8] ([i915#2842]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html > > * igt@gem_exec_fair@basic-pace-share@rcs0: > - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar > issue >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-tglb2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html > > * igt@gem_exec_fair@basic-throttle@rcs0: > - shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842]) >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html > - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2849]) >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-iclb2/igt@gem_exec_fair@basic-throt...@rcs0.html > > * igt@gem_exec_params@no-vebox: > - shard-iclb: NOTRUN -> [SKIP][15] ([fdo#109283]) >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-iclb7/igt@gem_exec_par...@no-vebox.html > > * igt@gen7_exec_parse@basic-allowed: > - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271]) +9 similar > issues >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-skl8/igt@gen7_exec_pa...@basic-allowed.html > > * igt@i915_pm_dc@dc6-psr: > - shard-iclb: [PASS][17] -> [FAIL][18] ([i915#454]) >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-iclb5/igt@i915_pm...@dc6-psr.html >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-iclb2/igt@i915_pm...@dc6-psr.html > > * igt@i915_pm_rpm@system-suspend-modeset: > - shard-kbl: [PASS][19] -> [INCOMPLETE][20] ([i915#151]) >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9688/shard-kbl7/igt@i915_pm_...@system-suspend-modeset.html >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-kbl3/igt@i915_pm_...@system-suspend-modeset.html > > * igt@kms_chamelium@hdmi-cmp-planar-formats: > - shard-glk: NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) > +1 similar issue >[21]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-glk1/igt@kms_chamel...@hdmi-cmp-planar-formats.html > > * igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes: > - shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827]) > +2 similar issues >[22]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19524/shard-skl8/igt@kms_color_chamel...@pipe-invalid-ctm-matrix-sizes.html > > * igt@kms_cursor_crc@pipe-a-cursor-256x85-onscreen: > - shard-skl: [PASS][23] -> [FAIL][24]
[Intel-gfx] [PATCH v2 12/14] drm/i915: Use .disable_clock() for pll sanitation
From: Ville Syrjälä
Instead of every new platform having yet another masive
copy of the whole PLL sanitation code, let's just reuse the
.disable_clock() hook for this purpose. We do need to plug
this into the ICL+ DSI code for that, but fortunately it
already has a suitable function we can use.
We do lose the debug message though on account of not bothering
to check if the clock is actually enabled or not before turning
it off. We could introduce yet another vfunc to query the current
state, but not sure it's worth the hassle?
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 92 +---
2 files changed, 3 insertions(+), 90 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 9d245a689323..a7edfaa09035 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1940,6 +1940,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
encoder->pipe_mask = ~0;
encoder->power_domain = POWER_DOMAIN_PORT_DSI;
encoder->get_power_domains = gen11_dsi_get_power_domains;
+ encoder->disable_clock = gen11_dsi_gate_clocks;
/* register DSI connector with DRM subsystem */
drm_connector_init(dev, connector, _dsi_connector_funcs,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 41287a496e38..f68ccde2bc7a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3110,23 +3110,6 @@ hsw_set_signal_levels(struct intel_dp *intel_dp,
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
}
-static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
-enum phy phy)
-{
- if (IS_ROCKETLAKE(dev_priv)) {
- return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
- } else if (intel_phy_is_combo(dev_priv, phy)) {
- return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
- } else if (intel_phy_is_tc(dev_priv, phy)) {
- enum tc_port tc_port = intel_port_to_tc(dev_priv,
- (enum port)phy);
-
- return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
- }
-
- return 0;
-}
-
static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t
reg,
u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
{
@@ -3262,75 +3245,6 @@ static void icl_ddi_combo_disable_clock(struct
intel_encoder *encoder)
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
-static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
- u32 port_mask, bool ddi_clk_needed)
-{
- enum port port;
- u32 val;
-
- for_each_port_masked(port, port_mask) {
- enum phy phy = intel_port_to_phy(dev_priv, port);
- bool ddi_clk_off;
-
- val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
- ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
-
- if (ddi_clk_needed == !ddi_clk_off)
- continue;
-
- /*
-* Punt on the case now where clock is gated, but it would
-* be needed by the port. Something else is really broken then.
-*/
- if (drm_WARN_ON(_priv->drm, ddi_clk_needed))
- continue;
-
- drm_notice(_priv->drm,
- "PHY %c is disabled with an ungated DDI clock, gate
it\n",
- phy_name(phy));
- val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
- intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
- }
-}
-
-static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
- u32 port_mask, bool ddi_clk_needed)
-{
- enum port port;
- bool ddi_clk_off;
- u32 val;
- i915_reg_t reg;
-
- for_each_port_masked(port, port_mask) {
- enum phy phy = intel_port_to_phy(dev_priv, port);
-
- if (IS_ALDERLAKE_S(dev_priv))
- reg = ADLS_DPCLKA_CFGCR(phy);
- else
- reg = ICL_DPCLKA_CFGCR0;
-
- val = intel_de_read(dev_priv, reg);
- ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
- phy);
-
- if (ddi_clk_needed == !ddi_clk_off)
- continue;
-
- /*
-* Punt on the case now where clock is gated, but it would
-* be needed by the port. Something else is really broken then.
-*/
- if (drm_WARN_ON(_priv->drm, ddi_clk_needed))
-
[Intel-gfx] [PATCH v2 11/14] drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable, disable}_clock()
From: Ville Syrjälä
Since .{enable,disable}_clock() are already vfuncs it's a bit silly to
have if-ladders inside them. Just provide specialized version for adl-s
and rkl so we don't need any of that.
v2: s/dev_priv/i915/ (Lucas)
Fix typos in platform names (Lucas)
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 91
1 file changed, 62 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index d195837f0a9f..41287a496e38 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3153,6 +3153,56 @@ static void _cnl_ddi_disable_clock(struct
drm_i915_private *i915, i915_reg_t reg
mutex_unlock(>dpll.lock);
}
+static void adls_ddi_enable_clock(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ if (drm_WARN_ON(>drm, !pll))
+ return;
+
+ _cnl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
+ ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
+ pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
+ ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+}
+
+static void adls_ddi_disable_clock(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ _cnl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
+ ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+}
+
+static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ if (drm_WARN_ON(>drm, !pll))
+ return;
+
+ _cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
+ RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+ RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
+ RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+}
+
+static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ _cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
+ RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+}
+
static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -3193,43 +3243,23 @@ static void icl_ddi_combo_enable_clock(struct
intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- u32 mask, sel;
- i915_reg_t reg;
-
- if (IS_ALDERLAKE_S(dev_priv)) {
- reg = ADLS_DPCLKA_CFGCR(phy);
- mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy);
- sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
- } else if (IS_ROCKETLAKE(dev_priv)) {
- reg = ICL_DPCLKA_CFGCR0;
- mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
- } else {
- reg = ICL_DPCLKA_CFGCR0;
- mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
- }
if (drm_WARN_ON(_priv->drm, !pll))
return;
- _cnl_ddi_enable_clock(dev_priv, reg, mask, sel,
- icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
+ _cnl_ddi_enable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
+ ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+ ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
+ ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- i915_reg_t reg;
- if (IS_ALDERLAKE_S(dev_priv))
- reg = ADLS_DPCLKA_CFGCR(phy);
- else
- reg = ICL_DPCLKA_CFGCR0;
-
- _cnl_ddi_disable_clock(dev_priv, reg,
-
[Intel-gfx] [PATCH v2 14/14] drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routing
From: Ville Syrjälä
Convert the remaining 'dev_priv's to 'i915's in the DDI
clock routing functions.
Cc: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 38
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 89f4e3615a2e..c1b42e72a6b5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3189,23 +3189,23 @@ static void rkl_ddi_disable_clock(struct intel_encoder
*encoder)
static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
- enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
- if (drm_WARN_ON(_priv->drm, !pll))
+ if (drm_WARN_ON(>drm, !pll))
return;
/*
* If we fail this, something went very wrong: first 2 PLLs should be
* used by first 2 phys and last 2 PLLs by last phys
*/
- if (drm_WARN_ON(_priv->drm,
+ if (drm_WARN_ON(>drm,
(pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
(pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
return;
- _cnl_ddi_enable_clock(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+ _cnl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
@@ -3213,24 +3213,24 @@ static void dg1_ddi_enable_clock(struct intel_encoder
*encoder,
static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
- _cnl_ddi_disable_clock(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+ _cnl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state
*crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
- enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
- if (drm_WARN_ON(_priv->drm, !pll))
+ if (drm_WARN_ON(>drm, !pll))
return;
- _cnl_ddi_enable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
+ _cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
@@ -3238,10 +3238,10 @@ static void icl_ddi_combo_enable_clock(struct
intel_encoder *encoder,
static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
- _cnl_ddi_disable_clock(dev_priv, ICL_DPCLKA_CFGCR0,
+ _cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
@@ -3407,7 +3407,7 @@ static void intel_ddi_disable_clock(struct intel_encoder
*encoder)
void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u32 port_mask;
bool ddi_clk_needed;
@@ -3427,7 +3427,7 @@ void icl_sanitize_encoder_pll_mapping(struct
intel_encoder *encoder)
* In the unlikely case that BIOS enables DP in MST mode, just
* warn since our MST HW readout is incomplete.
*/
- if (drm_WARN_ON(_priv->drm, is_mst))
+ if (drm_WARN_ON(>drm, is_mst))
return;
}
@@ -3442,11 +3442,11 @@ void icl_sanitize_encoder_pll_mapping(struct
intel_encoder
[Intel-gfx] [PATCH v2 13/14] drm/i915: Relocate icl_sanitize_encoder_pll_mapping()
From: Ville Syrjälä
Move icl_sanitize_encoder_pll_mapping() out from the middle
of the .{enable,disable}_clock() functions.
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 112 +++
1 file changed, 56 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index f68ccde2bc7a..89f4e3615a2e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3245,62 +3245,6 @@ static void icl_ddi_combo_disable_clock(struct
intel_encoder *encoder)
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
-void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 port_mask;
- bool ddi_clk_needed;
-
- /*
-* In case of DP MST, we sanitize the primary encoder only, not the
-* virtual ones.
-*/
- if (encoder->type == INTEL_OUTPUT_DP_MST)
- return;
-
- if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
- u8 pipe_mask;
- bool is_mst;
-
- intel_ddi_get_encoder_pipes(encoder, _mask, _mst);
- /*
-* In the unlikely case that BIOS enables DP in MST mode, just
-* warn since our MST HW readout is incomplete.
-*/
- if (drm_WARN_ON(_priv->drm, is_mst))
- return;
- }
-
- port_mask = BIT(encoder->port);
- ddi_clk_needed = encoder->base.crtc;
-
- if (encoder->type == INTEL_OUTPUT_DSI) {
- struct intel_encoder *other_encoder;
-
- port_mask = intel_dsi_encoder_ports(encoder);
- /*
-* Sanity check that we haven't incorrectly registered another
-* encoder using any of the ports of this DSI encoder.
-*/
- for_each_intel_encoder(_priv->drm, other_encoder) {
- if (other_encoder == encoder)
- continue;
-
- if (drm_WARN_ON(_priv->drm,
- port_mask & BIT(other_encoder->port)))
- return;
- }
- /*
-* For DSI we keep the ddi clocks gated
-* except during enable/disable sequence.
-*/
- ddi_clk_needed = false;
- }
-
- if (!ddi_clk_needed && encoder->disable_clock)
- encoder->disable_clock(encoder);
-}
-
static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -3461,6 +3405,62 @@ static void intel_ddi_disable_clock(struct intel_encoder
*encoder)
encoder->disable_clock(encoder);
}
+void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ u32 port_mask;
+ bool ddi_clk_needed;
+
+ /*
+* In case of DP MST, we sanitize the primary encoder only, not the
+* virtual ones.
+*/
+ if (encoder->type == INTEL_OUTPUT_DP_MST)
+ return;
+
+ if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
+ u8 pipe_mask;
+ bool is_mst;
+
+ intel_ddi_get_encoder_pipes(encoder, _mask, _mst);
+ /*
+* In the unlikely case that BIOS enables DP in MST mode, just
+* warn since our MST HW readout is incomplete.
+*/
+ if (drm_WARN_ON(_priv->drm, is_mst))
+ return;
+ }
+
+ port_mask = BIT(encoder->port);
+ ddi_clk_needed = encoder->base.crtc;
+
+ if (encoder->type == INTEL_OUTPUT_DSI) {
+ struct intel_encoder *other_encoder;
+
+ port_mask = intel_dsi_encoder_ports(encoder);
+ /*
+* Sanity check that we haven't incorrectly registered another
+* encoder using any of the ports of this DSI encoder.
+*/
+ for_each_intel_encoder(_priv->drm, other_encoder) {
+ if (other_encoder == encoder)
+ continue;
+
+ if (drm_WARN_ON(_priv->drm,
+ port_mask & BIT(other_encoder->port)))
+ return;
+ }
+ /*
+* For DSI we keep the ddi clocks gated
+* except during enable/disable sequence.
+*/
+ ddi_clk_needed = false;
+ }
+
+ if (!ddi_clk_needed && encoder->disable_clock)
+ encoder->disable_clock(encoder);
+}
+
static void
[Intel-gfx] [PATCH v2 10/14] drm/i915: Extract _cnl_ddi_{enable, disable}_clock()
From: Ville Syrjälä
All the DPCLKA_CFGCR handling follows a common pattern. Let's
extract that to a small helper that just takes a few parameters
each caller can customize.
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 108 +--
1 file changed, 44 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 0a2eb426616b..d195837f0a9f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3127,11 +3127,37 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct
drm_i915_private *dev_priv,
return 0;
}
+static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t
reg,
+ u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
+{
+ mutex_lock(>dpll.lock);
+
+ intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
+
+ /*
+* "This step and the step before must be
+* done with separate register writes."
+*/
+ intel_de_rmw(i915, reg, clk_off, 0);
+
+ mutex_unlock(>dpll.lock);
+}
+
+static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t
reg,
+ u32 clk_off)
+{
+ mutex_lock(>dpll.lock);
+
+ intel_de_rmw(i915, reg, 0, clk_off);
+
+ mutex_unlock(>dpll.lock);
+}
+
static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
if (drm_WARN_ON(_priv->drm, !pll))
@@ -3146,16 +3172,10 @@ static void dg1_ddi_enable_clock(struct intel_encoder
*encoder,
(pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
return;
- mutex_lock(_priv->dpll.lock);
-
- intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
-DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
-DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy));
-
- intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
-DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy), 0);
-
- mutex_unlock(_priv->dpll.lock);
+ _cnl_ddi_enable_clock(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+ DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+ DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
+ DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
@@ -3163,19 +3183,15 @@ static void dg1_ddi_disable_clock(struct intel_encoder
*encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- mutex_lock(_priv->dpll.lock);
-
- intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
-0, DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
-
- mutex_unlock(_priv->dpll.lock);
+ _cnl_ddi_disable_clock(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+ DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
}
static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
u32 mask, sel;
i915_reg_t reg;
@@ -3197,24 +3213,8 @@ static void icl_ddi_combo_enable_clock(struct
intel_encoder *encoder,
if (drm_WARN_ON(_priv->drm, !pll))
return;
- mutex_lock(_priv->dpll.lock);
-
- /*
-* Even though this register references DDIs, note that we
-* want to pass the PHY rather than the port (DDI). For
-* ICL, port=phy in all cases so it doesn't matter, but for
-* EHL the bspec notes the following:
-*
-* "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
-* Clock Select chooses the PLL for both DDIA and DDID and
-* drives port A in all cases."
-*/
- intel_de_rmw(dev_priv, reg, mask, sel);
-
- intel_de_rmw(dev_priv, reg,
-icl_dpclka_cfgcr0_clk_off(dev_priv, phy), 0);
-
- mutex_unlock(_priv->dpll.lock);
+ _cnl_ddi_enable_clock(dev_priv, reg, mask, sel,
+ icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
}
static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
@@ -3223,19 +3223,13 @@ static void
[Intel-gfx] [PATCH v2 09/14] drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()
From: Ville Syrjälä The other DDI .enable_clock() functions are trying to protect us against pll==NULL. A bit tempted to throw out all the WARNs as just unnecessary noise, but I guess they might have some use when poking around the shared_dpll code (not sure it wouldn't oops elsewhere though). So let's unify it all and sprinkle in the missing WARNs for icl/dg1. Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 0b2a1e0c1b8b..0a2eb426616b 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3134,6 +3134,9 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder, struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + if (drm_WARN_ON(_priv->drm, !pll)) + return; + /* * If we fail this, something went very wrong: first 2 PLLs should be * used by first 2 phys and last 2 PLLs by last phys @@ -3191,6 +3194,9 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); } + if (drm_WARN_ON(_priv->drm, !pll)) + return; + mutex_lock(_priv->dpll.lock); /* -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 08/14] drm/i915: Sprinkle a few missing locks around shared DDI clock registers
From: Ville Syrjälä The current code attempts to protect the RMWs into global clock routing registers with a mutex, but forgets to do so in a few places. Let's remedy that. Note that at the moment we serialize all modesets onto single wq, so this shouldn't actually matter. But maybe one day we wish to attempt parallel modesets again... Reviewed-by: Lucas De Marchi Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 76aa7d2dba52..0b2a1e0c1b8b 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3457,8 +3457,12 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum port port = encoder->port; + mutex_lock(>dpll.lock); + intel_de_rmw(i915, DPCLKA_CFGCR0, 0, DPCLKA_CFGCR0_DDI_CLK_OFF(port)); + + mutex_unlock(>dpll.lock); } static void skl_ddi_enable_clock(struct intel_encoder *encoder, @@ -3487,8 +3491,12 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum port port = encoder->port; + mutex_lock(>dpll.lock); + intel_de_rmw(i915, DPLL_CTRL2, 0, DPLL_CTRL2_DDI_CLK_OFF(port)); + + mutex_unlock(>dpll.lock); } static void hsw_ddi_enable_clock(struct intel_encoder *encoder, -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 07/14] drm/i915: Use intel_de_rmw() for DDI clock routing
From: Ville Syrjälä
The DDI clock routing programming is riddled with shared
registers, forcing us to do a lot of RMW. Switch over to
intel_de_rmw() to make that a bit less obnoxious.
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 77 +---
1 file changed, 28 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index d688ef231eeb..76aa7d2dba52 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3133,7 +3133,6 @@ static void dg1_ddi_enable_clock(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- u32 val;
/*
* If we fail this, something went very wrong: first 2 PLLs should be
@@ -3146,17 +3145,12 @@ static void dg1_ddi_enable_clock(struct intel_encoder
*encoder,
mutex_lock(_priv->dpll.lock);
- val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
- drm_WARN_ON(_priv->drm,
- (val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
+ intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy));
- val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
- val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
- intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
- intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
-
- val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
- intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+ intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy), 0);
mutex_unlock(_priv->dpll.lock);
}
@@ -3168,8 +3162,8 @@ static void dg1_ddi_disable_clock(struct intel_encoder
*encoder)
mutex_lock(_priv->dpll.lock);
- intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
-DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+ intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+0, DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
mutex_unlock(_priv->dpll.lock);
}
@@ -3180,7 +3174,7 @@ static void icl_ddi_combo_enable_clock(struct
intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- u32 val, mask, sel;
+ u32 mask, sel;
i915_reg_t reg;
if (IS_ALDERLAKE_S(dev_priv)) {
@@ -3199,10 +3193,6 @@ static void icl_ddi_combo_enable_clock(struct
intel_encoder *encoder,
mutex_lock(_priv->dpll.lock);
- val = intel_de_read(dev_priv, reg);
- drm_WARN_ON(_priv->drm,
- (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
-
/*
* Even though this register references DDIs, note that we
* want to pass the PHY rather than the port (DDI). For
@@ -3213,13 +3203,10 @@ static void icl_ddi_combo_enable_clock(struct
intel_encoder *encoder,
* Clock Select chooses the PLL for both DDIA and DDID and
* drives port A in all cases."
*/
- val &= ~mask;
- val |= sel;
- intel_de_write(dev_priv, reg, val);
- intel_de_posting_read(dev_priv, reg);
+ intel_de_rmw(dev_priv, reg, mask, sel);
- val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
- intel_de_write(dev_priv, reg, val);
+ intel_de_rmw(dev_priv, reg,
+icl_dpclka_cfgcr0_clk_off(dev_priv, phy), 0);
mutex_unlock(_priv->dpll.lock);
}
@@ -3228,7 +3215,6 @@ static void icl_ddi_combo_disable_clock(struct
intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- u32 val;
i915_reg_t reg;
mutex_lock(_priv->dpll.lock);
@@ -3238,10 +3224,10 @@ static void icl_ddi_combo_disable_clock(struct
intel_encoder *encoder)
else
reg = ICL_DPCLKA_CFGCR0;
- val = intel_de_read(dev_priv, reg);
- val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
+ mutex_lock(_priv->dpll.lock);
- intel_de_write(dev_priv, reg, val);
+ intel_de_rmw(dev_priv, reg,
+0, icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
mutex_unlock(_priv->dpll.lock);
}
@@ -3446,25 +3432,22 @@ static void cnl_ddi_enable_clock(struct intel_encoder
*encoder,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum port port = encoder->port;
-
[Intel-gfx] [PATCH v2 06/14] drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs
From: Ville Syrjälä
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 163 ++-
1 file changed, 102 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index cbeb75d00013..d688ef231eeb 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3174,8 +3174,8 @@ static void dg1_ddi_disable_clock(struct intel_encoder
*encoder)
mutex_unlock(_priv->dpll.lock);
}
-static void icl_map_plls_to_ports(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
@@ -3203,22 +3203,20 @@ static void icl_map_plls_to_ports(struct intel_encoder
*encoder,
drm_WARN_ON(_priv->drm,
(val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
- if (intel_phy_is_combo(dev_priv, phy)) {
- /*
-* Even though this register references DDIs, note that we
-* want to pass the PHY rather than the port (DDI). For
-* ICL, port=phy in all cases so it doesn't matter, but for
-* EHL the bspec notes the following:
-*
-* "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
-* Clock Select chooses the PLL for both DDIA and DDID and
-* drives port A in all cases."
-*/
- val &= ~mask;
- val |= sel;
- intel_de_write(dev_priv, reg, val);
- intel_de_posting_read(dev_priv, reg);
- }
+ /*
+* Even though this register references DDIs, note that we
+* want to pass the PHY rather than the port (DDI). For
+* ICL, port=phy in all cases so it doesn't matter, but for
+* EHL the bspec notes the following:
+*
+* "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
+* Clock Select chooses the PLL for both DDIA and DDID and
+* drives port A in all cases."
+*/
+ val &= ~mask;
+ val |= sel;
+ intel_de_write(dev_priv, reg, val);
+ intel_de_posting_read(dev_priv, reg);
val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
intel_de_write(dev_priv, reg, val);
@@ -3226,7 +3224,7 @@ static void icl_map_plls_to_ports(struct intel_encoder
*encoder,
mutex_unlock(_priv->dpll.lock);
}
-static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
+static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
@@ -3375,47 +3373,71 @@ void icl_sanitize_encoder_pll_mapping(struct
intel_encoder *encoder)
icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
}
-static void intel_ddi_clk_select(struct intel_encoder *encoder,
-const struct intel_crtc_state *crtc_state)
+static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum port port = encoder->port;
- enum phy phy = intel_port_to_phy(dev_priv, port);
+
+ if (drm_WARN_ON(>drm, !pll))
+ return;
+
+ /*
+* "For DDIC and
[Intel-gfx] [PATCH v2 05/14] drm/i915: Convert DG1 over to .{enable, disable}_clock()
From: Ville Syrjälä
Replace dg1_{map,unmap}_plls_to_ports() with the appropriate
encoder vfuncs. And let's relocate the disable function next to
the enable function while at it.
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 43
1 file changed, 21 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9ea408ff254b..cbeb75d00013 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3127,8 +3127,8 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct
drm_i915_private *dev_priv,
return 0;
}
-static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
@@ -3161,6 +3161,19 @@ static void dg1_map_plls_to_ports(struct intel_encoder
*encoder,
mutex_unlock(_priv->dpll.lock);
}
+static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+ mutex_lock(_priv->dpll.lock);
+
+ intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
+DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+
+ mutex_unlock(_priv->dpll.lock);
+}
+
static void icl_map_plls_to_ports(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -3213,19 +3226,6 @@ static void icl_map_plls_to_ports(struct intel_encoder
*encoder,
mutex_unlock(_priv->dpll.lock);
}
-static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-
- mutex_lock(_priv->dpll.lock);
-
- intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
-DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
-
- mutex_unlock(_priv->dpll.lock);
-}
-
static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -4007,9 +4007,7 @@ static void intel_ddi_pre_enable(struct
intel_atomic_state *state,
drm_WARN_ON(_priv->drm, crtc_state->has_pch_encoder);
- if (IS_DG1(dev_priv))
- dg1_map_plls_to_ports(encoder, crtc_state);
- else if (INTEL_GEN(dev_priv) >= 11)
+ if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11)
icl_map_plls_to_ports(encoder, crtc_state);
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -4210,9 +4208,7 @@ static void intel_ddi_post_disable(struct
intel_atomic_state *state,
intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
old_conn_state);
- if (IS_DG1(dev_priv))
- dg1_unmap_plls_to_ports(encoder);
- else if (INTEL_GEN(dev_priv) >= 11)
+ if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11)
icl_unmap_plls_to_ports(encoder);
if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
@@ -5657,7 +5653,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
encoder->cloneable = 0;
encoder->pipe_mask = ~0;
- if (IS_CANNONLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv)) {
+ encoder->enable_clock = dg1_ddi_enable_clock;
+ encoder->disable_clock = dg1_ddi_disable_clock;
+ } else if (IS_CANNONLAKE(dev_priv)) {
encoder->enable_clock = cnl_ddi_enable_clock;
encoder->disable_clock = cnl_ddi_disable_clock;
} else if (IS_GEN9_BC(dev_priv)) {
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 04/14] drm/i195: Extract cnl_ddi_{enable, disable}_clock()
From: Ville Syrjälä
Extract the DDI clock routing for CNL into the new vfuncs.
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 62
1 file changed, 42 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2a8e47a3a878..9ea408ff254b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3381,7 +3381,6 @@ static void intel_ddi_clk_select(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
enum phy phy = intel_port_to_phy(dev_priv, port);
- u32 val;
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
if (drm_WARN_ON(_priv->drm, !pll))
@@ -3400,21 +3399,6 @@ static void intel_ddi_clk_select(struct intel_encoder
*encoder,
*/
intel_de_write(dev_priv, DDI_CLK_SEL(port),
DDI_CLK_SEL_MG);
- } else if (IS_CANNONLAKE(dev_priv)) {
- /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
- val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
- val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
- val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
- intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
-
- /*
-* Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
-* This step and the step before must be done with separate
-* register writes.
-*/
- val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
- val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
- intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
}
mutex_unlock(_priv->dpll.lock);
@@ -3431,12 +3415,47 @@ static void intel_ddi_clk_disable(struct intel_encoder
*encoder)
(IS_JSL_EHL(dev_priv) && port >= PORT_C))
intel_de_write(dev_priv, DDI_CLK_SEL(port),
DDI_CLK_SEL_NONE);
- } else if (IS_CANNONLAKE(dev_priv)) {
- intel_de_write(dev_priv, DPCLKA_CFGCR0,
- intel_de_read(dev_priv, DPCLKA_CFGCR0) |
DPCLKA_CFGCR0_DDI_CLK_OFF(port));
}
}
+static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ enum port port = encoder->port;
+ u32 val;
+
+ if (drm_WARN_ON(>drm, !pll))
+ return;
+
+ mutex_lock(>dpll.lock);
+
+ val = intel_de_read(i915, DPCLKA_CFGCR0);
+ val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+ val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+ intel_de_write(i915, DPCLKA_CFGCR0, val);
+
+ /*
+* "This step and the step before must be
+* done with separate register writes."
+*/
+ val = intel_de_read(i915, DPCLKA_CFGCR0);
+ val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ intel_de_write(i915, DPCLKA_CFGCR0, val);
+
+ mutex_unlock(>dpll.lock);
+}
+
+static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+
+ intel_de_write(i915, DPCLKA_CFGCR0,
+ intel_de_read(i915, DPCLKA_CFGCR0) |
DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+}
+
static void skl_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -5638,7 +5657,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
encoder->cloneable = 0;
encoder->pipe_mask = ~0;
- if (IS_GEN9_BC(dev_priv)) {
+ if (IS_CANNONLAKE(dev_priv)) {
+ encoder->enable_clock = cnl_ddi_enable_clock;
+ encoder->disable_clock = cnl_ddi_disable_clock;
+ } else if (IS_GEN9_BC(dev_priv)) {
encoder->enable_clock = skl_ddi_enable_clock;
encoder->disable_clock = skl_ddi_disable_clock;
} else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 03/14] drm/i915: Extract skl_ddi_{enable, disable}_clock()
From: Ville Syrjälä
Extract the DDI clock routing clode for skl/derivatives
into the new encoder vfuncs.
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 53 +---
1 file changed, 38 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index b8af7b7df12a..2a8e47a3a878 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3415,17 +3415,6 @@ static void intel_ddi_clk_select(struct intel_encoder
*encoder,
val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
- } else if (IS_GEN9_BC(dev_priv)) {
- /* DDI -> PLL mapping */
- val = intel_de_read(dev_priv, DPLL_CTRL2);
-
- val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
-DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
- val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
- DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
-
- intel_de_write(dev_priv, DPLL_CTRL2, val);
-
}
mutex_unlock(_priv->dpll.lock);
@@ -3445,12 +3434,43 @@ static void intel_ddi_clk_disable(struct intel_encoder
*encoder)
} else if (IS_CANNONLAKE(dev_priv)) {
intel_de_write(dev_priv, DPCLKA_CFGCR0,
intel_de_read(dev_priv, DPCLKA_CFGCR0) |
DPCLKA_CFGCR0_DDI_CLK_OFF(port));
- } else if (IS_GEN9_BC(dev_priv)) {
- intel_de_write(dev_priv, DPLL_CTRL2,
- intel_de_read(dev_priv, DPLL_CTRL2) |
DPLL_CTRL2_DDI_CLK_OFF(port));
}
}
+static void skl_ddi_enable_clock(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ enum port port = encoder->port;
+ u32 val;
+
+ if (drm_WARN_ON(>drm, !pll))
+ return;
+
+ mutex_lock(>dpll.lock);
+
+ val = intel_de_read(i915, DPLL_CTRL2);
+
+ val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
+DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
+ val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
+ DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
+
+ intel_de_write(i915, DPLL_CTRL2, val);
+
+ mutex_unlock(>dpll.lock);
+}
+
+static void skl_ddi_disable_clock(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+
+ intel_de_write(i915, DPLL_CTRL2,
+ intel_de_read(i915, DPLL_CTRL2) |
DPLL_CTRL2_DDI_CLK_OFF(port));
+}
+
static void hsw_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -5618,7 +5638,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
encoder->cloneable = 0;
encoder->pipe_mask = ~0;
- if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+ if (IS_GEN9_BC(dev_priv)) {
+ encoder->enable_clock = skl_ddi_enable_clock;
+ encoder->disable_clock = skl_ddi_disable_clock;
+ } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
encoder->enable_clock = hsw_ddi_enable_clock;
encoder->disable_clock = hsw_ddi_disable_clock;
}
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 02/14] drm/i915: Extract hsw_ddi_{enable, disable}_clock()
From: Ville Syrjälä
Yank out the HSW/BDW code from intel_ddi_clk_{select,disable}()
and put it into the new encoder .{enable,disable}_clock() vfuncs.
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 32 +++-
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index fa032e377ebc..b8af7b7df12a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3426,9 +3426,6 @@ static void intel_ddi_clk_select(struct intel_encoder
*encoder,
intel_de_write(dev_priv, DPLL_CTRL2, val);
- } else if (INTEL_GEN(dev_priv) < 9) {
- intel_de_write(dev_priv, PORT_CLK_SEL(port),
- hsw_pll_to_ddi_pll_sel(pll));
}
mutex_unlock(_priv->dpll.lock);
@@ -3451,12 +3448,30 @@ static void intel_ddi_clk_disable(struct intel_encoder
*encoder)
} else if (IS_GEN9_BC(dev_priv)) {
intel_de_write(dev_priv, DPLL_CTRL2,
intel_de_read(dev_priv, DPLL_CTRL2) |
DPLL_CTRL2_DDI_CLK_OFF(port));
- } else if (INTEL_GEN(dev_priv) < 9) {
- intel_de_write(dev_priv, PORT_CLK_SEL(port),
- PORT_CLK_SEL_NONE);
}
}
+static void hsw_ddi_enable_clock(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ enum port port = encoder->port;
+
+ if (drm_WARN_ON(>drm, !pll))
+ return;
+
+ intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
+}
+
+static void hsw_ddi_disable_clock(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+
+ intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
+}
+
static void intel_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
@@ -5603,6 +5618,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
encoder->cloneable = 0;
encoder->pipe_mask = ~0;
+ if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+ encoder->enable_clock = hsw_ddi_enable_clock;
+ encoder->disable_clock = hsw_ddi_disable_clock;
+ }
+
if (IS_DG1(dev_priv))
encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
else if (IS_ROCKETLAKE(dev_priv))
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 01/14] drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs
From: Ville Syrjälä
The current code dealing with the clock routing for DDI encoders
is a maintenance nightmare. Let's start cleaning it up by allowing
the encoder to provide vfuncs for enablign/disabling the clock.
We leave them initially unimplemented, falling back to the old
if-else approach.
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 29 +++
.../drm/i915/display/intel_display_types.h| 6
2 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5bc5033a2dea..fa032e377ebc 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3457,6 +3457,23 @@ static void intel_ddi_clk_disable(struct intel_encoder
*encoder)
}
}
+static void intel_ddi_enable_clock(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ if (encoder->enable_clock)
+ encoder->enable_clock(encoder, crtc_state);
+ else
+ intel_ddi_clk_select(encoder, crtc_state);
+}
+
+static void intel_ddi_disable_clock(struct intel_encoder *encoder)
+{
+ if (encoder->disable_clock)
+ encoder->disable_clock(encoder);
+ else
+ intel_ddi_clk_disable(encoder);
+}
+
static void
icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
const struct intel_crtc_state *crtc_state)
@@ -3701,7 +3718,7 @@ static void tgl_ddi_pre_enable_dp(struct
intel_atomic_state *state,
* hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
* configure the PLL to port mapping here.
*/
- intel_ddi_clk_select(encoder, crtc_state);
+ intel_ddi_enable_clock(encoder, crtc_state);
/* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
if (!intel_phy_is_tc(dev_priv, phy) ||
@@ -3822,7 +3839,7 @@ static void hsw_ddi_pre_enable_dp(struct
intel_atomic_state *state,
intel_pps_on(intel_dp);
- intel_ddi_clk_select(encoder, crtc_state);
+ intel_ddi_enable_clock(encoder, crtc_state);
if (!intel_phy_is_tc(dev_priv, phy) ||
dig_port->tc_mode != TC_PORT_TBT_ALT) {
@@ -3897,7 +3914,7 @@ static void intel_ddi_pre_enable_hdmi(struct
intel_atomic_state *state,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
- intel_ddi_clk_select(encoder, crtc_state);
+ intel_ddi_enable_clock(encoder, crtc_state);
drm_WARN_ON(_priv->drm, dig_port->ddi_io_wakeref);
dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
@@ -4049,7 +4066,7 @@ static void intel_ddi_post_disable_dp(struct
intel_atomic_state *state,
dig_port->ddi_io_power_domain,
fetch_and_zero(_port->ddi_io_wakeref));
- intel_ddi_clk_disable(encoder);
+ intel_ddi_disable_clock(encoder);
}
static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
@@ -4072,7 +4089,7 @@ static void intel_ddi_post_disable_hdmi(struct
intel_atomic_state *state,
dig_port->ddi_io_power_domain,
fetch_and_zero(_port->ddi_io_wakeref));
- intel_ddi_clk_disable(encoder);
+ intel_ddi_disable_clock(encoder);
intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
}
@@ -4172,7 +4189,7 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state
*state,
intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
intel_disable_ddi_buf(encoder, old_crtc_state);
- intel_ddi_clk_disable(encoder);
+ intel_ddi_disable_clock(encoder);
val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 39397748b4b0..085162616112 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -219,6 +219,12 @@ struct intel_encoder {
* encoders have been disabled and suspended.
*/
void (*shutdown)(struct intel_encoder *encoder);
+ /*
+* Enable/disable the clock to the port.
+*/
+ void (*enable_clock)(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state);
+ void (*disable_clock)(struct intel_encoder *encoder);
enum hpd_pin hpd_pin;
enum intel_display_power_domain power_domain;
/* for communication with audio component; protected by av_mutex */
--
2.26.2
___
Intel-gfx mailing list
[Intel-gfx] [PATCH v2 00/14] drm/i915: Clean up the DDI clock routing mess
From: Ville Syrjälä
A revised version of the DDI clock routing refactoring.
Dropped the icl_dpclka_cfgcr0_reg() & co. extraction as Lucas
suggested since they got removed at the end anyway. Was a bit
worried it might make things more confusing due to
icl_dpclka_cfgcr0_clk_off() already being there, but looks OK
in the end anyway I think.
Also did a bunch if s/dev_priv/i915/ based on Lucas's review.
Didn't feel comfortable sneaking all of it into the other patches
since it would have lowered the SNR. Hence the new patch at the
end to clean up the stragglers.
Ville Syrjälä (14):
drm/i915: Introduce .{enable,disable}_clock() encoder vfuncs
drm/i915: Extract hsw_ddi_{enable,disable}_clock()
drm/i915: Extract skl_ddi_{enable,disable}_clock()
drm/i195: Extract cnl_ddi_{enable,disable}_clock()
drm/i915: Convert DG1 over to .{enable,disable}_clock()
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
drm/i915: Use intel_de_rmw() for DDI clock routing
drm/i915: Sprinkle a few missing locks around shared DDI clock
registers
drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()
drm/i915: Extract _cnl_ddi_{enable,disable}_clock()
drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable,disable}_clock()
drm/i915: Use .disable_clock() for pll sanitation
drm/i915: Relocate icl_sanitize_encoder_pll_mapping()
drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routing
drivers/gpu/drm/i915/display/icl_dsi.c| 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 576 ++
.../drm/i915/display/intel_display_types.h| 6 +
3 files changed, 315 insertions(+), 268 deletions(-)
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: cleanup the region class/instance encoding
== Series Details == Series: series starting with [1/2] drm/i915: cleanup the region class/instance encoding URL : https://patchwork.freedesktop.org/series/86694/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9730 -> Patchwork_19588 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19588 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19588, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19588/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19588: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_lrc: - fi-bsw-n3050: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19588/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html Known issues Here are the changes found in Patchwork_19588 that come from known issues: ### IGT changes ### Issues hit * igt@gem_close_race@basic-threads: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-tgl-y/igt@gem_close_r...@basic-threads.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19588/fi-tgl-y/igt@gem_close_r...@basic-threads.html * igt@kms_flip@basic-flip-vs-wf_vblank@a-vga1: - fi-pnv-d510:[PASS][5] -> [FAIL][6] ([i915#2122]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-pnv-d510/igt@kms_flip@basic-flip-vs-wf_vbl...@a-vga1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19588/fi-pnv-d510/igt@kms_flip@basic-flip-vs-wf_vbl...@a-vga1.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][7] ([i915#1982] / [i915#402]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-tgl-y/igt@debugfs_test@read_all_entries.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19588/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@gem_mmap_gtt@basic: - fi-tgl-y: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-tgl-y/igt@gem_mmap_...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19588/fi-tgl-y/igt@gem_mmap_...@basic.html * igt@i915_selftest@live@client: - fi-glk-dsi: [DMESG-FAIL][11] -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-glk-dsi/igt@i915_selftest@l...@client.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19588/fi-glk-dsi/igt@i915_selftest@l...@client.html * igt@i915_selftest@live@sanitycheck: - fi-kbl-7500u: [DMESG-WARN][13] ([i915#2605]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19588/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 38) -- Missing(5): fi-jsl-1 fi-ilk-m540 fi-byt-j1900 fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9730 -> Patchwork_19588 CI-20190529: 20190529 CI_DRM_9730: a70ac209cb308e06bc397cb3a6bf5764a4917333 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5990: e796ca7ce6fe9c54ee7d939be4110582d555fbb6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19588: 81f71fd67adc829e19b521a60be7fc7fcba1da87 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 81f71fd67adc drm/i915: give stolen system memory its own class 2a7b87cc63e4 drm/i915: cleanup the region class/instance encoding == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19588/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/display: Remove PSR2 on JSL and EHL
From: Edmund Dea
While JSL and EHL eDP transcoder supports PSR2, the phy of this
platforms only supports eDP 1.3, so removing PSR2 support as this
feature was added in eDP 1.4.
Signed-off-by: Edmund Dea
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 2c365b778f74..cccb8aff4336 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -718,6 +718,12 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
if (!dev_priv->psr.sink_psr2_support)
return false;
+ /* JSL and EHL only supports eDP 1.3 */
+ if (IS_JSL_EHL(dev_priv)) {
+ drm_dbg_kms(_priv->drm, "PSR2 not supported by phy\n");
+ return false;
+ }
+
if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
drm_dbg_kms(_priv->drm,
"PSR2 not supported in transcoder %s\n",
--
2.30.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/gtt/dg1: add PTE_LM plumbing for GGTT
Matthew Auld wrote on śro [2021-lut-03
18:32:34 +]:
> On Wed, 3 Feb 2021 at 18:01, Tang, CQ wrote:
> >
> >
> >
> > > -Original Message-
> > > From: Matthew Auld
> > > Sent: Wednesday, February 3, 2021 9:03 AM
> > > To: Tang, CQ
> > > Cc: Auld, Matthew ; intel-
> > > g...@lists.freedesktop.org; Chris Wilson
> > > Subject: Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/gtt/dg1: add PTE_LM
> > > plumbing for GGTT
> > >
> > > On Wed, 3 Feb 2021 at 16:51, Tang, CQ wrote:
> > > >
> > > >
> > > >
> > > > > -Original Message-
> > > > > From: Intel-gfx On Behalf
> > > > > Of Matthew Auld
> > > > > Sent: Wednesday, February 3, 2021 7:24 AM
> > > > > To: intel-gfx@lists.freedesktop.org
> > > > > Cc: Chris Wilson
> > > > > Subject: [Intel-gfx] [PATCH v3 3/3] drm/i915/gtt/dg1: add PTE_LM
> > > > > plumbing for GGTT
> > > > >
> > > > > For the PTEs we get an LM bit, to signal whether the page resides in
> > > > > SMEM or LMEM.
> > > > >
> > > > > Based on a patch from Michel Thierry.
> > > > >
> > > > > Signed-off-by: Matthew Auld
> > > > > Cc: Joonas Lahtinen
> > > > > Signed-off-by: Daniele Ceraolo Spurio
> > > > >
> > > > > Reviewed-by: Chris Wilson
> > > > > ---
> > > > > drivers/gpu/drm/i915/gt/intel_ggtt.c | 24 +++-
> > > > > drivers/gpu/drm/i915/gt/intel_gtt.h | 4 +++-
> > > > > 2 files changed, 22 insertions(+), 6 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > > > b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > > > index fc399ac16eda..b0b8ded834f0 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > > > @@ -10,6 +10,8 @@
> > > > >
> > > > > #include
> > > > >
> > > > > +#include "gem/i915_gem_lmem.h"
> > > > > +
> > > > > #include "intel_gt.h"
> > > > > #include "i915_drv.h"
> > > > > #include "i915_scatterlist.h"
> > > > > @@ -189,7 +191,12 @@ static u64 gen8_ggtt_pte_encode(dma_addr_t
> > > addr,
> > > > > enum i915_cache_level level,
> > > > > u32 flags) {
> > > > > - return addr | _PAGE_PRESENT;
> > > > > + gen8_pte_t pte = addr | _PAGE_PRESENT;
> > > > > +
> > > > > + if (flags & PTE_LM)
> > > > > + pte |= GEN12_GGTT_PTE_LM;
> > > > > +
> > > > > + return pte;
> > > > > }
> > > > >
> > > > > static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) @@
> > > > > -201,13
> > > > > +208,13 @@ static void gen8_ggtt_insert_page(struct
> > > > > +i915_address_space
> > > > > *vm,
> > > > > dma_addr_t addr,
> > > > > u64 offset,
> > > > > enum i915_cache_level level,
> > > > > - u32 unused)
> > > > > + u32 flags)
> > > > > {
> > > > > struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> > > > > gen8_pte_t __iomem *pte =
> > > > > (gen8_pte_t __iomem *)ggtt->gsm + offset /
> > > > > I915_GTT_PAGE_SIZE;
> > > > >
> > > > > - gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, 0));
> > > > > + gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));
> > > > >
> > > > > ggtt->invalidate(ggtt);
> > > > > }
> > > > > @@ -217,7 +224,7 @@ static void gen8_ggtt_insert_entries(struct
> > > > > i915_address_space *vm,
> > > > >enum i915_cache_level level,
> > > > >u32 flags) {
> > > > > - const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, 0);
> > > > > + const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level,
> > > > > flags);
> > > > > struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> > > > > gen8_pte_t __iomem *gte;
> > > > > gen8_pte_t __iomem *end;
> > > > > @@ -459,6 +466,8 @@ static void ggtt_bind_vma(struct
> > > > > i915_address_space *vm,
> > > > > pte_flags = 0;
> > > > > if (i915_gem_object_is_readonly(obj))
> > > > > pte_flags |= PTE_READ_ONLY;
> > > > > + if (i915_gem_object_is_lmem(obj))
> > > > > + pte_flags |= PTE_LM;
> > > > >
> > > > > vm->insert_entries(vm, vma, cache_level, pte_flags);
> > > > > vma->page_sizes.gtt = I915_GTT_PAGE_SIZE; @@ -794,6 +803,7 @@
> > > > > static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
> > > > > struct drm_i915_private *i915 = ggtt->vm.i915;
> > > > > struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > > > > phys_addr_t phys_addr;
> > > > > + u32 pte_flags;
> > > > > int ret;
> > > > >
> > > > > /* For Modern GENs the PTEs and register space are split in
> > > > > the BAR */ @@ -823,9 +833,13 @@ static int ggtt_probe_common(struct
> > > > > i915_ggtt *ggtt, u64 size)
> > > > > return ret;
> > > > > }
> > > > >
> > > > > + pte_flags = 0;
> > > > > + if
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: cleanup the region class/instance encoding
== Series Details ==
Series: series starting with [1/2] drm/i915: cleanup the region class/instance
encoding
URL : https://patchwork.freedesktop.org/series/86694/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2a7b87cc63e4 drm/i915: cleanup the region class/instance encoding
-:34: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#34: FILE: drivers/gpu/drm/i915/intel_memory_region.c:13:
+ [INTEL_REGION_SMEM] = {$
-:35: ERROR:CODE_INDENT: code indent should use tabs where possible
#35: FILE: drivers/gpu/drm/i915/intel_memory_region.c:14:
+ .class = INTEL_MEMORY_SYSTEM,$
-:35: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#35: FILE: drivers/gpu/drm/i915/intel_memory_region.c:14:
+ .class = INTEL_MEMORY_SYSTEM,$
-:36: ERROR:CODE_INDENT: code indent should use tabs where possible
#36: FILE: drivers/gpu/drm/i915/intel_memory_region.c:15:
+ .instance = 0,$
-:36: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#36: FILE: drivers/gpu/drm/i915/intel_memory_region.c:15:
+ .instance = 0,$
-:37: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#37: FILE: drivers/gpu/drm/i915/intel_memory_region.c:16:
+ },$
-:38: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#38: FILE: drivers/gpu/drm/i915/intel_memory_region.c:17:
+ [INTEL_REGION_LMEM] = {$
-:39: ERROR:CODE_INDENT: code indent should use tabs where possible
#39: FILE: drivers/gpu/drm/i915/intel_memory_region.c:18:
+ .class = INTEL_MEMORY_LOCAL,$
-:39: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#39: FILE: drivers/gpu/drm/i915/intel_memory_region.c:18:
+ .class = INTEL_MEMORY_LOCAL,$
-:40: ERROR:CODE_INDENT: code indent should use tabs where possible
#40: FILE: drivers/gpu/drm/i915/intel_memory_region.c:19:
+ .instance = 0,$
-:40: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#40: FILE: drivers/gpu/drm/i915/intel_memory_region.c:19:
+ .instance = 0,$
-:41: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#41: FILE: drivers/gpu/drm/i915/intel_memory_region.c:20:
+ },$
-:42: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#42: FILE: drivers/gpu/drm/i915/intel_memory_region.c:21:
+ [INTEL_REGION_STOLEN] = {$
-:43: ERROR:CODE_INDENT: code indent should use tabs where possible
#43: FILE: drivers/gpu/drm/i915/intel_memory_region.c:22:
+ .class = INTEL_MEMORY_STOLEN,$
-:43: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#43: FILE: drivers/gpu/drm/i915/intel_memory_region.c:22:
+ .class = INTEL_MEMORY_STOLEN,$
-:44: ERROR:CODE_INDENT: code indent should use tabs where possible
#44: FILE: drivers/gpu/drm/i915/intel_memory_region.c:23:
+ .instance = 0,$
-:44: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#44: FILE: drivers/gpu/drm/i915/intel_memory_region.c:23:
+ .instance = 0,$
-:45: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#45: FILE: drivers/gpu/drm/i915/intel_memory_region.c:24:
+ },$
total: 6 errors, 12 warnings, 0 checks, 79 lines checked
81f71fd67adc drm/i915: give stolen system memory its own class
-:71: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#71: FILE: drivers/gpu/drm/i915/intel_memory_region.c:21:
+ [INTEL_REGION_STOLEN_SMEM] = {$
-:72: ERROR:CODE_INDENT: code indent should use tabs where possible
#72: FILE: drivers/gpu/drm/i915/intel_memory_region.c:22:
+ .class = INTEL_MEMORY_STOLEN_SYSTEM,$
-:72: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#72: FILE: drivers/gpu/drm/i915/intel_memory_region.c:22:
+ .class = INTEL_MEMORY_STOLEN_SYSTEM,$
total: 1 errors, 2 warnings, 0 checks, 72 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [RFC,1/3] proc: Show GPU runtimes
== Series Details == Series: series starting with [RFC,1/3] proc: Show GPU runtimes URL : https://patchwork.freedesktop.org/series/86693/ State : success == Summary == CI Bug Log - changes from CI_DRM_9730 -> Patchwork_19587 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/index.html Known issues Here are the changes found in Patchwork_19587 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@sync-gfx0: - fi-bsw-n3050: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/fi-bsw-n3050/igt@amdgpu/amd_cs_...@sync-gfx0.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [PASS][2] -> [DMESG-WARN][3] ([i915#2868]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html * igt@prime_self_import@basic-with_one_bo_two_files: - fi-tgl-y: [PASS][4] -> [DMESG-WARN][5] ([i915#402]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html Possible fixes * igt@debugfs_test@read_all_entries: - fi-tgl-y: [DMESG-WARN][6] ([i915#1982] / [i915#402]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-tgl-y/igt@debugfs_test@read_all_entries.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/fi-tgl-y/igt@debugfs_test@read_all_entries.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-y: [DMESG-WARN][8] ([i915#2411] / [i915#402]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html * igt@gem_mmap_gtt@basic: - fi-tgl-y: [DMESG-WARN][10] ([i915#402]) -> [PASS][11] +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-tgl-y/igt@gem_mmap_...@basic.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/fi-tgl-y/igt@gem_mmap_...@basic.html * igt@i915_selftest@live@client: - fi-glk-dsi: [DMESG-FAIL][12] -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-glk-dsi/igt@i915_selftest@l...@client.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/fi-glk-dsi/igt@i915_selftest@l...@client.html * igt@i915_selftest@live@execlists: - fi-bsw-n3050: [INCOMPLETE][14] ([i915#2940]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@sanitycheck: - fi-kbl-7500u: [DMESG-WARN][16] ([i915#2605]) -> [PASS][17] +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/fi-kbl-7500u/igt@i915_selftest@l...@sanitycheck.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605 [i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (43 -> 39) -- Missing(4): fi-jsl-1 fi-ilk-m540 fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_9730 -> Patchwork_19587 CI-20190529: 20190529 CI_DRM_9730: a70ac209cb308e06bc397cb3a6bf5764a4917333 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5990: e796ca7ce6fe9c54ee7d939be4110582d555fbb6 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19587: 49cb9e5c8e5a0328b2c0921c52ce25eef351ff64 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 49cb9e5c8e5a drm/i915/gt: Export device and per-process runtimes via procfs b8f1256bd5ba drm/i915: Look up clients by pid 852e50fbb083 proc: Show GPU runtimes == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19587/index.html ___ Intel-gfx
Re: [Intel-gfx] linux-next: Tree for Feb 4 (gpu/drm/i915/)
On 2/4/21 1:13 AM, Stephen Rothwell wrote: > Hi all, > > Changes since 20210203: > on x86_64: Still seeing 2 unrelated issues: WARNING: unmet direct dependencies detected for DRM_I915_WERROR Depends on [n]: HAS_IOMEM [=y] && DRM_I915 [=m] && EXPERT [=y] && !COMPILE_TEST [=y] Selected by [m]: - DRM_I915_DEBUG [=y] && HAS_IOMEM [=y] && EXPERT [=y] && DRM_I915 [=m] ../drivers/gpu/drm/i915/i915_gem.c: In function ‘i915_gem_freeze_late’: ../drivers/gpu/drm/i915/i915_gem.c:1182:2: error: implicit declaration of function ‘wbinvd_on_all_cpus’; did you mean ‘wrmsr_on_cpus’? [-Werror=implicit-function-declaration] wbinvd_on_all_cpus(); Full randconfig file is attached. -- ~Randy Reported-by: Randy Dunlap config-r7644.gz Description: application/gzip ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] RFC: dma-buf: Require VM_SPECIAL vma for mmap
On Thu, Feb 4, 2021 at 5:13 PM Jason Gunthorpe wrote: > On Wed, Feb 03, 2021 at 10:19:48PM +0100, Daniel Vetter wrote: > > tldr; DMA buffers aren't normal memory, expecting that you can use > > them like that (like calling get_user_pages works, or that they're > > accounting like any other normal memory) cannot be guaranteed. > > > > Since some userspace only runs on integrated devices, where all > > buffers are actually all resident system memory, there's a huge > > temptation to assume that a struct page is always present and useable > > like for any more pagecache backed mmap. This has the potential to > > result in a uapi nightmare. > > > > To stop this gap require that DMA buffer mmaps are VM_SPECIAL, which > > blocks get_user_pages and all the other struct page based > > infrastructure for everyone. In spirit this is the uapi counterpart to > > the kernel-internal CONFIG_DMABUF_DEBUG. > > Fast gup needs the special flag set on the PTE as well.. Feels weird > to have a special VMA without also having special PTEs? There's kinda no convenient & cheap way to check for the pte_special flag. This here should at least catch accidental misuse, people building their own ptes we can't stop. Maybe we should exclude VM_MIXEDMAP to catch vm_insert_page in one of these. Hm looking at code I think we need to require VM_PFNMAP here to stop vm_insert_page. And looking at the various functions, that seems to be required (and I guess VM_IO is more for really funky architectures where io-space is somewhere else?). I guess I should check for VM_PFNMAP instead of VM_SPECIAL? -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/3] drm/i915/selftests: Restore previous heartbeat interval
== Series Details ==
Series: series starting with [v3,1/3] drm/i915/selftests: Restore previous
heartbeat interval
URL : https://patchwork.freedesktop.org/series/86690/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9730 -> Patchwork_19586
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19586 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19586, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19586/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19586:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gt_heartbeat:
- fi-pnv-d510:[PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-pnv-d510/igt@i915_selftest@live@gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19586/fi-pnv-d510/igt@i915_selftest@live@gt_heartbeat.html
- fi-elk-e7500: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-elk-e7500/igt@i915_selftest@live@gt_heartbeat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19586/fi-elk-e7500/igt@i915_selftest@live@gt_heartbeat.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@execlists:
- {fi-rkl-11500t}:[PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-rkl-11500t/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19586/fi-rkl-11500t/igt@i915_selftest@l...@execlists.html
- {fi-ehl-1}: [PASS][7] -> [INCOMPLETE][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-ehl-1/igt@i915_selftest@l...@execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19586/fi-ehl-1/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@gt_heartbeat:
- {fi-ehl-1}: [PASS][9] -> [DMESG-FAIL][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-ehl-1/igt@i915_selftest@live@gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19586/fi-ehl-1/igt@i915_selftest@live@gt_heartbeat.html
Known issues
Here are the changes found in Patchwork_19586 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@userptr:
- fi-byt-j1900: NOTRUN -> [SKIP][11] ([fdo#109271]) +17 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19586/fi-byt-j1900/igt@amdgpu/amd_ba...@userptr.html
* igt@i915_selftest@live@execlists:
- fi-kbl-r: [PASS][12] -> [INCOMPLETE][13] ([i915#1037] /
[i915#794])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-kbl-r/igt@i915_selftest@l...@execlists.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19586/fi-kbl-r/igt@i915_selftest@l...@execlists.html
- fi-cfl-8109u: [PASS][14] -> [INCOMPLETE][15] ([i915#1037])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19586/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
- fi-bsw-nick:[PASS][16] -> [INCOMPLETE][17] ([i915#2940])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19586/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
- fi-glk-dsi: [PASS][18] -> [INCOMPLETE][19] ([i915#1037])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-glk-dsi/igt@i915_selftest@l...@execlists.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19586/fi-glk-dsi/igt@i915_selftest@l...@execlists.html
- fi-kbl-x1275: [PASS][20] -> [INCOMPLETE][21] ([i915#1037] /
[i915#794])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-kbl-x1275/igt@i915_selftest@l...@execlists.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19586/fi-kbl-x1275/igt@i915_selftest@l...@execlists.html
- fi-icl-u2: [PASS][22] -> [INCOMPLETE][23] ([i915#1037] /
[i915#2276])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-icl-u2/igt@i915_selftest@l...@execlists.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19586/fi-icl-u2/igt@i915_selftest@l...@execlists.html
- fi-skl-6600u: [PASS][24] -> [INCOMPLETE][25] ([i915#1037])
[24]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [RFC,1/3] proc: Show GPU runtimes
== Series Details ==
Series: series starting with [RFC,1/3] proc: Show GPU runtimes
URL : https://patchwork.freedesktop.org/series/86693/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
852e50fbb083 proc: Show GPU runtimes
-:46: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IRUGO' are not preferred.
Consider using octal permissions '0444'.
#46: FILE: fs/proc/base.c:3269:
+ ONE("gpu", S_IRUGO, proc_pid_gpu),
-:54: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IRUGO' are not preferred.
Consider using octal permissions '0444'.
#54: FILE: fs/proc/base.c:3602:
+ ONE("gpu", S_IRUGO, proc_pid_gpu),
-:59: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#59:
new file mode 100644
total: 0 errors, 3 warnings, 0 checks, 149 lines checked
b8f1256bd5ba drm/i915: Look up clients by pid
49cb9e5c8e5a drm/i915/gt: Export device and per-process runtimes via procfs
-:56: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#56:
new file mode 100644
-:80: WARNING:CONSTANT_COMPARISON: Comparisons should place the constant on the
right side of the test
#80: FILE: drivers/gpu/drm/i915/gt/intel_gt_proc.c:20:
+ BUILD_BUG_ON(MAX_ENGINE_CLASS >= ARRAY_SIZE(rt->channel));
total: 0 errors, 2 warnings, 0 checks, 125 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915/selftests: Restore previous heartbeat interval
== Series Details == Series: series starting with [v2,1/2] drm/i915/selftests: Restore previous heartbeat interval URL : https://patchwork.freedesktop.org/series/86689/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9730 -> Patchwork_19585 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_19585 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19585, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19585/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19585: ### IGT changes ### Possible regressions * igt@gem_exec_parallel@engines@contexts: - fi-cfl-8109u: [PASS][1] -> [FAIL][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-cfl-8109u/igt@gem_exec_parallel@engi...@contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19585/fi-cfl-8109u/igt@gem_exec_parallel@engi...@contexts.html - fi-kbl-7500u: [PASS][3] -> [FAIL][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-kbl-7500u/igt@gem_exec_parallel@engi...@contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19585/fi-kbl-7500u/igt@gem_exec_parallel@engi...@contexts.html - fi-icl-u2: [PASS][5] -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-icl-u2/igt@gem_exec_parallel@engi...@contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19585/fi-icl-u2/igt@gem_exec_parallel@engi...@contexts.html - fi-bxt-dsi: [PASS][7] -> [FAIL][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-bxt-dsi/igt@gem_exec_parallel@engi...@contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19585/fi-bxt-dsi/igt@gem_exec_parallel@engi...@contexts.html - fi-skl-6600u: [PASS][9] -> [FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-skl-6600u/igt@gem_exec_parallel@engi...@contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19585/fi-skl-6600u/igt@gem_exec_parallel@engi...@contexts.html - fi-cfl-guc: [PASS][11] -> [FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-cfl-guc/igt@gem_exec_parallel@engi...@contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19585/fi-cfl-guc/igt@gem_exec_parallel@engi...@contexts.html - fi-glk-dsi: [PASS][13] -> [FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-glk-dsi/igt@gem_exec_parallel@engi...@contexts.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19585/fi-glk-dsi/igt@gem_exec_parallel@engi...@contexts.html - fi-kbl-x1275: [PASS][15] -> [FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-kbl-x1275/igt@gem_exec_parallel@engi...@contexts.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19585/fi-kbl-x1275/igt@gem_exec_parallel@engi...@contexts.html * igt@gem_exec_parallel@engines@fds: - fi-apl-guc: [PASS][17] -> [FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-apl-guc/igt@gem_exec_parallel@engi...@fds.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19585/fi-apl-guc/igt@gem_exec_parallel@engi...@fds.html * igt@gem_exec_parallel@engines@userptr: - fi-cfl-8109u: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-cfl-8109u/igt@gem_exec_parallel@engi...@userptr.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19585/fi-cfl-8109u/igt@gem_exec_parallel@engi...@userptr.html * igt@i915_selftest@live@gem_contexts: - fi-tgl-u2: [PASS][21] -> [DMESG-FAIL][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-tgl-u2/igt@i915_selftest@live@gem_contexts.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19585/fi-tgl-u2/igt@i915_selftest@live@gem_contexts.html - fi-skl-guc: [PASS][23] -> [DMESG-FAIL][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-skl-guc/igt@i915_selftest@live@gem_contexts.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19585/fi-skl-guc/igt@i915_selftest@live@gem_contexts.html - fi-kbl-guc: [PASS][25] -> [DMESG-FAIL][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9730/fi-kbl-guc/igt@i915_selftest@live@gem_contexts.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19585/fi-kbl-guc/igt@i915_selftest@live@gem_contexts.html - fi-kbl-x1275: [PASS][27] -> [DMESG-FAIL][28] [27]:
Re: [Intel-gfx] [PATCH V2] drm/i915/jsl: Disable cursor clock gating in HDR mode
> -Original Message-
> From: Intel-gfx On Behalf Of
> Surendrakumar Upadhyay, TejaskumarX
> Sent: 30 November 2020 21:21
> To: Souza, Jose ; intel-gfx@lists.freedesktop.org
> Cc: Pandey, Hariom
> Subject: Re: [Intel-gfx] [PATCH V2] drm/i915/jsl: Disable cursor clock gating
> in
> HDR mode
>
>
>
> > -Original Message-
> > From: Souza, Jose
> > Sent: 03 November 2020 05:32
> > To: Surendrakumar Upadhyay, TejaskumarX
> > ; intel-
> > g...@lists.freedesktop.org
> > Cc: Pandey, Hariom
> > Subject: Re: [PATCH V2] drm/i915/jsl: Disable cursor clock gating in
> > HDR mode
> >
> > On Mon, 2020-11-02 at 13:09 +0530, Tejas Upadhyay wrote:
> > > Display underrun in HDR mode when cursor is enabled.
> > > RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
> > > As per W/A 1604331009, Disable cursor clock gating in HDR mode.
> > >
> > > Bspec : 33451
> > >
> > > Changes since V1:
> > > - Modified way CLKGATE_DIS_PSL bit 28 was modified
> > >
> > > Cc: Souza Jose
> > > Signed-off-by: Tejas Upadhyay
> > >
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 28
>
> > > drivers/gpu/drm/i915/i915_reg.h | 5
> > > 2 files changed, 33 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index cddbda5303ff..b132585d9e78 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -541,6 +541,15 @@ icl_wa_scalerclkgating(struct drm_i915_private
> > *dev_priv, enum pipe pipe,
> > > intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) &
> > > ~DPFR_GATING_DIS); }
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > +/* Wa_1604331009:jsl */
> > > +static void
> > > +jsl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe
> > pipe,
> > > + bool enable)
> >
> > if this is a gen11 WA why naming as jsl? also include in the comment
> > icl and ehl.
> >
> > > +{
> > > +intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
> > > + CURSOR_GATING_DIS, enable ? CURSOR_GATING_DIS : 0); }
> > > +
> > > static bool
> > > needs_modeset(const struct intel_crtc_state *state) { @@ -6637,6
> > > +6646,16 @@ static bool needs_scalerclk_wa(const struct
> > > intel_crtc_state *crtc_state) return false; }
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > +static bool needs_cursorclk_wa(const struct intel_crtc_state
> > > +*crtc_state) { struct drm_i915_private *dev_priv =
> > > +to_i915(crtc_state->uapi.crtc->dev);
> >
> > line break here
> >
> > > +/* Wa_1604331009:jsl */
> > > +if (crtc_state->active_planes & icl_hdr_plane_mask() &&
> > > +IS_GEN(dev_priv, 11))
> > > +return true;
> >
> > line break here
> >
> > > +return false;
> > > +}
> > > +
> > > static bool planes_enabling(const struct intel_crtc_state
> > > *old_crtc_state,
> > > const struct intel_crtc_state *new_crtc_state) { @@ -6678,6
> > > +6697,10 @@ static void intel_post_plane_update(struct
> > > intel_atomic_state *state, if (needs_scalerclk_wa(old_crtc_state) &&
> > > !needs_scalerclk_wa(new_crtc_state))
> > > icl_wa_scalerclkgating(dev_priv, pipe, false);
> > > +
> > > +if (needs_cursorclk_wa(old_crtc_state) &&
> > > +!needs_cursorclk_wa(new_crtc_state))
> > > +jsl_wa_cursorclkgating(dev_priv, pipe, false);
> > > }
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > static void skl_disable_async_flip_wa(struct intel_atomic_state
> > > *state, @@ -6743,6 +6766,11 @@ static void
> > intel_pre_plane_update(struct intel_atomic_state *state,
> > > needs_scalerclk_wa(new_crtc_state))
> > > icl_wa_scalerclkgating(dev_priv, pipe, true);
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > +/* Wa_1604331009:jsl */
> > > +if (!needs_cursorclk_wa(old_crtc_state) &&
> > > +needs_cursorclk_wa(new_crtc_state))
> > > +jsl_wa_cursorclkgating(dev_priv, pipe, true);
> >
> > Like the idea of only enable the WA when a HDR plane is enabled but
> > there is some problems:
> > - never disable the wa
> > - not checking if a cursor plane is also active
> > - calling it in the post and pre
Re: [Intel-gfx] [PATCH 32/57] drm/i915: Move needs-breadcrumb flags to scheduler
Quoting Tvrtko Ursulin (2021-02-04 15:28:30)
>
> On 01/02/2021 08:56, Chris Wilson wrote:
> > Whether the scheduler depends on interrupt delivery for forward progress
> > is a property of the scheduler backend not of the underlying engine, so
> > move the flag from inside the engine to i915_sched_engine.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine.h| 6 ++
> > drivers/gpu/drm/i915/gt/intel_engine_types.h | 13 +++--
> > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> > drivers/gpu/drm/i915/i915_scheduler_types.h | 7 +++
> > 4 files changed, 17 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> > b/drivers/gpu/drm/i915/gt/intel_engine.h
> > index ca3a9cb06328..db5419ba1dc8 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> > @@ -285,4 +285,10 @@ intel_engine_has_timeslices(struct intel_engine_cs
> > *engine)
> > return i915_sched_has_timeslices(intel_engine_get_scheduler(engine));
> > }
> >
> > +static inline bool
> > +intel_engine_needs_breadcrumb_tasklet(struct intel_engine_cs *engine)
> > +{
> > + return
> > i915_sched_needs_breadcrumb_tasklet(intel_engine_get_scheduler(engine));
> > +}
> > +
> > #endif /* _INTEL_RINGBUFFER_H_ */
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > index 96a0aec29672..f856bd9b7dae 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > @@ -442,10 +442,9 @@ struct intel_engine_cs {
> > #define I915_ENGINE_SUPPORTS_STATS BIT(1)
> > #define I915_ENGINE_HAS_PREEMPTION BIT(2)
> > #define I915_ENGINE_HAS_SEMAPHORES BIT(3)
> > -#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
> > -#define I915_ENGINE_IS_VIRTUAL BIT(5)
> > -#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
> > -#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
> > +#define I915_ENGINE_IS_VIRTUAL BIT(4)
> > +#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(5)
> > +#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(6)
> > unsigned int flags;
> >
> > /*
> > @@ -540,12 +539,6 @@ intel_engine_has_semaphores(const struct
> > intel_engine_cs *engine)
> > return engine->flags & I915_ENGINE_HAS_SEMAPHORES;
> > }
> >
> > -static inline bool
> > -intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
> > -{
> > - return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
> > -}
> > -
> > static inline bool
> > intel_engine_is_virtual(const struct intel_engine_cs *engine)
> > {
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 887f38fb671f..e8c66d868c59 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -606,7 +606,6 @@ static void guc_default_vfuncs(struct intel_engine_cs
> > *engine)
> > }
> > engine->set_default_submission = guc_set_default_submission;
> >
> > - engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
> > engine->flags |= I915_ENGINE_HAS_PREEMPTION;
> >
> > /*
> > @@ -656,6 +655,7 @@ int intel_guc_submission_setup(struct intel_engine_cs
> > *engine)
> >
> > tasklet_setup(>sched.tasklet, guc_submission_tasklet);
> > __set_bit(I915_SCHED_ACTIVE_BIT, >sched.flags);
> > + __set_bit(I915_SCHED_NEEDS_BREADCRUMB_BIT, >sched.flags);
>
> Bah here my idea from earlier falls apart a bit. Don't know.
On the positive side, we've eliminated this patch by moving the
irq_handler to the engine!
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 30/57] drm/i915: Move timeslicing flag to scheduler
Quoting Tvrtko Ursulin (2021-02-04 15:18:31)
>
> On 01/02/2021 08:56, Chris Wilson wrote:
> > Whether a scheduler chooses to implement timeslicing is up to it, and
> > not an underlying property of the HW engine. The scheduler does depend
> > on the HW supporting preemption.
>
> Therefore, continuing on the comment I made in the previous patch, if we
> had a helper with which engine would request scheduling (setting the
> tasklet), if it passed in a pointer to itself, scheduler would then be
> able to inspect if the engine supports preemption and so set its own
> internal flag. Makes sense? It would require something like:
Actually not keen on pushing the inspection into the core scheduler and
would rather have the backend turn it on for itself. Because it's not
just about the engine supporting preemption, it's about whether or not
the backend wants to bother implement timeslicing itself.
If we skip to the end, it looks like this for execlists:
i915_sched_init(>sched, i915->drm.dev,
engine->name, engine->mask,
_ops, engine);
if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION) &&
intel_engine_has_preemption(engine))
__set_bit(I915_SCHED_TIMESLICE_BIT, >sched.flags);
if (intel_engine_has_preemption(engine)) {
__set_bit(I915_SCHED_BUSYWAIT_BIT, >sched.flags);
__set_bit(I915_SCHED_PREEMPT_RESET_BIT, >sched.flags);
}
with the virtual scheduler:
ve->base.sched =
i915_sched_create(ve->base.i915->drm.dev,
ve->base.name,
ve->base.mask,
_ops, ve);
if (!ve->base.sched) {
err = -ENOMEM;
goto err_put;
}
ve->base.sched->flags |= sched; /* override submission method */
I think the virtual scheduler suggests that we can't rely on the
scheduler core to dtrt by itself. And if you are still awake by the time
we get to this point, how to avoid ve->base.sched->flags |= sched are
welcome.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 29/57] drm/i915: Move scheduler flags
Quoting Tvrtko Ursulin (2021-02-04 15:14:20)
>
> On 01/02/2021 08:56, Chris Wilson wrote:
> > Start extracting the scheduling flags from the engine. We begin with its
> > own existence.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine.h| 6 ++
> > drivers/gpu/drm/i915/gt/intel_engine_types.h | 21 +++
> > .../drm/i915/gt/intel_execlists_submission.c | 6 +-
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> > drivers/gpu/drm/i915/i915_request.h | 2 +-
> > drivers/gpu/drm/i915/i915_scheduler.c | 2 +-
> > drivers/gpu/drm/i915/i915_scheduler_types.h | 10 +
> > 7 files changed, 31 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> > b/drivers/gpu/drm/i915/gt/intel_engine.h
> > index c530839627bb..4f0163457aed 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> > @@ -261,6 +261,12 @@ intel_engine_has_heartbeat(const struct
> > intel_engine_cs *engine)
> > return READ_ONCE(engine->props.heartbeat_interval_ms);
> > }
> >
> > +static inline bool
> > +intel_engine_has_scheduler(struct intel_engine_cs *engine)
> > +{
> > + return i915_sched_is_active(intel_engine_get_scheduler(engine));
> > +}
> > +
> > static inline void
> > intel_engine_kick_scheduler(struct intel_engine_cs *engine)
> > {
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > index 6b0bde292916..a3024a0de1de 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > @@ -440,14 +440,13 @@ struct intel_engine_cs {
> >
> > #define I915_ENGINE_USING_CMD_PARSER BIT(0)
> > #define I915_ENGINE_SUPPORTS_STATS BIT(1)
> > -#define I915_ENGINE_HAS_SCHEDULERBIT(2)
> > -#define I915_ENGINE_HAS_PREEMPTION BIT(3)
> > -#define I915_ENGINE_HAS_SEMAPHORES BIT(4)
> > -#define I915_ENGINE_HAS_TIMESLICES BIT(5)
> > -#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(6)
> > -#define I915_ENGINE_IS_VIRTUAL BIT(7)
> > -#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(8)
> > -#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(9)
> > +#define I915_ENGINE_HAS_PREEMPTION BIT(2)
> > +#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
> > +#define I915_ENGINE_HAS_TIMESLICES BIT(4)
> > +#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5)
> > +#define I915_ENGINE_IS_VIRTUAL BIT(6)
> > +#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7)
> > +#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8)
> > unsigned int flags;
> >
> > /*
> > @@ -530,12 +529,6 @@ intel_engine_supports_stats(const struct
> > intel_engine_cs *engine)
> > return engine->flags & I915_ENGINE_SUPPORTS_STATS;
> > }
> >
> > -static inline bool
> > -intel_engine_has_scheduler(const struct intel_engine_cs *engine)
> > -{
> > - return engine->flags & I915_ENGINE_HAS_SCHEDULER;
> > -}
> > -
> > static inline bool
> > intel_engine_has_preemption(const struct intel_engine_cs *engine)
> > {
> > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > index b1007e560527..3217cb4369ad 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > @@ -2913,7 +2913,6 @@ logical_ring_default_vfuncs(struct intel_engine_cs
> > *engine)
> >*/
> > }
> >
> > - engine->flags |= I915_ENGINE_HAS_SCHEDULER;
> > engine->flags |= I915_ENGINE_SUPPORTS_STATS;
> > if (!intel_vgpu_active(engine->i915)) {
> > engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
> > @@ -2981,6 +2980,7 @@ int intel_execlists_submission_setup(struct
> > intel_engine_cs *engine)
> > engine->sched.is_executing = execlists_is_executing;
> > engine->sched.show = execlists_show;
> > tasklet_setup(>sched.tasklet, execlists_submission_tasklet);
> > + __set_bit(I915_SCHED_ACTIVE_BIT, >sched.flags);
>
> This feels a bit dodgy - does is stay like this, with the engine setting
> up both the tasklet and setting the bit directly? Could we say that
> setting a tasklet via a helper could turn on the bit?
Bare with me for a few more patches. I didn't like it either. I guess I
should move that chunk earlier so we don't have the eyesore and rightful
questions over my sanity.
> > +static inline bool i915_sched_is_active(const struct i915_sched *se)
> > +{
> > + return test_bit(I915_SCHED_ACTIVE_BIT, >flags);
> > +}
>
> What do you have in mind for the distinction between "has scheduler" and
> "scheduler is active"?
By the end, we use the i915_scheduler for everything, including legacy
ringbuffer submission for which the i915_scheduler does nothing, as it
cannot support execution reordering.
So there's a scheduler behind every i915_request, but we
Re: [Intel-gfx] [PATCH] drm/vblank: Avoid storing a timestamp for the same frame twice
On Thu, Feb 04, 2021 at 04:32:16PM +0100, Daniel Vetter wrote: > On Thu, Feb 04, 2021 at 04:04:00AM +0200, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > drm_vblank_restore() exists because certain power saving states > > can clobber the hardware frame counter. The way it does this is > > by guesstimating how many frames were missed purely based on > > the difference between the last stored timestamp vs. a newly > > sampled timestamp. > > > > If we should call this function before a full frame has > > elapsed since we sampled the last timestamp we would end up > > with a possibly slightly different timestamp value for the > > same frame. Currently we will happily overwrite the already > > stored timestamp for the frame with the new value. This > > could cause userspace to observe two different timestamps > > for the same frame (and the timestamp could even go > > backwards depending on how much error we introduce when > > correcting the timestamp based on the scanout position). > > > > To avoid that let's not update the stored timestamp unless we're > > also incrementing the sequence counter. We do still want to update > > vblank->last with the freshly sampled hw frame counter value so > > that subsequent vblank irqs/queries can actually use the hw frame > > counter to determine how many frames have elapsed. > > Hm I'm not getting the reason for why we store the updated hw vblank > counter? Because next time a vblank irq happens the code will do: diff = current_hw_counter - vblank->last which won't work very well if vblank->last is garbage. Updating vblank->last is pretty much why drm_vblank_restore() exists at all. > There's definitely a race when we grab the hw timestamp at a bad time > (which can't happen for the irq handler, realistically), so maybe we > should first adjust that to make sure we never store anything inconsistent > in the vblank state? Not sure what race you mean, or what inconsistent thing we store? > > And when we have that we should be able to pull the inc == 0 check out > into _restore(), including comment. Which I think should be cleaner. > > Or I'm totally off with why you want to store the hw vblank counter? > > > > > Cc: Dhinakaran Pandiyan > > Cc: Rodrigo Vivi > > Cc: Daniel Vetter > > Signed-off-by: Ville Syrjälä > > --- > > drivers/gpu/drm/drm_vblank.c | 11 +++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c > > index 893165eeddf3..e127a7db2088 100644 > > --- a/drivers/gpu/drm/drm_vblank.c > > +++ b/drivers/gpu/drm/drm_vblank.c > > @@ -176,6 +176,17 @@ static void store_vblank(struct drm_device *dev, > > unsigned int pipe, > > > > vblank->last = last; > > > > + /* > > +* drm_vblank_restore() wants to always update > > +* vblank->last since we can't trust the frame counter > > +* across power saving states. But we don't want to alter > > +* the stored timestamp for the same frame number since > > +* that would cause userspace to potentially observe two > > +* different timestamps for the same frame. > > +*/ > > + if (vblank_count_inc == 0) > > + return; > > + > > write_seqlock(>seqlock); > > vblank->time = t_vblank; > > atomic64_add(vblank_count_inc, >count); > > -- > > 2.26.2 > > > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 34/57] drm/i915: Move preempt-reset flag to the scheduler
On 01/02/2021 08:56, Chris Wilson wrote:
While the HW may support preemption, whether or not the scheduler
enforces preemption by forcibly resetting the current context is
ultimately up to the scheduler.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h | 7 ++-
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 -
drivers/gpu/drm/i915/i915_scheduler_types.h | 9 +
3 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index db5419ba1dc8..33a29623571d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -244,12 +244,9 @@ static inline bool intel_engine_uses_guc(const struct
intel_engine_cs *engine)
}
static inline bool
-intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
+intel_engine_has_preempt_reset(struct intel_engine_cs *engine)
{
- if (!IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT))
- return false;
-
- return intel_engine_has_preemption(engine);
+ return i915_sched_has_preempt_reset(intel_engine_get_scheduler(engine));
}
static inline bool
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 9245499d2082..7ec33bd73d95 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2931,9 +2931,12 @@ logical_ring_default_vfuncs(struct intel_engine_cs
*engine)
__set_bit(I915_SCHED_HAS_TIMESLICES_BIT,
>sched.flags);
- if (intel_engine_has_preemption(engine))
+ if (intel_engine_has_preemption(engine)) {
__set_bit(I915_SCHED_USE_BUSYWAIT_BIT,
>sched.flags);
+ __set_bit(I915_SCHED_HAS_PREEMPT_RESET_BIT,
+ >sched.flags);
+ }
}
static void logical_ring_default_irqs(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h
b/drivers/gpu/drm/i915/i915_scheduler_types.h
index 37475024c0de..7271a0259a56 100644
--- a/drivers/gpu/drm/i915/i915_scheduler_types.h
+++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
@@ -20,6 +20,7 @@ struct i915_request;
enum {
I915_SCHED_ACTIVE_BIT = 0,
I915_SCHED_HAS_TIMESLICES_BIT,
+ I915_SCHED_HAS_PREEMPT_RESET_BIT,
I915_SCHED_NEEDS_BREADCRUMB_BIT,
I915_SCHED_USE_BUSYWAIT_BIT,
};
@@ -207,4 +208,12 @@ static inline bool i915_sched_use_busywait(const struct
i915_sched *se)
return test_bit(I915_SCHED_USE_BUSYWAIT_BIT, >flags);
}
+static inline bool i915_sched_has_preempt_reset(const struct i915_sched *se)
+{
+ if (!IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT))
+ return false;
+
+ return test_bit(I915_SCHED_HAS_PREEMPT_RESET_BIT, >flags);
+}
+
#endif /* _I915_SCHEDULER_TYPES_H_ */
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 33/57] drm/i915: Move busywaiting control to the scheduler
On 01/02/2021 08:56, Chris Wilson wrote:
Busy-waiting is used for preempt-to-busy by schedulers, if they so
choose. Since it is not a property of the engine, but that of the
submission backend, move the flag from out of the engine to
i915_sched_engine.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 4 ++--
.../drm/i915/gt/intel_execlists_submission.c | 6 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c| 19 +--
drivers/gpu/drm/i915/i915_request.h | 5 +
drivers/gpu/drm/i915/i915_scheduler_types.h | 6 ++
5 files changed, 31 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index cac80af7ad1c..8791e03ebe61 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -507,7 +507,7 @@ gen8_emit_fini_breadcrumb_tail(struct i915_request *rq, u32
*cs)
*cs++ = MI_USER_INTERRUPT;
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
- if (intel_engine_has_semaphores(rq->engine))
+ if (i915_request_use_busywait(rq))
cs = emit_preempt_busywait(rq, cs);
rq->tail = intel_ring_offset(rq, cs);
@@ -599,7 +599,7 @@ gen12_emit_fini_breadcrumb_tail(struct i915_request *rq,
u32 *cs)
*cs++ = MI_USER_INTERRUPT;
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
- if (intel_engine_has_semaphores(rq->engine))
+ if (i915_request_use_busywait(rq))
cs = gen12_emit_preempt_busywait(rq, cs);
rq->tail = intel_ring_offset(rq, cs);
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index d4b6d262265a..9245499d2082 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -304,7 +304,7 @@ static bool need_preempt(const struct intel_engine_cs
*engine,
const struct i915_sched *se = >sched;
int last_prio;
- if (!intel_engine_has_semaphores(engine))
+ if (!i915_sched_use_busywait(se))
return false;
/*
@@ -2930,6 +2930,10 @@ logical_ring_default_vfuncs(struct intel_engine_cs
*engine)
intel_engine_has_preemption(engine))
__set_bit(I915_SCHED_HAS_TIMESLICES_BIT,
>sched.flags);
+
+ if (intel_engine_has_preemption(engine))
+ __set_bit(I915_SCHED_USE_BUSYWAIT_BIT,
+ >sched.flags);
I checked GuC is not using this which was my initial concern.
}
static void logical_ring_default_irqs(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 279091e41b41..6d73add47109 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -679,9 +679,11 @@ static int live_lrc_gpr(void *arg)
if (err)
goto err;
- err = __live_lrc_gpr(engine, scratch, true);
- if (err)
- goto err;
+ if (intel_engine_has_preemption(engine)) {
+ err = __live_lrc_gpr(engine, scratch, true);
+ if (err)
+ goto err;
+ }
err:
st_engine_heartbeat_enable(engine);
@@ -859,9 +861,11 @@ static int live_lrc_timestamp(void *arg)
if (err)
break;
- err = __lrc_timestamp(, true);
- if (err)
- break;
+ if (intel_engine_has_preemption(data.engine)) {
+ err = __lrc_timestamp(, true);
+ if (err)
+ break;
+ }
}
err:
@@ -1508,6 +1512,9 @@ static int live_lrc_isolation(void *arg)
skip_isolation(engine))
continue;
+ if (!intel_engine_has_preemption(engine))
+ continue;
+
intel_engine_pm_get(engine);
for (i = 0; i < ARRAY_SIZE(poison); i++) {
int result;
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index 8eea25cb043e..7c29d33e7d51 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -642,4 +642,9 @@ static inline bool i915_request_use_semaphores(const struct
i915_request *rq)
return intel_engine_has_semaphores(rq->engine);
}
+static inline bool i915_request_use_busywait(const struct i915_request *rq)
+{
+ return i915_sched_use_busywait(i915_request_get_scheduler(rq));
+}
+
#endif /* I915_REQUEST_H */
diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h
b/drivers/gpu/drm/i915/i915_scheduler_types.h
index
[Intel-gfx] [PATCH] drm/i915: Make psr_safest_params and enable_psr2_sel_fetch parameters read only
By mistake those 2 parameters were defined as read and write in the .h file while in the .c file it is read only. The intention here was to be read only to avoid the need of additional handling. Cc: Gwan-gyeong Mun Cc: Petri Latvala Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_params.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index f031966af5b7..48f47e44e848 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -54,8 +54,8 @@ struct drm_printer; param(int, enable_dc, -1, 0400) \ param(int, enable_fbc, -1, 0600) \ param(int, enable_psr, -1, 0600) \ - param(bool, psr_safest_params, false, 0600) \ - param(bool, enable_psr2_sel_fetch, false, 0600) \ + param(bool, psr_safest_params, false, 0400) \ + param(bool, enable_psr2_sel_fetch, false, 0400) \ param(int, disable_power_well, -1, 0400) \ param(int, enable_ips, 1, 0600) \ param(int, invert_brightness, 0, 0600) \ -- 2.30.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/vblank: Avoid storing a timestamp for the same frame twice
On Thu, Feb 04, 2021 at 04:04:00AM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > drm_vblank_restore() exists because certain power saving states > can clobber the hardware frame counter. The way it does this is > by guesstimating how many frames were missed purely based on > the difference between the last stored timestamp vs. a newly > sampled timestamp. > > If we should call this function before a full frame has > elapsed since we sampled the last timestamp we would end up > with a possibly slightly different timestamp value for the > same frame. Currently we will happily overwrite the already > stored timestamp for the frame with the new value. This > could cause userspace to observe two different timestamps > for the same frame (and the timestamp could even go > backwards depending on how much error we introduce when > correcting the timestamp based on the scanout position). > > To avoid that let's not update the stored timestamp unless we're > also incrementing the sequence counter. We do still want to update > vblank->last with the freshly sampled hw frame counter value so > that subsequent vblank irqs/queries can actually use the hw frame > counter to determine how many frames have elapsed. Hm I'm not getting the reason for why we store the updated hw vblank counter? There's definitely a race when we grab the hw timestamp at a bad time (which can't happen for the irq handler, realistically), so maybe we should first adjust that to make sure we never store anything inconsistent in the vblank state? And when we have that we should be able to pull the inc == 0 check out into _restore(), including comment. Which I think should be cleaner. Or I'm totally off with why you want to store the hw vblank counter? > > Cc: Dhinakaran Pandiyan > Cc: Rodrigo Vivi > Cc: Daniel Vetter > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/drm_vblank.c | 11 +++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c > index 893165eeddf3..e127a7db2088 100644 > --- a/drivers/gpu/drm/drm_vblank.c > +++ b/drivers/gpu/drm/drm_vblank.c > @@ -176,6 +176,17 @@ static void store_vblank(struct drm_device *dev, > unsigned int pipe, > > vblank->last = last; > > + /* > + * drm_vblank_restore() wants to always update > + * vblank->last since we can't trust the frame counter > + * across power saving states. But we don't want to alter > + * the stored timestamp for the same frame number since > + * that would cause userspace to potentially observe two > + * different timestamps for the same frame. > + */ > + if (vblank_count_inc == 0) > + return; > + > write_seqlock(>seqlock); > vblank->time = t_vblank; > atomic64_add(vblank_count_inc, >count); > -- > 2.26.2 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 32/57] drm/i915: Move needs-breadcrumb flags to scheduler
On 01/02/2021 08:56, Chris Wilson wrote:
Whether the scheduler depends on interrupt delivery for forward progress
is a property of the scheduler backend not of the underlying engine, so
move the flag from inside the engine to i915_sched_engine.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h| 6 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 13 +++--
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/i915_scheduler_types.h | 7 +++
4 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index ca3a9cb06328..db5419ba1dc8 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -285,4 +285,10 @@ intel_engine_has_timeslices(struct intel_engine_cs *engine)
return i915_sched_has_timeslices(intel_engine_get_scheduler(engine));
}
+static inline bool
+intel_engine_needs_breadcrumb_tasklet(struct intel_engine_cs *engine)
+{
+ return
i915_sched_needs_breadcrumb_tasklet(intel_engine_get_scheduler(engine));
+}
+
#endif /* _INTEL_RINGBUFFER_H_ */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 96a0aec29672..f856bd9b7dae 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -442,10 +442,9 @@ struct intel_engine_cs {
#define I915_ENGINE_SUPPORTS_STATS BIT(1)
#define I915_ENGINE_HAS_PREEMPTION BIT(2)
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
-#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
-#define I915_ENGINE_IS_VIRTUAL BIT(5)
-#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
-#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
+#define I915_ENGINE_IS_VIRTUAL BIT(4)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(5)
+#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(6)
unsigned int flags;
/*
@@ -540,12 +539,6 @@ intel_engine_has_semaphores(const struct intel_engine_cs
*engine)
return engine->flags & I915_ENGINE_HAS_SEMAPHORES;
}
-static inline bool
-intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
-{
- return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
-}
-
static inline bool
intel_engine_is_virtual(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 887f38fb671f..e8c66d868c59 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -606,7 +606,6 @@ static void guc_default_vfuncs(struct intel_engine_cs
*engine)
}
engine->set_default_submission = guc_set_default_submission;
- engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
/*
@@ -656,6 +655,7 @@ int intel_guc_submission_setup(struct intel_engine_cs
*engine)
tasklet_setup(>sched.tasklet, guc_submission_tasklet);
__set_bit(I915_SCHED_ACTIVE_BIT, >sched.flags);
+ __set_bit(I915_SCHED_NEEDS_BREADCRUMB_BIT, >sched.flags);
Bah here my idea from earlier falls apart a bit. Don't know.
guc_default_vfuncs(engine);
guc_default_irqs(engine);
diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h
b/drivers/gpu/drm/i915/i915_scheduler_types.h
index dfb29b8c2bee..b4a0e4e26bfd 100644
--- a/drivers/gpu/drm/i915/i915_scheduler_types.h
+++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
@@ -20,6 +20,7 @@ struct i915_request;
enum {
I915_SCHED_ACTIVE_BIT = 0,
I915_SCHED_HAS_TIMESLICES_BIT,
+ I915_SCHED_NEEDS_BREADCRUMB_BIT,
};
/**
@@ -194,4 +195,10 @@ static inline bool i915_sched_has_timeslices(const struct
i915_sched *se)
return test_bit(I915_SCHED_HAS_TIMESLICES_BIT, >flags);
}
+static inline bool
+i915_sched_needs_breadcrumb_tasklet(const struct i915_sched *se)
+{
+ return test_bit(I915_SCHED_NEEDS_BREADCRUMB_BIT, >flags);
+}
+
#endif /* _I915_SCHEDULER_TYPES_H_ */
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 31/57] drm/i915/gt: Declare when we enabled timeslicing
On 01/02/2021 08:56, Chris Wilson wrote:
Let userspace know if they can trust timeslicing by including it as part
of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
v2: Only declare timeslicing if we can safely preempt userspace.
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 26 +++--
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 64eccdf32a22..50911fbe6368 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -90,13 +90,17 @@ static void sort_engines(struct drm_i915_private *i915,
static void set_scheduler_caps(struct drm_i915_private *i915)
{
static const struct {
- u8 engine;
- u8 sched;
- } map[] = {
+ u8 flag;
+ u8 cap;
+ } engine_map[] = {
#define MAP(x, y) { ilog2(I915_ENGINE_##x), ilog2(I915_SCHEDULER_CAP_##y) }
MAP(HAS_PREEMPTION, PREEMPTION),
MAP(HAS_SEMAPHORES, SEMAPHORES),
MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS),
+#undef MAP
+ }, sched_map[] = {
+#define MAP(x, y) { ilog2(I915_SCHED_##x), ilog2(I915_SCHEDULER_CAP_##y) }
+ MAP(HAS_TIMESLICES_BIT, TIMESLICING),
#undef MAP
};
struct intel_engine_cs *engine;
@@ -105,6 +109,7 @@ static void set_scheduler_caps(struct drm_i915_private
*i915)
enabled = 0;
disabled = 0;
for_each_uabi_engine(engine, i915) { /* all engines must agree! */
+ struct i915_sched *se = intel_engine_get_scheduler(engine);
int i;
if (intel_engine_has_scheduler(engine))
@@ -114,11 +119,18 @@ static void set_scheduler_caps(struct drm_i915_private
*i915)
disabled |= (I915_SCHEDULER_CAP_ENABLED |
I915_SCHEDULER_CAP_PRIORITY);
- for (i = 0; i < ARRAY_SIZE(map); i++) {
- if (engine->flags & BIT(map[i].engine))
- enabled |= BIT(map[i].sched);
+ for (i = 0; i < ARRAY_SIZE(engine_map); i++) {
+ if (engine->flags & BIT(engine_map[i].flag))
+ enabled |= BIT(engine_map[i].cap);
else
- disabled |= BIT(map[i].sched);
+ disabled |= BIT(engine_map[i].cap);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sched_map); i++) {
+ if (se->flags & BIT(sched_map[i].flag))
+ enabled |= BIT(sched_map[i].cap);
+ else
+ disabled |= BIT(sched_map[i].cap);
}
}
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 1987e2ea79a3..cda0f391d965 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -524,6 +524,7 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS(1ul << 4)
+#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5)
#define I915_PARAM_HUC_STATUS 42
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 30/57] drm/i915: Move timeslicing flag to scheduler
On 01/02/2021 08:56, Chris Wilson wrote:
Whether a scheduler chooses to implement timeslicing is up to it, and
not an underlying property of the HW engine. The scheduler does depend
on the HW supporting preemption.
Therefore, continuing on the comment I made in the previous patch, if we
had a helper with which engine would request scheduling (setting the
tasklet), if it passed in a pointer to itself, scheduler would then be
able to inspect if the engine supports preemption and so set its own
internal flag. Makes sense? It would require something like:
i915_sched_enable_scheduling(se, engine, tasklet)
Or something like that if my memory still holds.
Regards,
Tvrtko
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h | 6 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 18 --
.../drm/i915/gt/intel_execlists_submission.c | 9 ++---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 2 +-
drivers/gpu/drm/i915/i915_scheduler_types.h| 10 ++
5 files changed, 27 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 4f0163457aed..ca3a9cb06328 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -279,4 +279,10 @@ intel_engine_flush_scheduler(struct intel_engine_cs
*engine)
i915_sched_flush(intel_engine_get_scheduler(engine));
}
+static inline bool
+intel_engine_has_timeslices(struct intel_engine_cs *engine)
+{
+ return i915_sched_has_timeslices(intel_engine_get_scheduler(engine));
+}
+
#endif /* _INTEL_RINGBUFFER_H_ */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index a3024a0de1de..96a0aec29672 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -442,11 +442,10 @@ struct intel_engine_cs {
#define I915_ENGINE_SUPPORTS_STATS BIT(1)
#define I915_ENGINE_HAS_PREEMPTION BIT(2)
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
-#define I915_ENGINE_HAS_TIMESLICES BIT(4)
-#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5)
-#define I915_ENGINE_IS_VIRTUAL BIT(6)
-#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7)
-#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8)
+#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
+#define I915_ENGINE_IS_VIRTUAL BIT(5)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
+#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
unsigned int flags;
/*
@@ -541,15 +540,6 @@ intel_engine_has_semaphores(const struct intel_engine_cs
*engine)
return engine->flags & I915_ENGINE_HAS_SEMAPHORES;
}
-static inline bool
-intel_engine_has_timeslices(const struct intel_engine_cs *engine)
-{
- if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
- return false;
-
- return engine->flags & I915_ENGINE_HAS_TIMESLICES;
-}
-
static inline bool
intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 3217cb4369ad..d4b6d262265a 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1023,7 +1023,7 @@ static bool needs_timeslice(const struct intel_engine_cs
*engine,
{
const struct i915_sched *se = >sched;
- if (!intel_engine_has_timeslices(engine))
+ if (!i915_sched_has_timeslices(se))
return false;
/* If not currently active, or about to switch, wait for next event */
@@ -2918,8 +2918,6 @@ logical_ring_default_vfuncs(struct intel_engine_cs
*engine)
engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
if (can_preempt(engine)) {
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
- if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
- engine->flags |= I915_ENGINE_HAS_TIMESLICES;
}
}
@@ -2927,6 +2925,11 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
engine->emit_bb_start = gen8_emit_bb_start;
else
engine->emit_bb_start = gen8_emit_bb_start_noarb;
+
+ if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION) &&
+ intel_engine_has_preemption(engine))
+ __set_bit(I915_SCHED_HAS_TIMESLICES_BIT,
+ >sched.flags);
}
static void logical_ring_default_irqs(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index cfc0f4b9fbc5..147cbfd6dec0 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -3825,7 +3825,7 @@ static unsigned int
__select_siblings(struct intel_gt *gt,
Re: [Intel-gfx] [PATCH 29/57] drm/i915: Move scheduler flags
On 01/02/2021 08:56, Chris Wilson wrote:
Start extracting the scheduling flags from the engine. We begin with its
own existence.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine.h| 6 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 21 +++
.../drm/i915/gt/intel_execlists_submission.c | 6 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/i915_request.h | 2 +-
drivers/gpu/drm/i915/i915_scheduler.c | 2 +-
drivers/gpu/drm/i915/i915_scheduler_types.h | 10 +
7 files changed, 31 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index c530839627bb..4f0163457aed 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -261,6 +261,12 @@ intel_engine_has_heartbeat(const struct intel_engine_cs
*engine)
return READ_ONCE(engine->props.heartbeat_interval_ms);
}
+static inline bool
+intel_engine_has_scheduler(struct intel_engine_cs *engine)
+{
+ return i915_sched_is_active(intel_engine_get_scheduler(engine));
+}
+
static inline void
intel_engine_kick_scheduler(struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 6b0bde292916..a3024a0de1de 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -440,14 +440,13 @@ struct intel_engine_cs {
#define I915_ENGINE_USING_CMD_PARSER BIT(0)
#define I915_ENGINE_SUPPORTS_STATS BIT(1)
-#define I915_ENGINE_HAS_SCHEDULERBIT(2)
-#define I915_ENGINE_HAS_PREEMPTION BIT(3)
-#define I915_ENGINE_HAS_SEMAPHORES BIT(4)
-#define I915_ENGINE_HAS_TIMESLICES BIT(5)
-#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(6)
-#define I915_ENGINE_IS_VIRTUAL BIT(7)
-#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(8)
-#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(9)
+#define I915_ENGINE_HAS_PREEMPTION BIT(2)
+#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
+#define I915_ENGINE_HAS_TIMESLICES BIT(4)
+#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5)
+#define I915_ENGINE_IS_VIRTUAL BIT(6)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7)
+#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8)
unsigned int flags;
/*
@@ -530,12 +529,6 @@ intel_engine_supports_stats(const struct intel_engine_cs
*engine)
return engine->flags & I915_ENGINE_SUPPORTS_STATS;
}
-static inline bool
-intel_engine_has_scheduler(const struct intel_engine_cs *engine)
-{
- return engine->flags & I915_ENGINE_HAS_SCHEDULER;
-}
-
static inline bool
intel_engine_has_preemption(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index b1007e560527..3217cb4369ad 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2913,7 +2913,6 @@ logical_ring_default_vfuncs(struct intel_engine_cs
*engine)
*/
}
- engine->flags |= I915_ENGINE_HAS_SCHEDULER;
engine->flags |= I915_ENGINE_SUPPORTS_STATS;
if (!intel_vgpu_active(engine->i915)) {
engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
@@ -2981,6 +2980,7 @@ int intel_execlists_submission_setup(struct
intel_engine_cs *engine)
engine->sched.is_executing = execlists_is_executing;
engine->sched.show = execlists_show;
tasklet_setup(>sched.tasklet, execlists_submission_tasklet);
+ __set_bit(I915_SCHED_ACTIVE_BIT, >sched.flags);
This feels a bit dodgy - does is stay like this, with the engine setting
up both the tasklet and setting the bit directly? Could we say that
setting a tasklet via a helper could turn on the bit?
timer_setup(>execlists.timer, execlists_timeslice, 0);
timer_setup(>execlists.preempt, execlists_preempt, 0);
@@ -3386,6 +3386,7 @@ intel_execlists_create_virtual(struct intel_engine_cs **siblings,
unsigned int count)
{
struct virtual_engine *ve;
+ unsigned long sched;
unsigned int n;
int err;
@@ -3444,6 +3445,7 @@ intel_execlists_create_virtual(struct intel_engine_cs **siblings,
goto err_put;
}
+ sched = ~0U;
for (n = 0; n < count; n++) {
struct intel_engine_cs *sibling = siblings[n];
@@ -3473,6 +3475,7 @@ intel_execlists_create_virtual(struct intel_engine_cs **siblings,
ve->siblings[ve->num_siblings++] = sibling;
ve->base.mask |= sibling->mask;
+ sched &= sibling->sched.flags;
/*
* All physical engines must be compatible for their emission
@@ -3514,6 +3517,7 @@ intel_execlists_create_virtual(struct intel_engine_cs
**siblings,
Re: [Intel-gfx] [PATCH 28/57] drm/i915: Wrap i915_request_use_semaphores()
On 01/02/2021 08:56, Chris Wilson wrote:
Wrap the query on whether the backend engine supports us emitting
semaphores to coordinate multiple requests.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 2 +-
drivers/gpu/drm/i915/i915_request.h | 5 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 459f727b03cd..e7b4c4bc41a6 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1141,7 +1141,7 @@ __i915_request_await_execution(struct i915_request *to,
* immediate execution, and so we must wait until it reaches the
* active slot.
*/
- if (intel_engine_has_semaphores(to->engine) &&
+ if (i915_request_use_semaphores(to) &&
!i915_request_has_initial_breadcrumb(to)) {
err = __emit_semaphore_wait(to, from, from->fence.seqno - 1);
if (err < 0)
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index 8322f308b906..8d9e59e3cdcb 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -637,4 +637,9 @@ static inline bool i915_request_is_executing(const struct
i915_request *rq)
return i915_request_get_scheduler(rq)->is_executing(rq);
}
+static inline bool i915_request_use_semaphores(const struct i915_request *rq)
+{
+ return intel_engine_has_semaphores(rq->engine);
+}
+
#endif /* I915_REQUEST_H */
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
