[Intel-gfx] ✓ Fi.CI.IGT: success for HDMI2.1 PCON Misc Fixes (rev3)
== Series Details == Series: HDMI2.1 PCON Misc Fixes (rev3) URL : https://patchwork.freedesktop.org/series/86677/ State : success == Summary == CI Bug Log - changes from CI_DRM_9841_full -> Patchwork_19769_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_19769_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19769_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19769_full: ### IGT changes ### Warnings * igt@runner@aborted: - shard-kbl: ([FAIL][1], [FAIL][2], [FAIL][3], [FAIL][4], [FAIL][5], [FAIL][6], [FAIL][7], [FAIL][8], [FAIL][9], [FAIL][10]) ([i915#180] / [i915#1814] / [i915#2292] / [i915#2426] / [i915#2505] / [i915#2724] / [i915#3002] / [i915#602]) -> ([FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], [FAIL][21]) ([i915#180] / [i915#1814] / [i915#2426] / [i915#2505] / [i915#2724] / [i915#3002] / [i915#602]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/shard-kbl2/igt@run...@aborted.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/shard-kbl3/igt@run...@aborted.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/shard-kbl3/igt@run...@aborted.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/shard-kbl6/igt@run...@aborted.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/shard-kbl6/igt@run...@aborted.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/shard-kbl6/igt@run...@aborted.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/shard-kbl6/igt@run...@aborted.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/shard-kbl7/igt@run...@aborted.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/shard-kbl7/igt@run...@aborted.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/shard-kbl1/igt@run...@aborted.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/shard-kbl7/igt@run...@aborted.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/shard-kbl7/igt@run...@aborted.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/shard-kbl6/igt@run...@aborted.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/shard-kbl7/igt@run...@aborted.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/shard-kbl7/igt@run...@aborted.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/shard-kbl7/igt@run...@aborted.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/shard-kbl1/igt@run...@aborted.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/shard-kbl3/igt@run...@aborted.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/shard-kbl6/igt@run...@aborted.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/shard-kbl2/igt@run...@aborted.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/shard-kbl6/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_19769_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@display-3x: - shard-glk: NOTRUN -> [SKIP][22] ([fdo#109271]) +8 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/shard-glk6/igt@feature_discov...@display-3x.html * igt@gem_ctx_persistence@engines-mixed: - shard-snb: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#1099]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/shard-snb7/igt@gem_ctx_persiste...@engines-mixed.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][24] -> [TIMEOUT][25] ([i915#2369] / [i915#3063]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/shard-tglb8/igt@gem_...@unwedge-stress.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/shard-tglb7/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][26] -> [FAIL][27] ([i915#2842]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/shard-iclb1/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-apl: [PASS][28] -> [FAIL][29] ([i915#2842]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/shard-apl7/igt@gem_exec_fair@basic-n...@vcs0.html [29]: https://intel-gfx-ci.01.org/
[Intel-gfx] ✓ Fi.CI.BAT: success for HDMI2.1 PCON Misc Fixes (rev3)
== Series Details ==
Series: HDMI2.1 PCON Misc Fixes (rev3)
URL : https://patchwork.freedesktop.org/series/86677/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9841 -> Patchwork_19769
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/index.html
Known issues
Here are the changes found in Patchwork_19769 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_gttfill@basic:
- fi-kbl-8809g: [PASS][1] -> [TIMEOUT][2] ([i915#3145])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-soraka: [PASS][3] -> [INCOMPLETE][4] ([i915#155])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][5] ([i915#1602] / [i915#2029] /
[i915#2369])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/fi-bdw-5557u/igt@run...@aborted.html
Possible fixes
* igt@kms_frontbuffer_tracking@basic:
- {fi-rkl-11500t}:[SKIP][6] -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/fi-rkl-11500t/igt@kms_frontbuffer_track...@basic.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/fi-rkl-11500t/igt@kms_frontbuffer_track...@basic.html
Warnings
* igt@i915_pm_rpm@module-reload:
- fi-glk-dsi: [DMESG-WARN][8] ([i915#1982] / [i915#3143]) ->
[DMESG-WARN][9] ([i915#3143])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9841/fi-glk-dsi/igt@i915_pm_...@module-reload.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/fi-glk-dsi/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#3143]: https://gitlab.freedesktop.org/drm/intel/issues/3143
[i915#3145]: https://gitlab.freedesktop.org/drm/intel/issues/3145
Participating hosts (45 -> 41)
--
Additional (1): fi-bdw-5557u
Missing(5): fi-ilk-m540 fi-tgl-dsi fi-hsw-4200u fi-bsw-cyan fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9841 -> Patchwork_19769
CI-20190529: 20190529
CI_DRM_9841: 443e92e6d6c39f7a3e658d98eec6422b0d6547ba @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6026: 8b8bbecf2f32298544c2f193753a0153f39e7326 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19769: 8237da36a99af388964ee2556f872dcd6bba5d46 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8237da36a99a drm/i915/display: Configure HDMI2.1 Pcon for FRL only if Src-Ctl
mode is available
1cc3b98548db drm/i915/display: Remove FRL related code from disable DP sequence
for older platforms
3814cc7c4593 drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19769/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDMI2.1 PCON Misc Fixes (rev3)
== Series Details == Series: HDMI2.1 PCON Misc Fixes (rev3) URL : https://patchwork.freedesktop.org/series/86677/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/a
[Intel-gfx] [PATCH v3 3/3] drm/i915/display: Configure HDMI2.1 Pcon for FRL only if Src-Ctl mode is available
Currently we see only the MAX FRL BW from PCON before going for FRL. Also add the check if source control mode is supported by the PCON, before starting configuring PCON for FRL training. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 2e90359ce21f..8e401d3fd29d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2638,7 +2638,8 @@ void intel_dp_check_frl_training(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); /* Always go for FRL training if supported */ - if (!intel_dp_is_hdmi_2_1_sink(intel_dp) || + if (!(intel_dp->dpcd[2] & DP_PCON_SOURCE_CTL_MODE) || + !intel_dp_is_hdmi_2_1_sink(intel_dp) || intel_dp->frl.is_trained) return; -- 2.29.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/3] drm/i915/display: Remove FRL related code from disable DP sequence for older platforms
Remove code for resetting frl related members from intel_disable_dp, as this is not applicable for older platforms. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 85ec74ae952e..2e90359ce21f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2386,8 +2386,6 @@ static void intel_disable_dp(struct intel_atomic_state *state, intel_edp_backlight_off(old_conn_state); intel_dp_set_power(intel_dp, DP_SET_POWER_D3); intel_pps_off(intel_dp); - intel_dp->frl.is_trained = false; - intel_dp->frl.trained_rate_gbps = 0; } static void g4x_disable_dp(struct intel_atomic_state *state, -- 2.29.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
Currently the FRL training mode (Concurrent, Sequential) and
training type (Normal, Extended) are not defined properly and
are passed as bool values in drm_helpers for pcon
configuration for FRL training.
This patch:
-Add register masks for Sequential and Normal FRL training options.
-Fixes the drm_helpers for FRL Training configuration to use the
appropriate masks.
-Modifies the calls to the above drm_helpers in i915/intel_dp as per
the above change.
v2: Re-used the register masks for these options, instead of enum. (Ville)
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/drm_dp_helper.c | 24 ++--
drivers/gpu/drm/i915/display/intel_dp.c | 10 --
include/drm/drm_dp_helper.h | 6 --
3 files changed, 22 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index eedbb48815b7..cb2f53e56685 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -2635,14 +2635,16 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
* drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
* @aux: DisplayPort AUX channel
* @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
- * @concurrent_mode: true if concurrent mode or operation is required,
- * false otherwise.
+ * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
+ * In Concurrent Mode, the FRL link bring up can be done along with
+ * DP Link training. In Sequential mode, the FRL link bring up is done prior to
+ * the DP Link training.
*
* Returns 0 if success, else returns negative error code.
*/
int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
- bool concurrent_mode)
+ u8 frl_mode)
{
int ret;
u8 buf;
@@ -2651,7 +2653,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux,
int max_frl_gbps,
if (ret < 0)
return ret;
- if (concurrent_mode)
+ if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK)
buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
else
buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
@@ -2694,21 +2696,23 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
* drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
* @aux: DisplayPort AUX channel
* @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
- * @extended_train_mode : true for Extended Mode, false for Normal Mode.
- * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting
- * from min, and stops when link training is successful. In Extended mode, all
- * frl bw selected in the mask are trained by the PCON.
+ * @frl_type : FRL training type, can be Extended, or Normal.
+ * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask
+ * starting from min, and stops when link training is successful. In Extended
+ * FRL training, all frl bw selected in the mask are trained by the PCON.
*
* Returns 0 if success, else returns negative error code.
*/
int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
- bool extended_train_mode)
+ u8 frl_type)
{
int ret;
u8 buf = max_frl_mask;
- if (extended_train_mode)
+ if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED)
buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
+ else
+ buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
if (ret < 0)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4f89e0de5dde..85ec74ae952e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2557,10 +2557,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp
*intel_dp)
static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
{
-#define PCON_EXTENDED_TRAIN_MODE (1 > 0)
-#define PCON_CONCURRENT_MODE (1 > 0)
-#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
-#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
#define TIMEOUT_FRL_READY_MS 500
#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
@@ -2594,10 +2590,12 @@ static int intel_dp_pcon_start_frl_training(struct
intel_dp *intel_dp)
return -ETIMEDOUT;
max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
- ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
PCON_SEQUENTIAL_MODE);
+ ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
+ DP_PCON_ENABLE_SEQUENTIAL_LINK);
if (ret < 0)
return ret;
- ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
PCON_NORMAL_TRAIN_MODE);
+ ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
+
[Intel-gfx] [PATCH v3 0/3] HDMI2.1 PCON Misc Fixes
Patch1: Tweaks the drm_helpers for PCON configuration. Patch2: Removes unwanted code not applicable for older platforms. Patch3: Fixes condition for starting FRL link training. rev3: Patch-1 from rev2 [Read PCON DSC ENC caps only for DPCD rev >= 1.4] is dropped as it mixes DPCD and DP revisions. Ankit Nautiyal (3): drm/dp_helper: Define options for FRL training for HDMI2.1 PCON drm/i915/display: Remove FRL related code from disable DP sequence for older platforms drm/i915/display: Configure HDMI2.1 Pcon for FRL only if Src-Ctl mode is available drivers/gpu/drm/drm_dp_helper.c | 24 ++-- drivers/gpu/drm/i915/display/intel_dp.c | 15 ++- include/drm/drm_dp_helper.h | 6 -- 3 files changed, 24 insertions(+), 21 deletions(-) -- 2.29.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
As I realized, this patch is mixing DPCD rev and DP version, need an appropriate check instead. As for the gitlab issue https://gitlab.freedesktop.org/drm/intel/-/issues/2868 this seems to be not due to a DPCD register not defined for an older sink. The DPCD read in that case should have been 0, instead of timeout. I will drop this patch for now, from the series and revisit it later. Thanks & Regards, Ankit On 2/8/2021 5:14 PM, Nautiyal, Ankit K wrote: On 2/8/2021 4:45 PM, Jani Nikula wrote: On Thu, 04 Feb 2021, Ankit Nautiyal wrote: DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E. Do not read the registers if DPCD rev < 1.4. Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868 Please use Fixes: to reference commits that this patch fixes. Please use Closes: to reference issues that this patch fixes. No need to resend for this, can be fixed while applying, but please tell me the commit that introduced the problem. BR, Jani. Alright will take care. Please find below the commit that introduced this: b9d96dacdc3d983eae234b52401edb56dbceb764 Patch : drm/i915: Read DSC capabilities of the HDMI2.1 PCON encoder https://patchwork.freedesktop.org/patch/408779/ Thanks & Regards, Ankit Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8c12d5375607..2b83f0f433a2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2489,9 +2489,11 @@ static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) struct drm_i915_private *i915 = dp_to_i915(intel_dp); /* Clear the cached register set to avoid using stale values */ - memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); + if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) + return; + if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, intel_dp->pcon_dsc_dpcd, sizeof(intel_dp->pcon_dsc_dpcd)) < 0) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/12] drm/i915/bios: create fake child devices on missing VBT
On Wed, Feb 17, 2021 at 07:03:35PM +0200, Jani Nikula wrote:
Instead of initialing data directly in ddi_port_info array, create fake
child devices for default outputs when the VBT is missing. This makes
further unification of output handling easier.
This will make intel_bios_is_port_present() return true for the fake
child devices. This may cause subtle changes in a handful of places.
Cc: Lucas De Marchi
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 47 ++-
1 file changed, 37 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index b9d99324d66d..59d315b395c2 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2063,8 +2063,8 @@ init_vbt_missing_defaults(struct drm_i915_private *i915)
return;
for_each_port_masked(port, ports) {
- struct ddi_vbt_port_info *info =
- &i915->vbt.ddi_port_info[port];
+ struct display_device_data *devdata;
+ struct child_device_config *child;
enum phy phy = intel_port_to_phy(i915, port);
/*
@@ -2074,11 +2074,38 @@ init_vbt_missing_defaults(struct drm_i915_private *i915)
if (intel_phy_is_tc(i915, phy))
continue;
- info->supports_dvi = (port != PORT_A && port != PORT_E);
- info->supports_hdmi = info->supports_dvi;
- info->supports_dp = (port != PORT_E);
- info->supports_edp = (port == PORT_A);
+ /* Create fake child device config */
+ devdata = kzalloc(sizeof(*devdata), GFP_KERNEL);
+ if (!devdata)
+ break;
+
+ child = &devdata->child;
+
+ if (port == PORT_F)
+ child->dvo_port = DVO_PORT_HDMIF;
+ else if (port == PORT_E)
+ child->dvo_port = DVO_PORT_HDMIE;
+ else
+ child->dvo_port = DVO_PORT_HDMIA + port;
initially I was confused here, but after checking I understoo why you're
doing this, since DVO_PORT_HDMIE/DVO_PORT_HDMIF doesn't follow
DVO_PORT_HDMID
Reviewed-by: Lucas De Marchi
Lucas De Marchi
+
+ if (port != PORT_A && port != PORT_E)
+ child->device_type |= DEVICE_TYPE_TMDS_DVI_SIGNALING;
+
+ if (port != PORT_E)
+ child->device_type |= DEVICE_TYPE_DISPLAYPORT_OUTPUT;
+
+ if (port == PORT_A)
+ child->device_type |= DEVICE_TYPE_INTERNAL_CONNECTOR;
+
+ list_add_tail(&devdata->node, &i915->vbt.display_devices);
+
+ drm_dbg_kms(&i915->drm,
+ "Generating default VBT child device with type 0x04%x on
port %c\n",
+ child->device_type, port_name(port));
}
+
+ /* Bypass some minimum baseline VBT version checks */
+ i915->vbt.version = 155;
}
static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt)
@@ -2255,10 +2282,6 @@ void intel_bios_init(struct drm_i915_private *i915)
/* Depends on child device list */
parse_compression_parameters(i915, bdb);
- /* Further processing on pre-parsed data */
- parse_sdvo_device_mapping(i915);
- parse_ddi_ports(i915);
-
out:
if (!vbt) {
drm_info(&i915->drm,
@@ -2266,6 +2289,10 @@ void intel_bios_init(struct drm_i915_private *i915)
init_vbt_missing_defaults(i915);
}
+ /* Further processing on pre-parsed or generated child device data */
+ parse_sdvo_device_mapping(i915);
+ parse_ddi_ports(i915);
+
kfree(oprom_vbt);
}
--
2.20.1
___
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Re: [Intel-gfx] [PATCH] drm/atomic: Add the crtc to affected crtc only if uapi.enable = true
On Thu, Mar 04, 2021 at 10:42:23AM +0200, Pekka Paalanen wrote:
> On Wed, 3 Mar 2021 12:44:33 -0800
> "Navare, Manasi" wrote:
>
> > On Wed, Mar 03, 2021 at 10:47:44AM +0200, Pekka Paalanen wrote:
> > > On Tue, 2 Mar 2021 12:41:32 -0800
> > > Manasi Navare wrote:
> > >
> > > > In case of a modeset where a mode gets split across mutiple CRTCs
> > > > in the driver specific implementation (bigjoiner in i915) we wrongly
> > > > count
> > > > the affected CRTCs based on the drm_crtc_mask and indicate the stolen
> > > > CRTC as
> > > > an affected CRTC in atomic_check_only().
> > > > This triggers a warning since affected CRTCs doent match requested CRTC.
> > > >
> > > > To fix this in such bigjoiner configurations, we should only
> > > > increment affected crtcs if that CRTC is enabled in UAPI not
> > > > if it is just used internally in the driver to split the mode.
> > >
> > > Hi,
> > >
> > > I think that makes sense to me. Stealing CRTCs that are not currently
> > > used by the userspace (display server) should be ok, as long as that
> > > is completely invisible to userspace: meaning that it does not cause
> > > userspace to unexpectedly e.g. receive or miss per-crtc atomic
> > > completion events.
> >
> > Yes since we are only doing atomic_check_only() here, the stolen
>
> But the real not-test-only commit will follow if this test-only commit
> succeeds, and keeping the guarantees for the real commit are important.
Hmm well after the actual real commit, since the second crtc is stolen
even though it is not being used for the display output, it is
used for joiner so the uapi.enable will be true after the real commit.
so actually the assertion would fail in this case.
@Ville @Danvet any suggestions here in that case?
Manasi
>
> > crtc is completely invisible to the userspace and hence that is
> > indicated by uapi.enable which is not true for this stolen
> > crtc. However if allow modeset flag set, then it will do a full
> > modeset and indicate the uapi.enable for this stolen crtc as well
> > since that cannot be used for other modeset requested by userspace.
> >
> > >
> > > Can that also be asserted somehow, or does this already do that?
> >
> > Not clear what you want the assertion for? Could you elaborate
>
> As assertion that when the real atomic commit happens and then
> completion events are fired, they match exactly the affected crtcs mask.
>
> I understand this may be off-topic for this particular patch, but since
> we are discussing the topic, such checks would be really nice. I'm
> curious if such checks already exist.
>
>
> Thanks,
> pq
>
> >
> > Manasi
> >
> > >
> > >
> > > Thanks,
> > > pq
> > >
> > > > Cc: Ville Syrjälä
> > > > Cc: Simon Ser
> > > > Cc: Pekka Paalanen
> > > > Cc: Daniel Stone
> > > > Cc: Daniel Vetter
> > > > Cc: dri-de...@lists.freedesktop.org
> > > > Signed-off-by: Manasi Navare
> > > > ---
> > > > drivers/gpu/drm/drm_atomic.c | 6 --
> > > > 1 file changed, 4 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> > > > index 5b4547e0f775..d7acd6bbd97e 100644
> > > > --- a/drivers/gpu/drm/drm_atomic.c
> > > > +++ b/drivers/gpu/drm/drm_atomic.c
> > > > @@ -1358,8 +1358,10 @@ int drm_atomic_check_only(struct
> > > > drm_atomic_state *state)
> > > > }
> > > > }
> > > >
> > > > - for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)
> > > > - affected_crtc |= drm_crtc_mask(crtc);
> > > > + for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
> > > > + if (new_crtc_state->enable)
> > > > + affected_crtc |= drm_crtc_mask(crtc);
> > > > + }
> > > >
> > > > /*
> > > > * For commits that allow modesets drivers can add other CRTCs
> > > > to the
> > >
> >
> >
>
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Re: [Intel-gfx] [PATCH v3 2/8] drm/i915: split out stepping info to a new file
On Mon, Mar 08, 2021 at 03:56:39PM +0200, Jani Nikula wrote:
gt/intel_workarounds.c is decidedly the wrong place for handling
stepping info. Add new intel_step.[ch] for the data, and move the
stepping arrays there. No functional changes.
v2: Rename stepping->step
Signed-off-by: Jani Nikula
Reviewed-by: Lucas De Marchi
but what branch is this supposed to go to?
Lucas De Marchi
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 -
drivers/gpu/drm/i915/i915_drv.h | 19 +
drivers/gpu/drm/i915/intel_step.c | 46 +
drivers/gpu/drm/i915/intel_step.h | 25 +++
5 files changed, 74 insertions(+), 56 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_step.c
create mode 100644 drivers/gpu/drm/i915/intel_step.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index bc6138880c67..a9fb426d5e41 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -53,6 +53,7 @@ i915-y += i915_config.o \
intel_pm.o \
intel_runtime_pm.o \
intel_sideband.o \
+ intel_step.o \
intel_uncore.o \
intel_wakeref.o \
vlv_suspend.o
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3b4a7da60f0b..2827d4f2e086 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -52,45 +52,6 @@
* - Public functions to init or apply the given workaround type.
*/
-/*
- * KBL revision ID ordering is bizarre; higher revision ID's map to lower
- * steppings in some cases. So rather than test against the revision ID
- * directly, let's map that into our own range of increasing ID's that we
- * can test against in a regular manner.
- */
-
-const struct i915_rev_steppings kbl_revids[] = {
- [0] = { .gt_stepping = KBL_REVID_A0, .disp_stepping = KBL_REVID_A0 },
- [1] = { .gt_stepping = KBL_REVID_B0, .disp_stepping = KBL_REVID_B0 },
- [2] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B0 },
- [3] = { .gt_stepping = KBL_REVID_D0, .disp_stepping = KBL_REVID_B0 },
- [4] = { .gt_stepping = KBL_REVID_F0, .disp_stepping = KBL_REVID_C0 },
- [5] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B1 },
- [6] = { .gt_stepping = KBL_REVID_D1, .disp_stepping = KBL_REVID_B1 },
- [7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
-};
-
-const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
- [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
- [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
- [2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
- [3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 },
-};
-
-/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same
HW */
-const struct i915_rev_steppings tgl_revid_step_tbl[] = {
- [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 },
- [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
-};
-
-const struct i915_rev_steppings adls_revid_step_tbl[] = {
- [0x0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
- [0x1] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 },
- [0x4] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 },
- [0x8] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 },
- [0xC] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 },
-};
-
static void wa_init_start(struct i915_wa_list *wal, const char *name, const
char *engine_name)
{
wal->name = name;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2f511bf2bd82..02170edd6628 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -86,9 +86,10 @@
#include "gt/uc/intel_uc.h"
#include "intel_device_info.h"
+#include "intel_memory_region.h"
#include "intel_pch.h"
#include "intel_runtime_pm.h"
-#include "intel_memory_region.h"
+#include "intel_step.h"
#include "intel_uncore.h"
#include "intel_wakeref.h"
#include "intel_wopcm.h"
@@ -1471,14 +1472,6 @@ enum {
KBL_REVID_G0,
};
-struct i915_rev_steppings {
- u8 gt_stepping;
- u8 disp_stepping;
-};
-
-/* Defined in intel_workarounds.c */
-extern const struct i915_rev_steppings kbl_revids[];
-
#define IS_KBL_GT_REVID(dev_priv, since, until) \
(IS_KABYLAKE(dev_priv) && \
kbl_revids[INTEL_REVID(dev_priv)].gt_stepping >= since && \
@@ -1527,14 +1520,6 @@ enum {
STEP_D0,
};
-#define TGL_UY_REVID_STEP_TBL_SIZE 4
-#define TGL_REVID_STEP_TBL_SIZE2
-#define ADLS_REVID_STEP_TBL_SIZE 13
-
-extern const struct i915_rev_steppings
tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
-extern const struct i915_rev_steppings
tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
-extern co
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: refactor KBL/TGL/ADLS stepping scheme (rev2)
== Series Details == Series: drm/i915: refactor KBL/TGL/ADLS stepping scheme (rev2) URL : https://patchwork.freedesktop.org/series/87323/ State : success == Summary == CI Bug Log - changes from CI_DRM_9840_full -> Patchwork_19768_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_19768_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19768_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_19768_full: ### IGT changes ### Warnings * igt@runner@aborted: - shard-kbl: ([FAIL][1], [FAIL][2], [FAIL][3], [FAIL][4], [FAIL][5], [FAIL][6], [FAIL][7]) ([i915#180] / [i915#1814] / [i915#2292] / [i915#2724] / [i915#3002]) -> ([FAIL][8], [FAIL][9], [FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2292] / [i915#2505] / [i915#2724] / [i915#3002] / [i915#602] / [i915#92]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9840/shard-kbl3/igt@run...@aborted.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9840/shard-kbl7/igt@run...@aborted.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9840/shard-kbl7/igt@run...@aborted.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9840/shard-kbl7/igt@run...@aborted.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9840/shard-kbl4/igt@run...@aborted.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9840/shard-kbl2/igt@run...@aborted.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9840/shard-kbl3/igt@run...@aborted.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-kbl7/igt@run...@aborted.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-kbl2/igt@run...@aborted.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-kbl3/igt@run...@aborted.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-kbl7/igt@run...@aborted.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-kbl3/igt@run...@aborted.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-kbl3/igt@run...@aborted.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-kbl6/igt@run...@aborted.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-kbl7/igt@run...@aborted.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-kbl6/igt@run...@aborted.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-kbl3/igt@run...@aborted.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-kbl6/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_19768_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([i915#198]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9840/shard-skl9/igt@gem_ctx_isolation@preservation...@bcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-skl1/igt@gem_ctx_isolation@preservation...@bcs0.html - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9840/shard-kbl1/igt@gem_ctx_isolation@preservation...@bcs0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-kbl3/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_ctx_isolation@preservation-s3@vecs0: - shard-apl: NOTRUN -> [DMESG-WARN][23] ([i915#180]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-apl2/igt@gem_ctx_isolation@preservation...@vecs0.html * igt@gem_ctx_persistence@smoketest: - shard-snb: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#1099]) +3 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-snb2/igt@gem_ctx_persiste...@smoketest.html * igt@gem_eio@unwedge-stress: - shard-iclb: [PASS][25] -> [TIMEOUT][26] ([i915#2369] / [i915#2481] / [i915#3070]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9840/shard-iclb5/igt@gem_...@unwedge-stress.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-iclb1/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-skl: NOTRUN -> [SKIP][27] ([fdo#109271]) +68 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/shard-skl4/igt@gem_exec_fai
[Intel-gfx] 2021 X.Org Foundation Membership renewal ENDS on THURSDAY Mar 11
The nomination period for the 2021 X.Org Foundation Board of Directors Election closed yesterday and the election is rapidly approaching. We currently only see membership renewals for 59 people. If you have not renewed your membership please do so by Thursday, Mar 11 at https://members.x.org. The nominated candidates will be announced a week from yesterday. There were some hickups with our earlier emails and we realize some of you may have not received them. To ensure you receive this email we're BCCing any member that has been registered as a member in the last 2 years. ** Election Schedule ** Nomination period Start: Mon 22nd February Nomination period End: Sun 7th March Deadline of X.Org membership application or renewal: Thu 11th March Publication of Candidates & start of Candidate QA: Mon 15th March Election Planned Start: Mon 22nd March anywhere on earth Election Planned End: Sun 4th April anywhere on earth ** Election Committee ** * Eric Anholt * Mark Filion * Keith Packard * Harry Wentland Thanks, Harry Wentland, on behalf of the X.Org elections committee ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 13/16] drm/i915/pxp: User interface for Protected buffer
On 3/8/2021 1:01 PM, Lionel Landwerlin wrote:
On 08/03/2021 22:40, Rodrigo Vivi wrote:
On Wed, Mar 03, 2021 at 05:24:34PM -0800, Daniele Ceraolo Spurio wrote:
On 3/3/2021 4:10 PM, Daniele Ceraolo Spurio wrote:
On 3/3/2021 3:42 PM, Lionel Landwerlin wrote:
On 04/03/2021 01:25, Daniele Ceraolo Spurio wrote:
On 3/3/2021 3:16 PM, Lionel Landwerlin wrote:
On 03/03/2021 23:59, Daniele Ceraolo Spurio wrote:
On 3/3/2021 12:39 PM, Lionel Landwerlin wrote:
On 01/03/2021 21:31, Daniele Ceraolo Spurio wrote:
From: Bommu Krishnaiah
This api allow user mode to create Protected buffers. Only
contexts
marked as protected are allowed to operate on protected buffers.
We only allow setting the flags at creation time.
All protected objects that have backing storage will be
considered
invalid when the session is destroyed and they
won't be usable anymore.
This is a rework of the original code by Bommu Krishnaiah. I've
authorship unchanged since significant chunks
have not been modified.
v2: split context changes, fix defines and
improve documentation (Chris),
add object invalidation logic
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Daniele Ceraolo Spurio
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 27 +++--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 10 +
drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 +++
drivers/gpu/drm/i915/gem/i915_gem_object.h | 12 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 13 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c
| 40 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 13 ++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 5 +++
include/uapi/drm/i915_drm.h | 22 ++
9 files changed, 145 insertions(+), 3 deletions(-)
diff --git
a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 3ad3413c459f..d02e5938afbe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -5,6 +5,7 @@
#include "gem/i915_gem_ioctls.h"
#include "gem/i915_gem_region.h"
+#include "pxp/intel_pxp.h"
#include "i915_drv.h"
#include "i915_user_extensions.h"
@@ -13,7 +14,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -35,12 +37,17 @@ i915_gem_create(struct drm_file *file,
GEM_BUG_ON(size != obj->base.size);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
if (ret)
return ret;
+ if (user_flags & I915_GEM_OBJECT_PROTECTED)
+ intel_pxp_object_add(obj);
+
*handle_p = handle;
*size_p = size;
return 0;
@@ -89,11 +96,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
mem_type),
- &args->size, &args->handle);
+ &args->size, &args->handle, 0);
}
struct create_ext {
struct drm_i915_private *i915;
+ unsigned long user_flags;
};
static int __create_setparam(struct
drm_i915_gem_object_param *args,
@@ -104,6 +112,19 @@ static int
__create_setparam(struct
drm_i915_gem_object_param *args,
return -EINVAL;
}
+ switch (lower_32_bits(args->param)) {
+ case I915_OBJECT_PARAM_PROTECTED_CONTENT:
+ if (!intel_pxp_is_enabled(&ext_data->i915->gt.pxp))
+ return -ENODEV;
+ if (args->size) {
+ return -EINVAL;
+ } else if (args->data) {
+ ext_data->user_flags |= I915_GEM_OBJECT_PROTECTED;
+ return 0;
+ }
+ break;
+ }
+
return -EINVAL;
}
@@ -148,5 +169,5 @@
i915_gem_create_ioctl(struct drm_device *dev,
void *data,
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
- &args->size, &args->handle);
+ &args->size, &args->handle,
ext_data.user_flags);
}
diff --git
a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index e503c9f789c0..d10c4fcb6aec 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -20,6 +20,7 @@
#include "gt/intel_gt_buffer_pool.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_ring.h"
+#include "pxp/intel_pxp.h"
#include "pxp/intel_pxp.h"
@@ -500,6 +501,15 @@ eb_validate_vma(struct
i915_execbuffer *eb,
entry->offset !=
gen8_canonical_addr(entry->offset &
I915_GTT_PAGE_MASK)))
return -EINVAL;
Re: [Intel-gfx] [PATCH v2 13/16] drm/i915/pxp: User interface for Protected buffer
On 08/03/2021 22:40, Rodrigo Vivi wrote:
On Wed, Mar 03, 2021 at 05:24:34PM -0800, Daniele Ceraolo Spurio wrote:
On 3/3/2021 4:10 PM, Daniele Ceraolo Spurio wrote:
On 3/3/2021 3:42 PM, Lionel Landwerlin wrote:
On 04/03/2021 01:25, Daniele Ceraolo Spurio wrote:
On 3/3/2021 3:16 PM, Lionel Landwerlin wrote:
On 03/03/2021 23:59, Daniele Ceraolo Spurio wrote:
On 3/3/2021 12:39 PM, Lionel Landwerlin wrote:
On 01/03/2021 21:31, Daniele Ceraolo Spurio wrote:
From: Bommu Krishnaiah
This api allow user mode to create Protected buffers. Only contexts
marked as protected are allowed to operate on protected buffers.
We only allow setting the flags at creation time.
All protected objects that have backing storage will be considered
invalid when the session is destroyed and they
won't be usable anymore.
This is a rework of the original code by Bommu Krishnaiah. I've
authorship unchanged since significant chunks
have not been modified.
v2: split context changes, fix defines and
improve documentation (Chris),
add object invalidation logic
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Daniele Ceraolo Spurio
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 27 +++--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 10 +
drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 +++
drivers/gpu/drm/i915/gem/i915_gem_object.h | 12 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 13 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c
| 40 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 13 ++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 5 +++
include/uapi/drm/i915_drm.h | 22 ++
9 files changed, 145 insertions(+), 3 deletions(-)
diff --git
a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 3ad3413c459f..d02e5938afbe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -5,6 +5,7 @@
#include "gem/i915_gem_ioctls.h"
#include "gem/i915_gem_region.h"
+#include "pxp/intel_pxp.h"
#include "i915_drv.h"
#include "i915_user_extensions.h"
@@ -13,7 +14,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -35,12 +37,17 @@ i915_gem_create(struct drm_file *file,
GEM_BUG_ON(size != obj->base.size);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
if (ret)
return ret;
+ if (user_flags & I915_GEM_OBJECT_PROTECTED)
+ intel_pxp_object_add(obj);
+
*handle_p = handle;
*size_p = size;
return 0;
@@ -89,11 +96,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
mem_type),
- &args->size, &args->handle);
+ &args->size, &args->handle, 0);
}
struct create_ext {
struct drm_i915_private *i915;
+ unsigned long user_flags;
};
static int __create_setparam(struct
drm_i915_gem_object_param *args,
@@ -104,6 +112,19 @@ static int
__create_setparam(struct
drm_i915_gem_object_param *args,
return -EINVAL;
}
+ switch (lower_32_bits(args->param)) {
+ case I915_OBJECT_PARAM_PROTECTED_CONTENT:
+ if (!intel_pxp_is_enabled(&ext_data->i915->gt.pxp))
+ return -ENODEV;
+ if (args->size) {
+ return -EINVAL;
+ } else if (args->data) {
+ ext_data->user_flags |= I915_GEM_OBJECT_PROTECTED;
+ return 0;
+ }
+ break;
+ }
+
return -EINVAL;
}
@@ -148,5 +169,5 @@
i915_gem_create_ioctl(struct drm_device *dev,
void *data,
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
- &args->size, &args->handle);
+ &args->size, &args->handle,
ext_data.user_flags);
}
diff --git
a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index e503c9f789c0..d10c4fcb6aec 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -20,6 +20,7 @@
#include "gt/intel_gt_buffer_pool.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_ring.h"
+#include "pxp/intel_pxp.h"
#include "pxp/intel_pxp.h"
@@ -500,6 +501,15 @@ eb_validate_vma(struct i915_execbuffer *eb,
entry->offset !=
gen8_canonical_addr(entry->offset &
I915_GTT
[Intel-gfx] ✓ Fi.CI.IGT: success for gpu: drm: i915: fix error return code of igt_buddy_alloc_smoke()
== Series Details == Series: gpu: drm: i915: fix error return code of igt_buddy_alloc_smoke() URL : https://patchwork.freedesktop.org/series/87766/ State : success == Summary == CI Bug Log - changes from CI_DRM_9839_full -> Patchwork_19767_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_19767_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-hostile-preempt: - shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-hostile-preempt.html * igt@gem_eio@unwedge-stress: - shard-skl: [PASS][2] -> [TIMEOUT][3] ([i915#2369] / [i915#2771]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9839/shard-skl6/igt@gem_...@unwedge-stress.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/shard-skl9/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][4] ([i915#2846]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/shard-apl3/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-skl: NOTRUN -> [SKIP][5] ([fdo#109271]) +69 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/shard-skl6/igt@gem_exec_fair@basic-f...@rcs0.html - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9839/shard-tglb5/igt@gem_exec_fair@basic-f...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9839/shard-kbl2/igt@gem_exec_fair@basic-p...@vecs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/shard-kbl1/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-glk: NOTRUN -> [FAIL][10] ([i915#2389]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/shard-glk7/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_exec_reloc@basic-many-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][11] ([i915#2389]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/shard-iclb4/igt@gem_exec_reloc@basic-many-act...@vcs1.html * igt@gem_exec_reloc@basic-parallel: - shard-skl: NOTRUN -> [TIMEOUT][12] ([i915#1729]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/shard-skl2/igt@gem_exec_re...@basic-parallel.html - shard-apl: NOTRUN -> [TIMEOUT][13] ([i915#1729]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/shard-apl7/igt@gem_exec_re...@basic-parallel.html * igt@gem_exec_schedule@u-fairslice@rcs0: - shard-kbl: [PASS][14] -> [DMESG-WARN][15] ([i915#1610] / [i915#2803]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9839/shard-kbl3/igt@gem_exec_schedule@u-fairsl...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/shard-kbl4/igt@gem_exec_schedule@u-fairsl...@rcs0.html - shard-tglb: [PASS][16] -> [DMESG-WARN][17] ([i915#2803]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9839/shard-tglb8/igt@gem_exec_schedule@u-fairsl...@rcs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/shard-tglb8/igt@gem_exec_schedule@u-fairsl...@rcs0.html * igt@gem_mmap_gtt@cpuset-medium-copy: - shard-glk: [PASS][18] -> [FAIL][19] ([i915#307]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9839/shard-glk9/igt@gem_mmap_...@cpuset-medium-copy.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/shard-glk8/igt@gem_mmap_...@cpuset-medium-copy.html * igt@gem_pread@exhaustion: - shard-kbl: NOTRUN -> [WARN][20] ([i915#2658]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/shard-kbl6/igt@gem_pr...@exhaustion.html * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled: - shard-kbl: NOTRUN -> [SKIP][21] ([fdo#109271]) +43 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/shard-kbl4/igt@gem_render_c...@x-tiled-to-vebox-yf-tiled.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][22] ([i915#3002]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/shard-apl8/igt@gem_userptr_bl...@input-checking.html * igt@gem_userptr_blits@process-exit-mmap@wb: - shard-skl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#1699]) +3 similar issues [23]: https://intel-gfx-ci.01.org
Re: [Intel-gfx] [PATCH v2 13/16] drm/i915/pxp: User interface for Protected buffer
On Wed, Mar 03, 2021 at 05:24:34PM -0800, Daniele Ceraolo Spurio wrote:
>
>
> On 3/3/2021 4:10 PM, Daniele Ceraolo Spurio wrote:
> >
> >
> > On 3/3/2021 3:42 PM, Lionel Landwerlin wrote:
> > > On 04/03/2021 01:25, Daniele Ceraolo Spurio wrote:
> > > >
> > > >
> > > > On 3/3/2021 3:16 PM, Lionel Landwerlin wrote:
> > > > > On 03/03/2021 23:59, Daniele Ceraolo Spurio wrote:
> > > > > >
> > > > > >
> > > > > > On 3/3/2021 12:39 PM, Lionel Landwerlin wrote:
> > > > > > > On 01/03/2021 21:31, Daniele Ceraolo Spurio wrote:
> > > > > > > > From: Bommu Krishnaiah
> > > > > > > >
> > > > > > > > This api allow user mode to create Protected buffers. Only
> > > > > > > > contexts
> > > > > > > > marked as protected are allowed to operate on protected buffers.
> > > > > > > >
> > > > > > > > We only allow setting the flags at creation time.
> > > > > > > >
> > > > > > > > All protected objects that have backing storage will be
> > > > > > > > considered
> > > > > > > > invalid when the session is destroyed and they
> > > > > > > > won't be usable anymore.
> > > > > > > >
> > > > > > > > This is a rework of the original code by Bommu Krishnaiah. I've
> > > > > > > > authorship unchanged since significant chunks
> > > > > > > > have not been modified.
> > > > > > > >
> > > > > > > > v2: split context changes, fix defines and
> > > > > > > > improve documentation (Chris),
> > > > > > > > add object invalidation logic
> > > > > > > >
> > > > > > > > Signed-off-by: Bommu Krishnaiah
> > > > > > > > Signed-off-by: Daniele Ceraolo Spurio
> > > > > > > >
> > > > > > > > Cc: Telukuntla Sreedhar
> > > > > > > > Cc: Kondapally Kalyan
> > > > > > > > Cc: Gupta Anshuman
> > > > > > > > Cc: Huang Sean Z
> > > > > > > > Cc: Chris Wilson
> > > > > > > > ---
> > > > > > > > drivers/gpu/drm/i915/gem/i915_gem_create.c | 27
> > > > > > > > +++--
> > > > > > > > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 10 +
> > > > > > > > drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 +++
> > > > > > > > drivers/gpu/drm/i915/gem/i915_gem_object.h | 12 ++
> > > > > > > > .../gpu/drm/i915/gem/i915_gem_object_types.h | 13 ++
> > > > > > > > drivers/gpu/drm/i915/pxp/intel_pxp.c
> > > > > > > > | 40 +++
> > > > > > > > drivers/gpu/drm/i915/pxp/intel_pxp.h | 13 ++
> > > > > > > > drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 5 +++
> > > > > > > > include/uapi/drm/i915_drm.h | 22 ++
> > > > > > > > 9 files changed, 145 insertions(+), 3 deletions(-)
> > > > > > > >
> > > > > > > > diff --git
> > > > > > > > a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> > > > > > > > b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> > > > > > > > index 3ad3413c459f..d02e5938afbe 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> > > > > > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> > > > > > > > @@ -5,6 +5,7 @@
> > > > > > > > #include "gem/i915_gem_ioctls.h"
> > > > > > > > #include "gem/i915_gem_region.h"
> > > > > > > > +#include "pxp/intel_pxp.h"
> > > > > > > > #include "i915_drv.h"
> > > > > > > > #include "i915_user_extensions.h"
> > > > > > > > @@ -13,7 +14,8 @@ static int
> > > > > > > > i915_gem_create(struct drm_file *file,
> > > > > > > > struct intel_memory_region *mr,
> > > > > > > > u64 *size_p,
> > > > > > > > - u32 *handle_p)
> > > > > > > > + u32 *handle_p,
> > > > > > > > + u64 user_flags)
> > > > > > > > {
> > > > > > > > struct drm_i915_gem_object *obj;
> > > > > > > > u32 handle;
> > > > > > > > @@ -35,12 +37,17 @@ i915_gem_create(struct drm_file *file,
> > > > > > > > GEM_BUG_ON(size != obj->base.size);
> > > > > > > > + obj->user_flags = user_flags;
> > > > > > > > +
> > > > > > > > ret = drm_gem_handle_create(file, &obj->base, &handle);
> > > > > > > > /* drop reference from allocate - handle holds it now */
> > > > > > > > i915_gem_object_put(obj);
> > > > > > > > if (ret)
> > > > > > > > return ret;
> > > > > > > > + if (user_flags & I915_GEM_OBJECT_PROTECTED)
> > > > > > > > + intel_pxp_object_add(obj);
> > > > > > > > +
> > > > > > > > *handle_p = handle;
> > > > > > > > *size_p = size;
> > > > > > > > return 0;
> > > > > > > > @@ -89,11 +96,12 @@ i915_gem_dumb_create(struct drm_file *file,
> > > > > > > > return i915_gem_create(file,
> > > > > > > > intel_memory_region_by_type(to_i915(dev),
> > > > > > > > mem_type),
> > > > > > > > - &args->size, &args->handle);
> > > > > > > > + &args->size, &args->handle, 0);
> > > > > > > > }
> > > > > > > > struct create_ext {
> > > > > > > > struct drm_i915_private *i915;
> > > > > > > > + unsigned long user_flags;
> > > > > > > > };
> > > > > > > > static int __create_setparam(struct
> > >
Re: [Intel-gfx] [PATCH 1/4] drm/i915/gen12: Add recommended hardware tuning value
On Tue, Mar 02, 2021 at 07:14:07PM -0800, Matt Roper wrote:
On Tue, Mar 02, 2021 at 05:07:25PM -0800, Lucas De Marchi wrote:
From: Caz Yokoyama
Follow Bspec 31870 to set recommended tuning values for certain GT
register. These values aren't workarounds per-se, but it's best to
handle them in the same general area of the driver, especially since
there may be real workarounds that update other bits of the same
registers.
At the moment the only value we need to worry about is the
TDS_TIMER setting in FF_MODE2. This setting was previously
described as "Wa_1604555607" on some platforms, but the spec
tells us that we should continue to program this on all current
gen12 platforms, even those that do not have that WA.
Bspec: 31870
Cc: Clinton Taylor
Cc: Matt Roper
Signed-off-by: Caz Yokoyama
Signed-off-by: Lucas De Marchi
A couple minor nitpicks about the comments, but you can tweak those
while applying.
Reviewed-by: Matt Roper
There appear to be some other registers recommended on the same bspec
tuning page that we don't seem to be handling yet. Will those be coming
as additional patches?
I don't have those ready, but that is the intention, yes. Here I
basically wanted to get the basic changes in place to make those
possible, while moving the one we already have in the driver there.
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 -
1 file changed, 37 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3b4a7da60f0b..f6d9b849aa62 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -646,9 +646,38 @@ static void icl_ctx_workarounds_init(struct
intel_engine_cs *engine,
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
}
+/*
+ * These settings aren't actually workarounds, but general tuning settings that
+ * need to be programmed on several platforms.
+ */
+static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
+struct i915_wa_list *wal)
+{
+ /*
+* Although some platforms refer to it as Wa_1604555607, we need to
+* program it even on those that don't explicitly list that
+* workaround.
+*
+* Note that the implementation of this workaround is further modified
Since we just got done saying that this technically isn't a workaround,
even though some of the older platforms still list it that way, I'd
re-word the comment here. Maybe "Note that the programming of this
register is further modified..." would be more appropriate.
+* according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
+*
Minor nitpick; the new paragraph start here makes it sound like we've
moved on to describing something else, rather than explaining what
Wa_1608008084:gen12 asks us to do. I'd remove the blank line here and
start the next sentence with "Wa_1608008084 tells us..." to link the
statements together.
thanks. I changed those and will resubmit.
Lucas De Marchi
Matt
+* FF_MODE2 register will return the wrong value when read. The default
+* value for this register is zero for all fields and there are no bit
+* masks. So instead of doing a RMW we should just write TDS timer
+* value. For the same reason read verification is ignored.
+*/
+ wa_add(wal,
+ FF_MODE2,
+ FF_MODE2_TDS_TIMER_MASK,
+ FF_MODE2_TDS_TIMER_128,
+ 0);
+}
+
static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
+ gen12_ctx_gt_tuning_init(engine, wal);
+
/*
* Wa_1409142259:tgl
* Wa_1409347922:tgl
@@ -675,19 +704,15 @@ static void tgl_ctx_workarounds_init(struct
intel_engine_cs *engine,
gen12_ctx_workarounds_init(engine, wal);
/*
-* Wa_1604555607:tgl,rkl
+* Wa_16011163337
*
-* Note that the implementation of this workaround is further modified
-* according to the FF_MODE2 guidance given by Wa_1608008084:gen12.
-* FF_MODE2 register will return the wrong value when read. The default
-* value for this register is zero for all fields and there are no bit
-* masks. So instead of doing a RMW we should just write the GS Timer
-* and TDS timer values for Wa_1604555607 and Wa_16011163337.
+* Like in gen12_ctx_gt_tuning_init(), read verification is ignored due
+* to Wa_1608008084.
*/
wa_add(wal,
FF_MODE2,
- FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
- FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128,
+ FF_MODE2_GS_TIMER_MASK,
+ FF_MODE2_GS_TIMER_224,
0);
}
@@ -707,12 +732,13 @@ static void dg1_ctx_workarounds_init(struct
Re: [Intel-gfx] [PATCH v2 09/16] drm/i915/pxp: Implement PXP irq handler
On 3/3/2021 1:18 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:53)
From: "Huang, Sean Z"
The HW will generate a teardown interrupt when session termination is
required, which requires i915 to submit a terminating batch. Once the HW
is done with the termination it will generate another interrupt, at
which point it is safe to re-create the session.
v2: use struct completion instead of bool (Chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 34 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 ++
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 151 +++
drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 33
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 9 +-
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 10 +-
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 8 +
11 files changed, 268 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8b605f326039..5e9bd34dec38 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -274,6 +274,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_cmd.o \
+ pxp/intel_pxp_irq.o \
pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index d29126c458ba..0d3585efe2b8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -13,6 +13,7 @@
#include "intel_lrc_reg.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp_irq.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -64,6 +65,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>->rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(>->pxp, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
@@ -190,6 +194,9 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
+
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0);
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0);
}
void gen11_gt_irq_postinstall(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e5dd0203991b..97a6d0c638ec 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7958,6 +7958,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index cbec9395bde9..0ca1c2c16972 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -2,7 +2,9 @@
/*
* Copyright(c) 2020 Intel Corporation.
*/
+#include
#include "intel_pxp.h"
+#include "intel_pxp_irq.h"
#include "intel_pxp_tee.h"
#include "gt/intel_context.h"
#include "i915_drv.h"
@@ -67,12 +69,23 @@ void intel_pxp_init(struct intel_pxp *pxp)
mutex_init(&pxp->mutex);
+ /*
+* we'll use the completion to check if there is a termination pending,
+* so we start it as completed and we reinit it when a termination
+* is triggered.
+*/
+ init_completion(&pxp->termination);
+ complete_all(&pxp->termination);
+
kcr_pxp_enable(gt);
ret = create_vcs_context(pxp);
if (ret)
goto out_kcr;
+ intel_pxp_irq_init(pxp);
+ intel_pxp_irq_enable(pxp);
+
ret = intel_pxp_tee_component_init(pxp);
if (ret)
goto out_context;
@@ -94,10 +107,31 @@ void intel_pxp_fini(struct intel_pxp *pxp)
if (!intel_pxp_is_enabled(pxp))
return;
+ intel_pxp_irq_disable(pxp);
+
intel_pxp_tee_component_fini(pxp);
destroy_vcs_context(pxp);
kcr_pxp_disable(gt);
+}
+int intel_pxp_wait_for_termination_completion(struct intel_pxp *p
Re: [Intel-gfx] [PATCH v2 11/16] drm/i915/pxp: interface for creation of protected contexts
On 3/3/2021 3:16 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-03-01 19:31:55)
Usage of protected objects, coming in a follow-up patch, will be
restricted to protected contexts. Contexts can only be marked as
protected at creation time and they must be both bannable and not
recoverable.
When a PXP teardown occurs, all gem contexts marked as protected that
have been used at least once will be marked as invalid and all new
submissions using them will be rejected. All intel contexts within the
invalidated gem contexts will be marked banned.
A new flag has been added to the RESET_STATS ioctl to report the
invalidation to userspace.
v2: split to its own patch and improve doc (Chris), invalidate contexts
on teardown
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 59 ++-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 18 ++
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 13
drivers/gpu/drm/i915/pxp/intel_pxp.c | 38
drivers/gpu/drm/i915/pxp/intel_pxp.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 3 +
include/uapi/drm/i915_drm.h | 19 ++
8 files changed, 150 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ca37d93ef5e7..19ac24a3c42c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -76,6 +76,8 @@
#include "gt/intel_gpu_commands.h"
#include "gt/intel_ring.h"
+#include "pxp/intel_pxp.h"
+
#include "i915_drm_client.h"
#include "i915_gem_context.h"
#include "i915_globals.h"
@@ -2006,6 +2008,40 @@ static int set_priority(struct i915_gem_context *ctx,
return 0;
}
+static int set_protected(struct i915_gem_context *ctx,
+const struct drm_i915_gem_context_param *args)
+{
+ int ret = 0;
+
+ if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
+ ret = -ENODEV;
+ else if (ctx->client) /* can't change this after creation! */
+ ret = -EEXIST;
+ else if (args->size)
+ ret = -EINVAL;
+ else if (!args->value)
+ clear_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+ else if (i915_gem_context_is_recoverable(ctx) ||
+!i915_gem_context_is_bannable(ctx))
+ ret = -EPERM;
+ else
+ set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+
+ return ret;
+}
+
+static int get_protected(struct i915_gem_context *ctx,
+struct drm_i915_gem_context_param *args)
+{
+ if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
+ return -ENODEV;
+
+ args->size = 0;
+ args->value = i915_gem_context_can_use_protected_content(ctx);
+
+ return 0;
+}
+
static int ctx_setparam(struct drm_i915_file_private *fpriv,
struct i915_gem_context *ctx,
struct drm_i915_gem_context_param *args)
@@ -2038,6 +2074,8 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
ret = -EPERM;
else if (args->value)
i915_gem_context_set_bannable(ctx);
+ else if (i915_gem_context_can_use_protected_content(ctx))
+ ret = -EPERM; /* can't clear this for protected
contexts */
else
i915_gem_context_clear_bannable(ctx);
break;
@@ -2045,10 +2083,12 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
- else
+ else if (!args->value)
i915_gem_context_clear_recoverable(ctx);
+ else if (i915_gem_context_can_use_protected_content(ctx))
+ ret = -EPERM; /* can't set this for protected contexts
*/
+ else
+ i915_gem_context_set_recoverable(ctx);
break;
case I915_CONTEXT_PARAM_PRIORITY:
@@ -2075,6 +2115,10 @@ static int ctx_setparam(struct drm_i915_file_private
*fpriv,
ret = set_ringsize(ctx, args);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ ret = set_protected(ctx, args);
+ break;
+
case I915_CONTEXT_PARAM_BAN_PERIOD:
default:
ret = -EINVAL;
@@ -2532,6 +2576,10 @@ int i915_gem_context_getparam_ioctl(struct drm_device
*dev, void *data,
ret = get_ringsize(ctx, args);
break;
+ case I915_
Re: [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9
I've tested on GLK, KBL, CFL Intel NUC devices and got the following performance results, there is no performance regression per my testing. Patch: [v5] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 Test suite: phoronix-test-suite.supertuxkart.1024x768.Fullscreen.Ultimate.1.GranParadisoIsland.frames_per_second Kernel version: 5.12.0-rc1 (drm-tip) a. Device: Intel NUC kit NUC7JY Gemini Lake Celeron J4005 @2.7GHz (2 Cores) Without patch, fps=57.45 With patch, fps=57.49 b. Device: Intel NUC kit NUC8BEH Coffee Lake Core i3-8109U @3.6GHz(4 Cores) Without patch, fps=117.23 With patch, fps=117.27 c. Device: Intel NUC kit NUC7i3BNH Kaby Lake Core i3-7100U @2.4GHz(4 Cores) Without patch, fps=114.05 With patch, fps=114.34 Meanwhile, Intel lkp team has validated performance on lkp-kbl-nuc1 and no regression. f69d02e37a85645a d912096c40cdc3bc9364966971 testcase/testparams/testbox -- --- %stddev change %stddev \ |\ 29.79 29.67 phoronix-test-suite/performance-true-Fullscreen-Ultimate-1-Gran_Paradiso_Island__Approxima-supertuxkart-1.5.2-ucode=0xde/lkp-kbl-nuc1 29.79 29.67GEO-MEAN phoronix-test-suite.supertuxkart.1280x1024.Fullscreen.Ultimate.1.GranParadisoIsland.frames_per_second Best Regards, Cooper > We need testing on more that one box I'm afraid. Need to cover different > fusing configs of Gen9 with and without the patch. I don't have any useful > ideas on how to do it though. :( > > Regards, > > Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: refactor KBL/TGL/ADLS stepping scheme (rev2)
== Series Details ==
Series: drm/i915: refactor KBL/TGL/ADLS stepping scheme (rev2)
URL : https://patchwork.freedesktop.org/series/87323/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9840 -> Patchwork_19768
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/index.html
Known issues
Here are the changes found in Patchwork_19768 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_tiled_blits@basic:
- fi-kbl-8809g: [PASS][1] -> [TIMEOUT][2] ([i915#2502] / [i915#3145])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9840/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
* igt@i915_selftest@live@client:
- fi-glk-dsi: [PASS][3] -> [DMESG-FAIL][4] ([i915#3047])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9840/fi-glk-dsi/igt@i915_selftest@l...@client.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/fi-glk-dsi/igt@i915_selftest@l...@client.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [FAIL][5] ([i915#1888]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9840/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
* igt@gem_tiled_fence_blits@basic:
- fi-kbl-8809g: [TIMEOUT][7] ([i915#3145]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9840/fi-kbl-8809g/igt@gem_tiled_fence_bl...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/fi-kbl-8809g/igt@gem_tiled_fence_bl...@basic.html
* igt@i915_selftest@live@client:
- fi-bsw-kefka: [DMESG-FAIL][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9840/fi-bsw-kefka/igt@i915_selftest@l...@client.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/fi-bsw-kefka/igt@i915_selftest@l...@client.html
* igt@kms_flip@basic-flip-vs-modeset@d-dsi1:
- {fi-tgl-dsi}: [DMESG-WARN][11] ([i915#402]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9840/fi-tgl-dsi/igt@kms_flip@basic-flip-vs-mode...@d-dsi1.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/fi-tgl-dsi/igt@kms_flip@basic-flip-vs-mode...@d-dsi1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502
[i915#3047]: https://gitlab.freedesktop.org/drm/intel/issues/3047
[i915#3145]: https://gitlab.freedesktop.org/drm/intel/issues/3145
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (46 -> 42)
--
Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_9840 -> Patchwork_19768
CI-20190529: 20190529
CI_DRM_9840: c32ebbc1bfd09da5fd10264570b81c9e65091a08 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6026: 8b8bbecf2f32298544c2f193753a0153f39e7326 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19768: d1a2f1d5bb5c67b4f1bd95219ba73da00960d641 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d1a2f1d5bb5c drm/i915: rename i915_rev_steppings->intel_step_info
19a6fa288b97 drm/i915: rename disp_stepping->display_step and
gt_stepping->gt_step
f94a68bcd095 drm/i915: rename DISP_STEPPING->DISPLAY_STEP and
GT_STEPPING->GT_STEP
3ab291f069dc drm/i915: switch TGL and ADL to the new stepping scheme
c5a4a8ab6645 drm/i915: switch KBL to the new stepping scheme
93d71ad11f06 drm/i915: add new helpers for accessing stepping info
1d23fa9cb274 drm/i915: split out stepping info to a new file
c52f0ea75128 drm/i915: remove unused ADLS_REVID_* macros
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19768/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: refactor KBL/TGL/ADLS stepping scheme (rev2)
== Series Details == Series: drm/i915: refactor KBL/TGL/ADLS stepping scheme (rev2) URL : https://patchwork.freedesktop.org/series/87323/ State : warning == Summary == $ dim checkpatch origin/drm-tip c52f0ea75128 drm/i915: remove unused ADLS_REVID_* macros 1d23fa9cb274 drm/i915: split out stepping info to a new file -:123: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #123: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 162 lines checked 93d71ad11f06 drm/i915: add new helpers for accessing stepping info -:30: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #30: FILE: drivers/gpu/drm/i915/i915_drv.h:1280: +#define IS_DISPLAY_STEP(__i915, since, until) \ + (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ +INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until)) -:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #34: FILE: drivers/gpu/drm/i915/i915_drv.h:1284: +#define IS_GT_STEP(__i915, since, until) \ + (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \ +INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) <= (until)) total: 0 errors, 0 warnings, 2 checks, 70 lines checked c5a4a8ab6645 drm/i915: switch KBL to the new stepping scheme -:108: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #108: FILE: drivers/gpu/drm/i915/i915_drv.h:1478: +#define IS_KBL_GT_STEP(dev_priv, since, until) \ + (IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until)) -:110: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #110: FILE: drivers/gpu/drm/i915/i915_drv.h:1480: +#define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \ + (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until)) -:151: CHECK:LINE_SPACING: Please don't use multiple blank lines #151: FILE: drivers/gpu/drm/i915/intel_step.c:16: + total: 0 errors, 0 warnings, 3 checks, 198 lines checked 3ab291f069dc drm/i915: switch TGL and ADL to the new stepping scheme -:54: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #54: FILE: drivers/gpu/drm/i915/i915_drv.h:1513: +#define IS_TGL_DISP_STEPPING(__i915, since, until) \ + (IS_TIGERLAKE(__i915) && \ +IS_DISPLAY_STEP(__i915, since, until)) -:62: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #62: FILE: drivers/gpu/drm/i915/i915_drv.h:1517: +#define IS_TGL_UY_GT_STEPPING(__i915, since, until) \ + ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ +IS_GT_STEP(__i915, since, until)) -:71: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #71: FILE: drivers/gpu/drm/i915/i915_drv.h:1521: +#define IS_TGL_GT_STEPPING(__i915, since, until) \ + (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ +IS_GT_STEP(__i915, since, until)) -:85: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #85: FILE: drivers/gpu/drm/i915/i915_drv.h:1538: +#define IS_ADLS_DISP_STEPPING(__i915, since, until) \ + (IS_ALDERLAKE_S(__i915) && \ +IS_DISPLAY_STEP(__i915, since, until)) -:93: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #93: FILE: drivers/gpu/drm/i915/i915_drv.h:1542: +#define IS_ADLS_GT_STEPPING(__i915, since, until) \ + (IS_ALDERLAKE_S(__i915) && \ +IS_GT_STEP(__i915, since, until)) total: 0 errors, 0 warnings, 5 checks, 127 lines checked f94a68bcd095 drm/i915: rename DISP_STEPPING->DISPLAY_STEP and GT_STEPPING->GT_STEP -:113: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #113: FILE: drivers/gpu/drm/i915/i915_drv.h:1513: +#define IS_TGL_DISPLAY_STEP(__i915, since, until) \ (IS_TIGERLAKE(__i915) && \ IS_DISPLAY_STEP(__i915, since, until)) -:118: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #118: FILE: drivers/gpu/drm/i915/i915_drv.h:1517: +#define IS_TGL_UY_GT_STEP(__i915, since, until) \ ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ IS_GT_STEP(__i915, since, until)) -:123: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #123: FILE: drivers/gpu/drm/i915/i915_drv.h:1521: +#define IS_TGL_GT_STEP(__i915, since, until) \ (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ IS_GT_STEP(__i915, since, until)) -:132: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #132: FILE: drivers/gpu/drm/i915/i915_drv.h:1538: +#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \ (IS_ALDERLAKE_S(__i915) && \ IS_DISPLAY_STEP(__i915, since, until)) -:137: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects? #137: FILE: drivers/gpu/drm/i915/i915_drv.h:1542: +#define IS_ADLS_G
[Intel-gfx] ✓ Fi.CI.BAT: success for gpu: drm: i915: fix error return code of igt_buddy_alloc_smoke()
== Series Details == Series: gpu: drm: i915: fix error return code of igt_buddy_alloc_smoke() URL : https://patchwork.freedesktop.org/series/87766/ State : success == Summary == CI Bug Log - changes from CI_DRM_9839 -> Patchwork_19767 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/index.html Known issues Here are the changes found in Patchwork_19767 that come from known issues: ### IGT changes ### Possible fixes * igt@debugfs_test@read_all_entries: - fi-cfl-8109u: [DMESG-WARN][1] ([i915#203] / [i915#262]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9839/fi-cfl-8109u/igt@debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/fi-cfl-8109u/igt@debugfs_test@read_all_entries.html * igt@gem_exec_gttfill@basic: - fi-kbl-8809g: [TIMEOUT][3] ([i915#3145]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9839/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html * igt@gem_exec_suspend@basic-s0: - fi-cfl-8109u: [DMESG-WARN][5] ([i915#262]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9839/fi-cfl-8109u/igt@gem_exec_susp...@basic-s0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/fi-cfl-8109u/igt@gem_exec_susp...@basic-s0.html Warnings * igt@i915_pm_rpm@basic-rte: - fi-kbl-guc: [SKIP][7] ([fdo#109271]) -> [FAIL][8] ([i915#3049]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9839/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/fi-kbl-guc/igt@i915_pm_...@basic-rte.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#3049]: https://gitlab.freedesktop.org/drm/intel/issues/3049 [i915#3145]: https://gitlab.freedesktop.org/drm/intel/issues/3145 Participating hosts (46 -> 40) -- Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-bsw-cyan fi-icl-y fi-bdw-samus Build changes - * Linux: CI_DRM_9839 -> Patchwork_19767 CI-20190529: 20190529 CI_DRM_9839: 48d42dbb43fcd337539456172de1accfc8c7f78f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6026: 8b8bbecf2f32298544c2f193753a0153f39e7326 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19767: 5fb3de906bba02b4fba746ced8f9ddd0a65acf7b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5fb3de906bba gpu: drm: i915: fix error return code of igt_buddy_alloc_smoke() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19767/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 8/8] drm/i915: rename i915_rev_steppings->intel_step_info
Matter of taste. Match the prefix for everything else related to
steppings. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
drivers/gpu/drm/i915/intel_step.c| 12 ++--
drivers/gpu/drm/i915/intel_step.h| 2 +-
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index f84569e8e711..1bcae2a8c79b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -228,7 +228,7 @@ struct intel_runtime_info {
u32 rawclk_freq;
- struct i915_rev_steppings step;
+ struct intel_step_info step;
};
struct intel_driver_caps {
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 9df2dd264841..914a5de4346e 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -15,7 +15,7 @@
/* FIXME: what about REVID_E0 */
-static const struct i915_rev_steppings kbl_revids[] = {
+static const struct intel_step_info kbl_revids[] = {
[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
[1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
[2] = { .gt_step = STEP_C0, .display_step = STEP_B0 },
@@ -26,7 +26,7 @@ static const struct i915_rev_steppings kbl_revids[] = {
[7] = { .gt_step = STEP_G0, .display_step = STEP_C0 },
};
-static const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
+static const struct intel_step_info tgl_uy_revid_step_tbl[] = {
[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
[1] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
[2] = { .gt_step = STEP_B1, .display_step = STEP_C0 },
@@ -34,12 +34,12 @@ static const struct i915_rev_steppings
tgl_uy_revid_step_tbl[] = {
};
/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same
HW */
-static const struct i915_rev_steppings tgl_revid_step_tbl[] = {
+static const struct intel_step_info tgl_revid_step_tbl[] = {
[0] = { .gt_step = STEP_A0, .display_step = STEP_B0 },
[1] = { .gt_step = STEP_B0, .display_step = STEP_D0 },
};
-static const struct i915_rev_steppings adls_revid_step_tbl[] = {
+static const struct intel_step_info adls_revid_step_tbl[] = {
[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
[0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 },
[0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
@@ -49,10 +49,10 @@ static const struct i915_rev_steppings
adls_revid_step_tbl[] = {
void intel_step_init(struct drm_i915_private *i915)
{
- const struct i915_rev_steppings *revids = NULL;
+ const struct intel_step_info *revids = NULL;
int size = 0;
int revid = INTEL_REVID(i915);
- struct i915_rev_steppings step = {};
+ struct intel_step_info step = {};
if (IS_ALDERLAKE_S(i915)) {
revids = adls_revid_step_tbl;
diff --git a/drivers/gpu/drm/i915/intel_step.h
b/drivers/gpu/drm/i915/intel_step.h
index 102fd6a26893..958a8bb5d677 100644
--- a/drivers/gpu/drm/i915/intel_step.h
+++ b/drivers/gpu/drm/i915/intel_step.h
@@ -10,7 +10,7 @@
struct drm_i915_private;
-struct i915_rev_steppings {
+struct intel_step_info {
u8 gt_step;
u8 display_step;
};
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 7/8] drm/i915: rename disp_stepping->display_step and gt_stepping->gt_step
Matter of taste. Step matches the enums.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 4 +--
drivers/gpu/drm/i915/intel_step.c | 48 +++
drivers/gpu/drm/i915/intel_step.h | 4 +--
3 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 50f6f957c5db..ea82d93df7b8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1274,8 +1274,8 @@ static inline struct drm_i915_private
*pdev_to_i915(struct pci_dev *pdev)
#define IS_REVID(p, since, until) \
(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
-#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.disp_stepping)
-#define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_stepping)
+#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
+#define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step)
#define IS_DISPLAY_STEP(__i915, since, until) \
(drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 4593eba24a7d..9df2dd264841 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -16,35 +16,35 @@
/* FIXME: what about REVID_E0 */
static const struct i915_rev_steppings kbl_revids[] = {
- [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
- [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 },
- [2] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 },
- [3] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_B0 },
- [4] = { .gt_stepping = STEP_F0, .disp_stepping = STEP_C0 },
- [5] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B1 },
- [6] = { .gt_stepping = STEP_D1, .disp_stepping = STEP_B1 },
- [7] = { .gt_stepping = STEP_G0, .disp_stepping = STEP_C0 },
+ [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
+ [1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
+ [2] = { .gt_step = STEP_C0, .display_step = STEP_B0 },
+ [3] = { .gt_step = STEP_D0, .display_step = STEP_B0 },
+ [4] = { .gt_step = STEP_F0, .display_step = STEP_C0 },
+ [5] = { .gt_step = STEP_C0, .display_step = STEP_B1 },
+ [6] = { .gt_step = STEP_D1, .display_step = STEP_B1 },
+ [7] = { .gt_step = STEP_G0, .display_step = STEP_C0 },
};
static const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
- [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
- [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
- [2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
- [3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 },
+ [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
+ [1] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
+ [2] = { .gt_step = STEP_B1, .display_step = STEP_C0 },
+ [3] = { .gt_step = STEP_C0, .display_step = STEP_D0 },
};
/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same
HW */
static const struct i915_rev_steppings tgl_revid_step_tbl[] = {
- [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 },
- [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
+ [0] = { .gt_step = STEP_A0, .display_step = STEP_B0 },
+ [1] = { .gt_step = STEP_B0, .display_step = STEP_D0 },
};
static const struct i915_rev_steppings adls_revid_step_tbl[] = {
- [0x0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
- [0x1] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 },
- [0x4] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 },
- [0x8] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 },
- [0xC] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 },
+ [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
+ [0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 },
+ [0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
+ [0x8] = { .gt_step = STEP_C0, .display_step = STEP_B0 },
+ [0xC] = { .gt_step = STEP_D0, .display_step = STEP_C0 },
};
void intel_step_init(struct drm_i915_private *i915)
@@ -72,7 +72,7 @@ void intel_step_init(struct drm_i915_private *i915)
if (!revids)
return;
- if (revid < size && revids[revid].gt_stepping != STEP_NONE) {
+ if (revid < size && revids[revid].gt_step != STEP_NONE) {
step = revids[revid];
} else {
drm_dbg(&i915->drm, "Unknown revid 0x%02x\n", revid);
@@ -85,7 +85,7 @@ void intel_step_init(struct drm_i915_private *i915)
* steppings in the array are not monotonically increasing, but
* it's better than defaulting to 0.
*/
- while (revid < size && revids[revid].gt_stepping == STEP_NONE)
+ whil
[Intel-gfx] [PATCH v3 6/8] drm/i915: rename DISP_STEPPING->DISPLAY_STEP and GT_STEPPING->GT_STEP
Matter of taste. STEP matches the enums.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c| 10 +-
drivers/gpu/drm/i915/i915_drv.h| 10 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c| 2 +-
7 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7e0eaa872350..b1feec8e7081 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5333,7 +5333,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private
*dev_priv)
if (IS_ALDERLAKE_S(dev_priv) ||
IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
- IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
+ IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
/* Wa_1409767108:tgl,dg1,adl-s */
table = wa_1409767108_buddy_page_masks;
else
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index cd434285e3b7..71d084fdf26c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -548,7 +548,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
if (intel_dp->psr.psr2_sel_fetch_enabled) {
/* WA 1408330847 */
- if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
+ if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK,
@@ -1110,7 +1110,7 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
/* WA 1408330847 */
if (intel_dp->psr.psr2_sel_fetch_enabled &&
- (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) ||
+ (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 1f335cb09149..c4edfc673d47 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1858,7 +1858,7 @@ static bool gen12_plane_supports_mc_ccs(struct
drm_i915_private *dev_priv,
{
/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
- IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0))
+ IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
return false;
return plane_id < PLANE_SPRITE4;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 0c502a733779..4f8f9fbf6619 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1091,19 +1091,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
gen12_gt_workarounds_init(i915, wal);
/* Wa_1409420604:tgl */
- if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
+ if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
wa_write_or(wal,
SUBSLICE_UNIT_LEVEL_CLKGATE2,
CPSSUNIT_CLKGATE_DIS);
/* Wa_1607087056:tgl also know as BUG:1409180338 */
- if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
+ if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
wa_write_or(wal,
SLICE_UNIT_LEVEL_CLKGATE,
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
/* Wa_1408615072:tgl[a0] */
- if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0))
+ if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0))
wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
VSUNIT_CLKGATE_DIS_TGL);
}
@@ -1581,7 +1581,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
struct drm_i915_private *i915 = engine->i915;
if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
- IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) {
+ IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
/*
* Wa_1607138336:tgl[a0],dg1[a0]
* Wa_1607063988:tgl[a0],dg1[a0]
@@ -1591,7 +1591,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engin
[Intel-gfx] [PATCH v3 5/8] drm/i915: switch TGL and ADL to the new stepping scheme
This changes the way revids not present in the array are handled:
- For gaps in the array, the next present revid is used.
- For revids beyond the array, the new STEP_FUTURE is used instead of
the last revid in the array.
In both cases, we'll get debug logging of what's going on.
v2: Rename stepping->step
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 59 ---
drivers/gpu/drm/i915/intel_step.c | 17 ++---
drivers/gpu/drm/i915/intel_step.h | 8 -
3 files changed, 28 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7f259aab4226..991318e90b5a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1510,44 +1510,17 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_JSL_EHL_REVID(p, since, until) \
(IS_JSL_EHL(p) && IS_REVID(p, since, until))
-static inline const struct i915_rev_steppings *
-tgl_stepping_get(struct drm_i915_private *dev_priv)
-{
- u8 revid = INTEL_REVID(dev_priv);
- u8 size;
- const struct i915_rev_steppings *revid_step_tbl;
-
- if (IS_ALDERLAKE_S(dev_priv)) {
- revid_step_tbl = adls_revid_step_tbl;
- size = ARRAY_SIZE(adls_revid_step_tbl);
- } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
- revid_step_tbl = tgl_uy_revid_step_tbl;
- size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
- } else {
- revid_step_tbl = tgl_revid_step_tbl;
- size = ARRAY_SIZE(tgl_revid_step_tbl);
- }
-
- revid = min_t(u8, revid, size - 1);
-
- return &revid_step_tbl[revid];
-}
-
-#define IS_TGL_DISP_STEPPING(p, since, until) \
- (IS_TIGERLAKE(p) && \
-tgl_stepping_get(p)->disp_stepping >= (since) && \
-tgl_stepping_get(p)->disp_stepping <= (until))
+#define IS_TGL_DISP_STEPPING(__i915, since, until) \
+ (IS_TIGERLAKE(__i915) && \
+IS_DISPLAY_STEP(__i915, since, until))
-#define IS_TGL_UY_GT_STEPPING(p, since, until) \
- ((IS_TGL_U(p) || IS_TGL_Y(p)) && \
-tgl_stepping_get(p)->gt_stepping >= (since) && \
-tgl_stepping_get(p)->gt_stepping <= (until))
+#define IS_TGL_UY_GT_STEPPING(__i915, since, until) \
+ ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
+IS_GT_STEP(__i915, since, until))
-#define IS_TGL_GT_STEPPING(p, since, until) \
- (IS_TIGERLAKE(p) && \
-!(IS_TGL_U(p) || IS_TGL_Y(p)) && \
-tgl_stepping_get(p)->gt_stepping >= (since) && \
-tgl_stepping_get(p)->gt_stepping <= (until))
+#define IS_TGL_GT_STEPPING(__i915, since, until) \
+ (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
+IS_GT_STEP(__i915, since, until))
#define RKL_REVID_A0 0x0
#define RKL_REVID_B0 0x1
@@ -1562,15 +1535,13 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
#define IS_DG1_REVID(p, since, until) \
(IS_DG1(p) && IS_REVID(p, since, until))
-#define IS_ADLS_DISP_STEPPING(p, since, until) \
- (IS_ALDERLAKE_S(p) && \
-tgl_stepping_get(p)->disp_stepping >= (since) && \
-tgl_stepping_get(p)->disp_stepping <= (until))
+#define IS_ADLS_DISP_STEPPING(__i915, since, until) \
+ (IS_ALDERLAKE_S(__i915) && \
+IS_DISPLAY_STEP(__i915, since, until))
-#define IS_ADLS_GT_STEPPING(p, since, until) \
- (IS_ALDERLAKE_S(p) && \
-tgl_stepping_get(p)->gt_stepping >= (since) && \
-tgl_stepping_get(p)->gt_stepping <= (until))
+#define IS_ADLS_GT_STEPPING(__i915, since, until) \
+ (IS_ALDERLAKE_S(__i915) && \
+IS_GT_STEP(__i915, since, until))
#define IS_LP(dev_priv)(INTEL_INFO(dev_priv)->is_lp)
#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index aaa9494b0f4f..4593eba24a7d 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -26,7 +26,7 @@ static const struct i915_rev_steppings kbl_revids[] = {
[7] = { .gt_stepping = STEP_G0, .disp_stepping = STEP_C0 },
};
-const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
+static const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
[2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
@@ -34,12 +34,12 @@ const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
};
/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same
HW */
-const struct i915_rev_steppings tgl_revid_step_tbl[] = {
+static const struct i915_rev_steppings tgl_revid_step_tbl[] = {
[0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 },
[1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
};
-const struct i915_re
[Intel-gfx] [PATCH v3 4/8] drm/i915: switch KBL to the new stepping scheme
Add new symbolic names for revision ids, and convert KBL revids to use
them via the new stepping check macros.
This also fixes theoretical out of bounds access to kbl_revids array.
v2: Rename stepping->step
Signed-off-by: Jani Nikula
---
The initialization sounds like an early part of
intel_device_info_runtime_init(), and indeed touches runtime info.
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c| 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +-
drivers/gpu/drm/i915/i915_drv.c | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 24 ++-
drivers/gpu/drm/i915/intel_pm.c | 4 +-
drivers/gpu/drm/i915/intel_step.c | 69 ++---
drivers/gpu/drm/i915/intel_step.h | 11 +++-
7 files changed, 82 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index cac80af7ad1c..74e8acc72da0 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -42,7 +42,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
vf_flush_wa = true;
/* WaForGAMHang:kbl */
- if (IS_KBL_GT_REVID(rq->engine->i915, 0, KBL_REVID_B0))
+ if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_B0))
dc_flush_wa = true;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2827d4f2e086..0c502a733779 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -481,7 +481,7 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs
*engine,
gen9_ctx_workarounds_init(engine, wal);
/* WaToEnableHwFixForPushConstHWBug:kbl */
- if (IS_KBL_GT_REVID(i915, KBL_REVID_C0, REVID_FOREVER))
+ if (IS_KBL_GT_STEP(i915, STEP_C0, STEP_FOREVER))
wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
@@ -899,7 +899,7 @@ kbl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
gen9_gt_workarounds_init(i915, wal);
/* WaDisableDynamicCreditSharing:kbl */
- if (IS_KBL_GT_REVID(i915, 0, KBL_REVID_B0))
+ if (IS_KBL_GT_STEP(i915, 0, STEP_B0))
wa_write_or(wal,
GAMT_CHKN_BIT_REG,
GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
@@ -2020,7 +2020,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
struct drm_i915_private *i915 = engine->i915;
/* WaKBLVECSSemaphoreWaitPoll:kbl */
- if (IS_KBL_GT_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) {
+ if (IS_KBL_GT_STEP(i915, STEP_A0, STEP_E0)) {
wa_write(wal,
RING_SEMA_WAIT_POLL(engine->mmio_base),
1);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3edd5e47ad68..83214ffe6cf1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -273,7 +273,7 @@ static void intel_detect_preproduction_hw(struct
drm_i915_private *dev_priv)
pre |= IS_HSW_EARLY_SDV(dev_priv);
pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
- pre |= IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_A0);
+ pre |= IS_KBL_GT_STEP(dev_priv, 0, STEP_A0);
pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
if (pre) {
@@ -307,6 +307,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
return -ENODEV;
intel_device_info_subplatform_init(dev_priv);
+ intel_step_init(dev_priv);
intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
intel_uncore_init_early(&dev_priv->uncore, dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a543b1ad9ba9..7f259aab4226 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1475,26 +1475,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_BXT_REVID(dev_priv, since, until) \
(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
-enum {
- KBL_REVID_A0,
- KBL_REVID_B0,
- KBL_REVID_B1,
- KBL_REVID_C0,
- KBL_REVID_D0,
- KBL_REVID_D1,
- KBL_REVID_E0,
- KBL_REVID_F0,
- KBL_REVID_G0,
-};
-
-#define IS_KBL_GT_REVID(dev_priv, since, until) \
- (IS_KABYLAKE(dev_priv) && \
-kbl_revids[INTEL_REVID(dev_priv)].gt_stepping >= since && \
-kbl_revids[INTEL_REVID(dev_priv)].gt_stepping <= until)
-#define IS_KBL_DISP_REVID(dev_priv, since, until) \
- (IS_KABYLAKE(dev_priv) && \
-kbl_revids[INTEL_REVID(dev_priv)].disp_stepping >= since && \
-kbl_revids[INTEL_REVID(dev_priv)].disp_steppi
[Intel-gfx] [PATCH v3 3/8] drm/i915: add new helpers for accessing stepping info
Add new runtime info field for stepping. Add new helpers for accessing
them. As we'll be switching platforms over to the new scheme
incrementally, check for non-initialized steppings.
In case a platform does not have separate display and gt steppings, it's
okay to use a common shorthand. However, in this case the display
stepping must not be initialized, and gt stepping is the single point of
truth.
v2: Rename stepping->step
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 24 +++-
drivers/gpu/drm/i915/intel_device_info.h | 4
drivers/gpu/drm/i915/intel_step.h| 14 ++
3 files changed, 33 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 02170edd6628..a543b1ad9ba9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1274,6 +1274,21 @@ static inline struct drm_i915_private
*pdev_to_i915(struct pci_dev *pdev)
#define IS_REVID(p, since, until) \
(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
+#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.disp_stepping)
+#define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_stepping)
+
+#define IS_DISPLAY_STEP(__i915, since, until) \
+ (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
+INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <=
(until))
+
+#define IS_GT_STEP(__i915, since, until) \
+ (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \
+INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) <= (until))
+
+#define IS_STEP(p, since, until) \
+ (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) != STEP_NONE), \
+INTEL_GT_STEP(__i915, since, until))
+
static __always_inline unsigned int
__platform_mask_index(const struct intel_runtime_info *info,
enum intel_platform p)
@@ -1511,15 +1526,6 @@ enum {
#define IS_JSL_EHL_REVID(p, since, until) \
(IS_JSL_EHL(p) && IS_REVID(p, since, until))
-enum {
- STEP_A0,
- STEP_A2,
- STEP_B0,
- STEP_B1,
- STEP_C0,
- STEP_D0,
-};
-
static inline const struct i915_rev_steppings *
tgl_stepping_get(struct drm_i915_private *dev_priv)
{
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index d44f64b57b7a..f84569e8e711 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -27,6 +27,8 @@
#include
+#include "intel_step.h"
+
#include "display/intel_display.h"
#include "gt/intel_engine_types.h"
@@ -225,6 +227,8 @@ struct intel_runtime_info {
u8 num_scalers[I915_MAX_PIPES];
u32 rawclk_freq;
+
+ struct i915_rev_steppings step;
};
struct intel_driver_caps {
diff --git a/drivers/gpu/drm/i915/intel_step.h
b/drivers/gpu/drm/i915/intel_step.h
index af922ae3bb4e..8b3ef19d935b 100644
--- a/drivers/gpu/drm/i915/intel_step.h
+++ b/drivers/gpu/drm/i915/intel_step.h
@@ -22,4 +22,18 @@ extern const struct i915_rev_steppings
tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_T
extern const struct i915_rev_steppings
tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
extern const struct i915_rev_steppings
adls_revid_step_tbl[ADLS_REVID_STEP_TBL_SIZE];
+/*
+ * Symbolic steppings that do not match the hardware. These are valid both as
gt
+ * and display steppings as symbolic names.
+ */
+enum intel_step {
+ STEP_NONE = 0,
+ STEP_A0,
+ STEP_A2,
+ STEP_B0,
+ STEP_B1,
+ STEP_C0,
+ STEP_D0,
+};
+
#endif /* __INTEL_STEP_H__ */
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/8] drm/i915: split out stepping info to a new file
gt/intel_workarounds.c is decidedly the wrong place for handling
stepping info. Add new intel_step.[ch] for the data, and move the
stepping arrays there. No functional changes.
v2: Rename stepping->step
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 -
drivers/gpu/drm/i915/i915_drv.h | 19 +
drivers/gpu/drm/i915/intel_step.c | 46 +
drivers/gpu/drm/i915/intel_step.h | 25 +++
5 files changed, 74 insertions(+), 56 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_step.c
create mode 100644 drivers/gpu/drm/i915/intel_step.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index bc6138880c67..a9fb426d5e41 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -53,6 +53,7 @@ i915-y += i915_config.o \
intel_pm.o \
intel_runtime_pm.o \
intel_sideband.o \
+ intel_step.o \
intel_uncore.o \
intel_wakeref.o \
vlv_suspend.o
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3b4a7da60f0b..2827d4f2e086 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -52,45 +52,6 @@
* - Public functions to init or apply the given workaround type.
*/
-/*
- * KBL revision ID ordering is bizarre; higher revision ID's map to lower
- * steppings in some cases. So rather than test against the revision ID
- * directly, let's map that into our own range of increasing ID's that we
- * can test against in a regular manner.
- */
-
-const struct i915_rev_steppings kbl_revids[] = {
- [0] = { .gt_stepping = KBL_REVID_A0, .disp_stepping = KBL_REVID_A0 },
- [1] = { .gt_stepping = KBL_REVID_B0, .disp_stepping = KBL_REVID_B0 },
- [2] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B0 },
- [3] = { .gt_stepping = KBL_REVID_D0, .disp_stepping = KBL_REVID_B0 },
- [4] = { .gt_stepping = KBL_REVID_F0, .disp_stepping = KBL_REVID_C0 },
- [5] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B1 },
- [6] = { .gt_stepping = KBL_REVID_D1, .disp_stepping = KBL_REVID_B1 },
- [7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 },
-};
-
-const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = {
- [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
- [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 },
- [2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 },
- [3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 },
-};
-
-/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same
HW */
-const struct i915_rev_steppings tgl_revid_step_tbl[] = {
- [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 },
- [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 },
-};
-
-const struct i915_rev_steppings adls_revid_step_tbl[] = {
- [0x0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 },
- [0x1] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 },
- [0x4] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 },
- [0x8] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 },
- [0xC] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 },
-};
-
static void wa_init_start(struct i915_wa_list *wal, const char *name, const
char *engine_name)
{
wal->name = name;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2f511bf2bd82..02170edd6628 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -86,9 +86,10 @@
#include "gt/uc/intel_uc.h"
#include "intel_device_info.h"
+#include "intel_memory_region.h"
#include "intel_pch.h"
#include "intel_runtime_pm.h"
-#include "intel_memory_region.h"
+#include "intel_step.h"
#include "intel_uncore.h"
#include "intel_wakeref.h"
#include "intel_wopcm.h"
@@ -1471,14 +1472,6 @@ enum {
KBL_REVID_G0,
};
-struct i915_rev_steppings {
- u8 gt_stepping;
- u8 disp_stepping;
-};
-
-/* Defined in intel_workarounds.c */
-extern const struct i915_rev_steppings kbl_revids[];
-
#define IS_KBL_GT_REVID(dev_priv, since, until) \
(IS_KABYLAKE(dev_priv) && \
kbl_revids[INTEL_REVID(dev_priv)].gt_stepping >= since && \
@@ -1527,14 +1520,6 @@ enum {
STEP_D0,
};
-#define TGL_UY_REVID_STEP_TBL_SIZE 4
-#define TGL_REVID_STEP_TBL_SIZE2
-#define ADLS_REVID_STEP_TBL_SIZE 13
-
-extern const struct i915_rev_steppings
tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE];
-extern const struct i915_rev_steppings
tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE];
-extern const struct i915_rev_steppings
adls_revid_step_tbl[ADLS_REVID_STEP_TBL_SIZE];
-
static inline const struct i915_rev_steppings *
tgl
[Intel-gfx] [PATCH v3 1/8] drm/i915: remove unused ADLS_REVID_* macros
It's the adls_revid_step_tbl array indexes that matter. Reviewed-by: Lucas De Marchi Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 6 -- 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1d45d7492d10..2f511bf2bd82 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1587,12 +1587,6 @@ tgl_stepping_get(struct drm_i915_private *dev_priv) #define IS_DG1_REVID(p, since, until) \ (IS_DG1(p) && IS_REVID(p, since, until)) -#define ADLS_REVID_A0 0x0 -#define ADLS_REVID_A2 0x1 -#define ADLS_REVID_B0 0x4 -#define ADLS_REVID_G0 0x8 -#define ADLS_REVID_C0 0xC /*Same as H0 ADLS SOC stepping*/ - #define IS_ADLS_DISP_STEPPING(p, since, until) \ (IS_ALDERLAKE_S(p) && \ tgl_stepping_get(p)->disp_stepping >= (since) && \ -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 0/8] drm/i915: refactor KBL/TGL/ADLS stepping scheme
v3 of [1], mostly with just stepping->step renames BR, Jani. [1] https://patchwork.freedesktop.org/series/87323/ Jani Nikula (8): drm/i915: remove unused ADLS_REVID_* macros drm/i915: split out stepping info to a new file drm/i915: add new helpers for accessing stepping info drm/i915: switch KBL to the new stepping scheme drm/i915: switch TGL and ADL to the new stepping scheme drm/i915: rename DISP_STEPPING->DISPLAY_STEP and GT_STEPPING->GT_STEP drm/i915: rename disp_stepping->display_step and gt_stepping->gt_step drm/i915: rename i915_rev_steppings->intel_step_info drivers/gpu/drm/i915/Makefile | 1 + .../drm/i915/display/intel_display_power.c| 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 4 +- .../drm/i915/display/skl_universal_plane.c| 2 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 55 ++- drivers/gpu/drm/i915/i915_drv.c | 3 +- drivers/gpu/drm/i915/i915_drv.h | 134 +- drivers/gpu/drm/i915/intel_device_info.c | 2 +- drivers/gpu/drm/i915/intel_device_info.h | 4 + drivers/gpu/drm/i915/intel_pm.c | 6 +- drivers/gpu/drm/i915/intel_step.c | 106 ++ drivers/gpu/drm/i915/intel_step.h | 40 ++ 13 files changed, 207 insertions(+), 154 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_step.c create mode 100644 drivers/gpu/drm/i915/intel_step.h -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for gpu: drm: i915: fix error return code of igt_threaded_blt()
== Series Details ==
Series: gpu: drm: i915: fix error return code of igt_threaded_blt()
URL : https://patchwork.freedesktop.org/series/87765/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9838 -> Patchwork_19766
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_19766 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19766, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19766/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_19766:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@execlists:
- fi-cfl-8109u: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9838/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19766/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
Known issues
Here are the changes found in Patchwork_19766 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_gttfill@basic:
- fi-kbl-8809g: [PASS][3] -> [TIMEOUT][4] ([i915#3145]) +1 similar
issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9838/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19766/fi-kbl-8809g/igt@gem_exec_gttf...@basic.html
* igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u: [PASS][5] -> [DMESG-WARN][6] ([i915#203]) +2 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9838/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19766/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
Possible fixes
* igt@gem_linear_blits@basic:
- fi-kbl-8809g: [TIMEOUT][7] ([i915#2502] / [i915#3145]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9838/fi-kbl-8809g/igt@gem_linear_bl...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19766/fi-kbl-8809g/igt@gem_linear_bl...@basic.html
* igt@gem_tiled_blits@basic:
- fi-kbl-8809g: [TIMEOUT][9] ([i915#3145]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9838/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19766/fi-kbl-8809g/igt@gem_tiled_bl...@basic.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-rkl-11500t}:[SKIP][11] -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9838/fi-rkl-11500t/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19766/fi-rkl-11500t/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- {fi-tgl-dsi}: [DMESG-WARN][13] ([i915#402]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9838/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19766/fi-tgl-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
Warnings
* igt@i915_pm_rpm@module-reload:
- fi-glk-dsi: [DMESG-WARN][15] ([i915#3143]) -> [DMESG-WARN][16]
([i915#1982] / [i915#3143])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9838/fi-glk-dsi/igt@i915_pm_...@module-reload.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19766/fi-glk-dsi/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
[i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502
[i915#3143]: https://gitlab.freedesktop.org/drm/intel/issues/3143
[i915#3145]: https://gitlab.freedesktop.org/drm/intel/issues/3145
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (46 -> 41)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-icl-y fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9838 -> Patchwork_19766
CI-20190529: 20190529
CI_DRM_9838: 18041d32fb75fb42a0b6c8d26529dba5cf4afcf6 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6024: d8e03fe437f0c328c96717a92ad97719c02ba2cd @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19766: 8423b9a9d94492cde592a40efa26d79848bbceaa @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux
Re: [Intel-gfx] [PATCH 6/6] drm/i915: Extend icl_sanitize_encoder_pll_mapping() to all DDI platforms
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, February 24, 2021 4:42 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 6/6] drm/i915: Extend
> icl_sanitize_encoder_pll_mapping() to all DDI platforms
>
> From: Ville Syrjälä
>
> Now that all the encoder clock stuff is uniformly abstracted for all hsw+
> platforms, let's extend icl_sanitize_encoder_pll_mapping()
> to cover all of them.
>
> Not sure there is a particular benefit in doing so, but less special cases
> always
> makes me happy.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_ddi.h | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> 3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 7d477c4007c7..dd2203f87078 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2134,7 +2134,7 @@ static void intel_ddi_disable_clock(struct
> intel_encoder *encoder)
> encoder->disable_clock(encoder);
> }
>
> -void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
> +void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder
> +*encoder)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> u32 port_mask;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
> b/drivers/gpu/drm/i915/display/intel_ddi.h
> index 99cebbe6b586..59c6b01d4199 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -66,6 +66,6 @@ u32 ddi_signal_levels(struct intel_dp *intel_dp, int
> intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> enum transcoder cpu_transcoder,
> bool enable, u32 hdcp_mask);
> -void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
> +void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder
> +*encoder);
>
> #endif /* __INTEL_DDI_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8b5cb814b679..87db5331176b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13144,8 +13144,8 @@ static void intel_sanitize_encoder(struct
> intel_encoder *encoder)
> /* notify opregion of the sanitized encoder state */
> intel_opregion_notify_encoder(encoder, connector &&
> has_active_crtc);
>
> - if (INTEL_GEN(dev_priv) >= 11)
> - icl_sanitize_encoder_pll_mapping(encoder);
> + if (HAS_DDI(dev_priv))
> + intel_ddi_sanitize_encoder_pll_mapping(encoder);
> }
>
> /* FIXME read out full plane state for all planes */
> --
> 2.26.2
>
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Re: [Intel-gfx] [PATCH 5/6] drm/i915: Add encoder->is_clock_enabled()
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, February 24, 2021 4:42 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Add encoder->is_clock_enabled()
>
> From: Ville Syrjälä
>
> Support reading out the current state of the DDI clock.
>
> Not sure we really want this. Seems a bit excessive just to restore the debug
> print to icl_sanitize_encoder_pll_mapping()?
> But maybe there's more use for it?
>
> Signed-off-by: Ville Syrjälä
I guess there is no harm done if we have the state of the DDI clock in store.
Reviewed-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c| 19 +++
> drivers/gpu/drm/i915/display/intel_crt.c | 1 +
> drivers/gpu/drm/i915/display/intel_ddi.c | 123 +-
> drivers/gpu/drm/i915/display/intel_ddi.h | 1 +
> .../drm/i915/display/intel_display_types.h| 4 +
> 5 files changed, 146 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 29fe4919392a..7f2abc088a66 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -655,6 +655,24 @@ static void gen11_dsi_ungate_clocks(struct
> intel_encoder *encoder)
> mutex_unlock(&dev_priv->dpll.lock);
> }
>
> +static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> + bool clock_enabled = false;
> + enum phy phy;
> + u32 tmp;
> +
> + tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> +
> + for_each_dsi_phy(phy, intel_dsi->phys) {
> + if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))
> + clock_enabled = true;
> + }
> +
> + return clock_enabled;
> +}
> +
> static void gen11_dsi_map_pll(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) { @@ -
> 1939,6 +1957,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> encoder->power_domain = POWER_DOMAIN_PORT_DSI;
> encoder->get_power_domains = gen11_dsi_get_power_domains;
> encoder->disable_clock = gen11_dsi_gate_clocks;
> + encoder->is_clock_enabled = gen11_dsi_is_clock_enabled;
>
> /* register DSI connector with DRM subsystem */
> drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index b03f74076f64..7f3d11c5ce3e 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -1078,6 +1078,7 @@ void intel_crt_init(struct drm_i915_private
> *dev_priv)
> crt->base.post_disable = hsw_post_disable_crt;
> crt->base.enable_clock = hsw_ddi_enable_clock;
> crt->base.disable_clock = hsw_ddi_disable_clock;
> + crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;
> } else {
> if (HAS_PCH_SPLIT(dev_priv)) {
> crt->base.compute_config =
> pch_crt_compute_config; diff --git
> a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 56f5f55a7c8f..7d477c4007c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1589,6 +1589,12 @@ static void _cnl_ddi_disable_clock(struct
> drm_i915_private *i915, i915_reg_t reg
> mutex_unlock(&i915->dpll.lock);
> }
>
> +static bool _cnl_ddi_is_clock_enabled(struct drm_i915_private *i915,
> i915_reg_t reg,
> + u32 clk_off)
> +{
> + return !(intel_de_read(i915, reg) & clk_off); }
> +
> static struct intel_shared_dpll *
> _cnl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
>u32 clk_sel_mask, u32 clk_sel_shift) @@ -1625,6 +1631,15
> @@ static void adls_ddi_disable_clock(struct intel_encoder *encoder)
> ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> +static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + return _cnl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
> +
> ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> +}
> +
> static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder
> *encoder) {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev); @@ -
> 1660,6 +1675,15 @@ static void rkl_ddi_disable_clock(struct intel_encoder
> *encoder)
> RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> }
>
> +static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum ph
Re: [Intel-gfx] [PATCH 4/6] drm/i915: Move DDI clock readout to encoder->get_config()
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, February 24, 2021 4:42 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Move DDI clock readout to
> encoder->get_config()
>
> From: Ville Syrjälä
>
> Move the *_get_ddi_pll() stuff into the encodet->get_config() hook.
> There it neatly sits next to the matching .{enable,disable}_clock() functions.
>
> In order to avoid excessive boilerplate I changed the behaviour such that all
> platforms now do the readout via crtc_state->port_dpll[].
>
> ICL+ TC is still a bit special due to TBTPLL not having a functional
> .get_freq(). Should probably change that by adopting the LCPLL approach,
> but that would require a fairly substantial rework of the DPLL ID handling. So
> leave it for later.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 6 +-
> drivers/gpu/drm/i915/display/intel_crt.c | 2 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 321 +--
> drivers/gpu/drm/i915/display/intel_ddi.h | 8 +-
> drivers/gpu/drm/i915/display/intel_display.c | 219 -
> 5 files changed, 306 insertions(+), 250 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 05d5709ae537..29fe4919392a 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1490,14 +1490,10 @@ static void
> gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, static void
> gen11_dsi_get_config(struct intel_encoder *encoder,
>struct intel_crtc_state *pipe_config) {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
>
> - /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> - pipe_config->port_clock = intel_dpll_get_freq(i915,
> - pipe_config->shared_dpll,
> - &pipe_config-
> >dpll_hw_state);
> + intel_ddi_get_clock(encoder, pipe_config,
> +icl_ddi_combo_get_pll(encoder));
>
> pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
> if (intel_dsi->dual_link)
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index 91a8a42b4aa2..b03f74076f64 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -142,7 +142,7 @@ static void hsw_crt_get_config(struct intel_encoder
> *encoder, {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - intel_ddi_get_config(encoder, pipe_config);
> + hsw_ddi_get_config(encoder, pipe_config);
>
> pipe_config->hw.adjusted_mode.flags &=
> ~(DRM_MODE_FLAG_PHSYNC |
> DRM_MODE_FLAG_NHSYNC |
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index eeae78097a20..56f5f55a7c8f 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -304,25 +304,6 @@ static void ddi_dotclock_get(struct intel_crtc_state
> *pipe_config)
> pipe_config->hw.adjusted_mode.crtc_clock = dotclock; }
>
> -static void intel_ddi_clock_get(struct intel_encoder *encoder,
> - struct intel_crtc_state *pipe_config)
> -{
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> -
> - if (intel_phy_is_tc(dev_priv, phy) &&
> - intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) ==
> - DPLL_ID_ICL_TBTPLL)
> - pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
> - encoder-
> >port);
> - else
> - pipe_config->port_clock =
> - intel_dpll_get_freq(dev_priv, pipe_config-
> >shared_dpll,
> - &pipe_config->dpll_hw_state);
> -
> - ddi_dotclock_get(pipe_config);
> -}
> -
> void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state) {
> @@ -1608,6 +1589,17 @@ static void _cnl_ddi_disable_clock(struct
> drm_i915_private *i915, i915_reg_t reg
> mutex_unlock(&i915->dpll.lock);
> }
>
> +static struct intel_shared_dpll *
> +_cnl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
> + u32 clk_sel_mask, u32 clk_sel_shift) {
> + enum intel_dpll_id id;
> +
> + id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
> +
> + return intel_get_shared_dpll_by_id(i915, id); }
> +
> static vo
[Intel-gfx] [PATCH] gpu: drm: i915: fix error return code of igt_buddy_alloc_smoke()
When i915_random_order() returns NULL to order, no error return code of
igt_buddy_alloc_smoke() is assigned.
To fix this bug, err is assigned with -EINVAL in this case.
Fixes: 1fe3818d17c9 ("drm/i915/selftests: try to rein in alloc_smoke")
Reported-by: TOTE Robot
Signed-off-by: Jia-Ju Bai
---
drivers/gpu/drm/i915/selftests/i915_buddy.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_buddy.c
b/drivers/gpu/drm/i915/selftests/i915_buddy.c
index 632b912b0bc9..cf9b551b77e1 100644
--- a/drivers/gpu/drm/i915/selftests/i915_buddy.c
+++ b/drivers/gpu/drm/i915/selftests/i915_buddy.c
@@ -318,8 +318,10 @@ static int igt_buddy_alloc_smoke(void *arg)
}
order = i915_random_order(mm.max_order + 1, &prng);
- if (!order)
+ if (!order) {
+ err = -EINVAL;
goto out_fini;
+ }
for (i = 0; i <= mm.max_order; ++i) {
struct i915_buddy_block *block;
--
2.17.1
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Re: [Intel-gfx] [PATCH] gpu: drm: i915: fix error return code of igt_buddy_alloc_smoke()
On 2021/3/8 17:18, Chris Wilson wrote: Quoting Jia-Ju Bai (2021-03-08 08:59:52) When i915_random_order() returns NULL to order, no error return code of igt_buddy_alloc_smoke() is assigned. To fix this bug, err is assigned with -EINVAL in this case. It would not be EINVAL since that is used for a reference failure, but in this case the idea was to return 0 as no testing was done and the ENOMEM was raised before testing began i.e. not an internal and unexpected driver allocation failure. -Chris Okay, thanks for your reply :) Best wishes, Jia-Ju Bai ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] gpu: drm: i915: fix error return code of igt_threaded_blt()
When kcalloc() returns NULL to tsk or thread, no error code of
igt_threaded_blt() is returned.
To fix this bug, -ENOMEM is returned as error code.
Fixes: 0e99f939f08f ("drm/i915/selftests/blt: add some kthreads into the mix")
Reported-by: TOTE Robot
Signed-off-by: Jia-Ju Bai
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
index 23b6e11bbc3e..b54ba8a1fcec 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
@@ -471,11 +471,13 @@ static int igt_threaded_blt(struct intel_engine_cs
*engine,
tsk = kcalloc(n_cpus, sizeof(struct task_struct *), GFP_KERNEL);
if (!tsk)
- return 0;
+ return -ENOMEM;
thread = kcalloc(n_cpus, sizeof(struct igt_thread_arg), GFP_KERNEL);
- if (!thread)
+ if (!thread) {
+ err = -ENOMEM;
goto out_tsk;
+ }
thread[0].file = mock_file(engine->i915);
if (IS_ERR(thread[0].file)) {
--
2.17.1
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Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: Do intel_dpll_readout_hw_state() after encoder readout
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Thursday, February 25, 2021 6:12 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 2/6] drm/i915: Do
> intel_dpll_readout_hw_state() after encoder readout
>
> From: Ville Syrjälä
>
> The clock readout for DDI encoders needs to moved into the encoders.
> To that end intel_dpll_readout_hw_state() needs to happen after the
> encoder readout as otherwise it can't correctly populate the PLL
> crtc_mask/active_mask bitmasks.
>
> v2: Populate DPLL ref clocks before the encoder->get_config()
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 +++--
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 9 ++---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 +
> 3 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d0da88751c72..faf9507c9da2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12908,6 +12908,7 @@ int intel_modeset_init_nogem(struct
> drm_i915_private *i915)
>
> intel_update_czclk(i915);
> intel_modeset_init_hw(i915);
> + intel_dpll_update_ref_clks(i915);
>
> intel_hdcp_component_init(i915);
>
> @@ -13444,8 +13445,6 @@ static void
> intel_modeset_readout_hw_state(struct drm_device *dev)
>
> readout_plane_state(dev_priv);
>
> - intel_dpll_readout_hw_state(dev_priv);
> -
> for_each_intel_encoder(dev, encoder) {
> pipe = 0;
>
> @@ -13480,6 +13479,8 @@ static void
> intel_modeset_readout_hw_state(struct drm_device *dev)
> pipe_name(pipe));
> }
>
> + intel_dpll_readout_hw_state(dev_priv);
> +
> drm_connector_list_iter_begin(dev, &conn_iter);
> for_each_intel_connector_iter(connector, &conn_iter) {
> if (connector->get_hw_state(connector)) { diff --git
> a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 529b1d569af2..ac6460962e29 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4612,12 +4612,15 @@ static void readout_dpll_hw_state(struct
> drm_i915_private *i915,
> pll->info->name, pll->state.crtc_mask, pll->on); }
>
> -void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
> +void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
> {
> - int i;
> -
> if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks)
> i915->dpll.mgr->update_ref_clks(i915);
> +}
> +
> +void intel_dpll_readout_hw_state(struct drm_i915_private *i915) {
> + int i;
>
> for (i = 0; i < i915->dpll.num_shared_dpll; i++)
> readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 2eb7618ef957..81e67639dadb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -410,6 +410,7 @@ void intel_enable_shared_dpll(const struct
> intel_crtc_state *crtc_state); void intel_disable_shared_dpll(const struct
> intel_crtc_state *crtc_state); void intel_shared_dpll_swap_state(struct
> intel_atomic_state *state); void intel_shared_dpll_init(struct drm_device
> *dev);
> +void intel_dpll_update_ref_clks(struct drm_i915_private *dev_priv);
> void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv); void
> intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
>
> --
> 2.26.2
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH] gpu: drm: i915: fix error return code of igt_buddy_alloc_smoke()
Quoting Jia-Ju Bai (2021-03-08 08:59:52) > When i915_random_order() returns NULL to order, no error return code of > igt_buddy_alloc_smoke() is assigned. > To fix this bug, err is assigned with -EINVAL in this case. It would not be EINVAL since that is used for a reference failure, but in this case the idea was to return 0 as no testing was done and the ENOMEM was raised before testing began i.e. not an internal and unexpected driver allocation failure. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] gpu: drm: i915: fix error return code of igt_threaded_blt()
Quoting Jia-Ju Bai (2021-03-08 09:07:22) > When kcalloc() returns NULL to tsk or thread, no error code of > igt_threaded_blt() is returned. > To fix this bug, -ENOMEM is returned as error code. Because we decided to skip the test if it could not be run due to insufficient memory, as opposed to an internal allocation failure from the driver. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
