Re: [Intel-gfx] [PULL] drm-intel-gt-next
On Wed, 2 Jun 2021 at 14:17, Dave Airlie wrote: > > On Wed, 2 Jun 2021 at 10:28, Dave Airlie wrote: > > > > This has these two patches applied, and it doesn't build. > > > > drm/i915: drop the __i915_active_call pointer packing > > drm/i915: Fix crash in auto_retire > > > > The latter patch shouldn't be necessary after the former, please fix > > that up and resend and please build test trees before I get them in > > future. > > Oh maybe this is an unresolved conflict, not sure why drm-tip doesn't > catch this though, or is this next tree not in next? Oh looks like tip did catch it, I just didn't see it was done with a fixup. Dave. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PULL] drm-intel-gt-next
On Wed, 2 Jun 2021 at 10:28, Dave Airlie wrote: > > This has these two patches applied, and it doesn't build. > > drm/i915: drop the __i915_active_call pointer packing > drm/i915: Fix crash in auto_retire > > The latter patch shouldn't be necessary after the former, please fix > that up and resend and please build test trees before I get them in > future. Oh maybe this is an unresolved conflict, not sure why drm-tip doesn't catch this though, or is this next tree not in next? That would explain it then. I've pulled it with an fix in the merge commit. Dave. > > Dave. > > > On Fri, 28 May 2021 at 17:27, Joonas Lahtinen > wrote: > > > > Quoting Joonas Lahtinen (2021-05-28 10:25:57) > > > Hi Dave & Daniel, > > > > > > Here's drm-intel-gt-next pull request. > > > > > > Most notably it has the reworked DG1 uAPI (behind CONFIG_BROKEN) > > > as requested. Important fix for Gitlab issues #3293 and #3450 and > > > one another kernel crash. Adds missing workarounds for Gen11 and > > > Gen12. Hiding of modparams for compiled-out features. Conversion > > > to use trylock shrinking for BSW VT-d and BXT. > > > > > > Then there are the uAPI kerneldoc improvements as part of the DG1 > > > uAPI rework. Usual amount smaller fixes, code refactoring and > > > cleanups as prep for upcoming patches. > > > > And includes tag 'topic/intel-gen-to-ver-2021-04-19' (but that is > > already merged to drm-next). > > > > Regards, Joonas > > > > > Regards, Joonas > > > > > > *** > > > > > > drm-intel-gt-next-2021-05-28: > > > > > > UAPI Changes: > > > - Add reworked uAPI for DG1 behind CONFIG_BROKEN (Matt A, Abdiel) > > > > > > Driver Changes: > > > > > > - Fix for Gitlab issues #3293 and #3450: > > > Avoid kernel crash on older L-shape memory machines > > > > > > - Hide modparams for compiled-out features (Tvrtko) > > > - Add Wa_14010733141 (VDBox SFC reset) for Gen11+ (Aditya) > > > - Fix crash in auto_retire active retire callback due to > > > misalignment (Stephane) > > > - Use trylock in shrinker for GGTT on BSW VT-d and BXT (Maarten) > > > - Fix overlay active retire callback alignment (Tvrtko) > > > - Eliminate need to align active retire callbacks (Matt A, Ville, > > > Daniel) > > > - Program FF_MODE2 tuning value for all Gen12 platforms (Caz) > > > - Add Wa_14011060649 for TGL,RKL,DG1 and ADLS (Swathi) > > > - Create stolen memory region from local memory on DG1 (CQ) > > > - Place PD in LMEM on dGFX (Matt A) > > > - Use WC when default state object is allocated in LMEM (Venkata) > > > - Determine the coherent map type based on object location (Venkata) > > > - Use lmem physical addresses for fb_mmap() on discrete (Mohammed) > > > - Bypass aperture on fbdev when LMEM is available (Anusha) > > > - Return error value when displayable BO not in LMEM for dGFX (Mohammed) > > > - Do release kernel context if breadcrumb measure fails (Janusz) > > > - Apply Wa_22010271021 for all Gen11 platforms (Caz) > > > - Fix unlikely ref count race in arming the watchdog timer (Tvrtko) > > > - Check actual RC6 enable status in PMU (Tvrtko) > > > - Fix a double free in gen8_preallocate_top_level_pdp (Lv) > > > - Remove erroneous i915_is_ggtt check for > > > I915_GEM_OBJECT_UNBIND_VM_TRYLOCK (Maarten) > > > > > > - Convert uAPI headers to real kerneldoc (Matt A) > > > - Clean up kerneldoc warnings headers (Matt A, Maarten) > > > - Fail driver if LMEM training failed (Matt R) > > > - Avoid div-by-zero on Gen2 (Ville) > > > - Read C0DRB3/C1DRB3 as 16 bits again and add _BW suffix (Ville) > > > - Remove reference to struct drm_device.pdev (Thomas) > > > - Increase separation between GuC and execlists code (Chris, Matt B) > > > > > > - Use might_alloc() (Bernard) > > > - Split DGFX_FEATURES from GEN12_FEATURES (Lucas) > > > - Deduplicate Wa_22010271021 programming on (Jose) > > > - Drop duplicate WaDisable4x2SubspanOptimization:hsw (Tvrtko) > > > - Selftest improvements (Chris, Hsin-Yi, Tvrtko) > > > - Shuffle around init_memory_region for stolen (Matt) > > > - Typo fixes (wengjianfeng) > > > > > > The following changes since commit > > > 425390c5dce6da76578389629d19517fcd79c959: > > > > > > drm/i915: split dgfx features from gen 12 (2021-04-14 13:05:06 +0300) > > > > > > are available in the Git repository at: > > > > > > git://anongit.freedesktop.org/drm/drm-intel > > > tags/drm-intel-gt-next-2021-05-28 > > > > > > for you to fetch changes up to 5b26d57fdb499c2363f3d895ef008e73ec02eb9b: > > > > > > drm/i915: Add Wa_14010733141 (2021-05-27 11:05:09 -0700) > > > > > > > > > UAPI Changes: > > > - Add reworked uAPI for DG1 behind CONFIG_BROKEN (Matt A, Abdiel) > > > > > > Driver Changes: > > > > > > - Fix for Gitlab issues #3293 and #3450: > > > Avoid kernel crash on older L-shape memory machines > > > > > > - Add Wa_14010733141 (VDBox SFC reset) for Gen11+ (Aditya) > > > - Fix crash in auto_retire active retire callback due to > > > misalignment (Stephane) > > >
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: Remove the repeated declaration
== Series Details == Series: drm/i915/gem: Remove the repeated declaration URL : https://patchwork.freedesktop.org/series/90832/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10156_full -> Patchwork_20254_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20254_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20254_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20254_full: ### IGT changes ### Possible regressions * igt@kms_draw_crc@draw-method-xrgb-blt-ytiled: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-skl1/igt@kms_draw_...@draw-method-xrgb-blt-ytiled.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/shard-skl10/igt@kms_draw_...@draw-method-xrgb-blt-ytiled.html Known issues Here are the changes found in Patchwork_20254_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-clear: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#1888] / [i915#3160]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-glk5/igt@gem_cre...@create-clear.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/shard-glk9/igt@gem_cre...@create-clear.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][6] -> [TIMEOUT][7] ([i915#2369] / [i915#3063]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-tglb3/igt@gem_...@unwedge-stress.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/shard-tglb3/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-glk5/igt@gem_exec_fair@basic-none-r...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/shard-glk9/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: NOTRUN -> [FAIL][10] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-apl: NOTRUN -> [FAIL][12] ([i915#2389]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/shard-apl1/igt@gem_exec_reloc@basic-wide-act...@bcs0.html * igt@gem_exec_reloc@basic-wide-active@rcs0: - shard-iclb: NOTRUN -> [FAIL][13] ([i915#2389]) +4 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/shard-iclb2/igt@gem_exec_reloc@basic-wide-act...@rcs0.html - shard-kbl: NOTRUN -> [FAIL][14] ([i915#2389]) +4 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/shard-kbl2/igt@gem_exec_reloc@basic-wide-act...@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/shard-apl6/igt@gem_huc_c...@huc-copy.html - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#2190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/shard-skl1/igt@gem_huc_c...@huc-copy.html * igt@gem_mmap_gtt@cpuset-basic-small-copy-odd: - shard-snb: NOTRUN -> [INCOMPLETE][17] ([i915#2055] / [i915#3468]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/shard-snb2/igt@gem_mmap_...@cpuset-basic-small-copy-odd.html * igt@gem_mmap_gtt@cpuset-medium-copy-xy: - shard-kbl: [PASS][18] -> [INCOMPLETE][19] ([i915#3468]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-kbl7/igt@gem_mmap_...@cpuset-medium-copy-xy.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/shard-kbl7/igt@gem_mmap_...@cpuset-medium-copy-xy.html * igt@gem_mmap_gtt@fault-concurrent: - shard-skl: NOTRUN -> [INCOMPLETE][20] ([i915#3468]) [20]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/1] drm/i915/selftests: Fix error return code in live_parallel_switch()
== Series Details == Series: series starting with [1/1] drm/i915/selftests: Fix error return code in live_parallel_switch() URL : https://patchwork.freedesktop.org/series/90831/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10156_full -> Patchwork_20253_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20253_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20253_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20253_full: ### IGT changes ### Possible regressions * igt@gem_exec_whisper@basic-queues-all: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-iclb7/igt@gem_exec_whis...@basic-queues-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/shard-iclb7/igt@gem_exec_whis...@basic-queues-all.html Known issues Here are the changes found in Patchwork_20253_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-apl: NOTRUN -> [DMESG-WARN][3] ([i915#180]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/shard-apl1/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_eio@in-flight-contexts-10ms: - shard-iclb: [PASS][5] -> [TIMEOUT][6] ([i915#3070]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-iclb7/igt@gem_...@in-flight-contexts-10ms.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/shard-iclb5/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][7] -> [TIMEOUT][8] ([i915#2369] / [i915#3063]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-tglb3/igt@gem_...@unwedge-stress.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/shard-tglb3/igt@gem_...@unwedge-stress.html - shard-snb: NOTRUN -> [FAIL][9] ([i915#3354]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/shard-snb7/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-glk5/igt@gem_exec_fair@basic-none-r...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/shard-glk6/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-kbl1/igt@gem_exec_fair@basic-n...@vecs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/shard-kbl7/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: NOTRUN -> [FAIL][14] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-tglb: NOTRUN -> [FAIL][15] ([i915#2389]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/shard-tglb8/igt@gem_exec_reloc@basic-wide-act...@bcs0.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#2190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/shard-apl2/igt@gem_huc_c...@huc-copy.html - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/shard-skl2/igt@gem_huc_c...@huc-copy.html * igt@gem_mmap_gtt@big-copy: - shard-glk: [PASS][18] -> [FAIL][19] ([i915#307]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-glk8/igt@gem_mmap_...@big-copy.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/shard-glk5/igt@gem_mmap_...@big-copy.html * igt@gem_mmap_gtt@cpuset-basic-small-copy: - shard-apl: NOTRUN -> [INCOMPLETE][20] ([i915#3468]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/shard-apl7/igt@gem_mmap_...@cpuset-basic-small-copy.html * igt@gem_mmap_gtt@cpuset-basic-small-copy-odd: - shard-snb: NOTRUN ->
Re: [Intel-gfx] [PATCH 5/9] drm: Add Client Cap for advance gamma mode
Hi Uma, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on drm-tip/drm-tip drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master v5.13-rc4 next-20210601] [cannot apply to drm/drm-next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Uma-Shankar/Enhance-pipe-color-support-for-multi-segmented-luts/20210601-180720 base: git://anongit.freedesktop.org/drm-intel for-linux-next compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 reproduce: cd tools/perf && ./check-headers.sh If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot perfheadercheck warnings: (new ones prefixed by >>) Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 819> /** >> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from >> latest version at 'include/uapi/drm/drm.h': 820> * Add support for advance >> gamma mode UAPI >> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from >> latest version at 'include/uapi/drm/drm.h': 821> * If set to 1, DRM will >> enable advance gamma mode >> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from >> latest version at 'include/uapi/drm/drm.h': 822> * UAPI to process the >> gamma mode based on extended >> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from >> latest version at 'include/uapi/drm/drm.h': 823> * range and segments. Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 824> */ >> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from >> latest version at 'include/uapi/drm/drm.h': 825> #define >> DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES 6 Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 826> --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 60/97] drm/i915: Track 'serial' counts for virtual engines
On 6/1/2021 02:31, Tvrtko Ursulin wrote: On 27/05/2021 18:01, John Harrison wrote: On 5/27/2021 01:53, Tvrtko Ursulin wrote: On 26/05/2021 19:45, John Harrison wrote: On 5/26/2021 01:40, Tvrtko Ursulin wrote: On 25/05/2021 18:52, Matthew Brost wrote: On Tue, May 25, 2021 at 11:16:12AM +0100, Tvrtko Ursulin wrote: On 06/05/2021 20:14, Matthew Brost wrote: From: John Harrison The serial number tracking of engines happens at the backend of request submission and was expecting to only be given physical engines. However, in GuC submission mode, the decomposition of virtual to physical engines does not happen in i915. Instead, requests are submitted to their virtual engine mask all the way through to the hardware (i.e. to GuC). This would mean that the heart beat code thinks the physical engines are idle due to the serial number not incrementing. This patch updates the tracking to decompose virtual engines into their physical constituents and tracks the request against each. This is not entirely accurate as the GuC will only be issuing the request to one physical engine. However, it is the best that i915 can do given that it has no knowledge of the GuC's scheduling decisions. Commit text sounds a bit defeatist. I think instead of making up the serial counts, which has downsides (could you please document in the commit what they are), we should think how to design things properly. IMO, I don't think fixing serial counts is the scope of this series. We should focus on getting GuC submission in not cleaning up all the crap that is in the i915. Let's make a note of this though so we can revisit later. I will say again - commit message implies it is introducing an unspecified downside by not fully fixing an also unspecified issue. It is completely reasonable, and customary even, to ask for both to be documented in the commit message. Not sure what exactly is 'unspecified'. I thought the commit message described both the problem (heartbeat not running when using virtual engines) and the result (heartbeat running on more engines than strictly necessary). But in greater detail... The serial number tracking is a hack for the heartbeat code to know whether an engine is busy or idle, and therefore whether it should be pinged for aliveness. Whenever a submission is made to an engine, the serial number is incremented. The heartbeat code keeps a copy of the value. If the value has changed, the engine is busy and needs to be pinged. This works fine for execlist mode where virtual engine decomposition is done inside i915. It fails miserably for GuC mode where the decomposition is done by the hardware. The reason being that the heartbeat code only looks at physical engines but the serial count is only incremented on the virtual engine. Thus, the heartbeat sees everything as idle and does not ping. So hangcheck does not work. Or it works because GuC does it anyway. Either way, that's one thing to explicitly state in the commit message. This patch decomposes the virtual engines for the sake of incrementing the serial count on each sub-engine in order to keep the heartbeat code happy. The downside is that now the heartbeat sees all sub-engines as busy rather than only the one the submission actually ends up on. There really isn't much that can be done about that. The heartbeat code is in i915 not GuC, the scheduler is in GuC not i915. The only way to improve it is to either move the heartbeat code into GuC as well and completely disable the i915 side, or add some way for i915 to interrogate GuC as to which engines are or are not active. Technically, we do have both. GuC has (or at least had) an option to force a context switch on every execution quantum pre-emption. However, that is much, much, more heavy weight than the heartbeat. For the latter, we do (almost) have the engine usage statistics for PMU and such like. I'm not sure how much effort it would be to wire that up to the heartbeat code instead of using the serial count. In short, the serial count is ever so slightly inefficient in that it causes heartbeat pings on engines which are idle. On the other hand, it is way more efficient and simpler than the current alternatives. And the hack to make hangcheck work creates this inefficiency where heartbeats are sent to idle engines. Which is probably fine just needs to be explained. Does that answer the questions? With the two points I re-raise clearly explained, possibly even patch title changed, yeah. I am just wanting for it to be more easily obvious to patch reader what it is functionally about - not just what implementation details have been change but why as well. My understanding is that we don't explain every piece of code in minute detail in every checkin email that touches it. I thought my description was already pretty verbose. I've certainly seen way less informative checkins that apparently made it through review without
Re: [Intel-gfx] [PATCH v4 1/1] drm/i915/dg1: Add HWMON power sensor support
On 2021-06-01 14:39:11, Sundaresan, Sujaritha wrote: > Date: Tue, 1 Jun 2021 14:39:11 -0700 > From: "Sundaresan, Sujaritha" > To: Dale B Stimson , > intel-gfx@lists.freedesktop.org, dri-de...@lists.freedesktop.org > CC: Jon Ewins , Jani Nikula > > Subject: Re: [PATCH v4 1/1] drm/i915/dg1: Add HWMON power sensor support > User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) > Gecko/20100101 Thunderbird/78.10.2 > > > On 5/27/2021 5:44 PM, Dale B Stimson wrote: > > As part of the System Managemenent Interface (SMI), use the HWMON > > subsystem to display power utilization. > > > > The following standard HWMON power sensors are currently supported > > (and appropriately scaled): > >/sys/class/drm/card0/device/hwmon/hwmon > > - energy1_input > > - power1_cap > > - power1_max > > > > Some non-standard HWMON power information is also provided, such as > > enable bits and intervals. > > > > Signed-off-by: Dale B Stimson > > --- > > .../ABI/testing/sysfs-driver-intel-i915-hwmon | 116 +++ > > drivers/gpu/drm/i915/Kconfig | 1 + > > drivers/gpu/drm/i915/Makefile | 1 + > > drivers/gpu/drm/i915/i915_drv.c | 6 + > > drivers/gpu/drm/i915/i915_drv.h | 3 + > > drivers/gpu/drm/i915/i915_hwmon.c | 757 ++ > > drivers/gpu/drm/i915/i915_hwmon.h | 42 + > > drivers/gpu/drm/i915/i915_reg.h | 52 ++ > > 8 files changed, 978 insertions(+) > > create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon > > create mode 100644 drivers/gpu/drm/i915/i915_hwmon.c > > create mode 100644 drivers/gpu/drm/i915/i915_hwmon.h > > > > diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon > > b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon > > new file mode 100644 > > index 0..2ee7c413ca190 > > --- /dev/null > > +++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon > > @@ -0,0 +1,116 @@ > > +What: /sys/devices/.../hwmon/hwmon/energy1_input > > +Date: June 2021 > > +KernelVersion: 5.14 > > +Contact:dri-de...@lists.freedesktop.org > > +Description: > > +RO. Energy input of device in microjoules. > > + > > + The returned textual representation is an unsigned integer > > + number that can be stored in 64-bits. Warning: The hardware > > + register is 32-bits wide and can overflow by wrapping around. > > + A single wrap-around between calls to read this value can > > + be detected and will be accounted for in the returned value. > > + At a power consumption of 1 watt, the 32-bit hardware register > > + would wrap-around approximately every 3 days. > > + > > + Only supported for particular Intel i915 graphics platforms. > > + > > +What: /sys/devices/.../hwmon/hwmon/power1_max_enable > > +Date: June 2021 > > +KernelVersion: 5.14 > > +Contact:dri-de...@lists.freedesktop.org > > +Description: > > +RW. Sustained power limit is enabled - true or false. > > Hi Dale, > > This attribute should be read-only ? That is correct. The hardware implementation is read-only. > > + > > +The power controller will throttle the operating frequency > > +if the power averaged over a window (typically seconds) > > +exceeds this limit. > > + > > +See power1_max_enable power1_max power1_max_interval > > + > > + Only supported for particular Intel i915 graphics platforms. > > + > > +What: /sys/devices/.../hwmon/hwmon/power1_max > > +Date: June 2021 > > +KernelVersion: 5.14 > > +Contact:dri-de...@lists.freedesktop.org > > +Description: > > +RW. Sustained power limit in milliwatts > > + > > +The power controller will throttle the operating frequency > > +if the power averaged over a window (typically seconds) > > +exceeds this limit. > > + > > +See power1_max_enable power1_max power1_max_interval > > + > > + Only supported for particular Intel i915 graphics platforms. > > + > > +What: /sys/devices/.../hwmon/hwmon/power1_max_interval > > +Date: June 2021 > > +KernelVersion: 5.14 > > +Contact:dri-de...@lists.freedesktop.org > > +Description: > > +RW. Sustained power limit interval in milliseconds over > > +which sustained power is averaged. > > + > > +See power1_max_enable power1_max power1_max_interval > > + > > + Only supported for particular Intel i915 graphics platforms. > > + > > +What: /sys/devices/.../hwmon/hwmon/power1_cap_enable > > +Date: June 2021 > > +KernelVersion: 5.14 > > +Contact:dri-de...@lists.freedesktop.org > > +Description: > > + RW.
Re: [Intel-gfx] [PULL] drm-intel-gt-next
This has these two patches applied, and it doesn't build. drm/i915: drop the __i915_active_call pointer packing drm/i915: Fix crash in auto_retire The latter patch shouldn't be necessary after the former, please fix that up and resend and please build test trees before I get them in future. Dave. On Fri, 28 May 2021 at 17:27, Joonas Lahtinen wrote: > > Quoting Joonas Lahtinen (2021-05-28 10:25:57) > > Hi Dave & Daniel, > > > > Here's drm-intel-gt-next pull request. > > > > Most notably it has the reworked DG1 uAPI (behind CONFIG_BROKEN) > > as requested. Important fix for Gitlab issues #3293 and #3450 and > > one another kernel crash. Adds missing workarounds for Gen11 and > > Gen12. Hiding of modparams for compiled-out features. Conversion > > to use trylock shrinking for BSW VT-d and BXT. > > > > Then there are the uAPI kerneldoc improvements as part of the DG1 > > uAPI rework. Usual amount smaller fixes, code refactoring and > > cleanups as prep for upcoming patches. > > And includes tag 'topic/intel-gen-to-ver-2021-04-19' (but that is > already merged to drm-next). > > Regards, Joonas > > > Regards, Joonas > > > > *** > > > > drm-intel-gt-next-2021-05-28: > > > > UAPI Changes: > > - Add reworked uAPI for DG1 behind CONFIG_BROKEN (Matt A, Abdiel) > > > > Driver Changes: > > > > - Fix for Gitlab issues #3293 and #3450: > > Avoid kernel crash on older L-shape memory machines > > > > - Hide modparams for compiled-out features (Tvrtko) > > - Add Wa_14010733141 (VDBox SFC reset) for Gen11+ (Aditya) > > - Fix crash in auto_retire active retire callback due to > > misalignment (Stephane) > > - Use trylock in shrinker for GGTT on BSW VT-d and BXT (Maarten) > > - Fix overlay active retire callback alignment (Tvrtko) > > - Eliminate need to align active retire callbacks (Matt A, Ville, > > Daniel) > > - Program FF_MODE2 tuning value for all Gen12 platforms (Caz) > > - Add Wa_14011060649 for TGL,RKL,DG1 and ADLS (Swathi) > > - Create stolen memory region from local memory on DG1 (CQ) > > - Place PD in LMEM on dGFX (Matt A) > > - Use WC when default state object is allocated in LMEM (Venkata) > > - Determine the coherent map type based on object location (Venkata) > > - Use lmem physical addresses for fb_mmap() on discrete (Mohammed) > > - Bypass aperture on fbdev when LMEM is available (Anusha) > > - Return error value when displayable BO not in LMEM for dGFX (Mohammed) > > - Do release kernel context if breadcrumb measure fails (Janusz) > > - Apply Wa_22010271021 for all Gen11 platforms (Caz) > > - Fix unlikely ref count race in arming the watchdog timer (Tvrtko) > > - Check actual RC6 enable status in PMU (Tvrtko) > > - Fix a double free in gen8_preallocate_top_level_pdp (Lv) > > - Remove erroneous i915_is_ggtt check for > > I915_GEM_OBJECT_UNBIND_VM_TRYLOCK (Maarten) > > > > - Convert uAPI headers to real kerneldoc (Matt A) > > - Clean up kerneldoc warnings headers (Matt A, Maarten) > > - Fail driver if LMEM training failed (Matt R) > > - Avoid div-by-zero on Gen2 (Ville) > > - Read C0DRB3/C1DRB3 as 16 bits again and add _BW suffix (Ville) > > - Remove reference to struct drm_device.pdev (Thomas) > > - Increase separation between GuC and execlists code (Chris, Matt B) > > > > - Use might_alloc() (Bernard) > > - Split DGFX_FEATURES from GEN12_FEATURES (Lucas) > > - Deduplicate Wa_22010271021 programming on (Jose) > > - Drop duplicate WaDisable4x2SubspanOptimization:hsw (Tvrtko) > > - Selftest improvements (Chris, Hsin-Yi, Tvrtko) > > - Shuffle around init_memory_region for stolen (Matt) > > - Typo fixes (wengjianfeng) > > > > The following changes since commit 425390c5dce6da76578389629d19517fcd79c959: > > > > drm/i915: split dgfx features from gen 12 (2021-04-14 13:05:06 +0300) > > > > are available in the Git repository at: > > > > git://anongit.freedesktop.org/drm/drm-intel > > tags/drm-intel-gt-next-2021-05-28 > > > > for you to fetch changes up to 5b26d57fdb499c2363f3d895ef008e73ec02eb9b: > > > > drm/i915: Add Wa_14010733141 (2021-05-27 11:05:09 -0700) > > > > > > UAPI Changes: > > - Add reworked uAPI for DG1 behind CONFIG_BROKEN (Matt A, Abdiel) > > > > Driver Changes: > > > > - Fix for Gitlab issues #3293 and #3450: > > Avoid kernel crash on older L-shape memory machines > > > > - Add Wa_14010733141 (VDBox SFC reset) for Gen11+ (Aditya) > > - Fix crash in auto_retire active retire callback due to > > misalignment (Stephane) > > - Fix overlay active retire callback alignment (Tvrtko) > > - Eliminate need to align active retire callbacks (Matt A, Ville, > > Daniel) > > - Program FF_MODE2 tuning value for all Gen12 platforms (Caz) > > - Add Wa_14011060649 for TGL,RKL,DG1 and ADLS (Swathi) > > - Create stolen memory region from local memory on DG1 (CQ) > > - Place PD in LMEM on dGFX (Matt A) > > - Use WC when default state object is allocated in LMEM (Venkata) > > - Determine the coherent map type based on object
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/display: Introduce new intel_psr_pause/resume function
A call to intel_psr_flush() will active PSR between intel_psr_pause() and a
_resume() call.
On Tue, 2021-06-01 at 15:47 +0300, Gwan-gyeong Mun wrote:
> This introduces the following function that can exit and activate a psr
> source when intel_psr is already enabled.
>
> - intel_psr_pause(): Pause current PSR. It deactivates current psr state.
> - intel_psr_resume(): Resume paused PSR. It activates paused psr state.
>
> v2: Address Jose's review comment.
> - Remove unneeded changes around the intel_psr_enable().
> - Add intel_psr_post_exit() which processes waiting until PSR is idle
> and WA for SelectiveFetch.
>
> Cc: José Roberto de Souza
> Cc: Stanislav Lisovskiy
> Cc: Ville Syrjälä
> Signed-off-by: Gwan-gyeong Mun
> Signed-off-by: Matt Roper
> ---
> .../drm/i915/display/intel_display_types.h| 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 84 ---
> drivers/gpu/drm/i915/display/intel_psr.h | 2 +
> 3 files changed, 76 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b8d1f702d808..ee7cbdd7db87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1482,6 +1482,7 @@ struct intel_psr {
> bool sink_support;
> bool source_support;
> bool enabled;
> + bool paused;
> enum pipe pipe;
> enum transcoder transcoder;
> bool active;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 000e1ffe8c05..4ff71e529cd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1113,6 +1113,7 @@ static void intel_psr_enable_locked(struct intel_dp
> *intel_dp,
> intel_psr_enable_sink(intel_dp);
> intel_psr_enable_source(intel_dp);
> intel_dp->psr.enabled = true;
> + intel_dp->psr.paused = false;
>
> intel_psr_activate(intel_dp);
> }
> @@ -1182,22 +1183,12 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
> intel_dp->psr.active = false;
> }
>
> -static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> +static void intel_psr_post_exit(struct intel_dp *intel_dp)
Better name would be: intel_psr_wait_exit_locked() and it don't need to remove
WA 1408330847.
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> i915_reg_t psr_status;
> u32 psr_status_mask;
>
> - lockdep_assert_held(_dp->psr.lock);
> -
> - if (!intel_dp->psr.enabled)
> - return;
> -
> - drm_dbg_kms(_priv->drm, "Disabling PSR%s\n",
> - intel_dp->psr.psr2_enabled ? "2" : "1");
> -
> - intel_psr_exit(intel_dp);
> -
> if (intel_dp->psr.psr2_enabled) {
> psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
> psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
> @@ -1217,6 +1208,22 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
>IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> +}
> +
> +static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + lockdep_assert_held(_dp->psr.lock);
> +
> + if (!intel_dp->psr.enabled)
> + return;
> +
> + drm_dbg_kms(_priv->drm, "Disabling PSR%s\n",
> + intel_dp->psr.psr2_enabled ? "2" : "1");
> +
> + intel_psr_exit(intel_dp);
> + intel_psr_post_exit(intel_dp);
>
> /* Disable PSR on Sink */
> drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, 0);
> @@ -1254,6 +1261,61 @@ void intel_psr_disable(struct intel_dp *intel_dp,
> cancel_delayed_work_sync(_dp->psr.dc3co_work);
> }
>
> +/**
> + * intel_psr_pause - Pause PSR
> + * @intel_dp: Intel DP
> + *
> + * This function need to be called after enabling psr.
> + */
> +void intel_psr_pause(struct intel_dp *intel_dp)
> +{
> + struct intel_psr *psr = _dp->psr;
> +
> + if (!CAN_PSR(intel_dp))
> + return;
> +
> + mutex_lock(>lock);
> +
> + if (!psr->active) {
> + mutex_unlock(>lock);
> + return;
> + }
> +
> + intel_psr_exit(intel_dp);
> + intel_psr_post_exit(intel_dp);
> + psr->paused = true;
> +
> + mutex_unlock(>lock);
> +
> + cancel_work_sync(>work);
> + cancel_delayed_work_sync(>dc3co_work);
> +}
> +
> +/**
> + * intel_psr_resume - Resume PSR
> + * @intel_dp: Intel DP
> + *
> + * This function need to be called after pausing psr.
> + */
> +void intel_psr_resume(struct intel_dp *intel_dp)
> +{
> + struct intel_psr *psr = _dp->psr;
> +
> + if (!CAN_PSR(intel_dp))
> + return;
> +
> + mutex_lock(>lock);
> +
> + if (!psr->paused)
> +
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function
== Series Details == Series: series starting with [v2,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function URL : https://patchwork.freedesktop.org/series/90830/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10156_full -> Patchwork_20252_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20252_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20252_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20252_full: ### Piglit changes ### Possible regressions * spec@glsl-1.50@execution@built-in-functions@gs-op-bitand-not-ivec2-int (NEW): - pig-snb-2600: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/pig-snb-2600/spec@glsl-1.50@execution@built-in-functi...@gs-op-bitand-not-ivec2-int.html New tests - New tests have been introduced between CI_DRM_10156_full and Patchwork_20252_full: ### New Piglit tests (1) ### * spec@glsl-1.50@execution@built-in-functions@gs-op-bitand-not-ivec2-int: - Statuses : 1 fail(s) - Exec time: [0.15] s Known issues Here are the changes found in Patchwork_20252_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@engines-hostile: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/shard-snb7/igt@gem_ctx_persiste...@engines-hostile.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][3] ([i915#3354]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/shard-snb7/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-glk: [PASS][4] -> [FAIL][5] ([i915#2842]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-glk5/igt@gem_exec_fair@basic-none-r...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/shard-glk2/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: NOTRUN -> [FAIL][7] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/shard-kbl3/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][9] -> [SKIP][10] ([i915#2190]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-tglb1/igt@gem_huc_c...@huc-copy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/shard-tglb6/igt@gem_huc_c...@huc-copy.html - shard-apl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/shard-apl3/igt@gem_huc_c...@huc-copy.html - shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#2190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/shard-skl10/igt@gem_huc_c...@huc-copy.html * igt@gem_mmap_gtt@big-copy: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#307]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-glk8/igt@gem_mmap_...@big-copy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/shard-glk5/igt@gem_mmap_...@big-copy.html * igt@gem_mmap_gtt@cpuset-basic-small-copy-odd: - shard-snb: NOTRUN -> [INCOMPLETE][15] ([i915#2055] / [i915#3468]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/shard-snb6/igt@gem_mmap_...@cpuset-basic-small-copy-odd.html - shard-kbl: [PASS][16] -> [INCOMPLETE][17] ([i915#3468]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/shard-kbl2/igt@gem_mmap_...@cpuset-basic-small-copy-odd.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/shard-kbl4/igt@gem_mmap_...@cpuset-basic-small-copy-odd.html * igt@gem_mmap_gtt@fault-concurrent-y: - shard-kbl: NOTRUN -> [INCOMPLETE][18] ([i915#3468]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/shard-kbl4/igt@gem_mmap_...@fault-concurrent-y.html - shard-apl: NOTRUN -> [INCOMPLETE][19]
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/opregion: add support for mailbox #5 EDID
Le Tue, Jun 01, 2021 at 06:50:24PM +0300, Ville Syrj?l? a ?crit : > On Mon, May 31, 2021 at 10:46:41PM +0200, Anisse Astier wrote: > > The ACPI OpRegion Mailbox #5 ASLE extension may contain an EDID to be > > used for the embedded display. Add support for using it via by adding > > the EDID to the list of available modes on the connector, and use it for > > eDP when available. > > > > If a panel's EDID is broken, there may be an override EDID set in the > > ACPI OpRegion mailbox #5. Use it if available. > > Looks like Windows uses the ACPI _DDC method instead. We should probably > do the same, just in case some crazy machine stores the EDID somewhere > else. Thanks, I wouldn't have thought of this. It seems Daniel Dadap did a patch series to do just that, in a generic way: https://lore.kernel.org/amd-gfx/20200727205357.27839-1-dda...@nvidia.com/ I've tried patch 1 & 2, and after a fix[1] was able to call the _DDC method on most devices, but without any EDID being returned. I looked at the disassembled ACPI tables[2], and could not find any device with the _DDC method. Are you sure it's the only method the Windows driver uses to get the EDID ? Regards, Anisse [1] _DOD ids should only use 16 lower bits, see table here: https://uefi.org/specs/ACPI/6.4/Apx_B_Video_Extensions/display-specific-methods.html#dod-enumerate-all-devices-attached-to-the-display-adapter [2] acpidump: https://gitlab.freedesktop.org/drm/intel/-/issues/3454#note_913970 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/display: Drop FIXME about turn off infoframes
> -Original Message- > From: Intel-gfx On Behalf Of José > Roberto de Souza > Sent: Friday, May 14, 2021 4:23 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v2 4/4] drm/i915/display: Drop FIXME about turn > off infoframes > > intel_dp_set_infoframes() call in intel_ddi_post_disable_dp() will take care > to > disable all enabled infoframes. > > Cc: Ville Syrjälä Reviewed-by: Radhakrishna Sripada > Signed-off-by: José Roberto de Souza > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 5bc5528f3091..d3bc5a1a936a 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -2762,7 +2762,6 @@ static void intel_ddi_pre_enable(struct > intel_atomic_state *state, > conn_state); > > /* FIXME precompute everything properly */ > - /* FIXME how do we turn infoframes off again? */ > if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) > dig_port->set_infoframes(encoder, true, crtc_state, >conn_state); > -- > 2.31.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adl_p: CDCLK crawl support for ADL
== Series Details == Series: drm/i915/adl_p: CDCLK crawl support for ADL URL : https://patchwork.freedesktop.org/series/90842/ State : success == Summary == CI Bug Log - changes from CI_DRM_10156 -> Patchwork_20260 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/index.html Known issues Here are the changes found in Patchwork_20260 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gt_heartbeat: - fi-cml-s: [PASS][1] -> [DMESG-FAIL][2] ([i915#2291] / [i915#541]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-cml-s/igt@i915_selftest@live@gt_heartbeat.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-cml-s/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_frontbuffer_tracking@basic: - fi-tgl-u2: [PASS][3] -> [FAIL][4] ([i915#2416]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-tgl-u2/igt@kms_frontbuffer_track...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-tgl-u2/igt@kms_frontbuffer_track...@basic.html Warnings * igt@i915_selftest@live@execlists: - fi-tgl-u2: [INCOMPLETE][5] ([i915#3462]) -> [DMESG-FAIL][6] ([i915#3462]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-tgl-u2/igt@i915_selftest@l...@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-tgl-u2/igt@i915_selftest@l...@execlists.html * igt@runner@aborted: - fi-cfl-8700k: [FAIL][7] ([i915#3363]) -> [FAIL][8] ([i915#2426] / [i915#3363]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-cfl-8700k/igt@run...@aborted.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-cfl-8700k/igt@run...@aborted.html - fi-glk-dsi: [FAIL][9] ([i915#2426] / [i915#3363] / [k.org#202321]) -> [FAIL][10] ([i915#3363] / [k.org#202321]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-glk-dsi/igt@run...@aborted.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-glk-dsi/igt@run...@aborted.html - fi-kbl-r: [FAIL][11] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][12] ([i915#1436] / [i915#3363]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-r/igt@run...@aborted.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-kbl-r/igt@run...@aborted.html - fi-bdw-5557u: [FAIL][13] ([i915#3462]) -> [FAIL][14] ([i915#2426] / [i915#3462]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-bdw-5557u/igt@run...@aborted.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-bdw-5557u/igt@run...@aborted.html - fi-kbl-soraka: [FAIL][15] ([i915#1436] / [i915#3363]) -> [FAIL][16] ([i915#1436] / [i915#2426] / [i915#3363]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-soraka/igt@run...@aborted.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-kbl-soraka/igt@run...@aborted.html - fi-kbl-7500u: [FAIL][17] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][18] ([i915#1436] / [i915#3363]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-7500u/igt@run...@aborted.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-kbl-7500u/igt@run...@aborted.html - fi-bxt-dsi: [FAIL][19] ([i915#3363]) -> [FAIL][20] ([i915#2426] / [i915#3363]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-bxt-dsi/igt@run...@aborted.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20260/fi-bxt-dsi/igt@run...@aborted.html [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2416]: https://gitlab.freedesktop.org/drm/intel/issues/2416 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321 Participating hosts (47 -> 42) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_10156 -> Patchwork_20260 CI-20190529: 20190529 CI_DRM_10156: 551125c07e42a44a1b4bf8ad735619f2e315a0e2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6098: 1fbc1e7d602f96a7f4e2b95057eef994656b8e74 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_20260: 52b739da49bcfa793a2b3e5f320ab8a0d5f04707 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 52b739da49bc
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/vgem: Fix the pitch to be 64 byte aligned for Intel platforms
== Series Details ==
Series: drm/vgem: Fix the pitch to be 64 byte aligned for Intel platforms
URL : https://patchwork.freedesktop.org/series/90841/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10156 -> Patchwork_20259
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20259/index.html
Known issues
Here are the changes found in Patchwork_20259 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20259/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][2] ([i915#2782]) -> [PASS][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20259/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@prime_vgem@basic-fence-flip:
- fi-bsw-kefka: [SKIP][4] ([fdo#109271]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-bsw-kefka/igt@prime_v...@basic-fence-flip.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20259/fi-bsw-kefka/igt@prime_v...@basic-fence-flip.html
- fi-snb-2520m: [SKIP][6] ([fdo#109271]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-snb-2520m/igt@prime_v...@basic-fence-flip.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20259/fi-snb-2520m/igt@prime_v...@basic-fence-flip.html
Warnings
* igt@runner@aborted:
- fi-glk-dsi: [FAIL][8] ([i915#2426] / [i915#3363] /
[k.org#202321]) -> [FAIL][9] ([i915#3363] / [k.org#202321])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-glk-dsi/igt@run...@aborted.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20259/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-r: [FAIL][10] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][11] ([i915#1436] / [i915#3363])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-r/igt@run...@aborted.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20259/fi-kbl-r/igt@run...@aborted.html
- fi-kbl-soraka: [FAIL][12] ([i915#1436] / [i915#3363]) -> [FAIL][13]
([i915#1436] / [i915#2426] / [i915#3363])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-soraka/igt@run...@aborted.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20259/fi-kbl-soraka/igt@run...@aborted.html
- fi-kbl-7500u: [FAIL][14] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][15] ([i915#1436] / [i915#3363])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-7500u/igt@run...@aborted.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20259/fi-kbl-7500u/igt@run...@aborted.html
- fi-kbl-guc: [FAIL][16] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][17] ([i915#1436] / [i915#3363])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-guc/igt@run...@aborted.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20259/fi-kbl-guc/igt@run...@aborted.html
- fi-cfl-guc: [FAIL][18] ([i915#3363]) -> [FAIL][19] ([i915#2426] /
[i915#3363])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-cfl-guc/igt@run...@aborted.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20259/fi-cfl-guc/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (47 -> 41)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-bsw-cyan
fi-ctg-p8600 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_10156 -> Patchwork_20259
CI-20190529: 20190529
CI_DRM_10156: 551125c07e42a44a1b4bf8ad735619f2e315a0e2 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6098: 1fbc1e7d602f96a7f4e2b95057eef994656b8e74 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20259:
Re: [Intel-gfx] [PATCH v4 1/1] drm/i915/dg1: Add HWMON power sensor support
On 5/27/2021 5:44 PM, Dale B Stimson wrote: As part of the System Managemenent Interface (SMI), use the HWMON subsystem to display power utilization. The following standard HWMON power sensors are currently supported (and appropriately scaled): /sys/class/drm/card0/device/hwmon/hwmon - energy1_input - power1_cap - power1_max Some non-standard HWMON power information is also provided, such as enable bits and intervals. Signed-off-by: Dale B Stimson --- .../ABI/testing/sysfs-driver-intel-i915-hwmon | 116 +++ drivers/gpu/drm/i915/Kconfig | 1 + drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_drv.c | 6 + drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_hwmon.c | 757 ++ drivers/gpu/drm/i915/i915_hwmon.h | 42 + drivers/gpu/drm/i915/i915_reg.h | 52 ++ 8 files changed, 978 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon create mode 100644 drivers/gpu/drm/i915/i915_hwmon.c create mode 100644 drivers/gpu/drm/i915/i915_hwmon.h diff --git a/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon new file mode 100644 index 0..2ee7c413ca190 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon @@ -0,0 +1,116 @@ +What: /sys/devices/.../hwmon/hwmon/energy1_input +Date: June 2021 +KernelVersion: 5.14 +Contact:dri-de...@lists.freedesktop.org +Description: +RO. Energy input of device in microjoules. + + The returned textual representation is an unsigned integer + number that can be stored in 64-bits. Warning: The hardware + register is 32-bits wide and can overflow by wrapping around. + A single wrap-around between calls to read this value can + be detected and will be accounted for in the returned value. + At a power consumption of 1 watt, the 32-bit hardware register + would wrap-around approximately every 3 days. + + Only supported for particular Intel i915 graphics platforms. + +What: /sys/devices/.../hwmon/hwmon/power1_max_enable +Date: June 2021 +KernelVersion: 5.14 +Contact:dri-de...@lists.freedesktop.org +Description: +RW. Sustained power limit is enabled - true or false. Hi Dale, This attribute should be read-only ? + +The power controller will throttle the operating frequency +if the power averaged over a window (typically seconds) +exceeds this limit. + +See power1_max_enable power1_max power1_max_interval + + Only supported for particular Intel i915 graphics platforms. + +What: /sys/devices/.../hwmon/hwmon/power1_max +Date: June 2021 +KernelVersion: 5.14 +Contact:dri-de...@lists.freedesktop.org +Description: +RW. Sustained power limit in milliwatts + +The power controller will throttle the operating frequency +if the power averaged over a window (typically seconds) +exceeds this limit. + +See power1_max_enable power1_max power1_max_interval + + Only supported for particular Intel i915 graphics platforms. + +What: /sys/devices/.../hwmon/hwmon/power1_max_interval +Date: June 2021 +KernelVersion: 5.14 +Contact:dri-de...@lists.freedesktop.org +Description: +RW. Sustained power limit interval in milliseconds over +which sustained power is averaged. + +See power1_max_enable power1_max power1_max_interval + + Only supported for particular Intel i915 graphics platforms. + +What: /sys/devices/.../hwmon/hwmon/power1_cap_enable +Date: June 2021 +KernelVersion: 5.14 +Contact:dri-de...@lists.freedesktop.org +Description: + RW. Power burst limit is enabled - true or false + +See power1_cap_enable power1_cap + + Only supported for particular Intel i915 graphics platforms. + +What: /sys/devices/.../hwmon/hwmon/power1_cap +Date: June 2021 +KernelVersion: 5.14 +Contact:dri-de...@lists.freedesktop.org +Description: + RW. Power burst limit in milliwatts. + +See power1_cap_enable power1_cap + + Only supported for particular Intel i915 graphics platforms. + +What: /sys/devices/.../hwmon/hwmon/power_default_limit +Date: June 2021 +KernelVersion: 5.14 +Contact:dri-de...@lists.freedesktop.org +Description: +RO. Default power limit. + + Only supported for particular Intel i915 graphics platforms. +
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/vgem: Fix the pitch to be 64 byte aligned for Intel platforms
== Series Details == Series: drm/vgem: Fix the pitch to be 64 byte aligned for Intel platforms URL : https://patchwork.freedesktop.org/series/90841/ State : warning == Summary == $ dim checkpatch origin/drm-tip 790054616b42 drm/vgem: Fix the pitch to be 64 byte aligned for Intel platforms -:15: ERROR:GERRIT_CHANGE_ID: Remove Gerrit Change-Id's before submitting upstream #15: Change-Id: If68914421b1a9432a73af96c8b426045772629eb total: 1 errors, 0 warnings, 0 checks, 8 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/7] dma-buf: Rename dma_resv helpers from _rcu to _unlocked (v2)
Ack on all naming. -Daniel BTW As long as Jason nor you object I will prepare patches for the rename of the functions. Regards, Christian. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add relocation exceptions for two other platforms (rev4)
== Series Details ==
Series: drm/i915: Add relocation exceptions for two other platforms (rev4)
URL : https://patchwork.freedesktop.org/series/89594/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10156 -> Patchwork_20258
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20258/index.html
Known issues
Here are the changes found in Patchwork_20258 that come from known issues:
### IGT changes ###
Warnings
* igt@runner@aborted:
- fi-kbl-r: [FAIL][1] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][2] ([i915#1436] / [i915#3363])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-r/igt@run...@aborted.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20258/fi-kbl-r/igt@run...@aborted.html
- fi-skl-6700k2: [FAIL][3] ([i915#1436] / [i915#3363]) -> [FAIL][4]
([i915#1436] / [i915#2426] / [i915#3363])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-skl-6700k2/igt@run...@aborted.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20258/fi-skl-6700k2/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
Participating hosts (47 -> 42)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_10156 -> Patchwork_20258
CI-20190529: 20190529
CI_DRM_10156: 551125c07e42a44a1b4bf8ad735619f2e315a0e2 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6098: 1fbc1e7d602f96a7f4e2b95057eef994656b8e74 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20258: 41a20f6df2f115353360377f97f73b6c291313d0 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
41a20f6df2f1 drm/i915: Add relocation exceptions for two other platforms
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20258/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/7] dma-buf: Rename dma_resv helpers from _rcu to _unlocked (v2)
Am 01.06.21 um 16:34 schrieb Daniel Vetter:
On Thu, May 27, 2021 at 03:41:02PM +0200, Christian König wrote:
Am 27.05.21 um 15:25 schrieb Daniel Vetter:
On Thu, May 27, 2021 at 1:59 PM Christian König
wrote:
Am 27.05.21 um 12:39 schrieb Daniel Vetter:
On Wed, May 26, 2021 at 12:57:40PM +0200, Christian König wrote:
Am 25.05.21 um 23:17 schrieb Jason Ekstrand:
None of these helpers actually leak any RCU details to the caller. They
all assume you have a genuine reference, take the RCU read lock, and
retry if needed. Naming them with an _rcu is likely to cause callers
more panic than needed.
I'm really wondering if we need this postfix in the first place.
If we use the right rcu_dereference_check() macro then those functions can
be called with both the reservation object locked and unlocked. It shouldn't
matter to them.
But getting rid of the _rcu postfix sounds like a good idea in general to
me.
So does that count as an ack or not? If yes I think we should land this
patch right away, since it's going to conflict real fast badly.
I had some follow up discussion with Jason and I would rather like to
switch to using rcu_dereference_check() in all places and completely
remove the _rcu postfix.
Hm, I'm not sure whether spreading _rcu tricks further is an
especially bright idea. At least i915 is full of very clever _rcu
tricks, and encouraging drivers to roll out their own _rcu everywhere
is probably not in our best interest. Some fast-path checking is imo
ok, but that's it. Especially once we get into the entire
SLAB_TYPESAFE_BY_RCU business it becomes really nasty really quickly.
Oh, yes completely agree. SLAB_TYPESAFE_BY_RCU is optimizing for the wrong
use case I think.
You save a bit of overhead while freeing fences, but in return you have
extra overhead while adding fences to the dma_resv object.
Getting way off topic, but I'm wondering whether the entire rcu business
is really worth it for dma_fence.
Mostly we manipulate dma_resv while holding dma_resv anyway. There's maybe
a few waits and stuff, but I'm not sure whether the dma_resv_lock +
dma_fence_get + dma_resv_unlock + dma_fence_put really matter. And if you
have lock contention on a single buffer you've lost anyway.
At that point I think we have maybe some lockless tricks in the evict
code, but then again once you're evicting it's probably going pretty bad
already.
So SLAB_TYPESAFE_BY_RCU is something I want to analyze for i915 whether
it's really worth it and was justified, or whether we should drop it. But
I'm wondering whether we should drop rcu for fences outright. Would be
quite some audit to check out where it's used.
From i915 side we've done these lockless tricks back when
dev->struct_mutex was a thing and alwas contended. But with per-obj
locking now happening for real with dma-resv, that's probably not
justified.
But then looking at git history the rcu in dma_resv is older than that,
and was justified with ttm.
Scratching my head when and why TTM should have ever needed some
lockless operation when that was added? We do have some now, but just
because they where available.
On the other hand I'm pretty sure that we can make the whole RCU
handling in the dma_resv object much less painful. Basic problem here is
that we have two pointers instead of one, e.g. the excl fence and/or the
shared fences.
If we could move the exclusive fence pointer into the shared fences most
of the trouble would go away suddenly.
The other thing we should certainly have is more use case based
iterators. E.g. something like dma_resv_for_each_sync_fence(...) {...}.
Regards,
Christian.
That's why I'm slightly leaning towards _unlocked variants, except we
do use those in lots of places where we hold dma_resv_lock too. So not
sure what's the best plan overall here.
Well what function names are we actually talking about?
For the dma_resv_get_excl_rcu() case I agree we should probably name that to
dma_resv_get_excl_unlocked() because it makes no sense at all to use this
function while holding the lock.
But for the following functions:
dma_resv_get_fences_rcu
dma_resv_wait_timeout_rcu
dma_resv_test_signaled_rcu
I think we should just drop the _rcu naming because those are supposed to
work independent if the resv lock is held or not.
Ack on all naming.
-Daniel
Regards,
Christian.
-Daniel
But yes I see the pain of rebasing this as well.
Christian.
-Daniel
Christian.
v2 (Jason Ekstrand):
- Fix function argument indentation
Signed-off-by: Jason Ekstrand
Suggested-by: Daniel Vetter
Cc: Christian König
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: Lucas Stach
Cc: Rob Clark
Cc: Sean Paul
Cc: Huang Rui
Cc: Gerd Hoffmann
Cc: VMware Graphics
---
drivers/dma-buf/dma-buf.c | 4 +--
drivers/dma-buf/dma-resv.c| 28 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 ++--
Re: [Intel-gfx] [PATCH v4 04/17] drm/i915/gt: Export the pinned context constructor and destructor
On 6/1/2021 1:20 PM, Rodrigo Vivi wrote:
On Mon, May 24, 2021 at 10:47:50PM -0700, Daniele Ceraolo Spurio wrote:
From: Chris Wilson
Allow internal clients to create a pinned context.
v2 (Daniele): export destructor as well, allow optional usage of custom
vm for maximum flexibility.
Signed-off-by: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_engine.h| 10
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 29 +++
2 files changed, 29 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 47ee8578e511..a64d28aba257 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -18,7 +18,9 @@
#include "intel_workarounds.h"
struct drm_printer;
+struct intel_context;
struct intel_gt;
+struct lock_class_key;
/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
* but keeps the logic simple. Indeed, the whole purpose of this macro is just
@@ -255,6 +257,14 @@ struct i915_request *
intel_engine_find_active_request(struct intel_engine_cs *engine);
u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
+struct intel_context *
+intel_engine_create_pinned_context(struct intel_engine_cs *engine,
+ struct i915_address_space *vm,
+ unsigned int ring_size,
+ unsigned int hwsp,
+ struct lock_class_key *key,
+ const char *name);
+void intel_engine_destroy_pinned_context(struct intel_context *ce);
void intel_engine_init_active(struct intel_engine_cs *engine,
unsigned int subclass);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index eba2da9679a5..8cbf11497e8e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -801,11 +801,13 @@ intel_engine_init_active(struct intel_engine_cs *engine,
unsigned int subclass)
#endif
}
-static struct intel_context *
-create_pinned_context(struct intel_engine_cs *engine,
- unsigned int hwsp,
- struct lock_class_key *key,
- const char *name)
+struct intel_context *
+intel_engine_create_pinned_context(struct intel_engine_cs *engine,
+ struct i915_address_space *vm,
+ unsigned int ring_size,
+ unsigned int hwsp,
+ struct lock_class_key *key,
+ const char *name)
{
struct intel_context *ce;
int err;
@@ -816,6 +818,12 @@ create_pinned_context(struct intel_engine_cs *engine,
__set_bit(CONTEXT_BARRIER_BIT, >flags);
ce->timeline = page_pack_bits(NULL, hwsp);
+ ce->ring = __intel_context_ring_size(ring_size);
why do we need this now and we didn't need before?
Since we're now exporting the function as a more "official" interface,
the idea was to provide as much flexibility as possible. The ring size
could be used if e.g. we decide to use more pxp sessions and therefore
need more space in the ring to insert instructions. Same for the vm below.
Daniele
+
+ if (vm) {
+ i915_vm_put(ce->vm);
+ ce->vm = i915_vm_get(vm);
+ }
same question here...
err = intel_context_pin(ce); /* perma-pin so it is always available */
if (err) {
@@ -834,7 +842,7 @@ create_pinned_context(struct intel_engine_cs *engine,
return ce;
}
-static void destroy_pinned_context(struct intel_context *ce)
+void intel_engine_destroy_pinned_context(struct intel_context *ce)
{
struct intel_engine_cs *engine = ce->engine;
struct i915_vma *hwsp = engine->status_page.vma;
@@ -854,8 +862,9 @@ create_kernel_context(struct intel_engine_cs *engine)
{
static struct lock_class_key kernel;
- return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR,
-, "kernel_context");
+ return intel_engine_create_pinned_context(engine, NULL, SZ_4K,
+ I915_GEM_HWS_SEQNO_ADDR,
+ , "kernel_context");
}
/**
@@ -898,7 +907,7 @@ static int engine_init_common(struct intel_engine_cs
*engine)
return 0;
err_context:
- destroy_pinned_context(ce);
+ intel_engine_destroy_pinned_context(ce);
return ret;
}
@@ -956,7 +965,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
fput(engine->default_state);
if (engine->kernel_context)
- destroy_pinned_context(engine->kernel_context);
+
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/1] drm/i915/hdcp: Simplify code in intel_hdcp_auth_downstream()
== Series Details == Series: series starting with [1/1] drm/i915/hdcp: Simplify code in intel_hdcp_auth_downstream() URL : https://patchwork.freedesktop.org/series/90834/ State : success == Summary == CI Bug Log - changes from CI_DRM_10156 -> Patchwork_20257 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20257/index.html Known issues Here are the changes found in Patchwork_20257 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20257/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [PASS][2] -> [FAIL][3] ([i915#49]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20257/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[INCOMPLETE][4] ([i915#2782]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20257/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html Warnings * igt@i915_selftest@live@execlists: - fi-bsw-kefka: [INCOMPLETE][6] ([i915#2782] / [i915#2940] / [i915#3462]) -> [DMESG-FAIL][7] ([i915#3462]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20257/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html - fi-cml-s: [DMESG-FAIL][8] ([i915#3462]) -> [INCOMPLETE][9] ([i915#3462]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-cml-s/igt@i915_selftest@l...@execlists.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20257/fi-cml-s/igt@i915_selftest@l...@execlists.html * igt@runner@aborted: - fi-glk-dsi: [FAIL][10] ([i915#2426] / [i915#3363] / [k.org#202321]) -> [FAIL][11] ([i915#3363] / [k.org#202321]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-glk-dsi/igt@run...@aborted.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20257/fi-glk-dsi/igt@run...@aborted.html - fi-kbl-r: [FAIL][12] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][13] ([i915#1436] / [i915#3363]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-r/igt@run...@aborted.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20257/fi-kbl-r/igt@run...@aborted.html - fi-kbl-soraka: [FAIL][14] ([i915#1436] / [i915#3363]) -> [FAIL][15] ([i915#1436] / [i915#2426] / [i915#3363]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-soraka/igt@run...@aborted.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20257/fi-kbl-soraka/igt@run...@aborted.html - fi-kbl-7500u: [FAIL][16] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][17] ([i915#1436] / [i915#3363]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-7500u/igt@run...@aborted.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20257/fi-kbl-7500u/igt@run...@aborted.html - fi-cml-u2: [FAIL][18] ([i915#3363] / [i915#3462]) -> [FAIL][19] ([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-cml-u2/igt@run...@aborted.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20257/fi-cml-u2/igt@run...@aborted.html - fi-skl-6700k2: [FAIL][20] ([i915#1436] / [i915#3363]) -> [FAIL][21] ([i915#1436] / [i915#2426] / [i915#3363]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-skl-6700k2/igt@run...@aborted.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20257/fi-skl-6700k2/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321 Participating hosts (47 -> 41)
Re: [Intel-gfx] [PATCH v4 08/17] drm/i915/pxp: Create the arbitrary session after boot
On Mon, May 24, 2021 at 10:47:54PM -0700, Daniele Ceraolo Spurio wrote:
> From: "Huang, Sean Z"
>
> Create the arbitrary session, with the fixed session id 0xf, after
> system boot,
We will have to change this and only create on-demand.
Then delete when no one is using... but this will be a follow-up.
Also let's add this patch for preserving history and credits as well.
> for the case that application allocates the protected
> buffer without establishing any protection session. Because the
> hardware requires at least one alive session for protected buffer
> creation. This arbitrary session will need to be re-created after
> teardown or power event because hardware encryption key won't be
> valid after such cases.
>
> The session ID is exposed as part of the uapi so it can be used as part
> of userspace commands.
>
> v2: use gt->uncore->rpm (Chris)
> v3: s/arb_is_in_play/arb_is_valid (Chris), move set-up to the new
> init_hw function
> v4: move interface defs to separate header, set arb_is valid to false
> on fini (Rodrigo)
>
> Signed-off-by: Huang, Sean Z
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 5 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 74 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 15
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 68 +
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +
> .../drm/i915/pxp/intel_pxp_tee_interface.h| 37 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 9 +++
> include/uapi/drm/i915_drm.h | 3 +
> 10 files changed, 220 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 0dfff52fea24..739510549545 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -276,6 +276,7 @@ i915-y += i915_perf.o
> # Protected execution platform (PXP) support
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> + pxp/intel_pxp_session.o \
> pxp/intel_pxp_tee.o
>
> # Post-mortem debug and GPU hang state capture
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index ab19d2a23ec2..4e30e5e98522 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -3,6 +3,7 @@
> * Copyright(c) 2020 Intel Corporation.
> */
> #include "intel_pxp.h"
> +#include "intel_pxp_session.h"
> #include "intel_pxp_tee.h"
> #include "gt/intel_context.h"
> #include "i915_drv.h"
> @@ -86,6 +87,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
> if (!intel_pxp_is_enabled(pxp))
> return;
>
> + pxp->arb_is_valid = false;
> +
> intel_pxp_tee_component_fini(pxp);
>
> destroy_vcs_context(pxp);
> @@ -94,6 +97,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
> void intel_pxp_init_hw(struct intel_pxp *pxp)
> {
> kcr_pxp_enable(pxp_to_gt(pxp));
> +
> + intel_pxp_create_arb_session(pxp);
> }
>
> void intel_pxp_fini_hw(struct intel_pxp *pxp)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 5427c3b28aa9..8eeb65af78b1 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -19,6 +19,11 @@ static inline bool intel_pxp_is_enabled(const struct
> intel_pxp *pxp)
> return pxp->ce;
> }
>
> +static inline bool intel_pxp_is_active(const struct intel_pxp *pxp)
> +{
> + return pxp->arb_is_valid;
> +}
> +
> #ifdef CONFIG_DRM_I915_PXP
> void intel_pxp_init(struct intel_pxp *pxp);
> void intel_pxp_fini(struct intel_pxp *pxp);
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> new file mode 100644
> index ..3331868f354c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "drm/i915_drm.h"
> +#include "i915_drv.h"
> +
> +#include "intel_pxp.h"
> +#include "intel_pxp_session.h"
> +#include "intel_pxp_tee.h"
> +#include "intel_pxp_types.h"
> +
> +#define ARB_SESSION I915_PROTECTED_CONTENT_DEFAULT_SESSION /* shorter define
> */
> +
> +#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
> +
> +static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + intel_wakeref_t wakeref;
> + u32 sip = 0;
> +
> +
Re: [Intel-gfx] [PATCH v4 06/17] drm/i915/pxp: Implement funcs to create the TEE channel
On Mon, May 24, 2021 at 10:47:52PM -0700, Daniele Ceraolo Spurio wrote:
> From: "Huang, Sean Z"
>
> Implement the funcs to create the TEE channel, so kernel can
> send the TEE commands directly to TEE for creating the arbitrary
> (default) session.
>
> v2: fix locking, don't pollute dev_priv (Chris)
>
> v3: wait for mei PXP component to be bound.
good idea. it would be useful for the case where the mei side was
checking for the version instead i915 for instance...
>
> Signed-off-by: Huang, Sean Z
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Reviewed-by: Rodrigo Vivi #v2
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/Makefile | 3 +-
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 13
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 87 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 3 +
> 5 files changed, 119 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index efd950122e40..0dfff52fea24 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -275,7 +275,8 @@ i915-y += i915_perf.o
>
> # Protected execution platform (PXP) support
> i915-$(CONFIG_DRM_I915_PXP) += \
> - pxp/intel_pxp.o
> + pxp/intel_pxp.o \
> + pxp/intel_pxp_tee.o
>
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 3255c6da34e8..5df2a09c9e4b 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -3,6 +3,7 @@
> * Copyright(c) 2020 Intel Corporation.
> */
> #include "intel_pxp.h"
> +#include "intel_pxp_tee.h"
> #include "gt/intel_context.h"
> #include "i915_drv.h"
>
> @@ -50,7 +51,16 @@ void intel_pxp_init(struct intel_pxp *pxp)
> if (ret)
> return;
>
> + ret = intel_pxp_tee_component_init(pxp);
> + if (ret)
> + goto out_context;
> +
> drm_info(>i915->drm, "Protected Xe Path (PXP) protected content
> support initialized\n");
> +
> + return;
> +
> +out_context:
> + destroy_vcs_context(pxp);
> }
>
> void intel_pxp_fini(struct intel_pxp *pxp)
> @@ -58,5 +68,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
> if (!intel_pxp_is_enabled(pxp))
> return;
>
> + intel_pxp_tee_component_fini(pxp);
> +
> destroy_vcs_context(pxp);
> +
> }
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> new file mode 100644
> index ..4ed234d8584f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -0,0 +1,87 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +
> +#include
> +#include "drm/i915_pxp_tee_interface.h"
> +#include "drm/i915_component.h"
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_tee.h"
> +
> +static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
> +{
> + return _to_i915(i915_kdev)->gt.pxp;
> +}
> +
> +/**
> + * i915_pxp_tee_component_bind - bind function to pass the function pointers
> to pxp_tee
> + * @i915_kdev: pointer to i915 kernel device
> + * @tee_kdev: pointer to tee kernel device
> + * @data: pointer to pxp_tee_master containing the function pointers
> + *
> + * This bind function is called during the system boot or resume from system
> sleep.
> + *
> + * Return: return 0 if successful.
> + */
> +static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> +struct device *tee_kdev, void *data)
> +{
> + struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
> +
> + pxp->pxp_component = data;
> + pxp->pxp_component->tee_dev = tee_kdev;
> +
> + return 0;
> +}
> +
> +static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
> + struct device *tee_kdev, void *data)
> +{
> + struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
> +
> + pxp->pxp_component = NULL;
> +}
> +
> +static const struct component_ops i915_pxp_tee_component_ops = {
> + .bind = i915_pxp_tee_component_bind,
> + .unbind = i915_pxp_tee_component_unbind,
> +};
> +
> +int intel_pxp_tee_component_init(struct intel_pxp *pxp)
> +{
> + int ret;
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + struct drm_i915_private *i915 = gt->i915;
> +
> + ret = component_add_typed(i915->drm.dev, _pxp_tee_component_ops,
> + I915_COMPONENT_PXP);
> + if (ret < 0) {
> + drm_err(>drm, "Failed to add PXP component (%d)\n", ret);
> + return ret;
> + }
> +
> + /*
>
Re: [Intel-gfx] [PATCH v4 05/17] drm/i915/pxp: allocate a vcs context for pxp usage
On Mon, May 24, 2021 at 10:47:51PM -0700, Daniele Ceraolo Spurio wrote:
> The context is required to send the session termination commands to the
> VCS, which will be implemented in a follow-up patch. We can also use the
> presence of the context as a check of pxp initialization completion.
>
> v2: use perma-pinned context (Chris)
> v3: rename pinned_context functions (Chris)
> v4: split export of pinned_context functions to a separate patch (Rodrigo)
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/Makefile | 4 ++
> drivers/gpu/drm/i915/gt/intel_engine.h | 2 +
> drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 62 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 35
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 15 ++
> 7 files changed, 126 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 6947495bf34b..efd950122e40 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -273,6 +273,10 @@ i915-y += \
>
> i915-y += i915_perf.o
>
> +# Protected execution platform (PXP) support
> +i915-$(CONFIG_DRM_I915_PXP) += \
> + pxp/intel_pxp.o
> +
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> i915-$(CONFIG_DRM_I915_SELFTEST) += \
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> b/drivers/gpu/drm/i915/gt/intel_engine.h
> index a64d28aba257..903e498beb0b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -187,6 +187,8 @@ intel_write_status_page(struct intel_engine_cs *engine,
> int reg, u32 value)
> #define I915_GEM_HWS_PREEMPT_ADDR(I915_GEM_HWS_PREEMPT * sizeof(u32))
> #define I915_GEM_HWS_SEQNO 0x40
> #define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO *
> sizeof(u32))
> +#define I915_GEM_HWS_PXP 0x60
> +#define I915_GEM_HWS_PXP_ADDR(I915_GEM_HWS_PXP * sizeof(u32))
> #define I915_GEM_HWS_SCRATCH 0x80
>
> #define I915_HWS_CSB_BUF0_INDEX 0x10
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 8d77dcbad059..68f42fabc151 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -20,6 +20,7 @@
> #include "intel_uncore.h"
> #include "intel_pm.h"
> #include "shmem_utils.h"
> +#include "pxp/intel_pxp.h"
>
> void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> {
> @@ -627,6 +628,8 @@ int intel_gt_init(struct intel_gt *gt)
> if (err)
> goto err_gt;
>
> + intel_pxp_init(>pxp);
As we discussed today, we will need to move this earlier in the
initialization...
> +
> goto out_fw;
> err_gt:
> __intel_gt_disable(gt);
> @@ -661,6 +664,8 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
>
> intel_rps_driver_unregister(>rps);
>
> + intel_pxp_fini(>pxp);
> +
> /*
>* Upon unregistering the device to prevent any new users, cancel
>* all in-flight requests so that we can quickly unbind the active
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 0caf6ca0a784..53f44fd4a974 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -25,6 +25,7 @@
> #include "intel_rc6_types.h"
> #include "intel_rps_types.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp_types.h"
>
> struct drm_i915_private;
> struct i915_ggtt;
> @@ -148,6 +149,8 @@ struct intel_gt {
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
> } info;
> +
> + struct intel_pxp pxp;
> };
>
> enum intel_gt_scratch_field {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> new file mode 100644
> index ..3255c6da34e8
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -0,0 +1,62 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +#include "intel_pxp.h"
> +#include "gt/intel_context.h"
> +#include "i915_drv.h"
> +
> +static int create_vcs_context(struct intel_pxp *pxp)
> +{
> + static struct lock_class_key pxp_lock;
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + struct intel_engine_cs *engine;
> + struct intel_context *ce;
> +
> + /*
> + * Find the first VCS engine present. We're guaranteed there is one
> + * if we're in this function due to the check in has_pxp
> + */
> + for
Re: [Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL
On Tue, Jun 01, 2021 at 05:52:48PM +0300, Stanislav Lisovskiy wrote:
> From: Gwan-gyeong Mun
Aren't you (Stan) the original author of this patch? It looks like the
authorship got changed accidentally in one of the preparation rebases.
A couple other quick drive-by comments below.
>
> CDCLK crawl feature allows to change CDCLK frequency
> without disabling the actual PLL and doesn't require
> a full modeset.
>
> Cc: Mika Kahola
> Signed-off-by: Stanislav Lisovskiy
> Signed-off-by: Jani Nikula
> Signed-off-by: Gwan-gyeong Mun
> Cc: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++---
> drivers/gpu/drm/i915/i915_reg.h| 2 +
> 2 files changed, 65 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 618a9e1e2b0c..b9abed82328c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1548,6 +1548,35 @@ static void cnl_cdclk_pll_enable(struct
> drm_i915_private *dev_priv, int vco)
> dev_priv->cdclk.hw.vco = vco;
> }
>
> +static bool has_cdclk_crawl(struct drm_i915_private *i915)
> +{
> + return IS_ALDERLAKE_P(i915);
> +}
Would it make sense to make this a feature flag in the device info
structure?
> +
> +static void gen13_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
Function name prefix should either be "adlp" or "xelpd." Probably
"adlp" in this case since I think this functionality relates more to the
platform itself than the display architecture version.
Matt
> +{
> + int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
> + u32 val;
> +
> + /* Write PLL ratio without disabling */
> + val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
> + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> +
> + /* Submit freq change request */
> + val |= BXT_DE_PLL_FREQ_REQ;
> + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> +
> + /* Timeout 200us */
> + if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
> + BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
> + DRM_ERROR("timeout waiting for FREQ change request ack\n");
> +
> + val &= ~BXT_DE_PLL_FREQ_REQ;
> + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
> +
> + dev_priv->cdclk.hw.vco = vco;
> +}
> +
> static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe
> pipe)
> {
> if (DISPLAY_VER(dev_priv) >= 12) {
> @@ -1620,14 +1649,16 @@ static void bxt_set_cdclk(struct drm_i915_private
> *dev_priv,
> return;
> }
>
> - if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
> + if (has_cdclk_crawl(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0)
> {
> + if (dev_priv->cdclk.hw.vco != vco)
> + gen13_cdclk_pll_crawl(dev_priv, vco);
> + } else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
> if (dev_priv->cdclk.hw.vco != 0 &&
> dev_priv->cdclk.hw.vco != vco)
> cnl_cdclk_pll_disable(dev_priv);
>
> if (dev_priv->cdclk.hw.vco != vco)
> cnl_cdclk_pll_enable(dev_priv, vco);
> -
> } else {
> if (dev_priv->cdclk.hw.vco != 0 &&
> dev_priv->cdclk.hw.vco != vco)
> @@ -1820,6 +1851,28 @@ void intel_cdclk_uninit_hw(struct drm_i915_private
> *i915)
> skl_cdclk_uninit_hw(i915);
> }
>
> +static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_config *a,
> + const struct intel_cdclk_config *b)
> +{
> + int a_div, b_div;
> +
> + if (!has_cdclk_crawl(dev_priv))
> + return false;
> +
> + /*
> + * The vco and cd2x divider will change independently
> + * from each, so we disallow cd2x change when crawling.
> + */
> + a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
> + b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
> +
> + return a->vco != 0 && b->vco != 0 &&
> + a->vco != b->vco &&
> + a_div == b_div &&
> + a->ref == b->ref;
> +}
> +
> /**
> * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
> * configurations requires a modeset on all pipes
> @@ -2475,7 +2528,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
> *state)
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> const struct intel_cdclk_state *old_cdclk_state;
> struct intel_cdclk_state *new_cdclk_state;
> - enum pipe pipe;
> + enum pipe pipe = INVALID_PIPE;
> int ret;
>
> new_cdclk_state = intel_atomic_get_cdclk_state(state);
> @@ -2527,15 +2580,18 @@ int intel_modeset_calc_cdclk(struct
> intel_atomic_state *state)
>
Re: [Intel-gfx] [PATCH v4 04/17] drm/i915/gt: Export the pinned context constructor and destructor
On Mon, May 24, 2021 at 10:47:50PM -0700, Daniele Ceraolo Spurio wrote:
> From: Chris Wilson
>
> Allow internal clients to create a pinned context.
>
> v2 (Daniele): export destructor as well, allow optional usage of custom
> vm for maximum flexibility.
>
> Signed-off-by: Chris Wilson
> Signed-off-by: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h| 10
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 29 +++
> 2 files changed, 29 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 47ee8578e511..a64d28aba257 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -18,7 +18,9 @@
> #include "intel_workarounds.h"
>
> struct drm_printer;
> +struct intel_context;
> struct intel_gt;
> +struct lock_class_key;
>
> /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is
> overkill,
> * but keeps the logic simple. Indeed, the whole purpose of this macro is
> just
> @@ -255,6 +257,14 @@ struct i915_request *
> intel_engine_find_active_request(struct intel_engine_cs *engine);
>
> u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
> +struct intel_context *
> +intel_engine_create_pinned_context(struct intel_engine_cs *engine,
> +struct i915_address_space *vm,
> +unsigned int ring_size,
> +unsigned int hwsp,
> +struct lock_class_key *key,
> +const char *name);
> +void intel_engine_destroy_pinned_context(struct intel_context *ce);
>
> void intel_engine_init_active(struct intel_engine_cs *engine,
> unsigned int subclass);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index eba2da9679a5..8cbf11497e8e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -801,11 +801,13 @@ intel_engine_init_active(struct intel_engine_cs
> *engine, unsigned int subclass)
> #endif
> }
>
> -static struct intel_context *
> -create_pinned_context(struct intel_engine_cs *engine,
> - unsigned int hwsp,
> - struct lock_class_key *key,
> - const char *name)
> +struct intel_context *
> +intel_engine_create_pinned_context(struct intel_engine_cs *engine,
> +struct i915_address_space *vm,
> +unsigned int ring_size,
> +unsigned int hwsp,
> +struct lock_class_key *key,
> +const char *name)
> {
> struct intel_context *ce;
> int err;
> @@ -816,6 +818,12 @@ create_pinned_context(struct intel_engine_cs *engine,
>
> __set_bit(CONTEXT_BARRIER_BIT, >flags);
> ce->timeline = page_pack_bits(NULL, hwsp);
> + ce->ring = __intel_context_ring_size(ring_size);
why do we need this now and we didn't need before?
> +
> + if (vm) {
> + i915_vm_put(ce->vm);
> + ce->vm = i915_vm_get(vm);
> + }
same question here...
>
> err = intel_context_pin(ce); /* perma-pin so it is always available */
> if (err) {
> @@ -834,7 +842,7 @@ create_pinned_context(struct intel_engine_cs *engine,
> return ce;
> }
>
> -static void destroy_pinned_context(struct intel_context *ce)
> +void intel_engine_destroy_pinned_context(struct intel_context *ce)
> {
> struct intel_engine_cs *engine = ce->engine;
> struct i915_vma *hwsp = engine->status_page.vma;
> @@ -854,8 +862,9 @@ create_kernel_context(struct intel_engine_cs *engine)
> {
> static struct lock_class_key kernel;
>
> - return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR,
> - , "kernel_context");
> + return intel_engine_create_pinned_context(engine, NULL, SZ_4K,
> + I915_GEM_HWS_SEQNO_ADDR,
> + , "kernel_context");
> }
>
> /**
> @@ -898,7 +907,7 @@ static int engine_init_common(struct intel_engine_cs
> *engine)
> return 0;
>
> err_context:
> - destroy_pinned_context(ce);
> + intel_engine_destroy_pinned_context(ce);
> return ret;
> }
>
> @@ -956,7 +965,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs
> *engine)
> fput(engine->default_state);
>
> if (engine->kernel_context)
> - destroy_pinned_context(engine->kernel_context);
> + intel_engine_destroy_pinned_context(engine->kernel_context);
>
> GEM_BUG_ON(!llist_empty(>barrier_tasks));
> cleanup_status_page(engine);
> --
> 2.29.2
>
___
Intel-gfx mailing
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Remove the repeated declaration
== Series Details == Series: drm/i915/gem: Remove the repeated declaration URL : https://patchwork.freedesktop.org/series/90832/ State : success == Summary == CI Bug Log - changes from CI_DRM_10156 -> Patchwork_20254 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/index.html Known issues Here are the changes found in Patchwork_20254 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@module-reload: - fi-kbl-guc: [PASS][1] -> [FAIL][2] ([i915#2203] / [i915#579]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-guc/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/fi-kbl-guc/igt@i915_pm_...@module-reload.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a: - fi-tgl-u2: [PASS][3] -> [FAIL][4] ([i915#3487]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-tgl-u2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/fi-tgl-u2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-a.html Warnings * igt@i915_selftest@live@execlists: - fi-icl-u2: [INCOMPLETE][5] ([i915#2782] / [i915#3462]) -> [DMESG-FAIL][6] ([i915#3462]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-icl-u2/igt@i915_selftest@l...@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/fi-icl-u2/igt@i915_selftest@l...@execlists.html * igt@runner@aborted: - fi-kbl-x1275: [FAIL][7] ([i915#1436] / [i915#3363]) -> [FAIL][8] ([i915#1436] / [i915#2426] / [i915#3363]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-x1275/igt@run...@aborted.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/fi-kbl-x1275/igt@run...@aborted.html - fi-icl-u2: [FAIL][9] ([i915#2782] / [i915#3363]) -> [FAIL][10] ([i915#2426] / [i915#2782] / [i915#3363]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-icl-u2/igt@run...@aborted.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/fi-icl-u2/igt@run...@aborted.html - fi-glk-dsi: [FAIL][11] ([i915#2426] / [i915#3363] / [k.org#202321]) -> [FAIL][12] ([i915#3363] / [k.org#202321]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-glk-dsi/igt@run...@aborted.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/fi-glk-dsi/igt@run...@aborted.html - fi-kbl-r: [FAIL][13] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][14] ([i915#1436] / [i915#3363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-r/igt@run...@aborted.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/fi-kbl-r/igt@run...@aborted.html - fi-kbl-soraka: [FAIL][15] ([i915#1436] / [i915#3363]) -> [FAIL][16] ([i915#1436] / [i915#2426] / [i915#3363]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-soraka/igt@run...@aborted.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/fi-kbl-soraka/igt@run...@aborted.html - fi-kbl-7500u: [FAIL][17] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][18] ([i915#1436] / [i915#3363]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-7500u/igt@run...@aborted.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20254/fi-kbl-7500u/igt@run...@aborted.html [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462 [i915#3487]: https://gitlab.freedesktop.org/drm/intel/issues/3487 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321 Participating hosts (47 -> 42) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_10156 -> Patchwork_20254 CI-20190529: 20190529 CI_DRM_10156: 551125c07e42a44a1b4bf8ad735619f2e315a0e2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6098: 1fbc1e7d602f96a7f4e2b95057eef994656b8e74 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_20254: e5e281ad8710fe3d2f5bcf1927159866baef99c8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e5e281ad8710 drm/i915/gem: Remove the repeated declaration == Logs == For more details see:
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Restricted DMA (rev5)
== Series Details == Series: Restricted DMA (rev5) URL : https://patchwork.freedesktop.org/series/89341/ State : failure == Summary == Applying: swiotlb: Refactor swiotlb init functions Applying: swiotlb: Refactor swiotlb_create_debugfs Applying: swiotlb: Add DMA_RESTRICTED_POOL Applying: swiotlb: Add restricted DMA pool initialization Using index info to reconstruct a base tree... M drivers/base/core.c M include/linux/device.h M include/linux/swiotlb.h M kernel/dma/swiotlb.c Falling back to patching base and 3-way merge... Auto-merging kernel/dma/swiotlb.c CONFLICT (content): Merge conflict in kernel/dma/swiotlb.c Auto-merging include/linux/swiotlb.h CONFLICT (content): Merge conflict in include/linux/swiotlb.h Auto-merging include/linux/device.h CONFLICT (content): Merge conflict in include/linux/device.h Auto-merging drivers/base/core.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0004 swiotlb: Add restricted DMA pool initialization When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] regression on fedora 5.12 on Lenovo T400
On Tue, May 25, 2021 at 04:28:20PM +1000, Dave Airlie wrote:
> https://bugzilla.redhat.com/show_bug.cgi?id=1964252
>
> dmesg below.
> Feel free to point me at any fixes already in flight.
Hi Dave,
sorry for the delay here, but I'd like to just confirm if we are on the
same page that this got fixed with this patch:
036867e93ebf ("drm/i915/gem: Pin the L-shape quirked object as unshrinkable")
is this your current understanding?
>
> Dave.
>
> [ 140.302041] list_add double add: new=9ed109790fe0,
> prev=9ed109790fe0, next=9ed109465b38.
> [ 140.302076] [ cut here ]
> [ 140.302078] kernel BUG at lib/list_debug.c:29!
> [ 140.302091] invalid opcode: [#1] SMP PTI
> [ 140.302097] CPU: 1 PID: 1712 Comm: Xorg Kdump: loaded Tainted: G
> I 5.12.5-300.fc34.x86_64 #1
> [ 140.302103] Hardware name: LENOVO 6475H82/6475H82, BIOS 7UET91WW
> (3.21 ) 12/06/2010
> [ 140.302106] RIP: 0010:__list_add_valid.cold+0x26/0x3f
> [ 140.302117] Code: ee c1 a6 ff 4c 89 c1 48 c7 c7 f8 4d 41 9b e8 12
> 2c fe ff 0f 0b 48 89 f2 4c 89 c1 48 89 fe 48 c7 c7 a8 4e 41 9b e8 fb
> 2b fe ff <0f> 0b 48 89 d1 4c 89 c6 4c 89 ca 48 c7 c7 50 4e 41 9b e8 e4
> 2b fe
> [ 140.302122] RSP: 0018:ad63c0cbfcf8 EFLAGS: 00010082
> [ 140.302127] RAX: 0058 RBX: 9ed109790d00 RCX:
>
> [ 140.302131] RDX: 9ed137ca6720 RSI: 9ed137c985c0 RDI:
> 9ed137c985c0
> [ 140.302135] RBP: 9ed109465b38 R08: R09:
> ad63c0cbfb30
> [ 140.302139] R10: ad63c0cbfb28 R11: 9bb45f28 R12:
> 9ed10946
> [ 140.302142] R13: 0246 R14: 9ed109465b20 R15:
> 9ed109790fe0
> [ 140.302146] FS: 7f0edf882a80() GS:9ed137c8()
> knlGS:
> [ 140.302151] CS: 0010 DS: ES: CR0: 80050033
> [ 140.302155] CR2: 7f0ed7ba2001 CR3: 00011ff34000 CR4:
> 000406e0
> [ 140.302159] Call Trace:
> [ 140.302166] __i915_gem_object_make_shrinkable+0xa5/0xe0 [i915]
> [ 140.302330] i915_gem_object_set_tiling+0x4fe/0x530 [i915]
> [ 140.302473] i915_gem_set_tiling_ioctl+0x112/0x250 [i915]
> [ 140.302613] ? i915_gem_object_set_tiling+0x530/0x530 [i915]
> [ 140.302755] drm_ioctl_kernel+0x86/0xd0 [drm]
> [ 140.302819] drm_ioctl+0x20f/0x3c0 [drm]
> [ 140.302870] ? i915_gem_object_set_tiling+0x530/0x530 [i915]
> [ 140.303013] __x64_sys_ioctl+0x82/0xb0
> [ 140.303020] do_syscall_64+0x33/0x40
> [ 140.303026] entry_SYSCALL_64_after_hwframe+0x44/0xae
> [ 140.303033] RIP: 0033:0x7f0ee01070ab
> [ 140.303038] Code: ff ff ff 85 c0 79 9b 49 c7 c4 ff ff ff ff 5b 5d
> 4c 89 e0 41 5c c3 66 0f 1f 84 00 00 00 00 00 f3 0f 1e fa b8 10 00 00
> 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 95 bd 0c 00 f7 d8 64 89
> 01 48
> [ 140.303043] RSP: 002b:7ffc7bf48ff8 EFLAGS: 0246 ORIG_RAX:
> 0010
> [ 140.303048] RAX: ffda RBX: 55c6591c78d0 RCX:
> 7f0ee01070ab
> [ 140.303052] RDX: 7ffc7bf49010 RSI: c0106461 RDI:
> 0011
> [ 140.303056] RBP: 7ffc7bf49060 R08: 55c6583b39e0 R09:
>
> [ 140.303059] R10: 7f0ee01d3a00 R11: 0246 R12:
>
> [ 140.303063] R13: 55c6583b38c0 R14: c0106461 R15:
> 7ffc7bf49010
> [ 140.303069] Modules linked in: xt_CHECKSUM xt_MASQUERADE
> xt_conntrack ipt_REJECT nf_nat_tftp nf_conntrack_tftp bridge stp llc
> nft_objref nf_conntrack_netbios_ns nf_conntrack_broadcast nft_fib_inet
> nft_fib_ipv4 nft_fib_ipv6 nft_fib nft_reject_inet nf_reject_ipv4
> nf_reject_ipv6 nft_reject nft_ct nft_chain_nat ip6table_nat
> ip6table_mangle ip6table_raw ip6table_security iptable_nat nf_nat
> nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 iptable_mangle iptable_raw
> iptable_security ip_set nf_tables nfnetlink ip6table_filter ip6_tables
> iptable_filter sunrpc coretemp kvm_intel iTCO_wdt kvm intel_pmc_bxt
> mei_wdt iTCO_vendor_support snd_hda_codec_conexant
> snd_hda_codec_generic snd_hda_intel snd_intel_dspcfg
> snd_intel_sdw_acpi irqbypass snd_hda_codec joydev snd_hda_core
> snd_hwdep pcspkr wmi_bmof snd_seq i2c_i801 i2c_smbus thinkpad_acpi
> snd_seq_device snd_pcm platform_profile snd_timer ledtrig_audio snd
> rfkill soundcore mei_me mei lpc_ich zram ip_tables i915 i2c_algo_bit
> drm_kms_helper cec e1000e
> [ 140.303171] firewire_ohci serio_raw firewire_core drm yenta_socket
> crc_itu_t wmi video fuse
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 1/9] drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
On Fri, 21 May 2021, Rodrigo Vivi wrote:
> On Fri, May 14, 2021 at 02:14:55PM -0400, Lyude Paul wrote:
>> Noticed this while moving all of the VESA backlight code in i915 over to
>> DRM helpers: it would appear that we calculate the frequency value we want
>> to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never
>> actually changes during runtime. So, let's simplify things by just caching
>> this value in intel_panel.backlight, and re-writing it as-needed.
>>
>> Changes since v1:
>> * Wrap panel->backlight.edp.vesa.pwm_freq_pre_divider in
>> DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP check - Jani
>
> This looks okay to me now... Jani, agree?
Reviewed-by: Jani Nikula
>
>>
>> Signed-off-by: Lyude Paul
>> Cc: Jani Nikula
>> Cc: Dave Airlie
>> Cc: greg.depo...@gmail.com
>> ---
>> .../drm/i915/display/intel_display_types.h| 1 +
>> .../drm/i915/display/intel_dp_aux_backlight.c | 65 ++-
>> 2 files changed, 20 insertions(+), 46 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 9c0adfc60c6f..7054a37363fb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -311,6 +311,7 @@ struct intel_panel {
>> union {
>> struct {
>> u8 pwmgen_bit_count;
>> +u8 pwm_freq_pre_divider;
>> } vesa;
>> struct {
>> bool sdr_uses_aux;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> index 8e9ac9ba1d38..68bfe50ada59 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> @@ -373,50 +373,6 @@ intel_dp_aux_vesa_set_backlight(const struct
>> drm_connector_state *conn_state,
>> }
>> }
>>
>> -/*
>> - * Set PWM Frequency divider to match desired frequency in vbt.
>> - * The PWM Frequency is calculated as 27Mhz / (F x P).
>> - * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of
>> the
>> - * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
>> - * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
>> - * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
>> - */
>> -static bool intel_dp_aux_vesa_set_pwm_freq(struct intel_connector
>> *connector)
>> -{
>> -struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>> -struct intel_dp *intel_dp = intel_attached_dp(connector);
>> -const u8 pn = connector->panel.backlight.edp.vesa.pwmgen_bit_count;
>> -int freq, fxp, f, fxp_actual, fxp_min, fxp_max;
>> -
>> -freq = dev_priv->vbt.backlight.pwm_freq_hz;
>> -if (!freq) {
>> -drm_dbg_kms(_priv->drm,
>> -"Use panel default backlight frequency\n");
>> -return false;
>> -}
>> -
>> -fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
>> -f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
>> -fxp_actual = f << pn;
>> -
>> -/* Ensure frequency is within 25% of desired value */
>> -fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
>> -fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
>> -
>> -if (fxp_min > fxp_actual || fxp_actual > fxp_max) {
>> -drm_dbg_kms(_priv->drm, "Actual frequency out of range\n");
>> -return false;
>> -}
>> -
>> -if (drm_dp_dpcd_writeb(_dp->aux,
>> - DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
>> -drm_dbg_kms(_priv->drm,
>> -"Failed to write aux backlight freq\n");
>> -return false;
>> -}
>> -return true;
>> -}
>> -
>> static void
>> intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state
>> *crtc_state,
>> const struct drm_connector_state
>> *conn_state, u32 level)
>> @@ -459,9 +415,13 @@ intel_dp_aux_vesa_enable_backlight(const struct
>> intel_crtc_state *crtc_state,
>> break;
>> }
>>
>> -if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
>> -if (intel_dp_aux_vesa_set_pwm_freq(connector))
>> +if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
>> +if (drm_dp_dpcd_writeb(_dp->aux,
>> DP_EDP_BACKLIGHT_FREQ_SET,
>> +
>> panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
>> new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
>> +else
>> +drm_dbg_kms(>drm, "Failed to write aux backlight
>> frequency\n");
>> +}
>>
>> if (new_dpcd_buf != dpcd_buf) {
>> if (drm_dp_dpcd_writeb(_dp->aux,
>> @@ -482,6 +442,14 @@ static void intel_dp_aux_vesa_disable_backlight(const
>> struct
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/1] drm/i915/selftests: Fix error return code in live_parallel_switch()
== Series Details == Series: series starting with [1/1] drm/i915/selftests: Fix error return code in live_parallel_switch() URL : https://patchwork.freedesktop.org/series/90831/ State : success == Summary == CI Bug Log - changes from CI_DRM_10156 -> Patchwork_20253 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/index.html Known issues Here are the changes found in Patchwork_20253 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html * igt@gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][2] -> [FAIL][3] ([i915#1888]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html Possible fixes * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[INCOMPLETE][4] ([i915#2782]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html Warnings * igt@runner@aborted: - fi-kbl-x1275: [FAIL][6] ([i915#1436] / [i915#3363]) -> [FAIL][7] ([i915#1436] / [i915#2426] / [i915#3363]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-x1275/igt@run...@aborted.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/fi-kbl-x1275/igt@run...@aborted.html - fi-glk-dsi: [FAIL][8] ([i915#2426] / [i915#3363] / [k.org#202321]) -> [FAIL][9] ([i915#3363] / [k.org#202321]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-glk-dsi/igt@run...@aborted.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/fi-glk-dsi/igt@run...@aborted.html - fi-kbl-r: [FAIL][10] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][11] ([i915#1436] / [i915#3363]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-r/igt@run...@aborted.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/fi-kbl-r/igt@run...@aborted.html - fi-kbl-soraka: [FAIL][12] ([i915#1436] / [i915#3363]) -> [FAIL][13] ([i915#1436] / [i915#2426] / [i915#3363]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-soraka/igt@run...@aborted.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/fi-kbl-soraka/igt@run...@aborted.html - fi-kbl-7500u: [FAIL][14] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][15] ([i915#1436] / [i915#3363]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-7500u/igt@run...@aborted.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/fi-kbl-7500u/igt@run...@aborted.html - fi-skl-6700k2: [FAIL][16] ([i915#1436] / [i915#3363]) -> [FAIL][17] ([i915#1436] / [i915#2426] / [i915#3363]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-skl-6700k2/igt@run...@aborted.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/fi-skl-6700k2/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321 Participating hosts (47 -> 42) -- Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_10156 -> Patchwork_20253 CI-20190529: 20190529 CI_DRM_10156: 551125c07e42a44a1b4bf8ad735619f2e315a0e2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6098: 1fbc1e7d602f96a7f4e2b95057eef994656b8e74 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_20253: aee07aa359eda354f94b2493c53d6d75ceb4f032 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == aee07aa359ed drm/i915/selftests: Fix error return code in live_parallel_switch() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20253/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for lpsp with hdmi/dp outputs
== Series Details == Series: lpsp with hdmi/dp outputs URL : https://patchwork.freedesktop.org/series/90827/ State : success == Summary == CI Bug Log - changes from CI_DRM_10154_full -> Patchwork_20250_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20250_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-clear: - shard-glk: [PASS][1] -> [FAIL][2] ([i915#1888] / [i915#3160]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk9/igt@gem_cre...@create-clear.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-glk8/igt@gem_cre...@create-clear.html * igt@gem_ctx_persistence@idempotent: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-snb7/igt@gem_ctx_persiste...@idempotent.html * igt@gem_ctx_ringsize@active@bcs0: - shard-skl: [PASS][4] -> [INCOMPLETE][5] ([i915#3316]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl8/igt@gem_ctx_ringsize@act...@bcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl8/igt@gem_ctx_ringsize@act...@bcs0.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][6] ([i915#3354]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-snb6/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl2/igt@gem_exec_fair@basic-none-r...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl7/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][9] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-kbl7/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk6/igt@gem_exec_fair@basic-pace-s...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-glk5/igt@gem_exec_fair@basic-pace-s...@rcs0.html - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-tglb7/igt@gem_exec_fair@basic-pace-s...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-tglb6/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2849]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb5/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_reloc@basic-wide-active@rcs0: - shard-snb: NOTRUN -> [FAIL][16] ([i915#2389]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-snb5/igt@gem_exec_reloc@basic-wide-act...@rcs0.html * igt@gem_exec_whisper@basic-fds-forked: - shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#118] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk9/igt@gem_exec_whis...@basic-fds-forked.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-glk6/igt@gem_exec_whis...@basic-fds-forked.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2190]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-apl2/igt@gem_huc_c...@huc-copy.html * igt@gem_mmap_gtt@big-copy: - shard-skl: [PASS][20] -> [FAIL][21] ([i915#307]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl6/igt@gem_mmap_...@big-copy.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-skl6/igt@gem_mmap_...@big-copy.html * igt@gem_mmap_gtt@cpuset-basic-small-copy: - shard-glk: [PASS][22] -> [INCOMPLETE][23] ([i915#2055] / [i915#3468]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk5/igt@gem_mmap_...@cpuset-basic-small-copy.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-glk2/igt@gem_mmap_...@cpuset-basic-small-copy.html * igt@gem_mmap_gtt@cpuset-basic-small-copy-odd: - shard-iclb: NOTRUN -> [INCOMPLETE][24] ([i915#2910] / [i915#3468]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/shard-iclb8/igt@gem_mmap_...@cpuset-basic-small-copy-odd.html -
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/display: Introduce new
intel_psr_pause/resume function
URL : https://patchwork.freedesktop.org/series/90830/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10156 -> Patchwork_20252
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/index.html
Known issues
Here are the changes found in Patchwork_20252 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_frontbuffer_tracking@basic:
- fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#2416])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-tgl-u2/igt@kms_frontbuffer_track...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/fi-tgl-u2/igt@kms_frontbuffer_track...@basic.html
Warnings
* igt@i915_selftest@live@execlists:
- fi-icl-u2: [INCOMPLETE][3] ([i915#2782] / [i915#3462]) ->
[DMESG-FAIL][4] ([i915#3462])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-icl-u2/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/fi-icl-u2/igt@i915_selftest@l...@execlists.html
- fi-tgl-u2: [INCOMPLETE][5] ([i915#3462]) -> [DMESG-FAIL][6]
([i915#3462])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-tgl-u2/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/fi-tgl-u2/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-icl-u2: [FAIL][7] ([i915#2782] / [i915#3363]) -> [FAIL][8]
([i915#2426] / [i915#2782] / [i915#3363])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-icl-u2/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/fi-icl-u2/igt@run...@aborted.html
- fi-glk-dsi: [FAIL][9] ([i915#2426] / [i915#3363] /
[k.org#202321]) -> [FAIL][10] ([i915#3363] / [k.org#202321])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-glk-dsi/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-r: [FAIL][11] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][12] ([i915#1436] / [i915#3363])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-r/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/fi-kbl-r/igt@run...@aborted.html
- fi-kbl-7500u: [FAIL][13] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][14] ([i915#1436] / [i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-7500u/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/fi-kbl-7500u/igt@run...@aborted.html
- fi-kbl-guc: [FAIL][15] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][16] ([i915#1436] / [i915#3363])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-kbl-guc/igt@run...@aborted.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/fi-kbl-guc/igt@run...@aborted.html
- fi-cml-u2: [FAIL][17] ([i915#3363] / [i915#3462]) -> [FAIL][18]
([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-cml-u2/igt@run...@aborted.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/fi-cml-u2/igt@run...@aborted.html
- fi-skl-6700k2: [FAIL][19] ([i915#1436] / [i915#3363]) -> [FAIL][20]
([i915#1436] / [i915#2426] / [i915#3363])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10156/fi-skl-6700k2/igt@run...@aborted.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20252/fi-skl-6700k2/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
[i915#2416]: https://gitlab.freedesktop.org/drm/intel/issues/2416
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (47 -> 41)
--
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan
fi-ctg-p8600 fi-bdw-samus
Build changes
-
* Linux:
Re: [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER
On Tue, Jun 01, 2021 at 09:58:34AM -0700, Matt Roper wrote:
On Thu, May 27, 2021 at 11:16:54AM -0700, Lucas De Marchi wrote:
This was done by the following semantic patch:
Is the commit message here out-of-date? The cocci doesn't appear to
match the diff anymore. IS_GRAPHICS_VER() is the range macro now and
IS_GEN is being replaced with a direct "==" comparison.
not necessarily, it's included in "and friends...". Maybe rewording to
something like "replace gen-based macros with new ver-based ones" would
make it clearer?
Lucas De Marchi
Matt
@@ expression dev_priv, E; @@
- INTEL_GEN(dev_priv) == E
+ IS_GRAPHICS_VER(dev_priv, E)
@@ expression dev_priv; @@
- INTEL_GEN(dev_priv)
+ GRAPHICS_VER(dev_priv)
@@ expression dev_priv; expression E; @@
- IS_GEN(dev_priv, E)
+ IS_GRAPHICS_VER(dev_priv, E)
@@
expression dev_priv;
expression from, until;
@@
- IS_GEN_RANGE(dev_priv, from, until)
+ IS_GRAPHICS_RANGE(dev_priv, from, until)
@def@
expression E;
identifier id =~ "^gen$";
@@
- id = GRAPHICS_VER(E)
+ ver = GRAPHICS_VER(E)
@@
identifier def.id;
@@
- id
+ ver
It also takes care of renaming the variable we assign to GRAPHICS_VER()
so to use "ver" rather than "gen".
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 38 +--
drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 54 +++
.../drm/i915/gt/intel_execlists_submission.c | 18 ++---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 18 ++---
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 34 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 27
.../gpu/drm/i915/gt/intel_gt_clock_utils.c| 12 ++--
drivers/gpu/drm/i915/gt/intel_gt_irq.c| 6 +-
drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 10 +--
drivers/gpu/drm/i915/gt/intel_gtt.c | 14 ++--
drivers/gpu/drm/i915/gt/intel_llc.c | 6 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 46 ++---
drivers/gpu/drm/i915/gt/intel_mocs.c | 8 +--
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 6 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 16 ++---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 12 ++--
.../gpu/drm/i915/gt/intel_ring_submission.c | 64 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 60 -
drivers/gpu/drm/i915/gt/intel_sseu.c | 14 ++--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +--
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 6 +-
drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 4 +-
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 8 +--
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 +--
drivers/gpu/drm/i915/gt/selftest_llc.c| 4 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c| 8 +--
drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rc6.c| 4 +-
.../drm/i915/gt/selftest_ring_submission.c| 6 +-
drivers/gpu/drm/i915/gt/selftest_rps.c| 16 ++---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 6 +-
.../gpu/drm/i915/gt/selftest_workarounds.c| 8 +--
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 4 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +--
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
44 files changed, 323 insertions(+), 322 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index d4f4452ce5ed..0389bceebd06 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -85,14 +85,14 @@ static int gen6_drpc(struct seq_file *m)
gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
- if (INTEL_GEN(i915) >= 9) {
+ if (GRAPHICS_VER(i915) >= 9) {
gen9_powergate_enable =
intel_uncore_read(uncore, GEN9_PG_ENABLE);
gen9_powergate_status =
intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS);
}
- if (INTEL_GEN(i915) <= 7)
+ if (GRAPHICS_VER(i915) <= 7)
sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
, NULL);
@@ -100,7 +100,7 @@ static int
[Intel-gfx] ✓ Fi.CI.IGT: success for Enhance pipe color support for multi segmented luts
== Series Details == Series: Enhance pipe color support for multi segmented luts URL : https://patchwork.freedesktop.org/series/90821/ State : success == Summary == CI Bug Log - changes from CI_DRM_10154_full -> Patchwork_20248_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20248_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@display-2x: - shard-tglb: NOTRUN -> [SKIP][1] ([i915#1839]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@feature_discov...@display-2x.html - shard-iclb: NOTRUN -> [SKIP][2] ([i915#1839]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@feature_discov...@display-2x.html * igt@gem_create@create-clear: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#3160]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk9/igt@gem_cre...@create-clear.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-glk8/igt@gem_cre...@create-clear.html * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#198] / [i915#2910]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl7/igt@gem_ctx_isolation@preservation...@bcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl9/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_ctx_isolation@preservation-s3@vecs0: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-apl3/igt@gem_ctx_isolation@preservation...@vecs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-apl3/igt@gem_ctx_isolation@preservation...@vecs0.html * igt@gem_ctx_persistence@engines-queued: - shard-snb: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-snb5/igt@gem_ctx_persiste...@engines-queued.html * igt@gem_ctx_ringsize@active@bcs0: - shard-skl: [PASS][10] -> [INCOMPLETE][11] ([i915#3316]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl8/igt@gem_ctx_ringsize@act...@bcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl10/igt@gem_ctx_ringsize@act...@bcs0.html * igt@gem_eio@in-flight-contexts-10ms: - shard-iclb: [PASS][12] -> [TIMEOUT][13] ([i915#3070]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb6/igt@gem_...@in-flight-contexts-10ms.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][14] ([i915#3354]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-snb2/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-tglb: NOTRUN -> [FAIL][15] ([i915#2842]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@gem_exec_fair@basic-none-...@rcs0.html - shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#2842]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk6/igt@gem_exec_fair@basic-pace-s...@rcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-glk2/igt@gem_exec_fair@basic-pace-s...@rcs0.html - shard-tglb: [PASS][19] -> [FAIL][20] ([i915#2842]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-tglb7/igt@gem_exec_fair@basic-pace-s...@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb5/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][21] -> [FAIL][22] ([i915#2849]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_whisper@basic-fds-forked: - shard-glk: [PASS][23] -> [DMESG-WARN][24] ([i915#118] / [i915#95]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk9/igt@gem_exec_whis...@basic-fds-forked.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-glk4/igt@gem_exec_whis...@basic-fds-forked.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN ->
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function
== Series Details == Series: series starting with [v2,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function URL : https://patchwork.freedesktop.org/series/90830/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1893:21:expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1893:21:got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1893:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts
Re: [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER
On Thu, May 27, 2021 at 11:16:54AM -0700, Lucas De Marchi wrote:
> This was done by the following semantic patch:
Is the commit message here out-of-date? The cocci doesn't appear to
match the diff anymore. IS_GRAPHICS_VER() is the range macro now and
IS_GEN is being replaced with a direct "==" comparison.
Matt
>
> @@ expression dev_priv, E; @@
> - INTEL_GEN(dev_priv) == E
> + IS_GRAPHICS_VER(dev_priv, E)
>
> @@ expression dev_priv; @@
> - INTEL_GEN(dev_priv)
> + GRAPHICS_VER(dev_priv)
>
> @@ expression dev_priv; expression E; @@
> - IS_GEN(dev_priv, E)
> + IS_GRAPHICS_VER(dev_priv, E)
>
> @@
> expression dev_priv;
> expression from, until;
> @@
> - IS_GEN_RANGE(dev_priv, from, until)
> + IS_GRAPHICS_RANGE(dev_priv, from, until)
>
> @def@
> expression E;
> identifier id =~ "^gen$";
> @@
> - id = GRAPHICS_VER(E)
> + ver = GRAPHICS_VER(E)
>
> @@
> identifier def.id;
> @@
> - id
> + ver
>
> It also takes care of renaming the variable we assign to GRAPHICS_VER()
> so to use "ver" rather than "gen".
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 38 +--
> drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 54 +++
> .../drm/i915/gt/intel_execlists_submission.c | 18 ++---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 18 ++---
> drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 34 +-
> drivers/gpu/drm/i915/gt/intel_gt.c| 27
> .../gpu/drm/i915/gt/intel_gt_clock_utils.c| 12 ++--
> drivers/gpu/drm/i915/gt/intel_gt_irq.c| 6 +-
> drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 10 +--
> drivers/gpu/drm/i915/gt/intel_gtt.c | 14 ++--
> drivers/gpu/drm/i915/gt/intel_llc.c | 6 +-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 46 ++---
> drivers/gpu/drm/i915/gt/intel_mocs.c | 8 +--
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 6 +-
> drivers/gpu/drm/i915/gt/intel_rc6.c | 16 ++---
> drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_reset.c | 12 ++--
> .../gpu/drm/i915/gt/intel_ring_submission.c | 64 +-
> drivers/gpu/drm/i915/gt/intel_rps.c | 60 -
> drivers/gpu/drm/i915/gt/intel_sseu.c | 14 ++--
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +--
> drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 6 +-
> drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_execlists.c | 4 +-
> drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 8 +--
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 +--
> drivers/gpu/drm/i915/gt/selftest_llc.c| 4 +-
> drivers/gpu/drm/i915/gt/selftest_lrc.c| 8 +--
> drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_rc6.c| 4 +-
> .../drm/i915/gt/selftest_ring_submission.c| 6 +-
> drivers/gpu/drm/i915/gt/selftest_rps.c| 16 ++---
> drivers/gpu/drm/i915/gt/selftest_timeline.c | 6 +-
> .../gpu/drm/i915/gt/selftest_workarounds.c| 8 +--
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 4 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +--
> drivers/gpu/drm/i915/gt/uc/intel_huc.c| 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
> 44 files changed, 323 insertions(+), 322 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> index d4f4452ce5ed..0389bceebd06 100644
> --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> @@ -85,14 +85,14 @@ static int gen6_drpc(struct seq_file *m)
> gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
>
> rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
> - if (INTEL_GEN(i915) >= 9) {
> + if (GRAPHICS_VER(i915) >= 9) {
> gen9_powergate_enable =
> intel_uncore_read(uncore, GEN9_PG_ENABLE);
> gen9_powergate_status =
> intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS);
> }
>
> - if (INTEL_GEN(i915) <= 7)
> + if (GRAPHICS_VER(i915) <= 7)
> sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
> , NULL);
>
> @@ -100,7 +100,7 @@ static int gen6_drpc(struct seq_file *m)
> yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
>
Re: [Intel-gfx] [PATCH v7 01/15] swiotlb: Refactor swiotlb init functions
On 5/27/21 8:02 AM, Christoph Hellwig wrote: > On Wed, May 19, 2021 at 11:50:07AM -0700, Florian Fainelli wrote: >> You convert this call site with swiotlb_init_io_tlb_mem() which did not >> do the set_memory_decrypted()+memset(). Is this okay or should >> swiotlb_init_io_tlb_mem() add an additional argument to do this >> conditionally? > > The zeroing is useful and was missing before. I think having a clean > state here is the right thing. > > Not sure about the set_memory_decrypted, swiotlb_update_mem_attributes > kinda suggests it is too early to set the memory decrupted. > > Adding Tom who should now about all this. The reason for adding swiotlb_update_mem_attributes() was because having the call to set_memory_decrypted() in swiotlb_init_with_tbl() triggered a BUG_ON() related to interrupts not being enabled yet during boot. So that call had to be delayed until interrupts were enabled. Thanks, Tom > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 01/15] swiotlb: Refactor swiotlb init functions
On 5/27/21 9:41 AM, Tom Lendacky wrote: > On 5/27/21 8:02 AM, Christoph Hellwig wrote: >> On Wed, May 19, 2021 at 11:50:07AM -0700, Florian Fainelli wrote: >>> You convert this call site with swiotlb_init_io_tlb_mem() which did not >>> do the set_memory_decrypted()+memset(). Is this okay or should >>> swiotlb_init_io_tlb_mem() add an additional argument to do this >>> conditionally? >> >> The zeroing is useful and was missing before. I think having a clean >> state here is the right thing. >> >> Not sure about the set_memory_decrypted, swiotlb_update_mem_attributes >> kinda suggests it is too early to set the memory decrupted. >> >> Adding Tom who should now about all this. > > The reason for adding swiotlb_update_mem_attributes() was because having > the call to set_memory_decrypted() in swiotlb_init_with_tbl() triggered a > BUG_ON() related to interrupts not being enabled yet during boot. So that > call had to be delayed until interrupts were enabled. I pulled down and tested the patch set and booted with SME enabled. The following was seen during the boot: [0.134184] BUG: Bad page state in process swapper pfn:108002 [0.134196] page:(ptrval) refcount:0 mapcount:-128 mapping: index:0x0 pfn:0x108002 [0.134201] flags: 0x17c000(node=0|zone=2|lastcpupid=0x1f) [0.134208] raw: 0017c000 88847f355e28 88847f355e28 [0.134210] raw: 0001 ff7f [0.134212] page dumped because: nonzero mapcount [0.134213] Modules linked in: [0.134218] CPU: 0 PID: 0 Comm: swapper Not tainted 5.13.0-rc2-sos-custom #3 [0.134221] Hardware name: ... [0.134224] Call Trace: [0.134233] dump_stack+0x76/0x94 [0.134244] bad_page+0xa6/0xf0 [0.134252] __free_pages_ok+0x331/0x360 [0.134256] memblock_free_all+0x158/0x1c1 [0.134267] mem_init+0x1f/0x14c [0.134273] start_kernel+0x290/0x574 [0.134279] secondary_startup_64_no_verify+0xb0/0xbb I see this about 40 times during the boot, each with a different PFN. The system boots (which seemed odd), but I don't know if there will be side effects to this (I didn't stress the system). I modified the code to add a flag to not do the set_memory_decrypted(), as suggested by Florian, when invoked from swiotlb_init_with_tbl(), and that eliminated the bad page state BUG. Thanks, Tom > > Thanks, > Tom > >> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/9] drm: Add privacy-screen class (v2)
Hi Emil, On giu 1 2021, at 5:31 pm, Emil Velikov wrote: > Hi Hans, > > What happened with this series, did it fall through the cracks? It's mostly waiting me to finish to propose the changes to GNOME, unfortunately I've been busy in the past weeks with downstream work, so I couldn't finish it, but I hope I can be back at it soon. Cheers > >> --- /dev/null >> +++ b/drivers/gpu/drm/drm_privacy_screen.c > >> +#include "drm_internal.h" > > I think we don't need this include, do we? > > >> --- /dev/null >> +++ b/include/drm/drm_privacy_screen_consumer.h > >> +#include > > Ditto > >> --- /dev/null >> +++ b/include/drm/drm_privacy_screen_driver.h > >> +#include > > Ditto > > I like how you avoided leaking any DRM details within the new code, > modulo the includes above. With above tweaks, the series is: > Reviewed-by: Emil Velikov > > Theoretically one could also remove the `depends on DRM` from patch > 8/9 but I'm not sure how much that saves us. > > HTH > -Emil > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Introduce new intel_psr_pause/resume function
== Series Details == Series: drm/i915/display: Introduce new intel_psr_pause/resume function URL : https://patchwork.freedesktop.org/series/90819/ State : success == Summary == CI Bug Log - changes from CI_DRM_10154_full -> Patchwork_20247_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_20247_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20247_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20247_full: ### IGT changes ### Warnings * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: [FAIL][1] ([i915#2842]) -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/shard-iclb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html Known issues Here are the changes found in Patchwork_20247_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@display-2x: - shard-tglb: NOTRUN -> [SKIP][3] ([i915#1839]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/shard-tglb1/igt@feature_discov...@display-2x.html - shard-iclb: NOTRUN -> [SKIP][4] ([i915#1839]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/shard-iclb6/igt@feature_discov...@display-2x.html * igt@gem_ctx_persistence@many-contexts: - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2410]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-tglb6/igt@gem_ctx_persiste...@many-contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/shard-tglb3/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_ctx_persistence@smoketest: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/shard-snb7/igt@gem_ctx_persiste...@smoketest.html - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2896]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-tglb3/igt@gem_ctx_persiste...@smoketest.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/shard-tglb2/igt@gem_ctx_persiste...@smoketest.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][10] ([i915#3354]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/shard-snb5/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-tglb: NOTRUN -> [FAIL][11] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/shard-tglb1/igt@gem_exec_fair@basic-none-...@rcs0.html - shard-iclb: NOTRUN -> [FAIL][12] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/shard-iclb6/igt@gem_exec_fair@basic-none-...@rcs0.html - shard-glk: NOTRUN -> [FAIL][13] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/shard-glk4/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk6/igt@gem_exec_fair@basic-pace-s...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/shard-glk1/igt@gem_exec_fair@basic-pace-s...@rcs0.html - shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-tglb7/igt@gem_exec_fair@basic-pace-s...@rcs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/shard-tglb8/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][18] -> [FAIL][19] ([i915#2849]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-snb: NOTRUN -> [SKIP][20] ([fdo#109271]) +415 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/shard-snb7/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html * igt@gem_exec_reloc@basic-wide-active@rcs0: - shard-snb: NOTRUN -> [FAIL][21] ([i915#2389]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/shard-snb2/igt@gem_exec_reloc@basic-wide-act...@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-apl:
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/opregion: add support for mailbox #5 EDID
On Mon, May 31, 2021 at 10:46:41PM +0200, Anisse Astier wrote:
> The ACPI OpRegion Mailbox #5 ASLE extension may contain an EDID to be
> used for the embedded display. Add support for using it via by adding
> the EDID to the list of available modes on the connector, and use it for
> eDP when available.
>
> If a panel's EDID is broken, there may be an override EDID set in the
> ACPI OpRegion mailbox #5. Use it if available.
Looks like Windows uses the ACPI _DDC method instead. We should probably
do the same, just in case some crazy machine stores the EDID somewhere
else.
>
> Fixes the GPD Win Max display.
>
> Based on original patch series by: Jani Nikula
> https://patchwork.kernel.org/project/intel-gfx/patch/20200828061941.17051-1-jani.nik...@intel.com/
>
> Changes:
> - EDID is copied and validated with drm_edid_is_valid
> - Mode is now added via drm_add_edid_modes instead of using override
>mechanism
> - squashed the two patches
>
> Cc: Jani Nikula
> Cc: Uma Shankar
> Cc: Ville Syrjälä
> Signed-off-by: Anisse Astier
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 3 +
> drivers/gpu/drm/i915/display/intel_opregion.c | 69 ++-
> drivers/gpu/drm/i915/display/intel_opregion.h | 8 +++
> 3 files changed, 79 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5c983044..43fb485c0e02 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5191,6 +5191,9 @@ static bool intel_edp_init_connector(struct intel_dp
> *intel_dp,
> goto out_vdd_off;
> }
>
> + /* Set up override EDID, if any, from ACPI OpRegion */
> + intel_opregion_edid_probe(intel_connector);
> +
> mutex_lock(>mode_config.mutex);
> edid = drm_get_edid(connector, _dp->aux.ddc);
> if (edid) {
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
> b/drivers/gpu/drm/i915/display/intel_opregion.c
> index dfd724e506b5..ef8d38f041eb 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> @@ -196,6 +196,8 @@ struct opregion_asle_ext {
> #define ASLE_IUER_WINDOWS_BTN(1 << 1)
> #define ASLE_IUER_POWER_BTN (1 << 0)
>
> +#define ASLE_PHED_EDID_VALID_MASK0x3
> +
> /* Software System Control Interrupt (SWSCI) */
> #define SWSCI_SCIC_INDICATOR (1 << 0)
> #define SWSCI_SCIC_MAIN_FUNCTION_SHIFT 1
> @@ -909,8 +911,10 @@ int intel_opregion_setup(struct drm_i915_private
> *dev_priv)
> opregion->asle->ardy = ASLE_ARDY_NOT_READY;
> }
>
> - if (mboxes & MBOX_ASLE_EXT)
> + if (mboxes & MBOX_ASLE_EXT) {
> drm_dbg(_priv->drm, "ASLE extension supported\n");
> + opregion->asle_ext = base + OPREGION_ASLE_EXT_OFFSET;
> + }
>
> if (intel_load_vbt_firmware(dev_priv) == 0)
> goto out;
> @@ -1037,6 +1041,68 @@ intel_opregion_get_panel_type(struct drm_i915_private
> *dev_priv)
> return ret - 1;
> }
>
> +/**
> + * intel_opregion_edid_probe - Add EDID from ACPI OpRegion mailbox #5
> + * @intel_connector: eDP connector
> + *
> + * This reads the ACPI Opregion mailbox #5 to extract the EDID that is passed
> + * to it.
> + *
> + * Will take a lock on the DRM mode_config to add the EDID; make sure it
> isn't
> + * called with lock taken.
> + *
> + */
> +void intel_opregion_edid_probe(struct intel_connector *intel_connector)
> +{
> + struct drm_connector *connector = _connector->base;
> + struct drm_i915_private *i915 = to_i915(connector->dev);
> + struct intel_opregion *opregion = >opregion;
> + const void *in_edid;
> + const struct edid *edid;
> + struct edid *new_edid;
> + int len, ret, num;
> +
> + if (!opregion->asle_ext || connector->override_edid)
> + return;
> +
> + in_edid = opregion->asle_ext->bddc;
> +
> + /* Validity corresponds to number of 128-byte blocks */
> + len = (opregion->asle_ext->phed & ASLE_PHED_EDID_VALID_MASK) * 128;
> + if (!len || !memchr_inv(in_edid, 0, len))
> + return;
> +
> + edid = in_edid;
> +
> + if (len < EDID_LENGTH * (1 + edid->extensions)) {
> + drm_dbg_kms(>drm, "Invalid EDID in ACPI OpRegion (Mailbox
> #5)\n");
> + return;
> + }
> + new_edid = drm_edid_duplicate(edid);
> + if (!new_edid) {
> + drm_err(>drm, "Cannot duplicate EDID\n");
> + return;
> + }
> + if (!drm_edid_is_valid(new_edid)) {
> + kfree(new_edid);
> + drm_dbg_kms(>drm, "Cannot validate EDID in ACPI OpRegion
> (Mailbox #5)\n");
> + return;
> + }
> +
> + ret = drm_connector_update_edid_property(connector, new_edid);
> + if (ret) {
> + kfree(new_edid);
> + return;
> + }
> +
> + mutex_lock(>dev->mode_config.mutex);
> +
Re: [Intel-gfx] [PATCH v2 2/9] drm: Add privacy-screen class (v2)
Hi Hans, What happened with this series, did it fall through the cracks? On Wed, 21 Apr 2021 at 21:48, Hans de Goede wrote: > --- /dev/null > +++ b/drivers/gpu/drm/drm_privacy_screen.c > +#include "drm_internal.h" I think we don't need this include, do we? > --- /dev/null > +++ b/include/drm/drm_privacy_screen_consumer.h > +#include Ditto > --- /dev/null > +++ b/include/drm/drm_privacy_screen_driver.h > +#include Ditto I like how you avoided leaking any DRM details within the new code, modulo the includes above. With above tweaks, the series is: Reviewed-by: Emil Velikov Theoretically one could also remove the `depends on DRM` from patch 8/9 but I'm not sure how much that saves us. HTH -Emil ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Only set bind_async_flags when concurrent access wa is not active, v3. (rev2)
== Series Details ==
Series: drm/i915: Only set bind_async_flags when concurrent access wa is not
active, v3. (rev2)
URL : https://patchwork.freedesktop.org/series/90818/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20251
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20251 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20251, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20251/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_20251:
### IGT changes ###
Possible regressions
* igt@gem_exec_parallel@engines@fds:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-apl-guc/igt@gem_exec_parallel@engi...@fds.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20251/fi-apl-guc/igt@gem_exec_parallel@engi...@fds.html
Known issues
Here are the changes found in Patchwork_20251 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-u2: [PASS][3] -> [FAIL][4] ([i915#1888])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20251/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html
Possible fixes
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][5] ([i915#1372]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20251/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
Warnings
* igt@i915_selftest@live@execlists:
- fi-cml-s: [DMESG-FAIL][7] ([i915#3462]) -> [INCOMPLETE][8]
([i915#3462])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cml-s/igt@i915_selftest@l...@execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20251/fi-cml-s/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-glk-dsi: [FAIL][9] ([i915#2426] / [i915#3363] /
[k.org#202321]) -> [FAIL][10] ([i915#3363] / [k.org#202321])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-glk-dsi/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20251/fi-glk-dsi/igt@run...@aborted.html
- fi-bsw-nick:[FAIL][11] ([fdo#109271] / [i915#1436]) -> [FAIL][12]
([fdo#109271] / [i915#1436] / [i915#2722])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-bsw-nick/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20251/fi-bsw-nick/igt@run...@aborted.html
- fi-bdw-5557u: [FAIL][13] ([i915#3462]) -> [FAIL][14] ([i915#2426] /
[i915#3462])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-bdw-5557u/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20251/fi-bdw-5557u/igt@run...@aborted.html
- fi-kbl-soraka: [FAIL][15] ([i915#1436] / [i915#3363]) -> [FAIL][16]
([i915#1436] / [i915#2426] / [i915#3363])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-soraka/igt@run...@aborted.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20251/fi-kbl-soraka/igt@run...@aborted.html
- fi-bxt-dsi: [FAIL][17] ([i915#3363]) -> [FAIL][18] ([i915#2426] /
[i915#3363])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-bxt-dsi/igt@run...@aborted.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20251/fi-bxt-dsi/igt@run...@aborted.html
- fi-kbl-7567u: [FAIL][19] ([i915#1436] / [i915#3363]) -> [FAIL][20]
([i915#1436] / [i915#2426] / [i915#3363])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7567u/igt@run...@aborted.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20251/fi-kbl-7567u/igt@run...@aborted.html
- fi-skl-6700k2: [FAIL][21] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][22] ([i915#1436] / [i915#3363])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-skl-6700k2/igt@run...@aborted.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20251/fi-skl-6700k2/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1372]:
[Intel-gfx] [PULL] drm-misc-next
Hi Dave and Daniel, here's this week's PR for drm-misc-next. It also contains last week's tag because last week's email somehow went wrong. Each tag has it's individual description, but the overview below contains the sum of both. Some highlights from both weeks are * amdgpu hot-unplug support, * cached mappings for GEM CMA, and * new features for rockchip. We changed the names of generic fbdev devices in /proc/fb. It's a UAPI change, but probably a non-event. It's not expected that programs have hard dependencies on DRM fbdev driver names. Best regards Thomas drm-misc-next-2021-06-01: drm-misc-next for 5.14: UAPI Changes: * Use DRM driver names for fbdev Cross-subsystem Changes: Core Changes: * Fix leaked DMA handles * Improve documentation around DRM_CLIENT_CAP_* * Cleanups * dp_mst: Use kHz as link-rate unit during init * fourcc: Remove drm_gem_format_name() and drm_format_name_buf * gem-cma: Fix mmap for buffers with write combining * ttm: Don't override pre-set vm_ops; ttm_bo_mmap() removal and cleanups Driver Changes: * drm/amdgpu: Fix hot unplug during suspend; Implement mmap as GEM object function; Use %p4cc format-string modifier; Cleanups * drm/bridge: Cdns: Fix PM reference leak, Cleanups; Lt8912b: Fix Coccinelle warnings; Fix Kconfig dependencies; Fixes and cleanups * drm/hisilicon/kirin: Cleanups * drm/nouveau: Implement mmap as GEM object function * drm/radeon: Implement mmap as GEM object function * drm/rockchip: Remove generic drivers during init; Add scaling for RK3036 win1; Fix missing registers for RK3066 and 3188; Add alpha support for RK3036, RK3066, RK3126 and RK3188; Fixes and cleanups * drm/simpledrm: Use %p4cc: format-string modifier * drm/vmwgfx: Cleanups * fbdev/matrox: Use modern module_init() The following changes since commit 5522e9f7b0fbe2a0cb89c199b574523becc8c3ab: Merge v5.13-rc3 into drm-next (2021-05-27 13:07:47 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2021-06-01 for you to fetch changes up to 2e290c8d8d29278b9a20e2765ab8f6df02f2e707: drm: document minimum kernel version for DRM_CLIENT_CAP_* (2021-05-31 18:57:22 +0200) drm-misc-next for 5.14: UAPI Changes: * DRM_IOCTL_IRQ_BUSID is now marked as legacy; returns -EINVAL if legacy drivers are disabled * Use DRM driver names for fbdev Cross-subsystem Changes: * PCI: Add support for dev_groups * vgaarb: Use ACPI HID to find integrated GPU Core Changes: * Log errors in drm_gem_fb_init_with_funcs() * Fix leaked DMA handles * Improve documentation around DRM_CLIENT_CAP_* * Cleanups * dp_mst: Use kHz as link-rate unit during init * fourcc: Remove drm_gem_format_name() and drm_format_name_buf * gem-cma: Add support for non-coherent (i.e., cached) page mappings; Fix mmap for buffers with write combining * legacy: Drop some unnecessary includes and code; Add missing unlocks and frees in drm_legacy_addbufs_pci() * sched: Make timeout timer rearm conditional; Fix data corruptions and hangs * ttm: Remap all page faults to per-process dummy page (for device removal); Don't override pre-set vm_ops; ttm_bo_mmap() removal and cleanups; Documentation Driver Changes: * drm/amdgpu: A long list of patches that enable device hot-unplug; Implement mmap as GEM object function; Use %p4cc format-string modifier; Cleanups * drm/bridge: Lt66121: Fix error code and leak in probe; Anx7625: Use runtime PM and add synchronous suspend/resume hooks; Ti-sn65dsi86: Fix a returned value's type; Anx7688: Add driver plus DT bindings; Cdns: Fix PM reference leak, Cleanups; Lt8912b: Fix Coccinelle warnings; Fix Kconfig dependencies; Fixes and cleanups * drm/hisilicon/kirin: Cleanups * drm/ingenic: Fix pixcloc for 24-bit serial panels; Use non-coherent BO mappings with explict synchronization if possible * drm/nouveau: Implement mmap as GEM object function * drm/panel: Simple-panel: Add missing pm_runtime_dont_use_autosuspend() * drm/radeon: Implement mmap as GEM object function * drm/rockchip: Remove generic drivers during init; Add scaling for RK3036 win1; Fix missing registers for RK3066 and 3188; Add alpha support for RK3036, RK3066, RK3126 and RK3188; Fixes and cleanups * drm/simpledrm: Use %p4cc: format-string modifier * drm/tve200: Convert DT bindings to YAML * drm/vc4: Support BCM2711 VEC plus DT bindings; Pipeline setup fixes; HDMI fixes * drm/vmwgfx: Cleanups * drm/virtio: Fix NULL pointer in probe; Fix double-free in probe; Free virtqueues in probe * fbdev/matrox: Use modern module_init() Alex Bee (5): drm: rockchip: add scaling for RK3036 win1 drm: rockchip: add missing registers for RK3188 drm: rockchip: add missing registers for RK3066 drm: rockchip:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Only set bind_async_flags when concurrent access wa is not active, v3. (rev2)
== Series Details == Series: drm/i915: Only set bind_async_flags when concurrent access wa is not active, v3. (rev2) URL : https://patchwork.freedesktop.org/series/90818/ State : warning == Summary == $ dim checkpatch origin/drm-tip 99698554997c drm/i915: Only set bind_async_flags when concurrent access wa is not active, v3. -:74: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #74: FILE: drivers/gpu/drm/i915/i915_vma.c:439: + vma->ops->bind_vma(vma->vm, work ? >stash : NULL, vma, cache_level, bind_flags); total: 0 errors, 1 warnings, 0 checks, 44 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/adl_p: CDCLK crawl support for ADL
From: Gwan-gyeong Mun
CDCLK crawl feature allows to change CDCLK frequency
without disabling the actual PLL and doesn't require
a full modeset.
Cc: Mika Kahola
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Jani Nikula
Signed-off-by: Gwan-gyeong Mun
Cc: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++---
drivers/gpu/drm/i915/i915_reg.h| 2 +
2 files changed, 65 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 618a9e1e2b0c..b9abed82328c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1548,6 +1548,35 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private
*dev_priv, int vco)
dev_priv->cdclk.hw.vco = vco;
}
+static bool has_cdclk_crawl(struct drm_i915_private *i915)
+{
+ return IS_ALDERLAKE_P(i915);
+}
+
+static void gen13_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
+{
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ u32 val;
+
+ /* Write PLL ratio without disabling */
+ val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
+ intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+
+ /* Submit freq change request */
+ val |= BXT_DE_PLL_FREQ_REQ;
+ intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+
+ /* Timeout 200us */
+ if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
+ BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
+ DRM_ERROR("timeout waiting for FREQ change request ack\n");
+
+ val &= ~BXT_DE_PLL_FREQ_REQ;
+ intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
+
+ dev_priv->cdclk.hw.vco = vco;
+}
+
static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe
pipe)
{
if (DISPLAY_VER(dev_priv) >= 12) {
@@ -1620,14 +1649,16 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
return;
}
- if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
+ if (has_cdclk_crawl(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0)
{
+ if (dev_priv->cdclk.hw.vco != vco)
+ gen13_cdclk_pll_crawl(dev_priv, vco);
+ } else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
if (dev_priv->cdclk.hw.vco != 0 &&
dev_priv->cdclk.hw.vco != vco)
cnl_cdclk_pll_disable(dev_priv);
if (dev_priv->cdclk.hw.vco != vco)
cnl_cdclk_pll_enable(dev_priv, vco);
-
} else {
if (dev_priv->cdclk.hw.vco != 0 &&
dev_priv->cdclk.hw.vco != vco)
@@ -1820,6 +1851,28 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
skl_cdclk_uninit_hw(i915);
}
+static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *a,
+ const struct intel_cdclk_config *b)
+{
+ int a_div, b_div;
+
+ if (!has_cdclk_crawl(dev_priv))
+ return false;
+
+ /*
+* The vco and cd2x divider will change independently
+* from each, so we disallow cd2x change when crawling.
+*/
+ a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
+ b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
+
+ return a->vco != 0 && b->vco != 0 &&
+ a->vco != b->vco &&
+ a_div == b_div &&
+ a->ref == b->ref;
+}
+
/**
* intel_cdclk_needs_modeset - Determine if changong between the CDCLK
* configurations requires a modeset on all pipes
@@ -2475,7 +2528,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
const struct intel_cdclk_state *old_cdclk_state;
struct intel_cdclk_state *new_cdclk_state;
- enum pipe pipe;
+ enum pipe pipe = INVALID_PIPE;
int ret;
new_cdclk_state = intel_atomic_get_cdclk_state(state);
@@ -2527,15 +2580,18 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
if (drm_atomic_crtc_needs_modeset(_state->uapi))
pipe = INVALID_PIPE;
- } else {
- pipe = INVALID_PIPE;
}
- if (pipe != INVALID_PIPE) {
+ if (intel_cdclk_can_crawl(dev_priv,
+ _cdclk_state->actual,
+ _cdclk_state->actual)) {
+ drm_dbg_kms(_priv->drm,
+ "Can change cdclk via crawl\n");
+ } else if (pipe != INVALID_PIPE) {
new_cdclk_state->pipe = pipe;
drm_dbg_kms(_priv->drm,
- "Can change cdclk with pipe %c active\n",
+
[Intel-gfx] [PATCH] [RFC] drm/vgem: Fix the pitch to be 64 byte aligned for Intel platforms
User space like igt/kms_prime use vgem_gem_dumb_create before reaching i915_gem_dumb_create (which has 64 byte alignment done). For panel resolutions like 1366x768, the pitch calculated by vgem is not 64 byte aligned. This results in frame buffer not being created by intel_framebuffer_init. Test: igt/kms_prime with panel resolution 1366x768 Change-Id: If68914421b1a9432a73af96c8b426045772629eb Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/vgem/vgem_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c index fa54a6d1403d..48535c88aa27 100644 --- a/drivers/gpu/drm/vgem/vgem_drv.c +++ b/drivers/gpu/drm/vgem/vgem_drv.c @@ -215,7 +215,7 @@ static int vgem_gem_dumb_create(struct drm_file *file, struct drm_device *dev, struct drm_gem_object *gem_object; u64 pitch, size; - pitch = args->width * DIV_ROUND_UP(args->bpp, 8); + pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); size = args->height * pitch; if (size == 0) return -EINVAL; -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/7] dma-buf: Rename dma_resv helpers from _rcu to _unlocked (v2)
On Thu, May 27, 2021 at 03:41:02PM +0200, Christian König wrote: > Am 27.05.21 um 15:25 schrieb Daniel Vetter: > > On Thu, May 27, 2021 at 1:59 PM Christian König > > wrote: > > > Am 27.05.21 um 12:39 schrieb Daniel Vetter: > > > > On Wed, May 26, 2021 at 12:57:40PM +0200, Christian König wrote: > > > > > Am 25.05.21 um 23:17 schrieb Jason Ekstrand: > > > > > > None of these helpers actually leak any RCU details to the caller. > > > > > > They > > > > > > all assume you have a genuine reference, take the RCU read lock, and > > > > > > retry if needed. Naming them with an _rcu is likely to cause > > > > > > callers > > > > > > more panic than needed. > > > > > I'm really wondering if we need this postfix in the first place. > > > > > > > > > > If we use the right rcu_dereference_check() macro then those > > > > > functions can > > > > > be called with both the reservation object locked and unlocked. It > > > > > shouldn't > > > > > matter to them. > > > > > > > > > > But getting rid of the _rcu postfix sounds like a good idea in > > > > > general to > > > > > me. > > > > So does that count as an ack or not? If yes I think we should land this > > > > patch right away, since it's going to conflict real fast badly. > > > I had some follow up discussion with Jason and I would rather like to > > > switch to using rcu_dereference_check() in all places and completely > > > remove the _rcu postfix. > > Hm, I'm not sure whether spreading _rcu tricks further is an > > especially bright idea. At least i915 is full of very clever _rcu > > tricks, and encouraging drivers to roll out their own _rcu everywhere > > is probably not in our best interest. Some fast-path checking is imo > > ok, but that's it. Especially once we get into the entire > > SLAB_TYPESAFE_BY_RCU business it becomes really nasty really quickly. > > Oh, yes completely agree. SLAB_TYPESAFE_BY_RCU is optimizing for the wrong > use case I think. > > You save a bit of overhead while freeing fences, but in return you have > extra overhead while adding fences to the dma_resv object. Getting way off topic, but I'm wondering whether the entire rcu business is really worth it for dma_fence. Mostly we manipulate dma_resv while holding dma_resv anyway. There's maybe a few waits and stuff, but I'm not sure whether the dma_resv_lock + dma_fence_get + dma_resv_unlock + dma_fence_put really matter. And if you have lock contention on a single buffer you've lost anyway. At that point I think we have maybe some lockless tricks in the evict code, but then again once you're evicting it's probably going pretty bad already. So SLAB_TYPESAFE_BY_RCU is something I want to analyze for i915 whether it's really worth it and was justified, or whether we should drop it. But I'm wondering whether we should drop rcu for fences outright. Would be quite some audit to check out where it's used. >From i915 side we've done these lockless tricks back when dev->struct_mutex was a thing and alwas contended. But with per-obj locking now happening for real with dma-resv, that's probably not justified. But then looking at git history the rcu in dma_resv is older than that, and was justified with ttm. > > That's why I'm slightly leaning towards _unlocked variants, except we > > do use those in lots of places where we hold dma_resv_lock too. So not > > sure what's the best plan overall here. > > Well what function names are we actually talking about? > > For the dma_resv_get_excl_rcu() case I agree we should probably name that to > dma_resv_get_excl_unlocked() because it makes no sense at all to use this > function while holding the lock. > > But for the following functions: > dma_resv_get_fences_rcu > dma_resv_wait_timeout_rcu > dma_resv_test_signaled_rcu > > I think we should just drop the _rcu naming because those are supposed to > work independent if the resv lock is held or not. Ack on all naming. -Daniel > > Regards, > Christian. > > > -Daniel > > > > > But yes I see the pain of rebasing this as well. > > > > > > Christian. > > > > > > > -Daniel > > > > > > > > > Christian. > > > > > > > > > > > v2 (Jason Ekstrand): > > > > > > - Fix function argument indentation > > > > > > > > > > > > Signed-off-by: Jason Ekstrand > > > > > > Suggested-by: Daniel Vetter > > > > > > Cc: Christian König > > > > > > Cc: Maarten Lankhorst > > > > > > Cc: Maxime Ripard > > > > > > Cc: Thomas Zimmermann > > > > > > Cc: Lucas Stach > > > > > > Cc: Rob Clark > > > > > > Cc: Sean Paul > > > > > > Cc: Huang Rui > > > > > > Cc: Gerd Hoffmann > > > > > > Cc: VMware Graphics > > > > > > --- > > > > > > drivers/dma-buf/dma-buf.c | 4 +-- > > > > > > drivers/dma-buf/dma-resv.c| 28 > > > > > > +-- > > > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 ++-- > > > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +- > > > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 +--
Re: [Intel-gfx] [PATCH] drm/i915: Fix wrong name announced on FB driver switching
On Wed, 26 May 2021, Janusz Krzysztofik
wrote:
> Hi,
>
> On poniedziałek, 3 maja 2021 19:38:17 CEST Jani Nikula wrote:
>> On Thu, 29 Apr 2021, Janusz Krzysztofik
> wrote:
>> > Commit 7a0f9ef9703d ("drm/i915: Use drm_fb_helper_fill_info")
>> > effectively changed our FB driver name from "inteldrmfb" to
>> > "i915drmfb". However, we are still using the old name when kicking out
>> > a firmware fbdev driver potentially bound to our device. Use the new
>> > name to avoid confusion.
>> >
>> > Note: since the new name is assigned by a DRM fbdev helper called at
>> > the DRM driver registration time, that name is not available when we
>> > kick the other driver out early, hence a hardcoded name must be used
>> > unless the DRM layer exposes a macro for converting a DRM driver name
>> > to its associated fbdev driver name.
>> >
>> > Signed-off-by: Janusz Krzysztofik
>>
>> LGTM, Daniel?
>>
>> Reviewed-by: Jani Nikula
>
> Am I supposed to do something to push processing of this patch forward?
> Please note I have no push permissions so can't merge it myself.
I was hoping to get an ack from Daniel in case I missed something.
>
>>
>> $ dim fixes 7a0f9ef9703d
>> Fixes: 7a0f9ef9703d ("drm/i915: Use drm_fb_helper_fill_info")
>> Cc: Noralf Trønnes
>> Cc: Alex Deucher
>> Cc: Daniel Vetter
>> Cc: Jani Nikula
>> Cc: Joonas Lahtinen
>> Cc: Rodrigo Vivi
>> Cc: intel-gfx@lists.freedesktop.org
>> Cc: # v5.2+
>
> Should I resubmit with those tags appended?
No need, will be added by whoever applies the patch.
BR,
Jani.
>
> Thanks,
> Janusz
>
>>
>>
>> > ---
>> > drivers/gpu/drm/i915/i915_drv.c | 2 +-
>> > 1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/
> i915_drv.c
>> > index 785dcf20c77b..46082490dc9a 100644
>> > --- a/drivers/gpu/drm/i915/i915_drv.c
>> > +++ b/drivers/gpu/drm/i915/i915_drv.c
>> > @@ -554,7 +554,7 @@ static int i915_driver_hw_probe(struct
> drm_i915_private *dev_priv)
>> >if (ret)
>> >goto err_perf;
>> >
>> > - ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev,
> "inteldrmfb");
>> > + ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev,
> "i915drmfb");
>> >if (ret)
>> >goto err_ggtt;
>>
>>
>
>
>
>
--
Jani Nikula, Intel Open Source Graphics Center
___
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Re: [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
On Tue, Jun 01, 2021 at 11:09:47AM +0100, Tvrtko Ursulin wrote:
>
> On 27/05/2021 11:27, Daniel Vetter wrote:
> > On Thu, May 27, 2021 at 11:22:16AM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 27/05/2021 11:13, Daniel Vetter wrote:
> > > > On Wed, May 26, 2021 at 11:20:13AM +0100, Tvrtko Ursulin wrote:
> > > > >
> > > > > On 25/05/2021 15:47, Daniel Vetter wrote:
> > > > > > On Tue, May 25, 2021 at 03:19:47PM +0100, Tvrtko Ursulin wrote:
> > > > > > >
> > > > > > > + dri-devel as per process
> > > > > > >
> > > > > > > On 25/05/2021 14:55, Tejas Upadhyay wrote:
> > > > > > > > v2: Only declare timeslicing if we can safely preempt userspace.
> > > > > > >
> > > > > > > Commit message got butchered up somehow so you'll need to fix
> > > > > > > that at some
> > > > > > > point.
> > > > > > >
> > > > > > > Regards,
> > > > > > >
> > > > > > > Tvrtko
> > > > > > >
> > > > > > > > Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic
> > > > > > > > timeslicing")
> > > > > > > > Signed-off-by: Chris Wilson
> > > > > > > > Cc: Tvrtko Ursulin
> > > > > > > > Reviewed-by: Tvrtko Ursulin
> > > > > > > > ---
> > > > > > > > drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 +
> > > > > > > > include/uapi/drm/i915_drm.h | 1 +
> > > > > > > > 2 files changed, 2 insertions(+)
> > > > > > > >
> > > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > > > > > > b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > > > > > > index 3cca7ea2d6ea..12d165566ed2 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > > > > > > @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct
> > > > > > > > drm_i915_private *i915)
> > > > > > > > MAP(HAS_PREEMPTION, PREEMPTION),
> > > > > > > > MAP(HAS_SEMAPHORES, SEMAPHORES),
> > > > > > > > MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS),
> > > > > > > > + MAP(TIMESLICE_BIT, TIMESLICING),
> > > > > > > > #undef MAP
> > > > > > > > };
> > > > > > > > struct intel_engine_cs *engine;
> > > > > > > > diff --git a/include/uapi/drm/i915_drm.h
> > > > > > > > b/include/uapi/drm/i915_drm.h
> > > > > > > > index c2c7759b7d2e..af2212d6113c 100644
> > > > > > > > --- a/include/uapi/drm/i915_drm.h
> > > > > > > > +++ b/include/uapi/drm/i915_drm.h
> > > > > > > > @@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait {
> > > > > > > > #define I915_SCHEDULER_CAP_PREEMPTION(1ul << 2)
> > > > > > > > #define I915_SCHEDULER_CAP_SEMAPHORES(1ul << 3)
> > > > > > > > #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul <<
> > > > > > > > 4)
> > > > > > > > +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5)
> > > > > >
> > > > > > Since this is uapi I think we should at least have some nice
> > > > > > kerneldoc
> > > > > > that explains what exactly this is, what for (link to userspace)
> > > > > > and all
> > > > > > that. Ideally also minimally filing in the gaps in our uapi docs
> > > > > > for stuff
> > > > > > this references.
> > > > >
> > > > > IIUC there is no userspace apart from IGT needing it not to fail
> > > > > scheduling
> > > > > tests on ADL.
> > > > >
> > > > > Current tests use "has preemption + has semaphores" as a proxy to
> > > > > answer the
> > > > > "does the kernel support timeslicing" question. This stops working
> > > > > with the
> > > > > Guc backend because GuC decided not to support semaphores (for
> > > > > reasons yet
> > > > > unknown, see other thread), so explicit "has timeslicing" flag is
> > > > > needed in
> > > > > order for tests to know that GuC is supposed to support timeslicing,
> > > > > even if
> > > > > it doesn't use semaphores for inter-ring synchronisation.
> > > >
> > > > Since this if for igt only: Cant we do just extend the check in igt with
> > > > an || GEN >= 12? I really hope that our future hw will continue to
> > > > support
> > > > timeslicing ...
> > >
> > > Not the gen 12 check, but possible I think. Explicit feature test would
> > > be better, but if definitely not allowed then along the lines of:
> > >
> > > has_timeslicing =
> > > (has_preemption && has_semaphores) || uses_guc_submission;
> >
> > That works too. Otoh what exactly is the "uses guc submission" flag and
> > why do we have that? I've seen media use it as a stand-in for "does the
> > kernel want bonded or parallel ctx?". Maybe another thing to check.
> >
> > Another option, if you really think the feature flag is the best approach
> > (because future hw will drop timeslicing for some reason), then debugfs is
> > the place of igt-only api.
>
> Maybe check and potentially remove all I915_SCHEDULER_CAP_.. flags. It could
> be another easy pickings with a lot of IGT work type endeavour.
Yeah there's a lot unfortunately. I'll make a note internally that we need
to look at this again maybe next year,
[Intel-gfx] [PATCH] drm/i915: Add relocation exceptions for two other platforms
We have established previously we stop using relocations starting
from gen12 platforms with Tigerlake as an exception. We keep this
statement but we want to enable relocations conditionally for
Rocketlake and Alderlake under require_force_probe flag set.
Keeping relocations under require_force_probe flag is interim solution
until IGTs will be rewritten to use softpin.
v2: - remove inline from function definition (Jani)
- fix indentation
Signed-off-by: Zbigniew Kempczyński
Cc: Dave Airlie
Cc: Daniel Vetter
Cc: Jason Ekstrand
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 24 +++
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 297143511f99..78b86a7bc39a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -491,16 +491,30 @@ eb_unreserve_vma(struct eb_vma *ev)
ev->flags &= ~__EXEC_OBJECT_RESERVED;
}
+static bool platform_has_relocs_enabled(const struct i915_execbuffer *eb)
+{
+ /*
+* Relocations are disallowed starting from gen12 with Tigerlake
+* as an exception. We allow temporarily use relocations for Rocketlake
+* and Alderlake when require_force_probe flag is set.
+*/
+ if (INTEL_GEN(eb->i915) < 12 || IS_TIGERLAKE(eb->i915))
+ return true;
+
+ if (INTEL_INFO(eb->i915)->require_force_probe &&
+ (IS_ROCKETLAKE(eb->i915) || IS_ALDERLAKE_S(eb->i915) ||
+IS_ALDERLAKE_P(eb->i915)))
+ return true;
+
+ return false;
+}
+
static int
eb_validate_vma(struct i915_execbuffer *eb,
struct drm_i915_gem_exec_object2 *entry,
struct i915_vma *vma)
{
- /* Relocations are disallowed for all platforms after TGL-LP. This
-* also covers all platforms with local memory.
-*/
- if (entry->relocation_count &&
- INTEL_GEN(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
+ if (entry->relocation_count && !platform_has_relocs_enabled(eb))
return -EINVAL;
if (unlikely(entry->flags & eb->invalid_flags))
--
2.26.0
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for lpsp with hdmi/dp outputs
== Series Details ==
Series: lpsp with hdmi/dp outputs
URL : https://patchwork.freedesktop.org/series/90827/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20250
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/index.html
Known issues
Here are the changes found in Patchwork_20250 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][3] -> [FAIL][4] ([i915#49])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][5] ([i915#3303]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][7] ([i915#1372]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
Warnings
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[INCOMPLETE][9] ([i915#2782] / [i915#2940] /
[i915#3462]) -> [DMESG-FAIL][10] ([i915#3462])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
- fi-icl-u2: [INCOMPLETE][11] ([i915#2782] / [i915#3462]) ->
[DMESG-FAIL][12] ([i915#3462])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-icl-u2/igt@i915_selftest@l...@execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-icl-u2/igt@i915_selftest@l...@execlists.html
- fi-tgl-u2: [INCOMPLETE][13] ([i915#3462]) -> [DMESG-FAIL][14]
([i915#3462])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-tgl-u2/igt@i915_selftest@l...@execlists.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-tgl-u2/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-icl-u2: [FAIL][15] ([i915#2782] / [i915#3363]) -> [FAIL][16]
([i915#2426] / [i915#2782] / [i915#3363])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-icl-u2/igt@run...@aborted.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-icl-u2/igt@run...@aborted.html
- fi-glk-dsi: [FAIL][17] ([i915#2426] / [i915#3363] /
[k.org#202321]) -> [FAIL][18] ([i915#3363] / [k.org#202321])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-glk-dsi/igt@run...@aborted.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-soraka: [FAIL][19] ([i915#1436] / [i915#3363]) -> [FAIL][20]
([i915#1436] / [i915#2426] / [i915#3363])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-soraka/igt@run...@aborted.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-kbl-soraka/igt@run...@aborted.html
- fi-cml-u2: [FAIL][21] ([i915#3363] / [i915#3462]) -> [FAIL][22]
([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cml-u2/igt@run...@aborted.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-cml-u2/igt@run...@aborted.html
- fi-cfl-guc: [FAIL][23] ([i915#2426] / [i915#3363]) -> [FAIL][24]
([i915#3363])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cfl-guc/igt@run...@aborted.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-cfl-guc/igt@run...@aborted.html
- fi-skl-6700k2: [FAIL][25] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][26] ([i915#1436] / [i915#3363])
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-skl-6700k2/igt@run...@aborted.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20250/fi-skl-6700k2/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
[Intel-gfx] [PATCH i-g-t] [RFC] tests/kms_plane_alpha_blend: Don't set primary fb color in coverage-vs-premult-vs-constant
Patch removes setting primary fb color in coverage-vs-premult-vs-constant
as this is causing CRC mismatch on few Gen11 systems.
Similar change has already been done in tests constant_alpha_min and basic_alpha
where the test runs on all planes but dont set the primary fb color.
Signed-off-by: Vidya Srinivas
---
tests/kms_plane_alpha_blend.c | 4
1 file changed, 4 deletions(-)
diff --git a/tests/kms_plane_alpha_blend.c b/tests/kms_plane_alpha_blend.c
index a37cb27c7d62..224d79bd1749 100644
--- a/tests/kms_plane_alpha_blend.c
+++ b/tests/kms_plane_alpha_blend.c
@@ -447,10 +447,6 @@ static void coverage_premult_constant(data_t *data, enum
pipe pipe, igt_plane_t
igt_display_t *display = >display;
igt_crc_t ref_crc = {}, crc = {};
- /* Set a background color on the primary fb for testing */
- if (plane->type != DRM_PLANE_TYPE_PRIMARY)
- igt_plane_set_fb(igt_pipe_get_plane_type(>pipes[pipe],
DRM_PLANE_TYPE_PRIMARY), >gray_fb);
-
igt_plane_set_prop_enum(plane, IGT_PLANE_PIXEL_BLEND_MODE, "Coverage");
igt_plane_set_fb(plane, >argb_fb_cov_7e);
igt_display_commit2(display, COMMIT_ATOMIC);
--
2.7.4
___
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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] [RFC] tests/kms_plane_alpha_blend: Fix coverage-vs-premult-vs-constant tests
Thank you so much Petri. Apologies for the incorrect commit message. I will submit the patch with the clear commit message. Regards Vidya -Original Message- From: Latvala, Petri Sent: Tuesday, June 1, 2021 7:11 PM To: Srinivas, Vidya Cc: intel-gfx@lists.freedesktop.org; igt-...@lists.freedesktop.org Subject: Re: [igt-dev] [PATCH i-g-t] [RFC] tests/kms_plane_alpha_blend: Fix coverage-vs-premult-vs-constant tests On Tue, Jun 01, 2021 at 05:15:39PM +0530, Vidya Srinivas wrote: > tests/kms_plane_alpha_blend: Fix coverage-vs-premult-vs-constant tests > > Few Gen11 systems show CRC mismatch. Make > coverage-vs-premult-vs-constant code similar to constant_alpha_min or > basic_alpha > > Signed-off-by: Vidya Srinivas Please make the first line of the commit message a statement that tells what change you're making, and in the full text block state why that's done. "Fix a-b-c tests" is useless later when browsing oneliner git logs. It doesn't even tell which problem is fixed. Meaning, something like: == tests/kms_plane_alpha_blend: Don't set primary fb color in coverage-vs-premult-vs-constant Similar change has already been done in tests xxx and yyy. This fixes CRC mismatches seen with some Gen11 systems. Signed-off-by etc == -- Petri Latvala ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Fix return value check in live_breadcrumbs_smoketest()
== Series Details == Series: drm/i915/selftests: Fix return value check in live_breadcrumbs_smoketest() URL : https://patchwork.freedesktop.org/series/90817/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10154_full -> Patchwork_20245_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20245_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20245_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20245_full: ### Piglit changes ### Possible regressions * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 42 8 8 4 (NEW): - pig-glk-j5005: NOTRUN -> [INCOMPLETE][1] [1]: None New tests - New tests have been introduced between CI_DRM_10154_full and Patchwork_20245_full: ### New Piglit tests (1) ### * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 42 8 8 4: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_20245_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-cleanup: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-cleanup.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][3] ([i915#3354]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/shard-snb6/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: NOTRUN -> [FAIL][4] ([i915#2846]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/shard-kbl7/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][5] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/shard-kbl2/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-glk: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/shard-glk4/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk7/igt@gem_exec_fair@basic-n...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/shard-glk6/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#2842] / [i915#3468]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-apl6/igt@gem_exec_fair@basic-n...@vecs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/shard-apl6/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-tglb7/igt@gem_exec_fair@basic-pace-s...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/shard-tglb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2849]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/shard-iclb8/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_whisper@basic-fds-forked: - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#118] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk9/igt@gem_exec_whis...@basic-fds-forked.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/shard-glk4/igt@gem_exec_whis...@basic-fds-forked.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/shard-apl3/igt@gem_huc_c...@huc-copy.html * igt@gem_mmap_gtt@big-copy-xy: - shard-glk: [PASS][18] -> [FAIL][19] ([i915#307]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk1/igt@gem_mmap_...@big-copy-xy.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/shard-glk9/igt@gem_mmap_...@big-copy-xy.html * igt@gem_mmap_gtt@cpuset-basic-small-copy: - shard-apl: NOTRUN -> [INCOMPLETE][20]
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for lpsp with hdmi/dp outputs
== Series Details == Series: lpsp with hdmi/dp outputs URL : https://patchwork.freedesktop.org/series/90827/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1207:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock
[Intel-gfx] ✗ Fi.CI.BAT: failure for Add Support for Plane Color Lut and CSC features
== Series Details ==
Series: Add Support for Plane Color Lut and CSC features
URL : https://patchwork.freedesktop.org/series/90825/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20249
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20249 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20249, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20249/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_20249:
### IGT changes ###
Possible regressions
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-snb-2600:[PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-snb-2600/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20249/fi-snb-2600/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
Known issues
Here are the changes found in Patchwork_20249 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][3] ([i915#3303]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20249/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
Warnings
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [SKIP][5] ([fdo#109271]) -> [FAIL][6] ([i915#579])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-guc/igt@i915_pm_...@basic-rte.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20249/fi-kbl-guc/igt@i915_pm_...@basic-rte.html
* igt@runner@aborted:
- fi-glk-dsi: [FAIL][7] ([i915#2426] / [i915#3363] /
[k.org#202321]) -> [FAIL][8] ([i915#3363] / [k.org#202321])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-glk-dsi/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20249/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-soraka: [FAIL][9] ([i915#1436] / [i915#3363]) -> [FAIL][10]
([i915#1436] / [i915#2426] / [i915#3363])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-soraka/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20249/fi-kbl-soraka/igt@run...@aborted.html
- fi-cml-u2: [FAIL][11] ([i915#3363] / [i915#3462]) -> [FAIL][12]
([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cml-u2/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20249/fi-cml-u2/igt@run...@aborted.html
- fi-cfl-guc: [FAIL][13] ([i915#2426] / [i915#3363]) -> [FAIL][14]
([i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cfl-guc/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20249/fi-cfl-guc/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (47 -> 41)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-kbl-7500u
fi-ctg-p8600 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_10154 -> Patchwork_20249
CI-20190529: 20190529
CI_DRM_10154: 810010ed3d29e0500d452a90010a88a0879f2b45 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6097: f823d8ec14b34a6dd2c0804c684b07b0a50f7bb7 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20249: bfb9d2884ac15872da12acd934c939dd45bdc427 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bfb9d2884ac1 drm/i915/xelpd: Enable plane gamma
525c6ebbb2c5 drm/i915/xelpd: Program
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] [RFC] tests/kms_plane_alpha_blend: Fix coverage-vs-premult-vs-constant tests
On Tue, Jun 01, 2021 at 05:15:39PM +0530, Vidya Srinivas wrote: > tests/kms_plane_alpha_blend: Fix coverage-vs-premult-vs-constant tests > > Few Gen11 systems show CRC mismatch. Make coverage-vs-premult-vs-constant > code similar to constant_alpha_min or basic_alpha > > Signed-off-by: Vidya Srinivas Please make the first line of the commit message a statement that tells what change you're making, and in the full text block state why that's done. "Fix a-b-c tests" is useless later when browsing oneliner git logs. It doesn't even tell which problem is fixed. Meaning, something like: == tests/kms_plane_alpha_blend: Don't set primary fb color in coverage-vs-premult-vs-constant Similar change has already been done in tests xxx and yyy. This fixes CRC mismatches seen with some Gen11 systems. Signed-off-by etc == -- Petri Latvala ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add Support for Plane Color Lut and CSC features
== Series Details == Series: Add Support for Plane Color Lut and CSC features URL : https://patchwork.freedesktop.org/series/90825/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Disable PSR around cdclk changes
> -Original Message-
> From: Mun, Gwan-gyeong
> Sent: Tuesday, June 1, 2021 3:48 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Souza, Jose ; Lisovskiy, Stanislav
> ; ville.syrj...@linux.intel.com; Roper,
> Matthew D ; Kahola, Mika
>
> Subject: [PATCH v2 2/2] drm/i915: Disable PSR around cdclk changes
>
> From: Ville Syrjälä
>
> AUX logic is often clocked from cdclk. Disable PSR to make sure there are no
> hw initiated AUX transactions in flight while we change the cdclk frequency.
>
> Cc: Mika Kahola
> Signed-off-by: Ville Syrjälä
> Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 4656a6edc3be..618a9e1e2b0c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -28,6 +28,7 @@
> #include "intel_cdclk.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
> +#include "intel_psr.h"
> #include "intel_sideband.h"
>
> /**
> @@ -1908,6 +1909,12 @@ static void intel_set_cdclk(struct
> drm_i915_private *dev_priv,
>
> intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
>
> + for_each_intel_encoder_with_psr(_priv->drm, encoder) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + intel_psr_pause(intel_dp);
> + }
> +
> /*
>* Lock aux/gmbus while we change cdclk in case those
>* functions use cdclk. Not all platforms/ports do, @@ -1930,6
> +1937,12 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
> }
> mutex_unlock(_priv->gmbus_mutex);
>
> + for_each_intel_encoder_with_psr(_priv->drm, encoder) {
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + intel_psr_resume(intel_dp);
> + }
> +
> if (drm_WARN(_priv->drm,
>intel_cdclk_changed(_priv->cdclk.hw, cdclk_config),
>"cdclk state doesn't match!\n")) {
> --
> 2.31.1
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add Support for Plane Color Lut and CSC features
== Series Details == Series: Add Support for Plane Color Lut and CSC features URL : https://patchwork.freedesktop.org/series/90825/ State : warning == Summary == $ dim checkpatch origin/drm-tip 68c5484bfdad drm: Add Enhanced Gamma and color lut range attributes a1e53948f9d0 drm: Add Plane Degamma Mode property 684c709fb80f drm: Add Plane Degamma Lut property -:45: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #45: FILE: drivers/gpu/drm/drm_atomic_uapi.c:602: + ret = drm_atomic_replace_property_blob_from_id(dev, + >degamma_lut, total: 0 errors, 0 warnings, 1 checks, 101 lines checked 2bf36d661d4d drm/i915/xelpd: Define Degamma Lut range struct for HDR planes 0c1eabc62705 drm/i915/xelpd: Add register definitions for Plane Degamma -:37: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #37: FILE: drivers/gpu/drm/i915/i915_reg.h:11315: +#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \ + _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe)) -:49: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #49: FILE: drivers/gpu/drm/i915/i915_reg.h:11327: +#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i)\ + _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe), \ + _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe)) -:61: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #61: FILE: drivers/gpu/drm/i915/i915_reg.h:11339: +#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_1(pipe), \ + _PLANE_PRE_CSC_GAMC_INDEX_2(pipe)) -:73: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #73: FILE: drivers/gpu/drm/i915/i915_reg.h:11351: +#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i)\ + _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \ + _PLANE_PRE_CSC_GAMC_DATA_2(pipe)) total: 0 errors, 0 warnings, 4 checks, 64 lines checked 258e15146869 drm/i915/xelpd: Enable plane color features b7ea85214efd drm/i915/xelpd: Add color capabilities of SDR planes 66e7c29201d7 drm/i915/xelpd: Program Plane Degamma Registers -:68: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #68: FILE: drivers/gpu/drm/i915/display/intel_color.c:2243: + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), -:74: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #74: FILE: drivers/gpu/drm/i915/display/intel_color.c:2249: + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), -:80: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #80: FILE: drivers/gpu/drm/i915/display/intel_color.c:2255: + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v); -:84: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #84: FILE: drivers/gpu/drm/i915/display/intel_color.c:2259: + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), -:114: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #114: FILE: drivers/gpu/drm/i915/display/intel_color.c:2289: + intel_de_write(dev_priv, PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), v); total: 0 errors, 5 warnings, 0 checks, 148 lines checked ae7be4f9a5ff drm/i915/xelpd: Add plane color check to glk_plane_color_ctl 1f1fa094a94e drm/i915/xelpd: Initialize plane color features ab01acc58f9c drm/i915/xelpd: Load plane color luts from atomic flip 66d7c2419b53 drm: Add Plane CTM property -:41: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #41: FILE: drivers/gpu/drm/drm_atomic_uapi.c:609: + ret = drm_atomic_replace_property_blob_from_id(dev, + >ctm, total: 0 errors, 0 warnings, 1 checks, 87 lines checked 08ee867daa81 drm: Add helper to attach Plane ctm property 9d7042c9e95e drm/i915/xelpd: Define Plane CSC Registers -:29: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #29: FILE: drivers/gpu/drm/i915/i915_reg.h:7411: +#define PLANE_CSC_COEFF(pipe, plane, index)_MMIO_PLANE(plane, \ + _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ + _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) -:29: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #29: FILE: drivers/gpu/drm/i915/i915_reg.h:7411: +#define PLANE_CSC_COEFF(pipe, plane, index)_MMIO_PLANE(plane, \ + _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ +
[Intel-gfx] ✓ Fi.CI.BAT: success for Enhance pipe color support for multi segmented luts
== Series Details ==
Series: Enhance pipe color support for multi segmented luts
URL : https://patchwork.freedesktop.org/series/90821/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20248
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/index.html
Known issues
Here are the changes found in Patchwork_20248 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][1] ([i915#3303]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][3] ([i915#1372]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
Warnings
* igt@runner@aborted:
- fi-cfl-8700k: [FAIL][5] ([i915#3363]) -> [FAIL][6] ([i915#2426] /
[i915#3363])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cfl-8700k/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-cfl-8700k/igt@run...@aborted.html
- fi-glk-dsi: [FAIL][7] ([i915#2426] / [i915#3363] /
[k.org#202321]) -> [FAIL][8] ([i915#3363] / [k.org#202321])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-glk-dsi/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-soraka: [FAIL][9] ([i915#1436] / [i915#3363]) -> [FAIL][10]
([i915#1436] / [i915#2426] / [i915#3363])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-soraka/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-kbl-soraka/igt@run...@aborted.html
- fi-kbl-guc: [FAIL][11] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][12] ([i915#1436] / [i915#3363])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-guc/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-kbl-guc/igt@run...@aborted.html
- fi-cfl-guc: [FAIL][13] ([i915#2426] / [i915#3363]) -> [FAIL][14]
([i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cfl-guc/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-cfl-guc/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (47 -> 42)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_10154 -> Patchwork_20248
CI-20190529: 20190529
CI_DRM_10154: 810010ed3d29e0500d452a90010a88a0879f2b45 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6097: f823d8ec14b34a6dd2c0804c684b07b0a50f7bb7 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20248: 69e66620a121b94c53f9b381c048c32f45eb4fe2 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
69e66620a121 drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
6a09b3df0e61 drm/i915/xelpd: Add Pipe Color Lut caps to platform config
185822ca6347 drm/i915/xelpd: Enable Pipe Degamma
0a9c33e8f72b drm/i915/xelpd: logarithmic gamma enabled only with advance gamma
mode
7709e4e8ae04 drm: Add Client Cap for advance gamma mode
0db66299eaaf drm/i915/xelpd: Attach gamma mode property
0abd23286aa0 drm/i915/xelpd: Add support for Logarithmic gamma mode
fbd5ad2e2de9 drm/i915/xelpd: Define color lut range structure
cbbd9a9e8e24 drm: Add gamma mode property
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/index.html
___
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[Intel-gfx] [PATCH 1/1] drm/i915/hdcp: Simplify code in intel_hdcp_auth_downstream()
If intel_hdcp_validate_v_prime() has been successful within the allowed
number of tries, we can directly call drm_dbg_kms() and "goto out" without
jumping out of the loop and repeatedly judging whether the operation is
successful. This can help us reduce an unnecessary if judgment. And it's
a little clearer to read.
No functional change.
Signed-off-by: Zhen Lei
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 24 ++-
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index d8570e14fe60..c32a854eda66 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -663,13 +663,13 @@ int intel_hdcp_auth_downstream(struct intel_connector
*connector)
ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo);
if (ret)
- goto err;
+ goto out;
if (drm_hdcp_check_ksvs_revoked(_priv->drm, ksv_fifo,
num_downstream) > 0) {
drm_err(_priv->drm, "Revoked Ksv(s) in ksv_fifo\n");
ret = -EPERM;
- goto err;
+ goto out;
}
/*
@@ -680,20 +680,16 @@ int intel_hdcp_auth_downstream(struct intel_connector
*connector)
ret = intel_hdcp_validate_v_prime(connector, shim,
ksv_fifo, num_downstream,
bstatus);
- if (!ret)
- break;
- }
-
- if (i == tries) {
- drm_dbg_kms(_priv->drm,
- "V Prime validation failed.(%d)\n", ret);
- goto err;
+ if (!ret) {
+ drm_dbg_kms(_priv->drm,
+ "HDCP is enabled (%d downstream devices)\n",
+ num_downstream);
+ goto out;
+ }
}
- drm_dbg_kms(_priv->drm, "HDCP is enabled (%d downstream devices)\n",
- num_downstream);
- ret = 0;
-err:
+ drm_dbg_kms(_priv->drm, "V Prime validation failed.(%d)\n", ret);
+out:
kfree(ksv_fifo);
return ret;
}
--
2.25.1
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[Intel-gfx] [PATCH] INTEL_DII: drm/i915/adl_p: Same slices mask is not same Dbuf state
We currently treat same slice mask as a same DBuf state and skip updating the Dbuf slices, if we detect that. This is wrong as if we have a multi to single pipe change or vice versa, that would be treated as a same Dbuf state and thus no changes required, so we don't get Mbus updated, causing issues. Solution: check also mbus_join, in addition to slices mask. Cc: Ville Syrjälä Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/intel_pm.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 00f3dead20ad..804d83486e81 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8093,7 +8093,8 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state) intel_atomic_get_old_dbuf_state(state); if (!new_dbuf_state || - new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices) + ((new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices) + && (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))) return; WARN_ON(!new_dbuf_state->base.changed); @@ -8113,7 +8114,8 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state) intel_atomic_get_old_dbuf_state(state); if (!new_dbuf_state || - new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices) + ((new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices) + && (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))) return; WARN_ON(!new_dbuf_state->base.changed); -- 2.24.1.485.gad05a3d8e5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v7 14/15] dt-bindings: of: Add restricted DMA pool
On Wed, May 26, 2021 at 01:13:22PM +0100, Will Deacon wrote:
> On Tue, May 18, 2021 at 02:42:14PM +0800, Claire Chang wrote:
> > @@ -138,4 +160,9 @@ one for multimedia processing (named
> > multimedia-memory@7700, 64MiB).
> > memory-region = <_reserved>;
> > /* ... */
> > };
> > +
> > + pcie_device: pcie_device@0,0 {
> > + memory-region = <_dma_mem_reserved>;
> > + /* ... */
> > + };
>
> I still don't understand how this works for individual PCIe devices -- how
> is dev->of_node set to point at the node you have above?
>
> I tried adding the memory-region to the host controller instead, and then
> I see it crop up in dmesg:
>
> | pci-host-generic 4000.pci: assigned reserved memory node
> restricted_dma_mem_reserved
>
> but none of the actual PCI devices end up with 'dma_io_tlb_mem' set, and
> so the restricted DMA area is not used. In fact, swiotlb isn't used at all.
>
> What am I missing to make this work with PCIe devices?
Aha, looks like we're just missing the logic to inherit the DMA
configuration. The diff below gets things working for me.
Will
--->8
diff --git a/drivers/of/address.c b/drivers/of/address.c
index c562a9ff5f0b..bf499fdd6e93 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -1113,25 +1113,25 @@ bool of_dma_is_coherent(struct device_node *np)
}
EXPORT_SYMBOL_GPL(of_dma_is_coherent);
-int of_dma_set_restricted_buffer(struct device *dev)
+int of_dma_set_restricted_buffer(struct device *dev, struct device_node *np)
{
- struct device_node *node;
int count, i;
- if (!dev->of_node)
+ if (!np)
return 0;
- count = of_property_count_elems_of_size(dev->of_node, "memory-region",
+ count = of_property_count_elems_of_size(np, "memory-region",
sizeof(phandle));
for (i = 0; i < count; i++) {
- node = of_parse_phandle(dev->of_node, "memory-region", i);
+ struct device_node *node;
+
+ node = of_parse_phandle(np, "memory-region", i);
/* There might be multiple memory regions, but only one
-* restriced-dma-pool region is allowed.
+* restricted-dma-pool region is allowed.
*/
if (of_device_is_compatible(node, "restricted-dma-pool") &&
of_device_is_available(node))
- return of_reserved_mem_device_init_by_idx(
- dev, dev->of_node, i);
+ return of_reserved_mem_device_init_by_idx(dev, np, i);
}
return 0;
diff --git a/drivers/of/device.c b/drivers/of/device.c
index d8d865223e51..2defdca418ec 100644
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -166,7 +166,7 @@ int of_dma_configure_id(struct device *dev, struct
device_node *np,
arch_setup_dma_ops(dev, dma_start, size, iommu, coherent);
if (!iommu)
- return of_dma_set_restricted_buffer(dev);
+ return of_dma_set_restricted_buffer(dev, np);
return 0;
}
diff --git a/drivers/of/of_private.h b/drivers/of/of_private.h
index 9fc874548528..8fde97565d11 100644
--- a/drivers/of/of_private.h
+++ b/drivers/of/of_private.h
@@ -163,14 +163,15 @@ struct bus_dma_region;
#if defined(CONFIG_OF_ADDRESS) && defined(CONFIG_HAS_DMA)
int of_dma_get_range(struct device_node *np,
const struct bus_dma_region **map);
-int of_dma_set_restricted_buffer(struct device *dev);
+int of_dma_set_restricted_buffer(struct device *dev, struct device_node *np);
#else
static inline int of_dma_get_range(struct device_node *np,
const struct bus_dma_region **map)
{
return -ENODEV;
}
-static inline int of_dma_set_restricted_buffer(struct device *dev)
+static inline int of_dma_set_restricted_buffer(struct device *dev,
+ struct device_node *np)
{
return -ENODEV;
}
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[Intel-gfx] [PATCH] drm/i915/selftests: Fix return value check in live_breadcrumbs_smoketest()
In case of error, the function live_context() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().
Fixes: 52c0fdb25c7c9 ("drm/i915: Replace global breadcrumbs ...")
Reported-by: Hulk Robot
Signed-off-by: Zhihao Cheng
---
drivers/gpu/drm/i915/selftests/i915_request.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index ee8e753d98ce..eae0abd614cb 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -1592,8 +1592,8 @@ static int live_breadcrumbs_smoketest(void *arg)
for (n = 0; n < smoke[0].ncontexts; n++) {
smoke[0].contexts[n] = live_context(i915, file);
- if (!smoke[0].contexts[n]) {
- ret = -ENOMEM;
+ if (IS_ERR(smoke[0].contexts[n])) {
+ ret = PTR_ERR(smoke[0].contexts[n]);
goto out_contexts;
}
}
--
2.25.4
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Re: [Intel-gfx] [PATCH v7 14/15] dt-bindings: of: Add restricted DMA pool
On Thu, May 27, 2021 at 08:48:59PM +0800, Claire Chang wrote:
> On Thu, May 27, 2021 at 7:35 PM Will Deacon wrote:
> >
> > On Thu, May 27, 2021 at 07:29:20PM +0800, Claire Chang wrote:
> > > On Wed, May 26, 2021 at 11:53 PM Will Deacon wrote:
> > > >
> > > > On Wed, May 26, 2021 at 01:13:22PM +0100, Will Deacon wrote:
> > > > > On Tue, May 18, 2021 at 02:42:14PM +0800, Claire Chang wrote:
> > > > > > @@ -138,4 +160,9 @@ one for multimedia processing (named
> > > > > > multimedia-memory@7700, 64MiB).
> > > > > > memory-region = <_reserved>;
> > > > > > /* ... */
> > > > > > };
> > > > > > +
> > > > > > + pcie_device: pcie_device@0,0 {
> > > > > > + memory-region = <_dma_mem_reserved>;
> > > > > > + /* ... */
> > > > > > + };
> > > > >
> > > > > I still don't understand how this works for individual PCIe devices
> > > > > -- how
> > > > > is dev->of_node set to point at the node you have above?
> > > > >
> > > > > I tried adding the memory-region to the host controller instead, and
> > > > > then
> > > > > I see it crop up in dmesg:
> > > > >
> > > > > | pci-host-generic 4000.pci: assigned reserved memory node
> > > > > restricted_dma_mem_reserved
> > > > >
> > > > > but none of the actual PCI devices end up with 'dma_io_tlb_mem' set,
> > > > > and
> > > > > so the restricted DMA area is not used. In fact, swiotlb isn't used
> > > > > at all.
> > > > >
> > > > > What am I missing to make this work with PCIe devices?
> > > >
> > > > Aha, looks like we're just missing the logic to inherit the DMA
> > > > configuration. The diff below gets things working for me.
> > >
> > > I guess what was missing is the reg property in the pcie_device node.
> > > Will update the example dts.
> >
> > Thanks. I still think something like my diff makes sense, if you wouldn't
> > mind including
> > it, as it allows restricted DMA to be used for situations where the PCIe
> > topology is not static.
> >
> > Perhaps we should prefer dev->of_node if it exists, but then use the node
> > of the host bridge's parent node otherwise?
>
> Sure. Let me add in the next version.
Brill, thanks! I'll take it for a spin once it lands on the list.
Will
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[Intel-gfx] [PATCH] drm/i915/gem: Remove the repeated declaration
Function 'i915_gem_object_truncate' is declared twice, so remove the repeated declaration. Cc: Jani Nikula Cc: Joonas Lahtinen Cc: Rodrigo Vivi Signed-off-by: Shaokun Zhang --- drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index 2ebd79537aea..9226f122c329 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -79,7 +79,6 @@ void i915_gem_flush_free_objects(struct drm_i915_private *i915); struct sg_table * __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj); -void i915_gem_object_truncate(struct drm_i915_gem_object *obj); /** * i915_gem_object_lookup_rcu - look up a temporary GEM object from its handle -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/1] drm/i915/hdcp: Simplify code in intel_hdcp_auth_downstream()
On 2021/5/27 18:04, Jani Nikula wrote:
> On Thu, 27 May 2021, Zhen Lei wrote:
>> If intel_hdcp_validate_v_prime() has been successful within the allowed
>> number of tries, we can directly call drm_dbg_kms() and "goto out" without
>> jumping out of the loop and repeatedly judging whether the operation is
>> successful. This can help us reduce an unnecessary if judgment. And it's
>> a little clearer to read.
>
> Generally I think the "happy day scenario" should be at the topmost
> indentation level and not buried in the ifs with a goto exit.
for (xxx) {
if (a == b)
return found;
}
At least this way of writing is common.
>
> BR,
> Jani.
>
>>
>> No functional change.
>>
>> Signed-off-by: Zhen Lei
>> ---
>> drivers/gpu/drm/i915/display/intel_hdcp.c | 24 ++-
>> 1 file changed, 10 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
>> b/drivers/gpu/drm/i915/display/intel_hdcp.c
>> index d8570e14fe60..c32a854eda66 100644
>> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
>> @@ -663,13 +663,13 @@ int intel_hdcp_auth_downstream(struct intel_connector
>> *connector)
>>
>> ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo);
>> if (ret)
>> -goto err;
>> +goto out;
>>
>> if (drm_hdcp_check_ksvs_revoked(_priv->drm, ksv_fifo,
>> num_downstream) > 0) {
>> drm_err(_priv->drm, "Revoked Ksv(s) in ksv_fifo\n");
>> ret = -EPERM;
>> -goto err;
>> +goto out;
>> }
>>
>> /*
>> @@ -680,20 +680,16 @@ int intel_hdcp_auth_downstream(struct intel_connector
>> *connector)
>> ret = intel_hdcp_validate_v_prime(connector, shim,
>>ksv_fifo, num_downstream,
>>bstatus);
>> -if (!ret)
>> -break;
>> -}
>> -
>> -if (i == tries) {
>> -drm_dbg_kms(_priv->drm,
>> -"V Prime validation failed.(%d)\n", ret);
>> -goto err;
>> +if (!ret) {
>> +drm_dbg_kms(_priv->drm,
>> +"HDCP is enabled (%d downstream devices)\n",
>> +num_downstream);
>> +goto out;
>> +}
>> }
>>
>> -drm_dbg_kms(_priv->drm, "HDCP is enabled (%d downstream devices)\n",
>> -num_downstream);
>> -ret = 0;
>> -err:
>> +drm_dbg_kms(_priv->drm, "V Prime validation failed.(%d)\n", ret);
>> +out:
>> kfree(ksv_fifo);
>> return ret;
>> }
>
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Re: [Intel-gfx] Bug: 5.12.5 - list_add double add at __i915_gem_object_make_shrinkable+0xa6/0xe0
On Mon, 2021-05-24 at 14:38 +0100, Matthew Auld wrote:
> On Mon, 24 May 2021 at 13:05, Hillf Danton wrote:
> >
> > On Sun, 23 May 2021 12:47:34 -0700 Philippe Troin wrote:
> > > Found the following bug on a FUJITSU LIFEBOOK S6520.
> > >
> > > The kernel crash happens when selecting a user from the gdm login
> > > screen right after boot.
> > > The same hardware has no problems with 5.11.21.
>
> The trace looks similar to something that was fixed in 8777d17b68dc
> ("drm/i915/gem: Pin the L-shape quirked object as unshrinkable") which
> should now be in drm-tip. Could you try that? Otherwise could you
> please file a new bug report at
> https://gitlab.freedesktop.org/drm/intel/?
I verified that drm-tip is working as of
d6d3a2a996af7a82e567e96a19410ac9d7246794.
This issue was tracked in the Fedora bugzilla at
https://bugzilla.redhat.com/show_bug.cgi?id=1963782
Thanks.
Phil.
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[Intel-gfx] [PATCH 1/1] drm/i915/selftests: Fix error return code in live_parallel_switch()
The error code returned from intel_context_create() should be propagated
instead of 0, as done elsewhere in this function.
Fixes: 50d16d44cce4 ("drm/i915/selftests: Exercise context switching in
parallel")
Reported-by: Hulk Robot
Signed-off-by: Zhen Lei
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 5fef592390cb..7db9e31da385 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -338,8 +338,10 @@ static int live_parallel_switch(void *arg)
continue;
ce = intel_context_create(data[m].ce[0]->engine);
- if (IS_ERR(ce))
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
goto out;
+ }
err = intel_context_pin(ce);
if (err) {
--
2.25.1
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Re: [Intel-gfx] [PATCH v7 14/15] dt-bindings: of: Add restricted DMA pool
On Thu, May 27, 2021 at 07:29:20PM +0800, Claire Chang wrote:
> On Wed, May 26, 2021 at 11:53 PM Will Deacon wrote:
> >
> > On Wed, May 26, 2021 at 01:13:22PM +0100, Will Deacon wrote:
> > > On Tue, May 18, 2021 at 02:42:14PM +0800, Claire Chang wrote:
> > > > @@ -138,4 +160,9 @@ one for multimedia processing (named
> > > > multimedia-memory@7700, 64MiB).
> > > > memory-region = <_reserved>;
> > > > /* ... */
> > > > };
> > > > +
> > > > + pcie_device: pcie_device@0,0 {
> > > > + memory-region = <_dma_mem_reserved>;
> > > > + /* ... */
> > > > + };
> > >
> > > I still don't understand how this works for individual PCIe devices -- how
> > > is dev->of_node set to point at the node you have above?
> > >
> > > I tried adding the memory-region to the host controller instead, and then
> > > I see it crop up in dmesg:
> > >
> > > | pci-host-generic 4000.pci: assigned reserved memory node
> > > restricted_dma_mem_reserved
> > >
> > > but none of the actual PCI devices end up with 'dma_io_tlb_mem' set, and
> > > so the restricted DMA area is not used. In fact, swiotlb isn't used at
> > > all.
> > >
> > > What am I missing to make this work with PCIe devices?
> >
> > Aha, looks like we're just missing the logic to inherit the DMA
> > configuration. The diff below gets things working for me.
>
> I guess what was missing is the reg property in the pcie_device node.
> Will update the example dts.
Thanks. I still think something like my diff makes sense, if you wouldn't mind
including
it, as it allows restricted DMA to be used for situations where the PCIe
topology is not static.
Perhaps we should prefer dev->of_node if it exists, but then use the node
of the host bridge's parent node otherwise?
Will
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Re: [Intel-gfx] [PATCH v2] drm/i915/display: Introduce new intel_psr_pause/resume function
Another patchset has been uploaded. Please ignore this patch.
On Tue, 2021-06-01 at 12:53 +0300, Gwan-gyeong Mun wrote:
> This introduces the following function that can exit and activate a
> psr
> source when intel_psr is already enabled.
>
> - intel_psr_pause(): Pause current PSR. It deactivates current psr
> state.
> - intel_psr_resume(): Resume paused PSR. It activates paused psr
> state.
>
> v2: Address Jose's review comment.
> - Remove unneeded changes around the intel_psr_enable().
> - Add intel_psr_post_exit() which processes waiting until PSR is
> idle
> and WA for SelectiveFetch.
>
> Cc: José Roberto de Souza
> Cc: Stanislav Lisovskiy
> Cc: Ville Syrjälä
> Signed-off-by: Gwan-gyeong Mun
> Signed-off-by: Matt Roper
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 84 -
> --
> drivers/gpu/drm/i915/display/intel_psr.h | 2 +
> 3 files changed, 76 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b8d1f702d808..ee7cbdd7db87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1482,6 +1482,7 @@ struct intel_psr {
> bool sink_support;
> bool source_support;
> bool enabled;
> + bool paused;
> enum pipe pipe;
> enum transcoder transcoder;
> bool active;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 000e1ffe8c05..4ff71e529cd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1113,6 +1113,7 @@ static void intel_psr_enable_locked(struct
> intel_dp *intel_dp,
> intel_psr_enable_sink(intel_dp);
> intel_psr_enable_source(intel_dp);
> intel_dp->psr.enabled = true;
> + intel_dp->psr.paused = false;
>
> intel_psr_activate(intel_dp);
> }
> @@ -1182,22 +1183,12 @@ static void intel_psr_exit(struct intel_dp
> *intel_dp)
> intel_dp->psr.active = false;
> }
>
> -static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> +static void intel_psr_post_exit(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> i915_reg_t psr_status;
> u32 psr_status_mask;
>
> - lockdep_assert_held(_dp->psr.lock);
> -
> - if (!intel_dp->psr.enabled)
> - return;
> -
> - drm_dbg_kms(_priv->drm, "Disabling PSR%s\n",
> - intel_dp->psr.psr2_enabled ? "2" : "1");
> -
> - intel_psr_exit(intel_dp);
> -
> if (intel_dp->psr.psr2_enabled) {
> psr_status = EDP_PSR2_STATUS(intel_dp-
> >psr.transcoder);
> psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
> @@ -1217,6 +1208,22 @@ static void intel_psr_disable_locked(struct
> intel_dp *intel_dp)
> IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> +}
> +
> +static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + lockdep_assert_held(_dp->psr.lock);
> +
> + if (!intel_dp->psr.enabled)
> + return;
> +
> + drm_dbg_kms(_priv->drm, "Disabling PSR%s\n",
> + intel_dp->psr.psr2_enabled ? "2" : "1");
> +
> + intel_psr_exit(intel_dp);
> + intel_psr_post_exit(intel_dp);
>
> /* Disable PSR on Sink */
> drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, 0);
> @@ -1254,6 +1261,61 @@ void intel_psr_disable(struct intel_dp
> *intel_dp,
> cancel_delayed_work_sync(_dp->psr.dc3co_work);
> }
>
> +/**
> + * intel_psr_pause - Pause PSR
> + * @intel_dp: Intel DP
> + *
> + * This function need to be called after enabling psr.
> + */
> +void intel_psr_pause(struct intel_dp *intel_dp)
> +{
> + struct intel_psr *psr = _dp->psr;
> +
> + if (!CAN_PSR(intel_dp))
> + return;
> +
> + mutex_lock(>lock);
> +
> + if (!psr->active) {
> + mutex_unlock(>lock);
> + return;
> + }
> +
> + intel_psr_exit(intel_dp);
> + intel_psr_post_exit(intel_dp);
> + psr->paused = true;
> +
> + mutex_unlock(>lock);
> +
> + cancel_work_sync(>work);
> + cancel_delayed_work_sync(>dc3co_work);
> +}
> +
> +/**
> + * intel_psr_resume - Resume PSR
> + * @intel_dp: Intel DP
> + *
> + * This function need to be called after pausing psr.
> + */
> +void intel_psr_resume(struct intel_dp *intel_dp)
> +{
> + struct intel_psr *psr = _dp->psr;
> +
> + if (!CAN_PSR(intel_dp))
> + return;
> +
> + mutex_lock(>lock);
> +
> + if (!psr->paused)
> +
[Intel-gfx] [PATCH v2 2/2] drm/i915: Disable PSR around cdclk changes
From: Ville Syrjälä
AUX logic is often clocked from cdclk. Disable PSR to make sure
there are no hw initiated AUX transactions in flight while we
change the cdclk frequency.
Cc: Mika Kahola
Signed-off-by: Ville Syrjälä
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4656a6edc3be..618a9e1e2b0c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -28,6 +28,7 @@
#include "intel_cdclk.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_psr.h"
#include "intel_sideband.h"
/**
@@ -1908,6 +1909,12 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
+ for_each_intel_encoder_with_psr(_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_psr_pause(intel_dp);
+ }
+
/*
* Lock aux/gmbus while we change cdclk in case those
* functions use cdclk. Not all platforms/ports do,
@@ -1930,6 +1937,12 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
}
mutex_unlock(_priv->gmbus_mutex);
+ for_each_intel_encoder_with_psr(_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_psr_resume(intel_dp);
+ }
+
if (drm_WARN(_priv->drm,
intel_cdclk_changed(_priv->cdclk.hw, cdclk_config),
"cdclk state doesn't match!\n")) {
--
2.31.1
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[Intel-gfx] [PATCH v2 1/2] drm/i915/display: Introduce new intel_psr_pause/resume function
This introduces the following function that can exit and activate a psr
source when intel_psr is already enabled.
- intel_psr_pause(): Pause current PSR. It deactivates current psr state.
- intel_psr_resume(): Resume paused PSR. It activates paused psr state.
v2: Address Jose's review comment.
- Remove unneeded changes around the intel_psr_enable().
- Add intel_psr_post_exit() which processes waiting until PSR is idle
and WA for SelectiveFetch.
Cc: José Roberto de Souza
Cc: Stanislav Lisovskiy
Cc: Ville Syrjälä
Signed-off-by: Gwan-gyeong Mun
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 84 ---
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
3 files changed, 76 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index b8d1f702d808..ee7cbdd7db87 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1482,6 +1482,7 @@ struct intel_psr {
bool sink_support;
bool source_support;
bool enabled;
+ bool paused;
enum pipe pipe;
enum transcoder transcoder;
bool active;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 000e1ffe8c05..4ff71e529cd3 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1113,6 +1113,7 @@ static void intel_psr_enable_locked(struct intel_dp
*intel_dp,
intel_psr_enable_sink(intel_dp);
intel_psr_enable_source(intel_dp);
intel_dp->psr.enabled = true;
+ intel_dp->psr.paused = false;
intel_psr_activate(intel_dp);
}
@@ -1182,22 +1183,12 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
intel_dp->psr.active = false;
}
-static void intel_psr_disable_locked(struct intel_dp *intel_dp)
+static void intel_psr_post_exit(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
i915_reg_t psr_status;
u32 psr_status_mask;
- lockdep_assert_held(_dp->psr.lock);
-
- if (!intel_dp->psr.enabled)
- return;
-
- drm_dbg_kms(_priv->drm, "Disabling PSR%s\n",
- intel_dp->psr.psr2_enabled ? "2" : "1");
-
- intel_psr_exit(intel_dp);
-
if (intel_dp->psr.psr2_enabled) {
psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
@@ -1217,6 +1208,22 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
+}
+
+static void intel_psr_disable_locked(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ lockdep_assert_held(_dp->psr.lock);
+
+ if (!intel_dp->psr.enabled)
+ return;
+
+ drm_dbg_kms(_priv->drm, "Disabling PSR%s\n",
+ intel_dp->psr.psr2_enabled ? "2" : "1");
+
+ intel_psr_exit(intel_dp);
+ intel_psr_post_exit(intel_dp);
/* Disable PSR on Sink */
drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, 0);
@@ -1254,6 +1261,61 @@ void intel_psr_disable(struct intel_dp *intel_dp,
cancel_delayed_work_sync(_dp->psr.dc3co_work);
}
+/**
+ * intel_psr_pause - Pause PSR
+ * @intel_dp: Intel DP
+ *
+ * This function need to be called after enabling psr.
+ */
+void intel_psr_pause(struct intel_dp *intel_dp)
+{
+ struct intel_psr *psr = _dp->psr;
+
+ if (!CAN_PSR(intel_dp))
+ return;
+
+ mutex_lock(>lock);
+
+ if (!psr->active) {
+ mutex_unlock(>lock);
+ return;
+ }
+
+ intel_psr_exit(intel_dp);
+ intel_psr_post_exit(intel_dp);
+ psr->paused = true;
+
+ mutex_unlock(>lock);
+
+ cancel_work_sync(>work);
+ cancel_delayed_work_sync(>dc3co_work);
+}
+
+/**
+ * intel_psr_resume - Resume PSR
+ * @intel_dp: Intel DP
+ *
+ * This function need to be called after pausing psr.
+ */
+void intel_psr_resume(struct intel_dp *intel_dp)
+{
+ struct intel_psr *psr = _dp->psr;
+
+ if (!CAN_PSR(intel_dp))
+ return;
+
+ mutex_lock(>lock);
+
+ if (!psr->paused)
+ goto unlock;
+
+ psr->paused = false;
+ intel_psr_activate(intel_dp);
+
+unlock:
+ mutex_unlock(>lock);
+}
+
static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
b/drivers/gpu/drm/i915/display/intel_psr.h
index e3db85e97f4c..641521b101c8 100644
---
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enhance pipe color support for multi segmented luts
== Series Details == Series: Enhance pipe color support for multi segmented luts URL : https://patchwork.freedesktop.org/series/90821/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Introduce new intel_psr_pause/resume function
== Series Details ==
Series: drm/i915/display: Introduce new intel_psr_pause/resume function
URL : https://patchwork.freedesktop.org/series/90819/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20247
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/index.html
Known issues
Here are the changes found in Patchwork_20247 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][1] ([i915#3303]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][3] ([i915#1372]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
Warnings
* igt@i915_selftest@live@execlists:
- fi-icl-u2: [INCOMPLETE][5] ([i915#2782] / [i915#3462]) ->
[DMESG-FAIL][6] ([i915#3462])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-icl-u2/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-icl-u2/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-icl-u2: [FAIL][7] ([i915#2782] / [i915#3363]) -> [FAIL][8]
([i915#2426] / [i915#2782] / [i915#3363])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-icl-u2/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-icl-u2/igt@run...@aborted.html
- fi-kbl-r: [FAIL][9] ([i915#1436] / [i915#3363]) -> [FAIL][10]
([i915#1436] / [i915#2426] / [i915#3363])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-r/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-kbl-r/igt@run...@aborted.html
- fi-kbl-soraka: [FAIL][11] ([i915#1436] / [i915#3363]) -> [FAIL][12]
([i915#1436] / [i915#2426] / [i915#3363])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-soraka/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-kbl-soraka/igt@run...@aborted.html
- fi-kbl-7500u: [FAIL][13] ([i915#1436] / [i915#3363]) -> [FAIL][14]
([i915#1436] / [i915#2426] / [i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7500u/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-kbl-7500u/igt@run...@aborted.html
- fi-cfl-guc: [FAIL][15] ([i915#2426] / [i915#3363]) -> [FAIL][16]
([i915#3363])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cfl-guc/igt@run...@aborted.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-cfl-guc/igt@run...@aborted.html
- fi-kbl-7567u: [FAIL][17] ([i915#1436] / [i915#3363]) -> [FAIL][18]
([i915#1436] / [i915#2426] / [i915#3363])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7567u/igt@run...@aborted.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/fi-kbl-7567u/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
Participating hosts (47 -> 41)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-kbl-guc fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_10154 -> Patchwork_20247
CI-20190529: 20190529
CI_DRM_10154: 810010ed3d29e0500d452a90010a88a0879f2b45 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6097: f823d8ec14b34a6dd2c0804c684b07b0a50f7bb7 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20247: fb189a25c075a0ca12cc40723571630361a4b10d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fb189a25c075 drm/i915/display: Introduce new intel_psr_pause/resume function
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20247/index.html
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add relocation exceptions for two other platforms (rev3)
On Tue, Jun 01, 2021 at 11:36:54AM +, Patchwork wrote: >Patch Details > >Series: drm/i915: Add relocation exceptions for two other platforms > (rev3) >URL: https://patchwork.freedesktop.org/series/89594/ > >State: failure > >Details: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/index.html > > CI Bug Log - changes from CI_DRM_10153_full -> Patchwork_20244_full > > Summary > >FAILURE > >Serious unknown changes coming with Patchwork_20244_full absolutely need >to be >verified manually. > >If you think the reported changes have nothing to do with the changes >introduced in Patchwork_20244_full, please notify your bug team to allow >them >to document this new failure mode, which will reduce false positives in >CI. > > Possible new issues > >Here are the unknown changes that may have been introduced in >Patchwork_20244_full: > > IGT changes > > Possible regressions > > * igt@kms_plane_lowres@pipe-a-tiling-y: > * shard-iclb: NOTRUN -> SKIP > > Piglit changes > > Possible regressions > > * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 >8 128 4 (NEW): > * pig-glk-j5005: NOTRUN -> INCOMPLETE +1 similar issue I don't think change is related to regression mentiontioned above. -- Zbigniew > > New tests > >New tests have been introduced between CI_DRM_10153_full and >Patchwork_20244_full: > > New Piglit tests (2) > > * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 >8 128 4: > > * Statuses : 1 incomplete(s) > * Exec time: [0.0] s > * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 >8 128 7: > > * Statuses : 1 incomplete(s) > * Exec time: [0.0] s > > Known issues > >Here are the changes found in Patchwork_20244_full that come from known >issues: > > IGT changes > > Issues hit > > * igt@gem_create@create-clear: > > * shard-glk: PASS -> FAIL ([i915#3160]) > * igt@gem_ctx_persistence@engines-hostile@rcs0: > > * shard-glk: PASS -> FAIL ([i915#2410]) > * igt@gem_ctx_persistence@legacy-engines-mixed: > > * shard-snb: NOTRUN -> SKIP ([fdo#109271] / [i915#1099]) +8 similar > issues > * igt@gem_ctx_persistence@many-contexts: > > * shard-tglb: PASS -> FAIL ([i915#2410]) > * igt@gem_eio@unwedge-stress: > > * shard-snb: NOTRUN -> FAIL ([i915#3354]) > * igt@gem_exec_fair@basic-deadline: > > * shard-apl: NOTRUN -> FAIL ([i915#2846]) > * igt@gem_exec_fair@basic-throttle@rcs0: > > * shard-glk: PASS -> FAIL ([i915#2842]) > * igt@gem_exec_params@secure-non-master: > > * shard-iclb: NOTRUN -> SKIP ([fdo#112283]) > * igt@gem_media_vme: > > * shard-skl: NOTRUN -> SKIP ([fdo#109271]) +37 similar issues > * igt@gem_mmap_gtt@cpuset-basic-small-copy: > > * shard-skl: PASS -> INCOMPLETE ([i915#198] / [i915#3468]) > * igt@gem_mmap_gtt@cpuset-basic-small-copy-odd: > > * shard-apl: NOTRUN -> INCOMPLETE ([i915#3468]) +1 similar issue > * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy: > > * shard-tglb: PASS -> INCOMPLETE ([i915#3468]) > * igt@gem_mmap_gtt@fault-concurrent-y: > > * shard-snb: NOTRUN -> INCOMPLETE ([i915#3468]) +1 similar issue > * igt@gem_pread@exhaustion: > > * shard-snb: NOTRUN -> WARN ([i915#2658]) > > * shard-skl: NOTRUN -> WARN ([i915#2658]) > > * igt@gem_userptr_blits@dmabuf-sync: > > * shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#3323]) > * igt@gem_userptr_blits@input-checking: > > * shard-snb: NOTRUN -> DMESG-WARN ([i915#3002]) > * igt@gem_userptr_blits@invalid-mmap-offset-unsync: > > * shard-iclb: NOTRUN -> SKIP ([i915#3297]) > * igt@gen9_exec_parse@batch-zero-length: > > * shard-iclb: NOTRUN -> SKIP ([fdo#112306]) > * igt@gen9_exec_parse@bb-large: > > * shard-apl: NOTRUN -> FAIL ([i915#3296]) > * igt@i915_pm_rpm@modeset-lpsp-stress: > > * shard-apl: NOTRUN -> SKIP ([fdo#109271]) +181 similar issues > * igt@i915_suspend@forcewake: > > * shard-kbl: PASS -> DMESG-WARN ([i915#180]) +3 similar issues > * igt@kms_big_fb@linear-16bpp-rotate-90: > > * shard-iclb: NOTRUN -> SKIP ([fdo#110725] / [fdo#111614]) > * igt@kms_color@pipe-b-ctm-0-5: > > * shard-skl: PASS -> DMESG-WARN ([i915#1982]) > * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: > > * shard-snb: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +33 > similar issues > > * shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) > >
Re: [Intel-gfx] [PATCH v9 07/15] drm: Add a prefetching memcpy_from_wc
On Tue, 01 Jun 2021, Thomas Hellström wrote:
> Reading out of write-combining mapped memory is typically very slow
> since the CPU doesn't prefetch. However some archs have special
> instructions to do this.
>
> So add a best-effort memcpy_from_wc taking dma-buf-map pointer
> arguments that attempts to use a fast prefetching memcpy and
> otherwise falls back to ordinary memcopies, taking the iomem tagging
> into account.
>
> The code is largely copied from i915_memcpy_from_wc.
>
> Cc: Daniel Vetter
> Cc: Christian König
> Suggested-by: Daniel Vetter
> Signed-off-by: Thomas Hellström
> Acked-by: Christian König
> Acked-by: Daniel Vetter
> ---
> v7:
> - Perform a memcpy even if warning with in_interrupt(). Suggested by
> Christian König.
> - Fix compilation failure on !X86 (Reported by kernel test robot
> l...@intel.com)
> v8:
> - Skip kerneldoc for drm_memcpy_init_early()
> - Export drm_memcpy_from_wc() also for non-x86.
> ---
> Documentation/gpu/drm-mm.rst | 2 +-
> drivers/gpu/drm/drm_cache.c | 148 +++
> drivers/gpu/drm/drm_drv.c| 2 +
> include/drm/drm_cache.h | 7 ++
> 4 files changed, 158 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst
> index 21be6deadc12..c66058c5bce7 100644
> --- a/Documentation/gpu/drm-mm.rst
> +++ b/Documentation/gpu/drm-mm.rst
> @@ -469,7 +469,7 @@ DRM MM Range Allocator Function References
> .. kernel-doc:: drivers/gpu/drm/drm_mm.c
> :export:
>
> -DRM Cache Handling
> +DRM Cache Handling and Fast WC memcpy()
> ==
The title underline needs to be as long as the title.
BR,
Jani.
>
> .. kernel-doc:: drivers/gpu/drm/drm_cache.c
> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
> index 79a50ef1250f..546599f19a93 100644
> --- a/drivers/gpu/drm/drm_cache.c
> +++ b/drivers/gpu/drm/drm_cache.c
> @@ -28,6 +28,7 @@
> * Authors: Thomas Hellström
> */
>
> +#include
> #include
> #include
> #include
> @@ -35,6 +36,9 @@
>
> #include
>
> +/* A small bounce buffer that fits on the stack. */
> +#define MEMCPY_BOUNCE_SIZE 128
> +
> #if defined(CONFIG_X86)
> #include
>
> @@ -209,3 +213,147 @@ bool drm_need_swiotlb(int dma_bits)
> return max_iomem > ((u64)1 << dma_bits);
> }
> EXPORT_SYMBOL(drm_need_swiotlb);
> +
> +static void memcpy_fallback(struct dma_buf_map *dst,
> + const struct dma_buf_map *src,
> + unsigned long len)
> +{
> + if (!dst->is_iomem && !src->is_iomem) {
> + memcpy(dst->vaddr, src->vaddr, len);
> + } else if (!src->is_iomem) {
> + dma_buf_map_memcpy_to(dst, src->vaddr, len);
> + } else if (!dst->is_iomem) {
> + memcpy_fromio(dst->vaddr, src->vaddr_iomem, len);
> + } else {
> + /*
> + * Bounce size is not performance tuned, but using a
> + * bounce buffer like this is significantly faster than
> + * resorting to ioreadxx() + iowritexx().
> + */
> + char bounce[MEMCPY_BOUNCE_SIZE];
> + void __iomem *_src = src->vaddr_iomem;
> + void __iomem *_dst = dst->vaddr_iomem;
> +
> + while (len >= MEMCPY_BOUNCE_SIZE) {
> + memcpy_fromio(bounce, _src, MEMCPY_BOUNCE_SIZE);
> + memcpy_toio(_dst, bounce, MEMCPY_BOUNCE_SIZE);
> + _src += MEMCPY_BOUNCE_SIZE;
> + _dst += MEMCPY_BOUNCE_SIZE;
> + len -= MEMCPY_BOUNCE_SIZE;
> + }
> + if (len) {
> + memcpy_fromio(bounce, _src, MEMCPY_BOUNCE_SIZE);
> + memcpy_toio(_dst, bounce, MEMCPY_BOUNCE_SIZE);
> + }
> + }
> +}
> +
> +#ifdef CONFIG_X86
> +
> +static DEFINE_STATIC_KEY_FALSE(has_movntdqa);
> +
> +static void __memcpy_ntdqa(void *dst, const void *src, unsigned long len)
> +{
> + kernel_fpu_begin();
> +
> + while (len >= 4) {
> + asm("movntdqa (%0), %%xmm0\n"
> + "movntdqa 16(%0), %%xmm1\n"
> + "movntdqa 32(%0), %%xmm2\n"
> + "movntdqa 48(%0), %%xmm3\n"
> + "movaps %%xmm0, (%1)\n"
> + "movaps %%xmm1, 16(%1)\n"
> + "movaps %%xmm2, 32(%1)\n"
> + "movaps %%xmm3, 48(%1)\n"
> + :: "r" (src), "r" (dst) : "memory");
> + src += 64;
> + dst += 64;
> + len -= 4;
> + }
> + while (len--) {
> + asm("movntdqa (%0), %%xmm0\n"
> + "movaps %%xmm0, (%1)\n"
> + :: "r" (src), "r" (dst) : "memory");
> + src += 16;
> + dst += 16;
> + }
> +
> + kernel_fpu_end();
> +}
> +
> +/*
> + * __drm_memcpy_from_wc copies @len bytes from @src to @dst using
> + * non-temporal instructions where available. Note that all arguments
> + *
Re: [Intel-gfx] [PATCH] drm/i915: Add relocation exceptions for two other platforms
On Tue, 01 Jun 2021, Zbigniew Kempczyński
wrote:
> We have established previously we stop using relocations starting
> from gen12 platforms with Tigerlake as an exception. We keep this
> statement but we want to enable relocations conditionally for
> Rocketlake and Alderlake under require_force_probe flag set.
>
> Keeping relocations under require_force_probe flag is interim solution
> until IGTs will be rewritten to use softpin.
>
> Signed-off-by: Zbigniew Kempczyński
> Cc: Dave Airlie
> Cc: Daniel Vetter
> Cc: Jason Ekstrand
> ---
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 26 +++
> 1 file changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 297143511f99..c0562dd14837 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -491,16 +491,32 @@ eb_unreserve_vma(struct eb_vma *ev)
> ev->flags &= ~__EXEC_OBJECT_RESERVED;
> }
>
> +static inline bool
Please don't use the inline keyword in .c files. Let the compiler do its
job.
BR,
Jani.
> +platform_has_relocs_enabled(const struct i915_execbuffer *eb)
> +{
> + /*
> + * Relocations are disallowed starting from gen12 with Tigerlake
> + * as an exception. We allow temporarily use relocations for Rocketlake
> + * and Alderlake when require_force_probe flag is set.
> + */
> +
> + if (INTEL_GEN(eb->i915) < 12 || IS_TIGERLAKE(eb->i915))
> + return true;
> +
> + if (INTEL_INFO(eb->i915)->require_force_probe &&
> + (IS_ROCKETLAKE(eb->i915) || IS_ALDERLAKE_S(eb->i915) ||
> + IS_ALDERLAKE_P(eb->i915)))
> + return true;
> +
> + return false;
> +}
> +
> static int
> eb_validate_vma(struct i915_execbuffer *eb,
> struct drm_i915_gem_exec_object2 *entry,
> struct i915_vma *vma)
> {
> - /* Relocations are disallowed for all platforms after TGL-LP. This
> - * also covers all platforms with local memory.
> - */
> - if (entry->relocation_count &&
> - INTEL_GEN(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
> + if (entry->relocation_count && !platform_has_relocs_enabled(eb))
> return -EINVAL;
>
> if (unlikely(entry->flags & eb->invalid_flags))
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH] drm/i915: Use DRIVER_NAME for tracing unattached requests
On Tue, Jun 1, 2021 at 1:13 PM Matthew Auld wrote: > On 31/05/2021 08:53, Daniel Vetter wrote: > > On Thu, May 20, 2021 at 4:28 PM Daniel Vetter wrote: > >> > >> On Thu, May 20, 2021 at 08:35:14AM +0100, Matthew Auld wrote: > >>> From: Chris Wilson > >>> > >>> The first tracepoint for a request is trace_dma_fence_init called before > >>> we have associated the request with a device. The tracepoint uses > >>> fence->ops->get_driver_name() as a pretty name, and as we try to report > >>> the device name this oopses as it is then NULL. Support the early > >>> tracepoint by reporting the DRIVER_NAME instead of the actual device > >>> name. > >>> > >>> Note that rq->engine remains during the course of request recycling > >>> (SLAB_TYPESAFE_BY_RCU). For the physical engines, the pointer remains > >>> valid, however a virtual engine may be destroyed after the request is > >>> retired. If we process a preempt-to-busy completed request along the > >>> virtual engine, we should make sure we mark the request as no longer > >>> belonging to the virtual engine to remove the dangling pointers from the > >>> tracepoint. > >> > >> Why can't we assign the request beforehand? The idea behind these > >> tracepoints is that they actually match up, if trace_dma_fence_init is > >> different, then we're breaking that. > > > > Ok I looked a bit more and pondered this a bit, and the initial > > tracepoint is called from dma_fence_init, where we haven't yet set up > > rq->engine properly. So that part makes sense, but should have a > > bigger comment that explains this a bit more and why we can't solve > > this in a neater way. Probably should also drop the unlikely(), this > > isn't a performance critical path, ever. > > > > The other changes thgouh feel like they should be split out into a > > separate path, since they solve a conceptually totally different > > issue: SLAB_TYPESAFE_BY_RCU recycling. > > Hmm, I thought it all stems from having to tread very carefully around > SLAB_TYPESAFE_BY_RCU? If this were "normal" code, we would just allocate > the rq, initialise it properly, including the rq->engine, and only then > do the dma_fence_init? Or am I missing something? Uh, if this is the bug it's a lot more scary. SLAB_TYPESAFE_BY_RCU should only rear it's ugly head if we do clever tricks where we access pointers to dma_fence under rcu alone, _without_ holding a full dma_fence reference. As soon as we have a full reference (and checked that the reference is to the right fence, since we could race) then all this recycle issues are gonne since the kref_t provides the right barrier here. If we hit any of the dma_fence tracepoints without a full reference held then I think that's a bug an needs to be fixed. Maybe we should have a debug WARN_ON(!kref(dma_fence)>0)); in these tracepoints somewhere to prevent this. Doing real dma_fence ops without a refcount held is really too much clever imo, and even if we'd find some microbenchmark showing that e.g. the dma_fence_get/put around some dma_fence function we're calling is measurable, it's not worth the cost in bugfixes like this one here. And when we do hold a full reference, then the only problem I've found is that we call dma_fence_init before the request is fully set up, which is at least semi-reasonable and can easily be checked for and explained with a comment. I thought I looked at the code, and reordering the request init to not have this problem looked tricky. Another issue which would also be very questionable design that we need to re-analyze would be if the engine can disappear before the last reference for the dma_fence has been dropped. I'd also just call this a bug in our refcounting, this should be impossible, but I haven't checked. In all these cases SLAB_TYPESAFE_BY_RCU shouldn't make the situation worse, and if it does, it's a separate issue really. > I'm happy to split it though. And I think that bit at least fixes the > user reported issue I think. So thinking about this some more, if you think this can be easily fixed by pushing the dma_fence_init past the initialization of rq->engine, then that would probably be the cleanest fix of all of them. Assuming none of the above consideration point at further trouble (but then further trouble probably needs separate patches to address them). > > And I'm honestly not sure about > > that one whether it's even correct, there's another patch floating > > around that sprinkles rcu_read_lock around some of these accesssors, > > and that would be a breakage of dma_fence interaces where outside of > > i915 rcu isn't required for this stuff. So imo should be split out, > > and come with a wider analysis of what's going on there and why and > > how exactly i915 works. > > > > In generally SLAB_TYPESAFE_BY_RCU is extremely dangerous and I'm > > frankly not sure we have the perf data (outside of contrived > > microbenchmarks) showing that it's needed and justifies all the costs > > it's encurring. > > Right, I can try to
Re: [Intel-gfx] [PATCH 1/2] drm/i915/xelpd: Enabling dithering after the CC1
-Original Message-
From: Modem, Bhanuprakash
Sent: Wednesday, May 26, 2021 9:29 PM
To: Jani Nikula ; intel-gfx@lists.freedesktop.org;
Varide, Nischal ; Shankar, Uma
; Gupta, Anshuman
Subject: RE: [Intel-gfx] [PATCH 1/2] drm/i915/xelpd: Enabling dithering after
the CC1
> From: Jani Nikula
> Sent: Wednesday, May 26, 2021 7:34 PM
> To: Modem, Bhanuprakash ; intel-
> g...@lists.freedesktop.org; Varide, Nischal ;
> Shankar, Uma ; Gupta, Anshuman
>
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/xelpd: Enabling
> dithering after the CC1
>
> On Wed, 26 May 2021, Bhanuprakash Modem wrote:
> > From: Nischal Varide
> >
> > If the panel is 12bpc then Dithering is not enabled in the Legacy
> > dithering block , instead its Enabled after the C1 CC1 pipe post
> > color space conversion.For a 6bpc pannel Dithering is enabled in
> > Legacy block.
> >
> > Signed-off-by: Nischal Varide
>
> When you're sending someone else's patches, you need to add your own
> Signed-off-by here.
Patch 2/2 in this series has a dependency on this patch. And I haven't made any
changes in this patch, so not added my Signed-off-by :-)
- Bhanu
>
> > ---
> > drivers/gpu/drm/i915/display/intel_color.c | 15 +++
> > drivers/gpu/drm/i915/display/intel_display.c | 7 ++-
> > drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> > 3 files changed, 23 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> > index dab892d2251b..4ad5bd849695 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -1605,6 +1605,20 @@ static u32 icl_csc_mode(const struct
> > intel_crtc_state
> *crtc_state)
> > return csc_mode;
> > }
> >
> > +static u32 dither_after_cc1_12bpc(const struct intel_crtc_state
> *crtc_state)
> > +{
> > + u32 gamma_mode = crtc_state->gamma_mode;
> > + struct drm_i915_private *i915 =
> > +to_i915(crtc_state->uapi.crtc->dev);
> > +
> > + if (DISPLAY_VER(i915) >= 13) {
> > + if (!crtc_state->dither_force_disable &&
> > + (crtc_state->pipe_bpp == 36))
> > + gamma_mode |= GAMMA_MODE_DITHER_AFTER_CC1;
> > + }
> > +
> > + return gamma_mode;
> > +}
> > +
> > static int icl_color_check(struct intel_crtc_state *crtc_state) {
> > int ret;
> > @@ -1615,6 +1629,7 @@ static int icl_color_check(struct
> > intel_crtc_state
> *crtc_state)
> >
> > crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
> >
> > + crtc_state->gamma_mode = dither_after_cc1_12bpc(crtc_state);
>
> We don't really do the kind of thing where you need a sequence of
> calls where one depends on the other, adding to the same state member.
> At a glance, this just looks wrong, superficially overwriting the
> previously set value. I'd just add the check at the end of icl_gamma_mode().
Yes ,agree and will do the needful here.
>
> > crtc_state->csc_mode = icl_csc_mode(crtc_state);
> >
> > crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> > index 0bb2e582c87f..1a658bdaeab6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -5741,7 +5741,12 @@ static void bdw_set_pipemisc(const struct
> intel_crtc_state *crtc_state)
> > break;
> > }
> >
> > - if (crtc_state->dither)
> > + /*
> > +* If 12bpc panel then, Enables dithering after the CC1 pipe
> > +* post color space conversion and not here
> > +*/
> > +
> > + if (crtc_state->dither && (crtc_state->pipe_bpp != 36))
>
> This now duplicates the pipe_bpp condition in two places, which seems
> a bit fragile. Maybe the check should be on gamma_mode? It would
> remove the need for the whole comment above.
There are two bits for controlling the dithering one at pipe level and other at
gamma level,
So the checks at two places .
> > val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
> >
> > if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> > index 4dbe79009c0e..5700097475c0 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6155,7 +6155,7 @@ enum {
> > #define PIPEMISC_DITHER_8_BPC(0 << 5)
> > #define PIPEMISC_DITHER_10_BPC (1 << 5)
> > #define PIPEMISC_DITHER_6_BPC(2 << 5)
> > -#define PIPEMISC_DITHER_12_BPC (3 << 5)
> > +#define PIPEMISC_DITHER_12_BPC (4 << 5)
>
> We already use the macro. You can't just replace this like this
> without an explanation. Why would this not break existing stuff?
>
> > #define PIPEMISC_DITHER_ENABLE (1 << 4)
> > #define PIPEMISC_DITHER_TYPE_MASK(3 << 2)
> > #define
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Only set bind_async_flags when concurrent access wa is not active, v3.
== Series Details ==
Series: drm/i915: Only set bind_async_flags when concurrent access wa is not
active, v3.
URL : https://patchwork.freedesktop.org/series/90818/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20246
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20246 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20246, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_20246:
### IGT changes ###
Possible regressions
* igt@gem_ctx_create@basic-files:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-apl-guc/igt@gem_ctx_cre...@basic-files.html
Known issues
Here are the changes found in Patchwork_20246 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- {fi-jsl-1}: [DMESG-WARN][3] ([i915#1222]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-jsl-1/igt@i915_selftest@live@gt_heartbeat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-jsl-1/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][5] ([i915#1372]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
Warnings
* igt@i915_selftest@live@execlists:
- fi-tgl-u2: [INCOMPLETE][7] ([i915#3462]) -> [DMESG-FAIL][8]
([i915#3462])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-tgl-u2/igt@i915_selftest@l...@execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-tgl-u2/igt@i915_selftest@l...@execlists.html
- fi-cml-s: [DMESG-FAIL][9] ([i915#3462]) -> [INCOMPLETE][10]
([i915#3462])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cml-s/igt@i915_selftest@l...@execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-cml-s/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-glk-dsi: [FAIL][11] ([i915#2426] / [i915#3363] /
[k.org#202321]) -> [FAIL][12] ([i915#3363] / [k.org#202321])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-glk-dsi/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-r: [FAIL][13] ([i915#1436] / [i915#3363]) -> [FAIL][14]
([i915#1569] / [i915#192] / [i915#193] / [i915#194] / [i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-r/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-kbl-r/igt@run...@aborted.html
- fi-kbl-soraka: [FAIL][15] ([i915#1436] / [i915#3363]) -> [FAIL][16]
([i915#1436] / [i915#2426] / [i915#3363])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-soraka/igt@run...@aborted.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-kbl-soraka/igt@run...@aborted.html
- fi-cml-u2: [FAIL][17] ([i915#3363] / [i915#3462]) -> [FAIL][18]
([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cml-u2/igt@run...@aborted.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-cml-u2/igt@run...@aborted.html
- fi-bxt-dsi: [FAIL][19] ([i915#3363]) -> [FAIL][20] ([i915#2426] /
[i915#3363])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-bxt-dsi/igt@run...@aborted.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20246/fi-bxt-dsi/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1222]: https://gitlab.freedesktop.org/drm/intel/issues/1222
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569
[i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192
[i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193
[i915#194]:
[Intel-gfx] [PATCH i-g-t] [RFC] tests/kms_plane_alpha_blend: Fix coverage-vs-premult-vs-constant tests
Few Gen11 systems show CRC mismatch. Make coverage-vs-premult-vs-constant
code similar to constant_alpha_min or basic_alpha
Signed-off-by: Vidya Srinivas
---
tests/kms_plane_alpha_blend.c | 4
1 file changed, 4 deletions(-)
diff --git a/tests/kms_plane_alpha_blend.c b/tests/kms_plane_alpha_blend.c
index a37cb27c7d62..224d79bd1749 100644
--- a/tests/kms_plane_alpha_blend.c
+++ b/tests/kms_plane_alpha_blend.c
@@ -447,10 +447,6 @@ static void coverage_premult_constant(data_t *data, enum
pipe pipe, igt_plane_t
igt_display_t *display = >display;
igt_crc_t ref_crc = {}, crc = {};
- /* Set a background color on the primary fb for testing */
- if (plane->type != DRM_PLANE_TYPE_PRIMARY)
- igt_plane_set_fb(igt_pipe_get_plane_type(>pipes[pipe],
DRM_PLANE_TYPE_PRIMARY), >gray_fb);
-
igt_plane_set_prop_enum(plane, IGT_PLANE_PIXEL_BLEND_MODE, "Coverage");
igt_plane_set_fb(plane, >argb_fb_cov_7e);
igt_display_commit2(display, COMMIT_ATOMIC);
--
2.7.4
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add relocation exceptions for two other platforms (rev3)
== Series Details == Series: drm/i915: Add relocation exceptions for two other platforms (rev3) URL : https://patchwork.freedesktop.org/series/89594/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10153_full -> Patchwork_20244_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20244_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20244_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20244_full: ### IGT changes ### Possible regressions * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: NOTRUN -> [SKIP][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-iclb8/igt@kms_plane_low...@pipe-a-tiling-y.html ### Piglit changes ### Possible regressions * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 8 128 4 (NEW): - pig-glk-j5005: NOTRUN -> [INCOMPLETE][2] +1 similar issue [2]: None New tests - New tests have been introduced between CI_DRM_10153_full and Patchwork_20244_full: ### New Piglit tests (2) ### * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 8 128 4: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 8 128 7: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_20244_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-clear: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#3160]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-glk6/igt@gem_cre...@create-clear.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-glk7/igt@gem_cre...@create-clear.html * igt@gem_ctx_persistence@engines-hostile@rcs0: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2410]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-glk9/igt@gem_ctx_persistence@engines-host...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-glk9/igt@gem_ctx_persistence@engines-host...@rcs0.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_ctx_persistence@many-contexts: - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2410]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-tglb5/igt@gem_ctx_persiste...@many-contexts.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-tglb7/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][10] ([i915#3354]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-snb5/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][11] ([i915#2846]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-apl1/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-glk2/igt@gem_exec_fair@basic-throt...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_params@secure-non-master: - shard-iclb: NOTRUN -> [SKIP][14] ([fdo#112283]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-iclb8/igt@gem_exec_par...@secure-non-master.html * igt@gem_media_vme: - shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271]) +37 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-skl8/igt@gem_media_vme.html * igt@gem_mmap_gtt@cpuset-basic-small-copy: - shard-skl: [PASS][16] -> [INCOMPLETE][17] ([i915#198] / [i915#3468]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-skl1/igt@gem_mmap_...@cpuset-basic-small-copy.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20244/shard-skl3/igt@gem_mmap_...@cpuset-basic-small-copy.html * igt@gem_mmap_gtt@cpuset-basic-small-copy-odd: - shard-apl: NOTRUN -> [INCOMPLETE][18] ([i915#3468]) +1 similar issue [18]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Only set bind_async_flags when concurrent access wa is not active, v3.
== Series Details == Series: drm/i915: Only set bind_async_flags when concurrent access wa is not active, v3. URL : https://patchwork.freedesktop.org/series/90818/ State : warning == Summary == $ dim checkpatch origin/drm-tip 48e0a3099384 drm/i915: Only set bind_async_flags when concurrent access wa is not active, v3. -:74: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #74: FILE: drivers/gpu/drm/i915/i915_vma.c:439: + vma->ops->bind_vma(vma->vm, work ? >stash : NULL, vma, cache_level, bind_flags); total: 0 errors, 1 warnings, 0 checks, 44 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Use DRIVER_NAME for tracing unattached requests
On 31/05/2021 08:53, Daniel Vetter wrote:
On Thu, May 20, 2021 at 4:28 PM Daniel Vetter wrote:
On Thu, May 20, 2021 at 08:35:14AM +0100, Matthew Auld wrote:
From: Chris Wilson
The first tracepoint for a request is trace_dma_fence_init called before
we have associated the request with a device. The tracepoint uses
fence->ops->get_driver_name() as a pretty name, and as we try to report
the device name this oopses as it is then NULL. Support the early
tracepoint by reporting the DRIVER_NAME instead of the actual device
name.
Note that rq->engine remains during the course of request recycling
(SLAB_TYPESAFE_BY_RCU). For the physical engines, the pointer remains
valid, however a virtual engine may be destroyed after the request is
retired. If we process a preempt-to-busy completed request along the
virtual engine, we should make sure we mark the request as no longer
belonging to the virtual engine to remove the dangling pointers from the
tracepoint.
Why can't we assign the request beforehand? The idea behind these
tracepoints is that they actually match up, if trace_dma_fence_init is
different, then we're breaking that.
Ok I looked a bit more and pondered this a bit, and the initial
tracepoint is called from dma_fence_init, where we haven't yet set up
rq->engine properly. So that part makes sense, but should have a
bigger comment that explains this a bit more and why we can't solve
this in a neater way. Probably should also drop the unlikely(), this
isn't a performance critical path, ever.
The other changes thgouh feel like they should be split out into a
separate path, since they solve a conceptually totally different
issue: SLAB_TYPESAFE_BY_RCU recycling.
Hmm, I thought it all stems from having to tread very carefully around
SLAB_TYPESAFE_BY_RCU? If this were "normal" code, we would just allocate
the rq, initialise it properly, including the rq->engine, and only then
do the dma_fence_init? Or am I missing something?
I'm happy to split it though. And I think that bit at least fixes the
user reported issue I think.
And I'm honestly not sure about
that one whether it's even correct, there's another patch floating
around that sprinkles rcu_read_lock around some of these accesssors,
and that would be a breakage of dma_fence interaces where outside of
i915 rcu isn't required for this stuff. So imo should be split out,
and come with a wider analysis of what's going on there and why and
how exactly i915 works.
In generally SLAB_TYPESAFE_BY_RCU is extremely dangerous and I'm
frankly not sure we have the perf data (outside of contrived
microbenchmarks) showing that it's needed and justifies all the costs
it's encurring.
Right, I can try to search the git history.
-Daniel
-Daniel
Fixes: 855e39e65cfc ("drm/i915: Initialise basic fence before acquiring seqno")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Chintan M Patel
Cc: Andi Shyti
Cc: # v5.7+
Signed-off-by: Matthew Auld
---
.../drm/i915/gt/intel_execlists_submission.c | 20 ++-
drivers/gpu/drm/i915/i915_request.c | 7 ++-
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index de124870af44..75604e927d34 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3249,6 +3249,18 @@ static struct list_head *virtual_queue(struct
virtual_engine *ve)
return >base.execlists.default_priolist.requests;
}
+static void
+virtual_submit_completed(struct virtual_engine *ve, struct i915_request *rq)
+{
+ GEM_BUG_ON(!__i915_request_is_complete(rq));
+ GEM_BUG_ON(rq->engine != >base);
+
+ __i915_request_submit(rq);
+
+ /* Remove the dangling pointer to the stale virtual engine */
+ WRITE_ONCE(rq->engine, ve->siblings[0]);
+}
+
static void rcu_virtual_context_destroy(struct work_struct *wrk)
{
struct virtual_engine *ve =
@@ -3265,8 +3277,7 @@ static void rcu_virtual_context_destroy(struct
work_struct *wrk)
old = fetch_and_zero(>request);
if (old) {
- GEM_BUG_ON(!__i915_request_is_complete(old));
- __i915_request_submit(old);
+ virtual_submit_completed(ve, old);
i915_request_put(old);
}
@@ -3538,13 +3549,12 @@ static void virtual_submit_request(struct i915_request
*rq)
/* By the time we resubmit a request, it may be completed */
if (__i915_request_is_complete(rq)) {
- __i915_request_submit(rq);
+ virtual_submit_completed(ve, rq);
goto unlock;
}
if (ve->request) { /* background completion from preempt-to-busy */
- GEM_BUG_ON(!__i915_request_is_complete(ve->request));
- __i915_request_submit(ve->request);
+ virtual_submit_completed(ve,
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Fix return value check in live_breadcrumbs_smoketest()
== Series Details ==
Series: drm/i915/selftests: Fix return value check in
live_breadcrumbs_smoketest()
URL : https://patchwork.freedesktop.org/series/90817/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20245
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/index.html
Known issues
Here are the changes found in Patchwork_20245 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][2] ([i915#3303]) -> [PASS][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
- fi-snb-2600:[INCOMPLETE][4] ([i915#2782]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][6] ([i915#1372]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
Warnings
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[INCOMPLETE][8] ([i915#2782] / [i915#2940] /
[i915#3462]) -> [DMESG-FAIL][9] ([i915#3462])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
- fi-icl-u2: [INCOMPLETE][10] ([i915#2782] / [i915#3462]) ->
[DMESG-FAIL][11] ([i915#3462])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-icl-u2/igt@i915_selftest@l...@execlists.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-icl-u2/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][12] ([i915#1436] / [i915#3363]) -> [FAIL][13]
([i915#1436] / [i915#2426] / [i915#3363])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-skl-6600u/igt@run...@aborted.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-skl-6600u/igt@run...@aborted.html
- fi-icl-u2: [FAIL][14] ([i915#2782] / [i915#3363]) -> [FAIL][15]
([i915#2426] / [i915#2782] / [i915#3363])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-icl-u2/igt@run...@aborted.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-icl-u2/igt@run...@aborted.html
- fi-kbl-7500u: [FAIL][16] ([i915#1436] / [i915#3363]) -> [FAIL][17]
([i915#1436] / [i915#2426] / [i915#3363])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7500u/igt@run...@aborted.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-kbl-7500u/igt@run...@aborted.html
- fi-skl-6700k2: [FAIL][18] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][19] ([i915#1436] / [i915#3363])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-skl-6700k2/igt@run...@aborted.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20245/fi-skl-6700k2/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
Participating hosts (47 -> 42)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Fix return value check in live_breadcrumbs_smoketest()
== Series Details == Series: drm/i915/selftests: Fix return value check in live_breadcrumbs_smoketest() URL : https://patchwork.freedesktop.org/series/90817/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9f93f64b2ec8 drm/i915/selftests: Fix return value check in live_breadcrumbs_smoketest() -:19: WARNING:BAD_SIGN_OFF: Unexpected content after email: 'intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; chengzhih...@huawei.com; yuku...@huawei.com', should be: 'intel-gfx@lists.freedesktop.org; (dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; chengzhih...@huawei.com; yuku...@huawei.com)' #19: Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; chengzhih...@huawei.com; yuku...@huawei.com -:20: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #20: Subject: [PATCH] drm/i915/selftests: Fix return value check in live_breadcrumbs_smoketest() total: 0 errors, 2 warnings, 0 checks, 10 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function
The v2 patch which addressed Jose's comments was floated to
https://patchwork.freedesktop.org/series/90819/
On Fri, 2021-05-21 at 14:52 -0700, Souza, Jose wrote:
> On Fri, 2021-05-21 at 11:58 +0100, Mun, Gwan-gyeong wrote:
> > On Tue, 2021-05-18 at 14:06 +0300, Ville Syrjälä wrote:
> > > On Tue, May 18, 2021 at 09:33:09AM +, Mun, Gwan-gyeong wrote:
> > > > Hi Ville,
> > > > initially, intel_psr_pause() called intel_psr_disable_locked()
> > > > instead
> > > > of intel_psr_exit().
> > > > In intel_psr_resume(), _intel_psr_enable_locked() was called
> > > > instead
> > > > of
> > > > intel_psr_activate().
> > > > Can you share what problem the initial code caused when calling
> > > > intel_psr_pause() / intel_psr_resume()?
> > >
> > > It was doing illegal stuff with crtc->state/etc. That was oopsing.
> > > The other problem was that IIRC it was going to do DPCD accesses
> > > while the cdclk code was already holding the aux mutexes. I moved
> > > it
> > > out from under the lock, but I think we might actually want it
> > > inside
> > > the lock since we'll need that to prevent PSR during all AUX
> > > transfers
> > > anyway. Putting it back inside the lock should also make it less
> > > racy
> > > I guess.
> > >
> > > >
> > > > In addition, intel_psr_exit() /intel_psr_activate() function
> > > > disable
> > > > /
> > > > enable only the PSR source.
> > > > So, if disable/enable for PSR Sink Device is not called together,
> > > > there
> > > > will be a problem that the PSR state machine of sink and source
> > > > is
> > > > different.
> > > > What do you think?
> > >
> > > If possible I wouldn't want it touch the sink at all. It should
> > > basically be no different to eg. enabling the vblank interrupt.
> > >
> >
> > Hi Ville and Stan,
> > Thanks, Ville, for explaining.
> >
> > intel_psr_pause() and intel_psr_resume() are an api added to use when
> > reactivating (disable and enable) the psr functionality without
> > intel_crtc_state and drm_connector_state, as described in the commit
> > log.
> > And in order to deactivate and activate psr normally, we must
> > deactivate the psr functionality of the sink as well, and at this
> > time,
> > sink psr deactivate using dpcd.
> >
> > And in the part explaining disabling psr in cdclk setting in bspec,
> > the
> > following procedure is explained for disabling psr.
> > 1. Temporarily disable PSR1, PSR2, and GTC.
> > 2. Wait for disabling status from those functions.
> > 3. Wait for any pending Aux transactions to complete, and do not
> > start
> > any new Aux transaction.
> > ...
>
> I don't think we need to disable, psr_exit() + wait until PSR is idle
> is enough, all other stuff can be left as is.
>
> >
> > So, in my opinion, when the cdclk setting is called from
> > intel_atomic_commit_tail() with functions such as
> > intel_set_cdclk_pre_plane_update() /
> > intel_set_cdclk_post_plane_update(),
> > if psr deactivation/activation is necessary, it seems that
> > intel_set_cdclk_pre_plane_update() /
> > intel_set_cdclk_post_plane_update() should be called with
> > intel_psr_enable() / intel_psr_disable() functions together. What do
> > you think?
> >
> > Br,
> > G.G.
> > > >
> > > > On Mon, 2021-05-17 at 09:58 -0700, Souza, Jose wrote:
> > > > > On Fri, 2021-05-14 at 20:10 -0700, Matt Roper wrote:
> > > > > > From: Gwan-gyeong Mun
> > > > > >
> > > > > > This introduces the following function that can enable and
> > > > > > disable
> > > > > > psr
> > > > > > without intel_crtc_state/drm_connector_state when intel_psr
> > > > > > is
> > > > > > already
> > > > > > enabled with current intel_crtc_state and drm_connector_state
> > > > > > information.
> > > > > >
> > > > > > - intel_psr_pause(): Pause current PSR. it deactivates
> > > > > > current
> > > > > > psr
> > > > > > state.
> > > > > > - intel_psr_resume(): Resume paused PSR without
> > > > > > intel_crtc_state
> > > > > > and
> > > > > > drm_connector_state. It activates
> > > > > > paused
> > > > > > psr
> > > > > > state.
> > > > > >
> > > > > > Cc: José Roberto de Souza
> > > > > > Cc: Stanislav Lisovskiy
> > > > > > Cc: Ville Syrjälä
> > > > > > Signed-off-by: Gwan-gyeong Mun
> > > > > > Signed-off-by: Matt Roper
> > > > > > ---
> > > > > > .../drm/i915/display/intel_display_types.h | 1 +
> > > > > > drivers/gpu/drm/i915/display/intel_psr.c | 93
> > > > > > -
> > > > > > --
> > > > > > drivers/gpu/drm/i915/display/intel_psr.h | 2 +
> > > > > > 3 files changed, 82 insertions(+), 14 deletions(-)
> > > > > >
> > > > > > diff --git
> > > > > > a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > index b8d1f702d808..ee7cbdd7db87 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > @@ -1482,6 +1482,7 @@ struct intel_psr {
> > > > > >
[Intel-gfx] ✗ Fi.CI.IGT: failure for Move LMEM (VRAM) management over to TTM (rev5)
== Series Details == Series: Move LMEM (VRAM) management over to TTM (rev5) URL : https://patchwork.freedesktop.org/series/90681/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10153_full -> Patchwork_20243_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20243_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20243_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20243_full: ### IGT changes ### Possible regressions * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: NOTRUN -> [SKIP][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-iclb1/igt@kms_plane_low...@pipe-a-tiling-y.html Warnings * igt@perf@polling-parameterized: - shard-skl: [FAIL][2] ([i915#1542]) -> [INCOMPLETE][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-skl6/igt@p...@polling-parameterized.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-skl4/igt@p...@polling-parameterized.html ### Piglit changes ### Possible regressions * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 8 128 4 (NEW): - pig-glk-j5005: NOTRUN -> [INCOMPLETE][4] +1 similar issue [4]: None New tests - New tests have been introduced between CI_DRM_10153_full and Patchwork_20243_full: ### New Piglit tests (2) ### * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 8 128 4: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 1 8 128 7: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_20243_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@engines-hostile@rcs0: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2410]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-glk9/igt@gem_ctx_persistence@engines-host...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-glk4/igt@gem_ctx_persistence@engines-host...@rcs0.html - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2410]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-tglb6/igt@gem_ctx_persistence@engines-host...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-tglb5/igt@gem_ctx_persistence@engines-host...@rcs0.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][10] ([i915#3354]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-snb6/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][11] ([i915#2846]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-apl1/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-glk: NOTRUN -> [FAIL][12] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-glk6/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-glk8/igt@gem_exec_fair@basic-pace-s...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-glk4/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2849]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10153/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_params@secure-non-master: - shard-iclb: NOTRUN -> [SKIP][17] ([fdo#112283]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-iclb1/igt@gem_exec_par...@secure-non-master.html * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][18] ([i915#2389]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20243/shard-iclb2/igt@gem_exec_reloc@basic-wide-act...@vcs1.html *
[Intel-gfx] [RFC v3 2/2] drm/i915/display: Use AUDIO_VERBS for crtc power domain mask
Use POWER_DOMAIN_AUDIO_VERBS power domain instead of POWER_DOMAIN_AUDIO in crtc power domain mask. It will save the power in use cases when DP/HDMI connectors configured with PIPE_A without any audio playback. Cc: Ville Syrjälä Cc: Kai Vehmanen Cc: Uma Shankar Cc: Imre Deak Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 3d8918674153..55c392114272 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3494,7 +3494,7 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, if (cpu_transcoder == TRANSCODER_EDP) return false; - if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) + if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_VERBS)) return false; return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0bb2e582c87f..c24465739af5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3829,7 +3829,7 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) } if (HAS_DDI(dev_priv) && crtc_state->has_audio) - mask |= BIT_ULL(POWER_DOMAIN_AUDIO); + mask |= BIT_ULL(POWER_DOMAIN_AUDIO_VERBS); if (crtc_state->shared_dpll) mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC v3 1/2] drm/i915/dg1: Adjust the AUDIO power domain
DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power well. Adjusting the power domain accordingly to POWER_DOMAIN_AUDIO_VERBS for audio detection and POWER_DOMAIN_AUDIO for audio playback. Cc: Ville Syrjälä Cc: Kai Vehmanen Cc: Uma Shankar Cc: Imre Deak Signed-off-by: Anshuman Gupta --- .../drm/i915/display/intel_display_power.c| 382 +- .../drm/i915/display/intel_display_power.h| 1 + 2 files changed, 382 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 2f7d1664c473..da5894138e8b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -106,6 +106,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) return "PORT_OTHER"; case POWER_DOMAIN_VGA: return "VGA"; + case POWER_DOMAIN_AUDIO_VERBS: + return "AUDIO_VERBS"; case POWER_DOMAIN_AUDIO: return "AUDIO"; case POWER_DOMAIN_AUX_A: @@ -2499,6 +2501,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_PORT_DSI) |\ BIT_ULL(POWER_DOMAIN_PORT_CRT) |\ BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ BIT_ULL(POWER_DOMAIN_AUDIO) | \ BIT_ULL(POWER_DOMAIN_AUX_B) | \ BIT_ULL(POWER_DOMAIN_AUX_C) | \ @@ -2549,6 +2552,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\ BIT_ULL(POWER_DOMAIN_PORT_DSI) |\ BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ BIT_ULL(POWER_DOMAIN_AUDIO) | \ BIT_ULL(POWER_DOMAIN_AUX_B) | \ BIT_ULL(POWER_DOMAIN_AUX_C) | \ @@ -2582,6 +2586,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\ BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */\ BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ BIT_ULL(POWER_DOMAIN_AUDIO) | \ BIT_ULL(POWER_DOMAIN_INIT)) @@ -2598,6 +2603,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\ BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */\ BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ BIT_ULL(POWER_DOMAIN_AUDIO) | \ BIT_ULL(POWER_DOMAIN_INIT)) @@ -2616,6 +2622,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_AUX_B) | \ BIT_ULL(POWER_DOMAIN_AUX_C) | \ BIT_ULL(POWER_DOMAIN_AUX_D) | \ + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ BIT_ULL(POWER_DOMAIN_AUDIO) | \ BIT_ULL(POWER_DOMAIN_VGA) | \ BIT_ULL(POWER_DOMAIN_INIT)) @@ -2651,6 +2658,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\ BIT_ULL(POWER_DOMAIN_AUX_B) | \ BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ BIT_ULL(POWER_DOMAIN_AUDIO) | \ BIT_ULL(POWER_DOMAIN_VGA) | \ BIT_ULL(POWER_DOMAIN_INIT)) @@ -2684,6 +2692,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\ BIT_ULL(POWER_DOMAIN_AUX_B) | \ BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ BIT_ULL(POWER_DOMAIN_AUDIO) | \ BIT_ULL(POWER_DOMAIN_VGA) | \ BIT_ULL(POWER_DOMAIN_INIT)) @@ -2739,6 +2748,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, BIT_ULL(POWER_DOMAIN_AUX_C) | \ BIT_ULL(POWER_DOMAIN_AUX_D) | \ BIT_ULL(POWER_DOMAIN_AUX_F) | \ + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ BIT_ULL(POWER_DOMAIN_AUDIO) | \ BIT_ULL(POWER_DOMAIN_VGA) | \ BIT_ULL(POWER_DOMAIN_INIT)) @@ -2821,6 +2831,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
[Intel-gfx] [RFC v3 0/2] lpsp with hdmi/dp outputs
v2 link: https://patchwork.freedesktop.org/series/77866/ Anshuman Gupta (2): drm/i915/dg1: Adjust the AUDIO power domain drm/i915/display: Use AUDIO_VERBS for crtc power domain mask drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../drm/i915/display/intel_display_power.c| 382 +- .../drm/i915/display/intel_display_power.h| 1 + 4 files changed, 384 insertions(+), 3 deletions(-) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 21/21] drm/i915/xelpd: Enable plane gamma
Enable plane gamma feature in check callbacks. Decide based on the user input. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 6ba670b6a5c9..5d527d12ec45 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -959,7 +959,9 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); u32 plane_color_ctl = 0; - plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; + /* FIXME needs hw.gamma_lut */ + if (!plane_state->uapi.gamma_lut) + plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; /* FIXME needs hw.degamma_lut */ if (plane_state->uapi.degamma_lut) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 20/21] drm/i915/xelpd: Program Plane Gamma Registers
Extract the LUT and program plane gamma registers.
Enabled multi segmented lut as well.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 89 ++
drivers/gpu/drm/i915/i915_reg.h| 9 ++-
2 files changed, 94 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 7f091dd0bb19..daf2148fb2df 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -27,6 +27,9 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_sprite.h"
+
+#include "skl_universal_plane.h"
+
#include
#define CTM_COEFF_SIGN (1ULL << 63)
@@ -2434,16 +2437,102 @@ static void d13_program_plane_degamma_lut(const struct
drm_plane_state *state,
}
}
+static void d13_program_plane_gamma_lut(const struct drm_plane_state *state,
+ struct drm_color_lut_ext *gamma_lut,
+ u32 offset)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ u32 i, lut_size;
+
+ if (icl_is_hdr_plane(dev_priv, plane)) {
+ intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe,
plane, 0),
+ offset | PLANE_PAL_PREC_AUTO_INCREMENT);
+ if (gamma_lut) {
+ lut_size = 32;
+ for (i = 0; i < lut_size; i++) {
+ u64 word =
drm_color_lut_extract_ext(gamma_lut[i].green, 24);
+ u32 lut_val = (word & 0xff);
+
+ intel_de_write(dev_priv,
PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ lut_val);
+ }
+
+ do {
+ /* Program the max register to clamp values >
1.0. */
+ intel_de_write(dev_priv,
PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ gamma_lut[i].green);
+ } while (i++ < 34);
+ } else {
+ lut_size = 32;
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+
+ intel_de_write(dev_priv,
PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
+ }
+
+ do {
+ intel_de_write(dev_priv,
PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ 1 << 24);
+ } while (i++ < 34);
+ }
+
+ intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe,
plane, 0), 0);
+ } else {
+ lut_size = 32;
+ /*
+* First 3 planes are HDR, so reduce by 3 to get to the right
+* SDR plane offset
+*/
+ plane = plane - 3;
+
+ intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_INDEX(pipe, plane,
0),
+ offset | PLANE_PAL_PREC_AUTO_INCREMENT);
+
+ if (gamma_lut) {
+ for (i = 0; i < lut_size; i++)
+ intel_de_write(dev_priv,
PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0),
+ gamma_lut[i].green & 0x);
+ /* Program the max register to clamp values > 1.0. */
+ while (i < 35)
+ intel_de_write(dev_priv,
PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0),
+ gamma_lut[i++].green & 0x3);
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 16) - 1)) / (lut_size - 1);
+
+ intel_de_write(dev_priv,
PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0), v);
+ }
+
+ do {
+ intel_de_write(dev_priv,
PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0),
+ (1 << 16));
+ } while (i++ < 34);
+ }
+
+ intel_de_write(dev_priv, PLANE_POST_CSC_GAMC_INDEX(pipe, plane,
0), 0);
+ }
+}
+
static void d13_plane_load_luts(const struct drm_plane_state *plane_state)
{
const struct drm_property_blob *degamma_lut_blob =
plane_state->degamma_lut;
+ const struct drm_property_blob *gamma_lut_blob =
+ plane_state->gamma_lut;
struct drm_color_lut_ext *degamma_lut = NULL;
+ struct
[Intel-gfx] [PATCH 19/21] drm/i915/xelpd: Add register definitions for Plane Gamma
Add macros to define Plane Gamma registers
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 73 +
1 file changed, 73 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a8e35357aea0..2ebc92104f64 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11398,6 +11398,79 @@ enum skl_power_gate {
_MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \
_PLANE_PRE_CSC_GAMC_DATA_2(pipe))
+/* Display13 Plane Gamma Reg */
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A0x70160
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B0x71160
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A0x70260
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B0x71260
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe)_PIPE(pipe,
_PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A, \
+
_PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe)_PIPE(pipe,
_PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A, \
+
_PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B)
+#define PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, i) \
+ _MMIO_PLANE_GAMC(plane, i,
_PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A 0x70164
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B 0x71164
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A 0x70264
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B 0x71264
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A, \
+
_PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A, \
+
_PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B)
+#define PLANE_POST_CSC_GAMC_SEG0_DATA_ENH(pipe, plane, i) \
+ _MMIO_PLANE_GAMC(plane, i,
_PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A 0x701d8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B 0x711d8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A 0x702d8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B 0x712d8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_INDEX_ENH_1_A, \
+
_PLANE_POST_CSC_GAMC_INDEX_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_INDEX_ENH_2_A, \
+
_PLANE_POST_CSC_GAMC_INDEX_ENH_2_B)
+#define PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, i) \
+ _MMIO_PLANE_GAMC(plane, i,
_PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_A 0x701dc
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_B 0x711dc
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_A 0x702dc
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_B 0x712dc
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_DATA_ENH_1_A, \
+
_PLANE_POST_CSC_GAMC_DATA_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_DATA_ENH_2_A, \
+
_PLANE_POST_CSC_GAMC_DATA_ENH_2_B)
+#define PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, i) \
+ _MMIO_PLANE_GAMC(plane, i,
_PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe), \
+ _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_INDEX_1_A 0x704d8
+#define _PLANE_POST_CSC_GAMC_INDEX_1_B 0x714d8
+#define _PLANE_POST_CSC_GAMC_INDEX_2_A 0x705d8
+#define _PLANE_POST_CSC_GAMC_INDEX_2_B 0x715d8
+#define _PLANE_POST_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_INDEX_1_A, \
+ _PLANE_POST_CSC_GAMC_INDEX_1_B)
+#define _PLANE_POST_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_INDEX_2_A, \
+ _PLANE_POST_CSC_GAMC_INDEX_2_B)
+#define PLANE_POST_CSC_GAMC_INDEX(pipe, plane, i) \
+ _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_1(pipe), \
+ _PLANE_POST_CSC_GAMC_INDEX_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_DATA_1_A 0x704dc
+#define _PLANE_POST_CSC_GAMC_DATA_1_B 0x714dc
+#define _PLANE_POST_CSC_GAMC_DATA_2_A 0x705dc
+#define _PLANE_POST_CSC_GAMC_DATA_2_B 0x715dc
+#define _PLANE_POST_CSC_GAMC_DATA_1(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_DATA_1_A, \
+
[Intel-gfx] [PATCH 18/21] drm/i915/xelpd: Define and Initialize Plane Gamma Lut range
Define the structure with XE_LPD gamma lut ranges. HDR and SDR planes
have different capabilities, implemented respective structure for
the HDR planes. Degamma and GAMMA has same Lut caps for SDR planes,
extended the same.
Initialize the mode range caps as well.
Signed-off-by: Uma Shankar
Signed-off-by: Bhanuprakash Modem
---
drivers/gpu/drm/i915/display/intel_color.c | 112 ++---
1 file changed, 99 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 8b4f653b213d..7f091dd0bb19 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2248,7 +2248,7 @@ static const struct drm_color_lut_range d13_degamma_hdr[]
= {
};
/* FIXME input bpc? */
-static const struct drm_color_lut_range d13_degamma_sdr[] = {
+static const struct drm_color_lut_range d13_gamma_degamma_sdr[] = {
/* segment 1 */
{
.flags = (DRM_MODE_LUT_GAMMA |
@@ -2298,6 +2298,63 @@ static const struct drm_color_lut_range
d13_degamma_sdr[] = {
},
};
+ /* FIXME input bpc? */
+static const struct drm_color_lut_range d13_gamma_hdr[] = {
+ /*
+* ToDo: Add Segment 1
+* There is an optional fine segment added with 9 lut values
+* Will be added later
+*/
+
+ /* segment 2 */
+ {
+ .flags = (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_REFLECT_NEGATIVE |
+ DRM_MODE_LUT_INTERPOLATE |
+ DRM_MODE_LUT_NON_DECREASING),
+ .count = 32,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = 0, .end = (1 << 24) - 1,
+ .min = 0, .max = (1 << 24) - 1,
+ },
+ /* segment 3 */
+ {
+ .flags = (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_REFLECT_NEGATIVE |
+ DRM_MODE_LUT_INTERPOLATE |
+ DRM_MODE_LUT_REUSE_LAST |
+ DRM_MODE_LUT_NON_DECREASING),
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 24) - 1, .end = 1 << 24,
+ .min = 0, .max = 1 << 24,
+ },
+ /* Segment 4 */
+ {
+ .flags = (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_REFLECT_NEGATIVE |
+ DRM_MODE_LUT_INTERPOLATE |
+ DRM_MODE_LUT_REUSE_LAST |
+ DRM_MODE_LUT_NON_DECREASING),
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = 1 << 24, .end = 3 << 24,
+ .min = 0, .max = (3 << 24),
+ },
+ /* Segment 5 */
+ {
+ .flags = (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_REFLECT_NEGATIVE |
+ DRM_MODE_LUT_INTERPOLATE |
+ DRM_MODE_LUT_REUSE_LAST |
+ DRM_MODE_LUT_NON_DECREASING),
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = 3 << 24, .end = 7 << 24,
+ .min = 0, .max = (7 << 24),
+ },
+};
+
static void d13_program_plane_degamma_lut(const struct drm_plane_state *state,
struct drm_color_lut_ext *degamma_lut,
u32 offset)
@@ -2407,26 +2464,55 @@ int intel_plane_color_init(struct drm_plane *plane)
ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "no
degamma",
NULL, 0,
LUT_TYPE_DEGAMMA);
- if (icl_is_hdr_plane(dev_priv, to_intel_plane(plane)->id))
+ if (ret)
+ return ret;
+
+ ret = drm_plane_color_add_gamma_degamma_mode_range(plane, "no
gamma",
+ NULL, 0,
+
LUT_TYPE_GAMMA);
+ if (ret)
+ return ret;
+
+ if (icl_is_hdr_plane(dev_priv, to_intel_plane(plane)->id)) {
ret =
drm_plane_color_add_gamma_degamma_mode_range(plane, "plane degamma",
d13_degamma_hdr,
sizeof(d13_degamma_hdr),
LUT_TYPE_DEGAMMA);
- else
- ret =
drm_plane_color_add_gamma_degamma_mode_range(plane,
-
"plane degamma",
-
[Intel-gfx] [PATCH 17/21] drm: Add Plane Gamma Lut property
Add Plane Gamma Lut as a blob property.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic_state_helper.c | 3 +++
drivers/gpu/drm/drm_atomic_uapi.c | 10 ++
drivers/gpu/drm/drm_color_mgmt.c | 18 ++
include/drm/drm_plane.h | 14 ++
4 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index fafb8af1c9cb..7ddf6e4b956b 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -316,6 +316,8 @@ void __drm_atomic_helper_plane_duplicate_state(struct
drm_plane *plane,
drm_property_blob_get(state->degamma_lut);
if (state->ctm)
drm_property_blob_get(state->ctm);
+ if (state->gamma_lut)
+ drm_property_blob_get(state->gamma_lut);
state->color_mgmt_changed = false;
}
@@ -366,6 +368,7 @@ void __drm_atomic_helper_plane_destroy_state(struct
drm_plane_state *state)
drm_property_blob_put(state->fb_damage_clips);
drm_property_blob_put(state->degamma_lut);
drm_property_blob_put(state->ctm);
+ drm_property_blob_put(state->gamma_lut);
}
EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state);
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 6e3958491d10..4f5b7f76208d 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -614,6 +614,13 @@ static int drm_atomic_plane_set_property(struct drm_plane
*plane,
return ret;
} else if (property == plane->gamma_mode_property) {
state->gamma_mode = val;
+ } else if (property == plane->gamma_lut_property) {
+ ret = drm_atomic_replace_property_blob_from_id(dev,
+ >gamma_lut,
+ val, -1, sizeof(struct
drm_color_lut_ext),
+ );
+ state->color_mgmt_changed |= replaced;
+ return ret;
} else if (property == config->prop_fb_damage_clips) {
ret = drm_atomic_replace_property_blob_from_id(dev,
>fb_damage_clips,
@@ -689,6 +696,9 @@ drm_atomic_plane_get_property(struct drm_plane *plane,
*val = (state->ctm) ? state->ctm->base.id : 0;
} else if (property == plane->gamma_mode_property) {
*val = state->gamma_mode;
+ } else if (property == plane->gamma_lut_property) {
+ *val = (state->gamma_lut) ?
+ state->gamma_lut->base.id : 0;
} else if (property == config->prop_fb_damage_clips) {
*val = (state->fb_damage_clips) ?
state->fb_damage_clips->base.id : 0;
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 02367e691cf3..b5b3ff7f654d 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -613,6 +613,11 @@ EXPORT_SYMBOL(drm_plane_create_color_properties);
* to query and get the plane gamma color caps and choose the
* appropriate gamma mode and create lut values accordingly
*
+ * gamma_lut_property:
+ * Blob property which allows a userspace to provide LUT values
+ * to apply gamma curve using the h/w plane degamma processing
+ * engine, thereby making the content as non-linear.
+ *
*/
int drm_plane_create_color_mgmt_properties(struct drm_device *dev,
struct drm_plane *plane,
@@ -648,6 +653,13 @@ int drm_plane_create_color_mgmt_properties(struct
drm_device *dev,
plane->gamma_mode_property = prop;
+ prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
+ "PLANE_GAMMA_LUT", 0);
+ if (!prop)
+ return -ENOMEM;
+
+ plane->gamma_lut_property = prop;
+
return 0;
}
EXPORT_SYMBOL(drm_plane_create_color_mgmt_properties);
@@ -685,6 +697,12 @@ void drm_plane_attach_gamma_properties(struct drm_plane
*plane)
drm_object_attach_property(>base,
plane->gamma_mode_property, 0);
+
+ if (!plane->gamma_lut_property)
+ return;
+
+ drm_object_attach_property(>base,
+ plane->gamma_lut_property, 0);
}
EXPORT_SYMBOL(drm_plane_attach_gamma_properties);
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index a7b7c8599702..8989bb1aa46c 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -267,6 +267,14 @@ struct drm_plane_state {
*/
u32 gamma_mode;
+ /* @gamma_lut:
+*
+* Lookup table for converting framebuffer pixel data after applying the
+* color conversion matrix @ctm. See drm_plane_enable_color_mgmt(). The
+* blob (if not NULL) is an array of
