[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Initialize the mbus_offset to fix static analysis issue
== Series Details == Series: drm/i915: Initialize the mbus_offset to fix static analysis issue URL : https://patchwork.freedesktop.org/series/90975/ State : success == Summary == CI Bug Log - changes from CI_DRM_10168_full -> Patchwork_20281_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20281_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-apl: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/shard-apl2/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: [PASS][2] -> [DMESG-WARN][3] ([i915#180]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-kbl1/igt@gem_ctx_isolation@preservation...@vcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/shard-kbl3/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-tglb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/shard-tglb6/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-kbl4/igt@gem_exec_fair@basic-none-s...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/shard-kbl7/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-glk7/igt@gem_exec_fair@basic-n...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/shard-glk8/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2849]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-apl: NOTRUN -> [FAIL][15] ([i915#2389]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/shard-apl2/igt@gem_exec_reloc@basic-wide-act...@bcs0.html * igt@gem_exec_whisper@basic-contexts-all: - shard-glk: [PASS][16] -> [DMESG-WARN][17] ([i915#118] / [i915#95]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-glk3/igt@gem_exec_whis...@basic-contexts-all.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/shard-glk8/igt@gem_exec_whis...@basic-contexts-all.html * igt@gem_huc_copy@huc-copy: - shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#2190]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/shard-kbl3/igt@gem_huc_c...@huc-copy.html * igt@gem_mmap_gtt@cpuset-medium-copy-odd: - shard-iclb: [PASS][19] -> [FAIL][20] ([i915#2428]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-iclb7/igt@gem_mmap_...@cpuset-medium-copy-odd.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/shard-iclb7/igt@gem_mmap_...@cpuset-medium-copy-odd.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][21] ([i915#2658]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/shard-apl6/igt@gem_pr...@exhaustion.html * igt@gem_userptr_blits@vma-merge: - shard-apl: NOTRUN -> [FAIL][22] ([i915#3318]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/shard-apl7/igt@gem_userptr_bl...@vma-merge.html * igt@gen9_exec_parse@allowed-all: - shard-skl: [PASS][23] -> [DMESG-WARN][24] ([i915#1436] / [i915#716]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-skl8/igt@gen9_exec_pa...@allowed-all.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/shar
Re: [Intel-gfx] [RFC PATCH 64/97] drm/i915/guc: Reset implementation for new GuC interface
On Wed, Jun 02, 2021 at 03:33:43PM +0100, Tvrtko Ursulin wrote:
>
> On 06/05/2021 20:14, Matthew Brost wrote:
> > Reset implementation for new GuC interface. This is the legacy reset
> > implementation which is called when the i915 owns the engine hang check.
> > Future patches will offload the engine hang check to GuC but we will
> > continue to maintain this legacy path as a fallback and this code path
> > is also required if the GuC dies.
> >
> > With the new GuC interface it is not possible to reset individual
> > engines - it is only possible to reset the GPU entirely. This patch
> > forces an entire chip reset if any engine hangs.
> >
> > Cc: John Harrison
> > Signed-off-by: Matthew Brost
> > ---
> > drivers/gpu/drm/i915/gt/intel_context.c | 3 +
> > drivers/gpu/drm/i915/gt/intel_context_types.h | 7 +
> > drivers/gpu/drm/i915/gt/intel_engine_types.h | 6 +
> > .../drm/i915/gt/intel_execlists_submission.c | 40 ++
> > drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 +-
> > drivers/gpu/drm/i915/gt/intel_reset.c | 18 +-
> > .../gpu/drm/i915/gt/intel_ring_submission.c | 22 +
> > drivers/gpu/drm/i915/gt/mock_engine.c | 31 +
> > drivers/gpu/drm/i915/gt/uc/intel_guc.c| 16 +-
> > drivers/gpu/drm/i915/gt/uc/intel_guc.h| 8 +-
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 580 ++
> > drivers/gpu/drm/i915/gt/uc/intel_uc.c | 34 +-
> > drivers/gpu/drm/i915/gt/uc/intel_uc.h | 3 +
> > drivers/gpu/drm/i915/i915_request.c | 41 +-
> > drivers/gpu/drm/i915/i915_request.h | 2 +
> > 15 files changed, 643 insertions(+), 174 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
> > b/drivers/gpu/drm/i915/gt/intel_context.c
> > index b24a1b7a3f88..2f01437056a8 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> > @@ -392,6 +392,9 @@ intel_context_init(struct intel_context *ce, struct
> > intel_engine_cs *engine)
> > spin_lock_init(&ce->guc_state.lock);
> > INIT_LIST_HEAD(&ce->guc_state.fences);
> > + spin_lock_init(&ce->guc_active.lock);
> > + INIT_LIST_HEAD(&ce->guc_active.requests);
> > +
> > ce->guc_id = GUC_INVALID_LRC_ID;
> > INIT_LIST_HEAD(&ce->guc_id_link);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > index 6945963a31ba..b63c8cf7823b 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > @@ -165,6 +165,13 @@ struct intel_context {
> > struct list_head fences;
> > } guc_state;
> > + struct {
> > + /** lock: protects everything in guc_active */
> > + spinlock_t lock;
> > + /** requests: active requests on this context */
> > + struct list_head requests;
> > + } guc_active;
>
> More accounting, yeah, this is more of that where GuC gives with one hand
> and takes away with the other. :(
>
Yep but we probably can drop this once we switch to the DRM scheduler.
The drm_gpu_scheduler has a list of jobs and if don't mind searching the
whole thing on a reset that will probably work too. I think the only
reason we have a per context list is because of feedback I received a
a while go saying resets are per context with GuC so keep a list on the
context and engine list didn't really fit either. I'll make a to circle
back to this when we hook into the DRM scheduler.
> > +
> > /* GuC scheduling state that does not require a lock. */
> > atomic_t guc_sched_state_no_lock;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > index f7b6eed586ce..b84562b2708b 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > @@ -432,6 +432,12 @@ struct intel_engine_cs {
> > */
> > void(*release)(struct intel_engine_cs *engine);
> > + /*
> > +* Add / remove request from engine active tracking
> > +*/
> > + void(*add_active_request)(struct i915_request *rq);
> > + void(*remove_active_request)(struct i915_request *rq);
> > +
> > struct intel_engine_execlists execlists;
> > /*
> > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > index 396b1356ea3e..54518b64bdbd 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > @@ -3117,6 +3117,42 @@ static void execlists_park(struct intel_engine_cs
> > *engine)
> > cancel_timer(&engine->execlists.preempt);
> > }
> > +static void add_to_engine(struct i915_request *rq)
> > +{
> > + lockdep_assert_held(&rq->engine->sched_engine->lock);
> > + list_move_tail(&rq->sched.link, &rq->engine->sched_
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Initialize the mbus_offset to fix Klockwork issue
== Series Details == Series: drm/i915: Initialize the mbus_offset to fix Klockwork issue URL : https://patchwork.freedesktop.org/series/90972/ State : success == Summary == CI Bug Log - changes from CI_DRM_10168_full -> Patchwork_20280_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20280_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@vecs0: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-kbl1/igt@gem_ctx_isolation@preservation...@vecs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/shard-kbl3/igt@gem_ctx_isolation@preservation...@vecs0.html * igt@gem_ctx_persistence@legacy-engines-persistence: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-persistence.html * igt@gem_exec_fair@basic-deadline: - shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2846]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-tglb5/igt@gem_exec_f...@basic-deadline.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/shard-tglb8/igt@gem_exec_f...@basic-deadline.html - shard-glk: [PASS][6] -> [FAIL][7] ([i915#2846]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-glk9/igt@gem_exec_f...@basic-deadline.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/shard-glk7/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-kbl4/igt@gem_exec_fair@basic-none-s...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/shard-kbl2/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-glk7/igt@gem_exec_fair@basic-n...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/shard-glk9/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][12] -> [FAIL][13] ([i915#2851]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-kbl3/igt@gem_exec_fair@basic-p...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/shard-kbl3/igt@gem_exec_fair@basic-p...@rcs0.html - shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-iclb7/igt@gem_exec_fair@basic-p...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/shard-iclb4/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][17] -> [FAIL][18] ([i915#2849]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-apl: NOTRUN -> [FAIL][19] ([i915#2389]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/shard-apl6/igt@gem_exec_reloc@basic-wide-act...@bcs0.html * igt@gem_huc_copy@huc-copy: - shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#2190]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/shard-kbl1/igt@gem_huc_c...@huc-copy.html * igt@gem_mmap_gtt@big-copy: - shard-glk: [PASS][21] -> [FAIL][22] ([i915#307]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-glk1/igt@gem_mmap_...@big-copy.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/shard-glk6/igt@gem_mmap_...@big-copy.html - shard-skl: [PASS][23] -> [FAIL][24] ([i915#307]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-skl5/igt@gem_mmap_...@big-copy.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/shard-skl7/igt@gem_mmap_...@big-copy.html * igt@gem_mmap_gtt@cpuset-big-copy-odd: - shard-iclb: [PASS][25] -> [FAIL][26] ([i915#2428]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-iclb2/igt@gem_mmap_...@cpuset-big-copy-odd.html [26]
Re: [Intel-gfx] linux-next: manual merge of the amdgpu tree with the drm-misc tree
Hi all,
On Thu, 3 Jun 2021 12:48:47 +1000 Stephen Rothwell
wrote:
>
> Today's linux-next merge of the amdgpu tree got conflicts in:
>
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>
> between commit:
>
> d3116756a710 ("drm/ttm: rename bo->mem and make it a pointer")
>
> from the drm-misc tree and commits:
>
> b453e42a6e8b ("drm/amdgpu: Add new placement for preemptible SG BOs")
> 2a675640bc2d ("drm/amdgpu: move shadow bo validation to VM code")
> 59276f056fb7 ("drm/amdgpu: switch to amdgpu_bo_vm for vm code")
> 19a1d9350be6 ("drm/amdgpu: flush gart changes after all BO recovery")
>
> from the amdgpu tree.
>
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging. You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.
>
> --
> Cheers,
> Stephen Rothwell
>
> diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 663aa7d2e2ea,86259435803e..
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@@ -459,10 -479,11 +461,11 @@@ static int amdgpu_bo_move(struct ttm_bu
> {
> struct amdgpu_device *adev;
> struct amdgpu_bo *abo;
> -struct ttm_resource *old_mem = &bo->mem;
> +struct ttm_resource *old_mem = bo->resource;
> int r;
>
> - if (new_mem->mem_type == TTM_PL_TT) {
> + if (new_mem->mem_type == TTM_PL_TT ||
> + new_mem->mem_type == AMDGPU_PL_PREEMPT) {
> r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
> if (r)
> return r;
> @@@ -989,8 -1012,9 +995,9 @@@ int amdgpu_ttm_alloc_gart(struct ttm_bu
> return r;
> }
>
> + amdgpu_gart_invalidate_tlb(adev);
> -ttm_resource_free(bo, &bo->mem);
> -bo->mem = tmp;
> +ttm_resource_free(bo, bo->resource);
> +ttm_bo_assign_mem(bo, &tmp);
> }
>
> return 0;
> @@@ -1348,7 -1373,16 +1356,16 @@@ static bool amdgpu_ttm_bo_eviction_valu
> }
> }
>
> -switch (bo->mem.mem_type) {
> +switch (bo->resource->mem_type) {
> + case AMDGPU_PL_PREEMPT:
> + /* Preemptible BOs don't own system resources managed by the
> + * driver (pages, VRAM, GART space). They point to resources
> + * owned by someone else (e.g. pageable memory in user mode
> + * or a DMABuf). They are used in a preemptible context so we
> + * can guarantee no deadlocks and good QoS in case of MMU
> + * notifiers or DMABuf move notifiers from the resource owner.
> + */
> + return false;
> case TTM_PL_TT:
> if (amdgpu_bo_is_amdgpu_bo(bo) &&
> amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
> @@@ -1767,8 -1809,13 +1791,9 @@@ void amdgpu_ttm_fini(struct amdgpu_devi
> amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
> amdgpu_ttm_fw_reserve_vram_fini(adev);
>
> -if (adev->mman.aper_base_kaddr)
> -iounmap(adev->mman.aper_base_kaddr);
> -adev->mman.aper_base_kaddr = NULL;
> -
> amdgpu_vram_mgr_fini(adev);
> amdgpu_gtt_mgr_fini(adev);
> + amdgpu_preempt_mgr_fini(adev);
> ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
> ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
> ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
> @@@ -1919,7 -2010,12 +1944,12 @@@ int amdgpu_fill_buffer(struct amdgpu_b
> return -EINVAL;
> }
>
> -if (bo->tbo.mem.mem_type == AMDGPU_PL_PREEMPT) {
> ++if (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT) {
> + DRM_ERROR("Trying to clear preemptible memory.\n");
> + return -EINVAL;
> + }
> +
> -if (bo->tbo.mem.mem_type == TTM_PL_TT) {
> +if (bo->tbo.resource->mem_type == TTM_PL_TT) {
> r = amdgpu_ttm_alloc_gart(&bo->tbo);
> if (r)
> return r;
> diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index bcfd4a8d0288,1923f035713a..
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@@ -657,11 -657,10 +658,11 @@@ void amdgpu_vm_move_to_lru_tail(struct
> if (!bo->parent)
> continue;
>
> -ttm_bo_move_to_lru_tail(&bo->tbo, &bo->tbo.mem,
> +ttm_bo_move_to_lru_tail(&bo->tbo, bo->tbo.resource,
> &vm->lru_bulk_move);
> - if (bo->shadow)
> - ttm_bo_move_to_lru_tail(&bo->shadow->tbo,
> + if (shadow)
> -ttm_bo_move_to_lr
Re: [Intel-gfx] [PATCH 08/20] drm/i915: Promote ptrdiff() to i915_utils.h
On Thu, Jun 03, 2021 at 11:35:28PM +0200, Daniel Vetter wrote:
> On Wed, Jun 02, 2021 at 10:16:18PM -0700, Matthew Brost wrote:
> > From: Michal Wajdeczko
> >
> > Generic helpers should be placed in i915_utils.h.
>
> Random rant, but we're _way_ too happy to just stuff random things into
> i915_utils.h without trying to properly upstream it.
>
> For thinks like this the general dumping ground would be kernel.h, there's
> a few pointer helpers there already. Follow up patch maybe nice.
> -Daniel
>
Sure. I've added this to a list of follow ups so this comment doesn't
get lost.
Matt
> >
> > Signed-off-by: Michal Wajdeczko
> > Signed-off-by: Matthew Brost
> > Reviewed-by: Matthew Brost
> > ---
> > drivers/gpu/drm/i915/i915_utils.h | 5 +
> > drivers/gpu/drm/i915/i915_vma.h | 5 -
> > 2 files changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_utils.h
> > b/drivers/gpu/drm/i915/i915_utils.h
> > index f02f52ab5070..5259edacde38 100644
> > --- a/drivers/gpu/drm/i915/i915_utils.h
> > +++ b/drivers/gpu/drm/i915/i915_utils.h
> > @@ -201,6 +201,11 @@ __check_struct_size(size_t base, size_t arr, size_t
> > count, size_t *size)
> > __T;\
> > })
> >
> > +static __always_inline ptrdiff_t ptrdiff(const void *a, const void *b)
> > +{
> > + return a - b;
> > +}
> > +
> > /*
> > * container_of_user: Extract the superclass from a pointer to a member.
> > *
> > diff --git a/drivers/gpu/drm/i915/i915_vma.h
> > b/drivers/gpu/drm/i915/i915_vma.h
> > index dc6926d89626..eca452a9851f 100644
> > --- a/drivers/gpu/drm/i915/i915_vma.h
> > +++ b/drivers/gpu/drm/i915/i915_vma.h
> > @@ -151,11 +151,6 @@ static inline void i915_vma_put(struct i915_vma *vma)
> > i915_gem_object_put(vma->obj);
> > }
> >
> > -static __always_inline ptrdiff_t ptrdiff(const void *a, const void *b)
> > -{
> > - return a - b;
> > -}
> > -
> > static inline long
> > i915_vma_compare(struct i915_vma *vma,
> > struct i915_address_space *vm,
> > --
> > 2.28.0
> >
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce i915_sched_engine object (rev2)
== Series Details == Series: Introduce i915_sched_engine object (rev2) URL : https://patchwork.freedesktop.org/series/90630/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10168_full -> Patchwork_20279_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20279_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20279_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20279_full: ### IGT changes ### Possible regressions * igt@kms_draw_crc@draw-method-xrgb-blt-ytiled: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-skl6/igt@kms_draw_...@draw-method-xrgb-blt-ytiled.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/shard-skl3/igt@kms_draw_...@draw-method-xrgb-blt-ytiled.html Known issues Here are the changes found in Patchwork_20279_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-clear: - shard-skl: [PASS][3] -> [FAIL][4] ([i915#3160]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-skl6/igt@gem_cre...@create-clear.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/shard-skl3/igt@gem_cre...@create-clear.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-kbl1/igt@gem_ctx_isolation@preservation...@vcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/shard-kbl1/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_ctx_shared@q-in-order: - shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271]) +315 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/shard-snb6/igt@gem_ctx_sha...@q-in-order.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2846]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-glk9/igt@gem_exec_f...@basic-deadline.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/shard-glk1/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-glk7/igt@gem_exec_fair@basic-n...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/shard-glk1/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][15] -> [FAIL][16] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-kbl3/igt@gem_exec_fair@basic-p...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/shard-kbl1/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][17] -> [FAIL][18] ([i915#2849]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-apl: NOTRUN -> [FAIL][19] ([i915#2389]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/shard-apl7/igt@gem_exec_reloc@basic-wide-act...@bcs0.html * igt@gem_mmap_gtt@cpuset-big-copy-odd: - shard-iclb: [PASS][20] -> [FAIL][21] ([i915#307]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/shard-iclb2/igt@gem_mmap_...@cpuset-big-copy-odd.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/shard-iclb1/igt@gem_mmap_...@cpuset-big-copy-odd.html * igt@gem_mmap_gtt@cpuset-medium-copy-odd: - shard-iclb: [PASS][22] -> [FAIL][23] ([i915#2428]) [22]: ht
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Initialize the mbus_offset to fix static analysis issue
== Series Details ==
Series: drm/i915: Initialize the mbus_offset to fix static analysis issue
URL : https://patchwork.freedesktop.org/series/90975/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10168 -> Patchwork_20281
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/index.html
Known issues
Here are the changes found in Patchwork_20281 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- fi-glk-dsi: [DMESG-FAIL][1] ([i915#2291] / [i915#541]) ->
[PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-glk-dsi/igt@i915_selftest@live@gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/fi-glk-dsi/igt@i915_selftest@live@gt_heartbeat.html
Warnings
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][3] ([i915#1436] / [i915#3363]) -> [FAIL][4]
([i915#1436] / [i915#2426] / [i915#3363])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-skl-6600u/igt@run...@aborted.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/fi-skl-6600u/igt@run...@aborted.html
- fi-glk-dsi: [FAIL][5] ([i915#2426] / [i915#3363] /
[k.org#202321]) -> [FAIL][6] ([i915#3363] / [k.org#202321])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-glk-dsi/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-soraka: [FAIL][7] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][8] ([i915#1436] / [i915#3363])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-kbl-soraka/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/fi-kbl-soraka/igt@run...@aborted.html
- fi-cml-s: [FAIL][9] ([i915#2082] / [i915#2426] / [i915#3363] /
[i915#3462]) -> [FAIL][10] ([i915#3363] / [i915#3462])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-cml-s/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/fi-cml-s/igt@run...@aborted.html
- fi-cfl-guc: [FAIL][11] ([i915#3363]) -> [FAIL][12] ([i915#2426] /
[i915#3363])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-cfl-guc/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/fi-cfl-guc/igt@run...@aborted.html
- fi-kbl-7567u: [FAIL][13] ([i915#1436] / [i915#3363]) -> [FAIL][14]
([i915#1436] / [i915#2426] / [i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-kbl-7567u/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/fi-kbl-7567u/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (45 -> 40)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-skl-guc fi-bsw-cyan fi-bdw-samus
Build changes
-
* Linux: CI_DRM_10168 -> Patchwork_20281
CI-20190529: 20190529
CI_DRM_10168: ad6cb7b043355cf535e0027ff90c4a6aacb790d1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6098: 1fbc1e7d602f96a7f4e2b95057eef994656b8e74 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20281: c446f63666afe4de5514dde3acbb41d9cb96e974 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c446f63666af drm/i915: Initialize the mbus_offset to fix static analysis issue
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20281/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Initialize the mbus_offset to fix Klockwork issue
== Series Details ==
Series: drm/i915: Initialize the mbus_offset to fix Klockwork issue
URL : https://patchwork.freedesktop.org/series/90972/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10168 -> Patchwork_20280
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/index.html
Known issues
Here are the changes found in Patchwork_20280 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- fi-glk-dsi: [DMESG-FAIL][1] ([i915#2291] / [i915#541]) ->
[PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-glk-dsi/igt@i915_selftest@live@gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/fi-glk-dsi/igt@i915_selftest@live@gt_heartbeat.html
Warnings
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][3] ([i915#2782] / [i915#2940] /
[i915#3462]) -> [DMESG-FAIL][4] ([i915#3462])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@gt_pm:
- fi-tgl-y: [DMESG-FAIL][5] ([i915#1759]) -> [INCOMPLETE][6]
([i915#3436])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-tgl-y/igt@i915_selftest@live@gt_pm.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/fi-tgl-y/igt@i915_selftest@live@gt_pm.html
* igt@runner@aborted:
- fi-glk-dsi: [FAIL][7] ([i915#2426] / [i915#3363] /
[k.org#202321]) -> [FAIL][8] ([i915#3363] / [k.org#202321])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-glk-dsi/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/fi-glk-dsi/igt@run...@aborted.html
- fi-bdw-5557u: [FAIL][9] ([i915#3462]) -> [FAIL][10] ([i915#1602] /
[i915#2029])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-bdw-5557u/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/fi-bdw-5557u/igt@run...@aborted.html
- fi-cml-s: [FAIL][11] ([i915#2082] / [i915#2426] / [i915#3363] /
[i915#3462]) -> [FAIL][12] ([i915#3363] / [i915#3462])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-cml-s/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/fi-cml-s/igt@run...@aborted.html
- fi-skl-guc: [FAIL][13] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][14] ([i915#1436] / [i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-skl-guc/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20280/fi-skl-guc/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
[i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3436]: https://gitlab.freedesktop.org/drm/intel/issues/3436
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (45 -> 40)
--
Missing(5): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-bsw-cyan fi-bdw-samus
Build changes
-
* Linux: CI_DRM_10168 -> Patchwork_20280
CI-20190529: 20190529
CI_DRM_10168: ad6cb7b043355cf535e0027ff90c4a6aacb790d1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6098: 1fbc1e7d602f96a7f4e2b95057eef994656b8e74 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20280: 5328811602d5d7918ec7e38f88d36bec8c10cc9f @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5328811602d5 drm/i915: Initialize the m
[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce i915_sched_engine object (rev2)
== Series Details ==
Series: Introduce i915_sched_engine object (rev2)
URL : https://patchwork.freedesktop.org/series/90630/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10168 -> Patchwork_20279
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/index.html
Known issues
Here are the changes found in Patchwork_20279 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- fi-glk-dsi: [DMESG-FAIL][1] ([i915#2291] / [i915#541]) ->
[PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-glk-dsi/igt@i915_selftest@live@gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/fi-glk-dsi/igt@i915_selftest@live@gt_heartbeat.html
Warnings
* igt@runner@aborted:
- fi-bdw-5557u: [FAIL][3] ([i915#3462]) -> [FAIL][4] ([i915#2426] /
[i915#3462])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-bdw-5557u/igt@run...@aborted.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/fi-bdw-5557u/igt@run...@aborted.html
- fi-cml-u2: [FAIL][5] ([i915#3363] / [i915#3462]) -> [FAIL][6]
([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-cml-u2/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/fi-cml-u2/igt@run...@aborted.html
- fi-bxt-dsi: [FAIL][7] ([i915#3363]) -> [FAIL][8] ([i915#2426] /
[i915#3363])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-bxt-dsi/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/fi-bxt-dsi/igt@run...@aborted.html
- fi-cml-s: [FAIL][9] ([i915#2082] / [i915#2426] / [i915#3363] /
[i915#3462]) -> [FAIL][10] ([i915#3363] / [i915#3462])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-cml-s/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/fi-cml-s/igt@run...@aborted.html
- fi-cfl-guc: [FAIL][11] ([i915#3363]) -> [FAIL][12] ([i915#2426] /
[i915#3363])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-cfl-guc/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/fi-cfl-guc/igt@run...@aborted.html
- fi-kbl-7567u: [FAIL][13] ([i915#1436] / [i915#3363]) -> [FAIL][14]
([i915#1436] / [i915#2426] / [i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-kbl-7567u/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/fi-kbl-7567u/igt@run...@aborted.html
- fi-skl-guc: [FAIL][15] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][16] ([i915#1436] / [i915#3363])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10168/fi-skl-guc/igt@run...@aborted.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20279/fi-skl-guc/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (45 -> 41)
--
Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_10168 -> Patchwork_20279
CI-20190529: 20190529
CI_DRM_10168: ad6cb7b043355cf535e0027ff90c4a6aacb790d1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6098: 1fbc1e7d602f96a7f4e2b95057eef994656b8e74 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20279: 378f81235475bf26dcbe8c9daaafd01aea52fb13 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
378f81235475 drm/i915/doc: Add kernel doc for i915_sched_engine
ec126054a0f5 drm/i915: Move submission tasklet to i915_sched_engine
b0932841cafb drm/i915: Update i915_scheduler to operate on i915_sched_engine
6e59cded3265 drm/i915: Add kick_backend function to i915_sched_engine
f6110f5321ac drm/i915: Move engine->schedule to i915_sched_engine
e7485728abe3 drm/i915: Move active tracking to i915_sched_engine
148a2142a7c3 drm/i915: Add i915_sched_engine_reset_on_empty function
ce8653e69398 dr
[Intel-gfx] ✗ Fi.CI.DOCS: warning for Introduce i915_sched_engine object (rev2)
== Series Details == Series: Introduce i915_sched_engine object (rev2) URL : https://patchwork.freedesktop.org/series/90630/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/i915_scheduler_types.h:105: warning: cannot understand function prototype: 'struct i915_sched_engine ' ./drivers/gpu/drm/i915/i915_scheduler_types.h:1: warning: 'i915_sched_engine' not found ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce i915_sched_engine object (rev2)
== Series Details == Series: Introduce i915_sched_engine object (rev2) URL : https://patchwork.freedesktop.org/series/90630/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8225af1a908b drm/i915: Move priolist to new i915_sched_engine object -:17: WARNING:REPEATED_WORD: Possible repeated word: 'the' #17: This patch starts the aforementioned transition by moving the the total: 0 errors, 1 warnings, 0 checks, 682 lines checked ce8653e69398 drm/i915: Add i915_sched_engine_is_empty function 148a2142a7c3 drm/i915: Add i915_sched_engine_reset_on_empty function e7485728abe3 drm/i915: Move active tracking to i915_sched_engine f6110f5321ac drm/i915: Move engine->schedule to i915_sched_engine 6e59cded3265 drm/i915: Add kick_backend function to i915_sched_engine b0932841cafb drm/i915: Update i915_scheduler to operate on i915_sched_engine ec126054a0f5 drm/i915: Move submission tasklet to i915_sched_engine 378f81235475 drm/i915/doc: Add kernel doc for i915_sched_engine -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 76 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v3 PATCH 1/2] drm/i915/guc: Replace CTB array with explicit members
From: Michal Wajdeczko
Upcoming GuC firmware will always require just two CTBs and we
also plan to configure them with different sizes, so definining
them as array is no longer suitable.
v2: Use %p for ptrdiff print
v3: Use %tx for ptrdiff print
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
Reported-by: kernel test robot
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 46 ---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 7 +++-
2 files changed, 30 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 34c582105860..ec795d7c3a7d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -168,10 +168,10 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
struct intel_guc *guc = ct_to_guc(ct);
struct guc_ct_buffer_desc *desc;
u32 blob_size;
+ u32 cmds_size;
void *blob;
u32 *cmds;
int err;
- int i;
GEM_BUG_ON(ct->vma);
@@ -207,15 +207,23 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma),
blob_size);
- /* store pointers to desc and cmds */
- for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) {
- GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
+ /* store pointers to desc and cmds for send ctb */
+ desc = blob;
+ cmds = blob + PAGE_SIZE / 2;
+ cmds_size = PAGE_SIZE / 4;
+ CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u\n", "send",
+ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);
- desc = blob + PAGE_SIZE / 4 * i;
- cmds = blob + PAGE_SIZE / 4 * i + PAGE_SIZE / 2;
+ guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size);
- guc_ct_buffer_init(&ct->ctbs[i], desc, cmds, PAGE_SIZE / 4);
- }
+ /* store pointers to desc and cmds for recv ctb */
+ desc = blob + PAGE_SIZE / 4;
+ cmds = blob + PAGE_SIZE / 4 + PAGE_SIZE / 2;
+ cmds_size = PAGE_SIZE / 4;
+ CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u\n", "recv",
+ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);
+
+ guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size);
return 0;
}
@@ -246,7 +254,6 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
u32 base, cmds;
void *blob;
int err;
- int i;
GEM_BUG_ON(ct->enabled);
@@ -257,28 +264,25 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
/* blob should start with send descriptor */
blob = __px_vaddr(ct->vma->obj);
- GEM_BUG_ON(blob != ct->ctbs[CTB_SEND].desc);
+ GEM_BUG_ON(blob != ct->ctbs.send.desc);
/* (re)initialize descriptors */
- for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) {
- GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
+ cmds = base + ptrdiff(ct->ctbs.send.cmds, blob);
+ guc_ct_buffer_reset(&ct->ctbs.send, cmds);
- cmds = base + ptrdiff(ct->ctbs[i].cmds, blob);
- CT_DEBUG(ct, "%d: cmds addr=%#x\n", i, cmds);
-
- guc_ct_buffer_reset(&ct->ctbs[i], cmds);
- }
+ cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob);
+ guc_ct_buffer_reset(&ct->ctbs.recv, cmds);
/*
* Register both CT buffers starting with RECV buffer.
* Descriptors are in first half of the blob.
*/
- err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs[CTB_RECV].desc,
blob),
+ err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs.recv.desc, blob),
INTEL_GUC_CT_BUFFER_TYPE_RECV);
if (unlikely(err))
goto err_out;
- err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs[CTB_SEND].desc,
blob),
+ err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs.send.desc, blob),
INTEL_GUC_CT_BUFFER_TYPE_SEND);
if (unlikely(err))
goto err_deregister;
@@ -341,7 +345,7 @@ static int ct_write(struct intel_guc_ct *ct,
u32 len /* in dwords */,
u32 fence)
{
- struct intel_guc_ct_buffer *ctb = &ct->ctbs[CTB_SEND];
+ struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
struct guc_ct_buffer_desc *desc = ctb->desc;
u32 head = desc->head;
u32 tail = desc->tail;
@@ -557,7 +561,7 @@ static inline bool ct_header_is_response(u32 header)
static int ct_read(struct intel_guc_ct *ct, u32 *data)
{
- struct intel_guc_ct_buffer *ctb = &ct->ctbs[CTB_RECV];
+ struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv;
struct guc_ct_buffer_desc *desc = ctb->desc;
u32 head = desc->head;
u32 tail = desc->tail;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
inde
[Intel-gfx] [v3 PATCH 2/2] drm/i915/guc: Update sizes of CTB buffers
From: Michal Wajdeczko
Future GuC will require CTB buffers sizes to be multiple of 4K.
Make these changes now as this shouldn't impact us too much.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 60 ---
1 file changed, 32 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index ec795d7c3a7d..8d1173032431 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -38,6 +38,32 @@ static inline struct drm_device *ct_to_drm(struct
intel_guc_ct *ct)
#define CT_PROBE_ERROR(_ct, _fmt, ...) \
i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
+/**
+ * DOC: CTB Blob
+ *
+ * We allocate single blob to hold both CTB descriptors and buffers:
+ *
+ * ++---+--+
+ * | offset | contents | size |
+ * ++===+==+
+ * | 0x | H2G `CTB Descriptor`_ (send) | |
+ * ++---+ 4K |
+ * | 0x0800 | G2H `CTB Descriptor`_ (recv) | |
+ * ++---+--+
+ * | 0x1000 | H2G `CT Buffer`_ (send) | n*4K |
+ * || | |
+ * ++---+--+
+ * | 0x1000 | G2H `CT Buffer`_ (recv) | m*4K |
+ * | + n*4K | | |
+ * ++---+--+
+ *
+ * Size of each `CT Buffer`_ must be multiple of 4K.
+ * As we don't expect too many messages, for now use minimum sizes.
+ */
+#define CTB_DESC_SIZE ALIGN(sizeof(struct guc_ct_buffer_desc), SZ_2K)
+#define CTB_H2G_BUFFER_SIZE(SZ_4K)
+#define CTB_G2H_BUFFER_SIZE(SZ_4K)
+
struct ct_request {
struct list_head link;
u32 fence;
@@ -175,29 +201,7 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
GEM_BUG_ON(ct->vma);
- /* We allocate 1 page to hold both descriptors and both buffers.
-* ___.
-* |desc (SEND)| :
-* |___| PAGE/4
-* :___:
-* |desc (RECV)| :
-* |___| PAGE/4
-* :___:
-* |cmds (SEND)|
-* | PAGE/4
-* |___|
-* |cmds (RECV)|
-* | PAGE/4
-* |___|
-*
-* Each message can use a maximum of 32 dwords and we don't expect to
-* have more than 1 in flight at any time, so we have enough space.
-* Some logic further ahead will rely on the fact that there is only 1
-* page and that it is always mapped, so if the size is changed the
-* other code will need updating as well.
-*/
-
- blob_size = PAGE_SIZE;
+ blob_size = 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE +
CTB_G2H_BUFFER_SIZE;
err = intel_guc_allocate_and_map_vma(guc, blob_size, &ct->vma, &blob);
if (unlikely(err)) {
CT_PROBE_ERROR(ct, "Failed to allocate %u for CTB data (%pe)\n",
@@ -209,17 +213,17 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
/* store pointers to desc and cmds for send ctb */
desc = blob;
- cmds = blob + PAGE_SIZE / 2;
- cmds_size = PAGE_SIZE / 4;
+ cmds = blob + 2 * CTB_DESC_SIZE;
+ cmds_size = CTB_H2G_BUFFER_SIZE;
CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u\n", "send",
ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);
guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size);
/* store pointers to desc and cmds for recv ctb */
- desc = blob + PAGE_SIZE / 4;
- cmds = blob + PAGE_SIZE / 4 + PAGE_SIZE / 2;
- cmds_size = PAGE_SIZE / 4;
+ desc = blob + CTB_DESC_SIZE;
+ cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
+ cmds_size = CTB_G2H_BUFFER_SIZE;
CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u\n", "recv",
ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Initialize the mbus_offset to fix Klockwork issue
On Thu, Jun 03, 2021 at 02:53:38PM -0700, Manasi Navare wrote:
> Static analysis identified an issue in skl_crtc_allocate_ddb where
> mbus_offset may be used uninitialized.
> This patch fixes it.
>
> Fixes: 835c176cb1c4 ("drm/i915: Introduce MBUS relative dbuf offsets")
> Cc: Ville Syrjälä
> Signed-off-by: Manasi Navare
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 00f3dead20ad..a385b8b7414f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4163,7 +4163,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> struct intel_crtc_state *crtc_state;
> struct skl_ddb_entry ddb_slices;
> enum pipe pipe = crtc->pipe;
> - unsigned int mbus_offset;
> + unsigned int mbus_offset = 0;
> u32 ddb_range_size;
> u32 dbuf_slice_mask;
> u32 start, end;
> --
> 2.19.1
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/guc: Replace CTB array with explicit members
From: Michal Wajdeczko
Upcoming GuC firmware will always require just two CTBs and we
also plan to configure them with different sizes, so definining
them as array is no longer suitable.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
Reported-by: kernel test robot
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 46 ---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 7 +++-
2 files changed, 30 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 34c582105860..882ae1ed41b0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -168,10 +168,10 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
struct intel_guc *guc = ct_to_guc(ct);
struct guc_ct_buffer_desc *desc;
u32 blob_size;
+ u32 cmds_size;
void *blob;
u32 *cmds;
int err;
- int i;
GEM_BUG_ON(ct->vma);
@@ -207,15 +207,23 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma),
blob_size);
- /* store pointers to desc and cmds */
- for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) {
- GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
+ /* store pointers to desc and cmds for send ctb */
+ desc = blob;
+ cmds = blob + PAGE_SIZE / 2;
+ cmds_size = PAGE_SIZE / 4;
+ CT_DEBUG(ct, "%s desc %#p cmds %#p size %u\n", "send",
+ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);
- desc = blob + PAGE_SIZE / 4 * i;
- cmds = blob + PAGE_SIZE / 4 * i + PAGE_SIZE / 2;
+ guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size);
- guc_ct_buffer_init(&ct->ctbs[i], desc, cmds, PAGE_SIZE / 4);
- }
+ /* store pointers to desc and cmds for recv ctb */
+ desc = blob + PAGE_SIZE / 4;
+ cmds = blob + PAGE_SIZE / 4 + PAGE_SIZE / 2;
+ cmds_size = PAGE_SIZE / 4;
+ CT_DEBUG(ct, "%s desc %#p cmds %#p size %u\n", "recv",
+ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);
+
+ guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size);
return 0;
}
@@ -246,7 +254,6 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
u32 base, cmds;
void *blob;
int err;
- int i;
GEM_BUG_ON(ct->enabled);
@@ -257,28 +264,25 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
/* blob should start with send descriptor */
blob = __px_vaddr(ct->vma->obj);
- GEM_BUG_ON(blob != ct->ctbs[CTB_SEND].desc);
+ GEM_BUG_ON(blob != ct->ctbs.send.desc);
/* (re)initialize descriptors */
- for (i = 0; i < ARRAY_SIZE(ct->ctbs); i++) {
- GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
+ cmds = base + ptrdiff(ct->ctbs.send.cmds, blob);
+ guc_ct_buffer_reset(&ct->ctbs.send, cmds);
- cmds = base + ptrdiff(ct->ctbs[i].cmds, blob);
- CT_DEBUG(ct, "%d: cmds addr=%#x\n", i, cmds);
-
- guc_ct_buffer_reset(&ct->ctbs[i], cmds);
- }
+ cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob);
+ guc_ct_buffer_reset(&ct->ctbs.recv, cmds);
/*
* Register both CT buffers starting with RECV buffer.
* Descriptors are in first half of the blob.
*/
- err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs[CTB_RECV].desc,
blob),
+ err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs.recv.desc, blob),
INTEL_GUC_CT_BUFFER_TYPE_RECV);
if (unlikely(err))
goto err_out;
- err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs[CTB_SEND].desc,
blob),
+ err = ct_register_buffer(ct, base + ptrdiff(ct->ctbs.send.desc, blob),
INTEL_GUC_CT_BUFFER_TYPE_SEND);
if (unlikely(err))
goto err_deregister;
@@ -341,7 +345,7 @@ static int ct_write(struct intel_guc_ct *ct,
u32 len /* in dwords */,
u32 fence)
{
- struct intel_guc_ct_buffer *ctb = &ct->ctbs[CTB_SEND];
+ struct intel_guc_ct_buffer *ctb = &ct->ctbs.send;
struct guc_ct_buffer_desc *desc = ctb->desc;
u32 head = desc->head;
u32 tail = desc->tail;
@@ -557,7 +561,7 @@ static inline bool ct_header_is_response(u32 header)
static int ct_read(struct intel_guc_ct *ct, u32 *data)
{
- struct intel_guc_ct_buffer *ctb = &ct->ctbs[CTB_RECV];
+ struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv;
struct guc_ct_buffer_desc *desc = ctb->desc;
u32 head = desc->head;
u32 tail = desc->tail;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index 4009e2dd0de4..fc9486779e87 100644
--- a/drivers/gpu/drm/i915/g
[Intel-gfx] [PATCH 2/2] drm/i915/guc: Update sizes of CTB buffers
From: Michal Wajdeczko
Future GuC will require CTB buffers sizes to be multiple of 4K.
Make these changes now as this shouldn't impact us too much.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 60 ---
1 file changed, 32 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 882ae1ed41b0..8d70f637640b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -38,6 +38,32 @@ static inline struct drm_device *ct_to_drm(struct
intel_guc_ct *ct)
#define CT_PROBE_ERROR(_ct, _fmt, ...) \
i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
+/**
+ * DOC: CTB Blob
+ *
+ * We allocate single blob to hold both CTB descriptors and buffers:
+ *
+ * ++---+--+
+ * | offset | contents | size |
+ * ++===+==+
+ * | 0x | H2G `CTB Descriptor`_ (send) | |
+ * ++---+ 4K |
+ * | 0x0800 | G2H `CTB Descriptor`_ (recv) | |
+ * ++---+--+
+ * | 0x1000 | H2G `CT Buffer`_ (send) | n*4K |
+ * || | |
+ * ++---+--+
+ * | 0x1000 | G2H `CT Buffer`_ (recv) | m*4K |
+ * | + n*4K | | |
+ * ++---+--+
+ *
+ * Size of each `CT Buffer`_ must be multiple of 4K.
+ * As we don't expect too many messages, for now use minimum sizes.
+ */
+#define CTB_DESC_SIZE ALIGN(sizeof(struct guc_ct_buffer_desc), SZ_2K)
+#define CTB_H2G_BUFFER_SIZE(SZ_4K)
+#define CTB_G2H_BUFFER_SIZE(SZ_4K)
+
struct ct_request {
struct list_head link;
u32 fence;
@@ -175,29 +201,7 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
GEM_BUG_ON(ct->vma);
- /* We allocate 1 page to hold both descriptors and both buffers.
-* ___.
-* |desc (SEND)| :
-* |___| PAGE/4
-* :___:
-* |desc (RECV)| :
-* |___| PAGE/4
-* :___:
-* |cmds (SEND)|
-* | PAGE/4
-* |___|
-* |cmds (RECV)|
-* | PAGE/4
-* |___|
-*
-* Each message can use a maximum of 32 dwords and we don't expect to
-* have more than 1 in flight at any time, so we have enough space.
-* Some logic further ahead will rely on the fact that there is only 1
-* page and that it is always mapped, so if the size is changed the
-* other code will need updating as well.
-*/
-
- blob_size = PAGE_SIZE;
+ blob_size = 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE +
CTB_G2H_BUFFER_SIZE;
err = intel_guc_allocate_and_map_vma(guc, blob_size, &ct->vma, &blob);
if (unlikely(err)) {
CT_PROBE_ERROR(ct, "Failed to allocate %u for CTB data (%pe)\n",
@@ -209,17 +213,17 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
/* store pointers to desc and cmds for send ctb */
desc = blob;
- cmds = blob + PAGE_SIZE / 2;
- cmds_size = PAGE_SIZE / 4;
+ cmds = blob + 2 * CTB_DESC_SIZE;
+ cmds_size = CTB_H2G_BUFFER_SIZE;
CT_DEBUG(ct, "%s desc %#p cmds %#p size %u\n", "send",
ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);
guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size);
/* store pointers to desc and cmds for recv ctb */
- desc = blob + PAGE_SIZE / 4;
- cmds = blob + PAGE_SIZE / 4 + PAGE_SIZE / 2;
- cmds_size = PAGE_SIZE / 4;
+ desc = blob + CTB_DESC_SIZE;
+ cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE;
+ cmds_size = CTB_G2H_BUFFER_SIZE;
CT_DEBUG(ct, "%s desc %#p cmds %#p size %u\n", "recv",
ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);
--
2.28.0
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Finish conversion to GRAPHICS_VER
== Series Details == Series: drm/i915: Finish conversion to GRAPHICS_VER URL : https://patchwork.freedesktop.org/series/90964/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10166_full -> Patchwork_20277_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20277_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20277_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20277_full: ### IGT changes ### Possible regressions * igt@kms_big_fb@linear-16bpp-rotate-180: - shard-iclb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/shard-iclb2/igt@kms_big...@linear-16bpp-rotate-180.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/shard-iclb2/igt@kms_big...@linear-16bpp-rotate-180.html Known issues Here are the changes found in Patchwork_20277_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +7 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/shard-kbl1/igt@gem_ctx_isolation@preservation...@bcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/shard-kbl3/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_ctx_persistence@many-contexts: - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2410]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/shard-tglb3/igt@gem_ctx_persiste...@many-contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/shard-tglb7/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_ctx_persistence@smoketest: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +7 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/shard-snb2/igt@gem_ctx_persiste...@smoketest.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][8] ([i915#3354]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/shard-snb7/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2846]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/shard-glk7/igt@gem_exec_f...@basic-deadline.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/shard-glk4/igt@gem_exec_f...@basic-deadline.html - shard-apl: NOTRUN -> [FAIL][11] ([i915#2846]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/shard-apl8/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-kbl: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/shard-kbl4/igt@gem_exec_fair@basic-none-sh...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/shard-kbl3/igt@gem_exec_fair@basic-none-sh...@rcs0.html - shard-apl: [PASS][14] -> [SKIP][15] ([fdo#109271]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/shard-apl7/igt@gem_exec_fair@basic-none-sh...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/shard-apl7/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: NOTRUN -> [FAIL][16] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [PASS][17] -> [FAIL][18] ([i915#2842]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/shard-tglb8/igt@gem_exec_fair@basic-p...@vecs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/shard-tglb8/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_mmap_gtt@cpuset-big-copy-xy: - shard-iclb: [PASS][19] -> [FAIL][20] ([i915#307]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/shard-iclb2/igt@gem_mmap_...@cpuset-big-copy-xy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/shard-iclb4/igt@gem_mmap_...@cpuset-big-copy-xy.html * igt@gem_pwrite@basic-exhaustion: - shard-apl: NOTRUN -> [WARN][21] ([i915#2658]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/shard-apl7/igt@gem_pwr...@basic-exhaustion.html * igt@gem_userptr_blits@input-checking: - shard-snb: NOTRUN -> [DMESG-WARN][22] ([i915#3002]) [22]: https://intel-gfx-ci.01.org/t
[Intel-gfx] [PATCH v2] drm/i915: Initialize the mbus_offset to fix static analysis issue
Static analysis identified an issue in skl_crtc_allocate_ddb where
mbus_offset may be used uninitialized.
This patch fixes it.
Fixes: 835c176cb1c4 ("drm/i915: Introduce MBUS relative dbuf offsets")
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 00f3dead20ad..a385b8b7414f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4163,7 +4163,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state,
struct intel_crtc *crtc)
struct intel_crtc_state *crtc_state;
struct skl_ddb_entry ddb_slices;
enum pipe pipe = crtc->pipe;
- unsigned int mbus_offset;
+ unsigned int mbus_offset = 0;
u32 ddb_range_size;
u32 dbuf_slice_mask;
u32 start, end;
--
2.19.1
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for shmem helpers for vgem (rev5)
== Series Details ==
Series: shmem helpers for vgem (rev5)
URL : https://patchwork.freedesktop.org/series/90670/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10166 -> Patchwork_20278
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20278 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20278, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20278/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_20278:
### IGT changes ###
Possible regressions
* igt@prime_vgem@basic-fence-mmap:
- fi-bsw-kefka: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-bsw-kefka/igt@prime_v...@basic-fence-mmap.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20278/fi-bsw-kefka/igt@prime_v...@basic-fence-mmap.html
- fi-bsw-nick:[PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-bsw-nick/igt@prime_v...@basic-fence-mmap.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20278/fi-bsw-nick/igt@prime_v...@basic-fence-mmap.html
- fi-bwr-2160:[PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-bwr-2160/igt@prime_v...@basic-fence-mmap.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20278/fi-bwr-2160/igt@prime_v...@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- fi-ilk-650: [PASS][7] -> [INCOMPLETE][8] +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-ilk-650/igt@prime_v...@basic-fence-read.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20278/fi-ilk-650/igt@prime_v...@basic-fence-read.html
- fi-elk-e7500: [PASS][9] -> [INCOMPLETE][10] +1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-elk-e7500/igt@prime_v...@basic-fence-read.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20278/fi-elk-e7500/igt@prime_v...@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- fi-ilk-650: [PASS][11] -> [FAIL][12] +2 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-ilk-650/igt@prime_v...@basic-gtt.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20278/fi-ilk-650/igt@prime_v...@basic-gtt.html
- fi-elk-e7500: [PASS][13] -> [FAIL][14] +2 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-elk-e7500/igt@prime_v...@basic-gtt.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20278/fi-elk-e7500/igt@prime_v...@basic-gtt.html
* igt@prime_vgem@basic-read:
- fi-bwr-2160:[PASS][15] -> [FAIL][16] +3 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-bwr-2160/igt@prime_v...@basic-read.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20278/fi-bwr-2160/igt@prime_v...@basic-read.html
- fi-bsw-nick:[PASS][17] -> [FAIL][18] +3 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-bsw-nick/igt@prime_v...@basic-read.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20278/fi-bsw-nick/igt@prime_v...@basic-read.html
- fi-bsw-kefka: [PASS][19] -> [FAIL][20] +2 similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-bsw-kefka/igt@prime_v...@basic-read.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20278/fi-bsw-kefka/igt@prime_v...@basic-read.html
* igt@prime_vgem@basic-write:
- fi-pnv-d510:[PASS][21] -> [FAIL][22] +4 similar issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-pnv-d510/igt@prime_v...@basic-write.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20278/fi-pnv-d510/igt@prime_v...@basic-write.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@prime_self_import@basic-with_two_bos:
- {fi-rkl-11500t}:NOTRUN -> [FAIL][23] +5 similar issues
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20278/fi-rkl-11500t/igt@prime_self_import@basic-with_two_bos.html
* igt@prime_vgem@basic-fence-flip:
- {fi-rkl-11500t}:NOTRUN -> [SKIP][24] +11 similar issues
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20278/fi-rkl-11500t/igt@prime_v...@basic-fence-flip.html
Known issues
Here are the changes found in Patchwork_20278 that come from known issues:
### IGT changes ###
Warnings
* igt@i915_selftest@live@execl
[Intel-gfx] [PATCH] drm/i915: Initialize the mbus_offset to fix Klockwork issue
Static analysis identified an issue in skl_crtc_allocate_ddb where
mbus_offset may be used uninitialized.
This patch fixes it.
Fixes: 835c176cb1c4 ("drm/i915: Introduce MBUS relative dbuf offsets")
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 00f3dead20ad..a385b8b7414f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4163,7 +4163,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state,
struct intel_crtc *crtc)
struct intel_crtc_state *crtc_state;
struct skl_ddb_entry ddb_slices;
enum pipe pipe = crtc->pipe;
- unsigned int mbus_offset;
+ unsigned int mbus_offset = 0;
u32 ddb_range_size;
u32 dbuf_slice_mask;
u32 start, end;
--
2.19.1
___
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Re: [Intel-gfx] [PATCH 11/20] drm/i915/guc: Replace CTB array with explicit members
On Thu, Jun 03, 2021 at 03:25:29PM +0800, kernel test robot wrote:
> Hi Matthew,
>
> Thank you for the patch! Yet something to improve:
>
> [auto build test ERROR on drm-tip/drm-tip]
> [also build test ERROR on drm-exynos/exynos-drm-next
> tegra-drm/drm/tegra/for-next v5.13-rc4 next-20210602]
> [cannot apply to drm-intel/for-linux-next drm/drm-next]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url:
> https://github.com/0day-ci/linux/commits/Matthew-Brost/GuC-CTBs-changes-a-few-misc-patches/20210603-130102
> base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
> config: i386-randconfig-a015-20210603 (attached as .config)
> compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
> reproduce (this is a W=1 build):
> #
> https://github.com/0day-ci/linux/commit/7672d3ecddcd8af3a2a856facac49ca93d4bdf9e
> git remote add linux-review https://github.com/0day-ci/linux
> git fetch --no-tags linux-review
> Matthew-Brost/GuC-CTBs-changes-a-few-misc-patches/20210603-130102
> git checkout 7672d3ecddcd8af3a2a856facac49ca93d4bdf9e
> # save the attached .config to linux build tree
> make W=1 ARCH=i386
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot
>
> All errors (new ones prefixed by >>):
>
>In file included from include/drm/drm_mm.h:49,
> from include/drm/drm_vma_manager.h:26,
> from include/drm/drm_gem.h:40,
> from drivers/gpu/drm/i915/i915_drv.h:54,
> from drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:6:
>drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c: In function 'intel_guc_ct_init':
> >> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:34:26: error: format '%lx'
> >> expects argument of type 'long unsigned int', but argument 5 has type
> >> 'ptrdiff_t' {aka 'int'} [-Werror=format=]
> 34 | drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
> | ^~
>..
> 215 |ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);
> |~~~
> ||
> |ptrdiff_t {aka int}
>include/drm/drm_print.h:448:56: note: in definition of macro 'drm_dbg'
> 448 | drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DRIVER, fmt,
> ##__VA_ARGS__)
> |^~~
>drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:214:2: note: in expansion of
> macro 'CT_DEBUG'
> 214 | CT_DEBUG(ct, "%s desc %#lx cmds %#lx size %u\n", "send",
> | ^~~~
>drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:214:27: note: format string is
> defined here
> 214 | CT_DEBUG(ct, "%s desc %#lx cmds %#lx size %u\n", "send",
> |~~~^
> | |
> | long unsigned int
32bit ptrdiff vs 64bit printk modifier. You need something else here.
I've stuffed all the previous patches into drm-intel-gt-next. If you
resend with just this one fixed here I'll continue tomorrow (--in-reply-to
resend I mean).
Thanks, Daniel
> |%#x
>In file included from include/drm/drm_mm.h:49,
> from include/drm/drm_vma_manager.h:26,
> from include/drm/drm_gem.h:40,
> from drivers/gpu/drm/i915/i915_drv.h:54,
> from drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:6:
>drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:34:26: error: format '%lx'
> expects argument of type 'long unsigned int', but argument 6 has type
> 'ptrdiff_t' {aka 'int'} [-Werror=format=]
> 34 | drm_dbg(ct_to_drm(_ct), "CT: " _fmt, ##__VA_ARGS__)
> | ^~
>..
> 215 |ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size);
> | ~~~
> | |
> | ptrdiff_t {aka int}
>include/drm/drm_print.h:448:56: note: in definition of macro 'drm_dbg'
> 448 | drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DRIVER, fmt,
> ##__VA_ARGS__)
> |^~~
>drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:214:2: note: in expansion of
> macro 'CT_DEBUG
Re: [Intel-gfx] [PATCH 08/20] drm/i915: Promote ptrdiff() to i915_utils.h
On Wed, Jun 02, 2021 at 10:16:18PM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> Generic helpers should be placed in i915_utils.h.
Random rant, but we're _way_ too happy to just stuff random things into
i915_utils.h without trying to properly upstream it.
For thinks like this the general dumping ground would be kernel.h, there's
a few pointer helpers there already. Follow up patch maybe nice.
-Daniel
>
> Signed-off-by: Michal Wajdeczko
> Signed-off-by: Matthew Brost
> Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/i915_utils.h | 5 +
> drivers/gpu/drm/i915/i915_vma.h | 5 -
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_utils.h
> b/drivers/gpu/drm/i915/i915_utils.h
> index f02f52ab5070..5259edacde38 100644
> --- a/drivers/gpu/drm/i915/i915_utils.h
> +++ b/drivers/gpu/drm/i915/i915_utils.h
> @@ -201,6 +201,11 @@ __check_struct_size(size_t base, size_t arr, size_t
> count, size_t *size)
> __T;\
> })
>
> +static __always_inline ptrdiff_t ptrdiff(const void *a, const void *b)
> +{
> + return a - b;
> +}
> +
> /*
> * container_of_user: Extract the superclass from a pointer to a member.
> *
> diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
> index dc6926d89626..eca452a9851f 100644
> --- a/drivers/gpu/drm/i915/i915_vma.h
> +++ b/drivers/gpu/drm/i915/i915_vma.h
> @@ -151,11 +151,6 @@ static inline void i915_vma_put(struct i915_vma *vma)
> i915_gem_object_put(vma->obj);
> }
>
> -static __always_inline ptrdiff_t ptrdiff(const void *a, const void *b)
> -{
> - return a - b;
> -}
> -
> static inline long
> i915_vma_compare(struct i915_vma *vma,
>struct i915_address_space *vm,
> --
> 2.28.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for shmem helpers for vgem (rev5)
== Series Details ==
Series: shmem helpers for vgem (rev5)
URL : https://patchwork.freedesktop.org/series/90670/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9e8ef4e2828c dma-buf: Require VM_PFNMAP vma for mmap
-:34: WARNING:TYPO_SPELLING: 'entires' may be misspelled - perhaps 'entries'?
#34:
>From auditing the various functions to insert pfn pte entires
^^^
-:39: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#39:
References:
https://lore.kernel.org/lkml/cakmk7uhi+mg0z0humnt13qccvuturvjpcr0njrl12k-wbwz...@mail.gmail.com/
-:97: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by:
Daniel Vetter '
total: 0 errors, 3 warnings, 0 checks, 39 lines checked
dd1ffdf52775 drm/shmem-helper: Switch to vmf_insert_pfn
-:14: WARNING:TYPO_SPELLING: 'wont' may be misspelled - perhaps 'won't'?
#14:
helpers for these drivers on those platforms. As-is this wont work.
-:17: WARNING:TYPO_SPELLING: 'wont' may be misspelled - perhaps 'won't'?
#17:
definitely wont fly in practice since the pages are non-contig to
-:108: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by:
Daniel Vetter '
total: 0 errors, 3 warnings, 0 checks, 55 lines checked
6d03cb0b1181 drm/shmem-helper: Align to page size in dumb_create
-:37: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by:
Daniel Vetter '
total: 0 errors, 1 warnings, 0 checks, 15 lines checked
d4c823697fde drm/vgem: use shmem helpers
-:22: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 0cf2ef46c6c0 ("drm/shmem-helper:
Use cached mappings by default")'
#22:
v4: I got tricked by 0cf2ef46c6c0 ("drm/shmem-helper: Use cached
-:326: WARNING:TYPO_SPELLING: 'wont' may be misspelled - perhaps 'won't'?
#326: FILE: drivers/gpu/drm/vgem/vgem_drv.c:104:
+* coherent memory or dma-buf sharing just wont work.
-:457: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by:
Daniel Vetter '
total: 1 errors, 2 warnings, 0 checks, 402 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/9] drm/i915: Move active tracking to i915_sched_engine
Move active request tracking and its lock to i915_sched_engine. This
lock is also the submission lock so having it in the i915_sched_engine
is the correct place.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_engine.h| 2 -
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 43 +++-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 6 --
.../drm/i915/gt/intel_execlists_submission.c | 98 ++-
.../gpu/drm/i915/gt/intel_ring_submission.c | 12 +--
drivers/gpu/drm/i915/gt/mock_engine.c | 7 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 4 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 20 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
drivers/gpu/drm/i915/i915_request.c | 32 +++---
drivers/gpu/drm/i915/i915_request.h | 2 +-
drivers/gpu/drm/i915/i915_scheduler.c | 30 --
drivers/gpu/drm/i915/i915_scheduler_types.h | 9 ++
13 files changed, 134 insertions(+), 135 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 8d9184920c51..a8b2174b4395 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -257,8 +257,6 @@ intel_engine_find_active_request(struct intel_engine_cs
*engine);
u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
-void intel_engine_init_active(struct intel_engine_cs *engine,
- unsigned int subclass);
#define ENGINE_PHYSICAL0
#define ENGINE_MOCK1
#define ENGINE_VIRTUAL 2
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 85f2effe9dc6..33d879137908 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -719,7 +719,6 @@ static int engine_setup_common(struct intel_engine_cs
*engine)
if (err)
goto err_cmd_parser;
- intel_engine_init_active(engine, ENGINE_PHYSICAL);
intel_engine_init_execlists(engine);
intel_engine_init__pm(engine);
intel_engine_init_retire(engine);
@@ -778,11 +777,11 @@ static int measure_breadcrumb_dw(struct intel_context *ce)
frame->rq.ring = &frame->ring;
mutex_lock(&ce->timeline->mutex);
- spin_lock_irq(&engine->active.lock);
+ spin_lock_irq(&engine->sched_engine->lock);
dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
- spin_unlock_irq(&engine->active.lock);
+ spin_unlock_irq(&engine->sched_engine->lock);
mutex_unlock(&ce->timeline->mutex);
GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
@@ -791,28 +790,6 @@ static int measure_breadcrumb_dw(struct intel_context *ce)
return dw;
}
-void
-intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass)
-{
- INIT_LIST_HEAD(&engine->active.requests);
- INIT_LIST_HEAD(&engine->active.hold);
-
- spin_lock_init(&engine->active.lock);
- lockdep_set_subclass(&engine->active.lock, subclass);
-
- /*
-* Due to an interesting quirk in lockdep's internal debug tracking,
-* after setting a subclass we must ensure the lock is used. Otherwise,
-* nr_unused_locks is incremented once too often.
-*/
-#ifdef CONFIG_DEBUG_LOCK_ALLOC
- local_irq_disable();
- lock_map_acquire(&engine->active.lock.dep_map);
- lock_map_release(&engine->active.lock.dep_map);
- local_irq_enable();
-#endif
-}
-
static struct intel_context *
create_pinned_context(struct intel_engine_cs *engine,
unsigned int hwsp,
@@ -960,7 +937,7 @@ int intel_engines_init(struct intel_gt *gt)
*/
void intel_engine_cleanup_common(struct intel_engine_cs *engine)
{
- GEM_BUG_ON(!list_empty(&engine->active.requests));
+ GEM_BUG_ON(!list_empty(&engine->sched_engine->requests));
tasklet_kill(&engine->execlists.tasklet); /* flush the callback */
i915_sched_engine_put(engine->sched_engine);
@@ -1353,7 +1330,7 @@ static struct intel_timeline *get_timeline(struct
i915_request *rq)
struct intel_timeline *tl;
/*
-* Even though we are holding the engine->active.lock here, there
+* Even though we are holding the engine->sched_engine->lock here, there
* is no control over the submission queue per-se and we are
* inspecting the active state at a random point in time, with an
* unknown queue. Play safe and make sure the timeline remains valid.
@@ -1700,7 +1677,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
drm_printf(m, "\tRequests:\n");
- spin_lock_irqsave(&engine->active.lock, flags);
+ spin_lock_irqsave(&engine->sched_engine->lock, flags);
rq = intel_engine_find_active_request(engine);
if (rq) {
struct intel_timeline *tl = get_timeline(rq);
@@ -1731,8 +1708,9 @@ void intel_eng
[Intel-gfx] [PATCH 8/9] drm/i915: Move submission tasklet to i915_sched_engine
The submission tasklet operates on i915_sched_engine, thus it is the
correct place for it.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_engine.h| 14 ---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 +--
drivers/gpu/drm/i915/gt/intel_engine_types.h | 5 --
.../drm/i915/gt/intel_execlists_submission.c | 86 ++-
drivers/gpu/drm/i915/gt/mock_engine.c | 1 +
drivers/gpu/drm/i915/gt/selftest_execlists.c | 16 ++--
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c| 6 +-
drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 25 +++---
drivers/gpu/drm/i915/i915_scheduler.c | 1 +
drivers/gpu/drm/i915/i915_scheduler.h | 14 +++
drivers/gpu/drm/i915/i915_scheduler_types.h | 8 ++
13 files changed, 99 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index a8b2174b4395..988d9688ae4d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -123,20 +123,6 @@ execlists_active(const struct intel_engine_execlists
*execlists)
return active;
}
-static inline void
-execlists_active_lock_bh(struct intel_engine_execlists *execlists)
-{
- local_bh_disable(); /* prevent local softirq and lock recursion */
- tasklet_lock(&execlists->tasklet);
-}
-
-static inline void
-execlists_active_unlock_bh(struct intel_engine_execlists *execlists)
-{
- tasklet_unlock(&execlists->tasklet);
- local_bh_enable(); /* restore softirq, and kick ksoftirqd! */
-}
-
struct i915_request *
execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index b480fcb1aad1..837d2132e31b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -711,6 +711,7 @@ static int engine_setup_common(struct intel_engine_cs
*engine)
err = -ENOMEM;
goto err_sched_engine;
}
+ engine->sched_engine->engine = engine;
err = intel_engine_init_cmd_parser(engine);
if (err)
@@ -935,7 +936,6 @@ int intel_engines_init(struct intel_gt *gt)
void intel_engine_cleanup_common(struct intel_engine_cs *engine)
{
GEM_BUG_ON(!list_empty(&engine->sched_engine->requests));
- tasklet_kill(&engine->execlists.tasklet); /* flush the callback */
i915_sched_engine_put(engine->sched_engine);
intel_breadcrumbs_free(engine->breadcrumbs);
@@ -1221,7 +1221,7 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync)
{
- struct tasklet_struct *t = &engine->execlists.tasklet;
+ struct tasklet_struct *t = &engine->sched_engine->tasklet;
if (!t->callback)
return;
@@ -1482,8 +1482,8 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s,
timeslice? %s\n",
yesno(test_bit(TASKLET_STATE_SCHED,
- &engine->execlists.tasklet.state)),
-
enableddisabled(!atomic_read(&engine->execlists.tasklet.count)),
+
&engine->sched_engine->tasklet.state)),
+
enableddisabled(!atomic_read(&engine->sched_engine->tasklet.count)),
repr_timer(&engine->execlists.preempt),
repr_timer(&engine->execlists.timer));
@@ -1507,7 +1507,7 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
idx, hws[idx * 2], hws[idx * 2 + 1]);
}
- execlists_active_lock_bh(execlists);
+ i915_sched_engine_active_lock_bh(engine->sched_engine);
rcu_read_lock();
for (port = execlists->active; (rq = *port); port++) {
char hdr[160];
@@ -1538,7 +1538,7 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
i915_request_show(m, rq, hdr, 0);
}
rcu_read_unlock();
- execlists_active_unlock_bh(execlists);
+ i915_sched_engine_active_unlock_bh(engine->sched_engine);
} else if (INTEL_GEN(dev_priv) > 6) {
drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
ENGINE_READ(engine, RING_PP_DIR_BASE));
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index f1b14aff5118..6f2fd6f13ac4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -
[Intel-gfx] [PATCH 5/9] drm/i915: Move engine->schedule to i915_sched_engine
The schedule function should be in the schedule object.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_wait.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 3 ---
drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_engine_types.h | 8
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
.../gpu/drm/i915/gt/intel_execlists_submission.c | 4 ++--
drivers/gpu/drm/i915/gt/selftest_execlists.c | 16
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 4 ++--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c| 2 +-
drivers/gpu/drm/i915/i915_request.c | 10 +-
drivers/gpu/drm/i915/i915_scheduler_types.h | 8
11 files changed, 31 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
index 4b9856d5ba14..af1fbf8e2a9a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
@@ -104,8 +104,8 @@ static void fence_set_priority(struct dma_fence *fence,
engine = rq->engine;
rcu_read_lock(); /* RCU serialisation for set-wedged protection */
- if (engine->schedule)
- engine->schedule(rq, attr);
+ if (engine->sched_engine->schedule)
+ engine->sched_engine->schedule(rq, attr);
rcu_read_unlock();
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 33d879137908..b480fcb1aad1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -326,9 +326,6 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
if (engine->context_size)
DRIVER_CAPS(i915)->has_logical_contexts = true;
- /* Nothing to do here, execute in order of dependencies */
- engine->schedule = NULL;
-
ewma__engine_latency_init(&engine->latency);
seqcount_init(&engine->stats.lock);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index b99ac41695f3..b6a305e6a974 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -121,7 +121,7 @@ static void heartbeat(struct work_struct *wrk)
* but all other contexts, including the kernel
* context are stuck waiting for the signal.
*/
- } else if (engine->schedule &&
+ } else if (engine->sched_engine->schedule &&
rq->sched.attr.priority < I915_PRIORITY_BARRIER) {
/*
* Gradually raise the priority of the heartbeat to
@@ -136,7 +136,7 @@ static void heartbeat(struct work_struct *wrk)
attr.priority = I915_PRIORITY_BARRIER;
local_bh_disable();
- engine->schedule(rq, &attr);
+ engine->sched_engine->schedule(rq, &attr);
local_bh_enable();
} else {
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 7197b9fa5e35..f1b14aff5118 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -426,14 +426,6 @@ struct intel_engine_cs {
void(*bond_execute)(struct i915_request *rq,
struct dma_fence *signal);
- /*
-* Call when the priority on a request has changed and it and its
-* dependencies may need rescheduling. Note the request itself may
-* not be ready to run!
-*/
- void(*schedule)(struct i915_request *request,
- const struct i915_sched_attr *attr);
-
void(*release)(struct intel_engine_cs *engine);
struct intel_engine_execlists execlists;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 3cca7ea2d6ea..84142127ebd8 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -108,7 +108,7 @@ static void set_scheduler_caps(struct drm_i915_private
*i915)
for_each_uabi_engine(engine, i915) { /* all engines must agree! */
int i;
- if (engine->schedule)
+ if (engine->sched_engine->schedule)
enabled |= (I915_SCHEDULER_CAP_ENABLED |
I915_SCHEDULER_CAP_PRIORITY);
else
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index
[Intel-gfx] [PATCH 3/9] drm/i915: Add i915_sched_engine_reset_on_empty function
Rather than touching schedule state in the generic PM code, reset the
priolist allocation when empty in the submission code. Add a wrapper
function to do this and update the backends to call it in the correct
place.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c| 2 --
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c| 2 ++
drivers/gpu/drm/i915/i915_scheduler.h| 7 +++
4 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index b6a00dd72808..1f07ac4e0672 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -280,8 +280,6 @@ static int __engine_park(struct intel_wakeref *wf)
if (engine->park)
engine->park(engine);
- engine->sched_engine->no_priolist = false;
-
/* While gt calls i915_vma_parked(), we have to break the lock cycle */
intel_gt_pm_put_async(engine->gt);
return 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 2326a73af6d3..609753b5401a 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1553,6 +1553,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* interrupt for secondary ports).
*/
sched_engine->queue_priority_hint = queue_prio(sched_engine);
+ i915_sched_engine_reset_on_empty(sched_engine);
spin_unlock(&engine->active.lock);
/*
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 5d00f2e3c1de..f4a6fbfaf82e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -263,6 +263,8 @@ static void guc_submission_tasklet(struct tasklet_struct *t)
__guc_dequeue(engine);
+ i915_sched_engine_reset_on_empty(engine->sched_engine);
+
spin_unlock_irqrestore(&engine->active.lock, flags);
}
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h
b/drivers/gpu/drm/i915/i915_scheduler.h
index 5bec7b3b8456..713c38c99de9 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -72,6 +72,13 @@ i915_sched_engine_is_empty(struct i915_sched_engine
*sched_engine)
return RB_EMPTY_ROOT(&sched_engine->queue.rb_root);
}
+static inline void
+i915_sched_engine_reset_on_empty(struct i915_sched_engine *sched_engine)
+{
+ if (i915_sched_engine_is_empty(sched_engine))
+ sched_engine->no_priolist = false;
+}
+
void i915_request_show_with_schedule(struct drm_printer *m,
const struct i915_request *rq,
const char *prefix,
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 9/9] drm/i915/doc: Add kernel doc for i915_sched_engine
Signed-off-by: Matthew Brost
---
Documentation/gpu/i915.rst | 6
drivers/gpu/drm/i915/i915_scheduler_types.h | 37 ++---
2 files changed, 38 insertions(+), 5 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 42ce0196930a..8f4f5471a05b 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -425,6 +425,12 @@ User Batchbuffer Execution
.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
:doc: User command execution
+Scheduling
+--
+.. kernel-doc:: drivers/gpu/drm/i915/i915_scheduler_types.h
+ :functions: i915_sched_engine
+
+
Logical Rings, Logical Ring Contexts and Execlists
--
diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h
b/drivers/gpu/drm/i915/i915_scheduler_types.h
index 9d79514450de..e3da7517853f 100644
--- a/drivers/gpu/drm/i915/i915_scheduler_types.h
+++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
@@ -91,7 +91,21 @@ struct i915_dependency {
&(rq__)->sched.signalers_list, \
signal_link)
+/**
+ * sturct i915_sched_engine - scheduler engine
+ *
+ * A schedule engine represents a submission queue with different priority
+ * bands. It contains all the common state (relative to the backend) to queue,
+ * track, and submit a request.
+ *
+ * This object at the moment is quite i915 specific but will transition into a
+ * container for the drm_gpu_scheduler plus a few other variables once the i915
+ * is integrated with the DRM scheduler.
+ */
struct i915_sched_engine {
+ /**
+* @ref: reference count of schedule engine object
+*/
struct kref ref;
/**
@@ -100,11 +114,18 @@ struct i915_sched_engine {
*/
spinlock_t lock;
+ /**
+* @requests: list of requests inflight on this schedule engine
+*/
struct list_head requests;
- struct list_head hold; /* ready requests, but on hold */
/**
-* @tasklet: softirq tasklet for bottom handler
+* @hold: list of requests on hold.
+*/
+ struct list_head hold;
+
+ /**
+* @tasklet: softirq tasklet for submission
*/
struct tasklet_struct tasklet;
@@ -137,14 +158,20 @@ struct i915_sched_engine {
*/
bool no_priolist;
- /* Back pointer to engine */
+ /**
+* @engine: back pointer to engine
+*/
struct intel_engine_cs *engine;
- /* Kick backend */
+ /**
+* @kick_backed: kick back after a request's priority has changed
+*/
void(*kick_backend)(const struct i915_request *rq,
int prio);
- /*
+ /**
+* @schedule: schedule function to adjust priority of request
+*
* Call when the priority on a request has changed and it and its
* dependencies may need rescheduling. Note the request itself may
* not be ready to run!
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/9] drm/i915: Add kick_backend function to i915_sched_engine
Rather than touching execlist specific structures in the generic
scheduling code, add a callback function in the backend.
Signed-off-by: Matthew Brost
---
.../drm/i915/gt/intel_execlists_submission.c | 52
drivers/gpu/drm/i915/i915_scheduler.c | 62 +--
drivers/gpu/drm/i915/i915_scheduler_types.h | 4 ++
3 files changed, 58 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 23fd03815ad0..3fac17103837 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3116,10 +3116,61 @@ static bool can_preempt(struct intel_engine_cs *engine)
return engine->class != RENDER_CLASS;
}
+static void kick_execlists(const struct i915_request *rq, int prio)
+{
+ struct intel_engine_cs *engine = rq->engine;
+ struct i915_sched_engine *sched_engine = engine->sched_engine;
+ const struct i915_request *inflight;
+
+ /*
+* We only need to kick the tasklet once for the high priority
+* new context we add into the queue.
+*/
+ if (prio <= sched_engine->queue_priority_hint)
+ return;
+
+ rcu_read_lock();
+
+ /* Nothing currently active? We're overdue for a submission! */
+ inflight = execlists_active(&engine->execlists);
+ if (!inflight)
+ goto unlock;
+
+ /*
+* If we are already the currently executing context, don't
+* bother evaluating if we should preempt ourselves.
+*/
+ if (inflight->context == rq->context)
+ goto unlock;
+
+ ENGINE_TRACE(engine,
+"bumping queue-priority-hint:%d for rq:%llx:%lld,
inflight:%llx:%lld prio %d\n",
+prio,
+rq->fence.context, rq->fence.seqno,
+inflight->fence.context, inflight->fence.seqno,
+inflight->sched.attr.priority);
+
+ sched_engine->queue_priority_hint = prio;
+
+ /*
+* Allow preemption of low -> normal -> high, but we do
+* not allow low priority tasks to preempt other low priority
+* tasks under the impression that latency for low priority
+* tasks does not matter (as much as background throughput),
+* so kiss.
+*/
+ if (prio >= max(I915_PRIORITY_NORMAL, rq_prio(inflight)))
+ tasklet_hi_schedule(&engine->execlists.tasklet);
+
+unlock:
+ rcu_read_unlock();
+}
+
static void execlists_set_default_submission(struct intel_engine_cs *engine)
{
engine->submit_request = execlists_submit_request;
engine->sched_engine->schedule = i915_schedule;
+ engine->sched_engine->kick_backend = kick_execlists;
engine->execlists.tasklet.callback = execlists_submission_tasklet;
}
@@ -3702,6 +3753,7 @@ intel_execlists_create_virtual(struct intel_engine_cs
**siblings,
ve->base.request_alloc = execlists_request_alloc;
ve->base.sched_engine->schedule = i915_schedule;
+ ve->base.sched_engine->kick_backend = kick_execlists;
ve->base.submit_request = virtual_submit_request;
ve->base.bond_execute = virtual_bond_execute;
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 4bc6969f6a97..035b88f2e4aa 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -157,65 +157,6 @@ sched_lock_engine(const struct i915_sched_node *node,
return locked;
}
-static inline int rq_prio(const struct i915_request *rq)
-{
- return rq->sched.attr.priority;
-}
-
-static inline bool need_preempt(int prio, int active)
-{
- /*
-* Allow preemption of low -> normal -> high, but we do
-* not allow low priority tasks to preempt other low priority
-* tasks under the impression that latency for low priority
-* tasks does not matter (as much as background throughput),
-* so kiss.
-*/
- return prio >= max(I915_PRIORITY_NORMAL, active);
-}
-
-static void kick_submission(struct intel_engine_cs *engine,
- const struct i915_request *rq,
- int prio)
-{
- const struct i915_request *inflight;
-
- /*
-* We only need to kick the tasklet once for the high priority
-* new context we add into the queue.
-*/
- if (prio <= engine->sched_engine->queue_priority_hint)
- return;
-
- rcu_read_lock();
-
- /* Nothing currently active? We're overdue for a submission! */
- inflight = execlists_active(&engine->execlists);
- if (!inflight)
- goto unlock;
-
- /*
-* If we are already the currently executing context, don't
-* bother evaluating if we should preempt ourselves.
-*/
- if (infli
[Intel-gfx] [PATCH 2/9] drm/i915: Add i915_sched_engine_is_empty function
Add wrapper function around RB tree to determine if i915_sched_engine is
empty.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 +-
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 6 +++---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c| 2 +-
drivers/gpu/drm/i915/i915_scheduler.h| 6 ++
4 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index d0f3814440f6..85f2effe9dc6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1287,7 +1287,7 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
intel_engine_flush_submission(engine);
/* ELSP is empty, but there are ready requests? E.g. after reset */
- if (!RB_EMPTY_ROOT(&engine->sched_engine->queue.rb_root))
+ if (!i915_sched_engine_is_empty(engine->sched_engine))
return false;
/* Ring stopped? */
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index d1dc1db3e378..2326a73af6d3 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -384,7 +384,7 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine)
prio = rq_prio(rq);
pl = i915_sched_lookup_priolist(engine, prio);
}
- GEM_BUG_ON(RB_EMPTY_ROOT(&engine->sched_engine->queue.rb_root));
+ GEM_BUG_ON(i915_sched_engine_is_empty(engine->sched_engine));
list_move(&rq->sched.link, pl);
set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
@@ -1139,7 +1139,7 @@ static bool needs_timeslice(const struct intel_engine_cs
*engine,
}
/* Otherwise, ELSP[0] is by itself, but may be waiting in the queue */
- if (!RB_EMPTY_ROOT(&engine->sched_engine->queue.rb_root)) {
+ if (!i915_sched_engine_is_empty(engine->sched_engine)) {
ENGINE_TRACE(engine, "timeslice required for queue\n");
return true;
}
@@ -2487,7 +2487,7 @@ static void execlists_submit_request(struct i915_request
*request)
} else {
queue_request(engine, request);
- GEM_BUG_ON(RB_EMPTY_ROOT(&engine->sched_engine->queue.rb_root));
+ GEM_BUG_ON(i915_sched_engine_is_empty(engine->sched_engine));
GEM_BUG_ON(list_empty(&request->sched.link));
if (submit_queue(engine, request))
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index d42dea79ee64..5d00f2e3c1de 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -541,7 +541,7 @@ static void guc_submit_request(struct i915_request *rq)
queue_request(engine, rq, rq_prio(rq));
- GEM_BUG_ON(RB_EMPTY_ROOT(&engine->sched_engine->queue.rb_root));
+ GEM_BUG_ON(i915_sched_engine_is_empty(engine->sched_engine));
GEM_BUG_ON(list_empty(&rq->sched.link));
tasklet_hi_schedule(&engine->execlists.tasklet);
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h
b/drivers/gpu/drm/i915/i915_scheduler.h
index 91a04e34cac5..5bec7b3b8456 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -66,6 +66,12 @@ i915_sched_engine_put(struct i915_sched_engine *sched_engine)
kref_put(&sched_engine->ref, i915_sched_engine_free);
}
+static inline bool
+i915_sched_engine_is_empty(struct i915_sched_engine *sched_engine)
+{
+ return RB_EMPTY_ROOT(&sched_engine->queue.rb_root);
+}
+
void i915_request_show_with_schedule(struct drm_printer *m,
const struct i915_request *rq,
const char *prefix,
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/9] drm/i915: Update i915_scheduler to operate on i915_sched_engine
Rather passing around an intel_engine_cs in the scheduling code, pass
around a i915_sched_engine.
Signed-off-by: Matthew Brost
---
.../drm/i915/gt/intel_execlists_submission.c | 11 +++--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/i915_scheduler.c | 46 +--
drivers/gpu/drm/i915/i915_scheduler.h | 2 +-
4 files changed, 32 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 3fac17103837..7240c153be35 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -382,7 +382,8 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine)
GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
if (rq_prio(rq) != prio) {
prio = rq_prio(rq);
- pl = i915_sched_lookup_priolist(engine, prio);
+ pl = i915_sched_lookup_priolist(engine->sched_engine,
+ prio);
}
GEM_BUG_ON(i915_sched_engine_is_empty(engine->sched_engine));
@@ -1096,7 +1097,8 @@ static void defer_active(struct intel_engine_cs *engine)
if (!rq)
return;
- defer_request(rq, i915_sched_lookup_priolist(engine, rq_prio(rq)));
+ defer_request(rq, i915_sched_lookup_priolist(engine->sched_engine,
+rq_prio(rq)));
}
static bool
@@ -2083,7 +2085,7 @@ static void __execlists_unhold(struct i915_request *rq)
i915_request_clear_hold(rq);
list_move_tail(&rq->sched.link,
- i915_sched_lookup_priolist(rq->engine,
+
i915_sched_lookup_priolist(rq->engine->sched_engine,
rq_prio(rq)));
set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
@@ -2452,7 +2454,8 @@ static void queue_request(struct intel_engine_cs *engine,
{
GEM_BUG_ON(!list_empty(&rq->sched.link));
list_add_tail(&rq->sched.link,
- i915_sched_lookup_priolist(engine, rq_prio(rq)));
+ i915_sched_lookup_priolist(engine->sched_engine,
+rq_prio(rq)));
set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 4c5bbec0775d..7ed21670ef14 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -529,7 +529,7 @@ static inline void queue_request(struct intel_engine_cs
*engine,
{
GEM_BUG_ON(!list_empty(&rq->sched.link));
list_add_tail(&rq->sched.link,
- i915_sched_lookup_priolist(engine, prio));
+ i915_sched_lookup_priolist(engine->sched_engine, prio));
set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
}
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 035b88f2e4aa..3d36e4447b5d 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -61,14 +61,13 @@ static void assert_priolists(struct i915_sched_engine *
const sched_engine)
}
struct list_head *
-i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio)
+i915_sched_lookup_priolist(struct i915_sched_engine *sched_engine, int prio)
{
- struct i915_sched_engine * const sched_engine = engine->sched_engine;
struct i915_priolist *p;
struct rb_node **parent, *rb;
bool first = true;
- lockdep_assert_held(&engine->sched_engine->lock);
+ lockdep_assert_held(&sched_engine->lock);
assert_priolists(sched_engine);
if (unlikely(sched_engine->no_priolist))
@@ -130,13 +129,13 @@ struct sched_cache {
struct list_head *priolist;
};
-static struct intel_engine_cs *
-sched_lock_engine(const struct i915_sched_node *node,
- struct intel_engine_cs *locked,
+static struct i915_sched_engine *
+lock_sched_engine(struct i915_sched_node *node,
+ struct i915_sched_engine *locked,
struct sched_cache *cache)
{
const struct i915_request *rq = node_to_request(node);
- struct intel_engine_cs *engine;
+ struct i915_sched_engine *sched_engine;
GEM_BUG_ON(!locked);
@@ -146,14 +145,14 @@ sched_lock_engine(const struct i915_sched_node *node,
* engine lock. The simple ploy we use is to take the lock then
* check that the rq still belongs to the newly locked engine.
*/
- while (locked != (engine = READ_ONCE(rq->engine))) {
- spin_unlock(&locked->sched_engine->lock);
+ whil
[Intel-gfx] [PATCH 1/9] drm/i915: Move priolist to new i915_sched_engine object
Introduce i915_sched_engine object which is lower level data structure
that i915_scheduler / generic code can operate on without touching
execlist specific structures. This allows additional submission backends
to be added without breaking the layering.
This is a bit of detour to integrating the i915 with the DRM scheduler
but this object will still exist when the DRM scheduler lands in the
i915. It will however look a bit different. It will encapsulate the
drm_gpu_scheduler object plus and common variables (to the backends)
related to scheduling. Regardless this is a step in the right direction.
This patch starts the aforementioned transition by moving the the
priolist into the i915_sched_engine object.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 14 +++-
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 4 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 30 +--
.../drm/i915/gt/intel_execlists_submission.c | 81 +++
drivers/gpu/drm/i915/gt/mock_engine.c | 9 ++-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 19 ++---
drivers/gpu/drm/i915/i915_scheduler.c | 51 +---
drivers/gpu/drm/i915/i915_scheduler.h | 18 +
drivers/gpu/drm/i915/i915_scheduler_types.h | 33
9 files changed, 169 insertions(+), 90 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3f9a811eb02b..d0f3814440f6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -583,9 +583,6 @@ void intel_engine_init_execlists(struct intel_engine_cs
*engine)
memset(execlists->pending, 0, sizeof(execlists->pending));
execlists->active =
memset(execlists->inflight, 0, sizeof(execlists->inflight));
-
- execlists->queue_priority_hint = INT_MIN;
- execlists->queue = RB_ROOT_CACHED;
}
static void cleanup_status_page(struct intel_engine_cs *engine)
@@ -712,6 +709,12 @@ static int engine_setup_common(struct intel_engine_cs
*engine)
goto err_status;
}
+ engine->sched_engine = i915_sched_engine_create(ENGINE_PHYSICAL);
+ if (!engine->sched_engine) {
+ err = -ENOMEM;
+ goto err_sched_engine;
+ }
+
err = intel_engine_init_cmd_parser(engine);
if (err)
goto err_cmd_parser;
@@ -735,6 +738,8 @@ static int engine_setup_common(struct intel_engine_cs
*engine)
return 0;
err_cmd_parser:
+ i915_sched_engine_put(engine->sched_engine);
+err_sched_engine:
intel_breadcrumbs_free(engine->breadcrumbs);
err_status:
cleanup_status_page(engine);
@@ -958,6 +963,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
GEM_BUG_ON(!list_empty(&engine->active.requests));
tasklet_kill(&engine->execlists.tasklet); /* flush the callback */
+ i915_sched_engine_put(engine->sched_engine);
intel_breadcrumbs_free(engine->breadcrumbs);
intel_engine_fini_retire(engine);
@@ -1281,7 +1287,7 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
intel_engine_flush_submission(engine);
/* ELSP is empty, but there are ready requests? E.g. after reset */
- if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root))
+ if (!RB_EMPTY_ROOT(&engine->sched_engine->queue.rb_root))
return false;
/* Ring stopped? */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 47f4397095e5..b6a00dd72808 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -275,12 +275,12 @@ static int __engine_park(struct intel_wakeref *wf)
intel_breadcrumbs_park(engine->breadcrumbs);
/* Must be reset upon idling, or we may miss the busy wakeup. */
- GEM_BUG_ON(engine->execlists.queue_priority_hint != INT_MIN);
+ GEM_BUG_ON(engine->sched_engine->queue_priority_hint != INT_MIN);
if (engine->park)
engine->park(engine);
- engine->execlists.no_priolist = false;
+ engine->sched_engine->no_priolist = false;
/* While gt calls i915_vma_parked(), we have to break the lock cycle */
intel_gt_pm_put_async(engine->gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 9ef349cd5cea..86b41ddec373 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -59,6 +59,7 @@ struct drm_i915_reg_table;
struct i915_gem_context;
struct i915_request;
struct i915_sched_attr;
+struct i915_sched_engine;
struct intel_gt;
struct intel_ring;
struct intel_uncore;
@@ -152,11 +153,6 @@ struct intel_engine_execlists {
*/
struct timer_list preempt;
- /**
-* @default_priolist: priority list for I915_PRIORITY_NO
[Intel-gfx] [PATCH 0/9] Introduce i915_sched_engine object
As discussed in [1] we are breaking that large series into a several smaller ones. This series is stand alone patch part of step #4 which has no other dependencies or patches relevant to it. v2: (Daniel Vetter): - Split into several smaller patches - Add kernel doc for i915_sched_engine (Matthew Brost): - Drop wrapper functions for tasklet as eventually tasklet will be dropped Signed-off-by: Matthew Brost [1] https://patchwork.freedesktop.org/series/89844/ Matthew Brost (9): drm/i915: Move priolist to new i915_sched_engine object drm/i915: Add i915_sched_engine_is_empty function drm/i915: Add i915_sched_engine_reset_on_empty function drm/i915: Move active tracking to i915_sched_engine drm/i915: Move engine->schedule to i915_sched_engine drm/i915: Add kick_backend function to i915_sched_engine drm/i915: Update i915_scheduler to operate on i915_sched_engine drm/i915: Move submission tasklet to i915_sched_engine drm/i915/doc: Add kernel doc for i915_sched_engine Documentation/gpu/i915.rst| 6 + drivers/gpu/drm/i915/gem/i915_gem_wait.c | 4 +- drivers/gpu/drm/i915/gt/intel_engine.h| 16 - drivers/gpu/drm/i915/gt/intel_engine_cs.c | 72 ++-- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 4 +- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 4 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 47 +-- drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +- .../drm/i915/gt/intel_execlists_submission.c | 323 +++--- .../gpu/drm/i915/gt/intel_ring_submission.c | 12 +- drivers/gpu/drm/i915/gt/mock_engine.c | 17 +- drivers/gpu/drm/i915/gt/selftest_execlists.c | 36 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 6 +- drivers/gpu/drm/i915/gt/selftest_lrc.c| 6 +- drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 70 ++-- drivers/gpu/drm/i915/i915_gpu_error.c | 4 +- drivers/gpu/drm/i915/i915_request.c | 42 +-- drivers/gpu/drm/i915/i915_request.h | 2 +- drivers/gpu/drm/i915/i915_scheduler.c | 168 + drivers/gpu/drm/i915/i915_scheduler.h | 47 ++- drivers/gpu/drm/i915/i915_scheduler_types.h | 89 + 22 files changed, 554 insertions(+), 425 deletions(-) -- 2.28.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/vgem: use shmem helpers
Aside from deleting lots of code the real motivation here is to switch
the mmap over to VM_PFNMAP, to be more consistent with what real gpu
drivers do. They're all VM_PFNMP, which means get_user_pages doesn't
work, and even if you try and there's a struct page behind that,
touching it and mucking around with its refcount can upset drivers
real bad.
v2: Review from Thomas:
- sort #include
- drop more dead code that I didn't spot somehow
v3: select DRM_GEM_SHMEM_HELPER to make it build (intel-gfx-ci)
v4: I got tricked by 0cf2ef46c6c0 ("drm/shmem-helper: Use cached
mappings by default"), and we need WC in vgem because vgem doesn't
have explicit begin/end cpu access ioctls.
Also add a comment why exactly vgem has to use wc.
v5: Don't set obj->base.funcs, it will default to drm_gem_shmem_funcs
(Thomas)
v6: vgem also needs an MMU for remapping
Cc: Thomas Zimmermann
Acked-by: Thomas Zimmermann
Cc: John Stultz
Cc: Sumit Semwal
Cc: "Christian König"
Signed-off-by: Daniel Vetter
Cc: Melissa Wen
Cc: Chris Wilson
---
drivers/gpu/drm/Kconfig | 5 +-
drivers/gpu/drm/vgem/vgem_drv.c | 342 ++--
2 files changed, 16 insertions(+), 331 deletions(-)
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 9c21527b791f..1b785ec4b80a 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -267,7 +267,8 @@ source "drivers/gpu/drm/kmb/Kconfig"
config DRM_VGEM
tristate "Virtual GEM provider"
- depends on DRM
+ depends on DRM && MMU
+ select DRM_GEM_SHMEM_HELPER
help
Choose this option to get a virtual graphics memory manager,
as used by Mesa's software renderer for enhanced performance.
@@ -275,7 +276,7 @@ config DRM_VGEM
config DRM_VKMS
tristate "Virtual KMS (EXPERIMENTAL)"
- depends on DRM
+ depends on DRM && MMU
select DRM_KMS_HELPER
select DRM_GEM_SHMEM_HELPER
select CRC32
diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c
index bf38a7e319d1..a87eafa89e9f 100644
--- a/drivers/gpu/drm/vgem/vgem_drv.c
+++ b/drivers/gpu/drm/vgem/vgem_drv.c
@@ -38,6 +38,7 @@
#include
#include
+#include
#include
#include
#include
@@ -50,87 +51,11 @@
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 0
-static const struct drm_gem_object_funcs vgem_gem_object_funcs;
-
static struct vgem_device {
struct drm_device drm;
struct platform_device *platform;
} *vgem_device;
-static void vgem_gem_free_object(struct drm_gem_object *obj)
-{
- struct drm_vgem_gem_object *vgem_obj = to_vgem_bo(obj);
-
- kvfree(vgem_obj->pages);
- mutex_destroy(&vgem_obj->pages_lock);
-
- if (obj->import_attach)
- drm_prime_gem_destroy(obj, vgem_obj->table);
-
- drm_gem_object_release(obj);
- kfree(vgem_obj);
-}
-
-static vm_fault_t vgem_gem_fault(struct vm_fault *vmf)
-{
- struct vm_area_struct *vma = vmf->vma;
- struct drm_vgem_gem_object *obj = vma->vm_private_data;
- /* We don't use vmf->pgoff since that has the fake offset */
- unsigned long vaddr = vmf->address;
- vm_fault_t ret = VM_FAULT_SIGBUS;
- loff_t num_pages;
- pgoff_t page_offset;
- page_offset = (vaddr - vma->vm_start) >> PAGE_SHIFT;
-
- num_pages = DIV_ROUND_UP(obj->base.size, PAGE_SIZE);
-
- if (page_offset >= num_pages)
- return VM_FAULT_SIGBUS;
-
- mutex_lock(&obj->pages_lock);
- if (obj->pages) {
- get_page(obj->pages[page_offset]);
- vmf->page = obj->pages[page_offset];
- ret = 0;
- }
- mutex_unlock(&obj->pages_lock);
- if (ret) {
- struct page *page;
-
- page = shmem_read_mapping_page(
- file_inode(obj->base.filp)->i_mapping,
- page_offset);
- if (!IS_ERR(page)) {
- vmf->page = page;
- ret = 0;
- } else switch (PTR_ERR(page)) {
- case -ENOSPC:
- case -ENOMEM:
- ret = VM_FAULT_OOM;
- break;
- case -EBUSY:
- ret = VM_FAULT_RETRY;
- break;
- case -EFAULT:
- case -EINVAL:
- ret = VM_FAULT_SIGBUS;
- break;
- default:
- WARN_ON(PTR_ERR(page));
- ret = VM_FAULT_SIGBUS;
- break;
- }
-
- }
- return ret;
-}
-
-static const struct vm_operations_struct vgem_gem_vm_ops = {
- .fault = vgem_gem_fault,
- .open = drm_gem_vm_open,
- .close = drm_gem_vm_close,
-};
-
static int v
[Intel-gfx] [PATCH] drm/shmem-helper: Switch to vmf_insert_pfn
We want to stop gup, which isn't the case if we use vmf_insert_page
and VM_MIXEDMAP, because that does not set pte_special.
v2: With this shmem gem helpers now definitely need CONFIG_MMU (0day)
v3: add more depends on MMU. For usb drivers this is a bit awkward,
but really it's correct: To be able to provide a contig mapping of
buffers to userspace on !MMU platforms we'd need to use the cma
helpers for these drivers on those platforms. As-is this wont work.
Also not exactly sure why vm_insert_page doesn't go boom, because that
definitely wont fly in practice since the pages are non-contig to
begin with.
Signed-off-by: Daniel Vetter
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
---
drivers/gpu/drm/Kconfig| 2 +-
drivers/gpu/drm/drm_gem_shmem_helper.c | 4 ++--
drivers/gpu/drm/gud/Kconfig| 2 +-
drivers/gpu/drm/tiny/Kconfig | 4 ++--
drivers/gpu/drm/udl/Kconfig| 1 +
5 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 56a55a6e6239..9c21527b791f 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -206,7 +206,7 @@ config DRM_KMS_CMA_HELPER
config DRM_GEM_SHMEM_HELPER
bool
- depends on DRM
+ depends on DRM && MMU
help
Choose this if you need the GEM shmem helper functions
diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c
b/drivers/gpu/drm/drm_gem_shmem_helper.c
index 6d625cee7a6a..11edd54f0580 100644
--- a/drivers/gpu/drm/drm_gem_shmem_helper.c
+++ b/drivers/gpu/drm/drm_gem_shmem_helper.c
@@ -542,7 +542,7 @@ static vm_fault_t drm_gem_shmem_fault(struct vm_fault *vmf)
} else {
page = shmem->pages[page_offset];
- ret = vmf_insert_page(vma, vmf->address, page);
+ ret = vmf_insert_pfn(vma, vmf->address, page_to_pfn(page));
}
mutex_unlock(&shmem->pages_lock);
@@ -612,7 +612,7 @@ int drm_gem_shmem_mmap(struct drm_gem_object *obj, struct
vm_area_struct *vma)
return ret;
}
- vma->vm_flags |= VM_MIXEDMAP | VM_DONTEXPAND;
+ vma->vm_flags |= VM_PFNMAP | VM_DONTEXPAND;
vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
if (shmem->map_wc)
vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
diff --git a/drivers/gpu/drm/gud/Kconfig b/drivers/gpu/drm/gud/Kconfig
index 1c8601bf4d91..9c1e61f9eec3 100644
--- a/drivers/gpu/drm/gud/Kconfig
+++ b/drivers/gpu/drm/gud/Kconfig
@@ -2,7 +2,7 @@
config DRM_GUD
tristate "GUD USB Display"
- depends on DRM && USB
+ depends on DRM && USB && MMU
select LZ4_COMPRESS
select DRM_KMS_HELPER
select DRM_GEM_SHMEM_HELPER
diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig
index d46f95d9196d..a15f57ace9e7 100644
--- a/drivers/gpu/drm/tiny/Kconfig
+++ b/drivers/gpu/drm/tiny/Kconfig
@@ -31,7 +31,7 @@ config DRM_CIRRUS_QEMU
config DRM_GM12U320
tristate "GM12U320 driver for USB projectors"
- depends on DRM && USB
+ depends on DRM && USB && MMU
select DRM_KMS_HELPER
select DRM_GEM_SHMEM_HELPER
help
@@ -40,7 +40,7 @@ config DRM_GM12U320
config DRM_SIMPLEDRM
tristate "Simple framebuffer driver"
- depends on DRM
+ depends on DRM && MMU
select DRM_GEM_SHMEM_HELPER
select DRM_KMS_HELPER
help
diff --git a/drivers/gpu/drm/udl/Kconfig b/drivers/gpu/drm/udl/Kconfig
index 1f497d8f1ae5..c744175c6992 100644
--- a/drivers/gpu/drm/udl/Kconfig
+++ b/drivers/gpu/drm/udl/Kconfig
@@ -4,6 +4,7 @@ config DRM_UDL
depends on DRM
depends on USB
depends on USB_ARCH_HAS_HCD
+ depends on MMU
select DRM_GEM_SHMEM_HELPER
select DRM_KMS_HELPER
help
--
2.31.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for Use platform specific defaults for GuC/HuC enabling
== Series Details == Series: Use platform specific defaults for GuC/HuC enabling URL : https://patchwork.freedesktop.org/series/90956/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10166_full -> Patchwork_20275_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20275_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20275_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20275_full: ### IGT changes ### Possible regressions * igt@kms_flip@flip-vs-suspend@b-vga1: - shard-snb: NOTRUN -> [DMESG-WARN][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/shard-snb2/igt@kms_flip@flip-vs-susp...@b-vga1.html * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes: - shard-skl: [PASS][2] -> [INCOMPLETE][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/shard-skl8/igt@kms_plane@plane-panning-bottom-right-susp...@pipe-b-planes.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/shard-skl2/igt@kms_plane@plane-panning-bottom-right-susp...@pipe-b-planes.html Known issues Here are the changes found in Patchwork_20275_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-clear: - shard-glk: [PASS][4] -> [FAIL][5] ([i915#1888] / [i915#3160]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/shard-glk7/igt@gem_cre...@create-clear.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/shard-glk5/igt@gem_cre...@create-clear.html * igt@gem_ctx_persistence@smoketest: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +7 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/shard-snb6/igt@gem_ctx_persiste...@smoketest.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][7] ([i915#3354]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/shard-snb7/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2846]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/shard-kbl2/igt@gem_exec_f...@basic-deadline.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/shard-kbl1/igt@gem_exec_f...@basic-deadline.html - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2846]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/shard-glk7/igt@gem_exec_f...@basic-deadline.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/shard-glk6/igt@gem_exec_f...@basic-deadline.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][12] ([i915#2658]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/shard-apl2/igt@gem_pr...@exhaustion.html * igt@gem_userptr_blits@input-checking: - shard-snb: NOTRUN -> [DMESG-WARN][13] ([i915#3002]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/shard-snb6/igt@gem_userptr_bl...@input-checking.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][14] -> [FAIL][15] ([i915#454]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/shard-iclb2/igt@i915_pm...@dc6-psr.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/shard-iclb6/igt@i915_pm...@dc6-psr.html * igt@kms_big_joiner@basic: - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#2705]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/shard-kbl7/igt@kms_big_joi...@basic.html * igt@kms_ccs@pipe-a-ccs-on-another-bo: - shard-snb: NOTRUN -> [SKIP][17] ([fdo#109271]) +583 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/shard-snb5/igt@kms_...@pipe-a-ccs-on-another-bo.html * igt@kms_chamelium@dp-mode-timings: - shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +11 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/shard-apl1/igt@kms_chamel...@dp-mode-timings.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-snb: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +27 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/shard-snb6/igt@kms_color_chamel...@pipe-a-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-b-ctm-0-25: - shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +9 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/shard-kbl7/igt@k
Re: [Intel-gfx] [PATCH v2 2/4] drm/shmem-helper: Switch to vmf_insert_pfn
Hi Daniel, I love your patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master v5.13-rc4 next-20210603] [cannot apply to drm/drm-next] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Daniel-Vetter/shmem-helpers-for-igt/20210603-230602 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: h8300-randconfig-r021-20210603 (attached as .config) compiler: h8300-linux-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/5ce1f8f44bf2a1a96bb1a56ef34453d958142b45 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Daniel-Vetter/shmem-helpers-for-igt/20210603-230602 git checkout 5ce1f8f44bf2a1a96bb1a56ef34453d958142b45 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=h8300 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): h8300-linux-ld: section .init.text LMA [0059b760,005de3d5] overlaps section .text LMA [0158,0171c08b] h8300-linux-ld: section .data VMA [0040,0059b75f] overlaps section .text VMA [0158,0171c08b] h8300-linux-ld: drivers/gpu/drm/drm_gem_shmem_helper.o: in function `.Llt5': >> drm_gem_shmem_helper.c:(.text+0x16f): undefined reference to `vmf_insert_pfn' Kconfig warnings: (for reference only) WARNING: unmet direct dependencies detected for DRM_GEM_SHMEM_HELPER Depends on HAS_IOMEM && DRM && MMU Selected by - DRM_VKMS && HAS_IOMEM && DRM - DRM_UDL && HAS_IOMEM && DRM && USB && USB_ARCH_HAS_HCD - DRM_GM12U320 && HAS_IOMEM && DRM && USB --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org .config.gz Description: application/gzip ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Finish conversion to GRAPHICS_VER
== Series Details ==
Series: drm/i915: Finish conversion to GRAPHICS_VER
URL : https://patchwork.freedesktop.org/series/90964/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10166 -> Patchwork_20277
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_20277:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@prime_self_import@basic-with_two_bos:
- {fi-rkl-11500t}:NOTRUN -> [FAIL][1] +5 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/fi-rkl-11500t/igt@prime_self_import@basic-with_two_bos.html
* igt@prime_vgem@basic-fence-flip:
- {fi-rkl-11500t}:NOTRUN -> [SKIP][2] +11 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/fi-rkl-11500t/igt@prime_v...@basic-fence-flip.html
Known issues
Here are the changes found in Patchwork_20277 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][4] ([i915#2782]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
Warnings
* igt@i915_selftest@live@execlists:
- fi-cml-s: [DMESG-FAIL][6] ([i915#3462]) -> [INCOMPLETE][7]
([i915#3462])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-cml-s/igt@i915_selftest@l...@execlists.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/fi-cml-s/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-kbl-7500u: [FAIL][8] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][9] ([i915#1436] / [i915#3363])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-kbl-7500u/igt@run...@aborted.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/fi-kbl-7500u/igt@run...@aborted.html
- fi-cfl-guc: [FAIL][10] ([i915#3363]) -> [FAIL][11] ([i915#2426] /
[i915#3363])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-cfl-guc/igt@run...@aborted.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/fi-cfl-guc/igt@run...@aborted.html
- fi-skl-6700k2: [FAIL][12] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][13] ([i915#1436] / [i915#3363])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-skl-6700k2/igt@run...@aborted.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20277/fi-skl-6700k2/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3276]: https://gitlab.freedesktop.org/drm/intel/issues/3276
[i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#3542]: https://gitlab.freedesktop.org/drm/intel/issues/3542
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (45 -> 42)
--
Additional (1): fi-rkl-11500t
Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_10166 -> Patchwork_20277
CI-20190529: 20190529
CI_DRM_10166: 3fd
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Finish conversion to GRAPHICS_VER
== Series Details == Series: drm/i915: Finish conversion to GRAPHICS_VER URL : https://patchwork.freedesktop.org/series/90964/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1893:21:expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1893:21:got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1893:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1207:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Finish conversion to GRAPHICS_VER
== Series Details == Series: drm/i915: Finish conversion to GRAPHICS_VER URL : https://patchwork.freedesktop.org/series/90964/ State : warning == Summary == $ dim checkpatch origin/drm-tip dd73d7c8a448 drm/i915/gt: replace IS_GEN and friends with GRAPHICS_VER -:2330: WARNING:LONG_LINE: line length of 112 exceeds 100 columns #2330: FILE: drivers/gpu/drm/i915/gt/selftest_llc.c:47: + intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)), -:2339: WARNING:LONG_LINE: line length of 112 exceeds 100 columns #2339: FILE: drivers/gpu/drm/i915/gt/selftest_llc.c:57: + intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)), total: 0 errors, 2 warnings, 0 checks, 2260 lines checked ca3d76d381f1 drm/i915/gt: Add remaining conversions to GRAPHICS_VER 6cdb4e8cf7a6 drm/i915/gem: replace IS_GEN and friends with GRAPHICS_VER 9840a7aa1c31 drm/i915/gvt: replace IS_GEN and friends with GRAPHICS_VER 3d259936ef90 drm/i915: replace IS_GEN and friends with GRAPHICS_VER -:154: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #154: FILE: drivers/gpu/drm/i915/i915_debugfs.c:500: + (gt_perf_status & (GRAPHICS_VER(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8); total: 0 errors, 1 warnings, 0 checks, 1352 lines checked c8eebfaafb64 drm/i915: Add remaining conversions to GRAPHICS_VER -:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #24: FILE: drivers/gpu/drm/i915/i915_drv.h:1556: +#define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv)) -:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #25: FILE: drivers/gpu/drm/i915/i915_drv.h:1557: +#define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv)) -:60: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #60: FILE: drivers/gpu/drm/i915/i915_drv.h:1624: +#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \ IS_GEMINILAKE(dev_priv) || \ IS_KABYLAKE(dev_priv)) -:70: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #70: FILE: drivers/gpu/drm/i915/i915_drv.h:1631: +#define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \ +!(IS_I915G(dev_priv) || IS_I915GM(dev_priv))) -:79: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #79: FILE: drivers/gpu/drm/i915/i915_drv.h:1638: +#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7) total: 0 errors, 0 warnings, 5 checks, 215 lines checked 35e37380eaa4 drm/i915/display: replace IS_GEN() in commented code ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for shmem helpers for vgem (rev3)
== Series Details ==
Series: shmem helpers for vgem (rev3)
URL : https://patchwork.freedesktop.org/series/90670/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10166 -> Patchwork_20276
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20276 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20276, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20276/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_20276:
### IGT changes ###
Possible regressions
* igt@prime_vgem@basic-fence-mmap:
- fi-elk-e7500: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-elk-e7500/igt@prime_v...@basic-fence-mmap.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20276/fi-elk-e7500/igt@prime_v...@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- fi-bsw-kefka: [PASS][3] -> [INCOMPLETE][4] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20276/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html
- fi-ilk-650: [PASS][5] -> [INCOMPLETE][6] +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-ilk-650/igt@prime_v...@basic-fence-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20276/fi-ilk-650/igt@prime_v...@basic-fence-read.html
- fi-bwr-2160:[PASS][7] -> [INCOMPLETE][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-bwr-2160/igt@prime_v...@basic-fence-read.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20276/fi-bwr-2160/igt@prime_v...@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- fi-ilk-650: [PASS][9] -> [FAIL][10] +2 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-ilk-650/igt@prime_v...@basic-gtt.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20276/fi-ilk-650/igt@prime_v...@basic-gtt.html
- fi-elk-e7500: [PASS][11] -> [FAIL][12] +3 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-elk-e7500/igt@prime_v...@basic-gtt.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20276/fi-elk-e7500/igt@prime_v...@basic-gtt.html
* igt@prime_vgem@basic-read:
- fi-bwr-2160:[PASS][13] -> [FAIL][14] +3 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-bwr-2160/igt@prime_v...@basic-read.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20276/fi-bwr-2160/igt@prime_v...@basic-read.html
- fi-bsw-kefka: [PASS][15] -> [FAIL][16] +2 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-bsw-kefka/igt@prime_v...@basic-read.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20276/fi-bsw-kefka/igt@prime_v...@basic-read.html
* igt@prime_vgem@basic-write:
- fi-pnv-d510:[PASS][17] -> [FAIL][18] +4 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-pnv-d510/igt@prime_v...@basic-write.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20276/fi-pnv-d510/igt@prime_v...@basic-write.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@prime_self_import@basic-with_two_bos:
- {fi-rkl-11500t}:NOTRUN -> [FAIL][19] +5 similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20276/fi-rkl-11500t/igt@prime_self_import@basic-with_two_bos.html
* igt@prime_vgem@basic-fence-flip:
- {fi-rkl-11500t}:NOTRUN -> [SKIP][20] +11 similar issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20276/fi-rkl-11500t/igt@prime_v...@basic-fence-flip.html
Known issues
Here are the changes found in Patchwork_20276 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gt_heartbeat:
- fi-cml-s: [PASS][21] -> [DMESG-FAIL][22] ([i915#2291] /
[i915#541])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-cml-s/igt@i915_selftest@live@gt_heartbeat.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20276/fi-cml-s/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [PASS][23] -> [DMESG-WARN][24] ([i915#2203] /
[i915#2868])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[24]:
Re: [Intel-gfx] [PATCH] drm/i915: Add relocation exceptions for two other platforms
On Wed, Jun 2, 2021 at 12:25 AM Zbigniew Kempczyński
wrote:
>
> We have established previously we stop using relocations starting
> from gen12 platforms with Tigerlake as an exception. We keep this
> statement but we want to enable relocations conditionally for
> Rocketlake and Alderlake under require_force_probe flag set.
>
> Keeping relocations under require_force_probe flag is interim solution
> until IGTs will be rewritten to use softpin.
>
> v2: - remove inline from function definition (Jani)
> - fix indentation
>
> Signed-off-by: Zbigniew Kempczyński
> Cc: Dave Airlie
> Cc: Daniel Vetter
> Cc: Jason Ekstrand
Acked-by: Dave Airlie
> ---
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 24 +++
> 1 file changed, 19 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 297143511f99..78b86a7bc39a 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -491,16 +491,30 @@ eb_unreserve_vma(struct eb_vma *ev)
> ev->flags &= ~__EXEC_OBJECT_RESERVED;
> }
>
> +static bool platform_has_relocs_enabled(const struct i915_execbuffer *eb)
> +{
> + /*
> +* Relocations are disallowed starting from gen12 with Tigerlake
> +* as an exception. We allow temporarily use relocations for
> Rocketlake
> +* and Alderlake when require_force_probe flag is set.
> +*/
> + if (INTEL_GEN(eb->i915) < 12 || IS_TIGERLAKE(eb->i915))
> + return true;
> +
> + if (INTEL_INFO(eb->i915)->require_force_probe &&
> + (IS_ROCKETLAKE(eb->i915) || IS_ALDERLAKE_S(eb->i915) ||
> +IS_ALDERLAKE_P(eb->i915)))
> + return true;
> +
> + return false;
> +}
> +
> static int
> eb_validate_vma(struct i915_execbuffer *eb,
> struct drm_i915_gem_exec_object2 *entry,
> struct i915_vma *vma)
> {
> - /* Relocations are disallowed for all platforms after TGL-LP. This
> -* also covers all platforms with local memory.
> -*/
> - if (entry->relocation_count &&
> - INTEL_GEN(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
> + if (entry->relocation_count && !platform_has_relocs_enabled(eb))
> return -EINVAL;
>
> if (unlikely(entry->flags & eb->invalid_flags))
> --
> 2.26.0
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for shmem helpers for vgem (rev3)
== Series Details ==
Series: shmem helpers for vgem (rev3)
URL : https://patchwork.freedesktop.org/series/90670/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c0a84d0fb311 dma-buf: Require VM_PFNMAP vma for mmap
-:34: WARNING:TYPO_SPELLING: 'entires' may be misspelled - perhaps 'entries'?
#34:
>From auditing the various functions to insert pfn pte entires
^^^
-:39: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#39:
References:
https://lore.kernel.org/lkml/cakmk7uhi+mg0z0humnt13qccvuturvjpcr0njrl12k-wbwz...@mail.gmail.com/
-:97: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by:
Daniel Vetter '
total: 0 errors, 3 warnings, 0 checks, 39 lines checked
d1d5656bffd9 drm/shmem-helper: Switch to vmf_insert_pfn
-:52: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by:
Daniel Vetter '
total: 0 errors, 1 warnings, 0 checks, 24 lines checked
97e33fae0aa0 drm/shmem-helper: Align to page size in dumb_create
-:37: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by:
Daniel Vetter '
total: 0 errors, 1 warnings, 0 checks, 15 lines checked
a813167b42cc drm/vgem: use shmem helpers
-:22: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 0cf2ef46c6c0 ("drm/shmem-helper:
Use cached mappings by default")'
#22:
v4: I got tricked by 0cf2ef46c6c0 ("drm/shmem-helper: Use cached
-:313: WARNING:TYPO_SPELLING: 'wont' may be misspelled - perhaps 'won't'?
#313: FILE: drivers/gpu/drm/vgem/vgem_drv.c:104:
+* coherent memory or dma-buf sharing just wont work.
-:444: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by:
Daniel Vetter '
total: 1 errors, 2 warnings, 0 checks, 392 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 3/4] drm/shmem-helper: Align to page size in dumb_create
Am 03.06.21 um 17:03 schrieb Daniel Vetter:
shmem helpers seem a bit sloppy here by automatically rounding up when
actually creating the buffer, which results in under-reporting of what
we actually have. Caught by igt/vgem_basic tests.
Acked-by: Thomas Zimmermann
Signed-off-by: Daniel Vetter
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
Acked-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_gem_shmem_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c
b/drivers/gpu/drm/drm_gem_shmem_helper.c
index 32f1d7601ec6..2985744b4300 100644
--- a/drivers/gpu/drm/drm_gem_shmem_helper.c
+++ b/drivers/gpu/drm/drm_gem_shmem_helper.c
@@ -506,13 +506,13 @@ int drm_gem_shmem_dumb_create(struct drm_file *file,
struct drm_device *dev,
if (!args->pitch || !args->size) {
args->pitch = min_pitch;
- args->size = args->pitch * args->height;
+ args->size = PAGE_ALIGN(args->pitch * args->height);
} else {
/* ensure sane minimum values */
if (args->pitch < min_pitch)
args->pitch = min_pitch;
if (args->size < args->pitch * args->height)
- args->size = args->pitch * args->height;
+ args->size = PAGE_ALIGN(args->pitch * args->height);
}
shmem = drm_gem_shmem_create_with_handle(file, dev, args->size, &args->handle);
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
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Re: [Intel-gfx] [PATCH v2 4/4] drm/vgem: use shmem helpers
On Thu, Jun 03, 2021 at 09:42:00PM +0300, Andi Shyti wrote:
> Hi Daniel,
>
> > +/*
> > + * This just sets wc mode for shmem helpers. vgem doesn't have any
> > begin/end cpu
> > + * access ioctls, there must use coherent memory or dma-buf sharing just
> > wont
> > + * work.
> > + */
> > +static struct drm_gem_object *vgem_gem_create_object(struct drm_device
> > *dev, size_t size)
> > {
> > - struct drm_vgem_gem_object *obj;
> > - int npages;
> > + struct drm_gem_shmem_object *obj;
> >
> > - obj = __vgem_gem_create(dev, attach->dmabuf->size);
> > - if (IS_ERR(obj))
> > - return ERR_CAST(obj);
> > -
> > - npages = PAGE_ALIGN(attach->dmabuf->size) / PAGE_SIZE;
> > + obj = kzalloc(sizeof(*obj), GFP_KERNEL);
> > + if (!obj)
> > + return NULL;
> >
> > - obj->table = sg;
> > - obj->pages = kvmalloc_array(npages, sizeof(struct page *), GFP_KERNEL);
> > - if (!obj->pages) {
> > - __vgem_gem_destroy(obj);
> > - return ERR_PTR(-ENOMEM);
> > - }
> > + obj->base.funcs = &drm_gem_shmem_funcs;
> > + obj->map_wc = true;
> >
> > - obj->pages_pin_count++; /* perma-pinned */
> > - drm_prime_sg_to_page_array(obj->table, obj->pages, npages);
> > return &obj->base;
>
> here you are allocating a bigger object than what you are
> returning, in size. How does it get freed?
We're using the drm_gem_shmem_helper.c helpers, which set up all the shmem
functions for us, including an appropriate free callback.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] ✓ Fi.CI.BAT: success for Use platform specific defaults for GuC/HuC enabling
== Series Details ==
Series: Use platform specific defaults for GuC/HuC enabling
URL : https://patchwork.freedesktop.org/series/90956/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10166 -> Patchwork_20275
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_20275:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@prime_self_import@basic-with_two_bos:
- {fi-rkl-11500t}:NOTRUN -> [FAIL][1] +5 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/fi-rkl-11500t/igt@prime_self_import@basic-with_two_bos.html
* igt@prime_vgem@basic-fence-flip:
- {fi-rkl-11500t}:NOTRUN -> [SKIP][2] +11 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/fi-rkl-11500t/igt@prime_v...@basic-fence-flip.html
Known issues
Here are the changes found in Patchwork_20275 that come from known issues:
### IGT changes ###
Warnings
* igt@runner@aborted:
- fi-cfl-8700k: [FAIL][3] ([i915#2426] / [i915#3363]) -> [FAIL][4]
([i915#3363])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-cfl-8700k/igt@run...@aborted.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/fi-cfl-8700k/igt@run...@aborted.html
- fi-skl-6600u: [FAIL][5] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][6] ([i915#1436] / [i915#3363])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-skl-6600u/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/fi-skl-6600u/igt@run...@aborted.html
- fi-glk-dsi: [FAIL][7] ([i915#2426] / [i915#3363] /
[k.org#202321]) -> [FAIL][8] ([i915#3363] / [k.org#202321])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-glk-dsi/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/fi-glk-dsi/igt@run...@aborted.html
- fi-bdw-5557u: [FAIL][9] ([i915#3462]) -> [FAIL][10] ([i915#1602] /
[i915#2029])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-bdw-5557u/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/fi-bdw-5557u/igt@run...@aborted.html
- fi-kbl-7500u: [FAIL][11] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][12] ([i915#1436] / [i915#3363])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-kbl-7500u/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/fi-kbl-7500u/igt@run...@aborted.html
- fi-cml-s: [FAIL][13] ([i915#3363] / [i915#3462]) -> [FAIL][14]
([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-cml-s/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/fi-cml-s/igt@run...@aborted.html
- fi-skl-6700k2: [FAIL][15] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][16] ([i915#1436] / [i915#3363])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10166/fi-skl-6700k2/igt@run...@aborted.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20275/fi-skl-6700k2/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3276]: https://gitlab.freedesktop.org/drm/intel/issues/3276
[i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel
Re: [Intel-gfx] [PATCH v2 4/4] drm/vgem: use shmem helpers
Hi Daniel,
> +/*
> + * This just sets wc mode for shmem helpers. vgem doesn't have any begin/end
> cpu
> + * access ioctls, there must use coherent memory or dma-buf sharing just wont
> + * work.
> + */
> +static struct drm_gem_object *vgem_gem_create_object(struct drm_device *dev,
> size_t size)
> {
> - struct drm_vgem_gem_object *obj;
> - int npages;
> + struct drm_gem_shmem_object *obj;
>
> - obj = __vgem_gem_create(dev, attach->dmabuf->size);
> - if (IS_ERR(obj))
> - return ERR_CAST(obj);
> -
> - npages = PAGE_ALIGN(attach->dmabuf->size) / PAGE_SIZE;
> + obj = kzalloc(sizeof(*obj), GFP_KERNEL);
> + if (!obj)
> + return NULL;
>
> - obj->table = sg;
> - obj->pages = kvmalloc_array(npages, sizeof(struct page *), GFP_KERNEL);
> - if (!obj->pages) {
> - __vgem_gem_destroy(obj);
> - return ERR_PTR(-ENOMEM);
> - }
> + obj->base.funcs = &drm_gem_shmem_funcs;
> + obj->map_wc = true;
>
> - obj->pages_pin_count++; /* perma-pinned */
> - drm_prime_sg_to_page_array(obj->table, obj->pages, npages);
> return &obj->base;
here you are allocating a bigger object than what you are
returning, in size. How does it get freed?
Andi
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Re: [Intel-gfx] [PATCH] drm/i915/dsc: Remove redundant checks in DSC disable
On Thu, Jun 03, 2021 at 08:37:22AM -0700, Kulkarni, Vandita wrote:
> > -Original Message-
> > From: Manna, Animesh
> > Sent: Thursday, June 3, 2021 7:24 PM
> > To: Kulkarni, Vandita ; Nikula, Jani
> > ; Saarinen, Jani ; intel-
> > g...@lists.freedesktop.org
> > Cc: Navare, Manasi D
> > Subject: RE: [Intel-gfx] [PATCH] drm/i915/dsc: Remove redundant checks in
> > DSC disable
> >
> >
> >
> > > -Original Message-
> > > From: Kulkarni, Vandita
> > > Sent: Thursday, June 3, 2021 4:55 PM
> > > To: Nikula, Jani ; Saarinen, Jani
> > > ; intel-gfx@lists.freedesktop.org
> > > Cc: Manna, Animesh ; Navare, Manasi D
> > >
> > > Subject: RE: [Intel-gfx] [PATCH] drm/i915/dsc: Remove redundant checks
> > > in DSC disable
> > >
> > > > -Original Message-
> > > > From: Nikula, Jani
> > > > Sent: Thursday, June 3, 2021 3:11 PM
> > > > To: Kulkarni, Vandita ; Saarinen, Jani
> > > > ; intel-gfx@lists.freedesktop.org
> > > > Cc: Manna, Animesh ; Navare, Manasi D
> > > >
> > > > Subject: RE: [Intel-gfx] [PATCH] drm/i915/dsc: Remove redundant
> > > > checks in DSC disable
> > > >
> > > > On Thu, 03 Jun 2021, "Kulkarni, Vandita"
> > > >
> > > > wrote:
> > > > >> -Original Message-
> > > > >> From: Saarinen, Jani
> > > > >> Sent: Thursday, June 3, 2021 1:07 PM
> > > > >> To: Kulkarni, Vandita ; intel-
> > > > >> g...@lists.freedesktop.org
> > > > >> Cc: Nikula, Jani
> > > > >> Subject: RE: [Intel-gfx] [PATCH] drm/i915/dsc: Remove redundant
> > > > >> checks in DSC disable
> > > > >>
> > > > >> Hi,
> > > > >> > -Original Message-
> > > > >> > From: Intel-gfx On
> > > > >> > Behalf Of Vandita Kulkarni
> > > > >> > Sent: torstai 3. kesäkuuta 2021 9.54
> > > > >> > To: intel-gfx@lists.freedesktop.org
> > > > >> > Cc: Nikula, Jani
> > > > >> > Subject: [Intel-gfx] [PATCH] drm/i915/dsc: Remove redundant
> > > > >> > checks in DSC disable
> > > > >> >
> > > > >> > There can be a chance that pre os has enabled DSC and driver's
> > > > >> > compute config would not need dsc to be enabled, in such case
> > > > >> > if we check on compute config's compression state to disable,
> > > > >> > we might end up in state
> > > > >> mismatch.
> > > > >>
> > > > >> I assume this fixes real gitlab issue too?
> > > > > Okay, will add the tag
> > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3537
> > > >
> > > > See https://lore.kernel.org/r/87fsxzp9qx@intel.com
> > > >
> > > > The problem is with ->bigjoiner, not the entire statement.
> > > Thanks for pointing this out, true that bigjoiner not being enabled
> > > will stop dsc disabling.
> > > The bigjoiner check was making the entire condition check unnecessary.
> > >
> > > Will update and refloat.
> >
> > Hi Jani/Vandita,
> >
> > For uncompressed bigjoiner case if we want to use the same function to
> > clear the dsc_ctrl1 register we may need to remove both the condition
> > check.
> > As for uncompressed bigjoiner case, compression_enable Will be 0 and will
> > block in clearing the dss_ctl1_reg.
>
> Yes, I was going through and found that bit 20 and 21 of dss_ctl1 are being
> used
> for uncompressed joiner.
> So when dsc is not enabled to avoid writing the register we could add
> below code .
>
> if (dsc)
> clear dss_ctl2
> if ( bigjoiner | dsc)
> clear dss_ctl1;
> return;
>
> bigjoiner = 1 and dsc = 0 - uncompressed , I think there is no harm in
> clearing dsc bits again
> bigjoiner = 1 and dsc = 1 - compressed - uncompressed bits are already 0
> bigjoiner = 0 and dsc= 1 - just dsc - clear dsc rest are 0s already
> bigjoiner = 0 and dsc = 0 do nothing, return
>
> If I have missed any corner case, please let me know.
>
> Thanks,
> Vandita
I think in the original code the condition was just reversed, instead it should
be :
if !(dsc_en || bigjoiner_en) {
write 0 to dss ctl 1
write 0 to dss ctl 2
}
So here basically it meets all the conditions you mentioned Vandita:
- only when both dsc and bigjoiner are 0, it will do nothing
- In all other cases DSC + Bigjoiner : Clear all bits including uncompressed
bits which shd be 0 already
- In dsc = 0, bigjoiner = 1 (uncompressed), it will clear both again which is
okay since dsc bits are already 0
Does this make sense?
Regards
Manasi
> >
> > Regards,
> > Animesh
> > >
> > > Thanks,
> > > Vandita
> > > >
> > > >
> > > > BR,
> > > > Jani.
> > > >
> > > > >
> > > > > Thanks,
> > > > > Vandita
> > > > >>
> > > > >> >
> > > > >> > Signed-off-by: Vandita Kulkarni
> > > > >> > ---
> > > > >> > drivers/gpu/drm/i915/display/intel_vdsc.c | 4
> > > > >> > 1 file changed, 4 deletions(-)
> > > > >> >
> > > > >> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > > >> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > > >> > index 19cd9531c115..b05a96011d93 100644
> > > > >> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > > >> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > > >> > @@ -1161,10 +1161,6 @@ void int
Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
On Thu, Jun 03, 2021 at 06:49:23AM -0700, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Jani Nikula
> > Sent: Thursday, June 3, 2021 6:03 PM
> > To: Roper, Matthew D ; intel-
> > g...@lists.freedesktop.org
> > Cc: Manna, Animesh ; Navare, Manasi D
> > ; Kulkarni, Vandita
> > Subject: Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit
> > changes
> > for uncompressed joiner
> >
> > On Thu, 03 Jun 2021, Jani Nikula wrote:
> > > On Fri, 14 May 2021, Matt Roper wrote:
> > >> From: Animesh Manna
> > >>
> > >> Respective bit for master or slave to be set for uncompressed
> > >> bigjoiner in dss_ctl1 register.
> > >
> > > I was looking at the changes here due to a static checker complaint,
> > > and I think there are a number of issues here. Some more serious than
> > > others, and some predate the patch.
> > >
> > > Comments inline.
> > >
> > >> Cc: Manasi Navare
> > >> Signed-off-by: Animesh Manna
> > >> Signed-off-by: Clinton Taylor
> > >> Signed-off-by: Matt Roper
> > >> Reviewed-by: Manasi Navare
> > >> ---
> > >> drivers/gpu/drm/i915/display/intel_display.c | 6 +++
> > >> drivers/gpu/drm/i915/display/intel_vdsc.c| 40 +++-
> > >> drivers/gpu/drm/i915/display/intel_vdsc.h| 2 +
> > >> drivers/gpu/drm/i915/i915_reg.h | 2 +
> > >> 4 files changed, 49 insertions(+), 1 deletion(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > >> b/drivers/gpu/drm/i915/display/intel_display.c
> > >> index b5fd721137d3..422b59ebf6dc 100644
> > >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> > >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > >> @@ -3411,6 +3411,7 @@ static void icl_ddi_bigjoiner_pre_enable(struct
> > intel_atomic_state *state,
> > >> const struct intel_crtc_state
> > *crtc_state) {
> > >> struct intel_crtc *master =
> > >> to_intel_crtc(crtc_state->uapi.crtc);
> > >> +struct drm_i915_private *dev_priv = to_i915(master->base.dev);
> > >> struct intel_crtc_state *master_crtc_state;
> > >> struct drm_connector_state *conn_state;
> > >> struct drm_connector *conn;
> > >> @@ -3444,6 +3445,9 @@ static void icl_ddi_bigjoiner_pre_enable(struct
> > intel_atomic_state *state,
> > >> /* and DSC on slave */
> > >> intel_dsc_enable(NULL, crtc_state);
> > >> }
> > >> +
> > >> +if (DISPLAY_VER(dev_priv) >= 13)
> >
> > I don't think we should add these checks here. Make sure the crtc_state
> > only has
> > the relevant stuff enabled if the platform supports it. Don't duplicate the
> > checks.
>
> Agree.
>
> >
> > >> +intel_uncompressed_joiner_enable(crtc_state);
> >
> > As this is always called after intel_dsc_enable(), I think it would make
> > sense to
> > move this within intel_dsc_enable().
>
> Agree.
@Jani I had asked to create a separate joiner enable since having an
uncompressed enable inside dsc_enable
just from the names makes it contradicting.
But sure may be with a comment before calling uncompressed_joiner_enable() it
can be just called from inside dsc enable()
And instead of checking the display ver there we just use this condition:
if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
intel_uncompressed_joiner_enable(crtc_state);
}
Since the atomic check ensures that only for ver >=13 is when we allow big
joiner and no DSC combination.
Animesh, Jani does that sound good?
Manasi
> >
> > >> }
> > >>
> > >> static void hsw_crtc_enable(struct intel_atomic_state *state, @@
> > >> -6250,6 +6254,8 @@ static bool hsw_get_pipe_config(struct intel_crtc
> > >> *crtc,
> > >> }
> > >>
> > >> intel_dsc_get_config(pipe_config);
> > >> +if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config-
> > >dsc.compression_enable)
> > >> +intel_uncompressed_joiner_get_config(pipe_config);
> >
> > As this is always called after intel_dsc_get_config(), I think it would
> > make sense
> > to move this within intel_dsc_get_config.
> >
> > >>
> > >> if (!active) {
> > >> /* bigjoiner slave doesn't enable transcoder */ diff
> > >> --git
> > >> a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > >> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > >> index adcd6752f919..efc3184d8315 100644
> > >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > >> @@ -1021,6 +1021,22 @@ static i915_reg_t dss_ctl2_reg(const struct
> > intel_crtc_state *crtc_state)
> > >> return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) :
> > >> DSS_CTL2; }
> > >>
> > >> +void intel_uncompressed_joiner_enable(const struct intel_crtc_state
> > >> +*crtc_state)
> > >
> > > Naming. Basically for any new function, the function name prefix
> > > should match the file name. intel_vdsc.[ch] should have functions
> > > prefi
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Get rid of fence error propagation (rev2)
== Series Details == Series: drm/i915: Get rid of fence error propagation (rev2) URL : https://patchwork.freedesktop.org/series/90891/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10165_full -> Patchwork_20274_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20274_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20274_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20274_full: ### IGT changes ### Possible regressions * igt@gem_exec_reloc@basic-spin@bcs0: - shard-kbl: [PASS][1] -> [FAIL][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/shard-kbl4/igt@gem_exec_reloc@basic-s...@bcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/shard-kbl1/igt@gem_exec_reloc@basic-s...@bcs0.html - shard-apl: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/shard-apl7/igt@gem_exec_reloc@basic-s...@bcs0.html * igt@gem_exec_schedule@deep@bcs0: - shard-skl: [PASS][4] -> [FAIL][5] +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/shard-skl5/igt@gem_exec_schedule@d...@bcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/shard-skl4/igt@gem_exec_schedule@d...@bcs0.html - shard-glk: [PASS][6] -> [FAIL][7] +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/shard-glk2/igt@gem_exec_schedule@d...@bcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/shard-glk5/igt@gem_exec_schedule@d...@bcs0.html - shard-apl: [PASS][8] -> [FAIL][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/shard-apl3/igt@gem_exec_schedule@d...@bcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/shard-apl6/igt@gem_exec_schedule@d...@bcs0.html * igt@kms_big_fb@linear-16bpp-rotate-180: - shard-iclb: [PASS][10] -> [FAIL][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/shard-iclb7/igt@kms_big...@linear-16bpp-rotate-180.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/shard-iclb2/igt@kms_big...@linear-16bpp-rotate-180.html Known issues Here are the changes found in Patchwork_20274_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-clear: - shard-glk: [PASS][12] -> [FAIL][13] ([i915#3160]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/shard-glk2/igt@gem_cre...@create-clear.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/shard-glk8/igt@gem_cre...@create-clear.html * igt@gem_create@create-massive: - shard-apl: NOTRUN -> [DMESG-WARN][14] ([i915#3002]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/shard-apl3/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-cleanup: - shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#1099]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-cleanup.html * igt@gem_eio@in-flight-contexts-10ms: - shard-iclb: [PASS][16] -> [TIMEOUT][17] ([i915#3070]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/shard-iclb2/igt@gem_...@in-flight-contexts-10ms.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/shard-iclb8/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_exec_fair@basic-none@vcs1: - shard-kbl: [PASS][18] -> [FAIL][19] ([i915#2842]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs1.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_reloc@basic-many-active@bcs0: - shard-apl: [PASS][20] -> [FAIL][21] ([i915#2389]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/shard-apl8/igt@gem_exec_reloc@basic-many-act...@bcs0.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/shard-apl3/igt@gem_exec_reloc@basic-many-act...@bcs0.html - shard-skl: NOTRUN -> [FAIL][22] ([i915#2389]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/shard-skl6/igt@gem_exec_reloc@basic-many-act...@bcs0.html - shard-kbl: [PASS][23] -> [FAIL][24] ([i915#2389]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/shard-kbl3/igt@gem_exec_reloc@basic-many-act...@bcs0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Pat
[Intel-gfx] [PATCH i-g-t] tests/kms_color: Remove gamma code from degamma tests
CRC should be collected without degamma transformation
and after drawing gradient with degamma LUT.
This patch removes things which are not related to degamma
and makes it similar to pipe gamma test.
Signed-off-by: Vidya Srinivas
---
tests/kms_color.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/tests/kms_color.c b/tests/kms_color.c
index 3a42532a5c27..2c9821cdecce 100644
--- a/tests/kms_color.c
+++ b/tests/kms_color.c
@@ -31,8 +31,7 @@ static void test_pipe_degamma(data_t *data,
{
igt_output_t *output;
igt_display_t *display = &data->display;
- gamma_lut_t *degamma_linear, *degamma_full;
- gamma_lut_t *gamma_linear;
+ gamma_lut_t *degamma_full;
color_t red_green_blue[] = {
{ 1.0, 0.0, 0.0 },
{ 0.0, 1.0, 0.0 },
@@ -42,11 +41,8 @@ static void test_pipe_degamma(data_t *data,
igt_require(igt_pipe_obj_has_prop(primary->pipe, IGT_CRTC_DEGAMMA_LUT));
igt_require(igt_pipe_obj_has_prop(primary->pipe, IGT_CRTC_GAMMA_LUT));
- degamma_linear = generate_table(data->degamma_lut_size, 1.0);
degamma_full = generate_table_max(data->degamma_lut_size);
- gamma_linear = generate_table(data->gamma_lut_size, 1.0);
-
for_each_valid_output_on_pipe(&data->display, primary->pipe->pipe,
output) {
drmModeModeInfo *mode;
struct igt_fb fb_modeset, fb;
@@ -75,8 +71,7 @@ static void test_pipe_degamma(data_t *data,
igt_plane_set_fb(primary, &fb_modeset);
disable_ctm(primary->pipe);
- disable_degamma(primary->pipe);
- set_gamma(data, primary->pipe, gamma_linear);
+ set_degamma(data, primary->pipe, degamma_full);
igt_display_commit(&data->display);
/* Draw solid colors with no degamma transformation. */
@@ -92,7 +87,6 @@ static void test_pipe_degamma(data_t *data,
*/
paint_gradient_rectangles(data, mode, red_green_blue, &fb);
igt_plane_set_fb(primary, &fb);
- set_degamma(data, primary->pipe, degamma_full);
igt_display_commit(&data->display);
igt_wait_for_vblank(data->drm_fd,
display->pipes[primary->pipe->pipe].crtc_offset);
@@ -105,13 +99,13 @@ static void test_pipe_degamma(data_t *data,
igt_plane_set_fb(primary, NULL);
igt_output_set_pipe(output, PIPE_NONE);
+ igt_display_commit2(&data->display, data->display.is_atomic ?
+ COMMIT_ATOMIC :
COMMIT_LEGACY);
igt_remove_fb(data->drm_fd, &fb);
igt_remove_fb(data->drm_fd, &fb_modeset);
}
- free_lut(degamma_linear);
free_lut(degamma_full);
- free_lut(gamma_linear);
}
/*
@@ -191,6 +185,8 @@ static void test_pipe_gamma(data_t *data,
igt_plane_set_fb(primary, NULL);
igt_output_set_pipe(output, PIPE_NONE);
+ igt_display_commit2(&data->display, data->display.is_atomic ?
+ COMMIT_ATOMIC :
COMMIT_LEGACY);
igt_remove_fb(data->drm_fd, &fb);
igt_remove_fb(data->drm_fd, &fb_modeset);
}
--
2.7.4
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Get rid of fence error propagation (rev2)
== Series Details ==
Series: drm/i915: Get rid of fence error propagation (rev2)
URL : https://patchwork.freedesktop.org/series/90891/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10165 -> Patchwork_20274
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/index.html
Known issues
Here are the changes found in Patchwork_20274 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [PASS][1] -> [FAIL][2] ([i915#49])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][3] ([i915#3303]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
* igt@kms_frontbuffer_tracking@basic:
- fi-tgl-u2: [FAIL][5] ([i915#2416]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-tgl-u2/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/fi-tgl-u2/igt@kms_frontbuffer_track...@basic.html
Warnings
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[DMESG-FAIL][7] ([i915#3462]) -> [INCOMPLETE][8]
([i915#2782] / [i915#2940] / [i915#3462])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
- fi-tgl-u2: [INCOMPLETE][9] ([i915#3462]) -> [DMESG-FAIL][10]
([i915#3462])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-tgl-u2/igt@i915_selftest@l...@execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/fi-tgl-u2/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][11] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][12] ([i915#1436] / [i915#3363])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-skl-6600u/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/fi-skl-6600u/igt@run...@aborted.html
- fi-glk-dsi: [FAIL][13] ([i915#2426] / [i915#3363] /
[k.org#202321]) -> [FAIL][14] ([i915#3363] / [k.org#202321])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-glk-dsi/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-soraka: [FAIL][15] ([i915#1436] / [i915#3363]) -> [FAIL][16]
([i915#1436] / [i915#2426] / [i915#3363])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-kbl-soraka/igt@run...@aborted.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/fi-kbl-soraka/igt@run...@aborted.html
- fi-cml-u2: [FAIL][17] ([i915#2082] / [i915#2426] / [i915#3363] /
[i915#3462]) -> [FAIL][18] ([i915#3363] / [i915#3462])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-cml-u2/igt@run...@aborted.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/fi-cml-u2/igt@run...@aborted.html
- fi-cml-s: [FAIL][19] ([i915#3363] / [i915#3462]) -> [FAIL][20]
([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-cml-s/igt@run...@aborted.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/fi-cml-s/igt@run...@aborted.html
- fi-cfl-guc: [FAIL][21] ([i915#3363]) -> [FAIL][22] ([i915#2426] /
[i915#3363])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-cfl-guc/igt@run...@aborted.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/fi-cfl-guc/igt@run...@aborted.html
- fi-kbl-7567u: [FAIL][23] ([i915#1436] / [i915#2426] / [i915#3363])
-> [FAIL][24] ([i915#1436] / [i915#3363])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-kbl-7567u/igt@run...@aborted.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20274/fi-kbl-7567u/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
[i915#2416]: https://gitlab.freedesktop.org/drm/intel/issues/2416
[i915#2426]:
[Intel-gfx] [PATCH v3 0/7] drm/i915: Finish conversion to GRAPHICS_VER
v3 is a resend from v2 (https://patchwork.freedesktop.org/series/90693/) now with dri-devel Cc'ed. Notice that this patch series can be applied splitting it up through the trees, it's not necessary to apply them together. The intention is to apply first 3 patches on drm-intel-gt-next and the remaining on drm-intel-next. I'm intentionally _not_ removing the INTEL_GEN/IS_GEN/IS_GEN_RANGE macros now. A few days/weeks after this is applied and when drm-intel-gt-next and drm-intel-next is back in sync, we can remove any leftovers that went in and remove the macros via a topic branch. Latest version of previous series "drm/i915: Extend GEN renames to the rest of the driver" (https://patchwork.freedesktop.org/series/88825/) dropped one patch converting all the instances of IS_GEN() and INTEL_GEN() to GRAPHICS_VER() due to the patches changing the meaning of the macros IS_GRAPHICS_VER/GRAPHICS_VER and removal of IS_GRAPHICS_RANGE(). I couldn't find a way to convince coccinelle to fix all places, so I just did it manually in separate commits the places that were not updated. Finish the conversion splitting the changes so it can go to the different branches (drm-intel-gt-next and drm-intel-next). I also split the gvt changes, but I think it would be easier to take this directly on drm-intel-next. v2: update commit messages with the proper semantic patch (Matt Roper) and regenerate the patches to also convert changes that got added in between. v3: resend with dri-devel Cc'ed since we are touching gt/gem/core. Also, let's get an ack on merge strategy Cc: intel-gvt-...@lists.freedesktop.org Cc: Zhenyu Wang Lucas De Marchi (7): drm/i915/gt: replace IS_GEN and friends with GRAPHICS_VER drm/i915/gt: Add remaining conversions to GRAPHICS_VER drm/i915/gem: replace IS_GEN and friends with GRAPHICS_VER drm/i915/gvt: replace IS_GEN and friends with GRAPHICS_VER drm/i915: replace IS_GEN and friends with GRAPHICS_VER drm/i915: Add remaining conversions to GRAPHICS_VER drm/i915/display: replace IS_GEN() in commented code drivers/gpu/drm/i915/display/intel_tv.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 10 +-- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +- .../gpu/drm/i915/gem/i915_gem_object_blt.c| 8 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 16 ++-- drivers/gpu/drm/i915/gem/i915_gem_tiling.c| 12 +-- .../i915/gem/selftests/i915_gem_client_blt.c | 10 +-- .../i915/gem/selftests/i915_gem_coherency.c | 4 +- .../drm/i915/gem/selftests/i915_gem_context.c | 16 ++-- .../drm/i915/gem/selftests/i915_gem_mman.c| 14 ++-- .../drm/i915/gem/selftests/igt_gem_utils.c| 10 +-- drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 40 +- drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 54 ++--- drivers/gpu/drm/i915/gt/intel_engine_types.h | 4 +- .../drm/i915/gt/intel_execlists_submission.c | 18 ++--- drivers/gpu/drm/i915/gt/intel_ggtt.c | 18 ++--- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 34 drivers/gpu/drm/i915/gt/intel_gt.c| 27 --- .../gpu/drm/i915/gt/intel_gt_clock_utils.c| 12 +-- drivers/gpu/drm/i915/gt/intel_gt_irq.c| 6 +- drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 10 +-- drivers/gpu/drm/i915/gt/intel_gtt.c | 14 ++-- drivers/gpu/drm/i915/gt/intel_llc.c | 6 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 46 +-- drivers/gpu/drm/i915/gt/intel_mocs.c | 8 +- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 6 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 16 ++-- drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +- drivers/gpu/drm/i915/gt/intel_reset.c | 14 ++-- .../gpu/drm/i915/gt/intel_ring_submission.c | 64 +++ drivers/gpu/drm/i915/gt/intel_rps.c | 60 +++--- drivers/gpu/drm/i915/gt/intel_sseu.c | 14 ++-- drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 6 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +++ drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 6 +- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 +- drivers/gpu/drm/i915/gt/selftest_execlists.c | 4 +- drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 8 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 +- drivers/gpu/drm/i915/gt/selftest_llc.c| 4 +- drivers/gpu/drm/i915/gt/selftest_lrc.c| 8 +- drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +- drivers/gpu/drm/i915/gt/selftest_rc6.c| 4 +- .../drm/i915/gt/selftest_ring_submission.c| 6 +- drivers/gpu/drm/i915/gt/selftest_rps.c| 16 ++-- drivers/gpu/drm/i915/gt/selftest_timeline.c | 6 +- .../gpu/drm/i915/gt/selftest_wo
[Intel-gfx] [PATCH v3 1/7] drm/i915/gt: replace IS_GEN and friends with GRAPHICS_VER
This was done by the following semantic patch:
@@ expression i915; @@
- INTEL_GEN(i915)
+ GRAPHICS_VER(i915)
@@ expression i915; expression E; @@
- INTEL_GEN(i915) >= E
+ GRAPHICS_VER(i915) >= E
@@ expression dev_priv; expression E; @@
- !IS_GEN(dev_priv, E)
+ GRAPHICS_VER(dev_priv) != E
@@ expression dev_priv; expression E; @@
- IS_GEN(dev_priv, E)
+ GRAPHICS_VER(dev_priv) == E
@@
expression dev_priv;
expression from, until;
@@
- IS_GEN_RANGE(dev_priv, from, until)
+ IS_GRAPHICS_VER(dev_priv, from, until)
@def@
expression E;
identifier id =~ "^gen$";
@@
- id = GRAPHICS_VER(E)
+ ver = GRAPHICS_VER(E)
@@
identifier def.id;
@@
- id
+ ver
It also takes care of renaming the variable we assign to GRAPHICS_VER()
so to use "ver" rather than "gen".
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 38 +--
drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 54 +++
.../drm/i915/gt/intel_execlists_submission.c | 18 ++---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 18 ++---
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 34 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 27
.../gpu/drm/i915/gt/intel_gt_clock_utils.c| 12 ++--
drivers/gpu/drm/i915/gt/intel_gt_irq.c| 6 +-
drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 10 +--
drivers/gpu/drm/i915/gt/intel_gtt.c | 14 ++--
drivers/gpu/drm/i915/gt/intel_llc.c | 6 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 46 ++---
drivers/gpu/drm/i915/gt/intel_mocs.c | 8 +--
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 6 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 16 ++---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 14 ++--
.../gpu/drm/i915/gt/intel_ring_submission.c | 64 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 60 -
drivers/gpu/drm/i915/gt/intel_sseu.c | 14 ++--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +--
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 6 +-
drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 4 +-
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 8 +--
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 +--
drivers/gpu/drm/i915/gt/selftest_llc.c| 4 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c| 8 +--
drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rc6.c| 4 +-
.../drm/i915/gt/selftest_ring_submission.c| 6 +-
drivers/gpu/drm/i915/gt/selftest_rps.c| 16 ++---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 6 +-
.../gpu/drm/i915/gt/selftest_workarounds.c| 8 +--
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 4 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +--
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
44 files changed, 324 insertions(+), 323 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index d4f4452ce5ed..0389bceebd06 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -85,14 +85,14 @@ static int gen6_drpc(struct seq_file *m)
gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
- if (INTEL_GEN(i915) >= 9) {
+ if (GRAPHICS_VER(i915) >= 9) {
gen9_powergate_enable =
intel_uncore_read(uncore, GEN9_PG_ENABLE);
gen9_powergate_status =
intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS);
}
- if (INTEL_GEN(i915) <= 7)
+ if (GRAPHICS_VER(i915) <= 7)
sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
&rc6vids, NULL);
@@ -100,7 +100,7 @@ static int gen6_drpc(struct seq_file *m)
yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
seq_printf(m, "RC6 Enabled: %s\n",
yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
- if (INTEL_GEN(i915) >= 9) {
+ if (GRAPHICS_VER(i915) >= 9) {
seq_printf(m, "Render Well Gating Enabled: %s\n",
yesno(gen9_powerg
[Intel-gfx] [PATCH v3 6/7] drm/i915: Add remaining conversions to GRAPHICS_VER
For some reason coccinelle misses a few cases in header files with calls to INTEL_GEN()/IS_GEN(). Do a manual conversion for those. Signed-off-by: Lucas De Marchi Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/i915_drv.h | 37 - drivers/gpu/drm/i915/i915_reg.h | 26 +++ 2 files changed, 31 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 91fda14f8f6c..38ff2fb89744 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1552,9 +1552,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, (IS_ALDERLAKE_P(__i915) && \ IS_GT_STEP(__i915, since, until)) -#define IS_LP(dev_priv)(INTEL_INFO(dev_priv)->is_lp) -#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) -#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) +#define IS_LP(dev_priv)(INTEL_INFO(dev_priv)->is_lp) +#define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv)) +#define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv)) #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) @@ -1574,12 +1574,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution * All later gens can run the final buffer from the ppgtt */ -#define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7) +#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7) #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) #define HAS_SNOOP(dev_priv)(INTEL_INFO(dev_priv)->has_snoop) #define HAS_EDRAM(dev_priv)((dev_priv)->edram_size_mb) -#define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6) +#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6) #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv) #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) @@ -1612,7 +1612,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_BROKEN_CS_TLB(dev_priv)(IS_I830(dev_priv) || IS_I845G(dev_priv)) #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \ - (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9)) + (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9) /* WaRsDisableCoarsePowerGating:skl,cnl */ #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ @@ -1620,23 +1620,22 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, IS_SKL_GT3(dev_priv) ||\ IS_SKL_GT4(dev_priv)) -#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) -#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ +#define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4) +#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \ IS_GEMINILAKE(dev_priv) || \ IS_KABYLAKE(dev_priv)) /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte * rows, which changed the alignment requirements and fence programming. */ -#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ -!(IS_I915G(dev_priv) || \ -IS_I915GM(dev_priv))) +#define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \ +!(IS_I915G(dev_priv) || IS_I915GM(dev_priv))) #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) -#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) +#define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2) #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) -#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7) +#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7) #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) @@ -1647,7 +1646,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) #define HAS_PSR_HW_TRACKING(dev_priv) \ (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) -#define HAS_PSR2_SEL_FETCH(dev_priv)(INTEL_GEN(dev_priv) >= 12) +#define HAS_PSR2_SEL_FETCH(dev_priv)(GRAPHICS_VER(dev_priv) >= 12) #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0) #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) @@ -1658,7 +1657,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv
[Intel-gfx] [PATCH v3 4/7] drm/i915/gvt: replace IS_GEN and friends with GRAPHICS_VER
This was done by the following semantic patch:
@@ expression i915; @@
- INTEL_GEN(i915)
+ GRAPHICS_VER(i915)
@@ expression i915; expression E; @@
- INTEL_GEN(i915) >= E
+ GRAPHICS_VER(i915) >= E
@@ expression dev_priv; expression E; @@
- !IS_GEN(dev_priv, E)
+ GRAPHICS_VER(dev_priv) != E
@@ expression dev_priv; expression E; @@
- IS_GEN(dev_priv, E)
+ GRAPHICS_VER(dev_priv) == E
@@
expression dev_priv;
expression from, until;
@@
- IS_GEN_RANGE(dev_priv, from, until)
+ IS_GRAPHICS_VER(dev_priv, from, until)
@def@
expression E;
identifier id =~ "^gen$";
@@
- id = GRAPHICS_VER(E)
+ ver = GRAPHICS_VER(E)
@@
identifier def.id;
@@
- id
+ ver
It also takes care of renaming the variable we assign to GRAPHICS_VER()
so to use "ver" rather than "gen".
Cc: intel-gvt-...@lists.freedesktop.org
Cc: Zhenyu Wang
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 8
drivers/gpu/drm/i915/gvt/dmabuf.c | 2 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c | 10 +-
drivers/gpu/drm/i915/gvt/gtt.c | 4 ++--
drivers/gpu/drm/i915/gvt/handlers.c | 6 +++---
drivers/gpu/drm/i915/gvt/interrupt.c| 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 10 +-
drivers/gpu/drm/i915/gvt/scheduler.c| 4 ++--
drivers/gpu/drm/i915/gvt/vgpu.c | 4 ++--
9 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index ca9c9e27a43d..c4118b808268 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -1006,7 +1006,7 @@ static int cmd_reg_handler(struct parser_exec_state *s,
* update reg values in it into vregs, so LRIs in workload with
* inhibit context will restore with correct values
*/
- if (IS_GEN(s->engine->i915, 9) &&
+ if (GRAPHICS_VER(s->engine->i915) == 9 &&
intel_gvt_mmio_is_sr_in_ctx(gvt, offset) &&
!strncmp(cmd, "lri", 3)) {
intel_gvt_hypervisor_read_gpa(s->vgpu,
@@ -1390,7 +1390,7 @@ static int gen8_check_mi_display_flip(struct
parser_exec_state *s,
if (!info->async_flip)
return 0;
- if (INTEL_GEN(s->engine->i915) >= 9) {
+ if (GRAPHICS_VER(s->engine->i915) >= 9) {
stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
GENMASK(12, 10)) >> 10;
@@ -1418,7 +1418,7 @@ static int gen8_update_plane_mmio_from_mi_display_flip(
set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
info->surf_val << 12);
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (GRAPHICS_VER(dev_priv) >= 9) {
set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9,
0),
info->stride_val);
set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12,
10),
@@ -1446,7 +1446,7 @@ static int decode_mi_display_flip(struct
parser_exec_state *s,
{
if (IS_BROADWELL(s->engine->i915))
return gen8_decode_mi_display_flip(s, info);
- if (INTEL_GEN(s->engine->i915) >= 9)
+ if (GRAPHICS_VER(s->engine->i915) >= 9)
return skl_decode_mi_display_flip(s, info);
return -ENODEV;
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c
b/drivers/gpu/drm/i915/gvt/dmabuf.c
index d4f883f35b95..8e65cd8258b9 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.c
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -223,7 +223,7 @@ static struct drm_i915_gem_object *vgpu_create_gem(struct
drm_device *dev,
obj->read_domains = I915_GEM_DOMAIN_GTT;
obj->write_domain = 0;
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (GRAPHICS_VER(dev_priv) >= 9) {
unsigned int tiling_mode = 0;
unsigned int stride = 0;
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c
b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 0889ad8291b0..11a8baba6822 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -151,7 +151,7 @@ static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu,
int pipe,
u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;
u32 stride = stride_reg;
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (GRAPHICS_VER(dev_priv) >= 9) {
switch (tiled) {
case PLANE_CTL_TILED_LINEAR:
stride = stride_reg * 64;
@@ -215,7 +215,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
if (!plane->enabled)
return -ENODEV;
- if (INTEL_GEN(dev_priv) >
[Intel-gfx] [PATCH v3 3/7] drm/i915/gem: replace IS_GEN and friends with GRAPHICS_VER
This was done by the following semantic patch:
@@ expression i915; @@
- INTEL_GEN(i915)
+ GRAPHICS_VER(i915)
@@ expression i915; expression E; @@
- INTEL_GEN(i915) >= E
+ GRAPHICS_VER(i915) >= E
@@ expression dev_priv; expression E; @@
- !IS_GEN(dev_priv, E)
+ GRAPHICS_VER(dev_priv) != E
@@ expression dev_priv; expression E; @@
- IS_GEN(dev_priv, E)
+ GRAPHICS_VER(dev_priv) == E
@@
expression dev_priv;
expression from, until;
@@
- IS_GEN_RANGE(dev_priv, from, until)
+ IS_GRAPHICS_VER(dev_priv, from, until)
@def@
expression E;
identifier id =~ "^gen$";
@@
- id = GRAPHICS_VER(E)
+ ver = GRAPHICS_VER(E)
@@
identifier def.id;
@@
- id
+ ver
It also takes care of renaming the variable we assign to GRAPHICS_VER()
so to use "ver" rather than "gen".
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +++---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 10 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 8
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 16
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 12 ++--
.../drm/i915/gem/selftests/i915_gem_client_blt.c | 10 +-
.../drm/i915/gem/selftests/i915_gem_coherency.c | 4 ++--
.../drm/i915/gem/selftests/i915_gem_context.c| 16
.../gpu/drm/i915/gem/selftests/i915_gem_mman.c | 14 +++---
.../gpu/drm/i915/gem/selftests/igt_gem_utils.c | 10 +-
11 files changed, 54 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 188dee13e017..7720b8c22c81 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1190,7 +1190,7 @@ static void set_ppgtt_barrier(void *data)
{
struct i915_address_space *old = data;
- if (INTEL_GEN(old->i915) < 8)
+ if (GRAPHICS_VER(old->i915) < 8)
gen6_ppgtt_unpin_all(i915_vm_to_ppgtt(old));
i915_vm_close(old);
@@ -1436,7 +1436,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
context->max_eus_per_subslice = user->max_eus_per_subslice;
/* Part specific restrictions. */
- if (IS_GEN(i915, 11)) {
+ if (GRAPHICS_VER(i915) == 11) {
unsigned int hw_s = hweight8(device->slice_mask);
unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
unsigned int req_s = hweight8(context->slice_mask);
@@ -1503,7 +1503,7 @@ static int set_sseu(struct i915_gem_context *ctx,
if (args->size < sizeof(user_sseu))
return -EINVAL;
- if (!IS_GEN(i915, 11))
+ if (GRAPHICS_VER(i915) != 11)
return -ENODEV;
if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 297143511f99..24c0582e46fb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -500,7 +500,7 @@ eb_validate_vma(struct i915_execbuffer *eb,
* also covers all platforms with local memory.
*/
if (entry->relocation_count &&
- INTEL_GEN(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
+ GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
return -EINVAL;
if (unlikely(entry->flags & eb->invalid_flags))
@@ -1439,7 +1439,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
static bool reloc_can_use_engine(const struct intel_engine_cs *engine)
{
- return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6);
+ return engine->class != VIDEO_DECODE_CLASS ||
GRAPHICS_VER(engine->i915) != 6;
}
static u32 *reloc_gpu(struct i915_execbuffer *eb,
@@ -1671,7 +1671,7 @@ eb_relocate_entry(struct i915_execbuffer *eb,
* batchbuffers.
*/
if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
- IS_GEN(eb->i915, 6)) {
+ GRAPHICS_VER(eb->i915) == 6) {
err = i915_vma_bind(target->vma,
target->vma->obj->cache_level,
PIN_GLOBAL, NULL);
@@ -2332,7 +2332,7 @@ static int i915_reset_gen7_sol_offsets(struct
i915_request *rq)
u32 *cs;
int i;
- if (!IS_GEN(rq->engine->i915, 7) || rq->engine->id != RCS0) {
+ if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) {
drm_dbg(&rq->engine->i915->drm, "sol reset is
[Intel-gfx] [PATCH v3 7/7] drm/i915/display: replace IS_GEN() in commented code
Since we are replacing IS_GEN() with GRAPHICS_VER(), make sure we take
care of the comments as well.
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_tv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c
b/drivers/gpu/drm/i915/display/intel_tv.c
index ce73ebdfc669..aa52af7891f0 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -1307,7 +1307,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
* the active portion. Hence following this formula seems
* more trouble that it's worth.
*
-* if (IS_GEN(dev_priv, 4)) {
+* if (GRAPHICS_VER(dev_priv) == 4) {
* num = cdclk * (tv_mode->oversample >> !tv_mode->progressive);
* den = tv_mode->clock;
* } else {
--
2.31.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 5/7] drm/i915: replace IS_GEN and friends with GRAPHICS_VER
This was done by the following semantic patch:
@@ expression i915; @@
- INTEL_GEN(i915)
+ GRAPHICS_VER(i915)
@@ expression i915; expression E; @@
- INTEL_GEN(i915) >= E
+ GRAPHICS_VER(i915) >= E
@@ expression dev_priv; expression E; @@
- !IS_GEN(dev_priv, E)
+ GRAPHICS_VER(dev_priv) != E
@@ expression dev_priv; expression E; @@
- IS_GEN(dev_priv, E)
+ GRAPHICS_VER(dev_priv) == E
@@
expression dev_priv;
expression from, until;
@@
- IS_GEN_RANGE(dev_priv, from, until)
+ IS_GRAPHICS_VER(dev_priv, from, until)
@def@
expression E;
identifier id =~ "^gen$";
@@
- id = GRAPHICS_VER(E)
+ ver = GRAPHICS_VER(E)
@@
identifier def.id;
@@
- id
+ ver
It also takes care of renaming the variable we assign to GRAPHICS_VER()
so to use "ver" rather than "gen".
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/i915_cmd_parser.c| 10 +--
drivers/gpu/drm/i915/i915_debugfs.c | 32
drivers/gpu/drm/i915/i915_drv.c | 20 ++---
drivers/gpu/drm/i915/i915_gem.c | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 80 +--
drivers/gpu/drm/i915/i915_irq.c | 34
drivers/gpu/drm/i915/i915_perf.c | 44 +-
drivers/gpu/drm/i915/i915_pmu.c | 8 +-
drivers/gpu/drm/i915/i915_request.c | 4 +-
drivers/gpu/drm/i915/i915_suspend.c | 16 ++--
drivers/gpu/drm/i915/i915_sysfs.c | 2 +-
drivers/gpu/drm/i915/i915_vgpu.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 22 ++---
drivers/gpu/drm/i915/intel_dram.c | 14 ++--
drivers/gpu/drm/i915/intel_pch.c | 10 +--
drivers/gpu/drm/i915/intel_pm.c | 14 ++--
drivers/gpu/drm/i915/intel_sideband.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 26 +++---
drivers/gpu/drm/i915/intel_wopcm.c| 10 +--
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 +-
drivers/gpu/drm/i915/selftests/i915_perf.c| 6 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 8 +-
drivers/gpu/drm/i915/selftests/igt_spinner.c | 12 +--
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +-
24 files changed, 193 insertions(+), 193 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 5b4b2bd46e7c..3992c25a191d 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -946,8 +946,8 @@ int intel_engine_init_cmd_parser(struct intel_engine_cs
*engine)
int cmd_table_count;
int ret;
- if (!IS_GEN(engine->i915, 7) && !(IS_GEN(engine->i915, 9) &&
- engine->class == COPY_ENGINE_CLASS))
+ if (GRAPHICS_VER(engine->i915) != 7 && !(GRAPHICS_VER(engine->i915) ==
9 &&
+engine->class ==
COPY_ENGINE_CLASS))
return 0;
switch (engine->class) {
@@ -977,7 +977,7 @@ int intel_engine_init_cmd_parser(struct intel_engine_cs
*engine)
break;
case COPY_ENGINE_CLASS:
engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
- if (IS_GEN(engine->i915, 9)) {
+ if (GRAPHICS_VER(engine->i915) == 9) {
cmd_tables = gen9_blt_cmd_table;
cmd_table_count = ARRAY_SIZE(gen9_blt_cmd_table);
engine->get_cmd_length_mask =
@@ -993,7 +993,7 @@ int intel_engine_init_cmd_parser(struct intel_engine_cs
*engine)
cmd_table_count = ARRAY_SIZE(gen7_blt_cmd_table);
}
- if (IS_GEN(engine->i915, 9)) {
+ if (GRAPHICS_VER(engine->i915) == 9) {
engine->reg_tables = gen9_blt_reg_tables;
engine->reg_table_count =
ARRAY_SIZE(gen9_blt_reg_tables);
@@ -1537,7 +1537,7 @@ int intel_engine_cmd_parser(struct intel_engine_cs
*engine,
if (IS_HASWELL(engine->i915))
flags = MI_BATCH_NON_SECURE_HSW;
- GEM_BUG_ON(!IS_GEN_RANGE(engine->i915, 6, 7));
+ GEM_BUG_ON(!IS_GRAPHICS_VER(engine->i915, 6,
7));
__gen6_emit_bb_start(batch_end,
batch_addr,
flags);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a4d8a836bd57..0529576f069c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -361,7 +361,7 @@ sta
[Intel-gfx] [PATCH v3 2/7] drm/i915/gt: Add remaining conversions to GRAPHICS_VER
For some reason coccinelle misses a few cases in gt with calls to
INTEL_GEN()/IS_GEN(). Do a manual conversion for those.
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 4 ++--
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 6 +++---
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index 0389bceebd06..4270b5a34a83 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -230,7 +230,7 @@ static int drpc_show(struct seq_file *m, void *unused)
with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
err = vlv_drpc(m);
- else if (INTEL_GEN(i915) >= 6)
+ else if (GRAPHICS_VER(i915) >= 6)
err = gen6_drpc(m);
else
err = ilk_drpc(m);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 9ef349cd5cea..e113f93b3274 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -606,10 +606,10 @@ intel_engine_has_relative_mmio(const struct
intel_engine_cs * const engine)
}
#define instdone_has_slice(dev_priv___, sseu___, slice___) \
- ((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & BIT(slice___))
+ ((GRAPHICS_VER(dev_priv___) == 7 ? 1 : ((sseu___)->slice_mask)) &
BIT(slice___))
#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
- (IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
+ (GRAPHICS_VER(dev_priv__) == 7 ? (1 & BIT(subslice__)) : \
intel_sseu_has_subslice(sseu__, 0, subslice__))
#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index 51780282d872..714fe8495775 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
@@ -248,7 +248,7 @@ int intel_sseu_status(struct seq_file *m, struct intel_gt
*gt)
struct sseu_dev_info sseu;
intel_wakeref_t wakeref;
- if (INTEL_GEN(i915) < 8)
+ if (GRAPHICS_VER(i915) < 8)
return -ENODEV;
seq_puts(m, "SSEU Device Info\n");
@@ -265,9 +265,9 @@ int intel_sseu_status(struct seq_file *m, struct intel_gt
*gt)
cherryview_sseu_device_status(gt, &sseu);
else if (IS_BROADWELL(i915))
bdw_sseu_device_status(gt, &sseu);
- else if (IS_GEN(i915, 9))
+ else if (GRAPHICS_VER(i915) == 9)
gen9_sseu_device_status(gt, &sseu);
- else if (INTEL_GEN(i915) >= 10)
+ else if (GRAPHICS_VER(i915) >= 10)
gen10_sseu_device_status(gt, &sseu);
}
--
2.31.1
___
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[Intel-gfx] [PATCH v3 3/4] drm/shmem-helper: Align to page size in dumb_create
shmem helpers seem a bit sloppy here by automatically rounding up when
actually creating the buffer, which results in under-reporting of what
we actually have. Caught by igt/vgem_basic tests.
Acked-by: Thomas Zimmermann
Signed-off-by: Daniel Vetter
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
---
drivers/gpu/drm/drm_gem_shmem_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c
b/drivers/gpu/drm/drm_gem_shmem_helper.c
index 11edd54f0580..296ab1b7c07f 100644
--- a/drivers/gpu/drm/drm_gem_shmem_helper.c
+++ b/drivers/gpu/drm/drm_gem_shmem_helper.c
@@ -505,13 +505,13 @@ int drm_gem_shmem_dumb_create(struct drm_file *file,
struct drm_device *dev,
if (!args->pitch || !args->size) {
args->pitch = min_pitch;
- args->size = args->pitch * args->height;
+ args->size = PAGE_ALIGN(args->pitch * args->height);
} else {
/* ensure sane minimum values */
if (args->pitch < min_pitch)
args->pitch = min_pitch;
if (args->size < args->pitch * args->height)
- args->size = args->pitch * args->height;
+ args->size = PAGE_ALIGN(args->pitch * args->height);
}
shmem = drm_gem_shmem_create_with_handle(file, dev, args->size,
&args->handle);
--
2.31.0
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[Intel-gfx] [PATCH v3 4/4] drm/vgem: use shmem helpers
Aside from deleting lots of code the real motivation here is to switch
the mmap over to VM_PFNMAP, to be more consistent with what real gpu
drivers do. They're all VM_PFNMP, which means get_user_pages doesn't
work, and even if you try and there's a struct page behind that,
touching it and mucking around with its refcount can upset drivers
real bad.
v2: Review from Thomas:
- sort #include
- drop more dead code that I didn't spot somehow
v3: select DRM_GEM_SHMEM_HELPER to make it build (intel-gfx-ci)
v4: I got tricked by 0cf2ef46c6c0 ("drm/shmem-helper: Use cached
mappings by default"), and we need WC in vgem because vgem doesn't
have explicit begin/end cpu access ioctls.
Also add a comment why exactly vgem has to use wc.
v5: Don't set obj->base.funcs, it will default to drm_gem_shmem_funcs
(Thomas)
Cc: Thomas Zimmermann
Acked-by: Thomas Zimmermann
Cc: John Stultz
Cc: Sumit Semwal
Cc: "Christian König"
Signed-off-by: Daniel Vetter
Cc: Melissa Wen
Cc: Chris Wilson
---
drivers/gpu/drm/Kconfig | 1 +
drivers/gpu/drm/vgem/vgem_drv.c | 342 ++--
2 files changed, 14 insertions(+), 329 deletions(-)
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 9c21527b791f..fb38ef7b3206 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -268,6 +268,7 @@ source "drivers/gpu/drm/kmb/Kconfig"
config DRM_VGEM
tristate "Virtual GEM provider"
depends on DRM
+ select DRM_GEM_SHMEM_HELPER
help
Choose this option to get a virtual graphics memory manager,
as used by Mesa's software renderer for enhanced performance.
diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c
index bf38a7e319d1..a87eafa89e9f 100644
--- a/drivers/gpu/drm/vgem/vgem_drv.c
+++ b/drivers/gpu/drm/vgem/vgem_drv.c
@@ -38,6 +38,7 @@
#include
#include
+#include
#include
#include
#include
@@ -50,87 +51,11 @@
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 0
-static const struct drm_gem_object_funcs vgem_gem_object_funcs;
-
static struct vgem_device {
struct drm_device drm;
struct platform_device *platform;
} *vgem_device;
-static void vgem_gem_free_object(struct drm_gem_object *obj)
-{
- struct drm_vgem_gem_object *vgem_obj = to_vgem_bo(obj);
-
- kvfree(vgem_obj->pages);
- mutex_destroy(&vgem_obj->pages_lock);
-
- if (obj->import_attach)
- drm_prime_gem_destroy(obj, vgem_obj->table);
-
- drm_gem_object_release(obj);
- kfree(vgem_obj);
-}
-
-static vm_fault_t vgem_gem_fault(struct vm_fault *vmf)
-{
- struct vm_area_struct *vma = vmf->vma;
- struct drm_vgem_gem_object *obj = vma->vm_private_data;
- /* We don't use vmf->pgoff since that has the fake offset */
- unsigned long vaddr = vmf->address;
- vm_fault_t ret = VM_FAULT_SIGBUS;
- loff_t num_pages;
- pgoff_t page_offset;
- page_offset = (vaddr - vma->vm_start) >> PAGE_SHIFT;
-
- num_pages = DIV_ROUND_UP(obj->base.size, PAGE_SIZE);
-
- if (page_offset >= num_pages)
- return VM_FAULT_SIGBUS;
-
- mutex_lock(&obj->pages_lock);
- if (obj->pages) {
- get_page(obj->pages[page_offset]);
- vmf->page = obj->pages[page_offset];
- ret = 0;
- }
- mutex_unlock(&obj->pages_lock);
- if (ret) {
- struct page *page;
-
- page = shmem_read_mapping_page(
- file_inode(obj->base.filp)->i_mapping,
- page_offset);
- if (!IS_ERR(page)) {
- vmf->page = page;
- ret = 0;
- } else switch (PTR_ERR(page)) {
- case -ENOSPC:
- case -ENOMEM:
- ret = VM_FAULT_OOM;
- break;
- case -EBUSY:
- ret = VM_FAULT_RETRY;
- break;
- case -EFAULT:
- case -EINVAL:
- ret = VM_FAULT_SIGBUS;
- break;
- default:
- WARN_ON(PTR_ERR(page));
- ret = VM_FAULT_SIGBUS;
- break;
- }
-
- }
- return ret;
-}
-
-static const struct vm_operations_struct vgem_gem_vm_ops = {
- .fault = vgem_gem_fault,
- .open = drm_gem_vm_open,
- .close = drm_gem_vm_close,
-};
-
static int vgem_open(struct drm_device *dev, struct drm_file *file)
{
struct vgem_file *vfile;
@@ -159,266 +84,30 @@ static void vgem_postclose(struct drm_device *dev, struct
drm_file *file)
kfree(vfile);
}
-static struct drm_vgem_gem_object *__vgem_gem_create(struct drm_device *dev,
-
[Intel-gfx] [PATCH v3 2/4] drm/shmem-helper: Switch to vmf_insert_pfn
We want to stop gup, which isn't the case if we use vmf_insert_page
and VM_MIXEDMAP, because that does not set pte_special.
v2: With this shmem gem helpers now definitely need CONFIG_MMU (0day)
Signed-off-by: Daniel Vetter
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
---
drivers/gpu/drm/Kconfig| 2 +-
drivers/gpu/drm/drm_gem_shmem_helper.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 56a55a6e6239..9c21527b791f 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -206,7 +206,7 @@ config DRM_KMS_CMA_HELPER
config DRM_GEM_SHMEM_HELPER
bool
- depends on DRM
+ depends on DRM && MMU
help
Choose this if you need the GEM shmem helper functions
diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c
b/drivers/gpu/drm/drm_gem_shmem_helper.c
index 6d625cee7a6a..11edd54f0580 100644
--- a/drivers/gpu/drm/drm_gem_shmem_helper.c
+++ b/drivers/gpu/drm/drm_gem_shmem_helper.c
@@ -542,7 +542,7 @@ static vm_fault_t drm_gem_shmem_fault(struct vm_fault *vmf)
} else {
page = shmem->pages[page_offset];
- ret = vmf_insert_page(vma, vmf->address, page);
+ ret = vmf_insert_pfn(vma, vmf->address, page_to_pfn(page));
}
mutex_unlock(&shmem->pages_lock);
@@ -612,7 +612,7 @@ int drm_gem_shmem_mmap(struct drm_gem_object *obj, struct
vm_area_struct *vma)
return ret;
}
- vma->vm_flags |= VM_MIXEDMAP | VM_DONTEXPAND;
+ vma->vm_flags |= VM_PFNMAP | VM_DONTEXPAND;
vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
if (shmem->map_wc)
vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
--
2.31.0
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[Intel-gfx] [PATCH v3 1/4] dma-buf: Require VM_PFNMAP vma for mmap
tldr; DMA buffers aren't normal memory, expecting that you can use
them like that (like calling get_user_pages works, or that they're
accounting like any other normal memory) cannot be guaranteed.
Since some userspace only runs on integrated devices, where all
buffers are actually all resident system memory, there's a huge
temptation to assume that a struct page is always present and useable
like for any more pagecache backed mmap. This has the potential to
result in a uapi nightmare.
To stop this gap require that DMA buffer mmaps are VM_PFNMAP, which
blocks get_user_pages and all the other struct page based
infrastructure for everyone. In spirit this is the uapi counterpart to
the kernel-internal CONFIG_DMABUF_DEBUG.
Motivated by a recent patch which wanted to swich the system dma-buf
heap to vm_insert_page instead of vm_insert_pfn.
v2:
Jason brought up that we also want to guarantee that all ptes have the
pte_special flag set, to catch fast get_user_pages (on architectures
that support this). Allowing VM_MIXEDMAP (like VM_SPECIAL does) would
still allow vm_insert_page, but limiting to VM_PFNMAP will catch that.
From auditing the various functions to insert pfn pte entires
(vm_insert_pfn_prot, remap_pfn_range and all it's callers like
dma_mmap_wc) it looks like VM_PFNMAP is already required anyway, so
this should be the correct flag to check for.
References:
https://lore.kernel.org/lkml/cakmk7uhi+mg0z0humnt13qccvuturvjpcr0njrl12k-wbwz...@mail.gmail.com/
Acked-by: Christian König
Cc: Jason Gunthorpe
Cc: Suren Baghdasaryan
Cc: Matthew Wilcox
Cc: John Stultz
Signed-off-by: Daniel Vetter
Cc: Sumit Semwal
Cc: "Christian König"
Cc: linux-me...@vger.kernel.org
Cc: linaro-mm-...@lists.linaro.org
--
Resending this so I can test the next two patches for vgem/shmem in
intel-gfx-ci. Last round failed somehow, but I can't repro that at all
locally here.
No immediate plans to merge this patch here since ttm isn't addressed
yet (and there we have the hugepte issue, for which I don't think we
have a clear consensus yet).
-Daniel
---
drivers/dma-buf/dma-buf.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index eadd1eaa2fb5..dda583fb1f03 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -127,6 +127,7 @@ static struct file_system_type dma_buf_fs_type = {
static int dma_buf_mmap_internal(struct file *file, struct vm_area_struct *vma)
{
struct dma_buf *dmabuf;
+ int ret;
if (!is_dma_buf_file(file))
return -EINVAL;
@@ -142,7 +143,11 @@ static int dma_buf_mmap_internal(struct file *file, struct
vm_area_struct *vma)
dmabuf->size >> PAGE_SHIFT)
return -EINVAL;
- return dmabuf->ops->mmap(dmabuf, vma);
+ ret = dmabuf->ops->mmap(dmabuf, vma);
+
+ WARN_ON(!(vma->vm_flags & VM_PFNMAP));
+
+ return ret;
}
static loff_t dma_buf_llseek(struct file *file, loff_t offset, int whence)
@@ -1244,6 +1249,8 @@ EXPORT_SYMBOL_GPL(dma_buf_end_cpu_access);
int dma_buf_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma,
unsigned long pgoff)
{
+ int ret;
+
if (WARN_ON(!dmabuf || !vma))
return -EINVAL;
@@ -1264,7 +1271,11 @@ int dma_buf_mmap(struct dma_buf *dmabuf, struct
vm_area_struct *vma,
vma_set_file(vma, dmabuf->file);
vma->vm_pgoff = pgoff;
- return dmabuf->ops->mmap(dmabuf, vma);
+ ret = dmabuf->ops->mmap(dmabuf, vma);
+
+ WARN_ON(!(vma->vm_flags & VM_PFNMAP));
+
+ return ret;
}
EXPORT_SYMBOL_GPL(dma_buf_mmap);
--
2.31.0
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[Intel-gfx] [PATCH v3 0/4] shmem helpers for vgem
Hi all, Another small iteration, lost another patch, so another full resend. Thomas Zimmermann pointed out how to get at drm_gem_shmem_funcs without getting at drm_gem_shmem_funcs directly. Test-with: 20210527140732.5762-1-daniel.vet...@ffwll.ch Cheers, Daniel Daniel Vetter (4): dma-buf: Require VM_PFNMAP vma for mmap drm/shmem-helper: Switch to vmf_insert_pfn drm/shmem-helper: Align to page size in dumb_create drm/vgem: use shmem helpers drivers/dma-buf/dma-buf.c | 15 +- drivers/gpu/drm/Kconfig| 3 +- drivers/gpu/drm/drm_gem_shmem_helper.c | 8 +- drivers/gpu/drm/vgem/vgem_drv.c| 342 + 4 files changed, 32 insertions(+), 336 deletions(-) -- 2.31.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH 00/97] Basic GuC submission support in the i915
On Thu, Jun 03, 2021 at 09:51:19AM +0100, Tvrtko Ursulin wrote:
>
> On 03/06/2021 05:10, Matthew Brost wrote:
> > On Wed, Jun 02, 2021 at 04:27:18PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 25/05/2021 17:45, Matthew Brost wrote:
>
> [snip]
>
> > > > >* Kludgy way of interfacing with rest of the driver instead of
> > > > > refactoring
> > > > > to fit (idling, breadcrumbs, scheduler, tasklets, ...).
> > > > >
> > > >
> > > > Idling and breadcrumbs seem clean to me. Scheduler + tasklet are going
> > > > away once the DRM scheduler lands. No need rework those as we are just
> > > > going to rework this again.
> > >
> > > Well today I read the breadcrumbs patch and there is no way that's clean.
> > > It
> > > goes and creates one object per engine, then deletes them, replacing with
> > > GuC special one. All in the same engine setup. The same pattern of bolting
> > > on the GuC repeats too much for my taste.
> > >
> >
> > I don't think creating a default object /w a ref count then decrementing
> > the ref count + replacing it with a new object is that hard to
> > understand. IMO that is way better than how things worked previously
>
> It's not about it being hard to understand, although it certainly is far
> from the usual patterns, but about it being lazy design which in normal
> times would never be allowed. Because reduced and flattened to highlight the
> principal complaint it looks like this:
>
> engine_setup_for_each_engine:
>engine->breadcrumbs = create_breadcrumbs();
>if (guc) {
> if (!first_class_engine) {
> kfree(engine->breadcrumbs);
> engine->breadcrumbs = first_class_engine->breadcrumbs;
> } else {
> first_class_engine->breadcrumbs->vfuncs = guc_vfuncs;
> }
>}
>
I think are diving way to deep into individual patches on the cover
letter.
Agree this could be refactored bit more. Let me try a rework on this
patch in particular before this patch gets posted again.
Matt
> What I suggested is that patch should not break and hack the object oriented
> design and instead could do along the lines:
>
> gt_guc_setup:
>for_each_class:
> gt->uc.breadcrumbs[class] = create_guc_breadcrumbs();
>
> engine_setup_for_each_engine:
>if (guc)
> engine->breadcrumbs = get(gt->uc.breadcrumbs[class]);
>else
> engine->breadcrumbs = create_breadcrumbs();
>
> > where we just made implicit assumptions all over the driver of the
> > execlists backend behavior. If this was done properly in the current
> > i915 code base this really wouldn't be an issue.
>
> Don't really follow you here but it probably goes back to how upstream code
> was there available to be refactored all this time.
>
> Regards,
>
> Tvrtko
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Get rid of fence error propagation (rev2)
== Series Details == Series: drm/i915: Get rid of fence error propagation (rev2) URL : https://patchwork.freedesktop.org/series/90891/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter 'jump_whitelist' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter 'shadow_map' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter 'batch_map' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Function parameter or member 'trampoline' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter 'jump_whitelist' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter 'shadow_map' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function parameter 'batch_map' description in 'intel_engine_cmd_parser' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/ddi: Flush encoder power domain ref puts during driver unload
On Thu, May 27, 2021 at 06:40:00PM +, Patchwork wrote: > == Series Details == > > Series: series starting with [1/3] drm/i915/ddi: Flush encoder power domain > ref puts during driver unload > URL : https://patchwork.freedesktop.org/series/90613/ > State : success Thanks for the review, pushed to drm-intel-next. > > == Summary == > > CI Bug Log - changes from CI_DRM_10138_full -> Patchwork_20207_full > > > Summary > --- > > **SUCCESS** > > No regressions found. > > > > Known issues > > > Here are the changes found in Patchwork_20207_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@feature_discovery@display-3x: > - shard-tglb: NOTRUN -> [SKIP][1] ([i915#1839]) >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-tglb3/igt@feature_discov...@display-3x.html > > * igt@gem_ctx_persistence@legacy-engines-mixed: > - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +6 > similar issues >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-mixed.html > > * igt@gem_eio@in-flight-contexts-1us: > - shard-tglb: [PASS][3] -> [TIMEOUT][4] ([i915#3063]) >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10138/shard-tglb7/igt@gem_...@in-flight-contexts-1us.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-tglb5/igt@gem_...@in-flight-contexts-1us.html > > * igt@gem_exec_fair@basic-deadline: > - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2846]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10138/shard-glk6/igt@gem_exec_f...@basic-deadline.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-glk9/igt@gem_exec_f...@basic-deadline.html > - shard-apl: NOTRUN -> [FAIL][7] ([i915#2846]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-apl7/igt@gem_exec_f...@basic-deadline.html > > * igt@gem_exec_fair@basic-pace@rcs0: > - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar > issue >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10138/shard-kbl4/igt@gem_exec_fair@basic-p...@rcs0.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-kbl1/igt@gem_exec_fair@basic-p...@rcs0.html > > * igt@gem_exec_reloc@basic-wide-active@rcs0: > - shard-snb: NOTRUN -> [FAIL][10] ([i915#2389]) +2 similar issues >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-snb2/igt@gem_exec_reloc@basic-wide-act...@rcs0.html > > * igt@gem_exec_suspend@basic-s3: > - shard-kbl: NOTRUN -> [DMESG-WARN][11] ([i915#180]) >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-kbl1/igt@gem_exec_susp...@basic-s3.html > > * igt@gem_mmap_gtt@cpuset-basic-small-copy: > - shard-apl: [PASS][12] -> [INCOMPLETE][13] ([i915#3468]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10138/shard-apl6/igt@gem_mmap_...@cpuset-basic-small-copy.html >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-apl8/igt@gem_mmap_...@cpuset-basic-small-copy.html > - shard-skl: [PASS][14] -> [INCOMPLETE][15] ([i915#198] / > [i915#3468]) >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10138/shard-skl10/igt@gem_mmap_...@cpuset-basic-small-copy.html >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-skl3/igt@gem_mmap_...@cpuset-basic-small-copy.html > > * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy: > - shard-iclb: [PASS][16] -> [INCOMPLETE][17] ([i915#3468]) >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10138/shard-iclb6/igt@gem_mmap_...@cpuset-basic-small-copy-xy.html >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-iclb3/igt@gem_mmap_...@cpuset-basic-small-copy-xy.html > > * igt@gem_mmap_gtt@cpuset-big-copy-odd: > - shard-iclb: [PASS][18] -> [FAIL][19] ([i915#307]) >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10138/shard-iclb5/igt@gem_mmap_...@cpuset-big-copy-odd.html >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-iclb5/igt@gem_mmap_...@cpuset-big-copy-odd.html > > * igt@gem_mmap_gtt@cpuset-medium-copy-xy: > - shard-tglb: [PASS][20] -> [INCOMPLETE][21] ([i915#3468] / > [i915#750]) >[20]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10138/shard-tglb7/igt@gem_mmap_...@cpuset-medium-copy-xy.html >[21]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20207/shard-tglb1/igt@gem_mmap_...@cpuset-medium-copy-xy.html > > * igt@gem_mmap_gtt@fault-concurrent-x: > - shard-skl: NOTRUN -> [INCOMPLETE][22] ([i915#198] / > [i915#3468]) >[22]: > https://intel-gfx-ci.01.org/tree/d
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Get rid of fence error propagation (rev2)
== Series Details == Series: drm/i915: Get rid of fence error propagation (rev2) URL : https://patchwork.freedesktop.org/series/90891/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1893:21:expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1893:21:got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1893:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1207:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for bas
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Get rid of fence error propagation (rev2)
== Series Details ==
Series: drm/i915: Get rid of fence error propagation (rev2)
URL : https://patchwork.freedesktop.org/series/90891/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
20301afd39c9 drm/i915: Revert "drm/i915/gem: Asynchronous cmdparser"
-:6: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 686c7c35abc2 ("drm/i915/gem:
Asynchronous cmdparser")'
#6:
This reverts 686c7c35abc2 ("drm/i915/gem: Asynchronous cmdparser"). The
-:23: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 0edbb9ba1bfe ("drm/i915: Move
cmd parser pinning to execbuffer")'
#23:
This also reverts most of 0edbb9ba1bfe ("drm/i915: Move cmd parser
total: 2 errors, 0 warnings, 0 checks, 482 lines checked
b6fda25b1d9f Revert "drm/i915: Propagate errors on awaiting already signaled
fences"
-:34: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#34:
https://lore.kernel.org/dri-devel/20210602164149.391653-2-ja...@jlekstrand.net/
total: 0 errors, 1 warnings, 0 checks, 22 lines checked
7b00404854f1 drm/i915: Remove allow_alloc from i915_gem_object_get_sg*
-:6: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 0edbb9ba1bfe ("drm/i915: Move
cmd parser pinning to execbuffer")'
#6:
This reverts the rest of 0edbb9ba1bfe ("drm/i915: Move cmd parser
total: 1 errors, 0 warnings, 0 checks, 86 lines checked
8e472c11e36c drm/i915: Drop error handling from dma_fence_work
1013d3982bcb Revert "drm/i915: Skip over MI_NOOP when parsing"
-:6: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit a6c5e2aea704 ("drm/i915: Skip
over MI_NOOP when parsing")'
#6:
This reverts a6c5e2aea704 ("drm/i915: Skip over MI_NOOP when parsing").
total: 1 errors, 0 warnings, 0 checks, 83 lines checked
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[Intel-gfx] [PATCH 1/1] drm/i915/uc: Use platform specific defaults for GuC/HuC enabling
From: John Harrison The meaning of 'default' for the enable_guc module parameter has been updated to accurately reflect what is supported on current platforms. So start using the defaults instead of forcing everything off. Although, note that right now, the default is for everything to be off anyway. So this is not a change for current platforms. Signed-off-by: John Harrison Signed-off-by: Matthew Brost Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_params.c | 2 +- drivers/gpu/drm/i915/i915_params.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 0320878d96b0..e07f4cfea63a 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -160,7 +160,7 @@ i915_param_named_unsafe(edp_vswing, int, 0400, i915_param_named_unsafe(enable_guc, int, 0400, "Enable GuC load for GuC submission and/or HuC load. " "Required functionality can be selected using bitmask values. " - "(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load)"); + "(-1=auto [default], 0=disable, 1=GuC submission, 2=HuC load)"); i915_param_named(guc_log_level, int, 0400, "GuC firmware logging level. Requires GuC to be loaded. " diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 4a114a5ad000..f27eceb82c0f 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -59,7 +59,7 @@ struct drm_printer; param(int, disable_power_well, -1, 0400) \ param(int, enable_ips, 1, 0600) \ param(int, invert_brightness, 0, 0600) \ - param(int, enable_guc, 0, 0400) \ + param(int, enable_guc, -1, 0400) \ param(int, guc_log_level, -1, 0400) \ param(char *, guc_firmware_path, NULL, 0400) \ param(char *, huc_firmware_path, NULL, 0400) \ -- 2.28.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/1] Use platform specific defaults for GuC/HuC enabling
Reviewed a long time ago, resending for CI + to dri-devel. John Harrison (1): drm/i915/uc: Use platform specific defaults for GuC/HuC enabling drivers/gpu/drm/i915/i915_params.c | 2 +- drivers/gpu/drm/i915/i915_params.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 2.28.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 21/29] drm/i915/gem: Use the proto-context to handle create parameters (v2)
On Thu, Jun 3, 2021 at 2:32 AM Daniel Vetter wrote:
>
> On Thu, Jun 3, 2021 at 12:23 AM Jason Ekstrand wrote:
> >
> > On Mon, May 31, 2021 at 4:12 AM Daniel Vetter wrote:
> > >
> > > On Thu, May 27, 2021 at 11:26:42AM -0500, Jason Ekstrand wrote:
> > > > +static int set_proto_ctx_engines(struct drm_i915_file_private *fpriv,
> > > > + struct i915_gem_proto_context *pc,
> > > > + const struct drm_i915_gem_context_param
> > > > *args)
> > > > +{
> > > > + struct drm_i915_private *i915 = fpriv->dev_priv;
> > > > + struct set_proto_ctx_engines set = { .i915 = i915 };
> > > > + struct i915_context_param_engines __user *user =
> > > > + u64_to_user_ptr(args->value);
> > > > + unsigned int n;
> > > > + u64 extensions;
> > > > + int err;
> > > > +
> > > > + if (!args->size) {
> > > > + proto_context_free_user_engines(pc);
> > > > + memset(&pc->legacy_rcs_sseu, 0,
> > > > sizeof(pc->legacy_rcs_sseu));
> > >
> > > Hm I wonder whether we shouldn't put this into the cleanup helper, and
> > > then maybe call it proto_context_reset_user_engines()? I think that makes
> > > the entire user engines vs sseu flow a notch clearer again.
> >
> > I fought with myself over this. The other two callers of
> > free_user_engines() would be fine with clearing out the SSEU as well,
> > I think, but neither of them need it. I erred on the side of putting
> > it in the one place it's actually needed to make it clear what's going
> > on here. I can move it if you'd like.
>
> So I'm wondering about semantics here a bit, and whether this is all
> real, as in, used in real userspace:
>
> Instead of resetting engines here, shouldn't we just complain if
> there's more than one engines_set command, ever, on a context?
I don't think it's ever used. Let's kill it.
> > As a bit of a P.S., I really hate the SSEU handling. It's horrible.
> > If I had it to do all over again, SSEU would be a purly dynamic
> > context param that you aren't allowed to set at create time. But,
> > sadly, we're in the mess we're in. :-(
>
> Yeah it's rather annoying. If we go with "only one engines_set per ctx
> create", then maybe we could streamline the SSEU stuff some more too?
It certainly gets rid of this weird corner.
--Jason
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[Intel-gfx] ✗ Fi.CI.BAT: failure for shmem helpers for igt
== Series Details == Series: shmem helpers for igt URL : https://patchwork.freedesktop.org/series/90947/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10165 -> Patchwork_20273 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20273 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20273, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20273/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20273: ### IGT changes ### Possible regressions * igt@prime_vgem@basic-fence-mmap: - fi-bsw-nick:[PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-bsw-nick/igt@prime_v...@basic-fence-mmap.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20273/fi-bsw-nick/igt@prime_v...@basic-fence-mmap.html * igt@prime_vgem@basic-fence-read: - fi-bsw-kefka: [PASS][3] -> [INCOMPLETE][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20273/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html - fi-ilk-650: [PASS][5] -> [INCOMPLETE][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-ilk-650/igt@prime_v...@basic-fence-read.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20273/fi-ilk-650/igt@prime_v...@basic-fence-read.html - fi-elk-e7500: [PASS][7] -> [INCOMPLETE][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-elk-e7500/igt@prime_v...@basic-fence-read.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20273/fi-elk-e7500/igt@prime_v...@basic-fence-read.html - fi-bwr-2160:[PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-bwr-2160/igt@prime_v...@basic-fence-read.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20273/fi-bwr-2160/igt@prime_v...@basic-fence-read.html * igt@prime_vgem@basic-gtt: - fi-ilk-650: [PASS][11] -> [FAIL][12] +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-ilk-650/igt@prime_v...@basic-gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20273/fi-ilk-650/igt@prime_v...@basic-gtt.html - fi-elk-e7500: [PASS][13] -> [FAIL][14] +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-elk-e7500/igt@prime_v...@basic-gtt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20273/fi-elk-e7500/igt@prime_v...@basic-gtt.html - fi-bwr-2160:[PASS][15] -> [FAIL][16] +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-bwr-2160/igt@prime_v...@basic-gtt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20273/fi-bwr-2160/igt@prime_v...@basic-gtt.html * igt@prime_vgem@basic-read: - fi-bsw-nick:[PASS][17] -> [FAIL][18] +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-bsw-nick/igt@prime_v...@basic-read.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20273/fi-bsw-nick/igt@prime_v...@basic-read.html - fi-bsw-kefka: [PASS][19] -> [FAIL][20] +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-bsw-kefka/igt@prime_v...@basic-read.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20273/fi-bsw-kefka/igt@prime_v...@basic-read.html * igt@prime_vgem@basic-write: - fi-pnv-d510:[PASS][21] -> [FAIL][22] +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-pnv-d510/igt@prime_v...@basic-write.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20273/fi-pnv-d510/igt@prime_v...@basic-write.html Known issues Here are the changes found in Patchwork_20273 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600:NOTRUN -> [SKIP][23] ([fdo#109271]) +17 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20273/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7500u: [PASS][24] -> [DMESG-FAIL][25] ([i915#165]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20273/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
Re: [Intel-gfx] [PATCH 15/20] drm/i915/guc: Ensure H2G buffer updates visible before tail update
On Thu, Jun 03, 2021 at 11:44:57AM +0200, Michal Wajdeczko wrote:
>
>
> On 03.06.2021 07:16, Matthew Brost wrote:
> > Ensure H2G buffer updates are visible before descriptor tail updates by
> > inserting a barrier between the H2G buffer update and the tail. The
> > barrier is simple wmb() for SMEM and is register write for LMEM. This is
> > needed if more than 1 H2G can be inflight at once.
> >
> > If this barrier is not inserted it is possible the descriptor tail
> > update is scene by the GuC before H2G buffer update which results in the
> > GuC reading a corrupt H2G value. This can bring down the H2G channel
> > among other bad things.
> >
> > Signed-off-by: Matthew Brost
> > Cc: Michal Wajdeczko
> > Reviewed-by: John Harrison
> > ---
> > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 28 +++
> > 1 file changed, 28 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > index 80976fe40fbf..31f83956bfc3 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> > @@ -328,6 +328,28 @@ static u32 ct_get_next_fence(struct intel_guc_ct *ct)
> > return ++ct->requests.last_fence;
> > }
> >
> > +static void write_barrier(struct intel_guc_ct *ct)
> > +{
> > + struct intel_guc *guc = ct_to_guc(ct);
> > + struct intel_gt *gt = guc_to_gt(guc);
> > +
> > + if (i915_gem_object_is_lmem(guc->ct.vma->obj)) {
> > + GEM_BUG_ON(guc->send_regs.fw_domains);
> > + /*
> > +* This register is used by the i915 and GuC for MMIO based
> > +* communication. Once we are in this code CTBs are the only
> > +* method the i915 uses to communicate with the GuC so it is
> > +* safe to write to this register (a value of 0 is NOP for MMIO
> > +* communication). If we ever start mixing CTBs and MMIOs a new
> > +* register will have to be chosen.
> > +*/
> > + intel_uncore_write_fw(gt->uncore, GEN11_SOFT_SCRATCH(0), 0);
>
> can't we at least start with SOFT_SCRATCH register that is not used for
> GuC MMIO based communication on Gen12 LMEM platforms? see [1]
>
We likely can use this but I really don't feel comfortable switching the
register without some more testing first (e.g. let's change in this in
internal, let it soak for bit, then make the change upstream).
> I really don't feel comfortable that we are touching a register that
> elsewhere is protected with the mutex. And mixing CTBs and MMIO is not
> far away.
>
The only code that mixes CTBs and MMIOs is SRIOV which is a ways away
from landing.
Matt
> Michal
>
> [1]
> https://lore.kernel.org/intel-gfx/51b9bd05-7d6f-29f1-de0f-3a14bade6...@intel.com/
>
> > + } else {
> > + /* wmb() sufficient for a barrier if in smem */
> > + wmb();
> > + }
> > +}
> > +
> > /**
> > * DOC: CTB Host to GuC request
> > *
> > @@ -411,6 +433,12 @@ static int ct_write(struct intel_guc_ct *ct,
> > }
> > GEM_BUG_ON(tail > size);
> >
> > + /*
> > +* make sure H2G buffer update and LRC tail update (if this triggering a
> > +* submission) are visible before updating the descriptor tail
> > +*/
> > + write_barrier(ct);
> > +
> > /* now update desc tail (back in bytes) */
> > desc->tail = tail * 4;
> > return 0;
> >
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Re: [Intel-gfx] [PATCH 1/1] drm/i915: Introduce i915_sched_engine object
On Thu, Jun 03, 2021 at 11:05:15AM +0200, Daniel Vetter wrote: > On Thu, Jun 3, 2021 at 5:30 AM Matthew Brost wrote: > > > > On Mon, May 31, 2021 at 10:31:53AM +0200, Daniel Vetter wrote: > > > On Thu, May 27, 2021 at 4:19 PM Matthew Brost > > > wrote: > > > > > > > > On Thu, May 27, 2021 at 10:41:10AM +0100, Tvrtko Ursulin wrote: > > > > > > > > > > On 26/05/2021 21:03, Matthew Brost wrote: > > > > > > Introduce i915_sched_engine object which is lower level data > > > > > > structure > > > > > > that i915_scheduler / generic code can operate on without touching > > > > > > execlist specific structures. This allows additional submission > > > > > > backends > > > > > > to be added without breaking the layering. > > > > > > > > > > > > This is a bit of detour to integrating the i915 with the DRM > > > > > > scheduler > > > > > > but this object will still exist when the DRM scheduler lands in the > > > > > > i915. It will however look a bit different. It will encapsulate the > > > > > > drm_gpu_scheduler object plus and common variables (to the backends) > > > > > > related to scheduling. Regardless this is a step in the right > > > > > > direction. > > > > > > > > > > It looks like pretty much the same concept Chris implemented in > > > > > upstream(*) before they got removed. Both series move the scheduling > > > > > lists into a new object, be it i915_sched, or i915_sched_engine. > > > > > There probably are some differences but without looking much deeper > > > > > it is hard to say if they are important. > > > > > > > > > > Were you aware of this series and were there any technical objections > > > > > to it? > > > > > > > > > > > > > I haven't dug to deep into the series but yes, I am aware of this > > > > series. I > > > > merged my series to internal while Chris had this inflight upstream. > > > > They do > > > > have similar concepts of i915_sched_engine object. > > > > > > Imo both of them are a detour since it's not drm/scheduler, but also > > > we need one and this one here is the one we have so I'm not seeing the > > > point of repainting that bikeshed in different colors. Imo much better > > > if we just land this and then head as straight as possible towards > > > drm/scheduler as the interface. > > > > > > > Agree. > > > > > Now a bit of polish here might be good, but in entirely different ways: > > > - I think splitting the patch into the purely mechanical code movement > > > and addition of the new callbacks would be good. Should slice really > > > well I hope, so not much work. > > > > > > > This patch is basically find / replace in the sense it moves existing > > variables + vfuncs from one structure to another. It does add a few > > wrappers so not to touch the new structures variables but nothing else > > beyond that. IMO there really isn't a logical split point. > > The thing is, it's big, and in big patches like this it's easy to hide > an accidental change. And then it's really tricky to found out what > exactly happened. > > The other thing is, this is supposed to be entirely mechanical > refactors, piled up into a single patch. This should split easily, and > every step should be fully functional, if it doesn't, there's a > problem in the patch. > Ah, I see your point. We discussed this today in sync on upstreaming the GuC code and I will split this patch into a series of smaller ones which should result in the same full tree diff in the end + make the review quite a bit easier. Matt > Pretty much the only reason I don't care much here is that we're going > to redo this all again anyway, but in generally more splitting and > less smashing everything into one patch is better. > -Daniel > > > > > > - Proper kerneldoc for at least anything new around datastructures. > > > That means a) check the header is pulled in somewhere suitable in > > > i915.rst b) minimal fixes for any warnings it throws c) then do right > > > in anything new. Especially with datastructure stuff like > > > locking/lifetime rules or rules around callbacks and these big ticket > > > items are important to document and cross reference, and I think the > > > pain for doing a)&b) for these is worth it. > > > > > > > I'll add some kerenl doc in my next post of this patch. > > > > Matt > > > > > > > Because there do appear to be some extra advantages in the dropped > > > > > work, like consolidating finding of active request and moving some > > > > > other bits to be backend agnostic. > > > > > > > > > > > > > After briefly looking at this series most of Chris's changes are not > > > > relevent if > > > > we move to DRM scheduler. All of the the below series [1] and internal > > > > is based > > > > this code not Chris's. I don't see the point revisiting Chris's old > > > > patches when > > > > the goal is to merge GuC submission quickly, rework it is place as > > > > needed, and > > > > the long term goal is to move to the DRM scheduler. > > > > > > Agreed. > > > > > > Cheers, Daniel > > >
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for shmem helpers for igt
== Series Details ==
Series: shmem helpers for igt
URL : https://patchwork.freedesktop.org/series/90947/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
16d2d93866c0 drm/gem-shmem-helper: Export drm_gem_shmem_funcs
-:49: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by:
Daniel Vetter '
total: 0 errors, 1 warnings, 0 checks, 22 lines checked
9b0d01123c46 drm/shmem-helper: Switch to vmf_insert_pfn
-:52: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by:
Daniel Vetter '
total: 0 errors, 1 warnings, 0 checks, 24 lines checked
03c134e820dc drm/shmem-helper: Align to page size in dumb_create
-:37: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by:
Daniel Vetter '
total: 0 errors, 1 warnings, 0 checks, 15 lines checked
826ca3131cf3 drm/vgem: use shmem helpers
-:22: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 0cf2ef46c6c0 ("drm/shmem-helper:
Use cached mappings by default")'
#22:
v4: I got tricked by 0cf2ef46c6c0 ("drm/shmem-helper: Use cached
-:335: WARNING:TYPO_SPELLING: 'wont' may be misspelled - perhaps 'won't'?
#335: FILE: drivers/gpu/drm/vgem/vgem_drv.c:96:
+ * access ioctls, there must use coherent memory or dma-buf sharing just wont
-:444: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: Daniel Vetter ' != 'Signed-off-by:
Daniel Vetter '
total: 1 errors, 2 warnings, 0 checks, 395 lines checked
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Re: [Intel-gfx] [PATCH v2 1/4] drm/gem-shmem-helper: Export drm_gem_shmem_funcs
Hi
Am 03.06.21 um 17:03 schrieb Daniel Vetter:
Drivers which need to overwrite the drm_driver->gem_create_object hook
need this. Specifically vgem, which wants wc mode, but everything else
is fine as-is.
Signed-off-by: Daniel Vetter
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
---
drivers/gpu/drm/drm_gem_shmem_helper.c | 3 ++-
include/drm/drm_gem_shmem_helper.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c
b/drivers/gpu/drm/drm_gem_shmem_helper.c
index 6d625cee7a6a..4439004e62fe 100644
--- a/drivers/gpu/drm/drm_gem_shmem_helper.c
+++ b/drivers/gpu/drm/drm_gem_shmem_helper.c
@@ -24,7 +24,7 @@
* allocated using anonymous pageable memory.
*/
-static const struct drm_gem_object_funcs drm_gem_shmem_funcs = {
+const struct drm_gem_object_funcs drm_gem_shmem_funcs = {
.free = drm_gem_shmem_free_object,
.print_info = drm_gem_shmem_print_info,
.pin = drm_gem_shmem_pin,
@@ -34,6 +34,7 @@ static const struct drm_gem_object_funcs drm_gem_shmem_funcs
= {
.vunmap = drm_gem_shmem_vunmap,
.mmap = drm_gem_shmem_mmap,
};
+EXPORT_SYMBOL(drm_gem_shmem_funcs);
No that's not needed. If you leave out the funcs pointer in your
gem_create_object, __drm_gem_shmem_create() will set this default for
you. [1] So please drop this patch.
Best regards
Thomas
[1]
https://elixir.bootlin.com/linux/v5.12/source/drivers/gpu/drm/drm_gem_shmem_helper.c#L56
static struct drm_gem_shmem_object *
__drm_gem_shmem_create(struct drm_device *dev, size_t size, bool private)
diff --git a/include/drm/drm_gem_shmem_helper.h
b/include/drm/drm_gem_shmem_helper.h
index 434328d8a0d9..b29667f2b8a3 100644
--- a/include/drm/drm_gem_shmem_helper.h
+++ b/include/drm/drm_gem_shmem_helper.h
@@ -106,6 +106,7 @@ struct drm_gem_shmem_object {
#define to_drm_gem_shmem_obj(obj) \
container_of(obj, struct drm_gem_shmem_object, base)
+extern const struct drm_gem_object_funcs drm_gem_shmem_funcs;
struct drm_gem_shmem_object *drm_gem_shmem_create(struct drm_device *dev,
size_t size);
void drm_gem_shmem_free_object(struct drm_gem_object *obj);
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer
OpenPGP_signature
Description: OpenPGP digital signature
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Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
On Thu, 03 Jun 2021, "Manna, Animesh" wrote:
>> -Original Message-
>> From: Jani Nikula
>> Sent: Thursday, June 3, 2021 3:10 PM
>> To: Roper, Matthew D ; intel-
>> g...@lists.freedesktop.org
>> Cc: Manna, Animesh ; Navare, Manasi D
>> ; Kulkarni, Vandita
>> Subject: Re: [Intel-gfx] [CI 15/19] drm/i915/bigjoiner: atomic commit changes
>> for uncompressed joiner
>>
>> On Fri, 14 May 2021, Matt Roper wrote:
>> > From: Animesh Manna
>> >
>> > Respective bit for master or slave to be set for uncompressed
>> > bigjoiner in dss_ctl1 register.
>>
>> I was looking at the changes here due to a static checker complaint, and I
>> think
>> there are a number of issues here. Some more serious than others, and some
>> predate the patch.
>>
>> Comments inline.
>>
>> > Cc: Manasi Navare
>> > Signed-off-by: Animesh Manna
>> > Signed-off-by: Clinton Taylor
>> > Signed-off-by: Matt Roper
>> > Reviewed-by: Manasi Navare
>> > ---
>> > drivers/gpu/drm/i915/display/intel_display.c | 6 +++
>> > drivers/gpu/drm/i915/display/intel_vdsc.c| 40 +++-
>> > drivers/gpu/drm/i915/display/intel_vdsc.h| 2 +
>> > drivers/gpu/drm/i915/i915_reg.h | 2 +
>> > 4 files changed, 49 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> > b/drivers/gpu/drm/i915/display/intel_display.c
>> > index b5fd721137d3..422b59ebf6dc 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> > @@ -3411,6 +3411,7 @@ static void icl_ddi_bigjoiner_pre_enable(struct
>> intel_atomic_state *state,
>> > const struct intel_crtc_state
>> *crtc_state) {
>> >struct intel_crtc *master = to_intel_crtc(crtc_state->uapi.crtc);
>> > + struct drm_i915_private *dev_priv = to_i915(master->base.dev);
>> >struct intel_crtc_state *master_crtc_state;
>> >struct drm_connector_state *conn_state;
>> >struct drm_connector *conn;
>> > @@ -3444,6 +3445,9 @@ static void icl_ddi_bigjoiner_pre_enable(struct
>> intel_atomic_state *state,
>> >/* and DSC on slave */
>> >intel_dsc_enable(NULL, crtc_state);
>> >}
>> > +
>> > + if (DISPLAY_VER(dev_priv) >= 13)
>> > + intel_uncompressed_joiner_enable(crtc_state);
>> > }
>> >
>> > static void hsw_crtc_enable(struct intel_atomic_state *state, @@
>> > -6250,6 +6254,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
>> >}
>> >
>> >intel_dsc_get_config(pipe_config);
>> > + if (DISPLAY_VER(dev_priv) >= 13 && !pipe_config-
>> >dsc.compression_enable)
>> > + intel_uncompressed_joiner_get_config(pipe_config);
>> >
>> >if (!active) {
>> >/* bigjoiner slave doesn't enable transcoder */ diff --git
>> > a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > index adcd6752f919..efc3184d8315 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > @@ -1021,6 +1021,22 @@ static i915_reg_t dss_ctl2_reg(const struct
>> intel_crtc_state *crtc_state)
>> >return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2;
>> > }
>> >
>> > +void intel_uncompressed_joiner_enable(const struct intel_crtc_state
>> > +*crtc_state)
>>
>> Naming. Basically for any new function, the function name prefix should match
>> the file name. intel_vdsc.[ch] should have functions prefixed
>> intel_vdsc_*(). This
>> is where we're headed to increase clarity.
>>
>> intel_uncompressed_*() is something completely different.
>>
>> Granted, here we already have intel_dsc_*() in intel_vdsc.c. We should
>> probably
>> stick with intel_dsc_*(). A possible function or file rename is not out of
>> the
>> question, but that's a separate matter.
>
> As there is not separate register for uncompressed joiner, using bitfield of
> dsc register only the function name can be changed to
> intel_dsc_uncompressed_joiner_enable().
>
>>
>> > +{
>> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > + u32 dss_ctl1_val = 0;
>> > +
>> > + if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) {
>> > + if (crtc_state->bigjoiner_slave)
>> > + dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
>> > + else
>> > + dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
>> > +
>> > + intel_de_write(dev_priv, dss_ctl1_reg(crtc_state),
>> > dss_ctl1_val);
>> > + }
>> > +}
>> > +
>> > void intel_dsc_enable(struct intel_encoder *encoder,
>> > const struct intel_crtc_state *crtc_state) { @@ -1060,13
>> > +1076,35 @@ void intel_dsc_disable(const struct intel_crtc_state
>> *old_crtc_state)
>> >struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>> >struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> >
>> >
[Intel-gfx] [PATCH 5/5] Revert "drm/i915: Skip over MI_NOOP when parsing"
This reverts a6c5e2aea704 ("drm/i915: Skip over MI_NOOP when parsing").
It complicates the batch parsing code a bit and increases indentation
for no reason other than fast-skipping a command that userspace uses
only rarely. Sure, there may be IGT tests that fill batches with NOOPs
but that's not a case we should optimize for in the kernel. We should
optimize for code clarity instead.
Signed-off-by: Jason Ekstrand
Reviewed-by: Jon Bloomfield
Acked-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 67 +-
1 file changed, 34 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 056a233f443b4..8d34f05d22b75 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -1470,42 +1470,43 @@ int intel_engine_cmd_parser(struct intel_engine_cs
*engine,
* space. Parsing should be faster in some cases this way.
*/
batch_end = cmd + batch_length / sizeof(*batch_end);
- while (*cmd != MI_BATCH_BUFFER_END) {
- u32 length = 1;
-
- if (*cmd != MI_NOOP) { /* MI_NOOP == 0 */
- desc = find_cmd(engine, *cmd, desc, &default_desc);
- if (!desc) {
- DRM_DEBUG("CMD: Unrecognized command:
0x%08X\n", *cmd);
- ret = -EINVAL;
- break;
- }
+ do {
+ u32 length;
- if (desc->flags & CMD_DESC_FIXED)
- length = desc->length.fixed;
- else
- length = (*cmd & desc->length.mask) +
LENGTH_BIAS;
+ if (*cmd == MI_BATCH_BUFFER_END)
+ break;
- if ((batch_end - cmd) < length) {
- DRM_DEBUG("CMD: Command length exceeds batch
length: 0x%08X length=%u batchlen=%td\n",
- *cmd,
- length,
- batch_end - cmd);
- ret = -EINVAL;
- break;
- }
+ desc = find_cmd(engine, *cmd, desc, &default_desc);
+ if (!desc) {
+ DRM_DEBUG("CMD: Unrecognized command: 0x%08X\n", *cmd);
+ ret = -EINVAL;
+ break;
+ }
- if (!check_cmd(engine, desc, cmd, length)) {
- ret = -EACCES;
- break;
- }
+ if (desc->flags & CMD_DESC_FIXED)
+ length = desc->length.fixed;
+ else
+ length = (*cmd & desc->length.mask) + LENGTH_BIAS;
- if (cmd_desc_is(desc, MI_BATCH_BUFFER_START)) {
- ret = check_bbstart(cmd, offset, length,
batch_length,
- batch_addr, shadow_addr,
- jump_whitelist);
- break;
- }
+ if ((batch_end - cmd) < length) {
+ DRM_DEBUG("CMD: Command length exceeds batch length:
0x%08X length=%u batchlen=%td\n",
+ *cmd,
+ length,
+ batch_end - cmd);
+ ret = -EINVAL;
+ break;
+ }
+
+ if (!check_cmd(engine, desc, cmd, length)) {
+ ret = -EACCES;
+ break;
+ }
+
+ if (cmd_desc_is(desc, MI_BATCH_BUFFER_START)) {
+ ret = check_bbstart(cmd, offset, length, batch_length,
+ batch_addr, shadow_addr,
+ jump_whitelist);
+ break;
}
if (!IS_ERR_OR_NULL(jump_whitelist))
@@ -1518,7 +1519,7 @@ int intel_engine_cmd_parser(struct intel_engine_cs
*engine,
ret = -EINVAL;
break;
}
- }
+ } while (1);
if (trampoline) {
/*
--
2.31.1
___
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[Intel-gfx] [PATCH 4/5] drm/i915: Drop error handling from dma_fence_work
Asynchronous command parsing was the only thing which ever returned a
non-zero error. With that gone, we can drop the error handling from
dma_fence_work.
Signed-off-by: Jason Ekstrand
Reviewed-by: Jon Bloomfield
Acked-by: Daniel Vetter
---
drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 4 +---
drivers/gpu/drm/i915/i915_sw_fence_work.c | 5 +
drivers/gpu/drm/i915/i915_sw_fence_work.h | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 3 +--
4 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
index daf9284ef1f54..f0435c6feb68b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
@@ -24,13 +24,11 @@ static void __do_clflush(struct drm_i915_gem_object *obj)
i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
}
-static int clflush_work(struct dma_fence_work *base)
+static void clflush_work(struct dma_fence_work *base)
{
struct clflush *clflush = container_of(base, typeof(*clflush), base);
__do_clflush(clflush->obj);
-
- return 0;
}
static void clflush_release(struct dma_fence_work *base)
diff --git a/drivers/gpu/drm/i915/i915_sw_fence_work.c
b/drivers/gpu/drm/i915/i915_sw_fence_work.c
index a3a81bb8f2c36..5b33ef23d54c9 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence_work.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence_work.c
@@ -16,11 +16,8 @@ static void fence_complete(struct dma_fence_work *f)
static void fence_work(struct work_struct *work)
{
struct dma_fence_work *f = container_of(work, typeof(*f), work);
- int err;
- err = f->ops->work(f);
- if (err)
- dma_fence_set_error(&f->dma, err);
+ f->ops->work(f);
fence_complete(f);
dma_fence_put(&f->dma);
diff --git a/drivers/gpu/drm/i915/i915_sw_fence_work.h
b/drivers/gpu/drm/i915/i915_sw_fence_work.h
index 2c409f11c5c59..d56806918d131 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence_work.h
+++ b/drivers/gpu/drm/i915/i915_sw_fence_work.h
@@ -17,7 +17,7 @@ struct dma_fence_work;
struct dma_fence_work_ops {
const char *name;
- int (*work)(struct dma_fence_work *f);
+ void (*work)(struct dma_fence_work *f);
void (*release)(struct dma_fence_work *f);
};
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 0f227f28b2802..5b9dce0f443b0 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -300,14 +300,13 @@ struct i915_vma_work {
unsigned int flags;
};
-static int __vma_bind(struct dma_fence_work *work)
+static void __vma_bind(struct dma_fence_work *work)
{
struct i915_vma_work *vw = container_of(work, typeof(*vw), base);
struct i915_vma *vma = vw->vma;
vma->ops->bind_vma(vw->vm, &vw->stash,
vma, vw->cache_level, vw->flags);
- return 0;
}
static void __vma_release(struct dma_fence_work *work)
--
2.31.1
___
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[Intel-gfx] [PATCH 3/5] drm/i915: Remove allow_alloc from i915_gem_object_get_sg*
This reverts the rest of 0edbb9ba1bfe ("drm/i915: Move cmd parser
pinning to execbuffer"). Now that the only user of i915_gem_object_get_sg
without allow_alloc has been removed, we can drop the parameter. This
portion of the revert was broken into its own patch to aid review.
Signed-off-by: Jason Ekstrand
Cc: Maarten Lankhorst
Reviewed-by: Jon Bloomfield
Acked-by: Daniel Vetter
---
drivers/gpu/drm/i915/gem/i915_gem_object.h | 10 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 21 -
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
3 files changed, 10 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 2ebd79537aea9..329d848f3ff6d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -339,22 +339,22 @@ struct scatterlist *
__i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
struct i915_gem_object_page_iter *iter,
unsigned int n,
-unsigned int *offset, bool allow_alloc);
+unsigned int *offset);
static inline struct scatterlist *
i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
unsigned int n,
- unsigned int *offset, bool allow_alloc)
+ unsigned int *offset)
{
- return __i915_gem_object_get_sg(obj, &obj->mm.get_page, n, offset,
allow_alloc);
+ return __i915_gem_object_get_sg(obj, &obj->mm.get_page, n, offset);
}
static inline struct scatterlist *
i915_gem_object_get_sg_dma(struct drm_i915_gem_object *obj,
unsigned int n,
- unsigned int *offset, bool allow_alloc)
+ unsigned int *offset)
{
- return __i915_gem_object_get_sg(obj, &obj->mm.get_dma_page, n, offset,
allow_alloc);
+ return __i915_gem_object_get_sg(obj, &obj->mm.get_dma_page, n, offset);
}
struct page *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 6444e097016da..f234bd5bf22fc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -466,8 +466,7 @@ struct scatterlist *
__i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
struct i915_gem_object_page_iter *iter,
unsigned int n,
-unsigned int *offset,
-bool allow_alloc)
+unsigned int *offset)
{
const bool dma = iter == &obj->mm.get_dma_page;
struct scatterlist *sg;
@@ -490,9 +489,6 @@ __i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
if (n < READ_ONCE(iter->sg_idx))
goto lookup;
- if (!allow_alloc)
- goto manual_lookup;
-
mutex_lock(&iter->lock);
/* We prefer to reuse the last sg so that repeated lookup of this
@@ -542,16 +538,7 @@ __i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
if (unlikely(n < idx)) /* insertion completed by another thread */
goto lookup;
- goto manual_walk;
-
-manual_lookup:
- idx = 0;
- sg = obj->mm.pages->sgl;
- count = __sg_page_count(sg);
-
-manual_walk:
- /*
-* In case we failed to insert the entry into the radixtree, we need
+ /* In case we failed to insert the entry into the radixtree, we need
* to look beyond the current sg.
*/
while (idx + count <= n) {
@@ -598,7 +585,7 @@ i915_gem_object_get_page(struct drm_i915_gem_object *obj,
unsigned int n)
GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
- sg = i915_gem_object_get_sg(obj, n, &offset, true);
+ sg = i915_gem_object_get_sg(obj, n, &offset);
return nth_page(sg_page(sg), offset);
}
@@ -624,7 +611,7 @@ i915_gem_object_get_dma_address_len(struct
drm_i915_gem_object *obj,
struct scatterlist *sg;
unsigned int offset;
- sg = i915_gem_object_get_sg_dma(obj, n, &offset, true);
+ sg = i915_gem_object_get_sg_dma(obj, n, &offset);
if (len)
*len = sg_dma_len(sg) - (offset << PAGE_SHIFT);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 10c23a749a950..46c98887f17e3 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -1494,7 +1494,7 @@ intel_partial_pages(const struct i915_ggtt_view *view,
if (ret)
goto err_sg_alloc;
- iter = i915_gem_object_get_sg_dma(obj, view->partial.offset, &offset,
true);
+ iter = i915_gem_object_get_sg_dma(obj, view->partial.offset, &offset);
GEM_BUG_ON(!iter);
sg = st->sgl;
--
2.31.1
___
Intel-gfx mailing list
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[Intel-gfx] [PATCH 2/5] Revert "drm/i915: Propagate errors on awaiting already signaled fences"
This reverts commit 9e31c1fe45d555a948ff66f1f0e3fe1f83ca63f7. Ever
since that commit, we've been having issues where a hang in one client
can propagate to another. In particular, a hang in an app can propagate
to the X server which causes the whole desktop to lock up.
Error propagation along fences sound like a good idea, but as your bug
shows, surprising consequences, since propagating errors across security
boundaries is not a good thing.
What we do have is track the hangs on the ctx, and report information to
userspace using RESET_STATS. That's how arb_robustness works. Also, if my
understanding is still correct, the EIO from execbuf is when your context
is banned (because not recoverable or too many hangs). And in all these
cases it's up to userspace to figure out what is all impacted and should
be reported to the application, that's not on the kernel to guess and
automatically propagate.
What's more, we're also building more features on top of ctx error
reporting with RESET_STATS ioctl: Encrypted buffers use the same, and the
userspace fence wait also relies on that mechanism. So it is the path
going forward for reporting gpu hangs and resets to userspace.
So all together that's why I think we should just bury this idea again as
not quite the direction we want to go to, hence why I think the revert is
the right option here.
For backporters: Please note that you _must_ have a backport of
https://lore.kernel.org/dri-devel/20210602164149.391653-2-ja...@jlekstrand.net/
for otherwise backporting just this patch opens up a security bug.
v2: Augment commit message. Also restore Jason's sob that I
accidentally lost.
v3: Add a note for backporters
Signed-off-by: Jason Ekstrand
Reported-by: Marcin Slusarz
Cc: # v5.6+
Cc: Jason Ekstrand
Cc: Marcin Slusarz
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3080
Fixes: 9e31c1fe45d5 ("drm/i915: Propagate errors on awaiting already signaled
fences")
Acked-by: Daniel Vetter
Reviewed-by: Jon Bloomfield
---
drivers/gpu/drm/i915/i915_request.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 970d8f4986bbe..b796197c07722 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1426,10 +1426,8 @@ i915_request_await_execution(struct i915_request *rq,
do {
fence = *child++;
- if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
- i915_sw_fence_set_error_once(&rq->submit, fence->error);
+ if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
continue;
- }
if (fence->context == rq->fence.context)
continue;
@@ -1527,10 +1525,8 @@ i915_request_await_dma_fence(struct i915_request *rq,
struct dma_fence *fence)
do {
fence = *child++;
- if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
- i915_sw_fence_set_error_once(&rq->submit, fence->error);
+ if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
continue;
- }
/*
* Requests on the same timeline are explicitly ordered, along
--
2.31.1
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[Intel-gfx] [PATCH 0/5] drm/i915: Get rid of fence error propagation (v2)
Fence error propagation is sketchy at best. Instead of explicitly handling fences which might have errors set in the code which is aware of errors, we just kick them down the line and hope that userspace knows what to do when a wait eventually fails. This is sketchy at best because most userspace isn't prepared to handle errors in those places. To make things worse, it allows errors to propagate across processes in unpredictable ways. This is causing hangs in one client to kill X11. Unfortunately, there's no quick path from here to there thanks to the fact that we're now running the command parser asynchronously and relying on fence errors for when it fails. This series first gets rid of asynchronous command parsing and then cleans up from there. There was never any real use-case for asynchronous parsing and the platforms that rely heavily on the command parser are old enough (Gen7) that, when we changed the way the command parser works, it wasn't really a change anyone was asking for anyway. I think we probably want this whole mess back-ported. I'm happy to take suggestions on the strategy there because the history there is a bit annoying and I'm not 100% sure where the Linux release cuts land. In any case, I'm happy to make a version of this series per-release if needed for Greg to back-port. v2 (Daniel Vetter): - Re-order to put the reverts first - Add ACKs from Daniel - Add better CC and Fixes tags Cc: Daniel Vetter Cc: Jon Bloomfield Jason Ekstrand (5): drm/i915: Revert "drm/i915/gem: Asynchronous cmdparser" Revert "drm/i915: Propagate errors on awaiting already signaled fences" drm/i915: Remove allow_alloc from i915_gem_object_get_sg* drm/i915: Drop error handling from dma_fence_work Revert "drm/i915: Skip over MI_NOOP when parsing" drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 4 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 227 +- drivers/gpu/drm/i915/gem/i915_gem_object.h| 10 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 21 +- .../i915/gem/selftests/i915_gem_execbuffer.c | 4 + drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- drivers/gpu/drm/i915/i915_cmd_parser.c| 199 --- drivers/gpu/drm/i915/i915_drv.h | 7 +- drivers/gpu/drm/i915/i915_request.c | 8 +- drivers/gpu/drm/i915/i915_sw_fence_work.c | 5 +- drivers/gpu/drm/i915/i915_sw_fence_work.h | 2 +- drivers/gpu/drm/i915/i915_vma.c | 3 +- 12 files changed, 141 insertions(+), 351 deletions(-) -- 2.31.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/5] drm/i915: Revert "drm/i915/gem: Asynchronous cmdparser"
This reverts 686c7c35abc2 ("drm/i915/gem: Asynchronous cmdparser"). The
justification for this commit in the git history was a vague comment
about getting it out from under the struct_mutex. While this may
improve perf for some workloads on Gen7 platforms where we rely on the
command parser for features such as indirect rendering, no numbers were
provided to prove such an improvement. It claims to closed two
gitlab/bugzilla issues but with no explanation whatsoever as to why or
what bug it's fixing.
Meanwhile, by moving command parsing off to an async callback, it leaves
us with a problem of what to do on error. When things were synchronous,
EXECBUFFER2 would fail with an error code if parsing failed. When
moving it to async, we needed another way to handle that error and the
solution employed was to set an error on the dma_fence and then trust
that said error gets propagated to the client eventually. Moving back
to synchronous will help us untangle the fence error propagation mess.
This also reverts most of 0edbb9ba1bfe ("drm/i915: Move cmd parser
pinning to execbuffer") which is a refactor of some of our allocation
paths for asynchronous parsing. Now that everything is synchronous, we
don't need it.
v2 (Daniel Vetter):
- Add stabel Cc and Fixes tag
Signed-off-by: Jason Ekstrand
Cc: # v5.6+
Fixes: 9e31c1fe45d5 ("drm/i915: Propagate errors on awaiting already signaled
fences")
Cc: Maarten Lankhorst
Reviewed-by: Jon Bloomfield
Acked-by: Daniel Vetter
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 227 +-
.../i915/gem/selftests/i915_gem_execbuffer.c | 4 +
drivers/gpu/drm/i915/i915_cmd_parser.c| 132 +-
drivers/gpu/drm/i915/i915_drv.h | 7 +-
4 files changed, 91 insertions(+), 279 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 297143511f99b..a49da4b24d4d4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -25,10 +25,8 @@
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
#include "i915_gem_ioctls.h"
-#include "i915_sw_fence_work.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
-#include "i915_memcpy.h"
struct eb_vma {
struct i915_vma *vma;
@@ -1456,6 +1454,10 @@ static u32 *reloc_gpu(struct i915_execbuffer *eb,
int err;
struct intel_engine_cs *engine = eb->engine;
+ /* If we need to copy for the cmdparser, we will stall anyway */
+ if (eb_use_cmdparser(eb))
+ return ERR_PTR(-EWOULDBLOCK);
+
if (!reloc_can_use_engine(engine)) {
engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0];
if (!engine)
@@ -2372,217 +2374,6 @@ shadow_batch_pin(struct i915_execbuffer *eb,
return vma;
}
-struct eb_parse_work {
- struct dma_fence_work base;
- struct intel_engine_cs *engine;
- struct i915_vma *batch;
- struct i915_vma *shadow;
- struct i915_vma *trampoline;
- unsigned long batch_offset;
- unsigned long batch_length;
- unsigned long *jump_whitelist;
- const void *batch_map;
- void *shadow_map;
-};
-
-static int __eb_parse(struct dma_fence_work *work)
-{
- struct eb_parse_work *pw = container_of(work, typeof(*pw), base);
- int ret;
- bool cookie;
-
- cookie = dma_fence_begin_signalling();
- ret = intel_engine_cmd_parser(pw->engine,
- pw->batch,
- pw->batch_offset,
- pw->batch_length,
- pw->shadow,
- pw->jump_whitelist,
- pw->shadow_map,
- pw->batch_map);
- dma_fence_end_signalling(cookie);
-
- return ret;
-}
-
-static void __eb_parse_release(struct dma_fence_work *work)
-{
- struct eb_parse_work *pw = container_of(work, typeof(*pw), base);
-
- if (!IS_ERR_OR_NULL(pw->jump_whitelist))
- kfree(pw->jump_whitelist);
-
- if (pw->batch_map)
- i915_gem_object_unpin_map(pw->batch->obj);
- else
- i915_gem_object_unpin_pages(pw->batch->obj);
-
- i915_gem_object_unpin_map(pw->shadow->obj);
-
- if (pw->trampoline)
- i915_active_release(&pw->trampoline->active);
- i915_active_release(&pw->shadow->active);
- i915_active_release(&pw->batch->active);
-}
-
-static const struct dma_fence_work_ops eb_parse_ops = {
- .name = "eb_parse",
- .work = __eb_parse,
- .release = __eb_parse_release,
-};
-
-static inline int
-__parser_mark_active(struct i915_vma *vma,
-struct intel_timeline *tl,
-struct dma_fence *fence)
-{
- st
Re: [Intel-gfx] [PATCH] drm/i915/dsc: Remove redundant checks in DSC disable
> -Original Message- > From: Manna, Animesh > Sent: Thursday, June 3, 2021 7:24 PM > To: Kulkarni, Vandita ; Nikula, Jani > ; Saarinen, Jani ; intel- > g...@lists.freedesktop.org > Cc: Navare, Manasi D > Subject: RE: [Intel-gfx] [PATCH] drm/i915/dsc: Remove redundant checks in > DSC disable > > > > > -Original Message- > > From: Kulkarni, Vandita > > Sent: Thursday, June 3, 2021 4:55 PM > > To: Nikula, Jani ; Saarinen, Jani > > ; intel-gfx@lists.freedesktop.org > > Cc: Manna, Animesh ; Navare, Manasi D > > > > Subject: RE: [Intel-gfx] [PATCH] drm/i915/dsc: Remove redundant checks > > in DSC disable > > > > > -Original Message- > > > From: Nikula, Jani > > > Sent: Thursday, June 3, 2021 3:11 PM > > > To: Kulkarni, Vandita ; Saarinen, Jani > > > ; intel-gfx@lists.freedesktop.org > > > Cc: Manna, Animesh ; Navare, Manasi D > > > > > > Subject: RE: [Intel-gfx] [PATCH] drm/i915/dsc: Remove redundant > > > checks in DSC disable > > > > > > On Thu, 03 Jun 2021, "Kulkarni, Vandita" > > > > > > wrote: > > > >> -Original Message- > > > >> From: Saarinen, Jani > > > >> Sent: Thursday, June 3, 2021 1:07 PM > > > >> To: Kulkarni, Vandita ; intel- > > > >> g...@lists.freedesktop.org > > > >> Cc: Nikula, Jani > > > >> Subject: RE: [Intel-gfx] [PATCH] drm/i915/dsc: Remove redundant > > > >> checks in DSC disable > > > >> > > > >> Hi, > > > >> > -Original Message- > > > >> > From: Intel-gfx On > > > >> > Behalf Of Vandita Kulkarni > > > >> > Sent: torstai 3. kesäkuuta 2021 9.54 > > > >> > To: intel-gfx@lists.freedesktop.org > > > >> > Cc: Nikula, Jani > > > >> > Subject: [Intel-gfx] [PATCH] drm/i915/dsc: Remove redundant > > > >> > checks in DSC disable > > > >> > > > > >> > There can be a chance that pre os has enabled DSC and driver's > > > >> > compute config would not need dsc to be enabled, in such case > > > >> > if we check on compute config's compression state to disable, > > > >> > we might end up in state > > > >> mismatch. > > > >> > > > >> I assume this fixes real gitlab issue too? > > > > Okay, will add the tag > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3537 > > > > > > See https://lore.kernel.org/r/87fsxzp9qx@intel.com > > > > > > The problem is with ->bigjoiner, not the entire statement. > > Thanks for pointing this out, true that bigjoiner not being enabled > > will stop dsc disabling. > > The bigjoiner check was making the entire condition check unnecessary. > > > > Will update and refloat. > > Hi Jani/Vandita, > > For uncompressed bigjoiner case if we want to use the same function to > clear the dsc_ctrl1 register we may need to remove both the condition > check. > As for uncompressed bigjoiner case, compression_enable Will be 0 and will > block in clearing the dss_ctl1_reg. Yes, I was going through and found that bit 20 and 21 of dss_ctl1 are being used for uncompressed joiner. So when dsc is not enabled to avoid writing the register we could add below code . if (dsc) clear dss_ctl2 if ( bigjoiner | dsc) clear dss_ctl1; return; bigjoiner = 1 and dsc = 0 - uncompressed , I think there is no harm in clearing dsc bits again bigjoiner = 1 and dsc = 1 - compressed - uncompressed bits are already 0 bigjoiner = 0 and dsc= 1 - just dsc - clear dsc rest are 0s already bigjoiner = 0 and dsc = 0 do nothing, return If I have missed any corner case, please let me know. Thanks, Vandita > > Regards, > Animesh > > > > Thanks, > > Vandita > > > > > > > > > BR, > > > Jani. > > > > > > > > > > > Thanks, > > > > Vandita > > > >> > > > >> > > > > >> > Signed-off-by: Vandita Kulkarni > > > >> > --- > > > >> > drivers/gpu/drm/i915/display/intel_vdsc.c | 4 > > > >> > 1 file changed, 4 deletions(-) > > > >> > > > > >> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c > > > >> > b/drivers/gpu/drm/i915/display/intel_vdsc.c > > > >> > index 19cd9531c115..b05a96011d93 100644 > > > >> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > > > >> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > > > >> > @@ -1161,10 +1161,6 @@ void intel_dsc_disable(const struct > > > >> > intel_crtc_state > > > >> > *old_crtc_state) > > > >> > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state- > >uapi.crtc); > > > >> > struct drm_i915_private *dev_priv = to_i915(crtc- > >base.dev); > > > >> > > > > >> > -if (!(old_crtc_state->dsc.compression_enable && > > > >> > - old_crtc_state->bigjoiner)) > > > >> > -return; > > > >> > - > > > >> > intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0); > > > >> > intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0); } > > > >> > -- > > > >> > 2.21.0.5.gaeb582a > > > >> > > > > >> > ___ > > > >> > Intel-gfx mailing list > > > >> > Intel-gfx@lists.freedesktop.org > > > >> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > -- > > > Jani Nikula, Intel Open Source Graphics Cen
Re: [Intel-gfx] [PATCH 4/5] Revert "drm/i915: Propagate errors on awaiting already signaled fences"
On Thu, Jun 3, 2021 at 3:28 AM Daniel Vetter wrote:
>
> On Thu, Jun 03, 2021 at 10:25:00AM +0200, Daniel Vetter wrote:
> > On Thu, Jun 03, 2021 at 10:24:21AM +0200, Daniel Vetter wrote:
> > > On Wed, Jun 02, 2021 at 11:41:48AM -0500, Jason Ekstrand wrote:
> > > > This reverts commit 9e31c1fe45d555a948ff66f1f0e3fe1f83ca63f7. Ever
> > > > since that commit, we've been having issues where a hang in one client
> > > > can propagate to another. In particular, a hang in an app can propagate
> > > > to the X server which causes the whole desktop to lock up.
> > >
> > > I think we need a note to backporters here:
> > >
> > > "For backporters: Please note that you _must_ have a backport of
> > > https://lore.kernel.org/dri-devel/20210602164149.391653-2-ja...@jlekstrand.net/
> > > for otherwise backporting just this patch opens up a security bug."
Done.
> > > Or something like that.
> >
> > Oh also reordering the patch set so the 2 reverts which are cc: stable are
> > first, then the other stuff on top that cleans up the fallout.
Done.
> Oh also the longer commit message I've done would be nice to add. Or at
> least link it or something like that.
>
> https://lore.kernel.org/dri-devel/20210519101523.688398-1-daniel.vet...@ffwll.ch/
>
> I think I mentioned this on irc, but got lost I guess.
Drp. I thought I'd gotten that but I guess I failed. Fixed now.
> -Daniel
>
> > -Daniel
> >
> > > -Daniel
> > >
> > > > Signed-off-by: Jason Ekstrand
> > > > Reported-by: Marcin Slusarz
> > > > Cc: # v5.6+
> > > > Cc: Jason Ekstrand
> > > > Cc: Marcin Slusarz
> > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3080
> > > > Fixes: 9e31c1fe45d5 ("drm/i915: Propagate errors on awaiting already
> > > > signaled fences")
> > > > Signed-off-by: Daniel Vetter
> > > > Reviewed-by: Jon Bloomfield
> > > > ---
> > > > drivers/gpu/drm/i915/i915_request.c | 8 ++--
> > > > 1 file changed, 2 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_request.c
> > > > b/drivers/gpu/drm/i915/i915_request.c
> > > > index 970d8f4986bbe..b796197c07722 100644
> > > > --- a/drivers/gpu/drm/i915/i915_request.c
> > > > +++ b/drivers/gpu/drm/i915/i915_request.c
> > > > @@ -1426,10 +1426,8 @@ i915_request_await_execution(struct i915_request
> > > > *rq,
> > > >
> > > > do {
> > > > fence = *child++;
> > > > - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
> > > > - i915_sw_fence_set_error_once(&rq->submit,
> > > > fence->error);
> > > > + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
> > > > continue;
> > > > - }
> > > >
> > > > if (fence->context == rq->fence.context)
> > > > continue;
> > > > @@ -1527,10 +1525,8 @@ i915_request_await_dma_fence(struct i915_request
> > > > *rq, struct dma_fence *fence)
> > > >
> > > > do {
> > > > fence = *child++;
> > > > - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) {
> > > > - i915_sw_fence_set_error_once(&rq->submit,
> > > > fence->error);
> > > > + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
> > > > continue;
> > > > - }
> > > >
> > > > /*
> > > >* Requests on the same timeline are explicitly ordered, along
> > > > --
> > > > 2.31.1
> > > >
> > >
> > > --
> > > Daniel Vetter
> > > Software Engineer, Intel Corporation
> > > http://blog.ffwll.ch
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 1/5] drm/i915: Revert "drm/i915/gem: Asynchronous cmdparser"
On Thu, Jun 3, 2021 at 3:22 AM Daniel Vetter wrote:
>
> On Wed, Jun 02, 2021 at 11:41:45AM -0500, Jason Ekstrand wrote:
> > This reverts 686c7c35abc2 ("drm/i915/gem: Asynchronous cmdparser"). The
> > justification for this commit in the git history was a vague comment
> > about getting it out from under the struct_mutex. While this may
> > improve perf for some workloads on Gen7 platforms where we rely on the
> > command parser for features such as indirect rendering, no numbers were
> > provided to prove such an improvement. It claims to closed two
> > gitlab/bugzilla issues but with no explanation whatsoever as to why or
> > what bug it's fixing.
> >
> > Meanwhile, by moving command parsing off to an async callback, it leaves
> > us with a problem of what to do on error. When things were synchronous,
> > EXECBUFFER2 would fail with an error code if parsing failed. When
> > moving it to async, we needed another way to handle that error and the
> > solution employed was to set an error on the dma_fence and then trust
> > that said error gets propagated to the client eventually. Moving back
> > to synchronous will help us untangle the fence error propagation mess.
> >
> > This also reverts most of 0edbb9ba1bfe ("drm/i915: Move cmd parser
> > pinning to execbuffer") which is a refactor of some of our allocation
> > paths for asynchronous parsing. Now that everything is synchronous, we
> > don't need it.
> >
> > Signed-off-by: Jason Ekstrand
> > Cc: Maarten Lankhorst
> > Reviewed-by: Jon Bloomfield
>
> This needs the same Cc: stable and Fixes: lines as the dma_fence error
> propagation revert. Otherwise the cmd parser breaks, which isn't great.
Done. I may have to create multiple versions of this patch for Greg
but I can do that.
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[Intel-gfx] [PATCH i-g-t] tests/kms_color: Remove gamma code from degamma tests
CRC should be collected without degamma transformation
and after drawing gradient with degamma LUT.
This patch removes things which are not related to degamma
and makes it similar to pipe gamma test.
Change-Id: I37f957b3a95dfe95119f0f0941f20c10471f437c
Signed-off-by: Vidya Srinivas
---
tests/kms_color.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/tests/kms_color.c b/tests/kms_color.c
index 3a42532a5c27..2c9821cdecce 100644
--- a/tests/kms_color.c
+++ b/tests/kms_color.c
@@ -31,8 +31,7 @@ static void test_pipe_degamma(data_t *data,
{
igt_output_t *output;
igt_display_t *display = &data->display;
- gamma_lut_t *degamma_linear, *degamma_full;
- gamma_lut_t *gamma_linear;
+ gamma_lut_t *degamma_full;
color_t red_green_blue[] = {
{ 1.0, 0.0, 0.0 },
{ 0.0, 1.0, 0.0 },
@@ -42,11 +41,8 @@ static void test_pipe_degamma(data_t *data,
igt_require(igt_pipe_obj_has_prop(primary->pipe, IGT_CRTC_DEGAMMA_LUT));
igt_require(igt_pipe_obj_has_prop(primary->pipe, IGT_CRTC_GAMMA_LUT));
- degamma_linear = generate_table(data->degamma_lut_size, 1.0);
degamma_full = generate_table_max(data->degamma_lut_size);
- gamma_linear = generate_table(data->gamma_lut_size, 1.0);
-
for_each_valid_output_on_pipe(&data->display, primary->pipe->pipe,
output) {
drmModeModeInfo *mode;
struct igt_fb fb_modeset, fb;
@@ -75,8 +71,7 @@ static void test_pipe_degamma(data_t *data,
igt_plane_set_fb(primary, &fb_modeset);
disable_ctm(primary->pipe);
- disable_degamma(primary->pipe);
- set_gamma(data, primary->pipe, gamma_linear);
+ set_degamma(data, primary->pipe, degamma_full);
igt_display_commit(&data->display);
/* Draw solid colors with no degamma transformation. */
@@ -92,7 +87,6 @@ static void test_pipe_degamma(data_t *data,
*/
paint_gradient_rectangles(data, mode, red_green_blue, &fb);
igt_plane_set_fb(primary, &fb);
- set_degamma(data, primary->pipe, degamma_full);
igt_display_commit(&data->display);
igt_wait_for_vblank(data->drm_fd,
display->pipes[primary->pipe->pipe].crtc_offset);
@@ -105,13 +99,13 @@ static void test_pipe_degamma(data_t *data,
igt_plane_set_fb(primary, NULL);
igt_output_set_pipe(output, PIPE_NONE);
+ igt_display_commit2(&data->display, data->display.is_atomic ?
+ COMMIT_ATOMIC :
COMMIT_LEGACY);
igt_remove_fb(data->drm_fd, &fb);
igt_remove_fb(data->drm_fd, &fb_modeset);
}
- free_lut(degamma_linear);
free_lut(degamma_full);
- free_lut(gamma_linear);
}
/*
@@ -191,6 +185,8 @@ static void test_pipe_gamma(data_t *data,
igt_plane_set_fb(primary, NULL);
igt_output_set_pipe(output, PIPE_NONE);
+ igt_display_commit2(&data->display, data->display.is_atomic ?
+ COMMIT_ATOMIC :
COMMIT_LEGACY);
igt_remove_fb(data->drm_fd, &fb);
igt_remove_fb(data->drm_fd, &fb_modeset);
}
--
2.7.4
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[Intel-gfx] [PATCH v2 4/4] drm/vgem: use shmem helpers
Aside from deleting lots of code the real motivation here is to switch
the mmap over to VM_PFNMAP, to be more consistent with what real gpu
drivers do. They're all VM_PFNMP, which means get_user_pages doesn't
work, and even if you try and there's a struct page behind that,
touching it and mucking around with its refcount can upset drivers
real bad.
v2: Review from Thomas:
- sort #include
- drop more dead code that I didn't spot somehow
v3: select DRM_GEM_SHMEM_HELPER to make it build (intel-gfx-ci)
v4: I got tricked by 0cf2ef46c6c0 ("drm/shmem-helper: Use cached
mappings by default"), and we need WC in vgem because vgem doesn't
have explicit begin/end cpu access ioctls.
Also add a comment why exactly vgem has to use wc.
Cc: Thomas Zimmermann
Acked-by: Thomas Zimmermann
Cc: John Stultz
Cc: Sumit Semwal
Cc: "Christian König"
Signed-off-by: Daniel Vetter
Cc: Melissa Wen
Cc: Chris Wilson
---
drivers/gpu/drm/Kconfig | 1 +
drivers/gpu/drm/vgem/vgem_drv.c | 346 ++--
2 files changed, 17 insertions(+), 330 deletions(-)
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 9c21527b791f..fb38ef7b3206 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -268,6 +268,7 @@ source "drivers/gpu/drm/kmb/Kconfig"
config DRM_VGEM
tristate "Virtual GEM provider"
depends on DRM
+ select DRM_GEM_SHMEM_HELPER
help
Choose this option to get a virtual graphics memory manager,
as used by Mesa's software renderer for enhanced performance.
diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c
index bf38a7e319d1..031e8f026cfb 100644
--- a/drivers/gpu/drm/vgem/vgem_drv.c
+++ b/drivers/gpu/drm/vgem/vgem_drv.c
@@ -38,6 +38,7 @@
#include
#include
+#include
#include
#include
#include
@@ -50,87 +51,11 @@
#define DRIVER_MAJOR 1
#define DRIVER_MINOR 0
-static const struct drm_gem_object_funcs vgem_gem_object_funcs;
-
static struct vgem_device {
struct drm_device drm;
struct platform_device *platform;
} *vgem_device;
-static void vgem_gem_free_object(struct drm_gem_object *obj)
-{
- struct drm_vgem_gem_object *vgem_obj = to_vgem_bo(obj);
-
- kvfree(vgem_obj->pages);
- mutex_destroy(&vgem_obj->pages_lock);
-
- if (obj->import_attach)
- drm_prime_gem_destroy(obj, vgem_obj->table);
-
- drm_gem_object_release(obj);
- kfree(vgem_obj);
-}
-
-static vm_fault_t vgem_gem_fault(struct vm_fault *vmf)
-{
- struct vm_area_struct *vma = vmf->vma;
- struct drm_vgem_gem_object *obj = vma->vm_private_data;
- /* We don't use vmf->pgoff since that has the fake offset */
- unsigned long vaddr = vmf->address;
- vm_fault_t ret = VM_FAULT_SIGBUS;
- loff_t num_pages;
- pgoff_t page_offset;
- page_offset = (vaddr - vma->vm_start) >> PAGE_SHIFT;
-
- num_pages = DIV_ROUND_UP(obj->base.size, PAGE_SIZE);
-
- if (page_offset >= num_pages)
- return VM_FAULT_SIGBUS;
-
- mutex_lock(&obj->pages_lock);
- if (obj->pages) {
- get_page(obj->pages[page_offset]);
- vmf->page = obj->pages[page_offset];
- ret = 0;
- }
- mutex_unlock(&obj->pages_lock);
- if (ret) {
- struct page *page;
-
- page = shmem_read_mapping_page(
- file_inode(obj->base.filp)->i_mapping,
- page_offset);
- if (!IS_ERR(page)) {
- vmf->page = page;
- ret = 0;
- } else switch (PTR_ERR(page)) {
- case -ENOSPC:
- case -ENOMEM:
- ret = VM_FAULT_OOM;
- break;
- case -EBUSY:
- ret = VM_FAULT_RETRY;
- break;
- case -EFAULT:
- case -EINVAL:
- ret = VM_FAULT_SIGBUS;
- break;
- default:
- WARN_ON(PTR_ERR(page));
- ret = VM_FAULT_SIGBUS;
- break;
- }
-
- }
- return ret;
-}
-
-static const struct vm_operations_struct vgem_gem_vm_ops = {
- .fault = vgem_gem_fault,
- .open = drm_gem_vm_open,
- .close = drm_gem_vm_close,
-};
-
static int vgem_open(struct drm_device *dev, struct drm_file *file)
{
struct vgem_file *vfile;
@@ -159,266 +84,32 @@ static void vgem_postclose(struct drm_device *dev, struct
drm_file *file)
kfree(vfile);
}
-static struct drm_vgem_gem_object *__vgem_gem_create(struct drm_device *dev,
- unsigned long size)
-{
- struct drm_vgem_gem_obj
[Intel-gfx] [PATCH v2 3/4] drm/shmem-helper: Align to page size in dumb_create
shmem helpers seem a bit sloppy here by automatically rounding up when
actually creating the buffer, which results in under-reporting of what
we actually have. Caught by igt/vgem_basic tests.
Acked-by: Thomas Zimmermann
Signed-off-by: Daniel Vetter
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
---
drivers/gpu/drm/drm_gem_shmem_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c
b/drivers/gpu/drm/drm_gem_shmem_helper.c
index 32f1d7601ec6..2985744b4300 100644
--- a/drivers/gpu/drm/drm_gem_shmem_helper.c
+++ b/drivers/gpu/drm/drm_gem_shmem_helper.c
@@ -506,13 +506,13 @@ int drm_gem_shmem_dumb_create(struct drm_file *file,
struct drm_device *dev,
if (!args->pitch || !args->size) {
args->pitch = min_pitch;
- args->size = args->pitch * args->height;
+ args->size = PAGE_ALIGN(args->pitch * args->height);
} else {
/* ensure sane minimum values */
if (args->pitch < min_pitch)
args->pitch = min_pitch;
if (args->size < args->pitch * args->height)
- args->size = args->pitch * args->height;
+ args->size = PAGE_ALIGN(args->pitch * args->height);
}
shmem = drm_gem_shmem_create_with_handle(file, dev, args->size,
&args->handle);
--
2.31.0
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[Intel-gfx] [PATCH v2 1/4] drm/gem-shmem-helper: Export drm_gem_shmem_funcs
Drivers which need to overwrite the drm_driver->gem_create_object hook
need this. Specifically vgem, which wants wc mode, but everything else
is fine as-is.
Signed-off-by: Daniel Vetter
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
---
drivers/gpu/drm/drm_gem_shmem_helper.c | 3 ++-
include/drm/drm_gem_shmem_helper.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c
b/drivers/gpu/drm/drm_gem_shmem_helper.c
index 6d625cee7a6a..4439004e62fe 100644
--- a/drivers/gpu/drm/drm_gem_shmem_helper.c
+++ b/drivers/gpu/drm/drm_gem_shmem_helper.c
@@ -24,7 +24,7 @@
* allocated using anonymous pageable memory.
*/
-static const struct drm_gem_object_funcs drm_gem_shmem_funcs = {
+const struct drm_gem_object_funcs drm_gem_shmem_funcs = {
.free = drm_gem_shmem_free_object,
.print_info = drm_gem_shmem_print_info,
.pin = drm_gem_shmem_pin,
@@ -34,6 +34,7 @@ static const struct drm_gem_object_funcs drm_gem_shmem_funcs
= {
.vunmap = drm_gem_shmem_vunmap,
.mmap = drm_gem_shmem_mmap,
};
+EXPORT_SYMBOL(drm_gem_shmem_funcs);
static struct drm_gem_shmem_object *
__drm_gem_shmem_create(struct drm_device *dev, size_t size, bool private)
diff --git a/include/drm/drm_gem_shmem_helper.h
b/include/drm/drm_gem_shmem_helper.h
index 434328d8a0d9..b29667f2b8a3 100644
--- a/include/drm/drm_gem_shmem_helper.h
+++ b/include/drm/drm_gem_shmem_helper.h
@@ -106,6 +106,7 @@ struct drm_gem_shmem_object {
#define to_drm_gem_shmem_obj(obj) \
container_of(obj, struct drm_gem_shmem_object, base)
+extern const struct drm_gem_object_funcs drm_gem_shmem_funcs;
struct drm_gem_shmem_object *drm_gem_shmem_create(struct drm_device *dev,
size_t size);
void drm_gem_shmem_free_object(struct drm_gem_object *obj);
--
2.31.0
___
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[Intel-gfx] [PATCH v2 2/4] drm/shmem-helper: Switch to vmf_insert_pfn
We want to stop gup, which isn't the case if we use vmf_insert_page
and VM_MIXEDMAP, because that does not set pte_special.
v2: With this shmem gem helpers now definitely need CONFIG_MMU (0day)
Signed-off-by: Daniel Vetter
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
---
drivers/gpu/drm/Kconfig| 2 +-
drivers/gpu/drm/drm_gem_shmem_helper.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 56a55a6e6239..9c21527b791f 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -206,7 +206,7 @@ config DRM_KMS_CMA_HELPER
config DRM_GEM_SHMEM_HELPER
bool
- depends on DRM
+ depends on DRM && MMU
help
Choose this if you need the GEM shmem helper functions
diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c
b/drivers/gpu/drm/drm_gem_shmem_helper.c
index 4439004e62fe..32f1d7601ec6 100644
--- a/drivers/gpu/drm/drm_gem_shmem_helper.c
+++ b/drivers/gpu/drm/drm_gem_shmem_helper.c
@@ -543,7 +543,7 @@ static vm_fault_t drm_gem_shmem_fault(struct vm_fault *vmf)
} else {
page = shmem->pages[page_offset];
- ret = vmf_insert_page(vma, vmf->address, page);
+ ret = vmf_insert_pfn(vma, vmf->address, page_to_pfn(page));
}
mutex_unlock(&shmem->pages_lock);
@@ -613,7 +613,7 @@ int drm_gem_shmem_mmap(struct drm_gem_object *obj, struct
vm_area_struct *vma)
return ret;
}
- vma->vm_flags |= VM_MIXEDMAP | VM_DONTEXPAND;
+ vma->vm_flags |= VM_PFNMAP | VM_DONTEXPAND;
vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
if (shmem->map_wc)
vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
--
2.31.0
___
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[Intel-gfx] [PATCH v2 0/4] shmem helpers for igt
Hi all, I finally figured out why CI is unhappy on some machines, we've lost WC mode on the vgem side! Test-with: 20210527140732.5762-1-daniel.vet...@ffwll.ch Cheers, Daniel Daniel Vetter (4): drm/gem-shmem-helper: Export drm_gem_shmem_funcs drm/shmem-helper: Switch to vmf_insert_pfn drm/shmem-helper: Align to page size in dumb_create drm/vgem: use shmem helpers drivers/gpu/drm/Kconfig| 3 +- drivers/gpu/drm/drm_gem_shmem_helper.c | 11 +- drivers/gpu/drm/vgem/vgem_drv.c| 346 ++--- include/drm/drm_gem_shmem_helper.h | 1 + 4 files changed, 25 insertions(+), 336 deletions(-) -- 2.31.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for shmem helpers for vgem (rev2)
== Series Details ==
Series: shmem helpers for vgem (rev2)
URL : https://patchwork.freedesktop.org/series/90670/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10165 -> Patchwork_20272
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20272 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20272, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20272/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_20272:
### IGT changes ###
Possible regressions
* igt@prime_vgem@basic-fence-mmap:
- fi-bsw-nick:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-bsw-nick/igt@prime_v...@basic-fence-mmap.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20272/fi-bsw-nick/igt@prime_v...@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- fi-bsw-kefka: [PASS][3] -> [INCOMPLETE][4] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20272/fi-bsw-kefka/igt@prime_v...@basic-fence-read.html
- fi-ilk-650: [PASS][5] -> [INCOMPLETE][6] +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-ilk-650/igt@prime_v...@basic-fence-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20272/fi-ilk-650/igt@prime_v...@basic-fence-read.html
- fi-elk-e7500: [PASS][7] -> [INCOMPLETE][8] +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-elk-e7500/igt@prime_v...@basic-fence-read.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20272/fi-elk-e7500/igt@prime_v...@basic-fence-read.html
- fi-bwr-2160:[PASS][9] -> [INCOMPLETE][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-bwr-2160/igt@prime_v...@basic-fence-read.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20272/fi-bwr-2160/igt@prime_v...@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- fi-ilk-650: [PASS][11] -> [FAIL][12] +2 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-ilk-650/igt@prime_v...@basic-gtt.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20272/fi-ilk-650/igt@prime_v...@basic-gtt.html
- fi-elk-e7500: [PASS][13] -> [FAIL][14] +2 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-elk-e7500/igt@prime_v...@basic-gtt.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20272/fi-elk-e7500/igt@prime_v...@basic-gtt.html
* igt@prime_vgem@basic-read:
- fi-bwr-2160:[PASS][15] -> [FAIL][16] +3 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-bwr-2160/igt@prime_v...@basic-read.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20272/fi-bwr-2160/igt@prime_v...@basic-read.html
- fi-bsw-nick:[PASS][17] -> [FAIL][18] +2 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-bsw-nick/igt@prime_v...@basic-read.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20272/fi-bsw-nick/igt@prime_v...@basic-read.html
- fi-bsw-kefka: [PASS][19] -> [FAIL][20] +2 similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-bsw-kefka/igt@prime_v...@basic-read.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20272/fi-bsw-kefka/igt@prime_v...@basic-read.html
* igt@prime_vgem@basic-write:
- fi-pnv-d510:[PASS][21] -> [FAIL][22] +3 similar issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-pnv-d510/igt@prime_v...@basic-write.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20272/fi-pnv-d510/igt@prime_v...@basic-write.html
Known issues
Here are the changes found in Patchwork_20272 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-soraka: [PASS][23] -> [DMESG-WARN][24] ([i915#1982])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10165/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20272/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][25] ([i915#3303]) -> [PASS][26]
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/dsc: abstract helpers to get bigjoiner primary/secondary crtc
== Series Details == Series: series starting with [1/2] drm/i915/dsc: abstract helpers to get bigjoiner primary/secondary crtc URL : https://patchwork.freedesktop.org/series/90936/ State : success == Summary == CI Bug Log - changes from CI_DRM_10164_full -> Patchwork_20271_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20271_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-apl: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-apl3/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_ctx_ringsize@active@bcs0: - shard-skl: NOTRUN -> [INCOMPLETE][3] ([i915#3316]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-skl7/igt@gem_ctx_ringsize@act...@bcs0.html * igt@gem_ctx_shared@q-in-order: - shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271]) +249 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-snb5/igt@gem_ctx_sha...@q-in-order.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][5] ([i915#2846]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-skl1/igt@gem_exec_f...@basic-deadline.html - shard-apl: NOTRUN -> [FAIL][6] ([i915#2846]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-apl7/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10164/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10164/shard-iclb6/igt@gem_exec_fair@basic-p...@bcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-iclb6/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][11] -> [SKIP][12] ([fdo#109271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10164/shard-kbl2/igt@gem_exec_fair@basic-p...@vecs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-kbl4/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10164/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-glk4/igt@gem_exec_fair@basic-throt...@rcs0.html - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2849]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10164/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][17] ([i915#2658]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-apl1/igt@gem_pr...@exhaustion.html * igt@gem_softpin@evict-snoop: - shard-iclb: NOTRUN -> [SKIP][18] ([fdo#109312]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-iclb3/igt@gem_soft...@evict-snoop.html * igt@gem_userptr_blits@unsync-unmap: - shard-iclb: NOTRUN -> [SKIP][19] ([i915#3297]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-iclb3/igt@gem_userptr_bl...@unsync-unmap.html * igt@gem_userptr_blits@vma-merge: - shard-snb: NOTRUN -> [FAIL][20] ([i915#2724]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-snb5/igt@gem_userptr_bl...@vma-merge.html - shard-kbl: NOTRUN -> [FAIL][21] ([i915#3318]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-kbl4/igt@gem_userptr_bl...@vma-merge.html * igt@i915_pm_dc@dc6-psr: - shard-skl: NOTRUN -> [FAIL][22] ([i915#454]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-skl7/igt@i915_pm...@dc6-psr.html * igt@i915_selftest@live@hangcheck: - shard-snb: NOTRUN -> [INCOMPLETE][23] ([i915#2782]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20271/shard-snb6/igt@i915_selftest@l...@ha
Re: [Intel-gfx] [PATCH 4/5] drm/i915/ttm: Use TTM for system memory
On 6/3/21 11:48 AM, Matthew Auld wrote:
On Wed, 2 Jun 2021 at 18:08, Thomas Hellström
wrote:
For discrete, use TTM for both cached and WC system memory. That means
we currently rely on the TTM memory accounting / shrinker. For cached
system memory we should consider remaining shmem-backed, which can be
implemented from our ttm_tt_populate calback. We can then also reuse our
own very elaborate shrinker for that memory.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c| 22 ++
drivers/gpu/drm/i915/i915_drv.h| 3 ---
drivers/gpu/drm/i915/intel_memory_region.c | 7 ++-
drivers/gpu/drm/i915/intel_memory_region.h | 8
4 files changed, 36 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 8e1c01168c6d..42e89bf43708 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -755,3 +755,25 @@ int __i915_gem_ttm_object_init(struct intel_memory_region
*mem,
/* i915 wants -ENXIO when out of memory region space. */
return (ret == -ENOSPC) ? -ENXIO : ret;
}
+
+static const struct intel_memory_region_ops ttm_system_region_ops = {
+ .init_object = __i915_gem_ttm_object_init,
+};
+
+struct intel_memory_region *
+i915_gem_ttm_system_setup(struct drm_i915_private *i915,
+ u16 type, u16 instance)
+{
+ struct intel_memory_region *mr;
+
+ mr = intel_memory_region_create(i915, 0,
+ totalram_pages() << PAGE_SHIFT,
+ PAGE_SIZE, 0,
+ type, instance,
+ &ttm_system_region_ops);
+ if (IS_ERR_OR_NULL(mr))
region_create can't return NULL.
OK, will fix.
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for shmem helpers for vgem (rev2)
== Series Details == Series: shmem helpers for vgem (rev2) URL : https://patchwork.freedesktop.org/series/90670/ State : warning == Summary == $ dim checkpatch origin/drm-tip a1fb989b5b4e dma-buf: Require VM_PFNMAP vma for mmap -:34: WARNING:TYPO_SPELLING: 'entires' may be misspelled - perhaps 'entries'? #34: >From auditing the various functions to insert pfn pte entires ^^^ -:39: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #39: References: https://lore.kernel.org/lkml/cakmk7uhi+mg0z0humnt13qccvuturvjpcr0njrl12k-wbwz...@mail.gmail.com/ -:97: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 3 warnings, 0 checks, 39 lines checked 30c0bfaaf5ce drm/vgem: use shmem helpers -:424: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 381 lines checked 798ca0897370 drm/shmem-helper: Switch to vmf_insert_pfn -:38: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 16 lines checked 07cf6c8cf755 drm/shmem-helper: Align to page size in dumb_create -:37: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Daniel Vetter ' != 'Signed-off-by: Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 15 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915: Update object placement flags to be mutable
On 6/3/21 1:17 PM, Matthew Auld wrote:
On Wed, 2 Jun 2021 at 18:08, Thomas Hellström
wrote:
The object ops i915_GEM_OBJECT_HAS_IOMEM and the object
I915_BO_ALLOC_STRUCT_PAGE flags are considered immutable by
much of our code. Introduce a new mem_flags member to hold these
and make sure checks for these flags being set are either done
under the object lock or with pages properly pinned. The flags
will change during migration under the object lock.
What are the rules for the gem_object_ops flags? Like is_shrinkable?
Can't we just move these there(IOMEM vs PAGE)?
But the ops flags are immutable, right? We expect the IOMEM and PAGE
flags to change when an object is migrated. We could of course flip the
ops under the lock, but I'd consider that a bit risky?
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 7 +++-
drivers/gpu/drm/i915/gem/i915_gem_object.c| 38 +++
drivers/gpu/drm/i915/gem/i915_gem_object.h| 14 ++-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 20 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 10 +++--
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 4 +-
.../drm/i915/gem/selftests/huge_gem_object.c | 4 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 5 +--
.../drm/i915/gem/selftests/i915_gem_mman.c| 4 +-
.../drm/i915/gem/selftests/i915_gem_phys.c| 3 +-
14 files changed, 78 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index ce6b664b10aa..13b217f75055 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -177,8 +177,8 @@ i915_gem_object_create_internal(struct drm_i915_private
*i915,
return ERR_PTR(-ENOMEM);
drm_gem_private_object_init(&i915->drm, &obj->base, size);
- i915_gem_object_init(obj, &i915_gem_object_internal_ops, &lock_class,
-I915_BO_ALLOC_STRUCT_PAGE);
+ i915_gem_object_init(obj, &i915_gem_object_internal_ops, &lock_class,
0);
+ obj->mem_flags |= I915_BO_FLAG_STRUCT_PAGE;
/*
* Mark the object as volatile, such that the pages are marked as
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index d1de97e4adfd..171a21ca930c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -683,7 +683,7 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
if (mmap_type != I915_MMAP_TYPE_GTT &&
!i915_gem_object_has_struct_page(obj) &&
- !i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_IOMEM))
+ !i915_gem_object_has_iomem(obj))
return -ENODEV;
mmo = mmap_offset_attach(obj, mmap_type, file);
@@ -707,7 +707,12 @@ __assign_mmap_offset_handle(struct drm_file *file,
if (!obj)
return -ENOENT;
+ err = i915_gem_object_lock_interruptible(obj, NULL);
+ if (err)
+ goto out_put;
err = __assign_mmap_offset(obj, mmap_type, offset, file);
+ i915_gem_object_unlock(obj);
+out_put:
i915_gem_object_put(obj);
return err;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index cf18c430d51f..07e8ff9a8aae 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -475,6 +475,44 @@ bool i915_gem_object_migratable(struct drm_i915_gem_object
*obj)
return obj->mm.n_placements > 1;
}
+/**
+ * i915_gem_object_has_struct_page - Whether the object is page-backed
+ * @obj: The object to query.
+ *
+ * This function should only be called while the object is locked or pinned,
+ * otherwise the page backing may change under the caller.
+ *
+ * Return: True if page-backed, false otherwise.
+ */
+bool i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
+{
+#ifdef CONFIG_LOCKDEP
+ if (IS_DGFX(to_i915(obj->base.dev)) &&
+ i915_gem_object_evictable((void __force *)obj))
+ assert_object_held_shared(obj);
+#endif
+ return obj->mem_flags & I915_BO_FLAG_STRUCT_PAGE;
+}
+
+/**
+ * i915_gem_object_has_iomem - Whether the object is iomem-backed
+ * @obj: The object to query.
+ *
+ * This function should only be called while the object is locked or pinned,
+ * otherwise the iomem backing may change under the caller.
+ *
+ * Return: True if iomem-backed, false otherwise.
+ */
+bool i915_gem_object_has_iomem(const struct drm_i915_gem_object *obj)
+{
+#ifdef CONFIG_LOCKDEP
+ if (IS_DGFX(to_i915(obj->base.dev)) &&
+ i915_gem_object_e
Re: [Intel-gfx] [PATCH 1/2] drm/i915/dsc: abstract helpers to get bigjoiner primary/secondary crtc
> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, June 3, 2021 5:59 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Manna, Animesh
> ; Navare, Manasi D
> ; Kulkarni, Vandita
> Subject: [PATCH 1/2] drm/i915/dsc: abstract helpers to get bigjoiner
> primary/secondary crtc
>
> Add a single point of truth for figuring out the primary/secondary crtc for
> bigjoiner instead of duplicating the magic pipe +/- 1 in multiple places.
>
> Also fix the pipe validity checks to properly take non-contiguous pipes into
> account. The current checks may theoretically overflow
> i915->pipe_to_crtc_mapping[pipe], albeit with a warning, due to fused
> off pipes, as INTEL_NUM_PIPES() returns the actual number of pipes on the
> platform, and the check is for INTEL_NUM_PIPES() == pipe + 1.
>
> Prefer primary/secondary terminology going forward.
>
> Fixes: 8a029c113b17 ("drm/i915/dp: Modify VDSC helpers to configure DSC for
> Bigjoiner slave")
> Fixes: d961eb20adb6 ("drm/i915/bigjoiner: atomic commit changes for
> uncompressed joiner")
> Cc: Animesh Manna
> Cc: Manasi Navare
> Cc: Vandita Kulkarni
> Signed-off-by: Jani Nikula
Changes look good to me.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 7 ++--
> drivers/gpu/drm/i915/display/intel_vdsc.c| 42 ++--
> drivers/gpu/drm/i915/display/intel_vdsc.h| 2 +
> 3 files changed, 35 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index caf0414e0b50..1b213ed42396 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9603,7 +9603,6 @@ static int intel_atomic_check_bigjoiner(struct
> intel_atomic_state *state,
> struct intel_crtc_state *old_crtc_state,
> struct intel_crtc_state
> *new_crtc_state) {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc_state *slave_crtc_state, *master_crtc_state;
> struct intel_crtc *slave, *master;
>
> @@ -9619,15 +9618,15 @@ static int intel_atomic_check_bigjoiner(struct
> intel_atomic_state *state,
> if (!new_crtc_state->bigjoiner)
> return 0;
>
> - if (1 + crtc->pipe >= INTEL_NUM_PIPES(dev_priv)) {
> + slave = intel_dsc_get_bigjoiner_secondary(crtc);
> + if (!slave) {
> DRM_DEBUG_KMS("[CRTC:%d:%s] Big joiner configuration
> requires "
> "CRTC + 1 to be used, doesn't exist\n",
> crtc->base.base.id, crtc->base.name);
> return -EINVAL;
> }
>
> - slave = new_crtc_state->bigjoiner_linked_crtc =
> - intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
> + new_crtc_state->bigjoiner_linked_crtc = slave;
> slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave);
> master = crtc;
> if (IS_ERR(slave_crtc_state))
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 19cd9531c115..1fd81bd3ea09 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -1106,6 +1106,32 @@ static i915_reg_t dss_ctl2_reg(const struct
> intel_crtc_state *crtc_state)
> return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2; }
>
> +struct intel_crtc *
> +intel_dsc_get_bigjoiner_secondary(const struct intel_crtc
> +*primary_crtc) {
> + struct drm_i915_private *i915 = to_i915(primary_crtc->base.dev);
> + enum pipe pipe = primary_crtc->pipe + 1;
> +
> + if (drm_WARN_ON(&i915->drm, pipe >= I915_MAX_PIPES ||
> + !(INTEL_INFO(i915)->pipe_mask & BIT(pipe
> + return NULL;
> +
> + return intel_get_crtc_for_pipe(i915, pipe); }
> +
> +struct intel_crtc *
> +intel_dsc_get_bigjoiner_primary(const struct intel_crtc
> +*secondary_crtc) {
> + struct drm_i915_private *i915 = to_i915(secondary_crtc->base.dev);
> + enum pipe pipe = secondary_crtc->pipe - 1;
> +
> + if (drm_WARN_ON(&i915->drm, pipe <= INVALID_PIPE ||
> + !(INTEL_INFO(i915)->pipe_mask & BIT(pipe
> + return NULL;
> +
> + return intel_get_crtc_for_pipe(i915, pipe); }
> +
> void intel_uncompressed_joiner_enable(const struct intel_crtc_state
> *crtc_state) {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -1178,15 +1204,11 @@ void intel_uncompressed_joiner_get_config(struct
> intel_crtc_state *crtc_state)
> dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
> if (dss_ctl1 & UNCOMPRESSED_JOINER_MASTER) {
> crtc_state->bigjoiner = true;
> - if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
> - crtc_state->bigjoiner_linked_crtc =
> -
