[Intel-gfx] ✗ Fi.CI.BUILD: warning for x86/gpu: add JasperLake to gen11 early quirks (rev3)

[Patchwork]

== Series Details ==

Series: x86/gpu: add JasperLake to gen11 early quirks (rev3)
URL   : https://patchwork.freedesktop.org/series/91082/
State : warning

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  MODPOST modules-only.symvers
ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:150: recipe for target 'modules-only.symvers' failed
make[1]: *** [modules-only.symvers] Error 1
make[1]: *** Deleting file 'modules-only.symvers'
Makefile:1759: recipe for target 'modules' failed
make: *** [modules] Error 2

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20304/build_32bit.log
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[Intel-gfx] ✓ Fi.CI.BAT: success for x86/gpu: add JasperLake to gen11 early quirks (rev3)

[Patchwork]

== Series Details ==

Series: x86/gpu: add JasperLake to gen11 early quirks (rev3)
URL   : https://patchwork.freedesktop.org/series/91082/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10188 -> Patchwork_20304


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20304/index.html

Known issues


  Here are the changes found in Patchwork_20304 that come from known issues:

### IGT changes ###

 Warnings 

  * igt@runner@aborted:
- fi-skl-6600u:   [FAIL][1] ([i915#1436] / [i915#3363]) -> [FAIL][2] 
([i915#1436] / [i915#2426] / [i915#3363])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-skl-6600u/igt@run...@aborted.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20304/fi-skl-6600u/igt@run...@aborted.html
- fi-glk-dsi: [FAIL][3] ([i915#2426] / [i915#3363] / 
[k.org#202321]) -> [FAIL][4] ([i915#3363] / [k.org#202321])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-glk-dsi/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20304/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-8809g:   [FAIL][5] ([i915#1436] / [i915#2426] / [i915#3363]) 
-> [FAIL][6] ([i915#1436] / [i915#3363])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-kbl-8809g/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20304/fi-kbl-8809g/igt@run...@aborted.html
- fi-kbl-soraka:  [FAIL][7] ([i915#1436] / [i915#2426] / [i915#3363]) 
-> [FAIL][8] ([i915#1436] / [i915#3363])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-kbl-soraka/igt@run...@aborted.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20304/fi-kbl-soraka/igt@run...@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1222]: https://gitlab.freedesktop.org/drm/intel/issues/1222
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3276]: https://gitlab.freedesktop.org/drm/intel/issues/3276
  [i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3542]: https://gitlab.freedesktop.org/drm/intel/issues/3542
  [i915#3544]: https://gitlab.freedesktop.org/drm/intel/issues/3544
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (46 -> 41)
--

  Additional (1): fi-rkl-11500t 
  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 
fi-bdw-samus fi-snb-2600 


Build changes
-

  * Linux: CI_DRM_10188 -> Patchwork_20304

  CI-20190529: 20190529
  CI_DRM_10188: 8663aa75dada3153f7d48c8bc727da0444f98de2 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6099: adb9ee4ed7206725cfe3589bf49f47f9dcf661f2 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_20304: fb04a3c0192012680366c122ed71db418279af3f @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/Patchwork_20304/build_32bit.log

  CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  MODPOST modules-only.symvers
ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:150: recipe for target 'modules-only.symvers' failed
make[1]: *** [modules-only.symvers] Error 1
make[1]: *** Deleting file 'modules-only.symvers'
Makefile:1759: recipe for target 'modules' failed
make: *** [modules] Error 2


== Linux commits ==

fb04a3c01920 x86/gpu: add JasperLake to gen11 early quirks

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20304/index.html
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Re: [Intel-gfx] [PATCH V3] x86/gpu: add JasperLake to gen11 early quirks

[Surendrakumar Upadhyay, TejaskumarX]

Please ignore this. Multiple mail sent by mistake.

> -Original Message-
> From: Intel-gfx  On Behalf Of Tejas
> Upadhyay
> Sent: 08 June 2021 10:57
> To: intel-gfx@lists.freedesktop.org; t...@linutronix.de; mi...@redhat.com;
> b...@alien8.de
> Subject: [Intel-gfx] [PATCH V3] x86/gpu: add JasperLake to gen11 early quirks
> 
> Let's reserve JSL stolen memory for graphics.
> 
> JasperLake is a gen11 platform which is compatible with ICL/EHL changes.
> 
> Required due to below reference patch:
> 
> commit 24ea098b7c0d80b56d62a200608e0b029056baf6
> drm/i915/jsl: Split EHL/JSL platform info and PCI ids
> 
> V2:
> - Added maintainer list in cc
> - Added patch ref in commit message
> V1:
> - Added Cc: x...@kernel.org
> 
> Cc: Thomas Gleixner 
> Cc: Ingo Molnar 
> Cc: Borislav Petkov 
> Cc: "H. Peter Anvin" 
> Cc: x...@kernel.org
> Cc: José Roberto de Souza 
> Signed-off-by: Tejas Upadhyay
> 
> ---
>  arch/x86/kernel/early-quirks.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index b553ffe9b985..38837dad46e6 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -549,6 +549,7 @@ static const struct pci_device_id intel_early_ids[]
> __initconst = {
>   INTEL_CNL_IDS(_early_ops),
>   INTEL_ICL_11_IDS(_early_ops),
>   INTEL_EHL_IDS(_early_ops),
> + INTEL_JSL_IDS(_early_ops),
>   INTEL_TGL_12_IDS(_early_ops),
>   INTEL_RKL_IDS(_early_ops),
>   INTEL_ADLS_IDS(_early_ops),
> --
> 2.31.1
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH V3] x86/gpu: add JasperLake to gen11 early quirks

[Surendrakumar Upadhyay, TejaskumarX]

Please ignore this. Multiple mail sent by mistake.

> -Original Message-
> From: Intel-gfx  On Behalf Of Tejas
> Upadhyay
> Sent: 08 June 2021 10:57
> To: intel-gfx@lists.freedesktop.org; t...@linutronix.de; mi...@redhat.com;
> b...@alien8.de
> Subject: [Intel-gfx] [PATCH V3] x86/gpu: add JasperLake to gen11 early quirks
> 
> Let's reserve JSL stolen memory for graphics.
> 
> JasperLake is a gen11 platform which is compatible with ICL/EHL changes.
> 
> Required due to below reference patch:
> 
> commit 24ea098b7c0d80b56d62a200608e0b029056baf6
> drm/i915/jsl: Split EHL/JSL platform info and PCI ids
> 
> V2:
> - Added maintainer list in cc
> - Added patch ref in commit message
> V1:
> - Added Cc: x...@kernel.org
> 
> Cc: Thomas Gleixner 
> Cc: Ingo Molnar 
> Cc: Borislav Petkov 
> Cc: "H. Peter Anvin" 
> Cc: x...@kernel.org
> Cc: José Roberto de Souza 
> Signed-off-by: Tejas Upadhyay
> 
> ---
>  arch/x86/kernel/early-quirks.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index b553ffe9b985..38837dad46e6 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -549,6 +549,7 @@ static const struct pci_device_id intel_early_ids[]
> __initconst = {
>   INTEL_CNL_IDS(_early_ops),
>   INTEL_ICL_11_IDS(_early_ops),
>   INTEL_EHL_IDS(_early_ops),
> + INTEL_JSL_IDS(_early_ops),
>   INTEL_TGL_12_IDS(_early_ops),
>   INTEL_RKL_IDS(_early_ops),
>   INTEL_ADLS_IDS(_early_ops),
> --
> 2.31.1
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] [PATCH V3] x86/gpu: add JasperLake to gen11 early quirks

[Tejas Upadhyay]

Let's reserve JSL stolen memory for graphics.

JasperLake is a gen11 platform which is compatible with
ICL/EHL changes.

Required due to below reference patch:

commit 24ea098b7c0d80b56d62a200608e0b029056baf6
drm/i915/jsl: Split EHL/JSL platform info and PCI ids

V2:
- Added maintainer list in cc
- Added patch ref in commit message
V1:
- Added Cc: x...@kernel.org

Cc: Thomas Gleixner 
Cc: Ingo Molnar 
Cc: Borislav Petkov 
Cc: "H. Peter Anvin" 
Cc: x...@kernel.org
Cc: José Roberto de Souza 
Signed-off-by: Tejas Upadhyay 
---
 arch/x86/kernel/early-quirks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index b553ffe9b985..38837dad46e6 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -549,6 +549,7 @@ static const struct pci_device_id intel_early_ids[] 
__initconst = {
INTEL_CNL_IDS(_early_ops),
INTEL_ICL_11_IDS(_early_ops),
INTEL_EHL_IDS(_early_ops),
+   INTEL_JSL_IDS(_early_ops),
INTEL_TGL_12_IDS(_early_ops),
INTEL_RKL_IDS(_early_ops),
INTEL_ADLS_IDS(_early_ops),
-- 
2.31.1

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[Intel-gfx] [PATCH V3] x86/gpu: add JasperLake to gen11 early quirks

[Tejas Upadhyay]

Let's reserve JSL stolen memory for graphics.

JasperLake is a gen11 platform which is compatible with
ICL/EHL changes.

Required due to below reference patch:

commit 24ea098b7c0d80b56d62a200608e0b029056baf6
drm/i915/jsl: Split EHL/JSL platform info and PCI ids

V2:
- Added maintainer list in cc
- Added patch ref in commit message
V1:
- Added Cc: x...@kernel.org

Cc: Thomas Gleixner 
Cc: Ingo Molnar 
Cc: Borislav Petkov 
Cc: "H. Peter Anvin" 
Cc: x...@kernel.org
Cc: José Roberto de Souza 
Signed-off-by: Tejas Upadhyay 
---
 arch/x86/kernel/early-quirks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index b553ffe9b985..38837dad46e6 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -549,6 +549,7 @@ static const struct pci_device_id intel_early_ids[] 
__initconst = {
INTEL_CNL_IDS(_early_ops),
INTEL_ICL_11_IDS(_early_ops),
INTEL_EHL_IDS(_early_ops),
+   INTEL_JSL_IDS(_early_ops),
INTEL_TGL_12_IDS(_early_ops),
INTEL_RKL_IDS(_early_ops),
INTEL_ADLS_IDS(_early_ops),
-- 
2.31.1

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[Intel-gfx] [PATCH V3] x86/gpu: add JasperLake to gen11 early quirks

[Tejas Upadhyay]

Let's reserve JSL stolen memory for graphics.

JasperLake is a gen11 platform which is compatible with
ICL/EHL changes.

Required due to below reference patch:

commit 24ea098b7c0d80b56d62a200608e0b029056baf6
drm/i915/jsl: Split EHL/JSL platform info and PCI ids

V2:
- Added maintainer list in cc
- Added patch ref in commit message
V1:
- Added Cc: x...@kernel.org

Cc: Thomas Gleixner 
Cc: Ingo Molnar 
Cc: Borislav Petkov 
Cc: "H. Peter Anvin" 
Cc: x...@kernel.org
Cc: José Roberto de Souza 
Signed-off-by: Tejas Upadhyay 
---
 arch/x86/kernel/early-quirks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index b553ffe9b985..38837dad46e6 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -549,6 +549,7 @@ static const struct pci_device_id intel_early_ids[] 
__initconst = {
INTEL_CNL_IDS(_early_ops),
INTEL_ICL_11_IDS(_early_ops),
INTEL_EHL_IDS(_early_ops),
+   INTEL_JSL_IDS(_early_ops),
INTEL_TGL_12_IDS(_early_ops),
INTEL_RKL_IDS(_early_ops),
INTEL_ADLS_IDS(_early_ops),
-- 
2.31.1

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for x86/gpu: add JasperLake to gen11 early quirks (rev3)

[Patchwork]

== Series Details ==

Series: x86/gpu: add JasperLake to gen11 early quirks (rev3)
URL   : https://patchwork.freedesktop.org/series/91082/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
fb04a3c01920 x86/gpu: add JasperLake to gen11 early quirks
-:16: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ 
chars of sha1> ("")' - ie: 'commit 24ea098b7c0d ("drm/i915/jsl: 
Split EHL/JSL platform info and PCI ids")'
#16: 
commit 24ea098b7c0d80b56d62a200608e0b029056baf6

total: 1 errors, 0 warnings, 0 checks, 7 lines checked


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[Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915/dsc: Fix bigjoiner check in dsc_disable (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/dsc: Fix bigjoiner check in dsc_disable (rev4)
URL   : https://patchwork.freedesktop.org/series/91006/
State : warning

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  MODPOST modules-only.symvers
ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:150: recipe for target 'modules-only.symvers' failed
make[1]: *** [modules-only.symvers] Error 1
make[1]: *** Deleting file 'modules-only.symvers'
Makefile:1759: recipe for target 'modules' failed
make: *** [modules] Error 2

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20303/build_32bit.log
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsc: Fix bigjoiner check in dsc_disable (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/dsc: Fix bigjoiner check in dsc_disable (rev4)
URL   : https://patchwork.freedesktop.org/series/91006/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10188 -> Patchwork_20303


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20303/index.html

New tests
-

  New tests have been introduced between CI_DRM_10188 and Patchwork_20303:

### New IGT tests (16) ###

  * igt@kms_flip@basic-flip-vs-dpms@a-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.71] s

  * igt@kms_flip@basic-flip-vs-dpms@b-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.76] s

  * igt@kms_flip@basic-flip-vs-dpms@c-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.77] s

  * igt@kms_flip@basic-flip-vs-dpms@d-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.79] s

  * igt@kms_flip@basic-flip-vs-modeset@a-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.70] s

  * igt@kms_flip@basic-flip-vs-modeset@b-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.71] s

  * igt@kms_flip@basic-flip-vs-modeset@c-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.76] s

  * igt@kms_flip@basic-flip-vs-modeset@d-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.79] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-dp3:
- Statuses : 1 pass(s)
- Exec time: [1.01] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@b-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.98] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.98] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@d-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.97] s

  * igt@kms_flip@basic-plain-flip@a-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.73] s

  * igt@kms_flip@basic-plain-flip@b-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.69] s

  * igt@kms_flip@basic-plain-flip@c-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.69] s

  * igt@kms_flip@basic-plain-flip@d-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.69] s

  

Known issues


  Here are the changes found in Patchwork_20303 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][1] -> [INCOMPLETE][2] ([i915#2782])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20303/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  [PASS][3] -> [DMESG-WARN][4] ([i915#2868])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20303/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  
 Warnings 

  * igt@runner@aborted:
- fi-kbl-8809g:   [FAIL][5] ([i915#1436] / [i915#2426] / [i915#3363]) 
-> [FAIL][6] ([i915#1436] / [i915#3363])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-kbl-8809g/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20303/fi-kbl-8809g/igt@run...@aborted.html
- fi-kbl-guc: [FAIL][7] ([i915#1436] / [i915#3363]) -> [FAIL][8] 
([i915#1436] / [i915#2426] / [i915#3363])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-kbl-guc/igt@run...@aborted.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20303/fi-kbl-guc/igt@run...@aborted.html
- fi-skl-guc: [FAIL][9] ([i915#1436] / [i915#3363]) -> [FAIL][10] 
([i915#1436] / [i915#2426] / [i915#3363])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-skl-guc/igt@run...@aborted.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20303/fi-skl-guc/igt@run...@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1222]: https://gitlab.freedesktop.org/drm/intel/issues/1222
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
  [i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868
  [i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3276]: https://gitlab.freedesktop.org/drm/intel/issues/3276
  

Re: [Intel-gfx] [v3] drm/i915/dsc: Fix bigjoiner check in dsc_disable

[Navare, Manasi]

On Tue, Jun 08, 2021 at 09:36:59AM +0530, Vandita Kulkarni wrote:
> This change takes care of resetting the dss_ctl registers
> in case of dsc_disable, bigjoiner disable and also
> uncompressed joiner disable.
> 
> v2: Fix formatting
> v3: Fix the typo (Mansi)
> 
> Suggested-by: Jani Nikula 
> Fixes: d961eb20adb6 (drm/i915/bigjoiner: atomic commit changes for 
> uncompressed joiner)
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3537
> Signed-off-by: Vandita Kulkarni 

Looks good to me with this fix

Reviewed-by: Manasi Navare 

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c 
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 19cd9531c115..7121b66bf96d 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -1161,12 +1161,12 @@ void intel_dsc_disable(const struct intel_crtc_state 
> *old_crtc_state)
>   struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> - if (!(old_crtc_state->dsc.compression_enable &&
> -   old_crtc_state->bigjoiner))
> - return;
> -
> - intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
> - intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
> + /* Disable only if either of them is enabled */
> + if (old_crtc_state->dsc.compression_enable ||
> + old_crtc_state->bigjoiner) {
> + intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
> + intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
> + }
>  }
>  
>  void intel_uncompressed_joiner_get_config(struct intel_crtc_state 
> *crtc_state)
> -- 
> 2.21.0.5.gaeb582a
> 
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[Intel-gfx] [PATCH V3] x86/gpu: add JasperLake to gen11 early quirks

[Tejas Upadhyay]

Let's reserve JSL stolen memory for graphics.

JasperLake is a gen11 platform which is compatible with
ICL/EHL changes.

Required due to below reference patch:

commit 24ea098b7c0d80b56d62a200608e0b029056baf6
drm/i915/jsl: Split EHL/JSL platform info and PCI ids

V2:
- Added maintainer list in cc
- Added patch ref in commit message
V1:
- Added Cc: x...@kernel.org

Cc: Thomas Gleixner 
Cc: Ingo Molnar 
Cc: Borislav Petkov 
Cc: "H. Peter Anvin" 
Cc: x...@kernel.org
Cc: José Roberto de Souza 
Signed-off-by: Tejas Upadhyay 
---
 arch/x86/kernel/early-quirks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index b553ffe9b985..38837dad46e6 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -549,6 +549,7 @@ static const struct pci_device_id intel_early_ids[] 
__initconst = {
INTEL_CNL_IDS(_early_ops),
INTEL_ICL_11_IDS(_early_ops),
INTEL_EHL_IDS(_early_ops),
+   INTEL_JSL_IDS(_early_ops),
INTEL_TGL_12_IDS(_early_ops),
INTEL_RKL_IDS(_early_ops),
INTEL_ADLS_IDS(_early_ops),
-- 
2.31.1

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsc: Fix bigjoiner check in dsc_disable (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/dsc: Fix bigjoiner check in dsc_disable (rev4)
URL   : https://patchwork.freedesktop.org/series/91006/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
bfd70a7d1a4e drm/i915/dsc: Fix bigjoiner check in dsc_disable
-:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#6: 
This change takes care of resetting the dss_ctl registers in case of 
dsc_disable, bigjoiner disable and also uncompressed joiner disable.

-:44: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch 
author '"Navare, Manasi D" '

total: 1 errors, 1 warnings, 0 checks, 18 lines checked


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Re: [Intel-gfx] [v3] drm/i915/dsc: Fix bigjoiner check in dsc_disable

[Navare, Manasi D]

This change takes care of resetting the dss_ctl registers in case of 
dsc_disable, bigjoiner disable and also uncompressed joiner disable.

v2: Fix formatting
v3: Fix the typo (Mansi)

Suggested-by: Jani Nikula 
Fixes: d961eb20adb6 (drm/i915/bigjoiner: atomic commit changes for uncompressed 
joiner)
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3537
Signed-off-by: Vandita Kulkarni 

Looks good to me now

Reviewed-by: Manasi Navare 

Manasi

---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c 
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 19cd9531c115..7121b66bf96d 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -1161,12 +1161,12 @@ void intel_dsc_disable(const struct intel_crtc_state 
*old_crtc_state)
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-   if (!(old_crtc_state->dsc.compression_enable &&
- old_crtc_state->bigjoiner))
-   return;
-
-   intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
-   intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
+   /* Disable only if either of them is enabled */
+   if (old_crtc_state->dsc.compression_enable ||
+   old_crtc_state->bigjoiner) {
+   intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
+   intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
+   }
 }
 
 void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state)
--
2.21.0.5.gaeb582a

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[Intel-gfx] [v3] drm/i915/dsc: Fix bigjoiner check in dsc_disable

[Vandita Kulkarni]

This change takes care of resetting the dss_ctl registers
in case of dsc_disable, bigjoiner disable and also
uncompressed joiner disable.

v2: Fix formatting
v3: Fix the typo (Mansi)

Suggested-by: Jani Nikula 
Fixes: d961eb20adb6 (drm/i915/bigjoiner: atomic commit changes for uncompressed 
joiner)
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3537
Signed-off-by: Vandita Kulkarni 
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c 
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 19cd9531c115..7121b66bf96d 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -1161,12 +1161,12 @@ void intel_dsc_disable(const struct intel_crtc_state 
*old_crtc_state)
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-   if (!(old_crtc_state->dsc.compression_enable &&
- old_crtc_state->bigjoiner))
-   return;
-
-   intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
-   intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
+   /* Disable only if either of them is enabled */
+   if (old_crtc_state->dsc.compression_enable ||
+   old_crtc_state->bigjoiner) {
+   intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
+   intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
+   }
 }
 
 void intel_uncompressed_joiner_get_config(struct intel_crtc_state *crtc_state)
-- 
2.21.0.5.gaeb582a

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Re: [Intel-gfx] [v2] drm/i915/dsc: Fix bigjoiner check in dsc_disable

[Kulkarni, Vandita]

> -Original Message-
> From: Navare, Manasi D 
> Sent: Tuesday, June 8, 2021 2:01 AM
> To: Kulkarni, Vandita 
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
> Manna, Animesh 
> Subject: Re: [v2] drm/i915/dsc: Fix bigjoiner check in dsc_disable
> 
> On Mon, Jun 07, 2021 at 04:23:42PM +0530, Vandita Kulkarni wrote:
> > This change takes care of resetting the dss_ctl registers in case of
> > dsc_disable, bigjoiner disable and also uncompressed joiner disable.
> >
> > v2: Fix formatting
> >
> > Suggested-by: Jani Nikula 
> > Fixes: d961eb20adb6 (drm/i915/bigjoiner: atomic commit changes for
> > uncompressed joiner)
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3537
> > Signed-off-by: Vandita Kulkarni 
> > ---
> >  drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++--
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index 19cd9531c115..b9828852a68f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -1161,12 +1161,12 @@ void intel_dsc_disable(const struct
> intel_crtc_state *old_crtc_state)
> > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >
> > -   if (!(old_crtc_state->dsc.compression_enable &&
> > - old_crtc_state->bigjoiner))
> > -   return;
> > -
> > -   intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
> > -   intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
> > +   /* Disable only if either of them is enabled */
> > +   if (old_crtc_state->dsc.compression_enable ||
> > +   old_crtc_state->dsc.compression_enable) {
> 
> Vandita I think you have a copy paste error  the second condition should be
> old_crtc_state->bigjoiner ?
Sorry.
Will fix it.

Thanks,
Vandita
> 
> Manasi
> 
> > +   intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
> > +   intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
> > +   }
> >  }
> >
> >  void intel_uncompressed_joiner_get_config(struct intel_crtc_state
> > *crtc_state)
> > --
> > 2.21.0.5.gaeb582a
> >
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Re: [Intel-gfx] [PATCH] drm/i915/adl_p: Add initial ADL_P Workarounds

[Matt Roper]

On Mon, Jun 07, 2021 at 05:20:56PM -0700, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor 
> 
> Most of the context WA are already implemented.
> Adding adl_p platform tag to reflect so.
> 
> BSpec: 54369
> Cc: Matt Roper 
> Cc: Aditya Swarup 
> Signed-off-by: Radhakrishna Sripada 
> Signed-off-by: Anusha Srivatsa 
> Signed-off-by: Madhumitha Tolakanahalli Pradeep 
> 
> Signed-off-by: José Roberto de Souza 
> Signed-off-by: Swathi Dhanavanthri 
> Signed-off-by: Clint Taylor 
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  2 +-
>  drivers/gpu/drm/i915/gt/gen8_engine_cs.c  |  2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 39 ++-
>  drivers/gpu/drm/i915/intel_pm.c   |  8 ++--
>  4 files changed, 28 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 71ac57670043..79746d5c1378 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2675,7 +2675,7 @@ ehl_combo_pll_div_frac_wa_needed(struct 
> drm_i915_private *i915)
>  {
>   return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
>IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) ||
> -  IS_TIGERLAKE(i915)) &&
> +  IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&

There's a comment above this function that lists the platforms; we
should add adl-p to that list so it doesn't become stale.

I notice that we're also missing this workaround on ADL-S; we should
probably follow up with a separate patch to add that too.

>i915->dpll.ref_clks.nssc == 38400;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 94e0a5669f90..87b06572fd2e 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -208,7 +208,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 
> mode)
>   flags |= PIPE_CONTROL_FLUSH_L3;
>   flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>   flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> - /* Wa_1409600907:tgl */
> + /* Wa_1409600907:tgl,adl-p */
>   flags |= PIPE_CONTROL_DEPTH_STALL;
>   flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
>   flags |= PIPE_CONTROL_FLUSH_ENABLE;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index b62d1e31a645..e62cadb3fcd8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -640,15 +640,16 @@ static void gen12_ctx_workarounds_init(struct 
> intel_engine_cs *engine,
>   gen12_ctx_gt_tuning_init(engine, wal);
>  
>   /*
> -  * Wa_1409142259:tgl
> -  * Wa_1409347922:tgl
> -  * Wa_1409252684:tgl
> -  * Wa_1409217633:tgl
> -  * Wa_1409207793:tgl
> -  * Wa_1409178076:tgl
> -  * Wa_1408979724:tgl
> -  * Wa_14010443199:rkl
> -  * Wa_14010698770:rkl
> +  * Wa_1409142259:tgl,adl-p
> +  * Wa_1409347922:tgl,adl-p
> +  * Wa_1409252684:tgl,adl-p
> +  * Wa_1409217633:tgl,adl-p
> +  * Wa_1409207793:tgl,adl-p
> +  * Wa_1409178076:tgl,adl-p
> +  * Wa_1408979724:tgl,adl-p

Since we're updating the comments anyway, it looks like all of the ones
listed above should actually be "tgl,dg1,adl-p" for completeness and
grep-ability.

> +  * Wa_14010443199:rkl,adl-p

This one is tgl,rkl,dg1,adl-p

> +  * Wa_14010698770:rkl,adl-p
> +  * Wa_1409342910:adl-p

These two are tgl,rkl,dg1,adl-s,adl-p


Aside from the comment tweaks, all of the workarounds look correct to
me.

Reviewed-by: Matt Roper 


>*/
>   wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
>GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> @@ -1113,7 +1114,7 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915,
>  {
>   wa_init_mcr(i915, wal);
>  
> - /* Wa_14011060649:tgl,rkl,dg1,adls */
> + /* Wa_14011060649:tgl,rkl,dg1,adls,adl-p */
>   wa_14011060649(i915, wal);
>  }
>  
> @@ -1633,38 +1634,40 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
> struct i915_wa_list *wal)
>   GEN7_DISABLE_SAMPLER_PREFETCH);
>   }
>  
> - if (IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> + if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
>   IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> - /* Wa_1606931601:tgl,rkl,dg1,adl-s */
> + /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
>   wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
>  
>   /*
>* Wa_1407928979:tgl A*
>* Wa_18011464164:tgl[B0+],dg1[B0+]
>* Wa_22010931296:tgl[B0+],dg1[B0+]
> -  * Wa_14010919138:rkl,dg1,adl-s
> +  * 

[Intel-gfx] ✗ Fi.CI.BUILD: failure for linux-next: build failure after merge of the drm-misc tree

[Patchwork]

== Series Details ==

Series: linux-next: build failure after merge of the drm-misc tree
URL   : https://patchwork.freedesktop.org/series/91132/
State : failure

== Summary ==

Applying: linux-next: build failure after merge of the drm-misc tree
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
CONFLICT (content): Merge conflict in 
drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 linux-next: build failure after merge of the drm-misc tree
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".


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[Intel-gfx] linux-next: build failure after merge of the drm-misc tree

[Stephen Rothwell]

Hi all,

After merging the drm-misc tree, today's linux-next build (x86_64
allmodconfig) failed like this:

drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c: In function 
'amdgpu_preempt_mgr_new':
drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c:75:5: error: 'struct 
ttm_resource' has no member named 'mm_node'
   75 |  mem->mm_node = NULL;
  | ^~
drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c: At top level:
drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c:129:11: error: initialization 
of 'int (*)(struct ttm_resource_manager *, struct ttm_buffer_object *, const 
struct ttm_place *, struct ttm_resource **)' from incompatible pointer type 
'int (*)(struct ttm_resource_manager *, struct ttm_buffer_object *, const 
struct ttm_place *, struct ttm_resource *)' [-Werror=incompatible-pointer-types]
  129 |  .alloc = amdgpu_preempt_mgr_new,
  |   ^~
drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c:129:11: note: (near 
initialization for 'amdgpu_preempt_mgr_func.alloc')

Caused by commit

  cb1c81467af3 ("drm/ttm: flip the switch for driver allocated resources v2")

from the drm-misc tree interacting with commit

  b453e42a6e8b ("drm/amdgpu: Add new placement for preemptible SG BOs")

from the drm tree.

I don't know how to fix this, so I added the following hack (a better
fix would be nice):

From: Stephen Rothwell 
Date: Tue, 8 Jun 2021 12:41:16 +1000
Subject: [PATCH] hack fix up for needed amdgpu_preempt_mgr_new() fix up

Signed-off-by: Stephen Rothwell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
index d607f314cc1b..e1a7b3e967b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
@@ -66,14 +66,16 @@ static DEVICE_ATTR_RO(mem_info_preempt_used);
 static int amdgpu_preempt_mgr_new(struct ttm_resource_manager *man,
  struct ttm_buffer_object *tbo,
  const struct ttm_place *place,
- struct ttm_resource *mem)
+ struct ttm_resource **res)
 {
+#if 0
struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man);
 
atomic64_add(mem->num_pages, >used);
 
mem->mm_node = NULL;
mem->start = AMDGPU_BO_INVALID_OFFSET;
+#endif
return 0;
 }
 
-- 
2.30.2

-- 
Cheers,
Stephen Rothwell


pgpS0X9ihg7Bl.pgp
Description: OpenPGP digital signature
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Re: [Intel-gfx] [PATCH 08/13] drm/i915/guc: New CTB based communication

[Daniele Ceraolo Spurio]

On 6/7/2021 11:03 AM, Matthew Brost wrote:

From: Michal Wajdeczko 

Format of the CTB messages has changed:
  - support for multiple formats
  - message fence is now part of the header
  - reuse of unified HXG message formats

Signed-off-by: Michal Wajdeczko 
Signed-off-by: Matthew Brost 
Cc: Piotr Piórkowski 
---
  .../gt/uc/abi/guc_communication_ctb_abi.h |  56 +
  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 194 +++---
  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |   2 +-
  3 files changed, 135 insertions(+), 117 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
index 127b256a662c..92660726c094 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
@@ -60,6 +60,62 @@ struct guc_ct_buffer_desc {
  } __packed;
  static_assert(sizeof(struct guc_ct_buffer_desc) == 64);
  
+/**

+ * DOC: CTB Message
+ *
+ *  
+---+---+--+
+ *  |   | Bits  | Description  
|
+ *  
+===+===+==+
+ *  | 0 | 31:16 | **FENCE** - message identifier   
|
+ *  |   
+---+--+
+ *  |   | 15:12 | **FORMAT** - format of the CTB message   
|
+ *  |   |   |  - _`GUC_CTB_FORMAT_HXG` = 0 - see `CTB HXG Message`_
|
+ *  |   
+---+--+
+ *  |   |  11:8 | **RESERVED** 
|
+ *  |   
+---+--+
+ *  |   |   7:0 | **NUM_DWORDS** - length of the CTB message (w/o header)  
|
+ *  
+---+---+--+
+ *  | 1 |  31:0 | optional (depends on FORMAT) 
|
+ *  +---+---+  
|
+ *  |...|   |  
|
+ *  +---+---+  
|
+ *  | n |  31:0 |  
|
+ *  
+---+---+--+
+ */
+
+#define GUC_CTB_MSG_MIN_LEN1u
+#define GUC_CTB_MSG_MAX_LEN256u
+#define GUC_CTB_MSG_0_FENCE(0x << 16)
+#define GUC_CTB_MSG_0_FORMAT   (0xf << 12)
+#define   GUC_CTB_FORMAT_HXG   0u
+#define GUC_CTB_MSG_0_RESERVED (0xf << 8)
+#define GUC_CTB_MSG_0_NUM_DWORDS   (0xff << 0)
+
+/**
+ * DOC: CTB HXG Message
+ *
+ *  
+---+---+--+
+ *  |   | Bits  | Description  
|
+ *  
+===+===+==+
+ *  | 0 | 31:16 | FENCE
|
+ *  |   
+---+--+
+ *  |   | 15:12 | FORMAT = GUC_CTB_FORMAT_HXG_ 
|
+ *  |   
+---+--+
+ *  |   |  11:8 | RESERVED = MBZ   
|
+ *  |   
+---+--+
+ *  |   |   7:0 | NUM_DWORDS = length (in dwords) of the embedded HXG message  
|
+ *  
+---+---+--+
+ *  | 1 |  31:0 |  ++  
|
+ *  +---+---+  ||  
|
+ *  |...|   |  |  Embedded `HXG Message`_   |  
|
+ *  +---+---+  ||  
|
+ *  | n |  31:0 |  ++  
|
+ *  
+---+---+--+
+ */
+
+#define GUC_CTB_HXG_MSG_MIN_LEN(GUC_CTB_MSG_MIN_LEN + 
GUC_HXG_MSG_MIN_LEN)
+#define GUC_CTB_HXG_MSG_MAX_LENGUC_CTB_MSG_MAX_LEN
+
  /**
   * DOC: CTB based communication
   *
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 6a29be779cc9..729f29bc2a57 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -365,24 +365,6 @@ static void write_barrier(struct intel_guc_ct *ct)
}
  }
  
-/**

- * DOC: CTB Host to GuC request
- *
- * Format of the CTB Host to GuC request 

[Intel-gfx] ✓ Fi.CI.IGT: success for Update firmware to v62.0.0

[Patchwork]

== Series Details ==

Series: Update firmware to v62.0.0
URL   : https://patchwork.freedesktop.org/series/91106/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10187_full -> Patchwork_20298_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_20298_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@clone:
- shard-snb:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +2 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-snb5/igt@gem_ctx_persiste...@clone.html

  * igt@gem_ctx_persistence@legacy-engines-hang@blt:
- shard-skl:  NOTRUN -> [SKIP][2] ([fdo#109271]) +74 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-skl7/igt@gem_ctx_persistence@legacy-engines-h...@blt.html

  * igt@gem_exec_fair@basic-none@rcs0:
- shard-glk:  [PASS][3] -> [FAIL][4] ([i915#2842])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/shard-glk5/igt@gem_exec_fair@basic-n...@rcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-glk4/igt@gem_exec_fair@basic-n...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/shard-tglb7/igt@gem_exec_fair@basic-p...@vcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-tglb7/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk:  NOTRUN -> [FAIL][7] ([i915#2842]) +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-glk7/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][8] ([i915#2389])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-iclb1/igt@gem_exec_reloc@basic-wide-act...@vcs1.html

  * igt@gem_mmap_gtt@big-copy-xy:
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#307])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/shard-glk8/igt@gem_mmap_...@big-copy-xy.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-glk7/igt@gem_mmap_...@big-copy-xy.html

  * igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
- shard-glk:  [PASS][11] -> [FAIL][12] ([i915#307] / [i915#3468])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/shard-glk7/igt@gem_mmap_...@cpuset-basic-small-copy-xy.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-glk6/igt@gem_mmap_...@cpuset-basic-small-copy-xy.html

  * igt@gem_mmap_gtt@cpuset-big-copy:
- shard-iclb: [PASS][13] -> [FAIL][14] ([i915#307])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/shard-iclb4/igt@gem_mmap_...@cpuset-big-copy.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-iclb8/igt@gem_mmap_...@cpuset-big-copy.html

  * igt@gem_pread@exhaustion:
- shard-skl:  NOTRUN -> [WARN][15] ([i915#2658])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-skl2/igt@gem_pr...@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-snb:  NOTRUN -> [WARN][16] ([i915#2658]) +1 similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-snb5/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_userptr_blits@input-checking:
- shard-apl:  NOTRUN -> [DMESG-WARN][17] ([i915#3002])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-apl2/igt@gem_userptr_bl...@input-checking.html

  * igt@gen7_exec_parse@batch-without-end:
- shard-iclb: NOTRUN -> [SKIP][18] ([fdo#109289]) +1 similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-iclb5/igt@gen7_exec_pa...@batch-without-end.html
- shard-tglb: NOTRUN -> [SKIP][19] ([fdo#109289])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-tglb1/igt@gen7_exec_pa...@batch-without-end.html

  * igt@i915_pm_backlight@fade_with_dpms:
- shard-kbl:  NOTRUN -> [SKIP][20] ([fdo#109271]) +33 similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-kbl2/igt@i915_pm_backlight@fade_with_dpms.html

  * igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglb: NOTRUN -> [WARN][21] ([i915#2681])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-tglb3/igt@i915_pm_rc6_reside...@rc6-fence.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-tglb: NOTRUN -> [SKIP][22] ([fdo#111644] / [i915#1397] / 
[i915#2411])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/shard-tglb1/igt@i915_pm_...@dpms-mode-unset-non-lpsp.html
- shard-iclb: 

[Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915/adl_p: Add initial ADL_P Workarounds

[Patchwork]

== Series Details ==

Series: drm/i915/adl_p: Add initial ADL_P Workarounds
URL   : https://patchwork.freedesktop.org/series/91127/
State : warning

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  MODPOST modules-only.symvers
ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:150: recipe for target 'modules-only.symvers' failed
make[1]: *** [modules-only.symvers] Error 1
make[1]: *** Deleting file 'modules-only.symvers'
Makefile:1759: recipe for target 'modules' failed
make: *** [modules] Error 2

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20301/build_32bit.log
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adl_p: Add initial ADL_P Workarounds

[Patchwork]

== Series Details ==

Series: drm/i915/adl_p: Add initial ADL_P Workarounds
URL   : https://patchwork.freedesktop.org/series/91127/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10188 -> Patchwork_20301


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20301/index.html

Known issues


  Here are the changes found in Patchwork_20301 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][1] -> [INCOMPLETE][2] ([i915#2782])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20301/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  
 Warnings 

  * igt@runner@aborted:
- fi-kbl-8809g:   [FAIL][3] ([i915#1436] / [i915#2426] / [i915#3363]) 
-> [FAIL][4] ([i915#1436] / [i915#3363])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-kbl-8809g/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20301/fi-kbl-8809g/igt@run...@aborted.html
- fi-kbl-7500u:   [FAIL][5] ([i915#1436] / [i915#3363]) -> [FAIL][6] 
([i915#1436] / [i915#2426] / [i915#3363])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-kbl-7500u/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20301/fi-kbl-7500u/igt@run...@aborted.html
- fi-kbl-guc: [FAIL][7] ([i915#1436] / [i915#3363]) -> [FAIL][8] 
([i915#1436] / [i915#2426] / [i915#3363])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-kbl-guc/igt@run...@aborted.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20301/fi-kbl-guc/igt@run...@aborted.html
- fi-cml-s:   [FAIL][9] ([i915#3363] / [i915#3462]) -> [FAIL][10] 
([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-cml-s/igt@run...@aborted.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20301/fi-cml-s/igt@run...@aborted.html
- fi-kbl-7567u:   [FAIL][11] ([i915#1436] / [i915#3363]) -> [FAIL][12] 
([i915#1436] / [i915#2426] / [i915#3363])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-kbl-7567u/igt@run...@aborted.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20301/fi-kbl-7567u/igt@run...@aborted.html
- fi-skl-guc: [FAIL][13] ([i915#1436] / [i915#3363]) -> [FAIL][14] 
([i915#1436] / [i915#2426] / [i915#3363])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-skl-guc/igt@run...@aborted.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20301/fi-skl-guc/igt@run...@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1222]: https://gitlab.freedesktop.org/drm/intel/issues/1222
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
  [i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
  [i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3276]: https://gitlab.freedesktop.org/drm/intel/issues/3276
  [i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3542]: https://gitlab.freedesktop.org/drm/intel/issues/3542
  [i915#3544]: https://gitlab.freedesktop.org/drm/intel/issues/3544
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Participating hosts (46 -> 42)
--

  Additional (1): fi-rkl-11500t 
  Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 
fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_10188 -> Patchwork_20301

  CI-20190529: 20190529
  CI_DRM_10188: 8663aa75dada3153f7d48c8bc727da0444f98de2 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6099: adb9ee4ed7206725cfe3589bf49f47f9dcf661f2 @ 

Re: [Intel-gfx] [PATCH 07/13] drm/i915/guc: New definition of the CTB registration action

[Daniele Ceraolo Spurio]

On 6/7/2021 11:03 AM, Matthew Brost wrote:

From: Michal Wajdeczko 

Definition of the CTB registration action has changed.
Add some ABI documentation and implement required changes.

Signed-off-by: Michal Wajdeczko 
Signed-off-by: Matthew Brost 
Cc: Piotr Piórkowski  #4
---
  .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  | 107 ++
  .../gt/uc/abi/guc_communication_ctb_abi.h |   4 -
  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |  76 -
  3 files changed, 152 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 90efef8a73e4..6426fc183692 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -6,6 +6,113 @@
  #ifndef _ABI_GUC_ACTIONS_ABI_H
  #define _ABI_GUC_ACTIONS_ABI_H
  
+/**

+ * DOC: HOST2GUC_REGISTER_CTB
+ *
+ * This message is used as part of the `CTB based communication`_ setup.
+ *
+ * This message must be sent as `MMIO HXG Message`_.
+ *
+ *  
+---+---+--+
+ *  |   | Bits  | Description  
|
+ *  
+===+===+==+
+ *  | 0 |31 | ORIGIN = GUC_HXG_ORIGIN_HOST_
|
+ *  |   
+---+--+
+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ 
|
+ *  |   
+---+--+
+ *  |   | 27:16 | DATA0 = MBZ  
|
+ *  |   
+---+--+
+ *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_REGISTER_CTB` = 0x5200
|


Specs says 4505


+ *  
+---+---+--+
+ *  | 1 | 31:12 | RESERVED = MBZ   
|
+ *  |   
+---+--+
+ *  |   |  11:8 | **TYPE** - type for the `CT Buffer`_ 
|
+ *  |   |   |  
|
+ *  |   |   |   - _`GUC_CTB_TYPE_HOST2GUC` = 0 
|
+ *  |   |   |   - _`GUC_CTB_TYPE_GUC2HOST` = 1 
|
+ *  |   
+---+--+
+ *  |   |   7:0 | **SIZE** - size of the `CT Buffer`_ in 4K units minus 1  
|
+ *  
+---+---+--+
+ *  | 2 |  31:0 | **DESC_ADDR** - GGTT address of the `CTB Descriptor`_
|
+ *  
+---+---+--+
+ *  | 3 |  31:0 | **BUFF_ADDF** - GGTT address of the `CT Buffer`_ 
|
+ *  
+---+---+--+
+*
+ *  
+---+---+--+
+ *  |   | Bits  | Description  
|
+ *  
+===+===+==+
+ *  | 0 |31 | ORIGIN = GUC_HXG_ORIGIN_GUC_ 
|
+ *  |   
+---+--+
+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_
|
+ *  |   
+---+--+
+ *  |   |  27:0 | DATA0 = MBZ  
|
+ *  
+---+---+--+
+ */
+#define GUC_ACTION_HOST2GUC_REGISTER_CTB   0x4505 // FIXME 0x5200


Why FIXME? AFAICS the specs still says 4505, even if we plan to update 
at some point I don;t think this deserves a FIXME since nothing is 
incorrect.



+
+#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_LEN  
(GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)
+#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_0_MBZ
GUC_HXG_REQUEST_MSG_0_DATA0
+#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_1_MBZ(0xf << 12)
+#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_1_TYPE   (0xf << 8)
+#define   GUC_CTB_TYPE_HOST2GUC0u
+#define   GUC_CTB_TYPE_GUC2HOST1u
+#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_1_SIZE   (0xff << 0)
+#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_2_DESC_ADDR  
GUC_HXG_REQUEST_MSG_n_DATAn
+#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_3_BUFF_ADDR  
GUC_HXG_REQUEST_MSG_n_DATAn


The full mask still seems like overkill to me and I still think we 
should use BIT()/GENMASK() and a _MASK prefix, but not going to block on it.



+
+#define HOST2GUC_REGISTER_CTB_RESPONSE_MSG_LEN 

[Intel-gfx] ✗ Fi.CI.IGT: failure for x86/gpu: add JasperLake to gen11 early quirks (rev2)

[Patchwork]

== Series Details ==

Series: x86/gpu: add JasperLake to gen11 early quirks (rev2)
URL   : https://patchwork.freedesktop.org/series/91082/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10187_full -> Patchwork_20297_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_20297_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20297_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20297_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/shard-tglb3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-move.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/shard-tglb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-move.html

  
Known issues


  Here are the changes found in Patchwork_20297_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-clear:
- shard-glk:  [PASS][3] -> [FAIL][4] ([i915#1888] / [i915#3160])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/shard-glk4/igt@gem_cre...@create-clear.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/shard-glk4/igt@gem_cre...@create-clear.html

  * igt@gem_ctx_persistence@clone:
- shard-snb:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +1 
similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/shard-snb7/igt@gem_ctx_persiste...@clone.html

  * igt@gem_ctx_persistence@legacy-engines-hang@blt:
- shard-skl:  NOTRUN -> [SKIP][6] ([fdo#109271]) +80 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/shard-skl7/igt@gem_ctx_persistence@legacy-engines-h...@blt.html

  * igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][7] -> [TIMEOUT][8] ([i915#2369] / [i915#2481] 
/ [i915#3070])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/shard-iclb3/igt@gem_...@unwedge-stress.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/shard-iclb3/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-kbl:  [PASS][9] -> [SKIP][10] ([fdo#109271])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/shard-kbl2/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/shard-kbl4/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/shard-tglb7/igt@gem_exec_fair@basic-p...@vcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/shard-tglb6/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk:  NOTRUN -> [FAIL][13] ([i915#2842]) +2 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/shard-glk3/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][14] -> [FAIL][15] ([i915#2842]) +1 similar 
issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/shard-glk1/igt@gem_exec_fair@basic-throt...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][16] ([i915#2389])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/shard-iclb4/igt@gem_exec_reloc@basic-wide-act...@vcs1.html

  * igt@gem_pread@exhaustion:
- shard-skl:  NOTRUN -> [WARN][17] ([i915#2658])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/shard-skl7/igt@gem_pr...@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-snb:  NOTRUN -> [WARN][18] ([i915#2658])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/shard-snb7/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_workarounds@suspend-resume-fd:
- shard-kbl:  [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +4 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/shard-kbl2/igt@gem_workarou...@suspend-resume-fd.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/shard-kbl4/igt@gem_workarou...@suspend-resume-fd.html

  * igt@gen7_exec_parse@batch-without-end:
- shard-iclb: NOTRUN -> [SKIP][21] 

Re: [Intel-gfx] [PATCH 0/9] Enhance pipe color support for multi segmented luts

[Harry Wentland]

On 2021-06-07 2:01 p.m., Shankar, Uma wrote:
> 
> 
>> -Original Message-
>> From: Harry Wentland 
>> Sent: Saturday, June 5, 2021 12:21 AM
>> To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; 
>> dri-
>> de...@lists.freedesktop.org
>> Cc: Modem, Bhanuprakash ; Cyr, Aric
>> 
>> Subject: Re: [PATCH 0/9] Enhance pipe color support for multi segmented luts
>>
>> On 2021-06-01 6:41 a.m., Uma Shankar wrote:
>>> Modern hardwares have multi segmented lut approach to prioritize the
>>> darker regions of the spectrum. This series introduces a new UAPI to
>>> define the lut ranges supported by the respective hardware.
>>>
>>> This also enables Pipe Color Management Support for Intel's XE_LPD hw.
>>> Enable Support for Pipe Degamma with the increased lut samples
>>> supported by hardware. This also adds support for newly introduced
>>> Logarithmic Gamma for XE_LPD. Also added the gamma readout support.
>>>
>>> The Logarithmic gamma implementation on XE_LPD is non linear and adds
>>> 25 segments with non linear lut samples in each segment. The
>>> expectation is userspace will create the luts as per this distribution
>>> and pass the final samples to driver to be programmed in hardware.
>>>
>>
>> Is this design targetting Intel XE_LPD HW in particular or is it intended to 
>> be generic?
>>
>> If this is intended to be generic I think it would benefit from a lot more
>> documentation. At this point it's difficult for me to see how to adapt this 
>> to AMD
>> HW. It would take me a while to be comfortable to make a call on whether we 
>> can
>> use it or not. And what about other vendors?
> 
> This is expected to be generic for all vendors.  XE_LPD is just a reference 
> implementation.
> It's basically an extension of what we have for crtc color but designing the 
> UAPI to have it
> more scalable for future hardware. The legacy hardware implementation which 
> we have in
> crtc properties can easily fit in this new UAPI and this can help represent 
> hardware better
> with more precision and scalability. Credits to Ville as to this is his idea 
> of how we can represent
> hardware generically and advertise to userspace.
> 
> Sure, I will add more documentation to make this clearer. 
> 
>> I think we need to be cautious in directly exposing HW functionality through 
>> UAPI.
>> The CM parts of AMD HW seem to be changing in some way each generation and it
>> looks like the same is true for Intel. The trouble we have with adapting the 
>> old
>> gamma/degamma properties to modern HW is some indication to me that this
>> approach is somewhat problematic.
>>
> 
> The advantage of having flexibility in userspace is that we give access of 
> hardware to
> userspace.It can then control things based on various usecases and not 
> limited by just
> a subset of operations what we define (in the lack of such an implementation).
> 
>> It would be useful to understand and document the specific use-cases we want 
>> to
>> provide to userspace implementers with this functionality. Do we want to 
>> support
>> modern transfer functions such as PQ or HLG? If so, it might be beneficial 
>> to have an
>> API to explicitly specify that, and then use LUT tables in drivers that are 
>> optimized for
>> the implementing HW. Or is the use case tone mapping? If so, would a 
>> parametric
>> definition of tone mapping be easier to manage?
>>
> 
> Yes right, ideally this is what intend to achieve here. We cant have fixed 
> tables for operations
> like Tone mapping as it will depend on mastering luminance values which can 
> vary along with
> other attributes of metadata. Eventually this operation would be done by the 
> gamma block
> (non linear luts), the values for which would be calculated and send by 
> userspace. Thus making
> all this very generic. Also we can't do any color math in driver as it has 
> lot of floating operations.
> 
> So here the trade-off is between having a UAPI where userspace controls hw, 
> computes and sends
> values vs having just a fixed function operations with hard coded lut tables 
> in driver.
> 
> Maybe we can have both the options in order to give flexibility to hardware 
> vendors. We can
> document the usage of the UAPI we create which can help things co-exist. 
> Userspace can query
> the supported properties and implement based on the properties exposed by the 
> respective
> vendor driver implementation. 
> 
> My personal preference would be to go with generic option (expose hardware to 
> userspace) which
> will make life easier for userspace developers. This will help use hardware 
> for any color operation not
> just limited to linearization, CSC conversions and tone mapping. Also this is 
> already done for crtc, so it just
> need to be extended to planes.
> 

Thanks for providing more background.

How would a driver handle this segmented LUT when the implementing HW
doesn't have 512 points, but uses more, or less, or differently
distributed points?

What about HW that doesn't support RAM 

Re: [Intel-gfx] [PATCH 06/13] drm/i915/guc: New definition of the CTB descriptor

[Daniele Ceraolo Spurio]

On 6/7/2021 11:03 AM, Matthew Brost wrote:

From: Michal Wajdeczko 

Definition of the CTB descriptor has changed, leaving only
minimal shared fields like HEAD/TAIL/STATUS.

Both HEAD and TAIL are now in dwords.

Add some ABI documentation and implement required changes.

Signed-off-by: Michal Wajdeczko 
Signed-off-by: Matthew Brost 
---
  .../gt/uc/abi/guc_communication_ctb_abi.h | 70 ++-
  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 70 +--
  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |  2 +-
  3 files changed, 85 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
index d38935f47ecf..c2a069a78e01 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
@@ -7,6 +7,58 @@
  #define _ABI_GUC_COMMUNICATION_CTB_ABI_H
  
  #include 

+#include 
+
+#include "guc_messages_abi.h"
+
+/**
+ * DOC: CT Buffer
+ *
+ * TBD


What's the plan with this TBD here?


+ */
+
+/**
+ * DOC: CTB Descriptor
+ *
+ *  
+---+---+--+
+ *  |   | Bits  | Description  
|
+ *  
+===+===+==+
+ *  | 0 |  31:0 | **HEAD** - offset (in dwords) to the last dword that was 
|
+ *  |   |   | read from the `CT Buffer`_.  
|
+ *  |   |   | It can only be updated by the receiver.  
|
+ *  
+---+---+--+
+ *  | 1 |  31:0 | **TAIL** - offset (in dwords) to the last dword that was 
|
+ *  |   |   | written to the `CT Buffer`_. 
|
+ *  |   |   | It can only be updated by the sender.
|
+ *  
+---+---+--+
+ *  | 2 |  31:0 | **STATUS** - status of the CTB   
|
+ *  |   |   |  
|
+ *  |   |   |   - _`GUC_CTB_STATUS_NO_ERROR` = 0 (normal operation)
|
+ *  |   |   |   - _`GUC_CTB_STATUS_OVERFLOW` = 1 (head/tail too large) 
|
+ *  |   |   |   - _`GUC_CTB_STATUS_UNDERFLOW` = 2 (truncated message)  
|
+ *  |   |   |   - _`GUC_CTB_STATUS_MISMATCH` = 4 (head/tail modified)  
|
+ *  |   |   |   - _`GUC_CTB_STATUS_NO_BACKCHANNEL` = 8 
|
+ *  |   |   |   - _`GUC_CTB_STATUS_MALFORMED_MSG` = 16 
|


I don't see the last 2 error (8 & 16) in the 62.0.0 specs. Where is the 
reference for them?



+ *  
+---+---+--+
+ *  |...|   | RESERVED = MBZ   
|
+ *  
+---+---+--+
+ *  | 15|  31:0 | RESERVED = MBZ   
|
+ *  
+---+---+--+
+ */
+
+struct guc_ct_buffer_desc {
+   u32 head;
+   u32 tail;
+   u32 status;
+#define GUC_CTB_STATUS_NO_ERROR0
+#define GUC_CTB_STATUS_OVERFLOW(1 << 0)
+#define GUC_CTB_STATUS_UNDERFLOW   (1 << 1)
+#define GUC_CTB_STATUS_MISMATCH(1 << 2)
+#define GUC_CTB_STATUS_NO_BACKCHANNEL  (1 << 3)
+#define GUC_CTB_STATUS_MALFORMED_MSG   (1 << 4)


use BIT() ?


+   u32 reserved[13];
+} __packed;
+static_assert(sizeof(struct guc_ct_buffer_desc) == 64);
  
  /**

   * DOC: CTB based communication
@@ -60,24 +112,6 @@
   * - **flags**, holds various bits to control message handling
   */
  
-/*

- * Describes single command transport buffer.
- * Used by both guc-master and clients.
- */
-struct guc_ct_buffer_desc {
-   u32 addr;   /* gfx address */
-   u64 host_private;   /* host private data */
-   u32 size;   /* size in bytes */
-   u32 head;   /* offset updated by GuC*/
-   u32 tail;   /* offset updated by owner */
-   u32 is_in_error;/* error indicator */
-   u32 reserved1;
-   u32 reserved2;
-   u32 owner;  /* id of the channel owner */
-   u32 owner_sub_id;   /* owner-defined field for extra tracking */
-   u32 reserved[5];
-} __packed;
-
  /* Type of command transport buffer */
  #define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u
  #define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 63056ea0631e..3241a477196f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ 

[Intel-gfx] [PATCH] drm/i915/adl_p: Add initial ADL_P Workarounds

[clinton . a . taylor]

From: Clint Taylor 

Most of the context WA are already implemented.
Adding adl_p platform tag to reflect so.

BSpec: 54369
Cc: Matt Roper 
Cc: Aditya Swarup 
Signed-off-by: Radhakrishna Sripada 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Madhumitha Tolakanahalli Pradeep 

Signed-off-by: José Roberto de Souza 
Signed-off-by: Swathi Dhanavanthri 
Signed-off-by: Clint Taylor 
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  2 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 39 ++-
 drivers/gpu/drm/i915/intel_pm.c   |  8 ++--
 4 files changed, 28 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 71ac57670043..79746d5c1378 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2675,7 +2675,7 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private 
*i915)
 {
return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
 IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) ||
-IS_TIGERLAKE(i915)) &&
+IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
 i915->dpll.ref_clks.nssc == 38400;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 94e0a5669f90..87b06572fd2e 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -208,7 +208,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_FLUSH_L3;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
-   /* Wa_1409600907:tgl */
+   /* Wa_1409600907:tgl,adl-p */
flags |= PIPE_CONTROL_DEPTH_STALL;
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b62d1e31a645..e62cadb3fcd8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -640,15 +640,16 @@ static void gen12_ctx_workarounds_init(struct 
intel_engine_cs *engine,
gen12_ctx_gt_tuning_init(engine, wal);
 
/*
-* Wa_1409142259:tgl
-* Wa_1409347922:tgl
-* Wa_1409252684:tgl
-* Wa_1409217633:tgl
-* Wa_1409207793:tgl
-* Wa_1409178076:tgl
-* Wa_1408979724:tgl
-* Wa_14010443199:rkl
-* Wa_14010698770:rkl
+* Wa_1409142259:tgl,adl-p
+* Wa_1409347922:tgl,adl-p
+* Wa_1409252684:tgl,adl-p
+* Wa_1409217633:tgl,adl-p
+* Wa_1409207793:tgl,adl-p
+* Wa_1409178076:tgl,adl-p
+* Wa_1408979724:tgl,adl-p
+* Wa_14010443199:rkl,adl-p
+* Wa_14010698770:rkl,adl-p
+* Wa_1409342910:adl-p
 */
wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
@@ -1113,7 +1114,7 @@ gen12_gt_workarounds_init(struct drm_i915_private *i915,
 {
wa_init_mcr(i915, wal);
 
-   /* Wa_14011060649:tgl,rkl,dg1,adls */
+   /* Wa_14011060649:tgl,rkl,dg1,adls,adl-p */
wa_14011060649(i915, wal);
 }
 
@@ -1633,38 +1634,40 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
GEN7_DISABLE_SAMPLER_PREFETCH);
}
 
-   if (IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
+   if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
-   /* Wa_1606931601:tgl,rkl,dg1,adl-s */
+   /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
 
/*
 * Wa_1407928979:tgl A*
 * Wa_18011464164:tgl[B0+],dg1[B0+]
 * Wa_22010931296:tgl[B0+],dg1[B0+]
-* Wa_14010919138:rkl,dg1,adl-s
+* Wa_14010919138:rkl,dg1,adl-s,adl-p
 */
wa_write_or(wal, GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
 
/*
-* Wa_1606700617:tgl,dg1
-* Wa_22010271021:tgl,rkl,dg1, adl-s
+* Wa_1606700617:tgl,dg1,adl-p
+* Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p
+* Wa_14010826681:tgl,dg1,rkl,adl-p
 */
wa_masked_en(wal,
 GEN9_CS_DEBUG_MODE1,
 FF_DOP_CLOCK_GATE_DISABLE);
}
 
-   if (IS_ALDERLAKE_S(i915) || IS_DG1_REVID(i915, DG1_REVID_A0, 
DG1_REVID_A0) ||
+   if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
+   

Re: [Intel-gfx] [PATCH 03/13] drm/i915/guc: Update CTB response status definition

[Daniele Ceraolo Spurio]

On 6/7/2021 11:03 AM, Matthew Brost wrote:

From: Michal Wajdeczko 

Format of the STATUS dword in CTB response message now follows
definition of the HXG header. Update our code and remove any
obsolete legacy definitions.


This is kind of hard to review on its own against the specs, because 
there are larger changes to the CTB flows which AFAICS are part of patch 
8. If what you wanted to do here was a simple replacement of defines to 
keep the later patch simpler, then, considering all patches are going to 
be squashed anyway:


Reviewed-by: Daniele Ceraolo Spurio 

One suggestion below.



GuC: 55.0.0
Signed-off-by: Michal Wajdeczko 
Acked-by: Piotr Piórkowski 
---
  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c   | 14 --
  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 17 -
  2 files changed, 8 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 8f7b148fef58..3f7f48611487 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -477,7 +477,9 @@ static int wait_for_ct_request_update(struct ct_request 
*req, u32 *status)
 * up to that length of time, then switch to a slower sleep-wait loop.
 * No GuC command should ever take longer than 10ms.
 */
-#define done INTEL_GUC_MSG_IS_RESPONSE(READ_ONCE(req->status))
+#define done \
+   (FIELD_GET(GUC_HXG_MSG_0_ORIGIN, READ_ONCE(req->status)) == \
+GUC_HXG_ORIGIN_GUC)
err = wait_for_us(done, 10);
if (err)
err = wait_for(done, 10);
@@ -532,21 +534,21 @@ static int ct_send(struct intel_guc_ct *ct,
if (unlikely(err))
goto unlink;
  
-	if (!INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(*status)) {

+   if (FIELD_GET(GUC_HXG_MSG_0_TYPE, *status) != 
GUC_HXG_TYPE_RESPONSE_SUCCESS) {
err = -EIO;
goto unlink;
}
  
  	if (response_buf) {

/* There shall be no data in the status */
-   WARN_ON(INTEL_GUC_MSG_TO_DATA(request.status));
+   WARN_ON(FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, 
request.status));
/* Return actual response len */
err = request.response_len;
} else {
/* There shall be no response payload */
WARN_ON(request.response_len);
/* Return data decoded from the status dword */
-   err = INTEL_GUC_MSG_TO_DATA(*status);
+   err = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, *status);


Given that the same FIELD_GET() are repeated multiple times, IMO we 
could've kept some helper macros, something like:


INTEL_GUC_HXG_RESPONSE_TO_DATA(hxg) \
FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, hxg)

INTEL_GUC_HXG_ORIGIN_IS_GUC(hxg) \
(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, hxg) == GUC_HXG_ORIGIN_GUC)

INTEL_GUC_HXG_TYPE(hxg) \
FIELD_GET(GUC_HXG_MSG_0_TYPE, hxg)

Which could be useful in the mmio code as well.
Not sure how this changes in patch 8 though, I might put some more 
comments on that patch.


Daniele


}
  
  unlink:

@@ -741,8 +743,8 @@ static int ct_handle_response(struct intel_guc_ct *ct, 
struct ct_incoming_msg *r
status = response->msg[2];
datalen = len - 2;
  
-	/* Format of the status follows RESPONSE message */

-   if (unlikely(!INTEL_GUC_MSG_IS_RESPONSE(status))) {
+   /* Format of the status dword follows HXG header */
+   if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, status) != 
GUC_HXG_ORIGIN_GUC)) {
CT_ERROR(ct, "Corrupted response (status %#x)\n", status);
return -EPROTO;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index e9a9d85e2aa3..fb04e2211b79 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -414,23 +414,6 @@ struct guc_shared_ctx_data {
struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM];
  } __packed;
  
-#define __INTEL_GUC_MSG_GET(T, m) \

-   (((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT)
-#define INTEL_GUC_MSG_TO_TYPE(m)   __INTEL_GUC_MSG_GET(TYPE, m)
-#define INTEL_GUC_MSG_TO_DATA(m)   __INTEL_GUC_MSG_GET(DATA, m)
-#define INTEL_GUC_MSG_TO_CODE(m)   __INTEL_GUC_MSG_GET(CODE, m)
-
-#define __INTEL_GUC_MSG_TYPE_IS(T, m) \
-   (INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T)
-#define INTEL_GUC_MSG_IS_REQUEST(m)__INTEL_GUC_MSG_TYPE_IS(REQUEST, m)
-#define INTEL_GUC_MSG_IS_RESPONSE(m)   __INTEL_GUC_MSG_TYPE_IS(RESPONSE, m)
-
-#define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \
-(typecheck(u32, (m)) && \
- ((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \
- ((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \
-  (INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT)))
-
  /* This 

Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/display: Nuke has_infoframe

[Souza, Jose]

On Mon, 2021-06-07 at 15:49 +0300, Gwan-gyeong Mun wrote:
> 
> On 5/21/21 10:58 PM, Souza, Jose wrote:
> > On Fri, 2021-05-21 at 16:27 +0100, Mun, Gwan-gyeong wrote:
> > > On Fri, 2021-05-14 at 16:22 -0700, José Roberto de Souza wrote:
> > > > This was only reduntant information has_hdmi_sink can do the same job.
> > > > set_infoframes() hooks will call intel_write_infoframe() for the
> > > > supported infoframes types and it will only be enabled if given type
> > > > is set in crtc_state->infoframes.enable.
> > > > 
> > > > While at it also fixing the style of dig_port->set_infoframes() calls.
> > > > 
> > > > Cc: Ville Syrjälä 
> > > > Signed-off-by: José Roberto de Souza 
> > > > ---
> > > >   drivers/gpu/drm/i915/display/g4x_hdmi.c   | 22 ++-
> > > >   drivers/gpu/drm/i915/display/intel_ddi.c  | 17 +-
> > > >   drivers/gpu/drm/i915/display/intel_display.c  |  6 ++---
> > > >   .../drm/i915/display/intel_display_types.h|  3 ---
> > > >   drivers/gpu/drm/i915/display/intel_dp_mst.c   |  4 ++--
> > > >   drivers/gpu/drm/i915/display/intel_hdmi.c | 13 +--
> > > >   6 files changed, 22 insertions(+), 43 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> > > > b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> > > > index be352e9f0afc..f35db96e6239 100644
> > > > --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> > > > +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> > > > @@ -105,9 +105,6 @@ static void intel_hdmi_get_config(struct
> > > > intel_encoder *encoder,
> > > >  pipe_config->infoframes.enable |=
> > > >  intel_hdmi_infoframes_enabled(encoder, pipe_config);
> > > >   
> > > > -   if (pipe_config->infoframes.enable)
> > > > -   pipe_config->has_infoframe = true;
> > > > -
> > > "pipe_config->infoframes.enable" is set with information about the
> > > infoframes currently active in the hardware through "pipe_config-
> > > > infoframes.enable |= intel_hdmi_infoframes_enabled(encoder,
> > > pipe_config);".
> > > 
> > > Therefore, when calling set_infoframes() semantically, the
> > > has_infoframe information set by "if (pipe_config->infoframes.enable)
> > > pipe_config->has_infoframe = true;" is more clear.
> > 
> > That don't work because the functions that will check if a infoframe is 
> > needed and set pipe_config->infoframes.enable depends on pipe_config-
> > > has_infoframe/crtc_state->has_hdmi_sink.
> > That is probably because DVI ports don't support infoframes but in i915 are 
> > handle very similar to HDMI.
> > 
> > > 
> DP and HDMI can have infoframes that fit each specification in the 
> specification.
> And (although not used in this sense here) when dp has hdmi sink, it can 
> be thought of using dp to hdmi protocol converter. I think it might be a 
> little unclear, but what do you think?

Not sure if I understood what you mean but on intel_hdmi_compute_config(), 
has_infoframe is set right now after check if there is a HDMI sink(handling
DP and HDMI, intel_has_hdmi_sink()).

FYI I have applied all the other patches.


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Re: [Intel-gfx] [PATCH 02/13] drm/i915/guc: Update MMIO based communication

[Daniele Ceraolo Spurio]

On 6/7/2021 11:03 AM, Matthew Brost wrote:

From: Michal Wajdeczko 

The MMIO based Host-to-GuC communication protocol has been
updated to use unified HXG messages.

Update our intel_guc_send_mmio() function by correctly handle
BUSY, RETRY and FAILURE replies. Also update our documentation.

GuC: 55.0.0
Signed-off-by: Matthew Brost 
Signed-off-by: Michal Wajdeczko 
Cc: Piotr Piórkowski 
Cc: Michal Winiarski  #v3
---
  .../gt/uc/abi/guc_communication_mmio_abi.h| 63 ++---
  drivers/gpu/drm/i915/gt/uc/intel_guc.c| 92 ++-
  2 files changed, 97 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
index be066a62e9e0..3f9039e3ef9d 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
@@ -7,46 +7,43 @@
  #define _ABI_GUC_COMMUNICATION_MMIO_ABI_H
  
  /**

- * DOC: MMIO based communication
+ * DOC: GuC MMIO based communication
   *
- * The MMIO based communication between Host and GuC uses software scratch
- * registers, where first register holds data treated as message header,
- * and other registers are used to hold message payload.
+ * The MMIO based communication between Host and GuC relies on special
+ * hardware registers which format could be defined by the software
+ * (so called scratch registers).
   *
- * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8,
- * but no H2G command takes more than 8 parameters and the GuC FW
- * itself uses an 8-element array to store the H2G message.
- *
- *  +---+-+-+-+
- *  |  MMIO[0]  | MMIO[1] |   ...   | MMIO[n] |
- *  +---+-+-+-+
- *  | header|  optional payload   |
- *  +==++=+=+=+
- *  | 31:28|type| | | |
- *  +--++ | | |
- *  | 27:16|data| | | |
- *  +--++ | | |
- *  |  15:0|code| | | |
- *  +--++-+-+-+
- *
- * The message header consists of:
- *
- * - **type**, indicates message type
- * - **code**, indicates message code, is specific for **type**
- * - **data**, indicates message data, optional, depends on **code**
+ * Each MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H)
+ * messages, which maximum length depends on number of available scratch
+ * registers, is directly written into those scratch registers.
   *
- * The following message **types** are supported:
+ * For Gen9+, there are 16 software scratch registers 0xC180-0xC1B8,
+ * but no H2G command takes more than 8 parameters and the GuC firmware
+ * itself uses an 8-element array to store the H2G message.


Is this statement still true? I believe no MMIO H2G is over 4 DWs (given 
the limitation of the new gen11+ scratch regs), while CTB messages can 
be longer than 8 DWs.



   *
- * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code
- *   must be priovided in **code** field. Optional action specific parameters
- *   can be provided in remaining payload registers or **data** field.
+ * For Gen11+, there are additional 4 registers 0x190240-0x19024C, which
+ * are, regardless on lower count, preffered over legacy ones.


typo: preffered -> preferred


   *
- * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request,
- *   action response status will be provided in **code** field. Optional
- *   response data can be returned in remaining payload registers or **data**
- *   field.
+ * The MMIO based communication is mainly used during driver initialization
+ * phase to setup the `CTB based communication`_ that will be used afterwards.
   */
  
  #define GUC_MAX_MMIO_MSG_LEN		8


See comment above. Reduce this to 4?

  
+/**

+ * DOC: MMIO HXG Message
+ *
+ * Format of the MMIO messages follows definitions of `HXG Message`_.
+ *
+ *  
+---+---+--+
+ *  |   | Bits  | Description  
|
+ *  
+===+===+==+
+ *  | 0 |  31:0 |  ++  
|
+ *  +---+---+  ||  
|
+ *  |...|   |  |  Embedded `HXG Message`_   |  
|
+ *  +---+---+  ||  
|
+ *  | n |  31:0 |  ++  
|
+ *  
+---+---+--+
+ */
+
  #endif /* _ABI_GUC_COMMUNICATION_MMIO_ABI_H */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 

Re: [Intel-gfx] [PATCH 01/13] drm/i915/guc: Introduce unified HXG messages

[Daniele Ceraolo Spurio]

On 6/7/2021 11:03 AM, Matthew Brost wrote:

From: Michal Wajdeczko 

New GuC firmware will unify format of MMIO and CTB H2G messages.
Introduce their definitions now to allow gradual transition of
our code to match new changes.

Signed-off-by: Matthew Brost 
Signed-off-by: Michal Wajdeczko 
Cc: Michał Winiarski 
---
  .../gpu/drm/i915/gt/uc/abi/guc_messages_abi.h | 213 ++
  1 file changed, 213 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
index 775e21f3058c..29ac823acd4c 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
@@ -6,6 +6,219 @@
  #ifndef _ABI_GUC_MESSAGES_ABI_H
  #define _ABI_GUC_MESSAGES_ABI_H
  
+/**

+ * DOC: HXG Message
+ *
+ * All messages exchanged with GuC are defined using 32 bit dwords.
+ * First dword is treated as a message header. Remaining dwords are optional.
+ *
+ *  
+---+---+--+
+ *  |   | Bits  | Description  
|
+ *  
+===+===+==+
+ *  |   |   |  
|
+ *  | 0 |31 | **ORIGIN** - originator of the message   
|
+ *  |   |   |   - _`GUC_HXG_ORIGIN_HOST` = 0   
|
+ *  |   |   |   - _`GUC_HXG_ORIGIN_GUC` = 1
|
+ *  |   |   |  
|
+ *  |   
+---+--+
+ *  |   | 30:28 | **TYPE** - message type  
|
+ *  |   |   |   - _`GUC_HXG_TYPE_REQUEST` = 0  
|
+ *  |   |   |   - _`GUC_HXG_TYPE_EVENT` = 1
|
+ *  |   |   |   - _`GUC_HXG_TYPE_NO_RESPONSE_BUSY` = 3 
|
+ *  |   |   |   - _`GUC_HXG_TYPE_NO_RESPONSE_RETRY` = 5
|
+ *  |   |   |   - _`GUC_HXG_TYPE_RESPONSE_FAILURE` = 6 
|
+ *  |   |   |   - _`GUC_HXG_TYPE_RESPONSE_SUCCESS` = 7 
|
+ *  |   
+---+--+
+ *  |   |  27:0 | **AUX** - auxiliary data (depends on TYPE)   
|
+ *  
+---+---+--+
+ *  | 1 |  31:0 |  
|
+ *  +---+---+  
|
+ *  |...|   | **PAYLOAD** - optional payload (depends on TYPE) 
|
+ *  +---+---+  
|
+ *  | n |  31:0 |  
|
+ *  
+---+---+--+
+ */
+
+#define GUC_HXG_MSG_MIN_LEN1u
+#define GUC_HXG_MSG_0_ORIGIN   (0x1 << 31)


Any reason not to use BIT(31) here? same below with other bits and with 
GENMASK for masks.



+#define   GUC_HXG_ORIGIN_HOST  0u
+#define   GUC_HXG_ORIGIN_GUC   1u
+#define GUC_HXG_MSG_0_TYPE (0x7 << 28)


I think the masks could use a _MASK postfix


+#define   GUC_HXG_TYPE_REQUEST 0u
+#define   GUC_HXG_TYPE_EVENT   1u
+#define   GUC_HXG_TYPE_NO_RESPONSE_BUSY3u
+#define   GUC_HXG_TYPE_NO_RESPONSE_RETRY   5u
+#define   GUC_HXG_TYPE_RESPONSE_FAILURE6u
+#define   GUC_HXG_TYPE_RESPONSE_SUCCESS7u
+#define GUC_HXG_MSG_0_AUX  (0xfff << 0)
+#define GUC_HXG_MSG_n_PAYLOAD  (0x << 0)


Is a mask that covers the whole u32 really needed? Even for future 
proofing, I find it very unlikely that we'll ever have a case where the 
payload is not an entire dword.



+
+/**
+ * DOC: HXG Request
+ *
+ * The `HXG Request`_ message should be used to initiate synchronous activity
+ * for which confirmation or return data is expected.
+ *
+ * The recipient of this message shall use `HXG Response`_, `HXG Failure`_
+ * or `HXG Retry`_ message as a definite reply, and may use `HXG Busy`_
+ * message as a intermediate reply.
+ *
+ * Format of @DATA0 and all @DATAn fields depends on the @ACTION code.
+ *
+ *  
+---+---+--+
+ *  |   | Bits  | Description  
|
+ *  
+===+===+==+
+ *  | 0 |31 | ORIGIN   
|
+ *  |   
+---+--+
+ *  |   | 30:28 | TYPE = 

Re: [Intel-gfx] [PATCH 00/13] Update firmware to v62.0.0

[Daniele Ceraolo Spurio]

On 6/7/2021 11:03 AM, Matthew Brost wrote:

As part of enabling GuC submission [1] we need to update to the latest
and greatest firmware. This series does that. This is a destructive
change. e.g. Without all the patches in this series it will break the
i915 driver. As such, after we review all of these patches they will
squashed into a single patch for merging.


Can you resubmit with an added HAX patch for enable_guc=2 after the 
first round of review? none of the machines in CI seems to have 
attempted to load the guc, not even cfl-guc and kbl-guc. If all the 
reviews are good maybe just resubmit the squashed patch and the 
enablement with a CI tag, so we can merge once we get the results.


Daniele



Signed-off-by: Matthew Brost 

[1] https://patchwork.freedesktop.org/series/89844/

John Harrison (3):
   drm/i915/guc: Support per context scheduling policies
   drm/i915/guc: Unified GuC log
   drm/i915/guc: Update firmware to v62.0.0

Michal Wajdeczko (10):
   drm/i915/guc: Introduce unified HXG messages
   drm/i915/guc: Update MMIO based communication
   drm/i915/guc: Update CTB response status definition
   drm/i915/guc: Add flag for mark broken CTB
   drm/i915/guc: New definition of the CTB descriptor
   drm/i915/guc: New definition of the CTB registration action
   drm/i915/guc: New CTB based communication
   drm/i915/doc: Include GuC ABI documentation
   drm/i915/guc: Kill guc_clients.ct_pool
   drm/i915/guc: Kill ads.client_info

  Documentation/gpu/i915.rst|   8 +
  .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  | 107 ++
  .../gt/uc/abi/guc_communication_ctb_abi.h | 130 +--
  .../gt/uc/abi/guc_communication_mmio_abi.h|  63 ++--
  .../gpu/drm/i915/gt/uc/abi/guc_messages_abi.h | 213 +++
  drivers/gpu/drm/i915/gt/uc/intel_guc.c| 107 --
  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c|  45 +--
  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 355 +-
  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |   6 +-
  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |  75 +---
  drivers/gpu/drm/i915/gt/uc/intel_guc_log.c|  29 +-
  drivers/gpu/drm/i915/gt/uc/intel_guc_log.h|   6 +-
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  |  26 +-
  13 files changed, 750 insertions(+), 420 deletions(-)



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Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/display: Introduce new intel_psr_pause/resume function

[Souza, Jose]

On Mon, 2021-06-07 at 17:19 +0300, Gwan-gyeong Mun wrote:
> This introduces the following function that can exit and activate a psr
> source when intel_psr is already enabled.
> 
> - intel_psr_pause(): Pause current PSR. It deactivates current psr state.
> - intel_psr_resume(): Resume paused PSR. It activates paused psr state.
> 
> v2: Address Jose's review comment.
>   - Remove unneeded changes around the intel_psr_enable().
>   - Add intel_psr_post_exit() which processes waiting until PSR is idle
> and WA for SelectiveFetch.
> v3: Address Jose's review comment.
>   - Rename intel_psr_post_exit() to intel_psr_wait_exit_locked().
>   - Move WA_1408330847 to intel_psr_disable_locked()
>   - If the PSR is paused by an explicit intel_psr_paused() call, make the
> intel_psr_flush() not to activate PSR.
> 
> Cc: José Roberto de Souza 
> Cc: Stanislav Lisovskiy 
> Cc: Ville Syrjälä 
> Signed-off-by: Gwan-gyeong Mun 
> Signed-off-by: Matt Roper 
> ---
>  .../drm/i915/display/intel_display_types.h|  1 +
>  drivers/gpu/drm/i915/display/intel_psr.c  | 94 ---
>  drivers/gpu/drm/i915/display/intel_psr.h  |  2 +
>  3 files changed, 86 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b8d1f702d808..ee7cbdd7db87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1482,6 +1482,7 @@ struct intel_psr {
>   bool sink_support;
>   bool source_support;
>   bool enabled;
> + bool paused;
>   enum pipe pipe;
>   enum transcoder transcoder;
>   bool active;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 000e1ffe8c05..f547c80ed55c 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1113,6 +1113,7 @@ static void intel_psr_enable_locked(struct intel_dp 
> *intel_dp,
>   intel_psr_enable_sink(intel_dp);
>   intel_psr_enable_source(intel_dp);
>   intel_dp->psr.enabled = true;
> + intel_dp->psr.paused = false;
>  
>   intel_psr_activate(intel_dp);
>  }
> @@ -1182,22 +1183,12 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
>   intel_dp->psr.active = false;
>  }
>  
> -static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> +static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
>  {
>   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>   i915_reg_t psr_status;
>   u32 psr_status_mask;
>  
> - lockdep_assert_held(_dp->psr.lock);
> -
> - if (!intel_dp->psr.enabled)
> - return;
> -
> - drm_dbg_kms(_priv->drm, "Disabling PSR%s\n",
> - intel_dp->psr.psr2_enabled ? "2" : "1");
> -
> - intel_psr_exit(intel_dp);
> -
>   if (intel_dp->psr.psr2_enabled) {
>   psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
>   psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
> @@ -1210,6 +1201,22 @@ static void intel_psr_disable_locked(struct intel_dp 
> *intel_dp)
>   if (intel_de_wait_for_clear(dev_priv, psr_status,
>   psr_status_mask, 2000))
>   drm_err(_priv->drm, "Timed out waiting PSR idle state\n");
> +}
> +
> +static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + lockdep_assert_held(_dp->psr.lock);
> +
> + if (!intel_dp->psr.enabled)
> + return;
> +
> + drm_dbg_kms(_priv->drm, "Disabling PSR%s\n",
> + intel_dp->psr.psr2_enabled ? "2" : "1");
> +
> + intel_psr_exit(intel_dp);
> + intel_psr_wait_exit_locked(intel_dp);
>  
>   /* WA 1408330847 */
>   if (intel_dp->psr.psr2_sel_fetch_enabled &&
> @@ -1254,6 +1261,61 @@ void intel_psr_disable(struct intel_dp *intel_dp,
>   cancel_delayed_work_sync(_dp->psr.dc3co_work);
>  }
>  
> +/**
> + * intel_psr_pause - Pause PSR
> + * @intel_dp: Intel DP
> + *
> + * This function need to be called after enabling psr.
> + */
> +void intel_psr_pause(struct intel_dp *intel_dp)
> +{
> + struct intel_psr *psr = _dp->psr;
> +
> + if (!CAN_PSR(intel_dp))
> + return;
> +
> + mutex_lock(>lock);
> +
> + if (!psr->active) {

Hum just one more case came to mind.
PSR is not active but there is a scheduled psr->work that will execute after 
this call.
psr->active will be false, returning then a few msec later PSR will be 
activated.

So can you change this to psr->enabled?
intel_psr_exit() and intel_psr_wait_exit_locked() will handle the psr->active 
== false.

With that:
Reviewed-by: José Roberto de Souza 

> + mutex_unlock(>lock);
> + return;
> + }
> +
> + intel_psr_exit(intel_dp);
> + intel_psr_wait_exit_locked(intel_dp);
> + psr->paused = true;
> 

[Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915/gem: Fix fall-through warning for Clang

[Patchwork]

== Series Details ==

Series: drm/i915/gem: Fix fall-through warning for Clang
URL   : https://patchwork.freedesktop.org/series/91120/
State : warning

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  MODPOST modules-only.symvers
ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:150: recipe for target 'modules-only.symvers' failed
make[1]: *** [modules-only.symvers] Error 1
make[1]: *** Deleting file 'modules-only.symvers'
Makefile:1759: recipe for target 'modules' failed
make: *** [modules] Error 2

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20300/build_32bit.log
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Fix fall-through warning for Clang

[Patchwork]

== Series Details ==

Series: drm/i915/gem: Fix fall-through warning for Clang
URL   : https://patchwork.freedesktop.org/series/91120/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10188 -> Patchwork_20300


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20300/index.html

Known issues


  Here are the changes found in Patchwork_20300 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][1] -> [INCOMPLETE][2] ([i915#2782])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20300/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  
 Warnings 

  * igt@runner@aborted:
- fi-glk-dsi: [FAIL][3] ([i915#2426] / [i915#3363] / 
[k.org#202321]) -> [FAIL][4] ([i915#3363] / [k.org#202321])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-glk-dsi/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20300/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-8809g:   [FAIL][5] ([i915#1436] / [i915#2426] / [i915#3363]) 
-> [FAIL][6] ([i915#1436] / [i915#3363])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10188/fi-kbl-8809g/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20300/fi-kbl-8809g/igt@run...@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1222]: https://gitlab.freedesktop.org/drm/intel/issues/1222
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
  [i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
  [i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3276]: https://gitlab.freedesktop.org/drm/intel/issues/3276
  [i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3542]: https://gitlab.freedesktop.org/drm/intel/issues/3542
  [i915#3544]: https://gitlab.freedesktop.org/drm/intel/issues/3544
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (46 -> 42)
--

  Additional (1): fi-rkl-11500t 
  Missing(5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 
fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_10188 -> Patchwork_20300

  CI-20190529: 20190529
  CI_DRM_10188: 8663aa75dada3153f7d48c8bc727da0444f98de2 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6099: adb9ee4ed7206725cfe3589bf49f47f9dcf661f2 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_20300: 00bc001e2bff361b6b99a38b5d03b18341a21268 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/Patchwork_20300/build_32bit.log

  CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  MODPOST modules-only.symvers
ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:150: recipe for target 'modules-only.symvers' failed
make[1]: *** [modules-only.symvers] Error 1
make[1]: *** Deleting file 'modules-only.symvers'
Makefile:1759: recipe for target 'modules' failed
make: *** [modules] Error 2


== Linux commits ==

00bc001e2bff drm/i915/gem: Fix fall-through warning for Clang

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20300/index.html
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Re: [Intel-gfx] [PATCH][next] drm/i915/gem: Fix fall-through warning for Clang

[Joe Perches]

On Mon, 2021-06-07 at 15:32 -0500, Gustavo A. R. Silva wrote:
> In preparation to enable -Wimplicit-fallthrough for Clang, fix a
> warning by explicitly adding a fallthrough; statement.
[]
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
[]
> @@ -62,6 +62,7 @@ static void try_to_writeback(struct drm_i915_gem_object 
> *obj,
>   switch (obj->mm.madv) {
>   case I915_MADV_DONTNEED:
>   i915_gem_object_truncate(obj);
> + fallthrough;
>   case __I915_MADV_PURGED:
>   return;
>   }

I think fallthrough to return is not particularly nice to follow.

This is the current function:

static void try_to_writeback(struct drm_i915_gem_object *obj,
 unsigned int flags)
{
switch (obj->mm.madv) {
case I915_MADV_DONTNEED:
i915_gem_object_truncate(obj);
case __I915_MADV_PURGED:
return;
}

if (flags & I915_SHRINK_WRITEBACK)
i915_gem_object_writeback(obj);
}

One of these might be more typical:

static void try_to_writeback(struct drm_i915_gem_object *obj,
 unsigned int flags)
{
switch (obj->mm.madv) {
case I915_MADV_DONTNEED:
i915_gem_object_truncate(obj);
break;
case __I915_MADV_PURGED:
break;
default:
if (flags & I915_SHRINK_WRITEBACK)
i915_gem_object_writeback(obj);
break;
}
}

or maybe:

static void try_to_writeback(struct drm_i915_gem_object *obj,
 unsigned int flags)
{
switch (obj->mm.madv) {
case I915_MADV_DONTNEED:
i915_gem_object_truncate(obj);
return;
case __I915_MADV_PURGED:
return;
}

if (flags & I915_SHRINK_WRITEBACK)
i915_gem_object_writeback(obj);
}


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Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: Add handling for new "active bpc" property

[Werner Sembach]

Am 07.06.21 um 08:47 schrieb Werner Sembach:


Am 04.06.21 um 19:30 schrieb Ville Syrjälä:

On Fri, Jun 04, 2021 at 07:17:23PM +0200, Werner Sembach wrote:
This commits implements the "active bpc" drm property for the Intel 
GPU driver.


Signed-off-by: Werner Sembach 
---
  drivers/gpu/drm/i915/display/intel_display.c | 13 +
  drivers/gpu/drm/i915/display/intel_dp.c  |  8 ++--
  drivers/gpu/drm/i915/display/intel_dp_mst.c  |  4 +++-
  drivers/gpu/drm/i915/display/intel_hdmi.c    |  4 +++-
  4 files changed, 25 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c

index 64e9107d70f7..f7898d9d7438 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10164,6 +10164,8 @@ static void intel_atomic_commit_tail(struct 
intel_atomic_state *state)

  struct drm_i915_private *dev_priv = to_i915(dev);
  struct intel_crtc_state *new_crtc_state, *old_crtc_state;
  struct intel_crtc *crtc;
+    struct drm_connector *connector;
+    struct drm_connector_state *new_conn_state;
  u64 put_domains[I915_MAX_PIPES] = {};
  intel_wakeref_t wakeref = 0;
  int i;
@@ -10324,6 +10326,17 @@ static void intel_atomic_commit_tail(struct 
intel_atomic_state *state)

  }
  intel_runtime_pm_put(_priv->runtime_pm, state->wakeref);
  +    /* Extract information from crtc to communicate it to 
userspace as connector properties */
+    for_each_new_connector_in_state(>base, connector, 
new_conn_state, i) {

+    struct drm_crtc *crtc = new_conn_state->crtc;
+    if (crtc) {
+    new_crtc_state = 
to_intel_crtc_state(drm_atomic_get_new_crtc_state(>base, crtc));

intel_atomic_get_new_crtc_state()

Thanks, will use that.



+ new_conn_state->active_bpc = new_crtc_state->pipe_bpp / 3;
+    }
+    else
+    new_conn_state->active_bpc = 0;
+    }

This also seems too late. I think the whole thing should be
done somewhere around the normal swap_state() stuff.

Ok, will look into it.
So I tried to put it in intel_atomic_commit() after 
drm_atomic_helper_swap_state() and before 
INIT_WORK(>base.commit_work, intel_atomic_commit_work) (which 
creates a worker for intel_atomic_commit_tail), but somewhere in 
between, the connector_state seems to change: The bpc written with the 
for_each_new_connector_in_state() loop, gets discarded.



+
  /*
   * Defer the cleanup of the old state to a separate worker to not
   * impede the current task (userspace for blocking modesets) that
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c

index 642c60f3d9b1..67826ba976ed 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4671,10 +4671,14 @@ intel_dp_add_properties(struct intel_dp 
*intel_dp, struct drm_connector *connect

  intel_attach_force_audio_property(connector);
    intel_attach_broadcast_rgb_property(connector);
-    if (HAS_GMCH(dev_priv))
+    if (HAS_GMCH(dev_priv)) {
  drm_connector_attach_max_bpc_property(connector, 6, 10);
-    else if (DISPLAY_VER(dev_priv) >= 5)
+    drm_connector_attach_active_bpc_property(connector, 6, 10);
+    }
+    else if (DISPLAY_VER(dev_priv) >= 5) {
  drm_connector_attach_max_bpc_property(connector, 6, 12);
+    drm_connector_attach_active_bpc_property(connector, 6, 12);
+    }
    /* Register HDMI colorspace for case of lspcon */
  if (intel_bios_is_lspcon_present(dev_priv, port)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c

index 2daa3f67791e..5a1869dc2210 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -844,8 +844,10 @@ static struct drm_connector 
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo

   */
  connector->max_bpc_property =
intel_dp->attached_connector->base.max_bpc_property;
-    if (connector->max_bpc_property)
+    if (connector->max_bpc_property) {
  drm_connector_attach_max_bpc_property(connector, 6, 12);
+    drm_connector_attach_active_bpc_property(connector, 6, 12);
+    }
    return connector;
  diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c

index d69f0a6dc26d..8af78b27b6ce 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2463,8 +2463,10 @@ intel_hdmi_add_properties(struct intel_hdmi 
*intel_hdmi, struct drm_connector *c

  drm_object_attach_property(>base,
connector->dev->mode_config.hdr_output_metadata_property, 0);
  -    if (!HAS_GMCH(dev_priv))
+    if (!HAS_GMCH(dev_priv)) {
  drm_connector_attach_max_bpc_property(connector, 8, 12);
+    drm_connector_attach_active_bpc_property(connector, 8, 12);
+    }
  }
    /*
--
2.25.1

[Intel-gfx] [PATCH][next] drm/i915/gem: Fix fall-through warning for Clang

[Gustavo A. R. Silva]

In preparation to enable -Wimplicit-fallthrough for Clang, fix a
warning by explicitly adding a fallthrough; statement.

Link: https://github.com/KSPP/linux/issues/115
Signed-off-by: Gustavo A. R. Silva 
---
JFYI: We had thousands of these sorts of warnings and now we are down
  to just 13 in linux-next(20210607). This is one of those last
  remaining warnings. :)

 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c 
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index f4fb68e8955a..17714da24033 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -62,6 +62,7 @@ static void try_to_writeback(struct drm_i915_gem_object *obj,
switch (obj->mm.madv) {
case I915_MADV_DONTNEED:
i915_gem_object_truncate(obj);
+   fallthrough;
case __I915_MADV_PURGED:
return;
}
-- 
2.27.0

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Re: [Intel-gfx] [v2] drm/i915/dsc: Fix bigjoiner check in dsc_disable

[Navare, Manasi]

On Mon, Jun 07, 2021 at 04:23:42PM +0530, Vandita Kulkarni wrote:
> This change takes care of resetting the dss_ctl registers
> in case of dsc_disable, bigjoiner disable and also
> uncompressed joiner disable.
> 
> v2: Fix formatting
> 
> Suggested-by: Jani Nikula 
> Fixes: d961eb20adb6 (drm/i915/bigjoiner: atomic commit changes for 
> uncompressed joiner)
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3537
> Signed-off-by: Vandita Kulkarni 
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c 
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 19cd9531c115..b9828852a68f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -1161,12 +1161,12 @@ void intel_dsc_disable(const struct intel_crtc_state 
> *old_crtc_state)
>   struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> - if (!(old_crtc_state->dsc.compression_enable &&
> -   old_crtc_state->bigjoiner))
> - return;
> -
> - intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
> - intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
> + /* Disable only if either of them is enabled */
> + if (old_crtc_state->dsc.compression_enable ||
> + old_crtc_state->dsc.compression_enable) {

Vandita I think you have a copy paste error  the second condition should be 
old_crtc_state->bigjoiner ?

Manasi

> + intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
> + intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
> + }
>  }
>  
>  void intel_uncompressed_joiner_get_config(struct intel_crtc_state 
> *crtc_state)
> -- 
> 2.21.0.5.gaeb582a
> 
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for Add back the buddy allocator

[Patchwork]

== Series Details ==

Series: Add back the buddy allocator
URL   : https://patchwork.freedesktop.org/series/91110/
State : failure

== Summary ==

Applying: drm/i915/ttm: add ttm_buddy_man
Applying: drm/i915/ttm: add i915_sg_from_buddy_resource
Applying: drm/i915/ttm: Calculate the object placement at get_pages time
error: sha1 information is lacking or useless 
(drivers/gpu/drm/i915/gem/i915_gem_ttm.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0003 drm/i915/ttm: Calculate the object placement at get_pages 
time
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".


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Re: [Intel-gfx] [PATCH 09/13] drm/i915/doc: Include GuC ABI documentation

[Matthew Brost]

On Mon, Jun 07, 2021 at 09:38:58PM +0200, Michal Wajdeczko wrote:
> 
> 
> On 07.06.2021 19:45, Matthew Brost wrote:
> > On Mon, Jun 07, 2021 at 11:03:51AM -0700, Matthew Brost wrote:
> >> From: Michal Wajdeczko 
> >>
> >> GuC ABI documentation is now ready to be included in i915.rst
> >>
> >> Signed-off-by: Michal Wajdeczko 
> >> Signed-off-by: Matthew Brost 
> >> Cc: Piotr Piórkowski 
> > 
> > Michal - I noticed while putting this series together that there is
> > kernel doc in intel_guc_ct.* but this isn't inclued in i915.rst. Do you
> > think we should add the those here or in a new section (e.g. GuC CTBs)?
> > 
> > Let me know what you think and I can fix this up before this gets
> > merged.
> 
> What's in intel_guc_ct.* is implementation detail, that should be placed
> in separate section, while this patch adds pure ABI definitions that
> deserve its own dedicated section.
> 

Sounds good. Will fix that in the next rev.

> Btw, this patch does not need to be squashed with others, as it is about
> updating .rst only and is not breaking anything. Same for patch 1/13
> that introduces new definitions in new .h file.
> 

Agree. What I said in the cover letter isn't 100% correct as some of
patches probably don't have to be squashed. Next rev I'll go through
patch by patch and figure that part out.

Matt

> Michal
> 
> > 
> > With that, for this patch:
> > 
> > Reviewed-by: Matthew Brost 
> > 
> >> ---
> >>  Documentation/gpu/i915.rst | 8 
> >>  1 file changed, 8 insertions(+)
> >>
> >> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> >> index 42ce0196930a..c7846b1d9293 100644
> >> --- a/Documentation/gpu/i915.rst
> >> +++ b/Documentation/gpu/i915.rst
> >> @@ -518,6 +518,14 @@ GuC-based command submission
> >>  .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> >> :doc: GuC-based command submission
> >>  
> >> +GuC ABI
> >> +
> >> +
> >> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
> >> +.. kernel-doc:: 
> >> drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
> >> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
> >> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> >> +
> >>  HuC
> >>  ---
> >>  .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
> >> -- 
> >> 2.28.0
> >>
> >> ___
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> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > ___
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> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
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Re: [Intel-gfx] [PATCH 09/13] drm/i915/doc: Include GuC ABI documentation

[Michal Wajdeczko]

On 07.06.2021 19:45, Matthew Brost wrote:
> On Mon, Jun 07, 2021 at 11:03:51AM -0700, Matthew Brost wrote:
>> From: Michal Wajdeczko 
>>
>> GuC ABI documentation is now ready to be included in i915.rst
>>
>> Signed-off-by: Michal Wajdeczko 
>> Signed-off-by: Matthew Brost 
>> Cc: Piotr Piórkowski 
> 
> Michal - I noticed while putting this series together that there is
> kernel doc in intel_guc_ct.* but this isn't inclued in i915.rst. Do you
> think we should add the those here or in a new section (e.g. GuC CTBs)?
> 
> Let me know what you think and I can fix this up before this gets
> merged.

What's in intel_guc_ct.* is implementation detail, that should be placed
in separate section, while this patch adds pure ABI definitions that
deserve its own dedicated section.

Btw, this patch does not need to be squashed with others, as it is about
updating .rst only and is not breaking anything. Same for patch 1/13
that introduces new definitions in new .h file.

Michal

> 
> With that, for this patch:
> 
> Reviewed-by: Matthew Brost 
> 
>> ---
>>  Documentation/gpu/i915.rst | 8 
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
>> index 42ce0196930a..c7846b1d9293 100644
>> --- a/Documentation/gpu/i915.rst
>> +++ b/Documentation/gpu/i915.rst
>> @@ -518,6 +518,14 @@ GuC-based command submission
>>  .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> :doc: GuC-based command submission
>>  
>> +GuC ABI
>> +
>> +
>> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
>> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
>> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
>> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
>> +
>>  HuC
>>  ---
>>  .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
>> -- 
>> 2.28.0
>>
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Re: [Intel-gfx] [PATCH 13/13] drm/i915/guc: Update firmware to v62.0.0

[Matthew Brost]

On Mon, Jun 07, 2021 at 11:03:55AM -0700, Matthew Brost wrote:
> From: John Harrison 
> 
> Signed-off-by: John Harrison 
> Signed-off-by: Michal Wajdeczko 
> Signed-off-by: Matthew Brost 

Reviewed-by: Matthew Brost 

> ---
>  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 26 
>  1 file changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index df647c9a8d56..9f23e9de3237 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -48,19 +48,19 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
>   * firmware as TGL.
>   */
>  #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
> - fw_def(ALDERLAKE_S, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
> - fw_def(ROCKETLAKE,  0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
> - fw_def(TIGERLAKE,   0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
> - fw_def(JASPERLAKE,  0, guc_def(ehl, 49, 0, 1), huc_def(ehl,  9, 0, 0)) \
> - fw_def(ELKHARTLAKE, 0, guc_def(ehl, 49, 0, 1), huc_def(ehl,  9, 0, 0)) \
> - fw_def(ICELAKE, 0, guc_def(icl, 49, 0, 1), huc_def(icl,  9, 0, 0)) \
> - fw_def(COMETLAKE,   5, guc_def(cml, 49, 0, 1), huc_def(cml,  4, 0, 0)) \
> - fw_def(COMETLAKE,   0, guc_def(kbl, 49, 0, 1), huc_def(kbl,  4, 0, 0)) \
> - fw_def(COFFEELAKE,  0, guc_def(kbl, 49, 0, 1), huc_def(kbl,  4, 0, 0)) \
> - fw_def(GEMINILAKE,  0, guc_def(glk, 49, 0, 1), huc_def(glk,  4, 0, 0)) \
> - fw_def(KABYLAKE,0, guc_def(kbl, 49, 0, 1), huc_def(kbl,  4, 0, 0)) \
> - fw_def(BROXTON, 0, guc_def(bxt, 49, 0, 1), huc_def(bxt,  2, 0, 0)) \
> - fw_def(SKYLAKE, 0, guc_def(skl, 49, 0, 1), huc_def(skl,  2, 0, 0))
> + fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl,  7, 5, 0)) \
> + fw_def(ROCKETLAKE,  0, guc_def(tgl, 62, 0, 0), huc_def(tgl,  7, 5, 0)) \
> + fw_def(TIGERLAKE,   0, guc_def(tgl, 62, 0, 0), huc_def(tgl,  7, 5, 0)) \
> + fw_def(JASPERLAKE,  0, guc_def(ehl, 62, 0, 0), huc_def(ehl,  9, 0, 0)) \
> + fw_def(ELKHARTLAKE, 0, guc_def(ehl, 62, 0, 0), huc_def(ehl,  9, 0, 0)) \
> + fw_def(ICELAKE, 0, guc_def(icl, 62, 0, 0), huc_def(icl,  9, 0, 0)) \
> + fw_def(COMETLAKE,   5, guc_def(cml, 62, 0, 0), huc_def(cml,  4, 0, 0)) \
> + fw_def(COMETLAKE,   0, guc_def(kbl, 62, 0, 0), huc_def(kbl,  4, 0, 0)) \
> + fw_def(COFFEELAKE,  0, guc_def(kbl, 62, 0, 0), huc_def(kbl,  4, 0, 0)) \
> + fw_def(GEMINILAKE,  0, guc_def(glk, 62, 0, 0), huc_def(glk,  4, 0, 0)) \
> + fw_def(KABYLAKE,0, guc_def(kbl, 62, 0, 0), huc_def(kbl,  4, 0, 0)) \
> + fw_def(BROXTON, 0, guc_def(bxt, 62, 0, 0), huc_def(bxt,  2, 0, 0)) \
> + fw_def(SKYLAKE, 0, guc_def(skl, 62, 0, 0), huc_def(skl,  2, 0, 0))
>  
>  #define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \
>   "i915/" \
> -- 
> 2.28.0
> 
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Re: [Intel-gfx] [PATCH i-g-t] tests/kms_dp_dsc: Avoid SIGSEGV when release DRM connector.

[Mark Yacoub]

On Fri, Jun 4, 2021 at 2:48 PM Mark Yacoub  wrote:
>
> On Mon, May 31, 2021 at 11:34 AM Lee Shawn C  wrote:
> >
> > Got SIGSEGV fault while running kms_dp_dsc test but did not
> > connect DP DSC capable monitor on eDP/DP port. This test daemon
> > should "SKIP" test without any problem. We found kms_dp_dsc
> > can't get proper drmModeConnector and caused this SIGSEGV fault
> > when release it. Make sure drmModeConnector is available before
> > free it can avoid this issue.
> >
> Tested on ChromeOS on TGL (Delbin) and JSL (Drawlat).
Tested on ChromeOS AMD (Zork) with Kernel 5.4
> Tested-by: Mark Yacoub 
> > Signed-off-by: Lee Shawn C 
> > ---
> >  tests/kms_dp_dsc.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/tests/kms_dp_dsc.c b/tests/kms_dp_dsc.c
> > index 2446fd82bba3..ea7c9f4f72ce 100644
> > --- a/tests/kms_dp_dsc.c
> > +++ b/tests/kms_dp_dsc.c
> > @@ -262,7 +262,7 @@ igt_main
> > data_t data = {};
> > igt_output_t *output;
> > drmModeRes *res;
> > -   drmModeConnector *connector;
> > +   drmModeConnector *connector = NULL;
> > int i, test_conn_cnt, test_cnt;
> > int tests[] = {DRM_MODE_CONNECTOR_eDP, 
> > DRM_MODE_CONNECTOR_DisplayPort};
> >
> > @@ -311,7 +311,8 @@ igt_main
> > }
> >
> > igt_fixture {
> > -   drmModeFreeConnector(connector);
> > +   if (connector)
> > +   drmModeFreeConnector(connector);
> > drmModeFreeResources(res);
> > close(data.debugfs_fd);
> > close(data.drm_fd);
> > --
> > 2.17.1
> >
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dsc: Fix bigjoiner check in dsc_disable (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dsc: Fix bigjoiner check in dsc_disable (rev2)
URL   : https://patchwork.freedesktop.org/series/91006/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10184_full -> Patchwork_20294_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_20294_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@clone:
- shard-snb:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +6 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/shard-snb6/igt@gem_ctx_persiste...@clone.html

  * igt@gem_ctx_sseu@invalid-args:
- shard-tglb: NOTRUN -> [SKIP][2] ([i915#280])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/shard-tglb6/igt@gem_ctx_s...@invalid-args.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2842])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10184/shard-tglb7/igt@gem_exec_fair@basic-p...@vcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/shard-tglb1/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk:  [PASS][5] -> [FAIL][6] ([i915#2842]) +3 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10184/shard-glk3/igt@gem_exec_fair@basic-p...@vecs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/shard-glk4/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_whisper@basic-queues-all:
- shard-glk:  [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10184/shard-glk8/igt@gem_exec_whis...@basic-queues-all.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/shard-glk5/igt@gem_exec_whis...@basic-queues-all.html

  * igt@gem_exec_whisper@basic-queues-priority:
- shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([i915#1895])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10184/shard-iclb4/igt@gem_exec_whis...@basic-queues-priority.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/shard-iclb5/igt@gem_exec_whis...@basic-queues-priority.html

  * igt@gem_huc_copy@huc-copy:
- shard-kbl:  NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/shard-kbl1/igt@gem_huc_c...@huc-copy.html

  * igt@gem_mmap_gtt@big-copy-odd:
- shard-glk:  [PASS][12] -> [FAIL][13] ([i915#307])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10184/shard-glk7/igt@gem_mmap_...@big-copy-odd.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/shard-glk9/igt@gem_mmap_...@big-copy-odd.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-snb:  NOTRUN -> [WARN][14] ([i915#2658])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/shard-snb6/igt@gem_pwr...@basic-exhaustion.html

  * igt@gen7_exec_parse@basic-offset:
- shard-apl:  NOTRUN -> [SKIP][15] ([fdo#109271]) +155 similar 
issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/shard-apl2/igt@gen7_exec_pa...@basic-offset.html

  * igt@gen7_exec_parse@basic-rejected:
- shard-tglb: NOTRUN -> [SKIP][16] ([fdo#109289])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/shard-tglb6/igt@gen7_exec_pa...@basic-rejected.html

  * igt@gen9_exec_parse@batch-invalid-length:
- shard-snb:  NOTRUN -> [SKIP][17] ([fdo#109271]) +483 similar 
issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/shard-snb7/igt@gen9_exec_pa...@batch-invalid-length.html

  * igt@gen9_exec_parse@bb-oversize:
- shard-skl:  NOTRUN -> [SKIP][18] ([fdo#109271]) +59 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/shard-skl7/igt@gen9_exec_pa...@bb-oversize.html

  * igt@gen9_exec_parse@bb-start-out:
- shard-tglb: NOTRUN -> [SKIP][19] ([fdo#112306])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/shard-tglb6/igt@gen9_exec_pa...@bb-start-out.html

  * igt@i915_pm_dc@dc6-dpms:
- shard-skl:  NOTRUN -> [FAIL][20] ([i915#454]) +1 similar issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/shard-skl7/igt@i915_pm...@dc6-dpms.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#111614])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/shard-tglb6/igt@kms_big...@y-tiled-8bpp-rotate-270.html

  * igt@kms_chamelium@dp-edid-change-during-suspend:
- shard-apl:  NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827]) 
+13 similar issues
   [22]: 

Re: [Intel-gfx] [PATCH V2] x86/gpu: add JasperLake to gen11 early quirks

[Lucas De Marchi]

On Mon, Jun 07, 2021 at 07:42:16PM +0530, Tejas Upadhyay wrote:

Let's reserve JSL stolen memory for graphics.

JasperLake is a gen11 platform which is compatible with
ICL/EHL changes.

V1:
   - Added Cc: x...@kernel.org


except you didn't

Lucas De Marchi



Cc: x...@kernel.org
Signed-off-by: Tejas Upadhyay 
---
arch/x86/kernel/early-quirks.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index b553ffe9b985..38837dad46e6 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -549,6 +549,7 @@ static const struct pci_device_id intel_early_ids[] 
__initconst = {
INTEL_CNL_IDS(_early_ops),
INTEL_ICL_11_IDS(_early_ops),
INTEL_EHL_IDS(_early_ops),
+   INTEL_JSL_IDS(_early_ops),
INTEL_TGL_12_IDS(_early_ops),
INTEL_RKL_IDS(_early_ops),
INTEL_ADLS_IDS(_early_ops),
--
2.31.1

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[Intel-gfx] ✗ Fi.CI.BUILD: warning for Update firmware to v62.0.0

[Patchwork]

== Series Details ==

Series: Update firmware to v62.0.0
URL   : https://patchwork.freedesktop.org/series/91106/
State : warning

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  MODPOST modules-only.symvers
ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:150: recipe for target 'modules-only.symvers' failed
make[1]: *** [modules-only.symvers] Error 1
make[1]: *** Deleting file 'modules-only.symvers'
Makefile:1759: recipe for target 'modules' failed
make: *** [modules] Error 2

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/build_32bit.log
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[Intel-gfx] ✓ Fi.CI.BAT: success for Update firmware to v62.0.0

[Patchwork]

== Series Details ==

Series: Update firmware to v62.0.0
URL   : https://patchwork.freedesktop.org/series/91106/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10187 -> Patchwork_20298


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/index.html

Known issues


  Here are the changes found in Patchwork_20298 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_tiled_blits@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271]) +3 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/fi-kbl-soraka/igt@gem_tiled_bl...@basic.html

  * igt@i915_selftest@live@execlists:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][3] ([i915#2782] / [i915#3462] 
/ [i915#794])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][4] ([i915#1886] / [i915#2291])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][5] -> [INCOMPLETE][6] ([i915#2782])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka:  NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
- fi-kbl-soraka:  NOTRUN -> [FAIL][9] ([i915#1436] / [i915#3363])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/fi-kbl-soraka/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0:
- fi-kbl-soraka:  [INCOMPLETE][10] ([i915#155]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html

  * igt@i915_selftest@live@gt_pm:
- fi-cml-s:   [DMESG-FAIL][12] ([i915#2291]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-cml-s/igt@i915_selftest@live@gt_pm.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/fi-cml-s/igt@i915_selftest@live@gt_pm.html

  
 Warnings 

  * igt@i915_selftest@live@execlists:
- fi-cml-s:   [INCOMPLETE][14] ([i915#3462]) -> [DMESG-FAIL][15] 
([i915#3462])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-cml-s/igt@i915_selftest@l...@execlists.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/fi-cml-s/igt@i915_selftest@l...@execlists.html

  * igt@runner@aborted:
- fi-kbl-x1275:   [FAIL][16] ([i915#1436] / [i915#3363]) -> [FAIL][17] 
([i915#1436] / [i915#2426] / [i915#3363])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-kbl-x1275/igt@run...@aborted.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/fi-kbl-x1275/igt@run...@aborted.html
- fi-cfl-8700k:   [FAIL][18] ([i915#3363]) -> [FAIL][19] ([i915#2426] / 
[i915#3363])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-cfl-8700k/igt@run...@aborted.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/fi-cfl-8700k/igt@run...@aborted.html
- fi-glk-dsi: [FAIL][20] ([i915#3363] / [k.org#202321]) -> 
[FAIL][21] ([i915#2426] / [i915#3363] / [k.org#202321])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-glk-dsi/igt@run...@aborted.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-7500u:   [FAIL][22] ([i915#1436] / [i915#3363]) -> [FAIL][23] 
([i915#1436] / [i915#2426] / [i915#3363])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-kbl-7500u/igt@run...@aborted.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20298/fi-kbl-7500u/igt@run...@aborted.html
- fi-cfl-guc: [FAIL][24] ([i915#3363]) -> [FAIL][25] 

[Intel-gfx] [PATCH 5/6] drm/i915/ttm: switch over to ttm_buddy_man

[Matthew Auld]

Move back to the buddy allocator for managing device local memory, and
restore the lost mock selftests. Keep around the range manager related
bits, since we likely need this for managing stolen at some point. For
stolen we also don't need to reserve anything so no need to support a
generic reserve interface.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c   |  26 +--
 drivers/gpu/drm/i915/intel_memory_region.c|  55 +-
 drivers/gpu/drm/i915/intel_memory_region.h|  17 --
 drivers/gpu/drm/i915/intel_region_ttm.c   | 100 +++
 .../drm/i915/selftests/intel_memory_region.c  | 170 --
 drivers/gpu/drm/i915/selftests/mock_region.c  |  15 +-
 6 files changed, 168 insertions(+), 215 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 0b0fce445e9b..3f5624f36afc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -185,11 +185,7 @@ static bool i915_ttm_eviction_valuable(struct 
ttm_buffer_object *bo,
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
 
/* Will do for now. Our pinned objects are still on TTM's LRU lists */
-   if (!i915_gem_object_evictable(obj))
-   return false;
-
-   /* This isn't valid with a buddy allocator */
-   return ttm_bo_eviction_valuable(bo, place);
+   return i915_gem_object_evictable(obj);
 }
 
 static void i915_ttm_evict_flags(struct ttm_buffer_object *bo,
@@ -332,11 +328,15 @@ i915_ttm_resource_get_st(struct drm_i915_gem_object *obj,
struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
struct ttm_resource_manager *man =
ttm_manager_type(bo->bdev, res->mem_type);
+   struct intel_memory_region *mr = obj->mm.region;
 
if (man->use_tt)
return i915_ttm_tt_get_st(bo->ttm);
 
-   return intel_region_ttm_node_to_st(obj->mm.region, res->mm_node);
+   if (mr->is_range_manager)
+   return intel_region_ttm_node_to_st(mr, res);
+   else
+   return i915_sg_from_buddy_resource(res, mr->region.start);
 }
 
 static int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
@@ -661,20 +661,8 @@ int __i915_gem_ttm_object_init(struct intel_memory_region 
*mem,
static struct lock_class_key lock_class;
struct drm_i915_private *i915 = mem->i915;
enum ttm_bo_type bo_type;
-   size_t alignment = 0;
int ret;
 
-   /* Adjust alignment to GPU- and CPU huge page sizes. */
-
-   if (mem->is_range_manager) {
-   if (size >= SZ_1G)
-   alignment = SZ_1G >> PAGE_SHIFT;
-   else if (size >= SZ_2M)
-   alignment = SZ_2M >> PAGE_SHIFT;
-   else if (size >= SZ_64K)
-   alignment = SZ_64K >> PAGE_SHIFT;
-   }
-
drm_gem_private_object_init(>drm, >base, size);
i915_gem_object_init(obj, _gem_ttm_obj_ops, _class, flags);
i915_gem_object_init_memory_region(obj, mem);
@@ -696,7 +684,7 @@ int __i915_gem_ttm_object_init(struct intel_memory_region 
*mem,
 */
obj->base.vma_node.driver_private = i915_gem_to_ttm(obj);
ret = ttm_bo_init(>bdev, i915_gem_to_ttm(obj), size,
- bo_type, _sys_placement, alignment,
+ bo_type, _sys_placement, PAGE_SIZE,
  true, NULL, NULL, i915_ttm_bo_destroy);
 
if (!ret)
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c 
b/drivers/gpu/drm/i915/intel_memory_region.c
index 12fb5423fd5e..df59f884d37c 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -5,6 +5,7 @@
 
 #include "intel_memory_region.h"
 #include "i915_drv.h"
+#include "i915_ttm_buddy_manager.h"
 
 static const struct {
u16 class;
@@ -28,11 +29,6 @@ static const struct {
},
 };
 
-struct intel_region_reserve {
-   struct list_head link;
-   struct ttm_resource *res;
-};
-
 struct intel_memory_region *
 intel_memory_region_lookup(struct drm_i915_private *i915,
   u16 class, u16 instance)
@@ -63,27 +59,6 @@ intel_memory_region_by_type(struct drm_i915_private *i915,
return NULL;
 }
 
-/**
- * intel_memory_region_unreserve - Unreserve all previously reserved
- * ranges
- * @mem: The region containing the reserved ranges.
- */
-void intel_memory_region_unreserve(struct intel_memory_region *mem)
-{
-   struct intel_region_reserve *reserve, *next;
-
-   if (!mem->priv_ops || !mem->priv_ops->free)
-   return;
-
-   mutex_lock(>mm_lock);
-   list_for_each_entry_safe(reserve, next, >reserved, link) {
-   list_del(>link);
-   mem->priv_ops->free(mem, reserve->res);
-   kfree(reserve);
-   }
-   mutex_unlock(>mm_lock);
-}
-
 /**
  * intel_memory_region_reserve - 

[Intel-gfx] [PATCH 6/6] drm/i915/ttm: restore min_page_size behaviour

[Matthew Auld]

We now have bo->page_alignment which perfectly describes what we need if
we have min page size restrictions for lmem. We can also drop the flag
here, since this is the default behaviour for all objects.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c  | 3 +--
 drivers/gpu/drm/i915/intel_memory_region.h   | 3 +--
 drivers/gpu/drm/i915/intel_region_ttm.c  | 2 +-
 drivers/gpu/drm/i915/selftests/mock_region.c | 2 +-
 4 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 3f5624f36afc..eda6c258ea92 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -684,9 +684,8 @@ int __i915_gem_ttm_object_init(struct intel_memory_region 
*mem,
 */
obj->base.vma_node.driver_private = i915_gem_to_ttm(obj);
ret = ttm_bo_init(>bdev, i915_gem_to_ttm(obj), size,
- bo_type, _sys_placement, PAGE_SIZE,
+ bo_type, _sys_placement, mem->min_page_size,
  true, NULL, NULL, i915_ttm_bo_destroy);
-
if (!ret)
obj->ttm.created = true;
 
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h 
b/drivers/gpu/drm/i915/intel_memory_region.h
index b04fb22726d9..2be8433d373a 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -40,8 +40,7 @@ enum intel_region_id {
 #define REGION_STOLEN_SMEM   BIT(INTEL_REGION_STOLEN_SMEM)
 #define REGION_STOLEN_LMEM   BIT(INTEL_REGION_STOLEN_LMEM)
 
-#define I915_ALLOC_MIN_PAGE_SIZE  BIT(0)
-#define I915_ALLOC_CONTIGUOUS BIT(1)
+#define I915_ALLOC_CONTIGUOUS BIT(0)
 
 #define for_each_memory_region(mr, i915, id) \
for (id = 0; id < ARRAY_SIZE((i915)->mm.regions); id++) \
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c 
b/drivers/gpu/drm/i915/intel_region_ttm.c
index 23af995f7b67..59fa78225852 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -153,7 +153,7 @@ intel_region_ttm_node_alloc(struct intel_memory_region *mem,
int ret;
 
mock_bo.base.size = size;
-   mock_bo.page_alignment = PAGE_SIZE;
+   mock_bo.page_alignment = mem->min_page_size;
place.flags = flags;
 
ret = man->func->alloc(man, _bo, , );
diff --git a/drivers/gpu/drm/i915/selftests/mock_region.c 
b/drivers/gpu/drm/i915/selftests/mock_region.c
index d3e4e6573cb9..6ce0f9dacad7 100644
--- a/drivers/gpu/drm/i915/selftests/mock_region.c
+++ b/drivers/gpu/drm/i915/selftests/mock_region.c
@@ -28,7 +28,7 @@ static int mock_region_get_pages(struct drm_i915_gem_object 
*obj)
struct sg_table *pages;
int err;
 
-   flags = I915_ALLOC_MIN_PAGE_SIZE;
+   flags = 0;
if (obj->flags & I915_BO_ALLOC_CONTIGUOUS)
flags |= TTM_PL_FLAG_CONTIGUOUS;
 
-- 
2.26.3

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[Intel-gfx] [PATCH 4/6] drm/i915/ttm: pass along the I915_BO_ALLOC_CONTIGUOUS

[Matthew Auld]

Currently we just ignore the I915_BO_ALLOC_CONTIGUOUS flag, which is
fine since everything is already contiguous with the ttm range manager.
However in the next patch we want to switch over to the ttm buddy
manager, where allocations are by default not contiguous.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 73d52df8f2be..0b0fce445e9b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -86,10 +86,18 @@ i915_ttm_select_tt_caching(const struct drm_i915_gem_object 
*obj)
 
 static void
 i915_ttm_place_from_region(const struct intel_memory_region *mr,
-  struct ttm_place *place)
+  struct ttm_place *place,
+  unsigned int flags)
 {
memset(place, 0, sizeof(*place));
place->mem_type = intel_region_to_ttm_type(mr);
+
+   switch(mr->type) {
+   case INTEL_MEMORY_LOCAL:
+   if (flags & I915_BO_ALLOC_CONTIGUOUS)
+   place->flags = TTM_PL_FLAG_CONTIGUOUS;
+   break;
+   }
 }
 
 static void
@@ -100,15 +108,16 @@ i915_ttm_placement_from_obj(const struct 
drm_i915_gem_object *obj,
 {
unsigned int i;
unsigned int num_allowed = obj->mm.n_placements;
+   unsigned int flags = obj->flags;
 
placement->num_placement = 1;
i915_ttm_place_from_region(num_allowed ? obj->mm.placements[0] :
-  obj->mm.region, requested);
+  obj->mm.region, requested, flags);
 
/* Cache this on object? */
placement->num_busy_placement = num_allowed;
for (i = 0; i < placement->num_busy_placement; ++i)
-   i915_ttm_place_from_region(obj->mm.placements[i], busy + i);
+   i915_ttm_place_from_region(obj->mm.placements[i], busy + i, 
flags);
 
if (num_allowed == 0) {
*busy = *requested;
-- 
2.26.3

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[Intel-gfx] [PATCH 3/6] drm/i915/ttm: Calculate the object placement at get_pages time

[Matthew Auld]

From: Thomas Hellström 

Instead of relying on a static placement, calculate at get_pages() time.
This should work for LMEM regions and system for now. For stolen we need
to take preallocated range into account. That well be added later.

Signed-off-by: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 69 +
 drivers/gpu/drm/i915/intel_region_ttm.c |  8 ++-
 drivers/gpu/drm/i915/intel_region_ttm.h |  2 +
 3 files changed, 68 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 9dd6e4f69d53..73d52df8f2be 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -24,6 +24,11 @@
 #define I915_TTM_PRIO_NO_PAGES  1
 #define I915_TTM_PRIO_HAS_PAGES 2
 
+/*
+ * Size of struct ttm_place vector in on-stack struct ttm_placement allocs
+ */
+#define I915_TTM_MAX_PLACEMENTS 10
+
 /**
  * struct i915_ttm_tt - TTM page vector with additional private information
  * @ttm: The base TTM page vector.
@@ -56,13 +61,6 @@ static const struct ttm_place lmem0_sys_placement_flags[] = {
}
 };
 
-static struct ttm_placement i915_lmem0_placement = {
-   .num_placement = 1,
-   .placement = _sys_placement_flags[0],
-   .num_busy_placement = 1,
-   .busy_placement = _sys_placement_flags[0],
-};
-
 static struct ttm_placement i915_sys_placement = {
.num_placement = 1,
.placement = _sys_placement_flags[1],
@@ -72,6 +70,55 @@ static struct ttm_placement i915_sys_placement = {
 
 static void i915_ttm_adjust_lru(struct drm_i915_gem_object *obj);
 
+static enum ttm_caching
+i915_ttm_select_tt_caching(const struct drm_i915_gem_object *obj)
+{
+   /*
+* Objects only allowed in system get cached cpu-mappings.
+* Other objects get WC mapping for now. Even if in system.
+*/
+   if (obj->mm.region->type == INTEL_MEMORY_SYSTEM &&
+   obj->mm.n_placements <= 1)
+   return ttm_cached;
+
+   return ttm_write_combined;
+}
+
+static void
+i915_ttm_place_from_region(const struct intel_memory_region *mr,
+  struct ttm_place *place)
+{
+   memset(place, 0, sizeof(*place));
+   place->mem_type = intel_region_to_ttm_type(mr);
+}
+
+static void
+i915_ttm_placement_from_obj(const struct drm_i915_gem_object *obj,
+   struct ttm_place *requested,
+   struct ttm_place *busy,
+   struct ttm_placement *placement)
+{
+   unsigned int i;
+   unsigned int num_allowed = obj->mm.n_placements;
+
+   placement->num_placement = 1;
+   i915_ttm_place_from_region(num_allowed ? obj->mm.placements[0] :
+  obj->mm.region, requested);
+
+   /* Cache this on object? */
+   placement->num_busy_placement = num_allowed;
+   for (i = 0; i < placement->num_busy_placement; ++i)
+   i915_ttm_place_from_region(obj->mm.placements[i], busy + i);
+
+   if (num_allowed == 0) {
+   *busy = *requested;
+   placement->num_busy_placement = 1;
+   }
+
+   placement->placement = requested;
+   placement->busy_placement = busy;
+}
+
 static struct ttm_tt *i915_ttm_tt_create(struct ttm_buffer_object *bo,
 uint32_t page_flags)
 {
@@ -89,7 +136,8 @@ static struct ttm_tt *i915_ttm_tt_create(struct 
ttm_buffer_object *bo,
man->use_tt)
page_flags |= TTM_PAGE_FLAG_ZERO_ALLOC;
 
-   ret = ttm_tt_init(_tt->ttm, bo, page_flags, ttm_write_combined);
+   ret = ttm_tt_init(_tt->ttm, bo, page_flags,
+ i915_ttm_select_tt_caching(obj));
if (ret) {
kfree(i915_tt);
return NULL;
@@ -414,10 +462,13 @@ static int i915_ttm_get_pages(struct drm_i915_gem_object 
*obj)
.no_wait_gpu = false,
};
struct sg_table *st;
+   struct ttm_place requested, busy[I915_TTM_MAX_PLACEMENTS];
+   struct ttm_placement placement;
int ret;
 
/* Move to the requested placement. */
-   ret = ttm_bo_validate(bo, _lmem0_placement, );
+   i915_ttm_placement_from_obj(obj, , busy, );
+   ret = ttm_bo_validate(bo, , );
if (ret)
return ret == -ENOSPC ? -ENXIO : ret;
 
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c 
b/drivers/gpu/drm/i915/intel_region_ttm.c
index 27fe0668d094..5a664f6cc93f 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -50,12 +50,16 @@ void intel_region_ttm_device_fini(struct drm_i915_private 
*dev_priv)
  * driver-private types for now, reserving TTM_PL_VRAM for stolen
  * memory and TTM_PL_TT for GGTT use if decided to implement this.
  */
-static int intel_region_to_ttm_type(struct intel_memory_region *mem)
+int intel_region_to_ttm_type(const struct intel_memory_region *mem)
 {

[Intel-gfx] [PATCH 2/6] drm/i915/ttm: add i915_sg_from_buddy_resource

[Matthew Auld]

We need to be able to build an sg table from our list of buddy blocks,
so that we can later plug this into our ttm backend, and replace our use
of the range manager.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
---
 drivers/gpu/drm/i915/i915_scatterlist.c | 80 +
 drivers/gpu/drm/i915/i915_scatterlist.h |  5 ++
 2 files changed, 85 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_scatterlist.c 
b/drivers/gpu/drm/i915/i915_scatterlist.c
index 69e9e6c3135e..0959fe3efbbb 100644
--- a/drivers/gpu/drm/i915/i915_scatterlist.c
+++ b/drivers/gpu/drm/i915/i915_scatterlist.c
@@ -6,6 +6,9 @@
 
 #include "i915_scatterlist.h"
 
+#include "i915_buddy.h"
+#include "i915_ttm_buddy_manager.h"
+
 #include 
 
 #include 
@@ -104,6 +107,83 @@ struct sg_table *i915_sg_from_mm_node(const struct 
drm_mm_node *node,
return st;
 }
 
+/**
+ * i915_sg_from_buddy_resource - Create an sg_table from a struct
+ * i915_buddy_block list
+ * @res: The i915_ttm_buddy_resource.
+ * @region_start: An offset to add to the dma addresses of the sg list.
+ *
+ * Create a struct sg_table, initializing it from struct i915_buddy_block list,
+ * taking a maximum segment length into account, splitting into segments
+ * if necessary.
+ *
+ * Return: A pointer to a kmalloced struct sg_table on success, negative
+ * error code cast to an error pointer on failure.
+ */
+struct sg_table *i915_sg_from_buddy_resource(struct ttm_resource *res,
+u64 region_start)
+{
+   struct i915_ttm_buddy_resource *bman_res = to_ttm_buddy_resource(res);
+   struct i915_buddy_mm *mm = bman_res->mm;
+   const u64 size = res->num_pages << PAGE_SHIFT;
+   const u64 max_segment = UINT_MAX;
+   struct list_head *blocks = _res->blocks;
+   struct i915_buddy_block *block;
+   struct scatterlist *sg;
+   struct sg_table *st;
+   resource_size_t prev_end;
+
+   GEM_BUG_ON(list_empty(blocks));
+
+   st = kmalloc(sizeof(*st), GFP_KERNEL);
+   if (!st)
+   return ERR_PTR(-ENOMEM);
+
+   if (sg_alloc_table(st, size >> PAGE_SHIFT, GFP_KERNEL)) {
+   kfree(st);
+   return ERR_PTR(-ENOMEM);
+   }
+
+   sg = st->sgl;
+   st->nents = 0;
+   prev_end = (resource_size_t)-1;
+
+   list_for_each_entry(block, blocks, link) {
+   u64 block_size, offset;
+
+   block_size = min_t(u64, size, i915_buddy_block_size(mm, block));
+   offset = i915_buddy_block_offset(block);
+
+   while (block_size) {
+   u64 len;
+
+   if (offset != prev_end || sg->length >= max_segment) {
+   if (st->nents)
+   sg = __sg_next(sg);
+
+   sg_dma_address(sg) = region_start + offset;
+   sg_dma_len(sg) = 0;
+   sg->length = 0;
+   st->nents++;
+   }
+
+   len = min(block_size, max_segment - sg->length);
+   sg->length += len;
+   sg_dma_len(sg) += len;
+
+   offset += len;
+   block_size -= len;
+
+   prev_end = offset;
+   }
+   }
+
+   sg_mark_end(sg);
+   i915_sg_trim(st);
+
+   return st;
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftests/scatterlist.c"
 #endif
diff --git a/drivers/gpu/drm/i915/i915_scatterlist.h 
b/drivers/gpu/drm/i915/i915_scatterlist.h
index 5acca45ea981..b8bd5925b03f 100644
--- a/drivers/gpu/drm/i915/i915_scatterlist.h
+++ b/drivers/gpu/drm/i915/i915_scatterlist.h
@@ -14,6 +14,7 @@
 #include "i915_gem.h"
 
 struct drm_mm_node;
+struct ttm_resource;
 
 /*
  * Optimised SGL iterator for GEM objects
@@ -145,4 +146,8 @@ bool i915_sg_trim(struct sg_table *orig_st);
 
 struct sg_table *i915_sg_from_mm_node(const struct drm_mm_node *node,
  u64 region_start);
+
+struct sg_table *i915_sg_from_buddy_resource(struct ttm_resource *res,
+u64 region_start);
+
 #endif
-- 
2.26.3

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[Intel-gfx] [PATCH 1/6] drm/i915/ttm: add ttm_buddy_man

[Matthew Auld]

Add back our standalone i915_buddy allocator and integrate it into a
ttm_resource_manager. This will plug into our ttm backend for managing
device local-memory in the next couple of patches.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
---
 drivers/gpu/drm/i915/Makefile |   2 +
 drivers/gpu/drm/i915/i915_buddy.c | 412 +
 drivers/gpu/drm/i915/i915_buddy.h | 133 +++
 drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 246 ++
 drivers/gpu/drm/i915/i915_ttm_buddy_manager.h |  56 ++
 drivers/gpu/drm/i915/selftests/i915_buddy.c   | 789 ++
 6 files changed, 1638 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/i915_buddy.c
 create mode 100644 drivers/gpu/drm/i915/i915_buddy.h
 create mode 100644 drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
 create mode 100644 drivers/gpu/drm/i915/i915_ttm_buddy_manager.h
 create mode 100644 drivers/gpu/drm/i915/selftests/i915_buddy.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f57dfc74d6ce..6c84e96ab26a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -162,6 +162,7 @@ gem-y += \
 i915-y += \
  $(gem-y) \
  i915_active.o \
+ i915_buddy.o \
  i915_cmd_parser.o \
  i915_gem_evict.o \
  i915_gem_gtt.o \
@@ -171,6 +172,7 @@ i915-y += \
  i915_request.o \
  i915_scheduler.o \
  i915_trace_points.o \
+ i915_ttm_buddy_manager.o \
  i915_vma.o \
  intel_wopcm.o
 
diff --git a/drivers/gpu/drm/i915/i915_buddy.c 
b/drivers/gpu/drm/i915/i915_buddy.c
new file mode 100644
index ..29dd7d0310c1
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_buddy.c
@@ -0,0 +1,412 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include 
+
+#include "i915_buddy.h"
+
+#include "i915_gem.h"
+#include "i915_utils.h"
+
+static struct i915_buddy_block *i915_block_alloc(struct i915_buddy_mm *mm,
+struct i915_buddy_block 
*parent,
+unsigned int order,
+u64 offset)
+{
+   struct i915_buddy_block *block;
+
+   GEM_BUG_ON(order > I915_BUDDY_MAX_ORDER);
+
+   block = kmem_cache_zalloc(mm->slab_blocks, GFP_KERNEL);
+   if (!block)
+   return NULL;
+
+   block->header = offset;
+   block->header |= order;
+   block->parent = parent;
+
+   GEM_BUG_ON(block->header & I915_BUDDY_HEADER_UNUSED);
+   return block;
+}
+
+static void i915_block_free(struct i915_buddy_mm *mm,
+   struct i915_buddy_block *block)
+{
+   kmem_cache_free(mm->slab_blocks, block);
+}
+
+static void mark_allocated(struct i915_buddy_block *block)
+{
+   block->header &= ~I915_BUDDY_HEADER_STATE;
+   block->header |= I915_BUDDY_ALLOCATED;
+
+   list_del(>link);
+}
+
+static void mark_free(struct i915_buddy_mm *mm,
+ struct i915_buddy_block *block)
+{
+   block->header &= ~I915_BUDDY_HEADER_STATE;
+   block->header |= I915_BUDDY_FREE;
+
+   list_add(>link,
+>free_list[i915_buddy_block_order(block)]);
+}
+
+static void mark_split(struct i915_buddy_block *block)
+{
+   block->header &= ~I915_BUDDY_HEADER_STATE;
+   block->header |= I915_BUDDY_SPLIT;
+
+   list_del(>link);
+}
+
+int i915_buddy_init(struct i915_buddy_mm *mm, u64 size, u64 chunk_size)
+{
+   unsigned int i;
+   u64 offset;
+
+   if (size < chunk_size)
+   return -EINVAL;
+
+   if (chunk_size < PAGE_SIZE)
+   return -EINVAL;
+
+   if (!is_power_of_2(chunk_size))
+   return -EINVAL;
+
+   size = round_down(size, chunk_size);
+
+   mm->size = size;
+   mm->chunk_size = chunk_size;
+   mm->max_order = ilog2(size) - ilog2(chunk_size);
+
+   GEM_BUG_ON(mm->max_order > I915_BUDDY_MAX_ORDER);
+
+   mm->slab_blocks = KMEM_CACHE(i915_buddy_block, SLAB_HWCACHE_ALIGN);
+   if (!mm->slab_blocks)
+   return -ENOMEM;
+
+   mm->free_list = kmalloc_array(mm->max_order + 1,
+ sizeof(struct list_head),
+ GFP_KERNEL);
+   if (!mm->free_list)
+   goto out_destroy_slab;
+
+   for (i = 0; i <= mm->max_order; ++i)
+   INIT_LIST_HEAD(>free_list[i]);
+
+   mm->n_roots = hweight64(size);
+
+   mm->roots = kmalloc_array(mm->n_roots,
+ sizeof(struct i915_buddy_block *),
+ GFP_KERNEL);
+   if (!mm->roots)
+   goto out_free_list;
+
+   offset = 0;
+   i = 0;
+
+   /*
+* Split into power-of-two blocks, in case we are given a size that is
+* not itself a power-of-two.
+*/
+   do {
+   struct i915_buddy_block *root;
+  

[Intel-gfx] [PATCH 0/6] Add back the buddy allocator

[Matthew Auld]

Needs to be applied on top of:
https://patchwork.freedesktop.org/series/90681/

Matthew Auld (5):
  drm/i915/ttm: add ttm_buddy_man
  drm/i915/ttm: add i915_sg_from_buddy_resource
  drm/i915/ttm: pass along the I915_BO_ALLOC_CONTIGUOUS
  drm/i915/ttm: switch over to ttm_buddy_man
  drm/i915/ttm: restore min_page_size behaviour

Thomas Hellström (1):
  drm/i915/ttm: Calculate the object placement at get_pages time

 drivers/gpu/drm/i915/Makefile |   2 +
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c   | 105 ++-
 drivers/gpu/drm/i915/i915_buddy.c | 412 +
 drivers/gpu/drm/i915/i915_buddy.h | 133 +++
 drivers/gpu/drm/i915/i915_scatterlist.c   |  80 ++
 drivers/gpu/drm/i915/i915_scatterlist.h   |   5 +
 drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 246 ++
 drivers/gpu/drm/i915/i915_ttm_buddy_manager.h |  56 ++
 drivers/gpu/drm/i915/intel_memory_region.c|  55 +-
 drivers/gpu/drm/i915/intel_memory_region.h|  20 +-
 drivers/gpu/drm/i915/intel_region_ttm.c   | 108 +--
 drivers/gpu/drm/i915/intel_region_ttm.h   |   2 +
 drivers/gpu/drm/i915/selftests/i915_buddy.c   | 789 ++
 .../drm/i915/selftests/intel_memory_region.c  | 170 ++--
 drivers/gpu/drm/i915/selftests/mock_region.c  |  17 +-
 15 files changed, 1970 insertions(+), 230 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_buddy.c
 create mode 100644 drivers/gpu/drm/i915/i915_buddy.h
 create mode 100644 drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
 create mode 100644 drivers/gpu/drm/i915/i915_ttm_buddy_manager.h
 create mode 100644 drivers/gpu/drm/i915/selftests/i915_buddy.c

-- 
2.26.3

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Re: [Intel-gfx] [PATCH 12/13] drm/i915/guc: Unified GuC log

[Matthew Brost]

On Mon, Jun 07, 2021 at 11:03:54AM -0700, Matthew Brost wrote:
> From: John Harrison 
> 
> GuC v57 unified the 'DPC' and 'ISR' buffers into a single buffer with
> the option for it to be larger.
> 
> Signed-off-by: Matthew Brost 

Reviewed-by: Matthew Brost 

> Signed-off-by: John Harrison 
> Cc: Alan Previn 
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c  | 15 ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h |  9 +++
>  drivers/gpu/drm/i915/gt/uc/intel_guc_log.c  | 29 +++--
>  drivers/gpu/drm/i915/gt/uc/intel_guc_log.h  |  6 ++---
>  4 files changed, 20 insertions(+), 39 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index b773567cb080..6661dcb02239 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -219,24 +219,19 @@ static u32 guc_ctl_log_params_flags(struct intel_guc 
> *guc)
>  
>   BUILD_BUG_ON(!CRASH_BUFFER_SIZE);
>   BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, UNIT));
> - BUILD_BUG_ON(!DPC_BUFFER_SIZE);
> - BUILD_BUG_ON(!IS_ALIGNED(DPC_BUFFER_SIZE, UNIT));
> - BUILD_BUG_ON(!ISR_BUFFER_SIZE);
> - BUILD_BUG_ON(!IS_ALIGNED(ISR_BUFFER_SIZE, UNIT));
> + BUILD_BUG_ON(!DEBUG_BUFFER_SIZE);
> + BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, UNIT));
>  
>   BUILD_BUG_ON((CRASH_BUFFER_SIZE / UNIT - 1) >
>   (GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT));
> - BUILD_BUG_ON((DPC_BUFFER_SIZE / UNIT - 1) >
> - (GUC_LOG_DPC_MASK >> GUC_LOG_DPC_SHIFT));
> - BUILD_BUG_ON((ISR_BUFFER_SIZE / UNIT - 1) >
> - (GUC_LOG_ISR_MASK >> GUC_LOG_ISR_SHIFT));
> + BUILD_BUG_ON((DEBUG_BUFFER_SIZE / UNIT - 1) >
> + (GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT));
>  
>   flags = GUC_LOG_VALID |
>   GUC_LOG_NOTIFY_ON_HALF_FULL |
>   FLAG |
>   ((CRASH_BUFFER_SIZE / UNIT - 1) << GUC_LOG_CRASH_SHIFT) |
> - ((DPC_BUFFER_SIZE / UNIT - 1) << GUC_LOG_DPC_SHIFT) |
> - ((ISR_BUFFER_SIZE / UNIT - 1) << GUC_LOG_ISR_SHIFT) |
> + ((DEBUG_BUFFER_SIZE / UNIT - 1) << GUC_LOG_DEBUG_SHIFT) |
>   (offset << GUC_LOG_BUF_ADDR_SHIFT);
>  
>   #undef UNIT
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index f2df5c11c11d..617ec601648d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -81,10 +81,8 @@
>  #define   GUC_LOG_ALLOC_IN_MEGABYTE  (1 << 3)
>  #define   GUC_LOG_CRASH_SHIFT4
>  #define   GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT)
> -#define   GUC_LOG_DPC_SHIFT  6
> -#define   GUC_LOG_DPC_MASK   (0x7 << GUC_LOG_DPC_SHIFT)
> -#define   GUC_LOG_ISR_SHIFT  9
> -#define   GUC_LOG_ISR_MASK   (0x7 << GUC_LOG_ISR_SHIFT)
> +#define   GUC_LOG_DEBUG_SHIFT6
> +#define   GUC_LOG_DEBUG_MASK (0xF << GUC_LOG_DEBUG_SHIFT)
>  #define   GUC_LOG_BUF_ADDR_SHIFT 12
>  
>  #define GUC_CTL_WA   1
> @@ -311,8 +309,7 @@ struct guc_ads {
>  /* GuC logging structures */
>  
>  enum guc_log_buffer_type {
> - GUC_ISR_LOG_BUFFER,
> - GUC_DPC_LOG_BUFFER,
> + GUC_DEBUG_LOG_BUFFER,
>   GUC_CRASH_DUMP_LOG_BUFFER,
>   GUC_MAX_LOG_BUFFER
>  };
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> index c36d5eb5bbb9..ac0931f0374b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> @@ -197,10 +197,8 @@ static bool guc_check_log_buf_overflow(struct 
> intel_guc_log *log,
>  static unsigned int guc_get_log_buffer_size(enum guc_log_buffer_type type)
>  {
>   switch (type) {
> - case GUC_ISR_LOG_BUFFER:
> - return ISR_BUFFER_SIZE;
> - case GUC_DPC_LOG_BUFFER:
> - return DPC_BUFFER_SIZE;
> + case GUC_DEBUG_LOG_BUFFER:
> + return DEBUG_BUFFER_SIZE;
>   case GUC_CRASH_DUMP_LOG_BUFFER:
>   return CRASH_BUFFER_SIZE;
>   default:
> @@ -245,7 +243,7 @@ static void guc_read_update_log_buffer(struct 
> intel_guc_log *log)
>   src_data += PAGE_SIZE;
>   dst_data += PAGE_SIZE;
>  
> - for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
> + for (type = GUC_DEBUG_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
>   /*
>* Make a copy of the state structure, inside GuC log buffer
>* (which is uncached mapped), on the stack to avoid reading
> @@ -463,21 +461,16 @@ int intel_guc_log_create(struct intel_guc_log *log)
>*  +===+ 00B
>*  |Crash dump state header|
>*  +---+ 32B
> -  *  |   DPC state header|
> +  *  |  Debug state 

Re: [Intel-gfx] [PATCH 0/9] Enhance pipe color support for multi segmented luts

[Shankar, Uma]

> -Original Message-
> From: dri-devel  On Behalf Of Pekka
> Paalanen
> Sent: Monday, June 7, 2021 1:00 PM
> To: Harry Wentland 
> Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma ;
> Sebastian Wick ; dri-de...@lists.freedesktop.org;
> Modem, Bhanuprakash 
> Subject: Re: [PATCH 0/9] Enhance pipe color support for multi segmented luts
> 
> On Fri, 4 Jun 2021 14:51:25 -0400
> Harry Wentland  wrote:
> 
> > On 2021-06-01 6:41 a.m., Uma Shankar wrote:
> > > Modern hardwares have multi segmented lut approach to prioritize the
> > > darker regions of the spectrum. This series introduces a new UAPI to
> > > define the lut ranges supported by the respective hardware.
> > >
> > > This also enables Pipe Color Management Support for Intel's XE_LPD hw.
> > > Enable Support for Pipe Degamma with the increased lut samples
> > > supported by hardware. This also adds support for newly introduced
> > > Logarithmic Gamma for XE_LPD. Also added the gamma readout support.
> > >
> > > The Logarithmic gamma implementation on XE_LPD is non linear and
> > > adds 25 segments with non linear lut samples in each segment. The
> > > expectation is userspace will create the luts as per this
> > > distribution and pass the final samples to driver to be programmed in 
> > > hardware.
> > >
> >
> > Is this design targetting Intel XE_LPD HW in particular or is it
> > intended to be generic?
> >
> > If this is intended to be generic I think it would benefit from a lot
> > more documentation. At this point it's difficult for me to see how to
> > adapt this to AMD HW. It would take me a while to be comfortable to
> > make a call on whether we can use it or not. And what about other vendors?
> >
> > I think we need to be cautious in directly exposing HW functionality
> > through UAPI. The CM parts of AMD HW seem to be changing in some way
> > each generation and it looks like the same is true for Intel. The
> > trouble we have with adapting the old gamma/degamma properties to
> > modern HW is some indication to me that this approach is somewhat 
> > problematic.
> >
> > It would be useful to understand and document the specific use-cases
> > we want to provide to userspace implementers with this functionality.
> > Do we want to support modern transfer functions such as PQ or HLG? If
> > so, it might be beneficial to have an API to explicitly specify that,
> > and then use LUT tables in drivers that are optimized for the implementing 
> > HW.
> 
> Hi Harry,
> 
> from my very limited understanding so far, enum might be fine for PQ, but HLG 
> is not
> just one transfer function, although it may often be confused as one. PQ and 
> HLG
> are fundamentally different designs to HDR broadcasting I believe. It would be
> unfortunate to make a mistake here, engraving it into UAPI.

Yes Pekka, putting this in UAPI may limit us.

> > Or is the use case tone mapping? If so, would a parametric definition
> > of tone mapping be easier to manage?
> 
> A very good question at least I have no idea about.

Responded on earlier mail in thread. For non linear lut (gamma block), usecase 
is primarily tone
mapping but there are implementations where non linear blending is seeked 
(AFAIR Android does that),
so it leaves room for those usecases as well.

Regards,
Uma Shankar
> 
> Thanks,
> pq
> 
> > > +-+--+
> > > | x   |  2 pow x segment|No of Entries
> > > | |  0  | 1  |
> > > | 0   |  1  | 1  |
> > > | 1   |  2  | 2  |
> > > | 2   |  4  | 2  |
> > > | 3   |  8  | 2  |
> > > | 4   |  16 | 2  |
> > > | 5   |  32 | 4  |
> > > | 6   |  64 | 4  |
> > > | 7   |  128| 4  |
> > > | 8   |  256| 8  |
> > > | 9   |  512| 8  |
> > > | 10  |  1024   | 8  |
> > > | 11  |  2048   | 16 |
> > > | 12  |  4096   | 16 |
> > > | 13  |  8192   | 16 |
> > > | 14  |  16384  | 32 |
> > > | 15  |  32768  | 32 |
> > > | 16  |  65536  | 64 |
> > > | 17  |  131072 | 64 |
> > > | 18  |  262144 | 64 |
> > > | 19  |  524288 | 32 |
> > > | 20  |  1048576| 32 |
> > > | 21  |  2097152| 32 |
> > > | 22  |  4194304| 32 |
> > > | 23  |  8388608| 32 |
> > > | 24  |  16777216   | 1  |
> > > | | Total Entries   | 511|
> > >  -+-++
> > >
> > > Credits: Special mention and credits to Ville Syrjala for coming up
> > > with a design for this feature and inputs. This series is based on
> > > his original design.
> > >
> > > Note: Userspace support for this new UAPI will be done on Chrome and
> > > plan is to get this supported on mutter as well. We will notify the
> > > 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Update firmware to v62.0.0

[Patchwork]

== Series Details ==

Series: Update firmware to v62.0.0
URL   : https://patchwork.freedesktop.org/series/91106/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1893:21:expected struct 
i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1893:21:got void [noderef] 
__iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1893:21: warning: incorrect type 
in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1207:24: warning: Using plain 
integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 
16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative 
(-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative 
(-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' 
- different lock contexts for basic block

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Update firmware to v62.0.0

[Patchwork]

== Series Details ==

Series: Update firmware to v62.0.0
URL   : https://patchwork.freedesktop.org/series/91106/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5735522498b2 drm/i915/guc: Introduce unified HXG messages
067ec8d0b970 drm/i915/guc: Update MMIO based communication
c3c36fc8703e drm/i915/guc: Update CTB response status definition
4239eebfa25e drm/i915/guc: Support per context scheduling policies
fed4d47fabb2 drm/i915/guc: Add flag for mark broken CTB
98f39fdfdab9 drm/i915/guc: New definition of the CTB descriptor
f8e5520d648c drm/i915/guc: New definition of the CTB registration action
-:55: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each 
line
#55: FILE: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h:40:
+ *  
+---+---+--+
+*

-:56: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each 
line
#56: FILE: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h:41:
+*
+ *  
+---+---+--+

-:75: CHECK:CAMELCASE: Avoid CamelCase: 
#75: FILE: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h:60:
+#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_2_DESC_ADDR  
GUC_HXG_REQUEST_MSG_n_DATAn

-:107: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each 
line
#107: FILE: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h:92:
+ *  
+---+---+--+
+*

-:108: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each 
line
#108: FILE: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h:93:
+*
+ *  
+---+---+--+

total: 0 errors, 4 warnings, 1 checks, 261 lines checked
fe305e722d41 drm/i915/guc: New CTB based communication
4143260c8c99 drm/i915/doc: Include GuC ABI documentation
65b657159e48 drm/i915/guc: Kill guc_clients.ct_pool
1fcb4faa9a92 drm/i915/guc: Kill ads.client_info
14d7602095b1 drm/i915/guc: Unified GuC log
1998c178877b drm/i915/guc: Update firmware to v62.0.0
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

total: 0 errors, 1 warnings, 0 checks, 32 lines checked


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Re: [Intel-gfx] [PATCH 10/13] drm/i915/guc: Kill guc_clients.ct_pool

[Matthew Brost]

On Mon, Jun 07, 2021 at 11:03:52AM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko 
> 
> CTB pool is now maintained internally by the GuC as part of its
> "private data". No need to allocate separate buffer and pass it
> to GuC as yet another ADS.
> 
> Signed-off-by: Matthew Brost  #v4
> Signed-off-by: Michal Wajdeczko 
> Cc: Janusz Krzysztofik 

Reviewed-by: Matthew Brost 

> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c  | 12 
>  drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 12 +---
>  2 files changed, 1 insertion(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 4fcbe4b921f9..6e26fe04ce92 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -26,8 +26,6 @@
>   *  +---+
>   *  | guc_clients_info  |
>   *  +---+
> - *  | guc_ct_pool_entry[size]   |
> - *  +---+
>   *  | padding   |
>   *  +---+ <== 4K aligned
>   *  | private data  |
> @@ -40,7 +38,6 @@ struct __guc_ads_blob {
>   struct guc_policies policies;
>   struct guc_gt_system_info system_info;
>   struct guc_clients_info clients_info;
> - struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
>  } __packed;
>  
>  static u32 guc_ads_private_data_size(struct intel_guc *guc)
> @@ -68,11 +65,6 @@ static void guc_policies_init(struct guc_policies 
> *policies)
>   policies->is_valid = 1;
>  }
>  
> -static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num)
> -{
> - memset(pool, 0, num * sizeof(*pool));
> -}
> -
>  static void guc_mapping_table_init(struct intel_gt *gt,
>  struct guc_gt_system_info *system_info)
>  {
> @@ -161,11 +153,7 @@ static void __guc_ads_init(struct intel_guc *guc)
>   base = intel_guc_ggtt_offset(guc, guc->ads_vma);
>  
>   /* Clients info  */
> - guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));
> -
>   blob->clients_info.clients_num = 1;
> - blob->clients_info.ct_pool_addr = base + ptr_offset(blob, ct_pool);
> - blob->clients_info.ct_pool_count = ARRAY_SIZE(blob->ct_pool);
>  
>   /* ADS */
>   blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index 251c3836bd2c..2266444d074f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -295,19 +295,9 @@ struct guc_gt_system_info {
>  } __packed;
>  
>  /* Clients info */
> -struct guc_ct_pool_entry {
> - struct guc_ct_buffer_desc desc;
> - u32 reserved[7];
> -} __packed;
> -
> -#define GUC_CT_POOL_SIZE 2
> -
>  struct guc_clients_info {
>   u32 clients_num;
> - u32 reserved0[13];
> - u32 ct_pool_addr;
> - u32 ct_pool_count;
> - u32 reserved[4];
> + u32 reserved[19];
>  } __packed;
>  
>  /* GuC Additional Data Struct */
> -- 
> 2.28.0
> 
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Re: [Intel-gfx] [PATCH 0/9] Enhance pipe color support for multi segmented luts

[Shankar, Uma]

> -Original Message-
> From: Harry Wentland 
> Sent: Saturday, June 5, 2021 12:21 AM
> To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; 
> dri-
> de...@lists.freedesktop.org
> Cc: Modem, Bhanuprakash ; Cyr, Aric
> 
> Subject: Re: [PATCH 0/9] Enhance pipe color support for multi segmented luts
> 
> On 2021-06-01 6:41 a.m., Uma Shankar wrote:
> > Modern hardwares have multi segmented lut approach to prioritize the
> > darker regions of the spectrum. This series introduces a new UAPI to
> > define the lut ranges supported by the respective hardware.
> >
> > This also enables Pipe Color Management Support for Intel's XE_LPD hw.
> > Enable Support for Pipe Degamma with the increased lut samples
> > supported by hardware. This also adds support for newly introduced
> > Logarithmic Gamma for XE_LPD. Also added the gamma readout support.
> >
> > The Logarithmic gamma implementation on XE_LPD is non linear and adds
> > 25 segments with non linear lut samples in each segment. The
> > expectation is userspace will create the luts as per this distribution
> > and pass the final samples to driver to be programmed in hardware.
> >
> 
> Is this design targetting Intel XE_LPD HW in particular or is it intended to 
> be generic?
> 
> If this is intended to be generic I think it would benefit from a lot more
> documentation. At this point it's difficult for me to see how to adapt this 
> to AMD
> HW. It would take me a while to be comfortable to make a call on whether we 
> can
> use it or not. And what about other vendors?

This is expected to be generic for all vendors.  XE_LPD is just a reference 
implementation.
It's basically an extension of what we have for crtc color but designing the 
UAPI to have it
more scalable for future hardware. The legacy hardware implementation which we 
have in
crtc properties can easily fit in this new UAPI and this can help represent 
hardware better
with more precision and scalability. Credits to Ville as to this is his idea of 
how we can represent
hardware generically and advertise to userspace.

Sure, I will add more documentation to make this clearer. 

> I think we need to be cautious in directly exposing HW functionality through 
> UAPI.
> The CM parts of AMD HW seem to be changing in some way each generation and it
> looks like the same is true for Intel. The trouble we have with adapting the 
> old
> gamma/degamma properties to modern HW is some indication to me that this
> approach is somewhat problematic.
> 

The advantage of having flexibility in userspace is that we give access of 
hardware to
userspace.It can then control things based on various usecases and not limited 
by just
a subset of operations what we define (in the lack of such an implementation).

> It would be useful to understand and document the specific use-cases we want 
> to
> provide to userspace implementers with this functionality. Do we want to 
> support
> modern transfer functions such as PQ or HLG? If so, it might be beneficial to 
> have an
> API to explicitly specify that, and then use LUT tables in drivers that are 
> optimized for
> the implementing HW. Or is the use case tone mapping? If so, would a 
> parametric
> definition of tone mapping be easier to manage?
> 

Yes right, ideally this is what intend to achieve here. We cant have fixed 
tables for operations
like Tone mapping as it will depend on mastering luminance values which can 
vary along with
other attributes of metadata. Eventually this operation would be done by the 
gamma block
(non linear luts), the values for which would be calculated and send by 
userspace. Thus making
all this very generic. Also we can't do any color math in driver as it has lot 
of floating operations.

So here the trade-off is between having a UAPI where userspace controls hw, 
computes and sends
values vs having just a fixed function operations with hard coded lut tables in 
driver.

Maybe we can have both the options in order to give flexibility to hardware 
vendors. We can
document the usage of the UAPI we create which can help things co-exist. 
Userspace can query
the supported properties and implement based on the properties exposed by the 
respective
vendor driver implementation. 

My personal preference would be to go with generic option (expose hardware to 
userspace) which
will make life easier for userspace developers. This will help use hardware for 
any color operation not
just limited to linearization, CSC conversions and tone mapping. Also this is 
already done for crtc, so it just
need to be extended to planes.

> > +-+--+
> > | x   |  2 pow x segment|No of Entries
> > | |  0  | 1  |
> > | 0   |  1  | 1  |
> > | 1   |  2  | 2  |
> > | 2   |  4  | 2  |
> > | 3   |  8  | 2  |
> > | 4   |  16 | 2  |
> > | 5   |  32 | 4  |
> > | 6   |  64 | 4  

Re: [Intel-gfx] [PATCH 09/13] drm/i915/doc: Include GuC ABI documentation

[Matthew Brost]

On Mon, Jun 07, 2021 at 11:03:51AM -0700, Matthew Brost wrote:
> From: Michal Wajdeczko 
> 
> GuC ABI documentation is now ready to be included in i915.rst
> 
> Signed-off-by: Michal Wajdeczko 
> Signed-off-by: Matthew Brost 
> Cc: Piotr Piórkowski 

Michal - I noticed while putting this series together that there is
kernel doc in intel_guc_ct.* but this isn't inclued in i915.rst. Do you
think we should add the those here or in a new section (e.g. GuC CTBs)?

Let me know what you think and I can fix this up before this gets
merged.

With that, for this patch:

Reviewed-by: Matthew Brost 

> ---
>  Documentation/gpu/i915.rst | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index 42ce0196930a..c7846b1d9293 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -518,6 +518,14 @@ GuC-based command submission
>  .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> :doc: GuC-based command submission
>  
> +GuC ABI
> +
> +
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
> +.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> +
>  HuC
>  ---
>  .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
> -- 
> 2.28.0
> 
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/4] drm/i915/display: Fix fastsets involving PSR (rev2)

[Souza, Jose]

On Sat, 2021-05-15 at 13:15 +, Patchwork wrote:
Patch Details
Series: series starting with [v2,1/4] drm/i915/display: Fix fastsets involving 
PSR (rev2)
URL:https://patchwork.freedesktop.org/series/90184/
State:  failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20131/index.html
CI Bug Log - changes from CI_DRM_10085_full -> Patchwork_20131_full
Summary

FAILURE

Serious unknown changes coming with Patchwork_20131_full absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20131_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_20131_full:

IGT changes
Possible regressions

  *   igt@api_intel_bb@intel-bb-blit-none:

 *   shard-glk: 
PASS
 -> 
FAIL
  *   igt@kms_plane_cursor@pipe-a-viewport-size-128:

 *   shard-snb: NOTRUN -> 
FAIL
 +1 similar issue

Both are not related, the changes are related to display and snb don't support 
PSR.

Pushed the 3 patches reviewed, will follow up the other one latter.

Thanks for the reviews GG.

Warnings

  *   igt@gem_mmap_gtt@fault-concurrent-x:

 *   shard-glk: 
INCOMPLETE
 ([i915#3468]) -> 
INCOMPLETE
  *   igt@kms_plane_cursor@pipe-b-viewport-size-64:

 *   shard-tglb: 
FAIL
 ([i915#3457]) -> 
FAIL

Known issues

Here are the changes found in Patchwork_20131_full that come from known issues:

IGT changes
Issues hit

  *   igt@api_intel_bb@blit-noreloc-purge-cache:

 *   shard-apl: NOTRUN -> 
DMESG-FAIL
 ([i915#3457]) +1 similar issue

 *   shard-skl: NOTRUN -> 
DMESG-WARN
 ([i915#3457])

  *   igt@api_intel_bb@blit-noreloc-purge-cache-random:

 *   shard-kbl: NOTRUN -> 
DMESG-WARN
 ([i915#3457]) +1 similar issue
  *   igt@gem_create@create-clear:

 *   shard-skl: 
PASS
 -> 
FAIL
 ([i915#3160])
  *   igt@gem_create@create-massive:

 *   shard-kbl: NOTRUN -> 
DMESG-WARN
 ([i915#3002])
  *   igt@gem_ctx_persistence@legacy-engines-queued:

 *   shard-snb: NOTRUN -> 
SKIP
 ([fdo#109271] / [i915#1099]) +4 similar issues
  *   igt@gem_eio@in-flight-contexts-10ms:

 *   shard-tglb: 
PASS
 -> 
TIMEOUT
 ([i915#3063] / [i915#3457])
  *   igt@gem_exec_fair@basic-none-share@rcs0:

 *   shard-tglb: 
PASS
 -> 
FAIL
 ([i915#2842] / [i915#3457])
  *   igt@gem_exec_fair@basic-pace-solo@rcs0:

 *   shard-glk: NOTRUN -> 
FAIL
 ([i915#3457]) +3 similar issues
  *   igt@gem_exec_fair@basic-pace@vcs0:

 *   shard-iclb: 
PASS
 -> 
FAIL
 ([i915#2842] / 

[Intel-gfx] [PATCH 13/13] drm/i915/guc: Update firmware to v62.0.0

[Matthew Brost]

From: John Harrison 

Signed-off-by: John Harrison 
Signed-off-by: Michal Wajdeczko 
Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 26 
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index df647c9a8d56..9f23e9de3237 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -48,19 +48,19 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  * firmware as TGL.
  */
 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
-   fw_def(ALDERLAKE_S, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
-   fw_def(ROCKETLAKE,  0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
-   fw_def(TIGERLAKE,   0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
-   fw_def(JASPERLAKE,  0, guc_def(ehl, 49, 0, 1), huc_def(ehl,  9, 0, 0)) \
-   fw_def(ELKHARTLAKE, 0, guc_def(ehl, 49, 0, 1), huc_def(ehl,  9, 0, 0)) \
-   fw_def(ICELAKE, 0, guc_def(icl, 49, 0, 1), huc_def(icl,  9, 0, 0)) \
-   fw_def(COMETLAKE,   5, guc_def(cml, 49, 0, 1), huc_def(cml,  4, 0, 0)) \
-   fw_def(COMETLAKE,   0, guc_def(kbl, 49, 0, 1), huc_def(kbl,  4, 0, 0)) \
-   fw_def(COFFEELAKE,  0, guc_def(kbl, 49, 0, 1), huc_def(kbl,  4, 0, 0)) \
-   fw_def(GEMINILAKE,  0, guc_def(glk, 49, 0, 1), huc_def(glk,  4, 0, 0)) \
-   fw_def(KABYLAKE,0, guc_def(kbl, 49, 0, 1), huc_def(kbl,  4, 0, 0)) \
-   fw_def(BROXTON, 0, guc_def(bxt, 49, 0, 1), huc_def(bxt,  2, 0, 0)) \
-   fw_def(SKYLAKE, 0, guc_def(skl, 49, 0, 1), huc_def(skl,  2, 0, 0))
+   fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl,  7, 5, 0)) \
+   fw_def(ROCKETLAKE,  0, guc_def(tgl, 62, 0, 0), huc_def(tgl,  7, 5, 0)) \
+   fw_def(TIGERLAKE,   0, guc_def(tgl, 62, 0, 0), huc_def(tgl,  7, 5, 0)) \
+   fw_def(JASPERLAKE,  0, guc_def(ehl, 62, 0, 0), huc_def(ehl,  9, 0, 0)) \
+   fw_def(ELKHARTLAKE, 0, guc_def(ehl, 62, 0, 0), huc_def(ehl,  9, 0, 0)) \
+   fw_def(ICELAKE, 0, guc_def(icl, 62, 0, 0), huc_def(icl,  9, 0, 0)) \
+   fw_def(COMETLAKE,   5, guc_def(cml, 62, 0, 0), huc_def(cml,  4, 0, 0)) \
+   fw_def(COMETLAKE,   0, guc_def(kbl, 62, 0, 0), huc_def(kbl,  4, 0, 0)) \
+   fw_def(COFFEELAKE,  0, guc_def(kbl, 62, 0, 0), huc_def(kbl,  4, 0, 0)) \
+   fw_def(GEMINILAKE,  0, guc_def(glk, 62, 0, 0), huc_def(glk,  4, 0, 0)) \
+   fw_def(KABYLAKE,0, guc_def(kbl, 62, 0, 0), huc_def(kbl,  4, 0, 0)) \
+   fw_def(BROXTON, 0, guc_def(bxt, 62, 0, 0), huc_def(bxt,  2, 0, 0)) \
+   fw_def(SKYLAKE, 0, guc_def(skl, 62, 0, 0), huc_def(skl,  2, 0, 0))
 
 #define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \
"i915/" \
-- 
2.28.0

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[Intel-gfx] [PATCH 09/13] drm/i915/doc: Include GuC ABI documentation

[Matthew Brost]

From: Michal Wajdeczko 

GuC ABI documentation is now ready to be included in i915.rst

Signed-off-by: Michal Wajdeczko 
Signed-off-by: Matthew Brost 
Cc: Piotr Piórkowski 
---
 Documentation/gpu/i915.rst | 8 
 1 file changed, 8 insertions(+)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 42ce0196930a..c7846b1d9293 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -518,6 +518,14 @@ GuC-based command submission
 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
:doc: GuC-based command submission
 
+GuC ABI
+
+
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+
 HuC
 ---
 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
-- 
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[Intel-gfx] [PATCH 12/13] drm/i915/guc: Unified GuC log

[Matthew Brost]

From: John Harrison 

GuC v57 unified the 'DPC' and 'ISR' buffers into a single buffer with
the option for it to be larger.

Signed-off-by: Matthew Brost 
Signed-off-by: John Harrison 
Cc: Alan Previn 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.c  | 15 ---
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h |  9 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c  | 29 +++--
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.h  |  6 ++---
 4 files changed, 20 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index b773567cb080..6661dcb02239 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -219,24 +219,19 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
 
BUILD_BUG_ON(!CRASH_BUFFER_SIZE);
BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, UNIT));
-   BUILD_BUG_ON(!DPC_BUFFER_SIZE);
-   BUILD_BUG_ON(!IS_ALIGNED(DPC_BUFFER_SIZE, UNIT));
-   BUILD_BUG_ON(!ISR_BUFFER_SIZE);
-   BUILD_BUG_ON(!IS_ALIGNED(ISR_BUFFER_SIZE, UNIT));
+   BUILD_BUG_ON(!DEBUG_BUFFER_SIZE);
+   BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, UNIT));
 
BUILD_BUG_ON((CRASH_BUFFER_SIZE / UNIT - 1) >
(GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT));
-   BUILD_BUG_ON((DPC_BUFFER_SIZE / UNIT - 1) >
-   (GUC_LOG_DPC_MASK >> GUC_LOG_DPC_SHIFT));
-   BUILD_BUG_ON((ISR_BUFFER_SIZE / UNIT - 1) >
-   (GUC_LOG_ISR_MASK >> GUC_LOG_ISR_SHIFT));
+   BUILD_BUG_ON((DEBUG_BUFFER_SIZE / UNIT - 1) >
+   (GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT));
 
flags = GUC_LOG_VALID |
GUC_LOG_NOTIFY_ON_HALF_FULL |
FLAG |
((CRASH_BUFFER_SIZE / UNIT - 1) << GUC_LOG_CRASH_SHIFT) |
-   ((DPC_BUFFER_SIZE / UNIT - 1) << GUC_LOG_DPC_SHIFT) |
-   ((ISR_BUFFER_SIZE / UNIT - 1) << GUC_LOG_ISR_SHIFT) |
+   ((DEBUG_BUFFER_SIZE / UNIT - 1) << GUC_LOG_DEBUG_SHIFT) |
(offset << GUC_LOG_BUF_ADDR_SHIFT);
 
#undef UNIT
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index f2df5c11c11d..617ec601648d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -81,10 +81,8 @@
 #define   GUC_LOG_ALLOC_IN_MEGABYTE(1 << 3)
 #define   GUC_LOG_CRASH_SHIFT  4
 #define   GUC_LOG_CRASH_MASK   (0x3 << GUC_LOG_CRASH_SHIFT)
-#define   GUC_LOG_DPC_SHIFT6
-#define   GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT)
-#define   GUC_LOG_ISR_SHIFT9
-#define   GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT)
+#define   GUC_LOG_DEBUG_SHIFT  6
+#define   GUC_LOG_DEBUG_MASK   (0xF << GUC_LOG_DEBUG_SHIFT)
 #define   GUC_LOG_BUF_ADDR_SHIFT   12
 
 #define GUC_CTL_WA 1
@@ -311,8 +309,7 @@ struct guc_ads {
 /* GuC logging structures */
 
 enum guc_log_buffer_type {
-   GUC_ISR_LOG_BUFFER,
-   GUC_DPC_LOG_BUFFER,
+   GUC_DEBUG_LOG_BUFFER,
GUC_CRASH_DUMP_LOG_BUFFER,
GUC_MAX_LOG_BUFFER
 };
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index c36d5eb5bbb9..ac0931f0374b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -197,10 +197,8 @@ static bool guc_check_log_buf_overflow(struct 
intel_guc_log *log,
 static unsigned int guc_get_log_buffer_size(enum guc_log_buffer_type type)
 {
switch (type) {
-   case GUC_ISR_LOG_BUFFER:
-   return ISR_BUFFER_SIZE;
-   case GUC_DPC_LOG_BUFFER:
-   return DPC_BUFFER_SIZE;
+   case GUC_DEBUG_LOG_BUFFER:
+   return DEBUG_BUFFER_SIZE;
case GUC_CRASH_DUMP_LOG_BUFFER:
return CRASH_BUFFER_SIZE;
default:
@@ -245,7 +243,7 @@ static void guc_read_update_log_buffer(struct intel_guc_log 
*log)
src_data += PAGE_SIZE;
dst_data += PAGE_SIZE;
 
-   for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
+   for (type = GUC_DEBUG_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
/*
 * Make a copy of the state structure, inside GuC log buffer
 * (which is uncached mapped), on the stack to avoid reading
@@ -463,21 +461,16 @@ int intel_guc_log_create(struct intel_guc_log *log)
 *  +===+ 00B
 *  |Crash dump state header|
 *  +---+ 32B
-*  |   DPC state header|
+*  |  Debug state header   |
 *  +---+ 64B
-*  |   ISR state header|
-*  +---+ 96B
 *  |   |
 

[Intel-gfx] [PATCH 00/13] Update firmware to v62.0.0

[Matthew Brost]

As part of enabling GuC submission [1] we need to update to the latest
and greatest firmware. This series does that. This is a destructive
change. e.g. Without all the patches in this series it will break the
i915 driver. As such, after we review all of these patches they will
squashed into a single patch for merging.

Signed-off-by: Matthew Brost 

[1] https://patchwork.freedesktop.org/series/89844/

John Harrison (3):
  drm/i915/guc: Support per context scheduling policies
  drm/i915/guc: Unified GuC log
  drm/i915/guc: Update firmware to v62.0.0

Michal Wajdeczko (10):
  drm/i915/guc: Introduce unified HXG messages
  drm/i915/guc: Update MMIO based communication
  drm/i915/guc: Update CTB response status definition
  drm/i915/guc: Add flag for mark broken CTB
  drm/i915/guc: New definition of the CTB descriptor
  drm/i915/guc: New definition of the CTB registration action
  drm/i915/guc: New CTB based communication
  drm/i915/doc: Include GuC ABI documentation
  drm/i915/guc: Kill guc_clients.ct_pool
  drm/i915/guc: Kill ads.client_info

 Documentation/gpu/i915.rst|   8 +
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  | 107 ++
 .../gt/uc/abi/guc_communication_ctb_abi.h | 130 +--
 .../gt/uc/abi/guc_communication_mmio_abi.h|  63 ++--
 .../gpu/drm/i915/gt/uc/abi/guc_messages_abi.h | 213 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc.c| 107 --
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c|  45 +--
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 355 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |   6 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |  75 +---
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c|  29 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.h|   6 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  |  26 +-
 13 files changed, 750 insertions(+), 420 deletions(-)

-- 
2.28.0

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[Intel-gfx] [PATCH 08/13] drm/i915/guc: New CTB based communication

[Matthew Brost]

From: Michal Wajdeczko 

Format of the CTB messages has changed:
 - support for multiple formats
 - message fence is now part of the header
 - reuse of unified HXG message formats

Signed-off-by: Michal Wajdeczko 
Signed-off-by: Matthew Brost 
Cc: Piotr Piórkowski 
---
 .../gt/uc/abi/guc_communication_ctb_abi.h |  56 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 194 +++---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |   2 +-
 3 files changed, 135 insertions(+), 117 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
index 127b256a662c..92660726c094 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
@@ -60,6 +60,62 @@ struct guc_ct_buffer_desc {
 } __packed;
 static_assert(sizeof(struct guc_ct_buffer_desc) == 64);
 
+/**
+ * DOC: CTB Message
+ *
+ *  
+---+---+--+
+ *  |   | Bits  | Description  
|
+ *  
+===+===+==+
+ *  | 0 | 31:16 | **FENCE** - message identifier   
|
+ *  |   
+---+--+
+ *  |   | 15:12 | **FORMAT** - format of the CTB message   
|
+ *  |   |   |  - _`GUC_CTB_FORMAT_HXG` = 0 - see `CTB HXG Message`_
|
+ *  |   
+---+--+
+ *  |   |  11:8 | **RESERVED** 
|
+ *  |   
+---+--+
+ *  |   |   7:0 | **NUM_DWORDS** - length of the CTB message (w/o header)  
|
+ *  
+---+---+--+
+ *  | 1 |  31:0 | optional (depends on FORMAT) 
|
+ *  +---+---+  
|
+ *  |...|   |  
|
+ *  +---+---+  
|
+ *  | n |  31:0 |  
|
+ *  
+---+---+--+
+ */
+
+#define GUC_CTB_MSG_MIN_LEN1u
+#define GUC_CTB_MSG_MAX_LEN256u
+#define GUC_CTB_MSG_0_FENCE(0x << 16)
+#define GUC_CTB_MSG_0_FORMAT   (0xf << 12)
+#define   GUC_CTB_FORMAT_HXG   0u
+#define GUC_CTB_MSG_0_RESERVED (0xf << 8)
+#define GUC_CTB_MSG_0_NUM_DWORDS   (0xff << 0)
+
+/**
+ * DOC: CTB HXG Message
+ *
+ *  
+---+---+--+
+ *  |   | Bits  | Description  
|
+ *  
+===+===+==+
+ *  | 0 | 31:16 | FENCE
|
+ *  |   
+---+--+
+ *  |   | 15:12 | FORMAT = GUC_CTB_FORMAT_HXG_ 
|
+ *  |   
+---+--+
+ *  |   |  11:8 | RESERVED = MBZ   
|
+ *  |   
+---+--+
+ *  |   |   7:0 | NUM_DWORDS = length (in dwords) of the embedded HXG message  
|
+ *  
+---+---+--+
+ *  | 1 |  31:0 |  ++  
|
+ *  +---+---+  ||  
|
+ *  |...|   |  |  Embedded `HXG Message`_   |  
|
+ *  +---+---+  ||  
|
+ *  | n |  31:0 |  ++  
|
+ *  
+---+---+--+
+ */
+
+#define GUC_CTB_HXG_MSG_MIN_LEN(GUC_CTB_MSG_MIN_LEN + 
GUC_HXG_MSG_MIN_LEN)
+#define GUC_CTB_HXG_MSG_MAX_LENGUC_CTB_MSG_MAX_LEN
+
 /**
  * DOC: CTB based communication
  *
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 6a29be779cc9..729f29bc2a57 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -365,24 +365,6 @@ static void write_barrier(struct intel_guc_ct *ct)
}
 }
 
-/**
- * DOC: CTB Host to GuC request
- *
- * Format of the CTB Host to GuC request message is as follows::
- *
- *  

[Intel-gfx] [PATCH 07/13] drm/i915/guc: New definition of the CTB registration action

[Matthew Brost]

From: Michal Wajdeczko 

Definition of the CTB registration action has changed.
Add some ABI documentation and implement required changes.

Signed-off-by: Michal Wajdeczko 
Signed-off-by: Matthew Brost 
Cc: Piotr Piórkowski  #4
---
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  | 107 ++
 .../gt/uc/abi/guc_communication_ctb_abi.h |   4 -
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |  76 -
 3 files changed, 152 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 90efef8a73e4..6426fc183692 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -6,6 +6,113 @@
 #ifndef _ABI_GUC_ACTIONS_ABI_H
 #define _ABI_GUC_ACTIONS_ABI_H
 
+/**
+ * DOC: HOST2GUC_REGISTER_CTB
+ *
+ * This message is used as part of the `CTB based communication`_ setup.
+ *
+ * This message must be sent as `MMIO HXG Message`_.
+ *
+ *  
+---+---+--+
+ *  |   | Bits  | Description  
|
+ *  
+===+===+==+
+ *  | 0 |31 | ORIGIN = GUC_HXG_ORIGIN_HOST_
|
+ *  |   
+---+--+
+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ 
|
+ *  |   
+---+--+
+ *  |   | 27:16 | DATA0 = MBZ  
|
+ *  |   
+---+--+
+ *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_REGISTER_CTB` = 0x5200
|
+ *  
+---+---+--+
+ *  | 1 | 31:12 | RESERVED = MBZ   
|
+ *  |   
+---+--+
+ *  |   |  11:8 | **TYPE** - type for the `CT Buffer`_ 
|
+ *  |   |   |  
|
+ *  |   |   |   - _`GUC_CTB_TYPE_HOST2GUC` = 0 
|
+ *  |   |   |   - _`GUC_CTB_TYPE_GUC2HOST` = 1 
|
+ *  |   
+---+--+
+ *  |   |   7:0 | **SIZE** - size of the `CT Buffer`_ in 4K units minus 1  
|
+ *  
+---+---+--+
+ *  | 2 |  31:0 | **DESC_ADDR** - GGTT address of the `CTB Descriptor`_
|
+ *  
+---+---+--+
+ *  | 3 |  31:0 | **BUFF_ADDF** - GGTT address of the `CT Buffer`_ 
|
+ *  
+---+---+--+
+*
+ *  
+---+---+--+
+ *  |   | Bits  | Description  
|
+ *  
+===+===+==+
+ *  | 0 |31 | ORIGIN = GUC_HXG_ORIGIN_GUC_ 
|
+ *  |   
+---+--+
+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_
|
+ *  |   
+---+--+
+ *  |   |  27:0 | DATA0 = MBZ  
|
+ *  
+---+---+--+
+ */
+#define GUC_ACTION_HOST2GUC_REGISTER_CTB   0x4505 // FIXME 0x5200
+
+#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_LEN  
(GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)
+#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_0_MBZ
GUC_HXG_REQUEST_MSG_0_DATA0
+#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_1_MBZ(0xf << 12)
+#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_1_TYPE   (0xf << 8)
+#define   GUC_CTB_TYPE_HOST2GUC0u
+#define   GUC_CTB_TYPE_GUC2HOST1u
+#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_1_SIZE   (0xff << 0)
+#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_2_DESC_ADDR  
GUC_HXG_REQUEST_MSG_n_DATAn
+#define HOST2GUC_REGISTER_CTB_REQUEST_MSG_3_BUFF_ADDR  
GUC_HXG_REQUEST_MSG_n_DATAn
+
+#define HOST2GUC_REGISTER_CTB_RESPONSE_MSG_LEN 
GUC_HXG_RESPONSE_MSG_MIN_LEN
+#define HOST2GUC_REGISTER_CTB_RESPONSE_MSG_0_MBZ   
GUC_HXG_RESPONSE_MSG_0_DATA0
+
+/**
+ * DOC: HOST2GUC_DEREGISTER_CTB
+ *
+ * This message is used as part of the `CTB based communication`_ teardown.
+ *
+ * This message must be sent as `MMIO HXG Message`_.
+ *
+ *  
+---+---+--+
+ *  |   | Bits  | 

[Intel-gfx] [PATCH 10/13] drm/i915/guc: Kill guc_clients.ct_pool

[Matthew Brost]

From: Michal Wajdeczko 

CTB pool is now maintained internally by the GuC as part of its
"private data". No need to allocate separate buffer and pass it
to GuC as yet another ADS.

Signed-off-by: Matthew Brost  #v4
Signed-off-by: Michal Wajdeczko 
Cc: Janusz Krzysztofik 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c  | 12 
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 12 +---
 2 files changed, 1 insertion(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 4fcbe4b921f9..6e26fe04ce92 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -26,8 +26,6 @@
  *  +---+
  *  | guc_clients_info  |
  *  +---+
- *  | guc_ct_pool_entry[size]   |
- *  +---+
  *  | padding   |
  *  +---+ <== 4K aligned
  *  | private data  |
@@ -40,7 +38,6 @@ struct __guc_ads_blob {
struct guc_policies policies;
struct guc_gt_system_info system_info;
struct guc_clients_info clients_info;
-   struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
 } __packed;
 
 static u32 guc_ads_private_data_size(struct intel_guc *guc)
@@ -68,11 +65,6 @@ static void guc_policies_init(struct guc_policies *policies)
policies->is_valid = 1;
 }
 
-static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num)
-{
-   memset(pool, 0, num * sizeof(*pool));
-}
-
 static void guc_mapping_table_init(struct intel_gt *gt,
   struct guc_gt_system_info *system_info)
 {
@@ -161,11 +153,7 @@ static void __guc_ads_init(struct intel_guc *guc)
base = intel_guc_ggtt_offset(guc, guc->ads_vma);
 
/* Clients info  */
-   guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));
-
blob->clients_info.clients_num = 1;
-   blob->clients_info.ct_pool_addr = base + ptr_offset(blob, ct_pool);
-   blob->clients_info.ct_pool_count = ARRAY_SIZE(blob->ct_pool);
 
/* ADS */
blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 251c3836bd2c..2266444d074f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -295,19 +295,9 @@ struct guc_gt_system_info {
 } __packed;
 
 /* Clients info */
-struct guc_ct_pool_entry {
-   struct guc_ct_buffer_desc desc;
-   u32 reserved[7];
-} __packed;
-
-#define GUC_CT_POOL_SIZE   2
-
 struct guc_clients_info {
u32 clients_num;
-   u32 reserved0[13];
-   u32 ct_pool_addr;
-   u32 ct_pool_count;
-   u32 reserved[4];
+   u32 reserved[19];
 } __packed;
 
 /* GuC Additional Data Struct */
-- 
2.28.0

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[Intel-gfx] [PATCH 06/13] drm/i915/guc: New definition of the CTB descriptor

[Matthew Brost]

From: Michal Wajdeczko 

Definition of the CTB descriptor has changed, leaving only
minimal shared fields like HEAD/TAIL/STATUS.

Both HEAD and TAIL are now in dwords.

Add some ABI documentation and implement required changes.

Signed-off-by: Michal Wajdeczko 
Signed-off-by: Matthew Brost 
---
 .../gt/uc/abi/guc_communication_ctb_abi.h | 70 ++-
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 70 +--
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |  2 +-
 3 files changed, 85 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
index d38935f47ecf..c2a069a78e01 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
@@ -7,6 +7,58 @@
 #define _ABI_GUC_COMMUNICATION_CTB_ABI_H
 
 #include 
+#include 
+
+#include "guc_messages_abi.h"
+
+/**
+ * DOC: CT Buffer
+ *
+ * TBD
+ */
+
+/**
+ * DOC: CTB Descriptor
+ *
+ *  
+---+---+--+
+ *  |   | Bits  | Description  
|
+ *  
+===+===+==+
+ *  | 0 |  31:0 | **HEAD** - offset (in dwords) to the last dword that was 
|
+ *  |   |   | read from the `CT Buffer`_.  
|
+ *  |   |   | It can only be updated by the receiver.  
|
+ *  
+---+---+--+
+ *  | 1 |  31:0 | **TAIL** - offset (in dwords) to the last dword that was 
|
+ *  |   |   | written to the `CT Buffer`_. 
|
+ *  |   |   | It can only be updated by the sender.
|
+ *  
+---+---+--+
+ *  | 2 |  31:0 | **STATUS** - status of the CTB   
|
+ *  |   |   |  
|
+ *  |   |   |   - _`GUC_CTB_STATUS_NO_ERROR` = 0 (normal operation)
|
+ *  |   |   |   - _`GUC_CTB_STATUS_OVERFLOW` = 1 (head/tail too large) 
|
+ *  |   |   |   - _`GUC_CTB_STATUS_UNDERFLOW` = 2 (truncated message)  
|
+ *  |   |   |   - _`GUC_CTB_STATUS_MISMATCH` = 4 (head/tail modified)  
|
+ *  |   |   |   - _`GUC_CTB_STATUS_NO_BACKCHANNEL` = 8 
|
+ *  |   |   |   - _`GUC_CTB_STATUS_MALFORMED_MSG` = 16 
|
+ *  
+---+---+--+
+ *  |...|   | RESERVED = MBZ   
|
+ *  
+---+---+--+
+ *  | 15|  31:0 | RESERVED = MBZ   
|
+ *  
+---+---+--+
+ */
+
+struct guc_ct_buffer_desc {
+   u32 head;
+   u32 tail;
+   u32 status;
+#define GUC_CTB_STATUS_NO_ERROR0
+#define GUC_CTB_STATUS_OVERFLOW(1 << 0)
+#define GUC_CTB_STATUS_UNDERFLOW   (1 << 1)
+#define GUC_CTB_STATUS_MISMATCH(1 << 2)
+#define GUC_CTB_STATUS_NO_BACKCHANNEL  (1 << 3)
+#define GUC_CTB_STATUS_MALFORMED_MSG   (1 << 4)
+   u32 reserved[13];
+} __packed;
+static_assert(sizeof(struct guc_ct_buffer_desc) == 64);
 
 /**
  * DOC: CTB based communication
@@ -60,24 +112,6 @@
  * - **flags**, holds various bits to control message handling
  */
 
-/*
- * Describes single command transport buffer.
- * Used by both guc-master and clients.
- */
-struct guc_ct_buffer_desc {
-   u32 addr;   /* gfx address */
-   u64 host_private;   /* host private data */
-   u32 size;   /* size in bytes */
-   u32 head;   /* offset updated by GuC*/
-   u32 tail;   /* offset updated by owner */
-   u32 is_in_error;/* error indicator */
-   u32 reserved1;
-   u32 reserved2;
-   u32 owner;  /* id of the channel owner */
-   u32 owner_sub_id;   /* owner-defined field for extra tracking */
-   u32 reserved[5];
-} __packed;
-
 /* Type of command transport buffer */
 #define INTEL_GUC_CT_BUFFER_TYPE_SEND  0x0u
 #define INTEL_GUC_CT_BUFFER_TYPE_RECV  0x1u
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 63056ea0631e..3241a477196f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -112,32 +112,28 @@ static inline const char *guc_ct_buffer_type_to_str(u32 
type)
}
 }
 
-static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc,
-  

[Intel-gfx] [PATCH 11/13] drm/i915/guc: Kill ads.client_info

[Matthew Brost]

From: Michal Wajdeczko 

New GuC does not require it any more.

Reviewed-by: Matthew Brost 
Signed-off-by: Michal Wajdeczko 
Cc: Piotr Piórkowski 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c  | 7 ---
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 8 +---
 2 files changed, 1 insertion(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 6e26fe04ce92..b82145652d57 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -24,8 +24,6 @@
  *  +---+
  *  | guc_gt_system_info|
  *  +---+
- *  | guc_clients_info  |
- *  +---+
  *  | padding   |
  *  +---+ <== 4K aligned
  *  | private data  |
@@ -37,7 +35,6 @@ struct __guc_ads_blob {
struct guc_ads ads;
struct guc_policies policies;
struct guc_gt_system_info system_info;
-   struct guc_clients_info clients_info;
 } __packed;
 
 static u32 guc_ads_private_data_size(struct intel_guc *guc)
@@ -152,13 +149,9 @@ static void __guc_ads_init(struct intel_guc *guc)
 
base = intel_guc_ggtt_offset(guc, guc->ads_vma);
 
-   /* Clients info  */
-   blob->clients_info.clients_num = 1;
-
/* ADS */
blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
blob->ads.gt_system_info = base + ptr_offset(blob, system_info);
-   blob->ads.clients_info = base + ptr_offset(blob, clients_info);
 
/* Private Data */
blob->ads.private_data = base + guc_ads_private_data_offset(guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 2266444d074f..f2df5c11c11d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -294,19 +294,13 @@ struct guc_gt_system_info {
u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX];
 } __packed;
 
-/* Clients info */
-struct guc_clients_info {
-   u32 clients_num;
-   u32 reserved[19];
-} __packed;
-
 /* GuC Additional Data Struct */
 struct guc_ads {
struct guc_mmio_reg_set 
reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
u32 reserved0;
u32 scheduler_policies;
u32 gt_system_info;
-   u32 clients_info;
+   u32 reserved1;
u32 control_data;
u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
-- 
2.28.0

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[Intel-gfx] [PATCH 03/13] drm/i915/guc: Update CTB response status definition

[Matthew Brost]

From: Michal Wajdeczko 

Format of the STATUS dword in CTB response message now follows
definition of the HXG header. Update our code and remove any
obsolete legacy definitions.

GuC: 55.0.0
Signed-off-by: Michal Wajdeczko 
Acked-by: Piotr Piórkowski 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c   | 14 --
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 17 -
 2 files changed, 8 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 8f7b148fef58..3f7f48611487 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -477,7 +477,9 @@ static int wait_for_ct_request_update(struct ct_request 
*req, u32 *status)
 * up to that length of time, then switch to a slower sleep-wait loop.
 * No GuC command should ever take longer than 10ms.
 */
-#define done INTEL_GUC_MSG_IS_RESPONSE(READ_ONCE(req->status))
+#define done \
+   (FIELD_GET(GUC_HXG_MSG_0_ORIGIN, READ_ONCE(req->status)) == \
+GUC_HXG_ORIGIN_GUC)
err = wait_for_us(done, 10);
if (err)
err = wait_for(done, 10);
@@ -532,21 +534,21 @@ static int ct_send(struct intel_guc_ct *ct,
if (unlikely(err))
goto unlink;
 
-   if (!INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(*status)) {
+   if (FIELD_GET(GUC_HXG_MSG_0_TYPE, *status) != 
GUC_HXG_TYPE_RESPONSE_SUCCESS) {
err = -EIO;
goto unlink;
}
 
if (response_buf) {
/* There shall be no data in the status */
-   WARN_ON(INTEL_GUC_MSG_TO_DATA(request.status));
+   WARN_ON(FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, 
request.status));
/* Return actual response len */
err = request.response_len;
} else {
/* There shall be no response payload */
WARN_ON(request.response_len);
/* Return data decoded from the status dword */
-   err = INTEL_GUC_MSG_TO_DATA(*status);
+   err = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, *status);
}
 
 unlink:
@@ -741,8 +743,8 @@ static int ct_handle_response(struct intel_guc_ct *ct, 
struct ct_incoming_msg *r
status = response->msg[2];
datalen = len - 2;
 
-   /* Format of the status follows RESPONSE message */
-   if (unlikely(!INTEL_GUC_MSG_IS_RESPONSE(status))) {
+   /* Format of the status dword follows HXG header */
+   if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, status) != 
GUC_HXG_ORIGIN_GUC)) {
CT_ERROR(ct, "Corrupted response (status %#x)\n", status);
return -EPROTO;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index e9a9d85e2aa3..fb04e2211b79 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -414,23 +414,6 @@ struct guc_shared_ctx_data {
struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM];
 } __packed;
 
-#define __INTEL_GUC_MSG_GET(T, m) \
-   (((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT)
-#define INTEL_GUC_MSG_TO_TYPE(m)   __INTEL_GUC_MSG_GET(TYPE, m)
-#define INTEL_GUC_MSG_TO_DATA(m)   __INTEL_GUC_MSG_GET(DATA, m)
-#define INTEL_GUC_MSG_TO_CODE(m)   __INTEL_GUC_MSG_GET(CODE, m)
-
-#define __INTEL_GUC_MSG_TYPE_IS(T, m) \
-   (INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T)
-#define INTEL_GUC_MSG_IS_REQUEST(m)__INTEL_GUC_MSG_TYPE_IS(REQUEST, m)
-#define INTEL_GUC_MSG_IS_RESPONSE(m)   __INTEL_GUC_MSG_TYPE_IS(RESPONSE, m)
-
-#define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \
-(typecheck(u32, (m)) && \
- ((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \
- ((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \
-  (INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT)))
-
 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
 enum intel_guc_recv_message {
INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
-- 
2.28.0

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[Intel-gfx] [PATCH 01/13] drm/i915/guc: Introduce unified HXG messages

[Matthew Brost]

From: Michal Wajdeczko 

New GuC firmware will unify format of MMIO and CTB H2G messages.
Introduce their definitions now to allow gradual transition of
our code to match new changes.

Signed-off-by: Matthew Brost 
Signed-off-by: Michal Wajdeczko 
Cc: Michał Winiarski 
---
 .../gpu/drm/i915/gt/uc/abi/guc_messages_abi.h | 213 ++
 1 file changed, 213 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
index 775e21f3058c..29ac823acd4c 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
@@ -6,6 +6,219 @@
 #ifndef _ABI_GUC_MESSAGES_ABI_H
 #define _ABI_GUC_MESSAGES_ABI_H
 
+/**
+ * DOC: HXG Message
+ *
+ * All messages exchanged with GuC are defined using 32 bit dwords.
+ * First dword is treated as a message header. Remaining dwords are optional.
+ *
+ *  
+---+---+--+
+ *  |   | Bits  | Description  
|
+ *  
+===+===+==+
+ *  |   |   |  
|
+ *  | 0 |31 | **ORIGIN** - originator of the message   
|
+ *  |   |   |   - _`GUC_HXG_ORIGIN_HOST` = 0   
|
+ *  |   |   |   - _`GUC_HXG_ORIGIN_GUC` = 1
|
+ *  |   |   |  
|
+ *  |   
+---+--+
+ *  |   | 30:28 | **TYPE** - message type  
|
+ *  |   |   |   - _`GUC_HXG_TYPE_REQUEST` = 0  
|
+ *  |   |   |   - _`GUC_HXG_TYPE_EVENT` = 1
|
+ *  |   |   |   - _`GUC_HXG_TYPE_NO_RESPONSE_BUSY` = 3 
|
+ *  |   |   |   - _`GUC_HXG_TYPE_NO_RESPONSE_RETRY` = 5
|
+ *  |   |   |   - _`GUC_HXG_TYPE_RESPONSE_FAILURE` = 6 
|
+ *  |   |   |   - _`GUC_HXG_TYPE_RESPONSE_SUCCESS` = 7 
|
+ *  |   
+---+--+
+ *  |   |  27:0 | **AUX** - auxiliary data (depends on TYPE)   
|
+ *  
+---+---+--+
+ *  | 1 |  31:0 |  
|
+ *  +---+---+  
|
+ *  |...|   | **PAYLOAD** - optional payload (depends on TYPE) 
|
+ *  +---+---+  
|
+ *  | n |  31:0 |  
|
+ *  
+---+---+--+
+ */
+
+#define GUC_HXG_MSG_MIN_LEN1u
+#define GUC_HXG_MSG_0_ORIGIN   (0x1 << 31)
+#define   GUC_HXG_ORIGIN_HOST  0u
+#define   GUC_HXG_ORIGIN_GUC   1u
+#define GUC_HXG_MSG_0_TYPE (0x7 << 28)
+#define   GUC_HXG_TYPE_REQUEST 0u
+#define   GUC_HXG_TYPE_EVENT   1u
+#define   GUC_HXG_TYPE_NO_RESPONSE_BUSY3u
+#define   GUC_HXG_TYPE_NO_RESPONSE_RETRY   5u
+#define   GUC_HXG_TYPE_RESPONSE_FAILURE6u
+#define   GUC_HXG_TYPE_RESPONSE_SUCCESS7u
+#define GUC_HXG_MSG_0_AUX  (0xfff << 0)
+#define GUC_HXG_MSG_n_PAYLOAD  (0x << 0)
+
+/**
+ * DOC: HXG Request
+ *
+ * The `HXG Request`_ message should be used to initiate synchronous activity
+ * for which confirmation or return data is expected.
+ *
+ * The recipient of this message shall use `HXG Response`_, `HXG Failure`_
+ * or `HXG Retry`_ message as a definite reply, and may use `HXG Busy`_
+ * message as a intermediate reply.
+ *
+ * Format of @DATA0 and all @DATAn fields depends on the @ACTION code.
+ *
+ *  
+---+---+--+
+ *  |   | Bits  | Description  
|
+ *  
+===+===+==+
+ *  | 0 |31 | ORIGIN   
|
+ *  |   
+---+--+
+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ 
|
+ *  |   
+---+--+
+ *  |   | 27:16 | **DATA0** - request data (depends on ACTION) 
|
+ *  |   
+---+--+
+ *  |   |  15:0 | **ACTION** - requested action code   

[Intel-gfx] [PATCH 02/13] drm/i915/guc: Update MMIO based communication

[Matthew Brost]

From: Michal Wajdeczko 

The MMIO based Host-to-GuC communication protocol has been
updated to use unified HXG messages.

Update our intel_guc_send_mmio() function by correctly handle
BUSY, RETRY and FAILURE replies. Also update our documentation.

GuC: 55.0.0
Signed-off-by: Matthew Brost 
Signed-off-by: Michal Wajdeczko 
Cc: Piotr Piórkowski 
Cc: Michal Winiarski  #v3
---
 .../gt/uc/abi/guc_communication_mmio_abi.h| 63 ++---
 drivers/gpu/drm/i915/gt/uc/intel_guc.c| 92 ++-
 2 files changed, 97 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
index be066a62e9e0..3f9039e3ef9d 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
@@ -7,46 +7,43 @@
 #define _ABI_GUC_COMMUNICATION_MMIO_ABI_H
 
 /**
- * DOC: MMIO based communication
+ * DOC: GuC MMIO based communication
  *
- * The MMIO based communication between Host and GuC uses software scratch
- * registers, where first register holds data treated as message header,
- * and other registers are used to hold message payload.
+ * The MMIO based communication between Host and GuC relies on special
+ * hardware registers which format could be defined by the software
+ * (so called scratch registers).
  *
- * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8,
- * but no H2G command takes more than 8 parameters and the GuC FW
- * itself uses an 8-element array to store the H2G message.
- *
- *  +---+-+-+-+
- *  |  MMIO[0]  | MMIO[1] |   ...   | MMIO[n] |
- *  +---+-+-+-+
- *  | header|  optional payload   |
- *  +==++=+=+=+
- *  | 31:28|type| | | |
- *  +--++ | | |
- *  | 27:16|data| | | |
- *  +--++ | | |
- *  |  15:0|code| | | |
- *  +--++-+-+-+
- *
- * The message header consists of:
- *
- * - **type**, indicates message type
- * - **code**, indicates message code, is specific for **type**
- * - **data**, indicates message data, optional, depends on **code**
+ * Each MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H)
+ * messages, which maximum length depends on number of available scratch
+ * registers, is directly written into those scratch registers.
  *
- * The following message **types** are supported:
+ * For Gen9+, there are 16 software scratch registers 0xC180-0xC1B8,
+ * but no H2G command takes more than 8 parameters and the GuC firmware
+ * itself uses an 8-element array to store the H2G message.
  *
- * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code
- *   must be priovided in **code** field. Optional action specific parameters
- *   can be provided in remaining payload registers or **data** field.
+ * For Gen11+, there are additional 4 registers 0x190240-0x19024C, which
+ * are, regardless on lower count, preffered over legacy ones.
  *
- * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request,
- *   action response status will be provided in **code** field. Optional
- *   response data can be returned in remaining payload registers or **data**
- *   field.
+ * The MMIO based communication is mainly used during driver initialization
+ * phase to setup the `CTB based communication`_ that will be used afterwards.
  */
 
 #define GUC_MAX_MMIO_MSG_LEN   8
 
+/**
+ * DOC: MMIO HXG Message
+ *
+ * Format of the MMIO messages follows definitions of `HXG Message`_.
+ *
+ *  
+---+---+--+
+ *  |   | Bits  | Description  
|
+ *  
+===+===+==+
+ *  | 0 |  31:0 |  ++  
|
+ *  +---+---+  ||  
|
+ *  |...|   |  |  Embedded `HXG Message`_   |  
|
+ *  +---+---+  ||  
|
+ *  | n |  31:0 |  ++  
|
+ *  
+---+---+--+
+ */
+
 #endif /* _ABI_GUC_COMMUNICATION_MMIO_ABI_H */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index f147cb389a20..b773567cb080 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -376,29 +376,27 @@ void intel_guc_fini(struct intel_guc *guc)
 /*
  * This function implements the MMIO based host to GuC interface.
  */
-int 

[Intel-gfx] [PATCH 05/13] drm/i915/guc: Add flag for mark broken CTB

[Matthew Brost]

From: Michal Wajdeczko 

Once CTB descriptor is found in error state, either set by GuC
or us, there is no need continue checking descriptor any more,
we can rely on our internal flag.

Signed-off-by: Matthew Brost 
Signed-off-by: Michal Wajdeczko 
Cc: Piotr Piórkowski 
Reviewed-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 13 +++--
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |  2 ++
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 3f7f48611487..63056ea0631e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -123,6 +123,7 @@ static void guc_ct_buffer_desc_init(struct 
guc_ct_buffer_desc *desc,
 
 static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb, u32 cmds_addr)
 {
+   ctb->broken = false;
guc_ct_buffer_desc_init(ctb->desc, cmds_addr, ctb->size);
 }
 
@@ -387,9 +388,12 @@ static int ct_write(struct intel_guc_ct *ct,
u32 *cmds = ctb->cmds;
unsigned int i;
 
-   if (unlikely(desc->is_in_error))
+   if (unlikely(ctb->broken))
return -EPIPE;
 
+   if (unlikely(desc->is_in_error))
+   goto corrupted;
+
if (unlikely(!IS_ALIGNED(head | tail, 4) ||
 (tail | head) >= size))
goto corrupted;
@@ -451,6 +455,7 @@ static int ct_write(struct intel_guc_ct *ct,
CT_ERROR(ct, "Corrupted descriptor addr=%#x head=%u tail=%u size=%u\n",
 desc->addr, desc->head, desc->tail, desc->size);
desc->is_in_error = 1;
+   ctb->broken = true;
return -EPIPE;
 }
 
@@ -632,9 +637,12 @@ static int ct_read(struct intel_guc_ct *ct, struct 
ct_incoming_msg **msg)
unsigned int i;
u32 header;
 
-   if (unlikely(desc->is_in_error))
+   if (unlikely(ctb->broken))
return -EPIPE;
 
+   if (unlikely(desc->is_in_error))
+   goto corrupted;
+
if (unlikely(!IS_ALIGNED(head | tail, 4) ||
 (tail | head) >= size))
goto corrupted;
@@ -698,6 +706,7 @@ static int ct_read(struct intel_guc_ct *ct, struct 
ct_incoming_msg **msg)
CT_ERROR(ct, "Corrupted descriptor addr=%#x head=%u tail=%u size=%u\n",
 desc->addr, desc->head, desc->tail, desc->size);
desc->is_in_error = 1;
+   ctb->broken = true;
return -EPIPE;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index cb222f202301..7d3cd375d6a7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -32,12 +32,14 @@ struct intel_guc;
  * @desc: pointer to the buffer descriptor
  * @cmds: pointer to the commands buffer
  * @size: size of the commands buffer
+ * @broken: flag to indicate if descriptor data is broken
  */
 struct intel_guc_ct_buffer {
spinlock_t lock;
struct guc_ct_buffer_desc *desc;
u32 *cmds;
u32 size;
+   bool broken;
 };
 
 
-- 
2.28.0

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[Intel-gfx] [PATCH 04/13] drm/i915/guc: Support per context scheduling policies

[Matthew Brost]

From: John Harrison 

GuC firmware v53.0.0 introduced per context scheduling policies. This
includes changes to some of the ADS structures which are required to
load the firmware even if not using GuC submission.

Signed-off-by: John Harrison 
Signed-off-by: Matthew Brost 
Reviewed-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c  | 26 +++--
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 31 +
 2 files changed, 11 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 9abfbc6edbd6..4fcbe4b921f9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -59,30 +59,12 @@ static u32 guc_ads_blob_size(struct intel_guc *guc)
   guc_ads_private_data_size(guc);
 }
 
-static void guc_policy_init(struct guc_policy *policy)
-{
-   policy->execution_quantum = POLICY_DEFAULT_EXECUTION_QUANTUM_US;
-   policy->preemption_time = POLICY_DEFAULT_PREEMPTION_TIME_US;
-   policy->fault_time = POLICY_DEFAULT_FAULT_TIME_US;
-   policy->policy_flags = 0;
-}
-
 static void guc_policies_init(struct guc_policies *policies)
 {
-   struct guc_policy *policy;
-   u32 p, i;
-
-   policies->dpc_promote_time = POLICY_DEFAULT_DPC_PROMOTE_TIME_US;
-   policies->max_num_work_items = POLICY_MAX_NUM_WI;
-
-   for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) {
-   for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++) {
-   policy = >policy[p][i];
-
-   guc_policy_init(policy);
-   }
-   }
-
+   policies->dpc_promote_time = GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US;
+   policies->max_num_work_items = GLOBAL_POLICY_MAX_NUM_WI;
+   /* Disable automatic resets as not yet supported. */
+   policies->global_flags = GLOBAL_POLICY_DISABLE_ENGINE_RESET;
policies->is_valid = 1;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index fb04e2211b79..251c3836bd2c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -247,32 +247,14 @@ struct guc_stage_desc {
 
 /* Scheduling policy settings */
 
-/* Reset engine upon preempt failure */
-#define POLICY_RESET_ENGINE(1<<0)
-/* Preempt to idle on quantum expiry */
-#define POLICY_PREEMPT_TO_IDLE (1<<1)
-
-#define POLICY_MAX_NUM_WI 15
-#define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 50
-#define POLICY_DEFAULT_EXECUTION_QUANTUM_US 100
-#define POLICY_DEFAULT_PREEMPTION_TIME_US 50
-#define POLICY_DEFAULT_FAULT_TIME_US 25
-
-struct guc_policy {
-   /* Time for one workload to execute. (in micro seconds) */
-   u32 execution_quantum;
-   /* Time to wait for a preemption request to completed before issuing a
-* reset. (in micro seconds). */
-   u32 preemption_time;
-   /* How much time to allow to run after the first fault is observed.
-* Then preempt afterwards. (in micro seconds) */
-   u32 fault_time;
-   u32 policy_flags;
-   u32 reserved[8];
-} __packed;
+#define GLOBAL_POLICY_MAX_NUM_WI 15
+
+/* Don't reset an engine upon preemption failure */
+#define GLOBAL_POLICY_DISABLE_ENGINE_RESET BIT(0)
+
+#define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 50
 
 struct guc_policies {
-   struct guc_policy 
policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINE_CLASSES];
u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
/* In micro seconds. How much time to allow before DPC processing is
 * called back via interrupt (to prevent DPC queue drain starving).
@@ -286,6 +268,7 @@ struct guc_policies {
 * idle. */
u32 max_num_work_items;
 
+   u32 global_flags;
u32 reserved[4];
 } __packed;
 
-- 
2.28.0

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Re: [Intel-gfx] [RFC PATCH 36/97] drm/i915/guc: Add non blocking CTB send function

[Matthew Brost]

On Thu, May 27, 2021 at 04:11:50PM +0100, Tvrtko Ursulin wrote:
> 
> On 27/05/2021 15:35, Matthew Brost wrote:
> > On Thu, May 27, 2021 at 11:02:24AM +0100, Tvrtko Ursulin wrote:
> > > 
> > > On 26/05/2021 19:10, Matthew Brost wrote:
> > > 
> > > [snip]
> > > 
> > > > > > > > +static int ct_send_nb(struct intel_guc_ct *ct,
> > > > > > > > + const u32 *action,
> > > > > > > > + u32 len,
> > > > > > > > + u32 flags)
> > > > > > > > +{
> > > > > > > > +   struct intel_guc_ct_buffer *ctb = >ctbs.send;
> > > > > > > > +   unsigned long spin_flags;
> > > > > > > > +   u32 fence;
> > > > > > > > +   int ret;
> > > > > > > > +
> > > > > > > > +   spin_lock_irqsave(>lock, spin_flags);
> > > > > > > > +
> > > > > > > > +   ret = ctb_has_room(ctb, len + 1);
> > > > > > > > +   if (unlikely(ret))
> > > > > > > > +   goto out;
> > > > > > > > +
> > > > > > > > +   fence = ct_get_next_fence(ct);
> > > > > > > > +   ret = ct_write(ct, action, len, fence, flags);
> > > > > > > > +   if (unlikely(ret))
> > > > > > > > +   goto out;
> > > > > > > > +
> > > > > > > > +   intel_guc_notify(ct_to_guc(ct));
> > > > > > > > +
> > > > > > > > +out:
> > > > > > > > +   spin_unlock_irqrestore(>lock, spin_flags);
> > > > > > > > +
> > > > > > > > +   return ret;
> > > > > > > > +}
> > > > > > > > +
> > > > > > > >  static int ct_send(struct intel_guc_ct *ct,
> > > > > > > >const u32 *action,
> > > > > > > >u32 len,
> > > > > > > > @@ -473,6 +541,7 @@ static int ct_send(struct intel_guc_ct *ct,
> > > > > > > >u32 response_buf_size,
> > > > > > > >u32 *status)
> > > > > > > >  {
> > > > > > > > +   struct intel_guc_ct_buffer *ctb = >ctbs.send;
> > > > > > > > struct ct_request request;
> > > > > > > > unsigned long flags;
> > > > > > > > u32 fence;
> > > > > > > > @@ -482,8 +551,20 @@ static int ct_send(struct intel_guc_ct *ct,
> > > > > > > > GEM_BUG_ON(!len);
> > > > > > > > GEM_BUG_ON(len & ~GUC_CT_MSG_LEN_MASK);
> > > > > > > > GEM_BUG_ON(!response_buf && response_buf_size);
> > > > > > > > +   might_sleep();
> > > > > > > 
> > > > > > > Sleep is just cond_resched below or there is more?
> > > > > > > 
> > > > > > 
> > > > > > Yes, the cond_resched.
> > > > > > 
> > > > > > > > +   /*
> > > > > > > > +* We use a lazy spin wait loop here as we believe that 
> > > > > > > > if the CT
> > > > > > > > +* buffers are sized correctly the flow control 
> > > > > > > > condition should be
> > > > > > > > +* rare.
> > > > > > > > +*/
> > > > > > > > +retry:
> > > > > > > > spin_lock_irqsave(>ctbs.send.lock, flags);
> > > > > > > > +   if (unlikely(!ctb_has_room(ctb, len + 1))) {
> > > > > > > > +   spin_unlock_irqrestore(>ctbs.send.lock, 
> > > > > > > > flags);
> > > > > > > > +   cond_resched();
> > > > > > > > +   goto retry;
> > > > > > > > +   }
> > > > > > > 
> > > > > > > If this patch is about adding a non-blocking send function, and 
> > > > > > > below we can
> > > > > > > see that it creates a fork:
> > > > > > > 
> > > > > > > intel_guc_ct_send:
> > > > > > > ...
> > > > > > >   if (flags & INTEL_GUC_SEND_NB)
> > > > > > >   return ct_send_nb(ct, action, len, flags);
> > > > > > > 
> > > > > > >   ret = ct_send(ct, action, len, response_buf, 
> > > > > > > response_buf_size, );
> > > > > > > 
> > > > > > > Then why is there a change in ct_send here, which is not the new
> > > > > > > non-blocking path?
> > > > > > > 
> > > > > > 
> > > > > > There is not a change to ct_send(), just to intel_guc_ct_send.
> > > > > 
> > > > > I was doing by the diff which says:
> > > > > 
> > > > >static int ct_send(struct intel_guc_ct *ct,
> > > > >  const u32 *action,
> > > > >  u32 len,
> > > > > @@ -473,6 +541,7 @@ static int ct_send(struct intel_guc_ct *ct,
> > > > >  u32 response_buf_size,
> > > > >  u32 *status)
> > > > >{
> > > > > + struct intel_guc_ct_buffer *ctb = >ctbs.send;
> > > > >   struct ct_request request;
> > > > >   unsigned long flags;
> > > > >   u32 fence;
> > > > > @@ -482,8 +551,20 @@ static int ct_send(struct intel_guc_ct *ct,
> > > > >   GEM_BUG_ON(!len);
> > > > >   GEM_BUG_ON(len & ~GUC_CT_MSG_LEN_MASK);
> > > > >   GEM_BUG_ON(!response_buf && response_buf_size);
> > > > > + might_sleep();
> > > > > + /*
> > > > > +  * We use a lazy spin wait loop here as we believe that if the 
> > > > > CT
> > > > > +  * buffers are sized correctly the flow control condition 
> > > > > should be
> > > > > +  * rare.
> > > > > +  */
> > > > > +retry:
> > > > >   spin_lock_irqsave(>ctbs.send.lock, flags);
> > > > > + if 

[Intel-gfx] ✗ Fi.CI.BUILD: warning for x86/gpu: add JasperLake to gen11 early quirks (rev2)

[Patchwork]

== Series Details ==

Series: x86/gpu: add JasperLake to gen11 early quirks (rev2)
URL   : https://patchwork.freedesktop.org/series/91082/
State : warning

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  MODPOST modules-only.symvers
ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:150: recipe for target 'modules-only.symvers' failed
make[1]: *** [modules-only.symvers] Error 1
make[1]: *** Deleting file 'modules-only.symvers'
Makefile:1759: recipe for target 'modules' failed
make: *** [modules] Error 2

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/build_32bit.log
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[Intel-gfx] ✓ Fi.CI.BAT: success for x86/gpu: add JasperLake to gen11 early quirks (rev2)

[Patchwork]

== Series Details ==

Series: x86/gpu: add JasperLake to gen11 early quirks (rev2)
URL   : https://patchwork.freedesktop.org/series/91082/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10187 -> Patchwork_20297


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/index.html

Known issues


  Here are the changes found in Patchwork_20297 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_tiled_blits@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271]) +3 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/fi-kbl-soraka/igt@gem_tiled_bl...@basic.html

  * igt@i915_selftest@live@execlists:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][3] ([i915#2782] / [i915#3462] 
/ [i915#794])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][4] ([i915#1886] / [i915#2291])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][5] -> [INCOMPLETE][6] ([i915#2782])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka:  NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
- fi-kbl-soraka:  NOTRUN -> [FAIL][9] ([i915#1436] / [i915#2426] / 
[i915#3363])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/fi-kbl-soraka/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0:
- fi-kbl-soraka:  [INCOMPLETE][10] ([i915#155]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html

  * igt@i915_selftest@live@gt_pm:
- fi-cml-s:   [DMESG-FAIL][12] ([i915#2291]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-cml-s/igt@i915_selftest@live@gt_pm.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/fi-cml-s/igt@i915_selftest@live@gt_pm.html

  
 Warnings 

  * igt@i915_selftest@live@execlists:
- fi-icl-u2:  [DMESG-FAIL][14] ([i915#3462]) -> [INCOMPLETE][15] 
([i915#2782] / [i915#3462])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-icl-u2/igt@i915_selftest@l...@execlists.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/fi-icl-u2/igt@i915_selftest@l...@execlists.html
- fi-cml-s:   [INCOMPLETE][16] ([i915#3462]) -> [DMESG-FAIL][17] 
([i915#3462])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-cml-s/igt@i915_selftest@l...@execlists.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/fi-cml-s/igt@i915_selftest@l...@execlists.html

  * igt@runner@aborted:
- fi-icl-u2:  [FAIL][18] ([i915#2426] / [i915#2782] / [i915#3363]) 
-> [FAIL][19] ([i915#2782] / [i915#3363])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-icl-u2/igt@run...@aborted.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/fi-icl-u2/igt@run...@aborted.html
- fi-skl-6700k2:  [FAIL][20] ([i915#1436] / [i915#2426] / [i915#3363]) 
-> [FAIL][21] ([i915#1436] / [i915#3363])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-skl-6700k2/igt@run...@aborted.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20297/fi-skl-6700k2/igt@run...@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1436]: 

Re: [Intel-gfx] [PATCH 02/21] drm: Add Plane Degamma Mode property

[Shankar, Uma]

> -Original Message-
> From: Harry Wentland 
> Sent: Friday, June 4, 2021 11:54 PM
> To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; 
> dri-
> de...@lists.freedesktop.org
> Cc: Modem, Bhanuprakash ; Cyr, Aric
> 
> Subject: Re: [PATCH 02/21] drm: Add Plane Degamma Mode property
> 
> On 2021-06-01 6:51 a.m., Uma Shankar wrote:
> > Add Plane Degamma Mode as an enum property. Create a helper function
> > for all plane color management features.
> >
> > This is an enum property with values as blob_id's and exposes the
> > various gamma modes supported and the lut ranges. Getting the blob id
> > in userspace, user can get the mode supported and also the range of
> > gamma mode supported with number of lut coefficients. It can then set
> > one of the modes using this enum property.
> >
> > Lut values will be sent through separate GAMMA_LUT blob property.
> >
> > Signed-off-by: Uma Shankar 
> > ---
> >  Documentation/gpu/drm-kms.rst | 90 ++
> >  drivers/gpu/drm/drm_atomic.c  |  1 +
> >  drivers/gpu/drm/drm_atomic_state_helper.c |  2 +
> >  drivers/gpu/drm/drm_atomic_uapi.c |  4 +
> >  drivers/gpu/drm/drm_color_mgmt.c  | 93 ++-
> >  include/drm/drm_mode_object.h |  2 +-
> >  include/drm/drm_plane.h   | 23 ++
> >  7 files changed, 212 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/gpu/drm-kms.rst
> > b/Documentation/gpu/drm-kms.rst index 87e5023e3f55..752be545e7d7
> > 100644
> > --- a/Documentation/gpu/drm-kms.rst
> > +++ b/Documentation/gpu/drm-kms.rst
> > @@ -514,9 +514,99 @@ Damage Tracking Properties  Color Management
> > Properties
> >  ---
> >
> > +Below is how a typical hardware pipeline for color will look like:
> > +
> > +.. kernel-render:: DOT
> > +   :alt: Display Color Pipeline
> > +   :caption: Display Color Pipeline Overview
> > +
> > +   digraph "KMS" {
> > +  node [shape=box]
> > +
> > +  subgraph cluster_static {
> > +  style=dashed
> > +  label="Display Color Hardware Blocks"
> > +
> > +  node [bgcolor=grey style=filled]
> > +  "Plane Degamma A" -> "Plane CSC/CTM A"
> > +  "Plane CSC/CTM A" -> "Plane Gamma A"
> > +  "Pipe Blender" [color=lightblue,style=filled, width=5.25, 
> > height=0.75];
> > +  "Plane Gamma A" -> "Pipe Blender"
> > + "Pipe Blender" -> "Pipe DeGamma"
> > +  "Pipe DeGamma" -> "Pipe CSC/CTM"
> > +  "Pipe CSC/CTM" -> "Pipe Gamma"
> > +  "Pipe Gamma" -> "Pipe Output"
> > +  }
> > +
> 
> It might be worthwhile to also highlight the YCbCr coefficient matrix in the 
> pipeline,
> between the FB and Plane degamma, i.e.
>   YCbCr coefficients > plane degamma > csc > ...
> 
> One problem with this view is that not all HW will support all (or any) of 
> these CM
> blocks on all planes. For example, on AMD HW cursors are very different from 
> other
> planes and don't really have full CM support.
> 
> > +  subgraph cluster_static {
> > +  style=dashed
> > +
> > +  node [shape=box]
> > +  "Plane Degamma B" -> "Plane CSC/CTM B"
> > +  "Plane CSC/CTM B" -> "Plane Gamma B"
> > +  "Plane Gamma B" -> "Pipe Blender"
> > +  }
> > +
> > +  subgraph cluster_static {
> > +  style=dashed
> > +
> > +  node [shape=box]
> > +  "Plane Degamma C" -> "Plane CSC/CTM C"
> > +  "Plane CSC/CTM C" -> "Plane Gamma C"
> > +  "Plane Gamma C" -> "Pipe Blender"
> > +  }
> > +
> > +  subgraph cluster_fb {
> > +  style=dashed
> > +  label="RAM"
> > +
> > +  node [shape=box width=1.7 height=0.2]
> > +
> > +  "FB 1" -> "Plane Degamma A"
> > +  "FB 2" -> "Plane Degamma B"
> > +  "FB 3" -> "Plane Degamma C"
> > +  }
> > +   }
> > +
> > +In real world usecases,
> > +
> > +1. Plane Degamma can be used to linearize a non linear gamma encoded
> > +framebuffer. This is needed to do any linear math like color space
> > +conversion. For ex, linearize frames encoded in SRGB or by HDR curve.
> > +
> > +2. Later Plane CTM block can convert the content to some different
> > +colorspace. For ex, SRGB to BT2020 etc.
> > +
> > +3. Plane Gamma block can be used later to re-apply the non-linear
> > +curve. This can also be used to apply Tone Mapping for HDR usecases.
> > +
> 
> This would mean you're blending in gamma space which is likely not what most
> compositors expect. There are numerous articles that describe why blending in
> gamma space is problematic, such as [1]
> 
> [1] https://ninedegreesbelow.com/photography/linear-gamma-blur-normal-
> blend.html
> 
> To blend in linear space this should be configured to do
> 
>   Plane Degamma > Plane CTM > CRTC Gamma
> 
> I think it would also be good if we moved away from calling this gamma. It's 
> really
> only gamma for legacy SDR scenarios. For HDR cases I would never expect 

Re: [Intel-gfx] [PATCH 01/21] drm: Add Enhanced Gamma and color lut range attributes

[Shankar, Uma]

> -Original Message-
> From: Harry Wentland 
> Sent: Friday, June 4, 2021 8:53 PM
> To: Shankar, Uma ; Pekka Paalanen
> 
> Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Modem,
> Bhanuprakash 
> Subject: Re: [PATCH 01/21] drm: Add Enhanced Gamma and color lut range
> attributes
> 
> On 2021-06-02 4:26 p.m., Shankar, Uma wrote:
> >
> >
> >> -Original Message-
> >> From: Pekka Paalanen 
> >> Sent: Wednesday, June 2, 2021 3:04 PM
> >> To: Shankar, Uma 
> >> Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
> >> Modem, Bhanuprakash 
> >> Subject: Re: [PATCH 01/21] drm: Add Enhanced Gamma and color lut
> >> range attributes
> >>
> >> On Tue,  1 Jun 2021 16:21:58 +0530
> >> Uma Shankar  wrote:
> >>
> >>> Existing LUT precision structure is having only 16 bit precision.
> >>> This is not enough for upcoming enhanced hardwares and advance
> >>> usecases like HDR processing. Hence added a new structure with 32
> >>> bit precision values.
> >>>
> >>> This also defines a new structure to define color lut ranges, along
> >>> with related macro definitions and enums. This will help describe
> >>> multi segmented lut ranges in the hardware.
> >>>
> >>> Signed-off-by: Uma Shankar 
> >>> ---
> >>>  include/uapi/drm/drm_mode.h | 58
> >>> +
> >>>  1 file changed, 58 insertions(+)
> >>>
> >>> diff --git a/include/uapi/drm/drm_mode.h
> >>> b/include/uapi/drm/drm_mode.h index 9b6722d45f36..d0ce48d2e732
> >>> 100644
> >>> --- a/include/uapi/drm/drm_mode.h
> >>> +++ b/include/uapi/drm/drm_mode.h
> >>> @@ -819,6 +819,64 @@ struct hdr_output_metadata {
> >>>   };
> >>>  };
> >>>
> >>> +/*
> >>> + * DRM_MODE_LUT_GAMMA|DRM_MODE_LUT_DEGAMMA is legal and
> means
> >> the LUT
> >>> + * can be used for either purpose, but not simultaneously. To
> >>> + expose
> >>> + * modes that support gamma and degamma simultaneously the gamma
> >>> + mode
> >>> + * must declare distinct DRM_MODE_LUT_GAMMA and
> >> DRM_MODE_LUT_DEGAMMA
> >>> + * ranges.
> >>> + */
> >>> +/* LUT is for gamma (after CTM) */
> >>> +#define DRM_MODE_LUT_GAMMA BIT(0)
> >>> +/* LUT is for degamma (before CTM) */ #define DRM_MODE_LUT_DEGAMMA
> >>> +BIT(1)
> >>> +/* linearly interpolate between the points */ #define
> >>> +DRM_MODE_LUT_INTERPOLATE BIT(2)
> >>> +/*
> >>> + * the last value of the previous range is the
> >>> + * first value of the current range.
> >>> + */
> >>> +#define DRM_MODE_LUT_REUSE_LAST BIT(3)
> >>> +/* the curve must be non-decreasing */ #define
> >>> +DRM_MODE_LUT_NON_DECREASING BIT(4)
> >>> +/* the curve is reflected across origin for negative inputs */
> >>> +#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5)
> >>> +/* the same curve (red) is used for blue and green channels as well
> >>> +*/ #define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6)
> >>> +
> >>> +struct drm_color_lut_range {
> >>> + /* DRM_MODE_LUT_* */
> >>> + __u32 flags;
> >>> + /* number of points on the curve */
> >>> + __u16 count;
> >>> + /* input/output bits per component */
> >>> + __u8 input_bpc, output_bpc;
> >>> + /* input start/end values */
> >>> + __s32 start, end;
> >>> + /* output min/max values */
> >>> + __s32 min, max;
> >>> +};
> >>> +
> >>> +enum lut_type {
> >>
> >> Unprefixed type name in UAPI headers is probably not a good idea.
> >
> > Ok, will rename these.
> >
> >>> + LUT_TYPE_DEGAMMA = 0,
> >>> + LUT_TYPE_GAMMA = 1,
> >>> +};
> >>
> >> All the above stuff seems to be the same in your other patch series'
> >> patch "[PATCH 1/9] drm: Add gamma mode property". Is this series
> >> replacing the series "[PATCH 0/9] Enhance pipe color support for
> >> multi segmented luts" or what does this mean?
> >
> > The concept and idea is similar and the range definition is also
> > common. But this series focuses on plane color management while the other 
> > one
> is for pipe/crtc color features.
> > Hence separated and floated them as unique series for review.
> >
> 
> Might be better in this case to combine both patchsets. It wasn't entirely 
> clear to me
> whether I could base one patchset on top of the other (doesn't look like it) 
> and what
> base to apply them on. I had success applying the plane stuff on drm-next and 
> the
> crtc stuff on drm-intel.

Sure Harry, I guess its better to combine both the series to avoid any 
confusions.
I will send out next version with some more UAPI documentation based on the 
feedback
received.

Regards,
Uma Shankar
> 
> Harry
> 
> > Regards,
> > Uma Shankar
> >>
> >> Thanks,
> >> pq
> >>
> >>> +
> >>> +/*
> >>> + * Creating 64 bit palette entries for better data
> >>> + * precision. This will be required for HDR and
> >>> + * similar color processing usecases.
> >>> + */
> >>> +struct drm_color_lut_ext {
> >>> + /*
> >>> +  * Data is U32.32 fixed point format.
> >>> +  */
> >>> + __u64 red;
> >>> + __u64 green;
> >>> + __u64 blue;
> >>> + __u64 reserved;
> >>> +};
> >>> +
> >>>  #define DRM_MODE_PAGE_FLIP_EVENT 0x01  #define
> >>> 

[Intel-gfx] ✗ Fi.CI.BUILD: warning for series starting with [v3,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/2] drm/i915/display: Introduce new 
intel_psr_pause/resume function
URL   : https://patchwork.freedesktop.org/series/91096/
State : warning

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  MODPOST modules-only.symvers
ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:150: recipe for target 'modules-only.symvers' failed
make[1]: *** [modules-only.symvers] Error 1
make[1]: *** Deleting file 'modules-only.symvers'
Makefile:1759: recipe for target 'modules' failed
make: *** [modules] Error 2

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/build_32bit.log
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/2] drm/i915/display: Introduce new 
intel_psr_pause/resume function
URL   : https://patchwork.freedesktop.org/series/91096/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10187 -> Patchwork_20296


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_20296 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20296, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_20296:

### IGT changes ###

 Possible regressions 

  * igt@kms_chamelium@vga-edid-read:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@kms_chamel...@vga-edid-read.html

  
Known issues


  Here are the changes found in Patchwork_20296 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_tiled_blits@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271]) +3 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@gem_tiled_bl...@basic.html

  * igt@i915_selftest@live@execlists:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][4] ([i915#2782] / [i915#3462] 
/ [i915#794])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#2291])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][6] -> [INCOMPLETE][7] ([i915#2782])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
- fi-kbl-soraka:  NOTRUN -> [FAIL][10] ([i915#1436] / [i915#3363])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0:
- fi-kbl-soraka:  [INCOMPLETE][11] ([i915#155]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html

  * igt@i915_selftest@live@gt_pm:
- fi-cml-s:   [DMESG-FAIL][13] ([i915#2291]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-cml-s/igt@i915_selftest@live@gt_pm.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-cml-s/igt@i915_selftest@live@gt_pm.html

  
 Warnings 

  * igt@i915_selftest@live@execlists:
- fi-icl-u2:  [DMESG-FAIL][15] ([i915#3462]) -> [INCOMPLETE][16] 
([i915#2782] / [i915#3462])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-icl-u2/igt@i915_selftest@l...@execlists.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-icl-u2/igt@i915_selftest@l...@execlists.html
- fi-cml-s:   [INCOMPLETE][17] ([i915#3462]) -> [DMESG-FAIL][18] 
([i915#3462])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-cml-s/igt@i915_selftest@l...@execlists.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20296/fi-cml-s/igt@i915_selftest@l...@execlists.html

  * igt@runner@aborted:
- fi-icl-u2:  [FAIL][19] ([i915#2426] / [i915#2782] / [i915#3363]) 
-> [FAIL][20] ([i915#2782] / [i915#3363])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10187/fi-icl-u2/igt@run...@aborted.html
   [20]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/2] drm/i915/display: Introduce new intel_psr_pause/resume function

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/2] drm/i915/display: Introduce new 
intel_psr_pause/resume function
URL   : https://patchwork.freedesktop.org/series/91096/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1893:21:expected struct 
i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1893:21:got void [noderef] 
__iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1893:21: warning: incorrect type 
in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative 
(-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative 
(-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' 
- different lock contexts 

Re: [Intel-gfx] [RFC v3 1/2] drm/i915/dg1: Adjust the AUDIO power domain

[Kai Vehmanen]

Hi,

On Tue, 1 Jun 2021, Anshuman Gupta wrote:

> DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power
> well. Adjusting the power domain accordingly to
> POWER_DOMAIN_AUDIO_VERBS for audio detection and POWER_DOMAIN_AUDIO
> for audio playback.

thanks Anshuman! From audio perspective this looks good to go. 

It would seem we don't need any additional code in display/intel_audio.c. 
In theory, this leaves some corner cases, where we will take PD_AUDIO when 
only PD_AUDIO_VERBS would suffice, but these mostly relate to initial 
audio driver probe, so no need add separate logic for these.

Br, Kai

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[Intel-gfx] ✗ Fi.CI.IGT: failure for x86/gpu: add JasperLake to gen11 early quirks

[Patchwork]

== Series Details ==

Series: x86/gpu: add JasperLake to gen11 early quirks
URL   : https://patchwork.freedesktop.org/series/91082/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10182_full -> Patchwork_20293_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_20293_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20293_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20293_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_mmap_gtt@basic-small-bo-tiledx:
- shard-iclb: [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10182/shard-iclb7/igt@gem_mmap_...@basic-small-bo-tiledx.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/shard-iclb8/igt@gem_mmap_...@basic-small-bo-tiledx.html

  
Known issues


  Here are the changes found in Patchwork_20293_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-clear:
- shard-glk:  [PASS][3] -> [FAIL][4] ([i915#1888] / [i915#3160])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10182/shard-glk8/igt@gem_cre...@create-clear.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/shard-glk2/igt@gem_cre...@create-clear.html

  * igt@gem_ctx_persistence@engines-mixed:
- shard-snb:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +2 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/shard-snb2/igt@gem_ctx_persiste...@engines-mixed.html

  * igt@gem_ctx_persistence@smoketest:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2896])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10182/shard-tglb5/igt@gem_ctx_persiste...@smoketest.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/shard-tglb7/igt@gem_ctx_persiste...@smoketest.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][8] -> [FAIL][9] ([i915#2846])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10182/shard-glk9/igt@gem_exec_f...@basic-deadline.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/shard-glk4/igt@gem_exec_f...@basic-deadline.html
- shard-apl:  NOTRUN -> [FAIL][10] ([i915#2846])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/shard-apl3/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar 
issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10182/shard-iclb7/igt@gem_exec_fair@basic-none-r...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/shard-iclb2/igt@gem_exec_fair@basic-none-r...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842]) +2 similar 
issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10182/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/shard-tglb6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl:  [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10182/shard-kbl2/igt@gem_exec_fair@basic-p...@vcs1.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][17] -> [FAIL][18] ([i915#2842]) +3 similar 
issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10182/shard-glk1/igt@gem_exec_fair@basic-throt...@rcs0.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/shard-glk8/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_reloc@basic-wide-active@bcs0:
- shard-apl:  NOTRUN -> [FAIL][19] ([i915#2389]) +3 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/shard-apl3/igt@gem_exec_reloc@basic-wide-act...@bcs0.html

  * igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][20] ([i915#2389])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/shard-iclb1/igt@gem_exec_reloc@basic-wide-act...@vcs1.html

  * igt@gem_huc_copy@huc-copy:
- shard-apl:  NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#2190])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/shard-apl8/igt@gem_huc_c...@huc-copy.html

  * igt@gem_mmap_gtt@big-copy:
- shard-glk:  [PASS][22] -> [FAIL][23] 

[Intel-gfx] [PATCH V2] x86/gpu: add JasperLake to gen11 early quirks

[Tejas Upadhyay]

Let's reserve JSL stolen memory for graphics.

JasperLake is a gen11 platform which is compatible with
ICL/EHL changes.

V1:
- Added Cc: x...@kernel.org

Cc: x...@kernel.org
Signed-off-by: Tejas Upadhyay 
---
 arch/x86/kernel/early-quirks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index b553ffe9b985..38837dad46e6 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -549,6 +549,7 @@ static const struct pci_device_id intel_early_ids[] 
__initconst = {
INTEL_CNL_IDS(_early_ops),
INTEL_ICL_11_IDS(_early_ops),
INTEL_EHL_IDS(_early_ops),
+   INTEL_JSL_IDS(_early_ops),
INTEL_TGL_12_IDS(_early_ops),
INTEL_RKL_IDS(_early_ops),
INTEL_ADLS_IDS(_early_ops),
-- 
2.31.1

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[Intel-gfx] [PATCH v3 2/2] drm/i915: Disable PSR around cdclk changes

[Gwan-gyeong Mun]

From: Ville Syrjälä 

AUX logic is often clocked from cdclk. Disable PSR to make sure
there are no hw initiated AUX transactions in flight while we
change the cdclk frequency.

Cc: Mika Kahola 
Signed-off-by: Ville Syrjälä 
Signed-off-by: Gwan-gyeong Mun 
Reviewed-by: Mika Kahola 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4656a6edc3be..618a9e1e2b0c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -28,6 +28,7 @@
 #include "intel_cdclk.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
+#include "intel_psr.h"
 #include "intel_sideband.h"
 
 /**
@@ -1908,6 +1909,12 @@ static void intel_set_cdclk(struct drm_i915_private 
*dev_priv,
 
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
 
+   for_each_intel_encoder_with_psr(_priv->drm, encoder) {
+   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+   intel_psr_pause(intel_dp);
+   }
+
/*
 * Lock aux/gmbus while we change cdclk in case those
 * functions use cdclk. Not all platforms/ports do,
@@ -1930,6 +1937,12 @@ static void intel_set_cdclk(struct drm_i915_private 
*dev_priv,
}
mutex_unlock(_priv->gmbus_mutex);
 
+   for_each_intel_encoder_with_psr(_priv->drm, encoder) {
+   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+   intel_psr_resume(intel_dp);
+   }
+
if (drm_WARN(_priv->drm,
 intel_cdclk_changed(_priv->cdclk.hw, cdclk_config),
 "cdclk state doesn't match!\n")) {
-- 
2.31.1

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[Intel-gfx] [PATCH v3 1/2] drm/i915/display: Introduce new intel_psr_pause/resume function

[Gwan-gyeong Mun]

This introduces the following function that can exit and activate a psr
source when intel_psr is already enabled.

- intel_psr_pause(): Pause current PSR. It deactivates current psr state.
- intel_psr_resume(): Resume paused PSR. It activates paused psr state.

v2: Address Jose's review comment.
  - Remove unneeded changes around the intel_psr_enable().
  - Add intel_psr_post_exit() which processes waiting until PSR is idle
and WA for SelectiveFetch.
v3: Address Jose's review comment.
  - Rename intel_psr_post_exit() to intel_psr_wait_exit_locked().
  - Move WA_1408330847 to intel_psr_disable_locked()
  - If the PSR is paused by an explicit intel_psr_paused() call, make the
intel_psr_flush() not to activate PSR.

Cc: José Roberto de Souza 
Cc: Stanislav Lisovskiy 
Cc: Ville Syrjälä 
Signed-off-by: Gwan-gyeong Mun 
Signed-off-by: Matt Roper 
---
 .../drm/i915/display/intel_display_types.h|  1 +
 drivers/gpu/drm/i915/display/intel_psr.c  | 94 ---
 drivers/gpu/drm/i915/display/intel_psr.h  |  2 +
 3 files changed, 86 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index b8d1f702d808..ee7cbdd7db87 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1482,6 +1482,7 @@ struct intel_psr {
bool sink_support;
bool source_support;
bool enabled;
+   bool paused;
enum pipe pipe;
enum transcoder transcoder;
bool active;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 000e1ffe8c05..f547c80ed55c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1113,6 +1113,7 @@ static void intel_psr_enable_locked(struct intel_dp 
*intel_dp,
intel_psr_enable_sink(intel_dp);
intel_psr_enable_source(intel_dp);
intel_dp->psr.enabled = true;
+   intel_dp->psr.paused = false;
 
intel_psr_activate(intel_dp);
 }
@@ -1182,22 +1183,12 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
intel_dp->psr.active = false;
 }
 
-static void intel_psr_disable_locked(struct intel_dp *intel_dp)
+static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
 {
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
i915_reg_t psr_status;
u32 psr_status_mask;
 
-   lockdep_assert_held(_dp->psr.lock);
-
-   if (!intel_dp->psr.enabled)
-   return;
-
-   drm_dbg_kms(_priv->drm, "Disabling PSR%s\n",
-   intel_dp->psr.psr2_enabled ? "2" : "1");
-
-   intel_psr_exit(intel_dp);
-
if (intel_dp->psr.psr2_enabled) {
psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
@@ -1210,6 +1201,22 @@ static void intel_psr_disable_locked(struct intel_dp 
*intel_dp)
if (intel_de_wait_for_clear(dev_priv, psr_status,
psr_status_mask, 2000))
drm_err(_priv->drm, "Timed out waiting PSR idle state\n");
+}
+
+static void intel_psr_disable_locked(struct intel_dp *intel_dp)
+{
+   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+   lockdep_assert_held(_dp->psr.lock);
+
+   if (!intel_dp->psr.enabled)
+   return;
+
+   drm_dbg_kms(_priv->drm, "Disabling PSR%s\n",
+   intel_dp->psr.psr2_enabled ? "2" : "1");
+
+   intel_psr_exit(intel_dp);
+   intel_psr_wait_exit_locked(intel_dp);
 
/* WA 1408330847 */
if (intel_dp->psr.psr2_sel_fetch_enabled &&
@@ -1254,6 +1261,61 @@ void intel_psr_disable(struct intel_dp *intel_dp,
cancel_delayed_work_sync(_dp->psr.dc3co_work);
 }
 
+/**
+ * intel_psr_pause - Pause PSR
+ * @intel_dp: Intel DP
+ *
+ * This function need to be called after enabling psr.
+ */
+void intel_psr_pause(struct intel_dp *intel_dp)
+{
+   struct intel_psr *psr = _dp->psr;
+
+   if (!CAN_PSR(intel_dp))
+   return;
+
+   mutex_lock(>lock);
+
+   if (!psr->active) {
+   mutex_unlock(>lock);
+   return;
+   }
+
+   intel_psr_exit(intel_dp);
+   intel_psr_wait_exit_locked(intel_dp);
+   psr->paused = true;
+
+   mutex_unlock(>lock);
+
+   cancel_work_sync(>work);
+   cancel_delayed_work_sync(>dc3co_work);
+}
+
+/**
+ * intel_psr_resume - Resume PSR
+ * @intel_dp: Intel DP
+ *
+ * This function need to be called after pausing psr.
+ */
+void intel_psr_resume(struct intel_dp *intel_dp)
+{
+   struct intel_psr *psr = _dp->psr;
+
+   if (!CAN_PSR(intel_dp))
+   return;
+
+   mutex_lock(>lock);
+
+   if (!psr->paused)
+   goto unlock;
+
+   psr->paused = false;
+   intel_psr_activate(intel_dp);
+
+unlock:
+   mutex_unlock(>lock);
+}
+
 static 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: remove duplicated argument

[Patchwork]

== Series Details ==

Series: drm/i915/display: remove duplicated argument
URL   : https://patchwork.freedesktop.org/series/91086/
State : failure

== Summary ==

Applying: drm/i915/display: remove duplicated argument
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/display/intel_display_power.c
Falling back to patching base and 3-way merge...
No changes -- Patch already applied.


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[Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915/dsc: Fix bigjoiner check in dsc_disable (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dsc: Fix bigjoiner check in dsc_disable (rev2)
URL   : https://patchwork.freedesktop.org/series/91006/
State : warning

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  MODPOST modules-only.symvers
ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:150: recipe for target 'modules-only.symvers' failed
make[1]: *** [modules-only.symvers] Error 1
make[1]: *** Deleting file 'modules-only.symvers'
Makefile:1759: recipe for target 'modules' failed
make: *** [modules] Error 2

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/build_32bit.log
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsc: Fix bigjoiner check in dsc_disable (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dsc: Fix bigjoiner check in dsc_disable (rev2)
URL   : https://patchwork.freedesktop.org/series/91006/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10184 -> Patchwork_20294


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/index.html

New tests
-

  New tests have been introduced between CI_DRM_10184 and Patchwork_20294:

### New IGT tests (16) ###

  * igt@kms_flip@basic-flip-vs-dpms@a-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.69] s

  * igt@kms_flip@basic-flip-vs-dpms@b-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.76] s

  * igt@kms_flip@basic-flip-vs-dpms@c-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.76] s

  * igt@kms_flip@basic-flip-vs-dpms@d-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.78] s

  * igt@kms_flip@basic-flip-vs-modeset@a-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.68] s

  * igt@kms_flip@basic-flip-vs-modeset@b-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.77] s

  * igt@kms_flip@basic-flip-vs-modeset@c-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.75] s

  * igt@kms_flip@basic-flip-vs-modeset@d-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.77] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-dp3:
- Statuses : 1 pass(s)
- Exec time: [1.00] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@b-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.97] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.97] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@d-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.97] s

  * igt@kms_flip@basic-plain-flip@a-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.73] s

  * igt@kms_flip@basic-plain-flip@b-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.69] s

  * igt@kms_flip@basic-plain-flip@c-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.68] s

  * igt@kms_flip@basic-plain-flip@d-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.69] s

  

Known issues


  Here are the changes found in Patchwork_20294 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-skl-6600u:   NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html

  * igt@i915_selftest@live@execlists:
- fi-skl-6600u:   NOTRUN -> [DMESG-FAIL][2] ([i915#3462])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/fi-skl-6600u/igt@i915_selftest@l...@execlists.html

  * igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u:   NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u:   NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#533])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_vgem@basic-userptr:
- fi-skl-6600u:   NOTRUN -> [SKIP][5] ([fdo#109271]) +3 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/fi-skl-6600u/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- fi-skl-6600u:   NOTRUN -> [FAIL][6] ([i915#1436] / [i915#3363])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/fi-skl-6600u/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-skl-guc: [DMESG-FAIL][7] ([i915#2291] / [i915#541]) -> 
[PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10184/fi-skl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/fi-skl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2:  [DMESG-WARN][9] ([i915#2868]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10184/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html

  
 Warnings 

  * igt@i915_selftest@live@execlists:
- fi-icl-u2:  [DMESG-FAIL][11] ([i915#3462]) -> [INCOMPLETE][12] 
([i915#2782] / [i915#3462])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10184/fi-icl-u2/igt@i915_selftest@l...@execlists.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20294/fi-icl-u2/igt@i915_selftest@l...@execlists.html

  * igt@runner@aborted:
- fi-icl-u2:  [FAIL][13] ([i915#2426] / [i915#2782] / [i915#3363]) 
-> [FAIL][14] ([i915#2782] / [i915#3363])
   [13]: 

Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/display: Nuke has_infoframe

[Gwan-gyeong Mun]

On 5/21/21 10:58 PM, Souza, Jose wrote:

On Fri, 2021-05-21 at 16:27 +0100, Mun, Gwan-gyeong wrote:

On Fri, 2021-05-14 at 16:22 -0700, José Roberto de Souza wrote:

This was only reduntant information has_hdmi_sink can do the same job.
set_infoframes() hooks will call intel_write_infoframe() for the
supported infoframes types and it will only be enabled if given type
is set in crtc_state->infoframes.enable.

While at it also fixing the style of dig_port->set_infoframes() calls.

Cc: Ville Syrjälä 
Signed-off-by: José Roberto de Souza 
---
  drivers/gpu/drm/i915/display/g4x_hdmi.c   | 22 ++-
  drivers/gpu/drm/i915/display/intel_ddi.c  | 17 +-
  drivers/gpu/drm/i915/display/intel_display.c  |  6 ++---
  .../drm/i915/display/intel_display_types.h|  3 ---
  drivers/gpu/drm/i915/display/intel_dp_mst.c   |  4 ++--
  drivers/gpu/drm/i915/display/intel_hdmi.c | 13 +--
  6 files changed, 22 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c
b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index be352e9f0afc..f35db96e6239 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -105,9 +105,6 @@ static void intel_hdmi_get_config(struct
intel_encoder *encoder,
 pipe_config->infoframes.enable |=
 intel_hdmi_infoframes_enabled(encoder, pipe_config);
  
-   if (pipe_config->infoframes.enable)

-   pipe_config->has_infoframe = true;
-

"pipe_config->infoframes.enable" is set with information about the
infoframes currently active in the hardware through "pipe_config-

infoframes.enable |= intel_hdmi_infoframes_enabled(encoder,

pipe_config);".

Therefore, when calling set_infoframes() semantically, the
has_infoframe information set by "if (pipe_config->infoframes.enable)
pipe_config->has_infoframe = true;" is more clear.


That don't work because the functions that will check if a infoframe is needed and 
set pipe_config->infoframes.enable depends on pipe_config-

has_infoframe/crtc_state->has_hdmi_sink.

That is probably because DVI ports don't support infoframes but in i915 are 
handle very similar to HDMI.



DP and HDMI can have infoframes that fit each specification in the 
specification.
And (although not used in this sense here) when dp has hdmi sink, it can 
be thought of using dp to hdmi protocol converter. I think it might be a 
little unclear, but what do you think?

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Re: [Intel-gfx] [PATCH] drm/i915/display: remove duplicated argument

[Imre Deak]

On Sat, Jun 05, 2021 at 11:22:07AM +0800, Wan Jiabing wrote:
> Fix the following coccicheck warning:
> 
> ./drivers/gpu/drm/i915/display/intel_display_power.c:3081:1-28:
>  duplicated argument to & or |
> 
> This commit fixes duplicate argument. It might be a typo.
> But what I can do is to remove it now.
> 
> Signed-off-by: Wan Jiabing 

Thanks, pushed to drm-intel-next.

> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 3e1f6ec61514..4298ae684d7d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -3078,7 +3078,6 @@ intel_display_power_put_mask_in_set(struct 
> drm_i915_private *i915,
>   BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\
>   BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) |  \
>   BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) |  \
> - BIT_ULL(POWER_DOMAIN_AUX_C) |   \
>   BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) |  \
>   BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) |  \
>   BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) |  \
> -- 
> 2.20.1
> 
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[Intel-gfx] ✗ Fi.CI.BUILD: warning for x86/gpu: add JasperLake to gen11 early quirks

[Patchwork]

== Series Details ==

Series: x86/gpu: add JasperLake to gen11 early quirks
URL   : https://patchwork.freedesktop.org/series/91082/
State : warning

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  MODPOST modules-only.symvers
ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:150: recipe for target 'modules-only.symvers' failed
make[1]: *** [modules-only.symvers] Error 1
make[1]: *** Deleting file 'modules-only.symvers'
Makefile:1759: recipe for target 'modules' failed
make: *** [modules] Error 2

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/build_32bit.log
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[Intel-gfx] ✓ Fi.CI.BAT: success for x86/gpu: add JasperLake to gen11 early quirks

[Patchwork]

== Series Details ==

Series: x86/gpu: add JasperLake to gen11 early quirks
URL   : https://patchwork.freedesktop.org/series/91082/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10182 -> Patchwork_20293


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/index.html

Known issues


  Here are the changes found in Patchwork_20293 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html

  * igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u:   NOTRUN -> [WARN][2] ([i915#2283])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_huc_copy@huc-copy:
- fi-skl-6700k2:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-skl-6700k2/igt@gem_huc_c...@huc-copy.html

  * igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][4] -> [INCOMPLETE][5] ([i915#151])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10182/fi-kbl-guc/igt@i915_pm_...@module-reload.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-kbl-guc/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-kefka:   NOTRUN -> [INCOMPLETE][6] ([i915#2782] / [i915#2940] 
/ [i915#3462])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
- fi-skl-6700k2:  NOTRUN -> [DMESG-FAIL][7] ([i915#3462])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-skl-6700k2/igt@i915_selftest@l...@execlists.html
- fi-bdw-5557u:   NOTRUN -> [DMESG-FAIL][8] ([i915#3462])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-bdw-5557u/igt@i915_selftest@l...@execlists.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u:   [PASS][9] -> [FAIL][10] ([i915#1372])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10182/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-skl-6700k2:  NOTRUN -> [SKIP][11] ([fdo#109271]) +12 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-skl-6700k2/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_chamelium@hdmi-edid-read:
- fi-bsw-kefka:   NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-bsw-kefka/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6700k2:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-skl-6700k2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@cursor_plane_move:
- fi-bsw-kefka:   NOTRUN -> [SKIP][14] ([fdo#109271]) +14 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-bsw-kefka/igt@kms_psr@cursor_plane_move.html
- fi-bdw-5557u:   NOTRUN -> [SKIP][15] ([fdo#109271]) +5 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-bdw-5557u/igt@kms_psr@cursor_plane_move.html

  * igt@runner@aborted:
- fi-bsw-kefka:   NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#1436])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-bsw-kefka/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][17] ([i915#2782]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10182/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  
 Warnings 

  * igt@i915_selftest@live@execlists:
- fi-cfl-8109u:   [DMESG-FAIL][19] ([i915#3462]) -> [INCOMPLETE][20] 
([i915#3462])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10182/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
- fi-cml-s:   [DMESG-FAIL][21] ([i915#3462]) -> [INCOMPLETE][22] 
([i915#3462])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10182/fi-cml-s/igt@i915_selftest@l...@execlists.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20293/fi-cml-s/igt@i915_selftest@l...@execlists.html

  * 

Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/display: Allow fastsets when DP_SDP_VSC infoframe do not match with PSR enabled

[Gwan-gyeong Mun]

Looks good to me.
Reviewed-by: Gwan-gyeong Mun 

On 5/15/21 2:22 AM, José Roberto de Souza wrote:

When PSR is enabled it handles DP_SDP_VSC, changing revision and all
the other fields as necessary.
It can also enabled and disable this SDP as needed without a full
modeset.

So here masking DP_SDP_VSC bit when previous and future state PSR
enabled, it will still be checked when comparing the asked state
to what was programmed to hardware.

Cc: Gwan-gyeong Mun 
Cc: Radhakrishna Sripada 
Reported-by: Ville Syrjälä 
Fixes: 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration 
read out"
Signed-off-by: José Roberto de Souza 
---
  drivers/gpu/drm/i915/display/intel_display.c | 17 -
  1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 51f499271cc8..ebac1bd5cfe5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8260,6 +8260,16 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
} \
  } while (0)
  
+#define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \

+   if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
+   pipe_config_mismatch(fastset, crtc, __stringify(name), \
+"(expected 0x%08x, found 0x%08x)", \
+current_config->name & (mask), \
+pipe_config->name & (mask)); \
+   ret = false; \
+   } \
+} while (0)
+
  #define PIPE_CONF_CHECK_I(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_mismatch(fastset, crtc, __stringify(name), \
@@ -8606,7 +8616,12 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
PIPE_CONF_CHECK_I(min_voltage_level);
}
  
-	PIPE_CONF_CHECK_X(infoframes.enable);

+   if (fastset && (current_config->has_psr || pipe_config->has_psr))
+   PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
+   
~intel_hdmi_infoframe_enable(DP_SDP_VSC));
+   else
+   PIPE_CONF_CHECK_X(infoframes.enable);
+
PIPE_CONF_CHECK_X(infoframes.gcp);
PIPE_CONF_CHECK_INFOFRAME(avi);
PIPE_CONF_CHECK_INFOFRAME(spd);


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[Intel-gfx] [PATCH] drm/i915/display: remove duplicated argument

[Wan Jiabing]

Fix the following coccicheck warning:

./drivers/gpu/drm/i915/display/intel_display_power.c:3081:1-28:
 duplicated argument to & or |

This commit fixes duplicate argument. It might be a typo.
But what I can do is to remove it now.

Signed-off-by: Wan Jiabing 
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 3e1f6ec61514..4298ae684d7d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -3078,7 +3078,6 @@ intel_display_power_put_mask_in_set(struct 
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) |  \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) |  \
-   BIT_ULL(POWER_DOMAIN_AUX_C) |   \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) |  \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) |  \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) |  \
-- 
2.20.1

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