Re: [Intel-gfx] [PATCH] kernel/locking: Add context to ww_mutex_trylock.
Op 08-09-2021 om 12:14 schreef Peter Zijlstra:
> On Tue, Sep 07, 2021 at 03:20:44PM +0200, Maarten Lankhorst wrote:
>> i915 will soon gain an eviction path that trylock a whole lot of locks
>> for eviction, getting dmesg failures like below:
>>
>> BUG: MAX_LOCK_DEPTH too low!
>> turning off the locking correctness validator.
>> depth: 48 max: 48!
>> 48 locks held by i915_selftest/5776:
>> #0: 888101a79240 (>mutex){}-{3:3}, at:
>> __driver_attach+0x88/0x160
>> #1: c99778c0 (reservation_ww_class_acquire){+.+.}-{0:0}, at:
>> i915_vma_pin.constprop.63+0x39/0x1b0 [i915]
>> #2: 88800cf74de8 (reservation_ww_class_mutex){+.+.}-{3:3}, at:
>> i915_vma_pin.constprop.63+0x5f/0x1b0 [i915]
>> #3: 88810c7f9e38 (>mutex/1){+.+.}-{3:3}, at:
>> i915_vma_pin_ww+0x1c4/0x9d0 [i915]
>> #4: 88810bad5768 (reservation_ww_class_mutex){+.+.}-{3:3}, at:
>> i915_gem_evict_something+0x110/0x860 [i915]
>> #5: 88810bad60e8 (reservation_ww_class_mutex){+.+.}-{3:3}, at:
>> i915_gem_evict_something+0x110/0x860 [i915]
>> ...
>> #46: 88811964d768 (reservation_ww_class_mutex){+.+.}-{3:3}, at:
>> i915_gem_evict_something+0x110/0x860 [i915]
>> #47: 88811964e0e8 (reservation_ww_class_mutex){+.+.}-{3:3}, at:
>> i915_gem_evict_something+0x110/0x860 [i915]
>> INFO: lockdep is turned off.
>> As an intermediate solution, add an acquire context to ww_mutex_trylock,
>> which allows us to do proper nesting annotations on the trylocks, making
>> the above lockdep splat disappear.
> Fair enough I suppose.
>
>> +/**
>> + * ww_mutex_trylock - tries to acquire the w/w mutex with optional acquire
>> context
>> + * @lock: mutex to lock
>> + * @ctx: optional w/w acquire context
>> + *
>> + * Trylocks a mutex with the optional acquire context; no deadlock
>> detection is
>> + * possible. Returns 1 if the mutex has been acquired successfully, 0
>> otherwise.
>> + *
>> + * Unlike ww_mutex_lock, no deadlock handling is performed. However, if a
>> @ctx is
>> + * specified, -EALREADY and -EDEADLK handling may happen in calls to
>> ww_mutex_lock.
>> + *
>> + * A mutex acquired with this function must be released with
>> ww_mutex_unlock.
>> + */
>> +int __sched
>> +ww_mutex_trylock(struct ww_mutex *ww, struct ww_acquire_ctx *ctx)
>> +{
>> +bool locked;
>> +
>> +if (!ctx)
>> +return mutex_trylock(>base);
>> +
>> +#ifdef CONFIG_DEBUG_MUTEXES
>> +DEBUG_LOCKS_WARN_ON(ww->base.magic != >base);
>> +#endif
>> +
>> +preempt_disable();
>> +locked = __mutex_trylock(>base);
>> +
>> +if (locked) {
>> +ww_mutex_set_context_fastpath(ww, ctx);
>> +mutex_acquire_nest(>base.dep_map, 0, 1, >dep_map,
>> _RET_IP_);
>> +}
>> +preempt_enable();
>> +
>> +return locked;
>> +}
>> +EXPORT_SYMBOL(ww_mutex_trylock);
> You'll need a similar hunk in ww_rt_mutex.c
What tree has that file?
[Intel-gfx] ✓ Fi.CI.IGT: success for i915/uncore: constify the uncore vtables. (rev3)
== Series Details ==
Series: i915/uncore: constify the uncore vtables. (rev3)
URL : https://patchwork.freedesktop.org/series/94465/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10565_full -> Patchwork_20997_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20997_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_eio@hibernate:
- {shard-rkl}:[TIMEOUT][1] ([i915#3811]) -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-5/igt@gem_...@hibernate.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/shard-rkl-5/igt@gem_...@hibernate.html
Known issues
Here are the changes found in Patchwork_20997_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@in-flight-suspend:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#198])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-skl9/igt@gem_...@in-flight-suspend.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/shard-skl2/igt@gem_...@in-flight-suspend.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842]) +3 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/shard-tglb5/igt@gem_exec_fair@basic-f...@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][7] ([i915#2842])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html
* igt@gem_exec_suspend@basic-s0:
- shard-tglb: [PASS][10] -> [INCOMPLETE][11] ([i915#456])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-tglb3/igt@gem_exec_susp...@basic-s0.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/shard-tglb7/igt@gem_exec_susp...@basic-s0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][12] -> [SKIP][13] ([i915#2190])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-tglb8/igt@gem_huc_c...@huc-copy.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/shard-tglb6/igt@gem_huc_c...@huc-copy.html
* igt@gem_mmap_gtt@cpuset-big-copy:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#307])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-iclb8/igt@gem_mmap_...@cpuset-big-copy.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/shard-iclb4/igt@gem_mmap_...@cpuset-big-copy.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-glk: NOTRUN -> [SKIP][16] ([fdo#109271]) +3 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/shard-glk2/igt@gem_render_c...@linear-to-vebox-y-tiled.html
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#768])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/shard-iclb5/igt@gem_render_c...@linear-to-vebox-y-tiled.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-tglb: NOTRUN -> [SKIP][18] ([i915#3297])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/shard-tglb3/igt@gem_userptr_bl...@dmabuf-unsync.html
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#3297])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/shard-iclb5/igt@gem_userptr_bl...@dmabuf-unsync.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [PASS][20] -> [FAIL][21] ([i915#2521])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-skl5/igt@kms_async_fl...@alternate-sync-async-flip.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/shard-skl6/igt@kms_async_fl...@alternate-sync-async-flip.html
* igt@kms_atomic_interruptible@atomic-setmode:
- shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271]) +9 similar issues
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/shard-skl9/igt@kms_atomic_interrupti...@atomic-setmode.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][23] ([fdo#110725] / [fdo#111614])
[23]:
[Intel-gfx] ✓ Fi.CI.BAT: success for i915/uncore: constify the uncore vtables. (rev3)
== Series Details ==
Series: i915/uncore: constify the uncore vtables. (rev3)
URL : https://patchwork.freedesktop.org/series/94465/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10565 -> Patchwork_20997
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/index.html
Known issues
Here are the changes found in Patchwork_20997 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_selftest@live@gt_pm:
- {fi-jsl-1}: [DMESG-FAIL][1] ([i915#1886]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
Participating hosts (47 -> 32)
--
Missing(15): fi-ilk-m540 fi-hsw-gt1 fi-bdw-5557u bat-adls-5 bat-dg1-6
fi-bdw-gvtdvm fi-bsw-cyan fi-snb-2520m bat-adlp-4 fi-ctg-p8600 fi-hsw-4770
fi-ivb-3770 fi-bdw-samus bat-jsl-1 fi-snb-2600
Build changes
-
* Linux: CI_DRM_10565 -> Patchwork_20997
CI-20190529: 20190529
CI_DRM_10565: 8c3cd60dcfa81a649b14f0705eb5e5c9336f1881 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6201: be0d02ff0775235ead63ccb1e3a1e8c10f0209cf @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20997: fcc6ecfc788bdec6e2452aaca1238334b05c3b5d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fcc6ecfc788b drm/i915/uncore: constify the register vtables. (v2)
2e090337048c drm/i915/uncore: split the fw get function into separate vfunc
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20997/index.html
Re: [Intel-gfx] [PULL] drm-misc-fixes
On Thu, 9 Sept 2021 at 03:44, Thomas Zimmermann wrote: > > Hi Dave and Daniel, > > here's this week's PR for drm-misc-fixes. One patch is a potential deadlock > in TTM, the other enables an additional plane in kmb. I'm slightly unhappy > that the latter one ended up in -fixes as it's not a bugfix AFAICT. To avoid messy merge window, I'm not pulling this until after rc1 unless there is some major reason? the current drm-next doesn't have v5.14 in it, and the merge is rather ugly right now. (maybe I should always pull it in before sending to Linus to avoid this in future). Dave.
[Intel-gfx] [PATCH 2/2] drm/i915/uncore: constify the register vtables. (v2)
From: Dave Airlie
This reworks the uncore function vtable so that it's constant.
v2: fixup selftest mocking.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/intel_uncore.c | 133 +++
drivers/gpu/drm/i915/intel_uncore.h | 8 +-
drivers/gpu/drm/i915/selftests/mock_uncore.c | 9 +-
3 files changed, 89 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 8652e4221404..e0e7f133f2b9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1737,32 +1737,24 @@ __vgpu_write(8)
__vgpu_write(16)
__vgpu_write(32)
-#define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
-do { \
- (uncore)->funcs.mmio_writeb = x##_write8; \
- (uncore)->funcs.mmio_writew = x##_write16; \
- (uncore)->funcs.mmio_writel = x##_write32; \
-} while (0)
-
-#define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \
-do { \
- (uncore)->funcs.mmio_readb = x##_read8; \
- (uncore)->funcs.mmio_readw = x##_read16; \
- (uncore)->funcs.mmio_readl = x##_read32; \
- (uncore)->funcs.mmio_readq = x##_read64; \
-} while (0)
-
-#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
-do { \
- ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \
- (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
-} while (0)
-
-#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
-do { \
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \
- (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
-} while (0)
+#define MMIO_RAW_WRITE_VFUNCS(x) \
+ .mmio_writeb = x##_write8, \
+ .mmio_writew = x##_write16, \
+ .mmio_writel = x##_write32
+
+#define MMIO_RAW_READ_VFUNCS(x) \
+ .mmio_readb = x##_read8, \
+ .mmio_readw = x##_read16, \
+ .mmio_readl = x##_read32, \
+ .mmio_readq = x##_read64
+
+#define MMIO_WRITE_FW_VFUNCS(x)\
+ MMIO_RAW_WRITE_VFUNCS(x), \
+ .write_fw_domains = x##_reg_write_fw_domains
+
+#define MMIO_READ_FW_VFUNCS(x) \
+ MMIO_RAW_READ_VFUNCS(x),\
+ .read_fw_domains = x##_reg_read_fw_domains
static int __fw_domain_init(struct intel_uncore *uncore,
enum forcewake_domain_id domain_id,
@@ -2067,22 +2059,64 @@ void intel_uncore_init_early(struct intel_uncore
*uncore,
uncore->debug = >mmio_debug;
}
+static const struct intel_uncore_funcs vgpu_funcs = {
+ MMIO_RAW_WRITE_VFUNCS(vgpu),
+ MMIO_RAW_READ_VFUNCS(vgpu),
+};
+
+static const struct intel_uncore_funcs gen5_funcs = {
+ MMIO_RAW_WRITE_VFUNCS(gen5),
+ MMIO_RAW_READ_VFUNCS(gen5),
+};
+
+static const struct intel_uncore_funcs gen2_funcs = {
+ MMIO_RAW_WRITE_VFUNCS(gen2),
+ MMIO_RAW_READ_VFUNCS(gen2),
+};
+
static void uncore_raw_init(struct intel_uncore *uncore)
{
GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
if (intel_vgpu_active(uncore->i915)) {
- ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu);
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu);
+ uncore->funcs = _funcs;
} else if (GRAPHICS_VER(uncore->i915) == 5) {
- ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
+ uncore->funcs = _funcs;
} else {
- ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2);
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2);
+ uncore->funcs = _funcs;
}
}
+static const struct intel_uncore_funcs gen12_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen12_fwtable),
+ MMIO_READ_FW_VFUNCS(gen11_fwtable)
+};
+
+static const struct intel_uncore_funcs gen11_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen11_fwtable),
+ MMIO_READ_FW_VFUNCS(gen11_fwtable)
+};
+
+static const struct intel_uncore_funcs fwtable_funcs = {
+ MMIO_WRITE_FW_VFUNCS(fwtable),
+ MMIO_READ_FW_VFUNCS(fwtable)
+};
+
+static const struct intel_uncore_funcs gen8_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen8),
+ MMIO_READ_FW_VFUNCS(gen6)
+};
+
+static const struct intel_uncore_funcs vlv_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen6),
+ MMIO_READ_FW_VFUNCS(fwtable)
+};
+
+static const struct intel_uncore_funcs gen6_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen6),
+ MMIO_READ_FW_VFUNCS(gen6)
+};
+
static int uncore_forcewake_init(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore->i915;
@@ -2097,38 +2131,29 @@ static int uncore_forcewake_init(struct intel_uncore
*uncore)
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
- ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
- ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
+ uncore->funcs = _funcs;
}
[Intel-gfx] [PATCH 1/2] drm/i915/uncore: split the fw get function into separate vfunc
From: Dave Airlie
constify it while here. drop the put function since it was never
overloaded and always has done the same thing, no point in
indirecting it for show.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/intel_uncore.c | 70 -
drivers/gpu/drm/i915/intel_uncore.h | 7 +--
2 files changed, 43 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index f9767054dbdf..8652e4221404 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -36,6 +36,12 @@
#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
+static void
+fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
+{
+ uncore->fw_get_funcs->force_wake_get(uncore, fw_domains);
+}
+
void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
{
@@ -248,7 +254,7 @@ fw_domain_put(const struct intel_uncore_forcewake_domain *d)
}
static void
-fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
+fw_domains_get_normal(struct intel_uncore *uncore, enum forcewake_domains
fw_domains)
{
struct intel_uncore_forcewake_domain *d;
unsigned int tmp;
@@ -396,7 +402,7 @@ intel_uncore_fw_release_timer(struct hrtimer *timer)
GEM_BUG_ON(!domain->wake_count);
if (--domain->wake_count == 0)
- uncore->funcs.force_wake_put(uncore, domain->mask);
+ fw_domains_put(uncore, domain->mask);
spin_unlock_irqrestore(>lock, irqflags);
@@ -454,7 +460,7 @@ intel_uncore_forcewake_reset(struct intel_uncore *uncore)
fw = uncore->fw_domains_active;
if (fw)
- uncore->funcs.force_wake_put(uncore, fw);
+ fw_domains_put(uncore, fw);
fw_domains_reset(uncore, uncore->fw_domains);
assert_forcewakes_inactive(uncore);
@@ -562,7 +568,7 @@ static void forcewake_early_sanitize(struct intel_uncore
*uncore,
intel_uncore_forcewake_reset(uncore);
if (restore_forcewake) {
spin_lock_irq(>lock);
- uncore->funcs.force_wake_get(uncore, restore_forcewake);
+ fw_domains_get(uncore, restore_forcewake);
if (intel_uncore_has_fifo(uncore))
uncore->fifo_count = fifo_free_entries(uncore);
@@ -623,7 +629,7 @@ static void __intel_uncore_forcewake_get(struct
intel_uncore *uncore,
}
if (fw_domains)
- uncore->funcs.force_wake_get(uncore, fw_domains);
+ fw_domains_get(uncore, fw_domains);
}
/**
@@ -644,7 +650,7 @@ void intel_uncore_forcewake_get(struct intel_uncore *uncore,
{
unsigned long irqflags;
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
assert_rpm_wakelock_held(uncore->rpm);
@@ -711,7 +717,7 @@ void intel_uncore_forcewake_get__locked(struct intel_uncore
*uncore,
{
lockdep_assert_held(>lock);
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
__intel_uncore_forcewake_get(uncore, fw_domains);
@@ -733,7 +739,7 @@ static void __intel_uncore_forcewake_put(struct
intel_uncore *uncore,
continue;
}
- uncore->funcs.force_wake_put(uncore, domain->mask);
+ fw_domains_put(uncore, domain->mask);
}
}
@@ -750,7 +756,7 @@ void intel_uncore_forcewake_put(struct intel_uncore *uncore,
{
unsigned long irqflags;
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
spin_lock_irqsave(>lock, irqflags);
@@ -769,7 +775,7 @@ void intel_uncore_forcewake_flush(struct intel_uncore
*uncore,
struct intel_uncore_forcewake_domain *domain;
unsigned int tmp;
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
fw_domains &= uncore->fw_domains;
@@ -793,7 +799,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore
*uncore,
{
lockdep_assert_held(>lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
__intel_uncore_forcewake_put(uncore, fw_domains);
@@ -801,7 +807,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore
*uncore,
void assert_forcewakes_inactive(struct intel_uncore *uncore)
{
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
drm_WARN(>i915->drm, uncore->fw_domains_active,
@@ -818,7 +824,7 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
return;
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
[Intel-gfx] [PATCH 0/2] i915/uncore: constify the uncore vtables.
static const vtables are more secure than writeable function pointers. These two patches cleanup the uncore vtable to use static const tables. v2: rebased onto drm-tip v3: fix selftests build failure. Dave.
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/4] drm/i915: rename debugfs_gt files
== Series Details ==
Series: series starting with [1/4] drm/i915: rename debugfs_gt files
URL : https://patchwork.freedesktop.org/series/94489/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10565_full -> Patchwork_20993_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20993_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20993_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20993_full:
### IGT changes ###
Possible regressions
* igt@gem_exec_endless@dispatch@vcs1:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-tglb7/igt@gem_exec_endless@dispa...@vcs1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/shard-tglb8/igt@gem_exec_endless@dispa...@vcs1.html
* igt@kms_atomic@plane-cursor-legacy:
- shard-iclb: [PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-iclb4/igt@kms_ato...@plane-cursor-legacy.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/shard-iclb2/igt@kms_ato...@plane-cursor-legacy.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_eio@hibernate:
- {shard-rkl}:[TIMEOUT][5] ([i915#3811]) -> [FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-5/igt@gem_...@hibernate.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/shard-rkl-2/igt@gem_...@hibernate.html
* igt@gem_flink_race@flink_close:
- {shard-rkl}:[PASS][7] -> [FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-6/igt@gem_flink_race@flink_close.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/shard-rkl-2/igt@gem_flink_race@flink_close.html
Known issues
Here are the changes found in Patchwork_20993_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_create@create-massive:
- shard-apl: NOTRUN -> [DMESG-WARN][9] ([i915#3002])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/shard-apl6/igt@gem_cre...@create-massive.html
* igt@gem_ctx_persistence@smoketest:
- shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1099])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/shard-snb5/igt@gem_ctx_persiste...@smoketest.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-iclb: [PASS][11] -> [TIMEOUT][12] ([i915#3070])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-iclb4/igt@gem_...@in-flight-contexts-10ms.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/shard-iclb3/igt@gem_...@in-flight-contexts-10ms.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar
issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-tglb3/igt@gem_exec_fair@basic-p...@vcs1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/shard-tglb3/igt@gem_exec_fair@basic-p...@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][15] -> [FAIL][16] ([i915#2842])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/shard-kbl2/igt@gem_exec_fair@basic-p...@vecs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-snb: NOTRUN -> [SKIP][17] ([fdo#109271]) +250 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/shard-snb7/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html
* igt@gem_exec_gttfill@all:
- shard-glk: [PASS][18] -> [DMESG-WARN][19] ([i915#118] /
[i915#95])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-glk6/igt@gem_exec_gttf...@all.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/shard-glk4/igt@gem_exec_gttf...@all.html
* igt@gem_mmap_gtt@cpuset-medium-copy:
- shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#1982])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-skl6/igt@gem_mmap_...@cpuset-medium-copy.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/shard-skl6/igt@gem_mmap_...@cpuset-medium-copy.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-glk: NOTRUN -> [SKIP][22] ([fdo#109271]) +3 similar
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/uncore: split the fw get function into separate vfunc
== Series Details ==
Series: series starting with [1/2] drm/i915/uncore: split the fw get function
into separate vfunc
URL : https://patchwork.freedesktop.org/series/94495/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/intel_uncore.o
In file included from drivers/gpu/drm/i915/intel_uncore.c:2605:
drivers/gpu/drm/i915/selftests/mock_uncore.c: In function ‘mock_uncore_init’:
drivers/gpu/drm/i915/selftests/mock_uncore.c:47:2: error: implicit declaration
of function ‘ASSIGN_RAW_WRITE_MMIO_VFUNCS’; did you mean
‘MMIO_RAW_WRITE_VFUNCS’? [-Werror=implicit-function-declaration]
ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, nop);
^~~~
MMIO_RAW_WRITE_VFUNCS
drivers/gpu/drm/i915/selftests/mock_uncore.c:47:39: error: ‘nop’ undeclared
(first use in this function); did you mean ‘node’?
ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, nop);
^~~
node
drivers/gpu/drm/i915/selftests/mock_uncore.c:47:39: note: each undeclared
identifier is reported only once for each function it appears in
drivers/gpu/drm/i915/selftests/mock_uncore.c:48:2: error: implicit declaration
of function ‘ASSIGN_RAW_READ_MMIO_VFUNCS’; did you mean ‘MMIO_RAW_READ_VFUNCS’?
[-Werror=implicit-function-declaration]
ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, nop);
^~~
MMIO_RAW_READ_VFUNCS
At top level:
drivers/gpu/drm/i915/selftests/mock_uncore.c:36:1: error: ‘nop_read64’ defined
but not used [-Werror=unused-function]
nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return
0; }
^~~~
drivers/gpu/drm/i915/selftests/mock_uncore.c:36:1: note: in definition of macro
‘__nop_read’
nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return
0; }
^~~~
drivers/gpu/drm/i915/selftests/mock_uncore.c:36:1: error: ‘nop_read32’ defined
but not used [-Werror=unused-function]
nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return
0; }
^~~~
drivers/gpu/drm/i915/selftests/mock_uncore.c:36:1: note: in definition of macro
‘__nop_read’
nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return
0; }
^~~~
drivers/gpu/drm/i915/selftests/mock_uncore.c:36:1: error: ‘nop_read16’ defined
but not used [-Werror=unused-function]
nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return
0; }
^~~~
drivers/gpu/drm/i915/selftests/mock_uncore.c:36:1: note: in definition of macro
‘__nop_read’
nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return
0; }
^~~~
drivers/gpu/drm/i915/selftests/mock_uncore.c:36:1: error: ‘nop_read8’ defined
but not used [-Werror=unused-function]
nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return
0; }
^~~~
drivers/gpu/drm/i915/selftests/mock_uncore.c:36:1: note: in definition of macro
‘__nop_read’
nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return
0; }
^~~~
drivers/gpu/drm/i915/selftests/mock_uncore.c:29:1: error: ‘nop_write32’ defined
but not used [-Werror=unused-function]
nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool
trace) { }
^
drivers/gpu/drm/i915/selftests/mock_uncore.c:29:1: note: in definition of macro
‘__nop_write’
nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool
trace) { }
^
drivers/gpu/drm/i915/selftests/mock_uncore.c:29:1: error: ‘nop_write16’ defined
but not used [-Werror=unused-function]
nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool
trace) { }
^
drivers/gpu/drm/i915/selftests/mock_uncore.c:29:1: note: in definition of macro
‘__nop_write’
nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool
trace) { }
^
drivers/gpu/drm/i915/selftests/mock_uncore.c:29:1: error: ‘nop_write8’ defined
but not used [-Werror=unused-function]
nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool
trace) { }
^
drivers/gpu/drm/i915/selftests/mock_uncore.c:29:1: note: in definition of macro
‘__nop_write’
nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool
trace) { }
^
cc1: all warnings being treated as errors
scripts/Makefile.build:271: recipe for target
'drivers/gpu/drm/i915/intel_uncore.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_uncore.o] Error 1
scripts/Makefile.build:514: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:514: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:514: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1851: recipe for target 'drivers' failed
make: *** [drivers] Error 2
[Intel-gfx] [PATCH 2/2] drm/i915/uncore: constify the register vtables.
From: Dave Airlie
This reworks the uncore function vtable so that it's constant.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/intel_uncore.c | 133 +---
drivers/gpu/drm/i915/intel_uncore.h | 8 +-
2 files changed, 83 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 8652e4221404..e0e7f133f2b9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1737,32 +1737,24 @@ __vgpu_write(8)
__vgpu_write(16)
__vgpu_write(32)
-#define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
-do { \
- (uncore)->funcs.mmio_writeb = x##_write8; \
- (uncore)->funcs.mmio_writew = x##_write16; \
- (uncore)->funcs.mmio_writel = x##_write32; \
-} while (0)
-
-#define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \
-do { \
- (uncore)->funcs.mmio_readb = x##_read8; \
- (uncore)->funcs.mmio_readw = x##_read16; \
- (uncore)->funcs.mmio_readl = x##_read32; \
- (uncore)->funcs.mmio_readq = x##_read64; \
-} while (0)
-
-#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
-do { \
- ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \
- (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
-} while (0)
-
-#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
-do { \
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \
- (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
-} while (0)
+#define MMIO_RAW_WRITE_VFUNCS(x) \
+ .mmio_writeb = x##_write8, \
+ .mmio_writew = x##_write16, \
+ .mmio_writel = x##_write32
+
+#define MMIO_RAW_READ_VFUNCS(x) \
+ .mmio_readb = x##_read8, \
+ .mmio_readw = x##_read16, \
+ .mmio_readl = x##_read32, \
+ .mmio_readq = x##_read64
+
+#define MMIO_WRITE_FW_VFUNCS(x)\
+ MMIO_RAW_WRITE_VFUNCS(x), \
+ .write_fw_domains = x##_reg_write_fw_domains
+
+#define MMIO_READ_FW_VFUNCS(x) \
+ MMIO_RAW_READ_VFUNCS(x),\
+ .read_fw_domains = x##_reg_read_fw_domains
static int __fw_domain_init(struct intel_uncore *uncore,
enum forcewake_domain_id domain_id,
@@ -2067,22 +2059,64 @@ void intel_uncore_init_early(struct intel_uncore
*uncore,
uncore->debug = >mmio_debug;
}
+static const struct intel_uncore_funcs vgpu_funcs = {
+ MMIO_RAW_WRITE_VFUNCS(vgpu),
+ MMIO_RAW_READ_VFUNCS(vgpu),
+};
+
+static const struct intel_uncore_funcs gen5_funcs = {
+ MMIO_RAW_WRITE_VFUNCS(gen5),
+ MMIO_RAW_READ_VFUNCS(gen5),
+};
+
+static const struct intel_uncore_funcs gen2_funcs = {
+ MMIO_RAW_WRITE_VFUNCS(gen2),
+ MMIO_RAW_READ_VFUNCS(gen2),
+};
+
static void uncore_raw_init(struct intel_uncore *uncore)
{
GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
if (intel_vgpu_active(uncore->i915)) {
- ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu);
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu);
+ uncore->funcs = _funcs;
} else if (GRAPHICS_VER(uncore->i915) == 5) {
- ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
+ uncore->funcs = _funcs;
} else {
- ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2);
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2);
+ uncore->funcs = _funcs;
}
}
+static const struct intel_uncore_funcs gen12_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen12_fwtable),
+ MMIO_READ_FW_VFUNCS(gen11_fwtable)
+};
+
+static const struct intel_uncore_funcs gen11_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen11_fwtable),
+ MMIO_READ_FW_VFUNCS(gen11_fwtable)
+};
+
+static const struct intel_uncore_funcs fwtable_funcs = {
+ MMIO_WRITE_FW_VFUNCS(fwtable),
+ MMIO_READ_FW_VFUNCS(fwtable)
+};
+
+static const struct intel_uncore_funcs gen8_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen8),
+ MMIO_READ_FW_VFUNCS(gen6)
+};
+
+static const struct intel_uncore_funcs vlv_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen6),
+ MMIO_READ_FW_VFUNCS(fwtable)
+};
+
+static const struct intel_uncore_funcs gen6_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen6),
+ MMIO_READ_FW_VFUNCS(gen6)
+};
+
static int uncore_forcewake_init(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore->i915;
@@ -2097,38 +2131,29 @@ static int uncore_forcewake_init(struct intel_uncore
*uncore)
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
- ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
- ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
+ uncore->funcs = _funcs;
} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
[Intel-gfx] i915/uncore: constify the uncore vtables. (v2)
static const vtables are more secure than writeable function pointers. These two patches cleanup the uncore vtable to use static const tables. These are based on drm-tip, and should apply to the gt tree cleanly. Dave.
[Intel-gfx] [PATCH 1/2] drm/i915/uncore: split the fw get function into separate vfunc
From: Dave Airlie
constify it while here. drop the put function since it was never
overloaded and always has done the same thing, no point in
indirecting it for show.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/intel_uncore.c | 70 -
drivers/gpu/drm/i915/intel_uncore.h | 7 +--
2 files changed, 43 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index f9767054dbdf..8652e4221404 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -36,6 +36,12 @@
#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
+static void
+fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
+{
+ uncore->fw_get_funcs->force_wake_get(uncore, fw_domains);
+}
+
void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
{
@@ -248,7 +254,7 @@ fw_domain_put(const struct intel_uncore_forcewake_domain *d)
}
static void
-fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
+fw_domains_get_normal(struct intel_uncore *uncore, enum forcewake_domains
fw_domains)
{
struct intel_uncore_forcewake_domain *d;
unsigned int tmp;
@@ -396,7 +402,7 @@ intel_uncore_fw_release_timer(struct hrtimer *timer)
GEM_BUG_ON(!domain->wake_count);
if (--domain->wake_count == 0)
- uncore->funcs.force_wake_put(uncore, domain->mask);
+ fw_domains_put(uncore, domain->mask);
spin_unlock_irqrestore(>lock, irqflags);
@@ -454,7 +460,7 @@ intel_uncore_forcewake_reset(struct intel_uncore *uncore)
fw = uncore->fw_domains_active;
if (fw)
- uncore->funcs.force_wake_put(uncore, fw);
+ fw_domains_put(uncore, fw);
fw_domains_reset(uncore, uncore->fw_domains);
assert_forcewakes_inactive(uncore);
@@ -562,7 +568,7 @@ static void forcewake_early_sanitize(struct intel_uncore
*uncore,
intel_uncore_forcewake_reset(uncore);
if (restore_forcewake) {
spin_lock_irq(>lock);
- uncore->funcs.force_wake_get(uncore, restore_forcewake);
+ fw_domains_get(uncore, restore_forcewake);
if (intel_uncore_has_fifo(uncore))
uncore->fifo_count = fifo_free_entries(uncore);
@@ -623,7 +629,7 @@ static void __intel_uncore_forcewake_get(struct
intel_uncore *uncore,
}
if (fw_domains)
- uncore->funcs.force_wake_get(uncore, fw_domains);
+ fw_domains_get(uncore, fw_domains);
}
/**
@@ -644,7 +650,7 @@ void intel_uncore_forcewake_get(struct intel_uncore *uncore,
{
unsigned long irqflags;
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
assert_rpm_wakelock_held(uncore->rpm);
@@ -711,7 +717,7 @@ void intel_uncore_forcewake_get__locked(struct intel_uncore
*uncore,
{
lockdep_assert_held(>lock);
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
__intel_uncore_forcewake_get(uncore, fw_domains);
@@ -733,7 +739,7 @@ static void __intel_uncore_forcewake_put(struct
intel_uncore *uncore,
continue;
}
- uncore->funcs.force_wake_put(uncore, domain->mask);
+ fw_domains_put(uncore, domain->mask);
}
}
@@ -750,7 +756,7 @@ void intel_uncore_forcewake_put(struct intel_uncore *uncore,
{
unsigned long irqflags;
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
spin_lock_irqsave(>lock, irqflags);
@@ -769,7 +775,7 @@ void intel_uncore_forcewake_flush(struct intel_uncore
*uncore,
struct intel_uncore_forcewake_domain *domain;
unsigned int tmp;
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
fw_domains &= uncore->fw_domains;
@@ -793,7 +799,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore
*uncore,
{
lockdep_assert_held(>lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
__intel_uncore_forcewake_put(uncore, fw_domains);
@@ -801,7 +807,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore
*uncore,
void assert_forcewakes_inactive(struct intel_uncore *uncore)
{
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
drm_WARN(>i915->drm, uncore->fw_domains_active,
@@ -818,7 +824,7 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
return;
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
[Intel-gfx] ✗ Fi.CI.BAT: failure for i915/display: split and constify vtable (rev3)
== Series Details ==
Series: i915/display: split and constify vtable (rev3)
URL : https://patchwork.freedesktop.org/series/94459/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10565 -> Patchwork_20995
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20995 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20995, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_20995:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- fi-rkl-11600: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-rkl-11600/igt@run...@aborted.html
- fi-tgl-y: NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-tgl-y/igt@run...@aborted.html
- fi-bwr-2160:NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-bwr-2160/igt@run...@aborted.html
- fi-rkl-guc: NOTRUN -> [FAIL][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-rkl-guc/igt@run...@aborted.html
- fi-tgl-1115g4: NOTRUN -> [FAIL][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-tgl-1115g4/igt@run...@aborted.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-tgl-dsi}: NOTRUN -> [FAIL][6]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-tgl-dsi/igt@run...@aborted.html
- {fi-jsl-1}: NOTRUN -> [FAIL][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-jsl-1/igt@run...@aborted.html
- {fi-ehl-2}: NOTRUN -> [FAIL][8]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-ehl-2/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_20995 that come from known issues:
### IGT changes ###
Issues hit
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][9] ([i915#2403])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-pnv-d510/igt@run...@aborted.html
- fi-cfl-8700k: NOTRUN -> [FAIL][10] ([i915#3363] / [k.org#202107] /
[k.org#202109])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-cfl-8700k/igt@run...@aborted.html
- fi-skl-6600u: NOTRUN -> [FAIL][11] ([i915#3363])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-skl-6600u/igt@run...@aborted.html
- fi-cfl-8109u: NOTRUN -> [FAIL][12] ([i915#3363] / [k.org#202107] /
[k.org#202109])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-cfl-8109u/igt@run...@aborted.html
- fi-icl-u2: NOTRUN -> [FAIL][13] ([i915#1569] / [i915#3363])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-icl-u2/igt@run...@aborted.html
- fi-glk-dsi: NOTRUN -> [FAIL][14] ([i915#3363] / [k.org#202321])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-8809g: NOTRUN -> [FAIL][15] ([i915#1569] / [i915#192] /
[i915#193] / [i915#194] / [i915#3363])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-kbl-8809g/igt@run...@aborted.html
- fi-kbl-r: NOTRUN -> [FAIL][16] ([i915#1569] / [i915#192] /
[i915#193] / [i915#194] / [i915#3363])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-kbl-r/igt@run...@aborted.html
- fi-kbl-soraka: NOTRUN -> [FAIL][17] ([i915#1569] / [i915#192] /
[i915#193] / [i915#194] / [i915#3363])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-kbl-soraka/igt@run...@aborted.html
- fi-kbl-guc: NOTRUN -> [FAIL][18] ([i915#1569] / [i915#192] /
[i915#193] / [i915#194] / [i915#3363])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-kbl-guc/igt@run...@aborted.html
- fi-cml-u2: NOTRUN -> [FAIL][19] ([i915#3363])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-cml-u2/igt@run...@aborted.html
- fi-bxt-dsi: NOTRUN -> [FAIL][20] ([i915#3363])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-bxt-dsi/igt@run...@aborted.html
- fi-cfl-guc: NOTRUN -> [FAIL][21] ([i915#3363] / [k.org#202107] /
[k.org#202109])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20995/fi-cfl-guc/igt@run...@aborted.html
- fi-icl-y: NOTRUN -> [FAIL][22] ([i915#1569])
[22]:
[Intel-gfx] ✗ Fi.CI.DOCS: warning for i915/display: split and constify vtable (rev3)
== Series Details == Series: i915/display: split and constify vtable (rev3) URL : https://patchwork.freedesktop.org/series/94459/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_display.c:164: warning: Excess function parameter 'crtc' description in 'intel_update_watermarks'
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915/display: split and constify vtable (rev3)
== Series Details ==
Series: i915/display: split and constify vtable (rev3)
URL : https://patchwork.freedesktop.org/series/94459/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a76b5174980a drm/i915/pm: drop get_fifo_size vfunc.
a40a1ce2eb04 drm/i915: make update_wm take a dev_priv.
c888ddf45e84 drm/i915/wm: provide wrappers around watermark vfuncs calls
-:9: WARNING:TYPO_SPELLING: 'existance' may be misspelled - perhaps 'existence'?
#9:
One thing to note is that the code checks the existance of some
^
-:24: CHECK:LINE_SPACING: Please don't use multiple blank lines
#24: FILE: drivers/gpu/drm/i915/display/intel_display.c:129:
+
-:68: WARNING:LINE_SPACING: Missing a blank line after declarations
#68: FILE: drivers/gpu/drm/i915/display/intel_display.c:173:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.compute_pipe_wm)
-:77: WARNING:LINE_SPACING: Missing a blank line after declarations
#77: FILE: drivers/gpu/drm/i915/display/intel_display.c:182:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (drm_WARN_ON(_priv->drm,
-:89: WARNING:LINE_SPACING: Missing a blank line after declarations
#89: FILE: drivers/gpu/drm/i915/display/intel_display.c:194:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.initial_watermarks) {
-:100: WARNING:LINE_SPACING: Missing a blank line after declarations
#100: FILE: drivers/gpu/drm/i915/display/intel_display.c:205:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.atomic_update_watermarks)
-:108: WARNING:LINE_SPACING: Missing a blank line after declarations
#108: FILE: drivers/gpu/drm/i915/display/intel_display.c:213:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.optimize_watermarks)
-:115: WARNING:LINE_SPACING: Missing a blank line after declarations
#115: FILE: drivers/gpu/drm/i915/display/intel_display.c:220:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.compute_global_watermarks)
-:129: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional
statements (16, 20)
#129: FILE: drivers/gpu/drm/i915/display/intel_display.c:2626:
+ if (!intel_initial_watermarks(state, crtc))
+ if (new_crtc_state->update_wm_pre)
-:130: WARNING:TABSTOP: Statements should start on a tabstop
#130: FILE: drivers/gpu/drm/i915/display/intel_display.c:2627:
+ if (new_crtc_state->update_wm_pre)
-:171: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional
statements (8, 12)
#171: FILE: drivers/gpu/drm/i915/display/intel_display.c:3670:
+ if (!intel_initial_watermarks(state, crtc))
+ intel_update_watermarks(dev_priv);
total: 0 errors, 10 warnings, 1 checks, 319 lines checked
a3202c80554b drm/i915: add wrappers around cdclk vtable funcs.
-:30: WARNING:LINE_SPACING: Missing a blank line after declarations
#30: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:71:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ return dev_priv->display.bw_calc_min_cdclk(state);
total: 0 errors, 1 warnings, 0 checks, 127 lines checked
19bf5164731c drm/i915/display: add intel_fdi_link_train wrapper.
a794c1c9815e drm/i915: split clock gating init from display vtable
34a4acfe78be drm/i915: split watermark vfuncs from display vtable.
31adf6b0768e drm/i915: split color functions from display vtable
b702ff45c5cf drm/i915: split audio functions from display vtable
c572b0d86bf1 drm/i915: split cdclk functions from display vtable.
746f0aa2ec41 drm/i915: split irq hotplug function from display vtable
bffd1d2d4374 drm/i915: split fdi link training from display vtable.
69f8232ae750 drm/i915: split the dpll clock compute out from display vtable.
acb8f8b85236 drm/i915: constify fdi link training vtable
e083e0f99097 drm/i915: constify hotplug function vtable.
7e992c904e0f drm/i915: constify color function vtable.
-:196: CHECK:BRACES: Unbalanced braces around else statement
#196: FILE: drivers/gpu/drm/i915/display/intel_color.c:2194:
+ } else
total: 0 errors, 0 warnings, 1 checks, 187 lines checked
aae8c1731860 drm/i915: constify the audio function vtable
7dbce2d6cbf9 drm/i915: constify the dpll clock vtable
7b51b6fedb49 drm/i915: constify the cdclk vtable
c1efc73c0417 drm/i915: drop unused function ptr and comments.
70f608995c29 drm/i915: constify display function vtable
90e8b85e828a drm/i915: constify clock gating init vtable.
23ee99724f55 drm/i915: constify display wm vtable
[Intel-gfx] ✗ Fi.CI.BAT: failure for i915/display: split and constify vtable (rev2)
== Series Details ==
Series: i915/display: split and constify vtable (rev2)
URL : https://patchwork.freedesktop.org/series/94459/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10565 -> Patchwork_20994
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20994 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20994, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_20994:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- fi-rkl-11600: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-rkl-11600/igt@run...@aborted.html
- fi-tgl-y: NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-tgl-y/igt@run...@aborted.html
- fi-bwr-2160:NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-bwr-2160/igt@run...@aborted.html
- fi-rkl-guc: NOTRUN -> [FAIL][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-rkl-guc/igt@run...@aborted.html
- fi-tgl-1115g4: NOTRUN -> [FAIL][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-tgl-1115g4/igt@run...@aborted.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-tgl-dsi}: NOTRUN -> [FAIL][6]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-tgl-dsi/igt@run...@aborted.html
- {fi-jsl-1}: NOTRUN -> [FAIL][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-jsl-1/igt@run...@aborted.html
- {fi-ehl-2}: NOTRUN -> [FAIL][8]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-ehl-2/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_20994 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][9] -> [INCOMPLETE][10] ([i915#3921])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-bdw-5557u: NOTRUN -> [SKIP][11] ([fdo#109271]) +3 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-bdw-5557u/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][13] ([i915#2403])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-pnv-d510/igt@run...@aborted.html
- fi-cfl-8700k: NOTRUN -> [FAIL][14] ([i915#3363] / [k.org#202107] /
[k.org#202109])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-cfl-8700k/igt@run...@aborted.html
- fi-skl-6600u: NOTRUN -> [FAIL][15] ([i915#3363])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-skl-6600u/igt@run...@aborted.html
- fi-cfl-8109u: NOTRUN -> [FAIL][16] ([i915#3363] / [k.org#202107] /
[k.org#202109])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-cfl-8109u/igt@run...@aborted.html
- fi-icl-u2: NOTRUN -> [FAIL][17] ([i915#1569] / [i915#3363])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-icl-u2/igt@run...@aborted.html
- fi-glk-dsi: NOTRUN -> [FAIL][18] ([i915#3363] / [k.org#202321])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-glk-dsi/igt@run...@aborted.html
- fi-kbl-8809g: NOTRUN -> [FAIL][19] ([i915#1569] / [i915#192] /
[i915#193] / [i915#194] / [i915#3363])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-kbl-8809g/igt@run...@aborted.html
- fi-kbl-r: NOTRUN -> [FAIL][20] ([i915#1569] / [i915#192] /
[i915#193] / [i915#194] / [i915#3363])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20994/fi-kbl-r/igt@run...@aborted.html
- fi-kbl-soraka: NOTRUN -> [FAIL][21] ([i915#1569] / [i915#192] /
[i915#193] / [i915#194] / [i915#3363])
[21]:
[Intel-gfx] [PATCH 23/23] drm/i915: constify display wm vtable
From: Dave Airlie
Use a nop table for the cases where CxSR doesn't init properly.
v2: use a nop table (Jani)
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 34 -
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 80 ++--
3 files changed, 75 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8b9727d84435..502e9ac70de1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -162,16 +162,16 @@ static void intel_modeset_setup_hw_state(struct
drm_device *dev,
*/
static void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
- if (dev_priv->wm_disp.update_wm)
- dev_priv->wm_disp.update_wm(dev_priv);
+ if (dev_priv->wm_disp->update_wm)
+ dev_priv->wm_disp->update_wm(dev_priv);
}
static int intel_compute_pipe_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.compute_pipe_wm)
- return dev_priv->wm_disp.compute_pipe_wm(state, crtc);
+ if (dev_priv->wm_disp->compute_pipe_wm)
+ return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
return 0;
}
@@ -180,10 +180,10 @@ static int intel_compute_intermediate_wm(struct
intel_atomic_state *state,
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
if (drm_WARN_ON(_priv->drm,
- !dev_priv->wm_disp.compute_pipe_wm))
+ !dev_priv->wm_disp->compute_pipe_wm))
return 0;
- if (dev_priv->wm_disp.compute_pipe_wm)
- return dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
+ if (dev_priv->wm_disp->compute_pipe_wm)
+ return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
return 0;
}
@@ -191,8 +191,8 @@ static bool intel_initial_watermarks(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.initial_watermarks) {
- dev_priv->wm_disp.initial_watermarks(state, crtc);
+ if (dev_priv->wm_disp->initial_watermarks) {
+ dev_priv->wm_disp->initial_watermarks(state, crtc);
return true;
}
return false;
@@ -202,23 +202,23 @@ static void intel_atomic_update_watermarks(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.atomic_update_watermarks)
- dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
+ if (dev_priv->wm_disp->atomic_update_watermarks)
+ dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
}
static void intel_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.optimize_watermarks)
- dev_priv->wm_disp.optimize_watermarks(state, crtc);
+ if (dev_priv->wm_disp->optimize_watermarks)
+ dev_priv->wm_disp->optimize_watermarks(state, crtc);
}
static void intel_compute_global_watermarks(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.compute_global_watermarks)
- dev_priv->wm_disp.compute_global_watermarks(state);
+ if (dev_priv->wm_disp->compute_global_watermarks)
+ dev_priv->wm_disp->compute_global_watermarks(state);
}
/* returns HPLL frequency in kHz */
@@ -3735,7 +3735,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state
*state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
- if (!dev_priv->wm_disp.initial_watermarks)
+ if (!dev_priv->wm_disp->initial_watermarks)
intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
@@ -11409,7 +11409,7 @@ static void sanitize_watermarks(struct drm_i915_private
*dev_priv)
int i;
/* Only supported on platforms that use atomic watermark design */
- if (!dev_priv->wm_disp.optimize_watermarks)
+ if (!dev_priv->wm_disp->optimize_watermarks)
return;
state = drm_atomic_state_alloc(_priv->drm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fc7466bbc445..b9fa6bf4835d 100644
---
[Intel-gfx] [PATCH 22/23] drm/i915: constify clock gating init vtable.
From: Dave Airlie
I used a macro to avoid making any really silly mistakes here.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 78 +++--
2 files changed, 55 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5bbdd3b06e6d..fc7466bbc445 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -975,7 +975,7 @@ struct drm_i915_private {
struct workqueue_struct *flip_wq;
/* pm private clock gating functions */
- struct drm_i915_clock_gating_funcs clock_gating_funcs;
+ const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
/* pm display functions */
struct drm_i915_wm_disp_funcs wm_disp;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 826216a115fd..0a5c1e3c798b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating(struct drm_i915_private *dev_priv)
{
- dev_priv->clock_gating_funcs.init_clock_gating(dev_priv);
+ dev_priv->clock_gating_funcs->init_clock_gating(dev_priv);
}
void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7886,6 +7886,36 @@ static void nop_init_clock_gating(struct
drm_i915_private *dev_priv)
"No clock gating settings or workarounds applied.\n");
}
+#define CG_FUNCS(platform) \
+static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs
= { \
+ .init_clock_gating = platform##_init_clock_gating, \
+}
+
+CG_FUNCS(adlp);
+CG_FUNCS(dg1);
+CG_FUNCS(gen12lp);
+CG_FUNCS(icl);
+CG_FUNCS(cfl);
+CG_FUNCS(skl);
+CG_FUNCS(kbl);
+CG_FUNCS(bxt);
+CG_FUNCS(glk);
+CG_FUNCS(bdw);
+CG_FUNCS(chv);
+CG_FUNCS(hsw);
+CG_FUNCS(ivb);
+CG_FUNCS(vlv);
+CG_FUNCS(gen6);
+CG_FUNCS(ilk);
+CG_FUNCS(g4x);
+CG_FUNCS(i965gm);
+CG_FUNCS(i965g);
+CG_FUNCS(gen3);
+CG_FUNCS(i85x);
+CG_FUNCS(i830);
+CG_FUNCS(nop);
+#undef CG_FUNCS
+
/**
* intel_init_clock_gating_hooks - setup the clock gating hooks
* @dev_priv: device private
@@ -7898,52 +7928,52 @@ static void nop_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_ALDERLAKE_P(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
adlp_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_DG1(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
dg1_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 12)
- dev_priv->clock_gating_funcs.init_clock_gating =
gen12lp_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 11)
- dev_priv->clock_gating_funcs.init_clock_gating =
icl_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
cfl_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_SKYLAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
skl_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_KABYLAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
kbl_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_BROXTON(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
bxt_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_GEMINILAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
glk_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_BROADWELL(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
bdw_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
chv_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_HASWELL(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
hsw_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_IVYBRIDGE(dev_priv))
-
[Intel-gfx] [PATCH 20/23] drm/i915: drop unused function ptr and comments.
From: Dave Airlie
There was some excess comments and an unused vtbl ptr.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_drv.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b2c63ed5b8fe..2e8e4db627e3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -409,13 +409,6 @@ struct drm_i915_display_funcs {
void (*crtc_disable)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*commit_modeset_enables)(struct intel_atomic_state *state);
- void (*commit_modeset_disables)(struct intel_atomic_state *state);
-
- /* clock updates for mode set */
- /* cursor updates */
- /* render clock increase/decrease */
- /* display clock increase/decrease */
- /* pll clock increase/decrease */
};
--
2.31.1
[Intel-gfx] [PATCH 21/23] drm/i915: constify display function vtable
From: Dave Airlie
Make nice clear tables instead of having things in two places.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 81
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 52 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 2e672b988343..8b9727d84435 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3789,7 +3789,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc
*crtc,
drm_WARN_ON(_priv->drm, IS_ERR(temp_crtc_state) || ret);
- dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
+ dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
drm_atomic_state_put(state);
@@ -5994,7 +5994,7 @@ static bool intel_crtc_get_pipe_config(struct
intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- if (!i915->display.get_pipe_config(crtc, crtc_state))
+ if (!i915->display->get_pipe_config(crtc, crtc_state))
return false;
crtc_state->hw.active = true;
@@ -9802,7 +9802,7 @@ static void intel_enable_crtc(struct intel_atomic_state
*state,
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display.crtc_enable(state, crtc);
+ dev_priv->display->crtc_enable(state, crtc);
if (new_crtc_state->bigjoiner_slave)
return;
@@ -9890,7 +9890,7 @@ static void intel_old_crtc_state_disables(struct
intel_atomic_state *state,
*/
intel_crtc_disable_pipe_crc(crtc);
- dev_priv->display.crtc_disable(state, crtc);
+ dev_priv->display->crtc_disable(state, crtc);
crtc->active = false;
intel_fbc_disable(crtc);
intel_disable_shared_dpll(old_crtc_state);
@@ -10269,7 +10269,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
}
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
- dev_priv->display.commit_modeset_enables(state);
+ dev_priv->display->commit_modeset_enables(state);
if (state->modeset) {
intel_encoders_update_complete(state);
@@ -11272,6 +11272,46 @@ static const struct drm_mode_config_funcs
intel_mode_funcs = {
.atomic_state_free = intel_atomic_state_free,
};
+static const struct drm_i915_display_funcs skl_display_funcs = {
+ .get_pipe_config = hsw_get_pipe_config,
+ .crtc_enable = hsw_crtc_enable,
+ .crtc_disable = hsw_crtc_disable,
+ .commit_modeset_enables = skl_commit_modeset_enables,
+ .get_initial_plane_config = skl_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs ddi_display_funcs = {
+ .get_pipe_config = hsw_get_pipe_config,
+ .crtc_enable = hsw_crtc_enable,
+ .crtc_disable = hsw_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs pch_split_display_funcs = {
+ .get_pipe_config = ilk_get_pipe_config,
+ .crtc_enable = ilk_crtc_enable,
+ .crtc_disable = ilk_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs vlv_display_funcs = {
+ .get_pipe_config = i9xx_get_pipe_config,
+ .crtc_enable = valleyview_crtc_enable,
+ .crtc_disable = i9xx_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs i9xx_display_funcs = {
+ .get_pipe_config = i9xx_get_pipe_config,
+ .crtc_enable = i9xx_crtc_enable,
+ .crtc_disable = i9xx_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
/**
* intel_init_display_hooks - initialize the display modesetting hooks
* @dev_priv: device private
@@ -11287,38 +11327,19 @@ void intel_init_display_hooks(struct drm_i915_private
*dev_priv)
intel_dpll_init_clock_hook(dev_priv);
if (DISPLAY_VER(dev_priv) >= 9) {
- dev_priv->display.get_pipe_config = hsw_get_pipe_config;
- dev_priv->display.crtc_enable = hsw_crtc_enable;
- dev_priv->display.crtc_disable = hsw_crtc_disable;
+ dev_priv->display = _display_funcs;
} else if (HAS_DDI(dev_priv)) {
- dev_priv->display.get_pipe_config = hsw_get_pipe_config;
- dev_priv->display.crtc_enable =
[Intel-gfx] [PATCH 19/23] drm/i915: constify the cdclk vtable
From: Dave Airlie
This is a bit of a twisty one since each platform is slightly
different, so might take some more review care.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 300 ++---
drivers/gpu/drm/i915/i915_drv.h| 2 +-
2 files changed, 206 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 27a4a226aa49..f501c748458e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -62,32 +62,32 @@
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
- dev_priv->cdclk_funcs.get_cdclk(dev_priv, cdclk_config);
+ dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config);
}
int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- return dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
+ return dev_priv->cdclk_funcs->bw_calc_min_cdclk(state);
}
static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
+ dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe);
}
static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state
*cdclk_config)
{
- return dev_priv->cdclk_funcs.modeset_calc_cdclk(cdclk_config);
+ return dev_priv->cdclk_funcs->modeset_calc_cdclk(cdclk_config);
}
static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
int cdclk)
{
- return dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
+ return dev_priv->cdclk_funcs->calc_voltage_level(cdclk);
}
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
if (!intel_cdclk_changed(_priv->cdclk.hw, cdclk_config))
return;
- if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
+ if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
return;
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -2886,6 +2886,157 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static struct intel_cdclk_funcs tgl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs ehl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = ehl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs icl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = icl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs bxt_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = bxt_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs skl_cdclk_funcs = {
+ .get_cdclk = skl_get_cdclk,
+ .set_cdclk = skl_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = skl_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs bdw_cdclk_funcs = {
+ .get_cdclk = bdw_get_cdclk,
+ .set_cdclk = bdw_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bdw_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs chv_cdclk_funcs = {
+ .get_cdclk = vlv_get_cdclk,
+ .set_cdclk = chv_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs vlv_cdclk_funcs = {
+ .get_cdclk = vlv_get_cdclk,
+ .set_cdclk = vlv_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs hsw_cdclk_funcs = {
+ .get_cdclk = hsw_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk =
[Intel-gfx] [PATCH 17/23] drm/i915: constify the audio function vtable
From: Dave Airlie
Move the functions into read-only tables.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_audio.c | 43 ++
drivers/gpu/drm/i915/i915_drv.h| 2 +-
2 files changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index f539826c0424..0a6ad74d9173 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -848,10 +848,10 @@ void intel_audio_codec_enable(struct intel_encoder
*encoder,
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
- if (dev_priv->audio_funcs.audio_codec_enable)
- dev_priv->audio_funcs.audio_codec_enable(encoder,
-crtc_state,
-conn_state);
+ if (dev_priv->audio_funcs)
+ dev_priv->audio_funcs->audio_codec_enable(encoder,
+ crtc_state,
+ conn_state);
mutex_lock(_priv->av_mutex);
encoder->audio_connector = connector;
@@ -893,10 +893,10 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
- if (dev_priv->audio_funcs.audio_codec_disable)
- dev_priv->audio_funcs.audio_codec_disable(encoder,
- old_crtc_state,
- old_conn_state);
+ if (dev_priv->audio_funcs)
+ dev_priv->audio_funcs->audio_codec_disable(encoder,
+ old_crtc_state,
+ old_conn_state);
mutex_lock(_priv->av_mutex);
encoder->audio_connector = NULL;
@@ -915,6 +915,21 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
}
+static const struct intel_audio_funcs g4x_audio_funcs = {
+ .audio_codec_enable = g4x_audio_codec_enable,
+ .audio_codec_disable = g4x_audio_codec_disable,
+};
+
+static const struct intel_audio_funcs ilk_audio_funcs = {
+ .audio_codec_enable = ilk_audio_codec_enable,
+ .audio_codec_disable = ilk_audio_codec_disable,
+};
+
+static const struct intel_audio_funcs hsw_audio_funcs = {
+ .audio_codec_enable = hsw_audio_codec_enable,
+ .audio_codec_disable = hsw_audio_codec_disable,
+};
+
/**
* intel_init_audio_hooks - Set up chip specific audio hooks
* @dev_priv: device private
@@ -922,17 +937,13 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
{
if (IS_G4X(dev_priv)) {
- dev_priv->audio_funcs.audio_codec_enable =
g4x_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable =
g4x_audio_codec_disable;
+ dev_priv->audio_funcs = _audio_funcs;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- dev_priv->audio_funcs.audio_codec_enable =
ilk_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable =
ilk_audio_codec_disable;
+ dev_priv->audio_funcs = _audio_funcs;
} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->audio_funcs.audio_codec_enable =
hsw_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable =
hsw_audio_codec_disable;
+ dev_priv->audio_funcs = _audio_funcs;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->audio_funcs.audio_codec_enable =
ilk_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable =
ilk_audio_codec_disable;
+ dev_priv->audio_funcs = _audio_funcs;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 28cd816549b8..95f7a7a19a58 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1003,7 +1003,7 @@ struct drm_i915_private {
const struct intel_color_funcs *color_funcs;
/* Display internal audio functions */
- struct intel_audio_funcs audio_funcs;
+ const struct intel_audio_funcs *audio_funcs;
/* Display CDCLK functions */
struct intel_cdclk_funcs cdclk_funcs;
--
2.31.1
[Intel-gfx] [PATCH 18/23] drm/i915: constify the dpll clock vtable
From: Dave Airlie
Most the dpll vtable into read-only memory.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +--
drivers/gpu/drm/i915/display/intel_dpll.c| 48
drivers/gpu/drm/i915/i915_drv.h | 2 +-
3 files changed, 44 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 02a9e684c86b..2e672b988343 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6821,10 +6821,10 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
crtc_state->update_wm_post = true;
if (mode_changed && crtc_state->hw.enable &&
- dev_priv->dpll_funcs.crtc_compute_clock &&
+ dev_priv->dpll_funcs &&
!crtc_state->bigjoiner_slave &&
!drm_WARN_ON(_priv->drm, crtc_state->shared_dpll)) {
- ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
+ ret = dev_priv->dpll_funcs->crtc_compute_clock(crtc_state);
if (ret)
return ret;
}
@@ -8851,7 +8851,7 @@ static void intel_modeset_clear_plls(struct
intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
- if (!dev_priv->dpll_funcs.crtc_compute_clock)
+ if (!dev_priv->dpll_funcs)
return;
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 9326c7cbb05c..231b337df166 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1363,25 +1363,57 @@ static int i8xx_crtc_compute_clock(struct
intel_crtc_state *crtc_state)
return 0;
}
+static const struct intel_dpll_funcs hsw_dpll_funcs = {
+ .crtc_compute_clock = hsw_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs ilk_dpll_funcs = {
+ .crtc_compute_clock = ilk_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs chv_dpll_funcs = {
+ .crtc_compute_clock = chv_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs vlv_dpll_funcs = {
+ .crtc_compute_clock = vlv_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs g4x_dpll_funcs = {
+ .crtc_compute_clock = g4x_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs pnv_dpll_funcs = {
+ .crtc_compute_clock = pnv_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs i9xx_dpll_funcs = {
+ .crtc_compute_clock = i9xx_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs i8xx_dpll_funcs = {
+ .crtc_compute_clock = i8xx_crtc_compute_clock,
+};
+
void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
hsw_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (HAS_PCH_SPLIT(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
ilk_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
chv_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
vlv_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_G4X(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
g4x_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
pnv_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (DISPLAY_VER(dev_priv) != 2)
- dev_priv->dpll_funcs.crtc_compute_clock =
i9xx_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else
- dev_priv->dpll_funcs.crtc_compute_clock =
i8xx_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
}
static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 95f7a7a19a58..5ed624b9c3cc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -994,7 +994,7 @@ struct drm_i915_private {
const struct intel_fdi_funcs *fdi_funcs;
/* display pll funcs */
- struct intel_dpll_funcs dpll_funcs;
+ const struct intel_dpll_funcs *dpll_funcs;
/* Display functions */
struct drm_i915_display_funcs display;
--
2.31.1
[Intel-gfx] [PATCH 16/23] drm/i915: constify color function vtable.
From: Dave Airlie
This clarifies quite well what functions get used on what platforms
instead of having to decipher the old tree.
v2: fixed IVB mistake (Jani)
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_color.c | 138 ++---
drivers/gpu/drm/i915/i915_drv.h| 2 +-
2 files changed, 93 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index ed79075158dd..f5923f1c38bd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct
intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->color_funcs.load_luts(crtc_state);
+ dev_priv->color_funcs->load_luts(crtc_state);
}
void intel_color_commit(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->color_funcs.color_commit(crtc_state);
+ dev_priv->color_funcs->color_commit(crtc_state);
}
static bool intel_can_preload_luts(const struct intel_crtc_state
*new_crtc_state)
@@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- return dev_priv->color_funcs.color_check(crtc_state);
+ return dev_priv->color_funcs->color_check(crtc_state);
}
void intel_color_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (dev_priv->color_funcs.read_luts)
- dev_priv->color_funcs.read_luts(crtc_state);
+ if (dev_priv->color_funcs->read_luts)
+ dev_priv->color_funcs->read_luts(crtc_state);
}
static bool need_plane_update(struct intel_plane *plane,
@@ -2092,6 +2092,76 @@ static void icl_read_luts(struct intel_crtc_state
*crtc_state)
}
}
+static const struct intel_color_funcs chv_color_funcs = {
+ .color_check = chv_color_check,
+ .color_commit = i9xx_color_commit,
+ .load_luts = chv_load_luts,
+ .read_luts = chv_read_luts,
+};
+
+static const struct intel_color_funcs i965_color_funcs = {
+ .color_check = i9xx_color_check,
+ .color_commit = i9xx_color_commit,
+ .load_luts = i965_load_luts,
+ .read_luts = i965_read_luts,
+};
+
+static const struct intel_color_funcs i9xx_color_funcs = {
+ .color_check = i9xx_color_check,
+ .color_commit = i9xx_color_commit,
+ .load_luts = i9xx_load_luts,
+ .read_luts = i9xx_read_luts,
+};
+
+static const struct intel_color_funcs icl_color_funcs = {
+ .color_check = icl_color_check,
+ .color_commit = skl_color_commit,
+ .load_luts = icl_load_luts,
+ .read_luts = icl_read_luts,
+};
+
+static const struct intel_color_funcs glk_color_funcs = {
+ .color_check = glk_color_check,
+ .color_commit = skl_color_commit,
+ .load_luts = glk_load_luts,
+ .read_luts = glk_read_luts,
+};
+
+static const struct intel_color_funcs skl_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = skl_color_commit,
+ .load_luts = bdw_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs bdw_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = hsw_color_commit,
+ .load_luts = bdw_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs hsw_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = hsw_color_commit,
+ .load_luts = ivb_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs ivb_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = ilk_color_commit,
+ .load_luts = ivb_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs ilk_color_funcs = {
+ .color_check = ilk_color_check,
+ .color_commit = ilk_color_commit,
+ .load_luts = ilk_load_luts,
+ .read_luts = ilk_read_luts,
+};
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2101,52 +2171,28 @@ void intel_color_init(struct intel_crtc *crtc)
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->color_funcs.color_check = chv_color_check;
- dev_priv->color_funcs.color_commit = i9xx_color_commit;
- dev_priv->color_funcs.load_luts = chv_load_luts;
- dev_priv->color_funcs.read_luts = chv_read_luts;
+ dev_priv->color_funcs = _color_funcs;
} else if (DISPLAY_VER(dev_priv) >= 4) {
-
[Intel-gfx] [PATCH 14/23] drm/i915: constify fdi link training vtable
From: Dave Airlie
Put the vtable into ro memory.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fdi.c | 20
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index 94bb7e039fe7..148fb50035ff 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -15,7 +15,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
+ dev_priv->fdi_funcs->fdi_link_train(crtc, crtc_state);
}
/* units of 100MHz */
@@ -1013,15 +1013,27 @@ void lpt_fdi_program_mphy(struct drm_i915_private
*dev_priv)
intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
}
+static const struct intel_fdi_funcs ilk_funcs = {
+ .fdi_link_train = ilk_fdi_link_train,
+};
+
+static const struct intel_fdi_funcs gen6_funcs = {
+ .fdi_link_train = gen6_fdi_link_train,
+};
+
+static const struct intel_fdi_funcs ivb_funcs = {
+ .fdi_link_train = ivb_manual_fdi_link_train,
+};
+
void
intel_fdi_init_hook(struct drm_i915_private *dev_priv)
{
if (IS_IRONLAKE(dev_priv)) {
- dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
+ dev_priv->fdi_funcs = _funcs;
} else if (IS_SANDYBRIDGE(dev_priv)) {
- dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
+ dev_priv->fdi_funcs = _funcs;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
- dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
+ dev_priv->fdi_funcs = _funcs;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 575c46df5336..bb44ef4f6356 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -991,7 +991,7 @@ struct drm_i915_private {
struct intel_hotplug_funcs hotplug_funcs;
/* fdi display functions */
- struct intel_fdi_funcs fdi_funcs;
+ const struct intel_fdi_funcs *fdi_funcs;
/* display pll funcs */
struct intel_dpll_funcs dpll_funcs;
--
2.31.1
[Intel-gfx] [PATCH 15/23] drm/i915: constify hotplug function vtable.
From: Dave Airlie
Use a macro to avoid mistakes, this type of macro is only used
in a couple of places.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 4 +--
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 28 +++-
3 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 05f76aba4f8a..3c1cec953b42 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct
drm_i915_private *dev_priv)
static void intel_hpd_irq_setup(struct drm_i915_private *i915)
{
- if (i915->display_irqs_enabled && i915->hotplug_funcs.hpd_irq_setup)
- i915->hotplug_funcs.hpd_irq_setup(i915);
+ if (i915->display_irqs_enabled && i915->hotplug_funcs->hpd_irq_setup)
+ i915->hotplug_funcs->hpd_irq_setup(i915);
}
static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bb44ef4f6356..af1960856f19 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -988,7 +988,7 @@ struct drm_i915_private {
struct drm_i915_wm_disp_funcs wm_disp;
/* irq display functions */
- struct intel_hotplug_funcs hotplug_funcs;
+ const struct intel_hotplug_funcs *hotplug_funcs;
/* fdi display functions */
const struct intel_fdi_funcs *fdi_funcs;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c35065f8f429..77680bca46ee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4345,6 +4345,20 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
return ret;
}
+#define HPD_FUNCS(platform) \
+static const struct intel_hotplug_funcs platform##_hpd_funcs = { \
+ .hpd_irq_setup = platform##_hpd_irq_setup, \
+}
+
+HPD_FUNCS(i915);
+HPD_FUNCS(dg1);
+HPD_FUNCS(gen11);
+HPD_FUNCS(bxt);
+HPD_FUNCS(icp);
+HPD_FUNCS(spt);
+HPD_FUNCS(ilk);
+#undef HPD_FUNCS
+
/**
* intel_irq_init - initializes irq support
* @dev_priv: i915 device instance
@@ -4395,20 +4409,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
- dev_priv->hotplug_funcs.hpd_irq_setup =
i915_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
} else {
if (HAS_PCH_DG1(dev_priv))
- dev_priv->hotplug_funcs.hpd_irq_setup =
dg1_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->hotplug_funcs.hpd_irq_setup =
gen11_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->hotplug_funcs.hpd_irq_setup =
bxt_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- dev_priv->hotplug_funcs.hpd_irq_setup =
icp_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- dev_priv->hotplug_funcs.hpd_irq_setup =
spt_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else
- dev_priv->hotplug_funcs.hpd_irq_setup =
ilk_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
}
}
--
2.31.1
[Intel-gfx] [PATCH 13/23] drm/i915: split the dpll clock compute out from display vtable.
From: Dave Airlie
this single function might be possible to merge later, but
for now it's simple to just split it out.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dpll.c| 16
drivers/gpu/drm/i915/i915_drv.h | 8 +++-
3 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 413bc4667e47..02a9e684c86b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6821,10 +6821,10 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
crtc_state->update_wm_post = true;
if (mode_changed && crtc_state->hw.enable &&
- dev_priv->display.crtc_compute_clock &&
+ dev_priv->dpll_funcs.crtc_compute_clock &&
!crtc_state->bigjoiner_slave &&
!drm_WARN_ON(_priv->drm, crtc_state->shared_dpll)) {
- ret = dev_priv->display.crtc_compute_clock(crtc_state);
+ ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
if (ret)
return ret;
}
@@ -8851,7 +8851,7 @@ static void intel_modeset_clear_plls(struct
intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
- if (!dev_priv->display.crtc_compute_clock)
+ if (!dev_priv->dpll_funcs.crtc_compute_clock)
return;
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 210f91f4a576..9326c7cbb05c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1367,21 +1367,21 @@ void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
- dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
hsw_crtc_compute_clock;
else if (HAS_PCH_SPLIT(dev_priv))
- dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
ilk_crtc_compute_clock;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
chv_crtc_compute_clock;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
vlv_crtc_compute_clock;
else if (IS_G4X(dev_priv))
- dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
g4x_crtc_compute_clock;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
pnv_crtc_compute_clock;
else if (DISPLAY_VER(dev_priv) != 2)
- dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
i9xx_crtc_compute_clock;
else
- dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
i8xx_crtc_compute_clock;
}
static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 680301bce3ab..575c46df5336 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -393,6 +393,10 @@ struct intel_fdi_funcs {
const struct intel_crtc_state *crtc_state);
};
+struct intel_dpll_funcs {
+ int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
+};
+
struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -400,7 +404,6 @@ struct drm_i915_display_funcs {
struct intel_crtc_state *);
void (*get_initial_plane_config)(struct intel_crtc *,
struct intel_initial_plane_config *);
- int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
void (*crtc_enable)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*crtc_disable)(struct intel_atomic_state *state,
@@ -990,6 +993,9 @@ struct drm_i915_private {
/* fdi display functions */
struct intel_fdi_funcs fdi_funcs;
+ /* display pll funcs */
+ struct intel_dpll_funcs dpll_funcs;
+
/* Display
[Intel-gfx] [PATCH 12/23] drm/i915: split fdi link training from display vtable.
From: Dave Airlie
It may make sense to merge this with display again later,
however the fdi use of the vtable is limited to only a
few generations.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fdi.c | 8
drivers/gpu/drm/i915/i915_drv.h | 11 ---
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index 339243399a65..94bb7e039fe7 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -15,7 +15,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- dev_priv->display.fdi_link_train(crtc, crtc_state);
+ dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
}
/* units of 100MHz */
@@ -1017,11 +1017,11 @@ void
intel_fdi_init_hook(struct drm_i915_private *dev_priv)
{
if (IS_IRONLAKE(dev_priv)) {
- dev_priv->display.fdi_link_train = ilk_fdi_link_train;
+ dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
} else if (IS_SANDYBRIDGE(dev_priv)) {
- dev_priv->display.fdi_link_train = gen6_fdi_link_train;
+ dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
- dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
+ dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index caf854d251a6..680301bce3ab 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -388,6 +388,11 @@ struct intel_hotplug_funcs {
void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
};
+struct intel_fdi_funcs {
+ void (*fdi_link_train)(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state);
+};
+
struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -403,9 +408,6 @@ struct drm_i915_display_funcs {
void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*commit_modeset_disables)(struct intel_atomic_state *state);
- void (*fdi_link_train)(struct intel_crtc *crtc,
- const struct intel_crtc_state *crtc_state);
-
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
@@ -985,6 +987,9 @@ struct drm_i915_private {
/* irq display functions */
struct intel_hotplug_funcs hotplug_funcs;
+ /* fdi display functions */
+ struct intel_fdi_funcs fdi_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
--
2.31.1
[Intel-gfx] [PATCH 10/23] drm/i915: split cdclk functions from display vtable.
From: Dave Airlie
This moves all the cdclk related functions into their own vtable.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 142 ++---
drivers/gpu/drm/i915/i915_drv.h| 8 +-
2 files changed, 78 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0e09f259914f..27a4a226aa49 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -62,32 +62,32 @@
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
- dev_priv->display.get_cdclk(dev_priv, cdclk_config);
+ dev_priv->cdclk_funcs.get_cdclk(dev_priv, cdclk_config);
}
int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- return dev_priv->display.bw_calc_min_cdclk(state);
+ return dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
}
static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+ dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
}
static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state
*cdclk_config)
{
- return dev_priv->display.modeset_calc_cdclk(cdclk_config);
+ return dev_priv->cdclk_funcs.modeset_calc_cdclk(cdclk_config);
}
static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
int cdclk)
{
- return dev_priv->display.calc_voltage_level(cdclk);
+ return dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
}
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
if (!intel_cdclk_changed(_priv->cdclk.hw, cdclk_config))
return;
- if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->display.set_cdclk))
+ if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
return;
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -2893,119 +2893,119 @@ u32 intel_read_rawclk(struct drm_i915_private
*dev_priv)
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
if (IS_DG2(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk =
bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level =
tgl_calc_voltage_level;
dev_priv->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk =
bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level =
tgl_calc_voltage_level;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
else
dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk =
bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level =
tgl_calc_voltage_level;
[Intel-gfx] [PATCH 11/23] drm/i915: split irq hotplug function from display vtable
From: Dave Airlie
This provide a service from irq to display, so make it separate
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 9 -
drivers/gpu/drm/i915/i915_irq.c | 14 +++---
3 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 47c85ac97c87..05f76aba4f8a 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct
drm_i915_private *dev_priv)
static void intel_hpd_irq_setup(struct drm_i915_private *i915)
{
- if (i915->display_irqs_enabled && i915->display.hpd_irq_setup)
- i915->display.hpd_irq_setup(i915);
+ if (i915->display_irqs_enabled && i915->hotplug_funcs.hpd_irq_setup)
+ i915->hotplug_funcs.hpd_irq_setup(i915);
}
static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 11298f583cc0..caf854d251a6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -384,6 +384,10 @@ struct intel_cdclk_funcs {
u8 (*calc_voltage_level)(int cdclk);
};
+struct intel_hotplug_funcs {
+ void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
+};
+
struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -401,7 +405,7 @@ struct drm_i915_display_funcs {
void (*fdi_link_train)(struct intel_crtc *crtc,
const struct intel_crtc_state *crtc_state);
- void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
+
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
@@ -978,6 +982,9 @@ struct drm_i915_private {
/* pm display functions */
struct drm_i915_wm_disp_funcs wm_disp;
+ /* irq display functions */
+ struct intel_hotplug_funcs hotplug_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0a1681384c84..c35065f8f429 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4395,20 +4395,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
i915_hpd_irq_setup;
} else {
if (HAS_PCH_DG1(dev_priv))
- dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
dg1_hpd_irq_setup;
else if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
gen11_hpd_irq_setup;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
bxt_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
icp_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
spt_hpd_irq_setup;
else
- dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
ilk_hpd_irq_setup;
}
}
--
2.31.1
[Intel-gfx] [PATCH 09/23] drm/i915: split audio functions from display vtable
From: Dave Airlie
These are only used internally in the audio code
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_audio.c | 24 +++---
drivers/gpu/drm/i915/i915_drv.h| 19 +++--
2 files changed, 25 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 532237588511..f539826c0424 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -848,8 +848,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
- if (dev_priv->display.audio_codec_enable)
- dev_priv->display.audio_codec_enable(encoder,
+ if (dev_priv->audio_funcs.audio_codec_enable)
+ dev_priv->audio_funcs.audio_codec_enable(encoder,
crtc_state,
conn_state);
@@ -893,8 +893,8 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
- if (dev_priv->display.audio_codec_disable)
- dev_priv->display.audio_codec_disable(encoder,
+ if (dev_priv->audio_funcs.audio_codec_disable)
+ dev_priv->audio_funcs.audio_codec_disable(encoder,
old_crtc_state,
old_conn_state);
@@ -922,17 +922,17 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
{
if (IS_G4X(dev_priv)) {
- dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
- dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable =
g4x_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable =
g4x_audio_codec_disable;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
- dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable =
ilk_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable =
ilk_audio_codec_disable;
} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
- dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable =
hsw_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable =
hsw_audio_codec_disable;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
- dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable =
ilk_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable =
ilk_audio_codec_disable;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8930bf2db226..1ba94dee683e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -364,6 +364,15 @@ struct intel_color_funcs {
void (*read_luts)(struct intel_crtc_state *crtc_state);
};
+struct intel_audio_funcs {
+ void (*audio_codec_enable)(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state
*conn_state);
+ void (*audio_codec_disable)(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*old_crtc_state,
+ const struct drm_connector_state
*old_conn_state);
+};
+
struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config);
@@ -386,12 +395,7 @@ struct drm_i915_display_funcs {
struct intel_crtc *crtc);
void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*commit_modeset_disables)(struct intel_atomic_state *state);
- void (*audio_codec_enable)(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state
*conn_state);
- void (*audio_codec_disable)(struct intel_encoder *encoder,
- const struct intel_crtc_state
*old_crtc_state,
- const struct
[Intel-gfx] [PATCH 08/23] drm/i915: split color functions from display vtable
From: Dave Airlie
These are only used internally in the color module
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_color.c | 64 +++---
drivers/gpu/drm/i915/i915_drv.h| 39 +++--
2 files changed, 54 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index afcb4bf3826c..ed79075158dd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct
intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->display.load_luts(crtc_state);
+ dev_priv->color_funcs.load_luts(crtc_state);
}
void intel_color_commit(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->display.color_commit(crtc_state);
+ dev_priv->color_funcs.color_commit(crtc_state);
}
static bool intel_can_preload_luts(const struct intel_crtc_state
*new_crtc_state)
@@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- return dev_priv->display.color_check(crtc_state);
+ return dev_priv->color_funcs.color_check(crtc_state);
}
void intel_color_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (dev_priv->display.read_luts)
- dev_priv->display.read_luts(crtc_state);
+ if (dev_priv->color_funcs.read_luts)
+ dev_priv->color_funcs.read_luts(crtc_state);
}
static bool need_plane_update(struct intel_plane *plane,
@@ -2101,51 +2101,51 @@ void intel_color_init(struct intel_crtc *crtc)
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.color_check = chv_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = chv_load_luts;
- dev_priv->display.read_luts = chv_read_luts;
+ dev_priv->color_funcs.color_check = chv_color_check;
+ dev_priv->color_funcs.color_commit = i9xx_color_commit;
+ dev_priv->color_funcs.load_luts = chv_load_luts;
+ dev_priv->color_funcs.read_luts = chv_read_luts;
} else if (DISPLAY_VER(dev_priv) >= 4) {
- dev_priv->display.color_check = i9xx_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = i965_load_luts;
- dev_priv->display.read_luts = i965_read_luts;
+ dev_priv->color_funcs.color_check = i9xx_color_check;
+ dev_priv->color_funcs.color_commit = i9xx_color_commit;
+ dev_priv->color_funcs.load_luts = i965_load_luts;
+ dev_priv->color_funcs.read_luts = i965_read_luts;
} else {
- dev_priv->display.color_check = i9xx_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = i9xx_load_luts;
- dev_priv->display.read_luts = i9xx_read_luts;
+ dev_priv->color_funcs.color_check = i9xx_color_check;
+ dev_priv->color_funcs.color_commit = i9xx_color_commit;
+ dev_priv->color_funcs.load_luts = i9xx_load_luts;
+ dev_priv->color_funcs.read_luts = i9xx_read_luts;
}
} else {
if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->display.color_check = icl_color_check;
+ dev_priv->color_funcs.color_check = icl_color_check;
else if (DISPLAY_VER(dev_priv) >= 10)
- dev_priv->display.color_check = glk_color_check;
+ dev_priv->color_funcs.color_check = glk_color_check;
else if (DISPLAY_VER(dev_priv) >= 7)
- dev_priv->display.color_check = ivb_color_check;
+ dev_priv->color_funcs.color_check = ivb_color_check;
else
- dev_priv->display.color_check = ilk_color_check;
+ dev_priv->color_funcs.color_check = ilk_color_check;
if (DISPLAY_VER(dev_priv) >= 9)
- dev_priv->display.color_commit = skl_color_commit;
+ dev_priv->color_funcs.color_commit = skl_color_commit;
else if (IS_BROADWELL(dev_priv) ||
[Intel-gfx] [PATCH 06/23] drm/i915: split clock gating init from display vtable
From: Dave Airlie
This function is only used inside intel_pm.c
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_drv.h | 9 ++-
drivers/gpu/drm/i915/intel_pm.c | 48 -
2 files changed, 32 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 894c883044ee..48d30b967def 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -323,6 +323,11 @@ struct intel_crtc;
struct intel_limit;
struct dpll;
+/* functions used internal in intel_pm.c */
+struct drm_i915_clock_gating_funcs {
+ void (*init_clock_gating)(struct drm_i915_private *dev_priv);
+};
+
struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config);
@@ -365,7 +370,6 @@ struct drm_i915_display_funcs {
const struct drm_connector_state
*old_conn_state);
void (*fdi_link_train)(struct intel_crtc *crtc,
const struct intel_crtc_state *crtc_state);
- void (*init_clock_gating)(struct drm_i915_private *dev_priv);
void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
/* clock updates for mode set */
/* cursor updates */
@@ -954,6 +958,9 @@ struct drm_i915_private {
/* unbound hipri wq for page flips/plane updates */
struct workqueue_struct *flip_wq;
+ /* pm private clock gating functions */
+ struct drm_i915_clock_gating_funcs clock_gating_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4054c6f7a2f9..add50ff01d7c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating(struct drm_i915_private *dev_priv)
{
- dev_priv->display.init_clock_gating(dev_priv);
+ dev_priv->clock_gating_funcs.init_clock_gating(dev_priv);
}
void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7898,52 +7898,52 @@ static void nop_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_ALDERLAKE_P(dev_priv))
- dev_priv->display.init_clock_gating = adlp_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
adlp_init_clock_gating;
else if (IS_DG1(dev_priv))
- dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
dg1_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 12)
- dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
gen12lp_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 11)
- dev_priv->display.init_clock_gating = icl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
icl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
- dev_priv->display.init_clock_gating = cfl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
cfl_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
- dev_priv->display.init_clock_gating = skl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
skl_init_clock_gating;
else if (IS_KABYLAKE(dev_priv))
- dev_priv->display.init_clock_gating = kbl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
kbl_init_clock_gating;
else if (IS_BROXTON(dev_priv))
- dev_priv->display.init_clock_gating = bxt_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
bxt_init_clock_gating;
else if (IS_GEMINILAKE(dev_priv))
- dev_priv->display.init_clock_gating = glk_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
glk_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
- dev_priv->display.init_clock_gating = bdw_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
bdw_init_clock_gating;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->display.init_clock_gating = chv_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
chv_init_clock_gating;
else if (IS_HASWELL(dev_priv))
- dev_priv->display.init_clock_gating = hsw_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
hsw_init_clock_gating;
else if (IS_IVYBRIDGE(dev_priv))
-
[Intel-gfx] [PATCH 07/23] drm/i915: split watermark vfuncs from display vtable.
From: Dave Airlie
These are the watermark api between display and pm.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 35 -
drivers/gpu/drm/i915/i915_drv.h | 24
drivers/gpu/drm/i915/intel_pm.c | 40 ++--
3 files changed, 54 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f2678d26cd17..413bc4667e47 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -162,16 +162,16 @@ static void intel_modeset_setup_hw_state(struct
drm_device *dev,
*/
static void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
- if (dev_priv->display.update_wm)
- dev_priv->display.update_wm(dev_priv);
+ if (dev_priv->wm_disp.update_wm)
+ dev_priv->wm_disp.update_wm(dev_priv);
}
static int intel_compute_pipe_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.compute_pipe_wm)
- return dev_priv->display.compute_pipe_wm(state, crtc);
+ if (dev_priv->wm_disp.compute_pipe_wm)
+ return dev_priv->wm_disp.compute_pipe_wm(state, crtc);
return 0;
}
@@ -180,10 +180,10 @@ static int intel_compute_intermediate_wm(struct
intel_atomic_state *state,
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
if (drm_WARN_ON(_priv->drm,
- !dev_priv->display.compute_pipe_wm))
+ !dev_priv->wm_disp.compute_pipe_wm))
return 0;
- if (dev_priv->display.compute_pipe_wm)
- return dev_priv->display.compute_intermediate_wm(state, crtc);
+ if (dev_priv->wm_disp.compute_pipe_wm)
+ return dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
return 0;
}
@@ -191,8 +191,8 @@ static bool intel_initial_watermarks(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.initial_watermarks) {
- dev_priv->display.initial_watermarks(state, crtc);
+ if (dev_priv->wm_disp.initial_watermarks) {
+ dev_priv->wm_disp.initial_watermarks(state, crtc);
return true;
}
return false;
@@ -202,23 +202,23 @@ static void intel_atomic_update_watermarks(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.atomic_update_watermarks)
- dev_priv->display.atomic_update_watermarks(state, crtc);
+ if (dev_priv->wm_disp.atomic_update_watermarks)
+ dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
}
static void intel_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.optimize_watermarks)
- dev_priv->display.optimize_watermarks(state, crtc);
+ if (dev_priv->wm_disp.optimize_watermarks)
+ dev_priv->wm_disp.optimize_watermarks(state, crtc);
}
static void intel_compute_global_watermarks(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.compute_global_watermarks)
- dev_priv->display.compute_global_watermarks(state);
+ if (dev_priv->wm_disp.compute_global_watermarks)
+ dev_priv->wm_disp.compute_global_watermarks(state);
}
/* returns HPLL frequency in kHz */
@@ -3669,6 +3669,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state
*state,
if (!intel_initial_watermarks(state, crtc))
intel_update_watermarks(dev_priv);
+
intel_enable_pipe(new_crtc_state);
intel_crtc_vblank_on(new_crtc_state);
@@ -3734,7 +3735,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state
*state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
- if (!dev_priv->display.initial_watermarks)
+ if (!dev_priv->wm_disp.initial_watermarks)
intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
@@ -11387,7 +11388,7 @@ static void sanitize_watermarks(struct drm_i915_private
*dev_priv)
int i;
/* Only supported on platforms that use atomic watermark design */
- if (!dev_priv->display.optimize_watermarks)
+ if (!dev_priv->wm_disp.optimize_watermarks)
[Intel-gfx] [PATCH 04/23] drm/i915: add wrappers around cdclk vtable funcs.
From: Dave Airlie
This adds wrappers around all the vtable callers so they are in
one place.
Suggested by Jani.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_cdclk.c| 47 +++
drivers/gpu/drm/i915/display/intel_cdclk.h| 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
.../drm/i915/display/intel_display_power.c| 2 +-
4 files changed, 44 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9aec17b33819..0e09f259914f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -59,6 +59,37 @@
* dividers can be programmed correctly.
*/
+void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_config *cdclk_config)
+{
+ dev_priv->display.get_cdclk(dev_priv, cdclk_config);
+}
+
+int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ return dev_priv->display.bw_calc_min_cdclk(state);
+}
+
+static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *cdclk_config,
+ enum pipe pipe)
+{
+ dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+}
+
+static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_state
*cdclk_config)
+{
+ return dev_priv->display.modeset_calc_cdclk(cdclk_config);
+}
+
+static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
+int cdclk)
+{
+ return dev_priv->display.calc_voltage_level(cdclk);
+}
+
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
@@ -1466,7 +1497,7 @@ static void bxt_get_cdclk(struct drm_i915_private
*dev_priv,
* at least what the CDCLK frequency requires.
*/
cdclk_config->voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk);
}
static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1777,7 +1808,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private
*dev_priv)
cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
cdclk_config.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
bxt_set_cdclk(dev_priv, _config, INVALID_PIPE);
}
@@ -1789,7 +1820,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private
*dev_priv)
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
cdclk_config.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
bxt_set_cdclk(dev_priv, _config, INVALID_PIPE);
}
@@ -1956,7 +1987,7 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
_priv->gmbus_mutex);
}
- dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+ intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
for_each_intel_dp(_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2424,7 +2455,7 @@ static int bxt_modeset_calc_cdclk(struct
intel_cdclk_state *cdclk_state)
cdclk_state->logical.cdclk = cdclk;
cdclk_state->logical.voltage_level =
max_t(int, min_voltage_level,
- dev_priv->display.calc_voltage_level(cdclk));
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk));
if (!cdclk_state->active_pipes) {
cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
@@ -2433,7 +2464,7 @@ static int bxt_modeset_calc_cdclk(struct
intel_cdclk_state *cdclk_state)
cdclk_state->actual.vco = vco;
cdclk_state->actual.cdclk = cdclk;
cdclk_state->actual.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk);
} else {
cdclk_state->actual = cdclk_state->logical;
}
@@ -2525,7 +2556,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
new_cdclk_state->active_pipes =
intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
- ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
+ ret =
[Intel-gfx] [PATCH 05/23] drm/i915/display: add intel_fdi_link_train wrapper.
From: Dave Airlie
This wraps the fdi link training vfunc to make it clearer.
Suggested by Jani.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 8
drivers/gpu/drm/i915/display/intel_fdi.h | 2 ++
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8d2147880fa1..f2678d26cd17 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2156,7 +2156,7 @@ static void ilk_pch_enable(const struct
intel_atomic_state *state,
assert_pch_transcoder_disabled(dev_priv, pipe);
/* For PCH output, training FDI link */
- dev_priv->display.fdi_link_train(crtc, crtc_state);
+ intel_fdi_link_train(crtc, crtc_state);
/* We need to program the right clock selection before writing the pixel
* mutliplier into the DPLL. */
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index fc09b781f15f..339243399a65 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -10,6 +10,14 @@
#include "intel_fdi.h"
#include "intel_sideband.h"
+void intel_fdi_link_train(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ dev_priv->display.fdi_link_train(crtc, crtc_state);
+}
+
/* units of 100MHz */
static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
{
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h
b/drivers/gpu/drm/i915/display/intel_fdi.h
index 60acf2133145..61cb216a09f5 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.h
+++ b/drivers/gpu/drm/i915/display/intel_fdi.h
@@ -26,4 +26,6 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
void intel_fdi_pll_freq_update(struct drm_i915_private *i915);
void lpt_fdi_program_mphy(struct drm_i915_private *i915);
+void intel_fdi_link_train(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state);
#endif
--
2.31.1
[Intel-gfx] [PATCH 03/23] drm/i915/wm: provide wrappers around watermark vfuncs calls
From: Dave Airlie
This moves one wrapper from the pm->display side, and creates
wrappers for all the others, this should simplify things later.
One thing to note is that the code checks the existance of some
of these ptrs, so the wrappers are a bit complicated by that.
Suggested by Jani.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 187 ---
drivers/gpu/drm/i915/intel_pm.c | 39
drivers/gpu/drm/i915/intel_pm.h | 1 -
3 files changed, 123 insertions(+), 104 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e62f8317cbda..3d8afa9f3237 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -126,6 +126,101 @@ static void ilk_pfit_enable(const struct intel_crtc_state
*crtc_state);
static void intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx);
+
+/**
+ * intel_update_watermarks - update FIFO watermark values based on current
modes
+ * @crtc: the #intel_crtc on which to compute the WM
+ *
+ * Calculate watermark values for the various WM regs based on current mode
+ * and plane configuration.
+ *
+ * There are several cases to deal with here:
+ * - normal (i.e. non-self-refresh)
+ * - self-refresh (SR) mode
+ * - lines are large relative to FIFO size (buffer can hold up to 2)
+ * - lines are small relative to FIFO size (buffer can hold more than 2
+ * lines), so need to account for TLB latency
+ *
+ * The normal calculation is:
+ * watermark = dotclock * bytes per pixel * latency
+ * where latency is platform & configuration dependent (we assume pessimal
+ * values here).
+ *
+ * The SR calculation is:
+ * watermark = (trunc(latency/line time)+1) * surface width *
+ * bytes per pixel
+ * where
+ * line time = htotal / dotclock
+ * surface width = hdisplay for normal plane and 64 for cursor
+ * and latency is assumed to be high, as above.
+ *
+ * The final value programmed to the register should always be rounded up,
+ * and include an extra 2 entries to account for clock crossings.
+ *
+ * We don't use the sprite, so we can ignore that. And on Crestline we have
+ * to set the non-SR watermarks to 8.
+ */
+static void intel_update_watermarks(struct drm_i915_private *dev_priv)
+{
+ if (dev_priv->display.update_wm)
+ dev_priv->display.update_wm(dev_priv);
+}
+
+static int intel_compute_pipe_wm(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.compute_pipe_wm)
+ return dev_priv->display.compute_pipe_wm(state, crtc);
+ return 0;
+}
+
+static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (drm_WARN_ON(_priv->drm,
+ !dev_priv->display.compute_pipe_wm))
+ return 0;
+ if (dev_priv->display.compute_pipe_wm)
+ return dev_priv->display.compute_intermediate_wm(state, crtc);
+ return 0;
+}
+
+static bool intel_initial_watermarks(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.initial_watermarks) {
+ dev_priv->display.initial_watermarks(state, crtc);
+ return true;
+ }
+ return false;
+}
+
+static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.atomic_update_watermarks)
+ dev_priv->display.atomic_update_watermarks(state, crtc);
+}
+
+static void intel_optimize_watermarks(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.optimize_watermarks)
+ dev_priv->display.optimize_watermarks(state, crtc);
+}
+
+static void intel_compute_global_watermarks(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.compute_global_watermarks)
+ dev_priv->display.compute_global_watermarks(state);
+}
+
/* returns HPLL frequency in kHz */
int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
{
@@ -2528,9 +2623,8 @@ static void intel_pre_plane_update(struct
intel_atomic_state *state,
* we'll continue to update watermarks the
[Intel-gfx] [PATCH 02/23] drm/i915: make update_wm take a dev_priv.
From: Dave Airlie
The crtc was never being used here.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 18 ++
drivers/gpu/drm/i915/intel_pm.h | 2 +-
4 files changed, 13 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 134c792e1dbd..e62f8317cbda 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2374,7 +2374,7 @@ static void intel_post_plane_update(struct
intel_atomic_state *state,
intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
hsw_enable_ips(new_crtc_state);
@@ -2531,7 +2531,7 @@ static void intel_pre_plane_update(struct
intel_atomic_state *state,
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
else if (new_crtc_state->update_wm_pre)
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
}
/*
@@ -3578,7 +3578,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state
*state,
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
else
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
intel_enable_pipe(new_crtc_state);
intel_crtc_vblank_on(new_crtc_state);
@@ -3645,7 +3645,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state
*state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
if (!dev_priv->display.initial_watermarks)
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
if (IS_I830(dev_priv))
@@ -3721,7 +3721,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc
*crtc,
encoder->base.crtc = NULL;
intel_fbc_disable(crtc);
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
intel_disable_shared_dpll(crtc_state);
intel_display_power_put_all_in_set(dev_priv,
>enabled_power_domains);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fc546d2ff0fc..894c883044ee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -341,7 +341,7 @@ struct drm_i915_display_funcs {
void (*optimize_watermarks)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*compute_global_watermarks)(struct intel_atomic_state *state);
- void (*update_wm)(struct intel_crtc *crtc);
+ void (*update_wm)(struct drm_i915_private *dev_priv);
int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
u8 (*calc_voltage_level)(int cdclk);
/* Returns the active state of the crtc, and if the crtc is active,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d9993eb3730d..406baa49e6ad 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -881,9 +881,8 @@ static struct intel_crtc *single_enabled_crtc(struct
drm_i915_private *dev_priv)
return enabled;
}
-static void pnv_update_wm(struct intel_crtc *unused_crtc)
+static void pnv_update_wm(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
const struct cxsr_latency *latency;
u32 reg;
@@ -2253,9 +2252,8 @@ static void vlv_optimize_watermarks(struct
intel_atomic_state *state,
mutex_unlock(_priv->wm.wm_mutex);
}
-static void i965_update_wm(struct intel_crtc *unused_crtc)
+static void i965_update_wm(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
int srwm = 1;
int cursor_sr = 16;
@@ -2329,9 +2327,8 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
#undef FW_WM
-static void i9xx_update_wm(struct intel_crtc *unused_crtc)
+static void i9xx_update_wm(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
const struct intel_watermark_params *wm_info;
u32 fwater_lo;
u32 fwater_hi;
@@ -2481,9 +2478,8 @@ static void i9xx_update_wm(struct
[Intel-gfx] [PATCH 01/23] drm/i915/pm: drop get_fifo_size vfunc.
From: Dave Airlie
The i845_update_wm code was always calling the i845 variant,
and the i9xx_update_wm had only a choice between i830 and i9xx
paths, hardly worth the vfunc overhead.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/intel_pm.c | 20 +++-
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a8129153d1db..fc546d2ff0fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -330,8 +330,6 @@ struct drm_i915_display_funcs {
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe);
int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
- int (*get_fifo_size)(struct drm_i915_private *dev_priv,
-enum i9xx_plane_id i9xx_plane);
int (*compute_pipe_wm)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*compute_intermediate_wm)(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cfc41f8fa74a..d9993eb3730d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2347,7 +2347,10 @@ static void i9xx_update_wm(struct intel_crtc
*unused_crtc)
else
wm_info = _a_wm_info;
- fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
+ if (DISPLAY_VER(dev_priv) == 2)
+ fifo_size = i830_get_fifo_size(dev_priv, PLANE_A);
+ else
+ fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A);
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *pipe_mode =
@@ -2374,7 +2377,10 @@ static void i9xx_update_wm(struct intel_crtc
*unused_crtc)
if (DISPLAY_VER(dev_priv) == 2)
wm_info = _bc_wm_info;
- fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
+ if (DISPLAY_VER(dev_priv) == 2)
+ fifo_size = i830_get_fifo_size(dev_priv, PLANE_B);
+ else
+ fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B);
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *pipe_mode =
@@ -2490,7 +2496,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
pipe_mode = >config->hw.pipe_mode;
planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
_wm_info,
-
dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
+ i845_get_fifo_size(dev_priv, PLANE_A),
4, pessimal_latency_ns);
fwater_lo = intel_uncore_read(_priv->uncore, FW_BLC) & ~0xfff;
fwater_lo |= (3<<8) | planea_wm;
@@ -8054,15 +8060,11 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->display.update_wm = i965_update_wm;
} else if (DISPLAY_VER(dev_priv) == 3) {
dev_priv->display.update_wm = i9xx_update_wm;
- dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
} else if (DISPLAY_VER(dev_priv) == 2) {
- if (INTEL_NUM_PIPES(dev_priv) == 1) {
+ if (INTEL_NUM_PIPES(dev_priv) == 1)
dev_priv->display.update_wm = i845_update_wm;
- dev_priv->display.get_fifo_size = i845_get_fifo_size;
- } else {
+ else
dev_priv->display.update_wm = i9xx_update_wm;
- dev_priv->display.get_fifo_size = i830_get_fifo_size;
- }
} else {
drm_err(_priv->drm,
"unexpected fall-through in %s\n", __func__);
--
2.31.1
[Intel-gfx] [PATCH 00/23] i915/display: split and constify vtable (v3)
(v3 just adds some missing ,) Details below, I've taken all the review feedback (thanks Jani). I added 3 patches moving to wrappers before refactoring, and one other patch is unreviewed (07) but the main comment was wanting the wrappers. Jani if you are happy with the final 4 patches can you land this series, I don't think I have drm-intel commit rights. v1: This is orthogonal to my display ptr refactoring and should probably be applied first. The display funcs vtable was a bit of mess, lots of intermixing of internal display functionality and interfaces to watermarks/irqs. It's also considered not great security practice to leave writeable function pointers around for exploits to get into. This series attempts to address both problems, first there are a few cleanups, then it splits the function table into multiple pieces. Some of the splits might be bikesheds but I think we should apply first and merge things later if there is good reason. The second half converts all the vtables to static const structs, I've used macros in some of them to make it less messy, the cdclk one is probably the worst one. v2: Added some patches adding wrappers around things before refactoring them as suggested by Jani. Fixed up all struct names as suggested by Jani. Added s-o-b lines Added commit msgs. v3: added missing , (Jani) Dave.
[Intel-gfx] ✗ Fi.CI.DOCS: warning for i915/display: split and constify vtable (rev2)
== Series Details == Series: i915/display: split and constify vtable (rev2) URL : https://patchwork.freedesktop.org/series/94459/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_display.c:164: warning: Excess function parameter 'crtc' description in 'intel_update_watermarks'
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915/display: split and constify vtable (rev2)
== Series Details ==
Series: i915/display: split and constify vtable (rev2)
URL : https://patchwork.freedesktop.org/series/94459/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
861185f462cb drm/i915/pm: drop get_fifo_size vfunc.
0128f0dd02e7 drm/i915: make update_wm take a dev_priv.
6736ec4f3d7c drm/i915/wm: provide wrappers around watermark vfuncs calls
-:9: WARNING:TYPO_SPELLING: 'existance' may be misspelled - perhaps 'existence'?
#9:
One thing to note is that the code checks the existance of some
^
-:24: CHECK:LINE_SPACING: Please don't use multiple blank lines
#24: FILE: drivers/gpu/drm/i915/display/intel_display.c:129:
+
-:68: WARNING:LINE_SPACING: Missing a blank line after declarations
#68: FILE: drivers/gpu/drm/i915/display/intel_display.c:173:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.compute_pipe_wm)
-:77: WARNING:LINE_SPACING: Missing a blank line after declarations
#77: FILE: drivers/gpu/drm/i915/display/intel_display.c:182:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (drm_WARN_ON(_priv->drm,
-:89: WARNING:LINE_SPACING: Missing a blank line after declarations
#89: FILE: drivers/gpu/drm/i915/display/intel_display.c:194:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.initial_watermarks) {
-:100: WARNING:LINE_SPACING: Missing a blank line after declarations
#100: FILE: drivers/gpu/drm/i915/display/intel_display.c:205:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.atomic_update_watermarks)
-:108: WARNING:LINE_SPACING: Missing a blank line after declarations
#108: FILE: drivers/gpu/drm/i915/display/intel_display.c:213:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.optimize_watermarks)
-:115: WARNING:LINE_SPACING: Missing a blank line after declarations
#115: FILE: drivers/gpu/drm/i915/display/intel_display.c:220:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.compute_global_watermarks)
-:129: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional
statements (16, 20)
#129: FILE: drivers/gpu/drm/i915/display/intel_display.c:2626:
+ if (!intel_initial_watermarks(state, crtc))
+ if (new_crtc_state->update_wm_pre)
-:130: WARNING:TABSTOP: Statements should start on a tabstop
#130: FILE: drivers/gpu/drm/i915/display/intel_display.c:2627:
+ if (new_crtc_state->update_wm_pre)
-:171: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional
statements (8, 12)
#171: FILE: drivers/gpu/drm/i915/display/intel_display.c:3670:
+ if (!intel_initial_watermarks(state, crtc))
+ intel_update_watermarks(dev_priv);
total: 0 errors, 10 warnings, 1 checks, 319 lines checked
d4355a1ab8b5 drm/i915: add wrappers around cdclk vtable funcs.
-:30: WARNING:LINE_SPACING: Missing a blank line after declarations
#30: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:71:
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ return dev_priv->display.bw_calc_min_cdclk(state);
total: 0 errors, 1 warnings, 0 checks, 127 lines checked
50c640da1629 drm/i915/display: add intel_fdi_link_train wrapper.
8f69042761b2 drm/i915: split clock gating init from display vtable
c398feb04b80 drm/i915: split watermark vfuncs from display vtable.
15521fe74480 drm/i915: split color functions from display vtable
e7e7cb2df965 drm/i915: split audio functions from display vtable
293f7a3cd1ee drm/i915: split cdclk functions from display vtable.
833a11509155 drm/i915: split irq hotplug function from display vtable
e47bebd1891f drm/i915: split fdi link training from display vtable.
db3b4508c591 drm/i915: split the dpll clock compute out from display vtable.
34025d57fe46 drm/i915: constify fdi link training vtable
344a6d43dbcf drm/i915: constify hotplug function vtable.
31b6e09af8a9 drm/i915: constify color function vtable.
-:196: CHECK:BRACES: Unbalanced braces around else statement
#196: FILE: drivers/gpu/drm/i915/display/intel_color.c:2194:
+ } else
total: 0 errors, 0 warnings, 1 checks, 187 lines checked
75a66a44f968 drm/i915: constify the audio function vtable
15b1d958a0f9 drm/i915: constify the dpll clock vtable
d9a59612ea5b drm/i915: constify the cdclk vtable
847e28dad4f3 drm/i915: drop unused function ptr and comments.
49a26c76173c drm/i915: constify display function vtable
fecaefd7d43d drm/i915: constify clock gating init vtable.
95a2f0fcea26 drm/i915: constify display wm vtable
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: rename debugfs_gt files
== Series Details ==
Series: series starting with [1/4] drm/i915: rename debugfs_gt files
URL : https://patchwork.freedesktop.org/series/94489/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10565 -> Patchwork_20993
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/index.html
Known issues
Here are the changes found in Patchwork_20993 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +27 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html
* igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u: NOTRUN -> [WARN][2] ([i915#3718])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [PASS][3] -> [INCOMPLETE][4] ([i915#2940])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-tgl-y: [PASS][5] -> [DMESG-FAIL][6] ([i915#541])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html
* igt@runner@aborted:
- fi-bsw-n3050: NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#1436] /
[i915#2722] / [i915#3428])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/fi-bsw-n3050/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_pm:
- {fi-jsl-1}: [DMESG-FAIL][9] ([i915#1886]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (47 -> 38)
--
Missing(9): fi-kbl-soraka fi-ilk-m540 bat-adls-5 bat-dg1-6 fi-bsw-cyan
bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-1
Build changes
-
* Linux: CI_DRM_10565 -> Patchwork_20993
CI-20190529: 20190529
CI_DRM_10565: 8c3cd60dcfa81a649b14f0705eb5e5c9336f1881 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6201: be0d02ff0775235ead63ccb1e3a1e8c10f0209cf @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20993: 9c1930918f14247079ef11b7af3fbf06488fbb57 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9c1930918f14 drm/i915: deduplicate frequency dump on debugfs
139ac6e275d3 drm/i915: rename debugfs_gt_pm files
bdf1cc706705 drm/i915: rename debugfs_engines files
dc1cedc411a9 drm/i915: rename debugfs_gt files
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20993/index.html
[Intel-gfx] [PATCH 23/23] drm/i915: constify display wm vtable
From: Dave Airlie
Use a nop table for the cases where CxSR doesn't init properly.
v2: use a nop table (Jani)
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 34 -
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 80 ++--
3 files changed, 75 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8b9727d84435..502e9ac70de1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -162,16 +162,16 @@ static void intel_modeset_setup_hw_state(struct
drm_device *dev,
*/
static void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
- if (dev_priv->wm_disp.update_wm)
- dev_priv->wm_disp.update_wm(dev_priv);
+ if (dev_priv->wm_disp->update_wm)
+ dev_priv->wm_disp->update_wm(dev_priv);
}
static int intel_compute_pipe_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.compute_pipe_wm)
- return dev_priv->wm_disp.compute_pipe_wm(state, crtc);
+ if (dev_priv->wm_disp->compute_pipe_wm)
+ return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
return 0;
}
@@ -180,10 +180,10 @@ static int intel_compute_intermediate_wm(struct
intel_atomic_state *state,
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
if (drm_WARN_ON(_priv->drm,
- !dev_priv->wm_disp.compute_pipe_wm))
+ !dev_priv->wm_disp->compute_pipe_wm))
return 0;
- if (dev_priv->wm_disp.compute_pipe_wm)
- return dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
+ if (dev_priv->wm_disp->compute_pipe_wm)
+ return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
return 0;
}
@@ -191,8 +191,8 @@ static bool intel_initial_watermarks(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.initial_watermarks) {
- dev_priv->wm_disp.initial_watermarks(state, crtc);
+ if (dev_priv->wm_disp->initial_watermarks) {
+ dev_priv->wm_disp->initial_watermarks(state, crtc);
return true;
}
return false;
@@ -202,23 +202,23 @@ static void intel_atomic_update_watermarks(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.atomic_update_watermarks)
- dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
+ if (dev_priv->wm_disp->atomic_update_watermarks)
+ dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
}
static void intel_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.optimize_watermarks)
- dev_priv->wm_disp.optimize_watermarks(state, crtc);
+ if (dev_priv->wm_disp->optimize_watermarks)
+ dev_priv->wm_disp->optimize_watermarks(state, crtc);
}
static void intel_compute_global_watermarks(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.compute_global_watermarks)
- dev_priv->wm_disp.compute_global_watermarks(state);
+ if (dev_priv->wm_disp->compute_global_watermarks)
+ dev_priv->wm_disp->compute_global_watermarks(state);
}
/* returns HPLL frequency in kHz */
@@ -3735,7 +3735,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state
*state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
- if (!dev_priv->wm_disp.initial_watermarks)
+ if (!dev_priv->wm_disp->initial_watermarks)
intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
@@ -11409,7 +11409,7 @@ static void sanitize_watermarks(struct drm_i915_private
*dev_priv)
int i;
/* Only supported on platforms that use atomic watermark design */
- if (!dev_priv->wm_disp.optimize_watermarks)
+ if (!dev_priv->wm_disp->optimize_watermarks)
return;
state = drm_atomic_state_alloc(_priv->drm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fc7466bbc445..b9fa6bf4835d 100644
---
[Intel-gfx] [PATCH 22/23] drm/i915: constify clock gating init vtable.
From: Dave Airlie
I used a macro to avoid making any really silly mistakes here.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 78 +++--
2 files changed, 55 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5bbdd3b06e6d..fc7466bbc445 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -975,7 +975,7 @@ struct drm_i915_private {
struct workqueue_struct *flip_wq;
/* pm private clock gating functions */
- struct drm_i915_clock_gating_funcs clock_gating_funcs;
+ const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
/* pm display functions */
struct drm_i915_wm_disp_funcs wm_disp;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 826216a115fd..7466f2fca416 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating(struct drm_i915_private *dev_priv)
{
- dev_priv->clock_gating_funcs.init_clock_gating(dev_priv);
+ dev_priv->clock_gating_funcs->init_clock_gating(dev_priv);
}
void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7886,6 +7886,36 @@ static void nop_init_clock_gating(struct
drm_i915_private *dev_priv)
"No clock gating settings or workarounds applied.\n");
}
+#define CG_FUNCS(platform) \
+static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs
= { \
+ .init_clock_gating = platform##_init_clock_gating \
+}
+
+CG_FUNCS(adlp);
+CG_FUNCS(dg1);
+CG_FUNCS(gen12lp);
+CG_FUNCS(icl);
+CG_FUNCS(cfl);
+CG_FUNCS(skl);
+CG_FUNCS(kbl);
+CG_FUNCS(bxt);
+CG_FUNCS(glk);
+CG_FUNCS(bdw);
+CG_FUNCS(chv);
+CG_FUNCS(hsw);
+CG_FUNCS(ivb);
+CG_FUNCS(vlv);
+CG_FUNCS(gen6);
+CG_FUNCS(ilk);
+CG_FUNCS(g4x);
+CG_FUNCS(i965gm);
+CG_FUNCS(i965g);
+CG_FUNCS(gen3);
+CG_FUNCS(i85x);
+CG_FUNCS(i830);
+CG_FUNCS(nop);
+#undef CG_FUNCS
+
/**
* intel_init_clock_gating_hooks - setup the clock gating hooks
* @dev_priv: device private
@@ -7898,52 +7928,52 @@ static void nop_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_ALDERLAKE_P(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
adlp_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_DG1(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
dg1_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 12)
- dev_priv->clock_gating_funcs.init_clock_gating =
gen12lp_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 11)
- dev_priv->clock_gating_funcs.init_clock_gating =
icl_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
cfl_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_SKYLAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
skl_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_KABYLAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
kbl_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_BROXTON(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
bxt_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_GEMINILAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
glk_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_BROADWELL(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
bdw_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
chv_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_HASWELL(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
hsw_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_IVYBRIDGE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
ivb_init_clock_gating;
+
[Intel-gfx] [PATCH 21/23] drm/i915: constify display function vtable
From: Dave Airlie
Make nice clear tables instead of having things in two places.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 81
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 52 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 2e672b988343..8b9727d84435 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3789,7 +3789,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc
*crtc,
drm_WARN_ON(_priv->drm, IS_ERR(temp_crtc_state) || ret);
- dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
+ dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
drm_atomic_state_put(state);
@@ -5994,7 +5994,7 @@ static bool intel_crtc_get_pipe_config(struct
intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- if (!i915->display.get_pipe_config(crtc, crtc_state))
+ if (!i915->display->get_pipe_config(crtc, crtc_state))
return false;
crtc_state->hw.active = true;
@@ -9802,7 +9802,7 @@ static void intel_enable_crtc(struct intel_atomic_state
*state,
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display.crtc_enable(state, crtc);
+ dev_priv->display->crtc_enable(state, crtc);
if (new_crtc_state->bigjoiner_slave)
return;
@@ -9890,7 +9890,7 @@ static void intel_old_crtc_state_disables(struct
intel_atomic_state *state,
*/
intel_crtc_disable_pipe_crc(crtc);
- dev_priv->display.crtc_disable(state, crtc);
+ dev_priv->display->crtc_disable(state, crtc);
crtc->active = false;
intel_fbc_disable(crtc);
intel_disable_shared_dpll(old_crtc_state);
@@ -10269,7 +10269,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
}
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
- dev_priv->display.commit_modeset_enables(state);
+ dev_priv->display->commit_modeset_enables(state);
if (state->modeset) {
intel_encoders_update_complete(state);
@@ -11272,6 +11272,46 @@ static const struct drm_mode_config_funcs
intel_mode_funcs = {
.atomic_state_free = intel_atomic_state_free,
};
+static const struct drm_i915_display_funcs skl_display_funcs = {
+ .get_pipe_config = hsw_get_pipe_config,
+ .crtc_enable = hsw_crtc_enable,
+ .crtc_disable = hsw_crtc_disable,
+ .commit_modeset_enables = skl_commit_modeset_enables,
+ .get_initial_plane_config = skl_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs ddi_display_funcs = {
+ .get_pipe_config = hsw_get_pipe_config,
+ .crtc_enable = hsw_crtc_enable,
+ .crtc_disable = hsw_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs pch_split_display_funcs = {
+ .get_pipe_config = ilk_get_pipe_config,
+ .crtc_enable = ilk_crtc_enable,
+ .crtc_disable = ilk_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs vlv_display_funcs = {
+ .get_pipe_config = i9xx_get_pipe_config,
+ .crtc_enable = valleyview_crtc_enable,
+ .crtc_disable = i9xx_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs i9xx_display_funcs = {
+ .get_pipe_config = i9xx_get_pipe_config,
+ .crtc_enable = i9xx_crtc_enable,
+ .crtc_disable = i9xx_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
/**
* intel_init_display_hooks - initialize the display modesetting hooks
* @dev_priv: device private
@@ -11287,38 +11327,19 @@ void intel_init_display_hooks(struct drm_i915_private
*dev_priv)
intel_dpll_init_clock_hook(dev_priv);
if (DISPLAY_VER(dev_priv) >= 9) {
- dev_priv->display.get_pipe_config = hsw_get_pipe_config;
- dev_priv->display.crtc_enable = hsw_crtc_enable;
- dev_priv->display.crtc_disable = hsw_crtc_disable;
+ dev_priv->display = _display_funcs;
} else if (HAS_DDI(dev_priv)) {
- dev_priv->display.get_pipe_config = hsw_get_pipe_config;
- dev_priv->display.crtc_enable =
[Intel-gfx] [PATCH 20/23] drm/i915: drop unused function ptr and comments.
From: Dave Airlie
There was some excess comments and an unused vtbl ptr.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_drv.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b2c63ed5b8fe..2e8e4db627e3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -409,13 +409,6 @@ struct drm_i915_display_funcs {
void (*crtc_disable)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*commit_modeset_enables)(struct intel_atomic_state *state);
- void (*commit_modeset_disables)(struct intel_atomic_state *state);
-
- /* clock updates for mode set */
- /* cursor updates */
- /* render clock increase/decrease */
- /* display clock increase/decrease */
- /* pll clock increase/decrease */
};
--
2.31.1
[Intel-gfx] [PATCH 19/23] drm/i915: constify the cdclk vtable
From: Dave Airlie
This is a bit of a twisty one since each platform is slightly
different, so might take some more review care.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 300 ++---
drivers/gpu/drm/i915/i915_drv.h| 2 +-
2 files changed, 206 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 27a4a226aa49..f501c748458e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -62,32 +62,32 @@
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
- dev_priv->cdclk_funcs.get_cdclk(dev_priv, cdclk_config);
+ dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config);
}
int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- return dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
+ return dev_priv->cdclk_funcs->bw_calc_min_cdclk(state);
}
static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
+ dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe);
}
static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state
*cdclk_config)
{
- return dev_priv->cdclk_funcs.modeset_calc_cdclk(cdclk_config);
+ return dev_priv->cdclk_funcs->modeset_calc_cdclk(cdclk_config);
}
static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
int cdclk)
{
- return dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
+ return dev_priv->cdclk_funcs->calc_voltage_level(cdclk);
}
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
if (!intel_cdclk_changed(_priv->cdclk.hw, cdclk_config))
return;
- if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
+ if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
return;
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -2886,6 +2886,157 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static struct intel_cdclk_funcs tgl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs ehl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = ehl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs icl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = icl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs bxt_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = bxt_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs skl_cdclk_funcs = {
+ .get_cdclk = skl_get_cdclk,
+ .set_cdclk = skl_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = skl_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs bdw_cdclk_funcs = {
+ .get_cdclk = bdw_get_cdclk,
+ .set_cdclk = bdw_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bdw_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs chv_cdclk_funcs = {
+ .get_cdclk = vlv_get_cdclk,
+ .set_cdclk = chv_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs vlv_cdclk_funcs = {
+ .get_cdclk = vlv_get_cdclk,
+ .set_cdclk = vlv_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs hsw_cdclk_funcs = {
+ .get_cdclk = hsw_get_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk =
[Intel-gfx] [PATCH 17/23] drm/i915: constify the audio function vtable
From: Dave Airlie
Move the functions into read-only tables.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_audio.c | 43 ++
drivers/gpu/drm/i915/i915_drv.h| 2 +-
2 files changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index f539826c0424..0a6ad74d9173 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -848,10 +848,10 @@ void intel_audio_codec_enable(struct intel_encoder
*encoder,
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
- if (dev_priv->audio_funcs.audio_codec_enable)
- dev_priv->audio_funcs.audio_codec_enable(encoder,
-crtc_state,
-conn_state);
+ if (dev_priv->audio_funcs)
+ dev_priv->audio_funcs->audio_codec_enable(encoder,
+ crtc_state,
+ conn_state);
mutex_lock(_priv->av_mutex);
encoder->audio_connector = connector;
@@ -893,10 +893,10 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
- if (dev_priv->audio_funcs.audio_codec_disable)
- dev_priv->audio_funcs.audio_codec_disable(encoder,
- old_crtc_state,
- old_conn_state);
+ if (dev_priv->audio_funcs)
+ dev_priv->audio_funcs->audio_codec_disable(encoder,
+ old_crtc_state,
+ old_conn_state);
mutex_lock(_priv->av_mutex);
encoder->audio_connector = NULL;
@@ -915,6 +915,21 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
}
+static const struct intel_audio_funcs g4x_audio_funcs = {
+ .audio_codec_enable = g4x_audio_codec_enable,
+ .audio_codec_disable = g4x_audio_codec_disable,
+};
+
+static const struct intel_audio_funcs ilk_audio_funcs = {
+ .audio_codec_enable = ilk_audio_codec_enable,
+ .audio_codec_disable = ilk_audio_codec_disable,
+};
+
+static const struct intel_audio_funcs hsw_audio_funcs = {
+ .audio_codec_enable = hsw_audio_codec_enable,
+ .audio_codec_disable = hsw_audio_codec_disable,
+};
+
/**
* intel_init_audio_hooks - Set up chip specific audio hooks
* @dev_priv: device private
@@ -922,17 +937,13 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
{
if (IS_G4X(dev_priv)) {
- dev_priv->audio_funcs.audio_codec_enable =
g4x_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable =
g4x_audio_codec_disable;
+ dev_priv->audio_funcs = _audio_funcs;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- dev_priv->audio_funcs.audio_codec_enable =
ilk_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable =
ilk_audio_codec_disable;
+ dev_priv->audio_funcs = _audio_funcs;
} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->audio_funcs.audio_codec_enable =
hsw_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable =
hsw_audio_codec_disable;
+ dev_priv->audio_funcs = _audio_funcs;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->audio_funcs.audio_codec_enable =
ilk_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable =
ilk_audio_codec_disable;
+ dev_priv->audio_funcs = _audio_funcs;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 28cd816549b8..95f7a7a19a58 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1003,7 +1003,7 @@ struct drm_i915_private {
const struct intel_color_funcs *color_funcs;
/* Display internal audio functions */
- struct intel_audio_funcs audio_funcs;
+ const struct intel_audio_funcs *audio_funcs;
/* Display CDCLK functions */
struct intel_cdclk_funcs cdclk_funcs;
--
2.31.1
[Intel-gfx] [PATCH 18/23] drm/i915: constify the dpll clock vtable
From: Dave Airlie
Most the dpll vtable into read-only memory.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +--
drivers/gpu/drm/i915/display/intel_dpll.c| 48
drivers/gpu/drm/i915/i915_drv.h | 2 +-
3 files changed, 44 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 02a9e684c86b..2e672b988343 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6821,10 +6821,10 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
crtc_state->update_wm_post = true;
if (mode_changed && crtc_state->hw.enable &&
- dev_priv->dpll_funcs.crtc_compute_clock &&
+ dev_priv->dpll_funcs &&
!crtc_state->bigjoiner_slave &&
!drm_WARN_ON(_priv->drm, crtc_state->shared_dpll)) {
- ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
+ ret = dev_priv->dpll_funcs->crtc_compute_clock(crtc_state);
if (ret)
return ret;
}
@@ -8851,7 +8851,7 @@ static void intel_modeset_clear_plls(struct
intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
- if (!dev_priv->dpll_funcs.crtc_compute_clock)
+ if (!dev_priv->dpll_funcs)
return;
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 9326c7cbb05c..bfbbd9903b1a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1363,25 +1363,57 @@ static int i8xx_crtc_compute_clock(struct
intel_crtc_state *crtc_state)
return 0;
}
+static const struct intel_dpll_funcs hsw_dpll_funcs = {
+ .crtc_compute_clock = hsw_crtc_compute_clock
+};
+
+static const struct intel_dpll_funcs ilk_dpll_funcs = {
+ .crtc_compute_clock = ilk_crtc_compute_clock
+};
+
+static const struct intel_dpll_funcs chv_dpll_funcs = {
+ .crtc_compute_clock = chv_crtc_compute_clock
+};
+
+static const struct intel_dpll_funcs vlv_dpll_funcs = {
+ .crtc_compute_clock = vlv_crtc_compute_clock
+};
+
+static const struct intel_dpll_funcs g4x_dpll_funcs = {
+ .crtc_compute_clock = g4x_crtc_compute_clock
+};
+
+static const struct intel_dpll_funcs pnv_dpll_funcs = {
+ .crtc_compute_clock = pnv_crtc_compute_clock
+};
+
+static const struct intel_dpll_funcs i9xx_dpll_funcs = {
+ .crtc_compute_clock = i9xx_crtc_compute_clock
+};
+
+static const struct intel_dpll_funcs i8xx_dpll_funcs = {
+ .crtc_compute_clock = i8xx_crtc_compute_clock
+};
+
void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
hsw_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (HAS_PCH_SPLIT(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
ilk_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
chv_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
vlv_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_G4X(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
g4x_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
pnv_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (DISPLAY_VER(dev_priv) != 2)
- dev_priv->dpll_funcs.crtc_compute_clock =
i9xx_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else
- dev_priv->dpll_funcs.crtc_compute_clock =
i8xx_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
}
static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 95f7a7a19a58..5ed624b9c3cc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -994,7 +994,7 @@ struct drm_i915_private {
const struct intel_fdi_funcs *fdi_funcs;
/* display pll funcs */
- struct intel_dpll_funcs dpll_funcs;
+ const struct intel_dpll_funcs *dpll_funcs;
/* Display functions */
struct drm_i915_display_funcs display;
--
2.31.1
[Intel-gfx] [PATCH 16/23] drm/i915: constify color function vtable.
From: Dave Airlie
This clarifies quite well what functions get used on what platforms
instead of having to decipher the old tree.
v2: fixed IVB mistake (Jani)
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_color.c | 138 ++---
drivers/gpu/drm/i915/i915_drv.h| 2 +-
2 files changed, 93 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index ed79075158dd..f5923f1c38bd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct
intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->color_funcs.load_luts(crtc_state);
+ dev_priv->color_funcs->load_luts(crtc_state);
}
void intel_color_commit(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->color_funcs.color_commit(crtc_state);
+ dev_priv->color_funcs->color_commit(crtc_state);
}
static bool intel_can_preload_luts(const struct intel_crtc_state
*new_crtc_state)
@@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- return dev_priv->color_funcs.color_check(crtc_state);
+ return dev_priv->color_funcs->color_check(crtc_state);
}
void intel_color_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (dev_priv->color_funcs.read_luts)
- dev_priv->color_funcs.read_luts(crtc_state);
+ if (dev_priv->color_funcs->read_luts)
+ dev_priv->color_funcs->read_luts(crtc_state);
}
static bool need_plane_update(struct intel_plane *plane,
@@ -2092,6 +2092,76 @@ static void icl_read_luts(struct intel_crtc_state
*crtc_state)
}
}
+static const struct intel_color_funcs chv_color_funcs = {
+ .color_check = chv_color_check,
+ .color_commit = i9xx_color_commit,
+ .load_luts = chv_load_luts,
+ .read_luts = chv_read_luts,
+};
+
+static const struct intel_color_funcs i965_color_funcs = {
+ .color_check = i9xx_color_check,
+ .color_commit = i9xx_color_commit,
+ .load_luts = i965_load_luts,
+ .read_luts = i965_read_luts,
+};
+
+static const struct intel_color_funcs i9xx_color_funcs = {
+ .color_check = i9xx_color_check,
+ .color_commit = i9xx_color_commit,
+ .load_luts = i9xx_load_luts,
+ .read_luts = i9xx_read_luts,
+};
+
+static const struct intel_color_funcs icl_color_funcs = {
+ .color_check = icl_color_check,
+ .color_commit = skl_color_commit,
+ .load_luts = icl_load_luts,
+ .read_luts = icl_read_luts,
+};
+
+static const struct intel_color_funcs glk_color_funcs = {
+ .color_check = glk_color_check,
+ .color_commit = skl_color_commit,
+ .load_luts = glk_load_luts,
+ .read_luts = glk_read_luts,
+};
+
+static const struct intel_color_funcs skl_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = skl_color_commit,
+ .load_luts = bdw_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs bdw_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = hsw_color_commit,
+ .load_luts = bdw_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs hsw_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = hsw_color_commit,
+ .load_luts = ivb_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs ivb_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = ilk_color_commit,
+ .load_luts = ivb_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs ilk_color_funcs = {
+ .color_check = ilk_color_check,
+ .color_commit = ilk_color_commit,
+ .load_luts = ilk_load_luts,
+ .read_luts = ilk_read_luts,
+};
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2101,52 +2171,28 @@ void intel_color_init(struct intel_crtc *crtc)
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->color_funcs.color_check = chv_color_check;
- dev_priv->color_funcs.color_commit = i9xx_color_commit;
- dev_priv->color_funcs.load_luts = chv_load_luts;
- dev_priv->color_funcs.read_luts = chv_read_luts;
+ dev_priv->color_funcs = _color_funcs;
} else if (DISPLAY_VER(dev_priv) >= 4) {
-
[Intel-gfx] [PATCH 15/23] drm/i915: constify hotplug function vtable.
From: Dave Airlie
Use a macro to avoid mistakes, this type of macro is only used
in a couple of places.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 4 +--
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 28 +++-
3 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 05f76aba4f8a..3c1cec953b42 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct
drm_i915_private *dev_priv)
static void intel_hpd_irq_setup(struct drm_i915_private *i915)
{
- if (i915->display_irqs_enabled && i915->hotplug_funcs.hpd_irq_setup)
- i915->hotplug_funcs.hpd_irq_setup(i915);
+ if (i915->display_irqs_enabled && i915->hotplug_funcs->hpd_irq_setup)
+ i915->hotplug_funcs->hpd_irq_setup(i915);
}
static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bb44ef4f6356..af1960856f19 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -988,7 +988,7 @@ struct drm_i915_private {
struct drm_i915_wm_disp_funcs wm_disp;
/* irq display functions */
- struct intel_hotplug_funcs hotplug_funcs;
+ const struct intel_hotplug_funcs *hotplug_funcs;
/* fdi display functions */
const struct intel_fdi_funcs *fdi_funcs;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c35065f8f429..5c3baa470057 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4345,6 +4345,20 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
return ret;
}
+#define HPD_FUNCS(platform) \
+static const struct intel_hotplug_funcs platform##_hpd_funcs = { \
+ .hpd_irq_setup = platform##_hpd_irq_setup\
+}
+
+HPD_FUNCS(i915);
+HPD_FUNCS(dg1);
+HPD_FUNCS(gen11);
+HPD_FUNCS(bxt);
+HPD_FUNCS(icp);
+HPD_FUNCS(spt);
+HPD_FUNCS(ilk);
+#undef HPD_FUNCS
+
/**
* intel_irq_init - initializes irq support
* @dev_priv: i915 device instance
@@ -4395,20 +4409,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
- dev_priv->hotplug_funcs.hpd_irq_setup =
i915_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
} else {
if (HAS_PCH_DG1(dev_priv))
- dev_priv->hotplug_funcs.hpd_irq_setup =
dg1_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->hotplug_funcs.hpd_irq_setup =
gen11_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->hotplug_funcs.hpd_irq_setup =
bxt_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- dev_priv->hotplug_funcs.hpd_irq_setup =
icp_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- dev_priv->hotplug_funcs.hpd_irq_setup =
spt_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else
- dev_priv->hotplug_funcs.hpd_irq_setup =
ilk_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
}
}
--
2.31.1
[Intel-gfx] [PATCH 14/23] drm/i915: constify fdi link training vtable
From: Dave Airlie
Put the vtable into ro memory.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fdi.c | 20
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index 94bb7e039fe7..148fb50035ff 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -15,7 +15,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
+ dev_priv->fdi_funcs->fdi_link_train(crtc, crtc_state);
}
/* units of 100MHz */
@@ -1013,15 +1013,27 @@ void lpt_fdi_program_mphy(struct drm_i915_private
*dev_priv)
intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
}
+static const struct intel_fdi_funcs ilk_funcs = {
+ .fdi_link_train = ilk_fdi_link_train,
+};
+
+static const struct intel_fdi_funcs gen6_funcs = {
+ .fdi_link_train = gen6_fdi_link_train,
+};
+
+static const struct intel_fdi_funcs ivb_funcs = {
+ .fdi_link_train = ivb_manual_fdi_link_train,
+};
+
void
intel_fdi_init_hook(struct drm_i915_private *dev_priv)
{
if (IS_IRONLAKE(dev_priv)) {
- dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
+ dev_priv->fdi_funcs = _funcs;
} else if (IS_SANDYBRIDGE(dev_priv)) {
- dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
+ dev_priv->fdi_funcs = _funcs;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
- dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
+ dev_priv->fdi_funcs = _funcs;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 575c46df5336..bb44ef4f6356 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -991,7 +991,7 @@ struct drm_i915_private {
struct intel_hotplug_funcs hotplug_funcs;
/* fdi display functions */
- struct intel_fdi_funcs fdi_funcs;
+ const struct intel_fdi_funcs *fdi_funcs;
/* display pll funcs */
struct intel_dpll_funcs dpll_funcs;
--
2.31.1
[Intel-gfx] [PATCH 13/23] drm/i915: split the dpll clock compute out from display vtable.
From: Dave Airlie
this single function might be possible to merge later, but
for now it's simple to just split it out.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dpll.c| 16
drivers/gpu/drm/i915/i915_drv.h | 8 +++-
3 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 413bc4667e47..02a9e684c86b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6821,10 +6821,10 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
crtc_state->update_wm_post = true;
if (mode_changed && crtc_state->hw.enable &&
- dev_priv->display.crtc_compute_clock &&
+ dev_priv->dpll_funcs.crtc_compute_clock &&
!crtc_state->bigjoiner_slave &&
!drm_WARN_ON(_priv->drm, crtc_state->shared_dpll)) {
- ret = dev_priv->display.crtc_compute_clock(crtc_state);
+ ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
if (ret)
return ret;
}
@@ -8851,7 +8851,7 @@ static void intel_modeset_clear_plls(struct
intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
- if (!dev_priv->display.crtc_compute_clock)
+ if (!dev_priv->dpll_funcs.crtc_compute_clock)
return;
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 210f91f4a576..9326c7cbb05c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1367,21 +1367,21 @@ void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
- dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
hsw_crtc_compute_clock;
else if (HAS_PCH_SPLIT(dev_priv))
- dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
ilk_crtc_compute_clock;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
chv_crtc_compute_clock;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
vlv_crtc_compute_clock;
else if (IS_G4X(dev_priv))
- dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
g4x_crtc_compute_clock;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
pnv_crtc_compute_clock;
else if (DISPLAY_VER(dev_priv) != 2)
- dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
i9xx_crtc_compute_clock;
else
- dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
i8xx_crtc_compute_clock;
}
static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 680301bce3ab..575c46df5336 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -393,6 +393,10 @@ struct intel_fdi_funcs {
const struct intel_crtc_state *crtc_state);
};
+struct intel_dpll_funcs {
+ int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
+};
+
struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -400,7 +404,6 @@ struct drm_i915_display_funcs {
struct intel_crtc_state *);
void (*get_initial_plane_config)(struct intel_crtc *,
struct intel_initial_plane_config *);
- int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
void (*crtc_enable)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*crtc_disable)(struct intel_atomic_state *state,
@@ -990,6 +993,9 @@ struct drm_i915_private {
/* fdi display functions */
struct intel_fdi_funcs fdi_funcs;
+ /* display pll funcs */
+ struct intel_dpll_funcs dpll_funcs;
+
/* Display
[Intel-gfx] [PATCH 12/23] drm/i915: split fdi link training from display vtable.
From: Dave Airlie
It may make sense to merge this with display again later,
however the fdi use of the vtable is limited to only a
few generations.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fdi.c | 8
drivers/gpu/drm/i915/i915_drv.h | 11 ---
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index 339243399a65..94bb7e039fe7 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -15,7 +15,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- dev_priv->display.fdi_link_train(crtc, crtc_state);
+ dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
}
/* units of 100MHz */
@@ -1017,11 +1017,11 @@ void
intel_fdi_init_hook(struct drm_i915_private *dev_priv)
{
if (IS_IRONLAKE(dev_priv)) {
- dev_priv->display.fdi_link_train = ilk_fdi_link_train;
+ dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
} else if (IS_SANDYBRIDGE(dev_priv)) {
- dev_priv->display.fdi_link_train = gen6_fdi_link_train;
+ dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
- dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
+ dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index caf854d251a6..680301bce3ab 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -388,6 +388,11 @@ struct intel_hotplug_funcs {
void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
};
+struct intel_fdi_funcs {
+ void (*fdi_link_train)(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state);
+};
+
struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -403,9 +408,6 @@ struct drm_i915_display_funcs {
void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*commit_modeset_disables)(struct intel_atomic_state *state);
- void (*fdi_link_train)(struct intel_crtc *crtc,
- const struct intel_crtc_state *crtc_state);
-
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
@@ -985,6 +987,9 @@ struct drm_i915_private {
/* irq display functions */
struct intel_hotplug_funcs hotplug_funcs;
+ /* fdi display functions */
+ struct intel_fdi_funcs fdi_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
--
2.31.1
[Intel-gfx] [PATCH 10/23] drm/i915: split cdclk functions from display vtable.
From: Dave Airlie
This moves all the cdclk related functions into their own vtable.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 142 ++---
drivers/gpu/drm/i915/i915_drv.h| 8 +-
2 files changed, 78 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0e09f259914f..27a4a226aa49 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -62,32 +62,32 @@
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
- dev_priv->display.get_cdclk(dev_priv, cdclk_config);
+ dev_priv->cdclk_funcs.get_cdclk(dev_priv, cdclk_config);
}
int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- return dev_priv->display.bw_calc_min_cdclk(state);
+ return dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
}
static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+ dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
}
static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state
*cdclk_config)
{
- return dev_priv->display.modeset_calc_cdclk(cdclk_config);
+ return dev_priv->cdclk_funcs.modeset_calc_cdclk(cdclk_config);
}
static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
int cdclk)
{
- return dev_priv->display.calc_voltage_level(cdclk);
+ return dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
}
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
if (!intel_cdclk_changed(_priv->cdclk.hw, cdclk_config))
return;
- if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->display.set_cdclk))
+ if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
return;
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -2893,119 +2893,119 @@ u32 intel_read_rawclk(struct drm_i915_private
*dev_priv)
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
if (IS_DG2(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk =
bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level =
tgl_calc_voltage_level;
dev_priv->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk =
bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level =
tgl_calc_voltage_level;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
else
dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk =
bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level =
tgl_calc_voltage_level;
[Intel-gfx] [PATCH 11/23] drm/i915: split irq hotplug function from display vtable
From: Dave Airlie
This provide a service from irq to display, so make it separate
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 9 -
drivers/gpu/drm/i915/i915_irq.c | 14 +++---
3 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 47c85ac97c87..05f76aba4f8a 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct
drm_i915_private *dev_priv)
static void intel_hpd_irq_setup(struct drm_i915_private *i915)
{
- if (i915->display_irqs_enabled && i915->display.hpd_irq_setup)
- i915->display.hpd_irq_setup(i915);
+ if (i915->display_irqs_enabled && i915->hotplug_funcs.hpd_irq_setup)
+ i915->hotplug_funcs.hpd_irq_setup(i915);
}
static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 11298f583cc0..caf854d251a6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -384,6 +384,10 @@ struct intel_cdclk_funcs {
u8 (*calc_voltage_level)(int cdclk);
};
+struct intel_hotplug_funcs {
+ void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
+};
+
struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -401,7 +405,7 @@ struct drm_i915_display_funcs {
void (*fdi_link_train)(struct intel_crtc *crtc,
const struct intel_crtc_state *crtc_state);
- void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
+
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
@@ -978,6 +982,9 @@ struct drm_i915_private {
/* pm display functions */
struct drm_i915_wm_disp_funcs wm_disp;
+ /* irq display functions */
+ struct intel_hotplug_funcs hotplug_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0a1681384c84..c35065f8f429 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4395,20 +4395,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
i915_hpd_irq_setup;
} else {
if (HAS_PCH_DG1(dev_priv))
- dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
dg1_hpd_irq_setup;
else if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
gen11_hpd_irq_setup;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
bxt_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
icp_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
spt_hpd_irq_setup;
else
- dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
ilk_hpd_irq_setup;
}
}
--
2.31.1
[Intel-gfx] [PATCH 07/23] drm/i915: split watermark vfuncs from display vtable.
From: Dave Airlie
These are the watermark api between display and pm.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 35 -
drivers/gpu/drm/i915/i915_drv.h | 24
drivers/gpu/drm/i915/intel_pm.c | 40 ++--
3 files changed, 54 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f2678d26cd17..413bc4667e47 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -162,16 +162,16 @@ static void intel_modeset_setup_hw_state(struct
drm_device *dev,
*/
static void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
- if (dev_priv->display.update_wm)
- dev_priv->display.update_wm(dev_priv);
+ if (dev_priv->wm_disp.update_wm)
+ dev_priv->wm_disp.update_wm(dev_priv);
}
static int intel_compute_pipe_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.compute_pipe_wm)
- return dev_priv->display.compute_pipe_wm(state, crtc);
+ if (dev_priv->wm_disp.compute_pipe_wm)
+ return dev_priv->wm_disp.compute_pipe_wm(state, crtc);
return 0;
}
@@ -180,10 +180,10 @@ static int intel_compute_intermediate_wm(struct
intel_atomic_state *state,
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
if (drm_WARN_ON(_priv->drm,
- !dev_priv->display.compute_pipe_wm))
+ !dev_priv->wm_disp.compute_pipe_wm))
return 0;
- if (dev_priv->display.compute_pipe_wm)
- return dev_priv->display.compute_intermediate_wm(state, crtc);
+ if (dev_priv->wm_disp.compute_pipe_wm)
+ return dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
return 0;
}
@@ -191,8 +191,8 @@ static bool intel_initial_watermarks(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.initial_watermarks) {
- dev_priv->display.initial_watermarks(state, crtc);
+ if (dev_priv->wm_disp.initial_watermarks) {
+ dev_priv->wm_disp.initial_watermarks(state, crtc);
return true;
}
return false;
@@ -202,23 +202,23 @@ static void intel_atomic_update_watermarks(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.atomic_update_watermarks)
- dev_priv->display.atomic_update_watermarks(state, crtc);
+ if (dev_priv->wm_disp.atomic_update_watermarks)
+ dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
}
static void intel_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.optimize_watermarks)
- dev_priv->display.optimize_watermarks(state, crtc);
+ if (dev_priv->wm_disp.optimize_watermarks)
+ dev_priv->wm_disp.optimize_watermarks(state, crtc);
}
static void intel_compute_global_watermarks(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.compute_global_watermarks)
- dev_priv->display.compute_global_watermarks(state);
+ if (dev_priv->wm_disp.compute_global_watermarks)
+ dev_priv->wm_disp.compute_global_watermarks(state);
}
/* returns HPLL frequency in kHz */
@@ -3669,6 +3669,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state
*state,
if (!intel_initial_watermarks(state, crtc))
intel_update_watermarks(dev_priv);
+
intel_enable_pipe(new_crtc_state);
intel_crtc_vblank_on(new_crtc_state);
@@ -3734,7 +3735,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state
*state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
- if (!dev_priv->display.initial_watermarks)
+ if (!dev_priv->wm_disp.initial_watermarks)
intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
@@ -11387,7 +11388,7 @@ static void sanitize_watermarks(struct drm_i915_private
*dev_priv)
int i;
/* Only supported on platforms that use atomic watermark design */
- if (!dev_priv->display.optimize_watermarks)
+ if (!dev_priv->wm_disp.optimize_watermarks)
[Intel-gfx] [PATCH 09/23] drm/i915: split audio functions from display vtable
From: Dave Airlie
These are only used internally in the audio code
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_audio.c | 24 +++---
drivers/gpu/drm/i915/i915_drv.h| 19 +++--
2 files changed, 25 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 532237588511..f539826c0424 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -848,8 +848,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
- if (dev_priv->display.audio_codec_enable)
- dev_priv->display.audio_codec_enable(encoder,
+ if (dev_priv->audio_funcs.audio_codec_enable)
+ dev_priv->audio_funcs.audio_codec_enable(encoder,
crtc_state,
conn_state);
@@ -893,8 +893,8 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
- if (dev_priv->display.audio_codec_disable)
- dev_priv->display.audio_codec_disable(encoder,
+ if (dev_priv->audio_funcs.audio_codec_disable)
+ dev_priv->audio_funcs.audio_codec_disable(encoder,
old_crtc_state,
old_conn_state);
@@ -922,17 +922,17 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
{
if (IS_G4X(dev_priv)) {
- dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
- dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable =
g4x_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable =
g4x_audio_codec_disable;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
- dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable =
ilk_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable =
ilk_audio_codec_disable;
} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
- dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable =
hsw_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable =
hsw_audio_codec_disable;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
- dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable =
ilk_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable =
ilk_audio_codec_disable;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8930bf2db226..1ba94dee683e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -364,6 +364,15 @@ struct intel_color_funcs {
void (*read_luts)(struct intel_crtc_state *crtc_state);
};
+struct intel_audio_funcs {
+ void (*audio_codec_enable)(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state
*conn_state);
+ void (*audio_codec_disable)(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*old_crtc_state,
+ const struct drm_connector_state
*old_conn_state);
+};
+
struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config);
@@ -386,12 +395,7 @@ struct drm_i915_display_funcs {
struct intel_crtc *crtc);
void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*commit_modeset_disables)(struct intel_atomic_state *state);
- void (*audio_codec_enable)(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state
*conn_state);
- void (*audio_codec_disable)(struct intel_encoder *encoder,
- const struct intel_crtc_state
*old_crtc_state,
- const struct
[Intel-gfx] [PATCH 08/23] drm/i915: split color functions from display vtable
From: Dave Airlie
These are only used internally in the color module
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_color.c | 64 +++---
drivers/gpu/drm/i915/i915_drv.h| 39 +++--
2 files changed, 54 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index afcb4bf3826c..ed79075158dd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct
intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->display.load_luts(crtc_state);
+ dev_priv->color_funcs.load_luts(crtc_state);
}
void intel_color_commit(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->display.color_commit(crtc_state);
+ dev_priv->color_funcs.color_commit(crtc_state);
}
static bool intel_can_preload_luts(const struct intel_crtc_state
*new_crtc_state)
@@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- return dev_priv->display.color_check(crtc_state);
+ return dev_priv->color_funcs.color_check(crtc_state);
}
void intel_color_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (dev_priv->display.read_luts)
- dev_priv->display.read_luts(crtc_state);
+ if (dev_priv->color_funcs.read_luts)
+ dev_priv->color_funcs.read_luts(crtc_state);
}
static bool need_plane_update(struct intel_plane *plane,
@@ -2101,51 +2101,51 @@ void intel_color_init(struct intel_crtc *crtc)
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.color_check = chv_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = chv_load_luts;
- dev_priv->display.read_luts = chv_read_luts;
+ dev_priv->color_funcs.color_check = chv_color_check;
+ dev_priv->color_funcs.color_commit = i9xx_color_commit;
+ dev_priv->color_funcs.load_luts = chv_load_luts;
+ dev_priv->color_funcs.read_luts = chv_read_luts;
} else if (DISPLAY_VER(dev_priv) >= 4) {
- dev_priv->display.color_check = i9xx_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = i965_load_luts;
- dev_priv->display.read_luts = i965_read_luts;
+ dev_priv->color_funcs.color_check = i9xx_color_check;
+ dev_priv->color_funcs.color_commit = i9xx_color_commit;
+ dev_priv->color_funcs.load_luts = i965_load_luts;
+ dev_priv->color_funcs.read_luts = i965_read_luts;
} else {
- dev_priv->display.color_check = i9xx_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = i9xx_load_luts;
- dev_priv->display.read_luts = i9xx_read_luts;
+ dev_priv->color_funcs.color_check = i9xx_color_check;
+ dev_priv->color_funcs.color_commit = i9xx_color_commit;
+ dev_priv->color_funcs.load_luts = i9xx_load_luts;
+ dev_priv->color_funcs.read_luts = i9xx_read_luts;
}
} else {
if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->display.color_check = icl_color_check;
+ dev_priv->color_funcs.color_check = icl_color_check;
else if (DISPLAY_VER(dev_priv) >= 10)
- dev_priv->display.color_check = glk_color_check;
+ dev_priv->color_funcs.color_check = glk_color_check;
else if (DISPLAY_VER(dev_priv) >= 7)
- dev_priv->display.color_check = ivb_color_check;
+ dev_priv->color_funcs.color_check = ivb_color_check;
else
- dev_priv->display.color_check = ilk_color_check;
+ dev_priv->color_funcs.color_check = ilk_color_check;
if (DISPLAY_VER(dev_priv) >= 9)
- dev_priv->display.color_commit = skl_color_commit;
+ dev_priv->color_funcs.color_commit = skl_color_commit;
else if (IS_BROADWELL(dev_priv) ||
[Intel-gfx] [PATCH 06/23] drm/i915: split clock gating init from display vtable
From: Dave Airlie
This function is only used inside intel_pm.c
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_drv.h | 9 ++-
drivers/gpu/drm/i915/intel_pm.c | 48 -
2 files changed, 32 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 894c883044ee..48d30b967def 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -323,6 +323,11 @@ struct intel_crtc;
struct intel_limit;
struct dpll;
+/* functions used internal in intel_pm.c */
+struct drm_i915_clock_gating_funcs {
+ void (*init_clock_gating)(struct drm_i915_private *dev_priv);
+};
+
struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config);
@@ -365,7 +370,6 @@ struct drm_i915_display_funcs {
const struct drm_connector_state
*old_conn_state);
void (*fdi_link_train)(struct intel_crtc *crtc,
const struct intel_crtc_state *crtc_state);
- void (*init_clock_gating)(struct drm_i915_private *dev_priv);
void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
/* clock updates for mode set */
/* cursor updates */
@@ -954,6 +958,9 @@ struct drm_i915_private {
/* unbound hipri wq for page flips/plane updates */
struct workqueue_struct *flip_wq;
+ /* pm private clock gating functions */
+ struct drm_i915_clock_gating_funcs clock_gating_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4054c6f7a2f9..add50ff01d7c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating(struct drm_i915_private *dev_priv)
{
- dev_priv->display.init_clock_gating(dev_priv);
+ dev_priv->clock_gating_funcs.init_clock_gating(dev_priv);
}
void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7898,52 +7898,52 @@ static void nop_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_ALDERLAKE_P(dev_priv))
- dev_priv->display.init_clock_gating = adlp_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
adlp_init_clock_gating;
else if (IS_DG1(dev_priv))
- dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
dg1_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 12)
- dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
gen12lp_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 11)
- dev_priv->display.init_clock_gating = icl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
icl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
- dev_priv->display.init_clock_gating = cfl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
cfl_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
- dev_priv->display.init_clock_gating = skl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
skl_init_clock_gating;
else if (IS_KABYLAKE(dev_priv))
- dev_priv->display.init_clock_gating = kbl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
kbl_init_clock_gating;
else if (IS_BROXTON(dev_priv))
- dev_priv->display.init_clock_gating = bxt_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
bxt_init_clock_gating;
else if (IS_GEMINILAKE(dev_priv))
- dev_priv->display.init_clock_gating = glk_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
glk_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
- dev_priv->display.init_clock_gating = bdw_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
bdw_init_clock_gating;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->display.init_clock_gating = chv_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
chv_init_clock_gating;
else if (IS_HASWELL(dev_priv))
- dev_priv->display.init_clock_gating = hsw_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
hsw_init_clock_gating;
else if (IS_IVYBRIDGE(dev_priv))
-
[Intel-gfx] [PATCH 05/23] drm/i915/display: add intel_fdi_link_train wrapper.
From: Dave Airlie
This wraps the fdi link training vfunc to make it clearer.
Suggested by Jani.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 8
drivers/gpu/drm/i915/display/intel_fdi.h | 2 ++
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8d2147880fa1..f2678d26cd17 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2156,7 +2156,7 @@ static void ilk_pch_enable(const struct
intel_atomic_state *state,
assert_pch_transcoder_disabled(dev_priv, pipe);
/* For PCH output, training FDI link */
- dev_priv->display.fdi_link_train(crtc, crtc_state);
+ intel_fdi_link_train(crtc, crtc_state);
/* We need to program the right clock selection before writing the pixel
* mutliplier into the DPLL. */
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index fc09b781f15f..339243399a65 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -10,6 +10,14 @@
#include "intel_fdi.h"
#include "intel_sideband.h"
+void intel_fdi_link_train(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ dev_priv->display.fdi_link_train(crtc, crtc_state);
+}
+
/* units of 100MHz */
static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
{
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h
b/drivers/gpu/drm/i915/display/intel_fdi.h
index 60acf2133145..61cb216a09f5 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.h
+++ b/drivers/gpu/drm/i915/display/intel_fdi.h
@@ -26,4 +26,6 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
void intel_fdi_pll_freq_update(struct drm_i915_private *i915);
void lpt_fdi_program_mphy(struct drm_i915_private *i915);
+void intel_fdi_link_train(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state);
#endif
--
2.31.1
[Intel-gfx] [PATCH 04/23] drm/i915: add wrappers around cdclk vtable funcs.
From: Dave Airlie
This adds wrappers around all the vtable callers so they are in
one place.
Suggested by Jani.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_cdclk.c| 47 +++
drivers/gpu/drm/i915/display/intel_cdclk.h| 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
.../drm/i915/display/intel_display_power.c| 2 +-
4 files changed, 44 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9aec17b33819..0e09f259914f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -59,6 +59,37 @@
* dividers can be programmed correctly.
*/
+void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_config *cdclk_config)
+{
+ dev_priv->display.get_cdclk(dev_priv, cdclk_config);
+}
+
+int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ return dev_priv->display.bw_calc_min_cdclk(state);
+}
+
+static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *cdclk_config,
+ enum pipe pipe)
+{
+ dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+}
+
+static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_state
*cdclk_config)
+{
+ return dev_priv->display.modeset_calc_cdclk(cdclk_config);
+}
+
+static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
+int cdclk)
+{
+ return dev_priv->display.calc_voltage_level(cdclk);
+}
+
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
@@ -1466,7 +1497,7 @@ static void bxt_get_cdclk(struct drm_i915_private
*dev_priv,
* at least what the CDCLK frequency requires.
*/
cdclk_config->voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk);
}
static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1777,7 +1808,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private
*dev_priv)
cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
cdclk_config.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
bxt_set_cdclk(dev_priv, _config, INVALID_PIPE);
}
@@ -1789,7 +1820,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private
*dev_priv)
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
cdclk_config.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
bxt_set_cdclk(dev_priv, _config, INVALID_PIPE);
}
@@ -1956,7 +1987,7 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
_priv->gmbus_mutex);
}
- dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+ intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
for_each_intel_dp(_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2424,7 +2455,7 @@ static int bxt_modeset_calc_cdclk(struct
intel_cdclk_state *cdclk_state)
cdclk_state->logical.cdclk = cdclk;
cdclk_state->logical.voltage_level =
max_t(int, min_voltage_level,
- dev_priv->display.calc_voltage_level(cdclk));
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk));
if (!cdclk_state->active_pipes) {
cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
@@ -2433,7 +2464,7 @@ static int bxt_modeset_calc_cdclk(struct
intel_cdclk_state *cdclk_state)
cdclk_state->actual.vco = vco;
cdclk_state->actual.cdclk = cdclk;
cdclk_state->actual.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk);
} else {
cdclk_state->actual = cdclk_state->logical;
}
@@ -2525,7 +2556,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
new_cdclk_state->active_pipes =
intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
- ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
+ ret =
[Intel-gfx] [PATCH 02/23] drm/i915: make update_wm take a dev_priv.
From: Dave Airlie
The crtc was never being used here.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 18 ++
drivers/gpu/drm/i915/intel_pm.h | 2 +-
4 files changed, 13 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 134c792e1dbd..e62f8317cbda 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2374,7 +2374,7 @@ static void intel_post_plane_update(struct
intel_atomic_state *state,
intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
hsw_enable_ips(new_crtc_state);
@@ -2531,7 +2531,7 @@ static void intel_pre_plane_update(struct
intel_atomic_state *state,
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
else if (new_crtc_state->update_wm_pre)
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
}
/*
@@ -3578,7 +3578,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state
*state,
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
else
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
intel_enable_pipe(new_crtc_state);
intel_crtc_vblank_on(new_crtc_state);
@@ -3645,7 +3645,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state
*state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
if (!dev_priv->display.initial_watermarks)
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
if (IS_I830(dev_priv))
@@ -3721,7 +3721,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc
*crtc,
encoder->base.crtc = NULL;
intel_fbc_disable(crtc);
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
intel_disable_shared_dpll(crtc_state);
intel_display_power_put_all_in_set(dev_priv,
>enabled_power_domains);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fc546d2ff0fc..894c883044ee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -341,7 +341,7 @@ struct drm_i915_display_funcs {
void (*optimize_watermarks)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*compute_global_watermarks)(struct intel_atomic_state *state);
- void (*update_wm)(struct intel_crtc *crtc);
+ void (*update_wm)(struct drm_i915_private *dev_priv);
int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
u8 (*calc_voltage_level)(int cdclk);
/* Returns the active state of the crtc, and if the crtc is active,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d9993eb3730d..406baa49e6ad 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -881,9 +881,8 @@ static struct intel_crtc *single_enabled_crtc(struct
drm_i915_private *dev_priv)
return enabled;
}
-static void pnv_update_wm(struct intel_crtc *unused_crtc)
+static void pnv_update_wm(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
const struct cxsr_latency *latency;
u32 reg;
@@ -2253,9 +2252,8 @@ static void vlv_optimize_watermarks(struct
intel_atomic_state *state,
mutex_unlock(_priv->wm.wm_mutex);
}
-static void i965_update_wm(struct intel_crtc *unused_crtc)
+static void i965_update_wm(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
int srwm = 1;
int cursor_sr = 16;
@@ -2329,9 +2327,8 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
#undef FW_WM
-static void i9xx_update_wm(struct intel_crtc *unused_crtc)
+static void i9xx_update_wm(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
const struct intel_watermark_params *wm_info;
u32 fwater_lo;
u32 fwater_hi;
@@ -2481,9 +2478,8 @@ static void i9xx_update_wm(struct
[Intel-gfx] [PATCH 03/23] drm/i915/wm: provide wrappers around watermark vfuncs calls
From: Dave Airlie
This moves one wrapper from the pm->display side, and creates
wrappers for all the others, this should simplify things later.
One thing to note is that the code checks the existance of some
of these ptrs, so the wrappers are a bit complicated by that.
Suggested by Jani.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 187 ---
drivers/gpu/drm/i915/intel_pm.c | 39
drivers/gpu/drm/i915/intel_pm.h | 1 -
3 files changed, 123 insertions(+), 104 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e62f8317cbda..3d8afa9f3237 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -126,6 +126,101 @@ static void ilk_pfit_enable(const struct intel_crtc_state
*crtc_state);
static void intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx);
+
+/**
+ * intel_update_watermarks - update FIFO watermark values based on current
modes
+ * @crtc: the #intel_crtc on which to compute the WM
+ *
+ * Calculate watermark values for the various WM regs based on current mode
+ * and plane configuration.
+ *
+ * There are several cases to deal with here:
+ * - normal (i.e. non-self-refresh)
+ * - self-refresh (SR) mode
+ * - lines are large relative to FIFO size (buffer can hold up to 2)
+ * - lines are small relative to FIFO size (buffer can hold more than 2
+ * lines), so need to account for TLB latency
+ *
+ * The normal calculation is:
+ * watermark = dotclock * bytes per pixel * latency
+ * where latency is platform & configuration dependent (we assume pessimal
+ * values here).
+ *
+ * The SR calculation is:
+ * watermark = (trunc(latency/line time)+1) * surface width *
+ * bytes per pixel
+ * where
+ * line time = htotal / dotclock
+ * surface width = hdisplay for normal plane and 64 for cursor
+ * and latency is assumed to be high, as above.
+ *
+ * The final value programmed to the register should always be rounded up,
+ * and include an extra 2 entries to account for clock crossings.
+ *
+ * We don't use the sprite, so we can ignore that. And on Crestline we have
+ * to set the non-SR watermarks to 8.
+ */
+static void intel_update_watermarks(struct drm_i915_private *dev_priv)
+{
+ if (dev_priv->display.update_wm)
+ dev_priv->display.update_wm(dev_priv);
+}
+
+static int intel_compute_pipe_wm(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.compute_pipe_wm)
+ return dev_priv->display.compute_pipe_wm(state, crtc);
+ return 0;
+}
+
+static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (drm_WARN_ON(_priv->drm,
+ !dev_priv->display.compute_pipe_wm))
+ return 0;
+ if (dev_priv->display.compute_pipe_wm)
+ return dev_priv->display.compute_intermediate_wm(state, crtc);
+ return 0;
+}
+
+static bool intel_initial_watermarks(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.initial_watermarks) {
+ dev_priv->display.initial_watermarks(state, crtc);
+ return true;
+ }
+ return false;
+}
+
+static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.atomic_update_watermarks)
+ dev_priv->display.atomic_update_watermarks(state, crtc);
+}
+
+static void intel_optimize_watermarks(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.optimize_watermarks)
+ dev_priv->display.optimize_watermarks(state, crtc);
+}
+
+static void intel_compute_global_watermarks(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.compute_global_watermarks)
+ dev_priv->display.compute_global_watermarks(state);
+}
+
/* returns HPLL frequency in kHz */
int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
{
@@ -2528,9 +2623,8 @@ static void intel_pre_plane_update(struct
intel_atomic_state *state,
* we'll continue to update watermarks the
[Intel-gfx] [PATCH 01/23] drm/i915/pm: drop get_fifo_size vfunc.
From: Dave Airlie
The i845_update_wm code was always calling the i845 variant,
and the i9xx_update_wm had only a choice between i830 and i9xx
paths, hardly worth the vfunc overhead.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/intel_pm.c | 20 +++-
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a8129153d1db..fc546d2ff0fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -330,8 +330,6 @@ struct drm_i915_display_funcs {
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe);
int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
- int (*get_fifo_size)(struct drm_i915_private *dev_priv,
-enum i9xx_plane_id i9xx_plane);
int (*compute_pipe_wm)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*compute_intermediate_wm)(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cfc41f8fa74a..d9993eb3730d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2347,7 +2347,10 @@ static void i9xx_update_wm(struct intel_crtc
*unused_crtc)
else
wm_info = _a_wm_info;
- fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
+ if (DISPLAY_VER(dev_priv) == 2)
+ fifo_size = i830_get_fifo_size(dev_priv, PLANE_A);
+ else
+ fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A);
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *pipe_mode =
@@ -2374,7 +2377,10 @@ static void i9xx_update_wm(struct intel_crtc
*unused_crtc)
if (DISPLAY_VER(dev_priv) == 2)
wm_info = _bc_wm_info;
- fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
+ if (DISPLAY_VER(dev_priv) == 2)
+ fifo_size = i830_get_fifo_size(dev_priv, PLANE_B);
+ else
+ fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B);
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *pipe_mode =
@@ -2490,7 +2496,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
pipe_mode = >config->hw.pipe_mode;
planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
_wm_info,
-
dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
+ i845_get_fifo_size(dev_priv, PLANE_A),
4, pessimal_latency_ns);
fwater_lo = intel_uncore_read(_priv->uncore, FW_BLC) & ~0xfff;
fwater_lo |= (3<<8) | planea_wm;
@@ -8054,15 +8060,11 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->display.update_wm = i965_update_wm;
} else if (DISPLAY_VER(dev_priv) == 3) {
dev_priv->display.update_wm = i9xx_update_wm;
- dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
} else if (DISPLAY_VER(dev_priv) == 2) {
- if (INTEL_NUM_PIPES(dev_priv) == 1) {
+ if (INTEL_NUM_PIPES(dev_priv) == 1)
dev_priv->display.update_wm = i845_update_wm;
- dev_priv->display.get_fifo_size = i845_get_fifo_size;
- } else {
+ else
dev_priv->display.update_wm = i9xx_update_wm;
- dev_priv->display.get_fifo_size = i830_get_fifo_size;
- }
} else {
drm_err(_priv->drm,
"unexpected fall-through in %s\n", __func__);
--
2.31.1
[Intel-gfx] [PATCH 00/23] i915/display: split and constify vtable (v2)
Details below, I've taken all the review feedback (thanks Jani). I added 3 patches moving to wrappers before refactoring, and one other patch is unreviewed (07) but the main comment was wanting the wrappers. Jani if you are happy with the final 4 patches can you land this series, I don't think I have drm-intel commit rights. v1: This is orthogonal to my display ptr refactoring and should probably be applied first. The display funcs vtable was a bit of mess, lots of intermixing of internal display functionality and interfaces to watermarks/irqs. It's also considered not great security practice to leave writeable function pointers around for exploits to get into. This series attempts to address both problems, first there are a few cleanups, then it splits the function table into multiple pieces. Some of the splits might be bikesheds but I think we should apply first and merge things later if there is good reason. The second half converts all the vtables to static const structs, I've used macros in some of them to make it less messy, the cdclk one is probably the worst one. v2: Added some patches adding wrappers around things before refactoring them as suggested by Jani. Fixed up all struct names as suggested by Jani. Added s-o-b lines Added commit msgs. Dave.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: rename debugfs_gt files
== Series Details == Series: series starting with [1/4] drm/i915: rename debugfs_gt files URL : https://patchwork.freedesktop.org/series/94489/ State : warning == Summary == $ dim checkpatch origin/drm-tip dc1cedc411a9 drm/i915: rename debugfs_gt files -:168: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #168: rename from drivers/gpu/drm/i915/gt/debugfs_gt.c total: 0 errors, 1 warnings, 0 checks, 340 lines checked bdf1cc706705 drm/i915: rename debugfs_engines files -:33: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #33: deleted file mode 100644 total: 0 errors, 1 warnings, 0 checks, 66 lines checked 139ac6e275d3 drm/i915: rename debugfs_gt_pm files -:33: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #33: deleted file mode 100644 total: 0 errors, 1 warnings, 0 checks, 68 lines checked 9c1930918f14 drm/i915: deduplicate frequency dump on debugfs
[Intel-gfx] [PATCH 1/4] drm/i915: rename debugfs_gt files
We shouldn't be using debugfs_ namespace for this functionality. Rename
debugfs_gt.[ch] to intel_gt_debugfs.[ch] and then make functions,
defines and structs follow suit.
While at it and since we are renaming the header, sort the includes
alphabetically.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/gt/debugfs_engines.c | 6 +++---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c| 14 +++---
drivers/gpu/drm/i915/gt/intel_gt.c | 6 +++---
.../gt/{debugfs_gt.c => intel_gt_debugfs.c}| 8
.../gt/{debugfs_gt.h => intel_gt_debugfs.h}| 14 +++---
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 10 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c | 18 +-
.../gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c | 8
drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.c | 6 +++---
drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 6 +++---
11 files changed, 49 insertions(+), 49 deletions(-)
rename drivers/gpu/drm/i915/gt/{debugfs_gt.c => intel_gt_debugfs.c} (87%)
rename drivers/gpu/drm/i915/gt/{debugfs_gt.h => intel_gt_debugfs.h} (71%)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c36c8a4f0716..3e171f0b5f6a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -80,7 +80,6 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
# "Graphics Technology" (aka we talk to the gpu)
gt-y += \
gt/debugfs_engines.o \
- gt/debugfs_gt.o \
gt/debugfs_gt_pm.o \
gt/gen2_engine_cs.o \
gt/gen6_engine_cs.o \
@@ -101,6 +100,7 @@ gt-y += \
gt/intel_gt.o \
gt/intel_gt_buffer_pool.o \
gt/intel_gt_clock_utils.o \
+ gt/intel_gt_debugfs.o \
gt/intel_gt_irq.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/debugfs_engines.c
b/drivers/gpu/drm/i915/gt/debugfs_engines.c
index 5e3725e62241..2980dac5b171 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_engines.c
@@ -7,9 +7,9 @@
#include
#include "debugfs_engines.h"
-#include "debugfs_gt.h"
#include "i915_drv.h" /* for_each_engine! */
#include "intel_engine.h"
+#include "intel_gt_debugfs.h"
static int engines_show(struct seq_file *m, void *data)
{
@@ -24,11 +24,11 @@ static int engines_show(struct seq_file *m, void *data)
return 0;
}
-DEFINE_GT_DEBUGFS_ATTRIBUTE(engines);
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(engines);
void debugfs_engines_register(struct intel_gt *gt, struct dentry *root)
{
- static const struct debugfs_gt_file files[] = {
+ static const struct intel_gt_debugfs_file files[] = {
{ "engines", _fops },
};
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index f6733f279890..9222cf68c56c 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -6,11 +6,11 @@
#include
-#include "debugfs_gt.h"
#include "debugfs_gt_pm.h"
#include "i915_drv.h"
#include "intel_gt.h"
#include "intel_gt_clock_utils.h"
+#include "intel_gt_debugfs.h"
#include "intel_gt_pm.h"
#include "intel_llc.h"
#include "intel_rc6.h"
@@ -36,7 +36,7 @@ static int fw_domains_show(struct seq_file *m, void *data)
return 0;
}
-DEFINE_GT_DEBUGFS_ATTRIBUTE(fw_domains);
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(fw_domains);
static void print_rc6_res(struct seq_file *m,
const char *title,
@@ -238,7 +238,7 @@ static int drpc_show(struct seq_file *m, void *unused)
return err;
}
-DEFINE_GT_DEBUGFS_ATTRIBUTE(drpc);
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(drpc);
static int frequency_show(struct seq_file *m, void *unused)
{
@@ -480,7 +480,7 @@ static int frequency_show(struct seq_file *m, void *unused)
return 0;
}
-DEFINE_GT_DEBUGFS_ATTRIBUTE(frequency);
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(frequency);
static int llc_show(struct seq_file *m, void *data)
{
@@ -533,7 +533,7 @@ static bool llc_eval(void *data)
return HAS_LLC(gt->i915);
}
-DEFINE_GT_DEBUGFS_ATTRIBUTE(llc);
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(llc);
static const char *rps_power_to_str(unsigned int power)
{
@@ -612,11 +612,11 @@ static bool rps_eval(void *data)
return HAS_RPS(gt->i915);
}
-DEFINE_GT_DEBUGFS_ATTRIBUTE(rps_boost);
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost);
void debugfs_gt_pm_register(struct intel_gt *gt, struct dentry *root)
{
- static const struct debugfs_gt_file files[] = {
+ static const struct intel_gt_debugfs_file files[] = {
{ "drpc", _fops, NULL },
{ "frequency", _fops, NULL },
{ "forcewake", _domains_fops, NULL },
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 2aeaae036a6f..9dda17553e12 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++
[Intel-gfx] [PATCH 3/4] drm/i915: rename debugfs_gt_pm files
We shouldn't be using debugfs_ namespace for this functionality. Rename
debugfs_gt_pm.[ch] to intel_gt_pm_debugfs.[ch] and then make
functions, defines and structs follow suit.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/gt/debugfs_gt_pm.h| 14 --
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 4 ++--
.../gt/{debugfs_gt_pm.c => intel_gt_pm_debugfs.c} | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h | 14 ++
5 files changed, 19 insertions(+), 19 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt_pm.h
rename drivers/gpu/drm/i915/gt/{debugfs_gt_pm.c => intel_gt_pm_debugfs.c} (99%)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 232c9673a2e5..dd656f2d7721 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -79,7 +79,6 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
# "Graphics Technology" (aka we talk to the gpu)
gt-y += \
- gt/debugfs_gt_pm.o \
gt/gen2_engine_cs.o \
gt/gen6_engine_cs.o \
gt/gen6_ppgtt.o \
@@ -103,6 +102,7 @@ gt-y += \
gt/intel_gt_engines_debugfs.o \
gt/intel_gt_irq.o \
gt/intel_gt_pm.o \
+ gt/intel_gt_pm_debugfs.o \
gt/intel_gt_pm_irq.o \
gt/intel_gt_requests.o \
gt/intel_gtt.o \
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h
deleted file mode 100644
index 4cf5f5c9da7d..
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2019 Intel Corporation
- */
-
-#ifndef DEBUGFS_GT_PM_H
-#define DEBUGFS_GT_PM_H
-
-struct intel_gt;
-struct dentry;
-
-void debugfs_gt_pm_register(struct intel_gt *gt, struct dentry *root);
-
-#endif /* DEBUGFS_GT_PM_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index e5d173c235a3..4096ee893b69 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -5,10 +5,10 @@
#include
-#include "debugfs_gt_pm.h"
#include "i915_drv.h"
#include "intel_gt_debugfs.h"
#include "intel_gt_engines_debugfs.h"
+#include "intel_gt_pm_debugfs.h"
#include "intel_sseu_debugfs.h"
#include "uc/intel_uc_debugfs.h"
@@ -24,7 +24,7 @@ void intel_gt_register_debugfs(struct intel_gt *gt)
return;
intel_gt_engines_register_debugfs(gt, root);
- debugfs_gt_pm_register(gt, root);
+ intel_gt_pm_register_debugfs(gt, root);
intel_sseu_debugfs_register(gt, root);
intel_uc_debugfs_register(>uc, root);
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
similarity index 99%
rename from drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
rename to drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 9222cf68c56c..baca153c05dd 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -6,12 +6,12 @@
#include
-#include "debugfs_gt_pm.h"
#include "i915_drv.h"
#include "intel_gt.h"
#include "intel_gt_clock_utils.h"
#include "intel_gt_debugfs.h"
#include "intel_gt_pm.h"
+#include "intel_gt_pm_debugfs.h"
#include "intel_llc.h"
#include "intel_rc6.h"
#include "intel_rps.h"
@@ -614,7 +614,7 @@ static bool rps_eval(void *data)
DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost);
-void debugfs_gt_pm_register(struct intel_gt *gt, struct dentry *root)
+void intel_gt_pm_register_debugfs(struct intel_gt *gt, struct dentry *root)
{
static const struct intel_gt_debugfs_file files[] = {
{ "drpc", _fops, NULL },
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
new file mode 100644
index ..f44894579604
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef INTEL_GT_PM_DEBUGFS_H
+#define INTEL_GT_PM_DEBUGFS_H
+
+struct intel_gt;
+struct dentry;
+
+void intel_gt_pm_register_debugfs(struct intel_gt *gt, struct dentry *root);
+
+#endif /* INTEL_GT_PM_DEBUGFS_H */
--
2.32.0
[Intel-gfx] [PATCH 2/4] drm/i915: rename debugfs_engines files
We shouldn't be using debugfs_ namespace for this functionality. Rename
debugfs_engines.[ch] to intel_gt_engines_debugfs.[ch] and then make
functions, defines and structs follow suit.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/gt/debugfs_engines.h | 14 --
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 4 ++--
...ebugfs_engines.c => intel_gt_engines_debugfs.c} | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h | 14 ++
5 files changed, 19 insertions(+), 19 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/gt/debugfs_engines.h
rename drivers/gpu/drm/i915/gt/{debugfs_engines.c =>
intel_gt_engines_debugfs.c} (85%)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3e171f0b5f6a..232c9673a2e5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -79,7 +79,6 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
# "Graphics Technology" (aka we talk to the gpu)
gt-y += \
- gt/debugfs_engines.o \
gt/debugfs_gt_pm.o \
gt/gen2_engine_cs.o \
gt/gen6_engine_cs.o \
@@ -101,6 +100,7 @@ gt-y += \
gt/intel_gt_buffer_pool.o \
gt/intel_gt_clock_utils.o \
gt/intel_gt_debugfs.o \
+ gt/intel_gt_engines_debugfs.o \
gt/intel_gt_irq.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/debugfs_engines.h
b/drivers/gpu/drm/i915/gt/debugfs_engines.h
deleted file mode 100644
index f69257eaa1cc..
--- a/drivers/gpu/drm/i915/gt/debugfs_engines.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2019 Intel Corporation
- */
-
-#ifndef DEBUGFS_ENGINES_H
-#define DEBUGFS_ENGINES_H
-
-struct intel_gt;
-struct dentry;
-
-void debugfs_engines_register(struct intel_gt *gt, struct dentry *root);
-
-#endif /* DEBUGFS_ENGINES_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index a27ba11605d8..e5d173c235a3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -5,10 +5,10 @@
#include
-#include "debugfs_engines.h"
#include "debugfs_gt_pm.h"
#include "i915_drv.h"
#include "intel_gt_debugfs.h"
+#include "intel_gt_engines_debugfs.h"
#include "intel_sseu_debugfs.h"
#include "uc/intel_uc_debugfs.h"
@@ -23,7 +23,7 @@ void intel_gt_register_debugfs(struct intel_gt *gt)
if (IS_ERR(root))
return;
- debugfs_engines_register(gt, root);
+ intel_gt_engines_register_debugfs(gt, root);
debugfs_gt_pm_register(gt, root);
intel_sseu_debugfs_register(gt, root);
diff --git a/drivers/gpu/drm/i915/gt/debugfs_engines.c
b/drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.c
similarity index 85%
rename from drivers/gpu/drm/i915/gt/debugfs_engines.c
rename to drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.c
index 2980dac5b171..44b22384fcb2 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.c
@@ -6,10 +6,10 @@
#include
-#include "debugfs_engines.h"
#include "i915_drv.h" /* for_each_engine! */
#include "intel_engine.h"
#include "intel_gt_debugfs.h"
+#include "intel_gt_engines_debugfs.h"
static int engines_show(struct seq_file *m, void *data)
{
@@ -26,7 +26,7 @@ static int engines_show(struct seq_file *m, void *data)
}
DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(engines);
-void debugfs_engines_register(struct intel_gt *gt, struct dentry *root)
+void intel_gt_engines_register_debugfs(struct intel_gt *gt, struct dentry
*root)
{
static const struct intel_gt_debugfs_file files[] = {
{ "engines", _fops },
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h
b/drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h
new file mode 100644
index ..4163b496937b
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef INTEL_GT_ENGINES_DEBUGFS_H
+#define INTEL_GT_ENGINES_DEBUGFS_H
+
+struct intel_gt;
+struct dentry;
+
+void intel_gt_engines_register_debugfs(struct intel_gt *gt, struct dentry
*root);
+
+#endif /* INTEL_GT_ENGINES_DEBUGFS_H */
--
2.32.0
[Intel-gfx] [PATCH 4/4] drm/i915: deduplicate frequency dump on debugfs
Although commit 9dd4b065446a ("drm/i915/gt: Move pm debug files into a
gt aware debugfs") says it was moving debug files to gt/, the
i915_frequency_info file was left behind and its implementation copied
into drivers/gpu/drm/i915/gt/debugfs_gt_pm.c. Over time we had several
patches having to change both places to keep them in sync (and some
patches failing to do so). The initial idea was to remove
i915_frequency_info, but there are user space tools using it. From a
quick code search there are other scripts and test tools besides igt, so
it's not simply updating igt to get rid of the older file.
Here we export a function using drm_printer as parameter and make
both show() implementations to call this same function. Aside from a few
variable name differences, for i915_frequency_info this brings a few
lines that were not previously printed: RP UP EI, RP UP THRESHOLD, RP
DOWN THRESHOLD and RP DOWN EI. These came in as part of
commit 9c878557b1eb ("drm/i915/gt: Use the RPM config register to
determine clk frequencies"), which didn't change both places.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 127 +-
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h | 2 +
drivers/gpu/drm/i915/i915_debugfs.c | 231 +-
3 files changed, 76 insertions(+), 284 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index baca153c05dd..31d334d3b3b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -240,9 +240,8 @@ static int drpc_show(struct seq_file *m, void *unused)
}
DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(drpc);
-static int frequency_show(struct seq_file *m, void *unused)
+void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
{
- struct intel_gt *gt = m->private;
struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore = gt->uncore;
struct intel_rps *rps = >rps;
@@ -254,21 +253,21 @@ static int frequency_show(struct seq_file *m, void
*unused)
u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
- seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
- seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
- seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK)
>>
+ drm_printf(p, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
+ drm_printf(p, "Requested VID: %d\n", rgvswctl & 0x3f);
+ drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK)
>>
MEMSTAT_VID_SHIFT);
- seq_printf(m, "Current P-state: %d\n",
+ drm_printf(p, "Current P-state: %d\n",
(rgvstat & MEMSTAT_PSTATE_MASK) >>
MEMSTAT_PSTATE_SHIFT);
} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
u32 rpmodectl, freq_sts;
rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
- seq_printf(m, "Video Turbo Mode: %s\n",
+ drm_printf(p, "Video Turbo Mode: %s\n",
yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
- seq_printf(m, "HW control enabled: %s\n",
+ drm_printf(p, "HW control enabled: %s\n",
yesno(rpmodectl & GEN6_RP_ENABLE));
- seq_printf(m, "SW control enabled: %s\n",
+ drm_printf(p, "SW control enabled: %s\n",
yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
GEN6_RP_MEDIA_SW_MODE));
@@ -276,25 +275,25 @@ static int frequency_show(struct seq_file *m, void
*unused)
freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
vlv_punit_put(i915);
- seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
- seq_printf(m, "DDR freq: %d MHz\n", i915->mem_freq);
+ drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
+ drm_printf(p, "DDR freq: %d MHz\n", i915->mem_freq);
- seq_printf(m, "actual GPU freq: %d MHz\n",
+ drm_printf(p, "actual GPU freq: %d MHz\n",
intel_gpu_freq(rps, (freq_sts >> 8) & 0xff));
- seq_printf(m, "current GPU freq: %d MHz\n",
+ drm_printf(p, "current GPU freq: %d MHz\n",
intel_gpu_freq(rps, rps->cur_freq));
- seq_printf(m, "max GPU freq: %d MHz\n",
+ drm_printf(p, "max GPU freq: %d MHz\n",
intel_gpu_freq(rps, rps->max_freq));
- seq_printf(m, "min GPU freq: %d MHz\n",
+ drm_printf(p, "min GPU freq: %d MHz\n",
intel_gpu_freq(rps, rps->min_freq));
Re: [Intel-gfx] [PATCH 11/21] drm/i915: split the dpll clock compute out from display vtable.
On Wed, 8 Sept 2021 at 20:09, Jani Nikula wrote:
>
> On Wed, 08 Sep 2021, Dave Airlie wrote:
> > From: Dave Airlie
> >
> > this could be merged later but for now it's simple to split it out.
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
> > drivers/gpu/drm/i915/display/intel_dpll.c| 16
> > drivers/gpu/drm/i915/i915_drv.h | 8 +++-
> > 3 files changed, 18 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index b981a923cc2f..87950202f4ce 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6768,10 +6768,10 @@ static int intel_crtc_atomic_check(struct
> > intel_atomic_state *state,
> > crtc_state->update_wm_post = true;
> >
> > if (mode_changed && crtc_state->hw.enable &&
> > - dev_priv->display.crtc_compute_clock &&
> > + dev_priv->dpll_funcs.crtc_compute_clock &&
> > !crtc_state->bigjoiner_slave &&
> > !drm_WARN_ON(_priv->drm, crtc_state->shared_dpll)) {
> > - ret = dev_priv->display.crtc_compute_clock(crtc_state);
> > + ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
> > if (ret)
> > return ret;
>
> It was there before, but yuck. Conditions like this with checks on the
> existence of a vfunc are really ugly. Could benefit from a wrapper - but
> that requires figuring out what the condition actually is. *facepalm*.
>
> > }
> > @@ -8807,7 +8807,7 @@ static void intel_modeset_clear_plls(struct
> > intel_atomic_state *state)
> > struct intel_crtc *crtc;
> > int i;
> >
> > - if (!dev_priv->display.crtc_compute_clock)
> > + if (!dev_priv->dpll_funcs.crtc_compute_clock)
> > return;
> >
> > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> > b/drivers/gpu/drm/i915/display/intel_dpll.c
> > index 210f91f4a576..9326c7cbb05c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> > @@ -1367,21 +1367,21 @@ void
> > intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
> > {
> > if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
> > - dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
> > + dev_priv->dpll_funcs.crtc_compute_clock =
> > hsw_crtc_compute_clock;
> > else if (HAS_PCH_SPLIT(dev_priv))
> > - dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
> > + dev_priv->dpll_funcs.crtc_compute_clock =
> > ilk_crtc_compute_clock;
> > else if (IS_CHERRYVIEW(dev_priv))
> > - dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
> > + dev_priv->dpll_funcs.crtc_compute_clock =
> > chv_crtc_compute_clock;
> > else if (IS_VALLEYVIEW(dev_priv))
> > - dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
> > + dev_priv->dpll_funcs.crtc_compute_clock =
> > vlv_crtc_compute_clock;
> > else if (IS_G4X(dev_priv))
> > - dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
> > + dev_priv->dpll_funcs.crtc_compute_clock =
> > g4x_crtc_compute_clock;
> > else if (IS_PINEVIEW(dev_priv))
> > - dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
> > + dev_priv->dpll_funcs.crtc_compute_clock =
> > pnv_crtc_compute_clock;
> > else if (DISPLAY_VER(dev_priv) != 2)
> > - dev_priv->display.crtc_compute_clock =
> > i9xx_crtc_compute_clock;
> > + dev_priv->dpll_funcs.crtc_compute_clock =
> > i9xx_crtc_compute_clock;
> > else
> > - dev_priv->display.crtc_compute_clock =
> > i8xx_crtc_compute_clock;
> > + dev_priv->dpll_funcs.crtc_compute_clock =
> > i8xx_crtc_compute_clock;
> > }
> >
> > static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 49b23ea46475..461ab0a0f088 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -393,6 +393,10 @@ struct drm_i915_fdi_link_train_funcs {
> > const struct intel_crtc_state *crtc_state);
> > };
> >
> > +struct drm_i915_dpll_funcs {
>
> Nitpick, intel_dpll_funcs. Starting to spot the pattern? ;D
>
> Part of the point is that I think these may eventually move to their own
> headers, and I like to drive naming structs and functions after the file
> name. So, you'd find intel_dpll_* stuff in intel_dpll.[ch]. Or if they
> stay in i915_drv.h, at least that's the chrystal clear context.
I've got a follow up series to move some of them as an RFC locally,
so I'm quite happy to rename
Re: [Intel-gfx] [PATCH v5 25/25] drm/i915/guc: Add GuC kernel doc
On 9/3/2021 12:59, Daniele Ceraolo Spurio wrote:
From: Matthew Brost
Add GuC kernel doc for all structures added thus far for GuC submission
and update the main GuC submission section with the new interface
details.
v2:
- Drop guc_active.lock DOC
v3:
- Fixup a few kernel doc comments (Daniele)
v4 (Daniele):
- Implement doc suggestions from John
- Add kerneldoc for all members of the GuC structure and pull the file
in i915.rst
v5 (Daniele):
- Implement new doc suggestions from John
Signed-off-by: Matthew Brost
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Reviewed-by: John Harrison
---
Documentation/gpu/i915.rst| 2 +
drivers/gpu/drm/i915/gt/intel_context_types.h | 43 +---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 75 ++---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 100 ++
drivers/gpu/drm/i915/i915_request.h | 21 ++--
5 files changed, 181 insertions(+), 60 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 101dde3eb1ea..311e10400708 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -495,6 +495,8 @@ GuC
.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
:doc: GuC
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.h
+
GuC Firmware Layout
~~~
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 5285d660eacf..930569a1a01f 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -156,40 +156,51 @@ struct intel_context {
u8 wa_bb_page; /* if set, page num reserved for context workarounds */
struct {
- /** lock: protects everything in guc_state */
+ /** @lock: protects everything in guc_state */
spinlock_t lock;
/**
-* sched_state: scheduling state of this context using GuC
+* @sched_state: scheduling state of this context using GuC
* submission
*/
u32 sched_state;
/*
-* fences: maintains of list of requests that have a submit
-* fence related to GuC submission
+* @fences: maintains a list of requests that are currently
+* being fenced until a GuC operation completes
*/
struct list_head fences;
- /* GuC context blocked fence */
+ /**
+* @blocked: fence used to signal when the blocking of a
+* context's submissions is complete.
+*/
struct i915_sw_fence blocked;
- /* GuC committed requests */
+ /** @number_committed_requests: number of committed requests */
int number_committed_requests;
- /** requests: active requests on this context */
+ /** @requests: list of active requests on this context */
struct list_head requests;
- /*
-* GuC priority management
-*/
+ /** @prio: the context's current guc priority */
u8 prio;
+ /**
+* @prio_count: a counter of the number requests in flight in
+* each priority bucket
+*/
u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
} guc_state;
struct {
- /* GuC LRC descriptor ID */
+ /**
+* @id: handle which is used to uniquely identify this context
+* with the GuC, protected by guc->contexts_lock
+*/
u16 id;
-
- /* GuC LRC descriptor reference count */
+ /**
+* @ref: the number of references to the guc_id, when
+* transitioning in and out of zero protected by
+* guc->contexts_lock
+*/
atomic_t ref;
-
- /*
-* GuC ID link - in list when unpinned but guc_id still valid
in GuC
+ /**
+* @link: in guc->guc_id_list when the guc_id has no refs but is
+* still valid, protected by guc->contexts_lock
*/
struct list_head link;
} guc_id;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 2e27fe59786b..5dd174babf7a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -22,74 +22,121 @@
struct __guc_ads_blob;
-/*
- * Top level structure of GuC. It handles firmware loading and manages client
- * pool. intel_guc owns a intel_guc_client to replace the legacy ExecList
- * submission.
+/**
+ * struct intel_guc - Top level structure of GuC.
+ *
+ * It
Re: [Intel-gfx] [PATCH 03/21] drm/i915/wm: move the update watermark wrapper to display side.
On Wed, 8 Sept 2021 at 19:33, Jani Nikula wrote: > > On Wed, 08 Sep 2021, Dave Airlie wrote: > > From: Dave Airlie > > > > A vague goal is to have the vfunc table be the api between > > wm and display, not having direction function calls cross > > the boundary. > > > > This aligns the legacy update_wm with the newer vfuncs. > > > > The comment probably needs to live somewhere else, it seems > > like it should live in the pm side though not the display side, > > but I brought it along for the ride. > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 40 > > drivers/gpu/drm/i915/intel_pm.c | 39 --- > > drivers/gpu/drm/i915/intel_pm.h | 1 - > > 3 files changed, 40 insertions(+), 40 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > b/drivers/gpu/drm/i915/display/intel_display.c > > index d95283bf2631..b495371c1889 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > We haven't been axing stuff out of intel_display.c so we could add > somethign else back! ;) > > A new file for watermarks or display pm? Ville? The main reason I landed it there, was because all the other calls to the wm funcs are in intel_display, and this wrapper is very small and ends up being a static, the comment on the other hand, I've no idea where it should have landed. Dave.
Re: [Intel-gfx] [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain
On Wed, Sep 08, 2021 at 11:07:07AM +0100, Tvrtko Ursulin wrote: > > On 07/09/2021 18:19, Matt Roper wrote: > > The reset domain is shared between render and all compute engines, > > so resetting one will affect the others. > > > > Note: Before performing a reset on an RCS or CCS engine, the GuC will > > attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid > > impacting other clients (since some shared modules will be reset). If > > other engines are executing non-preemptable workloads, the impact is > > unavoidable and some work may be lost. > > Since here it talks about engine reset, should this patch add warning if > same is attempted by i915 on a GuC platform - to document it is not Did you mean "on a *non* GuC platform" here? We aren't going to have compute engine support on any platforms where GuC submission isn't the default operating model, so the only way to get compute engines + execlist submission is to force an override via module parameters (e.g., enable_guc=0). Doing so will taint the kernel, so I think the current consensus from offline discussion is that the user has already put themselves into a configuration where it's easier than usual to shoot themselves in the foot; it's not too much different than the kind of trouble a user could get themselves into if they loaded the driver with hangcheck disabled or something. Matt > implemented/supported? Or perhaps later in the series, or future series > works better. > > Reviewed-by: Tvrtko Ursulin > > Regards, > > Tvrtko > > > Bspec: 52549 > > Original-patch-by: Michel Thierry > > Cc: Tvrtko Ursulin > > Cc: Vinay Belgaumkar > > Signed-off-by: Daniele Ceraolo Spurio > > Signed-off-by: Aravind Iddamsetty > > Signed-off-by: Matt Roper > > --- > > drivers/gpu/drm/i915/gt/intel_reset.c | 4 > > 1 file changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c > > b/drivers/gpu/drm/i915/gt/intel_reset.c > > index 91200c43951f..30598c1d070c 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_reset.c > > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c > > @@ -507,6 +507,10 @@ static int gen11_reset_engines(struct intel_gt *gt, > > [VECS1] = GEN11_GRDOM_VECS2, > > [VECS2] = GEN11_GRDOM_VECS3, > > [VECS3] = GEN11_GRDOM_VECS4, > > + [CCS0] = GEN11_GRDOM_RENDER, > > + [CCS1] = GEN11_GRDOM_RENDER, > > + [CCS2] = GEN11_GRDOM_RENDER, > > + [CCS3] = GEN11_GRDOM_RENDER, > > }; > > struct intel_engine_cs *engine; > > intel_engine_mask_t tmp; > > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795
Re: [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
On Thu, 2021-09-09 at 01:20 +0530, Manna, Animesh wrote:
>
> > -Original Message-
> > From: Souza, Jose
> > Sent: Thursday, September 9, 2021 1:02 AM
> > To: Manna, Animesh ; intel-
> > g...@lists.freedesktop.org
> > Cc: Mun, Gwan-gyeong ; Nikula, Jani
> > ; Kahola, Mika ; Navare,
> > Manasi D
> > Subject: Re: [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and
> > compute config for panel replay
> >
> > On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> > > As panel replay feature similar to PSR feature of EDP panel, so
> > > currently utilized existing psr framework for panel replay.
> > >
> > > Signed-off-by: Animesh Manna
> > > ---
> > > .../drm/i915/display/intel_display_types.h| 4 ++
> > > drivers/gpu/drm/i915/display/intel_dp.c | 47 +++
> > > drivers/gpu/drm/i915/display/intel_psr.c | 43 +
> > > drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
> > > include/drm/drm_dp_helper.h | 3 ++
> > > 5 files changed, 91 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index c7bcf9183447..6ca9fabb9333 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1066,6 +1066,7 @@ struct intel_crtc_state {
> > > bool req_psr2_sdp_prior_scanline;
> > > u32 dc3co_exitline;
> > > u16 su_y_granularity;
> > > + bool has_panel_replay;
> > >
> > > /*
> > >* Frequence the dpll for the port should run at. Differs from the
> > > @@ -1526,6 +1527,8 @@ struct intel_psr {
> > > bool irq_aux_error;
> > > u16 su_w_granularity;
> > > u16 su_y_granularity;
> > > + bool sink_pr_support;
> > > + bool pr_enabled;
> >
> > Instead of all the above we could have a function that checks if
> > displayPort is
> > eDP or not, to know if is PSR or PR.
> > sink_support and all the others should be shared for PSR and PR.
>
> To get sink capability for panel replay dpcd address 0xb0 is read by the
> source. I feel PSR is using different dpcd address ...rt?
> DP 2.0 display only support panel replay ... maybe need to add a check for DP
> 2.0 also here before reading about panel replay capability or I am missing
> anything.
I mean in the function that we check if sink supports PSR we could check if is
DP 2.0 and if panel replay is supported and set sink_support to true.
From there we don't need those additional bools, if is eDP we know that PSR is
supported if is DisplayPort we know that is panel replay.
>
> Regards,
> Animesh
> >
> > > u32 dc3co_exitline;
> > > u32 dc3co_exit_delay;
> > > struct delayed_work dc3co_work;
> > > @@ -1552,6 +1555,7 @@ struct intel_dp {
> > > u8
> > lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
> > > u8 fec_capable;
> > > u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
> > > + u8 pr_dpcd;
> >
> > Used once why cache it?
> >
> > > /* source rates */
> > > int num_source_rates;
> > > const int *source_rates;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index d28bd8c4a8a5..90c708548811 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -1560,12 +1560,22 @@ static void
> > intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > >
> > > - /*
> > > - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > > - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > > - * Colorimetry Format indication.
> > > - */
> > > - vsc->revision = 0x5;
> > > + if (crtc_state->has_panel_replay) {
> > > + /*
> > > + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> > > + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> > > + * Encoding/Colorimetry Format indication.
> > > + */
> > > + vsc->revision = 0x7;
> > > + } else {
> > > + /*
> > > + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > > + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > > + * Colorimetry Format indication.
> > > + */
> > > + vsc->revision = 0x5;
> > > + }
> > > +
> > > vsc->length = 0x13;
> > >
> > > /* DP 1.4a spec, Table 2-120 */
> > > @@ -1674,6 +1684,22 @@ void intel_dp_compute_psr_vsc_sdp(struct
> > intel_dp *intel_dp,
> > > vsc->revision = 0x4;
> > > vsc->length = 0xe;
> > > }
> > > + } else if (intel_dp->psr.pr_enabled) {
> > > + if (intel_dp->psr.colorimetry_support &&
> > > + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> > > + /* [PR,
Re: [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
> -Original Message-
> From: Souza, Jose
> Sent: Thursday, September 9, 2021 1:02 AM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong ; Nikula, Jani
> ; Kahola, Mika ; Navare,
> Manasi D
> Subject: Re: [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and
> compute config for panel replay
>
> On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> > As panel replay feature similar to PSR feature of EDP panel, so
> > currently utilized existing psr framework for panel replay.
> >
> > Signed-off-by: Animesh Manna
> > ---
> > .../drm/i915/display/intel_display_types.h| 4 ++
> > drivers/gpu/drm/i915/display/intel_dp.c | 47 +++
> > drivers/gpu/drm/i915/display/intel_psr.c | 43 +
> > drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
> > include/drm/drm_dp_helper.h | 3 ++
> > 5 files changed, 91 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index c7bcf9183447..6ca9fabb9333 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1066,6 +1066,7 @@ struct intel_crtc_state {
> > bool req_psr2_sdp_prior_scanline;
> > u32 dc3co_exitline;
> > u16 su_y_granularity;
> > + bool has_panel_replay;
> >
> > /*
> > * Frequence the dpll for the port should run at. Differs from the
> > @@ -1526,6 +1527,8 @@ struct intel_psr {
> > bool irq_aux_error;
> > u16 su_w_granularity;
> > u16 su_y_granularity;
> > + bool sink_pr_support;
> > + bool pr_enabled;
>
> Instead of all the above we could have a function that checks if displayPort
> is
> eDP or not, to know if is PSR or PR.
> sink_support and all the others should be shared for PSR and PR.
To get sink capability for panel replay dpcd address 0xb0 is read by the
source. I feel PSR is using different dpcd address ...rt?
DP 2.0 display only support panel replay ... maybe need to add a check for DP
2.0 also here before reading about panel replay capability or I am missing
anything.
Regards,
Animesh
>
> > u32 dc3co_exitline;
> > u32 dc3co_exit_delay;
> > struct delayed_work dc3co_work;
> > @@ -1552,6 +1555,7 @@ struct intel_dp {
> > u8
> lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
> > u8 fec_capable;
> > u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
> > + u8 pr_dpcd;
>
> Used once why cache it?
>
> > /* source rates */
> > int num_source_rates;
> > const int *source_rates;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index d28bd8c4a8a5..90c708548811 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1560,12 +1560,22 @@ static void
> intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >
> > - /*
> > -* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > -* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > -* Colorimetry Format indication.
> > -*/
> > - vsc->revision = 0x5;
> > + if (crtc_state->has_panel_replay) {
> > + /*
> > +* Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> > +* VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> > +* Encoding/Colorimetry Format indication.
> > +*/
> > + vsc->revision = 0x7;
> > + } else {
> > + /*
> > +* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > +* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > +* Colorimetry Format indication.
> > +*/
> > + vsc->revision = 0x5;
> > + }
> > +
> > vsc->length = 0x13;
> >
> > /* DP 1.4a spec, Table 2-120 */
> > @@ -1674,6 +1684,22 @@ void intel_dp_compute_psr_vsc_sdp(struct
> intel_dp *intel_dp,
> > vsc->revision = 0x4;
> > vsc->length = 0xe;
> > }
> > + } else if (intel_dp->psr.pr_enabled) {
> > + if (intel_dp->psr.colorimetry_support &&
> > + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> > + /* [PR, +Colorimetry] */
> > + intel_dp_compute_vsc_colorimetry(crtc_state,
> conn_state,
> > +vsc);
> > + } else {
> > + /*
> > +* [PR, -Colorimetry]
> > +* Prepare VSC Header for SU as per DP 2.0 spec, Table
> 2-223
> > +* VSC SDP supporting 3D stereo + PR (applies to eDP
> v1.3 or
> > +* higher).
> > +
Re: [Intel-gfx] [PATCH 10/19] Move CONTEXT_VALID_BIT check
On Mon, Aug 30, 2021 at 02:09:57PM +0200, Maarten Lankhorst wrote:
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 1f07ac4e0672..df81a0dc481e 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -52,8 +52,6 @@ static int __engine_unpark(struct intel_wakeref *wf)
/* Discard stale context state from across idling */
ce = engine->kernel_context;
if (ce) {
- GEM_BUG_ON(test_bit(CONTEXT_VALID_BIT, >flags));
-
/* Flush all pending HW writes before we touch the context */
while (unlikely(intel_context_inflight(ce)))
intel_engine_flush_submission(engine);
@@ -68,6 +66,9 @@ static int __engine_unpark(struct intel_wakeref *wf)
ce->timeline->seqno,
READ_ONCE(*ce->timeline->hwsp_seqno),
ce->ring->emit);
+
+ GEM_BUG_ON(test_bit(CONTEXT_VALID_BIT, >flags));
+
Looks good to me.
Reviewed-by: Niranjana Vishwanathapura
GEM_BUG_ON(ce->timeline->seqno !=
READ_ONCE(*ce->timeline->hwsp_seqno));
}
--
2.32.0
Re: [Intel-gfx] [RFC 4/5] drm/i915/panelreplay: enable/disable panel replay
On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> TRANS_DP2_CTL register is programmed to enable panel replay from source
> and sink is enabled through panel replay dpcd configuration address.
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 30
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> include/drm/drm_dp_helper.h | 3 +++
> 3 files changed, 29 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 660e19c10aa8..1dc6b340d745 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -369,8 +369,12 @@ static void intel_psr_enable_sink(struct intel_dp
> *intel_dp)
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> u8 dpcd_val = DP_PSR_ENABLE;
>
> - /* Enable ALPM at sink for psr2 */
> - if (intel_dp->psr.psr2_enabled) {
> + if (intel_dp->psr.pr_enabled) {
> + drm_dp_dpcd_writeb(_dp->aux, PANEL_REPLAY_CONFIG,
> +PANEL_REPLAY_ENABLE);
> + return;
If you are sure no other dpcd write is needed better separate this if + return
from the other
if (intel_dp->psr.pr_enabled) {
...
return;
}
if (intel_dp->psr.psr2_enabled) {
} else {
...
}
> + } else if (intel_dp->psr.psr2_enabled) {
> + /* Enable ALPM at sink for psr2 */
> drm_dp_dpcd_writeb(_dp->aux, DP_RECEIVER_ALPM_CONFIG,
> DP_ALPM_ENABLE |
> DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> @@ -497,6 +501,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp
> *intel_dp)
> return val;
> }
>
> +static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
> +ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);
> +
> + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
> + TRANS_DP2_PANEL_REPLAY_ENABLE);
PSR2 is not supported in DG2 and I would believe that is the case for panel
relay.
> +}
> +
> static void hsw_activate_psr2(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -1077,8 +1092,10 @@ static void intel_psr_activate(struct intel_dp
> *intel_dp)
> drm_WARN_ON(_priv->drm, intel_dp->psr.active);
> lockdep_assert_held(_dp->psr.lock);
>
> - /* psr1 and psr2 are mutually exclusive.*/
> - if (intel_dp->psr.psr2_enabled)
> + /* psr1, psr2 and panel-replay are mutually exclusive.*/
> + if (intel_dp->psr.pr_enabled)
> + dg2_activate_panel_replay(intel_dp);
> + else if (intel_dp->psr.psr2_enabled)
> hsw_activate_psr2(intel_dp);
> else
> hsw_activate_psr1(intel_dp);
> @@ -1267,7 +1284,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
> return;
> }
>
> - if (intel_dp->psr.psr2_enabled) {
> + if (intel_dp->psr.pr_enabled) {
> + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
> + TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
> + } else if (intel_dp->psr.psr2_enabled) {
> tgl_disallow_dc3co_on_psr2_exit(intel_dp);
> val = intel_de_read(dev_priv,
> EDP_PSR2_CTL(intel_dp->psr.transcoder));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5bc8f22fa9a8..9effbc6e5539 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4720,6 +4720,7 @@ enum {
> #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME
> REG_BIT(3)
> #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAMEREG_BIT(2)
> #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATEREG_BIT(1)
> +#define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE
> REG_BIT(31)
> #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28,
> 16)
> #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)
> REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK
> REG_GENMASK(12, 0)
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 1b4dcee3b281..63face4e4f6f 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -707,6 +707,9 @@ struct drm_panel;
> #define DP_BRANCH_DEVICE_CTRL0x1a1
> # define DP_BRANCH_DEVICE_IRQ_HPD(1 << 0)
>
> +#define PANEL_REPLAY_CONFIG 0x1b0
> +# define PANEL_REPLAY_ENABLE(1 << 0)
> +
> #define
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Suspend / resume backup- and restore of LMEM. (rev3)
== Series Details == Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev3) URL : https://patchwork.freedesktop.org/series/94278/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10563_full -> Patchwork_20991_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_20991_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20991_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_20991_full: ### IGT changes ### Possible regressions * igt@i915_pm_rps@reset: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/shard-skl10/igt@i915_pm_...@reset.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-skl8/igt@i915_pm_...@reset.html Known issues Here are the changes found in Patchwork_20991_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-apl: NOTRUN -> [DMESG-WARN][3] ([i915#3002]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-apl3/igt@gem_cre...@create-massive.html * igt@gem_ctx_param@set-priority-not-supported: - shard-tglb: NOTRUN -> [SKIP][4] ([fdo#109314]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-tglb5/igt@gem_ctx_pa...@set-priority-not-supported.html * igt@gem_ctx_persistence@legacy-engines-mixed-process: - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-mixed-process.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][6] -> [FAIL][7] ([i915#2846]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/shard-glk3/igt@gem_exec_f...@basic-deadline.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-glk7/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/shard-glk5/igt@gem_exec_fair@basic-none-r...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-glk3/igt@gem_exec_fair@basic-none-r...@rcs0.html - shard-tglb: NOTRUN -> [FAIL][10] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-tglb5/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-iclb6/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_nop@basic-series: - shard-glk: [PASS][14] -> [DMESG-WARN][15] ([i915#118] / [i915#95]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/shard-glk4/igt@gem_exec_...@basic-series.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-glk7/igt@gem_exec_...@basic-series.html * igt@gem_exec_params@secure-non-master: - shard-tglb: NOTRUN -> [SKIP][16] ([fdo#112283]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-tglb1/igt@gem_exec_par...@secure-non-master.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][17] -> [SKIP][18] ([i915#2190]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/shard-tglb2/igt@gem_huc_c...@huc-copy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-tglb7/igt@gem_huc_c...@huc-copy.html * igt@gem_pwrite@basic-exhaustion: - shard-snb: NOTRUN -> [WARN][19] ([i915#2658]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-snb2/igt@gem_pwr...@basic-exhaustion.html - shard-kbl: NOTRUN -> [WARN][20] ([i915#2658]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/shard-kbl7/igt@gem_pwr...@basic-exhaustion.html * igt@gem_render_copy@linear-to-vebox-y-tiled: - shard-glk: NOTRUN -> [SKIP][21] ([fdo#109271]) +3 similar issues [21]:
Re: [Intel-gfx] [RFC 1/5] drm/i915/panelreplay: update plane selective fetch register definition
> -Original Message-
> From: Souza, Jose
> Sent: Thursday, September 9, 2021 12:57 AM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong ; Nikula, Jani
> ; Kahola, Mika ; Navare,
> Manasi D
> Subject: Re: [Intel-gfx] [RFC 1/5] drm/i915/panelreplay: update plane
> selective
> fetch register definition
>
> On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> > Panel replay can be enabled for all pipes driving DP 2.0 monitor, so
> > updated the plane selective fetch register difinition accordingly.
>
> It should mention that this changes are to accommodate differences in DG2.
>
> Anyways, DG2 had PSR2 support dropped so we don't need this whole patch.
Panel replay can also use selective fetch/update .. rt?
DG2 will support panel replay if not PSR2.
Regards,
Animesh
>
> >
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 8 +++---
> > drivers/gpu/drm/i915/i915_reg.h | 32 +---
> > 2 files changed, 22 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 3f6fb7d67f84..5fa76b148f6d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1445,7 +1445,7 @@ void intel_psr2_program_plane_sel_fetch(struct
> > intel_plane *plane,
> >
> > val = plane_state ? plane_state->ctl : 0;
> > val &= plane->id == PLANE_CURSOR ? val :
> PLANE_SEL_FETCH_CTL_ENABLE;
> > - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
> val);
> > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(dev_priv, pipe,
> > +plane->id), val);
> > if (!val || plane->id == PLANE_CURSOR)
> > return;
> >
> > @@ -1453,19 +1453,19 @@ void intel_psr2_program_plane_sel_fetch(struct
> > intel_plane *plane,
> >
> > val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
> > val |= plane_state->uapi.dst.x1;
> > - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id),
> val);
> > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(dev_priv, pipe,
> > +plane->id), val);
> >
> > /* TODO: consider auxiliary surfaces */
> > x = plane_state->uapi.src.x1 >> 16;
> > y = (plane_state->uapi.src.y1 >> 16) + clip->y1;
> > val = y << 16 | x;
> > - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane-
> >id),
> > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(dev_priv, pipe,
> > +plane->id),
> > val);
> >
> > /* Sizes are 0 based */
> > val = (drm_rect_height(clip) - 1) << 16;
> > val |= (drm_rect_width(_state->uapi.src) >> 16) - 1;
> > - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id),
> val);
> > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(dev_priv, pipe,
> > +plane->id), val);
> > }
> >
> > void intel_psr2_program_trans_man_trk_ctl(const struct
> > intel_crtc_state *crtc_state) diff --git
> > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index c2853cc005ee..5bc8f22fa9a8 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7471,6 +7471,7 @@ enum {
> > #define _SEL_FETCH_PLANE_BASE_7_A 0x70960
> > #define _SEL_FETCH_PLANE_BASE_CUR_A0x70880
> > #define _SEL_FETCH_PLANE_BASE_1_B 0x70990
> > +#define _DG2_SEL_FETCH_PLANE_BASE_1_B 0x71890
> >
> > #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
> > _SEL_FETCH_PLANE_BASE_1_A, \
> @@ -7481,31 +7482,34 @@ enum {
> > _SEL_FETCH_PLANE_BASE_6_A, \
> > _SEL_FETCH_PLANE_BASE_7_A, \
> > _SEL_FETCH_PLANE_BASE_CUR_A) -
> #define
> > _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe,
> _SEL_FETCH_PLANE_BASE_1_A,
> > _SEL_FETCH_PLANE_BASE_1_B) -#define _SEL_FETCH_PLANE_BASE(pipe,
> plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
> > - _SEL_FETCH_PLANE_BASE_1_A + \
> > - _SEL_FETCH_PLANE_BASE_A(plane))
> > +#define _SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) _PIPE(pipe,
> _SEL_FETCH_PLANE_BASE_1_A, \
> > + DISPLAY_VER(dev_priv) >
> 12 ? \
> > +
> _DG2_SEL_FETCH_PLANE_BASE_1_B : \
> > +
> _SEL_FETCH_PLANE_BASE_1_B) #define
> > +_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane)
> (_SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) - \
> > +
> _SEL_FETCH_PLANE_BASE_1_A + \
> > +
> _SEL_FETCH_PLANE_BASE_A(plane))
> >
> > #define _SEL_FETCH_PLANE_CTL_1_A 0x70890
> > -#define PLANE_SEL_FETCH_CTL(pipe, plane)
> > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> > +#define PLANE_SEL_FETCH_CTL(dev_priv, pipe, plane)
> > +_MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
> >
Re: [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> As panel replay feature similar to PSR feature of EDP panel, so currently
> utilized existing psr framework for panel replay.
>
> Signed-off-by: Animesh Manna
> ---
> .../drm/i915/display/intel_display_types.h| 4 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 47 +++
> drivers/gpu/drm/i915/display/intel_psr.c | 43 +
> drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
> include/drm/drm_dp_helper.h | 3 ++
> 5 files changed, 91 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c7bcf9183447..6ca9fabb9333 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1066,6 +1066,7 @@ struct intel_crtc_state {
> bool req_psr2_sdp_prior_scanline;
> u32 dc3co_exitline;
> u16 su_y_granularity;
> + bool has_panel_replay;
>
> /*
>* Frequence the dpll for the port should run at. Differs from the
> @@ -1526,6 +1527,8 @@ struct intel_psr {
> bool irq_aux_error;
> u16 su_w_granularity;
> u16 su_y_granularity;
> + bool sink_pr_support;
> + bool pr_enabled;
Instead of all the above we could have a function that checks if displayPort is
eDP or not, to know if is PSR or PR.
sink_support and all the others should be shared for PSR and PR.
> u32 dc3co_exitline;
> u32 dc3co_exit_delay;
> struct delayed_work dc3co_work;
> @@ -1552,6 +1555,7 @@ struct intel_dp {
> u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
> u8 fec_capable;
> u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
> + u8 pr_dpcd;
Used once why cache it?
> /* source rates */
> int num_source_rates;
> const int *source_rates;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index d28bd8c4a8a5..90c708548811 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1560,12 +1560,22 @@ static void intel_dp_compute_vsc_colorimetry(const
> struct intel_crtc_state *crtc
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - /*
> - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> - * Colorimetry Format indication.
> - */
> - vsc->revision = 0x5;
> + if (crtc_state->has_panel_replay) {
> + /*
> + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> + * Encoding/Colorimetry Format indication.
> + */
> + vsc->revision = 0x7;
> + } else {
> + /*
> + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> + * Colorimetry Format indication.
> + */
> + vsc->revision = 0x5;
> + }
> +
> vsc->length = 0x13;
>
> /* DP 1.4a spec, Table 2-120 */
> @@ -1674,6 +1684,22 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp
> *intel_dp,
> vsc->revision = 0x4;
> vsc->length = 0xe;
> }
> + } else if (intel_dp->psr.pr_enabled) {
> + if (intel_dp->psr.colorimetry_support &&
> + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> + /* [PR, +Colorimetry] */
> + intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> + vsc);
> + } else {
> + /*
> + * [PR, -Colorimetry]
> + * Prepare VSC Header for SU as per DP 2.0 spec, Table
> 2-223
> + * VSC SDP supporting 3D stereo + PR (applies to eDP
> v1.3 or
> + * higher).
> + */
> + vsc->revision = 0x6;
> + vsc->length = 0x10;
> + }
> } else {
> /*
>* [PSR1]
> @@ -1814,6 +1840,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>
> intel_vrr_compute_config(pipe_config, conn_state);
> intel_psr_compute_config(intel_dp, pipe_config);
> + intel_panel_replay_compute_config(intel_dp, pipe_config);
> intel_drrs_compute_config(intel_dp, pipe_config, output_bpp,
> constant_n);
> intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> @@ -2719,10 +2746,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct
> drm_dp_vsc_sdp
Re: [Intel-gfx] [RFC 2/5] drm/i915/panelreplay: Feature flag added for panel replay
On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> Platforms having Display 13 and above will support panel
> replay feature of DP 2.0 monitor. Added a feature flag
> for panel replay.
As all display 13 and newer platforms supports it would be better to have
#define HAS_PR(i915) (DISPLAY_VER(i915) >= 13) instead of add one more
parameter to intel_device_info.
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 3 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1fd3040b6771..5b26d7c09b2d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1645,6 +1645,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
> #define HAS_FPGA_DBG_UNCLAIMED(dev_priv)
> (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
> #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
> +#define HAS_PR(dev_priv) (INTEL_INFO(dev_priv)->display.has_pr)
> #define HAS_PSR_HW_TRACKING(dev_priv) \
> (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
> #define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d4a6a9dcf182..c58bd19b5bdf 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -946,6 +946,7 @@ static const struct intel_device_info adl_s_info = {
> .display.has_hotplug = 1,
> \
> .display.has_ipc = 1,
> \
> .display.has_psr = 1,
> \
> + .display.has_pr = 1,\
> .display.ver = 13,
> \
> .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> \
> .pipe_offsets = {
> \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index d328bb95c49b..4552a1f88568 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -161,6 +161,7 @@ enum intel_ppgtt_type {
> func(has_modular_fia); \
> func(has_overlay); \
> func(has_psr); \
> + func(has_pr); \
> func(has_psr_hw_tracking); \
> func(overlay_needs_physical); \
> func(supports_tv);
Re: [Intel-gfx] [RFC 1/5] drm/i915/panelreplay: update plane selective fetch register definition
On Wed, 2021-09-08 at 14:45 +0530, Animesh Manna wrote:
> Panel replay can be enabled for all pipes driving DP 2.0 monitor,
> so updated the plane selective fetch register difinition accordingly.
It should mention that this changes are to accommodate differences in DG2.
Anyways, DG2 had PSR2 support dropped so we don't need this whole patch.
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 8 +++---
> drivers/gpu/drm/i915/i915_reg.h | 32 +---
> 2 files changed, 22 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 3f6fb7d67f84..5fa76b148f6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1445,7 +1445,7 @@ void intel_psr2_program_plane_sel_fetch(struct
> intel_plane *plane,
>
> val = plane_state ? plane_state->ctl : 0;
> val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE;
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(dev_priv, pipe,
> plane->id), val);
> if (!val || plane->id == PLANE_CURSOR)
> return;
>
> @@ -1453,19 +1453,19 @@ void intel_psr2_program_plane_sel_fetch(struct
> intel_plane *plane,
>
> val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
> val |= plane_state->uapi.dst.x1;
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(dev_priv, pipe,
> plane->id), val);
>
> /* TODO: consider auxiliary surfaces */
> x = plane_state->uapi.src.x1 >> 16;
> y = (plane_state->uapi.src.y1 >> 16) + clip->y1;
> val = y << 16 | x;
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(dev_priv, pipe,
> plane->id),
> val);
>
> /* Sizes are 0 based */
> val = (drm_rect_height(clip) - 1) << 16;
> val |= (drm_rect_width(_state->uapi.src) >> 16) - 1;
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(dev_priv, pipe,
> plane->id), val);
> }
>
> void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state
> *crtc_state)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c2853cc005ee..5bc8f22fa9a8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7471,6 +7471,7 @@ enum {
> #define _SEL_FETCH_PLANE_BASE_7_A0x70960
> #define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880
> #define _SEL_FETCH_PLANE_BASE_1_B0x70990
> +#define _DG2_SEL_FETCH_PLANE_BASE_1_B0x71890
>
> #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
>_SEL_FETCH_PLANE_BASE_1_A, \
> @@ -7481,31 +7482,34 @@ enum {
>_SEL_FETCH_PLANE_BASE_6_A, \
>_SEL_FETCH_PLANE_BASE_7_A, \
>_SEL_FETCH_PLANE_BASE_CUR_A)
> -#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A,
> _SEL_FETCH_PLANE_BASE_1_B)
> -#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
> - _SEL_FETCH_PLANE_BASE_1_A + \
> - _SEL_FETCH_PLANE_BASE_A(plane))
> +#define _SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) _PIPE(pipe,
> _SEL_FETCH_PLANE_BASE_1_A, \
> + DISPLAY_VER(dev_priv) >
> 12 ? \
> +
> _DG2_SEL_FETCH_PLANE_BASE_1_B : \
> + _SEL_FETCH_PLANE_BASE_1_B)
> +#define _SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane)
> (_SEL_FETCH_PLANE_BASE_1(dev_priv, pipe) - \
> + _SEL_FETCH_PLANE_BASE_1_A
> + \
> +
> _SEL_FETCH_PLANE_BASE_A(plane))
>
> #define _SEL_FETCH_PLANE_CTL_1_A 0x70890
> -#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe,
> plane) + \
> +#define PLANE_SEL_FETCH_CTL(dev_priv, pipe, plane)
> _MMIO(_SEL_FETCH_PLANE_BASE(dev_priv, pipe, plane) + \
> _SEL_FETCH_PLANE_CTL_1_A - \
> _SEL_FETCH_PLANE_BASE_1_A)
> #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31)
>
> #define _SEL_FETCH_PLANE_POS_1_A 0x70894
> -#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe,
> plane) + \
> -_SEL_FETCH_PLANE_POS_1_A - \
>
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gt: Locking splats PREEMPT_RT
== Series Details == Series: drm/i915/gt: Locking splats PREEMPT_RT URL : https://patchwork.freedesktop.org/series/94480/ State : failure == Summary == Applying: drm/i915/gt: Queue and wait for the irq_work item. Applying: drm/i915/gt: Use spin_lock_irq() instead of local_irq_disable() + spin_lock() Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gt/intel_execlists_submission.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gt/intel_execlists_submission.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_execlists_submission.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0002 drm/i915/gt: Use spin_lock_irq() instead of local_irq_disable() + spin_lock() When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".
[Intel-gfx] [PATCH 0/2] drm/i915/gt: Locking splats PREEMPT_RT
Clark Williams reported two issues with the i915 driver running on PREEMPT_RT. While #1 looks simple I have no idea about #2 thus the RFC. Sebastian
[Intel-gfx] [PATCH 1/2] drm/i915/gt: Queue and wait for the irq_work item.
Disabling interrupts and invoking the irq_work function directly breaks
on PREEMPT_RT.
PREEMPT_RT does not invoke all irq_work from hardirq context because
some of the user have spinlock_t locking in the callback function.
These locks are then turned into a sleeping locks which can not be
acquired with disabled interrupts.
Using irq_work_queue() has the benefit that the irqwork will be invoked
in the regular context. In general there is "no" delay between enqueuing
the callback and its invocation because the interrupt is raised right
away on architectures which support it (which includes x86).
Use irq_work_queue() + irq_work_sync() instead invoking the callback
directly.
Reported-by: Clark Williams
Signed-off-by: Sebastian Andrzej Siewior
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index 38cc42783dfb2..594dec2f76954 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -318,10 +318,9 @@ void __intel_breadcrumbs_park(struct intel_breadcrumbs *b)
/* Kick the work once more to drain the signalers, and disarm the irq */
irq_work_sync(>irq_work);
while (READ_ONCE(b->irq_armed) && !atomic_read(>active)) {
- local_irq_disable();
- signal_irq_work(>irq_work);
- local_irq_enable();
+ irq_work_queue(>irq_work);
cond_resched();
+ irq_work_sync(>irq_work);
}
}
--
2.33.0
[Intel-gfx] [RFC PATCH 2/2] drm/i915/gt: Use spin_lock_irq() instead of local_irq_disable() + spin_lock()
execlists_dequeue() is invoked from a function which uses
local_irq_disable() to disable interrupts so the spin_lock() behaves
like spin_lock_irq().
This breaks PREEMPT_RT because local_irq_disable() + spin_lock() is not
the same as spin_lock_irq().
execlists_dequeue_irq() and execlists_dequeue() has each one caller
only. If intel_engine_cs::active::lock is acquired and released with the
_irq suffix then it behaves almost as if execlists_dequeue() would be
invoked with disabled interrupts. The difference is the last part of the
function which is then invoked with enabled interrupts.
I can't tell if this makes a difference. From looking at it, it might
work to move the last unlock at the end of the function as I didn't find
anything that would acquire the lock again.
Reported-by: Clark Williams
Signed-off-by: Sebastian Andrzej Siewior
---
.../drm/i915/gt/intel_execlists_submission.c| 17 +
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index fc77592d88a96..2ec1dd352960b 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1265,7 +1265,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* and context switches) submission.
*/
- spin_lock(>active.lock);
+ spin_lock_irq(>active.lock);
/*
* If the queue is higher priority than the last
@@ -1365,7 +1365,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* Even if ELSP[1] is occupied and not worthy
* of timeslices, our queue might be.
*/
- spin_unlock(>active.lock);
+ spin_unlock_irq(>active.lock);
return;
}
}
@@ -1391,7 +1391,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
if (last && !can_merge_rq(last, rq)) {
spin_unlock(>base.active.lock);
- spin_unlock(>active.lock);
+ spin_unlock_irq(>active.lock);
return; /* leave this for another sibling */
}
@@ -1552,7 +1552,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
* interrupt for secondary ports).
*/
execlists->queue_priority_hint = queue_prio(execlists);
- spin_unlock(>active.lock);
+ spin_unlock_irq(>active.lock);
/*
* We can skip poking the HW if we ended up with exactly the same set
@@ -1578,13 +1578,6 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
}
}
-static void execlists_dequeue_irq(struct intel_engine_cs *engine)
-{
- local_irq_disable(); /* Suspend interrupts across request submission */
- execlists_dequeue(engine);
- local_irq_enable(); /* flush irq_work (e.g. breadcrumb enabling) */
-}
-
static void clear_ports(struct i915_request **ports, int count)
{
memset_p((void **)ports, NULL, count);
@@ -2377,7 +2370,7 @@ static void execlists_submission_tasklet(struct
tasklet_struct *t)
}
if (!engine->execlists.pending[0]) {
- execlists_dequeue_irq(engine);
+ execlists_dequeue(engine);
start_timeslice(engine);
}
--
2.33.0
Re: [Intel-gfx] [PATCH] kernel/locking: Add context to ww_mutex_trylock.
On Wed, Sep 08, 2021 at 12:14:23PM +0200, Peter Zijlstra wrote:
> On Tue, Sep 07, 2021 at 03:20:44PM +0200, Maarten Lankhorst wrote:
> > i915 will soon gain an eviction path that trylock a whole lot of locks
> > for eviction, getting dmesg failures like below:
> >
> > BUG: MAX_LOCK_DEPTH too low!
> > turning off the locking correctness validator.
> > depth: 48 max: 48!
> > 48 locks held by i915_selftest/5776:
> > #0: 888101a79240 (>mutex){}-{3:3}, at:
> > __driver_attach+0x88/0x160
> > #1: c99778c0 (reservation_ww_class_acquire){+.+.}-{0:0}, at:
> > i915_vma_pin.constprop.63+0x39/0x1b0 [i915]
> > #2: 88800cf74de8 (reservation_ww_class_mutex){+.+.}-{3:3}, at:
> > i915_vma_pin.constprop.63+0x5f/0x1b0 [i915]
> > #3: 88810c7f9e38 (>mutex/1){+.+.}-{3:3}, at:
> > i915_vma_pin_ww+0x1c4/0x9d0 [i915]
> > #4: 88810bad5768 (reservation_ww_class_mutex){+.+.}-{3:3}, at:
> > i915_gem_evict_something+0x110/0x860 [i915]
> > #5: 88810bad60e8 (reservation_ww_class_mutex){+.+.}-{3:3}, at:
> > i915_gem_evict_something+0x110/0x860 [i915]
> > ...
> > #46: 88811964d768 (reservation_ww_class_mutex){+.+.}-{3:3}, at:
> > i915_gem_evict_something+0x110/0x860 [i915]
> > #47: 88811964e0e8 (reservation_ww_class_mutex){+.+.}-{3:3}, at:
> > i915_gem_evict_something+0x110/0x860 [i915]
> > INFO: lockdep is turned off.
>
> > As an intermediate solution, add an acquire context to ww_mutex_trylock,
> > which allows us to do proper nesting annotations on the trylocks, making
> > the above lockdep splat disappear.
>
> Fair enough I suppose.
What's maybe missing from the commit message
- we'll probably use this for ttm too eventually
- even when we add full ww_mutex locking we'll still have the trylock
fastpath. This is because we have a lock inversion against list locks in
these eviction paths, and the slow path unroll to drop that list lock is
a bit nasty (and defintely expensive).
iow even long term this here is needed in some form I think.
-Daniel
>
> > +/**
> > + * ww_mutex_trylock - tries to acquire the w/w mutex with optional acquire
> > context
> > + * @lock: mutex to lock
> > + * @ctx: optional w/w acquire context
> > + *
> > + * Trylocks a mutex with the optional acquire context; no deadlock
> > detection is
> > + * possible. Returns 1 if the mutex has been acquired successfully, 0
> > otherwise.
> > + *
> > + * Unlike ww_mutex_lock, no deadlock handling is performed. However, if a
> > @ctx is
> > + * specified, -EALREADY and -EDEADLK handling may happen in calls to
> > ww_mutex_lock.
> > + *
> > + * A mutex acquired with this function must be released with
> > ww_mutex_unlock.
> > + */
> > +int __sched
> > +ww_mutex_trylock(struct ww_mutex *ww, struct ww_acquire_ctx *ctx)
> > +{
> > + bool locked;
> > +
> > + if (!ctx)
> > + return mutex_trylock(>base);
> > +
> > +#ifdef CONFIG_DEBUG_MUTEXES
> > + DEBUG_LOCKS_WARN_ON(ww->base.magic != >base);
> > +#endif
> > +
> > + preempt_disable();
> > + locked = __mutex_trylock(>base);
> > +
> > + if (locked) {
> > + ww_mutex_set_context_fastpath(ww, ctx);
> > + mutex_acquire_nest(>base.dep_map, 0, 1, >dep_map,
> > _RET_IP_);
> > + }
> > + preempt_enable();
> > +
> > + return locked;
> > +}
> > +EXPORT_SYMBOL(ww_mutex_trylock);
>
> You'll need a similar hunk in ww_rt_mutex.c
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
[Intel-gfx] [PULL] drm-misc-fixes
Hi Dave and Daniel, here's this week's PR for drm-misc-fixes. One patch is a potential deadlock in TTM, the other enables an additional plane in kmb. I'm slightly unhappy that the latter one ended up in -fixes as it's not a bugfix AFAICT. Best regards Thomas drm-misc-fixes-2021-09-08: Short summary of fixes pull: * kmb: Emable second plane * ttm: Fix potential deadlock during swap The following changes since commit fa0b1ef5f7a694f48e00804a391245f3471aa155: drm: Copy drm_wait_vblank to user before returning (2021-08-17 13:56:03 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2021-09-08 for you to fetch changes up to c8704b7ec182f9293e6a994310c7d4203428cdfb: drm/kmb: Enable alpha blended second plane (2021-09-07 10:10:30 -0700) Short summary of fixes pull: * kmb: Emable second plane * ttm: Fix potential deadlock during swap Edmund Dea (1): drm/kmb: Enable alpha blended second plane xinhui pan (1): drm/ttm: Fix a deadlock if the target BO is not idle during swap drivers/gpu/drm/kmb/kmb_drv.c | 8 ++-- drivers/gpu/drm/kmb/kmb_drv.h | 5 +++ drivers/gpu/drm/kmb/kmb_plane.c | 81 - drivers/gpu/drm/kmb/kmb_plane.h | 5 ++- drivers/gpu/drm/kmb/kmb_regs.h | 3 ++ drivers/gpu/drm/ttm/ttm_bo.c| 6 +-- 6 files changed, 90 insertions(+), 18 deletions(-) -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Felix Imendörffer
Re: [Intel-gfx] [PATCH] drm/i915/request: fix early tracepoints
On Fri, Sep 03, 2021 at 12:24:05PM +0100, Matthew Auld wrote:
> Currently we blow up in trace_dma_fence_init, when calling into
> get_driver_name or get_timeline_name, since both the engine and context
> might be NULL(or contain some garbage address) in the case of newly
> allocated slab objects via the request ctor. Note that we also use
> SLAB_TYPESAFE_BY_RCU here, which allows requests to be immediately
> freed, but delay freeing the underlying page by an RCU grace period.
> With this scheme requests can be re-allocated, at the same time as they
> are also being read by some lockless RCU lookup mechanism.
>
> One possible fix, since we don't yet have a fully initialised request
> when in the ctor, is just setting the context/engine as NULL and adding
> some extra handling in get_driver_name etc. And since the ctor is only
> called for new slab objects(i.e allocate new page and call the ctor for
> each object) it's safe to reset the context/engine prior to calling into
> dma_fence_init, since we can be certain that no one is doing an RCU
> lookup which might depend on peeking at the engine/context, like in
> active_engine(), since the object can't yet be externally visible.
>
> In the recycled case(which might also be externally visible) the request
> refcount always transitions from 0->1 after we set the context/engine
> etc, which should ensure it's valid to dereference the engine for
> example, when doing an RCU list-walk, so long as we can also increment
> the refcount first. If the refcount is already zero, then the request is
> considered complete/released. If it's non-zero, then the request might
> be in the process of being re-allocated, or potentially still in flight,
> however after successfully incrementing the refcount, it's possible to
> carefully inspect the request state, to determine if the request is
> still what we were looking for. Note that all externally visible
> requests returned to the cache must have zero refcount.
The commit message here is a bit confusing, since you start out with
describing a solution that you're not actually implementing it. I usually
do this by putting alternate solutions at the bottom, starting with "An
alternate solution would be ..." or so.
And then closing with why we don't do that, here it would be that we do
no longer have a need for these partially set up i915_requests, and
therefore just reverting that complication is the simplest solution.
> An alternative fix then is to instead move the dma_fence_init out from
> the request ctor. Originally this was how it was done, but it was moved
> in:
>
> commit 855e39e65cfc33a73724f1cc644ffc5754864a20
> Author: Chris Wilson
> Date: Mon Feb 3 09:41:48 2020 +
>
> drm/i915: Initialise basic fence before acquiring seqno
>
> where it looks like intel_timeline_get_seqno() relied on some of the
> rq->fence state, but that is no longer the case since:
>
> commit 12ca695d2c1ed26b2dcbb528b42813bd0f216cfc
> Author: Maarten Lankhorst
> Date: Tue Mar 23 16:49:50 2021 +0100
>
> drm/i915: Do not share hwsp across contexts any more, v8.
>
> intel_timeline_get_seqno() could also be cleaned up slightly by dropping
> the request argument.
>
> Moving dma_fence_init back out of the ctor, should ensure we have enough
> of the request initialised in case of trace_dma_fence_init.
> Functionally this should be the same, and is effectively what we were
> already open coding before, except now we also assign the fence->lock
> and fence->ops, but since these are invariant for recycled
> requests(which might be externally visible), and will therefore already
> hold the same value, it shouldn't matter. We still leave the
> spin_lock_init() in the ctor, since we can't re-init the rq->lock in
> case it is already held.
Holding rq->lock without having a full reference to it sounds like really
bad taste. I think it would be good to have a (kerneldoc) comment next to
i915_request.lock about this, with a FIXME. But separate patch.
> Fixes: 855e39e65cfc ("drm/i915: Initialise basic fence before acquiring
> seqno")
> Signed-off-by: Matthew Auld
> Cc: Michael Mason
> Cc: Daniel Vetter
With the commit message restructured a bit, and assuming this one actually
works:
Reviewed-by: Daniel Vetter
But I'm really not confident :-(
-Daniel
> ---
> drivers/gpu/drm/i915/i915_request.c | 11 ++-
> 1 file changed, 2 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_request.c
> b/drivers/gpu/drm/i915/i915_request.c
> index ce446716d092..79da5eca60af 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -829,8 +829,6 @@ static void __i915_request_ctor(void *arg)
> i915_sw_fence_init(>submit, submit_notify);
> i915_sw_fence_init(>semaphore, semaphore_notify);
>
> - dma_fence_init(>fence, _fence_ops, >lock, 0, 0);
> -
> rq->capture_list = NULL;
>
> init_llist_head(>execute_cb);
> @@ -905,17 +903,12 @@
Re: [Intel-gfx] [PATCH][next] drm/i915: clean up inconsistent indenting
On Thu, Sep 02, 2021 at 10:57:37PM +0100, Colin King wrote:
> From: Colin Ian King
>
> There is a statement that is indented one character too deeply,
> clean this up.
>
> Signed-off-by: Colin Ian King
Queued to drm-intel-gt-next, thanks for patch.
-Daniel
> ---
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index de5f9c86b9a4..aeb324b701ec 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2565,7 +2565,7 @@ __execlists_context_pre_pin(struct intel_context *ce,
> if (!__test_and_set_bit(CONTEXT_INIT_BIT, >flags)) {
> lrc_init_state(ce, engine, *vaddr);
>
> - __i915_gem_object_flush_map(ce->state->obj, 0,
> engine->context_size);
> + __i915_gem_object_flush_map(ce->state->obj, 0,
> engine->context_size);
> }
>
> return 0;
> --
> 2.32.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
Re: [Intel-gfx] [PATCH v2] drm/i915: Handle Intel igfx + Intel dgfx hybrid graphics setup
On Thu, Sep 02, 2021 at 04:01:40PM +0100, Tvrtko Ursulin wrote: > > On 02/09/2021 15:33, Daniel Vetter wrote: > > On Tue, Aug 31, 2021 at 02:18:15PM +0100, Tvrtko Ursulin wrote: > > > > > > On 31/08/2021 13:43, Daniel Vetter wrote: > > > > On Tue, Aug 31, 2021 at 10:15:03AM +0100, Tvrtko Ursulin wrote: > > > > > > > > > > On 30/08/2021 09:26, Daniel Vetter wrote: > > > > > > On Fri, Aug 27, 2021 at 03:44:42PM +0100, Tvrtko Ursulin wrote: > > > > > > > > > > > > > > On 27/08/2021 15:39, Tvrtko Ursulin wrote: > > > > > > > > From: Tvrtko Ursulin > > > > > > > > > > > > > > > > In short this makes i915 work for hybrid setups (DRI_PRIME=1 > > > > > > > > with Mesa) > > > > > > > > when rendering is done on Intel dgfx and scanout/composition on > > > > > > > > Intel > > > > > > > > igfx. > > > > > > > > > > > > > > > > Before this patch the driver was not quite ready for that > > > > > > > > setup, mainly > > > > > > > > because it was able to emit a semaphore wait between the two > > > > > > > > GPUs, which > > > > > > > > results in deadlocks because semaphore target location in HWSP > > > > > > > > is neither > > > > > > > > shared between the two, nor mapped in both GGTT spaces. > > > > > > > > > > > > > > > > To fix it the patch adds an additional check to a couple of > > > > > > > > relevant code > > > > > > > > paths in order to prevent using semaphores for inter-engine > > > > > > > > synchronisation between different driver instances. > > > > > > > > > > > > > > > > Patch also moves singly used i915_gem_object_last_write_engine > > > > > > > > to be > > > > > > > > private in its only calling unit (debugfs), while modifying it > > > > > > > > to only > > > > > > > > show activity belonging to the respective driver instance. > > > > > > > > > > > > > > > > What remains in this problem space is the question of the GEM > > > > > > > > busy ioctl. > > > > > > > > We have a somewhat ambigous comment there saying only status of > > > > > > > > native > > > > > > > > fences will be reported, which could be interpreted as either > > > > > > > > i915, or > > > > > > > > native to the drm fd. For now I have decided to leave that as > > > > > > > > is, meaning > > > > > > > > any i915 instance activity continues to be reported. > > > > > > > > > > > > > > > > v2: > > > > > > > > * Avoid adding rq->i915. (Chris) > > > > > > > > > > > > > > > > Signed-off-by: Tvrtko Ursulin > > > > > > > > > > > > Can't we just delete semaphore code and done? > > > > > > - GuC won't have it > > > > > > - media team benchmarked on top of softpin media driver, found no > > > > > > difference > > > > > > > > > > You have S-curve for saturated workloads or something else? How > > > > > thorough and > > > > > which media team I guess. > > > > > > > > > > From memory it was a nice win for some benchmarks (non-saturated > > > > > ones), but > > > > > as I have told you previously, we haven't been putting numbers in > > > > > commit > > > > > messages since it wasn't allowed. I may be able to dig out some more > > > > > details > > > > > if I went trawling through GEM channel IRC logs, although probably > > > > > not the > > > > > actual numbers since those were usually on pastebin. Or you go an > > > > > talk with > > > > > Chris since he probably remembers more details. Or you just decide > > > > > you don't > > > > > care and remove it. I wouldn't do that without putting the complete > > > > > story in > > > > > writing, but it's your call after all. > > > > > > > > Media has also changed, they're not using relocations anymore. > > > > > > Meaning you think it changes the benchmarking story? When coupled with > > > removal of GPU relocations then possibly yes. > > > > > > > Unless there's solid data performance tuning of any kind that gets in > > > > the > > > > way simply needs to be removed. Yes this is radical, but the codebase is > > > > in a state to require this. > > > > > > > > So either way we'd need to rebenchmark this if it's really required. > > > > Also > > > > > > Therefore can you share what benchmarks have been done or is it secret? > > > As > > > said, I think the non-saturated case was the more interesting one here. > > > > > > > if we really need this code still someone needs to fix the design, the > > > > current code is making layering violations an art form. > > > > > > > > > Anyway, without the debugfs churn it is more or less two line patch > > > > > to fix > > > > > igfx + dgfx hybrid setup. So while mulling it over this could go in. > > > > > I'd > > > > > just refine it to use a GGTT check instead of GT. And unless DG1 ends > > > > > up > > > > > being GuC only. > > > > > > > > The minimal robust fix here is imo to stop us from upcasting dma_fence > > > > to > > > > i915_request if it's not for our device. Not sprinkle code here into the > > > > semaphore code. We shouldn't even get this far with foreign fences. > > > > > > Device check does not
Re: [Intel-gfx] [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain
On Tue, Sep 07, 2021 at 10:19:10AM -0700, Matt Roper wrote: > The reset domain is shared between render and all compute engines, > so resetting one will affect the others. > > Note: Before performing a reset on an RCS or CCS engine, the GuC will > attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid > impacting other clients (since some shared modules will be reset). If > other engines are executing non-preemptable workloads, the impact is > unavoidable and some work may be lost. > > Bspec: 52549 > Original-patch-by: Michel Thierry > Cc: Tvrtko Ursulin > Cc: Vinay Belgaumkar > Signed-off-by: Daniele Ceraolo Spurio > Signed-off-by: Aravind Iddamsetty > Signed-off-by: Matt Roper Do we have igts validating this all properly? Specifically that the reset stats are incremented correctly for guilty respectively victimized contexts. This is necessary if it doesn't exist yet. Also you need a patch set here that fixes up the igts which have wrong assumptions about context isolation. -Daniel > --- > drivers/gpu/drm/i915/gt/intel_reset.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c > b/drivers/gpu/drm/i915/gt/intel_reset.c > index 91200c43951f..30598c1d070c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_reset.c > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c > @@ -507,6 +507,10 @@ static int gen11_reset_engines(struct intel_gt *gt, > [VECS1] = GEN11_GRDOM_VECS2, > [VECS2] = GEN11_GRDOM_VECS3, > [VECS3] = GEN11_GRDOM_VECS4, > + [CCS0] = GEN11_GRDOM_RENDER, > + [CCS1] = GEN11_GRDOM_RENDER, > + [CCS2] = GEN11_GRDOM_RENDER, > + [CCS3] = GEN11_GRDOM_RENDER, > }; > struct intel_engine_cs *engine; > intel_engine_mask_t tmp; > -- > 2.25.4 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
Re: [Intel-gfx] [PATCH 1/8] drm/i915/xehp: Define compute class and engine
On Tue, Sep 07, 2021 at 10:19:09AM -0700, Matt Roper wrote:
> Introduce a Compute Command Streamer (CCS), which has access to
> the media and GPGPU pipelines (but not the 3D pipeline).
>
> To begin with, define the compute class/engine common functions, based
> on the existing render ones.
>
> Bspec: 46167, 45544
> Original-patch-by: Michel Thierry
> Cc: Daniele Ceraolo Spurio
> Cc: Tvrtko Ursulin
> Cc: Vinay Belgaumkar
> Cc: Szymon Morek
> UMD (compute): https://github.com/intel/compute-runtime/pull/451
> Signed-off-by: Rodrigo Vivi
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Aravind Iddamsetty
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c| 28
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 ++-
> drivers/gpu/drm/i915/gt/intel_engine_user.c | 5 +++-
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 13 +
> drivers/gpu/drm/i915/i915_reg.h | 8 ++
> include/uapi/drm/i915_drm.h | 1 +
> 6 files changed, 57 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 332efea696a5..69944bd8c19d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -153,6 +153,34 @@ static const struct engine_info intel_engines[] = {
> { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
> },
> },
> + [CCS0] = {
> + .class = COMPUTE_CLASS,
> + .instance = 0,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE }
> + }
> + },
> + [CCS1] = {
> + .class = COMPUTE_CLASS,
> + .instance = 1,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE }
> + }
> + },
> + [CCS2] = {
> + .class = COMPUTE_CLASS,
> + .instance = 2,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE }
> + }
> + },
> + [CCS3] = {
> + .class = COMPUTE_CLASS,
> + .instance = 3,
> + .mmio_bases = {
> + { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
> + }
> + },
> };
>
> /**
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index bfbfe53c23dd..dcb9d8b2362a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -33,7 +33,8 @@
> #define VIDEO_ENHANCEMENT_CLASS 2
> #define COPY_ENGINE_CLASS3
> #define OTHER_CLASS 4
> -#define MAX_ENGINE_CLASS 4
> +#define COMPUTE_CLASS5
> +#define MAX_ENGINE_CLASS 5
> #define MAX_ENGINE_INSTANCE 7
>
> #define I915_MAX_SLICES 3
> @@ -95,6 +96,7 @@ struct i915_ctx_workarounds {
>
> #define I915_MAX_VCS 8
> #define I915_MAX_VECS4
> +#define I915_MAX_CCS 4
>
> /*
> * Engine IDs definitions.
> @@ -117,6 +119,11 @@ enum intel_engine_id {
> VECS2,
> VECS3,
> #define _VECS(n) (VECS0 + (n))
> + CCS0,
> + CCS1,
> + CCS2,
> + CCS3,
> +#define _CCS(n) (CCS0 + (n))
> I915_NUM_ENGINES
> #define INVALID_ENGINE ((enum intel_engine_id)-1)
> };
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 8f8bea08e734..d981621a7c30 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -47,6 +47,7 @@ static const u8 uabi_classes[] = {
> [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
> [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
> [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
> + [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
> };
>
> static int engine_cmp(void *priv, const struct list_head *A,
> @@ -139,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
> [COPY_ENGINE_CLASS] = "bcs",
> [VIDEO_DECODE_CLASS] = "vcs",
> [VIDEO_ENHANCEMENT_CLASS] = "vecs",
> + [COMPUTE_CLASS] = "ccs",
> };
>
> if (class >= ARRAY_SIZE(uabi_names) || !uabi_names[class])
> @@ -162,6 +164,7 @@ static int legacy_ring_idx(const struct legacy_ring *ring)
> [COPY_ENGINE_CLASS] = { BCS0, 1 },
> [VIDEO_DECODE_CLASS] = { VCS0, I915_MAX_VCS },
> [VIDEO_ENHANCEMENT_CLASS] = { VECS0, I915_MAX_VECS },
> + [COMPUTE_CLASS] = { CCS0, I915_MAX_CCS },
> };
>
> if (GEM_DEBUG_WARN_ON(ring->class >= ARRAY_SIZE(map)))
> @@ -190,7 +193,7 @@ static void add_legacy_ring(struct legacy_ring *ring,
> void intel_engines_driver_register(struct drm_i915_private *i915)
> {
>
[Intel-gfx] ✓ Fi.CI.IGT: success for DSI driver improvement (rev4)
== Series Details == Series: DSI driver improvement (rev4) URL : https://patchwork.freedesktop.org/series/94237/ State : success == Summary == CI Bug Log - changes from CI_DRM_10562_full -> Patchwork_20990_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_20990_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-snb7/igt@gem_cre...@create-massive.html - shard-apl: NOTRUN -> [DMESG-WARN][2] ([i915#3002]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-apl3/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@idempotent: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-snb6/igt@gem_ctx_persiste...@idempotent.html * igt@gem_ctx_persistence@many-contexts: - shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2410]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-tglb6/igt@gem_ctx_persiste...@many-contexts.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-tglb8/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_ctx_shared@q-in-order: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271]) +362 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-snb5/igt@gem_ctx_sha...@q-in-order.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-glk6/igt@gem_exec_fair@basic-n...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-glk1/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-iclb1/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_suspend@basic-s3: - shard-apl: [PASS][12] -> [DMESG-WARN][13] ([i915#180]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-apl7/igt@gem_exec_susp...@basic-s3.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-apl8/igt@gem_exec_susp...@basic-s3.html * igt@gem_mmap_gtt@cpuset-medium-copy-xy: - shard-glk: [PASS][14] -> [FAIL][15] ([i915#1888] / [i915#307]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10562/shard-glk3/igt@gem_mmap_...@cpuset-medium-copy-xy.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-glk4/igt@gem_mmap_...@cpuset-medium-copy-xy.html * igt@gem_pwrite@basic-exhaustion: - shard-apl: NOTRUN -> [WARN][16] ([i915#2658]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-apl6/igt@gem_pwr...@basic-exhaustion.html * igt@gem_userptr_blits@coherency-sync: - shard-tglb: NOTRUN -> [SKIP][17] ([fdo#110542]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-tglb3/igt@gem_userptr_bl...@coherency-sync.html * igt@gem_userptr_blits@readonly-unsync: - shard-tglb: NOTRUN -> [SKIP][18] ([i915#3297]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-tglb3/igt@gem_userptr_bl...@readonly-unsync.html * igt@gem_userptr_blits@vma-merge: - shard-kbl: NOTRUN -> [FAIL][19] ([i915#3318]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-kbl1/igt@gem_userptr_bl...@vma-merge.html * igt@gem_workarounds@suspend-resume: - shard-apl: NOTRUN -> [DMESG-WARN][20] ([i915#180]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-apl3/igt@gem_workarou...@suspend-resume.html * igt@gen9_exec_parse@bb-start-cmd: - shard-tglb: NOTRUN -> [SKIP][21] ([i915#2856]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-tglb3/igt@gen9_exec_pa...@bb-start-cmd.html * igt@i915_pm_rpm@dpms-non-lpsp: - shard-iclb: NOTRUN -> [SKIP][22] ([fdo#110892]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20990/shard-iclb7/igt@i915_pm_...@dpms-non-lpsp.html * igt@i915_pm_rpm@gem-execbuf-stress-pc8: - shard-tglb: NOTRUN -> [SKIP][23] ([fdo#109506] / [i915#2411]) [23]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Suspend / resume backup- and restore of LMEM. (rev3)
== Series Details == Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev3) URL : https://patchwork.freedesktop.org/series/94278/ State : success == Summary == CI Bug Log - changes from CI_DRM_10563 -> Patchwork_20991 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/index.html Known issues Here are the changes found in Patchwork_20991 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +23 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@amdgpu/amd_cs_nop@sync-compute0: - fi-kbl-r: NOTRUN -> [SKIP][2] ([fdo#109271]) +21 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-r/igt@amdgpu/amd_cs_...@sync-compute0.html * igt@core_hotunplug@unbind-rebind: - fi-bdw-5557u: NOTRUN -> [WARN][3] ([i915#3718]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-1115g4: [PASS][4] -> [FAIL][5] ([i915#1888]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html - fi-kbl-r: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-r/igt@gem_huc_c...@huc-copy.html * igt@gem_tiled_blits@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-soraka/igt@gem_tiled_bl...@basic.html * igt@i915_pm_rpm@module-reload: - fi-kbl-guc: [PASS][9] -> [FAIL][10] ([i915#2203] / [i915#579]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/fi-kbl-guc/igt@i915_pm_...@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-guc/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][11] ([i915#1886] / [i915#2291]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-edid-read: - fi-kbl-r: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-r/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#533]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html - fi-kbl-r: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#533]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-r/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@prime_vgem@basic-userptr: - fi-pnv-d510:NOTRUN -> [SKIP][16] ([fdo#109271]) +48 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-pnv-d510/igt@prime_v...@basic-userptr.html Possible fixes * igt@gem_exec_parallel@engines@userptr: - fi-pnv-d510:[INCOMPLETE][17] ([i915#299]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/fi-pnv-d510/igt@gem_exec_parallel@engi...@userptr.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-pnv-d510/igt@gem_exec_parallel@engi...@userptr.html * igt@gem_exec_suspend@basic-s0: - fi-kbl-soraka: [INCOMPLETE][19] ([i915#155]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20991/fi-kbl-soraka/igt@gem_exec_susp...@basic-s0.html - fi-tgl-1115g4: [FAIL][21] ([i915#1888]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10563/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html [22]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Suspend / resume backup- and restore of LMEM. (rev3)
== Series Details == Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev3) URL : https://patchwork.freedesktop.org/series/94278/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6374ded0c677 drm/i915/ttm: Implement a function to copy the contents of two TTM-base objects 9f81cf996425 drm/i915/gem: Implement a function to process all gem objects of a region 6b06e53cb3c8 drm/i915 Implement LMEM backup and restore for suspend / resume -:291: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #291: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 498 lines checked 9fa23d69f7ed drm/i915/gt: Register the migrate contexts with their engines e829df93558f drm/i915: Don't back up pinned LMEM context images and rings during suspend b3a1b351a5bf drm/i915: Reduce the number of objects subject to memcpy recover
Re: [Intel-gfx] [PATCH] drm/i915: deduplicate frequency dump on debugfs
On Wed, Sep 08, 2021 at 07:14:00AM -0700, Lucas De Marchi wrote:
On Wed, Sep 08, 2021 at 11:54:40AM +0300, Jani Nikula wrote:
On Tue, 07 Sep 2021, Lucas De Marchi wrote:
Although commit 9dd4b065446a ("drm/i915/gt: Move pm debug files into a
gt aware debugfs") says it was moving debug files to gt/, the
i915_frequency_info file was left behind and its implementation copied
into drivers/gpu/drm/i915/gt/debugfs_gt_pm.c. Over time we had several
patches having to change both places to keep them in sync (and some
patches failing to do so). The initial idea was to remove i915_frequency_info,
but there are user space tools using it. From a quick code search there
are other scripts and test tools besides igt, so it's not simply
updating igt to get rid of the older file.
Here we export a function using drm_printer as parameter and make
both show() implementations to call this same function. Aside from a few
variable name differences, for i915_frequency_info this brings a few
lines that were not previously printed: RP UP EI, RP UP THRESHOLD, RP
DOWN THRESHOLD and RP DOWN EI. These came in as part of
commit 9c878557b1eb ("drm/i915/gt: Use the RPM config register to
determine clk frequencies"), which didn't change both places.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 127 ++---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.h | 2 +
drivers/gpu/drm/i915/i915_debugfs.c | 227 +---
3 files changed, 74 insertions(+), 282 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index f6733f279890..6a27c011d0ff 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -240,9 +240,8 @@ static int drpc_show(struct seq_file *m, void *unused)
}
DEFINE_GT_DEBUGFS_ATTRIBUTE(drpc);
-static int frequency_show(struct seq_file *m, void *unused)
+void debugfs_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
The debugfs prefix belongs to debugfs, and I don't think we should have
non-static functions with that prefix.
I know it's in line with what's currently in the file, and I've
complained about it before, but apparently that hasn't been enough.
I was surprised by the prefix too.
intel_gt_pm_debugfs.[hc] - would that be better or do you have another
suggestion?
Something like the below:
renamed:drivers/gpu/drm/i915/gt/debugfs_gt.c ->
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
renamed:drivers/gpu/drm/i915/gt/debugfs_gt.h ->
drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
renamed:drivers/gpu/drm/i915/gt/debugfs_engines.c ->
drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.c
renamed:drivers/gpu/drm/i915/gt/debugfs_engines.h ->
drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h
renamed:drivers/gpu/drm/i915/gt/debugfs_gt_pm.c ->
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
renamed:drivers/gpu/drm/i915/gt/debugfs_gt_pm.h ->
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
and then rename the functions/macros in these files to follow th
filename
Lucas De Marchi
thanks
Lucas De Marchi
