[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Introduce Intel PXP (rev8)
== Series Details ==
Series: drm/i915: Introduce Intel PXP (rev8)
URL : https://patchwork.freedesktop.org/series/90503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10605 -> Patchwork_21096
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21096:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload:
- {fi-ehl-2}: [INCOMPLETE][1] ([i915#4136]) -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-ehl-2/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/fi-ehl-2/igt@i915_module_l...@reload.html
Known issues
Here are the changes found in Patchwork_21096 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-sdma:
- fi-kbl-7500u: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/fi-kbl-7500u/igt@amdgpu/amd_ba...@cs-sdma.html
* igt@core_hotunplug@unbind-rebind:
- fi-skl-6700k2: [PASS][4] -> [INCOMPLETE][5] ([i915#4130])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html
- fi-cfl-guc: [PASS][6] -> [INCOMPLETE][7] ([i915#4130])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][8] ([i915#4130])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html
- fi-icl-u2: [PASS][9] -> [INCOMPLETE][10] ([i915#4130])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
- fi-kbl-7567u: [PASS][11] -> [INCOMPLETE][12] ([i915#4130])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-7567u/igt@core_hotunp...@unbind-rebind.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/fi-kbl-7567u/igt@core_hotunp...@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([i915#2190])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#1155])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([fdo#111827]) +8 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][16] ([i915#4103]) +1 similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][17] ([fdo#109285])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: NOTRUN -> [SKIP][18] ([i915#1072]) +3 similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4: NOTRUN -> [SKIP][19] ([i915#3301])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- fi-kbl-guc: NOTRUN -> [FAIL][20] ([i915#2426] / [i915#3363])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/fi-kbl-guc/igt@run...@aborted.html
- fi-tgl-1115g4: NOTRUN -> [FAIL][21] ([i915#1602] / [i915#2722])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21096/fi-tgl-1115g4/igt@run...@aborted.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-7500u: [INCOMPLETE][22] ([i915#4130]) ->
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/4] drm/i915: rename debugfs_gt files
== Series Details == Series: series starting with [CI,1/4] drm/i915: rename debugfs_gt files URL : https://patchwork.freedesktop.org/series/94827/ State : success == Summary == CI Bug Log - changes from CI_DRM_10605_full -> Patchwork_21095_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_21095_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_sseu@engines: - shard-skl: NOTRUN -> [SKIP][1] ([fdo#109271]) +6 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/shard-skl1/igt@gem_ctx_s...@engines.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][2] -> [FAIL][3] ([i915#2842]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][4] ([i915#2842]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/shard-kbl2/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_params@rsvd2-dirt: - shard-tglb: NOTRUN -> [SKIP][7] ([fdo#109283]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/shard-tglb6/igt@gem_exec_par...@rsvd2-dirt.html * igt@gem_huc_copy@huc-copy: - shard-kbl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/shard-kbl2/igt@gem_huc_c...@huc-copy.html * igt@gem_media_vme: - shard-tglb: NOTRUN -> [SKIP][9] ([i915#284]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/shard-tglb6/igt@gem_media_vme.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: NOTRUN -> [DMESG-WARN][10] ([i915#180]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/shard-kbl1/igt@gem_workarou...@suspend-resume-fd.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1436] / [i915#716]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl5/igt@gen9_exec_pa...@allowed-single.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/shard-skl6/igt@gen9_exec_pa...@allowed-single.html * igt@gen9_exec_parse@valid-registers: - shard-tglb: NOTRUN -> [SKIP][13] ([i915#2856]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/shard-tglb6/igt@gen9_exec_pa...@valid-registers.html * igt@i915_pm_rpm@pc8-residency: - shard-tglb: NOTRUN -> [SKIP][14] ([fdo#109506] / [i915#2411]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/shard-tglb6/igt@i915_pm_...@pc8-residency.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([i915#2411] / [i915#456] / [i915#750]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb5/igt@i915_pm_...@system-suspend-execbuf.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/shard-tglb7/igt@i915_pm_...@system-suspend-execbuf.html * igt@i915_suspend@sysfs-reader: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl3/igt@i915_susp...@sysfs-reader.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/shard-kbl1/igt@i915_susp...@sysfs-reader.html * igt@kms_big_fb@linear-8bpp-rotate-270: - shard-tglb: NOTRUN -> [SKIP][19] ([fdo#111614]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/shard-tglb6/igt@kms_big...@linear-8bpp-rotate-270.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3777]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/shard-kbl3/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow: - shard-tglb: NOTRUN -> [SKIP][21] ([fdo#111615]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/shard-tglb6/igt@kms_big...@yf-tiled-addfb-size-offset-overflow.html * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc: - shard-kbl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#3886]) +2 similar issues [22]:
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Introduce Intel PXP (rev8)
== Series Details == Series: drm/i915: Introduce Intel PXP (rev8) URL : https://patchwork.freedesktop.org/series/90503/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./include/uapi/drm/i915_drm.h:1904: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Introduce Intel PXP (rev8)
== Series Details == Series: drm/i915: Introduce Intel PXP (rev8) URL : https://patchwork.freedesktop.org/series/90503/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen8_write32' - different lock
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Introduce Intel PXP (rev8)
== Series Details == Series: drm/i915: Introduce Intel PXP (rev8) URL : https://patchwork.freedesktop.org/series/90503/ State : warning == Summary == $ dim checkpatch origin/drm-tip e27175183684 drm/i915/pxp: Define PXP component interface -:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #31: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 49 lines checked 012116d10cdd mei: pxp: export pavp client to me client bus -:36: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #36: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 276 lines checked af5e58681019 drm/i915/pxp: define PXP device flag and kconfig -:47: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #47: FILE: drivers/gpu/drm/i915/i915_drv.h:1681: +#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \ + INTEL_INFO(dev_priv)->has_pxp) && \ + VDBOX_MASK(_priv->gt) -:47: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #47: FILE: drivers/gpu/drm/i915/i915_drv.h:1681: +#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \ + INTEL_INFO(dev_priv)->has_pxp) && \ + VDBOX_MASK(_priv->gt) total: 1 errors, 0 warnings, 1 checks, 33 lines checked 5dedc9b4fe19 drm/i915/pxp: allocate a vcs context for pxp usage -:99: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #99: new file mode 100644 -:128: ERROR:TRAILING_STATEMENTS: trailing statements should be on next line #128: FILE: drivers/gpu/drm/i915/pxp/intel_pxp.c:25: + for (engine = gt->engine_class[VIDEO_DECODE_CLASS][0]; !engine; engine++); total: 1 errors, 1 warnings, 0 checks, 170 lines checked d38c24e6e3ee drm/i915/pxp: Implement funcs to create the TEE channel -:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #79: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 145 lines checked fa9eb97502e6 drm/i915/pxp: set KCR reg init -:30: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #30: FILE: drivers/gpu/drm/i915/pxp/intel_pxp.c:14: + +} total: 0 errors, 0 warnings, 1 checks, 64 lines checked 930d960635dc drm/i915/pxp: Create the arbitrary session after boot -:107: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #107: new file mode 100644 -:392: CHECK:LINE_SPACING: Please don't use multiple blank lines #392: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h:36: + + total: 0 errors, 1 warnings, 1 checks, 345 lines checked 5e0df3748521 drm/i915/pxp: Implement arb session teardown -:63: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #63: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:153: +#define MI_FLUSH_DW_PROTECTED_MEM_EN (1<<22) ^ -:117: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #117: new file mode 100644 total: 0 errors, 1 warnings, 1 checks, 283 lines checked 82b3c64893e8 drm/i915/pxp: Implement PXP irq handler -:212: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #212: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 424 lines checked c6743ef21dc4 drm/i915/pxp: interfaces for using protected objects 4eded7843af4 drm/i915/pxp: start the arb session on demand 575446839b7e drm/i915/pxp: Enable PXP power management -:121: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #121: new file mode 100644 -:195: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #195: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_pm.h:18: +} +static inline void intel_pxp_resume(struct intel_pxp *pxp) total: 0 errors, 1 warnings, 1 checks, 238 lines checked cb48f7c7e563 drm/i915/pxp: Add plane decryption support -:36: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #36: v10 (Daniele): update PXP check again to match rework in earlier patches and total: 0 errors, 1 warnings, 0 checks, 155 lines checked 0f9612c2a9dc drm/i915/pxp: black pixels on pxp disabled -:169: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #169: FILE: drivers/gpu/drm/i915/i915_reg.h:11412: +#define PLANE_CSC_COEFF(pipe, plane, index)_MMIO_PLANE(plane, \ + _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ + _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) -:169: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #169: FILE: drivers/gpu/drm/i915/i915_reg.h:11412: +#define PLANE_CSC_COEFF(pipe, plane, index)
Re: [Intel-gfx] [PATCH 14/19] drm/i915/oprom: Basic sanitization
On Mon, May 17, 2021 at 02:57:33PM +0300, Jani Nikula wrote: On Mon, 12 Apr 2021, Matthew Auld wrote: From: Anshuman Gupta Sanitize OPROM header, CPD signature and OPROM PCI version. OPROM_HEADER, EXPANSION_ROM_HEADER and OPROM_MEU_BLOB structures and PCI struct offsets are provided by GSC counterparts. These are yet to be Documented in B.Spec. After successful sanitization, extract VBT from opregion image. So I don't understand what the point is with two consecutive patches where the latter rewrites a lot of the former. I actually wonder what's the point of this. Getting it from spi is already the fallback and looks much more complex. Yes, it's pretty detailed and document the format pretty well, but it still looks more complex than the initial code. Do you see additional benefit in this one? Lucas De Marchi
[Intel-gfx] [PATCH v10 13/17] drm/i915/pxp: Add plane decryption support
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PXP session is enabled.
2. Buffer object is protected.
v2:
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
v3:
- intel_pxp_gem_object_status() API changes.
v4: use intel_pxp_is_active (Daniele)
v5: rebase and use the new protected object status checker (Daniele)
v6: used plane state for plane_decryption to handle async flip
as suggested by Ville.
v7: check pxp session while plane decrypt state computation. [Ville]
removed pointless code. [Ville]
v8 (Daniele): update PXP check
v9: move decrypt check after icl_check_nv12_planes() when overlays
have fb set (Juston)
v10 (Daniele): update PXP check again to match rework in earlier patches and
don't consider protection valid if the object has not been used in an
execbuf beforehand.
Cc: Bommu Krishnaiah
Cc: Huang Sean Z
Cc: Gaurav Kumar
Cc: Ville Syrjälä
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Juston Li
Reviewed-by: Rodrigo Vivi
Reviewed-by: Uma Shankar #v9
---
drivers/gpu/drm/i915/display/intel_display.c | 26 +++
.../drm/i915/display/intel_display_types.h| 3 +++
.../drm/i915/display/skl_universal_plane.c| 15 ---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +-
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 9 ---
drivers/gpu/drm/i915/pxp/intel_pxp.h | 7 +++--
7 files changed, 54 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f6c0c595f631..9369610378ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -71,6 +71,8 @@
#include "gt/intel_rps.h"
#include "gt/gen8_ppgtt.h"
+#include "pxp/intel_pxp.h"
+
#include "g4x_dp.h"
#include "g4x_hdmi.h"
#include "i915_drv.h"
@@ -9000,13 +9002,23 @@ static int intel_bigjoiner_add_affected_planes(struct
intel_atomic_state *state)
return 0;
}
+static bool bo_has_valid_encryption(struct drm_i915_gem_object *obj)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+
+ return intel_pxp_key_check(>gt.pxp, obj, false) == 0;
+}
+
static int intel_atomic_check_planes(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
struct intel_plane_state *plane_state;
struct intel_plane *plane;
+ struct intel_plane_state *new_plane_state;
+ struct intel_plane_state *old_plane_state;
struct intel_crtc *crtc;
+ const struct drm_framebuffer *fb;
int i, ret;
ret = icl_add_linked_planes(state);
@@ -9054,6 +9066,16 @@ static int intel_atomic_check_planes(struct
intel_atomic_state *state)
return ret;
}
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ new_plane_state = intel_atomic_get_new_plane_state(state,
plane);
+ old_plane_state = intel_atomic_get_old_plane_state(state,
plane);
+ fb = new_plane_state->hw.fb;
+ if (fb)
+ new_plane_state->decrypt =
bo_has_valid_encryption(intel_fb_obj(fb));
+ else
+ new_plane_state->decrypt = old_plane_state->decrypt;
+ }
+
return 0;
}
@@ -9340,6 +9362,10 @@ static int intel_atomic_check_async(struct
intel_atomic_state *state)
drm_dbg_kms(>drm, "Color range cannot be changed
in async flip\n");
return -EINVAL;
}
+
+ /* plane decryption is allow to change only in synchronous
flips */
+ if (old_plane_state->decrypt != new_plane_state->decrypt)
+ return -EINVAL;
}
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index e9e806d90eec..d75c8bd39abc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -625,6 +625,9 @@ struct intel_plane_state {
struct intel_fb_view view;
+ /* Plane pxp decryption state */
+ bool decrypt;
+
/* plane control register */
u32 ctl;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 724e7b04f3b6..55e3f093b951 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -18,6 +18,7 @@
#include "intel_sprite.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
+#include "pxp/intel_pxp.h"
static
[Intel-gfx] [PATCH v10 14/17] drm/i915/pxp: black pixels on pxp disabled
From: Anshuman Gupta
When protected sufaces has flipped and pxp session is disabled,
display black pixels by using plane color CTM correction.
v2:
- Display black pixels in async flip too.
v3:
- Removed the black pixels logic for async flip. [Ville]
- Used plane state to force black pixels. [Ville]
v4 (Daniele): update pxp_is_borked check.
v5: rebase on top of v9 plane decryption moving the decrypt check
(Juston)
Cc: Ville Syrjälä
Cc: Gaurav Kumar
Cc: Shankar Uma
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Juston Li
Reviewed-by: Rodrigo Vivi
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_display.c | 12 -
.../drm/i915/display/intel_display_types.h| 3 ++
.../drm/i915/display/skl_universal_plane.c| 36 ++-
drivers/gpu/drm/i915/i915_reg.h | 46 +++
4 files changed, 94 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9369610378ff..d786637b8b31 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9009,6 +9009,11 @@ static bool bo_has_valid_encryption(struct
drm_i915_gem_object *obj)
return intel_pxp_key_check(>gt.pxp, obj, false) == 0;
}
+static bool pxp_is_borked(struct drm_i915_gem_object *obj)
+{
+ return i915_gem_object_is_protected(obj) &&
!bo_has_valid_encryption(obj);
+}
+
static int intel_atomic_check_planes(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -9070,10 +9075,13 @@ static int intel_atomic_check_planes(struct
intel_atomic_state *state)
new_plane_state = intel_atomic_get_new_plane_state(state,
plane);
old_plane_state = intel_atomic_get_old_plane_state(state,
plane);
fb = new_plane_state->hw.fb;
- if (fb)
+ if (fb) {
new_plane_state->decrypt =
bo_has_valid_encryption(intel_fb_obj(fb));
- else
+ new_plane_state->force_black =
pxp_is_borked(intel_fb_obj(fb));
+ } else {
new_plane_state->decrypt = old_plane_state->decrypt;
+ new_plane_state->force_black =
old_plane_state->force_black;
+ }
}
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index d75c8bd39abc..9fa4ef06e377 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -628,6 +628,9 @@ struct intel_plane_state {
/* Plane pxp decryption state */
bool decrypt;
+ /* Plane state to display black pixels when pxp is borked */
+ bool force_black;
+
/* plane control register */
u32 ctl;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 55e3f093b951..c4adcb3e12b3 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1002,6 +1002,33 @@ static u32 skl_surf_address(const struct
intel_plane_state *plane_state,
}
}
+static void intel_load_plane_csc_black(struct intel_plane *intel_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
+ enum pipe pipe = intel_plane->pipe;
+ enum plane_id plane = intel_plane->id;
+ u16 postoff = 0;
+
+ drm_dbg_kms(_priv->drm, "plane color CTM to black %s:%d\n",
+ intel_plane->base.name, plane);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 0), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 1), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 2), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 3), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 4), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 5), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 0), postoff);
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 1), postoff);
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 2), postoff);
+}
+
static void
skl_program_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -1115,14 +1142,21 @@ skl_program_plane(struct intel_plane *plane,
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
plane_surf =
[Intel-gfx] [PATCH v10 02/17] mei: pxp: export pavp client to me client bus
From: Vitaly Lubart
Export PAVP client to work with i915 driver,
for binding it uses kernel component framework.
v2:drop debug prints, refactor match code to match mei_hdcp (Tomas)
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 229 +
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 270 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index f5fd5b786607..0e0bcd0da852 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -47,3 +47,5 @@ config INTEL_MEI_TXE
Intel Bay Trail
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index f1c76f7ee804..d8e5165917f2 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index ..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index ..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index ..f7380d387bab
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 - 2021 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .recv = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_component *comp_master =
[Intel-gfx] [PATCH v10 17/17] drm/i915/pxp: enable PXP for integrated Gen12
From: Daniele Ceraolo Spurio
Note that discrete cards can support PXP as well, but we haven't tested
on those yet so keeping it disabled for now.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d4a6a9dcf182..169837de395d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -865,6 +865,7 @@ static const struct intel_device_info jsl_info = {
}, \
TGL_CURSOR_OFFSETS, \
.has_global_mocs = 1, \
+ .has_pxp = 1, \
.display.has_dsb = 1
static const struct intel_device_info tgl_info = {
@@ -891,6 +892,7 @@ static const struct intel_device_info rkl_info = {
#define DGFX_FEATURES \
.memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
.has_llc = 0, \
+ .has_pxp = 0, \
.has_snoop = 1, \
.is_dgfx = 1
--
2.25.1
[Intel-gfx] [PATCH v10 07/17] drm/i915/pxp: Create the arbitrary session after boot
From: "Huang, Sean Z"
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session will need to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
The session ID is exposed as part of the uapi so it can be used as part
of userspace commands.
v2: use gt->uncore->rpm (Chris)
v3: s/arb_is_in_play/arb_is_valid (Chris), move set-up to the new
init_hw function
v4: move interface defs to separate header, set arb_is valid to false
on fini (Rodrigo)
v5: handle async component binding
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 12 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 74
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 15
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 87 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +
.../drm/i915/pxp/intel_pxp_tee_interface.h| 37
drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 10 +++
include/uapi/drm/i915_drm.h | 3 +
10 files changed, 244 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1d2fd5b9efd2..a161a1edfc92 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -283,6 +283,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 3fd9306b2ce4..53dd3001c5be 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -3,6 +3,7 @@
* Copyright(c) 2020 Intel Corporation.
*/
#include "intel_pxp.h"
+#include "intel_pxp_session.h"
#include "intel_pxp_tee.h"
#include "gt/intel_context.h"
#include "i915_drv.h"
@@ -13,6 +14,11 @@ struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)
}
+bool intel_pxp_is_active(const struct intel_pxp *pxp)
+{
+ return pxp->arb_is_valid;
+}
+
/* KCR register definitions */
#define KCR_INIT _MMIO(0x320f0)
/* Setting KCR Init bit is required after system boot */
@@ -70,6 +76,8 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (!HAS_PXP(gt->i915))
return;
+ mutex_init(>tee_mutex);
+
ret = create_vcs_context(pxp);
if (ret)
return;
@@ -91,6 +99,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
if (!intel_pxp_is_enabled(pxp))
return;
+ pxp->arb_is_valid = false;
+
intel_pxp_tee_component_fini(pxp);
destroy_vcs_context(pxp);
@@ -99,6 +109,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
void intel_pxp_init_hw(struct intel_pxp *pxp)
{
kcr_pxp_enable(pxp_to_gt(pxp));
+
+ intel_pxp_create_arb_session(pxp);
}
void intel_pxp_fini_hw(struct intel_pxp *pxp)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index cd6560b2605c..2960e8338c82 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -15,6 +15,8 @@ static inline bool intel_pxp_is_enabled(const struct
intel_pxp *pxp)
#ifdef CONFIG_DRM_I915_PXP
struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp);
+bool intel_pxp_is_active(const struct intel_pxp *pxp);
+
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
new file mode 100644
index ..3331868f354c
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "drm/i915_drm.h"
+#include "i915_drv.h"
+
+#include "intel_pxp.h"
+#include "intel_pxp_session.h"
+#include "intel_pxp_tee.h"
+#include "intel_pxp_types.h"
+
+#define ARB_SESSION I915_PROTECTED_CONTENT_DEFAULT_SESSION /* shorter define */
+
+#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
+
+static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
[Intel-gfx] [PATCH v10 10/17] drm/i915/pxp: interfaces for using protected objects
From: Daniele Ceraolo Spurio
This api allow user mode to create protected buffers and to mark
contexts as making use of such objects. Only when using contexts
marked in such a way is the execution guaranteed to work as expected.
Contexts can only be marked as using protected content at creation time
(i.e. the parameter is immutable) and they must be both bannable and not
recoverable. Given that the protected session gets invalidated on
suspend, contexts created this way hold a runtime pm wakeref until
they're either destroyed or invalidated.
All protected objects and contexts will be considered invalid when the
PXP session is destroyed and all new submissions using them will be
rejected. All intel contexts within the invalidated gem contexts will be
marked banned. Userspace can detect that an invalidation has occurred via
the RESET_STATS ioctl, where we report it the same way as a ban due to a
hang.
v5: squash patches, rebase on proto_ctx, update kerneldoc
v6: rebase on obj create_ext changes
v7: Use session counter to check if an object it valid, hold wakeref in
context, don't add a new flag to RESET_STATS (Daniel)
v8: don't increase guilty count for contexts banned during pxp
invalidation (Rodrigo)
v9: better comments, avoid wakeref put race between pxp_inval and
context_close, add usage examples (Rodrigo)
Signed-off-by: Alan Previn
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Bommu Krishnaiah
Cc: Rodrigo Vivi
Cc: Chris Wilson
Cc: Lionel Landwerlin
Cc: Jason Ekstrand
Cc: Daniel Vetter
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 95 +++---
drivers/gpu/drm/i915/gem/i915_gem_context.h | 6 ++
.../gpu/drm/i915/gem/i915_gem_context_types.h | 28 ++
drivers/gpu/drm/i915/gem/i915_gem_create.c| 72 ++
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 18
drivers/gpu/drm/i915/gem/i915_gem_object.c| 1 +
drivers/gpu/drm/i915/gem/i915_gem_object.h| 6 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 8 ++
.../gpu/drm/i915/gem/selftests/mock_context.c | 4 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 78 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 12 +++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 6 ++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 9 ++
include/uapi/drm/i915_drm.h | 96 ++-
14 files changed, 404 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c2ab0e22db0a..4ef643e20849 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -77,6 +77,8 @@
#include "gt/intel_gpu_commands.h"
#include "gt/intel_ring.h"
+#include "pxp/intel_pxp.h"
+
#include "i915_gem_context.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
@@ -186,10 +188,13 @@ static int validate_priority(struct drm_i915_private
*i915,
return 0;
}
-static void proto_context_close(struct i915_gem_proto_context *pc)
+static void proto_context_close(struct drm_i915_private *i915,
+ struct i915_gem_proto_context *pc)
{
int i;
+ if (pc->pxp_wakeref)
+ intel_runtime_pm_put(>runtime_pm, pc->pxp_wakeref);
if (pc->vm)
i915_vm_put(pc->vm);
if (pc->user_engines) {
@@ -241,6 +246,33 @@ static int proto_context_set_persistence(struct
drm_i915_private *i915,
return 0;
}
+static int proto_context_set_protected(struct drm_i915_private *i915,
+ struct i915_gem_proto_context *pc,
+ bool protected)
+{
+ int ret = 0;
+
+ if (!protected) {
+ pc->uses_protected_content = false;
+ } else if (!intel_pxp_is_enabled(>gt.pxp)) {
+ ret = -ENODEV;
+ } else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) ||
+ !(pc->user_flags & BIT(UCONTEXT_BANNABLE))) {
+ ret = -EPERM;
+ } else {
+ pc->uses_protected_content = true;
+
+ /*
+* protected context usage requires the PXP session to be up,
+* which in turn requires the device to be active.
+*/
+ pc->pxp_wakeref = intel_runtime_pm_get(>runtime_pm);
+ ret = intel_pxp_wait_for_arb_start(>gt.pxp);
+ }
+
+ return ret;
+}
+
static struct i915_gem_proto_context *
proto_context_create(struct drm_i915_private *i915, unsigned int flags)
{
@@ -269,7 +301,7 @@ proto_context_create(struct drm_i915_private *i915,
unsigned int flags)
return pc;
proto_close:
- proto_context_close(pc);
+ proto_context_close(i915, pc);
return err;
}
@@ -693,6 +725,8 @@ static int set_proto_ctx_param(struct drm_i915_file_private
*fpriv,
ret = -EPERM;
[Intel-gfx] [PATCH v10 09/17] drm/i915/pxp: Implement PXP irq handler
From: "Huang, Sean Z"
The HW will generate a teardown interrupt when session termination is
required, which requires i915 to submit a terminating batch. Once the HW
is done with the termination it will generate another interrupt, at
which point it is safe to re-create the session.
Since the termination and re-creation flow is something we want to
trigger from the driver as well, use a common work function that can be
called both from the irq handler and from the driver set-up flows, which
has the addded benefit of allowing us to skip any extra locks because
the work itself serializes the operations.
v2: use struct completion instead of bool (Chris)
v3: drop locks, clean up functions and improve comments (Chris),
move to common work function.
v4: improve comments, simplify wait logic (Rodrigo)
v5: unconditionally set interrupts, rename state_attacked var (Rodrigo)
Signed-off-by: Alan Previn
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 66 ++--
drivers/gpu/drm/i915/pxp/intel_pxp.h | 8 ++
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 100 +++
drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 32 ++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 54 +-
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 5 +-
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 8 +-
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 18
11 files changed, 284 insertions(+), 16 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 86ea9c98e815..892e17549314 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -284,6 +284,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_cmd.o \
+ pxp/intel_pxp_irq.o \
pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index b2de83be4d97..699a74582d32 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -13,6 +13,7 @@
#include "intel_lrc_reg.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp_irq.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -64,6 +65,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(>pxp, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
@@ -196,6 +200,9 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
+
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0);
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0);
}
void gen11_gt_irq_postinstall(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2853cc005ee..84bc884bd474 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8117,6 +8117,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 8a4755b235ad..584c998f79be 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -2,7 +2,9 @@
/*
* Copyright(c) 2020 Intel Corporation.
*/
+#include
#include "intel_pxp.h"
+#include "intel_pxp_irq.h"
#include "intel_pxp_session.h"
#include "intel_pxp_tee.h"
#include "gt/intel_context.h"
@@ -78,6 +80,16 @@ void intel_pxp_init(struct intel_pxp *pxp)
mutex_init(>tee_mutex);
+ /*
+* we'll use the completion to check if there is a termination pending,
+* so we start it as completed and we reinit it when a termination
+* is triggered.
+*/
+ init_completion(>termination);
+ complete_all(>termination);
+
+ INIT_WORK(>session_work, intel_pxp_session_work);
+
ret = create_vcs_context(pxp);
if (ret)
return;
@@ -106,19 +118,61 @@ void
[Intel-gfx] [PATCH v10 08/17] drm/i915/pxp: Implement arb session teardown
From: "Huang, Sean Z"
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. Additionally, we want to emit a
teardown operation to make sure we're clean on boot and resume
v2: emit in the ring, use high prio request (Chris)
v3: better defines, stalling flush, cleaned up and renamed submission
funcs (Chris)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 7 +-
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 141 +++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 ++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 29
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 1 +
7 files changed, 212 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a161a1edfc92..86ea9c98e815 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -283,6 +283,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_cmd.o \
pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 1c3af0fc0456..ec2a0a566c40 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -28,10 +28,13 @@
#define INSTR_26_TO_24_MASK0x700
#define INSTR_26_TO_24_SHIFT 24
+#define __INSTR(client) ((client) << INSTR_CLIENT_SHIFT)
+
/*
* Memory interface instructions used by the kernel
*/
-#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+#define MI_INSTR(opcode, flags) \
+ (__INSTR(INSTR_MI_CLIENT) | (opcode) << 23 | (flags))
/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
#define MI_GLOBAL_GTT(1<<22)
@@ -57,6 +60,7 @@
#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
#define MI_SUSPEND_FLUSH_EN (1<<0)
#define MI_SET_APPID MI_INSTR(0x0e, 0)
+#define MI_SET_APPID_SESSION_ID(x) ((x) << 0)
#define MI_OVERLAY_FLIPMI_INSTR(0x11, 0)
#define MI_OVERLAY_CONTINUE (0x0<<21)
#define MI_OVERLAY_ON(0x1<<21)
@@ -146,6 +150,7 @@
#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
#define MI_SRM_LRM_GLOBAL_GTT(1<<22)
#define MI_FLUSH_DWMI_INSTR(0x26, 1) /* for GEN6 */
+#define MI_FLUSH_DW_PROTECTED_MEM_EN (1<<22)
#define MI_FLUSH_DW_STORE_INDEX (1<<21)
#define MI_INVALIDATE_TLB(1<<18)
#define MI_FLUSH_DW_OP_STOREDW (1<<14)
@@ -272,6 +277,19 @@
#define MI_MATH_REG_ZF 0x32
#define MI_MATH_REG_CF 0x33
+/*
+ * Media instructions used by the kernel
+ */
+#define MEDIA_INSTR(pipe, op, sub_op, flags) \
+ (__INSTR(INSTR_RC_CLIENT) | (pipe) << INSTR_SUBCLIENT_SHIFT | \
+ (op) << INSTR_26_TO_24_SHIFT | (sub_op) << 16 | (flags))
+
+#define MFX_WAIT MEDIA_INSTR(1, 0, 0, 0)
+#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAGREG_BIT(8)
+#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAGREG_BIT(9)
+
+#define CRYPTO_KEY_EXCHANGEMEDIA_INSTR(2, 6, 9, 0)
+
/*
* Commands used only by the command parser
*/
@@ -328,8 +346,6 @@
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
-#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
-
#define COLOR_BLT ((0x2<<29)|(0x40<<22))
#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 53dd3001c5be..8a4755b235ad 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -108,9 +108,14 @@ void intel_pxp_fini(struct intel_pxp *pxp)
void intel_pxp_init_hw(struct intel_pxp *pxp)
{
+ int ret;
+
kcr_pxp_enable(pxp_to_gt(pxp));
- intel_pxp_create_arb_session(pxp);
+ /* always emit a full termination to clean the state */
+ ret = intel_pxp_terminate_arb_session_and_global(pxp);
+ if (!ret)
+ intel_pxp_create_arb_session(pxp);
}
void intel_pxp_fini_hw(struct intel_pxp *pxp)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
new file mode 100644
index ..80678dafde15
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
[Intel-gfx] [PATCH v10 15/17] drm/i915/pxp: add pxp debugfs
From: Daniele Ceraolo Spurio
2 debugfs files, one to query the current status of the pxp session and one
to trigger an invalidation for testing.
v2: rename debugfs, fix date (Alan)
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by : Alan Previn
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/debugfs_gt.c | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 78
drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.h | 21 ++
4 files changed, 102 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index ee31152ad764..a51c19275ab2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -284,6 +284,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_cmd.o \
+ pxp/intel_pxp_debugfs.o \
pxp/intel_pxp_irq.o \
pxp/intel_pxp_pm.o \
pxp/intel_pxp_session.o \
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c
b/drivers/gpu/drm/i915/gt/debugfs_gt.c
index 591eb60785db..c27847ddb796 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c
@@ -9,6 +9,7 @@
#include "debugfs_gt.h"
#include "debugfs_gt_pm.h"
#include "intel_sseu_debugfs.h"
+#include "pxp/intel_pxp_debugfs.h"
#include "uc/intel_uc_debugfs.h"
#include "i915_drv.h"
@@ -28,6 +29,7 @@ void debugfs_gt_register(struct intel_gt *gt)
intel_sseu_debugfs_register(gt, root);
intel_uc_debugfs_register(>uc, root);
+ intel_pxp_debugfs_register(>pxp, root);
}
void intel_gt_debugfs_register_files(struct dentry *root,
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
new file mode 100644
index ..cbb1853676cc
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include
+#include
+
+#include "gt/debugfs_gt.h"
+#include "pxp/intel_pxp.h"
+#include "pxp/intel_pxp_irq.h"
+#include "i915_drv.h"
+
+static int pxp_info_show(struct seq_file *m, void *data)
+{
+ struct intel_pxp *pxp = m->private;
+ struct drm_printer p = drm_seq_file_printer(m);
+ bool enabled = intel_pxp_is_enabled(pxp);
+
+ if (!enabled) {
+ drm_printf(, "pxp disabled\n");
+ return 0;
+ }
+
+ drm_printf(, "active: %s\n", yesno(intel_pxp_is_active(pxp)));
+ drm_printf(, "instance counter: %u\n", pxp->key_instance);
+
+ return 0;
+}
+DEFINE_GT_DEBUGFS_ATTRIBUTE(pxp_info);
+
+static int pxp_terminate_get(void *data, u64 *val)
+{
+ /* nothing to read */
+ return -EPERM;
+}
+
+static int pxp_terminate_set(void *data, u64 val)
+{
+ struct intel_pxp *pxp = data;
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
+ if (!intel_pxp_is_active(pxp))
+ return -ENODEV;
+
+ /* simulate a termination interrupt */
+ spin_lock_irq(>irq_lock);
+ intel_pxp_irq_handler(pxp,
GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT);
+ spin_unlock_irq(>irq_lock);
+
+ if (!wait_for_completion_timeout(>termination,
+msecs_to_jiffies(100)))
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(pxp_terminate_fops, pxp_terminate_get,
pxp_terminate_set, "%llx\n");
+void intel_pxp_debugfs_register(struct intel_pxp *pxp, struct dentry *gt_root)
+{
+ static const struct debugfs_gt_file files[] = {
+ { "info", _info_fops, NULL },
+ { "terminate_state", _terminate_fops, NULL },
+ };
+ struct dentry *root;
+
+ if (!gt_root)
+ return;
+
+ if (!HAS_PXP((pxp_to_gt(pxp)->i915)))
+ return;
+
+ root = debugfs_create_dir("pxp", gt_root);
+ if (IS_ERR(root))
+ return;
+
+ intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), pxp);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.h
new file mode 100644
index ..7e0c3d2f5d7e
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef __INTEL_PXP_DEBUGFS_H__
+#define __INTEL_PXP_DEBUGFS_H__
+
+struct intel_pxp;
+struct dentry;
+
+#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_debugfs_register(struct intel_pxp *pxp, struct dentry *root);
+#else
+static inline void
+intel_pxp_debugfs_register(struct intel_pxp *pxp, struct dentry *root)
+{
+}
+#endif
+
+#endif /* __INTEL_PXP_DEBUGFS_H__ */
--
2.25.1
[Intel-gfx] [PATCH v10 16/17] drm/i915/pxp: add PXP documentation
From: Daniele Ceraolo Spurio
Now that all the pieces are in place we can add a description of how the
feature works. Also modify the comments in struct intel_pxp into
kerneldoc.
v2: improve doc (Rodrigo)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Daniel Vetter
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
---
Documentation/gpu/i915.rst | 8
drivers/gpu/drm/i915/pxp/intel_pxp.c | 29 -
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 47 --
3 files changed, 71 insertions(+), 13 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 311e10400708..b7d801993bfa 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -471,6 +471,14 @@ Object Tiling IOCTLs
.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
:doc: buffer object tiling
+Protected Objects
+-
+
+.. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp.c
+ :doc: PXP
+
+.. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+
Microcontrollers
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 6f0755dbd6ac..0cc1b4a9c993 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -11,6 +11,34 @@
#include "gt/intel_context.h"
#include "i915_drv.h"
+/**
+ * DOC: PXP
+ *
+ * PXP (Protected Xe Path) is a feature available in Gen12 and newer platforms.
+ * It allows execution and flip to display of protected (i.e. encrypted)
+ * objects. The SW support is enabled via the CONFIG_DRM_I915_PXP kconfig.
+ *
+ * Objects can opt-in to PXP encryption at creation time via the
+ * I915_GEM_CREATE_EXT_PROTECTED_CONTENT create_ext flag. For objects to be
+ * correctly protected they must be used in conjunction with a context created
+ * with the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. See the documentation
+ * of those two uapi flags for details and restrictions.
+ *
+ * Protected objects are tied to a pxp session; currently we only support one
+ * session, which i915 manages and whose index is available in the uapi
+ * (I915_PROTECTED_CONTENT_DEFAULT_SESSION) for use in instructions targeting
+ * protected objects.
+ * The session is invalidated by the HW when certain events occur (e.g.
+ * suspend/resume). When this happens, all the objects that were used with the
+ * session are marked as invalid and all contexts marked as using protected
+ * content are banned. Any further attempt at using them in an execbuf call is
+ * rejected, while flips are converted to black frames.
+ *
+ * Some of the PXP setup operations are performed by the Management Engine,
+ * which is handled by the mei driver; communication between i915 and mei is
+ * performed via the mei_pxp component module.
+ */
+
struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)
{
return container_of(pxp, struct intel_gt, pxp);
@@ -267,4 +295,3 @@ void intel_pxp_invalidate(struct intel_pxp *pxp)
}
spin_unlock_irq(>gem.contexts.lock);
}
-
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index ae24064bb57e..73ef7d1754e1 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -16,42 +16,65 @@
struct intel_context;
struct i915_pxp_component;
+/**
+ * struct intel_pxp - pxp state
+ */
struct intel_pxp {
+ /**
+* @pxp_component: i915_pxp_component struct of the bound mei_pxp
+* module. Only set and cleared inside component bind/unbind functions,
+* which are protected by _mutex.
+*/
struct i915_pxp_component *pxp_component;
+ /**
+* @pxp_component_added: track if the pxp component has been added.
+* Set and cleared in tee init and fini functions respectively.
+*/
bool pxp_component_added;
+ /** @ce: kernel-owned context used for PXP operations */
struct intel_context *ce;
- /*
+ /** @arb_mutex: protects arb session start */
+ struct mutex arb_mutex;
+ /**
+* @arb_is_valid: tracks arb session status.
* After a teardown, the arb session can still be in play on the HW
* even if the keys are gone, so we can't rely on the HW state of the
* session to know if it's valid and need to track the status in SW.
*/
- struct mutex arb_mutex; /* protects arb session start */
bool arb_is_valid;
- /*
-* Keep track of which key instance we're on, so we can use it to
-* determine if an object was created using the current key or a
+ /**
+* @key_instance: tracks which key instance we're on, so we can use it
+* to determine if an object was created using the current key or a
* previous one.
*/
u32 key_instance;
- struct mutex tee_mutex; /* protects the tee channel binding */
+ /**
[Intel-gfx] [PATCH v10 11/17] drm/i915/pxp: start the arb session on demand
From: Daniele Ceraolo Spurio
Now that we can handle destruction and re-creation of the arb session,
we can postpone the start of the session to the first submission that
requires it, to avoid keeping it running with no user.
Signed-off-by: Alan Previn
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 37 +---
drivers/gpu/drm/i915/pxp/intel_pxp.h | 10 --
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 2 +-
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 6 ++--
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 10 +-
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 2 ++
7 files changed, 42 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 4ef643e20849..6b14f4d382d8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -267,7 +267,9 @@ static int proto_context_set_protected(struct
drm_i915_private *i915,
* which in turn requires the device to be active.
*/
pc->pxp_wakeref = intel_runtime_pm_get(>runtime_pm);
- ret = intel_pxp_wait_for_arb_start(>gt.pxp);
+
+ if (!intel_pxp_is_active(>gt.pxp))
+ ret = intel_pxp_start(>gt.pxp);
}
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index a237ae9f603c..47f50ba788b7 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -89,6 +89,7 @@ void intel_pxp_init(struct intel_pxp *pxp)
init_completion(>termination);
complete_all(>termination);
+ mutex_init(>arb_mutex);
INIT_WORK(>session_work, intel_pxp_session_work);
ret = create_vcs_context(pxp);
@@ -125,7 +126,7 @@ void intel_pxp_mark_termination_in_progress(struct
intel_pxp *pxp)
reinit_completion(>termination);
}
-static void intel_pxp_queue_termination(struct intel_pxp *pxp)
+static void pxp_queue_termination(struct intel_pxp *pxp)
{
struct intel_gt *gt = pxp_to_gt(pxp);
@@ -144,31 +145,41 @@ static void intel_pxp_queue_termination(struct intel_pxp
*pxp)
* the arb session is restarted from the irq work when we receive the
* termination completion interrupt
*/
-int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp)
+int intel_pxp_start(struct intel_pxp *pxp)
{
+ int ret = 0;
+
if (!intel_pxp_is_enabled(pxp))
- return 0;
+ return -ENODEV;
+
+ mutex_lock(>arb_mutex);
+
+ if (pxp->arb_is_valid)
+ goto unlock;
+
+ pxp_queue_termination(pxp);
if (!wait_for_completion_timeout(>termination,
-msecs_to_jiffies(100)))
- return -ETIMEDOUT;
+ msecs_to_jiffies(200))) {
+ ret = -ETIMEDOUT;
+ goto unlock;
+ }
+
+ /* make sure the compiler doesn't optimize the double access */
+ barrier();
if (!pxp->arb_is_valid)
- return -EIO;
+ ret = -EIO;
- return 0;
+unlock:
+ mutex_unlock(>arb_mutex);
+ return ret;
}
void intel_pxp_init_hw(struct intel_pxp *pxp)
{
kcr_pxp_enable(pxp_to_gt(pxp));
intel_pxp_irq_enable(pxp);
-
- /*
-* the session could've been attacked while we weren't loaded, so
-* handle it as if it was and re-create it.
-*/
- intel_pxp_queue_termination(pxp);
}
void intel_pxp_fini_hw(struct intel_pxp *pxp)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 430f01ea9860..bce0014d9ff9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -26,7 +26,8 @@ void intel_pxp_init_hw(struct intel_pxp *pxp);
void intel_pxp_fini_hw(struct intel_pxp *pxp);
void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
-int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp);
+
+int intel_pxp_start(struct intel_pxp *pxp);
int intel_pxp_key_check(struct intel_pxp *pxp, struct drm_i915_gem_object
*obj);
@@ -40,11 +41,16 @@ static inline void intel_pxp_fini(struct intel_pxp *pxp)
{
}
-static inline int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp)
+static inline int intel_pxp_start(struct intel_pxp *pxp)
{
return -ENODEV;
}
+static inline bool intel_pxp_is_active(const struct intel_pxp *pxp)
+{
+ return false;
+}
+
static inline int intel_pxp_key_check(struct intel_pxp *pxp,
struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
index 300cf2b96fda..7b25efa82b76 100644
---
[Intel-gfx] [PATCH v10 12/17] drm/i915/pxp: Enable PXP power management
From: "Huang, Sean Z"
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
session state might still be marked as alive after resume. Therefore,
we should consider the session as dead on suspend and invalidate all the
objects. The session will be automatically restarted on the first
protected submission on resume.
v2: runtime suspend also invalidates the keys
v3: fix return codes, simplify rpm ops (Chris), use the new worker func
v4: invalidate the objects on suspend, don't re-create the arb sesson on
resume (delayed to first submission).
v5: move irq changes back to irq patch (Rodrigo)
v6: drop invalidation in runtime suspend (Rodrigo)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 15 ++-
drivers/gpu/drm/i915/i915_drv.c | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 46
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 23 ++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 38 +++-
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 9
8 files changed, 124 insertions(+), 11 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 892e17549314..ee31152ad764 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -285,6 +285,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_irq.o \
+ pxp/intel_pxp_pm.o \
pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index dea8e2479897..b47a8d8f1bb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -18,6 +18,7 @@
#include "intel_rc6.h"
#include "intel_rps.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_pm.h"
static void user_forcewake(struct intel_gt *gt, bool suspend)
{
@@ -262,6 +263,8 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uc_resume(>uc);
+ intel_pxp_resume(>pxp);
+
user_forcewake(gt, false);
out_fw:
@@ -296,6 +299,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
user_forcewake(gt, true);
wait_for_suspend(gt);
+ intel_pxp_suspend(>pxp, false);
intel_uc_suspend(>uc);
}
@@ -346,6 +350,7 @@ void intel_gt_suspend_late(struct intel_gt *gt)
void intel_gt_runtime_suspend(struct intel_gt *gt)
{
+ intel_pxp_suspend(>pxp, true);
intel_uc_runtime_suspend(>uc);
GT_TRACE(gt, "\n");
@@ -353,11 +358,19 @@ void intel_gt_runtime_suspend(struct intel_gt *gt)
int intel_gt_runtime_resume(struct intel_gt *gt)
{
+ int ret;
+
GT_TRACE(gt, "\n");
intel_gt_init_swizzling(gt);
intel_ggtt_restore_fences(gt->ggtt);
- return intel_uc_runtime_resume(>uc);
+ ret = intel_uc_runtime_resume(>uc);
+ if (ret)
+ return ret;
+
+ intel_pxp_resume(>pxp);
+
+ return 0;
}
static ktime_t __intel_gt_get_awake_time(const struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 59fb4c710c8c..d5bcc70a22d4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -67,6 +67,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
index 7b25efa82b76..8d5553772ded 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
@@ -10,6 +10,7 @@
#include "gt/intel_gt_types.h"
#include "i915_irq.h"
#include "i915_reg.h"
+#include "intel_runtime_pm.h"
/**
* intel_pxp_irq_handler - Handles PXP interrupts.
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index ..23fd86de5a24
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "intel_pxp.h"
+#include "intel_pxp_irq.h"
+#include "intel_pxp_pm.h"
+#include "intel_pxp_session.h"
+
+void intel_pxp_suspend(struct intel_pxp *pxp, bool runtime)
+{
+ if (!intel_pxp_is_enabled(pxp))
+ return;
+
+ pxp->arb_is_valid = false;
+
+ /*
+* Contexts using protected objects keep a runtime PM reference, so we
+* can only runtime suspend when all of them have been
[Intel-gfx] [PATCH v10 05/17] drm/i915/pxp: Implement funcs to create the TEE channel
From: "Huang, Sean Z"
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(default) session.
v2: fix locking, don't pollute dev_priv (Chris)
v3: wait for mei PXP component to be bound.
v4: drop the wait, as the component might be bound after i915 load
completes. We'll instead check when sending a tee message.
v5: fix an issue with mei_pxp module removal
v6: don't use fetch_and_zero in fini (Rodrigo)
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 13
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 79 ++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 4 ++
5 files changed, 112 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 94ff5d5b673e..1d2fd5b9efd2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -282,7 +282,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
- pxp/intel_pxp.o
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index e18c32d242d3..4f22848a1001 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -3,6 +3,7 @@
* Copyright(c) 2020 Intel Corporation.
*/
#include "intel_pxp.h"
+#include "intel_pxp_tee.h"
#include "gt/intel_context.h"
#include "i915_drv.h"
@@ -55,7 +56,16 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (ret)
return;
+ ret = intel_pxp_tee_component_init(pxp);
+ if (ret)
+ goto out_context;
+
drm_info(>i915->drm, "Protected Xe Path (PXP) protected content
support initialized\n");
+
+ return;
+
+out_context:
+ destroy_vcs_context(pxp);
}
void intel_pxp_fini(struct intel_pxp *pxp)
@@ -63,5 +73,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
if (!intel_pxp_is_enabled(pxp))
return;
+ intel_pxp_tee_component_fini(pxp);
+
destroy_vcs_context(pxp);
+
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index ..f1d8de832653
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_tee.h"
+
+static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
+{
+ return _to_i915(i915_kdev)->gt.pxp;
+}
+
+/**
+ * i915_pxp_tee_component_bind - bind function to pass the function pointers
to pxp_tee
+ * @i915_kdev: pointer to i915 kernel device
+ * @tee_kdev: pointer to tee kernel device
+ * @data: pointer to pxp_tee_master containing the function pointers
+ *
+ * This bind function is called during the system boot or resume from system
sleep.
+ *
+ * Return: return 0 if successful.
+ */
+static int i915_pxp_tee_component_bind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
+
+ pxp->pxp_component = data;
+ pxp->pxp_component->tee_dev = tee_kdev;
+
+ return 0;
+}
+
+static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
+
+ pxp->pxp_component = NULL;
+}
+
+static const struct component_ops i915_pxp_tee_component_ops = {
+ .bind = i915_pxp_tee_component_bind,
+ .unbind = i915_pxp_tee_component_unbind,
+};
+
+int intel_pxp_tee_component_init(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ ret = component_add_typed(i915->drm.dev, _pxp_tee_component_ops,
+ I915_COMPONENT_PXP);
+ if (ret < 0) {
+ drm_err(>drm, "Failed to add PXP component (%d)\n", ret);
+ return ret;
+ }
+
+ pxp->pxp_component_added = true;
+
+ return 0;
+}
+
+void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
+{
+ struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+
+ if (!pxp->pxp_component_added)
+
[Intel-gfx] [PATCH v10 06/17] drm/i915/pxp: set KCR reg init
From: Daniele Ceraolo Spurio
The setting is required by hardware to allow us doing further protection
operation such as sending commands to GPU or TEE. The register needs to
be re-programmed on resume, so for simplicitly we bundle the programming
with the component binding, which is automatically called on resume.
Further HW set-up operations will be added in the same location in
follow-up patches, so get ready for them by using a couple of
init/fini_hw wrappers instead of calling the KCR funcs directly.
v3: move programming to component binding function, rework commit msg
Signed-off-by: Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 27
drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 4f22848a1001..3fd9306b2ce4 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -10,6 +10,24 @@
struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)
{
return container_of(pxp, struct intel_gt, pxp);
+
+}
+
+/* KCR register definitions */
+#define KCR_INIT _MMIO(0x320f0)
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
+
+static void kcr_pxp_enable(struct intel_gt *gt)
+{
+ intel_uncore_write(gt->uncore, KCR_INIT,
+
_MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
+}
+
+static void kcr_pxp_disable(struct intel_gt *gt)
+{
+ intel_uncore_write(gt->uncore, KCR_INIT,
+
_MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
}
static int create_vcs_context(struct intel_pxp *pxp)
@@ -76,5 +94,14 @@ void intel_pxp_fini(struct intel_pxp *pxp)
intel_pxp_tee_component_fini(pxp);
destroy_vcs_context(pxp);
+}
+
+void intel_pxp_init_hw(struct intel_pxp *pxp)
+{
+ kcr_pxp_enable(pxp_to_gt(pxp));
+}
+void intel_pxp_fini_hw(struct intel_pxp *pxp)
+{
+ kcr_pxp_disable(pxp_to_gt(pxp));
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 73acd879f2fb..cd6560b2605c 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -17,6 +17,9 @@ static inline bool intel_pxp_is_enabled(const struct
intel_pxp *pxp)
struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp);
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
+
+void intel_pxp_init_hw(struct intel_pxp *pxp);
+void intel_pxp_fini_hw(struct intel_pxp *pxp);
#else
static inline void intel_pxp_init(struct intel_pxp *pxp)
{
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index f1d8de832653..0c0c7946e6a0 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -33,6 +33,9 @@ static int i915_pxp_tee_component_bind(struct device
*i915_kdev,
pxp->pxp_component = data;
pxp->pxp_component->tee_dev = tee_kdev;
+ /* the component is required to fully start the PXP HW */
+ intel_pxp_init_hw(pxp);
+
return 0;
}
@@ -41,6 +44,8 @@ static void i915_pxp_tee_component_unbind(struct device
*i915_kdev,
{
struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
+ intel_pxp_fini_hw(pxp);
+
pxp->pxp_component = NULL;
}
--
2.25.1
[Intel-gfx] [PATCH v10 03/17] drm/i915/pxp: define PXP device flag and kconfig
From: Daniele Ceraolo Spurio
Ahead of the PXP implementation, define the relevant define flag and
kconfig option.
v2: flip kconfig default to N. Some machines have IFWIs that do not
support PXP, so we need it to be an opt-in until we add support to query
the caps from the mei device.
Signed-off-by: Alan Previn
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Kconfig | 11 +++
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index f960f5d7664e..8859444943a0 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -131,6 +131,17 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_PXP
+ bool "Enable Intel PXP support for Intel Gen12 and newer platform"
+ depends on DRM_I915
+ depends on INTEL_MEI && INTEL_MEI_PXP
+ default n
+ help
+ PXP (Protected Xe Path) is an i915 component, available on GEN12 and
+ newer GPUs, that helps to establish the hardware protected session and
+ manage the status of the alive software session, as well as its life
+ cycle.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 37c1ca266bcd..447a248f14aa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1678,6 +1678,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)
(INTEL_INFO(dev_priv)->has_global_mocs)
+#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \
+ INTEL_INFO(dev_priv)->has_pxp) && \
+ VDBOX_MASK(_priv->gt)
#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index d328bb95c49b..8e6f48d1eb7b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -133,6 +133,7 @@ enum intel_ppgtt_type {
func(has_logical_ring_elsq); \
func(has_mslices); \
func(has_pooled_eu); \
+ func(has_pxp); \
func(has_rc6); \
func(has_rc6p); \
func(has_rps); \
--
2.25.1
[Intel-gfx] [PATCH v10 00/17] drm/i915: Introduce Intel PXP
PXP (Protected Xe Path) is an i915 component, available on GEN12 and newer platforms, that helps to establish the hardware protected session and manage the status of the alive software session, as well as its life cycle. changes from v9: - Patch #3 - change comments from "Gen12+" to "Gen12 and newer" - Patch #4,#9 - Remove inclusion of intel_gt_types.h from intel_pxp.h - Patch #10 - Modify internal get/set-protected-context functions to not return -ENODEV when setting PXP param to false or when running on pxp-unsupported hw or when i915 was built with CONFIG_PXP off - Patch #11 - increase timeout when waiting in intel_pxp_start as firmware session startup is slower right after boot. Tested with: https://patchwork.freedesktop.org/series/87570/ Cc: Gaurav Kumar Cc: Chris Wilson Cc: Rodrigo Vivi Cc: Joonas Lahtinen Cc: Juston Li Cc: Alan Previn Cc: Lionel Landwerlin Cc: Jason Ekstrand Cc: Daniel Vetter Anshuman Gupta (2): drm/i915/pxp: Add plane decryption support drm/i915/pxp: black pixels on pxp disabled Daniele Ceraolo Spurio (9): drm/i915/pxp: Define PXP component interface drm/i915/pxp: define PXP device flag and kconfig drm/i915/pxp: allocate a vcs context for pxp usage drm/i915/pxp: set KCR reg init drm/i915/pxp: interfaces for using protected objects drm/i915/pxp: start the arb session on demand drm/i915/pxp: add pxp debugfs drm/i915/pxp: add PXP documentation drm/i915/pxp: enable PXP for integrated Gen12 Huang, Sean Z (5): drm/i915/pxp: Implement funcs to create the TEE channel drm/i915/pxp: Create the arbitrary session after boot drm/i915/pxp: Implement arb session teardown drm/i915/pxp: Implement PXP irq handler drm/i915/pxp: Enable PXP power management Vitaly Lubart (1): mei: pxp: export pavp client to me client bus Documentation/gpu/i915.rst| 8 + drivers/gpu/drm/i915/Kconfig | 11 + drivers/gpu/drm/i915/Makefile | 10 + drivers/gpu/drm/i915/display/intel_display.c | 34 ++ .../drm/i915/display/intel_display_types.h| 6 + .../drm/i915/display/skl_universal_plane.c| 49 ++- drivers/gpu/drm/i915/gem/i915_gem_context.c | 97 +- drivers/gpu/drm/i915/gem/i915_gem_context.h | 6 + .../gpu/drm/i915/gem/i915_gem_context_types.h | 28 ++ drivers/gpu/drm/i915/gem/i915_gem_create.c| 72 +++-- .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 18 ++ drivers/gpu/drm/i915/gem/i915_gem_object.c| 1 + drivers/gpu/drm/i915/gem/i915_gem_object.h| 6 + .../gpu/drm/i915/gem/i915_gem_object_types.h | 8 + .../gpu/drm/i915/gem/selftests/mock_context.c | 4 +- drivers/gpu/drm/i915/gt/debugfs_gt.c | 2 + drivers/gpu/drm/i915/gt/intel_engine.h| 2 + drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 +- drivers/gpu/drm/i915/gt/intel_gt.c| 5 + drivers/gpu/drm/i915/gt/intel_gt_irq.c| 7 + drivers/gpu/drm/i915/gt/intel_gt_pm.c | 15 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + drivers/gpu/drm/i915/i915_drv.c | 2 + drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_pci.c | 2 + drivers/gpu/drm/i915/i915_reg.h | 48 +++ drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/pxp/intel_pxp.c | 297 ++ drivers/gpu/drm/i915/pxp/intel_pxp.h | 64 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 141 + drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 + drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 78 + drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.h | 21 ++ drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 101 ++ drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 32 ++ drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 46 +++ drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 23 ++ drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 175 +++ drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 15 + drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 172 ++ drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 17 + .../drm/i915/pxp/intel_pxp_tee_interface.h| 37 +++ drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 83 + drivers/misc/mei/Kconfig | 2 + drivers/misc/mei/Makefile | 1 + drivers/misc/mei/pxp/Kconfig | 13 + drivers/misc/mei/pxp/Makefile | 7 + drivers/misc/mei/pxp/mei_pxp.c| 229 ++ drivers/misc/mei/pxp/mei_pxp.h| 18 ++ include/drm/i915_component.h | 1 + include/drm/i915_pxp_tee_interface.h | 42 +++ include/uapi/drm/i915_drm.h | 99 +- 52 files changed, 2157 insertions(+), 42 deletions(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h create mode 100644
[Intel-gfx] [PATCH v10 04/17] drm/i915/pxp: allocate a vcs context for pxp usage
From: Daniele Ceraolo Spurio
The context is required to send the session termination commands to the
VCS, which will be implemented in a follow-up patch. We can also use the
presence of the context as a check of pxp initialization completion.
v2: use perma-pinned context (Chris)
v3: rename pinned_context functions (Chris)
v4: split export of pinned_context functions to a separate patch (Rodrigo)
Signed-off-by: Alan Previn
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/Makefile | 4 ++
drivers/gpu/drm/i915/gt/intel_engine.h | 2 +
drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 67 ++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 30 ++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 17 ++
7 files changed, 128 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9d371be7dc5c..94ff5d5b673e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -280,6 +280,10 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-$(CONFIG_DRM_I915_PXP) += \
+ pxp/intel_pxp.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 87579affb952..eed4634c08cd 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -175,6 +175,8 @@ intel_write_status_page(struct intel_engine_cs *engine, int
reg, u32 value)
#define I915_GEM_HWS_SEQNO 0x40
#define I915_GEM_HWS_SEQNO_ADDR(I915_GEM_HWS_SEQNO *
sizeof(u32))
#define I915_GEM_HWS_MIGRATE (0x42 * sizeof(u32))
+#define I915_GEM_HWS_PXP 0x60
+#define I915_GEM_HWS_PXP_ADDR (I915_GEM_HWS_PXP * sizeof(u32))
#define I915_GEM_HWS_SCRATCH 0x80
#define I915_HWS_CSB_BUF0_INDEX0x10
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 55e87aff51d2..065c7a8ad285 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -21,6 +21,7 @@
#include "intel_uncore.h"
#include "intel_pm.h"
#include "shmem_utils.h"
+#include "pxp/intel_pxp.h"
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
{
@@ -712,6 +713,8 @@ int intel_gt_init(struct intel_gt *gt)
intel_migrate_init(>migrate, gt);
+ intel_pxp_init(>pxp);
+
goto out_fw;
err_gt:
__intel_gt_disable(gt);
@@ -747,6 +750,8 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
intel_rps_driver_unregister(>rps);
+ intel_pxp_fini(>pxp);
+
/*
* Upon unregistering the device to prevent any new users, cancel
* all in-flight requests so that we can quickly unbind the active
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 6fdcde64c180..8001a61f42e5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -26,6 +26,7 @@
#include "intel_rps_types.h"
#include "intel_migrate_types.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_types.h"
struct drm_i915_private;
struct i915_ggtt;
@@ -196,6 +197,8 @@ struct intel_gt {
struct {
u8 uc_index;
} mocs;
+
+ struct intel_pxp pxp;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index ..e18c32d242d3
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+#include "intel_pxp.h"
+#include "gt/intel_context.h"
+#include "i915_drv.h"
+
+struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)
+{
+ return container_of(pxp, struct intel_gt, pxp);
+}
+
+static int create_vcs_context(struct intel_pxp *pxp)
+{
+ static struct lock_class_key pxp_lock;
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ struct intel_engine_cs *engine;
+ struct intel_context *ce;
+
+ /*
+* Find the first VCS engine present. We're guaranteed there is one
+* if we're in this function due to the check in has_pxp
+*/
+ for (engine = gt->engine_class[VIDEO_DECODE_CLASS][0]; !engine;
engine++);
+ GEM_BUG_ON(!engine || engine->class != VIDEO_DECODE_CLASS);
+
+ ce = intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,
+
[Intel-gfx] [PATCH v10 01/17] drm/i915/pxp: Define PXP component interface
From: Daniele Ceraolo Spurio
This will be used for communication between the i915 driver and the mei
one. Defining it in a stand-alone patch to avoid circualr dependedencies
between the patches modifying the 2 drivers.
Split out from an original patch from Huang, Sean Z
v2: rename the component struct (Rodrigo)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
---
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 42
2 files changed, 43 insertions(+)
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 55c3b123581b..c1e2a43d2d1e 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -29,6 +29,7 @@
enum i915_component_type {
I915_COMPONENT_AUDIO = 1,
I915_COMPONENT_HDCP,
+ I915_COMPONENT_PXP
};
/* MAX_PORT is the number of port
diff --git a/include/drm/i915_pxp_tee_interface.h
b/include/drm/i915_pxp_tee_interface.h
new file mode 100644
index ..af593ec64469
--- /dev/null
+++ b/include/drm/i915_pxp_tee_interface.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef _I915_PXP_TEE_INTERFACE_H_
+#define _I915_PXP_TEE_INTERFACE_H_
+
+#include
+#include
+
+/**
+ * struct i915_pxp_component_ops - ops for PXP services.
+ * @owner: Module providing the ops
+ * @send: sends data to PXP
+ * @receive: receives data from PXP
+ */
+struct i915_pxp_component_ops {
+ /**
+* @owner: owner of the module provding the ops
+*/
+ struct module *owner;
+
+ int (*send)(struct device *dev, const void *message, size_t size);
+ int (*recv)(struct device *dev, void *buffer, size_t size);
+};
+
+/**
+ * struct i915_pxp_component - Used for communication between i915 and TEE
+ * drivers for the PXP services
+ * @tee_dev: device that provide the PXP service from TEE Bus.
+ * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
+ */
+struct i915_pxp_component {
+ struct device *tee_dev;
+ const struct i915_pxp_component_ops *ops;
+
+ /* To protect the above members. */
+ struct mutex mutex;
+};
+
+#endif /* _I915_TEE_PXP_INTERFACE_H_ */
--
2.25.1
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915: rename debugfs_gt files
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: rename debugfs_gt files
URL : https://patchwork.freedesktop.org/series/94827/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10605 -> Patchwork_21095
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_21095 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21095, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21095:
### IGT changes ###
Warnings
* igt@i915_module_load@reload:
- fi-icl-y: [INCOMPLETE][1] ([i915#4130]) -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-icl-y/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/fi-icl-y/igt@i915_module_l...@reload.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload:
- {fi-ehl-2}: [INCOMPLETE][3] ([i915#4136]) -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-ehl-2/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/fi-ehl-2/igt@i915_module_l...@reload.html
Known issues
Here are the changes found in Patchwork_21095 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-cfl-8700k: NOTRUN -> [SKIP][5] ([fdo#109271]) +17 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/fi-cfl-8700k/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html
* igt@core_hotunplug@unbind-rebind:
- fi-skl-6700k2: [PASS][6] -> [INCOMPLETE][7] ([i915#4130])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][8] ([i915#4130])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html
- fi-kbl-7567u: [PASS][9] -> [INCOMPLETE][10] ([i915#4130])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-7567u/igt@core_hotunp...@unbind-rebind.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/fi-kbl-7567u/igt@core_hotunp...@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([i915#2190])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html
* igt@i915_module_load@reload:
- fi-cfl-8109u: NOTRUN -> [INCOMPLETE][12] ([i915#4130])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/fi-cfl-8109u/igt@i915_module_l...@reload.html
- fi-kbl-7500u: NOTRUN -> [INCOMPLETE][13] ([i915#4130])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/fi-kbl-7500u/igt@i915_module_l...@reload.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#1155])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([fdo#111827]) +8 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][16] -> [FAIL][17] ([i915#1372])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][18] ([i915#4103]) +1 similar issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][19] ([fdo#109285])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21095/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: NOTRUN -> [SKIP][20] ([i915#1072]) +3 similar issues
[20]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/4] drm/i915: rename debugfs_gt files
== Series Details == Series: series starting with [CI,1/4] drm/i915: rename debugfs_gt files URL : https://patchwork.freedesktop.org/series/94827/ State : warning == Summary == $ dim checkpatch origin/drm-tip b981772f1a36 drm/i915: rename debugfs_gt files -:170: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #170: rename from drivers/gpu/drm/i915/gt/debugfs_gt.c total: 0 errors, 1 warnings, 0 checks, 340 lines checked 5a02c950b736 drm/i915: rename debugfs_engines files -:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #35: deleted file mode 100644 total: 0 errors, 1 warnings, 0 checks, 66 lines checked 9e15c3d9b639 drm/i915: rename debugfs_gt_pm files -:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #35: deleted file mode 100644 total: 0 errors, 1 warnings, 0 checks, 68 lines checked 8ad929eed8c2 drm/i915: deduplicate frequency dump on debugfs
[Intel-gfx] [CI 1/4] drm/i915: rename debugfs_gt files
We shouldn't be using debugfs_ namespace for this functionality. Rename
debugfs_gt.[ch] to intel_gt_debugfs.[ch] and then make functions,
defines and structs follow suit.
While at it and since we are renaming the header, sort the includes
alphabetically.
Signed-off-by: Lucas De Marchi
Acked-by: Jani Nikula
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/gt/debugfs_engines.c | 6 +++---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c| 14 +++---
drivers/gpu/drm/i915/gt/intel_gt.c | 6 +++---
.../gt/{debugfs_gt.c => intel_gt_debugfs.c}| 8
.../gt/{debugfs_gt.h => intel_gt_debugfs.h}| 14 +++---
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 10 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c | 18 +-
.../gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c | 8
drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.c | 6 +++---
drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 6 +++---
11 files changed, 49 insertions(+), 49 deletions(-)
rename drivers/gpu/drm/i915/gt/{debugfs_gt.c => intel_gt_debugfs.c} (87%)
rename drivers/gpu/drm/i915/gt/{debugfs_gt.h => intel_gt_debugfs.h} (71%)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9d371be7dc5c..cac22a9a1b02 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -79,7 +79,6 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
# "Graphics Technology" (aka we talk to the gpu)
gt-y += \
gt/debugfs_engines.o \
- gt/debugfs_gt.o \
gt/debugfs_gt_pm.o \
gt/gen2_engine_cs.o \
gt/gen6_engine_cs.o \
@@ -100,6 +99,7 @@ gt-y += \
gt/intel_gt.o \
gt/intel_gt_buffer_pool.o \
gt/intel_gt_clock_utils.o \
+ gt/intel_gt_debugfs.o \
gt/intel_gt_irq.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/debugfs_engines.c
b/drivers/gpu/drm/i915/gt/debugfs_engines.c
index 5e3725e62241..2980dac5b171 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_engines.c
@@ -7,9 +7,9 @@
#include
#include "debugfs_engines.h"
-#include "debugfs_gt.h"
#include "i915_drv.h" /* for_each_engine! */
#include "intel_engine.h"
+#include "intel_gt_debugfs.h"
static int engines_show(struct seq_file *m, void *data)
{
@@ -24,11 +24,11 @@ static int engines_show(struct seq_file *m, void *data)
return 0;
}
-DEFINE_GT_DEBUGFS_ATTRIBUTE(engines);
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(engines);
void debugfs_engines_register(struct intel_gt *gt, struct dentry *root)
{
- static const struct debugfs_gt_file files[] = {
+ static const struct intel_gt_debugfs_file files[] = {
{ "engines", _fops },
};
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index f6733f279890..9222cf68c56c 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -6,11 +6,11 @@
#include
-#include "debugfs_gt.h"
#include "debugfs_gt_pm.h"
#include "i915_drv.h"
#include "intel_gt.h"
#include "intel_gt_clock_utils.h"
+#include "intel_gt_debugfs.h"
#include "intel_gt_pm.h"
#include "intel_llc.h"
#include "intel_rc6.h"
@@ -36,7 +36,7 @@ static int fw_domains_show(struct seq_file *m, void *data)
return 0;
}
-DEFINE_GT_DEBUGFS_ATTRIBUTE(fw_domains);
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(fw_domains);
static void print_rc6_res(struct seq_file *m,
const char *title,
@@ -238,7 +238,7 @@ static int drpc_show(struct seq_file *m, void *unused)
return err;
}
-DEFINE_GT_DEBUGFS_ATTRIBUTE(drpc);
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(drpc);
static int frequency_show(struct seq_file *m, void *unused)
{
@@ -480,7 +480,7 @@ static int frequency_show(struct seq_file *m, void *unused)
return 0;
}
-DEFINE_GT_DEBUGFS_ATTRIBUTE(frequency);
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(frequency);
static int llc_show(struct seq_file *m, void *data)
{
@@ -533,7 +533,7 @@ static bool llc_eval(void *data)
return HAS_LLC(gt->i915);
}
-DEFINE_GT_DEBUGFS_ATTRIBUTE(llc);
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(llc);
static const char *rps_power_to_str(unsigned int power)
{
@@ -612,11 +612,11 @@ static bool rps_eval(void *data)
return HAS_RPS(gt->i915);
}
-DEFINE_GT_DEBUGFS_ATTRIBUTE(rps_boost);
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost);
void debugfs_gt_pm_register(struct intel_gt *gt, struct dentry *root)
{
- static const struct debugfs_gt_file files[] = {
+ static const struct intel_gt_debugfs_file files[] = {
{ "drpc", _fops, NULL },
{ "frequency", _fops, NULL },
{ "forcewake", _domains_fops, NULL },
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 55e87aff51d2..985922c03297 100644
[Intel-gfx] [CI 3/4] drm/i915: rename debugfs_gt_pm files
We shouldn't be using debugfs_ namespace for this functionality. Rename
debugfs_gt_pm.[ch] to intel_gt_pm_debugfs.[ch] and then make
functions, defines and structs follow suit.
Signed-off-by: Lucas De Marchi
Acked-by: Jani Nikula
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/gt/debugfs_gt_pm.h| 14 --
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 4 ++--
.../gt/{debugfs_gt_pm.c => intel_gt_pm_debugfs.c} | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h | 14 ++
5 files changed, 19 insertions(+), 19 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt_pm.h
rename drivers/gpu/drm/i915/gt/{debugfs_gt_pm.c => intel_gt_pm_debugfs.c} (99%)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0b21777fc77b..335a8c668848 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -78,7 +78,6 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
# "Graphics Technology" (aka we talk to the gpu)
gt-y += \
- gt/debugfs_gt_pm.o \
gt/gen2_engine_cs.o \
gt/gen6_engine_cs.o \
gt/gen6_ppgtt.o \
@@ -102,6 +101,7 @@ gt-y += \
gt/intel_gt_engines_debugfs.o \
gt/intel_gt_irq.o \
gt/intel_gt_pm.o \
+ gt/intel_gt_pm_debugfs.o \
gt/intel_gt_pm_irq.o \
gt/intel_gt_requests.o \
gt/intel_gtt.o \
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h
deleted file mode 100644
index 4cf5f5c9da7d..
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2019 Intel Corporation
- */
-
-#ifndef DEBUGFS_GT_PM_H
-#define DEBUGFS_GT_PM_H
-
-struct intel_gt;
-struct dentry;
-
-void debugfs_gt_pm_register(struct intel_gt *gt, struct dentry *root);
-
-#endif /* DEBUGFS_GT_PM_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index 3c77c2965e19..03fb4aefbf90 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -5,10 +5,10 @@
#include
-#include "debugfs_gt_pm.h"
#include "i915_drv.h"
#include "intel_gt_debugfs.h"
#include "intel_gt_engines_debugfs.h"
+#include "intel_gt_pm_debugfs.h"
#include "intel_sseu_debugfs.h"
#include "uc/intel_uc_debugfs.h"
@@ -24,7 +24,7 @@ void intel_gt_debugfs_register(struct intel_gt *gt)
return;
intel_gt_engines_debugfs_register(gt, root);
- debugfs_gt_pm_register(gt, root);
+ intel_gt_pm_debugfs_register(gt, root);
intel_sseu_debugfs_register(gt, root);
intel_uc_debugfs_register(>uc, root);
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
similarity index 99%
rename from drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
rename to drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 9222cf68c56c..250467108eda 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -6,12 +6,12 @@
#include
-#include "debugfs_gt_pm.h"
#include "i915_drv.h"
#include "intel_gt.h"
#include "intel_gt_clock_utils.h"
#include "intel_gt_debugfs.h"
#include "intel_gt_pm.h"
+#include "intel_gt_pm_debugfs.h"
#include "intel_llc.h"
#include "intel_rc6.h"
#include "intel_rps.h"
@@ -614,7 +614,7 @@ static bool rps_eval(void *data)
DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost);
-void debugfs_gt_pm_register(struct intel_gt *gt, struct dentry *root)
+void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root)
{
static const struct intel_gt_debugfs_file files[] = {
{ "drpc", _fops, NULL },
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
new file mode 100644
index ..b5c6a00cfa04
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef INTEL_GT_PM_DEBUGFS_H
+#define INTEL_GT_PM_DEBUGFS_H
+
+struct intel_gt;
+struct dentry;
+
+void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root);
+
+#endif /* INTEL_GT_PM_DEBUGFS_H */
--
2.33.0
[Intel-gfx] [CI 4/4] drm/i915: deduplicate frequency dump on debugfs
Although commit 9dd4b065446a ("drm/i915/gt: Move pm debug files into a
gt aware debugfs") says it was moving debug files to gt/, the
i915_frequency_info file was left behind and its implementation copied
into drivers/gpu/drm/i915/gt/debugfs_gt_pm.c. Over time we had several
patches having to change both places to keep them in sync (and some
patches failing to do so). The initial idea was to remove
i915_frequency_info, but there are user space tools using it. From a
quick code search there are other scripts and test tools besides igt, so
it's not simply updating igt to get rid of the older file.
Here we export a function using drm_printer as parameter and make
both show() implementations to call this same function. Aside from a few
variable name differences, for i915_frequency_info this brings a few
lines that were not previously printed: RP UP EI, RP UP THRESHOLD, RP
DOWN THRESHOLD and RP DOWN EI. These came in as part of
commit 9c878557b1eb ("drm/i915/gt: Use the RPM config register to
determine clk frequencies"), which didn't change both places.
Signed-off-by: Lucas De Marchi
Acked-by: Jani Nikula
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 127 +-
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h | 2 +
drivers/gpu/drm/i915/i915_debugfs.c | 231 +-
3 files changed, 76 insertions(+), 284 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 250467108eda..5f84ad602642 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -240,9 +240,8 @@ static int drpc_show(struct seq_file *m, void *unused)
}
DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(drpc);
-static int frequency_show(struct seq_file *m, void *unused)
+void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
{
- struct intel_gt *gt = m->private;
struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore = gt->uncore;
struct intel_rps *rps = >rps;
@@ -254,21 +253,21 @@ static int frequency_show(struct seq_file *m, void
*unused)
u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
- seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
- seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
- seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK)
>>
+ drm_printf(p, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
+ drm_printf(p, "Requested VID: %d\n", rgvswctl & 0x3f);
+ drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK)
>>
MEMSTAT_VID_SHIFT);
- seq_printf(m, "Current P-state: %d\n",
+ drm_printf(p, "Current P-state: %d\n",
(rgvstat & MEMSTAT_PSTATE_MASK) >>
MEMSTAT_PSTATE_SHIFT);
} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
u32 rpmodectl, freq_sts;
rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
- seq_printf(m, "Video Turbo Mode: %s\n",
+ drm_printf(p, "Video Turbo Mode: %s\n",
yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
- seq_printf(m, "HW control enabled: %s\n",
+ drm_printf(p, "HW control enabled: %s\n",
yesno(rpmodectl & GEN6_RP_ENABLE));
- seq_printf(m, "SW control enabled: %s\n",
+ drm_printf(p, "SW control enabled: %s\n",
yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
GEN6_RP_MEDIA_SW_MODE));
@@ -276,25 +275,25 @@ static int frequency_show(struct seq_file *m, void
*unused)
freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
vlv_punit_put(i915);
- seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
- seq_printf(m, "DDR freq: %d MHz\n", i915->mem_freq);
+ drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
+ drm_printf(p, "DDR freq: %d MHz\n", i915->mem_freq);
- seq_printf(m, "actual GPU freq: %d MHz\n",
+ drm_printf(p, "actual GPU freq: %d MHz\n",
intel_gpu_freq(rps, (freq_sts >> 8) & 0xff));
- seq_printf(m, "current GPU freq: %d MHz\n",
+ drm_printf(p, "current GPU freq: %d MHz\n",
intel_gpu_freq(rps, rps->cur_freq));
- seq_printf(m, "max GPU freq: %d MHz\n",
+ drm_printf(p, "max GPU freq: %d MHz\n",
intel_gpu_freq(rps, rps->max_freq));
- seq_printf(m, "min GPU freq: %d MHz\n",
+ drm_printf(p, "min GPU freq: %d MHz\n",
[Intel-gfx] [CI 2/4] drm/i915: rename debugfs_engines files
We shouldn't be using debugfs_ namespace for this functionality. Rename
debugfs_engines.[ch] to intel_gt_engines_debugfs.[ch] and then make
functions, defines and structs follow suit.
Signed-off-by: Lucas De Marchi
Acked-by: Jani Nikula
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/gt/debugfs_engines.h | 14 --
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 4 ++--
...ebugfs_engines.c => intel_gt_engines_debugfs.c} | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h | 14 ++
5 files changed, 19 insertions(+), 19 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/gt/debugfs_engines.h
rename drivers/gpu/drm/i915/gt/{debugfs_engines.c =>
intel_gt_engines_debugfs.c} (85%)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index cac22a9a1b02..0b21777fc77b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -78,7 +78,6 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
# "Graphics Technology" (aka we talk to the gpu)
gt-y += \
- gt/debugfs_engines.o \
gt/debugfs_gt_pm.o \
gt/gen2_engine_cs.o \
gt/gen6_engine_cs.o \
@@ -100,6 +99,7 @@ gt-y += \
gt/intel_gt_buffer_pool.o \
gt/intel_gt_clock_utils.o \
gt/intel_gt_debugfs.o \
+ gt/intel_gt_engines_debugfs.o \
gt/intel_gt_irq.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/debugfs_engines.h
b/drivers/gpu/drm/i915/gt/debugfs_engines.h
deleted file mode 100644
index f69257eaa1cc..
--- a/drivers/gpu/drm/i915/gt/debugfs_engines.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2019 Intel Corporation
- */
-
-#ifndef DEBUGFS_ENGINES_H
-#define DEBUGFS_ENGINES_H
-
-struct intel_gt;
-struct dentry;
-
-void debugfs_engines_register(struct intel_gt *gt, struct dentry *root);
-
-#endif /* DEBUGFS_ENGINES_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index b19648008265..3c77c2965e19 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -5,10 +5,10 @@
#include
-#include "debugfs_engines.h"
#include "debugfs_gt_pm.h"
#include "i915_drv.h"
#include "intel_gt_debugfs.h"
+#include "intel_gt_engines_debugfs.h"
#include "intel_sseu_debugfs.h"
#include "uc/intel_uc_debugfs.h"
@@ -23,7 +23,7 @@ void intel_gt_debugfs_register(struct intel_gt *gt)
if (IS_ERR(root))
return;
- debugfs_engines_register(gt, root);
+ intel_gt_engines_debugfs_register(gt, root);
debugfs_gt_pm_register(gt, root);
intel_sseu_debugfs_register(gt, root);
diff --git a/drivers/gpu/drm/i915/gt/debugfs_engines.c
b/drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.c
similarity index 85%
rename from drivers/gpu/drm/i915/gt/debugfs_engines.c
rename to drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.c
index 2980dac5b171..8f9b874fdc9c 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_engines.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.c
@@ -6,10 +6,10 @@
#include
-#include "debugfs_engines.h"
#include "i915_drv.h" /* for_each_engine! */
#include "intel_engine.h"
#include "intel_gt_debugfs.h"
+#include "intel_gt_engines_debugfs.h"
static int engines_show(struct seq_file *m, void *data)
{
@@ -26,7 +26,7 @@ static int engines_show(struct seq_file *m, void *data)
}
DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(engines);
-void debugfs_engines_register(struct intel_gt *gt, struct dentry *root)
+void intel_gt_engines_debugfs_register(struct intel_gt *gt, struct dentry
*root)
{
static const struct intel_gt_debugfs_file files[] = {
{ "engines", _fops },
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h
b/drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h
new file mode 100644
index ..dda113452da9
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef INTEL_GT_ENGINES_DEBUGFS_H
+#define INTEL_GT_ENGINES_DEBUGFS_H
+
+struct intel_gt;
+struct dentry;
+
+void intel_gt_engines_debugfs_register(struct intel_gt *gt, struct dentry
*root);
+
+#endif /* INTEL_GT_ENGINES_DEBUGFS_H */
--
2.33.0
[Intel-gfx] ✗ Fi.CI.BAT: failure for Check SFC fusing on Xe_HP (rev3)
== Series Details ==
Series: Check SFC fusing on Xe_HP (rev3)
URL : https://patchwork.freedesktop.org/series/94808/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10605 -> Patchwork_21094
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_21094 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21094, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21094/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21094:
### IGT changes ###
Possible regressions
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7500u: NOTRUN -> [DMESG-WARN][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21094/fi-kbl-7500u/igt@i915_pm_...@module-reload.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload:
- {fi-ehl-2}: [INCOMPLETE][2] ([i915#4136]) -> [INCOMPLETE][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-ehl-2/igt@i915_module_l...@reload.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21094/fi-ehl-2/igt@i915_module_l...@reload.html
Known issues
Here are the changes found in Patchwork_21094 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-sdma:
- fi-cfl-8109u: NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21094/fi-cfl-8109u/igt@amdgpu/amd_ba...@cs-sdma.html
* igt@amdgpu/amd_basic@semaphore:
- fi-icl-y: NOTRUN -> [SKIP][5] ([fdo#109315]) +17 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21094/fi-icl-y/igt@amdgpu/amd_ba...@semaphore.html
* igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-cfl-8700k: NOTRUN -> [SKIP][6] ([fdo#109271]) +17 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21094/fi-cfl-8700k/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html
* igt@core_hotunplug@unbind-rebind:
- fi-skl-6700k2: [PASS][7] -> [INCOMPLETE][8] ([i915#4130])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21094/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html
- fi-cfl-guc: [PASS][9] -> [INCOMPLETE][10] ([i915#4130])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21094/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][11] ([i915#4130])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21094/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html
- fi-icl-u2: [PASS][12] -> [INCOMPLETE][13] ([i915#4130])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21094/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
- fi-rkl-11600: [PASS][14] -> [INCOMPLETE][15] ([i915#4130])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-rkl-11600/igt@core_hotunp...@unbind-rebind.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21094/fi-rkl-11600/igt@core_hotunp...@unbind-rebind.html
- fi-kbl-7567u: [PASS][16] -> [INCOMPLETE][17] ([i915#4130])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-7567u/igt@core_hotunp...@unbind-rebind.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21094/fi-kbl-7567u/igt@core_hotunp...@unbind-rebind.html
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-1115g4: NOTRUN -> [FAIL][18] ([i915#1888])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21094/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][19] ([i915#2190])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21094/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html
* igt@i915_module_load@reload:
- fi-cfl-8109u: NOTRUN -> [DMESG-WARN][20] ([i915#4136])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21094/fi-cfl-8109u/igt@i915_module_l...@reload.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][21] ([i915#1155])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21094/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html
*
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: fix blank screen booting crashes (rev2)
== Series Details == Series: drm/i915: fix blank screen booting crashes (rev2) URL : https://patchwork.freedesktop.org/series/94822/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10605_full -> Patchwork_21092_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21092_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21092_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21092_full: ### IGT changes ### Possible regressions * igt@gem_exec_schedule@pi-common@rcs0: - shard-skl: [PASS][1] -> [FAIL][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl5/igt@gem_exec_schedule@pi-com...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/shard-skl5/igt@gem_exec_schedule@pi-com...@rcs0.html Known issues Here are the changes found in Patchwork_21092_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@vecs0: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl7/igt@gem_ctx_isolation@preservation...@vecs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/shard-kbl1/igt@gem_ctx_isolation@preservation...@vecs0.html * igt@gem_ctx_sseu@engines: - shard-skl: NOTRUN -> [SKIP][5] ([fdo#109271]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/shard-skl6/igt@gem_ctx_s...@engines.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl3/igt@gem_exec_fair@basic-none-...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/shard-kbl7/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_parallel@contexts@vecs0: - shard-iclb: [PASS][10] -> [INCOMPLETE][11] ([i915#2624]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb4/igt@gem_exec_parallel@conte...@vecs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/shard-iclb7/igt@gem_exec_parallel@conte...@vecs0.html * igt@gem_exec_params@rsvd2-dirt: - shard-tglb: NOTRUN -> [SKIP][12] ([fdo#109283]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/shard-tglb2/igt@gem_exec_par...@rsvd2-dirt.html * igt@gem_exec_suspend@basic-s0: - shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([i915#456]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb2/igt@gem_exec_susp...@basic-s0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/shard-tglb7/igt@gem_exec_susp...@basic-s0.html * igt@gem_huc_copy@huc-copy: - shard-kbl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/shard-kbl2/igt@gem_huc_c...@huc-copy.html * igt@gem_media_vme: - shard-tglb: NOTRUN -> [SKIP][16] ([i915#284]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/shard-tglb2/igt@gem_media_vme.html * igt@gem_pread@exhaustion: - shard-skl: NOTRUN -> [WARN][17] ([i915#2658]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/shard-skl5/igt@gem_pr...@exhaustion.html * igt@gen9_exec_parse@valid-registers: - shard-tglb: NOTRUN -> [SKIP][18] ([i915#2856]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/shard-tglb2/igt@gen9_exec_pa...@valid-registers.html * igt@i915_pm_rpm@pc8-residency: - shard-tglb: NOTRUN -> [SKIP][19] ([fdo#109506] / [i915#2411]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/shard-tglb2/igt@i915_pm_...@pc8-residency.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-tglb: [PASS][20] -> [INCOMPLETE][21] ([i915#2411] / [i915#456] / [i915#750]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb5/igt@i915_pm_...@system-suspend-execbuf.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/shard-tglb7/igt@i915_pm_...@system-suspend-execbuf.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Check SFC fusing on Xe_HP (rev3)
== Series Details == Series: Check SFC fusing on Xe_HP (rev3) URL : https://patchwork.freedesktop.org/series/94808/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen8_write32' - different lock
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Make wa list per-gt (rev2)
== Series Details == Series: drm/i915: Make wa list per-gt (rev2) URL : https://patchwork.freedesktop.org/series/94811/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10605_full -> Patchwork_21091_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21091_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21091_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21091_full: ### IGT changes ### Possible regressions * igt@kms_atomic@plane-invalid-params: - shard-iclb: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb6/igt@kms_ato...@plane-invalid-params.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/shard-iclb2/igt@kms_ato...@plane-invalid-params.html * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs: - shard-kbl: NOTRUN -> [INCOMPLETE][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/shard-kbl2/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs.html * igt@kms_sequence@queue-idle: - shard-skl: [PASS][4] -> [FAIL][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl8/igt@kms_seque...@queue-idle.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/shard-skl3/igt@kms_seque...@queue-idle.html Known issues Here are the changes found in Patchwork_21091_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_import_export@flink: - shard-tglb: [PASS][6] -> [INCOMPLETE][7] ([i915#750]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb7/igt@drm_import_exp...@flink.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/shard-tglb2/igt@drm_import_exp...@flink.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-skl: [PASS][8] -> [INCOMPLETE][9] ([i915#146] / [i915#198]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl6/igt@gem_ctx_isolation@preservation...@vcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/shard-skl4/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_ctx_sseu@engines: - shard-skl: NOTRUN -> [SKIP][10] ([fdo#109271]) +9 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/shard-skl10/igt@gem_ctx_s...@engines.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/shard-tglb5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_params@rsvd2-dirt: - shard-tglb: NOTRUN -> [SKIP][13] ([fdo#109283]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/shard-tglb1/igt@gem_exec_par...@rsvd2-dirt.html * igt@gem_media_vme: - shard-tglb: NOTRUN -> [SKIP][14] ([i915#284]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/shard-tglb1/igt@gem_media_vme.html * igt@gem_pread@exhaustion: - shard-skl: NOTRUN -> [WARN][15] ([i915#2658]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/shard-skl8/igt@gem_pr...@exhaustion.html * igt@gen9_exec_parse@valid-registers: - shard-tglb: NOTRUN -> [SKIP][16] ([i915#2856]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/shard-tglb1/igt@gen9_exec_pa...@valid-registers.html * igt@i915_pm_rpm@pc8-residency: - shard-tglb: NOTRUN -> [SKIP][17] ([fdo#109506] / [i915#2411]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/shard-tglb1/igt@i915_pm_...@pc8-residency.html * igt@kms_big_fb@linear-8bpp-rotate-270: - shard-tglb: NOTRUN -> [SKIP][18] ([fdo#111614]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/shard-tglb1/igt@kms_big...@linear-8bpp-rotate-270.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3777]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/shard-kbl7/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow: - shard-tglb: NOTRUN -> [SKIP][20] ([fdo#111615]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/shard-tglb1/igt@kms_big...@yf-tiled-addfb-size-offset-overflow.html *
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg1: Read OPROM via SPI controller
== Series Details ==
Series: drm/i915/dg1: Read OPROM via SPI controller
URL : https://patchwork.freedesktop.org/series/94826/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10605 -> Patchwork_21093
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_21093 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21093, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21093/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21093:
### IGT changes ###
Possible regressions
* igt@kms_flip@basic-flip-vs-wf_vblank@c-dp1:
- fi-cfl-8109u: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-wf_vbl...@c-dp1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21093/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-wf_vbl...@c-dp1.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload:
- {fi-jsl-1}: [TIMEOUT][3] ([i915#4136]) -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-jsl-1/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21093/fi-jsl-1/igt@i915_module_l...@reload.html
Known issues
Here are the changes found in Patchwork_21093 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-sdma:
- fi-kbl-7500u: NOTRUN -> [SKIP][5] ([fdo#109271]) +17 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21093/fi-kbl-7500u/igt@amdgpu/amd_ba...@cs-sdma.html
* igt@core_hotunplug@unbind-rebind:
- fi-cfl-guc: [PASS][6] -> [INCOMPLETE][7] ([i915#4130])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21093/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
- fi-icl-u2: [PASS][8] -> [INCOMPLETE][9] ([i915#4130])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21093/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
- fi-rkl-11600: [PASS][10] -> [INCOMPLETE][11] ([i915#4130])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-rkl-11600/igt@core_hotunp...@unbind-rebind.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21093/fi-rkl-11600/igt@core_hotunp...@unbind-rebind.html
* igt@debugfs_test@read_all_entries:
- fi-cfl-8109u: [PASS][12] -> [DMESG-WARN][13] ([i915#262] /
[i915#295])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-8109u/igt@debugfs_test@read_all_entries.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21093/fi-cfl-8109u/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s0:
- fi-cfl-8109u: [PASS][14] -> [DMESG-WARN][15] ([i915#165] /
[i915#262] / [i915#295])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-8109u/igt@gem_exec_susp...@basic-s0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21093/fi-cfl-8109u/igt@gem_exec_susp...@basic-s0.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][16] -> [DMESG-WARN][17] ([i915#295]) +18
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21093/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
* igt@runner@aborted:
- fi-skl-6700k2: NOTRUN -> [FAIL][18] ([i915#2426] / [i915#3363])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21093/fi-skl-6700k2/igt@run...@aborted.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-7500u: [INCOMPLETE][19] ([i915#4130]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21093/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-kbl-7567u: [DMESG-WARN][21] ([i915#4136]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-7567u/igt@i915_module_l...@reload.html
[22]:
Re: [Intel-gfx] 5.15-rc1 i915 blank screen booting on ThinkPads
On Thu, 16 Sep 2021, Jani Nikula wrote:
> On Thu, 16 Sep 2021, Tvrtko Ursulin wrote:
> > On 16/09/2021 05:37, Hugh Dickins wrote:
> >> Two Lenovo ThinkPads, old T420s (2011), newer X1 Carbon 5th gen (2017):
> >> i915 working fine on both up to 5.14, but blank screens booting 5.15-rc1,
> >> kernel crashed in some way.
...
> > Kernel logs with drm.debug=0xe, with the broken black screen state,
> > would probably answer a lot of questions if you could gather it from
> > both machines?
>
> And for that, I think it's best to file separate bugs at [1] and attach
> the logs there. It helps keep the info in one place. Thanks.
>
> BR,
> Jani.
>
> [1] https://gitlab.freedesktop.org/drm/intel/issues/new
Thanks for the quick replies: but of course, getting kernel logs was
the difficult part, this being bootup, with just a blank screen, and
no logging to disk at this stage. I've never needed it before, but
netconsole to the rescue.
Problem then obvious, both machines now working,
please let me skip the bug reports, here's a patch:
[PATCH] drm/i915: fix blank screen booting crashes
5.15-rc1 crashes with blank screen when booting up on two ThinkPads
using i915. Bisections converge convincingly, but arrive at different
and surprising "culprits", none of them the actual culprit.
netconsole (with init_netconsole() hacked to call i915_init() when
logging has started, instead of by module_init()) tells the story:
kernel BUG at drivers/gpu/drm/i915/i915_sw_fence.c:245!
with RSI: 814d408b pointing to sw_fence_dummy_notify().
I've been building with CONFIG_CC_OPTIMIZE_FOR_SIZE=y, and that
function needs to be 4-byte aligned.
Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
Signed-off-by: Hugh Dickins
---
drivers/gpu/drm/i915/gt/intel_context.c |1 +
1 file changed, 1 insertion(+)
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -362,6 +362,7 @@ static int __intel_context_active(struct
return 0;
}
+__aligned(4) /* Respect the I915_SW_FENCE_MASK */
static int sw_fence_dummy_notify(struct i915_sw_fence *sf,
enum i915_sw_fence_notify state)
{
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg1: Read OPROM via SPI controller
== Series Details ==
Series: drm/i915/dg1: Read OPROM via SPI controller
URL : https://patchwork.freedesktop.org/series/94826/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4fda5dd183cb drm/i915/dg1: Read OPROM via SPI controller
-:63: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#63: FILE: drivers/gpu/drm/i915/display/intel_bios.c:2319:
+ if (!vbt) {
+ drm_err(>drm, "Unable to allocate %u bytes for VBT
storage\n",
total: 0 errors, 1 warnings, 0 checks, 117 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: fix blank screen booting crashes (rev2)
== Series Details ==
Series: drm/i915: fix blank screen booting crashes (rev2)
URL : https://patchwork.freedesktop.org/series/94822/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10605 -> Patchwork_21092
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_21092 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21092, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21092:
### IGT changes ###
Warnings
* igt@i915_module_load@reload:
- fi-kbl-soraka: [INCOMPLETE][1] ([i915#4130] / [i915#4136]) ->
[INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-soraka/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/fi-kbl-soraka/igt@i915_module_l...@reload.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload:
- {fi-ehl-2}: [INCOMPLETE][3] ([i915#4136]) -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-ehl-2/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/fi-ehl-2/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@module-reload:
- {fi-jsl-1}: [PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-jsl-1/igt@i915_pm_...@module-reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/fi-jsl-1/igt@i915_pm_...@module-reload.html
* igt@runner@aborted:
- {fi-jsl-1}: NOTRUN -> [FAIL][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/fi-jsl-1/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_21092 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-icl-y: NOTRUN -> [SKIP][8] ([fdo#109315]) +17 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/fi-icl-y/igt@amdgpu/amd_ba...@semaphore.html
* igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-cfl-8700k: NOTRUN -> [SKIP][9] ([fdo#109271]) +17 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/fi-cfl-8700k/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html
* igt@core_hotunplug@unbind-rebind:
- fi-skl-6700k2: [PASS][10] -> [INCOMPLETE][11] ([i915#4130])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html
- fi-cfl-guc: [PASS][12] -> [INCOMPLETE][13] ([i915#4130])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][14] ([i915#4130])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([i915#2190])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html
* igt@i915_module_load@reload:
- fi-kbl-7500u: NOTRUN -> [INCOMPLETE][16] ([i915#4130])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/fi-kbl-7500u/igt@i915_module_l...@reload.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][17] ([i915#1155])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][18] ([fdo#111827]) +8 similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][19] ([i915#4103]) +1 similar issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21092/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][20] ([fdo#109285])
[20]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for 5.15-rc1 i915 blank screen booting on ThinkPads
== Series Details == Series: 5.15-rc1 i915 blank screen booting on ThinkPads URL : https://patchwork.freedesktop.org/series/94820/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10605_full -> Patchwork_21089_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21089_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21089_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21089_full: ### IGT changes ### Possible regressions * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs: - shard-kbl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/shard-kbl6/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs: - shard-tglb: [PASS][2] -> [INCOMPLETE][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb8/igt@kms_flip_scaled_...@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/shard-tglb6/igt@kms_flip_scaled_...@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html Known issues Here are the changes found in Patchwork_21089_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@unwedge-stress: - shard-skl: [PASS][4] -> [TIMEOUT][5] ([i915#2369] / [i915#3063]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl5/igt@gem_...@unwedge-stress.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/shard-skl6/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/shard-tglb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_params@rsvd2-dirt: - shard-tglb: NOTRUN -> [SKIP][9] ([fdo#109283]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/shard-tglb8/igt@gem_exec_par...@rsvd2-dirt.html * igt@gem_exec_suspend@basic-s0: - shard-tglb: [PASS][10] -> [INCOMPLETE][11] ([i915#456]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb2/igt@gem_exec_susp...@basic-s0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/shard-tglb7/igt@gem_exec_susp...@basic-s0.html * igt@gem_exec_suspend@basic-s3: - shard-kbl: [PASS][12] -> [DMESG-WARN][13] ([i915#180]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl1/igt@gem_exec_susp...@basic-s3.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/shard-kbl3/igt@gem_exec_susp...@basic-s3.html * igt@gem_huc_copy@huc-copy: - shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/shard-kbl2/igt@gem_huc_c...@huc-copy.html * igt@gem_media_vme: - shard-tglb: NOTRUN -> [SKIP][15] ([i915#284]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/shard-tglb8/igt@gem_media_vme.html * igt@gem_pread@exhaustion: - shard-skl: NOTRUN -> [WARN][16] ([i915#2658]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/shard-skl3/igt@gem_pr...@exhaustion.html * igt@gen9_exec_parse@valid-registers: - shard-tglb: NOTRUN -> [SKIP][17] ([i915#2856]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/shard-tglb8/igt@gen9_exec_pa...@valid-registers.html * igt@i915_pm_rpm@pc8-residency: - shard-tglb: NOTRUN -> [SKIP][18] ([fdo#109506] / [i915#2411]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/shard-tglb8/igt@i915_pm_...@pc8-residency.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([i915#2411] / [i915#456] / [i915#750]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb5/igt@i915_pm_...@system-suspend-execbuf.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/shard-tglb7/igt@i915_pm_...@system-suspend-execbuf.html * igt@kms_big_fb@linear-8bpp-rotate-270: - shard-tglb: NOTRUN -> [SKIP][21]
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Make wa list per-gt (rev2)
== Series Details ==
Series: drm/i915: Make wa list per-gt (rev2)
URL : https://patchwork.freedesktop.org/series/94811/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10605 -> Patchwork_21091
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_21091 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21091, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21091:
### IGT changes ###
Warnings
* igt@i915_module_load@reload:
- fi-kbl-soraka: [INCOMPLETE][1] ([i915#4130] / [i915#4136]) ->
[INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-soraka/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/fi-kbl-soraka/igt@i915_module_l...@reload.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload:
- {fi-ehl-2}: [INCOMPLETE][3] ([i915#4136]) -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-ehl-2/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/fi-ehl-2/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@module-reload:
- {fi-jsl-1}: [PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-jsl-1/igt@i915_pm_...@module-reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/fi-jsl-1/igt@i915_pm_...@module-reload.html
* igt@runner@aborted:
- {fi-jsl-1}: NOTRUN -> [FAIL][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/fi-jsl-1/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_21091 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-sdma:
- fi-cfl-8109u: NOTRUN -> [SKIP][8] ([fdo#109271]) +17 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/fi-cfl-8109u/igt@amdgpu/amd_ba...@cs-sdma.html
* igt@amdgpu/amd_basic@semaphore:
- fi-icl-y: NOTRUN -> [SKIP][9] ([fdo#109315]) +17 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/fi-icl-y/igt@amdgpu/amd_ba...@semaphore.html
* igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-cfl-8700k: NOTRUN -> [SKIP][10] ([fdo#109271]) +17 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/fi-cfl-8700k/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html
* igt@core_hotunplug@unbind-rebind:
- fi-skl-6700k2: [PASS][11] -> [INCOMPLETE][12] ([i915#4130])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-cfl-guc: [PASS][13] -> [INCOMPLETE][14] ([i915#4136])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-guc/igt@i915_module_l...@reload.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/fi-cfl-guc/igt@i915_module_l...@reload.html
- fi-rkl-guc: [PASS][15] -> [INCOMPLETE][16] ([i915#4136])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-rkl-guc/igt@i915_module_l...@reload.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/fi-rkl-guc/igt@i915_module_l...@reload.html
- fi-kbl-7500u: NOTRUN -> [INCOMPLETE][17] ([i915#4130])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/fi-kbl-7500u/igt@i915_module_l...@reload.html
* igt@runner@aborted:
- fi-kbl-7500u: NOTRUN -> [FAIL][18] ([i915#2426] / [i915#3363])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/fi-kbl-7500u/igt@run...@aborted.html
- fi-rkl-guc: NOTRUN -> [FAIL][19] ([i915#2722])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/fi-rkl-guc/igt@run...@aborted.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-cfl-8700k: [INCOMPLETE][20] ([i915#4130]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21091/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html
- fi-kbl-7500u: [INCOMPLETE][22] ([i915#4130]) -> [PASS][23]
[22]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for Check SFC fusing on Xe_HP (rev2)
== Series Details ==
Series: Check SFC fusing on Xe_HP (rev2)
URL : https://patchwork.freedesktop.org/series/94808/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10605 -> Patchwork_21090
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_21090 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21090, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21090/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21090:
### IGT changes ###
Possible regressions
* igt@i915_module_load@reload:
- fi-rkl-11600: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-rkl-11600/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21090/fi-rkl-11600/igt@i915_module_l...@reload.html
* igt@runner@aborted:
- fi-rkl-11600: NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21090/fi-rkl-11600/igt@run...@aborted.html
Warnings
* igt@i915_module_load@reload:
- fi-kbl-soraka: [INCOMPLETE][4] ([i915#4130] / [i915#4136]) ->
[INCOMPLETE][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-soraka/igt@i915_module_l...@reload.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21090/fi-kbl-soraka/igt@i915_module_l...@reload.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload:
- {fi-ehl-2}: [INCOMPLETE][6] ([i915#4136]) -> [INCOMPLETE][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-ehl-2/igt@i915_module_l...@reload.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21090/fi-ehl-2/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@module-reload:
- {fi-jsl-1}: [PASS][8] -> [INCOMPLETE][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-jsl-1/igt@i915_pm_...@module-reload.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21090/fi-jsl-1/igt@i915_pm_...@module-reload.html
* igt@runner@aborted:
- {fi-jsl-1}: NOTRUN -> [FAIL][10]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21090/fi-jsl-1/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_21090 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-cfl-8700k: NOTRUN -> [SKIP][11] ([fdo#109271]) +17 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21090/fi-cfl-8700k/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html
* igt@core_hotunplug@unbind-rebind:
- fi-skl-6700k2: [PASS][12] -> [INCOMPLETE][13] ([i915#4130])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21090/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][14] ([i915#4130])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21090/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([i915#2190])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21090/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][16] ([i915#1155])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21090/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][17] ([fdo#111827]) +8 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21090/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [PASS][18] -> [DMESG-WARN][19] ([i915#2868])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21090/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][20] ([i915#4103]) +1 similar issue
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21090/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4:
[Intel-gfx] [PATCH] drm/i915/dg1: Read OPROM via SPI controller
From: Clint Taylor
Read OPROM SPI through MMIO and find VBT entry since we can't use
OpRegion and PCI mapping may not work on some systems due to most BIOSes
not leaving the Option ROM mapped.
Cc: Ville Syrjälä
Cc: Tomas Winkler
Signed-off-by: Clint Taylor
Signed-off-by: Lucas De Marchi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 80 +--
drivers/gpu/drm/i915/i915_reg.h | 8 +++
2 files changed, 82 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 3c25926092de..7f179dbdec1b 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2280,6 +2280,66 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t
size)
return vbt;
}
+static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915)
+{
+ u32 count, data, found, store = 0;
+ u32 static_region, oprom_offset;
+ u32 oprom_size = 0x20;
+ u16 vbt_size;
+ u32 *vbt;
+
+ static_region = intel_uncore_read(>uncore, SPI_STATIC_REGIONS);
+ static_region &= OPTIONROM_SPI_REGIONID_MASK;
+ intel_uncore_write(>uncore, PRIMARY_SPI_REGIONID, static_region);
+
+ oprom_offset = intel_uncore_read(>uncore, OROM_OFFSET);
+ oprom_offset &= OROM_OFFSET_MASK;
+
+ for (count = 0; count < oprom_size; count += 4) {
+ intel_uncore_write(>uncore, PRIMARY_SPI_ADDRESS,
oprom_offset + count);
+ data = intel_uncore_read(>uncore, PRIMARY_SPI_TRIGGER);
+
+ if (data == *((const u32 *)"$VBT")) {
+ found = oprom_offset + count;
+ break;
+ }
+ }
+
+ if (count >= oprom_size)
+ goto err_not_found;
+
+ /* Get VBT size and allocate space for the VBT */
+ intel_uncore_write(>uncore, PRIMARY_SPI_ADDRESS, found +
+ offsetof(struct vbt_header, vbt_size));
+ vbt_size = intel_uncore_read(>uncore, PRIMARY_SPI_TRIGGER);
+ vbt_size &= 0x;
+
+ vbt = kzalloc(vbt_size, GFP_KERNEL);
+ if (!vbt) {
+ drm_err(>drm, "Unable to allocate %u bytes for VBT
storage\n",
+ vbt_size);
+ goto err_not_found;
+ }
+
+ for (count = 0; count < vbt_size; count += 4) {
+ intel_uncore_write(>uncore, PRIMARY_SPI_ADDRESS, found +
count);
+ data = intel_uncore_read(>uncore, PRIMARY_SPI_TRIGGER);
+ *(vbt + store++) = data;
+ }
+
+ if (!intel_bios_is_valid_vbt(vbt, vbt_size))
+ goto err_free_vbt;
+
+ drm_dbg_kms(>drm, "Found valid VBT in SPI flash\n");
+
+ return (struct vbt_header *)vbt;
+
+err_free_vbt:
+ kfree(vbt);
+err_not_found:
+ return NULL;
+}
+
static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
@@ -2329,6 +2389,8 @@ static struct vbt_header *oprom_get_vbt(struct
drm_i915_private *i915)
pci_unmap_rom(pdev, oprom);
+ drm_dbg_kms(>drm, "Found valid VBT in PCI ROM\n");
+
return vbt;
err_free_vbt:
@@ -2363,17 +2425,23 @@ void intel_bios_init(struct drm_i915_private *i915)
init_vbt_defaults(i915);
- /* If the OpRegion does not have VBT, look in PCI ROM. */
+ /*
+* If the OpRegion does not have VBT, look in SPI flash through MMIO or
+* PCI mapping
+*/
+ if (!vbt && IS_DGFX(i915)) {
+ oprom_vbt = spi_oprom_get_vbt(i915);
+ vbt = oprom_vbt;
+ }
+
if (!vbt) {
oprom_vbt = oprom_get_vbt(i915);
- if (!oprom_vbt)
- goto out;
-
vbt = oprom_vbt;
-
- drm_dbg_kms(>drm, "Found valid VBT in PCI ROM\n");
}
+ if (!vbt)
+ goto out;
+
bdb = get_bdb_header(vbt);
i915->vbt.version = bdb->version;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3a21f7c003d..fd3fee090412 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12771,6 +12771,14 @@ enum skl_power_gate {
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
+#define PRIMARY_SPI_TRIGGER_MMIO(0x102040)
+#define PRIMARY_SPI_ADDRESS_MMIO(0x102080)
+#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
+#define SPI_STATIC_REGIONS _MMIO(0x102090)
+#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
+#define OROM_OFFSET_MMIO(0x1020c0)
+#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
+
/* This register controls the Display State Buffer (DSB) engines. */
#define
[Intel-gfx] [PATCH] drm/i915: fix blank screen booting crashes
From: Hugh Dickins
5.15-rc1 crashes with blank screen when booting up on two ThinkPads
using i915. Bisections converge convincingly, but arrive at different
and surprising "culprits", none of them the actual culprit.
netconsole (with init_netconsole() hacked to call i915_init() when
logging has started, instead of by module_init()) tells the story:
kernel BUG at drivers/gpu/drm/i915/i915_sw_fence.c:245!
with RSI: 814d408b pointing to sw_fence_dummy_notify().
I've been building with CONFIG_CC_OPTIMIZE_FOR_SIZE=y, and that
function needs to be 4-byte aligned.
v2:
(Jani Nikula)
- Change BUG_ON to WARN_ON
Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
Signed-off-by: Hugh Dickins
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.c | 1 +
drivers/gpu/drm/i915/i915_sw_fence.c| 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index ff637147b1a9..f02c2202da9d 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -362,6 +362,7 @@ static int __intel_context_active(struct i915_active
*active)
return 0;
}
+__aligned(4) /* Respect the I915_SW_FENCE_MASK */
static int sw_fence_dummy_notify(struct i915_sw_fence *sf,
enum i915_sw_fence_notify state)
{
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c
b/drivers/gpu/drm/i915/i915_sw_fence.c
index c589a681da77..1217b124c1d0 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -14,8 +14,10 @@
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
#define I915_SW_FENCE_BUG_ON(expr) BUG_ON(expr)
+#define I915_SW_FENCE_WARN_ON(expr) WARN_ON(expr)
#else
#define I915_SW_FENCE_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
+#define I915_SW_FENCE_WARN_ON(expr) BUILD_BUG_ON_INVALID(expr)
#endif
static DEFINE_SPINLOCK(i915_sw_fence_lock);
@@ -242,7 +244,7 @@ void __i915_sw_fence_init(struct i915_sw_fence *fence,
const char *name,
struct lock_class_key *key)
{
- BUG_ON(!fn || (unsigned long)fn & ~I915_SW_FENCE_MASK);
+ I915_SW_FENCE_WARN_ON(!fn || (unsigned long)fn & ~I915_SW_FENCE_MASK);
__init_waitqueue_head(>wait, name, key);
fence->flags = (unsigned long)fn;
--
2.32.0
[Intel-gfx] [PATCH] drm/i915: fix blank screen booting crashes
From: Hugh Dickins
5.15-rc1 crashes with blank screen when booting up on two ThinkPads
using i915. Bisections converge convincingly, but arrive at different
and surprising "culprits", none of them the actual culprit.
netconsole (with init_netconsole() hacked to call i915_init() when
logging has started, instead of by module_init()) tells the story:
kernel BUG at drivers/gpu/drm/i915/i915_sw_fence.c:245!
with RSI: 814d408b pointing to sw_fence_dummy_notify().
I've been building with CONFIG_CC_OPTIMIZE_FOR_SIZE=y, and that
function needs to be 4-byte aligned.
v2:
(Jani Nikula)
- Change BUG_ON to WARN_ON
Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
Signed-off-by: Hugh Dickins
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.c | 1 +
drivers/gpu/drm/i915/i915_sw_fence.c| 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index ff637147b1a9..f02c2202da9d 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -362,6 +362,7 @@ static int __intel_context_active(struct i915_active
*active)
return 0;
}
+__aligned(4) /* Respect the I915_SW_FENCE_MASK */
static int sw_fence_dummy_notify(struct i915_sw_fence *sf,
enum i915_sw_fence_notify state)
{
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c
b/drivers/gpu/drm/i915/i915_sw_fence.c
index c589a681da77..1217b124c1d0 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -14,8 +14,10 @@
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
#define I915_SW_FENCE_BUG_ON(expr) BUG_ON(expr)
+#define I915_SW_FENCE_WARN_ON(expr) WARN_ON(expr)
#else
#define I915_SW_FENCE_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
+#define I915_SW_FENCE_WARN_ON(expr) BUILD_BUG_ON_INVALID(expr)
#endif
static DEFINE_SPINLOCK(i915_sw_fence_lock);
@@ -242,7 +244,7 @@ void __i915_sw_fence_init(struct i915_sw_fence *fence,
const char *name,
struct lock_class_key *key)
{
- BUG_ON(!fn || (unsigned long)fn & ~I915_SW_FENCE_MASK);
+ I915_SW_FENCE_WARN_ON(!fn || (unsigned long)fn & ~I915_SW_FENCE_MASK);
__init_waitqueue_head(>wait, name, key);
fence->flags = (unsigned long)fn;
--
2.32.0
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Add "intel_" as prefix in set_mocs_index() (rev3)
== Series Details == Series: drm/i915/gt: Add "intel_" as prefix in set_mocs_index() (rev3) URL : https://patchwork.freedesktop.org/series/94721/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10605_full -> Patchwork_21088_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21088_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21088_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21088_full: ### IGT changes ### Possible regressions * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs: - shard-iclb: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/shard-iclb7/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs.html * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile: - shard-iclb: [PASS][2] -> [SKIP][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb7/igt@kms_flip_scaled_...@flip-32bpp-ytileccs-to-64bpp-ytile.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/shard-iclb2/igt@kms_flip_scaled_...@flip-32bpp-ytileccs-to-64bpp-ytile.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt: - shard-tglb: [PASS][4] -> [INCOMPLETE][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb1/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-blt.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/shard-tglb8/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-blt.html Known issues Here are the changes found in Patchwork_21088_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_sseu@engines: - shard-skl: NOTRUN -> [SKIP][6] ([fdo#109271]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/shard-skl9/igt@gem_ctx_s...@engines.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/shard-tglb6/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl6/igt@gem_exec_fair@basic-p...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/shard-kbl6/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [PASS][11] -> [SKIP][12] ([fdo#109271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_params@rsvd2-dirt: - shard-tglb: NOTRUN -> [SKIP][14] ([fdo#109283]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/shard-tglb5/igt@gem_exec_par...@rsvd2-dirt.html * igt@gem_exec_suspend@basic-s0: - shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([i915#456]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb2/igt@gem_exec_susp...@basic-s0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/shard-tglb7/igt@gem_exec_susp...@basic-s0.html * igt@gem_huc_copy@huc-copy: - shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/shard-kbl6/igt@gem_huc_c...@huc-copy.html * igt@gem_media_vme: - shard-tglb: NOTRUN -> [SKIP][18] ([i915#284]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/shard-tglb5/igt@gem_media_vme.html * igt@gem_pread@exhaustion: - shard-skl: NOTRUN -> [WARN][19] ([i915#2658]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/shard-skl3/igt@gem_pr...@exhaustion.html * igt@gen9_exec_parse@valid-registers: - shard-tglb: NOTRUN -> [SKIP][20] ([i915#2856]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/shard-tglb5/igt@gen9_exec_pa...@valid-registers.html * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait: - shard-kbl:
Re: [Intel-gfx] 5.15-rc1 i915 blank screen booting on ThinkPads
On Sat, Sep 18, 2021 at 01:52:48AM +0300, Jani Nikula wrote:
> On Fri, 17 Sep 2021, Matthew Brost wrote:
> > On Fri, Sep 17, 2021 at 02:26:48PM -0700, Hugh Dickins wrote:
> >> On Thu, 16 Sep 2021, Jani Nikula wrote:
> >> > On Thu, 16 Sep 2021, Tvrtko Ursulin
> >> > wrote:
> >> > > On 16/09/2021 05:37, Hugh Dickins wrote:
> >> > >> Two Lenovo ThinkPads, old T420s (2011), newer X1 Carbon 5th gen
> >> > >> (2017):
> >> > >> i915 working fine on both up to 5.14, but blank screens booting
> >> > >> 5.15-rc1,
> >> > >> kernel crashed in some way.
> >> ...
> >> > > Kernel logs with drm.debug=0xe, with the broken black screen state,
> >> > > would probably answer a lot of questions if you could gather it from
> >> > > both machines?
> >> >
> >> > And for that, I think it's best to file separate bugs at [1] and attach
> >> > the logs there. It helps keep the info in one place. Thanks.
> >> >
> >> > BR,
> >> > Jani.
> >> >
> >> > [1] https://gitlab.freedesktop.org/drm/intel/issues/new
> >>
> >> Thanks for the quick replies: but of course, getting kernel logs was
> >> the difficult part, this being bootup, with just a blank screen, and
> >> no logging to disk at this stage. I've never needed it before, but
> >> netconsole to the rescue.
> >>
> >> Problem then obvious, both machines now working,
> >> please let me skip the bug reports, here's a patch:
> >>
> >
> > Thanks for finding / fixing this Hugh. I will post this patch in a way
> > our CI system can understand.
>
> Thanks indeed!
>
> Matt, please get rid of the BUG_ON while at it, and make it a
> WARN. Oopsing doesn't do anyone any good.
>
Sure. Will do. Long term we should just look to rip out crap this (i.e.
stealing bits from aligned addresses for flags).
Matt
> BR,
> Jani.
>
> >
> > Matt
> >
> >> [PATCH] drm/i915: fix blank screen booting crashes
> >>
> >> 5.15-rc1 crashes with blank screen when booting up on two ThinkPads
> >> using i915. Bisections converge convincingly, but arrive at different
> >> and surprising "culprits", none of them the actual culprit.
> >>
> >> netconsole (with init_netconsole() hacked to call i915_init() when
> >> logging has started, instead of by module_init()) tells the story:
> >>
> >> kernel BUG at drivers/gpu/drm/i915/i915_sw_fence.c:245!
> >> with RSI: 814d408b pointing to sw_fence_dummy_notify().
> >> I've been building with CONFIG_CC_OPTIMIZE_FOR_SIZE=y, and that
> >> function needs to be 4-byte aligned.
> >>
> >> Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
> >> Signed-off-by: Hugh Dickins
> >> ---
> >>
> >> drivers/gpu/drm/i915/gt/intel_context.c |1 +
> >> 1 file changed, 1 insertion(+)
> >>
> >> --- a/drivers/gpu/drm/i915/gt/intel_context.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> >> @@ -362,6 +362,7 @@ static int __intel_context_active(struct
> >>return 0;
> >> }
> >>
> >> +__aligned(4) /* Respect the I915_SW_FENCE_MASK */
> >> static int sw_fence_dummy_notify(struct i915_sw_fence *sf,
> >> enum i915_sw_fence_notify state)
> >> {
>
> --
> Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Check SFC fusing on Xe_HP (rev2)
== Series Details == Series: Check SFC fusing on Xe_HP (rev2) URL : https://patchwork.freedesktop.org/series/94808/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen8_write32' - different lock
Re: [Intel-gfx] [PATCH 13/19] drm/i915/dg1: Read OPROM via SPI controller
On Mon, Apr 12, 2021 at 10:05:20AM +0100, Matthew Auld wrote:
From: Clint Taylor
Read OPROM SPI through MMIO and find VBT entry since we can't use
OpRegion and PCI mapping may not work on some systems due to the BIOS
not leaving the Option ROM mapped.
I was surprised to see we still don't have this patch applied. There is
some coding style to fix, but if we don't have it we are basically
relying on the fallback of using a fake/hardcoded vbt. I will do some
fixups and re-submit.
Lucas De Marchi
v2 by Jani:
- switch to intel_uncore_read/intel_uncore_write
Cc: Ville Syrjälä
Cc: Tomas Winkler
Cc: Jon Bloomfield
Signed-off-by: Clint Taylor
Signed-off-by: Lucas De Marchi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 80 +--
drivers/gpu/drm/i915/i915_reg.h | 8 +++
2 files changed, 82 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index ea4837d485a1..f9dc651f1652 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2238,6 +2238,66 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t
size)
return vbt;
}
+static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915)
+{
+ u32 count, data, found, store = 0;
+ u32 static_region, oprom_offset;
+ u32 oprom_size = 0x20;
+ u16 vbt_size;
+ u32 *vbt;
+
+ static_region = intel_uncore_read(>uncore, SPI_STATIC_REGIONS);
+ static_region &= OPTIONROM_SPI_REGIONID_MASK;
+ intel_uncore_write(>uncore, PRIMARY_SPI_REGIONID, static_region);
+
+ oprom_offset = intel_uncore_read(>uncore, OROM_OFFSET);
+ oprom_offset &= OROM_OFFSET_MASK;
+
+ for (count = 0; count < oprom_size; count += 4) {
+ intel_uncore_write(>uncore, PRIMARY_SPI_ADDRESS,
oprom_offset + count);
+ data = intel_uncore_read(>uncore, PRIMARY_SPI_TRIGGER);
+
+ if (data == *((const u32 *)"$VBT")) {
+ found = oprom_offset + count;
+ break;
+ }
+ }
+
+ if (count >= oprom_size)
+ goto err_not_found;
+
+ /* Get VBT size and allocate space for the VBT */
+ intel_uncore_write(>uncore, PRIMARY_SPI_ADDRESS, found +
+ offsetof(struct vbt_header, vbt_size));
+ vbt_size = intel_uncore_read(>uncore, PRIMARY_SPI_TRIGGER);
+ vbt_size &= 0x;
+
+ vbt = kzalloc(vbt_size, GFP_KERNEL);
+ if (!vbt) {
+ DRM_ERROR("Unable to allocate %u bytes for VBT storage\n",
+ vbt_size);
+ goto err_not_found;
+ }
+
+ for (count = 0; count < vbt_size; count += 4) {
+ intel_uncore_write(>uncore, PRIMARY_SPI_ADDRESS, found +
count);
+ data = intel_uncore_read(>uncore, PRIMARY_SPI_TRIGGER);
+ *(vbt + store++) = data;
+ }
+
+ if (!intel_bios_is_valid_vbt(vbt, vbt_size))
+ goto err_free_vbt;
+
+ DRM_DEBUG_KMS("Found valid VBT in SPI flash\n");
+
+ return (struct vbt_header *)vbt;
+
+err_free_vbt:
+ kfree(vbt);
+err_not_found:
+ return NULL;
+}
+
static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
@@ -2287,6 +2347,8 @@ static struct vbt_header *oprom_get_vbt(struct
drm_i915_private *i915)
pci_unmap_rom(pdev, oprom);
+ DRM_DEBUG_KMS("Found valid VBT in PCI ROM\n");
+
return vbt;
err_free_vbt:
@@ -2321,17 +2383,23 @@ void intel_bios_init(struct drm_i915_private *i915)
init_vbt_defaults(i915);
- /* If the OpRegion does not have VBT, look in PCI ROM. */
+ /*
+* If the OpRegion does not have VBT, look in SPI flash through MMIO or
+* PCI mapping
+*/
+ if (!vbt && IS_DGFX(i915)) {
+ oprom_vbt = spi_oprom_get_vbt(i915);
+ vbt = oprom_vbt;
+ }
+
if (!vbt) {
oprom_vbt = oprom_get_vbt(i915);
- if (!oprom_vbt)
- goto out;
-
vbt = oprom_vbt;
-
- drm_dbg_kms(>drm, "Found valid VBT in PCI ROM\n");
}
+ if (!vbt)
+ goto out;
+
bdb = get_bdb_header(vbt);
i915->vbt.version = bdb->version;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index da73dc939e58..54ff63b86df6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12540,6 +12540,14 @@ enum skl_power_gate {
#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
+#define PRIMARY_SPI_TRIGGER_MMIO(0x102040)
+#define PRIMARY_SPI_ADDRESS_MMIO(0x102080)
+#define PRIMARY_SPI_REGIONID
Re: [Intel-gfx] [PATCH 15/15] doc: drm: remove TODO entry regarding DRM_MODSET_LOCK_ALL cleanup
> Can we remove drm_modeset_lock_all[_ctx] now? If so, let's queue that up as > part > of the set. > drm_modeset_lock_all() and drm_modeset_unlock_all() can be removed (I'll do that on v2 of this patch series). drm_modset_lock_all_ctx() is a different story and there are still two places (one in the i915 driver and another one in the amd driver) where they are needed. I would need to understand the code better before trying to remove those :)
Re: [Intel-gfx] [PATCH 14/15] drm/amd: cleanup: drm_modeset_lock_all() --> DRM_MODESET_LOCK_ALL_BEGIN()
> > + struct drm_modeset_acquire_ctx ctx;
> > int r;
> > + int ret;
>
> Relocate ret with r please
Done!
> > - drm_modeset_unlock_all(dev);
> > + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
>
> You should check ret here
Done!
> > int r;
> > + int ret;
>
> Relocate ret with r
Done!
> > - drm_modeset_unlock_all(dev);
> > + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
> >
> > return 0;
>
> Return ret
Done!
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 9b1fc54555ee..5196c1d26f87 100644
> > @@ -2661,13 +2657,18 @@ static void handle_hpd_irq(void *param)
> >
> > amdgpu_dm_update_connector_after_detect(aconnector);
> >
> > - drm_modeset_lock_all(dev);
> > - dm_restore_drm_connector_state(dev, connector);
> > - drm_modeset_unlock_all(dev);
> > -
> > - if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
> > - drm_kms_helper_hotplug_event(dev);
> > + } else {
> > + goto out;
> > }
> > +
> > + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret);
> > + dm_restore_drm_connector_state(dev, connector);
> > + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
>
> Check ret here please
This function ("handle_hpd_irq") returns void. What would the appropriate way of
checking the error be?
> > @@ -2841,14 +2838,17 @@ static void handle_hpd_rx_irq(void *param)
> >
> > amdgpu_dm_update_connector_after_detect(aconnector);
> >
> > + } else {
> > + goto finish;
>
> You used 'out' above and 'finish' here. It would be nice to be consistent with
> naming, I see 'out' a lot more than 'finish', so my vote would be to change
> this
> label to 'out'.
I originally used "out", but turns out there is already an "out" label in this
function :)
I then searched for other "go to end" labels and found "finish" being used in
this same file.
But I can rename it to somehitng else ("out2" maybe?) to make it less confusing.
> > + }
> >
> > - drm_modeset_lock_all(dev);
> > - dm_restore_drm_connector_state(dev, connector);
> > - drm_modeset_unlock_all(dev);
> > + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret);
> > + dm_restore_drm_connector_state(dev, connector);
> > + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
>
> Check ret here?
This is another irq-like function returning void.
What can we do here after having checked the error?
> > +#include
>
> Top-level headers generally come above the driver headers. Also, now that I
> think
> about this a bit more, all of the new includes in this set should probably be
> for 'drm_modeset_lock.h' instead of 'drm_drv.h'.
Ok. Let me try that.
> > @@ -1259,13 +1257,16 @@ static ssize_t trigger_hotplug(struct file *f,
> > const char __user *buf,
> > + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret);
> > + dm_restore_drm_connector_state(dev, connector);
> > + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
>
> Check ret here?
This is a .write file_operations function expected to return a "size". Is it ok
for it to return an error? I guess so, right?
Re: [Intel-gfx] [PATCH 12/15] drm/i915: cleanup: drm_modeset_lock_all() --> DRM_MODESET_LOCK_ALL_BEGIN()
> > int i; > > + int ret; > > Please move up with i Done! > > + DRM_MODESET_LOCK_ALL_END((_priv->drm), ctx, ret); > > > > return 0; > > Return ret here Done! > > + struct drm_modeset_acquire_ctx ctx; > > int i; > > + int ret; > > Please move up with i Done! > > - drm_modeset_unlock_all(dev); > > + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); > > > > return 0; > > Return ret Done! > > - drm_modeset_unlock_all(dev); > > + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); > > > > return 0; > > Return ret Done! > > - drm_modeset_unlock_all(dev); > > + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); > > > > Check ret here and return an error if it's != 0 Done! > > @@ -1194,14 +1195,11 @@ int intel_overlay_put_image_ioctl(struct drm_device > > *dev, void *data, > > if (ret != 0) > > goto out_unlock; > > > > - drm_modeset_unlock_all(dev); > > - i915_gem_object_put(new_bo); > > - > > - return 0; > > - > > out_unlock: > > - drm_modeset_unlock_all(dev); > > - i915_gem_object_put(new_bo); > > + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); > > + > > + if (params->flags & I915_OVERLAY_ENABLE) > > + i915_gem_object_put(new_bo); > > This function refactor is a bit more involved than the > s/drm_modeset_lock_all/DRM_MODESET_LOCK_ALL_*/ changes in the rest of the > patch. > Could you split it out into a separate patch so it's not hidden away? Sure, no problem.
Re: [Intel-gfx] 5.15-rc1 i915 blank screen booting on ThinkPads
On Fri, 17 Sep 2021, Matthew Brost wrote:
> On Fri, Sep 17, 2021 at 02:26:48PM -0700, Hugh Dickins wrote:
>> On Thu, 16 Sep 2021, Jani Nikula wrote:
>> > On Thu, 16 Sep 2021, Tvrtko Ursulin wrote:
>> > > On 16/09/2021 05:37, Hugh Dickins wrote:
>> > >> Two Lenovo ThinkPads, old T420s (2011), newer X1 Carbon 5th gen (2017):
>> > >> i915 working fine on both up to 5.14, but blank screens booting
>> > >> 5.15-rc1,
>> > >> kernel crashed in some way.
>> ...
>> > > Kernel logs with drm.debug=0xe, with the broken black screen state,
>> > > would probably answer a lot of questions if you could gather it from
>> > > both machines?
>> >
>> > And for that, I think it's best to file separate bugs at [1] and attach
>> > the logs there. It helps keep the info in one place. Thanks.
>> >
>> > BR,
>> > Jani.
>> >
>> > [1] https://gitlab.freedesktop.org/drm/intel/issues/new
>>
>> Thanks for the quick replies: but of course, getting kernel logs was
>> the difficult part, this being bootup, with just a blank screen, and
>> no logging to disk at this stage. I've never needed it before, but
>> netconsole to the rescue.
>>
>> Problem then obvious, both machines now working,
>> please let me skip the bug reports, here's a patch:
>>
>
> Thanks for finding / fixing this Hugh. I will post this patch in a way
> our CI system can understand.
Thanks indeed!
Matt, please get rid of the BUG_ON while at it, and make it a
WARN. Oopsing doesn't do anyone any good.
BR,
Jani.
>
> Matt
>
>> [PATCH] drm/i915: fix blank screen booting crashes
>>
>> 5.15-rc1 crashes with blank screen when booting up on two ThinkPads
>> using i915. Bisections converge convincingly, but arrive at different
>> and surprising "culprits", none of them the actual culprit.
>>
>> netconsole (with init_netconsole() hacked to call i915_init() when
>> logging has started, instead of by module_init()) tells the story:
>>
>> kernel BUG at drivers/gpu/drm/i915/i915_sw_fence.c:245!
>> with RSI: 814d408b pointing to sw_fence_dummy_notify().
>> I've been building with CONFIG_CC_OPTIMIZE_FOR_SIZE=y, and that
>> function needs to be 4-byte aligned.
>>
>> Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
>> Signed-off-by: Hugh Dickins
>> ---
>>
>> drivers/gpu/drm/i915/gt/intel_context.c |1 +
>> 1 file changed, 1 insertion(+)
>>
>> --- a/drivers/gpu/drm/i915/gt/intel_context.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
>> @@ -362,6 +362,7 @@ static int __intel_context_active(struct
>> return 0;
>> }
>>
>> +__aligned(4)/* Respect the I915_SW_FENCE_MASK */
>> static int sw_fence_dummy_notify(struct i915_sw_fence *sf,
>> enum i915_sw_fence_notify state)
>> {
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load
== Series Details ==
Series: series starting with [1/3] drm/i915/display/dmc: Set
DC_STATE_DEBUG_MASK_CORES after firmware load
URL : https://patchwork.freedesktop.org/series/94819/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10605_full -> Patchwork_21087_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_21087_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21087_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_21087_full:
### IGT changes ###
Possible regressions
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb1/igt@gem_ctx_isolation@preservation...@bcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-tglb7/igt@gem_ctx_isolation@preservation...@bcs0.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {shard-rkl}:([FAIL][3], [FAIL][4], [FAIL][5]) ([i915#3002] /
[i915#3811]) -> ([FAIL][6], [FAIL][7]) ([i915#3002])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-rkl-6/igt@run...@aborted.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-rkl-2/igt@run...@aborted.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-rkl-2/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-rkl-2/igt@run...@aborted.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-rkl-6/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_21087_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@device_reset@unbind-reset-rebind:
- shard-kbl: [PASS][8] -> [DMESG-WARN][9] ([i915#4130])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl1/igt@device_re...@unbind-reset-rebind.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl7/igt@device_re...@unbind-reset-rebind.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-iclb: [PASS][10] -> [TIMEOUT][11] ([i915#3070])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb3/igt@gem_...@in-flight-contexts-immediate.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb1/igt@gem_...@in-flight-contexts-immediate.html
* igt@gem_eio@unwedge-stress:
- shard-skl: [PASS][12] -> [TIMEOUT][13] ([i915#2369] /
[i915#3063])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl5/igt@gem_...@unwedge-stress.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-skl8/igt@gem_...@unwedge-stress.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-tglb6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html
* igt@gem_huc_copy@huc-copy:
- shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl3/igt@gem_huc_c...@huc-copy.html
* igt@gem_pread@exhaustion:
- shard-skl: NOTRUN -> [WARN][18] ([i915#2658])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-skl4/igt@gem_pr...@exhaustion.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271]) +63 similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl4/igt@i915_pm_...@modeset-lpsp-stress-no-wait.html
* igt@i915_suspend@debugfs-reader:
- shard-tglb: [PASS][20] -> [INCOMPLETE][21] ([i915#456])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb5/igt@i915_susp...@debugfs-reader.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-tglb3/igt@i915_susp...@debugfs-reader.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-kbl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#3777])
[22]:
Re: [Intel-gfx] [PATCH 11/15] drm/msm: cleanup: drm_modeset_lock_all() --> DRM_MODESET_LOCK_ALL_BEGIN()
> > int i, out_width; > > + int ret; > > Please put ret with i & out_width Done! > > - drm_modeset_unlock_all(crtc->dev); > > + DRM_MODESET_LOCK_ALL_END(crtc->dev, ctx, ret); > > > > return 0; > > Return ret here Done!
[Intel-gfx] ✓ Fi.CI.BAT: success for 5.15-rc1 i915 blank screen booting on ThinkPads
== Series Details ==
Series: 5.15-rc1 i915 blank screen booting on ThinkPads
URL : https://patchwork.freedesktop.org/series/94820/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10605 -> Patchwork_21089
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21089:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload:
- {fi-ehl-2}: [INCOMPLETE][1] ([i915#4136]) -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-ehl-2/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-ehl-2/igt@i915_module_l...@reload.html
- {fi-jsl-1}: [TIMEOUT][3] ([i915#4136]) -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-jsl-1/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-jsl-1/igt@i915_module_l...@reload.html
Known issues
Here are the changes found in Patchwork_21089 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-sdma:
- fi-cfl-8109u: NOTRUN -> [SKIP][5] ([fdo#109271]) +17 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-cfl-8109u/igt@amdgpu/amd_ba...@cs-sdma.html
- fi-kbl-7500u: NOTRUN -> [SKIP][6] ([fdo#109271]) +17 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-kbl-7500u/igt@amdgpu/amd_ba...@cs-sdma.html
* igt@amdgpu/amd_basic@semaphore:
- fi-icl-y: NOTRUN -> [SKIP][7] ([fdo#109315]) +17 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-icl-y/igt@amdgpu/amd_ba...@semaphore.html
* igt@core_hotunplug@unbind-rebind:
- fi-cfl-guc: [PASS][8] -> [INCOMPLETE][9] ([i915#4130])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][10] ([i915#4130])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html
- fi-icl-u2: [PASS][11] -> [INCOMPLETE][12] ([i915#4130])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-icl-u2/igt@core_hotunp...@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([i915#2190])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#1155])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([fdo#111827]) +8 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][16] ([i915#4103]) +1 similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][17] ([fdo#109285])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: NOTRUN -> [SKIP][18] ([i915#1072]) +3 similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4: NOTRUN -> [SKIP][19] ([i915#3301])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- fi-tgl-1115g4: NOTRUN -> [FAIL][20] ([i915#1602] / [i915#2722])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-tgl-1115g4/igt@run...@aborted.html
- fi-skl-6700k2: NOTRUN -> [FAIL][21] ([i915#2426] / [i915#3363])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21089/fi-skl-6700k2/igt@run...@aborted.html
Re: [Intel-gfx] [PATCH 09/15] drm/omapdrm: cleanup: drm_modeset_lock_all() --> DRM_MODESET_LOCK_ALL_BEGIN()
> > - drm_modeset_unlock_all(fb->dev); > > + DRM_MODESET_LOCK_ALL_END(fb->dev, ctx, ret); > > > > return 0; > > Return ret here. Done!
Re: [Intel-gfx] [PATCH 06/15] drm/tegra: cleanup: drm_modeset_lock_all() --> DRM_MODESET_LOCK_ALL_BEGIN()
> > int err = 0; > > + int ret; > > You can use err here instead. Done!
Re: [Intel-gfx] [PATCH 08/15] drm/radeon: cleanup: drm_modeset_lock_all() --> DRM_MODESET_LOCK_ALL_BEGIN()
> > + struct drm_modeset_acquire_ctx ctx; > > int i, r; > > + int ret; > > Could you please tuck this up with i & r? Done! > > - drm_modeset_unlock_all(dev); > > + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); > > You should check ret here Would it be save to return at this point if the lock fails? In other words, can I just add this? --> "if (ret) return ret;" > > + struct drm_modeset_acquire_ctx ctx; > > int r; > > + int ret; > > Same suggestion here, move up with r Done! > > - drm_modeset_unlock_all(dev); > > + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); > > Also check ret here Same question. Would "if (ret) return ret;" be safe here? > > int i; > > + int ret; > > Move up with i Done! > > - drm_modeset_unlock_all(dev); > > + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); > > return 0; I can also "return ret;" instead of "0". What happens when a DEFINE_SHOW_ATTRIBUTE'd function returns non-zero? Is it ok? Or do we want to always return "0" to print whatever we can?
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for 5.15-rc1 i915 blank screen booting on ThinkPads
== Series Details == Series: 5.15-rc1 i915 blank screen booting on ThinkPads URL : https://patchwork.freedesktop.org/series/94820/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0a23b1f1e8f8 5.15-rc1 i915 blank screen booting on ThinkPads -:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #7: > On Thu, 16 Sep 2021, Tvrtko Ursulin wrote: total: 0 errors, 1 warnings, 0 checks, 7 lines checked
Re: [Intel-gfx] [PATCH 01/15] dmr: cleanup: drm_modeset_lock_all_ctx() --> DRM_MODESET_LOCK_ALL_BEGIN()
> > Could you please fix the subject, changing dmr to drm? > Ups! Sure, I'll fix that. Thanks for noticing. > > I think you can just reuse 'ret' instead of creating a new variable. That > ensures if the lock fails we return the error from the macros. > I didn't reuse "ret" because otherwise I would have had to change the prototype of the function (which currently returns a "bool" instead of an "int"). However I could, for example, check for any error and convert that into "false". Would that be ok?
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add "intel_" as prefix in set_mocs_index() (rev3)
== Series Details == Series: drm/i915/gt: Add "intel_" as prefix in set_mocs_index() (rev3) URL : https://patchwork.freedesktop.org/series/94721/ State : success == Summary == CI Bug Log - changes from CI_DRM_10605 -> Patchwork_21088 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/index.html Known issues Here are the changes found in Patchwork_21088 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-skl-6700k2: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/fi-skl-6700k2/igt@amdgpu/amd_ba...@cs-gfx.html * igt@amdgpu/amd_basic@cs-sdma: - fi-cfl-8109u: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/fi-cfl-8109u/igt@amdgpu/amd_ba...@cs-sdma.html - fi-kbl-7500u: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/fi-kbl-7500u/igt@amdgpu/amd_ba...@cs-sdma.html * igt@amdgpu/amd_cs_nop@sync-fork-gfx0: - fi-cfl-8700k: NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/fi-cfl-8700k/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html * igt@core_hotunplug@unbind-rebind: - fi-rkl-guc: [PASS][5] -> [INCOMPLETE][6] ([i915#4130]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-rkl-guc/igt@core_hotunp...@unbind-rebind.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/fi-rkl-guc/igt@core_hotunp...@unbind-rebind.html * igt@i915_module_load@reload: - fi-rkl-11600: [PASS][7] -> [INCOMPLETE][8] ([i915#4136]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-rkl-11600/igt@i915_module_l...@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/fi-rkl-11600/igt@i915_module_l...@reload.html * igt@runner@aborted: - fi-kbl-r: NOTRUN -> [FAIL][9] ([i915#1569] / [i915#192] / [i915#193] / [i915#194] / [i915#3363]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/fi-kbl-r/igt@run...@aborted.html - fi-skl-guc: NOTRUN -> [FAIL][10] ([i915#2426] / [i915#3363]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/fi-skl-guc/igt@run...@aborted.html Possible fixes * igt@core_hotunplug@unbind-rebind: - fi-cfl-8700k: [INCOMPLETE][11] ([i915#4130]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/fi-cfl-8700k/igt@core_hotunp...@unbind-rebind.html - fi-kbl-7500u: [INCOMPLETE][13] ([i915#4130]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html - fi-cfl-8109u: [INCOMPLETE][15] ([i915#4130]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-8109u/igt@core_hotunp...@unbind-rebind.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/fi-cfl-8109u/igt@core_hotunp...@unbind-rebind.html * igt@i915_module_load@reload: - fi-skl-6700k2: [INCOMPLETE][17] ([i915#4136]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-skl-6700k2/igt@i915_module_l...@reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/fi-skl-6700k2/igt@i915_module_l...@reload.html - fi-kbl-7567u: [DMESG-WARN][19] ([i915#4136]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-7567u/igt@i915_module_l...@reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/fi-kbl-7567u/igt@i915_module_l...@reload.html - fi-kbl-guc: [INCOMPLETE][21] ([i915#4139]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-guc/igt@i915_module_l...@reload.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/fi-kbl-guc/igt@i915_module_l...@reload.html Warnings * igt@i915_module_load@reload: - fi-cml-u2: [INCOMPLETE][23] ([i915#4130] / [i915#4136]) -> [INCOMPLETE][24] ([i915#4130]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cml-u2/igt@i915_module_l...@reload.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21088/fi-cml-u2/igt@i915_module_l...@reload.html - fi-kbl-soraka: [INCOMPLETE][25] ([i915#4130] / [i915#4136]) -> [INCOMPLETE][26] ([i915#4130]) [25]:
Re: [Intel-gfx] [PATCH 00/15] drm: cleanup: Use DRM_MODESET_LOCK_ALL_* helpers where possible
On 21/09/17 05:24PM, Daniel Vetter wrote: > > Can we at least replace those with drm_modeset_lock_all_ctx and delete > drm_modeset_lock_all? That would be really nice goal to make sure these > don't spread further. I just checked and turns out no one else is using "drm_modeset_lock_all()" anymore. The only reference is the definition of the function itself, which I did not remove because it was being EXPORT_SYMBOL'ed and I was not sure whether it could be removed or not (to prevent breaking third party modules maybe?) The same goes true for its sibling "dmr_modeset_unlock_all()". But if you give me the green light I'll remove both of them right away :)
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load
== Series Details ==
Series: series starting with [1/3] drm/i915/display/dmc: Set
DC_STATE_DEBUG_MASK_CORES after firmware load
URL : https://patchwork.freedesktop.org/series/94819/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10605 -> Patchwork_21087
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21087:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload:
- {fi-jsl-1}: [TIMEOUT][1] ([i915#4136]) -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-jsl-1/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-jsl-1/igt@i915_module_l...@reload.html
Known issues
Here are the changes found in Patchwork_21087 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-sdma:
- fi-cfl-8109u: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-cfl-8109u/igt@amdgpu/amd_ba...@cs-sdma.html
* igt@core_hotunplug@unbind-rebind:
- fi-skl-6700k2: [PASS][4] -> [INCOMPLETE][5] ([i915#4130])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-skl-6700k2/igt@core_hotunp...@unbind-rebind.html
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][6] ([i915#4130])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html
- fi-skl-guc: [PASS][7] -> [INCOMPLETE][8] ([i915#4130])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-skl-guc/igt@core_hotunp...@unbind-rebind.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-skl-guc/igt@core_hotunp...@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([i915#2190])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html
* igt@i915_module_load@reload:
- fi-rkl-11600: [PASS][10] -> [DMESG-WARN][11] ([i915#4136])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-rkl-11600/igt@i915_module_l...@reload.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-rkl-11600/igt@i915_module_l...@reload.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([i915#1155])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([fdo#111827]) +8 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#4103]) +1 similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([fdo#109285])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: NOTRUN -> [SKIP][16] ([i915#1072]) +3 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4: NOTRUN -> [SKIP][17] ([i915#3301])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- fi-tgl-1115g4: NOTRUN -> [FAIL][18] ([i915#1602] / [i915#2722])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@run...@aborted.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-cfl-8109u: [INCOMPLETE][19] ([i915#4130]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-8109u/igt@core_hotunp...@unbind-rebind.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-cfl-8109u/igt@core_hotunp...@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-kbl-7567u: [DMESG-WARN][21] ([i915#4136]) -> [PASS][22]
[21]:
Re: [Intel-gfx] 5.15-rc1 i915 blank screen booting on ThinkPads
On Fri, Sep 17, 2021 at 02:26:48PM -0700, Hugh Dickins wrote:
> On Thu, 16 Sep 2021, Jani Nikula wrote:
> > On Thu, 16 Sep 2021, Tvrtko Ursulin wrote:
> > > On 16/09/2021 05:37, Hugh Dickins wrote:
> > >> Two Lenovo ThinkPads, old T420s (2011), newer X1 Carbon 5th gen (2017):
> > >> i915 working fine on both up to 5.14, but blank screens booting 5.15-rc1,
> > >> kernel crashed in some way.
> ...
> > > Kernel logs with drm.debug=0xe, with the broken black screen state,
> > > would probably answer a lot of questions if you could gather it from
> > > both machines?
> >
> > And for that, I think it's best to file separate bugs at [1] and attach
> > the logs there. It helps keep the info in one place. Thanks.
> >
> > BR,
> > Jani.
> >
> > [1] https://gitlab.freedesktop.org/drm/intel/issues/new
>
> Thanks for the quick replies: but of course, getting kernel logs was
> the difficult part, this being bootup, with just a blank screen, and
> no logging to disk at this stage. I've never needed it before, but
> netconsole to the rescue.
>
> Problem then obvious, both machines now working,
> please let me skip the bug reports, here's a patch:
>
Thanks for finding / fixing this Hugh. I will post this patch in a way
our CI system can understand.
Matt
> [PATCH] drm/i915: fix blank screen booting crashes
>
> 5.15-rc1 crashes with blank screen when booting up on two ThinkPads
> using i915. Bisections converge convincingly, but arrive at different
> and surprising "culprits", none of them the actual culprit.
>
> netconsole (with init_netconsole() hacked to call i915_init() when
> logging has started, instead of by module_init()) tells the story:
>
> kernel BUG at drivers/gpu/drm/i915/i915_sw_fence.c:245!
> with RSI: 814d408b pointing to sw_fence_dummy_notify().
> I've been building with CONFIG_CC_OPTIMIZE_FOR_SIZE=y, and that
> function needs to be 4-byte aligned.
>
> Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
> Signed-off-by: Hugh Dickins
> ---
>
> drivers/gpu/drm/i915/gt/intel_context.c |1 +
> 1 file changed, 1 insertion(+)
>
> --- a/drivers/gpu/drm/i915/gt/intel_context.c
> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> @@ -362,6 +362,7 @@ static int __intel_context_active(struct
> return 0;
> }
>
> +__aligned(4) /* Respect the I915_SW_FENCE_MASK */
> static int sw_fence_dummy_notify(struct i915_sw_fence *sf,
>enum i915_sw_fence_notify state)
> {
Re: [Intel-gfx] [PATCH v2 3/5] drm/i915/display: Workaround cursor left overs with PSR2 selective fetch enabled
On Fri, 2021-09-17 at 20:49 +0300, Ville Syrjälä wrote: > On Fri, Sep 17, 2021 at 05:02:21PM +, Souza, Jose wrote: > > On Fri, 2021-09-17 at 16:04 +0300, Ville Syrjälä wrote: > > > On Thu, Sep 16, 2021 at 05:09:08PM +, Souza, Jose wrote: > > > > On Thu, 2021-09-16 at 16:17 +0300, Ville Syrjälä wrote: > > > > > On Wed, Sep 15, 2021 at 06:18:35PM +, Souza, Jose wrote: > > > > > > On Wed, 2021-09-15 at 17:58 +0300, Ville Syrjälä wrote: > > > > > > > On Tue, Sep 14, 2021 at 02:25:05PM -0700, José Roberto de Souza > > > > > > > wrote: > > > > > > > > Not sure why but when moving the cursor fast it causes some > > > > > > > > artifacts > > > > > > > > of the cursor to be left in the cursor path, adding some pixels > > > > > > > > above > > > > > > > > the cursor to the damaged area fixes the issue, so leaving this > > > > > > > > as a > > > > > > > > workaround until proper fix is found. > > > > > > > > > > > > > > Have you tried warping the cursor clear across the screen while > > > > > > > a partial update is already pending? I think it will go badly. > > > > > > > > > > > > You mean move the cursor for example from 0x0 to 500x500 in one > > > > > > frame? > > > > > > It will mark as damaged the previous area and the new one. > > > > > > > > > > Legacy cursor updates bypass all that stuff so you're not going to > > > > > updating the sel fetch area for the other planes. > > > > > > > > > > > > > > > > > > > > > > > > > In fact I'm thinking the mailbox style legacy cursor updates are > > > > > > > just > > > > > > > fundementally incompatible with partial updates since the cursor > > > > > > > can move outside of the already committed update region any time. > > > > > > > Ie. I suspect while the cursor is visible we simply can't do > > > > > > > partial > > > > > > > updates. > > > > > > > > > > > > Probably I did not understand what you want to say, but each cursor > > > > > > update will be in one frame, updating the necessary area. > > > > > > > > > > The legacy cursor uses mailbox updates so there is no 1:1 relationship > > > > > between actual scanned out frames and cursor ioctl calls. You can > > > > > have umpteen thousand cursor updates per frame. > > > > > > > > Not if intel_legacy_cursor_update() is changed to go to the slow path > > > > and do one atomic commit for each move. > > > > https://patchwork.freedesktop.org/patch/453192/?series=94522=1 > > > > > > That's not going to fly. The whole reason for the legacy cursor thing is > > > that X likes to do thousands of cursor updates per frame. > > > > From user experience perspective there is no issues in converting to atomic > > commit, those 3 videos that I shared with you have this conversion. > > I don't know what you've tested but the legacy cursor fastpath is very > much needed. We've have numerous bug reports whenever it has > accidentally regressed, and I've witnessed the carnage myself as well. > Hmm, I guess you didn't actually disable it fully. To do that you > would have to clear state->legacy_cursor_update explicitly somewhere. Thanks for pointing out state->legacy_cursor_update and yes setting it to false makes causes the cursor to lag. > > Either way I just retested the earlier patches just with the nonblocking > commit for dirtyfb hacked in, and I left the cursor code using the > half fast path you made it take. The user experience is still as bad > as before. Just moving the mouse around makes glxgears stutter, and the > reported fps drops to ~400 from that alone. And doing anything more > involved like moving windows around is still a total fail. I have tested it in a TGL and ADL-P, will try to get some gen9 to try it. Other than that I don't know what could this big difference between our setups. I'm using Mate like you with 'enable software compositing window manager' disabled. >
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load
== Series Details == Series: series starting with [1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load URL : https://patchwork.freedesktop.org/series/94819/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9:
Re: [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load
On Fri, Sep 17, 2021 at 01:52:39PM -0700, José Roberto de Souza wrote:
> Specification asks for DC_STATE_DEBUG_MASK_CORES to be set for all
> platforms that supports DMC, not only for geminilake and broxton.
According to the spec it's only required for BXT and GLK, see
Bspec 4234, 49193, 49194.
The register description is a bit vague, would need to be clarified
probably.
> While at is also taking the oportunity to simply the code.
>
> BSpec: 7402
> BSpec: 49436
> Cc: Imre Deak
> Cc: Gwan-gyeong Mun
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 16 +++-
> 1 file changed, 3 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index b0268552b2863..2dc9d632969db 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -255,20 +255,10 @@ intel_get_stepping_info(struct drm_i915_private *i915,
>
> static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
> {
> - u32 val, mask;
> -
> - mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
> -
> - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> - mask |= DC_STATE_DEBUG_MASK_CORES;
> -
> /* The below bit doesn't need to be cleared ever afterwards */
> - val = intel_de_read(dev_priv, DC_STATE_DEBUG);
> - if ((val & mask) != mask) {
> - val |= mask;
> - intel_de_write(dev_priv, DC_STATE_DEBUG, val);
> - intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
> - }
> + intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0,
> + DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
> + intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
> }
>
> /**
> --
> 2.33.0
>
Re: [Intel-gfx] [PATCH v2 13/13] drm/msm: Implement HDCP 1.x using the new drm HDCP helpers
On Thu, Sep 16, 2021 at 11:00:25PM -0700, Stephen Boyd wrote:
> Quoting Sean Paul (2021-09-15 13:38:32)
/snip
> > diff --git a/drivers/gpu/drm/msm/dp/dp_debug.c
> > b/drivers/gpu/drm/msm/dp/dp_debug.c
> > index 2f6247e80e9d..de16fca8782a 100644
> > --- a/drivers/gpu/drm/msm/dp/dp_debug.c
> > +++ b/drivers/gpu/drm/msm/dp/dp_debug.c
> > @@ -8,6 +8,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > #include "dp_parser.h"
> > #include "dp_catalog.h"
> > @@ -15,6 +16,7 @@
> > #include "dp_ctrl.h"
> > #include "dp_debug.h"
> > #include "dp_display.h"
> > +#include "dp_hdcp.h"
> >
> > #define DEBUG_NAME "msm_dp"
> >
> > @@ -24,6 +26,7 @@ struct dp_debug_private {
> > struct dp_usbpd *usbpd;
> > struct dp_link *link;
> > struct dp_panel *panel;
> > + struct dp_hdcp *hdcp;
> > struct drm_connector **connector;
> > struct device *dev;
> > struct drm_device *drm_dev;
> > @@ -349,6 +352,38 @@ static int dp_test_active_open(struct inode *inode,
> > inode->i_private);
> > }
> >
> > +static ssize_t dp_hdcp_key_write(struct file *file, const char __user
> > *ubuf,
>
> Is this the API that userspace is going to use to set the key? Or a
> simple debug interface that's used to test this code out? I hope it's a
> debugging aid and not the normal flow given that it's through debugfs.
>
At the moment, generic UAPI is not useful beyond msm-based CrOS devices, which
is not really a burden upstream should be carrying. On other platforms
(including qc-based Android devices), the key injection is done in HW. As such,
I'm tempted to kick key injection UAPI down the road.
Once I finish the userspace client in CrOS, I can upload the UAPI for folks to
comment on.
/snip
> > diff --git a/drivers/gpu/drm/msm/dp/dp_display.h
> > b/drivers/gpu/drm/msm/dp/dp_display.h
> > index 8b47cdabb67e..421268e47f30 100644
> > --- a/drivers/gpu/drm/msm/dp/dp_display.h
> > +++ b/drivers/gpu/drm/msm/dp/dp_display.h
> > +static int dp_hdcp_load_keys(struct drm_connector *connector)
> > +{
> > + struct dp_hdcp *hdcp = dp_display_connector_to_hdcp(connector);
> > + struct dp_hdcp_key *key;
> > + int i, ret = 0;
> > +
> > + mutex_lock(>key_lock);
> > +
> > + key = hdcp->key;
> > +
> > + if (!key->valid) {
> > + ret = -ENOENT;
> > + goto out;
> > + }
> > +
> > + dp_hdcp_write_dp(hdcp, DP_HDCP_SW_LOWER_AKSV, key->ksv.words[0]);
> > + dp_hdcp_write_dp(hdcp, DP_HDCP_SW_UPPER_AKSV, key->ksv.words[1]);
> > +
> > + for (i = 0; i < DP_HDCP_NUM_KEYS; i++) {
> > + dp_hdcp_write_hdcp(hdcp, DP_HDCP_KEY_LSB(i),
> > + key->keys[i].words[0]);
> > + dp_hdcp_write_hdcp(hdcp, DP_HDCP_KEY_MSB(i),
> > + key->keys[i].words[1]);
> > + }
> > +
> > + dp_hdcp_write_hdcp(hdcp, DP_HDCP_KEY_VALID, DP_HDCP_SW_KEY_VALID);
> > + wmb();
>
> What are the wmb()s for? Can you add a comment indicating what we're
> trying to fix by having them?
>
I think these were left over from testing (when things weren't working for me).
Will remove in the next version, thanks for catching!
/snip
> > diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c
> > b/drivers/gpu/drm/msm/dp/dp_parser.c
> > index 0519dd3ac3c3..75a163b0b5af 100644
> > --- a/drivers/gpu/drm/msm/dp/dp_parser.c
> > +++ b/drivers/gpu/drm/msm/dp/dp_parser.c
/snip
> > @@ -55,6 +55,8 @@ static void dp_parser_unmap_io_resources(struct dp_parser
> > *parser)
> > {
> > struct dp_io *io = >io;
> >
> > + msm_dss_iounmap(>hdcp_tz);
> > + msm_dss_iounmap(>hdcp_key);
> > msm_dss_iounmap(>dp_controller);
> > }
> >
> > @@ -64,10 +66,20 @@ static int dp_parser_ctrl_res(struct dp_parser *parser)
> > struct platform_device *pdev = parser->pdev;
> > struct dp_io *io = >io;
> >
> > - rc = msm_dss_ioremap(pdev, >dp_controller);
> > - if (rc) {
> > - DRM_ERROR("unable to remap dp io resources, rc=%d\n", rc);
> > + rc = msm_dss_ioremap(pdev, >dp_controller, 0);
> > + if (rc)
> > goto err;
> > +
> > + rc = msm_dss_ioremap(pdev, >hdcp_key, 1);
> > + if (rc) {
> > + io->hdcp_key.base = NULL;
> > + io->hdcp_key.len = 0;
> > + }
> > +
> > + rc = msm_dss_ioremap(pdev, >hdcp_tz, 2);
> > + if (rc) {
> > + io->hdcp_tz.base = NULL;
> > + io->hdcp_tz.len = 0;
>
> Bjorn is trying to split the single io region apart into 4 different
> regions[1]. This would add two more io regions. Maybe this should come
> after those patches and be indexed later? I worry about needing to add
> more register properties later on though. Maybe a better approach would
> be to make them mandatory for certain compatible strings instead.
Thanks for the heads up, I'll look into adding a
[Intel-gfx] [PATCH 3/3] drm/i915/display: Match PSR2 selective fetch sequences with specification
We were not completely following the selective fetch programming
sequence, here some things we were doing wrong:
- not programming plane selective fetch a PSR2_MAN_TRK_CTL registers
when doing a modeset
- programming PSR2_MAN_TRK_CTL out of vblank
With this changes the last remainig underrun found in Alderlake-P is
fixed.
Bspec: 55229
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_cursor.c | 4 ++-
drivers/gpu/drm/i915/display/intel_display.c | 12 +++
drivers/gpu/drm/i915/display/intel_psr.c | 33 ++-
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
.../drm/i915/display/skl_universal_plane.c| 4 +--
5 files changed, 36 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index c7618fef01439..901ad3a4c8c3b 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -536,8 +536,10 @@ static void i9xx_update_cursor(struct intel_plane *plane,
if (DISPLAY_VER(dev_priv) >= 9)
skl_write_cursor_wm(plane, crtc_state);
- if (!intel_crtc_needs_modeset(crtc_state))
+ if (plane_state)
intel_psr2_program_plane_sel_fetch(plane, crtc_state,
plane_state, 0);
+ else
+ intel_psr2_disable_plane_sel_fetch(plane, crtc_state);
if (plane->cursor.base != base ||
plane->cursor.size != fbc_ctl ||
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f6c0c595f6313..224bf622a1c1a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6812,11 +6812,9 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
}
- if (!mode_changed) {
- ret = intel_psr2_sel_fetch_update(state, crtc);
- if (ret)
- return ret;
- }
+ ret = intel_psr2_sel_fetch_update(state, crtc);
+ if (ret)
+ return ret;
return 0;
}
@@ -9709,10 +9707,10 @@ static void commit_pipe_pre_planes(struct
intel_atomic_state *state,
if (new_crtc_state->update_pipe)
intel_pipe_fastset(old_crtc_state, new_crtc_state);
-
- intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
}
+ intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
+
if (dev_priv->display.atomic_update_watermarks)
dev_priv->display.atomic_update_watermarks(state, crtc);
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index bd13325782f11..101a23bdd7b5b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -561,15 +561,16 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val |= EDP_PSR2_SU_SDP_SCANLINE;
if (intel_dp->psr.psr2_sel_fetch_enabled) {
+ u32 tmp;
+
/* Wa_1408330847 */
if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK,
DIS_RAM_BYPASS_PSR2_MAN_TRACK);
- intel_de_write(dev_priv,
- PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
- PSR2_MAN_TRK_CTL_ENABLE);
+ tmp = intel_de_read(dev_priv,
PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
+ drm_WARN_ON(_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
} else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
intel_de_write(dev_priv,
PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);
@@ -1450,6 +1451,18 @@ static void psr_force_hw_tracking_exit(struct intel_dp
*intel_dp)
intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
}
+void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
+ const struct intel_crtc_state
*crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+
+ if (!crtc_state->enable_psr2_sel_fetch)
+ return;
+
+ intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
+}
+
void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
const struct intel_crtc_state
*crtc_state,
const struct intel_plane_state
*plane_state,
@@ -1464,11 +1477,11 @@ void intel_psr2_program_plane_sel_fetch(struct
intel_plane *plane,
if (!crtc_state->enable_psr2_sel_fetch)
return;
- val = plane_state ? plane_state->ctl : 0;
- val &= plane->id ==
[Intel-gfx] [PATCH 2/3] drm/i915/display: Wait PSR2 get out of deep sleep to update pipe
Alderlake-P was getting 'max time under evasion' messages when PSR2
was enabled, this is due PIPE_SCANLINE/PIPEDSL returning 0 over a
period of time longer than VBLANK_EVASION_TIME_US.
For PSR1 we had the same issue so intel_psr_wait_for_idle() was
implemented to wait for PSR1 to get into idle state but nothing was
done for PSR2.
For PSR2 we can't only wait for idle state as PSR2 tends to keep
into sleep state that means it is ready to send selective updates.
To do so it was necessary to add intel_wait_for_condition(), this
takes as parameter a function that will return true when the desidered
condition is meet.
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
.../drm/i915/display/intel_display_debugfs.c | 3 +-
drivers/gpu/drm/i915/display/intel_psr.c | 64 ---
drivers/gpu/drm/i915/i915_reg.h | 5 +-
drivers/gpu/drm/i915/intel_uncore.c | 47 ++
drivers/gpu/drm/i915/intel_uncore.h | 7 ++
5 files changed, 100 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 68f4ba8c46e75..662596adb1da6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -303,8 +303,7 @@ psr_source_status(struct intel_dp *intel_dp, struct
seq_file *m)
};
val = intel_de_read(dev_priv,
EDP_PSR2_STATUS(intel_dp->psr.transcoder));
- status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
- EDP_PSR2_STATUS_STATE_SHIFT;
+ status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
if (status_val < ARRAY_SIZE(live_status))
status = live_status[status_val];
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index c1894b056d6c1..bd13325782f11 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1763,15 +1763,33 @@ void intel_psr_update(struct intel_dp *intel_dp,
mutex_unlock(_dp->psr.lock);
}
-/**
- * psr_wait_for_idle - wait for PSR1 to idle
- * @intel_dp: Intel DP
- * @out_value: PSR status in case of failure
- *
- * Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
- *
- */
-static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value)
+static bool _is_psr2_read_for_pipe_update(void *data)
+{
+ struct intel_dp *intel_dp = data;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u32 val;
+
+ val = intel_uncore_read_fw(_priv->uncore,
+ EDP_PSR2_STATUS(intel_dp->psr.transcoder));
+ val &= EDP_PSR2_STATUS_STATE_MASK;
+
+ return val == EDP_PSR2_STATUS_STATE_SLEEP || val ==
EDP_PSR2_STATUS_STATE_IDLE;
+}
+
+static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ unsigned int fw;
+
+ fw = intel_uncore_forcewake_for_reg(_priv->uncore,
+
EDP_PSR2_STATUS(intel_dp->psr.transcoder),
+ FW_REG_READ);
+ return intel_wait_for_condition(_priv->uncore,
+ _is_psr2_read_for_pipe_update,
+ intel_dp, fw, 50);
+}
+
+static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1781,15 +1799,13 @@ static int psr_wait_for_idle(struct intel_dp *intel_dp,
u32 *out_value)
* exit training time + 1.5 ms of aux channel handshake. 50 ms is
* defensive enough to cover everything.
*/
- return __intel_wait_for_register(_priv->uncore,
-
EDP_PSR_STATUS(intel_dp->psr.transcoder),
-EDP_PSR_STATUS_STATE_MASK,
-EDP_PSR_STATUS_STATE_IDLE, 2, 50,
-out_value);
+ return intel_de_wait_for_clear(dev_priv,
+ EDP_PSR_STATUS(intel_dp->psr.transcoder),
+ EDP_PSR_STATUS_STATE_MASK, 50);
}
/**
- * intel_psr_wait_for_idle - wait for PSR1 to idle
+ * intel_psr_wait_for_idle - wait for PSR be ready for a pipe update
* @new_crtc_state: new CRTC state
*
* This function is expected to be called from pipe_update_start() where it is
@@ -1806,19 +1822,23 @@ void intel_psr_wait_for_idle(const struct
intel_crtc_state *new_crtc_state)
for_each_intel_encoder_mask_with_psr(_priv->drm, encoder,
new_crtc_state->uapi.encoder_mask)
{
struct intel_dp *intel_dp =
[Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load
Specification asks for DC_STATE_DEBUG_MASK_CORES to be set for all
platforms that supports DMC, not only for geminilake and broxton.
While at is also taking the oportunity to simply the code.
BSpec: 7402
BSpec: 49436
Cc: Imre Deak
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_dmc.c | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index b0268552b2863..2dc9d632969db 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -255,20 +255,10 @@ intel_get_stepping_info(struct drm_i915_private *i915,
static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
{
- u32 val, mask;
-
- mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
-
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- mask |= DC_STATE_DEBUG_MASK_CORES;
-
/* The below bit doesn't need to be cleared ever afterwards */
- val = intel_de_read(dev_priv, DC_STATE_DEBUG);
- if ((val & mask) != mask) {
- val |= mask;
- intel_de_write(dev_priv, DC_STATE_DEBUG, val);
- intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
- }
+ intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0,
+DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
+ intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
}
/**
--
2.33.0
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation (rev5)
On Fri, 2021-09-17 at 04:29 +, Patchwork wrote: > Patch Details > Series: series starting with [v2,1/5] drm/i915/display/adlp: Fix > PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation (rev5) > URL: https://patchwork.freedesktop.org/series/94674/ > State:failure > Details: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21082/index.html > CI Bug Log - changes from CI_DRM_10600_full -> Patchwork_21082_full > Summary > FAILURE > > Serious unknown changes coming with Patchwork_21082_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_21082_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > Possible new issues > Here are the unknown changes that may have been introduced in > Patchwork_21082_full: > > IGT changes > Possible regressions > igt@i915_pm_rpm@gem-mmap-type: Another INCOMPLETE because of audio issues, not related. > > shard-kbl: NOTRUN -> INCOMPLETE > igt@kms_atomic@plane-invalid-params: > > shard-iclb: PASS -> DMESG-WARN This is a missing FBC case, not related to this changes. Pushing this series even with CI not 100% back, 4 of 5 patches here only affects a feature that is not enabled by default the remaining one only makes sure that EDP_PSR2_FRAME_BEFORE_SU() minimum is 2 and not 1. The discussing going in 'drm/i915/display: Workaround cursor left overs with PSR2 selective fetch enabled' are not specific about that patch. Thanks for the reviews GG. > Known issues > Here are the changes found in Patchwork_21082_full that come from known > issues: > > IGT changes > Issues hit > igt@device_reset@unbind-reset-rebind: > > shard-kbl: NOTRUN -> DMESG-WARN (i915#4130) > igt@feature_discovery@chamelium: > > shard-skl: NOTRUN -> SKIP (fdo#109271) +18 similar issues > igt@gem_eio@unwedge-stress: > > shard-skl: PASS -> TIMEOUT (i915#2369 / i915#3063) > igt@gem_exec_fair@basic-none-solo@rcs0: > > shard-tglb: NOTRUN -> FAIL (i915#2842) > igt@gem_exec_fair@basic-pace@vcs0: > > shard-kbl: PASS -> FAIL (i915#2842) > igt@gem_exec_fair@basic-pace@vcs1: > > shard-iclb: NOTRUN -> FAIL (i915#2842) > igt@gem_pread@exhaustion: > > shard-tglb: NOTRUN -> WARN (i915#2658) > > shard-kbl: NOTRUN -> WARN (i915#2658) > > igt@gem_userptr_blits@input-checking: > > shard-kbl: NOTRUN -> DMESG-WARN (i915#3002) > igt@gen9_exec_parse@bb-start-cmd: > > shard-tglb: NOTRUN -> SKIP (i915#2856) > igt@i915_pm_rc6_residency@media-rc6-accuracy: > > shard-tglb: NOTRUN -> SKIP (fdo#109289 / fdo#111719) > igt@i915_pm_rpm@modeset-pc8-residency-stress: > > shard-tglb: NOTRUN -> SKIP (fdo#109506 / i915#2411) > igt@i915_suspend@fence-restore-untiled: > > shard-kbl: NOTRUN -> DMESG-WARN (i915#180) +1 similar issue > igt@kms_atomic@crtc-invalid-params-fence: > > shard-iclb: PASS -> DMESG-WARN (i915#3728) > igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip: > > shard-kbl: NOTRUN -> SKIP (fdo#109271 / i915#3777) +1 similar issue > igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip: > > shard-skl: NOTRUN -> FAIL (i915#3763) > igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip: > > shard-tglb: NOTRUN -> SKIP (fdo#111615) +1 similar issue > igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_ccs: > > shard-tglb: NOTRUN -> SKIP (i915#3689) > igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc: > > shard-kbl: NOTRUN -> SKIP (fdo#109271 / i915#3886) +6 similar issues > igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs: > > shard-skl: NOTRUN -> SKIP (fdo#109271 / i915#3886) +1 similar issue > igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs: > > shard-tglb: NOTRUN -> SKIP (i915#3689 / i915#3886) +2 similar issues > igt@kms_chamelium@dp-hpd-storm: > > shard-skl: NOTRUN -> SKIP (fdo#109271 / fdo#111827) > igt@kms_chamelium@hdmi-hpd-for-each-pipe: > > shard-kbl: NOTRUN -> SKIP (fdo#109271 / fdo#111827) +12 similar issues > igt@kms_color_chamelium@pipe-c-gamma: > > shard-tglb: NOTRUN -> SKIP (fdo#109284 / fdo#111827) +6 similar issues > igt@kms_cursor_crc@pipe-c-cursor-512x170-rapid-movement: > > shard-tglb: NOTRUN -> SKIP (i915#3359) +1 similar issue > igt@kms_cursor_crc@pipe-d-cursor-512x170-sliding: > > shard-tglb: NOTRUN -> SKIP (fdo#109279 / i915#3359) > igt@kms_cursor_crc@pipe-d-cursor-suspend: > > shard-kbl: NOTRUN -> SKIP (fdo#109271) +98 similar issues > igt@kms_flip@flip-vs-expired-vblank@a-edp1: > > shard-skl: PASS -> FAIL (i915#79) +1 similar issue > igt@kms_flip@flip-vs-suspend@a-edp1: > > shard-tglb: PASS -> INCOMPLETE (i915#456) +3 similar issues > igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff: > > shard-tglb: NOTRUN -> SKIP (fdo#111825) +10 similar issues > igt@kms_frontbuffer_tracking@fbcpsr-suspend: > > shard-tglb: PASS -> INCOMPLETE (i915#2411 / i915#456) > igt@kms_hdr@bpc-switch-dpms: > > shard-skl: PASS -> FAIL
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Make wa list per-gt
On Fri, Sep 17, 2021 at 05:44:55PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Make wa list per-gt
> URL : https://patchwork.freedesktop.org/series/94811/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_10604 -> Patchwork_21086
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_21086 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_21086, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/index.html
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_21086:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@kms_flip@basic-plain-flip@c-dp1:
> - fi-cfl-8109u: [PASS][1] -> [FAIL][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-cfl-8109u/igt@kms_flip@basic-plain-f...@c-dp1.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-cfl-8109u/igt@kms_flip@basic-plain-f...@c-dp1.html
(kms_flip:5362) CRITICAL: Test assertion failure function
__run_test_on_crtc_set, file ../tests/kms_flip.c:1333:
(kms_flip:5362) CRITICAL: Failed assertion: crtc_count > 1 || crtc_idxs[0] < 2
Not related to this GT workaround refactoring.
Matt
>
>
> Warnings
>
> * igt@i915_module_load@reload:
> - fi-kbl-soraka: [INCOMPLETE][3] ([i915#4130] / [i915#4136]) ->
> [INCOMPLETE][4]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-kbl-soraka/igt@i915_module_l...@reload.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-kbl-soraka/igt@i915_module_l...@reload.html
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@i915_module_load@reload:
> - {fi-ehl-2}: [INCOMPLETE][5] ([i915#4136]) -> [INCOMPLETE][6]
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-ehl-2/igt@i915_module_l...@reload.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-ehl-2/igt@i915_module_l...@reload.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_21086 that come from known issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@amdgpu/amd_basic@cs-gfx:
> - fi-rkl-guc: NOTRUN -> [SKIP][7] ([fdo#109315]) +17 similar
> issues
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html
>
> * igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
> - fi-cfl-8700k: NOTRUN -> [SKIP][8] ([fdo#109271]) +17 similar
> issues
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-cfl-8700k/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html
>
> * igt@core_hotunplug@unbind-rebind:
> - fi-cfl-guc: [PASS][9] -> [INCOMPLETE][10] ([i915#4130])
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
> - fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][11] ([i915#4130])
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html
> - fi-kbl-7567u: [PASS][12] -> [INCOMPLETE][13] ([i915#4130])
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-kbl-7567u/igt@core_hotunp...@unbind-rebind.html
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-kbl-7567u/igt@core_hotunp...@unbind-rebind.html
>
> * igt@gem_huc_copy@huc-copy:
> - fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#2190])
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html
>
> * igt@i915_module_load@reload:
> - fi-skl-6700k2: NOTRUN -> [INCOMPLETE][15] ([i915#4130])
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-skl-6700k2/igt@i915_module_l...@reload.html
> - fi-skl-guc: [PASS][16] -> [INCOMPLETE][17] ([i915#4130])
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-skl-guc/igt@i915_module_l...@reload.html
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-skl-guc/igt@i915_module_l...@reload.html
> - fi-kbl-guc: [PASS][18] -> [INCOMPLETE][19] ([i915#4139])
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-kbl-guc/igt@i915_module_l...@reload.html
>[19]:
>
Re: [Intel-gfx] [PATCH v2 3/5] drm/i915/display: Workaround cursor left overs with PSR2 selective fetch enabled
On Fri, Sep 17, 2021 at 05:02:21PM +, Souza, Jose wrote: > On Fri, 2021-09-17 at 16:04 +0300, Ville Syrjälä wrote: > > On Thu, Sep 16, 2021 at 05:09:08PM +, Souza, Jose wrote: > > > On Thu, 2021-09-16 at 16:17 +0300, Ville Syrjälä wrote: > > > > On Wed, Sep 15, 2021 at 06:18:35PM +, Souza, Jose wrote: > > > > > On Wed, 2021-09-15 at 17:58 +0300, Ville Syrjälä wrote: > > > > > > On Tue, Sep 14, 2021 at 02:25:05PM -0700, José Roberto de Souza > > > > > > wrote: > > > > > > > Not sure why but when moving the cursor fast it causes some > > > > > > > artifacts > > > > > > > of the cursor to be left in the cursor path, adding some pixels > > > > > > > above > > > > > > > the cursor to the damaged area fixes the issue, so leaving this > > > > > > > as a > > > > > > > workaround until proper fix is found. > > > > > > > > > > > > Have you tried warping the cursor clear across the screen while > > > > > > a partial update is already pending? I think it will go badly. > > > > > > > > > > You mean move the cursor for example from 0x0 to 500x500 in one frame? > > > > > It will mark as damaged the previous area and the new one. > > > > > > > > Legacy cursor updates bypass all that stuff so you're not going to > > > > updating the sel fetch area for the other planes. > > > > > > > > > > > > > > > > > > > > > In fact I'm thinking the mailbox style legacy cursor updates are > > > > > > just > > > > > > fundementally incompatible with partial updates since the cursor > > > > > > can move outside of the already committed update region any time. > > > > > > Ie. I suspect while the cursor is visible we simply can't do partial > > > > > > updates. > > > > > > > > > > Probably I did not understand what you want to say, but each cursor > > > > > update will be in one frame, updating the necessary area. > > > > > > > > The legacy cursor uses mailbox updates so there is no 1:1 relationship > > > > between actual scanned out frames and cursor ioctl calls. You can > > > > have umpteen thousand cursor updates per frame. > > > > > > Not if intel_legacy_cursor_update() is changed to go to the slow path and > > > do one atomic commit for each move. > > > https://patchwork.freedesktop.org/patch/453192/?series=94522=1 > > > > That's not going to fly. The whole reason for the legacy cursor thing is > > that X likes to do thousands of cursor updates per frame. > > From user experience perspective there is no issues in converting to atomic > commit, those 3 videos that I shared with you have this conversion. I don't know what you've tested but the legacy cursor fastpath is very much needed. We've have numerous bug reports whenever it has accidentally regressed, and I've witnessed the carnage myself as well. Hmm, I guess you didn't actually disable it fully. To do that you would have to clear state->legacy_cursor_update explicitly somewhere. Either way I just retested the earlier patches just with the nonblocking commit for dirtyfb hacked in, and I left the cursor code using the half fast path you made it take. The user experience is still as bad as before. Just moving the mouse around makes glxgears stutter, and the reported fps drops to ~400 from that alone. And doing anything more involved like moving windows around is still a total fail. -- Ville Syrjälä Intel
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Make wa list per-gt
== Series Details ==
Series: drm/i915: Make wa list per-gt
URL : https://patchwork.freedesktop.org/series/94811/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10604 -> Patchwork_21086
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_21086 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21086, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21086:
### IGT changes ###
Possible regressions
* igt@kms_flip@basic-plain-flip@c-dp1:
- fi-cfl-8109u: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-cfl-8109u/igt@kms_flip@basic-plain-f...@c-dp1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-cfl-8109u/igt@kms_flip@basic-plain-f...@c-dp1.html
Warnings
* igt@i915_module_load@reload:
- fi-kbl-soraka: [INCOMPLETE][3] ([i915#4130] / [i915#4136]) ->
[INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-kbl-soraka/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-kbl-soraka/igt@i915_module_l...@reload.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload:
- {fi-ehl-2}: [INCOMPLETE][5] ([i915#4136]) -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-ehl-2/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-ehl-2/igt@i915_module_l...@reload.html
Known issues
Here are the changes found in Patchwork_21086 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-rkl-guc: NOTRUN -> [SKIP][7] ([fdo#109315]) +17 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-cfl-8700k: NOTRUN -> [SKIP][8] ([fdo#109271]) +17 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-cfl-8700k/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html
* igt@core_hotunplug@unbind-rebind:
- fi-cfl-guc: [PASS][9] -> [INCOMPLETE][10] ([i915#4130])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][11] ([i915#4130])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html
- fi-kbl-7567u: [PASS][12] -> [INCOMPLETE][13] ([i915#4130])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-kbl-7567u/igt@core_hotunp...@unbind-rebind.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-kbl-7567u/igt@core_hotunp...@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#2190])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html
* igt@i915_module_load@reload:
- fi-skl-6700k2: NOTRUN -> [INCOMPLETE][15] ([i915#4130])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-skl-6700k2/igt@i915_module_l...@reload.html
- fi-skl-guc: [PASS][16] -> [INCOMPLETE][17] ([i915#4130])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-skl-guc/igt@i915_module_l...@reload.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-skl-guc/igt@i915_module_l...@reload.html
- fi-kbl-guc: [PASS][18] -> [INCOMPLETE][19] ([i915#4139])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-kbl-guc/igt@i915_module_l...@reload.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-kbl-guc/igt@i915_module_l...@reload.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][20] ([i915#1155])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][21] ([fdo#111827]) +8 similar issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21086/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html
*
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Check SFC fusing before recording/dumping SFC_DONE
On Fri, 2021-09-17 at 09:12 -0700, Matt Roper wrote: > On Xe_HP and beyond the SFC unit may be fused off, even if the > corresponding media engines are present. Check the SFC-specific fusing > before trying to dump the SFC_DONE instances. Reviewed-by: José Roberto de Souza > > Cc: José Roberto de Souza > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/i915_gpu_error.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c > b/drivers/gpu/drm/i915/i915_gpu_error.c > index b9f66dbd46bb..2a2d7643b551 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -753,7 +753,8 @@ static void err_print_gt(struct drm_i915_error_state_buf > *m, >* only exists if the corresponding VCS engine is >* present. >*/ > - if (!HAS_ENGINE(gt->_gt, _VCS(i * 2))) > + if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || > + !HAS_ENGINE(gt->_gt, _VCS(i * 2))) > continue; > > err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, > @@ -1632,7 +1633,8 @@ static void gt_record_regs(struct intel_gt_coredump *gt) >* only exists if the corresponding VCS engine is >* present. >*/ > - if (!HAS_ENGINE(gt->_gt, _VCS(i * 2))) > + if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || > + !HAS_ENGINE(gt->_gt, _VCS(i * 2))) > continue; > > gt->sfc_done[i] =
Re: [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Check new fuse bits for SFC availability
On Fri, 2021-09-17 at 09:12 -0700, Matt Roper wrote:
> Xe_HP adds some new bits to the FUSE1 register to let us know whether a
> given SFC unit is present. We should take this into account while
> initializing SFC availability to our VCS and VECS engines.
>
> While we're at it, update the FUSE1 register definition to use
> REG_GENMASK / REG_FIELD_GET notation.
>
> Note that, the bspec confusingly names the fuse bits "disable" despite
> the register reflecting the *enable* status of the SFC units. The
> original architecture documents which the bspec is based on do properly
> name this field "SFC_ENABLE."
Reviewed-by: José Roberto de Souza
>
> Bspec: 52543
> Cc: José Roberto de Souza
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 25 ++-
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
> drivers/gpu/drm/i915/gt/intel_sseu.c | 5 ++---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> 4 files changed, 27 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 332efea696a5..06dfe7f38953 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -398,7 +398,8 @@ static void __setup_engine_capabilities(struct
> intel_engine_cs *engine)
> engine->uabi_capabilities |=
> I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
> } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
> - if (GRAPHICS_VER(i915) >= 9)
> + if (GRAPHICS_VER(i915) >= 9 &&
> + engine->gt->info.sfc_mask & BIT(engine->instance))
> engine->uabi_capabilities |=
> I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
> }
> @@ -474,18 +475,25 @@ void intel_engines_free(struct intel_gt *gt)
> }
>
> static
> -bool gen11_vdbox_has_sfc(struct drm_i915_private *i915,
> +bool gen11_vdbox_has_sfc(struct intel_gt *gt,
>unsigned int physical_vdbox,
>unsigned int logical_vdbox, u16 vdbox_mask)
> {
> + struct drm_i915_private *i915 = gt->i915;
> +
> /*
>* In Gen11, only even numbered logical VDBOXes are hooked
>* up to an SFC (Scaler & Format Converter) unit.
>* In Gen12, Even numbered physical instance always are connected
>* to an SFC. Odd numbered physical instances have SFC only if
>* previous even instance is fused off.
> + *
> + * Starting with Xe_HP, there's also a dedicated SFC_ENABLE field
> + * in the fuse register that tells us whether a specific SFC is present.
>*/
> - if (GRAPHICS_VER(i915) == 12)
> + if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
> + return false;
> + else if (GRAPHICS_VER(i915) == 12)
> return (physical_vdbox % 2 == 0) ||
> !(BIT(physical_vdbox - 1) & vdbox_mask);
> else if (GRAPHICS_VER(i915) == 11)
> @@ -512,7 +520,7 @@ static intel_engine_mask_t init_engine_mask(struct
> intel_gt *gt)
> struct intel_uncore *uncore = gt->uncore;
> unsigned int logical_vdbox = 0;
> unsigned int i;
> - u32 media_fuse;
> + u32 media_fuse, fuse1;
> u16 vdbox_mask;
> u16 vebox_mask;
>
> @@ -534,6 +542,13 @@ static intel_engine_mask_t init_engine_mask(struct
> intel_gt *gt)
> vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> GEN11_GT_VEBOX_DISABLE_SHIFT;
>
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
> + fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
> + gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
> + } else {
> + gt->info.sfc_mask = ~0;
> + }
> +
> for (i = 0; i < I915_MAX_VCS; i++) {
> if (!HAS_ENGINE(gt, _VCS(i))) {
> vdbox_mask &= ~BIT(i);
> @@ -546,7 +561,7 @@ static intel_engine_mask_t init_engine_mask(struct
> intel_gt *gt)
> continue;
> }
>
> - if (gen11_vdbox_has_sfc(i915, i, logical_vdbox, vdbox_mask))
> + if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
> gt->info.vdbox_sfc_access |= BIT(i);
> logical_vdbox++;
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 6fdcde64c180..4492de7f79fd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -184,6 +184,9 @@ struct intel_gt {
>
> u8 num_engines;
>
> + /* General presence of SFC units */
> + u8 sfc_mask;
> +
> /* Media engine access to SFC per instance */
> u8 vdbox_sfc_access;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
>
Re: [Intel-gfx] [PATCH v2 10/13] drm/msm/dpu: Remove encoder->enable() hack
On Thu, Sep 16, 2021 at 08:53:50PM -0700, Stephen Boyd wrote: > Quoting Sean Paul (2021-09-15 13:38:29) > > From: Sean Paul > > > > encoder->commit() was being misused because there were some global > > resources which needed to be tweaked in encoder->enable() which were not > > accessible in dpu_encoder.c. That is no longer true and the redirect > > serves no purpose any longer. So remove the indirection. > > When did it become false? Just curious when this became obsolete. In commit commit cd6d923167b1bf3e051f9d90fa129456d78ef06e Author: Rob Clark Date: Thu Aug 29 09:45:17 2019 -0700 drm/msm/dpu: async commit support There was a call to dpu_crtc_commit_kickoff() which was removed from dpu_kms_encoder_enable(). That was the bit which required the back-and-forth between ->enable() and ->commit(). > > > > > Signed-off-by: Sean Paul > > Link: > > https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-11-s...@poorly.run > > #v1 > > > > Changes in v2: > > -None > > --- > > Reviewed-by: Stephen Boyd > Tested-by: Stephen Boyd Thanks! -- Sean Paul, Software Engineer, Google / Chromium OS
[Intel-gfx] [PATCH] drm/i915: Make wa list per-gt
From: Venkata Sandeep Dhanalakota
Support for multiple GT's within a single i915 device will be arriving
soon. Since each GT may have its own fusing and require different
workarounds, we need to make the GT workaround functions and multicast
steering setup per-gt.
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Signed-off-by: Venkata Sandeep Dhanalakota
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c| 3 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 143 +-
drivers/gpu/drm/i915/gt/intel_workarounds.h | 2 +-
.../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 -
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/i915_gem.c | 2 -
8 files changed, 81 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 55e87aff51d2..449ff6e83543 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -660,6 +660,8 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
return err;
+ intel_gt_init_workarounds(gt);
+
/*
* This is just a security blanket to placate dragons.
* On some systems, we very sporadically observe that the first TLBs
@@ -767,6 +769,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
if (vm) /* FIXME being called twice on error paths :( */
i915_vm_put(vm);
+ intel_wa_list_free(>wa_list);
intel_gt_pm_fini(gt);
intel_gt_fini_scratch(gt);
intel_gt_fini_buffer_pool(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 6fdcde64c180..ce127cae9e49 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -72,6 +72,8 @@ struct intel_gt {
struct intel_uc uc;
+ struct i915_wa_list wa_list;
+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index c314d4917b6b..1f0a54b383d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -804,7 +804,7 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
}
static void
-gen4_gt_workarounds_init(struct drm_i915_private *i915,
+gen4_gt_workarounds_init(struct intel_gt *gt,
struct i915_wa_list *wal)
{
/* WaDisable_RenderCache_OperationalFlush:gen4,ilk */
@@ -812,29 +812,29 @@ gen4_gt_workarounds_init(struct drm_i915_private *i915,
}
static void
-g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
+g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
{
- gen4_gt_workarounds_init(i915, wal);
+ gen4_gt_workarounds_init(gt, wal);
/* WaDisableRenderCachePipelinedFlush:g4x,ilk */
wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);
}
static void
-ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
+ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
{
- g4x_gt_workarounds_init(i915, wal);
+ g4x_gt_workarounds_init(gt, wal);
wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
}
static void
-snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
+snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
{
}
static void
-ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
+ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
{
/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
wa_masked_dis(wal,
@@ -850,7 +850,7 @@ ivb_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
}
static void
-vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
+vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
{
/* WaForceL3Serialization:vlv */
wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
@@ -863,7 +863,7 @@ vlv_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
}
static void
-hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
+hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
{
/* L3 caching of data atomics doesn't work -- disable it. */
wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
@@ -878,15 +878,15 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
}
static void
Re: [Intel-gfx] [PATCH 9/9] drm/i915: Add privacy-screen support
On Fri, Sep 17, 2021 at 06:42:04PM +0200, Hans de Goede wrote:
> Hi,
>
> On 9/17/21 6:25 PM, Ville Syrjälä wrote:
> > On Fri, Sep 17, 2021 at 04:37:14PM +0200, Hans de Goede wrote:
> >> Hi,
> >>
> >> On 9/16/21 3:45 PM, Ville Syrjälä wrote:
> >>> On Mon, Sep 06, 2021 at 09:35:19AM +0200, Hans de Goede wrote:
> Add support for eDP panels with a built-in privacy screen using the
> new drm_privacy_screen class.
>
> One thing which stands out here is the addition of these 2 lines to
> intel_atomic_commit_tail:
>
> for_each_new_connector_in_state(>base, connector, ...
> drm_connector_update_privacy_screen(connector, state);
>
> It may seem more logical to instead take care of updating the
> privacy-screen state by marking the crtc as needing a modeset and then
> do this in both the encoder update_pipe (for fast-sets) and enable
> (for full modesets) callbacks. But ATM these callbacks only get passed
> the new connector_state and these callbacks are all called after
> drm_atomic_helper_swap_state() at which point there is no way to get
> the old state from the new state.
> >>>
> >>> Pretty sure the full atomic state is plumbed all the way
> >>> down these days.
> >>
> >> Including the old state? AFAICT the old-state is being thrown away
> >> from drm_atomic_helper_swap_state(),
> >
> > No. That's just when those annoying foo_state->state pointers get
> > clobbered. We've been moving away from using those and just
> > plumbing the entire atomic state everywhere.
> >
> > Nothing actually gets freed until the whole drm_atomic_state gets
> > nuked after the commit is done.
> >
> >> so if we do this in a different
> >> place then we don't have access to the old-state.
> >>
> >>
> >>>
>
> Without access to the old state, we do not know if the sw_state of
> the privacy-screen has changes so we would need to call
> drm_privacy_screen_set_sw_state() unconditionally. This is undesirable
> since all current known privacy-screen providers use ACPI calls which
> are somewhat expensive to make.
> >>>
> >>> I doubt anyone is going to care about a bit of overhead for a modeset.
> >>
> >> But this is not a modeset, this is more like changing the backlight
> >> brightness,
> >> atm the code does not set the needs_modeset when only the privacy-screen
> >> sw-state has changed.
> >>
> >> Also in my experience the firmware (AML) code which we end up calling
> >> for this is not the highest quality code, often it has interesting
> >> issues / unhandled corner cases. So in my experience with ACPI we
> >> really should try to avoid these calls unless we absolutely must make them,
> >> but I guess not making unnecessary calls is something which could be
> >> handled
> >> inside the actual privacy-screen driver instead.
> >>
> >>> The usual rule is that a modeset doesn't skip anything. That way we
> >>> can be 100% sure we remeber to update everythinbg. For fastsets I guess
> >>> one could argue skipping it if not needed, but not sure even that is
> >>> warranted.
> >>
> >> Right, but again this is not a full modeset.
> >
> > In general fastset is is just an optimized modeset. Userspace asked
> > for a modeset, but we noticed it doesn't need it. I don't think
> > there is a particular expectation that it's super fast.
> >
> > But if this is really annoyingly slow in some actual usecase
>
> Yeah these acpi-calls might take like a 100 ms easily, so
> we really want to avoid it if it is not necessary.
>
> > then
> > one way to avoid that need to compare against the old state is just
> > introduce another foo_changed flag.
>
> Ok, so I have the feeling that you have an idea of how you think this
> should be done / how this code should look instead of what I have
> currently.
>
> Can you perhaps provide a rough sketch / description of how you
> think this should be done (instead of the current implementation) ?
>
> Should I do the update from the the encoder update_pipe (for fast-sets)
> and enable (for full modesets) callbacks instead as I mention in
> the commit message ?
>
> And since I still only want to do the call if there is an actual
> change, where could I best do the old / new sw_state change cmp to
> set the new foo_changed flag?
>
I guess it could be just something like this:
intel_digital_connector_duplicate_state()
{
foo_changed = false;
}
intel_digital_connector_atomic_check()
{
if (old_foo != new_foo) {
mode_changed = true;
foo_changed = true;
}
}
update_pipe()
{
if (foo_changed)
update_foo();
}
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v2 3/5] drm/i915/display: Workaround cursor left overs with PSR2 selective fetch enabled
On Fri, 2021-09-17 at 16:04 +0300, Ville Syrjälä wrote: > On Thu, Sep 16, 2021 at 05:09:08PM +, Souza, Jose wrote: > > On Thu, 2021-09-16 at 16:17 +0300, Ville Syrjälä wrote: > > > On Wed, Sep 15, 2021 at 06:18:35PM +, Souza, Jose wrote: > > > > On Wed, 2021-09-15 at 17:58 +0300, Ville Syrjälä wrote: > > > > > On Tue, Sep 14, 2021 at 02:25:05PM -0700, José Roberto de Souza wrote: > > > > > > Not sure why but when moving the cursor fast it causes some > > > > > > artifacts > > > > > > of the cursor to be left in the cursor path, adding some pixels > > > > > > above > > > > > > the cursor to the damaged area fixes the issue, so leaving this as a > > > > > > workaround until proper fix is found. > > > > > > > > > > Have you tried warping the cursor clear across the screen while > > > > > a partial update is already pending? I think it will go badly. > > > > > > > > You mean move the cursor for example from 0x0 to 500x500 in one frame? > > > > It will mark as damaged the previous area and the new one. > > > > > > Legacy cursor updates bypass all that stuff so you're not going to > > > updating the sel fetch area for the other planes. > > > > > > > > > > > > > > > > > In fact I'm thinking the mailbox style legacy cursor updates are just > > > > > fundementally incompatible with partial updates since the cursor > > > > > can move outside of the already committed update region any time. > > > > > Ie. I suspect while the cursor is visible we simply can't do partial > > > > > updates. > > > > > > > > Probably I did not understand what you want to say, but each cursor > > > > update will be in one frame, updating the necessary area. > > > > > > The legacy cursor uses mailbox updates so there is no 1:1 relationship > > > between actual scanned out frames and cursor ioctl calls. You can > > > have umpteen thousand cursor updates per frame. > > > > Not if intel_legacy_cursor_update() is changed to go to the slow path and > > do one atomic commit for each move. > > https://patchwork.freedesktop.org/patch/453192/?series=94522=1 > > That's not going to fly. The whole reason for the legacy cursor thing is > that X likes to do thousands of cursor updates per frame. From user experience perspective there is no issues in converting to atomic commit, those 3 videos that I shared with you have this conversion. > > > > > I believe compositors will do a single atomic commit updating cursor and > > all the other planes into a single commit. > > No. X obviously doesn't do that. And IIRC chromeos also uses the > legacy cursor ioctl for the cursor despite using atomic commits for > everything else. >
Re: [Intel-gfx] [PATCH v3 00/13] drm/i915/dp: dp 2.0 enabling prep work
On Fri, Sep 17, 2021 at 03:54:23PM +0300, Jani Nikula wrote: > On Thu, 09 Sep 2021, Jani Nikula wrote: > > v3 of https://patchwork.freedesktop.org/series/93800/ with minor tweaks > > and the already merged patches obviously dropped. > > > > Jani Nikula (13): > > drm/dp: add DP 2.0 UHBR link rate and bw code conversions > > drm/dp: use more of the extended receiver cap > > drm/dp: add LTTPR DP 2.0 DPCD addresses > > drm/dp: add helper for extracting adjust 128b/132b TX FFE preset > > Maarten, Maxime, Thomas, can I get an ack to merge these four patches > via drm-intel please, or would you prefer a topic branch instead? Yes, you can merge them through drm-intel Maxime signature.asc Description: PGP signature
[Intel-gfx] ✗ Fi.CI.BAT: failure for Check SFC fusing on Xe_HP
== Series Details ==
Series: Check SFC fusing on Xe_HP
URL : https://patchwork.freedesktop.org/series/94808/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10604 -> Patchwork_21085
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_21085 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21085, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21085/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21085:
### IGT changes ###
Possible regressions
* igt@gem_exec_parallel@engines@fds:
- fi-tgl-u2: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-tgl-u2/igt@gem_exec_parallel@engi...@fds.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21085/fi-tgl-u2/igt@gem_exec_parallel@engi...@fds.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload:
- {fi-ehl-2}: [INCOMPLETE][3] ([i915#4136]) -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-ehl-2/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21085/fi-ehl-2/igt@i915_module_l...@reload.html
Known issues
Here are the changes found in Patchwork_21085 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-sdma:
- fi-cfl-8109u: NOTRUN -> [SKIP][5] ([fdo#109271]) +17 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21085/fi-cfl-8109u/igt@amdgpu/amd_ba...@cs-sdma.html
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][6] ([fdo#109315]) +17 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21085/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html
* igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-cfl-8700k: NOTRUN -> [SKIP][7] ([fdo#109271]) +17 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21085/fi-cfl-8700k/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html
* igt@core_hotunplug@unbind-rebind:
- fi-cfl-guc: [PASS][8] -> [INCOMPLETE][9] ([i915#4130])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21085/fi-cfl-guc/igt@core_hotunp...@unbind-rebind.html
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][10] ([i915#4130])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21085/fi-tgl-1115g4/igt@core_hotunp...@unbind-rebind.html
- fi-rkl-11600: [PASS][11] -> [INCOMPLETE][12] ([i915#4130])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-rkl-11600/igt@core_hotunp...@unbind-rebind.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21085/fi-rkl-11600/igt@core_hotunp...@unbind-rebind.html
- fi-skl-guc: [PASS][13] -> [INCOMPLETE][14] ([i915#4130])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-skl-guc/igt@core_hotunp...@unbind-rebind.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21085/fi-skl-guc/igt@core_hotunp...@unbind-rebind.html
- fi-kbl-7567u: [PASS][15] -> [INCOMPLETE][16] ([i915#4130])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-kbl-7567u/igt@core_hotunp...@unbind-rebind.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21085/fi-kbl-7567u/igt@core_hotunp...@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][17] ([i915#2190])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21085/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html
* igt@i915_module_load@reload:
- fi-skl-6700k2: NOTRUN -> [INCOMPLETE][18] ([i915#4130])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21085/fi-skl-6700k2/igt@i915_module_l...@reload.html
- fi-kbl-guc: [PASS][19] -> [INCOMPLETE][20] ([i915#4130] /
[i915#4139])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/fi-kbl-guc/igt@i915_module_l...@reload.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21085/fi-kbl-guc/igt@i915_module_l...@reload.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][21] ([i915#1155])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21085/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][22]
Re: [Intel-gfx] [PATCH v2 0/9] Move vfio_ccw to the new mdev API
On Fri, Sep 17, 2021 at 01:59:16PM +0200, Cornelia Huck wrote:
> > ret = cio_cancel_halt_clear(sch, );
> > -
> > if (ret == -EIO) {
> > pr_err("vfio_ccw: could not quiesce subchannel
> > 0.%x.%04x!\n",
> >sch->schid.ssid, sch->schid.sch_no);
> > - break;
> > + return ret;
>
> Looking at this, I wonder why we had special-cased -EIO -- for -ENODEV
> we should be done as well, as then the device is dead and we do not need
> to disable it.
cio_cancel_halt_clear() should probably succeed in that case.
> > @@ -413,13 +403,28 @@ static void fsm_close(struct vfio_ccw_private
> > *private,
> > spin_unlock_irq(sch->lock);
> >
> > if (ret == -EBUSY)
> > - wait_for_completion_timeout(, 3*HZ);
> > + wait_for_completion_timeout(, 3 * HZ);
> >
> > private->completion = NULL;
> > flush_workqueue(vfio_ccw_work_q);
> > spin_lock_irq(sch->lock);
> > ret = cio_disable_subchannel(sch);
> > } while (ret == -EBUSY);
> > + return ret;
> > +}
> > +
> > +static void fsm_close(struct vfio_ccw_private *private,
> > + enum vfio_ccw_event event)
> > +{
> > + struct subchannel *sch = private->sch;
> > + int ret;
> > +
> > + spin_lock_irq(sch->lock);
> > + if (!sch->schib.pmcw.ena)
> > + goto err_unlock;
> > + ret = cio_disable_subchannel(sch);
>
> cio_disable_subchannel() should be happy to disable an already disabled
> subchannel, so I guess we can just walk through this and end up in
> CLOSED state... unless entering with !ena actually indicates that we
> messed up somewhere else in the state machine. I still need to find time
> to read the patches.
I don't know, I looked at that ena stuff for a bit and couldn't guess
what it is trying to do.
Arguably the channel should not be ripped away from vfio while the FSM
is in the open states, so I'm not sure what a lot of this is for.
Jason
Re: [Intel-gfx] [PATCH 9/9] drm/i915: Add privacy-screen support
Hi,
On 9/17/21 6:25 PM, Ville Syrjälä wrote:
> On Fri, Sep 17, 2021 at 04:37:14PM +0200, Hans de Goede wrote:
>> Hi,
>>
>> On 9/16/21 3:45 PM, Ville Syrjälä wrote:
>>> On Mon, Sep 06, 2021 at 09:35:19AM +0200, Hans de Goede wrote:
Add support for eDP panels with a built-in privacy screen using the
new drm_privacy_screen class.
One thing which stands out here is the addition of these 2 lines to
intel_atomic_commit_tail:
for_each_new_connector_in_state(>base, connector, ...
drm_connector_update_privacy_screen(connector, state);
It may seem more logical to instead take care of updating the
privacy-screen state by marking the crtc as needing a modeset and then
do this in both the encoder update_pipe (for fast-sets) and enable
(for full modesets) callbacks. But ATM these callbacks only get passed
the new connector_state and these callbacks are all called after
drm_atomic_helper_swap_state() at which point there is no way to get
the old state from the new state.
>>>
>>> Pretty sure the full atomic state is plumbed all the way
>>> down these days.
>>
>> Including the old state? AFAICT the old-state is being thrown away
>> from drm_atomic_helper_swap_state(),
>
> No. That's just when those annoying foo_state->state pointers get
> clobbered. We've been moving away from using those and just
> plumbing the entire atomic state everywhere.
>
> Nothing actually gets freed until the whole drm_atomic_state gets
> nuked after the commit is done.
>
>> so if we do this in a different
>> place then we don't have access to the old-state.
>>
>>
>>>
Without access to the old state, we do not know if the sw_state of
the privacy-screen has changes so we would need to call
drm_privacy_screen_set_sw_state() unconditionally. This is undesirable
since all current known privacy-screen providers use ACPI calls which
are somewhat expensive to make.
>>>
>>> I doubt anyone is going to care about a bit of overhead for a modeset.
>>
>> But this is not a modeset, this is more like changing the backlight
>> brightness,
>> atm the code does not set the needs_modeset when only the privacy-screen
>> sw-state has changed.
>>
>> Also in my experience the firmware (AML) code which we end up calling
>> for this is not the highest quality code, often it has interesting
>> issues / unhandled corner cases. So in my experience with ACPI we
>> really should try to avoid these calls unless we absolutely must make them,
>> but I guess not making unnecessary calls is something which could be handled
>> inside the actual privacy-screen driver instead.
>>
>>> The usual rule is that a modeset doesn't skip anything. That way we
>>> can be 100% sure we remeber to update everythinbg. For fastsets I guess
>>> one could argue skipping it if not needed, but not sure even that is
>>> warranted.
>>
>> Right, but again this is not a full modeset.
>
> In general fastset is is just an optimized modeset. Userspace asked
> for a modeset, but we noticed it doesn't need it. I don't think
> there is a particular expectation that it's super fast.
>
> But if this is really annoyingly slow in some actual usecase
Yeah these acpi-calls might take like a 100 ms easily, so
we really want to avoid it if it is not necessary.
> then
> one way to avoid that need to compare against the old state is just
> introduce another foo_changed flag.
Ok, so I have the feeling that you have an idea of how you think this
should be done / how this code should look instead of what I have
currently.
Can you perhaps provide a rough sketch / description of how you
think this should be done (instead of the current implementation) ?
Should I do the update from the the encoder update_pipe (for fast-sets)
and enable (for full modesets) callbacks instead as I mention in
the commit message ?
And since I still only want to do the call if there is an actual
change, where could I best do the old / new sw_state change cmp to
set the new foo_changed flag?
>
>>
>>>
>>> The current code you have in there is cettainly 110% dodgy. Since the
>>> sw_state is stored in the connector state I presume it's at least
>>> trying to be an atomic property, which means you shouldn't go poking
>>> at it after the swap_state ever.
>>
>> It is not being poked, it is only being read, also this is happening
>> before swap_state.
>>
>> Note I'm open for suggestions to handle this differently,
>> including changing the drm_connector_update_privacy_screen()
>> helper which currently relies on being passed the state before swap_state
>> is called:
>>
>> void drm_connector_update_privacy_screen(struct drm_connector *connector,
>> struct drm_atomic_state *state)
>> {
>> struct drm_connector_state *new_connector_state, *old_connector_state;
>> int ret;
>>
>> if (!connector->privacy_screen)
>> return;
>>
>> new_connector_state =
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Check SFC fusing on Xe_HP
== Series Details == Series: Check SFC fusing on Xe_HP URL : https://patchwork.freedesktop.org/series/94808/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen8_write32' - different lock contexts for
Re: [Intel-gfx] [PATCH 9/9] drm/i915: Add privacy-screen support
On Fri, Sep 17, 2021 at 04:37:14PM +0200, Hans de Goede wrote:
> Hi,
>
> On 9/16/21 3:45 PM, Ville Syrjälä wrote:
> > On Mon, Sep 06, 2021 at 09:35:19AM +0200, Hans de Goede wrote:
> >> Add support for eDP panels with a built-in privacy screen using the
> >> new drm_privacy_screen class.
> >>
> >> One thing which stands out here is the addition of these 2 lines to
> >> intel_atomic_commit_tail:
> >>
> >>for_each_new_connector_in_state(>base, connector, ...
> >>drm_connector_update_privacy_screen(connector, state);
> >>
> >> It may seem more logical to instead take care of updating the
> >> privacy-screen state by marking the crtc as needing a modeset and then
> >> do this in both the encoder update_pipe (for fast-sets) and enable
> >> (for full modesets) callbacks. But ATM these callbacks only get passed
> >> the new connector_state and these callbacks are all called after
> >> drm_atomic_helper_swap_state() at which point there is no way to get
> >> the old state from the new state.
> >
> > Pretty sure the full atomic state is plumbed all the way
> > down these days.
>
> Including the old state? AFAICT the old-state is being thrown away
> from drm_atomic_helper_swap_state(),
No. That's just when those annoying foo_state->state pointers get
clobbered. We've been moving away from using those and just
plumbing the entire atomic state everywhere.
Nothing actually gets freed until the whole drm_atomic_state gets
nuked after the commit is done.
> so if we do this in a different
> place then we don't have access to the old-state.
>
>
> >
> >>
> >> Without access to the old state, we do not know if the sw_state of
> >> the privacy-screen has changes so we would need to call
> >> drm_privacy_screen_set_sw_state() unconditionally. This is undesirable
> >> since all current known privacy-screen providers use ACPI calls which
> >> are somewhat expensive to make.
> >
> > I doubt anyone is going to care about a bit of overhead for a modeset.
>
> But this is not a modeset, this is more like changing the backlight
> brightness,
> atm the code does not set the needs_modeset when only the privacy-screen
> sw-state has changed.
>
> Also in my experience the firmware (AML) code which we end up calling
> for this is not the highest quality code, often it has interesting
> issues / unhandled corner cases. So in my experience with ACPI we
> really should try to avoid these calls unless we absolutely must make them,
> but I guess not making unnecessary calls is something which could be handled
> inside the actual privacy-screen driver instead.
>
> > The usual rule is that a modeset doesn't skip anything. That way we
> > can be 100% sure we remeber to update everythinbg. For fastsets I guess
> > one could argue skipping it if not needed, but not sure even that is
> > warranted.
>
> Right, but again this is not a full modeset.
In general fastset is is just an optimized modeset. Userspace asked
for a modeset, but we noticed it doesn't need it. I don't think
there is a particular expectation that it's super fast.
But if this is really annoyingly slow in some actual usecase then
one way to avoid that need to compare against the old state is just
introduce another foo_changed flag.
>
> >
> > The current code you have in there is cettainly 110% dodgy. Since the
> > sw_state is stored in the connector state I presume it's at least
> > trying to be an atomic property, which means you shouldn't go poking
> > at it after the swap_state ever.
>
> It is not being poked, it is only being read, also this is happening
> before swap_state.
>
> Note I'm open for suggestions to handle this differently,
> including changing the drm_connector_update_privacy_screen()
> helper which currently relies on being passed the state before swap_state
> is called:
>
> void drm_connector_update_privacy_screen(struct drm_connector *connector,
>struct drm_atomic_state *state)
> {
> struct drm_connector_state *new_connector_state, *old_connector_state;
> int ret;
>
> if (!connector->privacy_screen)
> return;
>
> new_connector_state = drm_atomic_get_new_connector_state(state,
> connector);
> old_connector_state = drm_atomic_get_old_connector_state(state,
> connector);
>
> if (new_connector_state->privacy_screen_sw_state ==
> old_connector_state->privacy_screen_sw_state)
> return;
>
> ret = drm_privacy_screen_set_sw_state(connector->privacy_screen,
> new_connector_state->privacy_screen_sw_state);
> if (ret) {
> drm_err(connector->dev, "Error updating privacy-screen
> sw_state\n");
> return;
> }
>
> So if you have any suggestions how to do this differently, please let me know
> and I will take a shot at implementing those suggestions.
You cut the code too soon. Just after this you call the other
update_privacy_screen() thing which
[Intel-gfx] [PATCH 0/2] Check SFC fusing on Xe_HP
Xe_HP adds some new fuse bits to indicate whether an SFC unit is fused off. We should utilize these when initializing VD/VE SFC access and also when capturing/dumping SFC_DONE for the error state. Matt Roper (2): drm/i915/xehp: Check new fuse bits for SFC availability drm/i915: Check SFC fusing before recording/dumping SFC_DONE drivers/gpu/drm/i915/gt/intel_engine_cs.c | 25 ++- drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++ drivers/gpu/drm/i915/gt/intel_sseu.c | 5 ++--- drivers/gpu/drm/i915/i915_gpu_error.c | 6 -- drivers/gpu/drm/i915/i915_reg.h | 4 ++-- 5 files changed, 31 insertions(+), 12 deletions(-) -- 2.33.0
[Intel-gfx] [PATCH 2/2] drm/i915: Check SFC fusing before recording/dumping SFC_DONE
On Xe_HP and beyond the SFC unit may be fused off, even if the corresponding media engines are present. Check the SFC-specific fusing before trying to dump the SFC_DONE instances. Cc: José Roberto de Souza Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/i915_gpu_error.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index b9f66dbd46bb..2a2d7643b551 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -753,7 +753,8 @@ static void err_print_gt(struct drm_i915_error_state_buf *m, * only exists if the corresponding VCS engine is * present. */ - if (!HAS_ENGINE(gt->_gt, _VCS(i * 2))) + if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || + !HAS_ENGINE(gt->_gt, _VCS(i * 2))) continue; err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, @@ -1632,7 +1633,8 @@ static void gt_record_regs(struct intel_gt_coredump *gt) * only exists if the corresponding VCS engine is * present. */ - if (!HAS_ENGINE(gt->_gt, _VCS(i * 2))) + if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || + !HAS_ENGINE(gt->_gt, _VCS(i * 2))) continue; gt->sfc_done[i] = -- 2.33.0
[Intel-gfx] [PATCH 1/2] drm/i915/xehp: Check new fuse bits for SFC availability
Xe_HP adds some new bits to the FUSE1 register to let us know whether a
given SFC unit is present. We should take this into account while
initializing SFC availability to our VCS and VECS engines.
While we're at it, update the FUSE1 register definition to use
REG_GENMASK / REG_FIELD_GET notation.
Note that, the bspec confusingly names the fuse bits "disable" despite
the register reflecting the *enable* status of the SFC units. The
original architecture documents which the bspec is based on do properly
name this field "SFC_ENABLE."
Bspec: 52543
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 25 ++-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
drivers/gpu/drm/i915/gt/intel_sseu.c | 5 ++---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
4 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 332efea696a5..06dfe7f38953 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -398,7 +398,8 @@ static void __setup_engine_capabilities(struct
intel_engine_cs *engine)
engine->uabi_capabilities |=
I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
} else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
- if (GRAPHICS_VER(i915) >= 9)
+ if (GRAPHICS_VER(i915) >= 9 &&
+ engine->gt->info.sfc_mask & BIT(engine->instance))
engine->uabi_capabilities |=
I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
}
@@ -474,18 +475,25 @@ void intel_engines_free(struct intel_gt *gt)
}
static
-bool gen11_vdbox_has_sfc(struct drm_i915_private *i915,
+bool gen11_vdbox_has_sfc(struct intel_gt *gt,
unsigned int physical_vdbox,
unsigned int logical_vdbox, u16 vdbox_mask)
{
+ struct drm_i915_private *i915 = gt->i915;
+
/*
* In Gen11, only even numbered logical VDBOXes are hooked
* up to an SFC (Scaler & Format Converter) unit.
* In Gen12, Even numbered physical instance always are connected
* to an SFC. Odd numbered physical instances have SFC only if
* previous even instance is fused off.
+*
+* Starting with Xe_HP, there's also a dedicated SFC_ENABLE field
+* in the fuse register that tells us whether a specific SFC is present.
*/
- if (GRAPHICS_VER(i915) == 12)
+ if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
+ return false;
+ else if (GRAPHICS_VER(i915) == 12)
return (physical_vdbox % 2 == 0) ||
!(BIT(physical_vdbox - 1) & vdbox_mask);
else if (GRAPHICS_VER(i915) == 11)
@@ -512,7 +520,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt
*gt)
struct intel_uncore *uncore = gt->uncore;
unsigned int logical_vdbox = 0;
unsigned int i;
- u32 media_fuse;
+ u32 media_fuse, fuse1;
u16 vdbox_mask;
u16 vebox_mask;
@@ -534,6 +542,13 @@ static intel_engine_mask_t init_engine_mask(struct
intel_gt *gt)
vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
GEN11_GT_VEBOX_DISABLE_SHIFT;
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
+ gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
+ } else {
+ gt->info.sfc_mask = ~0;
+ }
+
for (i = 0; i < I915_MAX_VCS; i++) {
if (!HAS_ENGINE(gt, _VCS(i))) {
vdbox_mask &= ~BIT(i);
@@ -546,7 +561,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt
*gt)
continue;
}
- if (gen11_vdbox_has_sfc(i915, i, logical_vdbox, vdbox_mask))
+ if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
gt->info.vdbox_sfc_access |= BIT(i);
logical_vdbox++;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 6fdcde64c180..4492de7f79fd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -184,6 +184,9 @@ struct intel_gt {
u8 num_engines;
+ /* General presence of SFC units */
+ u8 sfc_mask;
+
/* Media engine access to SFC per instance */
u8 vdbox_sfc_access;
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index b0e09b58005e..bdf09051b8a0 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -514,10 +514,9 @@ static void
[Intel-gfx] [PATCH 1/2] drm/i915/xehp: Check new fuse bits for SFC availability
Xe_HP adds some new bits to the FUSE1 register to let us know whether a
given SFC unit is present. We should take this into account while
initializing SFC availability to our VCS and VECS engines.
While we're at it, update the FUSE1 register definition to use
REG_GENMASK / REG_FIELD_GET notation.
Note that, the bspec confusingly names the fuse bits "disable" despite
the register reflecting the *enable* status of the SFC units. The
original architecture documents which the bspec is based on do properly
name this field "SFC_ENABLE."
Bspec: 52543
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 25 ++-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
drivers/gpu/drm/i915/gt/intel_sseu.c | 5 ++---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
4 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 332efea696a5..06dfe7f38953 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -398,7 +398,8 @@ static void __setup_engine_capabilities(struct
intel_engine_cs *engine)
engine->uabi_capabilities |=
I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
} else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
- if (GRAPHICS_VER(i915) >= 9)
+ if (GRAPHICS_VER(i915) >= 9 &&
+ engine->gt->info.sfc_mask & BIT(engine->instance))
engine->uabi_capabilities |=
I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
}
@@ -474,18 +475,25 @@ void intel_engines_free(struct intel_gt *gt)
}
static
-bool gen11_vdbox_has_sfc(struct drm_i915_private *i915,
+bool gen11_vdbox_has_sfc(struct intel_gt *gt,
unsigned int physical_vdbox,
unsigned int logical_vdbox, u16 vdbox_mask)
{
+ struct drm_i915_private *i915 = gt->i915;
+
/*
* In Gen11, only even numbered logical VDBOXes are hooked
* up to an SFC (Scaler & Format Converter) unit.
* In Gen12, Even numbered physical instance always are connected
* to an SFC. Odd numbered physical instances have SFC only if
* previous even instance is fused off.
+*
+* Starting with Xe_HP, there's also a dedicated SFC_ENABLE field
+* in the fuse register that tells us whether a specific SFC is present.
*/
- if (GRAPHICS_VER(i915) == 12)
+ if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
+ return false;
+ else if (GRAPHICS_VER(i915) == 12)
return (physical_vdbox % 2 == 0) ||
!(BIT(physical_vdbox - 1) & vdbox_mask);
else if (GRAPHICS_VER(i915) == 11)
@@ -512,7 +520,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt
*gt)
struct intel_uncore *uncore = gt->uncore;
unsigned int logical_vdbox = 0;
unsigned int i;
- u32 media_fuse;
+ u32 media_fuse, fuse1;
u16 vdbox_mask;
u16 vebox_mask;
@@ -534,6 +542,13 @@ static intel_engine_mask_t init_engine_mask(struct
intel_gt *gt)
vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
GEN11_GT_VEBOX_DISABLE_SHIFT;
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
+ gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
+ } else {
+ gt->info.sfc_mask = ~0;
+ }
+
for (i = 0; i < I915_MAX_VCS; i++) {
if (!HAS_ENGINE(gt, _VCS(i))) {
vdbox_mask &= ~BIT(i);
@@ -546,7 +561,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt
*gt)
continue;
}
- if (gen11_vdbox_has_sfc(i915, i, logical_vdbox, vdbox_mask))
+ if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
gt->info.vdbox_sfc_access |= BIT(i);
logical_vdbox++;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 6fdcde64c180..4492de7f79fd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -184,6 +184,9 @@ struct intel_gt {
u8 num_engines;
+ /* General presence of SFC units */
+ u8 sfc_mask;
+
/* Media engine access to SFC per instance */
u8 vdbox_sfc_access;
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index b0e09b58005e..bdf09051b8a0 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -514,10 +514,9 @@ static void
[Intel-gfx] [PATCH 2/2] drm/i915: Check SFC fusing before recording/dumping SFC_DONE
On Xe_HP and beyond the SFC unit may be fused off, even if the corresponding media engines are present. Check the SFC-specific fusing before trying to dump the SFC_DONE instances. Cc: José Roberto de Souza Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/i915_gpu_error.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index b9f66dbd46bb..2a2d7643b551 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -753,7 +753,8 @@ static void err_print_gt(struct drm_i915_error_state_buf *m, * only exists if the corresponding VCS engine is * present. */ - if (!HAS_ENGINE(gt->_gt, _VCS(i * 2))) + if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || + !HAS_ENGINE(gt->_gt, _VCS(i * 2))) continue; err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, @@ -1632,7 +1633,8 @@ static void gt_record_regs(struct intel_gt_coredump *gt) * only exists if the corresponding VCS engine is * present. */ - if (!HAS_ENGINE(gt->_gt, _VCS(i * 2))) + if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 || + !HAS_ENGINE(gt->_gt, _VCS(i * 2))) continue; gt->sfc_done[i] = -- 2.33.0
[Intel-gfx] [PATCH 0/2] Check SFC fusing on Xe_HP
Xe_HP adds some new fuse bits to indicate whether an SFC unit is fused off. We should utilize these when initializing VD/VE SFC access and also when capturing/dumping SFC_DONE for the error state. Matt Roper (2): drm/i915/xehp: Check new fuse bits for SFC availability drm/i915: Check SFC fusing before recording/dumping SFC_DONE drivers/gpu/drm/i915/gt/intel_engine_cs.c | 25 ++- drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++ drivers/gpu/drm/i915/gt/intel_sseu.c | 5 ++--- drivers/gpu/drm/i915/i915_gpu_error.c | 6 -- drivers/gpu/drm/i915/i915_reg.h | 4 ++-- 5 files changed, 31 insertions(+), 12 deletions(-) -- 2.33.0
Re: [Intel-gfx] [PATCH 15/15] doc: drm: remove TODO entry regarding DRM_MODSET_LOCK_ALL cleanup
On Thu, Sep 16, 2021 at 11:15:52PM +0200, Fernando Ramos wrote: > The previous commits do exactly what this entry in the TODO file asks > for, thus we can remove it now as it is no longer applicable. Thanks for doing this work! Can we remove drm_modeset_lock_all[_ctx] now? If so, let's queue that up as part of the set. Reviewed-by: Sean Paul > > Signed-off-by: Fernando Ramos > --- > Documentation/gpu/todo.rst| 17 - > Documentation/locking/ww-mutex-design.rst | 2 +- > 2 files changed, 1 insertion(+), 18 deletions(-) > > diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst > index 12e61869939e..6613543955e9 100644 > --- a/Documentation/gpu/todo.rst > +++ b/Documentation/gpu/todo.rst > @@ -353,23 +353,6 @@ converted, except for struct drm_driver.gem_prime_mmap. > > Level: Intermediate > > -Use DRM_MODESET_LOCK_ALL_* helpers instead of boilerplate > -- > - > -For cases where drivers are attempting to grab the modeset locks with a local > -acquire context. Replace the boilerplate code surrounding > -drm_modeset_lock_all_ctx() with DRM_MODESET_LOCK_ALL_BEGIN() and > -DRM_MODESET_LOCK_ALL_END() instead. > - > -This should also be done for all places where drm_modeset_lock_all() is still > -used. > - > -As a reference, take a look at the conversions already completed in drm core. > - > -Contact: Sean Paul, respective driver maintainers > - > -Level: Starter > - > Rename CMA helpers to DMA helpers > - > > diff --git a/Documentation/locking/ww-mutex-design.rst > b/Documentation/locking/ww-mutex-design.rst > index 6a4d7319f8f0..6a8f8beb9ec4 100644 > --- a/Documentation/locking/ww-mutex-design.rst > +++ b/Documentation/locking/ww-mutex-design.rst > @@ -60,7 +60,7 @@ Concepts > Compared to normal mutexes two additional concepts/objects show up in the > lock > interface for w/w mutexes: > > -Acquire context: To ensure eventual forward progress it is important the a > task > +Acquire context: To ensure eventual forward progress it is important that a > task > trying to acquire locks doesn't grab a new reservation id, but keeps the one > it > acquired when starting the lock acquisition. This ticket is stored in the > acquire context. Furthermore the acquire context keeps track of debugging > state > -- > 2.33.0 > -- Sean Paul, Software Engineer, Google / Chromium OS
Re: [Intel-gfx] [PATCH 14/15] drm/amd: cleanup: drm_modeset_lock_all() --> DRM_MODESET_LOCK_ALL_BEGIN()
On Thu, Sep 16, 2021 at 11:15:51PM +0200, Fernando Ramos wrote:
> As requested in Documentation/gpu/todo.rst, replace driver calls to
> drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
> DRM_MODESET_LOCK_ALL_END()
>
> Signed-off-by: Fernando Ramos
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 13 +++--
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 50 +--
> .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 23 +
> 3 files changed, 46 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 7a7316731911..55ecc4aa859f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -40,6 +40,7 @@
> #include
> #include
> #include
> +#include
>
> static void amdgpu_display_flip_callback(struct dma_fence *f,
>struct dma_fence_cb *cb)
> @@ -1543,16 +1544,18 @@ int amdgpu_display_suspend_helper(struct
> amdgpu_device *adev)
> struct drm_crtc *crtc;
> struct drm_connector *connector;
> struct drm_connector_list_iter iter;
> + struct drm_modeset_acquire_ctx ctx;
> int r;
> + int ret;
Relocate ret with r please
>
> /* turn off display hw */
> - drm_modeset_lock_all(dev);
> + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret);
> drm_connector_list_iter_begin(dev, );
> drm_for_each_connector_iter(connector, )
> drm_helper_connector_dpms(connector,
> DRM_MODE_DPMS_OFF);
> drm_connector_list_iter_end();
> - drm_modeset_unlock_all(dev);
> + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
You should check ret here
> /* unpin the front buffers and cursors */
> list_for_each_entry(crtc, >mode_config.crtc_list, head) {
> struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
> @@ -1590,7 +1593,9 @@ int amdgpu_display_resume_helper(struct amdgpu_device
> *adev)
> struct drm_connector *connector;
> struct drm_connector_list_iter iter;
> struct drm_crtc *crtc;
> + struct drm_modeset_acquire_ctx ctx;
> int r;
> + int ret;
Relocate ret with r
>
> /* pin cursors */
> list_for_each_entry(crtc, >mode_config.crtc_list, head) {
> @@ -1612,7 +1617,7 @@ int amdgpu_display_resume_helper(struct amdgpu_device
> *adev)
> drm_helper_resume_force_mode(dev);
>
> /* turn on display hw */
> - drm_modeset_lock_all(dev);
> + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret);
>
> drm_connector_list_iter_begin(dev, );
> drm_for_each_connector_iter(connector, )
> @@ -1620,7 +1625,7 @@ int amdgpu_display_resume_helper(struct amdgpu_device
> *adev)
> DRM_MODE_DPMS_ON);
> drm_connector_list_iter_end();
>
> - drm_modeset_unlock_all(dev);
> + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
>
> return 0;
Return ret
> }
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 9b1fc54555ee..5196c1d26f87 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -80,6 +80,7 @@
> #include
> #include
> #include
> +#include
>
> #if defined(CONFIG_DRM_AMD_DC_DCN)
> #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
> @@ -2621,6 +2622,9 @@ static void handle_hpd_irq(void *param)
> #ifdef CONFIG_DRM_AMD_DC_HDCP
> struct dm_connector_state *dm_con_state =
> to_dm_connector_state(connector->state);
> #endif
> + struct drm_modeset_acquire_ctx ctx;
> + int ret;
> +
>
> if (adev->dm.disable_hpd_irq)
> return;
> @@ -2646,14 +2650,6 @@ static void handle_hpd_irq(void *param)
> if (aconnector->base.force && new_connection_type ==
> dc_connection_none) {
> emulated_link_detect(aconnector->dc_link);
>
> -
> - drm_modeset_lock_all(dev);
> - dm_restore_drm_connector_state(dev, connector);
> - drm_modeset_unlock_all(dev);
> -
> - if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
> - drm_kms_helper_hotplug_event(dev);
> -
> } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
> if (new_connection_type == dc_connection_none &&
> aconnector->dc_link->type == dc_connection_none)
> @@ -2661,13 +2657,18 @@ static void handle_hpd_irq(void *param)
>
> amdgpu_dm_update_connector_after_detect(aconnector);
>
> - drm_modeset_lock_all(dev);
> - dm_restore_drm_connector_state(dev, connector);
> - drm_modeset_unlock_all(dev);
> -
> - if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
> - drm_kms_helper_hotplug_event(dev);
> + } else {
> + goto
Re: [Intel-gfx] [PATCH 13/15] drm/gma500: cleanup: drm_modeset_lock_all() --> DRM_MODESET_LOCK_ALL_BEGIN()
On Thu, Sep 16, 2021 at 11:15:50PM +0200, Fernando Ramos wrote:
> As requested in Documentation/gpu/todo.rst, replace driver calls to
> drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
> DRM_MODESET_LOCK_ALL_END()
>
> Signed-off-by: Fernando Ramos
> ---
> drivers/gpu/drm/gma500/psb_device.c | 14 ++
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/gma500/psb_device.c
> b/drivers/gpu/drm/gma500/psb_device.c
> index 951725a0f7a3..4e27f65a1f16 100644
> --- a/drivers/gpu/drm/gma500/psb_device.c
> +++ b/drivers/gpu/drm/gma500/psb_device.c
> @@ -8,6 +8,7 @@
> #include
>
> #include
> +#include
>
> #include "gma_device.h"
> #include "intel_bios.h"
> @@ -169,8 +170,10 @@ static int psb_save_display_registers(struct drm_device
> *dev)
> {
> struct drm_psb_private *dev_priv = dev->dev_private;
> struct drm_crtc *crtc;
> + struct drm_modeset_acquire_ctx ctx;
> struct gma_connector *connector;
> struct psb_state *regs = _priv->regs.psb;
> + int ret;
>
> /* Display arbitration control + watermarks */
> regs->saveDSPARB = PSB_RVDC32(DSPARB);
> @@ -183,7 +186,7 @@ static int psb_save_display_registers(struct drm_device
> *dev)
> regs->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
>
> /* Save crtc and output state */
> - drm_modeset_lock_all(dev);
> + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret);
> list_for_each_entry(crtc, >mode_config.crtc_list, head) {
> if (drm_helper_crtc_in_use(crtc))
> dev_priv->ops->save_crtc(crtc);
> @@ -193,7 +196,8 @@ static int psb_save_display_registers(struct drm_device
> *dev)
> if (connector->save)
> connector->save(>base);
>
> - drm_modeset_unlock_all(dev);
> + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
> +
> return 0;
Return ret here please
> }
>
> @@ -207,8 +211,10 @@ static int psb_restore_display_registers(struct
> drm_device *dev)
> {
> struct drm_psb_private *dev_priv = dev->dev_private;
> struct drm_crtc *crtc;
> + struct drm_modeset_acquire_ctx ctx;
> struct gma_connector *connector;
> struct psb_state *regs = _priv->regs.psb;
> + int ret;
>
> /* Display arbitration + watermarks */
> PSB_WVDC32(regs->saveDSPARB, DSPARB);
> @@ -223,7 +229,7 @@ static int psb_restore_display_registers(struct
> drm_device *dev)
> /*make sure VGA plane is off. it initializes to on after reset!*/
> PSB_WVDC32(0x8000, VGACNTRL);
>
> - drm_modeset_lock_all(dev);
> + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret);
> list_for_each_entry(crtc, >mode_config.crtc_list, head)
> if (drm_helper_crtc_in_use(crtc))
> dev_priv->ops->restore_crtc(crtc);
> @@ -232,7 +238,7 @@ static int psb_restore_display_registers(struct
> drm_device *dev)
> if (connector->restore)
> connector->restore(>base);
>
> - drm_modeset_unlock_all(dev);
> + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
> return 0;
Here too
> }
>
> --
> 2.33.0
>
--
Sean Paul, Software Engineer, Google / Chromium OS
Re: [Intel-gfx] [PATCH 12/15] drm/i915: cleanup: drm_modeset_lock_all() --> DRM_MODESET_LOCK_ALL_BEGIN()
On Thu, Sep 16, 2021 at 11:15:49PM +0200, Fernando Ramos wrote:
> As requested in Documentation/gpu/todo.rst, replace driver calls to
> drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
> DRM_MODESET_LOCK_ALL_END()
>
> Signed-off-by: Fernando Ramos
> ---
> drivers/gpu/drm/i915/display/intel_audio.c| 12 +++--
> drivers/gpu/drm/i915/display/intel_display.c | 5 ++-
> .../drm/i915/display/intel_display_debugfs.c | 35 ++-
> drivers/gpu/drm/i915/display/intel_overlay.c | 45 +--
> drivers/gpu/drm/i915/display/intel_pipe_crc.c | 5 ++-
> drivers/gpu/drm/i915/i915_drv.c | 12 +++--
> 6 files changed, 67 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index 532237588511..ab6a5a734b95 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -1214,7 +1214,9 @@ static int i915_audio_component_bind(struct device
> *i915_kdev,
> {
> struct i915_audio_component *acomp = data;
> struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
> + struct drm_modeset_acquire_ctx ctx;
> int i;
> + int ret;
Please move up with i
>
> if (drm_WARN_ON(_priv->drm, acomp->base.ops || acomp->base.dev))
> return -EEXIST;
> @@ -1224,14 +1226,14 @@ static int i915_audio_component_bind(struct device
> *i915_kdev,
>DL_FLAG_STATELESS)))
> return -ENOMEM;
>
> - drm_modeset_lock_all(_priv->drm);
> + DRM_MODESET_LOCK_ALL_BEGIN((_priv->drm), ctx, 0, ret);
> acomp->base.ops = _audio_component_ops;
> acomp->base.dev = i915_kdev;
> BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
> for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
> acomp->aud_sample_rate[i] = 0;
> dev_priv->audio_component = acomp;
> - drm_modeset_unlock_all(_priv->drm);
> + DRM_MODESET_LOCK_ALL_END((_priv->drm), ctx, ret);
>
> return 0;
Return ret here
> }
> @@ -1241,12 +1243,14 @@ static void i915_audio_component_unbind(struct device
> *i915_kdev,
> {
> struct i915_audio_component *acomp = data;
> struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
> + struct drm_modeset_acquire_ctx ctx;
> + int ret;
>
> - drm_modeset_lock_all(_priv->drm);
> + DRM_MODESET_LOCK_ALL_BEGIN((_priv->drm), ctx, 0, ret);
> acomp->base.ops = NULL;
> acomp->base.dev = NULL;
> dev_priv->audio_component = NULL;
> - drm_modeset_unlock_all(_priv->drm);
> + DRM_MODESET_LOCK_ALL_END((_priv->drm), ctx, ret);
>
> device_link_remove(hda_kdev, i915_kdev);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 997a16e85c85..dc2e4d89e5aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -12511,6 +12511,7 @@ int intel_modeset_init_noirq(struct drm_i915_private
> *i915)
> int intel_modeset_init_nogem(struct drm_i915_private *i915)
> {
> struct drm_device *dev = >drm;
> + struct drm_modeset_acquire_ctx ctx;
> enum pipe pipe;
> struct intel_crtc *crtc;
> int ret;
> @@ -12562,9 +12563,9 @@ int intel_modeset_init_nogem(struct drm_i915_private
> *i915)
> intel_vga_disable(i915);
> intel_setup_outputs(i915);
>
> - drm_modeset_lock_all(dev);
> + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret);
> intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
> - drm_modeset_unlock_all(dev);
> + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
>
> for_each_intel_crtc(dev, crtc) {
> struct intel_initial_plane_config plane_config = {};
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 8fdacb252bb1..d73af228862e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1057,11 +1057,13 @@ static int i915_display_info(struct seq_file *m, void
> *unused)
> struct intel_crtc *crtc;
> struct drm_connector *connector;
> struct drm_connector_list_iter conn_iter;
> + struct drm_modeset_acquire_ctx ctx;
> intel_wakeref_t wakeref;
> + int ret;
>
> wakeref = intel_runtime_pm_get(_priv->runtime_pm);
>
> - drm_modeset_lock_all(dev);
> + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret);
>
> seq_printf(m, "CRTC info\n");
> seq_printf(m, "-\n");
> @@ -1076,7 +1078,7 @@ static int i915_display_info(struct seq_file *m, void
> *unused)
> intel_connector_info(m, connector);
> drm_connector_list_iter_end(_iter);
>
> - drm_modeset_unlock_all(dev);
> + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
>
>
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/26] dma-buf: add dma_resv_for_each_fence_unlocked v2
== Series Details == Series: series starting with [01/26] dma-buf: add dma_resv_for_each_fence_unlocked v2 URL : https://patchwork.freedesktop.org/series/94805/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10604_full -> Patchwork_21084_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21084_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21084_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21084_full: ### IGT changes ### Possible regressions * igt@i915_pm_rpm@gem-mmap-type@wb: - shard-iclb: NOTRUN -> [FAIL][1] +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21084/shard-iclb6/igt@i915_pm_rpm@gem-mmap-t...@wb.html Known issues Here are the changes found in Patchwork_21084_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_sseu@invalid-args: - shard-tglb: NOTRUN -> [SKIP][2] ([i915#280]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21084/shard-tglb3/igt@gem_ctx_s...@invalid-args.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][3] -> [TIMEOUT][4] ([i915#2369] / [i915#3063] / [i915#3648]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/shard-tglb7/igt@gem_...@unwedge-stress.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21084/shard-tglb2/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-tglb: NOTRUN -> [FAIL][5] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21084/shard-tglb2/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21084/shard-kbl3/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][7] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21084/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/shard-tglb8/igt@gem_exec_fair@basic-p...@vcs1.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21084/shard-tglb3/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_params@secure-non-root: - shard-tglb: NOTRUN -> [SKIP][10] ([fdo#112283]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21084/shard-tglb3/igt@gem_exec_par...@secure-non-root.html * igt@gem_pread@exhaustion: - shard-kbl: NOTRUN -> [WARN][11] ([i915#2658]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21084/shard-kbl3/igt@gem_pr...@exhaustion.html * igt@gem_userptr_blits@input-checking: - shard-tglb: NOTRUN -> [DMESG-WARN][12] ([i915#3002]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21084/shard-tglb3/igt@gem_userptr_bl...@input-checking.html * igt@gem_userptr_blits@unsync-unmap-cycles: - shard-tglb: NOTRUN -> [SKIP][13] ([i915#3297]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21084/shard-tglb2/igt@gem_userptr_bl...@unsync-unmap-cycles.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][14] -> [DMESG-WARN][15] ([i915#1436] / [i915#716]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/shard-skl1/igt@gen9_exec_pa...@allowed-single.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21084/shard-skl1/igt@gen9_exec_pa...@allowed-single.html * igt@gen9_exec_parse@bb-start-far: - shard-tglb: NOTRUN -> [SKIP][16] ([i915#2856]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21084/shard-tglb2/igt@gen9_exec_pa...@bb-start-far.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-tglb: [PASS][17] -> [INCOMPLETE][18] ([i915#2411] / [i915#456] / [i915#750]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10604/shard-tglb3/igt@i915_pm_...@system-suspend-execbuf.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21084/shard-tglb7/igt@i915_pm_...@system-suspend-execbuf.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3777]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21084/shard-kbl3/igt@kms_big...@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_big_fb@y-tiled-8bpp-rotate-270: -
Re: [Intel-gfx] [PATCH 11/15] drm/msm: cleanup: drm_modeset_lock_all() --> DRM_MODESET_LOCK_ALL_BEGIN()
On Thu, Sep 16, 2021 at 11:15:48PM +0200, Fernando Ramos wrote: > As requested in Documentation/gpu/todo.rst, replace driver calls to > drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and > DRM_MODESET_LOCK_ALL_END() > > Signed-off-by: Fernando Ramos > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > index 768012243b44..4cbc79eaee17 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c > @@ -1172,14 +1172,16 @@ static int _dpu_debugfs_status_show(struct seq_file > *s, void *data) > struct drm_display_mode *mode; > struct drm_framebuffer *fb; > struct drm_plane_state *state; > + struct drm_modeset_acquire_ctx ctx; > struct dpu_crtc_state *cstate; > > int i, out_width; > + int ret; Please put ret with i & out_width > > dpu_crtc = s->private; > crtc = _crtc->base; > > - drm_modeset_lock_all(crtc->dev); > + DRM_MODESET_LOCK_ALL_BEGIN(crtc->dev, ctx, 0, ret); > cstate = to_dpu_crtc_state(crtc->state); > > mode = >state->adjusted_mode; > @@ -1263,7 +1265,7 @@ static int _dpu_debugfs_status_show(struct seq_file *s, > void *data) > dpu_crtc->vblank_cb_time = ktime_set(0, 0); > } > > - drm_modeset_unlock_all(crtc->dev); > + DRM_MODESET_LOCK_ALL_END(crtc->dev, ctx, ret); > > return 0; Return ret here > } > -- > 2.33.0 > -- Sean Paul, Software Engineer, Google / Chromium OS
Re: [Intel-gfx] [PATCH 10/15] drm/nouveau: cleanup: drm_modeset_lock_all() --> DRM_MODESET_LOCK_ALL_BEGIN()
On Thu, Sep 16, 2021 at 11:15:47PM +0200, Fernando Ramos wrote:
> As requested in Documentation/gpu/todo.rst, replace driver calls to
> drm_modeset_lock_all() with DRM_MODESET_LOCK_ALL_BEGIN() and
> DRM_MODESET_LOCK_ALL_END()
>
> Signed-off-by: Fernando Ramos
> ---
> drivers/gpu/drm/nouveau/dispnv50/disp.c | 12
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> index d7b9f7f8c9e3..eb613af4cdd5 100644
> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> @@ -667,15 +667,17 @@ nv50_audio_component_bind(struct device *kdev, struct
> device *hda_kdev,
> struct drm_device *drm_dev = dev_get_drvdata(kdev);
> struct nouveau_drm *drm = nouveau_drm(drm_dev);
> struct drm_audio_component *acomp = data;
> + struct drm_modeset_acquire_ctx ctx;
> + int ret;
>
> if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
> return -ENOMEM;
>
> - drm_modeset_lock_all(drm_dev);
> + DRM_MODESET_LOCK_ALL_BEGIN(drm_dev, ctx, 0, ret);
> acomp->ops = _audio_component_ops;
> acomp->dev = kdev;
> drm->audio.component = acomp;
> - drm_modeset_unlock_all(drm_dev);
> + DRM_MODESET_LOCK_ALL_END(drm_dev, ctx, ret);
> return 0;
Return ret here, with that fixed,
Reviewed-by: Sean Paul
> }
>
> @@ -686,12 +688,14 @@ nv50_audio_component_unbind(struct device *kdev, struct
> device *hda_kdev,
> struct drm_device *drm_dev = dev_get_drvdata(kdev);
> struct nouveau_drm *drm = nouveau_drm(drm_dev);
> struct drm_audio_component *acomp = data;
> + struct drm_modeset_acquire_ctx ctx;
> + int ret;
>
> - drm_modeset_lock_all(drm_dev);
> + DRM_MODESET_LOCK_ALL_BEGIN(drm_dev, ctx, 0, ret);
> drm->audio.component = NULL;
> acomp->ops = NULL;
> acomp->dev = NULL;
> - drm_modeset_unlock_all(drm_dev);
> + DRM_MODESET_LOCK_ALL_END(drm_dev, ctx, ret);
> }
>
> static const struct component_ops nv50_audio_component_bind_ops = {
> --
> 2.33.0
>
--
Sean Paul, Software Engineer, Google / Chromium OS
