Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Don't check CT descriptor status before CT write / read

[Jani Nikula]

On Thu, 20 Jan 2022, Matthew Brost  wrote:
> Don't check CT descriptor status, unless CONFIG_DRM_I915_DEBUG_GUC is
> set, before CT write / read as this could result in a read across the
> PCIe bus thus adding latency to every CT write / read. On well behavied
> systems this vaue should always read as zero. For some reason it doesn't
> the CT channel is broken and will eventually recover from a GT reset,
> albeit the GT reset will not be triggered immediately by seeing that
> descriptor status is non-zero.
>
> v2:
>  (CI)
>   - Fix build error (hide corrupted label in write function behind
> CONFIG_DRM_I915_DEBUG_GUC)
>
> Signed-off-by: Matthew Brost 
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index de89d40abd38d..948cf31429412 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -379,8 +379,10 @@ static int ct_write(struct intel_guc_ct *ct,
>   u32 *cmds = ctb->cmds;
>   unsigned int i;
>  
> +#ifdef CONFIG_DRM_I915_DEBUG_GUC
>   if (unlikely(desc->status))
>   goto corrupted;
> +#endif

Please don't add #ifdefs inline. You can use
IS_ENABLED(CONFIG_DRM_I915_DEBUG_GUC) in if statements, but otherwise
the code needs to be split out to a separate function.

BR,
Jani.

>  
>   GEM_BUG_ON(tail > size);
>  
> @@ -445,11 +447,13 @@ static int ct_write(struct intel_guc_ct *ct,
>  
>   return 0;
>  
> +#ifdef CONFIG_DRM_I915_DEBUG_GUC
>  corrupted:
>   CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
>desc->head, desc->tail, desc->status);
>   ctb->broken = true;
>   return -EPIPE;
> +#endif
>  }
>  
>  /**
> @@ -815,8 +819,10 @@ static int ct_read(struct intel_guc_ct *ct, struct 
> ct_incoming_msg **msg)
>   if (unlikely(ctb->broken))
>   return -EPIPE;
>  
> +#ifdef CONFIG_DRM_I915_DEBUG_GUC
>   if (unlikely(desc->status))
>   goto corrupted;
> +#endif
>  
>   GEM_BUG_ON(head > size);

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✓ Fi.CI.IGT: success for Flush G2H handler during a GT reset

[Patchwork]

== Series Details ==

Series: Flush G2H handler during a GT reset
URL   : https://patchwork.freedesktop.org/series/99136/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5_full -> Patchwork_22051_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_22051_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-apl:  [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +3 similar 
issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-apl3/igt@gem_ctx_isolation@preservation...@bcs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl8/igt@gem_ctx_isolation@preservation...@bcs0.html

  * igt@gem_ctx_persistence@engines-queued:
- shard-snb:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-snb5/igt@gem_ctx_persiste...@engines-queued.html

  * igt@gem_eio@in-flight-suspend:
- shard-kbl:  [PASS][4] -> [INCOMPLETE][5] ([i915#180] / 
[i915#3614])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-kbl3/igt@gem_...@in-flight-suspend.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl1/igt@gem_...@in-flight-suspend.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [PASS][6] -> [SKIP][7] ([i915#4525])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-iclb1/igt@gem_exec_balan...@parallel-keep-submit-fence.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb3/igt@gem_exec_balan...@parallel-keep-submit-fence.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][8] ([i915#2846])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl6/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-glk4/igt@gem_exec_fair@basic-n...@vcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-glk4/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl:  [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar 
issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2849])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-iclb8/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_suspend@basic-s3@smem:
- shard-apl:  NOTRUN -> [DMESG-WARN][16] ([i915#180])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl6/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-apl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl1/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3323])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl6/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@i915_pm_dc@dc6-dpms:
- shard-kbl:  NOTRUN -> [FAIL][19] ([i915#454])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-kbl6/igt@i915_pm...@dc6-dpms.html

  * igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-apl:  NOTRUN -> [SKIP][20] ([fdo#109271]) +64 similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-apl6/igt@i915_pm_...@modeset-lpsp-stress.html

  * igt@i915_pm_rpm@sysfs-read:
- shard-snb:  NOTRUN -> [SKIP][21] ([fdo#109271]) +21 similar issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/shard-snb5/igt@i915_pm_...@sysfs-read.html

  * igt@i915_selftest@live@hangcheck:
- shard-snb:  [PASS][22] -> [INCOMPLETE][23] ([i915#3921])
   [22]: 

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Add Wa_18018781329

[Matt Roper]

On Fri, Jan 21, 2022 at 01:05:07AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/dg2: Add Wa_18018781329
> URL   : https://patchwork.freedesktop.org/series/99128/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_5 -> Patchwork_22049
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_22049 absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_22049, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22049/index.html
> 
> Participating hosts (42 -> 40)
> --
> 
>   Missing(2): fi-bsw-cyan fi-bdw-samus 
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_22049:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@i915_selftest@live@execlists:
> - fi-glk-j4005:   [PASS][1] -> [INCOMPLETE][2]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-glk-j4005/igt@i915_selftest@l...@execlists.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22049/fi-glk-j4005/igt@i915_selftest@l...@execlists.html

Appears to be the same as
https://gitlab.freedesktop.org/drm/intel/-/issues/4920



Matt

> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_22049 that come from known issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@gem_flink_basic@bad-flink:
> - fi-skl-6600u:   [PASS][3] -> [INCOMPLETE][4] ([i915#4547])
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22049/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
> 
>   * igt@runner@aborted:
> - fi-skl-6600u:   NOTRUN -> [FAIL][5] ([i915#2722] / [i915#4312])
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22049/fi-skl-6600u/igt@run...@aborted.html
> - fi-glk-j4005:   NOTRUN -> [FAIL][6] ([i915#2722] / [i915#4312] / 
> [k.org#202321])
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22049/fi-glk-j4005/igt@run...@aborted.html
> 
>   
>  Possible fixes 
> 
>   * igt@i915_selftest@live@gtt:
> - fi-bdw-5557u:   [DMESG-FAIL][7] -> [PASS][8]
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22049/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html
> 
>   
>   {name}: This element is suppressed. This means it is ignored when computing
>   the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
>   [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
>   [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
>   [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
>   [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
>   [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
> 
> 
> Build changes
> -
> 
>   * Linux: CI_DRM_5 -> Patchwork_22049
> 
>   CI-20190529: 20190529
>   CI_DRM_5: 4e12213687264ffccb45d72fe638f94d3ca666bd @ 
> git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_6329: 38f656fdd61119105ecfa2c4dac157cd7dcad204 @ 
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
>   Patchwork_22049: 3bb57af567ca7c35813b4f945576dbf573308408 @ 
> git://anongit.freedesktop.org/gfx-ci/linux
> 
> 
> == Linux commits ==
> 
> 3bb57af567ca drm/i915/dg2: Add Wa_18018781329
> 
> == Logs ==
> 
> For more details see: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22049/index.html

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH] drm/i915/guc: Don't check CT descriptor status before CT write / read

[kernel test robot]

Hi Matthew,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next 
drm/drm-next tegra-drm/drm/tegra/for-next v5.16 next-20220121]
[cannot apply to airlied/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Matthew-Brost/drm-i915-guc-Don-t-check-CT-descriptor-status-before-CT-write-read/20220121-023033
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-a005-20220117 
(https://download.01.org/0day-ci/archive/20220121/202201211310.npkld1yy-...@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 
f7b7138a62648f4019c55e4671682af1f851f295)
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# 
https://github.com/0day-ci/linux/commit/0311a8b0f99c50ab1a666a5cdbe2b1a0a2c3c71d
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review 
Matthew-Brost/drm-i915-guc-Don-t-check-CT-descriptor-status-before-CT-write-read/20220121-023033
git checkout 0311a8b0f99c50ab1a666a5cdbe2b1a0a2c3c71d
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 
O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:469:1: error: unused label 
>> 'corrupted' [-Werror,-Wunused-label]
   corrupted:
   ^~
   1 error generated.


vim +/corrupted +469 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c

f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  422  
1d407096002beca drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2018-03-26  423  /*
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  424   * dw0: CT header (including fence)
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  425   * dw1: HXG header (including action code)
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  426   * dw2+: action data
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  427   */
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  428  header = FIELD_PREP(GUC_CTB_MSG_0_FORMAT, 
GUC_CTB_FORMAT_HXG) |
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  429   FIELD_PREP(GUC_CTB_MSG_0_NUM_DWORDS, len) |
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  430   FIELD_PREP(GUC_CTB_MSG_0_FENCE, fence);
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  431  
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost
2021-07-08  432  type = (flags & INTEL_GUC_CT_SEND_NB) ? GUC_HXG_TYPE_EVENT 
:
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost
2021-07-08  433  GUC_HXG_TYPE_REQUEST;
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost
2021-07-08  434  hxg = FIELD_PREP(GUC_HXG_MSG_0_TYPE, type) |
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost
2021-07-08  435  FIELD_PREP(GUC_HXG_EVENT_MSG_0_ACTION |
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost
2021-07-08  436 GUC_HXG_EVENT_MSG_0_DATA0, action[0]);
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  437  
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  438  CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  439   tail, 4, , 4, , 4 * (len - 1), 
[1]);
0a015ff9730c169 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2018-03-26  440  
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  441  cmds[tail] = header;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  442  tail = (tail + 1) % size;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  443  
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  444  cmds[tail] = hxg;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c   Michal 

[Intel-gfx] ✓ Fi.CI.BAT: success for Flush G2H handler during a GT reset

[Patchwork]

== Series Details ==

Series: Flush G2H handler during a GT reset
URL   : https://patchwork.freedesktop.org/series/99136/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5 -> Patchwork_22051


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/index.html

Participating hosts (42 -> 38)
--

  Missing(4): fi-kbl-soraka fi-bsw-cyan fi-bdw-samus fi-kbl-7500u 

Known issues


  Here are the changes found in Patchwork_22051 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html

  * igt@gem_flink_basic@bad-flink:
- fi-skl-6600u:   [PASS][2] -> [FAIL][3] ([i915#4547])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-6:  [PASS][4] -> [INCOMPLETE][5] ([i915#4418])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/bat-dg1-6/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [PASS][6] -> [DMESG-FAIL][7] ([i915#4528])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@runner@aborted:
- fi-skl-6600u:   NOTRUN -> [FAIL][8] ([i915#4312])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/fi-skl-6600u/igt@run...@aborted.html
- fi-bdw-5557u:   NOTRUN -> [FAIL][9] ([i915#2426] / [i915#4312])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/fi-bdw-5557u/igt@run...@aborted.html
- bat-dg1-6:  NOTRUN -> [FAIL][10] ([i915#4214] / [i915#4312])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/bat-dg1-6/igt@run...@aborted.html
- fi-blb-e6850:   NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/fi-blb-e6850/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][12] ([i915#3921]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  
 Warnings 

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-guc: [SKIP][14] ([fdo#109271]) -> [FAIL][15] ([i915#3049])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22051/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#3049]: https://gitlab.freedesktop.org/drm/intel/issues/3049
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4214]: https://gitlab.freedesktop.org/drm/intel/issues/4214
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897


Build changes
-

  * Linux: CI_DRM_5 -> Patchwork_22051

  CI-20190529: 20190529
  CI_DRM_5: 4e12213687264ffccb45d72fe638f94d3ca666bd @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6329: 38f656fdd61119105ecfa2c4dac157cd7dcad204 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22051: 41d8611617d3b97ce000ec529dcef74aaa2efe04 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

41d8611617d3 drm/i915/guc: Flush G2H handler during a GT reset
e99d26d68785 drm/i915/guc: Add work queue to trigger a GT reset
054f74cfab51 drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL

== Logs ==

For more details 

Re: [Intel-gfx] [PATCH] drm/i915/guc: Don't check CT descriptor status before CT write / read

[kernel test robot]

Hi Matthew,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next 
drm/drm-next tegra-drm/drm/tegra/for-next v5.16 next-20220121]
[cannot apply to airlied/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Matthew-Brost/drm-i915-guc-Don-t-check-CT-descriptor-status-before-CT-write-read/20220121-023033
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-defconfig 
(https://download.01.org/0day-ci/archive/20220121/202201211326.zspu6s33-...@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# 
https://github.com/0day-ci/linux/commit/0311a8b0f99c50ab1a666a5cdbe2b1a0a2c3c71d
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review 
Matthew-Brost/drm-i915-guc-Don-t-check-CT-descriptor-status-before-CT-write-read/20220121-023033
git checkout 0311a8b0f99c50ab1a666a5cdbe2b1a0a2c3c71d
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c: In function 'ct_write':
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:469:1: error: label 'corrupted' 
>> defined but not used [-Werror=unused-label]
 469 | corrupted:
 | ^
   cc1: all warnings being treated as errors


vim +/corrupted +469 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c

f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  422  
1d407096002beca drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2018-03-26  423  /*
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  424   * dw0: CT header (including fence)
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  425   * dw1: HXG header (including action code)
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  426   * dw2+: action data
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  427   */
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  428  header = FIELD_PREP(GUC_CTB_MSG_0_FORMAT, 
GUC_CTB_FORMAT_HXG) |
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  429   FIELD_PREP(GUC_CTB_MSG_0_NUM_DWORDS, len) |
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  430   FIELD_PREP(GUC_CTB_MSG_0_FENCE, fence);
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  431  
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost
2021-07-08  432  type = (flags & INTEL_GUC_CT_SEND_NB) ? GUC_HXG_TYPE_EVENT 
:
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost
2021-07-08  433  GUC_HXG_TYPE_REQUEST;
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost
2021-07-08  434  hxg = FIELD_PREP(GUC_HXG_MSG_0_TYPE, type) |
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost
2021-07-08  435  FIELD_PREP(GUC_HXG_EVENT_MSG_0_ACTION |
1681924d8bdeb24 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost
2021-07-08  436 GUC_HXG_EVENT_MSG_0_DATA0, action[0]);
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  437  
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  438  CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  439   tail, 4, , 4, , 4 * (len - 1), 
[1]);
0a015ff9730c169 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2018-03-26  440  
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  441  cmds[tail] = header;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  442  tail = (tail + 1) % size;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  443  
572f2a5cd9742c5 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  444  cmds[tail] = hxg;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  445  tail = (tail + 1) % size;
f8a58d639dd95b0 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  446  
f8a58d639dd95b0 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Introduce G12 subplatform of DG2

[Patchwork]

== Series Details ==

Series: drm/i915: Introduce G12 subplatform of DG2
URL   : https://patchwork.freedesktop.org/series/99129/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5_full -> Patchwork_22050_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_22050_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22050_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22050_full:

### IGT changes ###

 Warnings 

  * igt@runner@aborted:
- shard-apl:  ([FAIL][1], [FAIL][2], [FAIL][3], [FAIL][4], 
[FAIL][5], [FAIL][6]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / 
[i915#4312]) -> ([FAIL][7], [FAIL][8], [FAIL][9], [FAIL][10], [FAIL][11], 
[FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15], [FAIL][16], [FAIL][17]) 
([i915#180] / [i915#1814] / [i915#3002] / [i915#4312])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-apl2/igt@run...@aborted.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-apl1/igt@run...@aborted.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-apl1/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-apl8/igt@run...@aborted.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-apl6/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-apl1/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/shard-apl4/igt@run...@aborted.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/shard-apl7/igt@run...@aborted.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/shard-apl3/igt@run...@aborted.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/shard-apl7/igt@run...@aborted.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/shard-apl7/igt@run...@aborted.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/shard-apl7/igt@run...@aborted.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/shard-apl6/igt@run...@aborted.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/shard-apl7/igt@run...@aborted.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/shard-apl2/igt@run...@aborted.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/shard-apl7/igt@run...@aborted.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/shard-apl7/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_22050_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-apl:  [PASS][18] -> [DMESG-WARN][19] ([i915#180]) +1 
similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-apl3/igt@gem_ctx_isolation@preservation...@bcs0.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/shard-apl2/igt@gem_ctx_isolation@preservation...@bcs0.html

  * igt@gem_ctx_persistence@engines-queued:
- shard-snb:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#1099])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/shard-snb7/igt@gem_ctx_persiste...@engines-queued.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [PASS][21] -> [SKIP][22] ([i915#4525])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-iclb1/igt@gem_exec_balan...@parallel-keep-submit-fence.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/shard-iclb5/igt@gem_exec_balan...@parallel-keep-submit-fence.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][23] -> [FAIL][24] ([i915#2846])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-glk8/igt@gem_exec_f...@basic-deadline.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/shard-glk4/igt@gem_exec_f...@basic-deadline.html
- shard-apl:  NOTRUN -> [FAIL][25] ([i915#2846])
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/shard-apl7/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][26] -> [FAIL][27] ([i915#2842])
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html
   [27]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Flush G2H handler during a GT reset

[Patchwork]

== Series Details ==

Series: Flush G2H handler during a GT reset
URL   : https://patchwork.freedesktop.org/series/99136/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] [PATCH 0/3] Flush G2H handler during a GT reset

[Matthew Brost]

After a small fix to error capture code, we now can flush G2H during a
GT reset which simplifies code and seals some extreme corner case races. 

v2:
 (CI)
  - Don't trigger GT reset from G2H handler
v3:
  - Address John Harrison's comments
v4:
  - Address John Harrison's comments

Signed-off-by: Matthew Brost 


Matthew Brost (3):
  drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL
  drm/i915/guc: Add work queue to trigger a GT reset
  drm/i915/guc: Flush G2H handler during a GT reset

 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  9 +++
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 55 ---
 drivers/gpu/drm/i915/i915_gpu_error.c |  2 +-
 3 files changed, 44 insertions(+), 22 deletions(-)

-- 
2.34.1

[Intel-gfx] [PATCH 2/3] drm/i915/guc: Add work queue to trigger a GT reset

[Matthew Brost]

The G2H handler needs to be flushed during a GT reset but a G2H
indicating engine reset failure can trigger a GT reset. Add a worker to
trigger the GT rest when an engine reset failure is received to break
this circular dependency.

v2:
 (John Harrison)
  - Store engine reset mask
  - Fix typo in commit message
v3:
 (John Harrison)
  - Fix another typo in commit message
  - s/reset_*/reset_fail_*/

Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  9 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +--
 2 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 9d26a86fe557a..d59bbf49d1c2b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -119,6 +119,15 @@ struct intel_guc {
 * function as it might be in an atomic context (no sleeping)
 */
struct work_struct destroyed_worker;
+   /**
+* @reset_fail_worker: worker to trigger a GT reset after an
+* engine reset fails
+*/
+   struct work_struct reset_fail_worker;
+   /**
+* @reset_fail_mask: mask of engines that failed to reset
+*/
+   intel_engine_mask_t reset_fail_mask;
} submission_state;
 
/**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 3918f1be114fa..9a3f503d201aa 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1731,6 +1731,7 @@ void intel_guc_submission_reset_finish(struct intel_guc 
*guc)
 }
 
 static void destroyed_worker_func(struct work_struct *w);
+static void reset_fail_worker_func(struct work_struct *w);
 
 /*
  * Set up the memory resources to be shared with the GuC (via the GGTT)
@@ -1761,6 +1762,8 @@ int intel_guc_submission_init(struct intel_guc *guc)
INIT_LIST_HEAD(>submission_state.destroyed_contexts);
INIT_WORK(>submission_state.destroyed_worker,
  destroyed_worker_func);
+   INIT_WORK(>submission_state.reset_fail_worker,
+ reset_fail_worker_func);
 
guc->submission_state.guc_ids_bitmap =
bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
@@ -4026,6 +4029,26 @@ guc_lookup_engine(struct intel_guc *guc, u8 guc_class, 
u8 instance)
return gt->engine_class[engine_class][instance];
 }
 
+static void reset_fail_worker_func(struct work_struct *w)
+{
+   struct intel_guc *guc = container_of(w, struct intel_guc,
+
submission_state.reset_fail_worker);
+   struct intel_gt *gt = guc_to_gt(guc);
+   intel_engine_mask_t reset_fail_mask;
+   unsigned long flags;
+
+   spin_lock_irqsave(>submission_state.lock, flags);
+   reset_fail_mask = guc->submission_state.reset_fail_mask;
+   guc->submission_state.reset_fail_mask = 0;
+   spin_unlock_irqrestore(>submission_state.lock, flags);
+
+   if (likely(reset_fail_mask))
+   intel_gt_handle_error(gt, reset_fail_mask,
+ I915_ERROR_CAPTURE,
+ "GuC failed to reset engine mask=0x%x\n",
+ reset_fail_mask);
+}
+
 int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
 const u32 *msg, u32 len)
 {
@@ -4033,6 +4056,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc 
*guc,
struct intel_gt *gt = guc_to_gt(guc);
u8 guc_class, instance;
u32 reason;
+   unsigned long flags;
 
if (unlikely(len != 3)) {
drm_err(>i915->drm, "Invalid length %u", len);
@@ -4057,10 +4081,15 @@ int intel_guc_engine_failure_process_msg(struct 
intel_guc *guc,
drm_err(>i915->drm, "GuC engine reset request failed on %d:%d (%s) 
because 0x%08X",
guc_class, instance, engine->name, reason);
 
-   intel_gt_handle_error(gt, engine->mask,
- I915_ERROR_CAPTURE,
- "GuC failed to reset %s (reason=0x%08x)\n",
- engine->name, reason);
+   spin_lock_irqsave(>submission_state.lock, flags);
+   guc->submission_state.reset_fail_mask |= engine->mask;
+   spin_unlock_irqrestore(>submission_state.lock, flags);
+
+   /*
+* A GT reset flushes this worker queue (G2H handler) so we must use
+* another worker to trigger a GT reset.
+*/
+   queue_work(system_unbound_wq, >submission_state.reset_fail_worker);
 
return 0;
 }
-- 
2.34.1

[Intel-gfx] [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset

[Matthew Brost]

Now that the error capture is fully decoupled from fence signalling
(request retirement to free memory, which in turn depends on resets) we
can safely flush the G2H handler during a GT reset. This eliminates
corner cases where GuC generated G2H (e.g. engine resets) race with a GT
reset.

v2:
 (John Harrison)
  - Fix typo in commit message (s/is/in)

Signed-off-by: Matthew Brost 
Reviewed-by: John Harrison 
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c  | 18 +-
 1 file changed, 1 insertion(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 9a3f503d201aa..1331ff91c5b05 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc 
*guc);
 
 void intel_guc_submission_reset_prepare(struct intel_guc *guc)
 {
-   int i;
-
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
return;
@@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc 
*guc)
 
guc_flush_submissions(guc);
guc_flush_destroyed_contexts(guc);
-
-   /*
-* Handle any outstanding G2Hs before reset. Call IRQ handler directly
-* each pass as interrupt have been disabled. We always scrub for
-* outstanding G2H as it is possible for outstanding_submission_g2h to
-* be incremented after the context state update.
-*/
-   for (i = 0; i < 4 && atomic_read(>outstanding_submission_g2h); 
++i) {
-   intel_guc_to_host_event_handler(guc);
-#define wait_for_reset(guc, wait_var) \
-   intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20))
-   do {
-   wait_for_reset(guc, >outstanding_submission_g2h);
-   } while (!list_empty(>ct.requests.incoming));
-   }
+   flush_work(>ct.requests.worker);
 
scrub_guc_desc_for_outstanding_g2h(guc);
 }
-- 
2.34.1

[Intel-gfx] [PATCH 1/3] drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL

[Matthew Brost]

Allocate intel_engine_coredump_alloc with ALLOW_FAIL rather than
GFP_KERNEL to fully decouple the error capture from fence signalling.

v2:
 (John Harrison)
  - Fix typo in commit message (s/do/to)

Fixes: 8b91cdd4f8649 ("drm/i915: Use __GFP_KSWAPD_RECLAIM in the capture code")

Signed-off-by: Matthew Brost 
Reviewed-by: John Harrison 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 67f3515f07e7a..aee42eae4729f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1516,7 +1516,7 @@ capture_engine(struct intel_engine_cs *engine,
struct i915_request *rq = NULL;
unsigned long flags;
 
-   ee = intel_engine_coredump_alloc(engine, GFP_KERNEL);
+   ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL);
if (!ee)
return NULL;
 
-- 
2.34.1

Re: [Intel-gfx] [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset

[Matthew Brost]

On Thu, Jan 20, 2022 at 05:36:22PM -0800, John Harrison wrote:
> On 1/19/2022 13:24, Matthew Brost wrote:
> > Now that the error capture is fully decoupled from fence signalling
> > (request retirement to free memory, which in turn depends on resets) we
> > can safely flush the G2H handler during a GT reset. This is eliminates
> This eliminates
> 
> John.
> 

Yep, will fixup in the next rev.

Matt

> > corner cases where GuC generated G2H (e.g. engine resets) race with a GT
> > reset.
> > 
> > v2:
> >   (John Harrison)
> >- Fix typo in commit message (s/is/in)
> > 
> > Signed-off-by: Matthew Brost 
> > Reviewed-by: John Harrison 
> > ---
> >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c  | 18 +-
> >   1 file changed, 1 insertion(+), 17 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 514b3060b141..406dd2e3f5a9 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct 
> > intel_guc *guc);
> >   void intel_guc_submission_reset_prepare(struct intel_guc *guc)
> >   {
> > -   int i;
> > -
> > if (unlikely(!guc_submission_initialized(guc))) {
> > /* Reset called during driver load? GuC not yet initialised! */
> > return;
> > @@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct 
> > intel_guc *guc)
> > guc_flush_submissions(guc);
> > guc_flush_destroyed_contexts(guc);
> > -
> > -   /*
> > -* Handle any outstanding G2Hs before reset. Call IRQ handler directly
> > -* each pass as interrupt have been disabled. We always scrub for
> > -* outstanding G2H as it is possible for outstanding_submission_g2h to
> > -* be incremented after the context state update.
> > -*/
> > -   for (i = 0; i < 4 && atomic_read(>outstanding_submission_g2h); 
> > ++i) {
> > -   intel_guc_to_host_event_handler(guc);
> > -#define wait_for_reset(guc, wait_var) \
> > -   intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20))
> > -   do {
> > -   wait_for_reset(guc, >outstanding_submission_g2h);
> > -   } while (!list_empty(>ct.requests.incoming));
> > -   }
> > +   flush_work(>ct.requests.worker);
> > scrub_guc_desc_for_outstanding_g2h(guc);
> >   }
> 

Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Add work queue to trigger a GT reset

[Matthew Brost]

On Thu, Jan 20, 2022 at 05:34:54PM -0800, John Harrison wrote:
> On 1/19/2022 13:24, Matthew Brost wrote:
> > The G2H handler needs to be flushed during a GT reset but a G2H
> > indicating engine reset failure can trigger a GT reset. Add a worker to
> > trigger the GT when an engine reset failure is received to break this
> trigger the GT reset?
> 

Yes.

> > circular dependency.
> > 
> > v2:
> >   (John Harrison)
> >- Store engine reset mask
> >- Fix typo in commit message
> > 
> > Signed-off-by: Matthew Brost 
> > ---
> >   drivers/gpu/drm/i915/gt/uc/intel_guc.h|  9 +
> >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +--
> >   2 files changed, 42 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > index 9d26a86fe557..c4a9fc7dd246 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > @@ -119,6 +119,15 @@ struct intel_guc {
> >  * function as it might be in an atomic context (no sleeping)
> >  */
> > struct work_struct destroyed_worker;
> > +   /**
> > +* @reset_worker: worker to trigger a GT reset after an engine
> > +* reset fails
> > +*/
> > +   struct work_struct reset_worker;
> > +   /**
> > +* @reset_mask: mask of engines that failed to reset
> > +*/
> > +   intel_engine_mask_t reset_mask;
> reset_fail_mask might be a less ambiguous name? Same for the worker struct
> and function.
> 

How about:

struct {
worker;
mask;
} engine_reset_fail;

Matt

> John.
> 
> > } submission_state;
> > /**
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 3918f1be114f..514b3060b141 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -1731,6 +1731,7 @@ void intel_guc_submission_reset_finish(struct 
> > intel_guc *guc)
> >   }
> >   static void destroyed_worker_func(struct work_struct *w);
> > +static void reset_worker_func(struct work_struct *w);
> >   /*
> >* Set up the memory resources to be shared with the GuC (via the GGTT)
> > @@ -1761,6 +1762,8 @@ int intel_guc_submission_init(struct intel_guc *guc)
> > INIT_LIST_HEAD(>submission_state.destroyed_contexts);
> > INIT_WORK(>submission_state.destroyed_worker,
> >   destroyed_worker_func);
> > +   INIT_WORK(>submission_state.reset_worker,
> > + reset_worker_func);
> > guc->submission_state.guc_ids_bitmap =
> > bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
> > @@ -4026,6 +4029,26 @@ guc_lookup_engine(struct intel_guc *guc, u8 
> > guc_class, u8 instance)
> > return gt->engine_class[engine_class][instance];
> >   }
> > +static void reset_worker_func(struct work_struct *w)
> > +{
> > +   struct intel_guc *guc = container_of(w, struct intel_guc,
> > +submission_state.reset_worker);
> > +   struct intel_gt *gt = guc_to_gt(guc);
> > +   intel_engine_mask_t reset_mask;
> > +   unsigned long flags;
> > +
> > +   spin_lock_irqsave(>submission_state.lock, flags);
> > +   reset_mask = guc->submission_state.reset_mask;
> > +   guc->submission_state.reset_mask = 0;
> > +   spin_unlock_irqrestore(>submission_state.lock, flags);
> > +
> > +   if (likely(reset_mask))
> > +   intel_gt_handle_error(gt, reset_mask,
> > + I915_ERROR_CAPTURE,
> > + "GuC failed to reset engine mask=0x%x\n",
> > + reset_mask);
> > +}
> > +
> >   int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
> >  const u32 *msg, u32 len)
> >   {
> > @@ -4033,6 +4056,7 @@ int intel_guc_engine_failure_process_msg(struct 
> > intel_guc *guc,
> > struct intel_gt *gt = guc_to_gt(guc);
> > u8 guc_class, instance;
> > u32 reason;
> > +   unsigned long flags;
> > if (unlikely(len != 3)) {
> > drm_err(>i915->drm, "Invalid length %u", len);
> > @@ -4057,10 +4081,15 @@ int intel_guc_engine_failure_process_msg(struct 
> > intel_guc *guc,
> > drm_err(>i915->drm, "GuC engine reset request failed on %d:%d (%s) 
> > because 0x%08X",
> > guc_class, instance, engine->name, reason);
> > -   intel_gt_handle_error(gt, engine->mask,
> > - I915_ERROR_CAPTURE,
> > - "GuC failed to reset %s (reason=0x%08x)\n",
> > - engine->name, reason);
> > +   spin_lock_irqsave(>submission_state.lock, flags);
> > +   guc->submission_state.reset_mask |= engine->mask;
> > +   spin_unlock_irqrestore(>submission_state.lock, flags);
> > +
> > +   /*
> > +* A GT reset flushes this worker queue 

[Intel-gfx] ✗ Fi.CI.IGT: failure for Splitting up platform-specific calls

[Patchwork]

== Series Details ==

Series: Splitting up platform-specific calls
URL   : https://patchwork.freedesktop.org/series/99126/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5_full -> Patchwork_22048_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22048_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22048_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22048_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_schedule@smoketest-all:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-tglb2/igt@gem_exec_sched...@smoketest-all.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/shard-tglb6/igt@gem_exec_sched...@smoketest-all.html

  
 Warnings 

  * igt@runner@aborted:
- shard-apl:  ([FAIL][3], [FAIL][4], [FAIL][5], [FAIL][6], 
[FAIL][7], [FAIL][8]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / 
[i915#4312]) -> ([FAIL][9], [FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13], 
[FAIL][14]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#4312])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-apl2/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-apl6/igt@run...@aborted.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-apl1/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-apl1/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-apl1/igt@run...@aborted.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-apl8/igt@run...@aborted.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/shard-apl7/igt@run...@aborted.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/shard-apl7/igt@run...@aborted.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/shard-apl7/igt@run...@aborted.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/shard-apl6/igt@run...@aborted.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/shard-apl8/igt@run...@aborted.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/shard-apl7/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_22048_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl:  [PASS][15] -> [DMESG-WARN][16] ([i915#180])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-apl3/igt@gem_ctx_isolation@preservation...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/shard-apl8/igt@gem_ctx_isolation@preservation...@rcs0.html

  * igt@gem_ctx_persistence@engines-queued:
- shard-snb:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#1099])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/shard-snb4/igt@gem_ctx_persiste...@engines-queued.html

  * igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][18] -> [TIMEOUT][19] ([i915#2481] / 
[i915#3070])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-iclb8/igt@gem_...@unwedge-stress.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/shard-iclb2/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][20] -> [SKIP][21] ([i915#4525])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-iclb1/igt@gem_exec_balan...@parallel-keep-in-fence.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/shard-iclb3/igt@gem_exec_balan...@parallel-keep-in-fence.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][22] -> [FAIL][23] ([i915#2846])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-glk8/igt@gem_exec_f...@basic-deadline.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/shard-glk8/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][24] -> [FAIL][25] ([i915#2842])
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
   

Re: [Intel-gfx] [PATCH] drm/i915/guc: Don't check CT descriptor status before CT write / read

[kernel test robot]

Hi Matthew,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip drm-exynos/exynos-drm-next 
drm/drm-next tegra-drm/drm/tegra/for-next v5.16 next-20220120]
[cannot apply to airlied/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Matthew-Brost/drm-i915-guc-Don-t-check-CT-descriptor-status-before-CT-write-read/20220121-023033
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-r002-20220117 
(https://download.01.org/0day-ci/archive/20220121/202201211022.gq2u1jns-...@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 
f7b7138a62648f4019c55e4671682af1f851f295)
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# 
https://github.com/0day-ci/linux/commit/0311a8b0f99c50ab1a666a5cdbe2b1a0a2c3c71d
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review 
Matthew-Brost/drm-i915-guc-Don-t-check-CT-descriptor-status-before-CT-write-read/20220121-023033
git checkout 0311a8b0f99c50ab1a666a5cdbe2b1a0a2c3c71d
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 
O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c:469:1: warning: unused label 
>> 'corrupted' [-Wunused-label]
   corrupted:
   ^~
   1 warning generated.


vim +/corrupted +469 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c

f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  422  
1d407096002bec drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2018-03-26  423   /*
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  424* dw0: CT header (including fence)
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  425* dw1: HXG header (including action code)
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  426* dw2+: action data
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  427*/
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  428   header = FIELD_PREP(GUC_CTB_MSG_0_FORMAT, 
GUC_CTB_FORMAT_HXG) |
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  429FIELD_PREP(GUC_CTB_MSG_0_NUM_DWORDS, len) |
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  430FIELD_PREP(GUC_CTB_MSG_0_FENCE, fence);
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  431  
1681924d8bdeb2 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost
2021-07-08  432   type = (flags & INTEL_GUC_CT_SEND_NB) ? 
GUC_HXG_TYPE_EVENT :
1681924d8bdeb2 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost
2021-07-08  433   GUC_HXG_TYPE_REQUEST;
1681924d8bdeb2 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost
2021-07-08  434   hxg = FIELD_PREP(GUC_HXG_MSG_0_TYPE, type) |
1681924d8bdeb2 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost
2021-07-08  435   FIELD_PREP(GUC_HXG_EVENT_MSG_0_ACTION |
1681924d8bdeb2 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Matthew Brost
2021-07-08  436  GUC_HXG_EVENT_MSG_0_DATA0, action[0]);
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  437  
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  438   CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n",
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  439tail, 4, , 4, , 4 * (len - 1), 
[1]);
0a015ff9730c16 drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2018-03-26  440  
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  441   cmds[tail] = header;
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  442   tail = (tail + 1) % size;
f8a58d639dd95b drivers/gpu/drm/i915/intel_guc_ct.c   Michal Wajdeczko 
2017-05-26  443  
572f2a5cd9742c drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c Michal Wajdeczko 
2021-06-15  444   cmds[tail] = hxg;
f8a58d639dd95b dri

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Update guc shim control programming on newer platforms

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Update guc shim control programming on newer platforms
URL   : https://patchwork.freedesktop.org/series/99125/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_4_full -> Patchwork_22047_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_22047_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-apl:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24], [PASS][25]) -> ([FAIL][26], [PASS][27], [PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], 
[PASS][48], [PASS][49], [PASS][50]) ([i915#4386])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl8/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl8/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl8/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl8/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl8/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl7/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl7/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl6/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl6/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl6/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl6/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl4/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl4/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl3/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl3/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl3/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl2/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl2/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl2/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl1/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl1/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-apl1/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl1/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl1/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl1/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl1/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl2/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl2/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl2/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl3/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl3/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl3/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl4/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl4/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl4/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl4/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl6/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl6/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl6/boot.html
   [43]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/shard-apl6/boot.html
   [44]: 

Re: [Intel-gfx] [PATCH i-g-t] tests/i915/gem_exec_capture: Fix memory object size in gem_exec_capture

[Dixit, Ashutosh]

On Thu, 20 Jan 2022 17:09:28 -0800, john.c.harri...@intel.com wrote:
>
> From: John Harrison 
>
> The capture tests require knowing exactly how big the test allocation
> is. Part of the test is to compare the captured size against the
> allocated size to make sure they match. That doesn't work if the
> allocator creates an object of a different size than was requested
> without reporting the larger size.

Reviewed-by: Ashutosh Dixit 

> Fixes: 85a593809 ("tests/i915/gem_exec_capture: Add support for local memory")
> Signed-off-by: John Harrison 
> ---
>  tests/i915/gem_exec_capture.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/tests/i915/gem_exec_capture.c b/tests/i915/gem_exec_capture.c
> index 5b2482518..60f8df04c 100644
> --- a/tests/i915/gem_exec_capture.c
> +++ b/tests/i915/gem_exec_capture.c
> @@ -387,10 +387,9 @@ static void capture(int fd, int dir, const intel_ctx_t 
> *ctx,
>   const struct intel_execution_engine2 *e, uint32_t region)
>  {
>   uint32_t handle;
> - uint64_t ahnd;
> - int obj_size = 4096;
> + uint64_t ahnd, obj_size = 4096;
>
> - handle = gem_create_in_memory_regions(fd, obj_size, region);
> + igt_assert_eq(__gem_create_in_memory_regions(fd, , _size, 
> region), 0);
>   ahnd = get_reloc_ahnd(fd, ctx->id);
>
>   __capture1(fd, dir, ahnd, ctx, e, handle, obj_size, region);
> --
> 2.25.1
>

Re: [Intel-gfx] [PATCH 1/3] lib/string_helpers: Consolidate yesno() implementation

[Joe Perches]

On Wed, 2022-01-19 at 16:00 -0500, Steven Rostedt wrote:
> On Wed, 19 Jan 2022 21:25:08 +0200
> Andy Shevchenko  wrote:
> 
> > > I say keep it one line!
> > > 
> > > Reviewed-by: Steven Rostedt (Google)   
> > 
> > I believe Sakari strongly follows the 80 rule, which means...
> 
> Checkpatch says "100" I think we need to simply update the docs (the
> documentation always lags the code ;-)

checkpatch doesn't say anything normally, it's a stupid script.
It just mindlessly bleats a message when a line exceeds 100 chars...

Just fyi: I think it's nicer on a single line too.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Introduce G12 subplatform of DG2

[Patchwork]

== Series Details ==

Series: drm/i915: Introduce G12 subplatform of DG2
URL   : https://patchwork.freedesktop.org/series/99129/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5 -> Patchwork_22050


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/index.html

Participating hosts (42 -> 40)
--

  Additional (1): fi-pnv-d510 
  Missing(3): fi-bsw-cyan fi-bdw-samus fi-kbl-8809g 

Known issues


  Here are the changes found in Patchwork_22050 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-kefka:   [PASS][2] -> [INCOMPLETE][3] ([i915#2940])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gt_pm:
- fi-tgl-1115g4:  [PASS][4] -> [DMESG-FAIL][5] ([i915#3987])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html

  * igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][6] ([fdo#109271]) +57 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/fi-pnv-d510/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- fi-bsw-kefka:   NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#1436] / 
[i915#3428] / [i915#4312])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/fi-bsw-kefka/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@gtt:
- fi-bdw-5557u:   [DMESG-FAIL][8] -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-6:  [DMESG-FAIL][10] ([i915#4494]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-snb-2600:[INCOMPLETE][12] ([i915#3921]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494


Build changes
-

  * Linux: CI_DRM_5 -> Patchwork_22050

  CI-20190529: 20190529
  CI_DRM_5: 4e12213687264ffccb45d72fe638f94d3ca666bd @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6329: 38f656fdd61119105ecfa2c4dac157cd7dcad204 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22050: 74e47df4a75eeb545686e9fa91839afe29ed91ec @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

74e47df4a75e drm/i915: Introduce G12 subplatform of DG2

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22050/index.html

Re: [Intel-gfx] [PATCH 3/3] drm/i915/guc: Flush G2H handler during a GT reset

[John Harrison]

On 1/19/2022 13:24, Matthew Brost wrote:

Now that the error capture is fully decoupled from fence signalling
(request retirement to free memory, which in turn depends on resets) we
can safely flush the G2H handler during a GT reset. This is eliminates

This eliminates

John.


corner cases where GuC generated G2H (e.g. engine resets) race with a GT
reset.

v2:
  (John Harrison)
   - Fix typo in commit message (s/is/in)

Signed-off-by: Matthew Brost 
Reviewed-by: John Harrison 
---
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c  | 18 +-
  1 file changed, 1 insertion(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 514b3060b141..406dd2e3f5a9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1396,8 +1396,6 @@ static void guc_flush_destroyed_contexts(struct intel_guc 
*guc);
  
  void intel_guc_submission_reset_prepare(struct intel_guc *guc)

  {
-   int i;
-
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
return;
@@ -1414,21 +1412,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc 
*guc)
  
  	guc_flush_submissions(guc);

guc_flush_destroyed_contexts(guc);
-
-   /*
-* Handle any outstanding G2Hs before reset. Call IRQ handler directly
-* each pass as interrupt have been disabled. We always scrub for
-* outstanding G2H as it is possible for outstanding_submission_g2h to
-* be incremented after the context state update.
-*/
-   for (i = 0; i < 4 && atomic_read(>outstanding_submission_g2h); 
++i) {
-   intel_guc_to_host_event_handler(guc);
-#define wait_for_reset(guc, wait_var) \
-   intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20))
-   do {
-   wait_for_reset(guc, >outstanding_submission_g2h);
-   } while (!list_empty(>ct.requests.incoming));
-   }
+   flush_work(>ct.requests.worker);
  
  	scrub_guc_desc_for_outstanding_g2h(guc);

  }

Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Add work queue to trigger a GT reset

[John Harrison]

On 1/19/2022 13:24, Matthew Brost wrote:

The G2H handler needs to be flushed during a GT reset but a G2H
indicating engine reset failure can trigger a GT reset. Add a worker to
trigger the GT when an engine reset failure is received to break this

trigger the GT reset?


circular dependency.

v2:
  (John Harrison)
   - Store engine reset mask
   - Fix typo in commit message

Signed-off-by: Matthew Brost 
---
  drivers/gpu/drm/i915/gt/uc/intel_guc.h|  9 +
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +--
  2 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 9d26a86fe557..c4a9fc7dd246 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -119,6 +119,15 @@ struct intel_guc {
 * function as it might be in an atomic context (no sleeping)
 */
struct work_struct destroyed_worker;
+   /**
+* @reset_worker: worker to trigger a GT reset after an engine
+* reset fails
+*/
+   struct work_struct reset_worker;
+   /**
+* @reset_mask: mask of engines that failed to reset
+*/
+   intel_engine_mask_t reset_mask;
reset_fail_mask might be a less ambiguous name? Same for the worker 
struct and function.


John.


} submission_state;
  
  	/**

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 3918f1be114f..514b3060b141 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1731,6 +1731,7 @@ void intel_guc_submission_reset_finish(struct intel_guc 
*guc)
  }
  
  static void destroyed_worker_func(struct work_struct *w);

+static void reset_worker_func(struct work_struct *w);
  
  /*

   * Set up the memory resources to be shared with the GuC (via the GGTT)
@@ -1761,6 +1762,8 @@ int intel_guc_submission_init(struct intel_guc *guc)
INIT_LIST_HEAD(>submission_state.destroyed_contexts);
INIT_WORK(>submission_state.destroyed_worker,
  destroyed_worker_func);
+   INIT_WORK(>submission_state.reset_worker,
+ reset_worker_func);
  
  	guc->submission_state.guc_ids_bitmap =

bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
@@ -4026,6 +4029,26 @@ guc_lookup_engine(struct intel_guc *guc, u8 guc_class, 
u8 instance)
return gt->engine_class[engine_class][instance];
  }
  
+static void reset_worker_func(struct work_struct *w)

+{
+   struct intel_guc *guc = container_of(w, struct intel_guc,
+submission_state.reset_worker);
+   struct intel_gt *gt = guc_to_gt(guc);
+   intel_engine_mask_t reset_mask;
+   unsigned long flags;
+
+   spin_lock_irqsave(>submission_state.lock, flags);
+   reset_mask = guc->submission_state.reset_mask;
+   guc->submission_state.reset_mask = 0;
+   spin_unlock_irqrestore(>submission_state.lock, flags);
+
+   if (likely(reset_mask))
+   intel_gt_handle_error(gt, reset_mask,
+ I915_ERROR_CAPTURE,
+ "GuC failed to reset engine mask=0x%x\n",
+ reset_mask);
+}
+
  int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
 const u32 *msg, u32 len)
  {
@@ -4033,6 +4056,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc 
*guc,
struct intel_gt *gt = guc_to_gt(guc);
u8 guc_class, instance;
u32 reason;
+   unsigned long flags;
  
  	if (unlikely(len != 3)) {

drm_err(>i915->drm, "Invalid length %u", len);
@@ -4057,10 +4081,15 @@ int intel_guc_engine_failure_process_msg(struct 
intel_guc *guc,
drm_err(>i915->drm, "GuC engine reset request failed on %d:%d (%s) 
because 0x%08X",
guc_class, instance, engine->name, reason);
  
-	intel_gt_handle_error(gt, engine->mask,

- I915_ERROR_CAPTURE,
- "GuC failed to reset %s (reason=0x%08x)\n",
- engine->name, reason);
+   spin_lock_irqsave(>submission_state.lock, flags);
+   guc->submission_state.reset_mask |= engine->mask;
+   spin_unlock_irqrestore(>submission_state.lock, flags);
+
+   /*
+* A GT reset flushes this worker queue (G2H handler) so we must use
+* another worker to trigger a GT reset.
+*/
+   queue_work(system_unbound_wq, >submission_state.reset_worker);
  
  	return 0;

  }

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Introduce G12 subplatform of DG2

[Patchwork]

== Series Details ==

Series: drm/i915: Introduce G12 subplatform of DG2
URL   : https://patchwork.freedesktop.org/series/99129/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] [PATCH i-g-t] tests/i915/gem_exec_capture: Fix memory object size in gem_exec_capture

[John . C . Harrison]

From: John Harrison 

The capture tests require knowing exactly how big the test allocation
is. Part of the test is to compare the captured size against the
allocated size to make sure they match. That doesn't work if the
allocator creates an object of a different size than was requested
without reporting the larger size.

Fixes: 85a593809 ("tests/i915/gem_exec_capture: Add support for local memory")
Signed-off-by: John Harrison 
---
 tests/i915/gem_exec_capture.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/tests/i915/gem_exec_capture.c b/tests/i915/gem_exec_capture.c
index 5b2482518..60f8df04c 100644
--- a/tests/i915/gem_exec_capture.c
+++ b/tests/i915/gem_exec_capture.c
@@ -387,10 +387,9 @@ static void capture(int fd, int dir, const intel_ctx_t 
*ctx,
const struct intel_execution_engine2 *e, uint32_t region)
 {
uint32_t handle;
-   uint64_t ahnd;
-   int obj_size = 4096;
+   uint64_t ahnd, obj_size = 4096;
 
-   handle = gem_create_in_memory_regions(fd, obj_size, region);
+   igt_assert_eq(__gem_create_in_memory_regions(fd, , _size, 
region), 0);
ahnd = get_reloc_ahnd(fd, ctx->id);
 
__capture1(fd, dir, ahnd, ctx, e, handle, obj_size, region);
-- 
2.25.1

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Add Wa_18018781329

[Patchwork]

== Series Details ==

Series: drm/i915/dg2: Add Wa_18018781329
URL   : https://patchwork.freedesktop.org/series/99128/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5 -> Patchwork_22049


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22049 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22049, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22049/index.html

Participating hosts (42 -> 40)
--

  Missing(2): fi-bsw-cyan fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22049:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@execlists:
- fi-glk-j4005:   [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-glk-j4005/igt@i915_selftest@l...@execlists.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22049/fi-glk-j4005/igt@i915_selftest@l...@execlists.html

  
Known issues


  Here are the changes found in Patchwork_22049 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_flink_basic@bad-flink:
- fi-skl-6600u:   [PASS][3] -> [INCOMPLETE][4] ([i915#4547])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22049/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html

  * igt@runner@aborted:
- fi-skl-6600u:   NOTRUN -> [FAIL][5] ([i915#2722] / [i915#4312])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22049/fi-skl-6600u/igt@run...@aborted.html
- fi-glk-j4005:   NOTRUN -> [FAIL][6] ([i915#2722] / [i915#4312] / 
[k.org#202321])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22049/fi-glk-j4005/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@gtt:
- fi-bdw-5557u:   [DMESG-FAIL][7] -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22049/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Build changes
-

  * Linux: CI_DRM_5 -> Patchwork_22049

  CI-20190529: 20190529
  CI_DRM_5: 4e12213687264ffccb45d72fe638f94d3ca666bd @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6329: 38f656fdd61119105ecfa2c4dac157cd7dcad204 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22049: 3bb57af567ca7c35813b4f945576dbf573308408 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3bb57af567ca drm/i915/dg2: Add Wa_18018781329

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22049/index.html

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/wopcm: Handle pre-programmed WOPCM registers (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/wopcm: Handle pre-programmed WOPCM registers (rev3)
URL   : https://patchwork.freedesktop.org/series/98910/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_4_full -> Patchwork_22046_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_22046_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@engines-hang:
- shard-snb:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/shard-snb7/igt@gem_ctx_persiste...@engines-hang.html

  * igt@gem_eio@kms:
- shard-tglb: [PASS][2] -> [FAIL][3] ([i915#232])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-tglb6/igt@gem_...@kms.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/shard-tglb3/igt@gem_...@kms.html

  * igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][4] -> [SKIP][5] ([i915#4525]) +1 similar issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-iclb1/igt@gem_exec_balan...@parallel.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/shard-iclb6/igt@gem_exec_balan...@parallel.html

  * igt@gem_exec_endless@dispatch@vcs0:
- shard-tglb: [PASS][6] -> [INCOMPLETE][7] ([i915#3778])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-tglb7/igt@gem_exec_endless@dispa...@vcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/shard-tglb7/igt@gem_exec_endless@dispa...@vcs0.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/shard-tglb6/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  [PASS][10] -> [FAIL][11] ([i915#2842]) +2 similar 
issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/shard-kbl6/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk:  [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-glk2/igt@gem_exec_fair@basic-p...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/shard-glk5/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842]) +1 similar 
issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-iclb8/igt@gem_exec_fair@basic-p...@vcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/shard-iclb5/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2849])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_lmem_swapping@heavy-multi:
- shard-tglb: NOTRUN -> [SKIP][18] ([i915#4613])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/shard-tglb2/igt@gem_lmem_swapp...@heavy-multi.html

  * igt@gem_lmem_swapping@parallel-multi:
- shard-apl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/shard-apl2/igt@gem_lmem_swapp...@parallel-multi.html
- shard-kbl:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/shard-kbl6/igt@gem_lmem_swapp...@parallel-multi.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/shard-skl10/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_pread@exhaustion:
- shard-apl:  NOTRUN -> [WARN][22] ([i915#2658])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/shard-apl2/igt@gem_pr...@exhaustion.html
- shard-kbl:  NOTRUN -> [WARN][23] ([i915#2658])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/shard-kbl6/igt@gem_pr...@exhaustion.html

  * igt@gem_workarounds@suspend-resume-fd:
- shard-apl:  NOTRUN -> [DMESG-WARN][24] ([i915#180])
   [24]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg2: Add Wa_18018781329

[Patchwork]

== Series Details ==

Series: drm/i915/dg2: Add Wa_18018781329
URL   : https://patchwork.freedesktop.org/series/99128/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Splitting up platform-specific calls

[Patchwork]

== Series Details ==

Series: Splitting up platform-specific calls
URL   : https://patchwork.freedesktop.org/series/99126/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5 -> Patchwork_22048


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/index.html

Participating hosts (42 -> 42)
--

  Additional (2): bat-jsl-2 fi-pnv-d510 
  Missing(2): fi-bsw-cyan fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_22048 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html

  * igt@gem_flink_basic@bad-flink:
- fi-skl-6600u:   [PASS][2] -> [INCOMPLETE][3] ([i915#4547])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][4] -> [INCOMPLETE][5] ([i915#4785])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][6] ([fdo#109271]) +57 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/fi-pnv-d510/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- fi-skl-6600u:   NOTRUN -> [FAIL][7] ([i915#2722] / [i915#4312])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/fi-skl-6600u/igt@run...@aborted.html
- fi-hsw-4770:NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#1436] / 
[i915#4312])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/fi-hsw-4770/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rpls-1}:   [INCOMPLETE][9] ([i915#4898]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@gtt:
- fi-bdw-5557u:   [DMESG-FAIL][11] -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][13] ([i915#3921]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22048/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  

Re: [Intel-gfx] [PATCH] drm/i915: Add needs_compact_pt flag

[kernel test robot]

Hi Ramalingam,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next 
drm/drm-next next-20220120]
[cannot apply to tegra-drm/drm/tegra/for-next airlied/drm-next v5.16]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Add-needs_compact_pt-flag/20220121-002256
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a005 
(https://download.01.org/0day-ci/archive/20220121/202201210857.caeuyl4w-...@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 
f7b7138a62648f4019c55e4671682af1f851f295)
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# 
https://github.com/0day-ci/linux/commit/cf1a6660ac07b3b3618b35dccab57042d592ea2c
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review 
Ramalingam-C/drm-i915-Add-needs_compact_pt-flag/20220121-002256
git checkout cf1a6660ac07b3b3618b35dccab57042d592ea2c
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 
O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

   In file included from drivers/gpu/drm/i915/i915_config.c:6:
   In file included from drivers/gpu/drm/i915/i915_drv.h:83:
   In file included from drivers/gpu/drm/i915/gt/intel_engine.h:18:
   In file included from drivers/gpu/drm/i915/gt/intel_gt_types.h:18:
   In file included from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9:
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:19:
>> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h:12:2: error: embedding a #include 
>> directive within macro arguments is not supported
   #include "i915_gem.h"
^
   drivers/gpu/drm/i915/intel_device_info.h:201:25: note: expansion of macro 
'DEFINE_FLAG' requested here
   DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
  ^
   In file included from drivers/gpu/drm/i915/i915_config.c:6:
   In file included from drivers/gpu/drm/i915/i915_drv.h:83:
   In file included from drivers/gpu/drm/i915/gt/intel_engine.h:18:
   In file included from drivers/gpu/drm/i915/gt/intel_gt_types.h:18:
   In file included from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9:
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:19:
   drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h:13:2: error: embedding a #include 
directive within macro arguments is not supported
   #include "i915_vma.h"
^
   drivers/gpu/drm/i915/intel_device_info.h:201:25: note: expansion of macro 
'DEFINE_FLAG' requested here
   DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
  ^
   In file included from drivers/gpu/drm/i915/i915_config.c:6:
   In file included from drivers/gpu/drm/i915/i915_drv.h:83:
   In file included from drivers/gpu/drm/i915/gt/intel_engine.h:18:
   In file included from drivers/gpu/drm/i915/gt/intel_gt_types.h:18:
   In file included from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9:
>> drivers/gpu/drm/i915/gt/uc/intel_guc.h:20:2: error: embedding a #include 
>> directive within macro arguments is not supported
   #include "i915_utils.h"
^
   drivers/gpu/drm/i915/intel_device_info.h:201:25: note: expansion of macro 
'DEFINE_FLAG' requested here
   DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
  ^
   In file included from drivers/gpu/drm/i915/i915_config.c:6:
   In file included from drivers/gpu/drm/i915/i915_drv.h:83:
   In file included from drivers/gpu/drm/i915/gt/intel_engine.h:18:
   In file included from drivers/gpu/drm/i915/gt/intel_gt_types.h:18:
   In file included from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9:
   drivers/gpu/drm/i915/gt/uc/intel_guc.h:21:2: error: embedding a #include 
directive within macro arguments is not supported
   #include "i915_vma.h"
^
   drivers/gpu/drm/i915/intel_device_info.h:201:25: note: expansion of macro 
'DEFINE_FLAG' requested here
   DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
  ^
   In file included from drivers/gpu/drm/i915/i915_config.c:6:
   In file included from drivers/gpu/drm/i915/i915_drv.h:83:
   In file included from drivers/gpu/drm/i915/gt/intel_engine.h:18:
   In file included from drivers/gpu/drm/i915/gt/intel_gt_types.h:18:
>> drivers/gpu/drm/i915/gt/uc/intel_uc.h:10:2: error: embedding 

[Intel-gfx] ✓ Fi.CI.IGT: success for A few CT updates

[Patchwork]

== Series Details ==

Series: A few CT updates
URL   : https://patchwork.freedesktop.org/series/99117/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_4_full -> Patchwork_22044_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_22044_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@engines-hang:
- shard-snb:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/shard-snb4/igt@gem_ctx_persiste...@engines-hang.html

  * igt@gem_eio@in-flight-contexts-immediate:
- shard-tglb: [PASS][2] -> [TIMEOUT][3] ([i915#3063])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-tglb5/igt@gem_...@in-flight-contexts-immediate.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/shard-tglb3/igt@gem_...@in-flight-contexts-immediate.html

  * igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][4] -> [SKIP][5] ([i915#4525]) +1 similar issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-iclb1/igt@gem_exec_balan...@parallel.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/shard-iclb6/igt@gem_exec_balan...@parallel.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk:  [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-glk2/igt@gem_exec_fair@basic-p...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/shard-glk6/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-iclb8/igt@gem_exec_fair@basic-p...@vcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/shard-iclb6/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl:  [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar 
issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2849])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/shard-iclb8/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_suspend@basic-s3@smem:
- shard-apl:  NOTRUN -> [DMESG-WARN][14] ([i915#180])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/shard-apl4/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_exec_whisper@basic-contexts:
- shard-glk:  [PASS][15] -> [DMESG-WARN][16] ([i915#118]) +1 
similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/shard-glk6/igt@gem_exec_whis...@basic-contexts.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/shard-glk2/igt@gem_exec_whis...@basic-contexts.html

  * igt@gem_lmem_swapping@heavy-multi:
- shard-tglb: NOTRUN -> [SKIP][17] ([i915#4613])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/shard-tglb3/igt@gem_lmem_swapp...@heavy-multi.html

  * igt@gem_lmem_swapping@parallel-multi:
- shard-apl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/shard-apl6/igt@gem_lmem_swapp...@parallel-multi.html
- shard-kbl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/shard-kbl3/igt@gem_lmem_swapp...@parallel-multi.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/shard-skl9/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_pread@exhaustion:
- shard-apl:  NOTRUN -> [WARN][21] ([i915#2658])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/shard-apl6/igt@gem_pr...@exhaustion.html
- shard-kbl:  NOTRUN -> [WARN][22] ([i915#2658])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/shard-kbl3/igt@gem_pr...@exhaustion.html

  * igt@gen7_exec_parse@basic-offset:
- shard-apl:  NOTRUN -> [SKIP][23] ([fdo#109271]) +73 similar issues
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/shard-apl6/igt@gen7_exec_pa...@basic-offset.html

  * 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Splitting up platform-specific calls

[Patchwork]

== Series Details ==

Series: Splitting up platform-specific calls
URL   : https://patchwork.freedesktop.org/series/99126/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Splitting up platform-specific calls

[Patchwork]

== Series Details ==

Series: Splitting up platform-specific calls
URL   : https://patchwork.freedesktop.org/series/99126/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
cfedaf9b9519 i915/drm: Split out x86 and arm64 functionality
-:53: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#53: 
new file mode 100644

-:112: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#112: FILE: drivers/gpu/drm/i915/i915_platform_arm64.c:33:
+}
+/* End of i915_drv functionality */

-:151: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#151: FILE: drivers/gpu/drm/i915/i915_platform_x86.c:33:
+}
+/* End of i915_drv functionality */

total: 0 errors, 1 warnings, 2 checks, 110 lines checked

[Intel-gfx] [PATCH] drm/i915: Introduce G12 subplatform of DG2

[Matt Roper]

Another fork of the DG2 design has appeared, known as "DG2-G12;" let's
add it as a new subplatform.  As with G11, the GT stepping resets back
to A0 (so a DG2-G12 A0 is similar, but not identical, to a DG2-G10 C0)
but the display steppings continue to use the same numbering scheme as
G10 and G11.

Some existing DG2 workarounds are starting to be extended to the DG2-G12
subplatform.  So far only workarounds that were "permanent" for both
DG2-G10 and DG2-G11 have been tagged for DG2-G12, but more
stepping-specific workarounds are likely to show up in the future.

Bspec: 44477
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c |  2 +-
 drivers/gpu/drm/i915/i915_drv.h | 19 +++
 drivers/gpu/drm/i915/intel_device_info.h|  3 ++-
 drivers/gpu/drm/i915/intel_step.c   |  7 +++
 4 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6a4372c3a3c5..2d2e3ae9c997 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2077,7 +2077,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct 
i915_wa_list *wal)
}
 
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) ||
-   IS_DG2_G11(engine->i915)) {
+   IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) {
/* Wa_22013037850:dg2 */
wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
DISABLE_128B_EVICTION_COMMAND_UDW);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 890f1f6fbc49..a2fe5a0a7acd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1262,6 +1262,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
 #define IS_DG2_G11(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
+#define IS_DG2_G12(dev_priv) \
+   IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
 #define IS_ADLS_RPLS(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL_S)
 #define IS_ADLP_N(dev_priv) \
@@ -1378,16 +1380,17 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 
 /*
- * DG2 hardware steppings are a bit unusual.  The hardware design was forked
- * to create two variants (G10 and G11) which have distinct workaround sets.
- * The G11 fork of the DG2 design resets the GT stepping back to "A0" for its
- * first iteration, even though it's more similar to a G10 B0 stepping in terms
- * of functionality and workarounds.  However the display stepping does not
- * reset in the same manner --- a specific stepping like "B0" has a consistent
- * meaning regardless of whether it belongs to a G10 or G11 DG2.
+ * DG2 hardware steppings are a bit unusual.  The hardware design was forked to
+ * create three variants (G10, G11, and G12) which each have distinct
+ * workaround sets.  The G11 and G12 forks of the DG2 design reset the GT
+ * stepping back to "A0" for their first iterations, even though they're more
+ * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
+ * functionality and workarounds.  However the display stepping does not reset
+ * in the same manner --- a specific stepping like "B0" has a consistent
+ * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
  *
  * TLDR:  All GT workarounds and stepping-specific logic must be applied in
- * relation to a specific subplatform (G10 or G11), whereas display workarounds
+ * relation to a specific subplatform (G10/G11/G12), whereas display 
workarounds
  * and stepping-specific logic will be applied with a general DG2-wide stepping
  * number.
  */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 3699b1c539ea..364abcc7aa54 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -96,7 +96,7 @@ enum intel_platform {
  * it is fine for the same bit to be used on multiple parent platforms.
  */
 
-#define INTEL_SUBPLATFORM_BITS (2)
+#define INTEL_SUBPLATFORM_BITS (3)
 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
 
 /* HSW/BDW/SKL/KBL/CFL */
@@ -109,6 +109,7 @@ enum intel_platform {
 /* DG2 */
 #define INTEL_SUBPLATFORM_G10  0
 #define INTEL_SUBPLATFORM_G11  1
+#define INTEL_SUBPLATFORM_G12  2
 
 /* ADL-S */
 #define INTEL_SUBPLATFORM_RPL_S0
diff --git a/drivers/gpu/drm/i915/intel_step.c 
b/drivers/gpu/drm/i915/intel_step.c
index a4b16b9e2e55..46556883e93d 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -122,6 +122,10 @@ static const struct intel_step_info 
dg2_g11_revid_step_tbl[] = {
[0x5] = { COMMON_GT_MEDIA_STEP(B1), 

[Intel-gfx] [PATCH] drm/i915/dg2: Add Wa_18018781329

[Matt Roper]

A few more MOD registers need to be programmed on DG2.

Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
 drivers/gpu/drm/i915/i915_reg.h | 4 
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6a4372c3a3c5..748b2daf043f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1509,6 +1509,12 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
 */
wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS);
+
+   /* Wa_18018781329:dg2 */
+   wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
+   wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
+   wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
+   wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 460bce5c544d..d587257f392a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -339,6 +339,10 @@
 #define   TAG_BLOCK_CLKGATE_DISREG_BIT(7)
 
 #define GEN12_MERT_MOD_CTRL_MMIO(0xcf28)
+#define RENDER_MOD_CTRL_MMIO(0xcf2c)
+#define COMP_MOD_CTRL  _MMIO(0xcf30)
+#define VDBX_MOD_CTRL  _MMIO(0xcf34)
+#define VEBX_MOD_CTRL  _MMIO(0xcf38)
 #define   FORCE_MISS_FTLB  REG_BIT(3)
 
 #define GAB_CTL_MMIO(0x24000)
-- 
2.34.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Update guc shim control programming on newer platforms

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Update guc shim control programming on newer platforms
URL   : https://patchwork.freedesktop.org/series/99125/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_4 -> Patchwork_22047


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/index.html

Participating hosts (42 -> 40)
--

  Additional (3): bat-rpls-1 bat-jsl-2 fi-ilk-650 
  Missing(5): bat-dg1-5 fi-bsw-cyan bat-adlp-4 fi-pnv-d510 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_22047 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_cs_nop@nop-compute0:
- fi-ilk-650: NOTRUN -> [SKIP][1] ([fdo#109271]) +39 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/fi-ilk-650/igt@amdgpu/amd_cs_...@nop-compute0.html

  * igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u:   NOTRUN -> [FAIL][2] ([i915#4547])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-ilk-650: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- fi-bwr-2160:[FAIL][4] ([i915#3194]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/fi-bwr-2160/igt@core_hotunp...@unbind-rebind.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/fi-bwr-2160/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_exec_suspend@basic-s0@smem:
- fi-tgl-1115g4:  [FAIL][6] ([i915#1888]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html

  
 Warnings 

  * igt@runner@aborted:
- fi-skl-6600u:   [FAIL][8] ([i915#2722] / [i915#4312]) -> [FAIL][9] 
([i915#4312])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/fi-skl-6600u/igt@run...@aborted.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/fi-skl-6600u/igt@run...@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-

  * Linux: CI_DRM_4 -> Patchwork_22047

  CI-20190529: 20190529
  CI_DRM_4: 95f7fe1c9f81eff6c3faab2a73ccaca51440f73c @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6329: 38f656fdd61119105ecfa2c4dac157cd7dcad204 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22047: 0b46254f664d19c7e35b04e09c35b6a205f3825d @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

0b46254f664d drm/i915/guc: Update guc shim control programming on newer 
platforms

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22047/index.html

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc: Update guc shim control programming on newer platforms

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Update guc shim control programming on newer platforms
URL   : https://patchwork.freedesktop.org/series/99125/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
0b46254f664d drm/i915/guc: Update guc shim control programming on newer 
platforms
-:7: WARNING:REPEATED_WORD: Possible repeated word: 'of'
#7: 
Starting from xehpsdv, bit 0 of of the GuC shim control register has

total: 0 errors, 1 warnings, 0 checks, 18 lines checked

[Intel-gfx] [RFC PATCH 1/1] i915/drm: Split out x86 and arm64 functionality

[Casey Bowman]

Some x86 checks are unnecessary on arm64 systems, so they
are being split out to avoid being used. There may be
further arm64 implementations created in the future for
this area, so it's better to split this out now.

Signed-off-by: Casey Bowman 
---
 drivers/gpu/drm/i915/Makefile  |  4 +++
 drivers/gpu/drm/i915/i915_drv.h|  6 +---
 drivers/gpu/drm/i915/i915_platform.h   | 16 +++
 drivers/gpu/drm/i915/i915_platform_arm64.c | 33 ++
 drivers/gpu/drm/i915/i915_platform_x86.c   | 33 ++
 5 files changed, 87 insertions(+), 5 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_platform.h
 create mode 100644 drivers/gpu/drm/i915/i915_platform_arm64.c
 create mode 100644 drivers/gpu/drm/i915/i915_platform_x86.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 213c5f9fae32..dd66fe57934d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -320,6 +320,10 @@ i915-y += intel_gvt.o
 include $(src)/gvt/Makefile
 endif
 
+# Architecture-specific calls
+i915-$(CONFIG_X86)   += i915_platform_x86.o
+i915-$(CONFIG_ARM64) += i915_platform_arm64.o
+
 obj-$(CONFIG_DRM_I915) += i915.o
 obj-$(CONFIG_DRM_I915_GVT_KVMGT) += gvt/kvmgt.o
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 290dfd40c7b3..e688270c8257 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -107,6 +107,7 @@
 #include "gt/intel_timeline.h"
 #include "i915_vma.h"
 
+#include "i915_platform.h"
 
 /* General customization:
  */
@@ -1543,11 +1544,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define INTEL_DISPLAY_ENABLED(dev_priv) \
(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), 
!(dev_priv)->params.disable_display)
 
-static inline bool run_as_guest(void)
-{
-   return !hypervisor_is_type(X86_HYPER_NATIVE);
-}
-
 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
  IS_ALDERLAKE_S(dev_priv))
 
diff --git a/drivers/gpu/drm/i915/i915_platform.h 
b/drivers/gpu/drm/i915/i915_platform.h
new file mode 100644
index ..300f93d20f58
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_platform.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef _I915_PLATFORM_
+#define _I915_PLATFORM_
+
+#include 
+#include 
+
+/* Start of i915_drv functionality */
+bool run_as_guest(void);
+/* End of i915_drv functionality */
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_platform_arm64.c 
b/drivers/gpu/drm/i915/i915_platform_arm64.c
new file mode 100644
index ..95692c4dc75f
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_platform_arm64.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+/*
+ * Read before adding/removing content!
+ *
+ * Ensure that all functions defined here are also defined
+ * in the i915_platform_x86.c file.
+ *
+ * If the function is a dummy function, be sure to add
+ * a DRM_WARN() call to note that the function is a
+ * dummy function to users so that we can better track
+ * any issues that arise due to changes in either file.
+ *
+ * Also be sure to label Start/End of sections where
+ * functions originate from. These files will host
+ * architecture-specific content from a myriad of files,
+ * labeling the sections will help devs keep track of
+ * where the calls interact.
+ */
+
+#include "i915_platform.h"
+
+/* Start of i915_drv functionality */
+/* Intel VT-d is not used on ARM64 systems */
+bool run_as_guest(void)
+{
+   WARN(1, "%s not supported on arm64 platforms.", __func__);
+   return false;
+}
+/* End of i915_drv functionality */
diff --git a/drivers/gpu/drm/i915/i915_platform_x86.c 
b/drivers/gpu/drm/i915/i915_platform_x86.c
new file mode 100644
index ..9a7174ad2147
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_platform_x86.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+/*
+ * Read before adding/removing content!
+ *
+ * Ensure that all functions defined here are also defined
+ * in the i915_platform_arm64.c file.
+ *
+ * If the function is a dummy function, be sure to add
+ * a DRM_WARN() call to note that the function is a
+ * dummy function to users so that we can better track
+ * any issues that arise due to changes in either file.
+ *
+ * Also be sure to label Start/End of sections where
+ * functions originate from. These files will host
+ * architecture-specific content from a myriad of files,
+ * labeling the sections will help devs keep track of
+ * where the calls interact.
+ */
+
+#include "i915_platform.h"
+
+#include 
+
+/* Start of i915_drv functionality */
+bool run_as_guest(void)
+{
+   return !hypervisor_is_type(X86_HYPER_NATIVE);
+}
+/* End of i915_drv functionality */
-- 
2.25.1

[Intel-gfx] [RFC PATCH 0/1] Splitting up platform-specific calls

[Casey Bowman]

In this RFC I would like to ask the community their thoughts
on how we can best handle splitting architecture-specific
calls.

I would like to address the following:

1. How do we want to split architecture calls? Different object files
per platform? Separate function calls within the same object file?

2. How do we address dummy functions? If we have a function call that is
used for one or more platforms, but is not used in another, what should
we do for this case?

I've given an example of splitting an architecture call
in my patch with run_as_guest() being split into different
implementations for x86 and arm64 in separate object files, sharing
a single header.

Another suggestion from Michael (michael.ch...@intel.com) involved
using a single object file, a single header, and splitting various
functions calls via ifdefs in the header file.

I would appreciate any input on how we can avoid scaling issues when
including multiple architectures and multiple functions (as the number
of function calls will inevitably increase with more architectures).

Casey Bowman (1):
  i915/drm: Split out x86 and arm64 functionality

 drivers/gpu/drm/i915/Makefile  |  4 +++
 drivers/gpu/drm/i915/i915_drv.h|  6 +---
 drivers/gpu/drm/i915/i915_platform.h   | 16 +++
 drivers/gpu/drm/i915/i915_platform_arm64.c | 33 ++
 drivers/gpu/drm/i915/i915_platform_x86.c   | 33 ++
 5 files changed, 87 insertions(+), 5 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_platform.h
 create mode 100644 drivers/gpu/drm/i915/i915_platform_arm64.c
 create mode 100644 drivers/gpu/drm/i915/i915_platform_x86.c

-- 
2.25.1

[Intel-gfx] [PATCH] drm/i915/guc: Update guc shim control programming on newer platforms

[Daniele Ceraolo Spurio]

Starting from xehpsdv, bit 0 of of the GuC shim control register has
been repurposed, while bit 2 is now reserved, so we need to avoid
setting those for their old meaning on newer platforms.

Cc: Vinay Belgaumkar 
Cc: Stuart Summers 
Signed-off-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index f773e7f35bc1a..40f7d4779c9ec 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -15,13 +15,15 @@
 
 static void guc_prepare_xfer(struct intel_uncore *uncore)
 {
-   u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
-GUC_ENABLE_READ_CACHE_LOGIC |
-GUC_ENABLE_MIA_CACHING |
+   u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC |
 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
 GUC_ENABLE_MIA_CLOCK_GATING;
 
+   if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 50))
+   shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |
+ GUC_ENABLE_MIA_CACHING;
+
/* Must program this register before loading the ucode with DMA */
intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
 
-- 
2.25.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/wopcm: Handle pre-programmed WOPCM registers (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/wopcm: Handle pre-programmed WOPCM registers (rev3)
URL   : https://patchwork.freedesktop.org/series/98910/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_4 -> Patchwork_22046


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_22046 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22046, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/index.html

Participating hosts (42 -> 40)
--

  Additional (3): bat-rpls-1 bat-jsl-2 fi-ilk-650 
  Missing(5): bat-dg1-5 fi-bsw-cyan bat-adlp-4 fi-pnv-d510 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22046:

### IGT changes ###

 Warnings 

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-6:  [DMESG-FAIL][1] ([i915#4494]) -> [DMESG-FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html

  
Known issues


  Here are the changes found in Patchwork_22046 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_cs_nop@nop-compute0:
- fi-ilk-650: NOTRUN -> [SKIP][3] ([fdo#109271]) +39 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/fi-ilk-650/igt@amdgpu/amd_cs_...@nop-compute0.html

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u:   [PASS][4] -> [INCOMPLETE][5] ([i915#4547])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-ilk-650: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2:  [PASS][7] -> [DMESG-WARN][8] ([i915#4269])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- fi-bwr-2160:[FAIL][9] ([i915#3194]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/fi-bwr-2160/igt@core_hotunp...@unbind-rebind.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/fi-bwr-2160/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-tgl-1115g4:  [FAIL][11] ([i915#1888]) -> [PASS][12] +1 similar 
issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22046/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-

  * Linux: CI_DRM_4 -> Patchwork_22046

  CI-20190529: 20190529
  CI_DRM_4: 95f7fe1c9f81eff6c3faab2a73ccaca51440f73c @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6329: 38f656fdd61119105ecfa2c4dac157cd7dcad204 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22046: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/wopcm: Handle pre-programmed WOPCM registers (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/wopcm: Handle pre-programmed WOPCM registers (rev3)
URL   : https://patchwork.freedesktop.org/series/98910/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/wopcm: Handle pre-programmed WOPCM registers (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/wopcm: Handle pre-programmed WOPCM registers (rev3)
URL   : https://patchwork.freedesktop.org/series/98910/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
0abf9917c5c0 drm/i915/wopcm: Handle pre-programmed WOPCM registers
-:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#14: 
sometimes using a smaller WOPCM size that the actual HW support (which isn't

-:39: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#39: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h:98:
+#define   GUC_IS_PRIVILEGED(1<<29)
  ^

total: 0 errors, 1 warnings, 1 checks, 120 lines checked

[Intel-gfx] [CI] drm/i915/wopcm: Handle pre-programmed WOPCM registers

[Daniele Ceraolo Spurio]

Starting from DG2, some of the programming previously done by i915 and
the GuC has been moved to the GSC and the relevant registers are no
longer writable by either CPU or GuC. This is also referred to as GuC
deprivilege.
On the i915 side, this affects the WOPCM registers: these are no longer
programmed by the driver and we do instead expect to find them already
set. This can lead to verification failures because in i915 we cheat a bit
with the WOPCM size defines, to keep the code common across platforms, by
sometimes using a smaller WOPCM size that the actual HW support (which isn't
a problem because the extra size is not needed if the FW fits in the smaller
chunk), while the pre-programmed values can use the actual size.
Given tha the new programming entity is trusted, relax the amount of the
checks done on the pre-programmed values by not limiting the max
programmed size. In the extremely unlikely scenario that the registers
have been misprogrammed, we will still fail later at DMA time.

v2: drop special case for DG2 G10 A0 (Alan)

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Stuart Summers 
Cc: John Harrison 
Cc: Alan Previn 
Reviewed-by Alan Previn 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h |  3 ++
 drivers/gpu/drm/i915/i915_drv.h|  3 ++
 drivers/gpu/drm/i915/i915_pci.c|  1 +
 drivers/gpu/drm/i915/intel_device_info.h   |  1 +
 drivers/gpu/drm/i915/intel_wopcm.c | 42 ++
 5 files changed, 43 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
index e6bd66d6ce5a..cdb47c2291c8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
@@ -94,6 +94,9 @@
 #define   GUC_ENABLE_MIA_CLOCK_GATING  (1<<15)
 #define   GUC_GEN10_SHIM_WC_ENABLE (1<<21)
 
+#define GUC_SHIM_CONTROL2  _MMIO(0xc068)
+#define   GUC_IS_PRIVILEGED(1<<29)
+
 #define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
 #define   GUC_SEND_TRIGGER   (1<<0)
 #define GEN11_GUC_HOST_INTERRUPT   _MMIO(0x1901f0)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 890f1f6fbc49..0ba820ec4e49 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1557,6 +1557,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define INTEL_DISPLAY_ENABLED(dev_priv) \
(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), 
!(dev_priv)->params.disable_display)
 
+#define HAS_GUC_DEPRIVILEGE(dev_priv) \
+   (INTEL_INFO(dev_priv)->has_guc_deprivilege)
+
 static inline bool run_as_guest(void)
 {
return !hypervisor_is_type(X86_HYPER_NATIVE);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8261b6455747..983546d5f415 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1045,6 +1045,7 @@ static const struct intel_device_info dg2_info = {
.graphics.rel = 55,
.media.rel = 55,
PLATFORM(INTEL_DG2),
+   .has_guc_deprivilege = 1,
.has_64k_pages = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 3699b1c539ea..abf1e103c558 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -134,6 +134,7 @@ enum intel_ppgtt_type {
func(has_reset_engine); \
func(has_global_mocs); \
func(has_gt_uc); \
+   func(has_guc_deprivilege); \
func(has_l3_dpf); \
func(has_llc); \
func(has_logical_ring_contexts); \
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c 
b/drivers/gpu/drm/i915/intel_wopcm.c
index f06d21005106..322fb9eeb880 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -43,6 +43,7 @@
 /* Default WOPCM size is 2MB from Gen11, 1MB on previous platforms */
 #define GEN11_WOPCM_SIZE   SZ_2M
 #define GEN9_WOPCM_SIZESZ_1M
+#define MAX_WOPCM_SIZE SZ_8M
 /* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */
 #define WOPCM_RESERVED_SIZESZ_16K
 
@@ -207,6 +208,14 @@ static bool __wopcm_regs_locked(struct intel_uncore 
*uncore,
return true;
 }
 
+static bool __wopcm_regs_writable(struct intel_uncore *uncore)
+{
+   if (!HAS_GUC_DEPRIVILEGE(uncore->i915))
+   return true;
+
+   return intel_uncore_read(uncore, GUC_SHIM_CONTROL2) & GUC_IS_PRIVILEGED;
+}
+
 /**
  * intel_wopcm_init() - Initialize the WOPCM structure.
  * @wopcm: pointer to intel_wopcm.
@@ -224,18 +233,19 @@ void intel_wopcm_init(struct intel_wopcm *wopcm)
u32 guc_fw_size = intel_uc_fw_get_upload_size(>uc.guc.fw);
u32 huc_fw_size = intel_uc_fw_get_upload_size(>uc.huc.fw);
u32 ctx_rsvd = context_reserved_size(i915);
+   

[Intel-gfx] ✗ Fi.CI.BAT: failure for discrete card 64K page support

[Patchwork]

== Series Details ==

Series: discrete card 64K page support
URL   : https://patchwork.freedesktop.org/series/99119/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_4 -> Patchwork_22045


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22045 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22045, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/index.html

Participating hosts (42 -> 45)
--

  Additional (5): fi-kbl-soraka bat-adls-5 fi-ilk-650 bat-rpls-1 bat-jsl-2 
  Missing(2): fi-bsw-cyan fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22045:

### IGT changes ###

 Possible regressions 

  * igt@runner@aborted:
- fi-rkl-11600:   NOTRUN -> [FAIL][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/fi-rkl-11600/igt@run...@aborted.html
- bat-dg1-5:  NOTRUN -> [FAIL][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/bat-dg1-5/igt@run...@aborted.html
- fi-bwr-2160:NOTRUN -> [FAIL][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/fi-bwr-2160/igt@run...@aborted.html
- fi-hsw-4770:NOTRUN -> [FAIL][4]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/fi-hsw-4770/igt@run...@aborted.html
- bat-dg1-6:  NOTRUN -> [FAIL][5]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/bat-dg1-6/igt@run...@aborted.html

  
 Warnings 

  * igt@runner@aborted:
- bat-adlp-4: [FAIL][6] ([i915#4312]) -> [FAIL][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/bat-adlp-4/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/bat-adlp-4/igt@run...@aborted.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@runner@aborted:
- {bat-adls-5}:   NOTRUN -> [FAIL][8]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/bat-adls-5/igt@run...@aborted.html
- {bat-adlp-6}:   [FAIL][9] ([i915#4312]) -> [FAIL][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/bat-adlp-6/igt@run...@aborted.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/bat-adlp-6/igt@run...@aborted.html
- {bat-jsl-2}:NOTRUN -> [FAIL][11]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/bat-jsl-2/igt@run...@aborted.html
- {fi-jsl-1}: NOTRUN -> [FAIL][12]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/fi-jsl-1/igt@run...@aborted.html
- {bat-jsl-1}:NOTRUN -> [FAIL][13]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/bat-jsl-1/igt@run...@aborted.html
- {fi-ehl-2}: NOTRUN -> [FAIL][14]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/fi-ehl-2/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_22045 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@runner@aborted:
- fi-snb-2600:NOTRUN -> [FAIL][15] ([i915#2426])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/fi-snb-2600/igt@run...@aborted.html
- fi-ilk-650: NOTRUN -> [FAIL][16] ([i915#2426])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/fi-ilk-650/igt@run...@aborted.html
- fi-pnv-d510:NOTRUN -> [FAIL][17] ([i915#2403])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/fi-pnv-d510/igt@run...@aborted.html
- fi-kbl-x1275:   NOTRUN -> [FAIL][18] ([i915#2426])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/fi-kbl-x1275/igt@run...@aborted.html
- fi-bsw-kefka:   NOTRUN -> [FAIL][19] ([i915#3690])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/fi-bsw-kefka/igt@run...@aborted.html
- fi-bdw-gvtdvm:  NOTRUN -> [FAIL][20] ([i915#2426])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/fi-bdw-gvtdvm/igt@run...@aborted.html
- fi-cfl-8700k:   NOTRUN -> [FAIL][21] ([i915#2426])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/fi-cfl-8700k/igt@run...@aborted.html
- fi-cfl-8109u:   NOTRUN -> [FAIL][22] ([i915#2426])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/fi-cfl-8109u/igt@run...@aborted.html
- fi-glk-dsi: NOTRUN -> [FAIL][23] ([i915#2426] / [k.org#202321])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22045/fi-glk-dsi/igt@run...@aborted.html
- fi-bsw-nick: 

[Intel-gfx] ✓ Fi.CI.BAT: success for A few CT updates

[Patchwork]

== Series Details ==

Series: A few CT updates
URL   : https://patchwork.freedesktop.org/series/99117/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_4 -> Patchwork_22044


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/index.html

Participating hosts (42 -> 36)
--

  Additional (2): fi-kbl-soraka fi-ilk-650 
  Missing(8): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-adlp-4 
fi-pnv-d510 fi-bdw-samus bat-jsl-1 

Known issues


  Here are the changes found in Patchwork_22044 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_cs_nop@nop-compute0:
- fi-ilk-650: NOTRUN -> [SKIP][1] ([fdo#109271]) +39 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/fi-ilk-650/igt@amdgpu/amd_cs_...@nop-compute0.html

  * igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-skl-6600u:   NOTRUN -> [SKIP][2] ([fdo#109271]) +21 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271]) +8 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-skl-6600u:   NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u:   NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][8] ([i915#1886] / [i915#2291])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][9] -> [INCOMPLETE][10] ([i915#3303])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- fi-snb-2600:[PASS][11] -> [INCOMPLETE][12] ([i915#3921])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka:  NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-ilk-650: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u:   NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2:  [PASS][16] -> [DMESG-WARN][17] ([i915#4269])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u:   NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#533])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#533])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22044/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][20] ([fdo#109271] / [i915#1436] / 
[i915#4312])
   [20]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for discrete card 64K page support

[Patchwork]

== Series Details ==

Series: discrete card 64K page support
URL   : https://patchwork.freedesktop.org/series/99119/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for discrete card 64K page support

[Patchwork]

== Series Details ==

Series: discrete card 64K page support
URL   : https://patchwork.freedesktop.org/series/99119/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
2ad66084bf0b drm/i915: add needs_compact_pt flag
f2a348f85370 drm/i915: enforce min GTT alignment for discrete cards
-:288: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code 
refactoring
#288: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:457:
+   if (offset < hole_start + 
aligned_size)

-:300: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code 
refactoring
#300: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:481:
+   if (offset + aligned_size > 
hole_end)

-:318: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code 
refactoring
#318: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:497:
+   if (offset < hole_start + 
aligned_size)

-:330: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code 
refactoring
#330: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:520:
+   if (offset + aligned_size > 
hole_end)

-:348: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code 
refactoring
#348: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:536:
+   if (offset < hole_start + 
aligned_size)

-:360: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code 
refactoring
#360: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:560:
+   if (offset + aligned_size > 
hole_end)

-:378: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code 
refactoring
#378: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:576:
+   if (offset < hole_start + 
aligned_size)

-:390: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code 
refactoring
#390: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:599:
+   if (offset + aligned_size > 
hole_end)

total: 0 errors, 8 warnings, 0 checks, 433 lines checked
e270ed3aae8a drm/i915: support 64K GTT pages for discrete cards
3ccd33b30eb1 drm/i915: add gtt misalignment test
-:157: CHECK:LINE_SPACING: Please don't use multiple blank lines
#157: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:1260:
+
+

-:170: CHECK:LINE_SPACING: Please don't use multiple blank lines
#170: FILE: drivers/gpu/drm/i915/selftests/i915_gem_gtt.c:1338:
+
+

total: 0 errors, 0 warnings, 2 checks, 170 lines checked
5b1165701d6d drm/i915/uapi: document behaviour for DG2 64K support

Re: [Intel-gfx] [PATCH] drm/i915: Lock timeline mutex directly in error path of eb_pin_timeline

[John Harrison]

On 1/11/2022 08:39, Matthew Brost wrote:

Don't use the interruptable version of the timeline mutex lock in the
error path of eb_pin_timeline as the cleanup must always happen.

v2:
  (John Harrison)
   - Don't check for interrupt during mutex lock
v3:
  (Tvrtko)
   - A comment explaining why lock helper isn't used

Fixes: 544460c33821 ("drm/i915: Multi-BB execbuf")
Signed-off-by: Matthew Brost 

Reviewed-by: John Harrison 


---
  drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 9 +++--
  1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 9e221ce427075..4a611d62e991a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2518,9 +2518,14 @@ static int eb_pin_timeline(struct i915_execbuffer *eb, 
struct intel_context *ce,
  timeout) < 0) {
i915_request_put(rq);
  
-			tl = intel_context_timeline_lock(ce);

+   /*
+* Error path, cannot use intel_context_timeline_lock as
+* that is user interruptable and this clean up step
+* must be done.
+*/
+   mutex_lock(>timeline->mutex);
intel_context_exit(ce);
-   intel_context_timeline_unlock(tl);
+   mutex_unlock(>timeline->mutex);
  
  			if (nonblock)

return -EWOULDBLOCK;

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Don't restart WL for every frequency step

[Belgaumkar, Vinay]

On 1/20/2022 11:40 AM, Patchwork wrote:

Project List - Patchwork *Patch Details*
*Series:*   drm/i915/selftests: Don't restart WL for every frequency step
*URL:*  https://patchwork.freedesktop.org/series/99109/
*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22043/index.html



  CI Bug Log - changes from CI_DRM_3 -> Patchwork_22043


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_22043 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22043, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives 
in CI.


External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22043/index.html



Participating hosts (43 -> 35)

Additional (3): fi-kbl-soraka fi-kbl-guc fi-apl-guc
Missing (11): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-adlp-4 
fi-kbl-8809g fi-pnv-d510 bat-rpls-1 fi-bdw-samus bat-jsl-2 bat-jsl-1



Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_22043:



  IGT changes


Possible regressions

  * igt@i915_selftest@live@gt_engines:
  o fi-rkl-guc: PASS


-> INCOMPLETE



This failure is not related to the patch. It only changes a selftest, so 
shouldn't affect any other test.


Thanks,

Vinay.


 *


Known issues

Here are the changes found in Patchwork_22043 that come from known issues:


  IGT changes


Issues hit

 *

igt@debugfs_test@read_all_entries:

  o fi-apl-guc: NOTRUN -> DMESG-WARN


(i915#1610 )
 *

igt@gem_exec_fence@basic-busy@bcs0:

  o fi-kbl-soraka: NOTRUN -> SKIP


(fdo#109271
) +8
similar issues
 *

igt@gem_exec_suspend@basic-s3@smem:

  o fi-skl-6600u: PASS


-> INCOMPLETE


(i915#4547 )
 *

igt@gem_huc_copy@huc-copy:

  o fi-kbl-soraka: NOTRUN -> SKIP


(fdo#109271
 /
i915#2190 )
 *

igt@gem_lmem_swapping@basic:

 o

fi-kbl-guc: NOTRUN -> SKIP


(fdo#109271
 /
i915#4613
) +3
similar issues

 o

fi-kbl-soraka: NOTRUN -> SKIP


(fdo#109271
 /
i915#4613
) +3
similar issues

 *

igt@i915_selftest@live@gt_pm:

  o fi-kbl-soraka: NOTRUN -> DMESG-FAIL


(i915#1886
 /
i915#2291 )
 *

igt@i915_selftest@live@hangcheck:

  o fi-snb-2600: PASS


-> INCOMPLETE


(i915#3921 )
 *

igt@kms_busy@basic:

  o fi-kbl-guc: NOTRUN -> SKIP


(fdo#109271
 /
i915#1845 )
 *

[Intel-gfx] [GIT PULL] PCI fixes for v5.17

[Bjorn Helgaas]

The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf:

  Linux 5.16-rc1 (2021-11-14 13:56:52 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git 
tags/pci-v5.17-fixes-1

for you to fetch changes up to 9c494ca4d3a535f9ca11ad6af1813983c1c6cbdd:

  x86/gpu: Reserve stolen memory for first integrated Intel GPU (2022-01-18 
14:19:06 -0600)


PCI fixes:

  - Reserve "stolen memory" for integrated Intel GPU, even if it's not
the first GPU to be enumerated (Lucas De Marchi)


Lucas De Marchi (1):
  x86/gpu: Reserve stolen memory for first integrated Intel GPU

 arch/x86/kernel/early-quirks.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

[Intel-gfx] [PATCH v3 4/5] drm/i915: add gtt misalignment test

[Robert Beckett]

add test to check handling of misaligned offsets and sizes

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 130 ++
 1 file changed, 130 insertions(+)

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 2f3f0c01786b..76696a5e547e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -22,10 +22,12 @@
  *
  */
 
+#include "gt/intel_gtt.h"
 #include 
 #include 
 
 #include "gem/i915_gem_context.h"
+#include "gem/i915_gem_region.h"
 #include "gem/selftests/mock_context.h"
 #include "gt/intel_context.h"
 #include "gt/intel_gpu_commands.h"
@@ -1067,6 +1069,120 @@ static int shrink_boom(struct i915_address_space *vm,
return err;
 }
 
+static int misaligned_case(struct i915_address_space *vm, struct 
intel_memory_region *mr,
+  u64 addr, u64 size, unsigned long flags)
+{
+   struct drm_i915_gem_object *obj;
+   struct i915_vma *vma;
+   int err = 0;
+   u64 expected_vma_size, expected_node_size;
+
+   obj = i915_gem_object_create_region(mr, size, 0, 0);
+   if (IS_ERR(obj))
+   return PTR_ERR(obj);
+
+   vma = i915_vma_instance(obj, vm, NULL);
+   if (IS_ERR(vma)) {
+   err = PTR_ERR(vma);
+   goto err_put;
+   }
+
+   err = i915_vma_pin(vma, 0, 0, addr | flags);
+   if (err)
+   goto err_put;
+   i915_vma_unpin(vma);
+
+   if (!drm_mm_node_allocated(>node)) {
+   err = -EINVAL;
+   goto err_put;
+   }
+
+   if (i915_vma_misplaced(vma, 0, 0, addr | flags)) {
+   err = -EINVAL;
+   goto err_put;
+   }
+
+   expected_vma_size = round_up(size, 1 << 
(ffs(vma->resource->page_sizes_gtt) - 1));
+   expected_node_size = expected_vma_size;
+
+   if (IS_DG2(vm->i915) && i915_gem_object_is_lmem(obj)) {
+   /* dg2 should expand lmem node to 2MB */
+   expected_vma_size = round_up(size, I915_GTT_PAGE_SIZE_64K);
+   expected_node_size = round_up(size, I915_GTT_PAGE_SIZE_2M);
+   }
+
+   if (vma->size != expected_vma_size || vma->node.size != 
expected_node_size) {
+   err = i915_vma_unbind(vma);
+   err = -EBADSLT;
+   goto err_put;
+   }
+
+   err = i915_vma_unbind(vma);
+   if (err)
+   goto err_put;
+
+   GEM_BUG_ON(drm_mm_node_allocated(>node));
+
+err_put:
+   i915_gem_object_put(obj);
+   cleanup_freed_objects(vm->i915);
+   return err;
+}
+
+static int misaligned_pin(struct i915_address_space *vm,
+ u64 hole_start, u64 hole_end,
+ unsigned long end_time)
+{
+   struct intel_memory_region *mr;
+   enum intel_region_id id;
+   unsigned long flags = PIN_OFFSET_FIXED | PIN_USER;
+   int err = 0;
+   u64 hole_size = hole_end - hole_start;
+
+   if (i915_is_ggtt(vm))
+   flags |= PIN_GLOBAL;
+
+   for_each_memory_region(mr, vm->i915, id) {
+   u64 min_alignment = i915_vm_min_alignment(vm, id);
+   u64 size = min_alignment;
+   u64 addr = round_up(hole_start + (hole_size / 2), 
min_alignment);
+
+   /* we can't test < 4k alignment due to flags being encoded in 
lower bits */
+   if (min_alignment != I915_GTT_PAGE_SIZE_4K) {
+   err = misaligned_case(vm, mr, addr + (min_alignment / 
2), size, flags);
+   /* misaligned should error with -EINVAL*/
+   if (!err)
+   err = -EBADSLT;
+   if (err != -EINVAL)
+   return err;
+   }
+
+   /* test for vma->size expansion to min page size */
+   err = misaligned_case(vm, mr, addr, PAGE_SIZE, flags);
+   if (min_alignment > hole_size) {
+   if (!err)
+   err = -EBADSLT;
+   else if (err == -ENOSPC)
+   err = 0;
+   }
+   if (err)
+   return err;
+
+   /* test for intermediate size not expanding vma->size for large 
alignments */
+   err = misaligned_case(vm, mr, addr, size / 2, flags);
+   if (min_alignment > hole_size) {
+   if (!err)
+   err = -EBADSLT;
+   else if (err == -ENOSPC)
+   err = 0;
+   }
+   if (err)
+   return err;
+   }
+
+   return 0;
+}
+
 static int exercise_ppgtt(struct drm_i915_private *dev_priv,
  int (*func)(struct i915_address_space *vm,
  u64 hole_start, u64 hole_end,
@@ 

[Intel-gfx] [PATCH v3 5/5] drm/i915/uapi: document behaviour for DG2 64K support

[Robert Beckett]

From: Matthew Auld 

On discrete platforms like DG2, we need to support a minimum page size
of 64K when dealing with device local-memory. This is quite tricky for
various reasons, so try to document the new implicit uapi for this.

v3: fix typos and less emphasis
v2: Fixed suggestions on formatting [Daniel]

Signed-off-by: Matthew Auld 
Signed-off-by: Ramalingam C 
Signed-off-by: Robert Beckett 
Acked-by: Jordan Justen 
cc: Simon Ser 
cc: Pekka Paalanen 
Cc: Jordan Justen 
Cc: Kenneth Graunke 
Cc: mesa-...@lists.freedesktop.org
Cc: Tony Ye 
Cc: Slawomir Milczarek 
---
 include/uapi/drm/i915_drm.h | 44 -
 1 file changed, 39 insertions(+), 5 deletions(-)

diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 5e678917da70..77e5e74c32c1 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1118,10 +1118,16 @@ struct drm_i915_gem_exec_object2 {
/**
 * When the EXEC_OBJECT_PINNED flag is specified this is populated by
 * the user with the GTT offset at which this object will be pinned.
+*
 * When the I915_EXEC_NO_RELOC flag is specified this must contain the
 * presumed_offset of the object.
+*
 * During execbuffer2 the kernel populates it with the value of the
 * current GTT offset of the object, for future presumed_offset writes.
+*
+* See struct drm_i915_gem_create_ext for the rules when dealing with
+* alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with
+* minimum page sizes, like DG2.
 */
__u64 offset;
 
@@ -3145,11 +3151,39 @@ struct drm_i915_gem_create_ext {
 *
 * The (page-aligned) allocated size for the object will be returned.
 *
-* Note that for some devices we have might have further minimum
-* page-size restrictions(larger than 4K), like for device local-memory.
-* However in general the final size here should always reflect any
-* rounding up, if for example using the 
I915_GEM_CREATE_EXT_MEMORY_REGIONS
-* extension to place the object in device local-memory.
+*
+* DG2 64K min page size implications:
+*
+* On discrete platforms, starting from DG2, we have to contend with GTT
+* page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
+* objects.  Specifically the hardware only supports 64K or larger GTT
+* page sizes for such memory. The kernel will already ensure that all
+* I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
+* sizes underneath.
+*
+* Note that the returned size here will always reflect any required
+* rounding up done by the kernel, i.e 4K will now become 64K on devices
+* such as DG2.
+*
+* Special DG2 GTT address alignment requirement:
+*
+* The GTT alignment will also need to be at least 2M for such objects.
+*
+* Note that due to how the hardware implements 64K GTT page support, we
+* have some further complications:
+*
+*   1) The entire PDE (which covers a 2MB virtual address range), must
+*   contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
+*   PDE is forbidden by the hardware.
+*
+*   2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
+*   objects.
+*
+* To keep things simple for userland, we mandate that any GTT mappings
+* must be aligned to and rounded up to 2MB. As this only wastes virtual
+* address space and avoids userland having to copy any needlessly
+* complicated PDE sharing scheme (coloring) and only affects DG2, this
+* is deemed to be a good compromise.
 */
__u64 size;
/**
-- 
2.25.1

[Intel-gfx] [PATCH v3 3/5] drm/i915: support 64K GTT pages for discrete cards

[Robert Beckett]

From: Matthew Auld 

discrete cards optimise 64K GTT pages for local-memory, since everything
should be allocated at 64K granularity. We say goodbye to sparse
entries, and instead get a compact 256B page-table for 64K pages,
which should be more cache friendly. 4K pages for local-memory
are no longer supported by the HW.

Signed-off-by: Matthew Auld 
Signed-off-by: Stuart Summers 
Signed-off-by: Ramalingam C 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
---
 .../gpu/drm/i915/gem/selftests/huge_pages.c   |  60 ++
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c  | 108 +-
 drivers/gpu/drm/i915/gt/intel_gtt.h   |   3 +
 drivers/gpu/drm/i915/gt/intel_ppgtt.c |   1 +
 4 files changed, 169 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 26f997c376a2..7efa6a598b03 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1478,6 +1478,65 @@ static int igt_ppgtt_sanity_check(void *arg)
return err;
 }
 
+static int igt_ppgtt_compact(void *arg)
+{
+   struct drm_i915_private *i915 = arg;
+   struct drm_i915_gem_object *obj;
+   int err;
+
+   /*
+* Simple test to catch issues with compact 64K pages -- since the pt is
+* compacted to 256B that gives us 32 entries per pt, however since the
+* backing page for the pt is 4K, any extra entries we might incorrectly
+* write out should be ignored by the HW. If ever hit such a case this
+* test should catch it since some of our writes would land in scratch.
+*/
+
+   if (!HAS_64K_PAGES(i915)) {
+   pr_info("device lacks compact 64K page support, skipping\n");
+   return 0;
+   }
+
+   if (!HAS_LMEM(i915)) {
+   pr_info("device lacks LMEM support, skipping\n");
+   return 0;
+   }
+
+   /* We want the range to cover multiple page-table boundaries. */
+   obj = i915_gem_object_create_lmem(i915, SZ_4M, 0);
+   if (IS_ERR(obj))
+   return err;
+
+   err = i915_gem_object_pin_pages_unlocked(obj);
+   if (err)
+   goto out_put;
+
+   if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
+   pr_info("LMEM compact unable to allocate huge-page(s)\n");
+   goto out_unpin;
+   }
+
+   /*
+* Disable 2M GTT pages by forcing the page-size to 64K for the GTT
+* insertion.
+*/
+   obj->mm.page_sizes.sg = I915_GTT_PAGE_SIZE_64K;
+
+   err = igt_write_huge(i915, obj);
+   if (err)
+   pr_err("LMEM compact write-huge failed\n");
+
+out_unpin:
+   i915_gem_object_unpin_pages(obj);
+out_put:
+   i915_gem_object_put(obj);
+
+   if (err == -ENOMEM)
+   err = 0;
+
+   return err;
+}
+
 static int igt_tmpfs_fallback(void *arg)
 {
struct drm_i915_private *i915 = arg;
@@ -1735,6 +1794,7 @@ int i915_gem_huge_page_live_selftests(struct 
drm_i915_private *i915)
SUBTEST(igt_tmpfs_fallback),
SUBTEST(igt_ppgtt_smoke_huge),
SUBTEST(igt_ppgtt_sanity_check),
+   SUBTEST(igt_ppgtt_compact),
};
 
if (!HAS_PPGTT(i915)) {
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c 
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index c43e724afa9f..62471730266c 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -233,6 +233,8 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space * 
const vm,
   start, end, lvl);
} else {
unsigned int count;
+   unsigned int pte = gen8_pd_index(start, 0);
+   unsigned int num_ptes;
u64 *vaddr;
 
count = gen8_pt_count(start, end);
@@ -242,10 +244,18 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space * 
const vm,
atomic_read(>used));
GEM_BUG_ON(!count || count >= atomic_read(>used));
 
+   num_ptes = count;
+   if (pt->is_compact) {
+   GEM_BUG_ON(num_ptes % 16);
+   GEM_BUG_ON(pte % 16);
+   num_ptes /= 16;
+   pte /= 16;
+   }
+
vaddr = px_vaddr(pt);
-   memset64(vaddr + gen8_pd_index(start, 0),
+   memset64(vaddr + pte,
 vm->scratch[0]->encode,
-count);
+num_ptes);
 
atomic_sub(count, >used);
start += count;
@@ -453,6 +463,95 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,

[Intel-gfx] [PATCH v3 2/5] drm/i915: enforce min GTT alignment for discrete cards

[Robert Beckett]

From: Matthew Auld 

For local-memory objects we need to align the GTT addresses
to 64K, both for the ppgtt and ggtt.

We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.

For compact-pt we further align and pad lmem object GTT addresses
to 2MB to ensure PDEs contain consistent page sizes as
required by the HW.

v3:
* use needs_compact_pt flag to discriminate between
  64K and 64K with compact-pt
* add i915_vm_obj_min_alignment
* use i915_vm_obj_min_alignment to round up vma reservation
  if compact-pt instead of hard coding

Signed-off-by: Matthew Auld 
Signed-off-by: Ramalingam C 
Signed-off-by: Robert Beckett 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
---
 .../i915/gem/selftests/i915_gem_client_blt.c  | 23 +++--
 drivers/gpu/drm/i915/gt/intel_gtt.c   | 12 +++
 drivers/gpu/drm/i915/gt/intel_gtt.h   | 15 +++
 drivers/gpu/drm/i915/i915_vma.c   |  9 ++
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 96 ---
 5 files changed, 114 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index c08f766e6e15..7fee95a65414 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -39,6 +39,7 @@ struct tiled_blits {
struct blit_buffer scratch;
struct i915_vma *batch;
u64 hole;
+   u64 align;
u32 width;
u32 height;
 };
@@ -410,14 +411,21 @@ tiled_blits_create(struct intel_engine_cs *engine, struct 
rnd_state *prng)
goto err_free;
}
 
-   hole_size = 2 * PAGE_ALIGN(WIDTH * HEIGHT * 4);
+   t->align = I915_GTT_PAGE_SIZE_2M; /* XXX worst case, derive from vm! */
+   t->align = max(t->align,
+  i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_LOCAL));
+   t->align = max(t->align,
+  i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_SYSTEM));
+
+   hole_size = 2 * round_up(WIDTH * HEIGHT * 4, t->align);
hole_size *= 2; /* room to maneuver */
-   hole_size += 2 * I915_GTT_MIN_ALIGNMENT;
+   hole_size += 2 * t->align; /* padding on either side */
 
mutex_lock(>ce->vm->mutex);
memset(, 0, sizeof(hole));
err = drm_mm_insert_node_in_range(>ce->vm->mm, ,
- hole_size, 0, I915_COLOR_UNEVICTABLE,
+ hole_size, t->align,
+ I915_COLOR_UNEVICTABLE,
  0, U64_MAX,
  DRM_MM_INSERT_BEST);
if (!err)
@@ -428,7 +436,7 @@ tiled_blits_create(struct intel_engine_cs *engine, struct 
rnd_state *prng)
goto err_put;
}
 
-   t->hole = hole.start + I915_GTT_MIN_ALIGNMENT;
+   t->hole = hole.start + t->align;
pr_info("Using hole at %llx\n", t->hole);
 
err = tiled_blits_create_buffers(t, WIDTH, HEIGHT, prng);
@@ -455,7 +463,7 @@ static void tiled_blits_destroy(struct tiled_blits *t)
 static int tiled_blits_prepare(struct tiled_blits *t,
   struct rnd_state *prng)
 {
-   u64 offset = PAGE_ALIGN(t->width * t->height * 4);
+   u64 offset = round_up(t->width * t->height * 4, t->align);
u32 *map;
int err;
int i;
@@ -486,8 +494,7 @@ static int tiled_blits_prepare(struct tiled_blits *t,
 
 static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng)
 {
-   u64 offset =
-   round_up(t->width * t->height * 4, 2 * I915_GTT_MIN_ALIGNMENT);
+   u64 offset = round_up(t->width * t->height * 4, 2 * t->align);
int err;
 
/* We want to check position invariant tiling across GTT eviction */
@@ -500,7 +507,7 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct 
rnd_state *prng)
 
/* Reposition so that we overlap the old addresses, and slightly off */
err = tiled_blit(t,
->buffers[2], t->hole + I915_GTT_MIN_ALIGNMENT,
+>buffers[2], t->hole + t->align,
 >buffers[1], t->hole + 3 * offset / 2);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c 
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 46be4197b93f..df23ebdfc994 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -223,6 +223,18 @@ void i915_address_space_init(struct i915_address_space 
*vm, int subclass)
 
GEM_BUG_ON(!vm->total);
drm_mm_init(>mm, 0, vm->total);
+
+   memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT,
+ARRAY_SIZE(vm->min_alignment));
+
+   if (HAS_64K_PAGES(vm->i915) && 

[Intel-gfx] [PATCH v3 0/5] discrete card 64K page support

[Robert Beckett]

This series continues support for 64K pages for discrete cards.
It supersedes the 64K patches from 
https://patchwork.freedesktop.org/series/95686/#rev4
Changes since that series:

- set min alignment for DG2 to 2MB in i915_address_space_init
- replace coloring with simpler 2MB VA alignment for lmem buffers
- enforce alignment to 2MB for lmem objects on DG2 in i915_vma_insert
- expand vma reservation to round up to 2MB on DG2 in i915_vma_insert
- add alignment test

v2: rebase and fix for async vma that landed
v3:
* fix uapi doc typos
* add needs_compact_pt flag patch
* cleanup vma expansion to use vm->min_alignment instead of hard coding

Matthew Auld (3):
  drm/i915: enforce min GTT alignment for discrete cards
  drm/i915: support 64K GTT pages for discrete cards
  drm/i915/uapi: document behaviour for DG2 64K support

Ramalingam C (1):
  drm/i915: add needs_compact_pt flag

Robert Beckett (1):
  drm/i915: add gtt misalignment test

 .../gpu/drm/i915/gem/selftests/huge_pages.c   |  60 +
 .../i915/gem/selftests/i915_gem_client_blt.c  |  23 +-
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c  | 108 -
 drivers/gpu/drm/i915/gt/intel_gtt.c   |  12 +
 drivers/gpu/drm/i915/gt/intel_gtt.h   |  18 ++
 drivers/gpu/drm/i915/gt/intel_ppgtt.c |   1 +
 drivers/gpu/drm/i915/i915_drv.h   |  10 +-
 drivers/gpu/drm/i915/i915_pci.c   |   2 +
 drivers/gpu/drm/i915/i915_vma.c   |   9 +
 drivers/gpu/drm/i915/intel_device_info.h  |   1 +
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 226 +++---
 include/uapi/drm/i915_drm.h   |  44 +++-
 12 files changed, 462 insertions(+), 52 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH v3 1/5] drm/i915: add needs_compact_pt flag

[Robert Beckett]

From: Ramalingam C 

Add a new platform flag, needs_compact_pt, to mark the requirement of
compact pt layout support for the ppGTT when using 64K GTT pages.

With this flag has_64k_pages will only indicate requirement of 64K
GTT page sizes or larger for device local memory access.

Suggested-by: Matthew Auld 
Signed-off-by: Ramalingam C 
Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/i915_drv.h  | 10 +++---
 drivers/gpu/drm/i915/i915_pci.c  |  2 ++
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 890f1f6fbc49..23f4713005bb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1512,12 +1512,16 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 /*
  * Set this flag, when platform requires 64K GTT page sizes or larger for
- * device local memory access. Also this flag implies that we require or
- * at least support the compact PT layout for the ppGTT when using the 64K
- * GTT pages.
+ * device local memory access.
  */
 #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
 
+/* Set this flag when platform doesn't allow both 64k pages and 4k pages in
+ * the same PT. this flag means we need to support compact PT layout for the
+ * ppGTT when using the 64K GTT pages.
+ */
+#define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt)
+
 #define HAS_IPC(dev_priv)   (INTEL_INFO(dev_priv)->display.has_ipc)
 
 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4081fd50ba9d..799b56569ef5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1028,6 +1028,7 @@ static const struct intel_device_info xehpsdv_info = {
PLATFORM(INTEL_XEHPSDV),
.display = { },
.has_64k_pages = 1,
+   .needs_compact_pt = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
@@ -1045,6 +1046,7 @@ static const struct intel_device_info dg2_info = {
.media.rel = 55,
PLATFORM(INTEL_DG2),
.has_64k_pages = 1,
+   .needs_compact_pt = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) |
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 3699b1c539ea..c8aaf646430c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -130,6 +130,7 @@ enum intel_ppgtt_type {
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
func(has_64k_pages); \
+   func(needs_compact_pt); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_global_mocs); \
-- 
2.25.1

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Don't restart WL for every frequency step

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: Don't restart WL for every frequency step
URL   : https://patchwork.freedesktop.org/series/99109/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_3 -> Patchwork_22043


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22043 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22043, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22043/index.html

Participating hosts (43 -> 35)
--

  Additional (3): fi-kbl-soraka fi-kbl-guc fi-apl-guc 
  Missing(11): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-adlp-4 
fi-kbl-8809g fi-pnv-d510 bat-rpls-1 fi-bdw-samus bat-jsl-2 bat-jsl-1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22043:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gt_engines:
- fi-rkl-guc: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_3/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22043/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html

  
Known issues


  Here are the changes found in Patchwork_22043 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@read_all_entries:
- fi-apl-guc: NOTRUN -> [DMESG-WARN][3] ([i915#1610])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22043/fi-apl-guc/igt@debugfs_test@read_all_entries.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271]) +8 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22043/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u:   [PASS][5] -> [INCOMPLETE][6] ([i915#4547])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_3/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22043/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22043/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-guc: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22043/fi-kbl-guc/igt@gem_lmem_swapp...@basic.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22043/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][10] ([i915#1886] / [i915#2291])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22043/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][11] -> [INCOMPLETE][12] ([i915#3921])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_3/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22043/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_busy@basic:
- fi-kbl-guc: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1845])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22043/fi-kbl-guc/igt@kms_b...@basic.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka:  NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22043/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@vga-hpd-fast:
- fi-kbl-guc: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22043/fi-kbl-guc/igt@kms_chamel...@vga-hpd-fast.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2:  [PASS][16] -> [DMESG-WARN][17] ([i915#4269])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_3/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22043/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-guc: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#533])
   [18]: 

Re: [Intel-gfx] [PATCH] drm/i915/dmc: Eliminate remnant GEN references

[Lucas De Marchi]

On Thu, Jan 20, 2022 at 03:31:34AM +, Tolakanahalli Pradeep, Madhumitha 
wrote:

On Tue, 2022-01-18 at 13:37 -0800, Lucas De Marchi wrote:

On Thu, Dec 23, 2021 at 03:18:57AM +, Tolakanahalli Pradeep,
Madhumitha wrote:
> On Fri, 2021-12-17 at 21:37 +, Yokoyama, Caz wrote:
> > On Thu, 2021-12-16 at 19:41 -0800, Madhumitha Tolakanahalli
> > Pradeep
> > wrote:
> > > Replace GEN with DISPLAY_VER, in line with the naming
> > > convention
> > > followed in the i915 driver code.
> > >
> > > Signed-off-by: Madhumitha Tolakanahalli Pradeep <
> > > madhumitha.tolakanahalli.prad...@intel.com>

I was checking to apply this today, but BAT is failing on CI and it
didn't trigger the full run. Error seems unrelated and I don't think
this would trigger any error in the machines in CI, but I'd prefer to
merge this with a clean run.

Can you re-submit or trigger it again via patchwork if the patch
still
applies?

thanks
Lucas De Marchi


The error does seem pretty random. I've triggered a rerun, awaiting
results.


CI results are now clean. Pushed.

thanks
Lucas De Marchi

Re: [Intel-gfx] [PATCH] drm/i915/pmu: Use PM timestamp instead of RING TIMESTAMP for reference

[Teres Alexis, Alan Previn]

Reviewed-by: Alan Previn 

On Mon, 2022-01-10 at 17:55 -0800, Umesh Nerlige Ramappa wrote:
> All timestamps returned by GuC for GuC PMU busyness are captured from
> GUC PM TIMESTAMP. Since this timestamp does not tick when GuC goes idle,
> kmd uses RING_TIMESTAMP to measure busyness of an engine with an active
> context. In further stress testing, the MMIO read of the RING_TIMESTAMP
> is seen to cause a rare hang. Resolve the issue by using gt specific
> timestamp from PM which is in sync with the GuC PM timestamp.
> 
> Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to 
> pmu")
> Signed-off-by: Umesh Nerlige Ramappa 
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc.h|  5 ++
>  .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 56 ++-
>  drivers/gpu/drm/i915/i915_reg.h   |  3 +-
>  3 files changed, 50 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index f9240d4baa69..3aabe164c329 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -206,6 +206,11 @@ struct intel_guc {
>* context usage for overflows.
>*/
>   struct delayed_work work;
> +
> + /**
> +  * @shift: Right shift value for the gpm timestamp
> +  */
> + u32 shift;
>   } timestamp;
>  
>  #ifdef CONFIG_DRM_I915_SELFTEST
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 9989d121127d..d93e9547f5e4 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1149,23 +1149,51 @@ static void guc_update_engine_gt_clks(struct 
> intel_engine_cs *engine)
>   }
>  }
>  
> -static void guc_update_pm_timestamp(struct intel_guc *guc,
> - struct intel_engine_cs *engine,
> - ktime_t *now)
> +static u32 gpm_timestamp_shift(struct intel_gt *gt)
>  {
> - u32 gt_stamp_now, gt_stamp_hi;
> + intel_wakeref_t wakeref;
> + u32 reg, shift;
> +
> + with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> + reg = intel_uncore_read(gt->uncore, RPM_CONFIG0);
> +
> + shift = (reg & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
> + GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT;
> +
> + return 3 - shift;
> +}
> +
> +static u64 gpm_timestamp(struct intel_gt *gt)
> +{
> + u32 lo, hi, old_hi, loop = 0;
> +
> + hi = intel_uncore_read(gt->uncore, MISC_STATUS1);
> + do {
> + lo = intel_uncore_read(gt->uncore, MISC_STATUS0);
> + old_hi = hi;
> + hi = intel_uncore_read(gt->uncore, MISC_STATUS1);
> + } while (old_hi != hi && loop++ < 2);
> +
> + return ((u64)hi << 32) | lo;
> +}
> +
> +static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
> +{
> + struct intel_gt *gt = guc_to_gt(guc);
> + u32 gt_stamp_lo, gt_stamp_hi;
> + u64 gpm_ts;
>  
>   lockdep_assert_held(>timestamp.lock);
>  
>   gt_stamp_hi = upper_32_bits(guc->timestamp.gt_stamp);
> - gt_stamp_now = intel_uncore_read(engine->uncore,
> -  RING_TIMESTAMP(engine->mmio_base));
> + gpm_ts = gpm_timestamp(gt) >> guc->timestamp.shift;
> + gt_stamp_lo = lower_32_bits(gpm_ts);
>   *now = ktime_get();
>  
> - if (gt_stamp_now < lower_32_bits(guc->timestamp.gt_stamp))
> + if (gt_stamp_lo < lower_32_bits(guc->timestamp.gt_stamp))
>   gt_stamp_hi++;
>  
> - guc->timestamp.gt_stamp = ((u64)gt_stamp_hi << 32) | gt_stamp_now;
> + guc->timestamp.gt_stamp = ((u64)gt_stamp_hi << 32) | gt_stamp_lo;
>  }
>  
>  /*
> @@ -1209,7 +1237,7 @@ static ktime_t guc_engine_busyness(struct 
> intel_engine_cs *engine, ktime_t *now)
>   stats_saved = *stats;
>   gt_stamp_saved = guc->timestamp.gt_stamp;
>   guc_update_engine_gt_clks(engine);
> - guc_update_pm_timestamp(guc, engine, now);
> + guc_update_pm_timestamp(guc, now);
>   intel_gt_pm_put_async(gt);
>   if (i915_reset_count(gpu_error) != reset_count) {
>   *stats = stats_saved;
> @@ -1241,8 +1269,8 @@ static void __reset_guc_busyness_stats(struct intel_guc 
> *guc)
>  
>   spin_lock_irqsave(>timestamp.lock, flags);
>  
> + guc_update_pm_timestamp(guc, );
>   for_each_engine(engine, gt, id) {
> - guc_update_pm_timestamp(guc, engine, );
>   guc_update_engine_gt_clks(engine);
>   engine->stats.guc.prev_total = 0;
>   }
> @@ -1259,10 +1287,11 @@ static void __update_guc_busyness_stats(struct 
> intel_guc *guc)
>   ktime_t unused;
>  
>   spin_lock_irqsave(>timestamp.lock, flags);
> - for_each_engine(engine, gt, id) {
> - 

Re: [Intel-gfx] [PATCH] drm/i915/wopcm: Handle pre-programmed WOPCM registers

[Matthew Brost]

On Thu, Jan 20, 2022 at 06:13:47PM +, Teres Alexis, Alan Previn wrote:
> Just one nit below, (assuming that igt CI failure isnt related - kms flip not 
> completing)
> Reviewed-by Alan Previn 
> 
> -Original Message-
> From: Ceraolo Spurio, Daniele  
> Sent: Friday, January 14, 2022 11:33 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Ceraolo Spurio, Daniele 
> ; Summers, Stuart 
> ; Harrison, John C ; 
> Teres Alexis, Alan Previn 
> Subject: [PATCH] drm/i915/wopcm: Handle pre-programmed WOPCM registers
> 
> Starting from DG2, some of the programming previously done by i915 and the 
> GuC has been moved to the GSC and the relevant registers are no longer 
> writable by either CPU or GuC. This is also referred to as GuC deprivilege.
> On the i915 side, this affects the WOPCM registers: these are no longer 
> programmed by the driver and we do instead expect to find them already set. 
> This can lead to verification failures because in i915 we cheat a bit with 
> the WOPCM size defines, to keep the code common across platforms, by 
> sometimes using a smaller WOPCM size that the actual HW support (which isn't 
> a problem because the extra size is not needed if the FW fits in the smaller 
> chunk), while the pre-programmed values can use the actual size.
> Given tha the new programming entity is trusted, relax the amount of the 
> checks done on the pre-programmed values by not limiting the max programmed 
> size. In the extremely unlikely scenario that the registers have been 
> misprogrammed, we will still fail later at DMA time.
> 
> Signed-off-by: Daniele Ceraolo Spurio 
> Cc: Stuart Summers 
> Cc: John Harrison 
> Cc: Alan Previn 
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h |  3 ++
>  drivers/gpu/drm/i915/i915_drv.h|  3 ++
>  drivers/gpu/drm/i915/i915_pci.c|  1 +
>  drivers/gpu/drm/i915/intel_device_info.c   |  8 +
>  drivers/gpu/drm/i915/intel_device_info.h   |  1 +
>  drivers/gpu/drm/i915/intel_wopcm.c | 42 ++
>  6 files changed, 51 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 93b251b25aba..88aad892a0fc 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -394,6 +394,14 @@ void intel_device_info_runtime_init(struct 
> drm_i915_private *dev_priv)
>   memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
>   memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
>   }
> +
> + /*
> +  * Early DG2 steppings don't have the GuC depriv feature. We can't
> +  * rely on the fuse on those platforms because the meaning of the fuse
> +  * bit is inverted on platforms that do have the feature.
> +  */
> + if (IS_DG2_GRAPHICS_STEP(dev_priv, G10, STEP_A0, STEP_A1))
> + info->has_guc_deprivilege = 0;
> 
> Nit: not sure if it matters if this stepping is not-public (although I am not 
> 100% sure I am correct in my assumption this is not-public).

Agree with Alan.

Are we ever going to let A0 / A1 stepping for DG2 be publicly available?
If the answer is no, I think this can be removed.

Matt

>  }

Re: [Intel-gfx] [PATCH] drm/i915: Add needs_compact_pt flag

[Ramalingam C]

On 2022-01-20 at 16:42:52 +, Robert Beckett wrote:
> 
> 
> On 20/01/2022 16:21, Ramalingam C wrote:
> > Add a new platform flag, needs_compact_pt, to mark the requirement of
> > compact pt layout support for the ppGTT when using 64K GTT pages.
> > 
> > With this flag has_64k_pages will only indicate requirement of 64K
> > GTT page sizes or larger for device local memory access.
> > 
> > Suggested-by: Matthew Auld 
> > Signed-off-by: Ramalingam C 
> > cc: Robert Beckett 
> > ---
> >   drivers/gpu/drm/i915/i915_drv.h  | 10 +++---
> >   drivers/gpu/drm/i915/i915_pci.c  |  2 ++
> >   drivers/gpu/drm/i915/intel_device_info.h |  1 +
> >   3 files changed, 10 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 890f1f6fbc49..23f4713005bb 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1512,12 +1512,16 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >   /*
> >* Set this flag, when platform requires 64K GTT page sizes or larger for
> > - * device local memory access. Also this flag implies that we require or
> > - * at least support the compact PT layout for the ppGTT when using the 64K
> > - * GTT pages.
> > + * device local memory access.
> >*/
> >   #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
> > +/* Set this flag when platform doesn't allow both 64k pages and 4k pages in
> > + * the same PT. this flag means we need to support compact PT layout for 
> > the
> > + * ppGTT when using the 64K GTT pages.
> > + */
> > +#define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt)
> > +
> >   #define HAS_IPC(dev_priv)  (INTEL_INFO(dev_priv)->display.has_ipc)
> >   #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c 
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index 8261b6455747..3e7555ce6894 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -1028,6 +1028,7 @@ static const struct intel_device_info xehpsdv_info = {
> > PLATFORM(INTEL_XEHPSDV),
> > .display = { },
> > .has_64k_pages = 1,
> > +   .needs_compact_pt = 1,
> > .platform_engine_mask =
> > BIT(RCS0) | BIT(BCS0) |
> > BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
> > @@ -1046,6 +1047,7 @@ static const struct intel_device_info dg2_info = {
> > .media.rel = 55,
> > PLATFORM(INTEL_DG2),
> > .has_64k_pages = 1,
> > +   .needs_compact_pt = 1,
> > .platform_engine_mask =
> > BIT(RCS0) | BIT(BCS0) |
> > BIT(VECS0) | BIT(VECS1) |
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index 3699b1c539ea..8ff676f49471 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -130,6 +130,7 @@ enum intel_ppgtt_type {
> > /* Keep has_* in alphabetical order */ \
> > func(has_64bit_reloc); \
> > func(has_64k_pages); \
> > +   func(needs_compact_pt; \
> 
> missing `)`
> instead of chucking untested patches on ml, I'll add a fixed version to the
> in review series and include it in v3 after testing
Thanks

Ram
> 
> > func(gpu_reset_clobbers_display); \
> > func(has_reset_engine); \
> > func(has_global_mocs); \
> > 

[Intel-gfx] [PATCH 1/2] drm/i915/guc: Don't check CT descriptor status before CT write / read

[Matthew Brost]

Don't check CT descriptor status, unless CONFIG_DRM_I915_DEBUG_GUC is
set, before CT write / read as this could result in a read across the
PCIe bus thus adding latency to every CT write / read. On well behavied
systems this vaue should always read as zero. For some reason it doesn't
the CT channel is broken and will eventually recover from a GT reset,
albeit the GT reset will not be triggered immediately by seeing that
descriptor status is non-zero.

v2:
 (CI)
  - Fix build error (hide corrupted label in write function behind
CONFIG_DRM_I915_DEBUG_GUC)

Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index de89d40abd38d..948cf31429412 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -379,8 +379,10 @@ static int ct_write(struct intel_guc_ct *ct,
u32 *cmds = ctb->cmds;
unsigned int i;
 
+#ifdef CONFIG_DRM_I915_DEBUG_GUC
if (unlikely(desc->status))
goto corrupted;
+#endif
 
GEM_BUG_ON(tail > size);
 
@@ -445,11 +447,13 @@ static int ct_write(struct intel_guc_ct *ct,
 
return 0;
 
+#ifdef CONFIG_DRM_I915_DEBUG_GUC
 corrupted:
CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n",
 desc->head, desc->tail, desc->status);
ctb->broken = true;
return -EPIPE;
+#endif
 }
 
 /**
@@ -815,8 +819,10 @@ static int ct_read(struct intel_guc_ct *ct, struct 
ct_incoming_msg **msg)
if (unlikely(ctb->broken))
return -EPIPE;
 
+#ifdef CONFIG_DRM_I915_DEBUG_GUC
if (unlikely(desc->status))
goto corrupted;
+#endif
 
GEM_BUG_ON(head > size);
 
-- 
2.34.1

[Intel-gfx] [PATCH 2/2] drm/i915/guc: Print CT descriptor status in CT debug function

[Matthew Brost]

Noticed that the CT descriptor status was not printed in the CT debug
function, add that in.

Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 948cf31429412..5df2e3413796e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -1219,10 +1219,14 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct,
   ct->ctbs.send.desc->head);
drm_printf(p, "Tail: %u\n",
   ct->ctbs.send.desc->tail);
+   drm_printf(p, "Status: %u\n",
+  ct->ctbs.send.desc->status);
drm_printf(p, "G2H Space: %u\n",
   atomic_read(>ctbs.recv.space) * 4);
drm_printf(p, "Head: %u\n",
   ct->ctbs.recv.desc->head);
drm_printf(p, "Tail: %u\n",
   ct->ctbs.recv.desc->tail);
+   drm_printf(p, "Status: %u\n",
+  ct->ctbs.recv.desc->status);
 }
-- 
2.34.1

[Intel-gfx] [PATCH 0/2] A few CT updates

[Matthew Brost]

A couple of minor CT updates. 1 for performance, 1 for extra debug.

Signed-off-by: Matthew Brost 

Matthew Brost (2):
  drm/i915/guc: Don't check CT descriptor status before CT write / read
  drm/i915/guc: Print CT descriptor status in CT debug function

 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 10 ++
 1 file changed, 10 insertions(+)

-- 
2.34.1

[Intel-gfx] [PATCH] drm/i915/guc: Don't check CT descriptor status before CT write / read

[Matthew Brost]

Don't check CT descriptor status, unless CONFIG_DRM_I915_DEBUG_GUC is
set, before CT write / read as this could result in a read across the
PCIe bus thus adding latency to every CT write / read. On well behavied
systems this vaue should always read as zero. For some reason it doesn't
the CT channel is broken and will eventually recover from a GT reset,
albeit the GT reset will not be triggered immediately by seeing that
descriptor status is non-zero.

Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index de89d40abd38d..18af99a802f64 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -379,8 +379,10 @@ static int ct_write(struct intel_guc_ct *ct,
u32 *cmds = ctb->cmds;
unsigned int i;
 
+#ifdef CONFIG_DRM_I915_DEBUG_GUC
if (unlikely(desc->status))
goto corrupted;
+#endif
 
GEM_BUG_ON(tail > size);
 
@@ -815,8 +817,10 @@ static int ct_read(struct intel_guc_ct *ct, struct 
ct_incoming_msg **msg)
if (unlikely(ctb->broken))
return -EPIPE;
 
+#ifdef CONFIG_DRM_I915_DEBUG_GUC
if (unlikely(desc->status))
goto corrupted;
+#endif
 
GEM_BUG_ON(head > size);
 
-- 
2.34.1

Re: [Intel-gfx] [PATCH] drm/i915/wopcm: Handle pre-programmed WOPCM registers

[Teres Alexis, Alan Previn]

Just one nit below, (assuming that igt CI failure isnt related - kms flip not 
completing)
Reviewed-by Alan Previn 

-Original Message-
From: Ceraolo Spurio, Daniele  
Sent: Friday, January 14, 2022 11:33 AM
To: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org; Ceraolo Spurio, Daniele 
; Summers, Stuart ; 
Harrison, John C ; Teres Alexis, Alan Previn 

Subject: [PATCH] drm/i915/wopcm: Handle pre-programmed WOPCM registers

Starting from DG2, some of the programming previously done by i915 and the GuC 
has been moved to the GSC and the relevant registers are no longer writable by 
either CPU or GuC. This is also referred to as GuC deprivilege.
On the i915 side, this affects the WOPCM registers: these are no longer 
programmed by the driver and we do instead expect to find them already set. 
This can lead to verification failures because in i915 we cheat a bit with the 
WOPCM size defines, to keep the code common across platforms, by sometimes 
using a smaller WOPCM size that the actual HW support (which isn't a problem 
because the extra size is not needed if the FW fits in the smaller chunk), 
while the pre-programmed values can use the actual size.
Given tha the new programming entity is trusted, relax the amount of the checks 
done on the pre-programmed values by not limiting the max programmed size. In 
the extremely unlikely scenario that the registers have been misprogrammed, we 
will still fail later at DMA time.

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Stuart Summers 
Cc: John Harrison 
Cc: Alan Previn 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h |  3 ++
 drivers/gpu/drm/i915/i915_drv.h|  3 ++
 drivers/gpu/drm/i915/i915_pci.c|  1 +
 drivers/gpu/drm/i915/intel_device_info.c   |  8 +
 drivers/gpu/drm/i915/intel_device_info.h   |  1 +
 drivers/gpu/drm/i915/intel_wopcm.c | 42 ++
 6 files changed, 51 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 93b251b25aba..88aad892a0fc 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -394,6 +394,14 @@ void intel_device_info_runtime_init(struct 
drm_i915_private *dev_priv)
memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
}
+
+   /*
+* Early DG2 steppings don't have the GuC depriv feature. We can't
+* rely on the fuse on those platforms because the meaning of the fuse
+* bit is inverted on platforms that do have the feature.
+*/
+   if (IS_DG2_GRAPHICS_STEP(dev_priv, G10, STEP_A0, STEP_A1))
+   info->has_guc_deprivilege = 0;

Nit: not sure if it matters if this stepping is not-public (although I am not 
100% sure I am correct in my assumption this is not-public).
 }

[Intel-gfx] [PATCH] drm/i915/selftests: Don't restart WL for every frequency step

[Vinay Belgaumkar]

Move spinner start out of the steps loop. If we restart WL for each
freq step, the rapid start/stop causes SLPC algorithm to think that
GT busyness is 50% for it's evaluation interval. This leads to SLPC
not increasing the requested frequency as per the test expectation.

Fixes: 8ee2c227822e (drm/i915/guc/slpc: Add SLPC selftest)

Signed-off-by: Vinay Belgaumkar 
---
 drivers/gpu/drm/i915/gt/selftest_slpc.c | 104 
 1 file changed, 52 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c 
b/drivers/gpu/drm/i915/gt/selftest_slpc.c
index b768cea5943d..eef416747c67 100644
--- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
@@ -79,6 +79,29 @@ static int live_slpc_clamp_min(void *arg)
if (!intel_engine_can_store_dword(engine))
continue;
 
+   st_engine_heartbeat_disable(engine);
+
+   rq = igt_spinner_create_request(,
+   engine->kernel_context,
+   MI_NOOP);
+   if (IS_ERR(rq)) {
+   err = PTR_ERR(rq);
+   st_engine_heartbeat_enable(engine);
+   break;
+   }
+
+   i915_request_add(rq);
+
+   if (!igt_wait_for_spinner(, rq)) {
+   pr_err("%s: Spinner did not start\n",
+  engine->name);
+   igt_spinner_end();
+   st_engine_heartbeat_enable(engine);
+   intel_gt_set_wedged(engine->gt);
+   err = -EIO;
+   break;
+   }
+
/* Go from min to max in 5 steps */
step = (slpc_max_freq - slpc_min_freq) / NUM_STEPS;
max_act_freq = slpc_min_freq;
@@ -88,29 +111,6 @@ static int live_slpc_clamp_min(void *arg)
if (err)
break;
 
-   st_engine_heartbeat_disable(engine);
-
-   rq = igt_spinner_create_request(,
-   engine->kernel_context,
-   MI_NOOP);
-   if (IS_ERR(rq)) {
-   err = PTR_ERR(rq);
-   st_engine_heartbeat_enable(engine);
-   break;
-   }
-
-   i915_request_add(rq);
-
-   if (!igt_wait_for_spinner(, rq)) {
-   pr_err("%s: Spinner did not start\n",
-  engine->name);
-   igt_spinner_end();
-   st_engine_heartbeat_enable(engine);
-   intel_gt_set_wedged(engine->gt);
-   err = -EIO;
-   break;
-   }
-
/* Wait for GuC to detect business and raise
 * requested frequency if necessary.
 */
@@ -131,9 +131,6 @@ static int live_slpc_clamp_min(void *arg)
act_freq =  intel_rps_read_actual_frequency(rps);
if (act_freq > max_act_freq)
max_act_freq = act_freq;
-
-   igt_spinner_end();
-   st_engine_heartbeat_enable(engine);
}
 
pr_info("Max actual frequency for %s was %d\n",
@@ -145,6 +142,9 @@ static int live_slpc_clamp_min(void *arg)
err = -EINVAL;
}
 
+   igt_spinner_end();
+   st_engine_heartbeat_enable(engine);
+
if (err)
break;
}
@@ -210,6 +210,29 @@ static int live_slpc_clamp_max(void *arg)
if (!intel_engine_can_store_dword(engine))
continue;
 
+   st_engine_heartbeat_disable(engine);
+
+   rq = igt_spinner_create_request(,
+   engine->kernel_context,
+   MI_NOOP);
+   if (IS_ERR(rq)) {
+   st_engine_heartbeat_enable(engine);
+   err = PTR_ERR(rq);
+   break;
+   }
+
+   i915_request_add(rq);
+
+   if (!igt_wait_for_spinner(, rq)) {
+   pr_err("%s: SLPC spinner did not start\n",
+  engine->name);
+   igt_spinner_end();
+   st_engine_heartbeat_enable(engine);
+   intel_gt_set_wedged(engine->gt);
+   err = -EIO;
+   break;
+   }
+
/* Go from 

Re: [Intel-gfx] [PATCH v9 4/6] drm: implement a method to free unused pages

[Matthew Auld]

On 19/01/2022 11:37, Arunpravin wrote:

On contiguous allocation, we round up the size
to the *next* power of 2, implement a function
to free the unused pages after the newly allocate block.

v2(Matthew Auld):
   - replace function name 'drm_buddy_free_unused_pages' with
 drm_buddy_block_trim
   - replace input argument name 'actual_size' with 'new_size'
   - add more validation checks for input arguments
   - add overlaps check to avoid needless searching and splitting
   - merged the below patch to see the feature in action
  - add free unused pages support to i915 driver
   - lock drm_buddy_block_trim() function as it calls mark_free/mark_split
 are all globally visible

v3(Matthew Auld):
   - remove trim method error handling as we address the failure case
 at drm_buddy_block_trim() function

v4:
   - in case of trim, at __alloc_range() split_block failure path
 marks the block as free and removes it from the original list,
 potentially also freeing it, to overcome this problem, we turn
 the drm_buddy_block_trim() input node into a temporary node to
 prevent recursively freeing itself, but still retain the
 un-splitting/freeing of the other nodes(Matthew Auld)

   - modify the drm_buddy_block_trim() function return type

v5(Matthew Auld):
   - revert drm_buddy_block_trim() function return type changes in v4
   - modify drm_buddy_block_trim() passing argument n_pages to original_size
 as n_pages has already been rounded up to the next power-of-two and
 passing n_pages results noop

v6:
   - fix warnings reported by kernel test robot 

Signed-off-by: Arunpravin 
---
  drivers/gpu/drm/drm_buddy.c   | 65 +++
  drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 10 +++
  include/drm/drm_buddy.h   |  4 ++
  3 files changed, 79 insertions(+)

diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index 6aa5c1ce25bf..c5902a81b8c5 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -546,6 +546,71 @@ static int __drm_buddy_alloc_range(struct drm_buddy *mm,
return __alloc_range(mm, , start, size, blocks);
  }
  
+/**

+ * drm_buddy_block_trim - free unused pages
+ *
+ * @mm: DRM buddy manager
+ * @new_size: original size requested
+ * @blocks: output list head to add allocated blocks


@blocks: Input and output list of allocated blocks. MUST contain single 
block as input to be trimmed. On success will contain the newly 
allocated blocks making up the @new_size. Blocks always appear in 
ascending order.


?


+ *
+ * For contiguous allocation, we round up the size to the nearest
+ * power of two value, drivers consume *actual* size, so remaining
+ * portions are unused and it can be freed.


so remaining portions are unused and can be optionally freed with this 
function.


?


+ *
+ * Returns:
+ * 0 on success, error code on failure.
+ */
+int drm_buddy_block_trim(struct drm_buddy *mm,
+u64 new_size,
+struct list_head *blocks)
+{
+   struct drm_buddy_block *parent;
+   struct drm_buddy_block *block;
+   LIST_HEAD(dfs);
+   u64 new_start;
+   int err;
+
+   if (!list_is_singular(blocks))
+   return -EINVAL;
+
+   block = list_first_entry(blocks,
+struct drm_buddy_block,
+link);
+
+   if (!drm_buddy_block_is_allocated(block))


Maybe:

if (WARN_ON(!drm_buddy_block_is_allocated()))

AFAIK it should be normally impossible to be handed such non-allocated 
block, and so should be treated as a serious programmer error.


?


+   return -EINVAL;
+
+   if (new_size > drm_buddy_block_size(mm, block))
+   return -EINVAL;
+
+   if (!new_size && !IS_ALIGNED(new_size, mm->chunk_size))
+   return -EINVAL;


I assume that's a typo:

if (!new_size || ...)

Otherwise I think looks good. Some unit tests for this would be nice, 
but not a blocker. And this does at least pass the igt_mock_contiguous 
selftest, and I didn't see anything nasty when running on DG1, which 
does make use of TTM_PL_FLAG_CONTIGUOUS,

Reviewed-by: Matthew Auld 


+
+   if (new_size == drm_buddy_block_size(mm, block))
+   return 0;
+
+   list_del(>link);
+   mark_free(mm, block);
+   mm->avail += drm_buddy_block_size(mm, block);
+
+   /* Prevent recursively freeing this node */
+   parent = block->parent;
+   block->parent = NULL;
+
+   new_start = drm_buddy_block_offset(block);
+   list_add(>tmp_link, );
+   err =  __alloc_range(mm, , new_start, new_size, blocks);
+   if (err) {
+   mark_allocated(block);
+   mm->avail -= drm_buddy_block_size(mm, block);
+   list_add(>link, blocks);
+   }
+
+   block->parent = parent;
+   return err;
+}
+EXPORT_SYMBOL(drm_buddy_block_trim);
+
  /**
   * drm_buddy_alloc_blocks - 

[Intel-gfx] ✗ Fi.CI.IGT: failure for Add driver for GSC controller (rev3)

[Patchwork]

== Series Details ==

Series: Add driver for GSC controller (rev3)
URL   : https://patchwork.freedesktop.org/series/98066/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_2_full -> Patchwork_22041_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22041_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22041_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22041_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-tglb7/igt@kms_frontbuffer_track...@fbcpsr-indfb-scaledprimary.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/shard-tglb8/igt@kms_frontbuffer_track...@fbcpsr-indfb-scaledprimary.html

  
Known issues


  Here are the changes found in Patchwork_22041_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-apl:  ([PASS][3], [PASS][4], [PASS][5], [PASS][6], 
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], 
[PASS][25], [PASS][26], [PASS][27]) -> ([FAIL][28], [PASS][29], [PASS][30], 
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], 
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], 
[PASS][49], [PASS][50], [PASS][51], [PASS][52]) ([i915#4386])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl8/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl8/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl8/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl7/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl7/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl7/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl7/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl6/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl6/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl6/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl6/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl4/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl3/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl3/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl3/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl2/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl2/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl2/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl1/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl1/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl1/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl1/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/shard-apl1/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/shard-apl1/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/shard-apl1/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/shard-apl1/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/shard-apl2/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/shard-apl2/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/shard-apl2/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/shard-apl2/boot.html
   [36]: 

Re: [Intel-gfx] [PATCH 0/7] DRM kmap() fixes and kmap_local_page() conversions

[Ira Weiny]

On Thu, Jan 20, 2022 at 04:48:50PM +0100, Daniel Vetter wrote:
> On Thu, Jan 20, 2022 at 09:16:35AM +0100, Christian König wrote:
> > Am 20.01.22 um 00:55 schrieb Ira Weiny:
> > > On Wed, Jan 19, 2022 at 06:24:22PM +0100, Daniel Vetter wrote:
> > > > On Wed, Jan 19, 2022 at 08:53:56AM -0800, Ira Weiny wrote:
> > > > > On Fri, Dec 10, 2021 at 03:23:57PM -0800, 'Ira Weiny' wrote:
> > > > > > From: Ira Weiny 
> > > > > > 
> > > > > > This series starts by converting the last easy kmap() uses to
> > > > > > kmap_local_page().
> > > > > > 
> > > > > > There is one more call to kmap() wrapped in ttm_bo_kmap_ttm().  
> > > > > > Unfortunately,
> > > > > > ttm_bo_kmap_ttm() is called in a number of different ways including 
> > > > > > some which
> > > > > > are not thread local.  I have a patch to convert that call.  
> > > > > > However, it is not
> > > > > > straight forward so it is not included in this series.
> > > > > > 
> > > > > > The final 2 patches fix bugs found while working on the 
> > > > > > ttm_bo_kmap_ttm()
> > > > > > conversion.
> > > > > Gentile ping on this series?  Will it make this merge window?
> > > > I think this fell through the cracks and so no. Note that generally we
> > > > feature-freeze drm tree around -rc6 anyway for the upcoming merge 
> > > > window,
> > > > so you were cutting this all a bit close anyway.
> > > Ok, No problem.  I just had not heard if this was picked up or not.
> > > 
> > > > Also looks like the ttm
> > > > kmap caching question didn't get resolved?
> > > I'm sorry I thought it was resolve for this series.  Christian said the 
> > > patches
> > > in this series were "a good bug fix" even if not strictly necessary.[1]  
> > > Beyond
> > > this series I was discussing where to go from here, and is it possible to 
> > > go
> > > further with more changes.[2]  At the moment I don't think I will.
> > > 
> > > Christian did I misunderstand?  I can drop patch 6 and 7 if they are not 
> > > proper
> > > bug fixes or at least clarifications to the code.
> > 
> > Yeah, it is indeed a correct cleanup. I would just *not* put a CC stable on
> > it because it doesn't really fix anything.
> 
> Ok can you pls get the amd/radeon ones stuffed into alex' tree? Or do we
> want to put all the ttm ones into drm-misc instead?

I just updated to the latest master and there is a minor conflict.  Since this
is not going in this window.  Let me rebase and resend.

Ira

> -Daniel
> 

Re: [Intel-gfx] [PATCH 6/7] drm: Document fdinfo format specification

[Rob Clark]

On Wed, Jan 19, 2022 at 7:09 AM Daniel Vetter  wrote:
>
> On Thu, Jan 06, 2022 at 04:55:35PM +, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin 
> >
> > Proposal to standardise the fdinfo text format as optionally output by DRM
> > drivers.
> >
> > Idea is that a simple but, well defined, spec will enable generic
> > userspace tools to be written while at the same time avoiding a more heavy
> > handed approach of adding a mid-layer to DRM.
> >
> > i915 implements a subset of the spec, everything apart from the memory
> > stats currently, and a matching intel_gpu_top tool exists.
> >
> > Open is to see if AMD can migrate to using the proposed GPU utilisation
> > key-value pairs, or if they are not workable to see whether to go
> > vendor specific, or if a standardised  alternative can be found which is
> > workable for both drivers.
> >
> > Same for the memory utilisation key-value pairs proposal.
> >
> > v2:
> >  * Update for removal of name and pid.
> >
> > v3:
> >  * 'Drm-driver' tag will be obtained from struct drm_driver.name. (Daniel)
> >
> > Signed-off-by: Tvrtko Ursulin 
> > Cc: David M Nieto 
> > Cc: Christian König 
> > Cc: Daniel Vetter 
> > Cc: Daniel Stone 
> > Cc: Chris Healy 
> > Acked-by: Christian König 
>
> I'm assuming this ack here and later on is a "amdgpu plans to use this
> too" kind of affair. Especially also in the lights of eventually using
> matching semantics for cgroups and everything else tied to gpu execution
> resource management.
>
> If not I'm mildly worried that we're creating fake-standard stuff here
> which cannot actually be used by anything resembling driver-agnostic
> userspace.

I think I could implement something like this for drm/msm.  I am a bit
uncertain about the memory stats (ie. how are we intended to account
for imported/exported/shared bo's)?  But we already track cycles+time
per submit for devfreq, it would be pretty easy to add per drm_file
counters to accumulate the per-submit results.  We could even track
per-context (submitqueue) for processes that have more than a single
context, although not sure if that is useful.

And I think there is probably some room for shared helper to print
parts other than the per-engine stats (and maybe memory stats,
although even that could be a shared implementation for some
drivers).. with a driver callback for the non-generic parts, ie.
something like:

   drm_driver::show_client_stats(struct drm_file *, struct drm_printer *)

but that can come later.

If there is a tool somewhere that displays this info, that would be
useful for testing my implementation.

BR,
-R

> -Daniel
>
> > ---
> >  Documentation/gpu/drm-usage-stats.rst | 97 +++
> >  Documentation/gpu/index.rst   |  1 +
> >  2 files changed, 98 insertions(+)
> >  create mode 100644 Documentation/gpu/drm-usage-stats.rst
> >
> > diff --git a/Documentation/gpu/drm-usage-stats.rst 
> > b/Documentation/gpu/drm-usage-stats.rst
> > new file mode 100644
> > index ..c669026be244
> > --- /dev/null
> > +++ b/Documentation/gpu/drm-usage-stats.rst
> > @@ -0,0 +1,97 @@
> > +.. _drm-client-usage-stats:
> > +
> > +==
> > +DRM client usage stats
> > +==
> > +
> > +DRM drivers can choose to export partly standardised text output via the
> > +`fops->show_fdinfo()` as part of the driver specific file operations 
> > registered
> > +in the `struct drm_driver` object registered with the DRM core.
> > +
> > +One purpose of this output is to enable writing as generic as practicaly
> > +feasible `top(1)` like userspace monitoring tools.
> > +
> > +Given the differences between various DRM drivers the specification of the
> > +output is split between common and driver specific parts. Having said that,
> > +wherever possible effort should still be made to standardise as much as
> > +possible.
> > +
> > +File format specification
> > +=
> > +
> > +- File shall contain one key value pair per one line of text.
> > +- Colon character (`:`) must be used to delimit keys and values.
> > +- All keys shall be prefixed with `drm-`.
> > +- Whitespace between the delimiter and first non-whitespace character 
> > shall be
> > +  ignored when parsing.
> > +- Neither keys or values are allowed to contain whitespace characters.
> > +- Numerical key value pairs can end with optional unit string.
> > +- Data type of the value is fixed as defined in the specification.
> > +
> > +Key types
> > +-
> > +
> > +1. Mandatory, fully standardised.
> > +2. Optional, fully standardised.
> > +3. Driver specific.
> > +
> > +Data types
> > +--
> > +
> > +-  - Unsigned integer without defining the maximum value.
> > +-  - String excluding any above defined reserved characters or 
> > whitespace.
> > +
> > +Mandatory fully standardised keys
> > +-
> > +
> > +- drm-driver: 
> > +
> > +String shall contain the name this driver registered as via the respective
> > 

Re: [Intel-gfx] [PATCH] drm/i915: Add needs_compact_pt flag

[Robert Beckett]

On 20/01/2022 16:21, Ramalingam C wrote:

Add a new platform flag, needs_compact_pt, to mark the requirement of
compact pt layout support for the ppGTT when using 64K GTT pages.

With this flag has_64k_pages will only indicate requirement of 64K
GTT page sizes or larger for device local memory access.

Suggested-by: Matthew Auld 
Signed-off-by: Ramalingam C 
cc: Robert Beckett 
---
  drivers/gpu/drm/i915/i915_drv.h  | 10 +++---
  drivers/gpu/drm/i915/i915_pci.c  |  2 ++
  drivers/gpu/drm/i915/intel_device_info.h |  1 +
  3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 890f1f6fbc49..23f4713005bb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1512,12 +1512,16 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
  
  /*

   * Set this flag, when platform requires 64K GTT page sizes or larger for
- * device local memory access. Also this flag implies that we require or
- * at least support the compact PT layout for the ppGTT when using the 64K
- * GTT pages.
+ * device local memory access.
   */
  #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
  
+/* Set this flag when platform doesn't allow both 64k pages and 4k pages in

+ * the same PT. this flag means we need to support compact PT layout for the
+ * ppGTT when using the 64K GTT pages.
+ */
+#define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt)
+
  #define HAS_IPC(dev_priv)  (INTEL_INFO(dev_priv)->display.has_ipc)
  
  #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8261b6455747..3e7555ce6894 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1028,6 +1028,7 @@ static const struct intel_device_info xehpsdv_info = {
PLATFORM(INTEL_XEHPSDV),
.display = { },
.has_64k_pages = 1,
+   .needs_compact_pt = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
@@ -1046,6 +1047,7 @@ static const struct intel_device_info dg2_info = {
.media.rel = 55,
PLATFORM(INTEL_DG2),
.has_64k_pages = 1,
+   .needs_compact_pt = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) |
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 3699b1c539ea..8ff676f49471 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -130,6 +130,7 @@ enum intel_ppgtt_type {
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
func(has_64k_pages); \
+   func(needs_compact_pt; \


missing `)`
instead of chucking untested patches on ml, I'll add a fixed version to 
the in review series and include it in v3 after testing



func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_global_mocs); \

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Add needs_compact_pt flag

[Patchwork]

== Series Details ==

Series: drm/i915: Add needs_compact_pt flag
URL   : https://patchwork.freedesktop.org/series/99105/
State : failure

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  DESCEND objtool
  CHK include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/i915_driver.o
In file included from ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h:11,
 from ./drivers/gpu/drm/i915/gt/uc/intel_guc.h:19,
 from ./drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
 from ./drivers/gpu/drm/i915/gt/intel_gt_types.h:18,
 from ./drivers/gpu/drm/i915/gt/intel_engine.h:18,
 from ./drivers/gpu/drm/i915/i915_drv.h:85,
 from ./drivers/gpu/drm/i915/gt/intel_context.h:14,
 from drivers/gpu/drm/i915/gem/i915_gem_context.h:12,
 from drivers/gpu/drm/i915/i915_driver.c:64:
./drivers/gpu/drm/i915/intel_device_info.h:277: error: unterminated argument 
list invoking macro "DEFINE_FLAG"
 #endif
 
./drivers/gpu/drm/i915/intel_device_info.h:203:25: error: expected 
specifier-qualifier-list before ‘DEFINE_FLAG’
  DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 ^~~
./drivers/gpu/drm/i915/intel_device_info.h:133:2: note: in definition of macro 
‘DEV_INFO_FOR_EACH_FLAG’
  func(needs_compact_pt; \
  ^~~~
scripts/Makefile.build:287: recipe for target 
'drivers/gpu/drm/i915/i915_driver.o' failed
make[4]: *** [drivers/gpu/drm/i915/i915_driver.o] Error 1
scripts/Makefile.build:549: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:549: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:549: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1846: recipe for target 'drivers' failed
make: *** [drivers] Error 2

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915: enforce min GTT alignment for discrete cards

[C, Ramalingam]

On 2022-01-20 at 16:09:01 +, Robert Beckett wrote:
> 
> 
> On 20/01/2022 15:58, Matthew Auld wrote:
> > On 20/01/2022 15:44, Robert Beckett wrote:
> > > 
> > > 
> > > On 20/01/2022 14:59, Matthew Auld wrote:
> > > > On 20/01/2022 13:15, Robert Beckett wrote:
> > > > > 
> > > > > 
> > > > > On 20/01/2022 11:46, Ramalingam C wrote:
> > > > > > On 2022-01-18 at 17:50:34 +, Robert Beckett wrote:
> > > > > > > From: Matthew Auld 
> > > > > > > 
> > > > > > > For local-memory objects we need to align the GTT addresses
> > > > > > > to 64K, both for the ppgtt and ggtt.
> > > > > > > 
> > > > > > > We need to support vm->min_alignment > 4K, depending
> > > > > > > on the vm itself and the type of object we are inserting.
> > > > > > > With this in mind update the GTT selftests to take this
> > > > > > > into account.
> > > > > > > 
> > > > > > > For DG2 we further align and pad lmem object GTT addresses
> > > > > > > to 2MB to ensure PDEs contain consistent page sizes as
> > > > > > > required by the HW.
> > > > > > > 
> > > > > > > Signed-off-by: Matthew Auld 
> > > > > > > Signed-off-by: Ramalingam C 
> > > > > > > Signed-off-by: Robert Beckett 
> > > > > > > Cc: Joonas Lahtinen 
> > > > > > > Cc: Rodrigo Vivi 
> > > > > > > ---
> > > > > > >   .../i915/gem/selftests/i915_gem_client_blt.c  | 23 +++--
> > > > > > >   drivers/gpu/drm/i915/gt/intel_gtt.c   | 14 +++
> > > > > > >   drivers/gpu/drm/i915/gt/intel_gtt.h   |  9 ++
> > > > > > >   drivers/gpu/drm/i915/i915_vma.c   | 14 +++
> > > > > > >   drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 96
> > > > > > > ---
> > > > > > >   5 files changed, 115 insertions(+), 41 deletions(-)
> > > > > > > 
> > > > > > > diff --git
> > > > > > > a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> > > > > > > b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> > > > > > > index c08f766e6e15..7fee95a65414 100644
> > > > > > > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> > > > > > > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> > > > > > > @@ -39,6 +39,7 @@ struct tiled_blits {
> > > > > > >   struct blit_buffer scratch;
> > > > > > >   struct i915_vma *batch;
> > > > > > >   u64 hole;
> > > > > > > +    u64 align;
> > > > > > >   u32 width;
> > > > > > >   u32 height;
> > > > > > >   };
> > > > > > > @@ -410,14 +411,21 @@ tiled_blits_create(struct
> > > > > > > intel_engine_cs *engine, struct rnd_state *prng)
> > > > > > >   goto err_free;
> > > > > > >   }
> > > > > > > -    hole_size = 2 * PAGE_ALIGN(WIDTH * HEIGHT * 4);
> > > > > > > +    t->align = I915_GTT_PAGE_SIZE_2M; /* XXX worst
> > > > > > > case, derive from vm! */
> > > > > > > +    t->align = max(t->align,
> > > > > > > +   i915_vm_min_alignment(t->ce->vm,
> > > > > > > INTEL_MEMORY_LOCAL));
> > > > > > > +    t->align = max(t->align,
> > > > > > > +   i915_vm_min_alignment(t->ce->vm,
> > > > > > > INTEL_MEMORY_SYSTEM));
> > > > > > > +
> > > > > > > +    hole_size = 2 * round_up(WIDTH * HEIGHT * 4, t->align);
> > > > > > >   hole_size *= 2; /* room to maneuver */
> > > > > > > -    hole_size += 2 * I915_GTT_MIN_ALIGNMENT;
> > > > > > > +    hole_size += 2 * t->align; /* padding on either side */
> > > > > > >   mutex_lock(>ce->vm->mutex);
> > > > > > >   memset(, 0, sizeof(hole));
> > > > > > >   err = drm_mm_insert_node_in_range(>ce->vm->mm, ,
> > > > > > > -  hole_size, 0, I915_COLOR_UNEVICTABLE,
> > > > > > > +  hole_size, t->align,
> > > > > > > +  I915_COLOR_UNEVICTABLE,
> > > > > > >     0, U64_MAX,
> > > > > > >     DRM_MM_INSERT_BEST);
> > > > > > >   if (!err)
> > > > > > > @@ -428,7 +436,7 @@ tiled_blits_create(struct
> > > > > > > intel_engine_cs *engine, struct rnd_state *prng)
> > > > > > >   goto err_put;
> > > > > > >   }
> > > > > > > -    t->hole = hole.start + I915_GTT_MIN_ALIGNMENT;
> > > > > > > +    t->hole = hole.start + t->align;
> > > > > > >   pr_info("Using hole at %llx\n", t->hole);
> > > > > > >   err = tiled_blits_create_buffers(t, WIDTH, HEIGHT, prng);
> > > > > > > @@ -455,7 +463,7 @@ static void
> > > > > > > tiled_blits_destroy(struct tiled_blits *t)
> > > > > > >   static int tiled_blits_prepare(struct tiled_blits *t,
> > > > > > >  struct rnd_state *prng)
> > > > > > >   {
> > > > > > > -    u64 offset = PAGE_ALIGN(t->width * t->height * 4);
> > > > > > > +    u64 offset = round_up(t->width * t->height * 4, t->align);
> > > > > > >   u32 *map;
> > > > > > >   int err;
> > > > > > >   int i;
> > > > > > > @@ -486,8 +494,7 @@ static int
> > > > > > > tiled_blits_prepare(struct tiled_blits *t,
> > > > > > >   static int tiled_blits_bounce(struct tiled_blits
> > > > > > > *t, struct rnd_state *prng)
> > > > > > >   {
> > > > > > > -    u64 offset =
> 

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915: enforce min GTT alignment for discrete cards

[Matthew Auld]

On 20/01/2022 16:09, Robert Beckett wrote:



On 20/01/2022 15:58, Matthew Auld wrote:

On 20/01/2022 15:44, Robert Beckett wrote:



On 20/01/2022 14:59, Matthew Auld wrote:

On 20/01/2022 13:15, Robert Beckett wrote:



On 20/01/2022 11:46, Ramalingam C wrote:

On 2022-01-18 at 17:50:34 +, Robert Beckett wrote:

From: Matthew Auld 

For local-memory objects we need to align the GTT addresses
to 64K, both for the ppgtt and ggtt.

We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.

For DG2 we further align and pad lmem object GTT addresses
to 2MB to ensure PDEs contain consistent page sizes as
required by the HW.

Signed-off-by: Matthew Auld 
Signed-off-by: Ramalingam C 
Signed-off-by: Robert Beckett 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
---
  .../i915/gem/selftests/i915_gem_client_blt.c  | 23 +++--
  drivers/gpu/drm/i915/gt/intel_gtt.c   | 14 +++
  drivers/gpu/drm/i915/gt/intel_gtt.h   |  9 ++
  drivers/gpu/drm/i915/i915_vma.c   | 14 +++
  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 96 
---

  5 files changed, 115 insertions(+), 41 deletions(-)

diff --git 
a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

index c08f766e6e15..7fee95a65414 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -39,6 +39,7 @@ struct tiled_blits {
  struct blit_buffer scratch;
  struct i915_vma *batch;
  u64 hole;
+    u64 align;
  u32 width;
  u32 height;
  };
@@ -410,14 +411,21 @@ tiled_blits_create(struct intel_engine_cs 
*engine, struct rnd_state *prng)

  goto err_free;
  }
-    hole_size = 2 * PAGE_ALIGN(WIDTH * HEIGHT * 4);
+    t->align = I915_GTT_PAGE_SIZE_2M; /* XXX worst case, derive 
from vm! */

+    t->align = max(t->align,
+   i915_vm_min_alignment(t->ce->vm, 
INTEL_MEMORY_LOCAL));

+    t->align = max(t->align,
+   i915_vm_min_alignment(t->ce->vm, 
INTEL_MEMORY_SYSTEM));

+
+    hole_size = 2 * round_up(WIDTH * HEIGHT * 4, t->align);
  hole_size *= 2; /* room to maneuver */
-    hole_size += 2 * I915_GTT_MIN_ALIGNMENT;
+    hole_size += 2 * t->align; /* padding on either side */
  mutex_lock(>ce->vm->mutex);
  memset(, 0, sizeof(hole));
  err = drm_mm_insert_node_in_range(>ce->vm->mm, ,
-  hole_size, 0, I915_COLOR_UNEVICTABLE,
+  hole_size, t->align,
+  I915_COLOR_UNEVICTABLE,
    0, U64_MAX,
    DRM_MM_INSERT_BEST);
  if (!err)
@@ -428,7 +436,7 @@ tiled_blits_create(struct intel_engine_cs 
*engine, struct rnd_state *prng)

  goto err_put;
  }
-    t->hole = hole.start + I915_GTT_MIN_ALIGNMENT;
+    t->hole = hole.start + t->align;
  pr_info("Using hole at %llx\n", t->hole);
  err = tiled_blits_create_buffers(t, WIDTH, HEIGHT, prng);
@@ -455,7 +463,7 @@ static void tiled_blits_destroy(struct 
tiled_blits *t)

  static int tiled_blits_prepare(struct tiled_blits *t,
 struct rnd_state *prng)
  {
-    u64 offset = PAGE_ALIGN(t->width * t->height * 4);
+    u64 offset = round_up(t->width * t->height * 4, t->align);
  u32 *map;
  int err;
  int i;
@@ -486,8 +494,7 @@ static int tiled_blits_prepare(struct 
tiled_blits *t,
  static int tiled_blits_bounce(struct tiled_blits *t, struct 
rnd_state *prng)

  {
-    u64 offset =
-    round_up(t->width * t->height * 4, 2 * 
I915_GTT_MIN_ALIGNMENT);

+    u64 offset = round_up(t->width * t->height * 4, 2 * t->align);
  int err;
  /* We want to check position invariant tiling across GTT 
eviction */
@@ -500,7 +507,7 @@ static int tiled_blits_bounce(struct 
tiled_blits *t, struct rnd_state *prng)
  /* Reposition so that we overlap the old addresses, and 
slightly off */

  err = tiled_blit(t,
- >buffers[2], t->hole + I915_GTT_MIN_ALIGNMENT,
+ >buffers[2], t->hole + t->align,
   >buffers[1], t->hole + 3 * offset / 2);
  if (err)
  return err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c 
b/drivers/gpu/drm/i915/gt/intel_gtt.c

index 46be4197b93f..7c92b25c0f26 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -223,6 +223,20 @@ void i915_address_space_init(struct 
i915_address_space *vm, int subclass)

  GEM_BUG_ON(!vm->total);
  drm_mm_init(>mm, 0, vm->total);
+
+    memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT,
+ ARRAY_SIZE(vm->min_alignment));
+
+    if (HAS_64K_PAGES(vm->i915)) {
+    if (IS_DG2(vm->i915)) {
I think we need this 2M alignment for all platform with 
HAS_64K_PAGES.

Not only for DG2.


really? can we get confirmation of this?
this contradicts the documentation in patch 

[Intel-gfx] [PATCH] drm/i915: Add needs_compact_pt flag

[Ramalingam C]

Add a new platform flag, needs_compact_pt, to mark the requirement of
compact pt layout support for the ppGTT when using 64K GTT pages.

With this flag has_64k_pages will only indicate requirement of 64K
GTT page sizes or larger for device local memory access.

Suggested-by: Matthew Auld 
Signed-off-by: Ramalingam C 
cc: Robert Beckett 
---
 drivers/gpu/drm/i915/i915_drv.h  | 10 +++---
 drivers/gpu/drm/i915/i915_pci.c  |  2 ++
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 890f1f6fbc49..23f4713005bb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1512,12 +1512,16 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 /*
  * Set this flag, when platform requires 64K GTT page sizes or larger for
- * device local memory access. Also this flag implies that we require or
- * at least support the compact PT layout for the ppGTT when using the 64K
- * GTT pages.
+ * device local memory access.
  */
 #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
 
+/* Set this flag when platform doesn't allow both 64k pages and 4k pages in
+ * the same PT. this flag means we need to support compact PT layout for the
+ * ppGTT when using the 64K GTT pages.
+ */
+#define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt)
+
 #define HAS_IPC(dev_priv)   (INTEL_INFO(dev_priv)->display.has_ipc)
 
 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8261b6455747..3e7555ce6894 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1028,6 +1028,7 @@ static const struct intel_device_info xehpsdv_info = {
PLATFORM(INTEL_XEHPSDV),
.display = { },
.has_64k_pages = 1,
+   .needs_compact_pt = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
@@ -1046,6 +1047,7 @@ static const struct intel_device_info dg2_info = {
.media.rel = 55,
PLATFORM(INTEL_DG2),
.has_64k_pages = 1,
+   .needs_compact_pt = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) |
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 3699b1c539ea..8ff676f49471 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -130,6 +130,7 @@ enum intel_ppgtt_type {
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
func(has_64k_pages); \
+   func(needs_compact_pt; \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_global_mocs); \
-- 
2.20.1

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915: enforce min GTT alignment for discrete cards

[Robert Beckett]

On 20/01/2022 15:58, Matthew Auld wrote:

On 20/01/2022 15:44, Robert Beckett wrote:



On 20/01/2022 14:59, Matthew Auld wrote:

On 20/01/2022 13:15, Robert Beckett wrote:



On 20/01/2022 11:46, Ramalingam C wrote:

On 2022-01-18 at 17:50:34 +, Robert Beckett wrote:

From: Matthew Auld 

For local-memory objects we need to align the GTT addresses
to 64K, both for the ppgtt and ggtt.

We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.

For DG2 we further align and pad lmem object GTT addresses
to 2MB to ensure PDEs contain consistent page sizes as
required by the HW.

Signed-off-by: Matthew Auld 
Signed-off-by: Ramalingam C 
Signed-off-by: Robert Beckett 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
---
  .../i915/gem/selftests/i915_gem_client_blt.c  | 23 +++--
  drivers/gpu/drm/i915/gt/intel_gtt.c   | 14 +++
  drivers/gpu/drm/i915/gt/intel_gtt.h   |  9 ++
  drivers/gpu/drm/i915/i915_vma.c   | 14 +++
  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 96 
---

  5 files changed, 115 insertions(+), 41 deletions(-)

diff --git 
a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

index c08f766e6e15..7fee95a65414 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -39,6 +39,7 @@ struct tiled_blits {
  struct blit_buffer scratch;
  struct i915_vma *batch;
  u64 hole;
+    u64 align;
  u32 width;
  u32 height;
  };
@@ -410,14 +411,21 @@ tiled_blits_create(struct intel_engine_cs 
*engine, struct rnd_state *prng)

  goto err_free;
  }
-    hole_size = 2 * PAGE_ALIGN(WIDTH * HEIGHT * 4);
+    t->align = I915_GTT_PAGE_SIZE_2M; /* XXX worst case, derive 
from vm! */

+    t->align = max(t->align,
+   i915_vm_min_alignment(t->ce->vm, 
INTEL_MEMORY_LOCAL));

+    t->align = max(t->align,
+   i915_vm_min_alignment(t->ce->vm, 
INTEL_MEMORY_SYSTEM));

+
+    hole_size = 2 * round_up(WIDTH * HEIGHT * 4, t->align);
  hole_size *= 2; /* room to maneuver */
-    hole_size += 2 * I915_GTT_MIN_ALIGNMENT;
+    hole_size += 2 * t->align; /* padding on either side */
  mutex_lock(>ce->vm->mutex);
  memset(, 0, sizeof(hole));
  err = drm_mm_insert_node_in_range(>ce->vm->mm, ,
-  hole_size, 0, I915_COLOR_UNEVICTABLE,
+  hole_size, t->align,
+  I915_COLOR_UNEVICTABLE,
    0, U64_MAX,
    DRM_MM_INSERT_BEST);
  if (!err)
@@ -428,7 +436,7 @@ tiled_blits_create(struct intel_engine_cs 
*engine, struct rnd_state *prng)

  goto err_put;
  }
-    t->hole = hole.start + I915_GTT_MIN_ALIGNMENT;
+    t->hole = hole.start + t->align;
  pr_info("Using hole at %llx\n", t->hole);
  err = tiled_blits_create_buffers(t, WIDTH, HEIGHT, prng);
@@ -455,7 +463,7 @@ static void tiled_blits_destroy(struct 
tiled_blits *t)

  static int tiled_blits_prepare(struct tiled_blits *t,
 struct rnd_state *prng)
  {
-    u64 offset = PAGE_ALIGN(t->width * t->height * 4);
+    u64 offset = round_up(t->width * t->height * 4, t->align);
  u32 *map;
  int err;
  int i;
@@ -486,8 +494,7 @@ static int tiled_blits_prepare(struct 
tiled_blits *t,
  static int tiled_blits_bounce(struct tiled_blits *t, struct 
rnd_state *prng)

  {
-    u64 offset =
-    round_up(t->width * t->height * 4, 2 * 
I915_GTT_MIN_ALIGNMENT);

+    u64 offset = round_up(t->width * t->height * 4, 2 * t->align);
  int err;
  /* We want to check position invariant tiling across GTT 
eviction */
@@ -500,7 +507,7 @@ static int tiled_blits_bounce(struct 
tiled_blits *t, struct rnd_state *prng)
  /* Reposition so that we overlap the old addresses, and 
slightly off */

  err = tiled_blit(t,
- >buffers[2], t->hole + I915_GTT_MIN_ALIGNMENT,
+ >buffers[2], t->hole + t->align,
   >buffers[1], t->hole + 3 * offset / 2);
  if (err)
  return err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c 
b/drivers/gpu/drm/i915/gt/intel_gtt.c

index 46be4197b93f..7c92b25c0f26 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -223,6 +223,20 @@ void i915_address_space_init(struct 
i915_address_space *vm, int subclass)

  GEM_BUG_ON(!vm->total);
  drm_mm_init(>mm, 0, vm->total);
+
+    memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT,
+ ARRAY_SIZE(vm->min_alignment));
+
+    if (HAS_64K_PAGES(vm->i915)) {
+    if (IS_DG2(vm->i915)) {

I think we need this 2M alignment for all platform with HAS_64K_PAGES.
Not only for DG2.


really? can we get confirmation of this?
this contradicts the documentation in patch 4, which you reviewed, 
so I am confused 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: split out i915_reg_read_ioctl() to i915_ioctl.[ch] (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: split out i915_reg_read_ioctl() to i915_ioctl.[ch] (rev2)
URL   : https://patchwork.freedesktop.org/series/99096/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_2_full -> Patchwork_22040_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22040_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22040_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22040_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
- shard-skl:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-skl4/igt@kms_flip@flip-vs-suspend-interrupti...@a-edp1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/shard-skl8/igt@kms_flip@flip-vs-suspend-interrupti...@a-edp1.html

  
Known issues


  Here are the changes found in Patchwork_22040_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@in-flight-suspend:
- shard-apl:  [PASS][3] -> [INCOMPLETE][4] ([i915#180])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-apl3/igt@gem_...@in-flight-suspend.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/shard-apl1/igt@gem_...@in-flight-suspend.html

  * igt@gem_eio@kms:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#232])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-tglb7/igt@gem_...@kms.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/shard-tglb2/igt@gem_...@kms.html

  * igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#4525]) +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-iclb1/igt@gem_exec_balan...@parallel.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/shard-iclb7/igt@gem_exec_balan...@parallel.html

  * igt@gem_exec_capture@pi@vcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][9] ([i915#4547])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/shard-skl9/igt@gem_exec_capture@p...@vcs0.html

  * igt@gem_exec_fair@basic-deadline:
- shard-kbl:  [PASS][10] -> [FAIL][11] ([i915#2846])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-kbl3/igt@gem_exec_f...@basic-deadline.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/shard-kbl7/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl:  [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar 
issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs1.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/shard-kbl3/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2849])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-kbl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/shard-kbl3/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@parallel-random-verify:
- shard-skl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/shard-skl4/igt@gem_lmem_swapp...@parallel-random-verify.html

  * igt@gen7_exec_parse@basic-rejected:
- shard-tglb: NOTRUN -> [SKIP][18] ([fdo#109289])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/shard-tglb5/igt@gen7_exec_pa...@basic-rejected.html

  * igt@gen9_exec_parse@allowed-single:
- shard-skl:  [PASS][19] -> [DMESG-WARN][20] ([i915#1436] / 
[i915#716])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-skl8/igt@gen9_exec_pa...@allowed-single.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/shard-skl6/igt@gen9_exec_pa...@allowed-single.html

  * igt@i915_selftest@mock@requests:
- shard-skl:  [PASS][21] -> [INCOMPLETE][22] ([i915#4919])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/shard-skl7/igt@i915_selftest@m...@requests.html
   [22]: 

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915: enforce min GTT alignment for discrete cards

[Matthew Auld]

On 20/01/2022 15:44, Robert Beckett wrote:



On 20/01/2022 14:59, Matthew Auld wrote:

On 20/01/2022 13:15, Robert Beckett wrote:



On 20/01/2022 11:46, Ramalingam C wrote:

On 2022-01-18 at 17:50:34 +, Robert Beckett wrote:

From: Matthew Auld 

For local-memory objects we need to align the GTT addresses
to 64K, both for the ppgtt and ggtt.

We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.

For DG2 we further align and pad lmem object GTT addresses
to 2MB to ensure PDEs contain consistent page sizes as
required by the HW.

Signed-off-by: Matthew Auld 
Signed-off-by: Ramalingam C 
Signed-off-by: Robert Beckett 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
---
  .../i915/gem/selftests/i915_gem_client_blt.c  | 23 +++--
  drivers/gpu/drm/i915/gt/intel_gtt.c   | 14 +++
  drivers/gpu/drm/i915/gt/intel_gtt.h   |  9 ++
  drivers/gpu/drm/i915/i915_vma.c   | 14 +++
  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 96 
---

  5 files changed, 115 insertions(+), 41 deletions(-)

diff --git 
a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

index c08f766e6e15..7fee95a65414 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -39,6 +39,7 @@ struct tiled_blits {
  struct blit_buffer scratch;
  struct i915_vma *batch;
  u64 hole;
+    u64 align;
  u32 width;
  u32 height;
  };
@@ -410,14 +411,21 @@ tiled_blits_create(struct intel_engine_cs 
*engine, struct rnd_state *prng)

  goto err_free;
  }
-    hole_size = 2 * PAGE_ALIGN(WIDTH * HEIGHT * 4);
+    t->align = I915_GTT_PAGE_SIZE_2M; /* XXX worst case, derive 
from vm! */

+    t->align = max(t->align,
+   i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_LOCAL));
+    t->align = max(t->align,
+   i915_vm_min_alignment(t->ce->vm, 
INTEL_MEMORY_SYSTEM));

+
+    hole_size = 2 * round_up(WIDTH * HEIGHT * 4, t->align);
  hole_size *= 2; /* room to maneuver */
-    hole_size += 2 * I915_GTT_MIN_ALIGNMENT;
+    hole_size += 2 * t->align; /* padding on either side */
  mutex_lock(>ce->vm->mutex);
  memset(, 0, sizeof(hole));
  err = drm_mm_insert_node_in_range(>ce->vm->mm, ,
-  hole_size, 0, I915_COLOR_UNEVICTABLE,
+  hole_size, t->align,
+  I915_COLOR_UNEVICTABLE,
    0, U64_MAX,
    DRM_MM_INSERT_BEST);
  if (!err)
@@ -428,7 +436,7 @@ tiled_blits_create(struct intel_engine_cs 
*engine, struct rnd_state *prng)

  goto err_put;
  }
-    t->hole = hole.start + I915_GTT_MIN_ALIGNMENT;
+    t->hole = hole.start + t->align;
  pr_info("Using hole at %llx\n", t->hole);
  err = tiled_blits_create_buffers(t, WIDTH, HEIGHT, prng);
@@ -455,7 +463,7 @@ static void tiled_blits_destroy(struct 
tiled_blits *t)

  static int tiled_blits_prepare(struct tiled_blits *t,
 struct rnd_state *prng)
  {
-    u64 offset = PAGE_ALIGN(t->width * t->height * 4);
+    u64 offset = round_up(t->width * t->height * 4, t->align);
  u32 *map;
  int err;
  int i;
@@ -486,8 +494,7 @@ static int tiled_blits_prepare(struct 
tiled_blits *t,
  static int tiled_blits_bounce(struct tiled_blits *t, struct 
rnd_state *prng)

  {
-    u64 offset =
-    round_up(t->width * t->height * 4, 2 * 
I915_GTT_MIN_ALIGNMENT);

+    u64 offset = round_up(t->width * t->height * 4, 2 * t->align);
  int err;
  /* We want to check position invariant tiling across GTT 
eviction */
@@ -500,7 +507,7 @@ static int tiled_blits_bounce(struct 
tiled_blits *t, struct rnd_state *prng)
  /* Reposition so that we overlap the old addresses, and 
slightly off */

  err = tiled_blit(t,
- >buffers[2], t->hole + I915_GTT_MIN_ALIGNMENT,
+ >buffers[2], t->hole + t->align,
   >buffers[1], t->hole + 3 * offset / 2);
  if (err)
  return err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c 
b/drivers/gpu/drm/i915/gt/intel_gtt.c

index 46be4197b93f..7c92b25c0f26 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -223,6 +223,20 @@ void i915_address_space_init(struct 
i915_address_space *vm, int subclass)

  GEM_BUG_ON(!vm->total);
  drm_mm_init(>mm, 0, vm->total);
+
+    memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT,
+ ARRAY_SIZE(vm->min_alignment));
+
+    if (HAS_64K_PAGES(vm->i915)) {
+    if (IS_DG2(vm->i915)) {

I think we need this 2M alignment for all platform with HAS_64K_PAGES.
Not only for DG2.


really? can we get confirmation of this?
this contradicts the documentation in patch 4, which you reviewed, so 
I am confused now


Starting from DG2, some platforms will have 

[Intel-gfx] ✓ Fi.CI.BAT: success for Add driver for GSC controller (rev3)

[Patchwork]

== Series Details ==

Series: Add driver for GSC controller (rev3)
URL   : https://patchwork.freedesktop.org/series/98066/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_2 -> Patchwork_22041


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/index.html

Participating hosts (46 -> 44)
--

  Missing(2): fi-bsw-cyan fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_22041 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u:   [PASS][1] -> [INCOMPLETE][2] ([i915#146])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@gt_lrc:
- fi-rkl-11600:   [PASS][3] -> [DMESG-FAIL][4] ([i915#2373])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/fi-rkl-11600/igt@i915_selftest@live@gt_lrc.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/fi-rkl-11600/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][5] -> [INCOMPLETE][6] ([i915#3303])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- fi-snb-2600:[PASS][7] -> [INCOMPLETE][8] ([i915#3921])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_psr@primary_page_flip:
- fi-skl-6600u:   [PASS][9] -> [FAIL][10] ([i915#4547])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/fi-skl-6600u/igt@kms_psr@primary_page_flip.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#1436] / 
[i915#4312])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/fi-hsw-4770/igt@run...@aborted.html
- fi-skl-6600u:   NOTRUN -> [FAIL][12] ([i915#4312])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/fi-skl-6600u/igt@run...@aborted.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- fi-bwr-2160:[FAIL][13] ([i915#3194]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/fi-bwr-2160/igt@core_hotunp...@unbind-rebind.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/fi-bwr-2160/igt@core_hotunp...@unbind-rebind.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-6:  [DMESG-FAIL][15] ([i915#4494]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2:  [DMESG-WARN][17] ([i915#4269]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22041/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
  [i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547


Build changes
-

  * Linux: CI_DRM_2 -> Patchwork_22041

  CI-20190529: 20190529
  CI_DRM_2: 55b83480a1824372d372852b3b6ceb5f0827caf1 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6329: 38f656fdd61119105ecfa2c4dac157cd7dcad204 @ 

Re: [Intel-gfx] [PATCH 0/7] DRM kmap() fixes and kmap_local_page() conversions

[Daniel Vetter]

On Thu, Jan 20, 2022 at 09:16:35AM +0100, Christian König wrote:
> Am 20.01.22 um 00:55 schrieb Ira Weiny:
> > On Wed, Jan 19, 2022 at 06:24:22PM +0100, Daniel Vetter wrote:
> > > On Wed, Jan 19, 2022 at 08:53:56AM -0800, Ira Weiny wrote:
> > > > On Fri, Dec 10, 2021 at 03:23:57PM -0800, 'Ira Weiny' wrote:
> > > > > From: Ira Weiny 
> > > > > 
> > > > > This series starts by converting the last easy kmap() uses to
> > > > > kmap_local_page().
> > > > > 
> > > > > There is one more call to kmap() wrapped in ttm_bo_kmap_ttm().  
> > > > > Unfortunately,
> > > > > ttm_bo_kmap_ttm() is called in a number of different ways including 
> > > > > some which
> > > > > are not thread local.  I have a patch to convert that call.  However, 
> > > > > it is not
> > > > > straight forward so it is not included in this series.
> > > > > 
> > > > > The final 2 patches fix bugs found while working on the 
> > > > > ttm_bo_kmap_ttm()
> > > > > conversion.
> > > > Gentile ping on this series?  Will it make this merge window?
> > > I think this fell through the cracks and so no. Note that generally we
> > > feature-freeze drm tree around -rc6 anyway for the upcoming merge window,
> > > so you were cutting this all a bit close anyway.
> > Ok, No problem.  I just had not heard if this was picked up or not.
> > 
> > > Also looks like the ttm
> > > kmap caching question didn't get resolved?
> > I'm sorry I thought it was resolve for this series.  Christian said the 
> > patches
> > in this series were "a good bug fix" even if not strictly necessary.[1]  
> > Beyond
> > this series I was discussing where to go from here, and is it possible to go
> > further with more changes.[2]  At the moment I don't think I will.
> > 
> > Christian did I misunderstand?  I can drop patch 6 and 7 if they are not 
> > proper
> > bug fixes or at least clarifications to the code.
> 
> Yeah, it is indeed a correct cleanup. I would just *not* put a CC stable on
> it because it doesn't really fix anything.

Ok can you pls get the amd/radeon ones stuffed into alex' tree? Or do we
want to put all the ttm ones into drm-misc instead?
-Daniel

> 
> Christian.
> 
> > 
> > Ira
> > 
> > [1] 
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Flkml%2Fc3b173ea-6509-ebbe-b5f9-eeb29f1ce57e%40amd.com%2Fdata=04%7C01%7Cchristian.koenig%40amd.com%7C5e0192210d4640adb88b08d9dba734b1%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637782333459591089%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=4p7jCB6pB4nlcUtLWh6K2Sso9X%2BsRSK7mcD8UavzztQ%3Dreserved=0
> > [2] 
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Flkml%2F20211215210949.GW3538886%40iweiny-DESK2.sc.intel.com%2Fdata=04%7C01%7Cchristian.koenig%40amd.com%7C5e0192210d4640adb88b08d9dba734b1%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637782333459591089%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=6%2BGfSKshg8Xr%2FXJshiU28yHzbg2HcVisVJLDU6tVUT4%3Dreserved=0
> > 
> > > Anyway if patches are stuck resend with RESEND and if people still don't
> > > pick them up poke me and I'll apply as fallback.
> > > 
> > > Cheers, Daniel
> > > 
> > > > Thanks,
> > > > Ira
> > > > 
> > > > > 
> > > > > Ira Weiny (7):
> > > > > drm/i915: Replace kmap() with kmap_local_page()
> > > > > drm/amd: Replace kmap() with kmap_local_page()
> > > > > drm/gma: Remove calls to kmap()
> > > > > drm/radeon: Replace kmap() with kmap_local_page()
> > > > > drm/msm: Alter comment to use kmap_local_page()
> > > > > drm/amdgpu: Ensure kunmap is called on error
> > > > > drm/radeon: Ensure kunmap is called on error
> > > > > 
> > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 
> > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 1 +
> > > > > drivers/gpu/drm/gma500/gma_display.c | 6 ++
> > > > > drivers/gpu/drm/gma500/mmu.c | 8 
> > > > > drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 4 ++--
> > > > > drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 8 
> > > > > drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 ++--
> > > > > drivers/gpu/drm/i915/gt/shmem_utils.c | 4 ++--
> > > > > drivers/gpu/drm/i915/i915_gem.c | 8 
> > > > > drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++--
> > > > > drivers/gpu/drm/msm/msm_gem_submit.c | 4 ++--
> > > > > drivers/gpu/drm/radeon/radeon_ttm.c | 4 ++--
> > > > > drivers/gpu/drm/radeon/radeon_uvd.c | 1 +
> > > > > 13 files changed, 32 insertions(+), 32 deletions(-)
> > > > > 
> > > > > --
> > > > > 2.31.1
> > > > > 
> > > -- 
> > > Daniel Vetter
> > > Software Engineer, Intel Corporation
> > > 

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915: enforce min GTT alignment for discrete cards

[Robert Beckett]

On 20/01/2022 14:59, Matthew Auld wrote:

On 20/01/2022 13:15, Robert Beckett wrote:



On 20/01/2022 11:46, Ramalingam C wrote:

On 2022-01-18 at 17:50:34 +, Robert Beckett wrote:

From: Matthew Auld 

For local-memory objects we need to align the GTT addresses
to 64K, both for the ppgtt and ggtt.

We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.

For DG2 we further align and pad lmem object GTT addresses
to 2MB to ensure PDEs contain consistent page sizes as
required by the HW.

Signed-off-by: Matthew Auld 
Signed-off-by: Ramalingam C 
Signed-off-by: Robert Beckett 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
---
  .../i915/gem/selftests/i915_gem_client_blt.c  | 23 +++--
  drivers/gpu/drm/i915/gt/intel_gtt.c   | 14 +++
  drivers/gpu/drm/i915/gt/intel_gtt.h   |  9 ++
  drivers/gpu/drm/i915/i915_vma.c   | 14 +++
  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 96 
---

  5 files changed, 115 insertions(+), 41 deletions(-)

diff --git 
a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

index c08f766e6e15..7fee95a65414 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -39,6 +39,7 @@ struct tiled_blits {
  struct blit_buffer scratch;
  struct i915_vma *batch;
  u64 hole;
+    u64 align;
  u32 width;
  u32 height;
  };
@@ -410,14 +411,21 @@ tiled_blits_create(struct intel_engine_cs 
*engine, struct rnd_state *prng)

  goto err_free;
  }
-    hole_size = 2 * PAGE_ALIGN(WIDTH * HEIGHT * 4);
+    t->align = I915_GTT_PAGE_SIZE_2M; /* XXX worst case, derive 
from vm! */

+    t->align = max(t->align,
+   i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_LOCAL));
+    t->align = max(t->align,
+   i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_SYSTEM));
+
+    hole_size = 2 * round_up(WIDTH * HEIGHT * 4, t->align);
  hole_size *= 2; /* room to maneuver */
-    hole_size += 2 * I915_GTT_MIN_ALIGNMENT;
+    hole_size += 2 * t->align; /* padding on either side */
  mutex_lock(>ce->vm->mutex);
  memset(, 0, sizeof(hole));
  err = drm_mm_insert_node_in_range(>ce->vm->mm, ,
-  hole_size, 0, I915_COLOR_UNEVICTABLE,
+  hole_size, t->align,
+  I915_COLOR_UNEVICTABLE,
    0, U64_MAX,
    DRM_MM_INSERT_BEST);
  if (!err)
@@ -428,7 +436,7 @@ tiled_blits_create(struct intel_engine_cs 
*engine, struct rnd_state *prng)

  goto err_put;
  }
-    t->hole = hole.start + I915_GTT_MIN_ALIGNMENT;
+    t->hole = hole.start + t->align;
  pr_info("Using hole at %llx\n", t->hole);
  err = tiled_blits_create_buffers(t, WIDTH, HEIGHT, prng);
@@ -455,7 +463,7 @@ static void tiled_blits_destroy(struct 
tiled_blits *t)

  static int tiled_blits_prepare(struct tiled_blits *t,
 struct rnd_state *prng)
  {
-    u64 offset = PAGE_ALIGN(t->width * t->height * 4);
+    u64 offset = round_up(t->width * t->height * 4, t->align);
  u32 *map;
  int err;
  int i;
@@ -486,8 +494,7 @@ static int tiled_blits_prepare(struct 
tiled_blits *t,
  static int tiled_blits_bounce(struct tiled_blits *t, struct 
rnd_state *prng)

  {
-    u64 offset =
-    round_up(t->width * t->height * 4, 2 * 
I915_GTT_MIN_ALIGNMENT);

+    u64 offset = round_up(t->width * t->height * 4, 2 * t->align);
  int err;
  /* We want to check position invariant tiling across GTT 
eviction */
@@ -500,7 +507,7 @@ static int tiled_blits_bounce(struct tiled_blits 
*t, struct rnd_state *prng)
  /* Reposition so that we overlap the old addresses, and 
slightly off */

  err = tiled_blit(t,
- >buffers[2], t->hole + I915_GTT_MIN_ALIGNMENT,
+ >buffers[2], t->hole + t->align,
   >buffers[1], t->hole + 3 * offset / 2);
  if (err)
  return err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c 
b/drivers/gpu/drm/i915/gt/intel_gtt.c

index 46be4197b93f..7c92b25c0f26 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -223,6 +223,20 @@ void i915_address_space_init(struct 
i915_address_space *vm, int subclass)

  GEM_BUG_ON(!vm->total);
  drm_mm_init(>mm, 0, vm->total);
+
+    memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT,
+ ARRAY_SIZE(vm->min_alignment));
+
+    if (HAS_64K_PAGES(vm->i915)) {
+    if (IS_DG2(vm->i915)) {

I think we need this 2M alignment for all platform with HAS_64K_PAGES.
Not only for DG2.


really? can we get confirmation of this?
this contradicts the documentation in patch 4, which you reviewed, so 
I am confused now


Starting from DG2, some platforms will have this new 64K GTT page size 
restriction when 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add driver for GSC controller (rev3)

[Patchwork]

== Series Details ==

Series: Add driver for GSC controller (rev3)
URL   : https://patchwork.freedesktop.org/series/98066/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add driver for GSC controller (rev3)

[Patchwork]

== Series Details ==

Series: Add driver for GSC controller (rev3)
URL   : https://patchwork.freedesktop.org/series/98066/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
9ad89d8f20ab drm/i915/gsc: add gsc as a mei auxiliary device
-:50: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#50: 
new file mode 100644

-:120: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#120: FILE: drivers/gpu/drm/i915/gt/intel_gsc.c:66:
+{
+

-:428: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible 
side-effects?
#428: FILE: drivers/gpu/drm/i915/i915_drv.h:1511:
+#define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || 
HAS_HECI_GSCFI(dev_priv))

total: 0 errors, 1 warnings, 2 checks, 407 lines checked
39d40de075b3 mei: add support for graphics system controller (gsc) devices
-:56: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#56: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 295 lines checked
b48bdec85a23 mei: gsc: setup char driver alive in spite of firmware handshake 
failure
987f5b75c03e mei: gsc: add runtime pm handlers
e0818be8eb6f mei: gsc: retrieve the firmware version

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915: enforce min GTT alignment for discrete cards

[Matthew Auld]

On 20/01/2022 13:15, Robert Beckett wrote:



On 20/01/2022 11:46, Ramalingam C wrote:

On 2022-01-18 at 17:50:34 +, Robert Beckett wrote:

From: Matthew Auld 

For local-memory objects we need to align the GTT addresses
to 64K, both for the ppgtt and ggtt.

We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.

For DG2 we further align and pad lmem object GTT addresses
to 2MB to ensure PDEs contain consistent page sizes as
required by the HW.

Signed-off-by: Matthew Auld 
Signed-off-by: Ramalingam C 
Signed-off-by: Robert Beckett 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
---
  .../i915/gem/selftests/i915_gem_client_blt.c  | 23 +++--
  drivers/gpu/drm/i915/gt/intel_gtt.c   | 14 +++
  drivers/gpu/drm/i915/gt/intel_gtt.h   |  9 ++
  drivers/gpu/drm/i915/i915_vma.c   | 14 +++
  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 96 ---
  5 files changed, 115 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

index c08f766e6e15..7fee95a65414 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -39,6 +39,7 @@ struct tiled_blits {
  struct blit_buffer scratch;
  struct i915_vma *batch;
  u64 hole;
+    u64 align;
  u32 width;
  u32 height;
  };
@@ -410,14 +411,21 @@ tiled_blits_create(struct intel_engine_cs 
*engine, struct rnd_state *prng)

  goto err_free;
  }
-    hole_size = 2 * PAGE_ALIGN(WIDTH * HEIGHT * 4);
+    t->align = I915_GTT_PAGE_SIZE_2M; /* XXX worst case, derive from 
vm! */

+    t->align = max(t->align,
+   i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_LOCAL));
+    t->align = max(t->align,
+   i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_SYSTEM));
+
+    hole_size = 2 * round_up(WIDTH * HEIGHT * 4, t->align);
  hole_size *= 2; /* room to maneuver */
-    hole_size += 2 * I915_GTT_MIN_ALIGNMENT;
+    hole_size += 2 * t->align; /* padding on either side */
  mutex_lock(>ce->vm->mutex);
  memset(, 0, sizeof(hole));
  err = drm_mm_insert_node_in_range(>ce->vm->mm, ,
-  hole_size, 0, I915_COLOR_UNEVICTABLE,
+  hole_size, t->align,
+  I915_COLOR_UNEVICTABLE,
    0, U64_MAX,
    DRM_MM_INSERT_BEST);
  if (!err)
@@ -428,7 +436,7 @@ tiled_blits_create(struct intel_engine_cs 
*engine, struct rnd_state *prng)

  goto err_put;
  }
-    t->hole = hole.start + I915_GTT_MIN_ALIGNMENT;
+    t->hole = hole.start + t->align;
  pr_info("Using hole at %llx\n", t->hole);
  err = tiled_blits_create_buffers(t, WIDTH, HEIGHT, prng);
@@ -455,7 +463,7 @@ static void tiled_blits_destroy(struct 
tiled_blits *t)

  static int tiled_blits_prepare(struct tiled_blits *t,
 struct rnd_state *prng)
  {
-    u64 offset = PAGE_ALIGN(t->width * t->height * 4);
+    u64 offset = round_up(t->width * t->height * 4, t->align);
  u32 *map;
  int err;
  int i;
@@ -486,8 +494,7 @@ static int tiled_blits_prepare(struct tiled_blits 
*t,
  static int tiled_blits_bounce(struct tiled_blits *t, struct 
rnd_state *prng)

  {
-    u64 offset =
-    round_up(t->width * t->height * 4, 2 * I915_GTT_MIN_ALIGNMENT);
+    u64 offset = round_up(t->width * t->height * 4, 2 * t->align);
  int err;
  /* We want to check position invariant tiling across GTT 
eviction */
@@ -500,7 +507,7 @@ static int tiled_blits_bounce(struct tiled_blits 
*t, struct rnd_state *prng)
  /* Reposition so that we overlap the old addresses, and 
slightly off */

  err = tiled_blit(t,
- >buffers[2], t->hole + I915_GTT_MIN_ALIGNMENT,
+ >buffers[2], t->hole + t->align,
   >buffers[1], t->hole + 3 * offset / 2);
  if (err)
  return err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c 
b/drivers/gpu/drm/i915/gt/intel_gtt.c

index 46be4197b93f..7c92b25c0f26 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -223,6 +223,20 @@ void i915_address_space_init(struct 
i915_address_space *vm, int subclass)

  GEM_BUG_ON(!vm->total);
  drm_mm_init(>mm, 0, vm->total);
+
+    memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT,
+ ARRAY_SIZE(vm->min_alignment));
+
+    if (HAS_64K_PAGES(vm->i915)) {
+    if (IS_DG2(vm->i915)) {

I think we need this 2M alignment for all platform with HAS_64K_PAGES.
Not only for DG2.


really? can we get confirmation of this?
this contradicts the documentation in patch 4, which you reviewed, so I 
am confused now


Starting from DG2, some platforms will have this new 64K GTT page size 
restriction when dealing with LMEM. The HAS_64K_PAGES() macro is 

[Intel-gfx] [PATCH v3 5/5] mei: gsc: retrieve the firmware version

[Alexander Usyskin]

Add a hook to retrieve the firmware version of the
GSC devices to bus-fixup.
GSC has a different MKHI clients GUIDs but the same message structure
to retrieve the firmware version as MEI so mei_fwver() can be reused.

CC: Ashutosh Dixit 
Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 
---
 drivers/misc/mei/bus-fixup.c | 25 +
 drivers/misc/mei/hw-me.c |  2 ++
 2 files changed, 27 insertions(+)

diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 67844089db21..59506ba6fc48 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -30,6 +30,12 @@ static const uuid_le mei_nfc_info_guid = MEI_UUID_NFC_INFO;
 #define MEI_UUID_MKHIF_FIX UUID_LE(0x55213584, 0x9a29, 0x4916, \
0xba, 0xdf, 0xf, 0xb7, 0xed, 0x68, 0x2a, 0xeb)
 
+#define MEI_UUID_IGSC_MKHI UUID_LE(0xE2C2AFA2, 0x3817, 0x4D19, \
+   0x9D, 0x95, 0x06, 0xB1, 0x6B, 0x58, 0x8A, 0x5D)
+
+#define MEI_UUID_IGSC_MKHI_FIX UUID_LE(0x46E0C1FB, 0xA546, 0x414F, \
+   0x91, 0x70, 0xB7, 0xF4, 0x6D, 0x57, 0xB4, 0xAD)
+
 #define MEI_UUID_HDCP UUID_LE(0xB638AB7E, 0x94E2, 0x4EA2, \
  0xA5, 0x52, 0xD1, 0xC5, 0x4B, 0x62, 0x7F, 0x04)
 
@@ -241,6 +247,23 @@ static void mei_mkhi_fix(struct mei_cl_device *cldev)
mei_cldev_disable(cldev);
 }
 
+static void mei_gsc_mkhi_ver(struct mei_cl_device *cldev)
+{
+   int ret;
+
+   /* No need to enable the client if nothing is needed from it */
+   if (!cldev->bus->fw_f_fw_ver_supported)
+   return;
+
+   ret = mei_cldev_enable(cldev);
+   if (ret)
+   return;
+
+   ret = mei_fwver(cldev);
+   if (ret < 0)
+   dev_err(>dev, "FW version command failed %d\n", ret);
+   mei_cldev_disable(cldev);
+}
 /**
  * mei_wd - wd client on the bus, change protocol version
  *   as the API has changed.
@@ -492,6 +515,8 @@ static struct mei_fixup {
MEI_FIXUP(MEI_UUID_NFC_HCI, mei_nfc),
MEI_FIXUP(MEI_UUID_WD, mei_wd),
MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix),
+   MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver),
+   MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_ver),
MEI_FIXUP(MEI_UUID_HDCP, whitelist),
MEI_FIXUP(MEI_UUID_ANY, vt_support),
MEI_FIXUP(MEI_UUID_PAVP, whitelist),
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index 9748d14849a1..7e77328142ff 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -1577,12 +1577,14 @@ static const struct mei_cfg mei_me_pch15_sps_cfg = {
 static const struct mei_cfg mei_me_gsc_cfg = {
MEI_CFG_TYPE_GSC,
MEI_CFG_PCH8_HFS,
+   MEI_CFG_FW_VER_SUPP,
 };
 
 /* Graphics System Controller Firmware Interface */
 static const struct mei_cfg mei_me_gscfi_cfg = {
MEI_CFG_TYPE_GSCFI,
MEI_CFG_PCH8_HFS,
+   MEI_CFG_FW_VER_SUPP,
 };
 
 /*
-- 
2.32.0

[Intel-gfx] [PATCH v3 4/5] mei: gsc: add runtime pm handlers

[Alexander Usyskin]

From: Tomas Winkler 

Implement runtime handlers for mei-gsc, to track
idle state of the device properly.

CC: Rodrigo Vivi 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 
---
 drivers/misc/mei/gsc-me.c | 80 ++-
 1 file changed, 79 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index f58e54d2c1fc..fddae8009b62 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -158,7 +158,85 @@ static int __maybe_unused mei_gsc_pm_resume(struct device 
*device)
return 0;
 }
 
-static SIMPLE_DEV_PM_OPS(mei_gsc_pm_ops, mei_gsc_pm_suspend, 
mei_gsc_pm_resume);
+static int __maybe_unused mei_gsc_pm_runtime_idle(struct device *device)
+{
+   struct mei_device *dev;
+
+   dev_dbg(device, "rpm: me: runtime_idle\n");
+
+   dev = dev_get_drvdata(device);
+   if (!dev)
+   return -ENODEV;
+   if (mei_write_is_idle(dev))
+   pm_runtime_autosuspend(device);
+
+   return -EBUSY;
+}
+
+static int  __maybe_unused mei_gsc_pm_runtime_suspend(struct device *device)
+{
+   struct mei_device *dev;
+   struct mei_me_hw *hw;
+   int ret;
+
+   dev_dbg(device, "rpm: me: runtime suspend\n");
+
+   dev = dev_get_drvdata(device);
+   if (!dev)
+   return -ENODEV;
+
+   mutex_lock(>device_lock);
+
+   if (mei_write_is_idle(dev)) {
+   hw = to_me_hw(dev);
+   hw->pg_state = MEI_PG_ON;
+   ret = 0;
+   } else {
+   ret = -EAGAIN;
+   }
+
+   mutex_unlock(>device_lock);
+
+   dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
+
+   return ret;
+}
+
+static int __maybe_unused mei_gsc_pm_runtime_resume(struct device *device)
+{
+   struct mei_device *dev;
+   struct mei_me_hw *hw;
+   irqreturn_t irq_ret;
+
+   dev_dbg(device, "rpm: me: runtime resume\n");
+
+   dev = dev_get_drvdata(device);
+   if (!dev)
+   return -ENODEV;
+
+   mutex_lock(>device_lock);
+
+   hw = to_me_hw(dev);
+   hw->pg_state = MEI_PG_OFF;
+
+   mutex_unlock(>device_lock);
+
+   irq_ret = mei_me_irq_thread_handler(1, dev);
+   if (irq_ret != IRQ_HANDLED)
+   dev_err(dev->dev, "thread handler fail %d\n", irq_ret);
+
+   dev_dbg(device, "rpm: me: runtime resume ret = 0\n");
+
+   return 0;
+}
+
+static const struct dev_pm_ops mei_gsc_pm_ops = {
+   SET_SYSTEM_SLEEP_PM_OPS(mei_gsc_pm_suspend,
+   mei_gsc_pm_resume)
+   SET_RUNTIME_PM_OPS(mei_gsc_pm_runtime_suspend,
+  mei_gsc_pm_runtime_resume,
+  mei_gsc_pm_runtime_idle)
+};
 
 static const struct auxiliary_device_id mei_gsc_id_table[] = {
{
-- 
2.32.0

[Intel-gfx] [PATCH v3 3/5] mei: gsc: setup char driver alive in spite of firmware handshake failure

[Alexander Usyskin]

Setup char device in spite of firmware handshake failure.
In order to provide host access to the firmware status registers and other
information required for the manufacturing process.

Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 
---
 drivers/misc/mei/gsc-me.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index 8673ad5f0015..f58e54d2c1fc 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -79,11 +79,12 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
pm_runtime_set_active(device);
pm_runtime_enable(device);
 
-   if (mei_start(dev)) {
-   dev_err(device, "init hw failure.\n");
-   ret = -ENODEV;
-   goto err;
-   }
+   /* Continue to char device setup in spite of firmware handshake failure.
+* In order to provide access to the firmware status registers to the 
user
+* space via sysfs.
+*/
+   if (mei_start(dev))
+   dev_warn(device, "init hw failure.\n");
 
pm_runtime_set_autosuspend_delay(device, MEI_GSC_RPM_TIMEOUT);
pm_runtime_use_autosuspend(device);
-- 
2.32.0

[Intel-gfx] [PATCH v3 2/5] mei: add support for graphics system controller (gsc) devices

[Alexander Usyskin]

From: Tomas Winkler 

GSC is a graphics system controller, based on CSE, it provides
a chassis controller for graphics discrete cards, as well as it
supports media protection on selected devices.

mei_gsc binds to a auxiliary devices exposed by Intel discrete
driver i915.

Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 
---
 drivers/misc/mei/Kconfig  |  14 +++
 drivers/misc/mei/Makefile |   3 +
 drivers/misc/mei/gsc-me.c | 192 ++
 drivers/misc/mei/hw-me.c  |  27 +-
 drivers/misc/mei/hw-me.h  |   2 +
 5 files changed, 236 insertions(+), 2 deletions(-)
 create mode 100644 drivers/misc/mei/gsc-me.c

diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index 0e0bcd0da852..ec119bb98251 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -46,6 +46,20 @@ config INTEL_MEI_TXE
  Supported SoCs:
  Intel Bay Trail
 
+config INTEL_MEI_GSC
+   tristate "Intel MEI GSC embedded device"
+   select INTEL_MEI
+   select INTEL_MEI_ME
+   depends on X86 && PCI
+   depends on DRM_I915
+   help
+ Intel auxiliary driver for GSC devices embedded in Intel graphics 
devices.
+
+ An MEI device here called GSC can be embedded in an
+ Intel graphics devices, to support a range of chassis
+ tasks such as graphics card firmware update and security
+ tasks.
+
 source "drivers/misc/mei/hdcp/Kconfig"
 source "drivers/misc/mei/pxp/Kconfig"
 
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index d8e5165917f2..fb740d754900 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -18,6 +18,9 @@ obj-$(CONFIG_INTEL_MEI_ME) += mei-me.o
 mei-me-objs := pci-me.o
 mei-me-objs += hw-me.o
 
+obj-$(CONFIG_INTEL_MEI_GSC) += mei-gsc.o
+mei-gsc-objs := gsc-me.o
+
 obj-$(CONFIG_INTEL_MEI_TXE) += mei-txe.o
 mei-txe-objs := pci-txe.o
 mei-txe-objs += hw-txe.o
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
new file mode 100644
index ..8673ad5f0015
--- /dev/null
+++ b/drivers/misc/mei/gsc-me.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
+ *
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "mei_dev.h"
+#include "hw-me.h"
+#include "hw-me-regs.h"
+
+#include "mei-trace.h"
+
+#define MEI_GSC_RPM_TIMEOUT 500
+
+static int mei_gsc_read_hfs(const struct mei_device *dev, int where, u32 *val)
+{
+   struct mei_me_hw *hw = to_me_hw(dev);
+
+   *val = ioread32(hw->mem_addr + where + 0xC00);
+
+   return 0;
+}
+
+static int mei_gsc_probe(struct auxiliary_device *aux_dev,
+const struct auxiliary_device_id *aux_dev_id)
+{
+   struct mei_aux_device *adev = auxiliary_dev_to_mei_aux_dev(aux_dev);
+   struct mei_device *dev;
+   struct mei_me_hw *hw;
+   struct device *device;
+   const struct mei_cfg *cfg;
+   int ret;
+
+   cfg = mei_me_get_cfg(aux_dev_id->driver_data);
+   if (!cfg)
+   return -ENODEV;
+
+   device = _dev->dev;
+
+   dev = mei_me_dev_init(device, cfg);
+   if (IS_ERR(dev)) {
+   ret = PTR_ERR(dev);
+   goto err;
+   }
+
+   hw = to_me_hw(dev);
+   hw->mem_addr = devm_ioremap_resource(device, >bar);
+   if (IS_ERR(hw->mem_addr)) {
+   dev_err(device, "mmio not mapped\n");
+   ret = PTR_ERR(hw->mem_addr);
+   goto err;
+   }
+
+   hw->irq = adev->irq;
+   hw->read_fws = mei_gsc_read_hfs;
+
+   dev_set_drvdata(_dev->dev, dev);
+
+   ret = devm_request_threaded_irq(device, hw->irq,
+   mei_me_irq_quick_handler,
+   mei_me_irq_thread_handler,
+   IRQF_ONESHOT, KBUILD_MODNAME, dev);
+   if (ret) {
+   dev_err(device, "irq register failed %d\n", ret);
+   goto err;
+   }
+
+   pm_runtime_get_noresume(device);
+   pm_runtime_set_active(device);
+   pm_runtime_enable(device);
+
+   if (mei_start(dev)) {
+   dev_err(device, "init hw failure.\n");
+   ret = -ENODEV;
+   goto err;
+   }
+
+   pm_runtime_set_autosuspend_delay(device, MEI_GSC_RPM_TIMEOUT);
+   pm_runtime_use_autosuspend(device);
+
+   ret = mei_register(dev, device);
+   if (ret)
+   goto register_err;
+
+   pm_runtime_put_noidle(device);
+   return 0;
+
+register_err:
+   mei_stop(dev);
+
+err:
+   dev_err(device, "probe failed: %d\n", ret);
+   dev_set_drvdata(_dev->dev, NULL);
+   return ret;
+}
+
+static void mei_gsc_remove(struct auxiliary_device *aux_dev)
+{
+   struct mei_device *dev;
+
+   dev = dev_get_drvdata(_dev->dev);
+ 

[Intel-gfx] [PATCH v3 1/5] drm/i915/gsc: add gsc as a mei auxiliary device

[Alexander Usyskin]

From: Tomas Winkler 

GSC is a graphics system controller, it provides
a chassis controller for graphics discrete cards.

There are two MEI interfaces in GSC: HECI1 and HECI2.

Both interfaces are on the BAR0 at offsets 0x00258000 and 0x00259000.
GSC is a GT Engine (class 4: instance 6). HECI1 interrupt is signaled
via bit 15 and HECI2 via bit 14 in the interrupt register.

This patch exports GSC as auxiliary device for mei driver to bind to
for HECI2 interface.

CC: Rodrigo Vivi 
Signed-off-by: Tomas Winkler 
Signed-off-by: Vitaly Lubart 
Signed-off-by: Alexander Usyskin 
---
 drivers/gpu/drm/i915/Kconfig |   1 +
 drivers/gpu/drm/i915/Makefile|   3 +
 drivers/gpu/drm/i915/gt/intel_gsc.c  | 200 +++
 drivers/gpu/drm/i915/gt/intel_gsc.h  |  37 +
 drivers/gpu/drm/i915/gt/intel_gt.c   |   3 +
 drivers/gpu/drm/i915/gt/intel_gt.h   |   5 +
 drivers/gpu/drm/i915/gt/intel_gt_irq.c   |  13 ++
 drivers/gpu/drm/i915/gt/intel_gt_types.h |   2 +
 drivers/gpu/drm/i915/i915_drv.h  |   8 +
 drivers/gpu/drm/i915/i915_pci.c  |   3 +-
 drivers/gpu/drm/i915/i915_reg.h  |   3 +
 drivers/gpu/drm/i915/intel_device_info.h |   2 +
 include/linux/mei_aux.h  |  19 +++
 13 files changed, 298 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.h
 create mode 100644 include/linux/mei_aux.h

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 2ac220bfd0ed..3b0508e7a805 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -29,6 +29,7 @@ config DRM_I915
select VMAP_PFN
select DRM_TTM
select DRM_BUDDY
+   select AUXILIARY_BUS
help
  Choose this option if you have a system that has "Intel Graphics
  Media Accelerator" or "HD Graphics" integrated graphics,
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 451df10e3a36..5d5c04b5c0ac 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -194,6 +194,9 @@ i915-y += gt/uc/intel_uc.o \
  gt/uc/intel_huc_debugfs.o \
  gt/uc/intel_huc_fw.o
 
+# graphics system controller (GSC) support
+i915-y += gt/intel_gsc.o
+
 # modesetting core code
 i915-y += \
display/intel_atomic.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c 
b/drivers/gpu/drm/i915/gt/intel_gsc.c
new file mode 100644
index ..3fb1018dfe2d
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
+ */
+
+#include 
+#include 
+#include "i915_reg.h"
+#include "i915_drv.h"
+#include "gt/intel_gt.h"
+#include "intel_gsc.h"
+
+#define GSC_BAR_LENGTH  0x0FFC
+
+static void gsc_irq_mask(struct irq_data *d)
+{
+   /* generic irq handling */
+}
+
+static void gsc_irq_unmask(struct irq_data *d)
+{
+   /* generic irq handling */
+}
+
+static struct irq_chip gsc_irq_chip = {
+   .name = "gsc_irq_chip",
+   .irq_mask = gsc_irq_mask,
+   .irq_unmask = gsc_irq_unmask,
+};
+
+static int gsc_irq_init(struct drm_i915_private *dev_priv, int irq)
+{
+   irq_set_chip_and_handler_name(irq, _irq_chip,
+ handle_simple_irq, "gsc_irq_handler");
+
+   return irq_set_chip_data(irq, dev_priv);
+}
+
+struct intel_gsc_def {
+   const char *name;
+   const unsigned long bar;
+   size_t bar_size;
+};
+
+/* gscfi (graphics system controller firmware interface) resources */
+static const struct intel_gsc_def intel_gsc_def_dg1[] = {
+   {
+   },
+   {
+   .name = "mei-gscfi",
+   .bar = GSC_DG1_HECI2_BASE,
+   .bar_size = GSC_BAR_LENGTH,
+   }
+};
+
+static void intel_gsc_release_dev(struct device *dev)
+{
+   struct auxiliary_device *aux_dev = to_auxiliary_dev(dev);
+   struct mei_aux_device *adev = auxiliary_dev_to_mei_aux_dev(aux_dev);
+
+   kfree(adev);
+}
+
+static void intel_gsc_destroy_one(struct intel_gsc_intf *intf)
+{
+
+   if (intf->adev) {
+   auxiliary_device_delete(>adev->aux_dev);
+   auxiliary_device_uninit(>adev->aux_dev);
+   intf->adev = NULL;
+   }
+   if (intf->irq >= 0)
+   irq_free_desc(intf->irq);
+   intf->irq = -1;
+}
+
+static void intel_gsc_init_one(struct drm_i915_private *dev_priv,
+  struct intel_gsc_intf *intf,
+  unsigned int intf_id)
+{
+   struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+   struct mei_aux_device *adev;
+   struct auxiliary_device *aux_dev;
+   const struct intel_gsc_def *def;
+   int ret;
+
+   intf->irq = -1;
+   intf->id = intf_id;
+
+   if (intf_id == 0 && !HAS_HECI_PXP(dev_priv))
+   return;
+
+   def 

[Intel-gfx] [PATCH v3 0/5] Add driver for GSC controller

[Alexander Usyskin]

GSC is a graphics system controller, it provides
a chassis controller for graphics discrete cards.

There are two MEI interfaces in GSC: HECI1 and HECI2.

This series includes instantiation of the auxiliary devices for HECI2
and mei-gsc auxiliary device driver that binds to the auxiliary device.

In v2 the platform device was replaced by the auxiliary device.
v3 is the rebase over drm-tip to make public CI running.

Greg KH, please review and ACK the MEI patches after main merge window closure.
We are pushing all through gfx tree as the auxiliary device belongs there.

Alexander Usyskin (2):
  mei: gsc: setup char driver alive in spite of firmware handshake
failure
  mei: gsc: retrieve the firmware version

Tomas Winkler (3):
  drm/i915/gsc: add gsc as a mei auxiliary device
  mei: add support for graphics system controller (gsc) devices
  mei: gsc: add runtime pm handlers

 drivers/gpu/drm/i915/Kconfig |   1 +
 drivers/gpu/drm/i915/Makefile|   3 +
 drivers/gpu/drm/i915/gt/intel_gsc.c  | 200 +
 drivers/gpu/drm/i915/gt/intel_gsc.h  |  37 
 drivers/gpu/drm/i915/gt/intel_gt.c   |   3 +
 drivers/gpu/drm/i915/gt/intel_gt.h   |   5 +
 drivers/gpu/drm/i915/gt/intel_gt_irq.c   |  13 ++
 drivers/gpu/drm/i915/gt/intel_gt_types.h |   2 +
 drivers/gpu/drm/i915/i915_drv.h  |   8 +
 drivers/gpu/drm/i915/i915_pci.c  |   3 +-
 drivers/gpu/drm/i915/i915_reg.h  |   3 +
 drivers/gpu/drm/i915/intel_device_info.h |   2 +
 drivers/misc/mei/Kconfig |  14 ++
 drivers/misc/mei/Makefile|   3 +
 drivers/misc/mei/bus-fixup.c |  25 +++
 drivers/misc/mei/gsc-me.c| 271 +++
 drivers/misc/mei/hw-me.c |  29 ++-
 drivers/misc/mei/hw-me.h |   2 +
 include/linux/mei_aux.h  |  19 ++
 19 files changed, 640 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.h
 create mode 100644 drivers/misc/mei/gsc-me.c
 create mode 100644 include/linux/mei_aux.h

-- 
2.32.0

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: split out i915_reg_read_ioctl() to i915_ioctl.[ch] (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: split out i915_reg_read_ioctl() to i915_ioctl.[ch] (rev2)
URL   : https://patchwork.freedesktop.org/series/99096/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_2 -> Patchwork_22040


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/index.html

Participating hosts (46 -> 42)
--

  Missing(4): fi-kbl-soraka fi-bsw-cyan fi-bdw-samus fi-pnv-d510 

Known issues


  Here are the changes found in Patchwork_22040 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][1] -> [INCOMPLETE][2] ([i915#4785])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_psr@primary_page_flip:
- fi-skl-6600u:   [PASS][3] -> [FAIL][4] ([i915#4547])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/fi-skl-6600u/igt@kms_psr@primary_page_flip.html

  * igt@runner@aborted:
- fi-skl-6600u:   NOTRUN -> [FAIL][5] ([i915#4312])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/fi-skl-6600u/igt@run...@aborted.html
- fi-hsw-4770:NOTRUN -> [FAIL][6] ([fdo#109271] / [i915#1436] / 
[i915#4312])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/fi-hsw-4770/igt@run...@aborted.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- fi-bwr-2160:[FAIL][7] ([i915#3194]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/fi-bwr-2160/igt@core_hotunp...@unbind-rebind.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/fi-bwr-2160/igt@core_hotunp...@unbind-rebind.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-5:  [DMESG-FAIL][9] ([i915#4494]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_2/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785


Build changes
-

  * Linux: CI_DRM_2 -> Patchwork_22040

  CI-20190529: 20190529
  CI_DRM_2: 55b83480a1824372d372852b3b6ceb5f0827caf1 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6329: 38f656fdd61119105ecfa2c4dac157cd7dcad204 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22040: eb1cf9369ca6883c6b533d30932a44bb151992e7 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

eb1cf9369ca6 drm/i915: split out i915_reg_read_ioctl() to i915_ioctl.[ch]

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22040/index.html

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [RESEND,1/7] drm/i915/mst: fix intel_dp_mst_hpd_irq() indentation (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [RESEND,1/7] drm/i915/mst: fix 
intel_dp_mst_hpd_irq() indentation (rev2)
URL   : https://patchwork.freedesktop.org/series/98788/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_1_full -> Patchwork_22037_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22037_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22037_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22037_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_suspend@sysfs-reader:
- shard-iclb: [PASS][1] -> [SKIP][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1/shard-iclb8/igt@i915_susp...@sysfs-reader.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22037/shard-iclb5/igt@i915_susp...@sysfs-reader.html

  
Known issues


  Here are the changes found in Patchwork_22037_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-tglb: NOTRUN -> [DMESG-WARN][3] ([i915#3002] / [i915#4856])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22037/shard-tglb1/igt@gem_cre...@create-massive.html
- shard-skl:  NOTRUN -> [DMESG-WARN][4] ([i915#3002])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22037/shard-skl6/igt@gem_cre...@create-massive.html

  * igt@gem_ctx_persistence@engines-hang:
- shard-snb:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22037/shard-snb4/igt@gem_ctx_persiste...@engines-hang.html

  * igt@gem_eio@kms:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#232])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1/shard-tglb6/igt@gem_...@kms.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22037/shard-tglb3/igt@gem_...@kms.html

  * igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) +1 similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1/shard-iclb1/igt@gem_exec_balan...@parallel.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22037/shard-iclb3/igt@gem_exec_balan...@parallel.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][10] ([i915#2846])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22037/shard-apl3/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl:  [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1/shard-kbl7/igt@gem_exec_fair@basic-p...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22037/shard-kbl1/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22037/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][14] ([fdo#112283])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22037/shard-iclb8/igt@gem_exec_par...@secure-non-root.html

  * igt@gem_exec_suspend@basic-s3@smem:
- shard-apl:  [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +2 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1/shard-apl6/igt@gem_exec_suspend@basic...@smem.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22037/shard-apl4/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-kbl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22037/shard-kbl1/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
- shard-skl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22037/shard-skl3/igt@gem_lmem_swapp...@heavy-verify-multi.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- shard-apl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22037/shard-apl2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_userptr_blits@vma-merge:
- shard-skl:  NOTRUN -> [FAIL][20] ([i915#3318])
   [20]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: split out i915_reg_read_ioctl() to i915_ioctl.[ch] (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: split out i915_reg_read_ioctl() to i915_ioctl.[ch] (rev2)
URL   : https://patchwork.freedesktop.org/series/99096/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: split out i915_reg_read_ioctl() to i915_ioctl.[ch] (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: split out i915_reg_read_ioctl() to i915_ioctl.[ch] (rev2)
URL   : https://patchwork.freedesktop.org/series/99096/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
eb1cf9369ca6 drm/i915: split out i915_reg_read_ioctl() to i915_ioctl.[ch]
-:57: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#57: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 210 lines checked

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915: enforce min GTT alignment for discrete cards

[Robert Beckett]

On 20/01/2022 11:46, Ramalingam C wrote:

On 2022-01-18 at 17:50:34 +, Robert Beckett wrote:

From: Matthew Auld 

For local-memory objects we need to align the GTT addresses
to 64K, both for the ppgtt and ggtt.

We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into account.

For DG2 we further align and pad lmem object GTT addresses
to 2MB to ensure PDEs contain consistent page sizes as
required by the HW.

Signed-off-by: Matthew Auld 
Signed-off-by: Ramalingam C 
Signed-off-by: Robert Beckett 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
---
  .../i915/gem/selftests/i915_gem_client_blt.c  | 23 +++--
  drivers/gpu/drm/i915/gt/intel_gtt.c   | 14 +++
  drivers/gpu/drm/i915/gt/intel_gtt.h   |  9 ++
  drivers/gpu/drm/i915/i915_vma.c   | 14 +++
  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 96 ---
  5 files changed, 115 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index c08f766e6e15..7fee95a65414 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -39,6 +39,7 @@ struct tiled_blits {
struct blit_buffer scratch;
struct i915_vma *batch;
u64 hole;
+   u64 align;
u32 width;
u32 height;
  };
@@ -410,14 +411,21 @@ tiled_blits_create(struct intel_engine_cs *engine, struct 
rnd_state *prng)
goto err_free;
}
  
-	hole_size = 2 * PAGE_ALIGN(WIDTH * HEIGHT * 4);

+   t->align = I915_GTT_PAGE_SIZE_2M; /* XXX worst case, derive from vm! */
+   t->align = max(t->align,
+  i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_LOCAL));
+   t->align = max(t->align,
+  i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_SYSTEM));
+
+   hole_size = 2 * round_up(WIDTH * HEIGHT * 4, t->align);
hole_size *= 2; /* room to maneuver */
-   hole_size += 2 * I915_GTT_MIN_ALIGNMENT;
+   hole_size += 2 * t->align; /* padding on either side */
  
  	mutex_lock(>ce->vm->mutex);

memset(, 0, sizeof(hole));
err = drm_mm_insert_node_in_range(>ce->vm->mm, ,
- hole_size, 0, I915_COLOR_UNEVICTABLE,
+ hole_size, t->align,
+ I915_COLOR_UNEVICTABLE,
  0, U64_MAX,
  DRM_MM_INSERT_BEST);
if (!err)
@@ -428,7 +436,7 @@ tiled_blits_create(struct intel_engine_cs *engine, struct 
rnd_state *prng)
goto err_put;
}
  
-	t->hole = hole.start + I915_GTT_MIN_ALIGNMENT;

+   t->hole = hole.start + t->align;
pr_info("Using hole at %llx\n", t->hole);
  
  	err = tiled_blits_create_buffers(t, WIDTH, HEIGHT, prng);

@@ -455,7 +463,7 @@ static void tiled_blits_destroy(struct tiled_blits *t)
  static int tiled_blits_prepare(struct tiled_blits *t,
   struct rnd_state *prng)
  {
-   u64 offset = PAGE_ALIGN(t->width * t->height * 4);
+   u64 offset = round_up(t->width * t->height * 4, t->align);
u32 *map;
int err;
int i;
@@ -486,8 +494,7 @@ static int tiled_blits_prepare(struct tiled_blits *t,
  
  static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng)

  {
-   u64 offset =
-   round_up(t->width * t->height * 4, 2 * I915_GTT_MIN_ALIGNMENT);
+   u64 offset = round_up(t->width * t->height * 4, 2 * t->align);
int err;
  
  	/* We want to check position invariant tiling across GTT eviction */

@@ -500,7 +507,7 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct 
rnd_state *prng)
  
  	/* Reposition so that we overlap the old addresses, and slightly off */

err = tiled_blit(t,
->buffers[2], t->hole + I915_GTT_MIN_ALIGNMENT,
+>buffers[2], t->hole + t->align,
 >buffers[1], t->hole + 3 * offset / 2);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c 
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 46be4197b93f..7c92b25c0f26 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -223,6 +223,20 @@ void i915_address_space_init(struct i915_address_space 
*vm, int subclass)
  
  	GEM_BUG_ON(!vm->total);

drm_mm_init(>mm, 0, vm->total);
+
+   memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT,
+ARRAY_SIZE(vm->min_alignment));
+
+   if (HAS_64K_PAGES(vm->i915)) {
+   if (IS_DG2(vm->i915)) {

I think we need this 2M alignment for all platform with HAS_64K_PAGES.
Not only for DG2.


really? can we get confirmation of this?
this 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: split out i915_reg_read_ioctl() to i915_ioctl.[ch]

[Patchwork]

== Series Details ==

Series: drm/i915: split out i915_reg_read_ioctl() to i915_ioctl.[ch]
URL   : https://patchwork.freedesktop.org/series/99096/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_1 -> Patchwork_22039


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22039 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22039, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22039/index.html

Participating hosts (48 -> 43)
--

  Additional (2): fi-kbl-soraka bat-adlp-4 
  Missing(7): shard-tglu fi-bsw-cyan fi-icl-u2 fi-pnv-d510 shard-rkl 
shard-dg1 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22039:

### IGT changes ###

 Possible regressions 

  * igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
- bat-adlp-4: NOTRUN -> [DMESG-WARN][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22039/bat-adlp-4/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html

  
Known issues


  Here are the changes found in Patchwork_22039 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271]) +8 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22039/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u:   [PASS][3] -> [INCOMPLETE][4] ([i915#4547])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22039/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
- fi-tgl-1115g4:  [PASS][5] -> [FAIL][6] ([i915#1888])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22039/fi-tgl-1115g4/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22039/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- bat-adlp-4: NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22039/bat-adlp-4/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22039/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
- bat-adlp-4: NOTRUN -> [SKIP][10] ([i915#3282])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22039/bat-adlp-4/igt@gem_tiled_pread_basic.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][11] ([i915#1886] / [i915#2291])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22039/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-6:  [PASS][12] -> [DMESG-FAIL][13] ([i915#4494])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22039/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-ivb-3770:[PASS][14] -> [INCOMPLETE][15] ([i915#3303])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1/fi-ivb-3770/igt@i915_selftest@l...@hangcheck.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22039/fi-ivb-3770/igt@i915_selftest@l...@hangcheck.html
- bat-dg1-5:  [PASS][16] -> [DMESG-FAIL][17] ([i915#4494])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22039/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@dp-edid-read:
- fi-kbl-soraka:  NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22039/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#533])
   [19]: 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/mst: DP MST ESI handling improvements (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/mst: DP MST ESI handling improvements (rev2)
URL   : https://patchwork.freedesktop.org/series/98479/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_1_full -> Patchwork_22036_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22036_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22036_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22036_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-iclb: [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1/shard-iclb3/igt@kms_cursor_leg...@cursor-vs-flip-atomic-transitions-varying-size.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22036/shard-iclb7/igt@kms_cursor_leg...@cursor-vs-flip-atomic-transitions-varying-size.html

  
Known issues


  Here are the changes found in Patchwork_22036_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-tglb: NOTRUN -> [DMESG-WARN][3] ([i915#3002] / [i915#4856])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22036/shard-tglb1/igt@gem_cre...@create-massive.html
- shard-skl:  NOTRUN -> [DMESG-WARN][4] ([i915#3002])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22036/shard-skl9/igt@gem_cre...@create-massive.html

  * igt@gem_eio@kms:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#232])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1/shard-tglb6/igt@gem_...@kms.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22036/shard-tglb5/igt@gem_...@kms.html

  * igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#4525]) +1 similar issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1/shard-iclb1/igt@gem_exec_balan...@parallel.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22036/shard-iclb7/igt@gem_exec_balan...@parallel.html

  * igt@gem_exec_capture@pi@vcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][9] ([i915#4547])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22036/shard-skl9/igt@gem_exec_capture@p...@vcs0.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar 
issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22036/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][12] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22036/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_params@no-vebox:
- shard-skl:  NOTRUN -> [SKIP][13] ([fdo#109271]) +175 similar 
issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22036/shard-skl6/igt@gem_exec_par...@no-vebox.html

  * igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][14] ([fdo#112283])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22036/shard-iclb5/igt@gem_exec_par...@secure-non-root.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-kbl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22036/shard-kbl3/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- shard-apl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22036/shard-apl7/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@verify:
- shard-skl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22036/shard-skl6/igt@gem_lmem_swapp...@verify.html

  * igt@gem_userptr_blits@vma-merge:
- shard-skl:  NOTRUN -> [FAIL][18] ([i915#3318])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22036/shard-skl6/igt@gem_userptr_bl...@vma-merge.html

  * igt@gen9_exec_parse@allowed-single:
- shard-skl:  [PASS][19] -> [DMESG-WARN][20] ([i915#1436] / 
[i915#716])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1/shard-skl2/igt@gen9_exec_pa...@allowed-single.html
   [20]: 

Re: [Intel-gfx] [PATCH v3 0/2] Add support for querying hw info that UMDs need

[Cencelewska, Katarzyna]

++

-Original Message-
From: Harrison, John C  
Sent: Wednesday, January 19, 2022 9:36 PM
To: Intel-GFX@Lists.FreeDesktop.Org
Cc: dri-de...@lists.freedesktop.org; Harrison, John C 
; Cencelewska, Katarzyna 
; Ye, Tony ; Jason Ekstrand 
; Brost, Matthew 
Subject: [PATCH v3 0/2] Add support for querying hw info that UMDs need

From: John Harrison 

Various UMDs require hardware configuration information about the current 
platform. A bunch of static information is available in a fixed table that can 
be retrieved from the GuC.

v2: Rebased to newer baseline and added a kerneldoc comment.
v3: Rebased to newer baseline and newer GuC interface.

Test-with: 20220119200137.2364940-2-john.c.harri...@intel.com
UMD: https://github.com/intel/compute-runtime/pull/432/files
UMD: https://github.com/intel/media-driver/pull/1239/files

CC: Katarzyna Cencelewska 
CC: Tony Ye 
CC: Jason Ekstrand 
Signed-off-by: John Harrison 
Reviewed-by: Matthew Brost 


John Harrison (1):
  drm/i915/guc: Add fetch of hwconfig table

Rodrigo Vivi (1):
  drm/i915/uapi: Add query for hwconfig table

 drivers/gpu/drm/i915/Makefile |   1 +
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |   1 +
 .../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h   |   4 +
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|   3 +
 .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.c   | 151 ++
 .../gpu/drm/i915/gt/uc/intel_guc_hwconfig.h   |  19 +++
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |   6 +
 drivers/gpu/drm/i915/i915_query.c |  23 +++
 include/uapi/drm/i915_drm.h   |   1 +
 9 files changed, 209 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.h

--
2.25.1

-
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
Kapital zakladowy 200.000 PLN.
Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i 
moze zawierac informacje poufne. W razie przypadkowego otrzymania tej 
wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; 
jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole 
use of the intended recipient(s). If you are not the intended recipient, please 
contact the sender and delete all copies; any review or distribution by others 
is strictly prohibited.

Re: [Intel-gfx] [PATCH] drm/locking: fix drm_modeset_acquire_ctx kernel-doc

[Jani Nikula]

On Thu, 20 Jan 2022, Daniel Vetter  wrote:
> On Thu, Jan 20, 2022 at 10:49 AM Jani Nikula  wrote:
>>
>> The stack_depot member was added without kernel-doc, leading to below
>> warning. Fix it.
>>
>> ./include/drm/drm_modeset_lock.h:74: warning: Function parameter or
>> member 'stack_depot' not described in 'drm_modeset_acquire_ctx'
>>
>> Reported-by: Stephen Rothwell 
>> Fixes: cd06ab2fd48f ("drm/locking: add backtrace for locking contended locks 
>> without backoff")
>> Signed-off-by: Jani Nikula 
>> ---
>>  include/drm/drm_modeset_lock.h | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/include/drm/drm_modeset_lock.h b/include/drm/drm_modeset_lock.h
>> index b84693fbd2b5..ec4f543c3d95 100644
>> --- a/include/drm/drm_modeset_lock.h
>> +++ b/include/drm/drm_modeset_lock.h
>> @@ -34,6 +34,7 @@ struct drm_modeset_lock;
>>   * struct drm_modeset_acquire_ctx - locking context (see ww_acquire_ctx)
>>   * @ww_ctx: base acquire ctx
>>   * @contended: used internally for -EDEADLK handling
>> + * @stack_depot: used internally for contention debugging
>
> Uh would be nice to switch to the inline style, since we already have
> inline comments (just not kerneldoc). Either way:
>
> Reviewed-by: Daniel Vetter 

Thanks for the review and testing, pushed to drm-misc-next.

BR,
Jani.

>
>
>>   * @locked: list of held locks
>>   * @trylock_only: trylock mode used in atomic contexts/panic notifiers
>>   * @interruptible: whether interruptible locking should be used.
>> --
>> 2.30.2
>>

-- 
Jani Nikula, Intel Open Source Graphics Center