Re: [Intel-gfx] [RFC PATCH v2 3/3] drm/i915: Enabling WD Transcoder
Hi All,
Gentle Reminder
Regards,
Suraj Kandpal
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 89 +-
> drivers/gpu/drm/i915/display/intel_display.h | 9 +
> .../drm/i915/display/intel_display_types.h| 13 +
> drivers/gpu/drm/i915/display/intel_dpll.c | 3 +
> drivers/gpu/drm/i915/display/intel_opregion.c | 3 +
> drivers/gpu/drm/i915/display/intel_wd.c | 978 ++
> drivers/gpu/drm/i915/display/intel_wd.h | 82 ++
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/i915_irq.c | 8 +-
> drivers/gpu/drm/i915/i915_pci.c | 7 +-
> drivers/gpu/drm/i915/i915_reg.h | 137 +++
> 13 files changed, 1330 insertions(+), 3 deletions(-) create mode 100644
> drivers/gpu/drm/i915/display/intel_wd.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_wd.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 087bd9d1b397..5ee32513a945 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -287,6 +287,7 @@ i915-y += \
> display/intel_vdsc.o \
> display/intel_vrr.o \
> display/intel_wb_connector.o\
> + display/intel_wd.o\
> display/vlv_dsi.o \
> display/vlv_dsi_pll.o
>
> diff --git a/drivers/gpu/drm/i915/display/intel_acpi.c
> b/drivers/gpu/drm/i915/display/intel_acpi.c
> index e78430001f07..ae08db164f73 100644
> --- a/drivers/gpu/drm/i915/display/intel_acpi.c
> +++ b/drivers/gpu/drm/i915/display/intel_acpi.c
> @@ -247,6 +247,7 @@ static u32 acpi_display_type(struct intel_connector
> *connector)
> case DRM_MODE_CONNECTOR_LVDS:
> case DRM_MODE_CONNECTOR_eDP:
> case DRM_MODE_CONNECTOR_DSI:
> + case DRM_MODE_CONNECTOR_WRITEBACK:
> display_type = ACPI_DISPLAY_TYPE_INTERNAL_DIGITAL;
> break;
> case DRM_MODE_CONNECTOR_Unknown:
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index eb49973621f0..6dedc7921f54 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -111,6 +111,7 @@
> #include "intel_sprite.h"
> #include "intel_tc.h"
> #include "intel_vga.h"
> +#include "intel_wd.h"
> #include "i9xx_plane.h"
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
> @@ -1544,6 +1545,72 @@ static void
> intel_encoders_update_complete(struct intel_atomic_state *state)
> }
> }
>
> +static void intel_queue_writeback_job(struct intel_atomic_state *state,
> + struct intel_crtc *intel_crtc, struct intel_crtc_state
> *crtc_state) {
> + struct drm_connector_state *new_conn_state;
> + struct drm_connector *connector;
> + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev);
> + struct intel_wd *intel_wd;
> + struct intel_connector *intel_connector;
> + struct intel_digital_connector_state *intel_conn_state;
> + struct intel_encoder *encoder;
> + int i;
> +
> + for_each_intel_encoder_with_wd(>drm, encoder) {
> + intel_wd = enc_to_intel_wd(encoder);
> +
> + if (intel_wd->wd_crtc != intel_crtc)
> + return;
> +
> + }
> +
> + for_each_new_connector_in_state(>base, connector,
> new_conn_state,
> + i) {
> + intel_conn_state =
> to_intel_digital_connector_state(new_conn_state);
> + if (!intel_conn_state->job)
> + continue;
> + intel_connector = to_intel_connector(connector);
> + intel_writeback_queue_job(_connector->wb_conn,
> new_conn_state);
> + drm_dbg_kms(>drm, "queueing writeback job\n");
> + }
> +}
> +
> +static void intel_find_writeback_connector(struct intel_atomic_state
> *state,
> + struct intel_crtc *intel_crtc, struct intel_crtc_state
> *crtc_state) {
> + struct drm_connector_state *new_conn_state;
> + struct drm_connector *connector;
> + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev);
> + struct intel_wd *intel_wd;
> + struct intel_encoder *encoder;
> + int i;
> +
> + for_each_intel_encoder_with_wd(>drm, encoder) {
> + intel_wd = enc_to_intel_wd(encoder);
> +
> + if (intel_wd->wd_crtc != intel_crtc)
> + return;
> +
> + }
> +
> + for_each_new_connector_in_state(>base, connector,
> new_conn_state,
> + i) {
> + struct intel_connector *intel_connector;
> +
> + intel_connector = to_intel_connector(connector);
> + drm_dbg_kms(>drm, "[CONNECTOR:%d:%s]: status:
> %s\n",
> + connector->base.id, connector->name,
> +
> drm_get_connector_status_name(connector->status));
> +
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg1: remove redundant uc_index assignment
== Series Details == Series: drm/i915/dg1: remove redundant uc_index assignment URL : https://patchwork.freedesktop.org/series/101765/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11403_full -> Patchwork_22676_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22676_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22676_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (12 -> 11) -- Missing(1): shard-rkl Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22676_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gem_contexts: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/shard-skl6/igt@i915_selftest@live@gem_contexts.html Known issues Here are the changes found in Patchwork_22676_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-glk: ([PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [FAIL][23], [PASS][24], [PASS][25], [PASS][26]) ([i915#4392]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk9/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk9/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk9/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk8/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk8/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk8/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk7/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk7/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk6/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk6/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk6/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk5/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk5/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk5/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk4/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk4/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk4/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk3/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk3/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk2/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk2/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk1/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk1/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/shard-glk9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/shard-glk9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/shard-glk9/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/shard-glk8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/shard-glk8/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/shard-glk8/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/shard-glk7/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/shard-glk7/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/shard-glk7/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/shard-glk6/boot.html [37]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg1: remove redundant uc_index assignment
== Series Details ==
Series: drm/i915/dg1: remove redundant uc_index assignment
URL : https://patchwork.freedesktop.org/series/101765/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22676
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/index.html
Participating hosts (44 -> 41)
--
Additional (1): bat-adlm-1
Missing(4): fi-bsw-cyan shard-rkl shard-tglu fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22676:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_timelines:
- {bat-rpls-2}: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/bat-rpls-2/igt@i915_selftest@live@gt_timelines.html
Known issues
Here are the changes found in Patchwork_22676 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_module_load@reload:
- {bat-rpls-2}: [DMESG-WARN][2] ([i915#4391]) -> [PASS][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/bat-rpls-2/igt@i915_module_l...@reload.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/bat-rpls-2/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}: [INCOMPLETE][4] -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/bat-rpls-2/igt@i915_pm_...@module-reload.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/bat-rpls-2/igt@i915_pm_...@module-reload.html
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: [DMESG-WARN][6] ([i915#3576]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/bat-adlp-6/igt@kms_busy@ba...@flip.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/bat-adlp-6/igt@kms_busy@ba...@flip.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-cfl-8109u: [DMESG-WARN][8] ([i915#295] / [i915#5341]) ->
[PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][10] ([i915#295]) -> [PASS][11] +10
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5339]: https://gitlab.freedesktop.org/drm/intel/issues/5339
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
[i915#5342]: https://gitlab.freedesktop.org/drm/intel/issues/5342
Build changes
-
* Linux: CI_DRM_11403 -> Patchwork_22676
CI-20190529: 20190529
CI_DRM_11403: 76ccfdacc3c78b22c90127356a2d19241f452208 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6392: 5a78ea9ff9c0a77bec5b094bf7e9d82c9848702b @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22676: 8a42786f165a39acc64fdac322643436101ec5d6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8a42786f165a drm/i915/dg1: remove redundant uc_index assignment
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22676/index.html
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dg1: remove redundant uc_index assignment
== Series Details == Series: drm/i915/dg1: remove redundant uc_index assignment URL : https://patchwork.freedesktop.org/series/101765/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/hwconfig: Add DG2 support
== Series Details == Series: drm/i915/hwconfig: Add DG2 support URL : https://patchwork.freedesktop.org/series/101760/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11403_full -> Patchwork_22674_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22674_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22674_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (12 -> 11) -- Missing(1): shard-rkl Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22674_full: ### IGT changes ### Possible regressions * igt@i915_selftest@live@client: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/shard-skl4/igt@i915_selftest@l...@client.html Known issues Here are the changes found in Patchwork_22674_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-glk: ([PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [FAIL][23], [PASS][24], [PASS][25], [PASS][26]) ([i915#4392]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk9/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk9/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk9/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk8/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk8/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk8/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk7/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk7/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk6/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk6/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk6/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk5/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk5/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk5/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk4/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk4/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk4/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk3/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk3/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk2/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk2/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk1/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/shard-glk1/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/shard-glk9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/shard-glk9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/shard-glk7/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/shard-glk7/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/shard-glk7/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/shard-glk8/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/shard-glk8/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/shard-glk9/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/shard-glk1/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/shard-glk1/boot.html [37]:
[Intel-gfx] [PATCH] drm/i915/dg1: remove redundant uc_index assignment
Just clean up the redundant uc_index assignment for DG1.
Signed-off-by: Chuansheng Liu
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index c4c37585ae8c..0c300727a5c2 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -445,7 +445,6 @@ static unsigned int get_mocs_settings(const struct
drm_i915_private *i915,
table->table = dg1_mocs_table;
table->uc_index = 1;
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
- table->uc_index = 1;
table->unused_entries_index = 5;
} else if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) {
/* For TGL/RKL, Can't be changed now for ABI reasons */
--
2.25.0.rc2
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: fix one mem leak in mmap_offset_attach() (rev4)
== Series Details ==
Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev4)
URL : https://patchwork.freedesktop.org/series/100532/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22675
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22675 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22675, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22675/index.html
Participating hosts (43 -> 40)
--
Missing(3): fi-bsw-cyan shard-tglu fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22675:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22675/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_timelines:
- {bat-rpls-2}: NOTRUN -> [INCOMPLETE][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22675/bat-rpls-2/igt@i915_selftest@live@gt_timelines.html
Known issues
Here are the changes found in Patchwork_22675 that come from known issues:
### IGT changes ###
Issues hit
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][4] ([fdo#109271] / [i915#1436] /
[i915#2722] / [i915#4312])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22675/fi-hsw-4770/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- {fi-rkl-11600}: [INCOMPLETE][5] ([i915#5127]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22675/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_module_load@reload:
- {bat-rpls-2}: [DMESG-WARN][7] ([i915#4391]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/bat-rpls-2/igt@i915_module_l...@reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22675/bat-rpls-2/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}: [INCOMPLETE][9] -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/bat-rpls-2/igt@i915_pm_...@module-reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22675/bat-rpls-2/igt@i915_pm_...@module-reload.html
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: [DMESG-WARN][11] ([i915#3576]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/bat-adlp-6/igt@kms_busy@ba...@flip.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22675/bat-adlp-6/igt@kms_busy@ba...@flip.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][13] ([i915#295]) -> [PASS][14] +10
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22675/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-cfl-8109u: [DMESG-WARN][15] ([i915#295] / [i915#5341]) ->
[PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22675/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#295]:
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: fix one mem leak in mmap_offset_attach() (rev4)
== Series Details == Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev4) URL : https://patchwork.freedesktop.org/series/100532/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/hwconfig: Add DG2 support
== Series Details ==
Series: drm/i915/hwconfig: Add DG2 support
URL : https://patchwork.freedesktop.org/series/101760/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22674
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/index.html
Participating hosts (43 -> 41)
--
Additional (1): fi-pnv-d510
Missing(3): fi-bsw-cyan shard-tglu fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22674:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@basic-pci-d3-state:
- {bat-jsl-2}:[PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/bat-jsl-2/igt@i915_pm_...@basic-pci-d3-state.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/bat-jsl-2/igt@i915_pm_...@basic-pci-d3-state.html
Known issues
Here are the changes found in Patchwork_22674 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-pnv-d510:NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#5341])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/fi-pnv-d510/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/fi-snb-2600/igt@kms_setm...@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][5] ([fdo#109271]) +57 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/fi-pnv-d510/igt@prime_v...@basic-userptr.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- {fi-rkl-11600}: [INCOMPLETE][6] ([i915#5127]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][8] ([i915#295]) -> [PASS][9] +10 similar
issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-cfl-8109u: [DMESG-WARN][10] ([i915#295] / [i915#5341]) ->
[PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11403/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22674/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#5195]: https://gitlab.freedesktop.org/drm/intel/issues/5195
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5341]:
[Intel-gfx] [PATCH v2] drm/i915: fix one mem leak in mmap_offset_attach()
The below memory leak information is caught:
unreferenced object 0x997dd4e3b240 (size 64):
comm "gem_tiled_fence", pid 10332, jiffies 4294959326 (age
220778.420s)
hex dump (first 32 bytes):
01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 be f2 d4 7d 99 ff ff }...
backtrace:
[] kmem_cache_alloc_trace+0x2e5/0x450
[] drm_vma_node_allow+0x2c/0xe0 [drm]
[] __assign_mmap_offset_handle+0x1da/0x4a0 [i915]
[] i915_gem_mmap_offset_ioctl+0x55/0xb0 [i915]
[] drm_ioctl_kernel+0xb4/0x140 [drm]
[] drm_ioctl+0x257/0x410 [drm]
[] __x64_sys_ioctl+0x8e/0xc0
[] do_syscall_64+0x38/0xc0
[] entry_SYSCALL_64_after_hwframe+0x44/0xae
The issue is always reproduced with the test:
gem_tiled_fence_blits --run-subtest basic
It tries to mmap_gtt the same object several times, it is like:
create BO
mmap_gtt BO
unmap BO
mmap_gtt BO <== second time mmap_gtt
unmap
close BO
The leak happens at the second time mmap_gtt in function
mmap_offset_attach(),it will simply increase the reference
count to 2 by calling drm_vma_node_allow() directly since
the mmo has been created at the first time.
However the driver just revokes the vma_node only one time
when closing the object, it leads to memory leak easily.
This patch is to fix the memory leak by calling drm_vma_node_allow() one
time also.
V2: add "Fixes and Cc stable". (Tvrtko Ursulin)
Fixes: 786555987207 ("drm/i915/gem: Store mmap_offsets in an rbtree
rather than a plain list")
Cc: # v5.7+
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Signed-off-by: Chuansheng Liu
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index c3ea243d414d..fda346d687fd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -680,7 +680,7 @@ mmap_offset_attach(struct drm_i915_gem_object *obj,
mmo = insert_mmo(obj, mmo);
GEM_BUG_ON(lookup_mmo(obj, mmap_type) != mmo);
out:
- if (file)
+ if (file && !drm_vma_node_is_allowed(>vma_node, file))
drm_vma_node_allow(>vma_node, file);
return mmo;
--
2.25.0.rc2
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/hwconfig: Add DG2 support
== Series Details == Series: drm/i915/hwconfig: Add DG2 support URL : https://patchwork.freedesktop.org/series/101760/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found
[Intel-gfx] [PATCH] drm/i915/hwconfig: Add DG2 support
From: Rodrigo Vivi
DG2 support for hwconfig tables varies by both SKU and stepping.
Signed-off-by: Rodrigo Vivi
Signed-off-by: John Harrison
Signed-off-by: Ramalingam C
Tested-by: Jordan Justen
---
drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
index e0f65bdd1c84..b34833cca44a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
@@ -96,6 +96,8 @@ static bool has_table(struct drm_i915_private *i915)
{
if (IS_ALDERLAKE_P(i915))
return true;
+ if (IS_DG2_G11(i915) || IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A2,
STEP_FOREVER))
+ return true;
return false;
}
--
2.35.1
Re: [Intel-gfx] [PATCH 1/1] drm/i915: Handle the DG2 max bw properly
On Thu, 2022-03-24 at 08:39 +, Murthy, Arun R wrote:
> > }
> >
> > +static unsigned int dg2_max_bw(struct drm_i915_private *i915) {
> > + struct intel_bw_info *bi = >max_bw[0];
> > +
> > + return bi->deratedbw[0];
> > +}
>
> Would it look better to have this as a macro rather than a function?
Hey Thanks for the comment!
Ideally probably yes.. I thought the function might be better here
But in any case, actually V2 for this patch is in progress. I had abandoned
that extra function
instead use value directly.
> Thanks and Regards,
> Arun R Murthy
>
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch
== Series Details == Series: series starting with [1/2] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch URL : https://patchwork.freedesktop.org/series/101752/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11402_full -> Patchwork_22673_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22673_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22673_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22673_full: ### IGT changes ### Possible regressions * igt@gem_softpin@allocator-evict@bcs0: - shard-kbl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/shard-kbl4/igt@gem_softpin@allocator-ev...@bcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/shard-kbl6/igt@gem_softpin@allocator-ev...@bcs0.html Known issues Here are the changes found in Patchwork_22673_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@psr2: - shard-iclb: NOTRUN -> [SKIP][3] ([i915#658]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/shard-iclb6/igt@feature_discov...@psr2.html * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-kbl: [PASS][4] -> [INCOMPLETE][5] ([i915#1373] / [i915#794]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/shard-kbl1/igt@gem_ctx_isolation@preservation...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/shard-kbl4/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_eio@in-flight-contexts-immediate: - shard-tglb: [PASS][6] -> [TIMEOUT][7] ([i915#3063]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/shard-tglb3/igt@gem_...@in-flight-contexts-immediate.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/shard-tglb5/igt@gem_...@in-flight-contexts-immediate.html * igt@gem_eio@kms: - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#232]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/shard-tglb6/igt@gem_...@kms.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/shard-tglb1/igt@gem_...@kms.html * igt@gem_exec_balancer@parallel: - shard-kbl: NOTRUN -> [DMESG-WARN][10] ([i915#5076]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/shard-kbl7/igt@gem_exec_balan...@parallel.html * igt@gem_exec_balancer@parallel-bb-first: - shard-iclb: NOTRUN -> [SKIP][11] ([i915#4525]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/shard-iclb8/igt@gem_exec_balan...@parallel-bb-first.html * igt@gem_exec_capture@pi@rcs0: - shard-skl: NOTRUN -> [INCOMPLETE][12] ([i915#1888] / [i915#4547]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/shard-skl4/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_fair@basic-deadline: - shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2846]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/shard-tglb2/igt@gem_exec_f...@basic-deadline.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/shard-tglb1/igt@gem_exec_f...@basic-deadline.html - shard-skl: NOTRUN -> [FAIL][15] ([i915#2846]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/shard-skl7/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/shard-iclb4/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-tglb: NOTRUN -> [FAIL][17] ([i915#2842]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/shard-tglb1/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][18] -> [FAIL][19] ([i915#2842]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/shard-glk5/igt@gem_exec_fair@basic-n...@rcs0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/shard-glk1/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][20] -> [FAIL][21] ([i915#2842]) +2 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/shard-kbl6/igt@gem_exec_fair@basic-n...@vcs0.html [21]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for lmem_size modparam
== Series Details ==
Series: lmem_size modparam
URL : https://patchwork.freedesktop.org/series/101744/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11402_full -> Patchwork_22671_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22671_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22671_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22671_full:
### IGT changes ###
Possible regressions
* igt@gem_exec_schedule@wide@vcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-skl2/igt@gem_exec_schedule@w...@vcs0.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- {shard-tglu}: NOTRUN -> [SKIP][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-tglu-2/igt@kms_frontbuffer_track...@fbc-tiling-4.html
Known issues
Here are the changes found in Patchwork_22671_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@psr2:
- shard-iclb: NOTRUN -> [SKIP][3] ([i915#658])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-iclb7/igt@feature_discov...@psr2.html
* igt@gem_ctx_persistence@engines-mixed:
- shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +1
similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-snb5/igt@gem_ctx_persiste...@engines-mixed.html
* igt@gem_ctx_sseu@engines:
- shard-tglb: NOTRUN -> [SKIP][5] ([i915#280])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-tglb3/igt@gem_ctx_s...@engines.html
* igt@gem_eio@in-flight-suspend:
- shard-kbl: NOTRUN -> [INCOMPLETE][6] ([i915#3614])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-kbl4/igt@gem_...@in-flight-suspend.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][7] -> [TIMEOUT][8] ([i915#2481] / [i915#3070])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/shard-iclb4/igt@gem_...@unwedge-stress.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-iclb3/igt@gem_...@unwedge-stress.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1888])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-skl9/igt@gem_exec_balan...@parallel-bb-first.html
- shard-tglb: NOTRUN -> [DMESG-WARN][10] ([i915#5076])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-tglb5/igt@gem_exec_balan...@parallel-bb-first.html
- shard-kbl: NOTRUN -> [DMESG-WARN][11] ([i915#5076])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-kbl4/igt@gem_exec_balan...@parallel-bb-first.html
- shard-iclb: NOTRUN -> [DMESG-WARN][12] ([i915#5076])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-iclb1/igt@gem_exec_balan...@parallel-bb-first.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][13] ([i915#4547])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-skl7/igt@gem_exec_capture@p...@rcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [PASS][14] -> [FAIL][15] ([i915#2846])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/shard-kbl1/igt@gem_exec_f...@basic-deadline.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-kbl4/igt@gem_exec_f...@basic-deadline.html
- shard-skl: NOTRUN -> [FAIL][16] ([i915#2846])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-skl9/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][17] ([i915#2842])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-kbl4/igt@gem_exec_fair@basic-none-s...@rcs0.html
- shard-iclb: NOTRUN -> [FAIL][18] ([i915#2842]) +1 similar issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/shard-iclb3/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-tglb: NOTRUN -> [FAIL][19] ([i915#2842]) +1 similar issue
[19]:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch
== Series Details ==
Series: series starting with [1/2] drm/i915/display/psr: Set partial frame
enable when forcing full frame fetch
URL : https://patchwork.freedesktop.org/series/101752/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11402 -> Patchwork_22673
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/index.html
Participating hosts (45 -> 41)
--
Additional (1): fi-hsw-4770
Missing(5): shard-tglu fi-bsw-cyan shard-rkl bat-jsl-2 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22673:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/bat-rpls-2/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/bat-rpls-2/igt@i915_pm_...@module-reload.html
Known issues
Here are the changes found in Patchwork_22673 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#109315]) +17
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html
* igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#3012])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick:[PASS][6] -> [DMESG-FAIL][7] ([i915#2927] /
[i915#3428])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][8] -> [DMESG-FAIL][9] ([i915#4528])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1072]) +3
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html
* igt@runner@aborted:
- fi-blb-e6850: NOTRUN -> [FAIL][13] ([fdo#109271] / [i915#2403] /
[i915#4312])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/fi-blb-e6850/igt@run...@aborted.html
- fi-bsw-nick:NOTRUN -> [FAIL][14] ([fdo#109271] / [i915#1436] /
[i915#3428] / [i915#4312])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/fi-bsw-nick/igt@run...@aborted.html
Possible fixes
* igt@i915_pm_rpm@module-reload:
- {bat-adlp-6}: [DMESG-WARN][15] ([i915#3576]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/bat-adlp-6/igt@i915_pm_...@module-reload.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22673/bat-adlp-6/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2927]:
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch
== Series Details == Series: series starting with [1/2] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch URL : https://patchwork.freedesktop.org/series/101752/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found
Re: [Intel-gfx] [RFC] drm/i915: Split out intel_vtd_active and run_as_guest to own header
On Thu, 24 Mar 2022, Tvrtko Ursulin wrote: > On 24/03/2022 11:57, Jani Nikula wrote: >> On Thu, 24 Mar 2022, Tvrtko Ursulin wrote: >>> On 24/03/2022 09:31, Jani Nikula wrote: On Tue, 22 Mar 2022, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > ... > > Signed-off-by: Tvrtko Ursulin > Cc: Jani Nikula > Cc: Lucas De Marchi > --- > Typed up how I see it - bash away. So is intel_vtd_active() so performance critical that it needs to be inline? We're passing struct drm_i915_private * everywhere we can, and it just feels silly to use struct drm_device * to avoid the include. Static inlines considered harmful. :p >>> >>> Same as it is ;), and gee, who was it that he said he was just trying to >>> declutter i915_drv.h.. ;p >> >> Not at the cost of clarity elsewhere! > > To be clear now you oppose intel_vtd_active taking struct device? I > thought you expressed general agreement when I presented the idea in the > previous thread. > > I don't mind hugely to go either way, but I also don't see how taking > struct device makes anything unclear. (I only think > intel_vtd_run_as_guest is really wrong in this story but that's old news.) > > And if I make it take i915 then I would want to name it i915_vtd_active > as well. But then you wouldn't like that. > > Should we just stuff all this into i915_utils for now, as I think Lucas > suggested? Static inline or not, I don't care. Just general grumpiness. Acked-by: Jani Nikula > > Regards, > > Tvrtko -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH 2/2] drm/i915/display/psr: Use continuos full frame to handle frontbuffer invalidations
Instead of exit PSR when a frontbuffer invalidation happens, we can
enable the PSR2 selective fetch continuous full frame, that will keep
the panel updated like PSR was disabled but without keeping PSR active.
So as soon as the frontbuffer flush happens we can disable the
continuous full frame and start to do selective fetches much quicker
than the path that would enable PSR, that will wait a few frames
to actually activate PSR.
Also this approach has proven to fix some glitches found in Alderlake-P
when there are a lot of invalidations happening together with page
flips.
Some may ask why it is writing to CURSURFLIVE(), it is because
that is the way that hardware team provided us to poke display to
handle PSR updates, and it is being used since display 9.
Cc: Khaled Almahallawy
Cc: Shawn C Lee
Cc: Jouni Högander
Cc: Mika Kahola
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 109 ---
1 file changed, 95 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index d87b357806c91..f7b7b374374b1 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1450,6 +1450,22 @@ static inline u32
man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev
PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
}
+static inline u32 man_trk_ctl_continuos_full_frame(struct drm_i915_private
*dev_priv)
+{
+ return IS_ALDERLAKE_P(dev_priv) ?
+ ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME :
+ PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
+}
+
+static inline u32 man_trk_ctl_su_region_start_end_mask(struct drm_i915_private
*dev_priv)
+{
+ if (IS_ALDERLAKE_P(dev_priv))
+ return ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK |
+ ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK;
+ return PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK |
+ PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK;
+}
+
static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1546,8 +1562,9 @@ void intel_psr2_program_trans_man_trk_ctl(const struct
intel_crtc_state *crtc_st
if (!crtc_state->enable_psr2_sel_fetch)
return;
- intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder),
- crtc_state->psr2_man_track_ctl);
+ intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder),
+man_trk_ctl_su_region_start_end_mask(dev_priv),
+crtc_state->psr2_man_track_ctl);
}
static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
@@ -2127,6 +2144,26 @@ static void intel_psr_work(struct work_struct *work)
mutex_unlock(_dp->psr.lock);
}
+static void _psr_invalidate_handle(struct intel_dp *intel_dp,
+ unsigned int prev_busy_frontbuffer_bits)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ if (intel_dp->psr.psr2_sel_fetch_enabled) {
+ u32 val = man_trk_ctl_continuos_full_frame(dev_priv) |
+ man_trk_ctl_partial_frame_bit_get(dev_priv);
+
+ /* continuos full frame is already enabled */
+ if (prev_busy_frontbuffer_bits)
+ return;
+
+ intel_de_rmw(dev_priv,
PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0, val);
+ intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
+ } else {
+ intel_psr_exit(intel_dp);
+ }
+}
+
/**
* intel_psr_invalidate - Invalidade PSR
* @dev_priv: i915 device
@@ -2151,6 +2188,7 @@ void intel_psr_invalidate(struct drm_i915_private
*dev_priv,
for_each_intel_encoder_with_psr(_priv->drm, encoder) {
unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ unsigned int prev_busy_frontbuffer_bits;
mutex_lock(_dp->psr.lock);
if (!intel_dp->psr.enabled) {
@@ -2158,12 +2196,13 @@ void intel_psr_invalidate(struct drm_i915_private
*dev_priv,
continue;
}
+ prev_busy_frontbuffer_bits =
intel_dp->psr.busy_frontbuffer_bits;
pipe_frontbuffer_bits &=
INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
if (pipe_frontbuffer_bits)
- intel_psr_exit(intel_dp);
+ _psr_invalidate_handle(intel_dp,
prev_busy_frontbuffer_bits);
mutex_unlock(_dp->psr.lock);
}
@@ -2195,6 +2234,49 @@ tgl_dc3co_flush_locked(struct intel_dp *intel_dp,
unsigned int frontbuffer_bits,
[Intel-gfx] [PATCH 1/2] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch
Following up what was done in commit 804f46885317 ("drm/i915/psr: Set
"SF Partial Frame Enable" also on full update") and also setting
partial frame enable when psr_force_hw_tracking_exit() is called.
Cc: Jouni Högander
Cc: Mika Kahola
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 80002ca6a6ebe..d87b357806c91 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1457,7 +1457,8 @@ static void psr_force_hw_tracking_exit(struct intel_dp
*intel_dp)
if (intel_dp->psr.psr2_sel_fetch_enabled)
intel_de_rmw(dev_priv,
PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0,
-man_trk_ctl_single_full_frame_bit_get(dev_priv));
+man_trk_ctl_single_full_frame_bit_get(dev_priv) |
+man_trk_ctl_partial_frame_bit_get(dev_priv));
/*
* Display WA #0884: skl+
--
2.35.1
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS
== Series Details ==
Series: series starting with [1/2] drm/i915/ttm: limit where we apply
TTM_PL_FLAG_CONTIGUOUS
URL : https://patchwork.freedesktop.org/series/101749/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11402 -> Patchwork_22672
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22672 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22672, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22672/index.html
Participating hosts (44 -> 41)
--
Additional (1): fi-hsw-4770
Missing(4): fi-bsw-cyan shard-tglu fi-bdw-samus fi-pnv-d510
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22672:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22672/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
Known issues
Here are the changes found in Patchwork_22672 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271]) +9 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22672/fi-hsw-4770/igt@gem_huc_c...@huc-copy.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#3012])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22672/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22672/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#533])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22672/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1072]) +3
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22672/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#1436] /
[i915#2722] / [i915#4312])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22672/fi-hsw-4770/igt@run...@aborted.html
Possible fixes
* igt@i915_pm_rpm@module-reload:
- {bat-adlp-6}: [DMESG-WARN][8] ([i915#3576]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/bat-adlp-6/igt@i915_pm_...@module-reload.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22672/bat-adlp-6/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-
* Linux: CI_DRM_11402 -> Patchwork_22672
CI-20190529: 20190529
CI_DRM_11402: 07be21d8f94f3d18394522fe5d6c75a08036c3a6 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6392: 5a78ea9ff9c0a77bec5b094bf7e9d82c9848702b @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22672: 08e8f2b636b531310d59b2490f6e2ed5cb5f6ca6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
08e8f2b636b5 drm/i915/migrate: move the sanity check
3f4a111f6047 drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22672/index.html
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 3/4] tests/gem_lmem_swapping: limit lmem to 4G
On Thu, 24 Mar 2022 07:26:20 -0700, Matthew Auld wrote:
>
> @@ -554,6 +560,7 @@ igt_main_args("", long_options, help_str, opt_handler,
> NULL)
> igt_fixture {
> free(regions);
> close(i915);
> + igt_i915_driver_unload();
I thought we'd reload the module with default params here but when the next
test runs the module gets loaded automatically so maybe this is ok?
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/4] test/gem_lmem_swapping: fix physical engine usage
On Thu, 24 Mar 2022 07:26:19 -0700, Matthew Auld wrote:
>
> @@ -353,14 +356,17 @@ static void test_evict(int i915,
> if (flags & TEST_PARALLEL) {
> int fd = gem_reopen_driver(i915);
>
> + ctx = intel_ctx_create_all_physical(fd);
> + __gem_context_set_persistence(i915, ctx->id, false);
> +
> igt_fork(child, nproc)
> - __do_evict(fd, >region, ,
> + __do_evict(fd, ctx, >region, ,
> params.seed + child + 1);
>
> igt_waitchildren();
> close(fd);
We might introduce some memory leak tests some time so it would be good to
destroy any contexts we create with intel_ctx_destroy().
> @@ -528,17 +536,20 @@ igt_main_args("", long_options, help_str, opt_handler,
> NULL)
> for_each_physical_engine(i915, e)
> __num_engines__++;
> igt_require(__num_engines__);
> + ctx = intel_ctx_create_all_physical(i915);
> + __gem_context_set_persistence(i915, ctx->id, false);
> +
> }
>
> for (test = tests; test->name; test++) {
> igt_describe("Exercise local memory swapping to system memory");
> dynamic_lmem_subtest(region, regions, test->name)
> - test_evict(i915, region, test->flags);
> + test_evict(i915, ctx, region, test->flags);
> }
>
> igt_describe("Exercise local memory swapping during exhausting system
> memory");
> dynamic_lmem_subtest(region, regions, "smem-oom")
> - test_smem_oom(i915, region);
> + test_smem_oom(i915, ctx, region);
>
> igt_fixture {
> free(regions);
Here too.
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS
== Series Details == Series: series starting with [1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS URL : https://patchwork.freedesktop.org/series/101749/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found
Re: [Intel-gfx] [PATCH i-g-t 1/4] test/gem_lmem_swapping: account for object rounding
On Thu, 24 Mar 2022 07:26:18 -0700, Matthew Auld wrote: > > On DG2 the object size might be rounded when allocating lmem. Make sure > we account for any rounding up. Reviewed-by: Ashutosh Dixit
[Intel-gfx] [PATCH 2/2] drm/i915/migrate: move the sanity check
Move the sanity check that both src and dst are never both system
memory, which should never happen on discrete, and likely means we have
a bug. The only exception is on integrated where we trigger this path in
the selftests.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 20444d6ceb3c..950fd6da146c 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -530,6 +530,7 @@ intel_context_migrate_copy(struct intel_context *ce,
int err;
GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
+ GEM_BUG_ON(IS_DGFX(ce->engine->i915) && (!src_is_lmem && !dst_is_lmem));
*out = NULL;
GEM_BUG_ON(ce->ring->size < SZ_64K);
@@ -566,8 +567,6 @@ intel_context_migrate_copy(struct intel_context *ce,
src_offset = 0;
dst_offset = CHUNK_SZ;
if (HAS_64K_PAGES(ce->engine->i915)) {
- GEM_BUG_ON(!src_is_lmem && !dst_is_lmem);
-
src_offset = 0;
dst_offset = 0;
if (src_is_lmem)
--
2.34.1
[Intel-gfx] [PATCH 1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS
We only need this when allocating device local-memory, where this
influences the drm_buddy. Currently there is some funny behaviour where
an "in limbo" system memory object is lacking the relevant placement
flags etc. before we first allocate the ttm_tt, leading to ttm
performing a move when not needed, since the current placement is seen
as not compatible.
Suggested-by: Thomas Hellström
Fixes: 2ed38cec5606 ("drm/i915: opportunistically apply ALLOC_CONTIGIOUS")
Signed-off-by: Matthew Auld
Cc: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index e4a06fcf741a..97e648fa76bd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -133,6 +133,9 @@ i915_ttm_place_from_region(const struct intel_memory_region
*mr,
memset(place, 0, sizeof(*place));
place->mem_type = intel_region_to_ttm_type(mr);
+ if (mr->type == INTEL_MEMORY_SYSTEM)
+ return;
+
if (flags & I915_BO_ALLOC_CONTIGUOUS)
place->flags |= TTM_PL_FLAG_CONTIGUOUS;
if (offset != I915_BO_INVALID_OFFSET) {
--
2.34.1
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Extend DP HDR support to hsw+ (rev4)
== Series Details ==
Series: drm/i915/display: Extend DP HDR support to hsw+ (rev4)
URL : https://patchwork.freedesktop.org/series/101708/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11401_full -> Patchwork_22670_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22670_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22670_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22670_full:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@reset:
- shard-skl: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-skl4/igt@i915_selftest@l...@reset.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- {shard-tglu}: NOTRUN -> [SKIP][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-tglu-2/igt@kms_frontbuffer_track...@fbc-tiling-4.html
Known issues
Here are the changes found in Patchwork_22670_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@psr2:
- shard-iclb: NOTRUN -> [SKIP][3] ([i915#658])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-iclb3/igt@feature_discov...@psr2.html
* igt@gem_eio@kms:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#232])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11401/shard-tglb6/igt@gem_...@kms.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-tglb2/igt@gem_...@kms.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][6] -> [SKIP][7] ([i915#4525])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11401/shard-iclb2/igt@gem_exec_balan...@parallel-balancer.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-iclb6/igt@gem_exec_balan...@parallel-balancer.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-tglb: NOTRUN -> [DMESG-WARN][8] ([i915#5076])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-tglb2/igt@gem_exec_balan...@parallel-contexts.html
* igt@gem_exec_fair@basic-deadline:
- shard-skl: NOTRUN -> [FAIL][9] ([i915#2846])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-skl10/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-tglb: NOTRUN -> [FAIL][10] ([i915#2842])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-tglb6/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11401/shard-kbl1/igt@gem_exec_fair@basic-none-...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-kbl6/igt@gem_exec_fair@basic-none-...@rcs0.html
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842]) +2 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-iclb3/igt@gem_exec_fair@basic-none-...@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11401/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_lmem_swapping@basic:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#4613])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-iclb3/igt@gem_lmem_swapp...@basic.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-kbl3/igt@gem_lmem_swapp...@parallel-multi.html
* igt@gem_lmem_swapping@random:
- shard-tglb: NOTRUN -> [SKIP][18] ([i915#4613])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-tglb6/igt@gem_lmem_swapp...@random.html
* igt@gem_lmem_swapping@verify-random:
- shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/shard-skl2/igt@gem_lmem_swapp...@verify-random.html
*
Re: [Intel-gfx] [PATCH v5 8/9] drm/i915/gem: Add extra pages in ttm_tt for ccs data
On 3/21/22 23:44, Ramalingam C wrote:
On Xe-HP and later devices, dedicated compression control state (CCS)
stored in local memory is used for each surface, to support the
3D and media compression formats.
The memory required for the CCS of the entire local memory is 1/256 of
the local memory size. So before the kernel boot, the required memory
is reserved for the CCS data and a secure register will be programmed
with the CCS base address
So when an object is allocated in local memory, dont need to explicitly
allocate the space for ccs data. But when the obj is evicted into the
smem, to hold the compression related data along with the obj extra space
is needed in smem. i.e obj_size + (obj_size/256).
Hence when a smem pages are allocated for an obj with lmem placement
possibility we create with the extra pages required for the ccs data for
the obj size.
v2:
Used imperative wording [Thomas]
v3:
Inflate the pages only when obj's placement is lmem only
Signed-off-by: Ramalingam C
cc: Christian Koenig
cc: Hellstrom Thomas
Reviewed-by: Thomas Hellstrom
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 29 -
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 3b9f99c765c4..0305a150b9d4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -20,6 +20,7 @@
#include "gem/i915_gem_ttm.h"
#include "gem/i915_gem_ttm_move.h"
#include "gem/i915_gem_ttm_pm.h"
+#include "gt/intel_gpu_commands.h"
#define I915_TTM_PRIO_PURGE 0
#define I915_TTM_PRIO_NO_PAGES 1
@@ -262,12 +263,33 @@ static const struct i915_refct_sgt_ops tt_rsgt_ops = {
.release = i915_ttm_tt_release
};
+static inline bool
+i915_gem_object_needs_ccs_pages(struct drm_i915_gem_object *obj)
+{
+ bool lmem_placement = false;
+ int i;
+
+ for (i = 0; i < obj->mm.n_placements; i++) {
+ /* Compression is not allowed for the objects with smem
placement */
+ if (obj->mm.placements[i]->type == INTEL_MEMORY_SYSTEM)
+ return false;
+ if (!lmem_placement &&
+ obj->mm.placements[i]->type == INTEL_MEMORY_LOCAL)
+ lmem_placement = true;
+ }
+
+ return lmem_placement;
+}
+
static struct ttm_tt *i915_ttm_tt_create(struct ttm_buffer_object *bo,
uint32_t page_flags)
{
+ struct drm_i915_private *i915 = container_of(bo->bdev, typeof(*i915),
+bdev);
struct ttm_resource_manager *man =
ttm_manager_type(bo->bdev, bo->resource->mem_type);
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+ unsigned long ccs_pages = 0;
enum ttm_caching caching;
struct i915_ttm_tt *i915_tt;
int ret;
@@ -290,7 +312,12 @@ static struct ttm_tt *i915_ttm_tt_create(struct
ttm_buffer_object *bo,
i915_tt->is_shmem = true;
}
- ret = ttm_tt_init(_tt->ttm, bo, page_flags, caching, 0);
+ if (HAS_FLAT_CCS(i915) && i915_gem_object_needs_ccs_pages(obj))
+ ccs_pages = DIV_ROUND_UP(DIV_ROUND_UP(bo->base.size,
+ NUM_BYTES_PER_CCS_BYTE),
+PAGE_SIZE);
+
+ ret = ttm_tt_init(_tt->ttm, bo, page_flags, caching, ccs_pages);
if (ret)
goto err_free;
Since we need to respin could we add (in __i915_ttm_get_pages())
/* Verify that gem never sees inflated system pages. Keep that local to
ttm */GEM_BUG_ON(bo->ttm && ((obj->base.size >> PAGE_SHIFT) <
bo->ttm->num_pages))
/Thomas
Re: [Intel-gfx] [PATCH v5 6/9] drm/i915/gt: offset handling for multiple copy engines
On 3/21/22 23:44, Ramalingam C wrote: Handle the src and dst chunk offsets for different instances of the copy engines. Signed-off-by: Ramalingam C --- drivers/gpu/drm/i915/gt/intel_migrate.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c index 39a5f8ae664d..5f6341f91622 100644 --- a/drivers/gpu/drm/i915/gt/intel_migrate.c +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c @@ -614,6 +614,9 @@ static int emit_copy(struct i915_request *rq, u32 instance = rq->engine->instance; u32 *cs; + src_offset += (u64)rq->engine->instance << 32; + dst_offset += (u64)rq->engine->instance << 32; + Again, these are nops since the offsets are 32-bit. Also the instance selection is already handled in the functon, so I think this patch can be dropped. cs = intel_ring_begin(rq, ver >= 8 ? 10 : 6); if (IS_ERR(cs)) return PTR_ERR(cs);
Re: [Intel-gfx] [PATCH v5 17/19] drm/i915/dg2: Flat CCS Support
On Tue, Feb 01, 2022 at 04:11:30PM +0530, Ramalingam C wrote:
> From: Anshuman Gupta
>
> DG2 onwards discrete gfx has support for new flat CCS mapping,
> which brings in display feature in to avoid Aux walk for compressed
> surface. This support build on top of Flat CCS support added in XEHPSDV.
> FLAT CCS surface base address should be 64k aligned,
> Compressed displayable surfaces must use tile4 format.
>
> HAS: 1407880786
> B.Spec : 7655
> B.Spec : 53902
>
> Cc: Mika Kahola
> Signed-off-by: Anshuman Gupta
> Signed-off-by: Juha-Pekka Heikkilä
> Signed-off-by: Ramalingam C
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++-
> drivers/gpu/drm/i915/display/intel_fb.c | 32 +--
> .../drm/i915/display/skl_universal_plane.c| 16 ++
> 3 files changed, 36 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 189767cef356..2828ae612179 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8588,7 +8588,9 @@ static void
> intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
>
> /*
>* The layout of the fast clear color value expected by HW
> - * (the DRM ABI requiring this value to be located in fb at
> offset 0 of plane#2):
> + * (the DRM ABI requiring this value to be located in fb at
> + * offset 0 of cc plane, plane #2 previous generations or
> + * plane #1 for flat ccs):
>* - 4 x 4 bytes per-channel value
>* (in surface type specific float/int format provided by the
> fb user)
>* - 8 bytes native color value used by the display
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> b/drivers/gpu/drm/i915/display/intel_fb.c
> index 3df6ef5ffec5..e94923e9dbb1 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -107,6 +107,21 @@ static const struct drm_format_info
> gen12_ccs_cc_formats[] = {
> .hsub = 1, .vsub = 1, .has_alpha = true },
> };
>
> +static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
> + { .format = DRM_FORMAT_XRGB, .depth = 24, .num_planes = 2,
> + .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_XBGR, .depth = 24, .num_planes = 2,
> + .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_ARGB, .depth = 32, .num_planes = 2,
> + .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR, .depth = 32, .num_planes = 2,
> + .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> +};
> +
> struct intel_modifier_desc {
> u64 modifier;
> struct {
> @@ -150,6 +165,8 @@ static const struct intel_modifier_desc intel_modifiers[]
> = {
> .plane_caps = INTEL_PLANE_CAP_TILING_4 |
> INTEL_PLANE_CAP_CCS_RC_CC,
>
> .ccs.cc_planes = BIT(1),
> +
> + FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats),
> }, {
> .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
> .display_ver = { 13, 13 },
> @@ -399,17 +416,13 @@ bool intel_fb_plane_supports_modifier(struct
> intel_plane *plane, u64 modifier)
> static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md,
>const struct drm_format_info *info)
> {
> - int yuv_planes;
> -
> if (!info->is_yuv)
> return false;
>
> - if (plane_caps_contain_any(md->plane_caps, INTEL_PLANE_CAP_CCS_MASK))
> - yuv_planes = 4;
> + if (hweight8(md->ccs.planar_aux_planes) == 2)
> + return info->num_planes == 4;
> else
> - yuv_planes = 2;
> -
> - return info->num_planes == yuv_planes;
> + return info->num_planes == 2;
> }
>
> /**
> @@ -534,12 +547,13 @@ static unsigned int gen12_ccs_aux_stride(struct
> intel_framebuffer *fb, int ccs_p
>
> int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
> {
> + const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
> struct drm_i915_private *i915 = to_i915(fb->dev);
>
> - if (intel_fb_is_ccs_modifier(fb->modifier))
> + if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes)
> return main_to_ccs_plane(fb, main_plane);
> else if (DISPLAY_VER(i915) < 11 &&
> - intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
> + format_is_yuv_semiplanar(md, fb->format))
>
Re: [Intel-gfx] [PATCH v5 3/9] drm/i915/gt: Clear compress metadata for Flat-ccs objects
Hi, Ram
On 3/21/22 23:44, Ramalingam C wrote:
Xe-HP and latest devices support Flat CCS which reserved a portion of
the device memory to store compression metadata, during the clearing of
device memory buffer object we also need to clear the associated
CCS buffer.
XY_CTRL_SURF_COPY_BLT is a BLT cmd used for reading and writing the
ccs surface of a lmem memory. So on Flat-CCS capable platform we use
XY_CTRL_SURF_COPY_BLT to clear the CCS meta data.
v2: Fixed issues with platform naming [Lucas]
v3: Rebased [Ram]
Used the round_up funcs [Bob]
v4: Fixed ccs blk calculation [Ram]
Added Kdoc on flat-ccs.
v5: GENMASK is used [Matt]
mocs fix [Matt]
Comments Fix [Matt]
Flush address programming [Ram]
v6: FLUSH_DW is fixed
Few coding style fix
v7: Adopting the XY_FAST_COLOR_BLT (Thomas]
v8: XY_CTRL_SURF_COPY_BLT for ccs clearing.
v9: emit_copy_ccs is used.
Signed-off-by: Ramalingam C
Signed-off-by: Ayaz A Siddiqui
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 15 ++
drivers/gpu/drm/i915/gt/intel_migrate.c | 164 ++-
2 files changed, 175 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 925e55b6a94f..6b4eb7927ec7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -153,8 +153,10 @@
#define MI_FLUSH_DW_PROTECTED_MEM_EN(1 << 22)
#define MI_FLUSH_DW_STORE_INDEX (1<<21)
#define MI_INVALIDATE_TLB (1<<18)
+#define MI_FLUSH_DW_CCS (1<<16)
#define MI_FLUSH_DW_OP_STOREDW (1<<14)
#define MI_FLUSH_DW_OP_MASK (3<<14)
+#define MI_FLUSH_DW_LLC (1<<9)
#define MI_FLUSH_DW_NOTIFY (1<<8)
#define MI_INVALIDATE_BSD (1<<7)
#define MI_FLUSH_DW_USE_GTT (1<<2)
@@ -203,6 +205,19 @@
#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
+#define XY_CTRL_SURF_INSTR_SIZE 5
+#define MI_FLUSH_DW_SIZE 3
+#define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)
+#define SRC_ACCESS_TYPE_SHIFT21
+#define DST_ACCESS_TYPE_SHIFT20
+#define CCS_SIZE_MASKGENMASK(17, 8)
+#define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 25)
+#define NUM_CCS_BYTES_PER_BLOCK 256
+#define NUM_BYTES_PER_CCS_BYTE 256
+#define NUM_CCS_BLKS_PER_XFER1024
+#define INDIRECT_ACCESS 0
+#define DIRECT_ACCESS1
+
#define COLOR_BLT_CMD (2 << 29 | 0x40 << 22 | (5 - 2))
#define XY_COLOR_BLT_CMD (2 << 29 | 0x50 << 22)
#define XY_FAST_COLOR_BLT_CMD (2 << 29 | 0x44 << 22)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index b656685a486d..39a5f8ae664d 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -16,7 +16,8 @@ struct insert_pte_data {
};
#define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
-
+#define GET_CCS_BYTES(i915, size) (HAS_FLAT_CCS(i915) ? \
+DIV_ROUND_UP(size,
NUM_BYTES_PER_CCS_BYTE) : 0)
static bool engine_supports_migration(struct intel_engine_cs *engine)
{
if (!engine)
@@ -467,6 +468,145 @@ static bool wa_1209644611_applies(int ver, u32 size)
return height % 4 == 3 && height <= 8;
}
+/**
+ * DOC: Flat-CCS - Memory compression for Local memory
+ *
+ * On Xe-HP and later devices, we use dedicated compression control state (CCS)
+ * stored in local memory for each surface, to support the 3D and media
+ * compression formats.
+ *
+ * The memory required for the CCS of the entire local memory is 1/256 of the
+ * local memory size. So before the kernel boot, the required memory is
reserved
+ * for the CCS data and a secure register will be programmed with the CCS base
+ * address.
+ *
+ * Flat CCS data needs to be cleared when a lmem object is allocated.
+ * And CCS data can be copied in and out of CCS region through
+ * XY_CTRL_SURF_COPY_BLT. CPU can't access the CCS data directly.
+ *
+ * When we exhaust the lmem, if the object's placements support smem, then we
can
+ * directly decompress the compressed lmem object into smem and start using it
+ * from smem itself.
+ *
+ * But when we need to swapout the compressed lmem object into a smem region
+ * though objects' placement doesn't support smem, then we copy the lmem
content
+ * as it is into smem region along with ccs data (using XY_CTRL_SURF_COPY_BLT).
+ * When the object is referred, lmem content will be swaped in along with
+ * restoration of the CCS data (using XY_CTRL_SURF_COPY_BLT) at corresponding
+ * location.
+ */
+
+static inline u32 *i915_flush_dw(u32 *cmd, u32 flags)
+{
+ *cmd++ = MI_FLUSH_DW |
[Intel-gfx] ✓ Fi.CI.BAT: success for lmem_size modparam
== Series Details ==
Series: lmem_size modparam
URL : https://patchwork.freedesktop.org/series/101744/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11402 -> Patchwork_22671
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/index.html
Participating hosts (44 -> 42)
--
Additional (2): fi-kbl-soraka fi-hsw-4770
Missing(4): fi-bsw-cyan shard-tglu fi-bdw-samus fi-pnv-d510
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22671:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/bat-rpls-2/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/bat-rpls-2/igt@i915_pm_...@module-reload.html
Known issues
Here are the changes found in Patchwork_22671 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#109315]) +17
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/fi-hsw-4770/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#3012])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-kbl-soraka: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1072]) +3
similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html
Possible fixes
* igt@i915_pm_rpm@module-reload:
- {bat-adlp-6}: [DMESG-WARN][15] ([i915#3576]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11402/bat-adlp-6/igt@i915_pm_...@module-reload.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/bat-adlp-6/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]:
Re: [Intel-gfx] [CI 1/1] drm/i915: add lmem_size modparam
LGTM Reviewed-by: Nirmoy Das
On 3/24/2022 3:31 PM, Matthew Auld wrote:
From: CQ Tang
lmem_size is used to limit the amount of lmem. Default is to use
hardware available lmem size, when setting this modpraram which is in MB
unit.
Signed-off-by: CQ Tang
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4
drivers/gpu/drm/i915/i915_params.c | 3 +++
drivers/gpu/drm/i915/i915_params.h | 1 +
3 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 783d81072c3b..f5111c0a0060 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -123,6 +123,10 @@ static struct intel_memory_region *setup_lmem(struct
intel_gt *gt)
lmem_size = intel_uncore_read64(>uncore, GEN12_GSMBASE);
}
+ if (i915->params.lmem_size > 0) {
+ lmem_size = min_t(resource_size_t, lmem_size,
+ mul_u32_u32(i915->params.lmem_size, SZ_1M));
+ }
io_start = pci_resource_start(pdev, 2);
io_size = min(pci_resource_len(pdev, 2), lmem_size);
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 5ad071e09301..701fbc98afa0 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -202,6 +202,9 @@ i915_param_named_unsafe(request_timeout_ms, uint, 0600,
"Default request/fence/batch buffer expiration
timeout.");
#endif
+i915_param_named_unsafe(lmem_size, uint, 0400,
+ "Set the lmem size(in MiB) for each region. (default: 0, all
memory)");
+
static __always_inline void _print_param(struct drm_printer *p,
const char *name,
const char *type,
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index c779a6f85c7e..b5e7ea45d191 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -73,6 +73,7 @@ struct drm_printer;
param(int, enable_dpcd_backlight, -1, 0600) \
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
param(unsigned int, request_timeout_ms,
CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
+ param(unsigned int, lmem_size, 0, 0400) \
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
param(bool, load_detect_test, false, 0600) \
[Intel-gfx] ✗ Fi.CI.DOCS: warning for lmem_size modparam
== Series Details == Series: lmem_size modparam URL : https://patchwork.freedesktop.org/series/101744/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found
Re: [Intel-gfx] [PATCH v5 2/9] drm/i915/gt: Optimize the migration and clear loop
On 3/21/22 23:44, Ramalingam C wrote:
Move the static calculations out of the loops for copy and clear.
Signed-off-by: Ramalingam C
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 44 -
1 file changed, 21 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 73199ebf0671..b656685a486d 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -526,6 +526,7 @@ intel_context_migrate_copy(struct intel_context *ce,
struct i915_request **out)
{
struct sgt_dma it_src = sg_sgt(src), it_dst = sg_sgt(dst);
+ u32 src_offset, dst_offset;
struct i915_request *rq;
int err;
@@ -534,8 +535,20 @@ intel_context_migrate_copy(struct intel_context *ce,
GEM_BUG_ON(ce->ring->size < SZ_64K);
+ src_offset = 0;
+ dst_offset = CHUNK_SZ;
+ if (HAS_64K_PAGES(ce->engine->i915)) {
+ GEM_BUG_ON(!src_is_lmem && !dst_is_lmem);
+
+ src_offset = 0;
+ dst_offset = 0;
+ if (src_is_lmem)
+ src_offset = CHUNK_SZ;
+ if (dst_is_lmem)
+ dst_offset = 2 * CHUNK_SZ;
+ }
+
do {
- u32 src_offset, dst_offset;
int len;
rq = i915_request_create(ce);
@@ -563,19 +576,6 @@ intel_context_migrate_copy(struct intel_context *ce,
if (err)
goto out_rq;
- src_offset = 0;
- dst_offset = CHUNK_SZ;
- if (HAS_64K_PAGES(ce->engine->i915)) {
- GEM_BUG_ON(!src_is_lmem && !dst_is_lmem);
-
- src_offset = 0;
- dst_offset = 0;
- if (src_is_lmem)
- src_offset = CHUNK_SZ;
- if (dst_is_lmem)
- dst_offset = 2 * CHUNK_SZ;
- }
-
len = emit_pte(rq, _src, src_cache_level, src_is_lmem,
src_offset, CHUNK_SZ);
if (len <= 0) {
@@ -585,12 +585,10 @@ intel_context_migrate_copy(struct intel_context *ce,
err = emit_pte(rq, _dst, dst_cache_level, dst_is_lmem,
dst_offset, len);
- if (err < 0)
- goto out_rq;
- if (err < len) {
+ if (err < len)
err = -EINVAL;
+ if (err < 0)
goto out_rq;
- }
err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
if (err)
@@ -694,6 +692,7 @@ intel_context_migrate_clear(struct intel_context *ce,
{
struct sgt_dma it = sg_sgt(sg);
struct i915_request *rq;
+ u32 offset;
int err;
GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
@@ -701,8 +700,11 @@ intel_context_migrate_clear(struct intel_context *ce,
GEM_BUG_ON(ce->ring->size < SZ_64K);
+ offset = 0;
+ if (HAS_64K_PAGES(ce->engine->i915) && is_lmem)
+ offset = CHUNK_SZ;
+
do {
- u32 offset;
int len;
rq = i915_request_create(ce);
@@ -730,10 +732,6 @@ intel_context_migrate_clear(struct intel_context *ce,
if (err)
goto out_rq;
- offset = 0;
- if (HAS_64K_PAGES(ce->engine->i915) && is_lmem)
- offset = CHUNK_SZ;
-
len = emit_pte(rq, , cache_level, is_lmem, offset, CHUNK_SZ);
if (len <= 0) {
err = len;
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for lmem_size modparam
== Series Details == Series: lmem_size modparam URL : https://patchwork.freedesktop.org/series/101744/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] Backlight Regression in i915 that isn't handled appropriately afaics
Hi i915 maintainers, this is your Linux kernel regression tracker! What's up with the following regression? https://gitlab.freedesktop.org/drm/intel/-/issues/5284 That report it more than two weeks old now, but seems nothing of substance happened. And the thing is: the report is older, as the issue in fact was reported on 2022-01-31 already here: https://bugzilla.kernel.org/show_bug.cgi?id=215553 After that there was a different ticket about it later here: https://gitlab.freedesktop.org/drm/intel/-/issues/5027 But it got confusing, so the reporter created the ticket the first link in this message points to. I fully understand some of the reasons why this was not handled appropriately, but it looks like even the latest ticket is mostly ignored, apart from some bug triaging. So could anybody please take a look into this at at least tell the reporter what to do to (bisection maybe?) get this solved? Ciao, Thorsten (wearing his 'the Linux kernel's regression tracker' hat) P.S.: As the Linux kernel's regression tracker I'm getting a lot of reports on my table. I can only look briefly into most of them and lack knowledge about most of the areas they concern. I thus unfortunately will sometimes get things wrong or miss something important. I hope that's not the case here; if you think it is, don't hesitate to tell me in a public reply, it's in everyone's interest to set the public record straight. P.S.S.: for rezgbot: Link: https://lore.kernel.org/regressions/74ee2216-a295-c2b6-328b-3e6d0cc18...@leemhuis.info/
Re: [Intel-gfx] [PATCH i-g-t 2/4] test/gem_lmem_swapping: fix physical engine usage
On 24/03/2022 14:26, Matthew Auld wrote:
DG2 seems to have too many physical engines, and during execbuf just hits:
FWIW it's not that DG2 has too many engines but the test was apparently
broken (because considering legacy eb ring selector as consecutive index
namespace within total number of engines is wrong) during porting to
upstream codebase.
Regards,
Tvrtko
"execbuf with unknown ring: 5"
Convert the test over to using the non-legacy API where we instead fill
the ctx with all the physical engines and then engine/ring becomes the
index into this.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5192
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
---
tests/i915/gem_lmem_swapping.c | 27 +++
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
index 193ff370..995a663f 100644
--- a/tests/i915/gem_lmem_swapping.c
+++ b/tests/i915/gem_lmem_swapping.c
@@ -126,6 +126,7 @@ verify_object(int i915, const struct object *obj, unsigned
int flags)
}
static void move_to_lmem(int i915,
+const intel_ctx_t *ctx,
struct object *list,
unsigned int num,
uint32_t batch,
@@ -137,6 +138,7 @@ static void move_to_lmem(int i915,
.buffers_ptr = to_user_pointer(obj),
.buffer_count = 1 + num,
.flags = I915_EXEC_NO_RELOC | I915_EXEC_HANDLE_LUT | engine,
+ .rsvd1 = ctx->id,
};
unsigned int i, ret;
@@ -156,6 +158,7 @@ retry:
}
static void __do_evict(int i915,
+ const intel_ctx_t *ctx,
struct drm_i915_gem_memory_class_instance *region,
struct params *params,
unsigned int seed)
@@ -170,7 +173,6 @@ static void __do_evict(int i915,
struct timespec t = {};
unsigned int num;
- __gem_context_set_persistence(i915, 0, false);
size = 4096;
batch = create_bo(i915, , region, params->oom_test);
@@ -201,7 +203,7 @@ static void __do_evict(int i915,
}
obj->handle = create_bo(i915, >size, region,
params->oom_test);
- move_to_lmem(i915, objects + i, 1, batch, engine,
+ move_to_lmem(i915, ctx, objects + i, 1, batch, engine,
params->oom_test);
if (params->flags & TEST_VERIFY)
init_object(i915, obj, rand(), params->flags);
@@ -226,7 +228,7 @@ static void __do_evict(int i915,
idx = (idx + 1) % params->count;
}
- move_to_lmem(i915, list, num, batch, engine, params->oom_test);
+ move_to_lmem(i915, ctx, list, num, batch, engine,
params->oom_test);
if (params->flags & TEST_ENGINES)
engine = (engine + 1) % __num_engines__;
@@ -342,6 +344,7 @@ static void fill_params(int i915, struct params *params,
}
static void test_evict(int i915,
+ const intel_ctx_t *ctx,
struct drm_i915_memory_region_info *region,
unsigned int flags)
{
@@ -353,14 +356,17 @@ static void test_evict(int i915,
if (flags & TEST_PARALLEL) {
int fd = gem_reopen_driver(i915);
+ ctx = intel_ctx_create_all_physical(fd);
+ __gem_context_set_persistence(i915, ctx->id, false);
+
igt_fork(child, nproc)
- __do_evict(fd, >region, ,
+ __do_evict(fd, ctx, >region, ,
params.seed + child + 1);
igt_waitchildren();
close(fd);
} else {
- __do_evict(i915, >region, , params.seed);
+ __do_evict(i915, ctx, >region, , params.seed);
}
}
@@ -399,6 +405,7 @@ static void smem_oom_exit_handler(int sig)
}
static void test_smem_oom(int i915,
+ const intel_ctx_t *ctx,
struct drm_i915_memory_region_info *region)
{
const uint64_t smem_size = intel_get_total_ram_mb() +
@@ -421,7 +428,7 @@ static void test_smem_oom(int i915,
fill_params(i915, , region, 0, 1, true);
igt_install_exit_handler(smem_oom_exit_handler);
- __do_evict(fd, >region, ,
+ __do_evict(fd, ctx, >region, ,
params.seed + child + 1);
close(fd);
@@ -513,6 +520,7 @@ igt_main_args("", long_options, help_str, opt_handler, NULL)
{ "parallel-multi", TEST_PARALLEL | TEST_RANDOM | TEST_VERIFY |
TEST_ENGINES | TEST_MULTI },
{ }
};
+ const intel_ctx_t *ctx;
int i915 = -1;
igt_fixture {
@@ -528,17 +536,20 @@ igt_main_args("", long_options, help_str, opt_handler,
NULL)
Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Introduce format modifier for DG2 clear color
On Thu, Mar 24, 2022 at 01:42:33AM +0200, Chery, Nanley G wrote:
> > -Original Message-
> > From: Deak, Imre
> > Sent: Monday, March 21, 2022 6:20 AM
> > To: Chery, Nanley G ; Juha-Pekka Heikkila
> >
> > Cc: Nanley Chery ; C, Ramalingam
> > ; intel-gfx ;
> > Auld, Matthew ; dri-devel
> >
> > Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Introduce format
> > modifier for DG2 clear color
> >
> > Hi Nanley, JP,
> >
> > On Tue, Feb 15, 2022 at 09:34:22PM +0200, Juha-Pekka Heikkila wrote:
> > > [...]
> > > > > > > > > > > diff --git a/include/uapi/drm/drm_fourcc.h
> > > > > > > > > > > b/include/uapi/drm/drm_fourcc.h index
> > > > > > > > > > > b8fb7b44c03c..697614ea4b84 100644
> > > > > > > > > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > > > > > > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > > > > > > > > @@ -605,6 +605,16 @@ extern "C" {
> > > > > > > > > > > */
> > > > > > > > > > > #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS
> > > > > > > > > > > fourcc_mod_code(INTEL, 11)
> > > > > > > > > > >
> > > > > > > > > > > +/*
> > > > > > > > > > > + * Intel color control surfaces (CCS) for DG2 clear
> > > > > > > > > > > color render compression.
> > > > > > > > > > > + *
> > > > > > > > > > > + * DG2 uses a unified compression format for clear color
> > > > > > > > > > > render compression.
> > > > > > > > > >
> > > > > > > > > > What's unified about DG2's compression format? If this
> > > > > > > > > > doesn't
> > > > > > > > > > affect the layout, maybe we should drop this sentence.
> >
> > Unified here probably refers to the fact the DG2 render engine is
> > capable of generating both a render and a media compressed surface as
> > opposed to earlier platforms. The display engine still needs to know
> > which compression format the FB uses, hence we need both an RC and MC
> > modifier. Based on this I also think we can drop the mention of unified
> > compression.
> >
> > > > > > > > > > > + * The general layout is a tiled layout using 4Kb tiles
> > > > > > > > > > > i.e. Tile4 layout.
> > > > > > > > > > > + *
> > > > > > > > > >
> > > > > > > > > > This also needs a pitch aligned to four tiles, right? I
> > > > > > > > > > think we
> > > > > > > > > > can save some effort by referencing the DG2_RC_CCS modifier
> > > > > > > > > > here.
> > > > > > > > > >
> > > > > > > > > > > + * Fast clear color value expected by HW is located in
> > > > > > > > > > > fb at offset 0 of plane#1
> > > > > > > > > >
> > > > > > > > > > Why is the expected offset hardcoded to 0 instead of
> > > > > > > > > > relying on
> > > > > > > > > > the offset provided by the modifier API? This looks like a
> > > > > > > > > > bug.
> > > > > > > > >
> > > > > > > > > Hi Nanley,
> > > > > > > > >
> > > > > > > > > can you elaborate a bit, which offset from modifier API that
> > > > > > > > > applies to cc surface?
> > > > > > > >
> > > > > > > > Hi Juha-Pekka,
> > > > > > > >
> > > > > > > > On the kernel-side of things, I'm thinking of
> > > > > > > > drm_mode_fb_cmd2::offsets[1].
> > > > > > >
> > > > > > > Hi Nanley,
> > > > > > >
> > > > > > > this offset is coming from userspace on creation of framebuffer,
> > > > > > > at
> > > > > > > that moment from userspace caller can point to offset of desire.
> > > > > > > Normally offset[0] is set at 0 and then offset[n] at plane n start
> > > > > > > which is not stated to have to be exactly after plane n-1 end. Or
> > > > > > > did I
> > > > > > > misunderstand what you meant?
> > > > > >
> > > > > > Perhaps, at least, I'm not sure what you're meaning to say. This
> > > > > > modifier description seems to say that the drm_mode_fb_cmd2::offsets
> > > > > > value for the clear color plane must be zero. Are you saying that
> > > > > > it's
> > > > > > correct? This doesn't match the GEN12_RC_CCS_CC behavior and doesn't
> > > > > > match mesa's expectations.
> > > > >
> > > > > It doesn't say "drm_mode_fb_cmd2::offsets value for the clear color
> > > > > plane must
> > > > > be zero", it says "Fast clear color value expected by HW is located
> > > > > in fb at offset 0
> > > > > of plane#1".
> > > >
> > > > Yes, it doesn't say that exactly, but that's what it seems to say. With
> > > > every other
> > > > modifier, it's implied that the data for the plane begins at the offset
> > > > specified
> > > > through the modifier API. So, explicitly mentioning it here (and with
> > > > that wording)
> > > > conveys a new requirement.
> > >
> > > I don't have objections on changing this description but for reference
> > > gen12
> > > version of the same says "The main surface is Y-tiled and is at plane
> > > index
> > > 0 whereas CCS is linear and at index 1. The clear color is stored at index
> > > 2, and the pitch should be ignored.", only plane indexes are mentioned. I
> > > anyway wrote neither of these descriptions.
> > >
> > > > > Plane#1 location is pointed by drm_mode_fb_cmd2::offsets[1] and
> > > > > there's
> > > > > nothing
Re: [Intel-gfx] [PATCH i-g-t 3/4] tests/gem_lmem_swapping: limit lmem to 4G
On 3/24/22 15:26, Matthew Auld wrote:
From: CQ Tang
On some systems lmem can be as large as 16G, which seems to trigger
various CI timeouts, and in the best case just takes a long time. For
the purposes of the test we should be able to limit to 4G, without any
big loss in coverage.
Signed-off-by: CQ Tang
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
Reviewed-by: Thomas Hellström
---
tests/i915/gem_lmem_swapping.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
index 995a663f..ad1c989c 100644
--- a/tests/i915/gem_lmem_swapping.c
+++ b/tests/i915/gem_lmem_swapping.c
@@ -526,7 +526,13 @@ igt_main_args("", long_options, help_str, opt_handler,
NULL)
igt_fixture {
struct intel_execution_engine2 *e;
- i915 = drm_open_driver(DRIVER_INTEL);
+ igt_i915_driver_unload();
+ if (igt_i915_driver_load("lmem_size=4096")) {
+ igt_debug("i915 missing lmem_size modparam support\n");
+ igt_assert_eq(igt_i915_driver_load(NULL), 0);
+ }
+
+ i915 = __drm_open_driver(DRIVER_INTEL);
igt_require_gem(i915);
igt_require(gem_has_lmem(i915));
@@ -554,6 +560,7 @@ igt_main_args("", long_options, help_str, opt_handler, NULL)
igt_fixture {
free(regions);
close(i915);
+ igt_i915_driver_unload();
}
igt_exit();
[Intel-gfx] [CI 0/1] lmem_size modparam
Test-with: 20220324142621.347452-1-matthew.a...@intel.com -- 2.34.1
[Intel-gfx] [CI 1/1] drm/i915: add lmem_size modparam
From: CQ Tang
lmem_size is used to limit the amount of lmem. Default is to use
hardware available lmem size, when setting this modpraram which is in MB
unit.
Signed-off-by: CQ Tang
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4
drivers/gpu/drm/i915/i915_params.c | 3 +++
drivers/gpu/drm/i915/i915_params.h | 1 +
3 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 783d81072c3b..f5111c0a0060 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -123,6 +123,10 @@ static struct intel_memory_region *setup_lmem(struct
intel_gt *gt)
lmem_size = intel_uncore_read64(>uncore, GEN12_GSMBASE);
}
+ if (i915->params.lmem_size > 0) {
+ lmem_size = min_t(resource_size_t, lmem_size,
+ mul_u32_u32(i915->params.lmem_size, SZ_1M));
+ }
io_start = pci_resource_start(pdev, 2);
io_size = min(pci_resource_len(pdev, 2), lmem_size);
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 5ad071e09301..701fbc98afa0 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -202,6 +202,9 @@ i915_param_named_unsafe(request_timeout_ms, uint, 0600,
"Default request/fence/batch buffer expiration
timeout.");
#endif
+i915_param_named_unsafe(lmem_size, uint, 0400,
+ "Set the lmem size(in MiB) for each region. (default:
0, all memory)");
+
static __always_inline void _print_param(struct drm_printer *p,
const char *name,
const char *type,
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index c779a6f85c7e..b5e7ea45d191 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -73,6 +73,7 @@ struct drm_printer;
param(int, enable_dpcd_backlight, -1, 0600) \
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
param(unsigned int, request_timeout_ms,
CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
+ param(unsigned int, lmem_size, 0, 0400) \
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
param(bool, load_detect_test, false, 0600) \
--
2.34.1
[Intel-gfx] [PATCH i-g-t 4/4] tests/gem_lmem_swapping: reduce the timeout
300s is way too much for some BAT test. Drop it down to 45s.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
---
tests/i915/gem_lmem_swapping.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
index ad1c989c..6c47bff2 100644
--- a/tests/i915/gem_lmem_swapping.c
+++ b/tests/i915/gem_lmem_swapping.c
@@ -219,7 +219,7 @@ static void __do_evict(int i915,
* For TEST_MULTI runs, make each object counts a loop to
* avoid excessive run times.
*/
- for (l = 0; l < params->loops && igt_seconds_elapsed() < 300; l +=
num) {
+ for (l = 0; l < params->loops && igt_seconds_elapsed() < 45; l +=
num) {
unsigned int idx = rand() % params->count;
num = params->flags & TEST_MULTI ? rand() % max_swap_in + 1 : 1;
--
2.34.1
[Intel-gfx] [PATCH i-g-t 3/4] tests/gem_lmem_swapping: limit lmem to 4G
From: CQ Tang
On some systems lmem can be as large as 16G, which seems to trigger
various CI timeouts, and in the best case just takes a long time. For
the purposes of the test we should be able to limit to 4G, without any
big loss in coverage.
Signed-off-by: CQ Tang
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
---
tests/i915/gem_lmem_swapping.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
index 995a663f..ad1c989c 100644
--- a/tests/i915/gem_lmem_swapping.c
+++ b/tests/i915/gem_lmem_swapping.c
@@ -526,7 +526,13 @@ igt_main_args("", long_options, help_str, opt_handler,
NULL)
igt_fixture {
struct intel_execution_engine2 *e;
- i915 = drm_open_driver(DRIVER_INTEL);
+ igt_i915_driver_unload();
+ if (igt_i915_driver_load("lmem_size=4096")) {
+ igt_debug("i915 missing lmem_size modparam support\n");
+ igt_assert_eq(igt_i915_driver_load(NULL), 0);
+ }
+
+ i915 = __drm_open_driver(DRIVER_INTEL);
igt_require_gem(i915);
igt_require(gem_has_lmem(i915));
@@ -554,6 +560,7 @@ igt_main_args("", long_options, help_str, opt_handler, NULL)
igt_fixture {
free(regions);
close(i915);
+ igt_i915_driver_unload();
}
igt_exit();
--
2.34.1
[Intel-gfx] [PATCH i-g-t 2/4] test/gem_lmem_swapping: fix physical engine usage
DG2 seems to have too many physical engines, and during execbuf just hits:
"execbuf with unknown ring: 5"
Convert the test over to using the non-legacy API where we instead fill
the ctx with all the physical engines and then engine/ring becomes the
index into this.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5192
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
---
tests/i915/gem_lmem_swapping.c | 27 +++
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
index 193ff370..995a663f 100644
--- a/tests/i915/gem_lmem_swapping.c
+++ b/tests/i915/gem_lmem_swapping.c
@@ -126,6 +126,7 @@ verify_object(int i915, const struct object *obj, unsigned
int flags)
}
static void move_to_lmem(int i915,
+const intel_ctx_t *ctx,
struct object *list,
unsigned int num,
uint32_t batch,
@@ -137,6 +138,7 @@ static void move_to_lmem(int i915,
.buffers_ptr = to_user_pointer(obj),
.buffer_count = 1 + num,
.flags = I915_EXEC_NO_RELOC | I915_EXEC_HANDLE_LUT | engine,
+ .rsvd1 = ctx->id,
};
unsigned int i, ret;
@@ -156,6 +158,7 @@ retry:
}
static void __do_evict(int i915,
+ const intel_ctx_t *ctx,
struct drm_i915_gem_memory_class_instance *region,
struct params *params,
unsigned int seed)
@@ -170,7 +173,6 @@ static void __do_evict(int i915,
struct timespec t = {};
unsigned int num;
- __gem_context_set_persistence(i915, 0, false);
size = 4096;
batch = create_bo(i915, , region, params->oom_test);
@@ -201,7 +203,7 @@ static void __do_evict(int i915,
}
obj->handle = create_bo(i915, >size, region,
params->oom_test);
- move_to_lmem(i915, objects + i, 1, batch, engine,
+ move_to_lmem(i915, ctx, objects + i, 1, batch, engine,
params->oom_test);
if (params->flags & TEST_VERIFY)
init_object(i915, obj, rand(), params->flags);
@@ -226,7 +228,7 @@ static void __do_evict(int i915,
idx = (idx + 1) % params->count;
}
- move_to_lmem(i915, list, num, batch, engine, params->oom_test);
+ move_to_lmem(i915, ctx, list, num, batch, engine,
params->oom_test);
if (params->flags & TEST_ENGINES)
engine = (engine + 1) % __num_engines__;
@@ -342,6 +344,7 @@ static void fill_params(int i915, struct params *params,
}
static void test_evict(int i915,
+ const intel_ctx_t *ctx,
struct drm_i915_memory_region_info *region,
unsigned int flags)
{
@@ -353,14 +356,17 @@ static void test_evict(int i915,
if (flags & TEST_PARALLEL) {
int fd = gem_reopen_driver(i915);
+ ctx = intel_ctx_create_all_physical(fd);
+ __gem_context_set_persistence(i915, ctx->id, false);
+
igt_fork(child, nproc)
- __do_evict(fd, >region, ,
+ __do_evict(fd, ctx, >region, ,
params.seed + child + 1);
igt_waitchildren();
close(fd);
} else {
- __do_evict(i915, >region, , params.seed);
+ __do_evict(i915, ctx, >region, , params.seed);
}
}
@@ -399,6 +405,7 @@ static void smem_oom_exit_handler(int sig)
}
static void test_smem_oom(int i915,
+ const intel_ctx_t *ctx,
struct drm_i915_memory_region_info *region)
{
const uint64_t smem_size = intel_get_total_ram_mb() +
@@ -421,7 +428,7 @@ static void test_smem_oom(int i915,
fill_params(i915, , region, 0, 1, true);
igt_install_exit_handler(smem_oom_exit_handler);
- __do_evict(fd, >region, ,
+ __do_evict(fd, ctx, >region, ,
params.seed + child + 1);
close(fd);
@@ -513,6 +520,7 @@ igt_main_args("", long_options, help_str, opt_handler, NULL)
{ "parallel-multi", TEST_PARALLEL | TEST_RANDOM | TEST_VERIFY |
TEST_ENGINES | TEST_MULTI },
{ }
};
+ const intel_ctx_t *ctx;
int i915 = -1;
igt_fixture {
@@ -528,17 +536,20 @@ igt_main_args("", long_options, help_str, opt_handler,
NULL)
for_each_physical_engine(i915, e)
__num_engines__++;
igt_require(__num_engines__);
+ ctx = intel_ctx_create_all_physical(i915);
+ __gem_context_set_persistence(i915, ctx->id, false);
+
}
[Intel-gfx] [PATCH i-g-t 1/4] test/gem_lmem_swapping: account for object rounding
On DG2 the object size might be rounded when allocating lmem. Make sure
we account for any rounding up.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
---
tests/i915/gem_lmem_swapping.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
index 582111dd..193ff370 100644
--- a/tests/i915/gem_lmem_swapping.c
+++ b/tests/i915/gem_lmem_swapping.c
@@ -72,7 +72,7 @@ struct object {
};
static uint32_t create_bo(int i915,
- uint64_t size,
+ uint64_t *size,
struct drm_i915_gem_memory_class_instance *region,
bool do_oom_test)
{
@@ -80,7 +80,7 @@ static uint32_t create_bo(int i915,
int ret;
retry:
- ret = __gem_create_in_memory_region_list(i915, , , region,
1);
+ ret = __gem_create_in_memory_region_list(i915, , size, region,
1);
if (do_oom_test && ret == -ENOMEM)
goto retry;
igt_assert_eq(ret, 0);
@@ -172,7 +172,7 @@ static void __do_evict(int i915,
__gem_context_set_persistence(i915, 0, false);
size = 4096;
- batch = create_bo(i915, size, region, params->oom_test);
+ batch = create_bo(i915, , region, params->oom_test);
gem_write(i915, batch, 0, , sizeof(bbe));
@@ -199,7 +199,7 @@ static void __do_evict(int i915,
params->count = i;
break;
}
- obj->handle = create_bo(i915, obj->size, region,
params->oom_test);
+ obj->handle = create_bo(i915, >size, region,
params->oom_test);
move_to_lmem(i915, objects + i, 1, batch, engine,
params->oom_test);
@@ -270,7 +270,7 @@ static void fill_params(int i915, struct params *params,
if (flags & TEST_RANDOM) {
params->size.min = 4096;
- handle = create_bo(i915, params->size.min, >region,
+ handle = create_bo(i915, >size.min, >region,
do_oom_test);
gem_close(i915, handle);
params->size.max = 2 * size + params->size.min;
--
2.34.1
[Intel-gfx] [PATCH i-g-t 0/4] Some gem_lmem_swapping tweaks
-- 2.34.1
Re: [Intel-gfx] [PATCH v5 15/19] drm/i915/dg2: Add DG2 unified compression
On Thu, Mar 24, 2022 at 01:40:37AM +0200, Chery, Nanley G wrote: > > [...] > > Capturing all the above would you be ok with the following?: > > > > Intel color control surfaces (CCS) for DG2 render compression. > > > > The main surface is Tile 4 and at plane index 0. The CCS data is stored > > outside of the GEM object in a reserved memory area dedicated for the > > storage of the CCS data from all GEM objects. The main surface pitch is > > required to be a multiple of four Tile 4 widths. > > > > > > Intel color control surfaces (CCS) for DG2 media compression. > > > > The main surface is Tile 4 and at plane index 0. For semi-planar formats > > like NV12, the UV plane is Tile 4 at plane index 1. The CCS data both for > > the main and semi-planar UV planes are stored outside of the GEM object > > This kind of implies that the Y plane is the main surface, but it's not more > "main" than the UV plane right? Seems like we should specifically call out the > Y plane for clarity. Maybe something like: > > For semi-planar formats like NV12, the Y and UV planes are Tile 4 and are > located at plane indices 0 and 1, respectively. The CCS for all planes are > stored > outside of the GEM object Ok, makes sense. > > in a reserved memory area dedicated for the storage of the CCS data from > > all GEM objects. The main surface pitch is required to be a multiple of > > four Tile 4 widths. > > Looks good to me. Main suggestion I have here is to substitute > "from all GEM objects" with "for all compressible GEM objects". "for all RC/RC_CC/MC CCS compressible GEM objects" would be more precise, in case there are other ways to compress data. Either way looks ok to me. > Happy to look at further revisions, but with that change at least, > Acked-by: Nanley Chery Thanks. --Imre
Re: [Intel-gfx] [RFC] drm/i915: Split out intel_vtd_active and run_as_guest to own header
On 24/03/2022 11:57, Jani Nikula wrote: On Thu, 24 Mar 2022, Tvrtko Ursulin wrote: On 24/03/2022 09:31, Jani Nikula wrote: On Tue, 22 Mar 2022, Tvrtko Ursulin wrote: From: Tvrtko Ursulin ... Signed-off-by: Tvrtko Ursulin Cc: Jani Nikula Cc: Lucas De Marchi --- Typed up how I see it - bash away. So is intel_vtd_active() so performance critical that it needs to be inline? We're passing struct drm_i915_private * everywhere we can, and it just feels silly to use struct drm_device * to avoid the include. Static inlines considered harmful. :p Same as it is ;), and gee, who was it that he said he was just trying to declutter i915_drv.h.. ;p Not at the cost of clarity elsewhere! To be clear now you oppose intel_vtd_active taking struct device? I thought you expressed general agreement when I presented the idea in the previous thread. I don't mind hugely to go either way, but I also don't see how taking struct device makes anything unclear. (I only think intel_vtd_run_as_guest is really wrong in this story but that's old news.) And if I make it take i915 then I would want to name it i915_vtd_active as well. But then you wouldn't like that. Should we just stuff all this into i915_utils for now, as I think Lucas suggested? Static inline or not, I don't care. Regards, Tvrtko
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Extend DP HDR support to hsw+ (rev4)
== Series Details ==
Series: drm/i915/display: Extend DP HDR support to hsw+ (rev4)
URL : https://patchwork.freedesktop.org/series/101708/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11401 -> Patchwork_22670
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_22670 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22670, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/index.html
Participating hosts (46 -> 41)
--
Additional (1): fi-kbl-8809g
Missing(6): fi-kbl-soraka shard-tglu bat-adlm-1 fi-bsw-cyan fi-pnv-d510
fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22670:
### IGT changes ###
Warnings
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][1] ([i915#4785]) -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11401/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_engines:
- {bat-rpls-2}: NOTRUN -> [INCOMPLETE][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/bat-rpls-2/igt@i915_selftest@live@gt_engines.html
Known issues
Here are the changes found in Patchwork_22670 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s0@smem:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][4] ([i915#4962]) +1 similar
issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/fi-kbl-8809g/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/fi-kbl-8809g/igt@gem_lmem_swapp...@random-engines.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: NOTRUN -> [DMESG-FAIL][7] ([i915#4494] / [i915#4957])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-snb-2600:[PASS][8] -> [INCOMPLETE][9] ([i915#3921])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11401/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-8809g: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-kbl-8809g: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#5341])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-8809g: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@cursor_plane_move:
- fi-kbl-8809g: NOTRUN -> [SKIP][13] ([fdo#109271]) +54 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html
Possible fixes
* igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}: [INCOMPLETE][14] -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11401/bat-rpls-2/igt@i915_pm_...@module-reload.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/bat-rpls-2/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-6: [INCOMPLETE][16] ([i915#4418]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11401/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22670/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the
Re: [Intel-gfx] [v3] drm/i915/display: Extend DP HDR support to hsw+
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, March 24, 2022 6:30 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v3] drm/i915/display: Extend DP HDR support to hsw+
>
> On Thu, Mar 24, 2022 at 11:58:15AM +, Shankar, Uma wrote:
> >
> >
> > > -Original Message-
> > > From: Ville Syrjälä
> > > Sent: Thursday, March 24, 2022 5:12 PM
> > > To: Shankar, Uma
> > > Cc: intel-gfx@lists.freedesktop.org
> > > Subject: Re: [v3] drm/i915/display: Extend DP HDR support to hsw+
> > >
> > > On Thu, Mar 24, 2022 at 04:39:59PM +0530, Uma Shankar wrote:
> > > > HSW+ platforms are able to send out HDR Metadata SDP DIP
> > > > packet as GMP. Hence, extending the support for HDR on DP encoders
> > > > for the same.
> > > >
> > > > v2: Limited to non eDP ports on hsw/bdw and removed it for lspcon
> > > > as it is done separately (suggested by Ville)
> > > >
> > > > v3: Added helper and limited eDP restriction to port A (Ville)
> > > >
> > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5389
> > > > Cc: Ville Syrjälä
> > > > Signed-off-by: Uma Shankar
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 22
> > > > +-
> > > > 1 file changed, 21 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index 9e19165fd175..c993d82c7ec9 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -4913,6 +4913,26 @@ bool intel_dp_is_port_edp(struct
> > > > drm_i915_private
> > > *dev_priv, enum port port)
> > > > return intel_bios_is_port_edp(dev_priv, port); }
> > > >
> > > > +static bool
> > > > +has_gamut_metadata_dip(struct drm_i915_private *dev_priv,
> > >
> > > s/dev_priv/i915/ for modern style
> >
> > Ok, will update
> >
> > >
> > > > + struct intel_dp *intel_dp, enum port port) {
> > > > + if (intel_bios_is_lspcon_present(dev_priv, port))
> > > > + return false;
> > > > +
> > > > + if (DISPLAY_VER(dev_priv) >= 10 && !IS_GEMINILAKE(dev_priv))
> > > > + return true;
> > >
> > > DISPLAY_VER >= 11
> > >
> > > > +
> > > > + if (port == PORT_A && intel_dp_is_edp(intel_dp))
> > >
> > > The is_edp check is still wrong. Should be just port==A.
> > > Also allows you to drop the intel_dp argument to the function.
> >
> > In the register description for VIDEO_DIP_CTL, (Bspec:7748)
> > BitField: VDIP Enable GMP
> > [BDW, SKL, BXT, KBL, KBLH, GLK, GLV, CFL, WHL, AML, CML, CNL, LKFR]
> > GMP is not supported on transcoder EDP going to DDI A.
> >
> > That's why was checking for eDP. But port A check should be good enough.
>
> Transcoder EDP is hardwired to DDI A. Despite the name it has nothing to do
> with
> eDP vs. DP.
>
> Having the eDP check would be just wrong because it would then attach the
> property
> to DDI A when it is used as an external DP port. And yes, such machines do in
> fact
> exist.
Yeah got the point. Thanks Ville for the review and valuable comments.
Regards,
Uma Shankar
>
> > Will drop it.
> >
> > > > + return false;
> > > > +
> > > > + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
> > > > + IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 9)
> > > > + return true;
> > >
> > > The IS_GLK check is redundant.
> >
> > Yeah will drop it.
> >
> > > > +
> > > > + return false;
> > > > +}
> > > > +
> > > > static void
> > > > intel_dp_add_properties(struct intel_dp *intel_dp, struct
> > > > drm_connector *connector) { @@ -4939,7 +4959,7 @@
> > > > intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector
> *connect
> > > > intel_attach_dp_colorspace_property(connector);
> > > > }
> > > >
> > > > - if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
> > > > + if (has_gamut_metadata_dip(dev_priv, intel_dp, port))
> > > > drm_object_attach_property(>base,
> > > >connector->dev-
> > > >mode_config.hdr_output_metadata_property,
> > > >0);
> > > > --
> > > > 2.25.1
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
[Intel-gfx] [PULL] drm-misc-next-fixes
The previous pull request tag was botched due to my key expiring, updated! drm-misc-next-fixes-2022-03-24-1: drm-misc-next-fixes for v5.18-rc1: - Make audio and color plane support checking only happen when a CEA extension block is found. - Fix a small regression from ttm_resource_fini() - Small selftest fix. The following changes since commit f6d790e5a7fe42706756c7fa1686d08d230610fc: Merge tag 'drm-intel-next-fixes-2022-03-10' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2022-03-11 13:27:00 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-fixes-2022-03-24-1 for you to fetch changes up to 7344bad7fb6daa4877a1c064b52c7d5f9182c41b: drm/edid: fix CEA extension byte #3 parsing (2022-03-24 11:41:14 +0200) drm-misc-next-fixes for v5.18-rc1: - Make audio and color plane support checking only happen when a CEA extension block is found. - Fix a small regression from ttm_resource_fini() - Small selftest fix. Cooper Chiou (1): drm/edid: check basic audio support on CEA extension block Jani Nikula (1): drm/edid: fix CEA extension byte #3 parsing Nathan Chancellor (1): drm/selftest: plane_helper: Put test structures in static storage Zack Rusin (1): drm/ttm: Fix a kernel oops due to an invalid read drivers/gpu/drm/drm_edid.c| 15 ++- drivers/gpu/drm/selftests/test-drm_plane_helper.c | 8 drivers/gpu/drm/ttm/ttm_range_manager.c | 2 +- 3 files changed, 15 insertions(+), 10 deletions(-)
[Intel-gfx] [PULL] drm-misc-next-fixes
drm-misc-next-fixes-2022-03-24: Short summary of fixes pull (less than what git shortlog provides): - explain anything non-fixes (e.g. cleanups) and why it's appropriate - highlight regressions - summarize pull requests contained This shouldn't be more than a few lines (or it indicates your fixes pull is a bit too big). The following changes since commit f6d790e5a7fe42706756c7fa1686d08d230610fc: Merge tag 'drm-intel-next-fixes-2022-03-10' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2022-03-11 13:27:00 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-fixes-2022-03-24 for you to fetch changes up to 7344bad7fb6daa4877a1c064b52c7d5f9182c41b: drm/edid: fix CEA extension byte #3 parsing (2022-03-24 11:41:14 +0200) Short summary of fixes pull (less than what git shortlog provides): - explain anything non-fixes (e.g. cleanups) and why it's appropriate - highlight regressions - summarize pull requests contained This shouldn't be more than a few lines (or it indicates your fixes pull is a bit too big). Cooper Chiou (1): drm/edid: check basic audio support on CEA extension block Jani Nikula (1): drm/edid: fix CEA extension byte #3 parsing Nathan Chancellor (1): drm/selftest: plane_helper: Put test structures in static storage Zack Rusin (1): drm/ttm: Fix a kernel oops due to an invalid read drivers/gpu/drm/drm_edid.c| 15 ++- drivers/gpu/drm/selftests/test-drm_plane_helper.c | 8 drivers/gpu/drm/ttm/ttm_range_manager.c | 2 +- 3 files changed, 15 insertions(+), 10 deletions(-)
Re: [Intel-gfx] [v4] drm/i915/display: Extend DP HDR support to hsw+
On Thu, Mar 24, 2022 at 05:34:38PM +0530, Uma Shankar wrote:
> HSW+ platforms are able to send out HDR Metadata SDP DIP
> packet as GMP. Hence, extending the support for HDR on DP
> encoders for the same.
>
> v2: Limited to non eDP ports on hsw/bdw and removed it for
> lspcon as it is done separately (suggested by Ville)
>
> v3: Added helper and limited eDP restriction to port A (Ville)
>
> v4: Dropped some redundant checks (Ville)
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5389
> Cc: Ville Syrjälä
> Signed-off-by: Uma Shankar
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 21 -
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9e19165fd175..fdcb169adb54 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4913,6 +4913,25 @@ bool intel_dp_is_port_edp(struct drm_i915_private
> *dev_priv, enum port port)
> return intel_bios_is_port_edp(dev_priv, port);
> }
>
> +static bool
> +has_gamut_metadata_dip(struct drm_i915_private *i915, enum port port)
> +{
> + if (intel_bios_is_lspcon_present(i915, port))
> + return false;
> +
> + if (DISPLAY_VER(i915) >= 11)
> + return true;
> +
> + if (port == PORT_A)
> + return false;
> +
> + if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
> + DISPLAY_VER(i915) >= 9)
> + return true;
> +
> + return false;
> +}
> +
> static void
> intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector
> *connector)
> {
> @@ -4939,7 +4958,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp,
> struct drm_connector *connect
> intel_attach_dp_colorspace_property(connector);
> }
>
> - if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
> + if (has_gamut_metadata_dip(dev_priv, port))
> drm_object_attach_property(>base,
>
> connector->dev->mode_config.hdr_output_metadata_property,
> 0);
> --
> 2.25.1
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [v3] drm/i915/display: Extend DP HDR support to hsw+
On Thu, Mar 24, 2022 at 11:58:15AM +, Shankar, Uma wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: Thursday, March 24, 2022 5:12 PM
> > To: Shankar, Uma
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [v3] drm/i915/display: Extend DP HDR support to hsw+
> >
> > On Thu, Mar 24, 2022 at 04:39:59PM +0530, Uma Shankar wrote:
> > > HSW+ platforms are able to send out HDR Metadata SDP DIP
> > > packet as GMP. Hence, extending the support for HDR on DP encoders for
> > > the same.
> > >
> > > v2: Limited to non eDP ports on hsw/bdw and removed it for lspcon as
> > > it is done separately (suggested by Ville)
> > >
> > > v3: Added helper and limited eDP restriction to port A (Ville)
> > >
> > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5389
> > > Cc: Ville Syrjälä
> > > Signed-off-by: Uma Shankar
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp.c | 22 +-
> > > 1 file changed, 21 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 9e19165fd175..c993d82c7ec9 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -4913,6 +4913,26 @@ bool intel_dp_is_port_edp(struct drm_i915_private
> > *dev_priv, enum port port)
> > > return intel_bios_is_port_edp(dev_priv, port); }
> > >
> > > +static bool
> > > +has_gamut_metadata_dip(struct drm_i915_private *dev_priv,
> >
> > s/dev_priv/i915/ for modern style
>
> Ok, will update
>
> >
> > > +struct intel_dp *intel_dp, enum port port) {
> > > + if (intel_bios_is_lspcon_present(dev_priv, port))
> > > + return false;
> > > +
> > > + if (DISPLAY_VER(dev_priv) >= 10 && !IS_GEMINILAKE(dev_priv))
> > > + return true;
> >
> > DISPLAY_VER >= 11
> >
> > > +
> > > + if (port == PORT_A && intel_dp_is_edp(intel_dp))
> >
> > The is_edp check is still wrong. Should be just port==A.
> > Also allows you to drop the intel_dp argument to the function.
>
> In the register description for VIDEO_DIP_CTL, (Bspec:7748)
> BitField: VDIP Enable GMP
> [BDW, SKL, BXT, KBL, KBLH, GLK, GLV, CFL, WHL, AML, CML, CNL, LKFR]
> GMP is not supported on transcoder EDP going to DDI A.
>
> That's why was checking for eDP. But port A check should be good enough.
Transcoder EDP is hardwired to DDI A. Despite the name it has
nothing to do with eDP vs. DP.
Having the eDP check would be just wrong because it would then
attach the property to DDI A when it is used as an external DP
port. And yes, such machines do in fact exist.
> Will drop it.
>
> > > + return false;
> > > +
> > > + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
> > > + IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 9)
> > > + return true;
> >
> > The IS_GLK check is redundant.
>
> Yeah will drop it.
>
> > > +
> > > + return false;
> > > +}
> > > +
> > > static void
> > > intel_dp_add_properties(struct intel_dp *intel_dp, struct
> > > drm_connector *connector) { @@ -4939,7 +4959,7 @@
> > > intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector
> > > *connect
> > > intel_attach_dp_colorspace_property(connector);
> > > }
> > >
> > > - if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
> > > + if (has_gamut_metadata_dip(dev_priv, intel_dp, port))
> > > drm_object_attach_property(>base,
> > > connector->dev-
> > >mode_config.hdr_output_metadata_property,
> > > 0);
> > > --
> > > 2.25.1
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL
On Thu, 2022-03-24 at 13:30 +0200, Ville Syrjälä wrote:
> On Tue, Mar 22, 2022 at 02:46:15PM -0700, José Roberto de Souza wrote:
> > PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being
> > enabled but that could potentially cause issues as it could have
> > mismatching values while pipes are being enabled.
> >
> > So here moving the PIPE_MBUS_DBOX_CTL programming of all pipes to be
> > executed before the function that enables all pipes, leaving all pipes
> > with a matching A_CREDIT value.
> >
> > While at it, also moving it to intel_pm.c as we are trying to reduce
> > the gigantic size of it and intel_pm.c have other MBUS programing
> > sequences.
> >
> > v2:
> > - do not program PIPE_MBUS_DBOX_CTL if pipe will not be active or
> > when it do not needs modeset
> > - remove the checks to wait a vblank
> >
> > BSpec: 49213
> > BSpec: 50343
> > Cc: Ville Syrjälä
> > Cc: Stanislav Lisovskiy
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 37 +--
> > drivers/gpu/drm/i915/intel_pm.c | 47
> > drivers/gpu/drm/i915/intel_pm.h | 1 +
> > 3 files changed, 49 insertions(+), 36 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 424cd7e9afe60..ef5076b5e7027 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1824,35 +1824,6 @@ static void glk_pipe_scaler_clock_gating_wa(struct
> > drm_i915_private *dev_priv,
> > intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
> > }
> >
> > -static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
> > -{
> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > - enum pipe pipe = crtc->pipe;
> > - u32 val;
> > -
> > - val = intel_de_read(dev_priv, PIPE_MBUS_DBOX_CTL(pipe));
> > - val &= ~MBUS_DBOX_A_CREDIT_MASK;
> > - /* Wa_22010947358:adl-p */
> > - if (IS_ALDERLAKE_P(dev_priv))
> > - val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
> > MBUS_DBOX_A_CREDIT(4);
> > - else
> > - val |= MBUS_DBOX_A_CREDIT(2);
> > -
> > - val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK);
> > - if (IS_ALDERLAKE_P(dev_priv)) {
> > - val |= MBUS_DBOX_BW_CREDIT(2);
> > - val |= MBUS_DBOX_B_CREDIT(8);
> > - } else if (DISPLAY_VER(dev_priv) >= 12) {
> > - val |= MBUS_DBOX_BW_CREDIT(2);
> > - val |= MBUS_DBOX_B_CREDIT(12);
> > - } else {
> > - val |= MBUS_DBOX_BW_CREDIT(1);
> > - val |= MBUS_DBOX_B_CREDIT(8);
> > - }
> > -
> > - intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
> > -}
> > -
> > static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > @@ -1988,13 +1959,6 @@ static void hsw_crtc_enable(struct
> > intel_atomic_state *state,
> >
> > intel_initial_watermarks(state, crtc);
> >
> > - if (DISPLAY_VER(dev_priv) >= 11) {
> > - const struct intel_dbuf_state *dbuf_state =
> > - intel_atomic_get_new_dbuf_state(state);
> > -
> > - icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus);
> > - }
> > -
> > if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
> > intel_crtc_vblank_on(new_crtc_state);
> >
> > @@ -8599,6 +8563,7 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> > intel_encoders_update_prepare(state);
> >
> > intel_dbuf_pre_plane_update(state);
> > + intel_mbus_dbox_update(state);
> >
> > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > if (new_crtc_state->do_async_flip)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index e60c02d760ffa..cf290bb704221 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -8258,3 +8258,50 @@ void intel_dbuf_post_plane_update(struct
> > intel_atomic_state *state)
> > gen9_dbuf_slices_update(dev_priv,
> > new_dbuf_state->enabled_slices);
> > }
> > +
> > +void intel_mbus_dbox_update(struct intel_atomic_state *state)
> > +{
> > + struct drm_i915_private *i915 = to_i915(state->base.dev);
> > + struct intel_crtc_state *new_crtc_state;
> > + struct intel_dbuf_state *new_dbuf_state;
> > + struct intel_crtc *crtc;
> > + int i;
> > +
> > + if (DISPLAY_VER(i915) < 11 || !state->modeset)
> > + return;
> > +
> > + if (HAS_MBUS_JOINING(i915))
> > + new_dbuf_state = intel_atomic_get_dbuf_state(state);
> > +
> > + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > + u32 val;
> > +
> > + if (!new_crtc_state->hw.active ||
> > +
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/display: Extend DP HDR support to hsw+ (rev4)
== Series Details == Series: drm/i915/display: Extend DP HDR support to hsw+ (rev4) URL : https://patchwork.freedesktop.org/series/101708/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Extend DP HDR support to hsw+ (rev2)
== Series Details ==
Series: drm/i915/display: Extend DP HDR support to hsw+ (rev2)
URL : https://patchwork.freedesktop.org/series/101708/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11398_full -> Patchwork_22669_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22669_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22669_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (12 -> 12)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22669_full:
### IGT changes ###
Possible regressions
* igt@kms_color@pipe-c-legacy-gamma:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-kbl3/igt@kms_co...@pipe-c-legacy-gamma.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/shard-kbl6/igt@kms_co...@pipe-c-legacy-gamma.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- {shard-rkl}:NOTRUN -> [SKIP][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/shard-rkl-4/igt@kms_frontbuffer_track...@fbcpsr-tiling-4.html
Known issues
Here are the changes found in Patchwork_22669_full that come from known
issues:
### CI changes ###
Issues hit
* boot:
- shard-glk: ([PASS][4], [PASS][5], [PASS][6], [PASS][7],
[PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13],
[PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19],
[PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25],
[PASS][26], [PASS][27], [PASS][28]) -> ([FAIL][29], [PASS][30], [PASS][31],
[PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37],
[PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43],
[PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49],
[PASS][50], [PASS][51], [PASS][52], [PASS][53]) ([i915#4392])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk6/boot.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk7/boot.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk7/boot.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk8/boot.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk8/boot.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk8/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk9/boot.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk9/boot.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk9/boot.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk6/boot.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk5/boot.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk5/boot.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk4/boot.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk4/boot.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk4/boot.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk3/boot.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk3/boot.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk3/boot.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk2/boot.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk2/boot.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk2/boot.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk1/boot.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk1/boot.html
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk1/boot.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk1/boot.html
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/shard-glk1/boot.html
[30]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/shard-glk1/boot.html
[31]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/shard-glk1/boot.html
[32]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/shard-glk2/boot.html
[33]:
[Intel-gfx] [v4] drm/i915/display: Extend DP HDR support to hsw+
HSW+ platforms are able to send out HDR Metadata SDP DIP
packet as GMP. Hence, extending the support for HDR on DP
encoders for the same.
v2: Limited to non eDP ports on hsw/bdw and removed it for
lspcon as it is done separately (suggested by Ville)
v3: Added helper and limited eDP restriction to port A (Ville)
v4: Dropped some redundant checks (Ville)
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5389
Cc: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9e19165fd175..fdcb169adb54 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4913,6 +4913,25 @@ bool intel_dp_is_port_edp(struct drm_i915_private
*dev_priv, enum port port)
return intel_bios_is_port_edp(dev_priv, port);
}
+static bool
+has_gamut_metadata_dip(struct drm_i915_private *i915, enum port port)
+{
+ if (intel_bios_is_lspcon_present(i915, port))
+ return false;
+
+ if (DISPLAY_VER(i915) >= 11)
+ return true;
+
+ if (port == PORT_A)
+ return false;
+
+ if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
+ DISPLAY_VER(i915) >= 9)
+ return true;
+
+ return false;
+}
+
static void
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector
*connector)
{
@@ -4939,7 +4958,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct
drm_connector *connect
intel_attach_dp_colorspace_property(connector);
}
- if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
+ if (has_gamut_metadata_dip(dev_priv, port))
drm_object_attach_property(>base,
connector->dev->mode_config.hdr_output_metadata_property,
0);
--
2.25.1
Re: [Intel-gfx] [v3] drm/i915/display: Extend DP HDR support to hsw+
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, March 24, 2022 5:12 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v3] drm/i915/display: Extend DP HDR support to hsw+
>
> On Thu, Mar 24, 2022 at 04:39:59PM +0530, Uma Shankar wrote:
> > HSW+ platforms are able to send out HDR Metadata SDP DIP
> > packet as GMP. Hence, extending the support for HDR on DP encoders for
> > the same.
> >
> > v2: Limited to non eDP ports on hsw/bdw and removed it for lspcon as
> > it is done separately (suggested by Ville)
> >
> > v3: Added helper and limited eDP restriction to port A (Ville)
> >
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5389
> > Cc: Ville Syrjälä
> > Signed-off-by: Uma Shankar
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 22 +-
> > 1 file changed, 21 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 9e19165fd175..c993d82c7ec9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -4913,6 +4913,26 @@ bool intel_dp_is_port_edp(struct drm_i915_private
> *dev_priv, enum port port)
> > return intel_bios_is_port_edp(dev_priv, port); }
> >
> > +static bool
> > +has_gamut_metadata_dip(struct drm_i915_private *dev_priv,
>
> s/dev_priv/i915/ for modern style
Ok, will update
>
> > + struct intel_dp *intel_dp, enum port port) {
> > + if (intel_bios_is_lspcon_present(dev_priv, port))
> > + return false;
> > +
> > + if (DISPLAY_VER(dev_priv) >= 10 && !IS_GEMINILAKE(dev_priv))
> > + return true;
>
> DISPLAY_VER >= 11
>
> > +
> > + if (port == PORT_A && intel_dp_is_edp(intel_dp))
>
> The is_edp check is still wrong. Should be just port==A.
> Also allows you to drop the intel_dp argument to the function.
In the register description for VIDEO_DIP_CTL, (Bspec:7748)
BitField: VDIP Enable GMP
[BDW, SKL, BXT, KBL, KBLH, GLK, GLV, CFL, WHL, AML, CML, CNL, LKFR]
GMP is not supported on transcoder EDP going to DDI A.
That's why was checking for eDP. But port A check should be good enough.
Will drop it.
> > + return false;
> > +
> > + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
> > + IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 9)
> > + return true;
>
> The IS_GLK check is redundant.
Yeah will drop it.
> > +
> > + return false;
> > +}
> > +
> > static void
> > intel_dp_add_properties(struct intel_dp *intel_dp, struct
> > drm_connector *connector) { @@ -4939,7 +4959,7 @@
> > intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector
> > *connect
> > intel_attach_dp_colorspace_property(connector);
> > }
> >
> > - if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
> > + if (has_gamut_metadata_dip(dev_priv, intel_dp, port))
> > drm_object_attach_property(>base,
> >connector->dev-
> >mode_config.hdr_output_metadata_property,
> >0);
> > --
> > 2.25.1
>
> --
> Ville Syrjälä
> Intel
Re: [Intel-gfx] [RFC] drm/i915: Split out intel_vtd_active and run_as_guest to own header
On Thu, 24 Mar 2022, Tvrtko Ursulin wrote:
> On 24/03/2022 09:31, Jani Nikula wrote:
>> On Tue, 22 Mar 2022, Tvrtko Ursulin wrote:
>>> From: Tvrtko Ursulin
>>>
>>> ...
>>>
>>> Signed-off-by: Tvrtko Ursulin
>>> Cc: Jani Nikula
>>> Cc: Lucas De Marchi
>>> ---
>>> Typed up how I see it - bash away.
>>
>> So is intel_vtd_active() so performance critical that it needs to be
>> inline?
>>
>> We're passing struct drm_i915_private * everywhere we can, and it just
>> feels silly to use struct drm_device * to avoid the include.
>>
>> Static inlines considered harmful. :p
>
> Same as it is ;), and gee, who was it that he said he was just trying to
> declutter i915_drv.h.. ;p
Not at the cost of clarity elsewhere!
>
> Regards,
>
> Tvrtko
>
>>
>> BR,
>> Jani.
>>
>>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_bw.c | 3 +-
>>> drivers/gpu/drm/i915/display/intel_display.c | 9 -
>>> drivers/gpu/drm/i915/display/intel_display.h | 2 ++
>>> drivers/gpu/drm/i915/display/intel_fbc.c | 3 +-
>>> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 3 +-
>>> drivers/gpu/drm/i915/gem/i915_gemfs.c| 3 +-
>>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 5 +--
>>> drivers/gpu/drm/i915/gt/intel_gtt.c | 12 +++
>>> drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++
>>> drivers/gpu/drm/i915/i915_debugfs.c | 1 +
>>> drivers/gpu/drm/i915/i915_driver.c | 3 +-
>>> drivers/gpu/drm/i915/i915_driver.h | 4 +++
>>> drivers/gpu/drm/i915/i915_drv.h | 37
>>> drivers/gpu/drm/i915/i915_gpu_error.c| 3 +-
>>> drivers/gpu/drm/i915/intel_device_info.c | 4 ++-
>>> drivers/gpu/drm/i915/intel_pch.c | 3 +-
>>> drivers/gpu/drm/i915/intel_vtd.h | 27 ++
>>> 17 files changed, 76 insertions(+), 48 deletions(-)
>>> create mode 100644 drivers/gpu/drm/i915/intel_vtd.h
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
>>> b/drivers/gpu/drm/i915/display/intel_bw.c
>>> index ac11ff19e47d..6c9cb4f97218 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>>> @@ -13,6 +13,7 @@
>>> #include "intel_mchbar_regs.h"
>>> #include "intel_pcode.h"
>>> #include "intel_pm.h"
>>> +#include "intel_vtd.h"
>>>
>>> /* Parameters for Qclk Geyserville (QGV) */
>>> struct intel_qgv_point {
>>> @@ -649,7 +650,7 @@ static unsigned int intel_bw_data_rate(struct
>>> drm_i915_private *dev_priv,
>>> for_each_pipe(dev_priv, pipe)
>>> data_rate += bw_state->data_rate[pipe];
>>>
>>> - if (DISPLAY_VER(dev_priv) >= 13 && intel_vtd_active(dev_priv))
>>> + if (DISPLAY_VER(dev_priv) >= 13 && intel_vtd_active(dev_priv->drm.dev))
>>> data_rate = DIV_ROUND_UP(data_rate * 105, 100);
>>>
>>> return data_rate;
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>>> b/drivers/gpu/drm/i915/display/intel_display.c
>>> index dc6e21e4ef0b..e80f3ca3ee4e 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>> @@ -110,6 +110,7 @@
>>> #include "intel_quirks.h"
>>> #include "intel_sprite.h"
>>> #include "intel_tc.h"
>>> +#include "intel_vtd.h"
>>> #include "intel_vga.h"
>>> #include "i9xx_plane.h"
>>> #include "skl_scaler.h"
>>> @@ -1197,7 +1198,7 @@ static bool needs_async_flip_vtd_wa(const struct
>>> intel_crtc_state *crtc_state)
>>> {
>>> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>>>
>>> - return crtc_state->uapi.async_flip && intel_vtd_active(i915) &&
>>> + return crtc_state->uapi.async_flip && intel_vtd_active(i915->drm.dev) &&
>>> (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) ||
>>> IS_HASWELL(i915));
>>> }
>>>
>>> @@ -10699,3 +10700,9 @@ void intel_display_driver_unregister(struct
>>> drm_i915_private *i915)
>>> acpi_video_unregister();
>>> intel_opregion_unregister(i915);
>>> }
>>> +
>>> +bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
>>> +{
>>> + return DISPLAY_VER(dev_priv) >= 6 &&
>>> + intel_vtd_active(dev_priv->drm.dev);
>>> +}
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
>>> b/drivers/gpu/drm/i915/display/intel_display.h
>>> index 8513703086b7..d69587c76e71 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.h
>>> @@ -694,4 +694,6 @@ void assert_transcoder(struct drm_i915_private
>>> *dev_priv,
>>> #define I915_STATE_WARN_ON(x)
>>> \
>>> I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
>>>
>>> +bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv);
>>> +
>>> #endif
>>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
>>> b/drivers/gpu/drm/i915/display/intel_fbc.c
>>> index 142280b6ce6d..00a3e30587a5 100644
>>> ---
Re: [Intel-gfx] [RFC] drm/i915: Split out intel_vtd_active and run_as_guest to own header
On 24/03/2022 09:31, Jani Nikula wrote:
On Tue, 22 Mar 2022, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
...
Signed-off-by: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Lucas De Marchi
---
Typed up how I see it - bash away.
So is intel_vtd_active() so performance critical that it needs to be
inline?
We're passing struct drm_i915_private * everywhere we can, and it just
feels silly to use struct drm_device * to avoid the include.
Static inlines considered harmful. :p
Same as it is ;), and gee, who was it that he said he was just trying to
declutter i915_drv.h.. ;p
Regards,
Tvrtko
BR,
Jani.
---
drivers/gpu/drm/i915/display/intel_bw.c | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 9 -
drivers/gpu/drm/i915/display/intel_display.h | 2 ++
drivers/gpu/drm/i915/display/intel_fbc.c | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 3 +-
drivers/gpu/drm/i915/gem/i915_gemfs.c| 3 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 5 +--
drivers/gpu/drm/i915/gt/intel_gtt.c | 12 +++
drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++
drivers/gpu/drm/i915/i915_debugfs.c | 1 +
drivers/gpu/drm/i915/i915_driver.c | 3 +-
drivers/gpu/drm/i915/i915_driver.h | 4 +++
drivers/gpu/drm/i915/i915_drv.h | 37
drivers/gpu/drm/i915/i915_gpu_error.c| 3 +-
drivers/gpu/drm/i915/intel_device_info.c | 4 ++-
drivers/gpu/drm/i915/intel_pch.c | 3 +-
drivers/gpu/drm/i915/intel_vtd.h | 27 ++
17 files changed, 76 insertions(+), 48 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_vtd.h
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index ac11ff19e47d..6c9cb4f97218 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -13,6 +13,7 @@
#include "intel_mchbar_regs.h"
#include "intel_pcode.h"
#include "intel_pm.h"
+#include "intel_vtd.h"
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
@@ -649,7 +650,7 @@ static unsigned int intel_bw_data_rate(struct
drm_i915_private *dev_priv,
for_each_pipe(dev_priv, pipe)
data_rate += bw_state->data_rate[pipe];
- if (DISPLAY_VER(dev_priv) >= 13 && intel_vtd_active(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 13 && intel_vtd_active(dev_priv->drm.dev))
data_rate = DIV_ROUND_UP(data_rate * 105, 100);
return data_rate;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index dc6e21e4ef0b..e80f3ca3ee4e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -110,6 +110,7 @@
#include "intel_quirks.h"
#include "intel_sprite.h"
#include "intel_tc.h"
+#include "intel_vtd.h"
#include "intel_vga.h"
#include "i9xx_plane.h"
#include "skl_scaler.h"
@@ -1197,7 +1198,7 @@ static bool needs_async_flip_vtd_wa(const struct
intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- return crtc_state->uapi.async_flip && intel_vtd_active(i915) &&
+ return crtc_state->uapi.async_flip && intel_vtd_active(i915->drm.dev) &&
(DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) ||
IS_HASWELL(i915));
}
@@ -10699,3 +10700,9 @@ void intel_display_driver_unregister(struct drm_i915_private *i915)
acpi_video_unregister();
intel_opregion_unregister(i915);
}
+
+bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
+{
+ return DISPLAY_VER(dev_priv) >= 6 &&
+ intel_vtd_active(dev_priv->drm.dev);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 8513703086b7..d69587c76e71 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -694,4 +694,6 @@ void assert_transcoder(struct drm_i915_private *dev_priv,
#define I915_STATE_WARN_ON(x) \
I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
+bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv);
+
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 142280b6ce6d..00a3e30587a5 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -50,6 +50,7 @@
#include "intel_display_types.h"
#include "intel_fbc.h"
#include "intel_frontbuffer.h"
+#include "intel_vtd.h"
#define for_each_fbc_id(__dev_priv, __fbc_id) \
for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS;
(__fbc_id)++) \
@@ -1643,7 +1644,7 @@ static int intel_sanitize_fbc_option(struct
drm_i915_private *i915)
static bool need_fbc_vtd_wa(struct drm_i915_private *i915)
{
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dsb: modified to drm_info in dsb_prepare()
== Series Details ==
Series: drm/i915/dsb: modified to drm_info in dsb_prepare()
URL : https://patchwork.freedesktop.org/series/101723/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11398_full -> Patchwork_22668_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (12 -> 12)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22668_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_nop@basic-series:
- {shard-rkl}:NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/shard-rkl-5/igt@gem_exec_...@basic-series.html
Known issues
Here are the changes found in Patchwork_22668_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: [PASS][2] -> [DMESG-WARN][3] ([i915#180]) +1 similar
issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-kbl7/igt@gem_ctx_isolation@preservation...@bcs0.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/shard-kbl1/igt@gem_ctx_isolation@preservation...@bcs0.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][4] -> [SKIP][5] ([i915#4525])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-iclb4/igt@gem_exec_balan...@parallel-balancer.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/shard-iclb3/igt@gem_exec_balan...@parallel-balancer.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2846])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-kbl1/igt@gem_exec_f...@basic-deadline.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/shard-kbl4/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-skl: NOTRUN -> [SKIP][8] ([fdo#109271]) +105 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/shard-skl1/igt@gem_exec_fair@basic-f...@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/shard-apl4/igt@gem_exec_fair@basic-n...@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/shard-tglb6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][15] -> [FAIL][16] ([i915#2842])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-kbl7/igt@gem_exec_fair@basic-p...@vecs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/shard-kbl7/igt@gem_exec_fair@basic-p...@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#2849])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/shard-iclb3/igt@gem_exec_fair@basic-throt...@rcs0.html
* igt@gem_lmem_swapping@heavy-random:
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#4613])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/shard-tglb7/igt@gem_lmem_swapp...@heavy-random.html
* igt@gem_lmem_swapping@parallel-random:
- shard-skl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/shard-skl6/igt@gem_lmem_swapp...@parallel-random.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/shard-apl3/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_mmap_gtt@fault-concurrent-y:
- shard-snb: [PASS][22] -> [INCOMPLETE][23] ([i915#5161])
[22]:
Re: [Intel-gfx] [v3] drm/i915/display: Extend DP HDR support to hsw+
On Thu, Mar 24, 2022 at 04:39:59PM +0530, Uma Shankar wrote:
> HSW+ platforms are able to send out HDR Metadata SDP DIP
> packet as GMP. Hence, extending the support for HDR on DP
> encoders for the same.
>
> v2: Limited to non eDP ports on hsw/bdw and removed it for
> lspcon as it is done separately (suggested by Ville)
>
> v3: Added helper and limited eDP restriction to port A (Ville)
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5389
> Cc: Ville Syrjälä
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 22 +-
> 1 file changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9e19165fd175..c993d82c7ec9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4913,6 +4913,26 @@ bool intel_dp_is_port_edp(struct drm_i915_private
> *dev_priv, enum port port)
> return intel_bios_is_port_edp(dev_priv, port);
> }
>
> +static bool
> +has_gamut_metadata_dip(struct drm_i915_private *dev_priv,
s/dev_priv/i915/ for modern style
> +struct intel_dp *intel_dp, enum port port)
> +{
> + if (intel_bios_is_lspcon_present(dev_priv, port))
> + return false;
> +
> + if (DISPLAY_VER(dev_priv) >= 10 && !IS_GEMINILAKE(dev_priv))
> + return true;
DISPLAY_VER >= 11
> +
> + if (port == PORT_A && intel_dp_is_edp(intel_dp))
The is_edp check is still wrong. Should be just port==A.
Also allows you to drop the intel_dp argument to the function.
> + return false;
> +
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
> + IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 9)
> + return true;
The IS_GLK check is redundant.
> +
> + return false;
> +}
> +
> static void
> intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector
> *connector)
> {
> @@ -4939,7 +4959,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp,
> struct drm_connector *connect
> intel_attach_dp_colorspace_property(connector);
> }
>
> - if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
> + if (has_gamut_metadata_dip(dev_priv, intel_dp, port))
> drm_object_attach_property(>base,
>
> connector->dev->mode_config.hdr_output_metadata_property,
> 0);
> --
> 2.25.1
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL
On Tue, Mar 22, 2022 at 02:46:15PM -0700, José Roberto de Souza wrote:
> PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being
> enabled but that could potentially cause issues as it could have
> mismatching values while pipes are being enabled.
>
> So here moving the PIPE_MBUS_DBOX_CTL programming of all pipes to be
> executed before the function that enables all pipes, leaving all pipes
> with a matching A_CREDIT value.
>
> While at it, also moving it to intel_pm.c as we are trying to reduce
> the gigantic size of it and intel_pm.c have other MBUS programing
> sequences.
>
> v2:
> - do not program PIPE_MBUS_DBOX_CTL if pipe will not be active or
> when it do not needs modeset
> - remove the checks to wait a vblank
>
> BSpec: 49213
> BSpec: 50343
> Cc: Ville Syrjälä
> Cc: Stanislav Lisovskiy
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 37 +--
> drivers/gpu/drm/i915/intel_pm.c | 47
> drivers/gpu/drm/i915/intel_pm.h | 1 +
> 3 files changed, 49 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 424cd7e9afe60..ef5076b5e7027 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1824,35 +1824,6 @@ static void glk_pipe_scaler_clock_gating_wa(struct
> drm_i915_private *dev_priv,
> intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
> }
>
> -static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
> -{
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - enum pipe pipe = crtc->pipe;
> - u32 val;
> -
> - val = intel_de_read(dev_priv, PIPE_MBUS_DBOX_CTL(pipe));
> - val &= ~MBUS_DBOX_A_CREDIT_MASK;
> - /* Wa_22010947358:adl-p */
> - if (IS_ALDERLAKE_P(dev_priv))
> - val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
> MBUS_DBOX_A_CREDIT(4);
> - else
> - val |= MBUS_DBOX_A_CREDIT(2);
> -
> - val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK);
> - if (IS_ALDERLAKE_P(dev_priv)) {
> - val |= MBUS_DBOX_BW_CREDIT(2);
> - val |= MBUS_DBOX_B_CREDIT(8);
> - } else if (DISPLAY_VER(dev_priv) >= 12) {
> - val |= MBUS_DBOX_BW_CREDIT(2);
> - val |= MBUS_DBOX_B_CREDIT(12);
> - } else {
> - val |= MBUS_DBOX_BW_CREDIT(1);
> - val |= MBUS_DBOX_B_CREDIT(8);
> - }
> -
> - intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
> -}
> -
> static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -1988,13 +1959,6 @@ static void hsw_crtc_enable(struct intel_atomic_state
> *state,
>
> intel_initial_watermarks(state, crtc);
>
> - if (DISPLAY_VER(dev_priv) >= 11) {
> - const struct intel_dbuf_state *dbuf_state =
> - intel_atomic_get_new_dbuf_state(state);
> -
> - icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus);
> - }
> -
> if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
> intel_crtc_vblank_on(new_crtc_state);
>
> @@ -8599,6 +8563,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> intel_encoders_update_prepare(state);
>
> intel_dbuf_pre_plane_update(state);
> + intel_mbus_dbox_update(state);
>
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> if (new_crtc_state->do_async_flip)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e60c02d760ffa..cf290bb704221 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8258,3 +8258,50 @@ void intel_dbuf_post_plane_update(struct
> intel_atomic_state *state)
> gen9_dbuf_slices_update(dev_priv,
> new_dbuf_state->enabled_slices);
> }
> +
> +void intel_mbus_dbox_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_crtc_state *new_crtc_state;
> + struct intel_dbuf_state *new_dbuf_state;
> + struct intel_crtc *crtc;
> + int i;
> +
> + if (DISPLAY_VER(i915) < 11 || !state->modeset)
> + return;
> +
> + if (HAS_MBUS_JOINING(i915))
> + new_dbuf_state = intel_atomic_get_dbuf_state(state);
> +
> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> + u32 val;
> +
> + if (!new_crtc_state->hw.active ||
> + !intel_crtc_needs_modeset(new_crtc_state))
> + continue;
> +
> + val = intel_de_read(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe));
> + val &= ~MBUS_DBOX_A_CREDIT_MASK;
> + /*
Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/display: Remove MBUS joining invalid TODOs
On Tue, Mar 22, 2022 at 02:46:16PM -0700, José Roberto de Souza wrote:
> skl_compute_ddb() will for a modeset in all pipes when MBUS joining
> changes between states, so all pipes will be disabled, have all
> MBUS related registers updated and then each pipe enabled.
> So no vblank syncronization is necessary and here droping those TODOs.
The TODO is about removing that modeset. So it should stay put.
>
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_pm.c | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index cf290bb704221..9ccf0f062862c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6066,7 +6066,6 @@ skl_compute_ddb(struct intel_atomic_state *state)
> return ret;
>
> if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus)
> {
> - /* TODO: Implement vblank synchronized MBUS joining
> changes */
> ret = intel_modeset_all_pipes(state);
> if (ret)
> return ret;
> @@ -8195,10 +8194,6 @@ static void update_mbus_pre_enable(struct
> intel_atomic_state *state)
> if (!HAS_MBUS_JOINING(dev_priv))
> return;
>
> - /*
> - * TODO: Implement vblank synchronized MBUS joining changes.
> - * Must be properly coordinated with dbuf reprogramming.
> - */
> if (dbuf_state->joined_mbus) {
> mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
> MBUS_JOIN_PIPE_SELECT_NONE;
> --
> 2.35.1
--
Ville Syrjälä
Intel
[Intel-gfx] [v3] drm/i915/display: Extend DP HDR support to hsw+
HSW+ platforms are able to send out HDR Metadata SDP DIP
packet as GMP. Hence, extending the support for HDR on DP
encoders for the same.
v2: Limited to non eDP ports on hsw/bdw and removed it for
lspcon as it is done separately (suggested by Ville)
v3: Added helper and limited eDP restriction to port A (Ville)
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5389
Cc: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9e19165fd175..c993d82c7ec9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4913,6 +4913,26 @@ bool intel_dp_is_port_edp(struct drm_i915_private
*dev_priv, enum port port)
return intel_bios_is_port_edp(dev_priv, port);
}
+static bool
+has_gamut_metadata_dip(struct drm_i915_private *dev_priv,
+ struct intel_dp *intel_dp, enum port port)
+{
+ if (intel_bios_is_lspcon_present(dev_priv, port))
+ return false;
+
+ if (DISPLAY_VER(dev_priv) >= 10 && !IS_GEMINILAKE(dev_priv))
+ return true;
+
+ if (port == PORT_A && intel_dp_is_edp(intel_dp))
+ return false;
+
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
+ IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 9)
+ return true;
+
+ return false;
+}
+
static void
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector
*connector)
{
@@ -4939,7 +4959,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct
drm_connector *connect
intel_attach_dp_colorspace_property(connector);
}
- if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
+ if (has_gamut_metadata_dip(dev_priv, intel_dp, port))
drm_object_attach_property(>base,
connector->dev->mode_config.hdr_output_metadata_property,
0);
--
2.25.1
Re: [Intel-gfx] [v2] drm/i915/display: Extend DP HDR support to hsw+
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, March 24, 2022 3:12 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v2] drm/i915/display: Extend DP HDR support to hsw+
>
> On Thu, Mar 24, 2022 at 02:42:15PM +0530, Uma Shankar wrote:
> > HSW+ platforms are able to send out HDR Metadata SDP DIP
> > packet as GMP. Hence, extending the support for HDR on DP encoders for
> > the same.
> >
> > v2: Limited to non eDP ports on hsw/bdw and removed it for lspcon as
> > it is done separately (suggested by Ville)
> >
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5389
> > Cc: Ville Syrjälä
> > Signed-off-by: Uma Shankar
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 10 ++
> > 1 file changed, 6 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 9e19165fd175..09382b6133bc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -4939,10 +4939,12 @@ intel_dp_add_properties(struct intel_dp *intel_dp,
> struct drm_connector *connect
> > intel_attach_dp_colorspace_property(connector);
> > }
> >
> > - if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
> > - drm_object_attach_property(>base,
> > - connector->dev-
> >mode_config.hdr_output_metadata_property,
> > - 0);
> > + if (!intel_bios_is_lspcon_present(dev_priv, port))
> > + if (((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
> > +!intel_dp_is_edp(intel_dp)) || DISPLAY_VER(dev_priv) >= 9)
>
> s/is_edp/port==A/
Yeah missed to limit only for port A, will fix it.
> I would put all of that into a helper (has_gamut_metadata_dip() or
> something) to make it actually legible.
Sure, will add a helper.
Regards,
Uma Shankar
>
> > + drm_object_attach_property(>base,
> > + connector->dev-
> >mode_config.hdr_output_metadata_property,
> > + 0);
> >
> > if (intel_dp_is_edp(intel_dp)) {
> > u32 allowed_scalers;
> > --
> > 2.25.1
>
> --
> Ville Syrjälä
> Intel
Re: [Intel-gfx] Commit messages (was: [PATCH v11] drm/amdgpu: add drm buddy support to amdgpu)
On Wed, 23 Mar 2022 at 16:32, Christian König wrote: > > Am 23.03.22 um 16:24 schrieb Daniel Stone: > > On Wed, 23 Mar 2022 at 15:14, Alex Deucher wrote: > >> On Wed, Mar 23, 2022 at 11:04 AM Daniel Stone wrote: > >>> That's not what anyone's saying here ... > >>> > >>> No-one's demanding AMD publish RTL, or internal design docs, or > >>> hardware specs, or URLs to JIRA tickets no-one can access. > >>> > >>> This is a large and invasive commit with pretty big ramifications; > >>> containing exactly two lines of commit message, one of which just > >>> duplicates the subject. > >>> > >>> It cannot be the case that it's completely impossible to provide any > >>> justification, background, or details, about this commit being made. > >>> Unless, of course, it's to fix a non-public security issue, that is > >>> reasonable justification for eliding some of the details. But then > >>> again, 'huge change which is very deliberately opaque' is a really > >>> good way to draw a lot of attention to the commit, and it would be > >>> better to provide more detail about the change to help it slip under > >>> the radar. > >>> > >>> If dri-devel@ isn't allowed to inquire about patches which are posted, > >>> then CCing the list is just a façade; might as well just do it all > >>> internally and periodically dump out pull requests. > >> I think we are in agreement. I think the withheld information > >> Christian was referring to was on another thread with Christian and > >> Paul discussing a workaround for a hardware bug: > >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.spinics.net%2Flists%2Famd-gfx%2Fmsg75908.htmldata=04%7C01%7Cchristian.koenig%40amd.com%7C6a3f2815d83b4872577008da0ce1347a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637836458652370599%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=QtNB0XHMhTgH%2FNHMwF23Qn%2BgSdYyHJSenbpP%2FHG%2BkxE%3Dreserved=0 > > Right, that definitely seems like some crossed wires. I don't see > > anything wrong with that commit at all: the commit message and a > > comment notes that there is a hardware issue preventing Raven from > > being able to do TMZ+GTT, and the code does the very straightforward > > and obvious thing to ensure that on VCN 1.0, any TMZ buffer must be > > VRAM-placed. > > > > This one, on the other hand, is much less clear ... > > Yes, completely agree. I mean a good bunch of comments on commit > messages are certainly valid and we could improve them. > > But this patch here was worked on by both AMD and Intel developers. > Where both sides and I think even people from other companies perfectly > understands why, what, how etc... > > When now somebody comes along and asks for a whole explanation of the > context why we do it then that sounds really strange to me. Yeah gpus are using pages a lot more like the cpu (with bigger pages of benefit, but not required, hence the buddy allocator to coalesce them), and extremely funny contig allocations with bonkers requirements aren't needed anymore (which was the speciality of drm_mm.c). Hence why both i915 and amdgpu move over to this new buddy allocator for managing vram. I guess that could be added to the commit message, but also it's kinda well known - the i915 patches also didn't explain why we want to manage our vram with a buddy allocator (I think some of the earlier versions explained it a bit, but the version with ttm integration that landed didnt). But yeah the confusing comments about hiding stuff that somehow spilled over from other discussions into this didn't help :-/ -Daniel > Thanks for jumping in here, > Christian. > > > > > Cheers, > > Daniel > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
Re: [Intel-gfx] [PATCH] drm/edid: fix CEA extension byte #3 parsing
On Wed, 23 Mar 2022, Ville Syrjälä wrote:
> On Wed, Mar 23, 2022 at 12:04:38PM +0200, Jani Nikula wrote:
>> Only an EDID CEA extension has byte #3, while the CTA DisplayID Data
>> Block does not. Don't interpret bogus data for color formats.
>
> I think what we might want eventually is a cleaner split between
> the CTA data blocks vs. the rest of the EDID CTA ext block. Only
> the former is relevant for DisplayID.
>
> But for a bugfix we want to keep it simple.
>
> Reviewed-by: Ville Syrjälä
Thanks, pushed to drm-misc-next-fixes.
BR,
Jani.
>
>>
>> For most displays it's probably an unlikely scenario you'd have a CTA
>> DisplayID Data Block without a CEA extension, but they do exist.
>>
>> Fixes: e28ad544f462 ("drm/edid: parse CEA blocks embedded in DisplayID")
>> Cc: # v4.15
>> Cc: Shawn C Lee
>> Cc: Ville Syrjälä
>> Signed-off-by: Jani Nikula
>>
>> ---
>>
>> commit e28ad544f462 was merged in v5.3, but it has Cc: stable for v4.15.
>>
>> This is also fixed in my CEA data block iteration series [1], but we'll
>> want the simple fix for stable first.
>>
>> Hum, CTA is formerly CEA, I and the code seem to use both, should we use
>> only one or the other?
>
> And before CEA it was called EIA (IIRC). Dunno if we also use that name
> somewhere.
>
> If someone cares enough I guess we could rename everything to "cta".
>
>>
>> [1] https://patchwork.freedesktop.org/series/101659/
>> ---
>> drivers/gpu/drm/drm_edid.c | 12
>> 1 file changed, 8 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>> index 561f53831e29..ccf7031a6797 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -5187,10 +5187,14 @@ static void drm_parse_cea_ext(struct drm_connector
>> *connector,
>>
>> /* The existence of a CEA block should imply RGB support */
>> info->color_formats = DRM_COLOR_FORMAT_RGB444;
>> -if (edid_ext[3] & EDID_CEA_YCRCB444)
>> -info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
>> -if (edid_ext[3] & EDID_CEA_YCRCB422)
>> -info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
>> +
>> +/* CTA DisplayID Data Block does not have byte #3 */
>> +if (edid_ext[0] == CEA_EXT) {
>> +if (edid_ext[3] & EDID_CEA_YCRCB444)
>> +info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
>> +if (edid_ext[3] & EDID_CEA_YCRCB422)
>> +info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
>> +}
>>
>> if (cea_db_offsets(edid_ext, , ))
>> return;
>> --
>> 2.30.2
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [v3] drm/edid: check basic audio support on CEA extension block
On Thu, 24 Mar 2022, Lee Shawn C wrote:
> From: Cooper Chiou
>
> Tag code stored in bit7:5 for CTA block byte[3] is not the same as
> CEA extension block definition. Only check CEA block has
> basic audio support.
>
> v3: update commit message.
>
> Cc: sta...@vger.kernel.org
> Cc: Jani Nikula
> Cc: Shawn C Lee
> Cc: intel-gfx
> Signed-off-by: Cooper Chiou
> Signed-off-by: Lee Shawn C
> Fixes: e28ad544f462 ("drm/edid: parse CEA blocks embedded in DisplayID")
> Reviewed-by: Jani Nikula
Thanks for the patch, pushed to drm-misc-next-fixes.
BR,
Jani.
> ---
> drivers/gpu/drm/drm_edid.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 561f53831e29..f07af6786cec 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4859,7 +4859,8 @@ bool drm_detect_monitor_audio(struct edid *edid)
> if (!edid_ext)
> goto end;
>
> - has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
> + has_audio = (edid_ext[0] == CEA_EXT &&
> + (edid_ext[3] & EDID_BASIC_AUDIO) != 0);
>
> if (has_audio) {
> DRM_DEBUG_KMS("Monitor has basic audio support\n");
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Extend DP HDR support to hsw+ (rev2)
== Series Details ==
Series: drm/i915/display: Extend DP HDR support to hsw+ (rev2)
URL : https://patchwork.freedesktop.org/series/101708/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11398 -> Patchwork_22669
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/index.html
Participating hosts (46 -> 42)
--
Additional (5): bat-dg2-8 bat-dg2-9 fi-kbl-8809g bat-rpls-1 bat-jsl-1
Missing(9): shard-tglu fi-hsw-4200u bat-adlm-1 fi-bsw-cyan fi-ctg-p8600
fi-pnv-d510 shard-rkl shard-dg1 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22669:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@hugepages:
- {bat-rpls-2}: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/bat-rpls-2/igt@i915_selftest@l...@hugepages.html
- {fi-jsl-1}: [PASS][2] -> [DMESG-FAIL][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/fi-jsl-1/igt@i915_selftest@l...@hugepages.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/fi-jsl-1/igt@i915_selftest@l...@hugepages.html
Known issues
Here are the changes found in Patchwork_22669 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_exec_suspend@basic-s0@smem:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][5] ([i915#4962]) +1 similar
issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/fi-kbl-8809g/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/fi-kbl-8809g/igt@gem_lmem_swapp...@random-engines.html
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-8809g: NOTRUN -> [SKIP][8] ([fdo#109271]) +54 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/fi-kbl-8809g/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: [PASS][9] -> [INCOMPLETE][10] ([i915#2373])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-8809g: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-cfl-8109u: [PASS][12] -> [DMESG-WARN][13] ([i915#295])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/fi-cfl-8109u/igt@kms_force_connector_ba...@prune-stale-modes.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/fi-cfl-8109u/igt@kms_force_connector_ba...@prune-stale-modes.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-kbl-8809g: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#5341])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-8809g: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#533])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
Possible fixes
* igt@i915_selftest@live@gt_timelines:
- {bat-rpls-2}: [DMESG-WARN][16] ([i915#4391]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/bat-rpls-2/igt@i915_selftest@live@gt_timelines.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22669/bat-rpls-2/igt@i915_selftest@live@gt_timelines.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][18] ([i915#3921]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[19]:
Re: [Intel-gfx] [v2] drm/i915/display: Extend DP HDR support to hsw+
On Thu, Mar 24, 2022 at 02:42:15PM +0530, Uma Shankar wrote:
> HSW+ platforms are able to send out HDR Metadata SDP DIP
> packet as GMP. Hence, extending the support for HDR on DP
> encoders for the same.
>
> v2: Limited to non eDP ports on hsw/bdw and removed it for
> lspcon as it is done separately (suggested by Ville)
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5389
> Cc: Ville Syrjälä
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9e19165fd175..09382b6133bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4939,10 +4939,12 @@ intel_dp_add_properties(struct intel_dp *intel_dp,
> struct drm_connector *connect
> intel_attach_dp_colorspace_property(connector);
> }
>
> - if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
> - drm_object_attach_property(>base,
> -
> connector->dev->mode_config.hdr_output_metadata_property,
> -0);
> + if (!intel_bios_is_lspcon_present(dev_priv, port))
> + if (((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
> + !intel_dp_is_edp(intel_dp)) || DISPLAY_VER(dev_priv) >= 9)
s/is_edp/port==A/
I would put all of that into a helper (has_gamut_metadata_dip() or
something) to make it actually legible.
> + drm_object_attach_property(>base,
> +
> connector->dev->mode_config.hdr_output_metadata_property,
> + 0);
>
> if (intel_dp_is_edp(intel_dp)) {
> u32 allowed_scalers;
> --
> 2.25.1
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH] drm/i915/guc: Correctly free guc capture struct on error
Reviewed-by: Nirmoy Das
On 3/24/2022 1:04 AM, Daniele Ceraolo Spurio wrote:
On error the "new" allocation is not freed, so add the required kfree.
Fixes: 247f8071d5893 ("drm/i915/guc: Pre-allocate output nodes for extraction")
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index afdcbe63e9eb1..c4e25966d3e9f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -1040,6 +1040,7 @@ guc_capture_alloc_one_node(struct intel_guc *guc)
if (!new->reginfo[i].regs) {
while (i)
kfree(new->reginfo[--i].regs);
+ kfree(new);
return NULL;
}
}
Re: [Intel-gfx] [RFC] drm/i915: Split out intel_vtd_active and run_as_guest to own header
On Thu, 24 Mar 2022, Jani Nikula wrote:
> On Tue, 22 Mar 2022, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin
>>
>> ...
>>
>> Signed-off-by: Tvrtko Ursulin
>> Cc: Jani Nikula
>> Cc: Lucas De Marchi
>> ---
>> Typed up how I see it - bash away.
>
> So is intel_vtd_active() so performance critical that it needs to be
> inline?
>
> We're passing struct drm_i915_private * everywhere we can, and it just
> feels silly to use struct drm_device * to avoid the include.
>
> Static inlines considered harmful. :p
Otherwise,
Acked-by: Jani Nikula
>
>
> BR,
> Jani.
>
>
>> ---
>> drivers/gpu/drm/i915/display/intel_bw.c | 3 +-
>> drivers/gpu/drm/i915/display/intel_display.c | 9 -
>> drivers/gpu/drm/i915/display/intel_display.h | 2 ++
>> drivers/gpu/drm/i915/display/intel_fbc.c | 3 +-
>> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 3 +-
>> drivers/gpu/drm/i915/gem/i915_gemfs.c| 3 +-
>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 5 +--
>> drivers/gpu/drm/i915/gt/intel_gtt.c | 12 +++
>> drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++
>> drivers/gpu/drm/i915/i915_debugfs.c | 1 +
>> drivers/gpu/drm/i915/i915_driver.c | 3 +-
>> drivers/gpu/drm/i915/i915_driver.h | 4 +++
>> drivers/gpu/drm/i915/i915_drv.h | 37
>> drivers/gpu/drm/i915/i915_gpu_error.c| 3 +-
>> drivers/gpu/drm/i915/intel_device_info.c | 4 ++-
>> drivers/gpu/drm/i915/intel_pch.c | 3 +-
>> drivers/gpu/drm/i915/intel_vtd.h | 27 ++
>> 17 files changed, 76 insertions(+), 48 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/intel_vtd.h
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
>> b/drivers/gpu/drm/i915/display/intel_bw.c
>> index ac11ff19e47d..6c9cb4f97218 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>> @@ -13,6 +13,7 @@
>> #include "intel_mchbar_regs.h"
>> #include "intel_pcode.h"
>> #include "intel_pm.h"
>> +#include "intel_vtd.h"
>>
>> /* Parameters for Qclk Geyserville (QGV) */
>> struct intel_qgv_point {
>> @@ -649,7 +650,7 @@ static unsigned int intel_bw_data_rate(struct
>> drm_i915_private *dev_priv,
>> for_each_pipe(dev_priv, pipe)
>> data_rate += bw_state->data_rate[pipe];
>>
>> -if (DISPLAY_VER(dev_priv) >= 13 && intel_vtd_active(dev_priv))
>> +if (DISPLAY_VER(dev_priv) >= 13 && intel_vtd_active(dev_priv->drm.dev))
>> data_rate = DIV_ROUND_UP(data_rate * 105, 100);
>>
>> return data_rate;
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index dc6e21e4ef0b..e80f3ca3ee4e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -110,6 +110,7 @@
>> #include "intel_quirks.h"
>> #include "intel_sprite.h"
>> #include "intel_tc.h"
>> +#include "intel_vtd.h"
>> #include "intel_vga.h"
>> #include "i9xx_plane.h"
>> #include "skl_scaler.h"
>> @@ -1197,7 +1198,7 @@ static bool needs_async_flip_vtd_wa(const struct
>> intel_crtc_state *crtc_state)
>> {
>> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>>
>> -return crtc_state->uapi.async_flip && intel_vtd_active(i915) &&
>> +return crtc_state->uapi.async_flip && intel_vtd_active(i915->drm.dev) &&
>> (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) ||
>> IS_HASWELL(i915));
>> }
>>
>> @@ -10699,3 +10700,9 @@ void intel_display_driver_unregister(struct
>> drm_i915_private *i915)
>> acpi_video_unregister();
>> intel_opregion_unregister(i915);
>> }
>> +
>> +bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
>> +{
>> +return DISPLAY_VER(dev_priv) >= 6 &&
>> + intel_vtd_active(dev_priv->drm.dev);
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
>> b/drivers/gpu/drm/i915/display/intel_display.h
>> index 8513703086b7..d69587c76e71 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display.h
>> @@ -694,4 +694,6 @@ void assert_transcoder(struct drm_i915_private *dev_priv,
>> #define I915_STATE_WARN_ON(x)
>> \
>> I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
>>
>> +bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv);
>> +
>> #endif
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
>> b/drivers/gpu/drm/i915/display/intel_fbc.c
>> index 142280b6ce6d..00a3e30587a5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>> @@ -50,6 +50,7 @@
>> #include "intel_display_types.h"
>> #include "intel_fbc.h"
>> #include "intel_frontbuffer.h"
>> +#include "intel_vtd.h"
>>
>> #define for_each_fbc_id(__dev_priv, __fbc_id) \
>> for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) <
Re: [Intel-gfx] [RFC] drm/i915: Split out intel_vtd_active and run_as_guest to own header
On Tue, 22 Mar 2022, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> ...
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Jani Nikula
> Cc: Lucas De Marchi
> ---
> Typed up how I see it - bash away.
So is intel_vtd_active() so performance critical that it needs to be
inline?
We're passing struct drm_i915_private * everywhere we can, and it just
feels silly to use struct drm_device * to avoid the include.
Static inlines considered harmful. :p
BR,
Jani.
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 3 +-
> drivers/gpu/drm/i915/display/intel_display.c | 9 -
> drivers/gpu/drm/i915/display/intel_display.h | 2 ++
> drivers/gpu/drm/i915/display/intel_fbc.c | 3 +-
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 3 +-
> drivers/gpu/drm/i915/gem/i915_gemfs.c| 3 +-
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 5 +--
> drivers/gpu/drm/i915/gt/intel_gtt.c | 12 +++
> drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++
> drivers/gpu/drm/i915/i915_debugfs.c | 1 +
> drivers/gpu/drm/i915/i915_driver.c | 3 +-
> drivers/gpu/drm/i915/i915_driver.h | 4 +++
> drivers/gpu/drm/i915/i915_drv.h | 37
> drivers/gpu/drm/i915/i915_gpu_error.c| 3 +-
> drivers/gpu/drm/i915/intel_device_info.c | 4 ++-
> drivers/gpu/drm/i915/intel_pch.c | 3 +-
> drivers/gpu/drm/i915/intel_vtd.h | 27 ++
> 17 files changed, 76 insertions(+), 48 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_vtd.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index ac11ff19e47d..6c9cb4f97218 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -13,6 +13,7 @@
> #include "intel_mchbar_regs.h"
> #include "intel_pcode.h"
> #include "intel_pm.h"
> +#include "intel_vtd.h"
>
> /* Parameters for Qclk Geyserville (QGV) */
> struct intel_qgv_point {
> @@ -649,7 +650,7 @@ static unsigned int intel_bw_data_rate(struct
> drm_i915_private *dev_priv,
> for_each_pipe(dev_priv, pipe)
> data_rate += bw_state->data_rate[pipe];
>
> - if (DISPLAY_VER(dev_priv) >= 13 && intel_vtd_active(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 13 && intel_vtd_active(dev_priv->drm.dev))
> data_rate = DIV_ROUND_UP(data_rate * 105, 100);
>
> return data_rate;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index dc6e21e4ef0b..e80f3ca3ee4e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -110,6 +110,7 @@
> #include "intel_quirks.h"
> #include "intel_sprite.h"
> #include "intel_tc.h"
> +#include "intel_vtd.h"
> #include "intel_vga.h"
> #include "i9xx_plane.h"
> #include "skl_scaler.h"
> @@ -1197,7 +1198,7 @@ static bool needs_async_flip_vtd_wa(const struct
> intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>
> - return crtc_state->uapi.async_flip && intel_vtd_active(i915) &&
> + return crtc_state->uapi.async_flip && intel_vtd_active(i915->drm.dev) &&
> (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) ||
> IS_HASWELL(i915));
> }
>
> @@ -10699,3 +10700,9 @@ void intel_display_driver_unregister(struct
> drm_i915_private *i915)
> acpi_video_unregister();
> intel_opregion_unregister(i915);
> }
> +
> +bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
> +{
> + return DISPLAY_VER(dev_priv) >= 6 &&
> +intel_vtd_active(dev_priv->drm.dev);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 8513703086b7..d69587c76e71 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -694,4 +694,6 @@ void assert_transcoder(struct drm_i915_private *dev_priv,
> #define I915_STATE_WARN_ON(x)
> \
> I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
>
> +bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv);
> +
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 142280b6ce6d..00a3e30587a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -50,6 +50,7 @@
> #include "intel_display_types.h"
> #include "intel_fbc.h"
> #include "intel_frontbuffer.h"
> +#include "intel_vtd.h"
>
> #define for_each_fbc_id(__dev_priv, __fbc_id) \
> for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS;
> (__fbc_id)++) \
> @@ -1643,7 +1644,7 @@ static int intel_sanitize_fbc_option(struct
> drm_i915_private *i915)
> static bool need_fbc_vtd_wa(struct drm_i915_private *i915)
> {
>
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/display: Extend DP HDR support to hsw+ (rev2)
== Series Details == Series: drm/i915/display: Extend DP HDR support to hsw+ (rev2) URL : https://patchwork.freedesktop.org/series/101708/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Extend DP HDR support to hsw+ (rev2)
== Series Details == Series: drm/i915/display: Extend DP HDR support to hsw+ (rev2) URL : https://patchwork.freedesktop.org/series/101708/ State : warning == Summary == $ dim checkpatch origin/drm-tip a2f43ef1952e drm/i915/display: Extend DP HDR support to hsw+ -:36: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #36: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4946: + drm_object_attach_property(>base, + connector->dev->mode_config.hdr_output_metadata_property, total: 0 errors, 0 warnings, 1 checks, 16 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsb: modified to drm_info in dsb_prepare()
== Series Details ==
Series: drm/i915/dsb: modified to drm_info in dsb_prepare()
URL : https://patchwork.freedesktop.org/series/101723/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11398 -> Patchwork_22668
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/index.html
Participating hosts (46 -> 45)
--
Additional (6): bat-adls-5 bat-dg2-8 bat-dg2-9 fi-kbl-8809g bat-rpls-1
bat-jsl-1
Missing(7): shard-tglu fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 shard-rkl
shard-dg1 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22668:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@migrate:
- {bat-rpls-2}: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/bat-rpls-2/igt@i915_selftest@l...@migrate.html
* igt@runner@aborted:
- {bat-adlm-1}: NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/bat-adlm-1/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_22668 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_exec_suspend@basic-s0@smem:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][4] ([i915#4962]) +1 similar
issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/fi-kbl-8809g/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/fi-kbl-8809g/igt@gem_lmem_swapp...@random-engines.html
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-8809g: NOTRUN -> [SKIP][7] ([fdo#109271]) +54 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/fi-kbl-8809g/igt@i915_pm_...@basic-rte.html
* igt@i915_pm_rpm@module-reload:
- fi-bsw-n3050: [PASS][8] -> [DMESG-WARN][9] ([i915#1982])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/fi-bsw-n3050/igt@i915_pm_...@module-reload.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/fi-bsw-n3050/igt@i915_pm_...@module-reload.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-8809g: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-kbl-8809g: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#5341])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-8809g: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
Possible fixes
* igt@i915_selftest@live@gt_timelines:
- {bat-rpls-2}: [DMESG-WARN][13] ([i915#4391]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/bat-rpls-2/igt@i915_selftest@live@gt_timelines.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/bat-rpls-2/igt@i915_selftest@live@gt_timelines.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][15] ([i915#4494] / [i915#4957]) ->
[PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-snb-2600:[INCOMPLETE][17] ([i915#3921]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22668/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@kms_busy@basic@modeset:
- {bat-adlp-6}: [DMESG-WARN][19] ([i915#3576]) -> [PASS][20]
[19]:
Re: [Intel-gfx] [PATCH] drm/i915/display: Extend DP HDR support to hsw+
> -Original Message- > From: Ville Syrjälä > Sent: Thursday, March 24, 2022 12:49 AM > To: Shankar, Uma > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Extend DP HDR support to > hsw+ > > On Wed, Mar 23, 2022 at 09:04:36PM +0200, Ville Syrjälä wrote: > > On Thu, Mar 24, 2022 at 12:15:22AM +0530, Uma Shankar wrote: > > > HSW+ platforms are able to send out HDR Metadata SDP DIP > > > packet as GMP. Hence, extending the support for HDR on DP encoders > > > for the same. > > > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5389 > > > Cc: Ville Syrjälä > > > Signed-off-by: Uma Shankar > > > --- > > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > index 9e19165fd175..e10d2c151abf 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > @@ -4939,7 +4939,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, > struct drm_connector *connect > > > intel_attach_dp_colorspace_property(connector); > > > } > > > > > > - if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11) > > > + if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) > > > > CHV does not have this at all, and HSW/BDW don't have it on transcoder EDP. > > Actually vlv/chv might have it since the vlv video DIP was supposedly ripped > from ibx. > So potentially we could just enable this for all ilk+. > But that would require actual testing, so hsw+ seems like good enough for now. Sure, will update this. > > > > Also if we're going to attach this unconditionally then we should stop > > attaching it again in the LSPCON init path. Or we should skip this one > > when LSPCON is present. Ok, have taken care of it and sent out the next version. Thanks Ville for the feedback. Regards, Uma Shankar > > > > > drm_object_attach_property(>base, > > > connector->dev- > >mode_config.hdr_output_metadata_property, > > > 0); > > > -- > > > 2.25.1 > > > > -- > > Ville Syrjälä > > Intel > > -- > Ville Syrjälä > Intel
[Intel-gfx] [v2] drm/i915/display: Extend DP HDR support to hsw+
HSW+ platforms are able to send out HDR Metadata SDP DIP
packet as GMP. Hence, extending the support for HDR on DP
encoders for the same.
v2: Limited to non eDP ports on hsw/bdw and removed it for
lspcon as it is done separately (suggested by Ville)
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5389
Cc: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9e19165fd175..09382b6133bc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4939,10 +4939,12 @@ intel_dp_add_properties(struct intel_dp *intel_dp,
struct drm_connector *connect
intel_attach_dp_colorspace_property(connector);
}
- if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
- drm_object_attach_property(>base,
-
connector->dev->mode_config.hdr_output_metadata_property,
- 0);
+ if (!intel_bios_is_lspcon_present(dev_priv, port))
+ if (((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
+!intel_dp_is_edp(intel_dp)) || DISPLAY_VER(dev_priv) >= 9)
+ drm_object_attach_property(>base,
+
connector->dev->mode_config.hdr_output_metadata_property,
+ 0);
if (intel_dp_is_edp(intel_dp)) {
u32 allowed_scalers;
--
2.25.1
Re: [Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in dsb_prepare()
On 3/24/2022 8:43 AM, Animesh Manna wrote:
The request to aqquire gem resources is failing for DSB in rare
scenario where it is busy and the register programming will be done
through mmio fallback path.
DSB has extra advantage of faster register programming which may
go away through mmio path. Adding wait for gem resource also may
not be right as anyways losing time.
To make the CI execution happy replaced drm_dbg_kms() to drm_info()
for printing debuf info during dsb buffer preparation.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index b34a67309976..b68dd7bd5271 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -275,7 +275,7 @@ void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
dsb = kmalloc(sizeof(*dsb), GFP_KERNEL);
if (!dsb) {
- drm_err(>drm, "DSB object creation failed\n");
+ drm_info(>drm, "DSB object creation failed\n");
return;
}
@@ -283,14 +283,14 @@ void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
if (IS_ERR(obj)) {
- drm_err(>drm, "Gem object creation failed\n");
+ drm_info(>drm, "Gem object creation failed\n");
If CI is happy with drm_warn then it makes sense to use drm_warn.
kfree(dsb);
goto out;
}
vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
if (IS_ERR(vma)) {
- drm_err(>drm, "Vma creation failed\n");
+ drm_info(>drm, "Vma creation failed\n");
These messages are bit vague, add "DSB VMA creation failed" or something
similar.
With that Acked-by: Nirmoy Das
Nirmoy
i915_gem_object_put(obj);
kfree(dsb);
goto out;
@@ -298,7 +298,7 @@ void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
buf = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WC);
if (IS_ERR(buf)) {
- drm_err(>drm, "Command buffer creation failed\n");
+ drm_info(>drm, "Command buffer creation failed\n");
i915_vma_unpin_and_release(, I915_VMA_RELEASE_MAP);
kfree(dsb);
goto out;
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dsb: modified to drm_info in dsb_prepare()
== Series Details == Series: drm/i915/dsb: modified to drm_info in dsb_prepare() URL : https://patchwork.freedesktop.org/series/101723/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsb: modified to drm_info in dsb_prepare()
== Series Details ==
Series: drm/i915/dsb: modified to drm_info in dsb_prepare()
URL : https://patchwork.freedesktop.org/series/101723/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d7c0e5b3bf10 drm/i915/dsb: modified to drm_info in dsb_prepare()
-:28: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#28: FILE: drivers/gpu/drm/i915/display/intel_dsb.c:278:
if (!dsb) {
+ drm_info(>drm, "DSB object creation failed\n");
total: 0 errors, 1 warnings, 0 checks, 32 lines checked
[Intel-gfx] [PULL] drm-intel-next-fixes
Hi Dave, Daniel, A few fixes for the merge window. Apart from a uninteresting rename of a field in an unused macro, the rest are display fixes - two for SAGV and one for TDMS rate calculation on Icelake and above. Regards, Tvrtko drm-intel-next-fixes-2022-03-24: - Reject unsupported TMDS rates on ICL+ (Ville Syrjälä) - Treat SAGV block time 0 as SAGV disabled (Ville Syrjälä) - Fix PSF GV point mask when SAGV is not possible (Ville Syrjälä) - Fix renamed INTEL_INFO->media.arch/ver field (Lucas De Marchi) The following changes since commit 278da06c03655c2bb9bc36ebdf45b90a079b3bfd: drm/i915/display: Do not re-enable PSR after it was marked as not reliable (2022-03-16 08:17:40 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-fixes-2022-03-24 for you to fetch changes up to 00f4150d27d2c01eaeffe1091fc311a7c0872c69: drm/i915: Fix renamed struct field (2022-03-21 11:48:00 +) - Reject unsupported TMDS rates on ICL+ (Ville Syrjälä) - Treat SAGV block time 0 as SAGV disabled (Ville Syrjälä) - Fix PSF GV point mask when SAGV is not possible (Ville Syrjälä) - Fix renamed INTEL_INFO->media.arch/ver field (Lucas De Marchi) Lucas De Marchi (1): drm/i915: Fix renamed struct field Ville Syrjälä (3): drm/i915: Reject unsupported TMDS rates on ICL+ drm/i915: Treat SAGV block time 0 as SAGV disabled drm/i915: Fix PSF GV point mask when SAGV is not possible drivers/gpu/drm/i915/display/intel_bw.c | 3 ++- drivers/gpu/drm/i915/display/intel_hdmi.c | 9 + drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 10 ++ 4 files changed, 18 insertions(+), 6 deletions(-)
Re: [Intel-gfx] [PATCH 1/1] drm/i915: Handle the DG2 max bw properly
> }
>
> +static unsigned int dg2_max_bw(struct drm_i915_private *i915) {
> + struct intel_bw_info *bi = >max_bw[0];
> +
> + return bi->deratedbw[0];
> +}
Would it look better to have this as a macro rather than a function?
Thanks and Regards,
Arun R Murthy
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/dg2: Add relocation exception" (rev2)
On Wed, Mar 23, 2022 at 06:51:17PM +, Patchwork wrote:
>Patch Details
>
>Series: Revert "drm/i915/dg2: Add relocation exception" (rev2)
>
>URL: https://patchwork.freedesktop.org/series/101669/
>
>State: failure
>
>Details:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22660/index.html
>
>CI Bug Log - changes from CI_DRM_11398 -> Patchwork_22660
>
> Summary
>
>FAILURE
>
>Serious unknown changes coming with Patchwork_22660 absolutely need to be
>verified manually.
>
>If you think the reported changes have nothing to do with the changes
>introduced in Patchwork_22660, please notify your bug team to allow them
>to document this new failure mode, which will reduce false positives in
>CI.
>
>External URL:
>https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22660/index.html
>
> Participating hosts (45 -> 42)
>
>Additional (5): bat-dg2-8 bat-dg2-9 fi-kbl-8809g bat-rpls-1 bat-jsl-1
>Missing (8): fi-kbl-soraka shard-tglu fi-hsw-4200u bat-adlm-1 fi-bsw-cyan
>fi-ctg-p8600 shard-rkl fi-bdw-samus
>
> Possible new issues
>
>Here are the unknown changes that may have been introduced in
>Patchwork_22660:
>
> IGT changes
>
> Possible regressions
>
> * igt@i915_selftest@live@hangcheck:
> * fi-hsw-4770: PASS -> INCOMPLETE
Unrelated to the change.
>
> Suppressed
>
>The following results come from untrusted machines, tests, or statuses.
>They do not affect the overall result.
>
> * igt@gem_busy@busy@all:
>
> * {bat-dg2-8}: NOTRUN -> INCOMPLETE
> * igt@gem_exec_gttfill@basic:
>
> * {bat-dg2-9}: NOTRUN -> SKIP
> * igt@gem_exec_suspend@basic-s0@smem:
>
> * {bat-dg2-9}: NOTRUN -> FAIL +7 similar issues
For this one I got success on no-reloc code:
./gem_exec_suspend --run basic-S0
IGT-Version: 1.26-NO-GIT (x86_64) (Linux: 5.17.0+ x86_64)
Starting subtest: basic-S0
Starting dynamic subtest: smem
[cmd] rtcwake: assuming RTC uses UTC ...
rtcwake: wakeup from "freeze" using /dev/rtc0 at Thu Mar 24 07:56:03 2022
Dynamic subtest smem: SUCCESS (2.817s)
Starting dynamic subtest: lmem0
[cmd] rtcwake: assuming RTC uses UTC ...
rtcwake: wakeup from "freeze" using /dev/rtc0 at Thu Mar 24 07:56:20 2022
Dynamic subtest lmem0: SUCCESS (3.184s)
Subtest basic-S0: SUCCESS (6.001s)
@Lucas - please consider reverting relocations for dg2. This will speed
up our work and I've fixed yesterday all potential problems with no-reloc
for BAT on dg2.
--
Zbigniew
>
> Known issues
>
>Here are the changes found in Patchwork_22660 that come from known issues:
>
> IGT changes
>
> Issues hit
>
> * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
>
> * fi-snb-2600: NOTRUN -> SKIP (fdo#109271) +17 similar issues
> * igt@gem_exec_suspend@basic-s0@smem:
>
> * fi-kbl-8809g: NOTRUN -> DMESG-WARN (i915#4962) +1 similar issue
> * igt@gem_huc_copy@huc-copy:
>
> * fi-kbl-8809g: NOTRUN -> SKIP (fdo#109271 / i915#2190)
> * igt@gem_lmem_swapping@random-engines:
>
> * fi-kbl-8809g: NOTRUN -> SKIP (fdo#109271 / i915#4613) +3 similar
> issues
> * igt@i915_pm_rpm@basic-rte:
>
> * fi-kbl-8809g: NOTRUN -> SKIP (fdo#109271) +54 similar issues
> * igt@i915_selftest@live@gt_engines:
>
> * bat-dg1-6: PASS -> INCOMPLETE (i915#4418)
> * igt@kms_chamelium@hdmi-edid-read:
>
> * fi-kbl-8809g: NOTRUN -> SKIP (fdo#109271 / fdo#111827) +8 similar
> issues
> * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
>
> * fi-kbl-8809g: NOTRUN -> SKIP (fdo#109271 / i915#5341)
> * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
>
> * fi-kbl-8809g: NOTRUN -> SKIP (fdo#109271 / i915#533)
> * igt@runner@aborted:
>
> * fi-hsw-4770: NOTRUN -> FAIL (fdo#109271 / i915#1436 / i915#2722 /
> i915#4312)
>
> * bat-dg1-6: NOTRUN -> FAIL (i915#4312 / i915#5257)
>
> Possible fixes
>
> * igt@i915_selftest@live@gt_timelines:
>
> * {bat-rpls-2}: DMESG-WARN (i915#4391) -> PASS
> * igt@i915_selftest@live@hangcheck:
>
> * fi-snb-2600: INCOMPLETE (i915#3921) -> PASS
> * igt@kms_busy@basic@modeset:
>
> * {bat-adlp-6}: DMESG-WARN (i915#3576) -> PASS
> * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
>
> * fi-cfl-8109u: DMESG-WARN (i915#295 / i915#5341) -> PASS
> * igt@kms_pipe_crc_basic@read-crc-pipe-b:
>
> * fi-cfl-8109u: DMESG-WARN (i915#295) -> PASS +10 similar issues
>
> Warnings
>
> * igt@runner@aborted:
> * fi-apl-guc: FAIL (i915#2426 / i915#4312) -> FAIL (i915#4312)
>
>{name}: This element is suppressed. This means it is ignored when
>computing
>the status of the
[Intel-gfx] [PULL] drm-misc-fixes
Hi Dave and Daniel, here's the weekly PR for drm-misc-fixes. Best regards Thomas drm-misc-fixes-2022-03-24: * drm/panel/ili9341: Fix optional regulator handling The following changes since commit 3c3384050d68570f9de0fec9e58824decfefba7a: drm: Don't make DRM_PANEL_BRIDGE dependent on DRM_KMS_HELPERS (2022-03-17 11:07:57 +0100) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2022-03-24 for you to fetch changes up to d14eb80e27795b7b20060f7b151cdfe39722a813: drm/panel: ili9341: fix optional regulator handling (2022-03-18 11:08:42 +0100) * drm/panel/ili9341: Fix optional regulator handling Daniel Mack (1): drm/panel: ili9341: fix optional regulator handling drivers/gpu/drm/panel/panel-ilitek-ili9341.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Felix Imendörffer
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/edid: filter DisplayID v2.0 CTA block in audio detection (rev4)
== Series Details == Series: drm/edid: filter DisplayID v2.0 CTA block in audio detection (rev4) URL : https://patchwork.freedesktop.org/series/101565/ State : success == Summary == CI Bug Log - changes from CI_DRM_11398_full -> Patchwork_22667_full Summary --- **SUCCESS** No regressions found. Participating hosts (12 -> 12) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22667_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][1] -> [FAIL][2] ([i915#2842]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-glk2/igt@gem_exec_fair@basic-n...@vecs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/shard-glk3/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-apl2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/shard-apl6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-kbl7/igt@gem_exec_fair@basic-p...@vecs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/shard-kbl1/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2849]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_schedule@noreorder-corked@rcs0: - shard-iclb: [PASS][11] -> [DMESG-WARN][12] ([i915#4391]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/shard-iclb7/igt@gem_exec_schedule@noreorder-cor...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/shard-iclb7/igt@gem_exec_schedule@noreorder-cor...@rcs0.html * igt@gem_lmem_swapping@heavy-random: - shard-tglb: NOTRUN -> [SKIP][13] ([i915#4613]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/shard-tglb1/igt@gem_lmem_swapp...@heavy-random.html * igt@gem_lmem_swapping@parallel-random-engines: - shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/shard-apl2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_pwrite@basic-exhaustion: - shard-skl: NOTRUN -> [WARN][15] ([i915#2658]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/shard-skl10/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@fail-invalid-protected-context: - shard-tglb: NOTRUN -> [SKIP][16] ([i915#4270]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/shard-tglb7/igt@gem_...@fail-invalid-protected-context.html * igt@gem_pxp@verify-pxp-stale-buf-optout-execution: - shard-iclb: NOTRUN -> [SKIP][17] ([i915#4270]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/shard-iclb7/igt@gem_...@verify-pxp-stale-buf-optout-execution.html * igt@gem_render_copy@y-tiled-to-vebox-y-tiled: - shard-iclb: NOTRUN -> [SKIP][18] ([i915#768]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/shard-iclb7/igt@gem_render_c...@y-tiled-to-vebox-y-tiled.html * igt@gem_userptr_blits@vma-merge: - shard-snb: NOTRUN -> [FAIL][19] ([i915#2724]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/shard-snb4/igt@gem_userptr_bl...@vma-merge.html * igt@gen9_exec_parse@allowed-single: - shard-iclb: NOTRUN -> [SKIP][20] ([i915#2856]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/shard-iclb7/igt@gen9_exec_pa...@allowed-single.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp: - shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#1937]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/shard-apl2/igt@i915_pm_lpsp@kms-l...@kms-lpsp-dp.html * igt@i915_pm_rc6_residency@media-rc6-accuracy: - shard-iclb: NOTRUN -> [SKIP][22] ([fdo#109289]) [22]:
[Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in dsb_prepare()
The request to aqquire gem resources is failing for DSB in rare
scenario where it is busy and the register programming will be done
through mmio fallback path.
DSB has extra advantage of faster register programming which may
go away through mmio path. Adding wait for gem resource also may
not be right as anyways losing time.
To make the CI execution happy replaced drm_dbg_kms() to drm_info()
for printing debuf info during dsb buffer preparation.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index b34a67309976..b68dd7bd5271 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -275,7 +275,7 @@ void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
dsb = kmalloc(sizeof(*dsb), GFP_KERNEL);
if (!dsb) {
- drm_err(>drm, "DSB object creation failed\n");
+ drm_info(>drm, "DSB object creation failed\n");
return;
}
@@ -283,14 +283,14 @@ void intel_dsb_prepare(struct intel_crtc_state
*crtc_state)
obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
if (IS_ERR(obj)) {
- drm_err(>drm, "Gem object creation failed\n");
+ drm_info(>drm, "Gem object creation failed\n");
kfree(dsb);
goto out;
}
vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
if (IS_ERR(vma)) {
- drm_err(>drm, "Vma creation failed\n");
+ drm_info(>drm, "Vma creation failed\n");
i915_gem_object_put(obj);
kfree(dsb);
goto out;
@@ -298,7 +298,7 @@ void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
buf = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WC);
if (IS_ERR(buf)) {
- drm_err(>drm, "Command buffer creation failed\n");
+ drm_info(>drm, "Command buffer creation failed\n");
i915_vma_unpin_and_release(, I915_VMA_RELEASE_MAP);
kfree(dsb);
goto out;
--
2.29.0
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: filter DisplayID v2.0 CTA block in audio detection (rev4)
== Series Details ==
Series: drm/edid: filter DisplayID v2.0 CTA block in audio detection (rev4)
URL : https://patchwork.freedesktop.org/series/101565/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11398 -> Patchwork_22667
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/index.html
Participating hosts (46 -> 42)
--
Additional (5): bat-dg2-8 bat-dg2-9 fi-kbl-8809g bat-rpls-1 bat-jsl-1
Missing(9): shard-tglu fi-hsw-4200u bat-adlm-1 fi-bsw-cyan fi-ctg-p8600
fi-bsw-kefka shard-rkl shard-dg1 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22667 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_exec_suspend@basic-s0@smem:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][2] ([i915#4962]) +1 similar
issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/fi-kbl-8809g/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/fi-kbl-8809g/igt@gem_lmem_swapp...@random-engines.html
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-8809g: NOTRUN -> [SKIP][5] ([fdo#109271]) +54 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/fi-kbl-8809g/igt@i915_pm_...@basic-rte.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-8809g: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-kbl-8809g: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#5341])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-8809g: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
Possible fixes
* igt@i915_selftest@live@gt_timelines:
- {bat-rpls-2}: [DMESG-WARN][9] ([i915#4391]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/bat-rpls-2/igt@i915_selftest@live@gt_timelines.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/bat-rpls-2/igt@i915_selftest@live@gt_timelines.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][11] ([i915#3921]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-cfl-8109u: [DMESG-WARN][13] ([i915#295] / [i915#5341]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][15] ([i915#295]) -> [PASS][16] +10
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html
Warnings
* igt@runner@aborted:
- fi-apl-guc: [FAIL][17] ([i915#2426] / [i915#4312]) -> [FAIL][18]
([i915#4312])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11398/fi-apl-guc/igt@run...@aborted.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22667/fi-apl-guc/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/edid: filter DisplayID v2.0 CTA block in audio detection (rev4)
== Series Details == Series: drm/edid: filter DisplayID v2.0 CTA block in audio detection (rev4) URL : https://patchwork.freedesktop.org/series/101565/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found
[Intel-gfx] [v3] drm/edid: check basic audio support on CEA extension block
From: Cooper Chiou
Tag code stored in bit7:5 for CTA block byte[3] is not the same as
CEA extension block definition. Only check CEA block has
basic audio support.
v3: update commit message.
Cc: sta...@vger.kernel.org
Cc: Jani Nikula
Cc: Shawn C Lee
Cc: intel-gfx
Signed-off-by: Cooper Chiou
Signed-off-by: Lee Shawn C
Fixes: e28ad544f462 ("drm/edid: parse CEA blocks embedded in DisplayID")
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 561f53831e29..f07af6786cec 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4859,7 +4859,8 @@ bool drm_detect_monitor_audio(struct edid *edid)
if (!edid_ext)
goto end;
- has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
+ has_audio = (edid_ext[0] == CEA_EXT &&
+ (edid_ext[3] & EDID_BASIC_AUDIO) != 0);
if (has_audio) {
DRM_DEBUG_KMS("Monitor has basic audio support\n");
--
2.17.1
