Re: [Intel-gfx] [PATCH 2/2] drm/i915/display/psr: Use continuos full frame to handle frontbuffer invalidations

[Hogander, Jouni]

Hello Jose,

Thank you for your response. I'm sorry for the delay on my side. See my
comment below.
 
On Fri, 2022-03-25 at 14:46 +, Souza, Jose wrote:
> On Fri, 2022-03-25 at 14:21 +, Hogander, Jouni wrote:
> > Hello Jose,
> > 
> > See my comments below.
> > 
> > On Thu, 2022-03-24 at 11:13 -0700, José Roberto de Souza wrote:
> > > Instead of exit PSR when a frontbuffer invalidation happens, we
> > > can
> > > enable the PSR2 selective fetch continuous full frame, that will
> > > keep
> > > the panel updated like PSR was disabled but without keeping PSR
> > > active.
> > 
> > with keeping PSR active? I don't think it's like PSR was disabled.
> > New
> > full frame is updated only via atomic commit. Having PSR disabled
> > new
> > full frame is updated all the time as PSR wasn't existing at all.
> > 
> > > So as soon as the frontbuffer flush happens we can disable the
> > > continuous full frame and start to do selective fetches much
> > > quicker
> > > than the path that would enable PSR, that will wait a few frames
> > > to actually activate PSR.
> > > 
> > > Also this approach has proven to fix some glitches found in
> > > Alderlake-P
> > > when there are a lot of invalidations happening together with
> > > page
> > > flips.
> > > 
> > > Some may ask why it is writing to CURSURFLIVE(), it is because
> > > that is the way that hardware team provided us to poke display to
> > > handle PSR updates, and it is being used since display 9.
> > 
> > Generic comments:
> > 
> > Current logic is to disable psr2 in invalidate callback and start
> > sending fullframe updates on every vblank period. This is done
> > until
> > flush callback where psr2 is re-enabled. Intention is to update
> > possible frontbuffer writes between invalidate/flush instantly.
> > 
> > Now you are changing the logic to update one full frame when
> 
> It is not enabling the one full frame, it is enabling the continuous
> full frame so at every vblank panel will be updated until this bit
> cleared.

There is comment in bspec stating otherwise (55229). I think it is
important to clarify so that we really understand what this WA is doing
and to avoid hiding the issue just for this specific case.

Currently I'm suspecting that "SF Continuous Full Frame" just
configures next selective update to full frame and then write to
CURSURFLIVE triggers flip which is sending that full frame (only one
frame). Updates between invalidate and flush are just depending if
there are flips in between. After getting this clarified we can
properly review this WA patch.

> 
> > frontbuffer write starts (_psr_invalidate_handle) and another one
> > when
> > it stops (_psr_flush_handle) without disabling psr at all. Have I
> > understood your patch correctly?
> > 
> > Propably we wont notice this change as we have these
> > invalidate/flush
> > calls scattered around in the code. Also parallel atomic commits
> > are
> > triggering updates. In theory we could observe latency in updates
> > between invalidate/flush? Do we care? What do you think?
> > 
> > Do we need to send update in invalidate at all? Isn't that usually
> > called before doing any frontbuffer writing? I.e. we would be
> > sending
> > frame that is already in RFB?
> > 
> > > Cc: Khaled Almahallawy 
> > > Cc: Shawn C Lee 
> > > Cc: Jouni Högander 
> > > Cc: Mika Kahola 
> > > Signed-off-by: José Roberto de Souza 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_psr.c | 109
> > > -
> > > --
> > >  1 file changed, 95 insertions(+), 14 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index d87b357806c91..f7b7b374374b1 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -1450,6 +1450,22 @@ static inline u32
> > > man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev
> > >  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > >  }
> > > 
> > > +static inline u32 man_trk_ctl_continuos_full_frame(struct
> > > drm_i915_private *dev_priv)
> > > +{
> > > + return IS_ALDERLAKE_P(dev_priv) ?
> > > +ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME :
> > > +PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
> > > +}
> > > +
> > > +static inline u32 man_trk_ctl_su_region_start_end_mask(struct
> > > drm_i915_private *dev_priv)
> > > +{
> > > + if (IS_ALDERLAKE_P(dev_priv))
> > > + return
> > > ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK
> > > +ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MAS
> > > K;
> > > + return PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK |
> > > +PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK;
> > > +}
> > > +
> > >  static void psr_force_hw_tracking_exit(struct intel_dp
> > > *intel_dp)
> > >  {
> > >   struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > @@ -1546,8 +1562,9 @@ void
> > > intel_psr2_program_trans_man_trk_ctl(co

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Start reordering modeset clock calculations (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Start reordering modeset clock calculations (rev3)
URL   : https://patchwork.freedesktop.org/series/101789/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22729_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22729_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22729_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22729_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_flip@flip-vs-suspend@b-edp1:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb7/igt@kms_flip@flip-vs-susp...@b-edp1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb1/igt@kms_flip@flip-vs-susp...@b-edp1.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_psr_stress_test@flip-primary-invalidate-overlay}:
- shard-tglb: [PASS][3] -> [SKIP][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb6/igt@kms_psr_stress_t...@flip-primary-invalidate-overlay.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb5/igt@kms_psr_stress_t...@flip-primary-invalidate-overlay.html

  
Known issues


  Here are the changes found in Patchwork_22729_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +1 
similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-queued.html

  * igt@gem_ctx_sseu@invalid-sseu:
- shard-tglb: NOTRUN -> [SKIP][6] ([i915#280])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@gem_ctx_s...@invalid-sseu.html

  * igt@gem_eio@in-flight-contexts-10ms:
- shard-apl:  [PASS][7] -> [TIMEOUT][8] ([i915#3063])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl2/igt@gem_...@in-flight-contexts-10ms.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-apl7/igt@gem_...@in-flight-contexts-10ms.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#232])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb7/igt@gem_...@unwedge-stress.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb3/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-skl:  [PASS][11] -> [INCOMPLETE][12] ([i915#4547])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl2/igt@gem_exec_capture@p...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl10/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-iclb5/igt@gem_exec_fair@basic-pace-s...@rcs0.html
- shard-glk:  [PASS][17] -> [FAIL][18] ([i915#2842])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk8/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-glk4/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_schedule@submit-early-slice@bcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][19] ([i915#3797])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-skl3/igt@gem_exec_schedule@submit-early-sl...@bcs0.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#4613])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/shard-tglb6/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@smem-oom:
- shard-apl:  NOTRU

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Start reordering modeset clock calculations (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Start reordering modeset clock calculations (rev3)
URL   : https://patchwork.freedesktop.org/series/101789/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22729


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/index.html

Participating hosts (44 -> 45)
--

  Additional (6): fi-tgl-u2 fi-skl-guc fi-icl-u2 fi-cfl-8700k fi-ivb-3770 
fi-pnv-d510 
  Missing(5): shard-tglu fi-bsw-cyan shard-rkl shard-dg1 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_22729 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka:   NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#109315]) +17 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html

  * igt@amdgpu/amd_basic@userptr:
- fi-cfl-8700k:   NOTRUN -> [SKIP][3] ([fdo#109271]) +29 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-cfl-8700k/igt@amdgpu/amd_ba...@userptr.html

  * igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2:  NOTRUN -> [SKIP][4] ([fdo#109315]) +17 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html

  * igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][5] ([fdo#109271]) +57 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
- fi-tgl-u2:  NOTRUN -> [SKIP][6] ([i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html
- fi-cfl-8700k:   NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-cfl-8700k/igt@gem_huc_c...@huc-copy.html
- fi-icl-u2:  NOTRUN -> [SKIP][8] ([i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
- fi-skl-guc: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-skl-guc/igt@gem_lmem_swapp...@random-engines.html
- fi-ivb-3770:NOTRUN -> [SKIP][11] ([fdo#109271]) +36 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-ivb-3770/igt@gem_lmem_swapp...@random-engines.html
- fi-cfl-8700k:   NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-cfl-8700k/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2:  NOTRUN -> [SKIP][13] ([i915#4613]) +3 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-tgl-u2/igt@gem_lmem_swapp...@verify-random.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-u2:  NOTRUN -> [SKIP][14] ([fdo#109284] / [fdo#111827]) +8 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-tgl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-skl-guc: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-skl-guc/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-cfl-8700k:   NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-cfl-8700k/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-ivb-3770:NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-ivb-3770/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][18] ([fdo#111827]) +8 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22729/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2:  NOTRUN -> [SKIP][19] ([i915#4

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Start reordering modeset clock calculations (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Start reordering modeset clock calculations (rev3)
URL   : https://patchwork.freedesktop.org/series/101789/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Start reordering modeset clock calculations (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Start reordering modeset clock calculations (rev3)
URL   : https://patchwork.freedesktop.org/series/101789/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Start reordering modeset clock calculations (rev3)
URL   : https://patchwork.freedesktop.org/series/101789/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
eef669f225cd drm/i915: Make .get_dplls() return int
526bd16336db drm/i915: Pass dev_priv to intel_shared_dpll_init()
657130d86c57 drm/i915: Remove pointless dpll_funcs checks
d97da58c081b drm/i915: Adjust .crtc_compute_clock() calling convention
8229e8880231 drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
fc05b45e8924 drm/i915: Move the dpll_hw_state clearing to 
intel_dpll_crtc_compute_clock()
afcd83860b16 drm/i915: Clear the dpll_hw_state when disabling a pipe
871f0d8b7c92 drm/i915: Split out dg2_crtc_compute_clock()
2ebb495949cc drm/i915: Add crtc .crtc_get_shared_dpll()
1d067b0daf49 drm/i915: Split shared dpll .get_dplls() into compute and get 
phases
-:191: CHECK:CAMELCASE: Avoid CamelCase: 
#191: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063:
+   SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;

total: 0 errors, 0 warnings, 1 checks, 516 lines checked
f52d29ef90c2 drm/i915: Do .crtc_compute_clock() earlier
282084c82d01 drm/i915: Clean up DPLL related debugs
0c8cf5704839 drm/i915: Reassign DPLLs only for crtcs going throug 
.compute_config()

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/4] drm/i915/display/tgl+: Set default values 
for all registers in PIPE_MBUS_DBOX_CTL
URL   : https://patchwork.freedesktop.org/series/101937/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22726_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22726_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_psr_stress_test@flip-primary-invalidate-overlay}:
- shard-tglb: [PASS][1] -> [SKIP][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb6/igt@kms_psr_stress_t...@flip-primary-invalidate-overlay.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb7/igt@kms_psr_stress_t...@flip-primary-invalidate-overlay.html

  
Known issues


  Here are the changes found in Patchwork_22726_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ccs@ctrl-surf-copy:
- shard-iclb: NOTRUN -> [SKIP][3] ([i915#5327])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@gem_...@ctrl-surf-copy.html

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl:  [PASS][4] -> [DMESG-WARN][5] ([i915#180]) +2 similar 
issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-kbl6/igt@gem_ctx_isolation@preservation...@bcs0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-kbl7/igt@gem_ctx_isolation@preservation...@bcs0.html

  * igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb:  NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +1 
similar issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-queued.html

  * igt@gem_ctx_sseu@invalid-sseu:
- shard-tglb: NOTRUN -> [SKIP][7] ([i915#280])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@gem_ctx_s...@invalid-sseu.html

  * igt@gem_eio@suspend:
- shard-tglb: [PASS][8] -> [DMESG-WARN][9] ([i915#2867])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb5/igt@gem_...@suspend.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb2/igt@gem_...@suspend.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][10] -> [TIMEOUT][11] ([i915#3063] / 
[i915#3648])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb7/igt@gem_...@unwedge-stress.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb6/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-apl:  [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl8/igt@gem_exec_fair@basic-n...@vcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-apl7/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb1/igt@gem_exec_fair@basic-pace-s...@rcs0.html
- shard-glk:  [PASS][16] -> [FAIL][17] ([i915#2842])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk8/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-glk8/igt@gem_exec_fair@basic-pace-s...@rcs0.html
- shard-apl:  NOTRUN -> [FAIL][18] ([i915#2842])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-apl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_schedule@submit-early-slice@vcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][19] ([i915#3797])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-skl6/igt@gem_exec_schedule@submit-early-sl...@vcs0.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#4613])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-iclb6/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-tglb: NOTRUN -> [SKIP][21] ([i915#4613])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/shard-tglb3/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@smem-oom:
- shard-apl:  NOTRUN -> [SKIP

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Splitting intel-gtt calls for non-x86 platforms (rev3)

[Patchwork]

== Series Details ==

Series: Splitting intel-gtt calls for non-x86 platforms (rev3)
URL   : https://patchwork.freedesktop.org/series/101552/
State : failure

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  DESCEND objtool
  CHK include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/gt/intel_ggtt.o
In file included from ./include/drm/drm_mm.h:51,
 from ./drivers/gpu/drm/i915/i915_vma.h:31,
 from drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h:13,
 from drivers/gpu/drm/i915/gt/uc/intel_guc.h:19,
 from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
 from drivers/gpu/drm/i915/gt/intel_gt_types.h:18,
 from drivers/gpu/drm/i915/gt/intel_gt.h:10,
 from drivers/gpu/drm/i915/gt/intel_ggtt.c:12:
drivers/gpu/drm/i915/gt/intel_ggtt.c: In function ‘ggtt_probe_hw’:
drivers/gpu/drm/i915/gt/intel_ggtt.c:610:23: error: ‘intel_graphics_stolen_res’ 
undeclared (first use in this function); did you mean ‘intel_engine_stop_cs’?
   (u64)resource_size(&intel_graphics_stolen_res) >> 20);
   ^
./include/drm/drm_print.h:461:63: note: in definition of macro ‘drm_dbg’
  drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DRIVER, fmt, ##__VA_ARGS__)
   ^~~
drivers/gpu/drm/i915/gt/intel_ggtt.c:610:23: note: each undeclared identifier 
is reported only once for each function it appears in
   (u64)resource_size(&intel_graphics_stolen_res) >> 20);
   ^
./include/drm/drm_print.h:461:63: note: in definition of macro ‘drm_dbg’
  drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DRIVER, fmt, ##__VA_ARGS__)
   ^~~
scripts/Makefile.build:288: recipe for target 
'drivers/gpu/drm/i915/gt/intel_ggtt.o' failed
make[4]: *** [drivers/gpu/drm/i915/gt/intel_ggtt.o] Error 1
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1831: recipe for target 'drivers' failed
make: *** [drivers] Error 2

Re: [Intel-gfx] [PATCH] drm/i915/display/: Refactor hsw_crtc_enable for bigjoiner cleanup

[Navare, Manasi]

Hi Ville,

I was looking at your suggestion of extracting the per pipe stuff out.
Currently in hsw_crtc_enable: the Only non per pipe stuff which gets enabled 
for the encoders is :
encoder specific is pre_pll_enable(), enable_shared_dpll, encoders_pre_enable 
and configure_cpu_transcoder() - All of this 
can be put in a function hsw_encoder_configure() or something that can still be 
called from with hsw_crtc_enable

Then the remaining can go into a per pipe function that can be called for each 
slave pipe

But it means still pretty much splitting the current hsw_crtc_enable into 2 
separate functions

Does this refactoring make sense?

Manasi


On Thu, Mar 17, 2022 at 09:14:16PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 17, 2022 at 12:05:47PM -0700, Navare, Manasi wrote:
> > On Thu, Mar 17, 2022 at 08:52:52PM +0200, Ville Syrjälä wrote:
> > > On Tue, Mar 15, 2022 at 04:38:56PM -0700, Manasi Navare wrote:
> > > > This patch abstracts pieces of hsw_crtc_enable corresponding to 
> > > > different
> > > > Bspec enable sequence steps into separate functions.
> > > > This helps to call them in a specific order for bigjoiner master/slave
> > > > in a cleaner fashion.
> > > > 
> > > > Cc: Ville Syrjälä 
> > > > Cc: Animesh Manna 
> > > > Signed-off-by: Manasi Navare 
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_display.c | 125 ++-
> > > >  1 file changed, 66 insertions(+), 59 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index eb49973621f0..d8e6466c9fa0 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -1865,24 +1865,6 @@ static void hsw_set_frame_start_delay(const 
> > > > struct intel_crtc_state *crtc_state)
> > > > intel_de_write(dev_priv, reg, val);
> > > >  }
> > > >  
> > > > -static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state 
> > > > *state,
> > > > -const struct intel_crtc_state 
> > > > *crtc_state)
> > > > -{
> > > > -   struct intel_crtc *master_crtc = intel_master_crtc(crtc_state);
> > > > -
> > > > -   /*
> > > > -* Enable sequence steps 1-7 on bigjoiner master
> > > > -*/
> > > > -   if (intel_crtc_is_bigjoiner_slave(crtc_state))
> > > > -   intel_encoders_pre_pll_enable(state, master_crtc);
> > > > -
> > > > -   if (crtc_state->shared_dpll)
> > > > -   intel_enable_shared_dpll(crtc_state);
> > > > -
> > > > -   if (intel_crtc_is_bigjoiner_slave(crtc_state))
> > > > -   intel_encoders_pre_enable(state, master_crtc);
> > > > -}
> > > > -
> > > >  static void hsw_configure_cpu_transcoder(const struct intel_crtc_state 
> > > > *crtc_state)
> > > >  {
> > > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > @@ -1910,70 +1892,73 @@ static void hsw_configure_cpu_transcoder(const 
> > > > struct intel_crtc_state *crtc_sta
> > > > hsw_set_transconf(crtc_state);
> > > >  }
> > > >  
> > > > -static void hsw_crtc_enable(struct intel_atomic_state *state,
> > > > -   struct intel_crtc *crtc)
> > > > +static void hsw_crtc_pre_pll_enable(struct intel_atomic_state *state,
> > > > +   const struct intel_crtc_state 
> > > > *crtc_state)
> > > >  {
> > > > -   const struct intel_crtc_state *new_crtc_state =
> > > > -   intel_atomic_get_new_crtc_state(state, crtc);
> > > > -   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > > -   enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
> > > > -   enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
> > > > -   bool psl_clkgate_wa;
> > > > -
> > > > -   if (drm_WARN_ON(&dev_priv->drm, crtc->active))
> > > > -   return;
> > > > +   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > >  
> > > > -   if (!new_crtc_state->bigjoiner_pipes) {
> > > > -   intel_encoders_pre_pll_enable(state, crtc);
> > > > +   /*
> > > > +* Enable sequence steps 1 - 7 on all pipes
> > > > +*/
> > > > +   intel_encoders_pre_pll_enable(state, crtc);
> > > > +   if (crtc_state->shared_dpll)
> > > > +   intel_enable_shared_dpll(crtc_state);
> > > >  
> > > > -   if (new_crtc_state->shared_dpll)
> > > > -   intel_enable_shared_dpll(new_crtc_state);
> > > > +   intel_encoders_pre_enable(state, crtc);
> > > > +}
> > > >  
> > > > -   intel_encoders_pre_enable(state, crtc);
> > > > -   } else {
> > > > -   icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
> > > > -   }
> > > > +static void hsw_crtc_post_pll_enable(struct intel_atomic_state *state,
> > > > +const struct intel_crtc_state 
> > > > *crtc_sta

[Intel-gfx] [PATCH v3 1/2] drm/i915/gt: Split intel-gtt functions by arch

[Casey Bowman]

Some functions defined in the intel-gtt module are used in several
areas, but is only supported on x86 platforms.

By separating these calls and their static underlying functions to
another area, we are able to compile out these functions for
non-x86 builds and provide stubs for the non-x86 implementations.

In addition to the problematic calls, we are moving the gmch-related
functions to the new area.

Signed-off-by: Casey Bowman 
---
 drivers/gpu/drm/i915/Makefile   |   2 +
 drivers/gpu/drm/i915/gt/intel_ggtt.c| 665 +---
 drivers/gpu/drm/i915/gt/intel_gt.c  |   4 +-
 drivers/gpu/drm/i915/gt/intel_gt.h  |   9 +
 drivers/gpu/drm/i915/gt/intel_gt_gmch.c | 653 +++
 drivers/gpu/drm/i915/gt/intel_gt_gmch.h |  46 ++
 drivers/gpu/drm/i915/gt/intel_gtt.h |   9 +
 7 files changed, 735 insertions(+), 653 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c837a29ffac8..b7bdaec99118 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -126,6 +126,8 @@ gt-y += \
gt/intel_workarounds.o \
gt/shmem_utils.o \
gt/sysfs_engines.o
+# x86 intel-gtt module support
+gt-$(CONFIG_X86) += gt/intel_gt_gmch.o
 # autogenerated null render state
 gt-y += \
gt/gen6_renderstate.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 04191fe2ee34..97a595e42135 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -3,18 +3,14 @@
  * Copyright © 2020 Intel Corporation
  */
 
-#include 
-#include 
-
+#include 
 #include 
 #include 
 
-#include 
-#include 
-
 #include "gem/i915_gem_lmem.h"
 
 #include "intel_gt.h"
+#include "intel_gt_gmch.h"
 #include "intel_gt_regs.h"
 #include "i915_drv.h"
 #include "i915_scatterlist.h"
@@ -94,28 +90,6 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
return 0;
 }
 
-/*
- * Certain Gen5 chipsets require idling the GPU before
- * unmapping anything from the GTT when VT-d is enabled.
- */
-static bool needs_idle_maps(struct drm_i915_private *i915)
-{
-   /*
-* Query intel_iommu to see if we need the workaround. Presumably that
-* was loaded first.
-*/
-   if (!intel_vtd_active(i915))
-   return false;
-
-   if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915))
-   return true;
-
-   if (GRAPHICS_VER(i915) == 12)
-   return true; /* XXX DMAR fault reason 7 */
-
-   return false;
-}
-
 /**
  * i915_ggtt_suspend_vm - Suspend the memory mappings for a GGTT or DPT VM
  * @vm: The VM to suspend the mappings for
@@ -204,7 +178,7 @@ void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
spin_unlock_irq(&uncore->lock);
 }
 
-static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
+void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 
@@ -229,11 +203,6 @@ static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 }
 
-static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
-{
-   intel_gtt_chipset_flush();
-}
-
 u64 gen8_ggtt_pte_encode(dma_addr_t addr,
 enum i915_cache_level level,
 u32 flags)
@@ -246,258 +215,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
return pte;
 }
 
-static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
-{
-   writeq(pte, addr);
-}
-
-static void gen8_ggtt_insert_page(struct i915_address_space *vm,
- dma_addr_t addr,
- u64 offset,
- enum i915_cache_level level,
- u32 flags)
-{
-   struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
-   gen8_pte_t __iomem *pte =
-   (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
-
-   gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));
-
-   ggtt->invalidate(ggtt);
-}
-
-static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
-struct i915_vma_resource *vma_res,
-enum i915_cache_level level,
-u32 flags)
-{
-   const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);
-   struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
-   gen8_pte_t __iomem *gte;
-   gen8_pte_t __iomem *end;
-   struct sgt_iter iter;
-   dma_addr_t addr;
-
-   /*
-* Note that we ignore PTE_READ_ONLY here. The caller must be careful
-* not to allow the user to override access to a read only page.
-*/
-
-   gte = (gen8_pte_t __iomem *)ggtt->gsm;
-   gte += vma_res->start / I91

[Intel-gfx] [PATCH v3 2/2] drm/i915: Require INTEL_GTT to depend on X86

[Casey Bowman]

The intel-gtt module is not used on other, non-x86 platforms, so we
will restrict it to x86 platforms only.

Signed-off-by: Casey Bowman 
---
 drivers/gpu/drm/i915/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 63db8bcf03bf..b381e14863a6 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -4,7 +4,7 @@ config DRM_I915
depends on DRM
depends on X86 && PCI
depends on !PREEMPT_RT
-   select INTEL_GTT
+   select INTEL_GTT if X86
select INTERVAL_TREE
# we need shmfs for the swappable backing store, and in particular
# the shmem_readpage() which depends upon tmpfs
-- 
2.25.1

[Intel-gfx] [PATCH v3 0/2] Splitting intel-gtt calls for non-x86 platforms

[Casey Bowman]

The intel-gtt module defines some functions used by i915, but they are
only supported by x86 platforms. In order to bring i915 to a more
arch-neutral state, we split out these functions and provide stubs in
the case of non-x86 builds.

There may be a better filename choice for the files used in splitting
the calls, it's very much open to discussion.

v2: Refactored to move gmch functions, renamed exported functions
v3: Added drm/i915_drm.h header

Casey Bowman (2):
  drm/i915/gt: Split intel-gtt functions by arch
  drm/i915: Moved drm/i915_drm.h header to intel_gt_gmch.c

 drivers/gpu/drm/i915/Kconfig|   2 +-
 drivers/gpu/drm/i915/Makefile   |   2 +
 drivers/gpu/drm/i915/gt/intel_ggtt.c| 665 +---
 drivers/gpu/drm/i915/gt/intel_gt.c  |   4 +-
 drivers/gpu/drm/i915/gt/intel_gt.h  |   9 +
 drivers/gpu/drm/i915/gt/intel_gt_gmch.c | 653 +++
 drivers/gpu/drm/i915/gt/intel_gt_gmch.h |  46 ++
 drivers/gpu/drm/i915/gt/intel_gtt.h |   9 +
 8 files changed, 736 insertions(+), 654 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.h

-- 
2.25.1

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Splitting intel-gtt calls for non-x86 platforms (rev2)

[Patchwork]

== Series Details ==

Series: Splitting intel-gtt calls for non-x86 platforms (rev2)
URL   : https://patchwork.freedesktop.org/series/101552/
State : failure

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  DESCEND objtool
  CHK include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt_gmch.o
drivers/gpu/drm/i915/gt/intel_gt_gmch.c: In function ‘gen6_get_total_gtt_size’:
drivers/gpu/drm/i915/gt/intel_gt_gmch.c:411:19: error: ‘SNB_GMCH_GGMS_SHIFT’ 
undeclared (first use in this function); did you mean ‘SHM_HUGE_SHIFT’?
  snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
   ^~~
   SHM_HUGE_SHIFT
drivers/gpu/drm/i915/gt/intel_gt_gmch.c:411:19: note: each undeclared 
identifier is reported only once for each function it appears in
drivers/gpu/drm/i915/gt/intel_gt_gmch.c:412:18: error: ‘SNB_GMCH_GGMS_MASK’ 
undeclared (first use in this function); did you mean ‘SHM_HUGE_MASK’?
  snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
  ^~
  SHM_HUGE_MASK
drivers/gpu/drm/i915/gt/intel_gt_gmch.c: In function ‘gen8_get_total_gtt_size’:
drivers/gpu/drm/i915/gt/intel_gt_gmch.c:418:19: error: ‘BDW_GMCH_GGMS_SHIFT’ 
undeclared (first use in this function); did you mean ‘HSW_CAGF_SHIFT’?
  bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
   ^~~
   HSW_CAGF_SHIFT
drivers/gpu/drm/i915/gt/intel_gt_gmch.c:419:18: error: ‘BDW_GMCH_GGMS_MASK’ 
undeclared (first use in this function); did you mean ‘BITMAP_MEM_MASK’?
  bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
  ^~
  BITMAP_MEM_MASK
drivers/gpu/drm/i915/gt/intel_gt_gmch.c: In function ‘intel_gt_gmch_gen6_probe’:
drivers/gpu/drm/i915/gt/intel_gt_gmch.c:547:29: error: ‘SNB_GMCH_CTRL’ 
undeclared (first use in this function); did you mean ‘VDBX_MOD_CTRL’?
  pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 ^
 VDBX_MOD_CTRL
drivers/gpu/drm/i915/gt/intel_gt_gmch.c: In function ‘chv_get_total_gtt_size’:
drivers/gpu/drm/i915/gt/intel_gt_gmch.c:583:16: error: ‘SNB_GMCH_GGMS_SHIFT’ 
undeclared (first use in this function); did you mean ‘SHM_HUGE_SHIFT’?
  gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
^~~
SHM_HUGE_SHIFT
drivers/gpu/drm/i915/gt/intel_gt_gmch.c:584:15: error: ‘SNB_GMCH_GGMS_MASK’ 
undeclared (first use in this function); did you mean ‘SHM_HUGE_MASK’?
  gmch_ctrl &= SNB_GMCH_GGMS_MASK;
   ^~
   SHM_HUGE_MASK
drivers/gpu/drm/i915/gt/intel_gt_gmch.c: In function ‘intel_gt_gmch_gen8_probe’:
drivers/gpu/drm/i915/gt/intel_gt_gmch.c:605:29: error: ‘SNB_GMCH_CTRL’ 
undeclared (first use in this function); did you mean ‘VDBX_MOD_CTRL’?
  pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 ^
 VDBX_MOD_CTRL
scripts/Makefile.build:288: recipe for target 
'drivers/gpu/drm/i915/gt/intel_gt_gmch.o' failed
make[4]: *** [drivers/gpu/drm/i915/gt/intel_gt_gmch.o] Error 1
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1831: recipe for target 'drivers' failed
make: *** [drivers] Error 2

[Intel-gfx] [PATCH v2 2/2] drm/i915: Require INTEL_GTT to depend on X86

[Casey Bowman]

The intel-gtt module is not used on other, non-x86 platforms, so we
will restrict it to x86 platforms only.

Signed-off-by: Casey Bowman 
---
 drivers/gpu/drm/i915/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 63db8bcf03bf..b381e14863a6 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -4,7 +4,7 @@ config DRM_I915
depends on DRM
depends on X86 && PCI
depends on !PREEMPT_RT
-   select INTEL_GTT
+   select INTEL_GTT if X86
select INTERVAL_TREE
# we need shmfs for the swappable backing store, and in particular
# the shmem_readpage() which depends upon tmpfs
-- 
2.25.1

[Intel-gfx] [PATCH v2 1/2] drm/i915/gt: Split intel-gtt functions by arch

[Casey Bowman]

Some functions defined in the intel-gtt module are used in several
areas, but is only supported on x86 platforms.

By separating these calls and their static underlying functions to
another area, we are able to compile out these functions for
non-x86 builds and provide stubs for the non-x86 implementations.

In addition to the problematic calls, we are moving the gmch-related
functions to the new area.

Signed-off-by: Casey Bowman 
---
 drivers/gpu/drm/i915/Makefile   |   2 +
 drivers/gpu/drm/i915/gt/intel_ggtt.c| 663 +---
 drivers/gpu/drm/i915/gt/intel_gt.c  |   4 +-
 drivers/gpu/drm/i915/gt/intel_gt.h  |   9 +
 drivers/gpu/drm/i915/gt/intel_gt_gmch.c | 653 +++
 drivers/gpu/drm/i915/gt/intel_gt_gmch.h |  46 ++
 drivers/gpu/drm/i915/gt/intel_gtt.h |   9 +
 7 files changed, 735 insertions(+), 651 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c837a29ffac8..b7bdaec99118 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -126,6 +126,8 @@ gt-y += \
gt/intel_workarounds.o \
gt/shmem_utils.o \
gt/sysfs_engines.o
+# x86 intel-gtt module support
+gt-$(CONFIG_X86) += gt/intel_gt_gmch.o
 # autogenerated null render state
 gt-y += \
gt/gen6_renderstate.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 04191fe2ee34..934f2ed6c2dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -3,18 +3,16 @@
  * Copyright © 2020 Intel Corporation
  */
 
-#include 
-#include 
-
+#include 
 #include 
 #include 
 
 #include 
-#include 
 
 #include "gem/i915_gem_lmem.h"
 
 #include "intel_gt.h"
+#include "intel_gt_gmch.h"
 #include "intel_gt_regs.h"
 #include "i915_drv.h"
 #include "i915_scatterlist.h"
@@ -94,28 +92,6 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
return 0;
 }
 
-/*
- * Certain Gen5 chipsets require idling the GPU before
- * unmapping anything from the GTT when VT-d is enabled.
- */
-static bool needs_idle_maps(struct drm_i915_private *i915)
-{
-   /*
-* Query intel_iommu to see if we need the workaround. Presumably that
-* was loaded first.
-*/
-   if (!intel_vtd_active(i915))
-   return false;
-
-   if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915))
-   return true;
-
-   if (GRAPHICS_VER(i915) == 12)
-   return true; /* XXX DMAR fault reason 7 */
-
-   return false;
-}
-
 /**
  * i915_ggtt_suspend_vm - Suspend the memory mappings for a GGTT or DPT VM
  * @vm: The VM to suspend the mappings for
@@ -204,7 +180,7 @@ void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
spin_unlock_irq(&uncore->lock);
 }
 
-static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
+void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 
@@ -229,11 +205,6 @@ static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
 }
 
-static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
-{
-   intel_gtt_chipset_flush();
-}
-
 u64 gen8_ggtt_pte_encode(dma_addr_t addr,
 enum i915_cache_level level,
 u32 flags)
@@ -246,258 +217,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
return pte;
 }
 
-static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
-{
-   writeq(pte, addr);
-}
-
-static void gen8_ggtt_insert_page(struct i915_address_space *vm,
- dma_addr_t addr,
- u64 offset,
- enum i915_cache_level level,
- u32 flags)
-{
-   struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
-   gen8_pte_t __iomem *pte =
-   (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
-
-   gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));
-
-   ggtt->invalidate(ggtt);
-}
-
-static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
-struct i915_vma_resource *vma_res,
-enum i915_cache_level level,
-u32 flags)
-{
-   const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);
-   struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
-   gen8_pte_t __iomem *gte;
-   gen8_pte_t __iomem *end;
-   struct sgt_iter iter;
-   dma_addr_t addr;
-
-   /*
-* Note that we ignore PTE_READ_ONLY here. The caller must be careful
-* not to allow the user to override access to a read only page.
-*/
-
-   gte = (gen8_pte_t __iomem *)ggtt->gsm;
-   gte += vma_res->start / I91

[Intel-gfx] [PATCH v2 0/2] Splitting intel-gtt calls for non-x86 platforms

[Casey Bowman]

The intel-gtt module defines some functions used by i915, but they are
only supported by x86 platforms. In order to bring i915 to a more
arch-neutral state, we split out these functions and provide stubs in
the case of non-x86 builds.

There may be a better filename choice for the files used in splitting
the calls, it's very much open to discussion.

v2: Refactored to move gmch functions, renamed exported functions

Casey Bowman (2):
  drm/i915/gt: Split intel-gtt functions by arch
  drm/i915: Require INTEL_GTT to depend on X86

 drivers/gpu/drm/i915/Kconfig|   2 +-
 drivers/gpu/drm/i915/Makefile   |   2 +
 drivers/gpu/drm/i915/gt/intel_ggtt.c| 663 +---
 drivers/gpu/drm/i915/gt/intel_gt.c  |   4 +-
 drivers/gpu/drm/i915/gt/intel_gt.h  |   9 +
 drivers/gpu/drm/i915/gt/intel_gt_gmch.c | 653 +++
 drivers/gpu/drm/i915/gt/intel_gt_gmch.h |  46 ++
 drivers/gpu/drm/i915/gt/intel_gtt.h |   9 +
 8 files changed, 736 insertions(+), 652 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_gmch.h

-- 
2.25.1

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/4] drm/i915/display/tgl+: Set default values 
for all registers in PIPE_MBUS_DBOX_CTL
URL   : https://patchwork.freedesktop.org/series/101937/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22726


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/index.html

Participating hosts (43 -> 44)
--

  Additional (5): fi-tgl-u2 fi-skl-guc fi-cfl-8700k bat-adlp-4 fi-ivb-3770 
  Missing(4): fi-bsw-cyan shard-rkl shard-tglu fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_22726 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka:   NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#109315]) +17 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html

  * igt@amdgpu/amd_basic@userptr:
- fi-cfl-8700k:   NOTRUN -> [SKIP][3] ([fdo#109271]) +29 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-cfl-8700k/igt@amdgpu/amd_ba...@userptr.html

  * igt@gem_huc_copy@huc-copy:
- fi-tgl-u2:  NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html
- fi-cfl-8700k:   NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-cfl-8700k/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
- fi-skl-guc: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-skl-guc/igt@gem_lmem_swapp...@random-engines.html
- fi-ivb-3770:NOTRUN -> [SKIP][7] ([fdo#109271]) +36 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-ivb-3770/igt@gem_lmem_swapp...@random-engines.html
- fi-cfl-8700k:   NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-cfl-8700k/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2:  NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-tgl-u2/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-6:  [PASS][10] -> [INCOMPLETE][11] ([i915#4418])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/bat-dg1-6/igt@i915_selftest@live@gt_engines.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-u2:  NOTRUN -> [SKIP][12] ([fdo#109284] / [fdo#111827]) +8 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-tgl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-skl-guc: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-skl-guc/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-cfl-8700k:   NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-cfl-8700k/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-ivb-3770:NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-ivb-3770/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2:  NOTRUN -> [SKIP][16] ([i915#4103]) +1 similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-tgl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_flip@basic-flip-vs-dpms@a-edp1:
- fi-tgl-u2:  NOTRUN -> [DMESG-WARN][17] ([i915#402]) +1 similar 
issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-tgl-u2/igt@kms_flip@basic-flip-vs-d...@a-edp1.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2:  NOTRUN -> [SKIP][18] ([fdo#109285])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22726/fi-tgl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pi

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg2: Add Wa_22014226127 (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/dg2: Add Wa_22014226127 (rev6)
URL   : https://patchwork.freedesktop.org/series/101792/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22725_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22725_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22725_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22725_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_schedule@fairslice-all:
- shard-kbl:  NOTRUN -> [DMESG-WARN][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/shard-kbl3/igt@gem_exec_sched...@fairslice-all.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-kbl:  NOTRUN -> [DMESG-FAIL][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/shard-kbl3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html

  
Known issues


  Here are the changes found in Patchwork_22725_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl:  [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar 
issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl2/igt@gem_ctx_isolation@preservation...@rcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/shard-apl4/igt@gem_ctx_isolation@preservation...@rcs0.html

  * igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +1 
similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-queued.html

  * igt@gem_ctx_sseu@invalid-sseu:
- shard-tglb: NOTRUN -> [SKIP][6] ([i915#280])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/shard-tglb6/igt@gem_ctx_s...@invalid-sseu.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-skl:  [PASS][7] -> [INCOMPLETE][8] ([i915#4547])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl2/igt@gem_exec_capture@p...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/shard-skl9/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/shard-iclb4/igt@gem_exec_fair@basic-pace-s...@rcs0.html
- shard-glk:  [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk8/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/shard-glk4/igt@gem_exec_fair@basic-pace-s...@rcs0.html
- shard-kbl:  NOTRUN -> [FAIL][13] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/shard-kbl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
- shard-apl:  NOTRUN -> [FAIL][14] ([i915#2842])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/shard-apl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2849])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb5/igt@gem_exec_fair@basic-throt...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/shard-iclb8/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_schedule@submit-early-slice@vcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][17] ([i915#3797])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/shard-skl7/igt@gem_exec_schedule@submit-early-sl...@vcs0.html

  * igt@gem_lmem_swapping@heavy-verify-random:
- shard-kbl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/shard-kbl3/igt@gem_lmem_swapp...@heavy-verify-random.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#4613])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/shard-tglb6/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@smem-oom:
- shard-apl:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613])
   [20]: 
https://

Re: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children runtime status

[Dixit, Ashutosh]

On Mon, 28 Mar 2022 03:22:27 -0700, Anshuman Gupta wrote:
>
> +#ifdef CONFIG_PM
> +static int i915_runtime_dump_child_status(struct device *dev, void *data)
> +{
> + struct seq_file *m = data;
> + const char *rpm_status;
> +
> + /* Early return if runtime_pm is disabled */
> + if (dev->power.disable_depth)
> + return 0;
> +
> + switch (dev->power.runtime_status) {
> + case RPM_SUSPENDED:
> + rpm_status = "suspended";
> + break;
> + case RPM_SUSPENDING:
> + rpm_status = "suspending";
> + break;
> + case RPM_RESUMING:
> + rpm_status = "resuming";
> + break;
> + case RPM_ACTIVE:
> + rpm_status = "active";
> + break;
> + default:
> + rpm_status = "unknown";
> + }
> +
> + seq_printf(m, "\t%s %s: Runtime status: %s\n", dev_driver_string(dev),
> +dev_name(dev), rpm_status);
> +
> + return 0;
> +}
> +#endif

Maybe a nit, but perhaps defining a const array is better than having a
switch statement? Similar to what is done in rtpm_status_str(). The
function itself is very similar to rtpm_status_str() so can probably
benefit from that similarity. Can perhaps even be nearly identical to
rtpm_status_str() (since that is static in the genpd (generic power domain)
code).

See also 2bd5306a8764 ("PM / Domains: add debugfs listing of struct
generic_pm_domain-s"), though I am not sure if genpd's are applicable in
our case and certainly look way out of scope for now. Thanks.

> +
>  static int i915_runtime_pm_status(struct seq_file *m, void *unused)
>  {
>   struct drm_i915_private *dev_priv = node_to_i915(m->private);
> @@ -500,6 +534,10 @@ static int i915_runtime_pm_status(struct seq_file *m, 
> void *unused)
>  #ifdef CONFIG_PM
>   seq_printf(m, "Usage count: %d\n",
>  atomic_read(&dev_priv->drm.dev->power.usage_count));
> + seq_printf(m, "Runtime active children: %d\n",
> +atomic_read(&dev_priv->drm.dev->power.child_count));
> + device_for_each_child(&pdev->dev, m, i915_runtime_dump_child_status);
> +
>  #else
>   seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
>  #endif
> --
> 2.26.2
>

Re: [Intel-gfx] [PATCH] drm/i915/hwconfig: Add DG2 support

[John Harrison]

On 3/24/2022 17:21, Jordan Justen wrote:

From: Rodrigo Vivi 

DG2 support for hwconfig tables varies by both SKU and stepping.

Signed-off-by: Rodrigo Vivi 
Signed-off-by: John Harrison 
Signed-off-by: Ramalingam C 
Tested-by: Jordan Justen 
---
  drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
index e0f65bdd1c84..b34833cca44a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
@@ -96,6 +96,8 @@ static bool has_table(struct drm_i915_private *i915)
  {
if (IS_ALDERLAKE_P(i915))
return true;
+   if (IS_DG2_G11(i915) || IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A2, 
STEP_FOREVER))

This should just be 'IS_DG2()'.

John.


+   return true;
  
  	return false;

  }

[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/4] drm/i915/display/tgl+: Set default values 
for all registers in PIPE_MBUS_DBOX_CTL
URL   : https://patchwork.freedesktop.org/series/101937/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/4] drm/i915/display/tgl+: Set default values 
for all registers in PIPE_MBUS_DBOX_CTL
URL   : https://patchwork.freedesktop.org/series/101937/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/4] drm/i915/display/tgl+: Set default values 
for all registers in PIPE_MBUS_DBOX_CTL
URL   : https://patchwork.freedesktop.org/series/101937/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
736622c4b868 drm/i915/display/tgl+: Set default values for all registers in 
PIPE_MBUS_DBOX_CTL
-:74: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#74: FILE: drivers/gpu/drm/i915/i915_reg.h::
+#define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x)  
REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x)

-:76: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#76: FILE: drivers/gpu/drm/i915/i915_reg.h:1113:
+#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x)
REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x)

total: 0 errors, 2 warnings, 0 checks, 55 lines checked
3b609035e3bc drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits
d26e768a064e drm/i915/display: Add HAS_MBUS_JOINING
34348e3c5a7f drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL

[Intel-gfx] [PATCH v4 4/4] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL

[José Roberto de Souza]

PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being
enabled but that could potentially cause issues as it could have
mismatching values while pipes are being enabled.

So here moving the PIPE_MBUS_DBOX_CTL programming of all pipes to be
executed before the function that enables all pipes, leaving all pipes
with a matching A_CREDIT value.

While at it, also moving it to intel_pm.c as we are trying to reduce
the gigantic size of intel_display.c and intel_pm.c have other MBUS
programing sequences.

v2:
- do not program PIPE_MBUS_DBOX_CTL if pipe will not be active or
when it do not needs modeset
- remove the checks to wait a vblank

v3:
- checking if dbuf state is present in state before using it

v4:
- removing redundant checks
- calling intel_atomic_get_new_dbuf_state instead of
intel_atomic_get_dbuf_state

BSpec: 49213
BSpec: 50343
Cc: Ville Syrjälä 
Cc: Stanislav Lisovskiy 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/display/intel_display.c | 41 +--
 drivers/gpu/drm/i915/intel_pm.c  | 52 
 drivers/gpu/drm/i915/intel_pm.h  |  1 +
 3 files changed, 54 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 389a3c988dc6f..1bd869af15bf8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1825,39 +1825,6 @@ static void glk_pipe_scaler_clock_gating_wa(struct 
drm_i915_private *dev_priv,
intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
 }
 
-static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
-{
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   enum pipe pipe = crtc->pipe;
-   u32 val = 0;
-
-   if (DISPLAY_VER(dev_priv) >= 12) {
-   val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
-   val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
-   val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
-   }
-
-   /* Wa_22010947358:adl-p */
-   if (IS_ALDERLAKE_P(dev_priv))
-   val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
-MBUS_DBOX_A_CREDIT(4);
-   else
-   val |= MBUS_DBOX_A_CREDIT(2);
-
-   if (IS_ALDERLAKE_P(dev_priv)) {
-   val |= MBUS_DBOX_BW_CREDIT(2);
-   val |= MBUS_DBOX_B_CREDIT(8);
-   } else if (DISPLAY_VER(dev_priv) >= 12) {
-   val |= MBUS_DBOX_BW_CREDIT(2);
-   val |= MBUS_DBOX_B_CREDIT(12);
-   } else {
-   val |= MBUS_DBOX_BW_CREDIT(1);
-   val |= MBUS_DBOX_B_CREDIT(8);
-   }
-
-   intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
-}
-
 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -1994,13 +1961,6 @@ static void hsw_crtc_enable(struct intel_atomic_state 
*state,
 
intel_initial_watermarks(state, crtc);
 
-   if (DISPLAY_VER(dev_priv) >= 11) {
-   const struct intel_dbuf_state *dbuf_state =
-   intel_atomic_get_new_dbuf_state(state);
-
-   icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus);
-   }
-
if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
intel_crtc_vblank_on(new_crtc_state);
 
@@ -8612,6 +8572,7 @@ static void intel_atomic_commit_tail(struct 
intel_atomic_state *state)
intel_encoders_update_prepare(state);
 
intel_dbuf_pre_plane_update(state);
+   intel_mbus_dbox_update(state);
 
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (new_crtc_state->do_async_flip)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e60c02d760ffa..90ea5b87b52bb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8258,3 +8258,55 @@ void intel_dbuf_post_plane_update(struct 
intel_atomic_state *state)
gen9_dbuf_slices_update(dev_priv,
new_dbuf_state->enabled_slices);
 }
+
+void intel_mbus_dbox_update(struct intel_atomic_state *state)
+{
+   struct drm_i915_private *i915 = to_i915(state->base.dev);
+   struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
+   struct intel_crtc_state *new_crtc_state;
+   struct intel_crtc *crtc;
+   u32 val = 0;
+   int i;
+
+   if (DISPLAY_VER(i915) < 11)
+   return;
+
+   new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
+   old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
+   if (!new_dbuf_state ||
+   (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
+new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
+   return;
+
+   if (DISPLAY_VER(i915) >= 12) {
+   val |= MBUS_DBOX_B2B_TRANSACTION

[Intel-gfx] [PATCH v4 3/4] drm/i915/display: Add HAS_MBUS_JOINING

[José Roberto de Souza]

This will make easy to extend MBUS joining support to future platforms
that also supports this feature.

Reviewed-by: Ville Syrjälä 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_drv.h | 2 ++
 drivers/gpu/drm/i915/intel_pm.c | 6 +++---
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 217c09422711b..d7f4a95006c0d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1387,6 +1387,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_PERCTX_PREEMPT_CTRL(i915) \
((GRAPHICS_VER(i915) >= 9) &&  GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
 
+#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
+
 static inline bool run_as_guest(void)
 {
return !hypervisor_is_type(X86_HYPER_NATIVE);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2c3cd4d775daf..e60c02d760ffa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6038,7 +6038,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
return ret;
}
 
-   if (IS_ALDERLAKE_P(dev_priv))
+   if (HAS_MBUS_JOINING(dev_priv))
new_dbuf_state->joined_mbus =
adlp_check_mbus_joined(new_dbuf_state->active_pipes);
 
@@ -6530,7 +6530,7 @@ void skl_wm_get_hw_state(struct drm_i915_private 
*dev_priv)
to_intel_dbuf_state(dev_priv->dbuf.obj.state);
struct intel_crtc *crtc;
 
-   if (IS_ALDERLAKE_P(dev_priv))
+   if (HAS_MBUS_JOINING(dev_priv))
dbuf_state->joined_mbus = intel_de_read(dev_priv, MBUS_CTL) & 
MBUS_JOIN;
 
for_each_intel_crtc(&dev_priv->drm, crtc) {
@@ -8192,7 +8192,7 @@ static void update_mbus_pre_enable(struct 
intel_atomic_state *state)
const struct intel_dbuf_state *dbuf_state =
intel_atomic_get_new_dbuf_state(state);
 
-   if (!IS_ALDERLAKE_P(dev_priv))
+   if (!HAS_MBUS_JOINING(dev_priv))
return;
 
/*
-- 
2.35.1

[Intel-gfx] [PATCH v4 2/4] drm/i915/display/adlp: Adjust MBUS DBOX BW and B credits

[José Roberto de Souza]

From: Caz Yokoyama 

Alderlake-P has different MBUS DBOX BW and B credits than other
platforms, so here setting it properly.

BSpec: 49213
BSpec: 50343
Cc: Matt Roper 
Cc: Stanislav Lisovskiy 
Cc: Jani Nikula 
Cc: Ville Syrjälä 
Signed-off-by: Caz Yokoyama 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/display/intel_display.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 234f363aad651..389a3c988dc6f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1844,7 +1844,10 @@ static void icl_pipe_mbus_enable(struct intel_crtc 
*crtc, bool joined_mbus)
else
val |= MBUS_DBOX_A_CREDIT(2);
 
-   if (DISPLAY_VER(dev_priv) >= 12) {
+   if (IS_ALDERLAKE_P(dev_priv)) {
+   val |= MBUS_DBOX_BW_CREDIT(2);
+   val |= MBUS_DBOX_B_CREDIT(8);
+   } else if (DISPLAY_VER(dev_priv) >= 12) {
val |= MBUS_DBOX_BW_CREDIT(2);
val |= MBUS_DBOX_B_CREDIT(12);
} else {
-- 
2.35.1

[Intel-gfx] [PATCH v4 1/4] drm/i915/display/tgl+: Set default values for all registers in PIPE_MBUS_DBOX_CTL

[José Roberto de Souza]

MBUS_DBOX_B2B_TRANSACTIONS_MAX, MBUS_DBOX_B2B_TRANSACTIONS_DELAY and
MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN were being programmed with
zeros while specification has different default values for this
registers in display 12 and newer.

While at it also converting all MBUS_DBOX macros to use REG_* macros.

BSpec: 50343
BSpec: 20231
Cc: Ville Syrjälä 
Cc: Stanislav Lisovskiy 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/display/intel_display.c | 13 +++---
 drivers/gpu/drm/i915/i915_reg.h  | 26 
 2 files changed, 26 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 28bfb73ae6471..234f363aad651 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1829,13 +1829,20 @@ static void icl_pipe_mbus_enable(struct intel_crtc 
*crtc, bool joined_mbus)
 {
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
-   u32 val;
+   u32 val = 0;
+
+   if (DISPLAY_VER(dev_priv) >= 12) {
+   val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
+   val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
+   val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
+   }
 
/* Wa_22010947358:adl-p */
if (IS_ALDERLAKE_P(dev_priv))
-   val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : 
MBUS_DBOX_A_CREDIT(4);
+   val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
+MBUS_DBOX_A_CREDIT(4);
else
-   val = MBUS_DBOX_A_CREDIT(2);
+   val |= MBUS_DBOX_A_CREDIT(2);
 
if (DISPLAY_VER(dev_priv) >= 12) {
val |= MBUS_DBOX_BW_CREDIT(2);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a0d652f19ff93..f47f9dfc9b0ce 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1103,16 +1103,22 @@
 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
 #define MBUS_ABOX_BT_CREDIT_POOL1(x)   ((x) << 0)
 
-#define _PIPEA_MBUS_DBOX_CTL   0x7003C
-#define _PIPEB_MBUS_DBOX_CTL   0x7103C
-#define PIPE_MBUS_DBOX_CTL(pipe)   _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
-  _PIPEB_MBUS_DBOX_CTL)
-#define MBUS_DBOX_BW_CREDIT_MASK   (3 << 14)
-#define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
-#define MBUS_DBOX_B_CREDIT_MASK(0x1F << 8)
-#define MBUS_DBOX_B_CREDIT(x)  ((x) << 8)
-#define MBUS_DBOX_A_CREDIT_MASK(0xF << 0)
-#define MBUS_DBOX_A_CREDIT(x)  ((x) << 0)
+#define _PIPEA_MBUS_DBOX_CTL   0x7003C
+#define _PIPEB_MBUS_DBOX_CTL   0x7103C
+#define PIPE_MBUS_DBOX_CTL(pipe)   _MMIO_PIPE(pipe, 
_PIPEA_MBUS_DBOX_CTL, \
+  _PIPEB_MBUS_DBOX_CTL)
+#define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASKREG_GENMASK(24, 20)
+#define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x)  
REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x)
+#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK  REG_GENMASK(19, 17)
+#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x)
REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x)
+#define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK  REG_GENMASK(19, 17)
+#define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16)
+#define MBUS_DBOX_BW_CREDIT_MASK   REG_GENMASK(15, 14)
+#define MBUS_DBOX_BW_CREDIT(x) 
REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)
+#define MBUS_DBOX_B_CREDIT_MASKREG_GENMASK(12, 8)
+#define MBUS_DBOX_B_CREDIT(x)  
REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)
+#define MBUS_DBOX_A_CREDIT_MASKREG_GENMASK(3, 0)
+#define MBUS_DBOX_A_CREDIT(x)  
REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)
 
 #define MBUS_UBOX_CTL  _MMIO(0x4503C)
 #define MBUS_BBOX_CTL_S1   _MMIO(0x45040)
-- 
2.35.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Add Wa_22014226127 (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/dg2: Add Wa_22014226127 (rev6)
URL   : https://patchwork.freedesktop.org/series/101792/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22725


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/index.html

Participating hosts (43 -> 44)
--

  Additional (7): fi-cml-u2 fi-tgl-u2 fi-skl-guc fi-cfl-8700k bat-adlp-4 
fi-ivb-3770 fi-pnv-d510 
  Missing(6): shard-tglu bat-dg2-8 fi-bsw-cyan fi-kbl-7500u shard-rkl 
fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22725:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}:   [FAIL][1] ([i915#5323]) -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-rpls-2/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/bat-rpls-2/igt@i915_pm_...@module-reload.html

  
Known issues


  Here are the changes found in Patchwork_22725 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka:   NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#109315]) +17 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html

  * igt@amdgpu/amd_basic@userptr:
- fi-cfl-8700k:   NOTRUN -> [SKIP][5] ([fdo#109271]) +29 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/fi-cfl-8700k/igt@amdgpu/amd_ba...@userptr.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][6] ([i915#1208]) +1 similar issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][7] ([fdo#109271]) +57 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
- fi-tgl-u2:  NOTRUN -> [SKIP][8] ([i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html
- fi-cfl-8700k:   NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/fi-cfl-8700k/igt@gem_huc_c...@huc-copy.html
- fi-cml-u2:  NOTRUN -> [SKIP][10] ([i915#2190])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/fi-cml-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-cml-u2:  NOTRUN -> [SKIP][11] ([i915#4613]) +3 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/fi-cml-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
- fi-skl-guc: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/fi-skl-guc/igt@gem_lmem_swapp...@random-engines.html
- fi-ivb-3770:NOTRUN -> [SKIP][13] ([fdo#109271]) +36 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/fi-ivb-3770/igt@gem_lmem_swapp...@random-engines.html
- fi-cfl-8700k:   NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/fi-cfl-8700k/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2:  NOTRUN -> [SKIP][15] ([i915#4613]) +3 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/fi-tgl-u2/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-n3050:   [PASS][16] -> [INCOMPLETE][17] ([i915#2940])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html

  * igt@kms_busy@basic@flip:
- fi-tgl-u2:  NOTRUN -> [DMESG-WARN][18] ([i915#402])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22725/fi-tgl-u2/igt@kms_busy@ba...@flip.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-u2:  NOTRUN -> [SKIP][19] ([fdo#109284] / [fdo#111827]) +8 
similar issues
   [19]: 
https://intel-gfx-ci.

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dg2: Add Wa_22014226127 (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/dg2: Add Wa_22014226127 (rev6)
URL   : https://patchwork.freedesktop.org/series/101792/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/edid: cleanup and refactoring around validity checks

[Patchwork]

== Series Details ==

Series: drm/edid: cleanup and refactoring around validity checks
URL   : https://patchwork.freedesktop.org/series/101931/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22724_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 10)
--

  Missing(1): shard-tglu 

Known issues


  Here are the changes found in Patchwork_22724_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +1 
similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-queued.html

  * igt@gem_ctx_persistence@smoketest:
- shard-apl:  NOTRUN -> [FAIL][2] ([i915#5099])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/shard-apl6/igt@gem_ctx_persiste...@smoketest.html

  * igt@gem_ctx_sseu@invalid-sseu:
- shard-tglb: NOTRUN -> [SKIP][3] ([i915#280])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/shard-tglb6/igt@gem_ctx_s...@invalid-sseu.html

  * igt@gem_eio@in-flight-contexts-immediate:
- shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb1/igt@gem_...@in-flight-contexts-immediate.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/shard-tglb3/igt@gem_...@in-flight-contexts-immediate.html

  * igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][6] -> [TIMEOUT][7] ([i915#2481] / [i915#3070])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb1/igt@gem_...@unwedge-stress.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/shard-iclb6/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-skl:  [PASS][8] -> [INCOMPLETE][9] ([i915#4547])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl2/igt@gem_exec_capture@p...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/shard-skl3/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar 
issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/shard-iclb4/igt@gem_exec_fair@basic-pace-s...@rcs0.html
- shard-glk:  [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk8/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/shard-glk6/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_schedule@submit-early-slice@vcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][14] ([i915#3797])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/shard-skl1/igt@gem_exec_schedule@submit-early-sl...@vcs0.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-tglb: NOTRUN -> [SKIP][15] ([i915#4613])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/shard-tglb6/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@verify-random:
- shard-skl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/shard-skl10/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_pread@exhaustion:
- shard-snb:  NOTRUN -> [WARN][17] ([i915#2658])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/shard-snb2/igt@gem_pr...@exhaustion.html

  * igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#4270])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/shard-iclb7/igt@gem_...@reject-modify-context-protection-off-2.html

  * igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#4270])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/shard-tglb6/igt@gem_...@verify-pxp-stale-buf-optout-execution.html

  * igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#768])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/shard-iclb7/igt@gem_render_c...@linear-to-vebox-y-tiled.html

  * igt@gen7_exec_parse@basic-allowed:
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#109289]) +1 similar issue
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/shard-tglb6/igt@gen7_exec_pa...@basic-allowed.html

  * igt@gen9_exec_parse@allowed-single:
- shard-skl:  [PASS][22] -> [DMESG-WARN]

Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL

[Ville Syrjälä]

On Mon, Mar 28, 2022 at 12:16:17PM -0700, José Roberto de Souza wrote:
> PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being
> enabled but that could potentially cause issues as it could have
> mismatching values while pipes are being enabled.
> 
> So here moving the PIPE_MBUS_DBOX_CTL programming of all pipes to be
> executed before the function that enables all pipes, leaving all pipes
> with a matching A_CREDIT value.
> 
> While at it, also moving it to intel_pm.c as we are trying to reduce
> the gigantic size of it and intel_pm.c have other MBUS programing
> sequences.
> 
> v2:
> - do not program PIPE_MBUS_DBOX_CTL if pipe will not be active or
> when it do not needs modeset
> - remove the checks to wait a vblank
> 
> v3:
> - checking if dbuf state is present in state before using it
> 
> BSpec: 49213
> BSpec: 50343
> Cc: Ville Syrjälä 
> Cc: Stanislav Lisovskiy 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 37 +-
>  drivers/gpu/drm/i915/intel_pm.c  | 51 
>  drivers/gpu/drm/i915/intel_pm.h  |  1 +
>  3 files changed, 53 insertions(+), 36 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 078ada041e1cd..4e8afd94e58d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1824,35 +1824,6 @@ static void glk_pipe_scaler_clock_gating_wa(struct 
> drm_i915_private *dev_priv,
>   intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
>  }
>  
> -static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
> -{
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - enum pipe pipe = crtc->pipe;
> - u32 val;
> -
> - val = intel_de_read(dev_priv, PIPE_MBUS_DBOX_CTL(pipe));
> - val &= ~MBUS_DBOX_A_CREDIT_MASK;
> - /* Wa_22010947358:adl-p */
> - if (IS_ALDERLAKE_P(dev_priv))
> - val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) : 
> MBUS_DBOX_A_CREDIT(4);
> - else
> - val |= MBUS_DBOX_A_CREDIT(2);
> -
> - val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK);
> - if (IS_ALDERLAKE_P(dev_priv)) {
> - val |= MBUS_DBOX_BW_CREDIT(2);
> - val |= MBUS_DBOX_B_CREDIT(8);
> - } else if (DISPLAY_VER(dev_priv) >= 12) {
> - val |= MBUS_DBOX_BW_CREDIT(2);
> - val |= MBUS_DBOX_B_CREDIT(12);
> - } else {
> - val |= MBUS_DBOX_BW_CREDIT(1);
> - val |= MBUS_DBOX_B_CREDIT(8);
> - }
> -
> - intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
> -}
> -
>  static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
>  {
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -1988,13 +1959,6 @@ static void hsw_crtc_enable(struct intel_atomic_state 
> *state,
>  
>   intel_initial_watermarks(state, crtc);
>  
> - if (DISPLAY_VER(dev_priv) >= 11) {
> - const struct intel_dbuf_state *dbuf_state =
> - intel_atomic_get_new_dbuf_state(state);
> -
> - icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus);
> - }
> -
>   if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
>   intel_crtc_vblank_on(new_crtc_state);
>  
> @@ -8586,6 +8550,7 @@ static void intel_atomic_commit_tail(struct 
> intel_atomic_state *state)
>   intel_encoders_update_prepare(state);
>  
>   intel_dbuf_pre_plane_update(state);
> + intel_mbus_dbox_update(state);
>  
>   for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>   if (new_crtc_state->do_async_flip)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e60c02d760ffa..8881944c80c5b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8258,3 +8258,54 @@ void intel_dbuf_post_plane_update(struct 
> intel_atomic_state *state)
>   gen9_dbuf_slices_update(dev_priv,
>   new_dbuf_state->enabled_slices);
>  }
> +
> +void intel_mbus_dbox_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
> + struct intel_crtc_state *new_crtc_state;
> + struct intel_crtc *crtc;
> + int i;
> +
> + if (DISPLAY_VER(i915) < 11 || !state->modeset)
> + return;

The state->modeset check seems redundant.

> +
> + new_dbuf_state = intel_atomic_get_dbuf_state(state);

get_new

> + old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
> + if (!new_dbuf_state || !old_dbuf_state ||

If you have one you have the other, so no need to check both old and new
presence.

> + (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
> +  new_dbuf_state->active_pipes == old_

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Add Wa_22014226127 (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/dg2: Add Wa_22014226127 (rev5)
URL   : https://patchwork.freedesktop.org/series/101792/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22723


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/index.html

Participating hosts (43 -> 48)
--

  Additional (8): fi-tgl-u2 fi-skl-guc bat-adlm-1 fi-icl-u2 fi-cfl-8700k 
bat-adlp-4 fi-ivb-3770 fi-pnv-d510 
  Missing(3): shard-rkl fi-bsw-cyan fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_22723 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka:   NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#109315]) +17 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html

  * igt@amdgpu/amd_basic@userptr:
- fi-cfl-8700k:   NOTRUN -> [SKIP][3] ([fdo#109271]) +29 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-cfl-8700k/igt@amdgpu/amd_ba...@userptr.html

  * igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2:  NOTRUN -> [SKIP][4] ([fdo#109315]) +17 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html

  * igt@gem_exec_suspend@basic-s0@smem:
- fi-glk-dsi: [PASS][5] -> [DMESG-WARN][6] ([i915#2943])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-glk-dsi/igt@gem_exec_suspend@basic...@smem.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-glk-dsi/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][7] ([fdo#109271]) +57 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
- fi-tgl-u2:  NOTRUN -> [SKIP][8] ([i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html
- fi-cfl-8700k:   NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-cfl-8700k/igt@gem_huc_c...@huc-copy.html
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([i915#2190])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][11] ([i915#4613]) +3 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
- fi-skl-guc: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-skl-guc/igt@gem_lmem_swapp...@random-engines.html
- fi-ivb-3770:NOTRUN -> [SKIP][13] ([fdo#109271]) +36 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-ivb-3770/igt@gem_lmem_swapp...@random-engines.html
- fi-cfl-8700k:   NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-cfl-8700k/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2:  NOTRUN -> [SKIP][15] ([i915#4613]) +3 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-tgl-u2/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_ringfill@basic-all:
- bat-dg1-6:  [PASS][16] -> [TIMEOUT][17] ([i915#5199])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg1-6/igt@gem_ringf...@basic-all.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/bat-dg1-6/igt@gem_ringf...@basic-all.html

  * igt@i915_selftest@live@execlists:
- fi-kbl-soraka:  [PASS][18] -> [INCOMPLETE][19] ([i915#794])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gem_contexts:
- bat-dg1-6:  [PASS][20] -> [INCOMPLETE][21] ([i915#5458])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg1-6/igt@i915_selftest@live@gem_contexts.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/bat-dg1-6/igt@i915_selftest@live@gem_contexts.html

  * i

[Intel-gfx] [drm-tip:drm-tip 4/8] drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:200:33: error: no member named 'tbo' in 'struct ttm_range_mgr_node'

[kernel test robot]

tree:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
head:   a8459e73b79b7c55405331f36fe8a48e1bad5c33
commit: 752f483905202334e91d2d5b87a3904df72aa147 [4/8] Merge remote-tracking 
branch 'drm-misc/drm-misc-next' into drm-tip
config: s390-randconfig-r006-20220327 
(https://download.01.org/0day-ci/archive/20220330/202203300449.ngue9zxn-...@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 
0f6d9501cf49ce02937099350d08f20c4af86f3d)
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# install s390 cross compiling tool for clang build
# apt-get install binutils-s390x-linux-gnu
git remote add drm-tip git://anongit.freedesktop.org/drm/drm-tip
git fetch --no-tags drm-tip drm-tip
git checkout 752f483905202334e91d2d5b87a3904df72aa147
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 
O=build_dir ARCH=s390 SHELL=/bin/bash drivers/gpu/drm/amd/amdgpu/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

   In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:25:
   In file included from include/drm/ttm/ttm_range_manager.h:6:
   In file included from include/drm/ttm/ttm_resource.h:31:
   In file included from include/linux/iosys-map.h:9:
   In file included from include/linux/io.h:13:
   In file included from arch/s390/include/asm/io.h:75:
   include/asm-generic/io.h:464:31: warning: performing pointer arithmetic on a 
null pointer has undefined behavior [-Wnull-pointer-arithmetic]
   val = __raw_readb(PCI_IOBASE + addr);
 ~~ ^
   include/asm-generic/io.h:477:61: warning: performing pointer arithmetic on a 
null pointer has undefined behavior [-Wnull-pointer-arithmetic]
   val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
   ~~ ^
   include/uapi/linux/byteorder/big_endian.h:37:59: note: expanded from macro 
'__le16_to_cpu'
   #define __le16_to_cpu(x) __swab16((__force __u16)(__le16)(x))
 ^
   include/uapi/linux/swab.h:102:54: note: expanded from macro '__swab16'
   #define __swab16(x) (__u16)__builtin_bswap16((__u16)(x))
^
   In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:25:
   In file included from include/drm/ttm/ttm_range_manager.h:6:
   In file included from include/drm/ttm/ttm_resource.h:31:
   In file included from include/linux/iosys-map.h:9:
   In file included from include/linux/io.h:13:
   In file included from arch/s390/include/asm/io.h:75:
   include/asm-generic/io.h:490:61: warning: performing pointer arithmetic on a 
null pointer has undefined behavior [-Wnull-pointer-arithmetic]
   val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));
   ~~ ^
   include/uapi/linux/byteorder/big_endian.h:35:59: note: expanded from macro 
'__le32_to_cpu'
   #define __le32_to_cpu(x) __swab32((__force __u32)(__le32)(x))
 ^
   include/uapi/linux/swab.h:115:54: note: expanded from macro '__swab32'
   #define __swab32(x) (__u32)__builtin_bswap32((__u32)(x))
^
   In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:25:
   In file included from include/drm/ttm/ttm_range_manager.h:6:
   In file included from include/drm/ttm/ttm_resource.h:31:
   In file included from include/linux/iosys-map.h:9:
   In file included from include/linux/io.h:13:
   In file included from arch/s390/include/asm/io.h:75:
   include/asm-generic/io.h:501:33: warning: performing pointer arithmetic on a 
null pointer has undefined behavior [-Wnull-pointer-arithmetic]
   __raw_writeb(value, PCI_IOBASE + addr);
   ~~ ^
   include/asm-generic/io.h:511:59: warning: performing pointer arithmetic on a 
null pointer has undefined behavior [-Wnull-pointer-arithmetic]
   __raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);
 ~~ ^
   include/asm-generic/io.h:521:59: warning: performing pointer arithmetic on a 
null pointer has undefined behavior [-Wnull-pointer-arithmetic]
   __raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);
 ~~ ^
   include/asm-generic/io.h:609:20: warning: performing pointer arithmetic on a 
null pointer has undefined behavior [-Wnull-pointer-arithmetic]
   readsb

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/ats-m: add ATS-M platform info

[Matt Roper]

On Tue, Mar 29, 2022 at 06:17:11AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with [1/2] drm/i915/ats-m: add ATS-M platform info
> URL   : https://patchwork.freedesktop.org/series/101907/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_11415_full -> Patchwork_22711_full
> 
> 
> Summary
> ---
> 
>   **SUCCESS**
> 
>   No regressions found.

Patch #1 applied to drm-intel-next and #2 applied to topic/core-for-CI.
Thanks for the reviews.


Matt

> 
>   
> 
> Participating hosts (10 -> 10)
> --
> 
>   No changes in participating hosts
> 
> Known issues
> 
> 
>   Here are the changes found in Patchwork_22711_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@api_intel_bb@blit-noreloc-purge-cache:
> - shard-glk:  [PASS][1] -> [INCOMPLETE][2] ([i915#5441]) +2 
> similar issues
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11415/shard-glk6/igt@api_intel...@blit-noreloc-purge-cache.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-glk7/igt@api_intel...@blit-noreloc-purge-cache.html
> 
>   * igt@core_hotunplug@unbind-rebind:
> - shard-tglb: NOTRUN -> [INCOMPLETE][3] ([i915#1373] / 
> [i915#5441])
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-tglb7/igt@core_hotunp...@unbind-rebind.html
> - shard-iclb: NOTRUN -> [INCOMPLETE][4] ([i915#1373] / 
> [i915#5441])
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-iclb5/igt@core_hotunp...@unbind-rebind.html
> 
>   * igt@feature_discovery@chamelium:
> - shard-tglb: NOTRUN -> [SKIP][5] ([fdo#111827])
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-tglb6/igt@feature_discov...@chamelium.html
> 
>   * igt@feature_discovery@psr2:
> - shard-iclb: NOTRUN -> [SKIP][6] ([i915#658]) +1 similar issue
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-iclb8/igt@feature_discov...@psr2.html
> 
>   * igt@gem_create@create-massive:
> - shard-iclb: NOTRUN -> [DMESG-WARN][7] ([i915#4991])
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-iclb7/igt@gem_cre...@create-massive.html
> 
>   * igt@gem_ctx_persistence@legacy-engines-mixed:
> - shard-snb:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099])
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-snb4/igt@gem_ctx_persiste...@legacy-engines-mixed.html
> 
>   * igt@gem_eio@unwedge-stress:
> - shard-tglb: NOTRUN -> [TIMEOUT][9] ([i915#3063] / [i915#3648])
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-tglb6/igt@gem_...@unwedge-stress.html
> 
>   * igt@gem_exec_balancer@parallel:
> - shard-iclb: NOTRUN -> [SKIP][10] ([i915#4525]) +1 similar issue
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-iclb6/igt@gem_exec_balan...@parallel.html
> 
>   * igt@gem_exec_fair@basic-none-rrul@rcs0:
> - shard-glk:  NOTRUN -> [FAIL][11] ([i915#2842]) +1 similar issue
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-glk8/igt@gem_exec_fair@basic-none-r...@rcs0.html
> - shard-tglb: NOTRUN -> [FAIL][12] ([i915#2842])
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-tglb7/igt@gem_exec_fair@basic-none-r...@rcs0.html
> 
>   * igt@gem_exec_params@rsvd2-dirt:
> - shard-tglb: NOTRUN -> [SKIP][13] ([fdo#109283])
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-tglb7/igt@gem_exec_par...@rsvd2-dirt.html
> 
>   * igt@gem_exec_schedule@u-semaphore-user:
> - shard-snb:  NOTRUN -> [SKIP][14] ([fdo#109271]) +55 similar 
> issues
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-snb4/igt@gem_exec_sched...@u-semaphore-user.html
> 
>   * igt@gem_huc_copy@huc-copy:
> - shard-apl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190])
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-apl1/igt@gem_huc_c...@huc-copy.html
> - shard-glk:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#2190])
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-glk8/igt@gem_huc_c...@huc-copy.html
> 
>   * igt@gem_lmem_swapping@heavy-verify-multi:
> - shard-skl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613])
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-skl10/igt@gem_lmem_swapp...@heavy-verify-multi.html
> 
>   * igt@gem_lmem_swapping@parallel-random-engines:
> - shard-glk:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) 
> +1 similar issue
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22711/shard-glk5/igt@gem_lmem_swapp...@parallel-random-engi

[Intel-gfx] [drm-tip:drm-tip 4/8] drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:200:45: error: 'struct ttm_range_mgr_node' has no member named 'tbo'

[kernel test robot]

tree:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
head:   a8459e73b79b7c55405331f36fe8a48e1bad5c33
commit: 752f483905202334e91d2d5b87a3904df72aa147 [4/8] Merge remote-tracking 
branch 'drm-misc/drm-misc-next' into drm-tip
config: parisc-randconfig-r003-20220327 
(https://download.01.org/0day-ci/archive/20220330/202203300408.sl8g1bqn-...@intel.com/config)
compiler: hppa-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
git remote add drm-tip git://anongit.freedesktop.org/drm/drm-tip
git fetch --no-tags drm-tip drm-tip
git checkout 752f483905202334e91d2d5b87a3904df72aa147
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross 
O=build_dir ARCH=parisc SHELL=/bin/bash drivers/gpu/drm/amd/amdgpu/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c: In function 
'amdgpu_gtt_mgr_recover':
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:200:45: error: 'struct 
>> ttm_range_mgr_node' has no member named 'tbo'
 200 | amdgpu_ttm_recover_gart(node->tbo);
 | ^~


vim +200 drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c

bb990bb09235a3 Christian König 2016-09-09  182  
a614b336f1c16d Christian König 2021-02-11  183  /**
a614b336f1c16d Christian König 2021-02-11  184   * amdgpu_gtt_mgr_recover - 
re-init gart
a614b336f1c16d Christian König 2021-02-11  185   *
1dd8b1b987fad9 Nirmoy Das  2022-01-07  186   * @mgr: amdgpu_gtt_mgr pointer
a614b336f1c16d Christian König 2021-02-11  187   *
a614b336f1c16d Christian König 2021-02-11  188   * Re-init the gart for each 
known BO in the GTT.
a614b336f1c16d Christian König 2021-02-11  189   */
1b08dfb889b2c5 Christian König 2022-01-18  190  void 
amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr)
c1c7ce8f5687bb Christian König 2017-10-16  191  {
77ef271faee9c3 Christian König 2021-07-16  192  struct 
ttm_range_mgr_node *node;
c1c7ce8f5687bb Christian König 2017-10-16  193  struct drm_mm_node 
*mm_node;
1dd8b1b987fad9 Nirmoy Das  2022-01-07  194  struct amdgpu_device 
*adev;
c1c7ce8f5687bb Christian König 2017-10-16  195  
19a1d9350be632 Nirmoy Das  2021-05-28  196  adev = 
container_of(mgr, typeof(*adev), mman.gtt_mgr);
c1c7ce8f5687bb Christian König 2017-10-16  197  spin_lock(&mgr->lock);
c1c7ce8f5687bb Christian König 2017-10-16  198  
drm_mm_for_each_node(mm_node, &mgr->mm) {
77ef271faee9c3 Christian König 2021-07-16  199  node = 
container_of(mm_node, typeof(*node), mm_nodes[0]);
1b08dfb889b2c5 Christian König 2022-01-18 @200  
amdgpu_ttm_recover_gart(node->tbo);
c1c7ce8f5687bb Christian König 2017-10-16  201  }
c1c7ce8f5687bb Christian König 2017-10-16  202  spin_unlock(&mgr->lock);
c1c7ce8f5687bb Christian König 2017-10-16  203  
19a1d9350be632 Nirmoy Das  2021-05-28  204  
amdgpu_gart_invalidate_tlb(adev);
c1c7ce8f5687bb Christian König 2017-10-16  205  }
c1c7ce8f5687bb Christian König 2017-10-16  206  

:: The code at line 200 was first introduced by commit
:: 1b08dfb889b2c584b444538c9500af24ba0a6dc7 drm/amdgpu: remove gart.ready 
flag

:: TO: Christian König 
:: CC: Alex Deucher 

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: cleanup and refactoring around validity checks

[Patchwork]

== Series Details ==

Series: drm/edid: cleanup and refactoring around validity checks
URL   : https://patchwork.freedesktop.org/series/101931/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22724


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/index.html

Participating hosts (43 -> 44)
--

  Additional (6): fi-tgl-u2 fi-skl-guc bat-adlm-1 fi-cfl-8700k bat-adlp-4 
fi-ivb-3770 
  Missing(5): fi-kbl-soraka shard-tglu fi-bsw-cyan shard-rkl fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_22724 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka:   NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#109315]) +17 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html

  * igt@amdgpu/amd_basic@userptr:
- fi-cfl-8700k:   NOTRUN -> [SKIP][3] ([fdo#109271]) +29 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-cfl-8700k/igt@amdgpu/amd_ba...@userptr.html

  * igt@gem_huc_copy@huc-copy:
- fi-tgl-u2:  NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html
- fi-cfl-8700k:   NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-cfl-8700k/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
- fi-skl-guc: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-skl-guc/igt@gem_lmem_swapp...@random-engines.html
- fi-ivb-3770:NOTRUN -> [SKIP][7] ([fdo#109271]) +36 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-ivb-3770/igt@gem_lmem_swapp...@random-engines.html
- fi-cfl-8700k:   NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-cfl-8700k/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2:  NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-tgl-u2/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][10] -> [INCOMPLETE][11] ([i915#3921])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_busy@basic@flip:
- fi-tgl-u2:  NOTRUN -> [DMESG-WARN][12] ([i915#402])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-tgl-u2/igt@kms_busy@ba...@flip.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-u2:  NOTRUN -> [SKIP][13] ([fdo#109284] / [fdo#111827]) +8 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-tgl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-skl-guc: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-skl-guc/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-cfl-8700k:   NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-cfl-8700k/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-ivb-3770:NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-ivb-3770/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2:  NOTRUN -> [SKIP][17] ([i915#4103]) +1 similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-tgl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2:  NOTRUN -> [SKIP][18] ([fdo#109285])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22724/fi-tgl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-guc: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#53

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Add Wa_22014226127

[Patchwork]

== Series Details ==

Series: drm/i915/dg2: Add Wa_22014226127
URL   : https://patchwork.freedesktop.org/series/101792/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22684


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/index.html

Participating hosts (48 -> 44)
--

  Missing(4): fi-bdw-samus fi-tgl-1115g4 fi-bsw-cyan bat-adlp-4 

Known issues


  Here are the changes found in Patchwork_22684 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@core_hotunplug@unbind-rebind:
- fi-bsw-nick:NOTRUN -> [INCOMPLETE][1] ([i915#5441])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-bsw-nick/igt@core_hotunp...@unbind-rebind.html
- fi-cfl-8109u:   NOTRUN -> [INCOMPLETE][2] ([i915#5441])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-cfl-8109u/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_render_tiled_blits@basic:
- fi-cfl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#1982])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-cfl-guc/igt@gem_render_tiled_bl...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-cfl-guc/igt@gem_render_tiled_bl...@basic.html
- fi-ilk-650: NOTRUN -> [INCOMPLETE][5] ([i915#5441])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-ilk-650/igt@gem_render_tiled_bl...@basic.html
- fi-bsw-n3050:   [PASS][6] -> [INCOMPLETE][7] ([i915#5441])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-bsw-n3050/igt@gem_render_tiled_bl...@basic.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-bsw-n3050/igt@gem_render_tiled_bl...@basic.html
- fi-bsw-kefka:   [PASS][8] -> [INCOMPLETE][9] ([i915#5441])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-bsw-kefka/igt@gem_render_tiled_bl...@basic.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-bsw-kefka/igt@gem_render_tiled_bl...@basic.html
- fi-kbl-8809g:   [PASS][10] -> [INCOMPLETE][11] ([i915#5441])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-kbl-8809g/igt@gem_render_tiled_bl...@basic.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-kbl-8809g/igt@gem_render_tiled_bl...@basic.html
- fi-glk-dsi: [PASS][12] -> [INCOMPLETE][13] ([i915#5441])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-glk-dsi/igt@gem_render_tiled_bl...@basic.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-glk-dsi/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_softpin@allocator-basic:
- fi-snb-2520m:   NOTRUN -> [SKIP][14] ([fdo#109271]) +1 similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-snb-2520m/igt@gem_soft...@allocator-basic.html

  * igt@gem_tiled_blits@basic:
- fi-elk-e7500:   [PASS][15] -> [INCOMPLETE][16] ([i915#5441])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-elk-e7500/igt@gem_tiled_bl...@basic.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-elk-e7500/igt@gem_tiled_bl...@basic.html
- fi-skl-6700k2:  [PASS][17] -> [INCOMPLETE][18] ([i915#5441])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-skl-6700k2/igt@gem_tiled_bl...@basic.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-skl-6700k2/igt@gem_tiled_bl...@basic.html
- fi-blb-e6850:   [PASS][19] -> [INCOMPLETE][20] ([i915#5441])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-blb-e6850/igt@gem_tiled_bl...@basic.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-blb-e6850/igt@gem_tiled_bl...@basic.html
- fi-snb-2520m:   NOTRUN -> [INCOMPLETE][21] ([i915#5441])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-snb-2520m/igt@gem_tiled_bl...@basic.html

  * igt@kms_chamelium@vga-edid-read:
- fi-bsw-nick:NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-bsw-nick/igt@kms_chamel...@vga-edid-read.html

  * igt@kms_chamelium@vga-hpd-fast:
- fi-cfl-8109u:   NOTRUN -> [SKIP][23] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-cfl-8109u/igt@kms_chamel...@vga-hpd-fast.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-bsw-nick:NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#5341])
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-bsw-nick/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
- fi-bwr-2160:NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#5341])
   [25]: 
https://intel

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/dg2: Add relocation exception" (rev2)

[Lucas De Marchi]

On Thu, Mar 24, 2022 at 09:00:52AM +0100, Zbigniew Kempczyński wrote:

On Wed, Mar 23, 2022 at 06:51:17PM +, Patchwork wrote:

   Patch Details

   Series:  Revert "drm/i915/dg2: Add relocation exception" (rev2)
   URL: https://patchwork.freedesktop.org/series/101669/
   State:   failure
   Details: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22660/index.html

   CI Bug Log - changes from CI_DRM_11398 -> Patchwork_22660

Summary

   FAILURE

   Serious unknown changes coming with Patchwork_22660 absolutely need to be
   verified manually.

   If you think the reported changes have nothing to do with the changes
   introduced in Patchwork_22660, please notify your bug team to allow them
   to document this new failure mode, which will reduce false positives in
   CI.

   External URL:
   https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22660/index.html

Participating hosts (45 -> 42)

   Additional (5): bat-dg2-8 bat-dg2-9 fi-kbl-8809g bat-rpls-1 bat-jsl-1
   Missing (8): fi-kbl-soraka shard-tglu fi-hsw-4200u bat-adlm-1 fi-bsw-cyan
   fi-ctg-p8600 shard-rkl fi-bdw-samus

Possible new issues

   Here are the unknown changes that may have been introduced in
   Patchwork_22660:

  IGT changes

Possible regressions

 * igt@i915_selftest@live@hangcheck:
  * fi-hsw-4770: PASS -> INCOMPLETE


Unrelated to the change.



Suppressed

   The following results come from untrusted machines, tests, or statuses.
   They do not affect the overall result.

 * igt@gem_busy@busy@all:

  * {bat-dg2-8}: NOTRUN -> INCOMPLETE
 * igt@gem_exec_gttfill@basic:

  * {bat-dg2-9}: NOTRUN -> SKIP
 * igt@gem_exec_suspend@basic-s0@smem:

  * {bat-dg2-9}: NOTRUN -> FAIL +7 similar issues


For this one I got success on no-reloc code:

./gem_exec_suspend --run basic-S0
IGT-Version: 1.26-NO-GIT (x86_64) (Linux: 5.17.0+ x86_64)
Starting subtest: basic-S0
Starting dynamic subtest: smem
[cmd] rtcwake: assuming RTC uses UTC ...
rtcwake: wakeup from "freeze" using /dev/rtc0 at Thu Mar 24 07:56:03 2022
Dynamic subtest smem: SUCCESS (2.817s)
Starting dynamic subtest: lmem0
[cmd] rtcwake: assuming RTC uses UTC ...
rtcwake: wakeup from "freeze" using /dev/rtc0 at Thu Mar 24 07:56:20 2022
Dynamic subtest lmem0: SUCCESS (3.184s)
Subtest basic-S0: SUCCESS (6.001s)

@Lucas - please consider reverting relocations for dg2. This will speed
up our work and I've fixed yesterday all potential problems with no-reloc
for BAT on dg2.


Please trigger a re-test on this to compare to a recent drm-tip.
It would be bad if this then blocks the execution of other tests and we
drop the pass and execution rates.

Lucas De Marchi

Re: [Intel-gfx] [PATCH 2/2] topic/core-for-CI: Add ATS-M PCI IDs

[Lucas De Marchi]

On Mon, Mar 28, 2022 at 05:08:22PM -0700, Matt Roper wrote:

ATS-M device IDs should be considered to behave as additional DG2-G10
IDs (for ATS-M150) or DG2-G11 IDs (for ATS-M75).

Bspec: 44477
Signed-off-by: Matt Roper 



Acked-by: Lucas De Marchi 

Lucas De Marchi

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Add Wa_22014226127 (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/dg2: Add Wa_22014226127 (rev5)
URL   : https://patchwork.freedesktop.org/series/101792/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22723


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22723 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22723, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/index.html

Participating hosts (43 -> 46)
--

  Additional (8): fi-tgl-u2 fi-skl-guc bat-adlm-1 fi-icl-u2 fi-cfl-8700k 
bat-adlp-4 fi-ivb-3770 fi-pnv-d510 
  Missing(5): fi-kbl-soraka shard-tglu fi-bsw-cyan shard-rkl fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22723:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gem_contexts:
- bat-dg1-6:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg1-6/igt@i915_selftest@live@gem_contexts.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/bat-dg1-6/igt@i915_selftest@live@gem_contexts.html

  
Known issues


  Here are the changes found in Patchwork_22723 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka:   NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#109315]) +17 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html

  * igt@amdgpu/amd_basic@userptr:
- fi-cfl-8700k:   NOTRUN -> [SKIP][5] ([fdo#109271]) +29 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-cfl-8700k/igt@amdgpu/amd_ba...@userptr.html

  * igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2:  NOTRUN -> [SKIP][6] ([fdo#109315]) +17 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html

  * igt@gem_exec_suspend@basic-s0@smem:
- fi-glk-dsi: [PASS][7] -> [DMESG-WARN][8] ([i915#2943])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-glk-dsi/igt@gem_exec_suspend@basic...@smem.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-glk-dsi/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][9] ([fdo#109271]) +57 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
- fi-tgl-u2:  NOTRUN -> [SKIP][10] ([i915#2190])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html
- fi-cfl-8700k:   NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-cfl-8700k/igt@gem_huc_c...@huc-copy.html
- fi-icl-u2:  NOTRUN -> [SKIP][12] ([i915#2190])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][13] ([i915#4613]) +3 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
- fi-skl-guc: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-skl-guc/igt@gem_lmem_swapp...@random-engines.html
- fi-ivb-3770:NOTRUN -> [SKIP][15] ([fdo#109271]) +36 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-ivb-3770/igt@gem_lmem_swapp...@random-engines.html
- fi-cfl-8700k:   NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-cfl-8700k/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2:  NOTRUN -> [SKIP][17] ([i915#4613]) +3 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22723/fi-tgl-u2/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_ringfill@basic-all:
- bat-dg1-6:  [PASS][18] -> [TIMEOUT][19] ([i915#5199])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg1-6/

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/edid: cleanup and refactoring around validity checks

[Patchwork]

== Series Details ==

Series: drm/edid: cleanup and refactoring around validity checks
URL   : https://patchwork.freedesktop.org/series/101931/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/edid: cleanup and refactoring around validity checks

[Patchwork]

== Series Details ==

Series: drm/edid: cleanup and refactoring around validity checks
URL   : https://patchwork.freedesktop.org/series/101931/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static 
assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu

Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values

[Souza, Jose]

On Tue, 2022-03-29 at 21:14 +0300, Ville Syrjälä wrote:
> On Mon, Mar 28, 2022 at 12:16:15PM -0700, José Roberto de Souza wrote:
> > From: Caz Yokoyama 
> > 
> > B credits set by IFWI do not match with specification default, so here
> > programming the right value.
> > 
> > Also while at it, taking the oportunity to do a read-modify-write to
> > not overwrite all other bits in this register that specification don't
> > ask us to change.
> 
> RMWs considered harmful. This is a double buffered register and in the
> future we may have to program it via DSB to update it atomically with
> the rest of the registers (eg. if we want to avoid the modeset for the
> mbus joining change). And when that happens the RMW will have to be
> removed again since the DSB can't even read registers. So IMO better
> to not even start down this path.

Okay but right now it is not harmful as affected pipes would be disabled at 
this point.
Without the RMW will need to set the default value for 3 other registers in 
PIPE_MBUS_DBOX_CTL offset.

I'm good with any, option. 

> 
> > 
> > BSpec: 49213
> > BSpec: 50343
> > Cc: Matt Roper 
> > Cc: Stanislav Lisovskiy 
> > Cc: Jani Nikula 
> > Signed-off-by: Caz Yokoyama 
> > Signed-off-by: José Roberto de Souza 
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 12 +---
> >  1 file changed, 9 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 3d2ff258f0a94..078ada041e1cd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1830,13 +1830,19 @@ static void icl_pipe_mbus_enable(struct intel_crtc 
> > *crtc, bool joined_mbus)
> > enum pipe pipe = crtc->pipe;
> > u32 val;
> >  
> > +   val = intel_de_read(dev_priv, PIPE_MBUS_DBOX_CTL(pipe));
> > +   val &= ~MBUS_DBOX_A_CREDIT_MASK;
> > /* Wa_22010947358:adl-p */
> > if (IS_ALDERLAKE_P(dev_priv))
> > -   val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : 
> > MBUS_DBOX_A_CREDIT(4);
> > +   val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) : 
> > MBUS_DBOX_A_CREDIT(4);
> > else
> > -   val = MBUS_DBOX_A_CREDIT(2);
> > +   val |= MBUS_DBOX_A_CREDIT(2);
> >  
> > -   if (DISPLAY_VER(dev_priv) >= 12) {
> > +   val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK);
> > +   if (IS_ALDERLAKE_P(dev_priv)) {
> > +   val |= MBUS_DBOX_BW_CREDIT(2);
> > +   val |= MBUS_DBOX_B_CREDIT(8);
> > +   } else if (DISPLAY_VER(dev_priv) >= 12) {
> > val |= MBUS_DBOX_BW_CREDIT(2);
> > val |= MBUS_DBOX_B_CREDIT(12);
> > } else {
> > -- 
> > 2.35.1
> 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Add Wa_22014226127

[Patchwork]

== Series Details ==

Series: drm/i915/dg2: Add Wa_22014226127
URL   : https://patchwork.freedesktop.org/series/101792/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22684


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/index.html

Participating hosts (48 -> 44)
--

  Missing(4): fi-bdw-samus fi-tgl-1115g4 fi-bsw-cyan bat-adlp-4 

Known issues


  Here are the changes found in Patchwork_22684 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@core_hotunplug@unbind-rebind:
- fi-bsw-nick:NOTRUN -> [INCOMPLETE][1] ([i915#5441])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-bsw-nick/igt@core_hotunp...@unbind-rebind.html
- fi-cfl-8109u:   NOTRUN -> [INCOMPLETE][2] ([i915#5441])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-cfl-8109u/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_render_tiled_blits@basic:
- fi-cfl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#1982])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-cfl-guc/igt@gem_render_tiled_bl...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-cfl-guc/igt@gem_render_tiled_bl...@basic.html
- fi-ilk-650: NOTRUN -> [INCOMPLETE][5] ([i915#5441])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-ilk-650/igt@gem_render_tiled_bl...@basic.html
- fi-bsw-n3050:   [PASS][6] -> [INCOMPLETE][7] ([i915#5441])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-bsw-n3050/igt@gem_render_tiled_bl...@basic.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-bsw-n3050/igt@gem_render_tiled_bl...@basic.html
- fi-bsw-kefka:   [PASS][8] -> [INCOMPLETE][9] ([i915#5441])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-bsw-kefka/igt@gem_render_tiled_bl...@basic.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-bsw-kefka/igt@gem_render_tiled_bl...@basic.html
- fi-kbl-8809g:   [PASS][10] -> [INCOMPLETE][11] ([i915#5441])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-kbl-8809g/igt@gem_render_tiled_bl...@basic.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-kbl-8809g/igt@gem_render_tiled_bl...@basic.html
- fi-glk-dsi: [PASS][12] -> [INCOMPLETE][13] ([i915#5441])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-glk-dsi/igt@gem_render_tiled_bl...@basic.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-glk-dsi/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_softpin@allocator-basic:
- fi-snb-2520m:   NOTRUN -> [SKIP][14] ([fdo#109271]) +1 similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-snb-2520m/igt@gem_soft...@allocator-basic.html

  * igt@gem_tiled_blits@basic:
- fi-elk-e7500:   [PASS][15] -> [INCOMPLETE][16] ([i915#5441])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-elk-e7500/igt@gem_tiled_bl...@basic.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-elk-e7500/igt@gem_tiled_bl...@basic.html
- fi-skl-6700k2:  [PASS][17] -> [INCOMPLETE][18] ([i915#5441])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-skl-6700k2/igt@gem_tiled_bl...@basic.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-skl-6700k2/igt@gem_tiled_bl...@basic.html
- fi-blb-e6850:   [PASS][19] -> [INCOMPLETE][20] ([i915#5441])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11405/fi-blb-e6850/igt@gem_tiled_bl...@basic.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-blb-e6850/igt@gem_tiled_bl...@basic.html
- fi-snb-2520m:   NOTRUN -> [INCOMPLETE][21] ([i915#5441])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-snb-2520m/igt@gem_tiled_bl...@basic.html

  * igt@kms_chamelium@vga-edid-read:
- fi-bsw-nick:NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-bsw-nick/igt@kms_chamel...@vga-edid-read.html

  * igt@kms_chamelium@vga-hpd-fast:
- fi-cfl-8109u:   NOTRUN -> [SKIP][23] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-cfl-8109u/igt@kms_chamel...@vga-hpd-fast.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-bsw-nick:NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#5341])
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22684/fi-bsw-nick/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
- fi-bwr-2160:NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#5341])
   [25]: 
https://intel

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dg2: Add Wa_22014226127 (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/dg2: Add Wa_22014226127 (rev5)
URL   : https://patchwork.freedesktop.org/series/101792/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

[Intel-gfx] [PATCH 11/12] drm/edid: track invalid blocks in drm_do_get_edid()

[Jani Nikula]

Track invalid blocks instead of valid extensions to minimize impact on
the happy day scenario, and hide the details in the separate function.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 17 -
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index dee95332d7e1..d0a76781ed19 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1822,9 +1822,10 @@ bool drm_edid_is_valid(struct edid *edid)
 EXPORT_SYMBOL(drm_edid_is_valid);
 
 static struct edid *edid_filter_invalid_blocks(const struct edid *edid,
-  int valid_extensions)
+  int invalid_blocks)
 {
struct edid *new, *base;
+   int valid_extensions = edid->extensions - invalid_blocks;
int i;
 
new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, GFP_KERNEL);
@@ -2060,7 +2061,7 @@ struct edid *drm_do_get_edid(struct drm_connector 
*connector,
  size_t len),
void *data)
 {
-   int j, valid_extensions = 0;
+   int j, invalid_blocks = 0;
struct edid *edid, *new, *override;
 
override = drm_get_override_edid(connector);
@@ -2071,12 +2072,10 @@ struct edid *drm_do_get_edid(struct drm_connector 
*connector,
if (!edid)
return NULL;
 
-   /* if there's no extensions or no connector, we're done */
-   valid_extensions = edid->extensions;
-   if (valid_extensions == 0)
+   if (edid->extensions == 0)
return edid;
 
-   new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
+   new = krealloc(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
if (!new)
goto out;
edid = new;
@@ -2093,13 +2092,13 @@ struct edid *drm_do_get_edid(struct drm_connector 
*connector,
}
 
if (try == 4)
-   valid_extensions--;
+   invalid_blocks++;
}
 
-   if (valid_extensions != edid->extensions) {
+   if (invalid_blocks) {
connector_bad_edid(connector, (u8 *)edid, edid->extensions + 1);
 
-   edid = edid_filter_invalid_blocks(edid, valid_extensions);
+   edid = edid_filter_invalid_blocks(edid, invalid_blocks);
}
 
return edid;
-- 
2.30.2

[Intel-gfx] [PATCH 12/12] drm/edid: reduce magic when updating the EDID block checksum

[Jani Nikula]

The code modifying the EDID block should not need to do tricks to fix
the checksum. We have a function for computing the checksum, use it.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index d0a76781ed19..d2dfab28b5b7 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1840,8 +1840,8 @@ static struct edid *edid_filter_invalid_blocks(const 
struct edid *edid,
memcpy(base++, block, EDID_LENGTH);
}
 
-   new->checksum += new->extensions - valid_extensions;
new->extensions = valid_extensions;
+   new->checksum = edid_block_compute_checksum(new);
 
 out:
kfree(edid);
-- 
2.30.2

[Intel-gfx] [PATCH 10/12] drm/edid: split out invalid block filtering to a separate function

[Jani Nikula]

It's such a special case there's no point in keeping it inline in the
happy day scenario, confusing matters.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 52 --
 1 file changed, 28 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index a1be5c3a80e5..dee95332d7e1 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1821,6 +1821,33 @@ bool drm_edid_is_valid(struct edid *edid)
 }
 EXPORT_SYMBOL(drm_edid_is_valid);
 
+static struct edid *edid_filter_invalid_blocks(const struct edid *edid,
+  int valid_extensions)
+{
+   struct edid *new, *base;
+   int i;
+
+   new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, GFP_KERNEL);
+   if (!new)
+   goto out;
+
+   base = new;
+   for (i = 0; i <= edid->extensions; i++) {
+   const void *block = edid + i;
+
+   if (edid_block_valid(block, i == 0))
+   memcpy(base++, block, EDID_LENGTH);
+   }
+
+   new->checksum += new->extensions - valid_extensions;
+   new->extensions = valid_extensions;
+
+out:
+   kfree(edid);
+
+   return new;
+}
+
 #define DDC_SEGMENT_ADDR 0x30
 /**
  * drm_do_probe_ddc_edid() - get EDID information via I2C
@@ -2070,32 +2097,9 @@ struct edid *drm_do_get_edid(struct drm_connector 
*connector,
}
 
if (valid_extensions != edid->extensions) {
-   struct edid *base;
-   int i;
-
connector_bad_edid(connector, (u8 *)edid, edid->extensions + 1);
 
-   edid->checksum += edid->extensions - valid_extensions;
-   edid->extensions = valid_extensions;
-
-   new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
-   GFP_KERNEL);
-   if (!new)
-   goto out;
-
-   base = new;
-   for (i = 0; i <= edid->extensions; i++) {
-   void *block = edid + i;
-
-   if (!edid_block_valid(block, i == 0))
-   continue;
-
-   memcpy(base, block, EDID_LENGTH);
-   base++;
-   }
-
-   kfree(edid);
-   edid = new;
+   edid = edid_filter_invalid_blocks(edid, valid_extensions);
}
 
return edid;
-- 
2.30.2

[Intel-gfx] [PATCH 09/12] drm/edid: simplify block check when filtering invalid blocks

[Jani Nikula]

There's no need to handle complicated scenarios or debug log when
filtering blocks that have already been identified as invalid. Simplify
by adding an edid_block_valid() helper that operates on const data and
prints nothing.

(Finally, here's the justification for the previously added separate
edid_block_status_valid() function!)

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 235d3cde2e97..a1be5c3a80e5 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1713,6 +1713,12 @@ static bool edid_block_status_valid(enum 
edid_block_status status, int tag)
(status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
 }
 
+static bool edid_block_valid(const void *block, bool base)
+{
+   return edid_block_status_valid(edid_block_check(block, base),
+  edid_block_tag(block));
+}
+
 /**
  * drm_edid_block_valid - Sanity check the EDID block (base or extension)
  * @raw_edid: pointer to raw EDID block
@@ -2081,7 +2087,7 @@ struct edid *drm_do_get_edid(struct drm_connector 
*connector,
for (i = 0; i <= edid->extensions; i++) {
void *block = edid + i;
 
-   if (!drm_edid_block_valid(block, i, false, NULL))
+   if (!edid_block_valid(block, i == 0))
continue;
 
memcpy(base, block, EDID_LENGTH);
-- 
2.30.2

[Intel-gfx] [PATCH 08/12] drm/edid: use a better variable name for EDID block read retries

[Jani Nikula]

Just i is a bit terse, clarify what it's about.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 16 +---
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 04eb6949c9c8..235d3cde2e97 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1971,25 +1971,25 @@ static struct edid *drm_do_get_edid_base_block(struct 
drm_connector *connector,
int *null_edid_counter = connector ? &connector->null_edid_counter : 
NULL;
bool *edid_corrupt = connector ? &connector->edid_corrupt : NULL;
void *edid;
-   int i;
+   int try;
 
edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
if (edid == NULL)
return NULL;
 
/* base block fetch */
-   for (i = 0; i < 4; i++) {
+   for (try = 0; try < 4; try++) {
if (get_edid_block(data, edid, 0, EDID_LENGTH))
goto out;
if (drm_edid_block_valid(edid, 0, false, edid_corrupt))
break;
-   if (i == 0 && edid_is_zero(edid, EDID_LENGTH)) {
+   if (try == 0 && edid_is_zero(edid, EDID_LENGTH)) {
if (null_edid_counter)
(*null_edid_counter)++;
goto carp;
}
}
-   if (i == 4)
+   if (try == 4)
goto carp;
 
return edid;
@@ -2027,7 +2027,7 @@ struct edid *drm_do_get_edid(struct drm_connector 
*connector,
  size_t len),
void *data)
 {
-   int i, j = 0, valid_extensions = 0;
+   int j, valid_extensions = 0;
struct edid *edid, *new, *override;
 
override = drm_get_override_edid(connector);
@@ -2050,20 +2050,22 @@ struct edid *drm_do_get_edid(struct drm_connector 
*connector,
 
for (j = 1; j <= edid->extensions; j++) {
void *block = edid + j;
+   int try;
 
-   for (i = 0; i < 4; i++) {
+   for (try = 0; try < 4; try++) {
if (get_edid_block(data, block, j, EDID_LENGTH))
goto out;
if (drm_edid_block_valid(block, j, false, NULL))
break;
}
 
-   if (i == 4)
+   if (try == 4)
valid_extensions--;
}
 
if (valid_extensions != edid->extensions) {
struct edid *base;
+   int i;
 
connector_bad_edid(connector, (u8 *)edid, edid->extensions + 1);
 
-- 
2.30.2

[Intel-gfx] [PATCH 07/12] drm/edid: split drm_edid_block_valid() to check and act parts

[Jani Nikula]

Add edid_block_check() that only checks the EDID block validity, without
any actions. Turns out it's simple and crystal clear.

Rewrite drm_edid_block_valid() around it, keeping all the functionality
fairly closely the same, warts and all. Turns out it's incredibly
complicated for a function you'd expect to be simple, with all the
fixing and printing and special casing. (Maybe we'll want to simplify it
in the future.)

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 150 ++---
 1 file changed, 88 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 481643751d10..04eb6949c9c8 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1668,10 +1668,55 @@ bool drm_edid_are_equal(const struct edid *edid1, const 
struct edid *edid2)
 }
 EXPORT_SYMBOL(drm_edid_are_equal);
 
+enum edid_block_status {
+   EDID_BLOCK_OK = 0,
+   EDID_BLOCK_NULL,
+   EDID_BLOCK_HEADER_CORRUPT,
+   EDID_BLOCK_HEADER_REPAIR,
+   EDID_BLOCK_HEADER_FIXED,
+   EDID_BLOCK_CHECKSUM,
+   EDID_BLOCK_VERSION,
+};
+
+static enum edid_block_status edid_block_check(const void *_block, bool base)
+{
+   const struct edid *block = _block;
+
+   if (!block)
+   return EDID_BLOCK_NULL;
+
+   if (base) {
+   int score = drm_edid_header_is_valid(block);
+
+   if (score < clamp(edid_fixup, 6, 8))
+   return EDID_BLOCK_HEADER_CORRUPT;
+
+   if (score < 8)
+   return EDID_BLOCK_HEADER_REPAIR;
+   }
+
+   if (edid_block_compute_checksum(block) != 
edid_block_get_checksum(block))
+   return EDID_BLOCK_CHECKSUM;
+
+   if (base) {
+   if (block->version != 1)
+   return EDID_BLOCK_VERSION;
+   }
+
+   return EDID_BLOCK_OK;
+}
+
+static bool edid_block_status_valid(enum edid_block_status status, int tag)
+{
+   return status == EDID_BLOCK_OK ||
+   status == EDID_BLOCK_HEADER_FIXED ||
+   (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
+}
+
 /**
  * drm_edid_block_valid - Sanity check the EDID block (base or extension)
  * @raw_edid: pointer to raw EDID block
- * @block: type of block to validate (0 for base, extension otherwise)
+ * @block_num: type of block to validate (0 for base, extension otherwise)
  * @print_bad_edid: if true, dump bad EDID blocks to the console
  * @edid_corrupt: if true, the header or checksum is invalid
  *
@@ -1680,88 +1725,69 @@ EXPORT_SYMBOL(drm_edid_are_equal);
  *
  * Return: True if the block is valid, false otherwise.
  */
-bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
+bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
  bool *edid_corrupt)
 {
-   u8 csum;
-   struct edid *edid = (struct edid *)raw_edid;
+   struct edid *block = (struct edid *)_block;
+   enum edid_block_status status;
+   bool base = block_num == 0;
+   bool valid;
 
-   if (WARN_ON(!raw_edid))
+   if (WARN_ON(!block))
return false;
 
-   if (edid_fixup > 8 || edid_fixup < 0)
-   edid_fixup = 6;
-
-   if (block == 0) {
-   int score = drm_edid_header_is_valid(raw_edid);
+   status = edid_block_check(block, base);
+   if (status == EDID_BLOCK_HEADER_REPAIR) {
+   DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
+   edid_header_fix(block);
 
-   if (score == 8) {
-   if (edid_corrupt)
-   *edid_corrupt = false;
-   } else if (score >= edid_fixup) {
-   /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
-* The corrupt flag needs to be set here otherwise, the
-* fix-up code here will correct the problem, the
-* checksum is correct and the test fails
-*/
-   if (edid_corrupt)
-   *edid_corrupt = true;
-   DRM_DEBUG("Fixing EDID header, your hardware may be 
failing\n");
-   edid_header_fix(raw_edid);
-   } else {
-   if (edid_corrupt)
-   *edid_corrupt = true;
-   goto bad;
-   }
+   /* Retry with fixed header, update status if that worked. */
+   status = edid_block_check(block, base);
+   if (status == EDID_BLOCK_OK)
+   status = EDID_BLOCK_HEADER_FIXED;
}
 
-   csum = edid_block_compute_checksum(raw_edid);
-   if (csum != edid_block_get_checksum(raw_edid)) {
-   if (edid_corrupt)
+   if (edid_corrupt) {
+   /*
+* Unknown major versio

[Intel-gfx] [PATCH 06/12] drm/edid: split out edid_header_fix()

[Jani Nikula]

Give a name to the EDID header fixup instead of having an inline memcpy.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 422db8ae0ac1..481643751d10 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1572,6 +1572,11 @@ static const u8 edid_header[] = {
0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
 };
 
+static void edid_header_fix(void *edid)
+{
+   memcpy(edid, edid_header, sizeof(edid_header));
+}
+
 /**
  * drm_edid_header_is_valid - sanity check the header of the base EDID block
  * @raw_edid: pointer to raw base EDID block
@@ -1702,7 +1707,7 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool 
print_bad_edid,
if (edid_corrupt)
*edid_corrupt = true;
DRM_DEBUG("Fixing EDID header, your hardware may be 
failing\n");
-   memcpy(raw_edid, edid_header, sizeof(edid_header));
+   edid_header_fix(raw_edid);
} else {
if (edid_corrupt)
*edid_corrupt = true;
-- 
2.30.2

[Intel-gfx] [PATCH 05/12] drm/edid: clean up edid_is_zero()

[Jani Nikula]

Simplify, rename, take void pointer. No need for the drm_ prefix for
internal helpers.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 13 +
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index b5b21b50e476..422db8ae0ac1 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1627,12 +1627,9 @@ static int edid_block_tag(const void *_block)
return block[0];
 }
 
-static bool drm_edid_is_zero(const u8 *in_edid, int length)
+static bool edid_is_zero(const void *edid, int length)
 {
-   if (memchr_inv(in_edid, 0, length))
-   return false;
-
-   return true;
+   return !memchr_inv(edid, 0, length);
 }
 
 /**
@@ -1750,7 +1747,7 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool 
print_bad_edid,
 
 bad:
if (print_bad_edid) {
-   if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
+   if (edid_is_zero(raw_edid, EDID_LENGTH)) {
pr_notice("EDID block is all zeroes\n");
} else {
pr_notice("Raw EDID:\n");
@@ -1878,7 +1875,7 @@ static void connector_bad_edid(struct drm_connector 
*connector,
u8 *block = edid + i * EDID_LENGTH;
char prefix[20];
 
-   if (drm_edid_is_zero(block, EDID_LENGTH))
+   if (edid_is_zero(block, EDID_LENGTH))
sprintf(prefix, "\t[%02x] ZERO ", i);
else if (!drm_edid_block_valid(block, i, false, NULL))
sprintf(prefix, "\t[%02x] BAD  ", i);
@@ -1955,7 +1952,7 @@ static struct edid *drm_do_get_edid_base_block(struct 
drm_connector *connector,
goto out;
if (drm_edid_block_valid(edid, 0, false, edid_corrupt))
break;
-   if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
+   if (i == 0 && edid_is_zero(edid, EDID_LENGTH)) {
if (null_edid_counter)
(*null_edid_counter)++;
goto carp;
-- 
2.30.2

[Intel-gfx] [PATCH 04/12] drm/edid: make drm_edid_header_is_valid() accept void pointer

[Jani Nikula]

It will be useful to accept a struct edid *, but for compatibility with
existing usage accept void *.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 8 +---
 include/drm/drm_edid.h | 2 +-
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 95f0303bc63e..b5b21b50e476 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1580,13 +1580,15 @@ static const u8 edid_header[] = {
  *
  * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
  */
-int drm_edid_header_is_valid(const u8 *raw_edid)
+int drm_edid_header_is_valid(const void *_edid)
 {
+   const struct edid *edid = _edid;
int i, score = 0;
 
-   for (i = 0; i < sizeof(edid_header); i++)
-   if (raw_edid[i] == edid_header[i])
+   for (i = 0; i < sizeof(edid_header); i++) {
+   if (edid->header[i] == edid_header[i])
score++;
+   }
 
return score;
 }
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 48b1bf9c315a..b7e170584000 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -578,7 +578,7 @@ int drm_add_modes_noedid(struct drm_connector *connector,
 void drm_set_preferred_mode(struct drm_connector *connector,
int hpref, int vpref);
 
-int drm_edid_header_is_valid(const u8 *raw_edid);
+int drm_edid_header_is_valid(const void *edid);
 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
  bool *edid_corrupt);
 bool drm_edid_is_valid(struct edid *edid);
-- 
2.30.2

[Intel-gfx] [PATCH 03/12] drm/edid: add edid_block_tag() helper to get the EDID extension tag

[Jani Nikula]

The extension tag at offset 0 is not present in struct edid, add a
helper for it to reduce the need to use u8 *.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 73f05e0363c0..95f0303bc63e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1618,6 +1618,13 @@ static int edid_block_get_checksum(const void *_block)
return block->checksum;
 }
 
+static int edid_block_tag(const void *_block)
+{
+   const u8 *block = _block;
+
+   return block[0];
+}
+
 static bool drm_edid_is_zero(const u8 *in_edid, int length)
 {
if (memchr_inv(in_edid, 0, length))
@@ -1710,7 +1717,7 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool 
print_bad_edid,
*edid_corrupt = true;
 
/* allow CEA to slide through, switches mangle this */
-   if (raw_edid[0] == CEA_EXT) {
+   if (edid_block_tag(raw_edid) == CEA_EXT) {
DRM_DEBUG("EDID checksum is invalid, remainder is 
%d\n", csum);
DRM_DEBUG("Assuming a KVM switch modified the CEA block 
but left the original checksum\n");
} else {
@@ -1722,7 +1729,7 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool 
print_bad_edid,
}
 
/* per-block-type checks */
-   switch (raw_edid[0]) {
+   switch (edid_block_tag(raw_edid)) {
case 0: /* base */
if (edid->version != 1) {
DRM_NOTE("EDID has major version %d, instead of 1\n", 
edid->version);
@@ -3366,7 +3373,7 @@ const u8 *drm_find_edid_extension(const struct edid *edid,
/* Find CEA extension */
for (i = *ext_index; i < edid->extensions; i++) {
edid_ext = (const u8 *)edid + EDID_LENGTH * (i + 1);
-   if (edid_ext[0] == ext_id)
+   if (edid_block_tag(edid_ext) == ext_id)
break;
}
 
-- 
2.30.2

[Intel-gfx] [PATCH 02/12] drm/edid: clean up EDID block checksum functions

[Jani Nikula]

Have two clear functions, one to compute the checksum over the EDID, and
another to get the checksum from the EDID. Throw away the diff function.

Ditch the drm_ prefix for static functions, and accept const void * to
help transition to struct edid * usage.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 0650b9217aa2..73f05e0363c0 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1597,25 +1597,25 @@ module_param_named(edid_fixup, edid_fixup, int, 0400);
 MODULE_PARM_DESC(edid_fixup,
 "Minimum number of valid EDID header bytes (0-8, default 6)");
 
-static int drm_edid_block_checksum(const u8 *raw_edid)
+static int edid_block_compute_checksum(const void *_block)
 {
+   const u8 *block = _block;
int i;
u8 csum = 0, crc = 0;
 
for (i = 0; i < EDID_LENGTH - 1; i++)
-   csum += raw_edid[i];
+   csum += block[i];
 
crc = 0x100 - csum;
 
return crc;
 }
 
-static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
+static int edid_block_get_checksum(const void *_block)
 {
-   if (raw_edid[EDID_LENGTH - 1] != real_checksum)
-   return true;
-   else
-   return false;
+   const struct edid *block = _block;
+
+   return block->checksum;
 }
 
 static bool drm_edid_is_zero(const u8 *in_edid, int length)
@@ -1704,8 +1704,8 @@ bool drm_edid_block_valid(u8 *raw_edid, int block, bool 
print_bad_edid,
}
}
 
-   csum = drm_edid_block_checksum(raw_edid);
-   if (drm_edid_block_checksum_diff(raw_edid, csum)) {
+   csum = edid_block_compute_checksum(raw_edid);
+   if (csum != edid_block_get_checksum(raw_edid)) {
if (edid_corrupt)
*edid_corrupt = true;
 
@@ -1859,7 +1859,7 @@ static void connector_bad_edid(struct drm_connector 
*connector,
/* Calculate real checksum for the last edid extension block data */
if (last_block < num_blocks)
connector->real_edid_checksum =
-   drm_edid_block_checksum(edid + last_block * 
EDID_LENGTH);
+   edid_block_compute_checksum(edid + last_block * 
EDID_LENGTH);
 
if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
return;
-- 
2.30.2

[Intel-gfx] [PATCH 01/12] drm/edid: use struct edid * in drm_do_get_edid()

[Jani Nikula]

Mixing u8 * and struct edid * is confusing, switch to the latter.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 31 +++
 1 file changed, 15 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index d79b06f7f34c..0650b9217aa2 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1991,29 +1991,28 @@ struct edid *drm_do_get_edid(struct drm_connector 
*connector,
void *data)
 {
int i, j = 0, valid_extensions = 0;
-   u8 *edid, *new;
-   struct edid *override;
+   struct edid *edid, *new, *override;
 
override = drm_get_override_edid(connector);
if (override)
return override;
 
-   edid = (u8 *)drm_do_get_edid_base_block(connector, get_edid_block, 
data);
+   edid = drm_do_get_edid_base_block(connector, get_edid_block, data);
if (!edid)
return NULL;
 
/* if there's no extensions or no connector, we're done */
-   valid_extensions = edid[0x7e];
+   valid_extensions = edid->extensions;
if (valid_extensions == 0)
-   return (struct edid *)edid;
+   return edid;
 
new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
if (!new)
goto out;
edid = new;
 
-   for (j = 1; j <= edid[0x7e]; j++) {
-   u8 *block = edid + j * EDID_LENGTH;
+   for (j = 1; j <= edid->extensions; j++) {
+   void *block = edid + j;
 
for (i = 0; i < 4; i++) {
if (get_edid_block(data, block, j, EDID_LENGTH))
@@ -2026,13 +2025,13 @@ struct edid *drm_do_get_edid(struct drm_connector 
*connector,
valid_extensions--;
}
 
-   if (valid_extensions != edid[0x7e]) {
-   u8 *base;
+   if (valid_extensions != edid->extensions) {
+   struct edid *base;
 
-   connector_bad_edid(connector, edid, edid[0x7e] + 1);
+   connector_bad_edid(connector, (u8 *)edid, edid->extensions + 1);
 
-   edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
-   edid[0x7e] = valid_extensions;
+   edid->checksum += edid->extensions - valid_extensions;
+   edid->extensions = valid_extensions;
 
new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
GFP_KERNEL);
@@ -2040,21 +2039,21 @@ struct edid *drm_do_get_edid(struct drm_connector 
*connector,
goto out;
 
base = new;
-   for (i = 0; i <= edid[0x7e]; i++) {
-   u8 *block = edid + i * EDID_LENGTH;
+   for (i = 0; i <= edid->extensions; i++) {
+   void *block = edid + i;
 
if (!drm_edid_block_valid(block, i, false, NULL))
continue;
 
memcpy(base, block, EDID_LENGTH);
-   base += EDID_LENGTH;
+   base++;
}
 
kfree(edid);
edid = new;
}
 
-   return (struct edid *)edid;
+   return edid;
 
 out:
kfree(edid);
-- 
2.30.2

[Intel-gfx] [PATCH 00/12] drm/edid: cleanup and refactoring around validity checks

[Jani Nikula]

Another day, another batch of EDID code refactoring.

Mostly the goal was to simplify drm_do_get_edid(), but trying to extract
a const function for checking a single block validity lead me down a
rabbit hole...

BR,
Jani.


Cc: Ville Syrjälä 
Cc: Emil Velikov 

Jani Nikula (12):
  drm/edid: use struct edid * in drm_do_get_edid()
  drm/edid: clean up EDID block checksum functions
  drm/edid: add edid_block_tag() helper to get the EDID extension tag
  drm/edid: make drm_edid_header_is_valid() accept void pointer
  drm/edid: clean up edid_is_zero()
  drm/edid: split out edid_header_fix()
  drm/edid: split drm_edid_block_valid() to check and act parts
  drm/edid: use a better variable name for EDID block read retries
  drm/edid: simplify block check when filtering invalid blocks
  drm/edid: split out invalid block filtering to a separate function
  drm/edid: track invalid blocks in drm_do_get_edid()
  drm/edid: reduce magic when updating the EDID block checksum

 drivers/gpu/drm/drm_edid.c | 293 +
 include/drm/drm_edid.h |   2 +-
 2 files changed, 171 insertions(+), 124 deletions(-)

-- 
2.30.2

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Refactor the display power domain mappings (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Refactor the display power domain mappings (rev3)
URL   : https://patchwork.freedesktop.org/series/99476/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22722


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22722 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22722, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/index.html

Participating hosts (42 -> 47)
--

  Additional (9): fi-cml-u2 fi-tgl-u2 fi-skl-guc bat-adlm-1 fi-icl-u2 
fi-cfl-8700k bat-adlp-4 fi-ivb-3770 fi-pnv-d510 
  Missing(4): fi-kbl-soraka fi-bsw-cyan shard-tglu fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22722:

### IGT changes ###

 Possible regressions 

  * igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlp-4/igt@run...@aborted.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_suspend@basic-s0@smem:
- {bat-dg2-9}:[DMESG-WARN][2] ([i915#5193]) -> [DMESG-WARN][3] +3 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-dg2-8}:[DMESG-WARN][4] ([i915#5193]) -> [DMESG-WARN][5] +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg2-8/igt@gem_exec_suspend@basic...@smem.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-dg2-8/igt@gem_exec_suspend@basic...@smem.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- {bat-adlm-1}:   NOTRUN -> [INCOMPLETE][6]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlm-1/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- {bat-dg2-9}:NOTRUN -> [DMESG-WARN][7]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-dg2-9/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html

  
Known issues


  Here are the changes found in Patchwork_22722 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka:   NOTRUN -> [SKIP][8] ([fdo#109271]) +17 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_basic@userptr:
- fi-cfl-8700k:   NOTRUN -> [SKIP][9] ([fdo#109271]) +29 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@amdgpu/amd_ba...@userptr.html

  * igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([fdo#109315]) +17 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html

  * igt@amdgpu/amd_cs_nop@sync-compute0:
- fi-cml-u2:  NOTRUN -> [SKIP][11] ([fdo#109315]) +17 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@amdgpu/amd_cs_...@sync-compute0.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][12] ([i915#1208]) +1 similar issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][13] ([fdo#109271]) +57 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
- fi-tgl-u2:  NOTRUN -> [SKIP][14] ([i915#2190])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html
- fi-cfl-8700k:   NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@gem_huc_c...@huc-copy.html
- fi-icl-u2:  NOTRUN -> [SKIP][16] ([i915#2190])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
- fi-cml-u2:  NOTRUN -> [SKIP][17] ([i915#2190])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][18] ([i9

Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values

[Ville Syrjälä]

On Mon, Mar 28, 2022 at 12:16:15PM -0700, José Roberto de Souza wrote:
> From: Caz Yokoyama 
> 
> B credits set by IFWI do not match with specification default, so here
> programming the right value.
> 
> Also while at it, taking the oportunity to do a read-modify-write to
> not overwrite all other bits in this register that specification don't
> ask us to change.

RMWs considered harmful. This is a double buffered register and in the
future we may have to program it via DSB to update it atomically with
the rest of the registers (eg. if we want to avoid the modeset for the
mbus joining change). And when that happens the RMW will have to be
removed again since the DSB can't even read registers. So IMO better
to not even start down this path.

> 
> BSpec: 49213
> BSpec: 50343
> Cc: Matt Roper 
> Cc: Stanislav Lisovskiy 
> Cc: Jani Nikula 
> Signed-off-by: Caz Yokoyama 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 12 +---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 3d2ff258f0a94..078ada041e1cd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1830,13 +1830,19 @@ static void icl_pipe_mbus_enable(struct intel_crtc 
> *crtc, bool joined_mbus)
>   enum pipe pipe = crtc->pipe;
>   u32 val;
>  
> + val = intel_de_read(dev_priv, PIPE_MBUS_DBOX_CTL(pipe));
> + val &= ~MBUS_DBOX_A_CREDIT_MASK;
>   /* Wa_22010947358:adl-p */
>   if (IS_ALDERLAKE_P(dev_priv))
> - val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : 
> MBUS_DBOX_A_CREDIT(4);
> + val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) : 
> MBUS_DBOX_A_CREDIT(4);
>   else
> - val = MBUS_DBOX_A_CREDIT(2);
> + val |= MBUS_DBOX_A_CREDIT(2);
>  
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK);
> + if (IS_ALDERLAKE_P(dev_priv)) {
> + val |= MBUS_DBOX_BW_CREDIT(2);
> + val |= MBUS_DBOX_B_CREDIT(8);
> + } else if (DISPLAY_VER(dev_priv) >= 12) {
>   val |= MBUS_DBOX_BW_CREDIT(2);
>   val |= MBUS_DBOX_B_CREDIT(12);
>   } else {
> -- 
> 2.35.1

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values

[Sripada, Radhakrishna]

> -Original Message-
> From: Intel-gfx  On Behalf Of José
> Roberto de Souza
> Sent: Tuesday, March 29, 2022 12:46 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani 
> Subject: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Program
> PIPE_MBUS_DBOX_CTL with adl-p values
> 
> From: Caz Yokoyama 
> 
> B credits set by IFWI do not match with specification default, so here
> programming the right value.
> 
> Also while at it, taking the oportunity to do a read-modify-write to
> not overwrite all other bits in this register that specification don't
> ask us to change.
> 
> BSpec: 49213
> BSpec: 50343
> Cc: Matt Roper 
> Cc: Stanislav Lisovskiy 
> Cc: Jani Nikula 
Reviewed-by: Radhakrishna Sripada 


> Signed-off-by: Caz Yokoyama 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 12 +---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 3d2ff258f0a94..078ada041e1cd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1830,13 +1830,19 @@ static void icl_pipe_mbus_enable(struct intel_crtc
> *crtc, bool joined_mbus)
>   enum pipe pipe = crtc->pipe;
>   u32 val;
> 
> + val = intel_de_read(dev_priv, PIPE_MBUS_DBOX_CTL(pipe));
> + val &= ~MBUS_DBOX_A_CREDIT_MASK;
>   /* Wa_22010947358:adl-p */
>   if (IS_ALDERLAKE_P(dev_priv))
> - val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
> MBUS_DBOX_A_CREDIT(4);
> + val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
> MBUS_DBOX_A_CREDIT(4);
>   else
> - val = MBUS_DBOX_A_CREDIT(2);
> + val |= MBUS_DBOX_A_CREDIT(2);
> 
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + val &= ~(MBUS_DBOX_BW_CREDIT_MASK |
> MBUS_DBOX_B_CREDIT_MASK);
> + if (IS_ALDERLAKE_P(dev_priv)) {
> + val |= MBUS_DBOX_BW_CREDIT(2);
> + val |= MBUS_DBOX_B_CREDIT(8);
> + } else if (DISPLAY_VER(dev_priv) >= 12) {
>   val |= MBUS_DBOX_BW_CREDIT(2);
>   val |= MBUS_DBOX_B_CREDIT(12);
>   } else {
> --
> 2.35.1

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Refactor the display power domain mappings (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Refactor the display power domain mappings (rev3)
URL   : https://patchwork.freedesktop.org/series/99476/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Refactor the display power domain mappings (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Refactor the display power domain mappings (rev3)
URL   : https://patchwork.freedesktop.org/series/99476/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Refactor the display power domain mappings (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Refactor the display power domain mappings (rev3)
URL   : https://patchwork.freedesktop.org/series/99476/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b760be68ea17 drm/i915: Move per-platform power well hooks to 
intel_display_power_well.c
-:2157: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#2157: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:265:
+
+   }

-:2367: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see 
Documentation/timers/timers-howto.rst
#2367: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:475:
+   msleep(1);

-:2372: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see 
Documentation/timers/timers-howto.rst
#2372: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:480:
+   msleep(1);

-:2693: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#2693: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:801:
+
DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),

-:2733: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#2733: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:841:
+  intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | 
SKL_SELECT_ALTERNATE_DC_EXIT);

-:2760: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#2760: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:868:
+  intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | 
SKL_SELECT_ALTERNATE_DC_EXIT);

-:2862: WARNING:REPEATED_WORD: Possible repeated word: 'power'
#2862: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:970:
+"Unexpected DBuf power power state (0x%08x, expected 
0x%08x)\n",

-:2937: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2937: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:1045:
+static bool i9xx_always_on_power_well_enabled(struct drm_i915_private 
*dev_priv,
+struct i915_power_well *power_well)

-:3209: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'bits' - possible 
side-effects?
#3209: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:1317:
+#define BITS_SET(val, bits) (((val) & (bits)) == (bits))

-:3664: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see 
Documentation/timers/timers-howto.rst
#3664: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:1772:
+   msleep(1);

-:3710: CHECK:LINE_SPACING: Please don't use multiple blank lines
#3710: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:1818:
+
+

total: 0 errors, 7 warnings, 4 checks, 3856 lines checked
86cb72f00160 drm/i915: Unexport the for_each_power_well() macros
-:23: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#23: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:24:
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)
\
+   for_each_power_well(__dev_priv, __power_well)   
\
+   for_each_if((__power_well)->desc->domains & (__domain_mask))

-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible 
side-effects?
#23: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:24:
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)
\
+   for_each_power_well(__dev_priv, __power_well)   
\
+   for_each_if((__power_well)->desc->domains & (__domain_mask))

-:27: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#27: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:28:
+#define for_each_power_domain_well_reverse(__dev_priv, __power_well, 
__domain_mask) \
+   for_each_power_well_reverse(__dev_priv, __power_well)   
\
+   for_each_if((__power_well)->desc->domains & (__domain_mask))

-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible 
side-effects?
#27: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:28:
+#define for_each_power_domain_well_reverse(__dev_priv, __power_well, 
__domain_mask) \
+   for_each_power_well_reverse(__dev_priv, __power_well)   
\
+   for_each_if((__power_well)->desc->domains & (__domain_mask))

-:73: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__dev_priv' - possible 
side-effects?
#73: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.h:15:
+#define for_each_power_well(__dev_priv, __power_well)  
\
+   for ((__power_well) = (__dev_priv)->power_domains.power_wells;  \
+(__power_well) - (__dev_priv)->power_domains.power_wells < \
+   (__dev_priv)->power_domains.power_well_count;   \
+(__power_well)++)

-:73: CHECK:MACRO_ARG_REUS

[Intel-gfx] ✗ Fi.CI.BAT: failure for Add driver for GSC controller (rev13)

[Patchwork]

== Series Details ==

Series: Add driver for GSC controller (rev13)
URL   : https://patchwork.freedesktop.org/series/98066/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22721


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22721 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22721, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/index.html

Participating hosts (42 -> 43)
--

  Additional (7): fi-cml-u2 fi-tgl-u2 fi-skl-guc bat-adlm-1 fi-cfl-8700k 
bat-adlp-4 fi-ivb-3770 
  Missing(6): fi-kbl-soraka shard-tglu fi-bsw-cyan fi-bdw-samus bat-jsl-2 
bat-jsl-1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22721:

### IGT changes ###

 Possible regressions 

  * igt@gem_lmem_swapping@verify-random:
- bat-dg1-6:  NOTRUN -> [FAIL][1] +3 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/bat-dg1-6/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_module_load@reload:
- bat-dg1-6:  [PASS][2] -> [WARN][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg1-6/igt@i915_module_l...@reload.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/bat-dg1-6/igt@i915_module_l...@reload.html

  * igt@i915_pm_rpm@module-reload:
- bat-dg1-6:  [PASS][4] -> [FAIL][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg1-6/igt@i915_pm_...@module-reload.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/bat-dg1-6/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live:
- bat-dg1-6:  NOTRUN -> [SKIP][6]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/bat-dg1-6/igt@i915_selft...@live.html

  * igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][7]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/bat-adlp-4/igt@run...@aborted.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_lmem_swapping@verify-random:
- {bat-dg2-8}:NOTRUN -> [FAIL][8] +3 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/bat-dg2-8/igt@gem_lmem_swapp...@verify-random.html
- {bat-dg2-9}:NOTRUN -> [FAIL][9] +3 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/bat-dg2-9/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_module_load@reload:
- {bat-dg2-9}:NOTRUN -> [WARN][10]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/bat-dg2-9/igt@i915_module_l...@reload.html
- {bat-dg2-8}:[PASS][11] -> [WARN][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg2-8/igt@i915_module_l...@reload.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/bat-dg2-8/igt@i915_module_l...@reload.html

  * igt@i915_selftest@live:
- {bat-dg2-8}:NOTRUN -> [SKIP][13]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/bat-dg2-8/igt@i915_selft...@live.html
- {bat-dg2-9}:NOTRUN -> [SKIP][14]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/bat-dg2-9/igt@i915_selft...@live.html

  
Known issues


  Here are the changes found in Patchwork_22721 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770:NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#109315]) 
+17 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html

  * igt@amdgpu/amd_basic@memory-alloc:
- fi-cml-u2:  NOTRUN -> [SKIP][16] ([fdo#109315]) +17 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/fi-cml-u2/igt@amdgpu/amd_ba...@memory-alloc.html

  * igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka:   NOTRUN -> [SKIP][17] ([fdo#109271]) +17 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-cfl-8700k:   NOTRUN -> [SKIP][18] ([fdo#109271]) +29 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/fi-cfl-8700k/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][19] ([i915#1208]) +1 similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22721/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.htm

[Intel-gfx] ✗ Fi.CI.DOCS: warning for Add driver for GSC controller (rev13)

[Patchwork]

== Series Details ==

Series: Add driver for GSC controller (rev13)
URL   : https://patchwork.freedesktop.org/series/98066/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Add Wa_22014226127 (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/dg2: Add Wa_22014226127 (rev4)
URL   : https://patchwork.freedesktop.org/series/101792/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22719


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22719 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22719, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/index.html

Participating hosts (42 -> 44)
--

  Additional (7): fi-tgl-u2 fi-skl-guc fi-icl-u2 fi-cfl-8700k bat-adlp-4 
fi-ivb-3770 fi-pnv-d510 
  Missing(5): fi-kbl-soraka shard-tglu fi-bsw-cyan bat-jsl-2 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22719:

### IGT changes ###

 Possible regressions 

  * igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/bat-adlp-4/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_22719 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#109315]) +17 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html

  * igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka:   NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2:  NOTRUN -> [SKIP][4] ([fdo#109315]) +17 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html

  * igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-cfl-8700k:   NOTRUN -> [SKIP][5] ([fdo#109271]) +29 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/fi-cfl-8700k/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html

  * igt@gem_huc_copy@huc-copy:
- fi-tgl-u2:  NOTRUN -> [SKIP][6] ([i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html
- fi-cfl-8700k:   NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/fi-cfl-8700k/igt@gem_huc_c...@huc-copy.html
- fi-icl-u2:  NOTRUN -> [SKIP][8] ([i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-skl-guc: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/fi-skl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([i915#4613]) +3 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html
- fi-cfl-8700k:   NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/fi-cfl-8700k/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
- fi-ivb-3770:NOTRUN -> [SKIP][12] ([fdo#109271]) +36 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/fi-ivb-3770/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2:  NOTRUN -> [SKIP][13] ([i915#4613]) +3 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/fi-tgl-u2/igt@gem_lmem_swapp...@verify-random.html

  * igt@kms_busy@basic@flip:
- fi-tgl-u2:  NOTRUN -> [DMESG-WARN][14] ([i915#402])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/fi-tgl-u2/igt@kms_busy@ba...@flip.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-skl-guc: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/fi-skl-guc/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-ivb-3770:NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22719/fi-ivb-3770/igt@kms_chamel...@dp-hpd-fast.html
- fi-tgl-u2:  NOTRUN -> [SKIP][17] ([fdo#109284] / [fdo#111827]) +8 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add driver for GSC controller (rev13)

[Patchwork]

== Series Details ==

Series: Add driver for GSC controller (rev13)
URL   : https://patchwork.freedesktop.org/series/98066/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add driver for GSC controller (rev13)

[Patchwork]

== Series Details ==

Series: Add driver for GSC controller (rev13)
URL   : https://patchwork.freedesktop.org/series/98066/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
8a042c9ddfdf drm/i915/gsc: add gsc as a mei auxiliary device
-:65: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#65: 
new file mode 100644

-:459: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible 
side-effects?
#459: FILE: drivers/gpu/drm/i915/i915_drv.h:1324:
+#define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || 
HAS_HECI_GSCFI(dev_priv))

total: 0 errors, 1 warnings, 1 checks, 418 lines checked
274227441fc8 mei: add support for graphics system controller (gsc) devices
-:57: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#57: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 297 lines checked
2f89b1a58b70 mei: gsc: setup char driver alive in spite of firmware handshake 
failure
056c168b2ae9 mei: gsc: add runtime pm handlers
4c6bf16ccc6e mei: gsc: retrieve the firmware version
5266af5250c6 HAX: drm/i915: force INTEL_MEI_GSC on for CI

Re: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children runtime status

[Nilawar, Badal]

On 28-03-2022 15:52, Anshuman Gupta wrote:

i915 doesn't use pm_suspend_ignore_children() which warrants that
any runtime active child of i915 will block the runtime suspend
of i915.
i915_runtime_pm_status only exposes i915 runtime pm usage_count,
which is not sufficient to debug in the scenarios when i915 has
zero usage_count but there are runtime active children.
Dump i915 child's runtime pm status to debug such
i915 runtime suspend issues.

Cc: Chris Wilson 
Signed-off-by: Anshuman Gupta 
---
  drivers/gpu/drm/i915/i915_debugfs.c | 38 +
  1 file changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 445b4da23950..ea1730419f8d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -483,6 +483,40 @@ static int i915_rps_boost_info(struct seq_file *m, void 
*data)
return 0;
  }
  
+#ifdef CONFIG_PM

+static int i915_runtime_dump_child_status(struct device *dev, void *data)
+{
+   struct seq_file *m = data;
+   const char *rpm_status;
+
+   /* Early return if runtime_pm is disabled */
+   if (dev->power.disable_depth)
+   return 0;
+
+   switch (dev->power.runtime_status) {
+   case RPM_SUSPENDED:
+   rpm_status = "suspended";
+   break;
+   case RPM_SUSPENDING:
+   rpm_status = "suspending";
+   break;
+   case RPM_RESUMING:
+   rpm_status = "resuming";
+   break;
+   case RPM_ACTIVE:
+   rpm_status = "active";
+   break;
+   default:
+   rpm_status = "unknown";
+   }
+
+   seq_printf(m, "\t%s %s: Runtime status: %s\n", dev_driver_string(dev),
+  dev_name(dev), rpm_status);
+
+   return 0;
+}
+#endif
+
  static int i915_runtime_pm_status(struct seq_file *m, void *unused)
  {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -500,6 +534,10 @@ static int i915_runtime_pm_status(struct seq_file *m, void 
*unused)
  #ifdef CONFIG_PM
seq_printf(m, "Usage count: %d\n",
   atomic_read(&dev_priv->drm.dev->power.usage_count));
+   seq_printf(m, "Runtime active children: %d\n",
+  atomic_read(&dev_priv->drm.dev->power.child_count));
+   device_for_each_child(&pdev->dev, m, i915_runtime_dump_child_status);
+

These changes looks fine to me.
Reviewed-by: Badal Nilawar 

  #else
seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
  #endif

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Finish off static DRRS

[Patchwork]

== Series Details ==

Series: drm/i915: Finish off static DRRS
URL   : https://patchwork.freedesktop.org/series/101928/
State : failure

== Summary ==

Applying: drm/i915: Extract intel_edp_has_drrs()
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/display/intel_dp.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/intel_dp.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_dp.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915: Extract intel_edp_has_drrs()
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

Re: [Intel-gfx] [PATCH 1/2] drm/i915/ats-m: add ATS-M platform info

[Balasubramani Vivekanandan]

Looks good to me.

Reviewed-by: Balasubramani Vivekanandan 

On 28.03.2022 17:08, Matt Roper wrote:
> ATS-M is a server platform based on Xe_HPG and Xe_HPM, but without
> display support.  From a driver point of view, it's easiest to just
> handle it as DG2 (including identifying as PLATFORM_DG2), but with the
> display disabled in the device info.
> 
> Signed-off-by: Matt Roper 
> ---
>  drivers/gpu/drm/i915/i915_pci.c | 40 -
>  1 file changed, 25 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 67b89769f577..2025e1114927 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1040,25 +1040,35 @@ static const struct intel_device_info xehpsdv_info = {
>   .require_force_probe = 1,
>  };
>  
> +#define DG2_FEATURES \
> + XE_HP_FEATURES, \
> + XE_HPM_FEATURES, \
> + DGFX_FEATURES, \
> + .graphics.rel = 55, \
> + .media.rel = 55, \
> + PLATFORM(INTEL_DG2), \
> + .has_4tile = 1, \
> + .has_64k_pages = 1, \
> + .has_guc_deprivilege = 1, \
> + .needs_compact_pt = 1, \
> + .platform_engine_mask = \
> + BIT(RCS0) | BIT(BCS0) | \
> + BIT(VECS0) | BIT(VECS1) | \
> + BIT(VCS0) | BIT(VCS2)
> +
>  static const struct intel_device_info dg2_info = {
> - XE_HP_FEATURES,
> - XE_HPM_FEATURES,
> + DG2_FEATURES,
>   XE_LPD_FEATURES,
> - DGFX_FEATURES,
> - .graphics.rel = 55,
> - .media.rel = 55,
> - .has_4tile = 1,
> - PLATFORM(INTEL_DG2),
> - .has_guc_deprivilege = 1,
> - .has_64k_pages = 1,
> - .needs_compact_pt = 1,
> - .platform_engine_mask =
> - BIT(RCS0) | BIT(BCS0) |
> - BIT(VECS0) | BIT(VECS1) |
> - BIT(VCS0) | BIT(VCS2),
> - .require_force_probe = 1,
>   .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>  BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> + .require_force_probe = 1,
> +};
> +
> +__maybe_unused
> +static const struct intel_device_info ats_m_info = {
> + DG2_FEATURES,
> + .display = { 0 },
> + .require_force_probe = 1,
>  };
>  
>  #undef PLATFORM
> -- 
> 2.34.1
> 

[Intel-gfx] [PATCH v3 10/18] drm/i915: Simplify power well definitions by adding power well instances

[Imre Deak]

All the port specific AUX/DDI_IO power wells share the same power well
ops struct and flags, so we can save some space and simplify the
definition of these by listing for all such power wells only the params
specific to them (name, domains, power well register index, id). Move
these params to a new i915_power_well_instance struct and convert the
per-platform power well definitions accordingly.

For all power well instance the name and power domain list params must
be specified, while the register index and id are optional, add the
I915_PW() macro that both simplifies the definitions and ensures that
the required params are set.

Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander 
---
 .../i915/display/intel_display_power_map.c| 1515 +
 .../i915/display/intel_display_power_well.c   |   72 +-
 .../i915/display/intel_display_power_well.h   |   48 +-
 3 files changed, 505 insertions(+), 1130 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c 
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index a9e0ebf18fca5..c282e05bfc1ac 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -30,16 +30,23 @@
 #define I915_PW_DOMAINS_NONE   NULL
 #define I915_PW_DOMAINS_ALL/* zero-length list */
 
+#define I915_PW_INSTANCES(...) \
+   (const struct i915_power_well_instance_list) \
+   __LIST(__LIST_INLINE_ELEMS(struct i915_power_well_instance, 
__VA_ARGS__))
+
+#define I915_PW(_name, _domain_list, ...) \
+   { .name = _name, .domain_list = _domain_list, ## __VA_ARGS__ }
+
 
 I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
 
 static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
{
-   .name = "always-on",
-   .domain_list = &i9xx_pwdoms_always_on,
+   .instances = &I915_PW_INSTANCES(
+   I915_PW("always-on", &i9xx_pwdoms_always_on),
+   ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
-   .id = DISP_PW_ID_NONE,
},
 };
 
@@ -54,16 +61,16 @@ I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
 
 static const struct i915_power_well_desc i830_power_wells[] = {
{
-   .name = "always-on",
-   .domain_list = &i9xx_pwdoms_always_on,
+   .instances = &I915_PW_INSTANCES(
+   I915_PW("always-on", &i9xx_pwdoms_always_on),
+   ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
-   .id = DISP_PW_ID_NONE,
}, {
-   .name = "pipes",
-   .domain_list = &i830_pwdoms_pipes,
+   .instances = &I915_PW_INSTANCES(
+   I915_PW("pipes", &i830_pwdoms_pipes),
+   ),
.ops = &i830_pipes_power_well_ops,
-   .id = DISP_PW_ID_NONE,
},
 };
 
@@ -87,20 +94,19 @@ I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
 
 static const struct i915_power_well_desc hsw_power_wells[] = {
{
-   .name = "always-on",
-   .domain_list = &i9xx_pwdoms_always_on,
+   .instances = &I915_PW_INSTANCES(
+   I915_PW("always-on", &i9xx_pwdoms_always_on),
+   ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
-   .id = DISP_PW_ID_NONE,
}, {
-   .name = "display",
-   .domain_list = &hsw_pwdoms_display,
+   .instances = &I915_PW_INSTANCES(
+   I915_PW("display", &hsw_pwdoms_display,
+   .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
+   .id = HSW_DISP_PW_GLOBAL),
+   ),
.ops = &hsw_power_well_ops,
.has_vga = true,
-   .id = HSW_DISP_PW_GLOBAL,
-   {
-   .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
-   },
},
 };
 
@@ -123,21 +129,20 @@ I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
 
 static const struct i915_power_well_desc bdw_power_wells[] = {
{
-   .name = "always-on",
-   .domain_list = &i9xx_pwdoms_always_on,
+   .instances = &I915_PW_INSTANCES(
+   I915_PW("always-on", &i9xx_pwdoms_always_on),
+   ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
-   .id = DISP_PW_ID_NONE,
}, {
-   .name = "display",
-   .domain_list = &bdw_pwdoms_display,
+   .instances = &I915_PW_INSTANCES(
+   I915_PW("display", &bdw_pwdoms_display,
+   .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
+   .id = HSW_DISP_PW_GLOBAL),
+   ),
.ops = &hsw_power_well_ops,
 

[Intel-gfx] [PATCH v3 06/18] drm/i915: Rename the power domain names to end with pipes/ports

[Imre Deak]

Make all power domain names end with the pipe/port instance for
consistency.

No functional changes.

Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/icl_dsi.c|   8 +-
 drivers/gpu/drm/i915/display/intel_ddi.c  |   2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  34 ++--
 .../drm/i915/display/intel_display_power.c| 116 +--
 .../drm/i915/display/intel_display_power.h|  66 +++
 .../i915/display/intel_display_power_map.c| 184 +-
 6 files changed, 205 insertions(+), 205 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 44f4c65522b97..019a98bbb769e 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -399,8 +399,8 @@ static void get_dsi_io_power_domains(struct 
drm_i915_private *dev_priv,
intel_dsi->io_wakeref[port] =
intel_display_power_get(dev_priv,
port == PORT_A ?
-   POWER_DOMAIN_PORT_DDI_A_IO :
-   POWER_DOMAIN_PORT_DDI_B_IO);
+   POWER_DOMAIN_PORT_DDI_IO_A :
+   POWER_DOMAIN_PORT_DDI_IO_B);
}
 }
 
@@ -1425,8 +1425,8 @@ static void gen11_dsi_disable_io_power(struct 
intel_encoder *encoder)
wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
intel_display_power_put(dev_priv,
port == PORT_A ?
-   POWER_DOMAIN_PORT_DDI_A_IO :
-   POWER_DOMAIN_PORT_DDI_B_IO,
+   POWER_DOMAIN_PORT_DDI_IO_A :
+   POWER_DOMAIN_PORT_DDI_IO_B,
wakeref);
}
 
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index dc208df829f16..afbb794d1f586 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4499,7 +4499,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
enum port port)
}
 
drm_WARN_ON(&dev_priv->drm, port > PORT_I);
-   dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
+   dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_IO_A +
  port - PORT_A;
 
if (init_dp) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 28bfb73ae6471..28ba0319357e6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2190,23 +2190,23 @@ enum intel_display_power_domain 
intel_port_to_power_domain(enum port port)
 {
switch (port) {
case PORT_A:
-   return POWER_DOMAIN_PORT_DDI_A_LANES;
+   return POWER_DOMAIN_PORT_DDI_LANES_A;
case PORT_B:
-   return POWER_DOMAIN_PORT_DDI_B_LANES;
+   return POWER_DOMAIN_PORT_DDI_LANES_B;
case PORT_C:
-   return POWER_DOMAIN_PORT_DDI_C_LANES;
+   return POWER_DOMAIN_PORT_DDI_LANES_C;
case PORT_D:
-   return POWER_DOMAIN_PORT_DDI_D_LANES;
+   return POWER_DOMAIN_PORT_DDI_LANES_D;
case PORT_E:
-   return POWER_DOMAIN_PORT_DDI_E_LANES;
+   return POWER_DOMAIN_PORT_DDI_LANES_E;
case PORT_F:
-   return POWER_DOMAIN_PORT_DDI_F_LANES;
+   return POWER_DOMAIN_PORT_DDI_LANES_F;
case PORT_G:
-   return POWER_DOMAIN_PORT_DDI_G_LANES;
+   return POWER_DOMAIN_PORT_DDI_LANES_G;
case PORT_H:
-   return POWER_DOMAIN_PORT_DDI_H_LANES;
+   return POWER_DOMAIN_PORT_DDI_LANES_H;
case PORT_I:
-   return POWER_DOMAIN_PORT_DDI_I_LANES;
+   return POWER_DOMAIN_PORT_DDI_LANES_I;
default:
MISSING_CASE(port);
return POWER_DOMAIN_PORT_OTHER;
@@ -2219,22 +2219,22 @@ intel_aux_power_domain(struct intel_digital_port 
*dig_port)
if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
switch (dig_port->aux_ch) {
case AUX_CH_C:
-   return POWER_DOMAIN_AUX_C_TBT;
+   return POWER_DOMAIN_AUX_TBT_C;
case AUX_CH_D:
-   return POWER_DOMAIN_AUX_D_TBT;
+   return POWER_DOMAIN_AUX_TBT_D;
case AUX_CH_E:
-   return POWER_DOMAIN_AUX_E_TBT;
+   return POWER_DOMAIN_AUX_TBT_E;
case AUX_CH_F:
-   return POWER_DOMAIN_AUX_F_TBT;
+   return POWER_DOMAIN_AUX_

[Intel-gfx] [PATCH v3 03/18] drm/i915: Move the power domain->well mappings to intel_display_power_map.c

[Imre Deak]

Move the list of platform specific power domain -> power well
definitions to intel_display_power_map.c. While at it group the
platforms' power domain macros with the corresponding power well lists
and keep all the power domain lists in the same order (matching the enum
order).

No functional changes.

v2:
- s/intel_display_power_internal.h/intel_display_power_map.h/ (Jani)
- Simplify intel_cleanup_power_wells().
- Don't move intel_display_power_domain_str().
v3:
- Rename intel_init/cleanup_power_wells() to
  intel_display_power_map_init/cleanup().
- Add documentation to intel_display_power_map_init/cleanup().

Cc: Jani Nikula 
Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander  (v2)
---
 drivers/gpu/drm/i915/Makefile |1 +
 .../drm/i915/display/intel_display_power.c| 2260 +
 .../i915/display/intel_display_power_map.c| 2150 
 .../i915/display/intel_display_power_map.h|   14 +
 4 files changed, 2168 insertions(+), 2257 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_power_map.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_power_map.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c1d5540f60529..469ee62982b4b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -216,6 +216,7 @@ i915-y += \
display/intel_cursor.o \
display/intel_display.o \
display/intel_display_power.o \
+   display/intel_display_power_map.o \
display/intel_display_power_well.o \
display/intel_dmc.o \
display/intel_dpio_phy.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 25b614bf09d83..e999433589715 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -11,6 +11,7 @@
 #include "intel_combo_phy.h"
 #include "intel_de.h"
 #include "intel_display_power.h"
+#include "intel_display_power_map.h"
 #include "intel_display_power_well.h"
 #include "intel_display_types.h"
 #include "intel_dmc.h"
@@ -848,2169 +849,6 @@ intel_display_power_put_mask_in_set(struct 
drm_i915_private *i915,
}
 }
 
-#define I830_PIPES_POWER_DOMAINS ( \
-   BIT_ULL(POWER_DOMAIN_PIPE_A) |  \
-   BIT_ULL(POWER_DOMAIN_PIPE_B) |  \
-   BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
-   BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
-   BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |\
-   BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
-   BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DISPLAY_POWER_DOMAINS (\
-   BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) |\
-   BIT_ULL(POWER_DOMAIN_PIPE_A) |  \
-   BIT_ULL(POWER_DOMAIN_PIPE_B) |  \
-   BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
-   BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
-   BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |\
-   BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |\
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\
-   BIT_ULL(POWER_DOMAIN_PORT_DSI) |\
-   BIT_ULL(POWER_DOMAIN_PORT_CRT) |\
-   BIT_ULL(POWER_DOMAIN_VGA) | \
-   BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
-   BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
-   BIT_ULL(POWER_DOMAIN_AUX_B) |   \
-   BIT_ULL(POWER_DOMAIN_AUX_C) |   \
-   BIT_ULL(POWER_DOMAIN_GMBUS) |   \
-   BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_CMN_BC_POWER_DOMAINS (\
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |\
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\
-   BIT_ULL(POWER_DOMAIN_PORT_CRT) |\
-   BIT_ULL(POWER_DOMAIN_AUX_B) |   \
-   BIT_ULL(POWER_DOMAIN_AUX_C) |   \
-   BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |\
-   BIT_ULL(POWER_DOMAIN_AUX_B) |   \
-   BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |\
-   BIT_ULL(POWER_DOMAIN_AUX_B) |   \
-   BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\
-   BIT_ULL(POWER_DOMAIN_AUX_C) |   \
-   BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
-   BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\
-   BIT_ULL(POWER_DOMAIN_AUX_C) |   \
-   BIT_ULL(POWER_DOMAIN_INIT))
-
-#define CHV_DISPLAY_POWER_DOMAINS (\
-   BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) |\
-   BIT_ULL(POWER_DOMAIN_PIPE_A) |  \
-   BIT_ULL(PO

[Intel-gfx] [PATCH v3 02/18] drm/i915: Unexport the for_each_power_well() macros

[Imre Deak]

The for_each_power_well() macros are only used in intel_display_power.c
and intel_display_power_well.c, so unexport them.

Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander 
---
 .../drm/i915/display/intel_display_power.c|  8 
 .../drm/i915/display/intel_display_power.h| 20 ---
 .../i915/display/intel_display_power_well.h   | 12 +++
 3 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 35a5e36df8206..25b614bf09d83 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -21,6 +21,14 @@
 #include "intel_snps_phy.h"
 #include "vlv_sideband.h"
 
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)
\
+   for_each_power_well(__dev_priv, __power_well)   
\
+   for_each_if((__power_well)->desc->domains & (__domain_mask))
+
+#define for_each_power_domain_well_reverse(__dev_priv, __power_well, 
__domain_mask) \
+   for_each_power_well_reverse(__dev_priv, __power_well)   
\
+   for_each_if((__power_well)->desc->domains & (__domain_mask))
+
 const char *
 intel_display_power_domain_str(enum intel_display_power_domain domain)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h 
b/drivers/gpu/drm/i915/display/intel_display_power.h
index 95b9391499109..e80317e7868b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -172,26 +172,6 @@ struct intel_display_power_domain_set {
for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
for_each_if(BIT_ULL(domain) & (mask))
 
-#define for_each_power_well(__dev_priv, __power_well)  
\
-   for ((__power_well) = (__dev_priv)->power_domains.power_wells;  \
-(__power_well) - (__dev_priv)->power_domains.power_wells < \
-   (__dev_priv)->power_domains.power_well_count;   \
-(__power_well)++)
-
-#define for_each_power_well_reverse(__dev_priv, __power_well)  
\
-   for ((__power_well) = (__dev_priv)->power_domains.power_wells + 
\
- (__dev_priv)->power_domains.power_well_count - 1; 
\
-(__power_well) - (__dev_priv)->power_domains.power_wells >= 0; 
\
-(__power_well)--)
-
-#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)
\
-   for_each_power_well(__dev_priv, __power_well)   
\
-   for_each_if((__power_well)->desc->domains & (__domain_mask))
-
-#define for_each_power_domain_well_reverse(__dev_priv, __power_well, 
__domain_mask) \
-   for_each_power_well_reverse(__dev_priv, __power_well)   
\
-   for_each_if((__power_well)->desc->domains & (__domain_mask))
-
 int intel_power_domains_init(struct drm_i915_private *dev_priv);
 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
resume);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h 
b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index de3ee1bfb06d9..c4a8a3d728e06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -12,6 +12,18 @@
 struct drm_i915_private;
 struct i915_power_well;
 
+#define for_each_power_well(__dev_priv, __power_well)  
\
+   for ((__power_well) = (__dev_priv)->power_domains.power_wells;  \
+(__power_well) - (__dev_priv)->power_domains.power_wells < \
+   (__dev_priv)->power_domains.power_well_count;   \
+(__power_well)++)
+
+#define for_each_power_well_reverse(__dev_priv, __power_well)  
\
+   for ((__power_well) = (__dev_priv)->power_domains.power_wells + 
\
+ (__dev_priv)->power_domains.power_well_count - 1; 
\
+(__power_well) - (__dev_priv)->power_domains.power_wells >= 0; 
\
+(__power_well)--)
+
 /*
  * i915_power_well_id:
  *
-- 
2.30.2

[Intel-gfx] [PATCH v3 01/18] drm/i915: Move per-platform power well hooks to intel_display_power_well.c

[Imre Deak]

Move the implementation of platform specific power well hooks to
intel_display_power_well.c, to reduce the clutter in
intel_display_power.c.

The locking of all the power domain/power well state is handled in the
power domain functions in intel_display_power.c using
i915_power_domains::lock. This patch also moves the
chy_phy_powergate_ch/lanes() functions to intel_display_power_well.c
which borrow the same lock to protect the DISPLAY_PHY_CONTROL register
state, which the HW uses both for toggling power wells and power gating
PHY lanes.

No functional change.

v2:
- Clarify in the commit log why CHV functions using the
  i915_power_domains::lock were moved, while others locking the power
  domain/well state were kept in intel_display_power.c . (Jouni)
- Move forward declaration of chv_phy_powergate_ch/lanes() to
  intel_display_power_well.h .

Signed-off-by: Imre Deak 
---
 .../drm/i915/display/intel_display_power.c| 1759 
 .../drm/i915/display/intel_display_power.h|5 -
 .../i915/display/intel_display_power_well.c   | 1817 +
 .../i915/display/intel_display_power_well.h   |   62 +-
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |1 +
 drivers/gpu/drm/i915/display/intel_pps.c  |1 +
 6 files changed, 1846 insertions(+), 1799 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 3dc859032bac7..35a5e36df8206 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -9,24 +9,16 @@
 #include "i915_irq.h"
 #include "intel_cdclk.h"
 #include "intel_combo_phy.h"
-#include "intel_combo_phy_regs.h"
-#include "intel_crt.h"
 #include "intel_de.h"
 #include "intel_display_power.h"
 #include "intel_display_power_well.h"
 #include "intel_display_types.h"
 #include "intel_dmc.h"
-#include "intel_dpio_phy.h"
-#include "intel_dpll.h"
-#include "intel_hotplug.h"
 #include "intel_mchbar_regs.h"
 #include "intel_pch_refclk.h"
 #include "intel_pcode.h"
 #include "intel_pm.h"
-#include "intel_pps.h"
 #include "intel_snps_phy.h"
-#include "intel_tc.h"
-#include "intel_vga.h"
 #include "vlv_sideband.h"
 
 const char *
@@ -235,604 +227,6 @@ bool intel_display_power_is_enabled(struct 
drm_i915_private *dev_priv,
return ret;
 }
 
-/*
- * Starting with Haswell, we have a "Power Down Well" that can be turned off
- * when not needed anymore. We have 4 registers that can request the power well
- * to be enabled, and it will only be disabled if none of the registers is
- * requesting it to be enabled.
- */
-static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
-  u8 irq_pipe_mask, bool has_vga)
-{
-   if (has_vga)
-   intel_vga_reset_io_mem(dev_priv);
-
-   if (irq_pipe_mask)
-   gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
-}
-
-static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
-  u8 irq_pipe_mask)
-{
-   if (irq_pipe_mask)
-   gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
-}
-
-#define ICL_AUX_PW_TO_CH(pw_idx)   \
-   ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
-
-#define ICL_TBT_AUX_PW_TO_CH(pw_idx)   \
-   ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
-
-static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well)
-{
-   int pw_idx = power_well->desc->hsw.idx;
-
-   return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
-ICL_AUX_PW_TO_CH(pw_idx);
-}
-
-static struct intel_digital_port *
-aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
-  enum aux_ch aux_ch)
-{
-   struct intel_digital_port *dig_port = NULL;
-   struct intel_encoder *encoder;
-
-   for_each_intel_encoder(&dev_priv->drm, encoder) {
-   /* We'll check the MST primary port */
-   if (encoder->type == INTEL_OUTPUT_DP_MST)
-   continue;
-
-   dig_port = enc_to_dig_port(encoder);
-   if (!dig_port)
-   continue;
-
-   if (dig_port->aux_ch != aux_ch) {
-   dig_port = NULL;
-   continue;
-   }
-
-   break;
-   }
-
-   return dig_port;
-}
-
-static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915,
- const struct i915_power_well *power_well)
-{
-   enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
-   struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, 
aux_ch);
-
-   return intel_port_to_phy(i915, dig_port->base.port);
-}
-
-static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
-  struct i915_power_well *power_well,
-   

[Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings

[Imre Deak]

This is v3 of the second half of [1], rebased on drm-tip (containing the
first half [2]), addressing the review comments from Jouni and with a
minor documentation/rename change in patch 3.

[1] https://patchwork.freedesktop.org/series/99476/
[2] https://patchwork.freedesktop.org/series/100591/

Cc: Jouni Högander 
Cc: Jani Nikula 

Imre Deak (18):
  drm/i915: Move per-platform power well hooks to intel_display_power_well.c
  drm/i915: Unexport the for_each_power_well() macros
  drm/i915: Move the power domain->well mappings to intel_display_power_map.c
  drm/i915: Move the dg2 fixed_enable_delay power well param to a common 
bitfield
  drm/i915: Move the HSW power well flags to a common bitfield
  drm/i915: Rename the power domain names to end with pipes/ports
  drm/i915: Sanitize the power well names
  drm/i915: Convert the power well descriptor domain mask to an array of domains
  drm/i915: Convert the u64 power well domains mask to a bitmap
  drm/i915: Simplify power well definitions by adding power well instances
  drm/i915: Allow platforms to share power well descriptors
  drm/i915: Simplify the DG1 power well descriptors
  drm/i915: Sanitize the ADL-S power well definition
  drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform
  drm/i915: Remove the aliasing of power domain enum values
  drm/i915: Remove the ICL specific TBT power domains
  drm/i915: Remove duplicate DDI/AUX power domain mappings
  drm/i915: Remove the XELPD specific AUX and DDI power domains

 drivers/gpu/drm/i915/Makefile |1 +
 drivers/gpu/drm/i915/display/g4x_dp.c |3 +-
 drivers/gpu/drm/i915/display/g4x_hdmi.c   |3 +-
 drivers/gpu/drm/i915/display/icl_dsi.c|8 +-
 drivers/gpu/drm/i915/display/intel_ddi.c  |6 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  150 +-
 drivers/gpu/drm/i915/display/intel_display.h  |4 +-
 .../drm/i915/display/intel_display_power.c| 4477 ++---
 .../drm/i915/display/intel_display_power.h|  122 +-
 .../i915/display/intel_display_power_map.c| 1501 ++
 .../i915/display/intel_display_power_map.h|   14 +
 .../i915/display/intel_display_power_well.c   | 1838 ++-
 .../i915/display/intel_display_power_well.h   |  132 +-
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |1 +
 drivers/gpu/drm/i915/display/intel_pps.c  |1 +
 drivers/gpu/drm/i915/display/intel_tc.c   |5 +-
 16 files changed, 3881 insertions(+), 4385 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_power_map.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_power_map.h

-- 
2.30.2

[Intel-gfx] [PATCH v3 12/18] drm/i915: Simplify the DG1 power well descriptors

[Imre Deak]

Simplify the definition of DG1 power wells by reusing the identical
RKL DDI/AUX descriptors.

This reorders the DG1 DDI/AUX vs. PW4/5 power wells, but this shouldn't
make a difference (it is the order on RKL and the DDI/AUX power wells
don't have a dependency on PW4/5).

Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander 
---
 .../i915/display/intel_display_power_map.c| 24 ++-
 1 file changed, 7 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c 
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 7babe3f1a3624..4443cf0015d1e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1035,7 +1035,11 @@ static const struct i915_power_well_desc 
rkl_power_wells_main[] = {
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
-   }, {
+   },
+};
+
+static const struct i915_power_well_desc rkl_power_wells_ddi_aux[] = {
+   {
.instances = &I915_PW_INSTANCES(
I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_A),
I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_B),
@@ -1058,6 +1062,7 @@ static const struct i915_power_well_desc_list 
rkl_power_wells[] = {
I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
I915_PW_DESCRIPTORS(rkl_power_wells_main),
+   I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux),
 };
 
 /*
@@ -1117,22 +1122,6 @@ static const struct i915_power_well_desc 
dg1_power_wells_main[] = {
.irq_pipe_mask = BIT(PIPE_B),
.has_vga = true,
.has_fuses = true,
-   }, {
-   .instances = &I915_PW_INSTANCES(
-   I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_A),
-   I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_B),
-   I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx 
= TGL_PW_CTL_IDX_DDI_TC1),
-   I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx 
= TGL_PW_CTL_IDX_DDI_TC2),
-   ),
-   .ops = &icl_ddi_power_well_ops,
-   }, {
-   .instances = &I915_PW_INSTANCES(
-   I915_PW("AUX_A", &tgl_pwdoms_aux_a, .hsw.idx = 
ICL_PW_CTL_IDX_AUX_A),
-   I915_PW("AUX_B", &tgl_pwdoms_aux_b, .hsw.idx = 
ICL_PW_CTL_IDX_AUX_B),
-   I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = 
TGL_PW_CTL_IDX_AUX_TC1),
-   I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = 
TGL_PW_CTL_IDX_AUX_TC2),
-   ),
-   .ops = &icl_aux_power_well_ops,
}, {
.instances = &I915_PW_INSTANCES(
I915_PW("PW_4", &tgl_pwdoms_pw_4,
@@ -1156,6 +1145,7 @@ static const struct i915_power_well_desc_list 
dg1_power_wells[] = {
I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
I915_PW_DESCRIPTORS(dg1_power_wells_main),
+   I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux),
 };
 
 /*
-- 
2.30.2

[Intel-gfx] [PATCH v3 09/18] drm/i915: Convert the u64 power well domains mask to a bitmap

[Imre Deak]

To remove the aliasing of the power domain enum values in a follow-up
patch in this patchset (requiring a bigger mask) and allow for defining
additional power domains in the future (at least some upcoming TypeC
changes requires this) convert the u64 i915_power_well_desc::domains
mask to a bitmap.

For simplicity I changed the for_each_power_domain_well() macros to
accept one domain only instead of a mask, as there isn't any current
user passing multiple domains.

v2: Don't add a typedef for the bitmap struct. (Jani)

Cc: Jani Nikula 
Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_display.c  |  65 ++-
 .../drm/i915/display/intel_display_power.c| 108 +++---
 .../drm/i915/display/intel_display_power.h|  18 +--
 .../i915/display/intel_display_power_map.c|   4 +-
 .../i915/display/intel_display_power_well.c   |   4 +-
 .../i915/display/intel_display_power_well.h   |   5 +-
 6 files changed, 116 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 28ba0319357e6..fa6580cdbc4b2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2273,66 +2273,71 @@ intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
}
 }
 
-static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
+static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
+  struct intel_power_domain_mask *mask)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
struct drm_encoder *encoder;
enum pipe pipe = crtc->pipe;
-   u64 mask;
+
+   bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
 
if (!crtc_state->hw.active)
-   return 0;
+   return;
 
-   mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
-   mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(cpu_transcoder));
+   set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
+   set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
if (crtc_state->pch_pfit.enabled ||
crtc_state->pch_pfit.force_thru)
-   mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
+   set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
 
drm_for_each_encoder_mask(encoder, &dev_priv->drm,
  crtc_state->uapi.encoder_mask) {
struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 
-   mask |= BIT_ULL(intel_encoder->power_domain);
+   set_bit(intel_encoder->power_domain, mask->bits);
}
 
if (HAS_DDI(dev_priv) && crtc_state->has_audio)
-   mask |= BIT_ULL(POWER_DOMAIN_AUDIO_MMIO);
+   set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
 
if (crtc_state->shared_dpll)
-   mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
+   set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
 
if (crtc_state->dsc.compression_enable)
-   mask |= BIT_ULL(intel_dsc_power_domain(crtc, cpu_transcoder));
-
-   return mask;
+   set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), 
mask->bits);
 }
 
-static u64
-modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
+static void
+modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
+  struct intel_power_domain_mask *old_domains)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum intel_display_power_domain domain;
-   u64 domains, new_domains, old_domains;
+   struct intel_power_domain_mask domains, new_domains;
 
-   domains = get_crtc_power_domains(crtc_state);
+   get_crtc_power_domains(crtc_state, &domains);
 
-   new_domains = domains & ~crtc->enabled_power_domains.mask;
-   old_domains = crtc->enabled_power_domains.mask & ~domains;
+   bitmap_andnot(new_domains.bits,
+ domains.bits,
+ crtc->enabled_power_domains.mask.bits,
+ POWER_DOMAIN_NUM);
+   bitmap_andnot(old_domains->bits,
+ crtc->enabled_power_domains.mask.bits,
+ domains.bits,
+ POWER_DOMAIN_NUM);
 
-   for_each_power_domain(domain, new_domains)
+   for_each_power_domain(domain, &new_domains)
intel_display_power_get_in_set(dev_priv,
   &crtc->enabled_power_domains,
   domain);
-
-   return old_domains;
 }
 
 static void modeset_put_crtc_power_domains(struct intel_crtc *crtc,
- 

[Intel-gfx] [PATCH v3 16/18] drm/i915: Remove the ICL specific TBT power domains

[Imre Deak]

The spec calls the ICL TBT AUX power well instances TBT1-4 (similarly to
all later platforms), align the power domain names with the spec.

Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander 
---
 .../gpu/drm/i915/display/intel_display_power.c   | 10 +-
 .../gpu/drm/i915/display/intel_display_power.h   |  4 
 .../drm/i915/display/intel_display_power_map.c   | 16 
 3 files changed, 9 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7065b6265ea20..21da53aabff8b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -166,14 +166,6 @@ intel_display_power_domain_str(enum 
intel_display_power_domain domain)
return "AUX_E_XELPD";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
-   case POWER_DOMAIN_AUX_TBT_C:
-   return "AUX_TBT_C";
-   case POWER_DOMAIN_AUX_TBT_D:
-   return "AUX_TBT_D";
-   case POWER_DOMAIN_AUX_TBT_E:
-   return "AUX_TBT_E";
-   case POWER_DOMAIN_AUX_TBT_F:
-   return "AUX_TBT_F";
case POWER_DOMAIN_AUX_TBT1:
return "AUX_TBT1";
case POWER_DOMAIN_AUX_TBT2:
@@ -2341,7 +2333,7 @@ d11_port_domains[] = {
.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C,
.ddi_io = POWER_DOMAIN_PORT_DDI_IO_C,
.aux_legacy_usbc = POWER_DOMAIN_AUX_C,
-   .aux_tbt = POWER_DOMAIN_AUX_TBT_C,
+   .aux_tbt = POWER_DOMAIN_AUX_TBT1,
},
 };
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h 
b/drivers/gpu/drm/i915/display/intel_display_power.h
index b58c5bada6d85..e04b2ff7b4b99 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -100,10 +100,6 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_E_XELPD,
 
POWER_DOMAIN_AUX_IO_A,
-   POWER_DOMAIN_AUX_TBT_C,
-   POWER_DOMAIN_AUX_TBT_D,
-   POWER_DOMAIN_AUX_TBT_E,
-   POWER_DOMAIN_AUX_TBT_F,
 
POWER_DOMAIN_AUX_TBT1,
POWER_DOMAIN_AUX_TBT2,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c 
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 86d937f8bfe13..d9cf3d3bc02e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -622,10 +622,10 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
POWER_DOMAIN_AUX_D, \
POWER_DOMAIN_AUX_E, \
POWER_DOMAIN_AUX_F, \
-   POWER_DOMAIN_AUX_TBT_C, \
-   POWER_DOMAIN_AUX_TBT_D, \
-   POWER_DOMAIN_AUX_TBT_E, \
-   POWER_DOMAIN_AUX_TBT_F
+   POWER_DOMAIN_AUX_TBT1, \
+   POWER_DOMAIN_AUX_TBT2, \
+   POWER_DOMAIN_AUX_TBT3, \
+   POWER_DOMAIN_AUX_TBT4
 
 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3,
ICL_PW_3_POWER_DOMAINS,
@@ -668,10 +668,10 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,
POWER_DOMAIN_AUX_C);
 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d, POWER_DOMAIN_AUX_D);
 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e, POWER_DOMAIN_AUX_E);
 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f, POWER_DOMAIN_AUX_F);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1,  POWER_DOMAIN_AUX_TBT_C);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2,  POWER_DOMAIN_AUX_TBT_D);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3,  POWER_DOMAIN_AUX_TBT_E);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4,  POWER_DOMAIN_AUX_TBT_F);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1,  POWER_DOMAIN_AUX_TBT1);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2,  POWER_DOMAIN_AUX_TBT2);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3,  POWER_DOMAIN_AUX_TBT3);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4,  POWER_DOMAIN_AUX_TBT4);
 
 static const struct i915_power_well_desc icl_power_wells_pw_1[] = {
{
-- 
2.30.2

[Intel-gfx] [PATCH v3 08/18] drm/i915: Convert the power well descriptor domain mask to an array of domains

[Imre Deak]

The next patch converts the i915_power_well_desc::domain mask from a u64
mask to a bitmap. I didn't find a reasonably simple way to initialize
bitmaps statically, so prepare for the next patch here by converting the
masks to an array of domain enums and initing the masks from these
arrays during module loading.

v2: Clarify list vs. array in the commit message. (Jani)

Cc: Jani Nikula 
Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander 
---
 .../drm/i915/display/intel_display_power.c|4 +-
 .../i915/display/intel_display_power_map.c| 1427 +
 .../i915/display/intel_display_power_well.c   |2 +-
 .../i915/display/intel_display_power_well.h   |6 +-
 4 files changed, 754 insertions(+), 685 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index e524b24c329a2..b9ba8500bf984 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -24,11 +24,11 @@
 
 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)
\
for_each_power_well(__dev_priv, __power_well)   
\
-   for_each_if((__power_well)->desc->domains & (__domain_mask))
+   for_each_if((__power_well)->domains & (__domain_mask))
 
 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, 
__domain_mask) \
for_each_power_well_reverse(__dev_priv, __power_well)   
\
-   for_each_if((__power_well)->desc->domains & (__domain_mask))
+   for_each_if((__power_well)->domains & (__domain_mask))
 
 const char *
 intel_display_power_domain_str(enum intel_display_power_domain domain)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c 
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 42b813cf47dbf..b7aa13d6a33f3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -11,70 +11,90 @@
 #include "intel_display_power_map.h"
 #include "intel_display_power_well.h"
 
-#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
+#define __LIST_INLINE_ELEMS(__elem_type, ...) \
+   ((__elem_type[]) { __VA_ARGS__ })
+
+#define __LIST(__elems) { \
+   .list = __elems, \
+   .count = ARRAY_SIZE(__elems), \
+}
+
+#define I915_PW_DOMAINS(...) \
+   (const struct i915_power_domain_list) \
+   __LIST(__LIST_INLINE_ELEMS(enum intel_display_power_domain, 
__VA_ARGS__))
+
+#define I915_DECL_PW_DOMAINS(__name, ...) \
+   static const struct i915_power_domain_list __name = 
I915_PW_DOMAINS(__VA_ARGS__)
+
+/* Zero-length list assigns all power domains, a NULL list assigns none. */
+#define I915_PW_DOMAINS_NONE   NULL
+#define I915_PW_DOMAINS_ALL/* zero-length list */
+
+
+I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
 
 static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
{
.name = "always-on",
-   .domains = POWER_DOMAIN_MASK,
+   .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
},
 };
 
-#define I830_PIPES_POWER_DOMAINS ( \
-   BIT_ULL(POWER_DOMAIN_PIPE_A) |  \
-   BIT_ULL(POWER_DOMAIN_PIPE_B) |  \
-   BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
-   BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
-   BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |\
-   BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
-   BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
+   POWER_DOMAIN_PIPE_A,
+   POWER_DOMAIN_PIPE_B,
+   POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+   POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+   POWER_DOMAIN_TRANSCODER_A,
+   POWER_DOMAIN_TRANSCODER_B,
+   POWER_DOMAIN_INIT);
 
 static const struct i915_power_well_desc i830_power_wells[] = {
{
.name = "always-on",
-   .domains = POWER_DOMAIN_MASK,
+   .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "pipes",
-   .domains = I830_PIPES_POWER_DOMAINS,
+   .domain_list = &i830_pwdoms_pipes,
.ops = &i830_pipes_power_well_ops,
.id = DISP_PW_ID_NONE,
},
 };
 
-#define HSW_DISPLAY_POWER_DOMAINS (\
-   BIT_ULL(POWER_DOMAIN_PIPE_B) |  \
-   BIT_ULL(POWER_DOMAIN_PIPE_C) |  \
-   BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
-   BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
-   BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
-   B

[Intel-gfx] [PATCH v3 11/18] drm/i915: Allow platforms to share power well descriptors

[Imre Deak]

Some power wells - like always-on and skl+/icl+ PW_1 - with the same
name, domain list, flags, ops are used by multiple platforms, so allow
platforms to reuse the descriptors of such power wells.

This change also lets the follow up patches to simplify the DG1/RKL
power well definitions, and remove the ADL-S skip_mask special casing.

Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander 
---
 .../i915/display/intel_display_power_map.c| 281 --
 1 file changed, 122 insertions(+), 159 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c 
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index c282e05bfc1ac..7babe3f1a3624 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -38,9 +38,17 @@
{ .name = _name, .domain_list = _domain_list, ## __VA_ARGS__ }
 
 
+struct i915_power_well_desc_list {
+   const struct i915_power_well_desc *list;
+   u8 count;
+};
+
+#define I915_PW_DESCRIPTORS(x) __LIST(x)
+
+
 I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
 
-static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
+static const struct i915_power_well_desc i9xx_power_wells_always_on[] = {
{
.instances = &I915_PW_INSTANCES(
I915_PW("always-on", &i9xx_pwdoms_always_on),
@@ -50,6 +58,10 @@ static const struct i915_power_well_desc 
i9xx_always_on_power_well[] = {
},
 };
 
+static const struct i915_power_well_desc_list i9xx_power_wells[] = {
+   I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+};
+
 I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
POWER_DOMAIN_PIPE_A,
POWER_DOMAIN_PIPE_B,
@@ -59,14 +71,8 @@ I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_INIT);
 
-static const struct i915_power_well_desc i830_power_wells[] = {
+static const struct i915_power_well_desc i830_power_wells_main[] = {
{
-   .instances = &I915_PW_INSTANCES(
-   I915_PW("always-on", &i9xx_pwdoms_always_on),
-   ),
-   .ops = &i9xx_always_on_power_well_ops,
-   .always_on = true,
-   }, {
.instances = &I915_PW_INSTANCES(
I915_PW("pipes", &i830_pwdoms_pipes),
),
@@ -74,6 +80,11 @@ static const struct i915_power_well_desc i830_power_wells[] 
= {
},
 };
 
+static const struct i915_power_well_desc_list i830_power_wells[] = {
+   I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+   I915_PW_DESCRIPTORS(i830_power_wells_main),
+};
+
 I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
POWER_DOMAIN_PIPE_B,
POWER_DOMAIN_PIPE_C,
@@ -92,14 +103,8 @@ I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
POWER_DOMAIN_AUDIO_PLAYBACK,
POWER_DOMAIN_INIT);
 
-static const struct i915_power_well_desc hsw_power_wells[] = {
+static const struct i915_power_well_desc hsw_power_wells_main[] = {
{
-   .instances = &I915_PW_INSTANCES(
-   I915_PW("always-on", &i9xx_pwdoms_always_on),
-   ),
-   .ops = &i9xx_always_on_power_well_ops,
-   .always_on = true,
-   }, {
.instances = &I915_PW_INSTANCES(
I915_PW("display", &hsw_pwdoms_display,
.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
@@ -110,6 +115,11 @@ static const struct i915_power_well_desc hsw_power_wells[] 
= {
},
 };
 
+static const struct i915_power_well_desc_list hsw_power_wells[] = {
+   I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+   I915_PW_DESCRIPTORS(hsw_power_wells_main),
+};
+
 I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
POWER_DOMAIN_PIPE_B,
POWER_DOMAIN_PIPE_C,
@@ -127,14 +137,8 @@ I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
POWER_DOMAIN_AUDIO_PLAYBACK,
POWER_DOMAIN_INIT);
 
-static const struct i915_power_well_desc bdw_power_wells[] = {
+static const struct i915_power_well_desc bdw_power_wells_main[] = {
{
-   .instances = &I915_PW_INSTANCES(
-   I915_PW("always-on", &i9xx_pwdoms_always_on),
-   ),
-   .ops = &i9xx_always_on_power_well_ops,
-   .always_on = true,
-   }, {
.instances = &I915_PW_INSTANCES(
I915_PW("display", &bdw_pwdoms_display,
.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
@@ -146,6 +150,11 @@ static const struct i915_power_well_desc bdw_power_wells[] 
= {
},
 };
 
+static const struct i915_power_well_desc_list bdw_power_wells[] = {
+   I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+   I915_PW_DESCRIPTORS(bdw_power_wells_main),
+};
+
 I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
POWER_DOMAIN_DISPLAY_CORE,
POWER_DOMAIN_PIPE_A,
@@ -181,14 +190,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_

[Intel-gfx] [PATCH v3 14/18] drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform

[Imre Deak]

Atm the port -> DDI and AUX power domain mapping is specified by relying
on the aliasing of the platform specific intel_display_power_domain enum
values. For instance D12+ platforms refer to the 'D' port and power
domain instances, which doesn't match the bspec terminology, on these
platforms the corresponding port is TC1. To make it clear what
port/domain the code refers to add a mapping between them which matches
the bspec terms on different display versions.

This also allows for removing the aliasing in enum values in a follow-up
patch.

v2: Add the functions to intel_display_power.c, use
intel_display_power_ prefix.

Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/g4x_dp.c |   3 +-
 drivers/gpu/drm/i915/display/g4x_hdmi.c   |   3 +-
 drivers/gpu/drm/i915/display/intel_ddi.c  |   6 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  85 +---
 drivers/gpu/drm/i915/display/intel_display.h  |   4 +-
 .../drm/i915/display/intel_display_power.c| 206 ++
 .../drm/i915/display/intel_display_power.h|  12 +
 drivers/gpu/drm/i915/display/intel_tc.c   |   5 +-
 8 files changed, 235 insertions(+), 89 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c 
b/drivers/gpu/drm/i915/display/g4x_dp.c
index 8e1338678d91a..ec353dece49bc 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -13,6 +13,7 @@
 #include "intel_connector.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
+#include "intel_display_power.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_dp_link_training.h"
@@ -1383,7 +1384,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
dig_port->max_lanes = 4;
 
intel_encoder->type = INTEL_OUTPUT_DP;
-   intel_encoder->power_domain = intel_port_to_power_domain(port);
+   intel_encoder->power_domain = 
intel_display_power_ddi_lanes_domain(dev_priv, port);
if (IS_CHERRYVIEW(dev_priv)) {
if (port == PORT_D)
intel_encoder->pipe_mask = BIT(PIPE_C);
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c 
b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 06e00b1eaa7ce..56fa6dfba020c 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -10,6 +10,7 @@
 #include "intel_connector.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
+#include "intel_display_power.h"
 #include "intel_display_types.h"
 #include "intel_dpio_phy.h"
 #include "intel_fifo_underrun.h"
@@ -588,7 +589,7 @@ void g4x_hdmi_init(struct drm_i915_private *dev_priv,
intel_encoder->shutdown = intel_hdmi_encoder_shutdown;
 
intel_encoder->type = INTEL_OUTPUT_HDMI;
-   intel_encoder->power_domain = intel_port_to_power_domain(port);
+   intel_encoder->power_domain = 
intel_display_power_ddi_lanes_domain(dev_priv, port);
intel_encoder->port = port;
if (IS_CHERRYVIEW(dev_priv)) {
if (port == PORT_D)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index afbb794d1f586..7ce3bdca5f8fe 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -40,6 +40,7 @@
 #include "intel_ddi.h"
 #include "intel_ddi_buf_trans.h"
 #include "intel_de.h"
+#include "intel_display_power.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_dp_link_training.h"
@@ -4371,7 +4372,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
enum port port)
encoder->get_power_domains = intel_ddi_get_power_domains;
 
encoder->type = INTEL_OUTPUT_DDI;
-   encoder->power_domain = intel_port_to_power_domain(port);
+   encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, 
port);
encoder->port = port;
encoder->cloneable = 0;
encoder->pipe_mask = ~0;
@@ -4499,8 +4500,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
enum port port)
}
 
drm_WARN_ON(&dev_priv->drm, port > PORT_I);
-   dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_IO_A +
- port - PORT_A;
+   dig_port->ddi_io_power_domain = 
intel_display_power_ddi_io_domain(dev_priv, port);
 
if (init_dp) {
if (!intel_ddi_init_dp_connector(dig_port))
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index fa6580cdbc4b2..e0337cc88bb24 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -51,6 +51,7 @@
 #include "display/intel_crt.h"
 #include "display/intel_ddi.h"
 #include "display/intel_display_debugfs.h"
+#include "display/intel_display_power.h"
 #include "display/intel_dp.h"
 #include "display/intel_dp_mst.h"
 #include "display/intel_dpll.h"
@@ -2186,91 +2187,15 @@ enum tc_port intel_port_to_tc(struct 

[Intel-gfx] [PATCH v3 17/18] drm/i915: Remove duplicate DDI/AUX power domain mappings

[Imre Deak]

The DDI and AUX domain -> power well mappings are identical for a few
platforms/power well instances, reuse the mappings of earlier platforms
for these removing the duplicate mapping of new platforms.

Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander 
---
 .../i915/display/intel_display_power_map.c| 89 +++
 1 file changed, 31 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c 
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index d9cf3d3bc02e7..d647fb5da6b44 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -653,9 +653,6 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off,
POWER_DOMAIN_DC_OFF,
POWER_DOMAIN_INIT);
 
-I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_a,  POWER_DOMAIN_PORT_DDI_IO_A);
-I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_b,  POWER_DOMAIN_PORT_DDI_IO_B);
-I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_c,  POWER_DOMAIN_PORT_DDI_IO_C);
 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_d,  POWER_DOMAIN_PORT_DDI_IO_D);
 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e,  POWER_DOMAIN_PORT_DDI_IO_E);
 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f,  POWER_DOMAIN_PORT_DDI_IO_F);
@@ -714,9 +711,9 @@ static const struct i915_power_well_desc 
icl_power_wells_main[] = {
.has_fuses = true,
}, {
.instances = &I915_PW_INSTANCES(
-   I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_A),
-   I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_B),
-   I915_PW("DDI_IO_C", &icl_pwdoms_ddi_io_c, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_C),
+   I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_A),
+   I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_B),
+   I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_C),
I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_D),
I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_E),
I915_PW("DDI_IO_F", &icl_pwdoms_ddi_io_f, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_F),
@@ -828,12 +825,6 @@ I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc4,
POWER_DOMAIN_PORT_DDI_IO_TC4);
 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc5,POWER_DOMAIN_PORT_DDI_IO_TC5);
 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc6,POWER_DOMAIN_PORT_DDI_IO_TC6);
 
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_a,
-   POWER_DOMAIN_AUX_A,
-   POWER_DOMAIN_AUX_IO_A);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_b, POWER_DOMAIN_AUX_B);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_c, POWER_DOMAIN_AUX_C);
-
 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1);
 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2);
 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3);
@@ -841,10 +832,6 @@ I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc4, 
POWER_DOMAIN_AUX_USBC4);
 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc5, POWER_DOMAIN_AUX_USBC5);
 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc6, POWER_DOMAIN_AUX_USBC6);
 
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt1,  POWER_DOMAIN_AUX_TBT1);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt2,  POWER_DOMAIN_AUX_TBT2);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt3,  POWER_DOMAIN_AUX_TBT3);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt4,  POWER_DOMAIN_AUX_TBT4);
 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt5,  POWER_DOMAIN_AUX_TBT5);
 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt6,  POWER_DOMAIN_AUX_TBT6);
 
@@ -890,9 +877,9 @@ static const struct i915_power_well_desc 
tgl_power_wells_main[] = {
.has_fuses = true,
}, {
.instances = &I915_PW_INSTANCES(
-   I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_A),
-   I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_B),
-   I915_PW("DDI_IO_C", &icl_pwdoms_ddi_io_c, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_C),
+   I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_A),
+   I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_B),
+   I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = 
ICL_PW_CTL_IDX_DDI_C),
I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx 
= TGL_PW_CTL_IDX_DDI_TC1),
I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx 
= TGL_PW_CTL_IDX_DDI_TC2),
I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx 
= TGL_PW_CTL_IDX_DDI_TC3),
@@ -933,9 +920,9 @@ static const struct i915_power_well_desc 
tgl_power_wells_tc_cold_off[] = {
 static const struct i915_power_well_desc tg

[Intel-gfx] [PATCH v3 18/18] drm/i915: Remove the XELPD specific AUX and DDI power domains

[Imre Deak]

The spec calls the XELPD_D/E ports just D/E, the platform prefix in the
domain names was only needed by the port->domain mapping relying on
matching enum values for the whole port/domain range (and the
corresponding aliasing between the platform specific domain enums).
Since a previous patch we can define the port->domain mapping explicitly
so do this by reusing the already existing D/E power domain names.

Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander 
---
 .../drm/i915/display/intel_display_power.c| 18 +++
 .../drm/i915/display/intel_display_power.h|  9 
 .../i915/display/intel_display_power_map.c| 22 +++
 3 files changed, 11 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 21da53aabff8b..831eb122953c6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -92,10 +92,6 @@ intel_display_power_domain_str(enum 
intel_display_power_domain domain)
return "PORT_DDI_LANES_TC5";
case POWER_DOMAIN_PORT_DDI_LANES_TC6:
return "PORT_DDI_LANES_TC6";
-   case POWER_DOMAIN_PORT_DDI_LANES_D_XELPD:
-   return "PORT_DDI_LANES_D_XELPD";
-   case POWER_DOMAIN_PORT_DDI_LANES_E_XELPD:
-   return "PORT_DDI_LANES_E_XELPD";
case POWER_DOMAIN_PORT_DDI_IO_A:
return "PORT_DDI_IO_A";
case POWER_DOMAIN_PORT_DDI_IO_B:
@@ -120,10 +116,6 @@ intel_display_power_domain_str(enum 
intel_display_power_domain domain)
return "PORT_DDI_IO_TC5";
case POWER_DOMAIN_PORT_DDI_IO_TC6:
return "PORT_DDI_IO_TC6";
-   case POWER_DOMAIN_PORT_DDI_IO_D_XELPD:
-   return "PORT_DDI_IO_D_XELPD";
-   case POWER_DOMAIN_PORT_DDI_IO_E_XELPD:
-   return "PORT_DDI_IO_E_XELPD";
case POWER_DOMAIN_PORT_DSI:
return "PORT_DSI";
case POWER_DOMAIN_PORT_CRT:
@@ -160,10 +152,6 @@ intel_display_power_domain_str(enum 
intel_display_power_domain domain)
return "AUX_USBC5";
case POWER_DOMAIN_AUX_USBC6:
return "AUX_USBC6";
-   case POWER_DOMAIN_AUX_D_XELPD:
-   return "AUX_D_XELPD";
-   case POWER_DOMAIN_AUX_E_XELPD:
-   return "AUX_E_XELPD";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
case POWER_DOMAIN_AUX_TBT1:
@@ -2390,9 +2378,9 @@ d13_port_domains[] = {
.aux_ch_start = AUX_CH_D_XELPD,
.aux_ch_end = AUX_CH_E_XELPD,
 
-   .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D_XELPD,
-   .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D_XELPD,
-   .aux_legacy_usbc = POWER_DOMAIN_AUX_D_XELPD,
+   .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D,
+   .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D,
+   .aux_legacy_usbc = POWER_DOMAIN_AUX_D,
.aux_tbt = POWER_DOMAIN_INVALID,
},
 };
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h 
b/drivers/gpu/drm/i915/display/intel_display_power.h
index e04b2ff7b4b99..7136ea3f233e9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -56,9 +56,6 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_LANES_TC5,
POWER_DOMAIN_PORT_DDI_LANES_TC6,
 
-   POWER_DOMAIN_PORT_DDI_LANES_D_XELPD,
-   POWER_DOMAIN_PORT_DDI_LANES_E_XELPD,
-
POWER_DOMAIN_PORT_DDI_IO_A,
POWER_DOMAIN_PORT_DDI_IO_B,
POWER_DOMAIN_PORT_DDI_IO_C,
@@ -73,9 +70,6 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_IO_TC5,
POWER_DOMAIN_PORT_DDI_IO_TC6,
 
-   POWER_DOMAIN_PORT_DDI_IO_D_XELPD,
-   POWER_DOMAIN_PORT_DDI_IO_E_XELPD,
-
POWER_DOMAIN_PORT_DSI,
POWER_DOMAIN_PORT_CRT,
POWER_DOMAIN_PORT_OTHER,
@@ -96,9 +90,6 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_USBC5,
POWER_DOMAIN_AUX_USBC6,
 
-   POWER_DOMAIN_AUX_D_XELPD,
-   POWER_DOMAIN_AUX_E_XELPD,
-
POWER_DOMAIN_AUX_IO_A,
 
POWER_DOMAIN_AUX_TBT1,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c 
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index d647fb5da6b44..af6f54a26a351 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1207,8 +1207,8 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
XELPD_PW_C_POWER_DOMAINS, \
XELPD_PW_D_POWER_DOMAINS, \
POWER_DOMAIN_PORT_DDI_LANES_C, \
-   POWER_DOMAIN_PORT_DDI_LANES_D_XELPD, \
-   POWER_DOMAIN_PORT_DDI_LANES_E_XELPD, \
+   POWER_DOMAIN_PORT_DDI_LANES_D, \
+   POWER_DOMAIN_PORT_DDI_LANES_E, \
POWER_DOMAIN_PORT_DDI_LANES_TC1, \
POWER_DOMAIN_PORT_DDI_LANES_TC2, \
POWER_DOM

[Intel-gfx] [PATCH v3 15/18] drm/i915: Remove the aliasing of power domain enum values

[Imre Deak]

Aliasing the intel_display_power_domain enum values was required because
of the u64 power domain mask size limit. This makes the dmesg/debugfs
printouts of the domain names somewhat unclear, for instance domain
names for port D are shown on D12+ platforms where the corresponding
port is called TC1. Make this clearer by removing the aliasing which is
possible after a previous patch converting the mask to a bitmap.

Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander 
---
 .../drm/i915/display/intel_display_power.c| 84 +--
 .../drm/i915/display/intel_display_power.h| 26 ++
 2 files changed, 67 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 5915d70eaf00b..7065b6265ea20 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -80,12 +80,22 @@ intel_display_power_domain_str(enum 
intel_display_power_domain domain)
return "PORT_DDI_LANES_E";
case POWER_DOMAIN_PORT_DDI_LANES_F:
return "PORT_DDI_LANES_F";
-   case POWER_DOMAIN_PORT_DDI_LANES_G:
-   return "PORT_DDI_LANES_G";
-   case POWER_DOMAIN_PORT_DDI_LANES_H:
-   return "PORT_DDI_LANES_H";
-   case POWER_DOMAIN_PORT_DDI_LANES_I:
-   return "PORT_DDI_LANES_I";
+   case POWER_DOMAIN_PORT_DDI_LANES_TC1:
+   return "PORT_DDI_LANES_TC1";
+   case POWER_DOMAIN_PORT_DDI_LANES_TC2:
+   return "PORT_DDI_LANES_TC2";
+   case POWER_DOMAIN_PORT_DDI_LANES_TC3:
+   return "PORT_DDI_LANES_TC3";
+   case POWER_DOMAIN_PORT_DDI_LANES_TC4:
+   return "PORT_DDI_LANES_TC4";
+   case POWER_DOMAIN_PORT_DDI_LANES_TC5:
+   return "PORT_DDI_LANES_TC5";
+   case POWER_DOMAIN_PORT_DDI_LANES_TC6:
+   return "PORT_DDI_LANES_TC6";
+   case POWER_DOMAIN_PORT_DDI_LANES_D_XELPD:
+   return "PORT_DDI_LANES_D_XELPD";
+   case POWER_DOMAIN_PORT_DDI_LANES_E_XELPD:
+   return "PORT_DDI_LANES_E_XELPD";
case POWER_DOMAIN_PORT_DDI_IO_A:
return "PORT_DDI_IO_A";
case POWER_DOMAIN_PORT_DDI_IO_B:
@@ -98,12 +108,22 @@ intel_display_power_domain_str(enum 
intel_display_power_domain domain)
return "PORT_DDI_IO_E";
case POWER_DOMAIN_PORT_DDI_IO_F:
return "PORT_DDI_IO_F";
-   case POWER_DOMAIN_PORT_DDI_IO_G:
-   return "PORT_DDI_IO_G";
-   case POWER_DOMAIN_PORT_DDI_IO_H:
-   return "PORT_DDI_IO_H";
-   case POWER_DOMAIN_PORT_DDI_IO_I:
-   return "PORT_DDI_IO_I";
+   case POWER_DOMAIN_PORT_DDI_IO_TC1:
+   return "PORT_DDI_IO_TC1";
+   case POWER_DOMAIN_PORT_DDI_IO_TC2:
+   return "PORT_DDI_IO_TC2";
+   case POWER_DOMAIN_PORT_DDI_IO_TC3:
+   return "PORT_DDI_IO_TC3";
+   case POWER_DOMAIN_PORT_DDI_IO_TC4:
+   return "PORT_DDI_IO_TC4";
+   case POWER_DOMAIN_PORT_DDI_IO_TC5:
+   return "PORT_DDI_IO_TC5";
+   case POWER_DOMAIN_PORT_DDI_IO_TC6:
+   return "PORT_DDI_IO_TC6";
+   case POWER_DOMAIN_PORT_DDI_IO_D_XELPD:
+   return "PORT_DDI_IO_D_XELPD";
+   case POWER_DOMAIN_PORT_DDI_IO_E_XELPD:
+   return "PORT_DDI_IO_E_XELPD";
case POWER_DOMAIN_PORT_DSI:
return "PORT_DSI";
case POWER_DOMAIN_PORT_CRT:
@@ -128,12 +148,22 @@ intel_display_power_domain_str(enum 
intel_display_power_domain domain)
return "AUX_E";
case POWER_DOMAIN_AUX_F:
return "AUX_F";
-   case POWER_DOMAIN_AUX_G:
-   return "AUX_G";
-   case POWER_DOMAIN_AUX_H:
-   return "AUX_H";
-   case POWER_DOMAIN_AUX_I:
-   return "AUX_I";
+   case POWER_DOMAIN_AUX_USBC1:
+   return "AUX_USBC1";
+   case POWER_DOMAIN_AUX_USBC2:
+   return "AUX_USBC2";
+   case POWER_DOMAIN_AUX_USBC3:
+   return "AUX_USBC3";
+   case POWER_DOMAIN_AUX_USBC4:
+   return "AUX_USBC4";
+   case POWER_DOMAIN_AUX_USBC5:
+   return "AUX_USBC5";
+   case POWER_DOMAIN_AUX_USBC6:
+   return "AUX_USBC6";
+   case POWER_DOMAIN_AUX_D_XELPD:
+   return "AUX_D_XELPD";
+   case POWER_DOMAIN_AUX_E_XELPD:
+   return "AUX_E_XELPD";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
case POWER_DOMAIN_AUX_TBT_C:
@@ -144,12 +174,18 @@ intel_display_power_domain_str(enum 
intel_display_power_domain domain)
return "AUX_TBT_E";
case POWER_DOMAIN_AUX_TBT_F:
return "AUX_TBT_F";
-   case POWER_DOMAIN_AUX_TBT_G:
-   return "AUX_TBT_G";
-   case POWER_DOMAIN_AUX_TBT_H:
-   return "AUX_TBT_H";
-   case POWER_D

[Intel-gfx] [PATCH v3 04/18] drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield

[Imre Deak]

The DG2 fixed delay duration is always 600usec, so save some space in
the power well descriptors by converting the parameter to a flag. While
at it also use a bitfield for both the always_on and fixed_enable_delay
flag.

This change also lets simplifying the definiton of power wells sharing
the same flags in an upcoming patch.

Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander 
---
 .../gpu/drm/i915/display/intel_display_power_map.c | 10 +-
 .../drm/i915/display/intel_display_power_well.c|  5 ++---
 .../drm/i915/display/intel_display_power_well.h| 14 +++---
 3 files changed, 14 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c 
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 97e0daec95449..e1824936a998f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1920,37 +1920,37 @@ static const struct i915_power_well_desc 
xelpd_power_wells[] = {
.name = "AUX A",
.domains = ICL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+   .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
-   .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX B",
.domains = ICL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+   .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
-   .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX C",
.domains = TGL_AUX_C_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+   .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
-   .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX D_XELPD",
.domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+   .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
-   .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX E_XELPD",
@@ -1964,10 +1964,10 @@ static const struct i915_power_well_desc 
xelpd_power_wells[] = {
.name = "AUX USBC1",
.domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+   .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
-   .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX USBC2",
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c 
b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index a92bb807f1972..0e13c15edfdd2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -242,15 +242,14 @@ static void hsw_wait_for_power_well_enable(struct 
drm_i915_private *dev_priv,
 {
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
int pw_idx = power_well->desc->hsw.idx;
-   int enable_delay = power_well->desc->hsw.fixed_enable_delay;
 
/*
 * For some power wells we're not supposed to watch the status bit for
 * an ack, but rather just wait a fixed amount of time and then
 * proceed.  This is only used on DG2.
 */
-   if (IS_DG2(dev_priv) && enable_delay) {
-   usleep_range(enable_delay, 2 * enable_delay);
+   if (IS_DG2(dev_priv) && power_well->desc->fixed_enable_delay) {
+   usleep_range(600, 1200);
return;
}
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h 
b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index c4a8a3d728e06..cb4681d0ffc6a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -50,8 +50,14 @@ enum i915_power_well_id {
 
 struct i915_power_well_desc {
const char *name;
-   bool always_on;
u64 domains;
+   u8 always_on:1;
+   /*
+* Instead of waiting for the status bit to ack enables,
+* just wait a specific amount of time and then consider
+* the well enabled.
+*/
+   u8 fixed_enable_delay:1;
/* unique identifier for this power well */
enum i915_power_well_id id;
/*
@@ -77,12 +83,6 @@

[Intel-gfx] [PATCH v3 05/18] drm/i915: Move the HSW power well flags to a common bitfield

[Imre Deak]

Save some space by grouping the HSW power well descriptor flags along
with other flags in one bitfield.

This change also lets simplifying the definition of power well
descriptors sharing the same flags in an upcoming patch.

Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander 
---
 .../i915/display/intel_display_power_map.c| 166 +-
 .../i915/display/intel_display_power_well.c   |  16 +-
 .../i915/display/intel_display_power_well.h   |  25 +--
 3 files changed, 104 insertions(+), 103 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c 
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index e1824936a998f..d566e638ac9b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -76,10 +76,10 @@ static const struct i915_power_well_desc hsw_power_wells[] 
= {
.name = "display",
.domains = HSW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+   .has_vga = true,
.id = HSW_DISP_PW_GLOBAL,
{
.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
-   .hsw.has_vga = true,
},
},
 };
@@ -112,11 +112,11 @@ static const struct i915_power_well_desc 
bdw_power_wells[] = {
.name = "display",
.domains = BDW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+   .has_vga = true,
+   .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.id = HSW_DISP_PW_GLOBAL,
{
.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
-   .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
-   .hsw.has_vga = true,
},
},
 };
@@ -368,10 +368,10 @@ static const struct i915_power_well_desc 
skl_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+   .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
-   .hsw.has_fuses = true,
},
}, {
.name = "MISC IO power well",
@@ -392,12 +392,12 @@ static const struct i915_power_well_desc 
skl_power_wells[] = {
.name = "power well 2",
.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+   .has_vga = true,
+   .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+   .has_fuses = true,
.id = SKL_DISP_PW_2,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_2,
-   .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
-   .hsw.has_vga = true,
-   .hsw.has_fuses = true,
},
}, {
.name = "DDI A/E IO power well",
@@ -484,10 +484,10 @@ static const struct i915_power_well_desc 
bxt_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+   .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
-   .hsw.has_fuses = true,
},
}, {
.name = "DC off",
@@ -498,12 +498,12 @@ static const struct i915_power_well_desc 
bxt_power_wells[] = {
.name = "power well 2",
.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+   .has_vga = true,
+   .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+   .has_fuses = true,
.id = SKL_DISP_PW_2,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_2,
-   .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
-   .hsw.has_vga = true,
-   .hsw.has_fuses = true,
},
}, {
.name = "dpio-common-a",
@@ -594,10 +594,10 @@ static const struct i915_power_well_desc 
glk_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+   .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
-   .hsw.has_fuses = true,
},
}, {
.name = "DC off",
@@ -608,12 +608,12 @@ static const struct i915_power_well_desc 
glk_power_wells[] = {
.name = "power well 2",
.domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+   .has_vga = true,
+   .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+   .has_

[Intel-gfx] [PATCH v3 13/18] drm/i915: Sanitize the ADL-S power well definition

[Imre Deak]

Instead of the skip_mask special casing of the ADL-S power well
descriptors, add a power well descriptor list for ADL-S as well reusing
the TGL descriptors, w/o the TC-cold power well. ADL-S doesn't have
TypeC PHYs, so a better way would be having ADL-S specific AUX
descriptors, but I left changing this for a follow-up.

This changes the ordering of the AUX and TC-cold vs. PW_4/5 power wells
on TGL and ADL-S, but this shouldn't make a difference (PW_4/5 don't
depend on the AUX/TC-cold power wells).

Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander 
---
 .../i915/display/intel_display_power_map.c| 69 +++
 1 file changed, 39 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c 
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 4443cf0015d1e..86d937f8bfe13 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -902,12 +902,36 @@ static const struct i915_power_well_desc 
tgl_power_wells_main[] = {
),
.ops = &icl_ddi_power_well_ops,
}, {
+   .instances = &I915_PW_INSTANCES(
+   I915_PW("PW_4", &tgl_pwdoms_pw_4,
+   .hsw.idx = ICL_PW_CTL_IDX_PW_4),
+   ),
+   .ops = &hsw_power_well_ops,
+   .has_fuses = true,
+   .irq_pipe_mask = BIT(PIPE_C),
+   }, {
+   .instances = &I915_PW_INSTANCES(
+   I915_PW("PW_5", &tgl_pwdoms_pw_5,
+   .hsw.idx = TGL_PW_CTL_IDX_PW_5),
+   ),
+   .ops = &hsw_power_well_ops,
+   .has_fuses = true,
+   .irq_pipe_mask = BIT(PIPE_D),
+   },
+};
+
+static const struct i915_power_well_desc tgl_power_wells_tc_cold_off[] = {
+   {
.instances = &I915_PW_INSTANCES(
I915_PW("TC_cold_off", &tgl_pwdoms_tc_cold_off,
.id = TGL_DISP_PW_TC_COLD_OFF),
),
.ops = &tgl_tc_cold_off_ops,
-   }, {
+   },
+};
+
+static const struct i915_power_well_desc tgl_power_wells_aux[] = {
+   {
.instances = &I915_PW_INSTANCES(
I915_PW("AUX_A", &tgl_pwdoms_aux_a, .hsw.idx = 
ICL_PW_CTL_IDX_AUX_A),
I915_PW("AUX_B", &tgl_pwdoms_aux_b, .hsw.idx = 
ICL_PW_CTL_IDX_AUX_B),
@@ -931,22 +955,6 @@ static const struct i915_power_well_desc 
tgl_power_wells_main[] = {
),
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
-   }, {
-   .instances = &I915_PW_INSTANCES(
-   I915_PW("PW_4", &tgl_pwdoms_pw_4,
-   .hsw.idx = ICL_PW_CTL_IDX_PW_4),
-   ),
-   .ops = &hsw_power_well_ops,
-   .has_fuses = true,
-   .irq_pipe_mask = BIT(PIPE_C),
-   }, {
-   .instances = &I915_PW_INSTANCES(
-   I915_PW("PW_5", &tgl_pwdoms_pw_5,
-   .hsw.idx = TGL_PW_CTL_IDX_PW_5),
-   ),
-   .ops = &hsw_power_well_ops,
-   .has_fuses = true,
-   .irq_pipe_mask = BIT(PIPE_D),
},
 };
 
@@ -954,6 +962,15 @@ static const struct i915_power_well_desc_list 
tgl_power_wells[] = {
I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
I915_PW_DESCRIPTORS(tgl_power_wells_main),
+   I915_PW_DESCRIPTORS(tgl_power_wells_tc_cold_off),
+   I915_PW_DESCRIPTORS(tgl_power_wells_aux),
+};
+
+static const struct i915_power_well_desc_list adls_power_wells[] = {
+   I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+   I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+   I915_PW_DESCRIPTORS(tgl_power_wells_main),
+   I915_PW_DESCRIPTORS(tgl_power_wells_aux),
 };
 
 #define RKL_PW_4_POWER_DOMAINS \
@@ -1400,7 +1417,7 @@ static void init_power_well_domains(const struct 
i915_power_well_instance *inst,
 static int
 __set_power_wells(struct i915_power_domains *power_domains,
  const struct i915_power_well_desc_list *power_well_descs,
- int power_well_descs_sz, u64 skip_mask)
+ int power_well_descs_sz)
 {
struct drm_i915_private *i915 = container_of(power_domains,
 struct drm_i915_private,
@@ -1413,8 +1430,7 @@ __set_power_wells(struct i915_power_domains 
*power_domains,
int plt_idx = 0;
 
for_each_power_well_instance(power_well_descs, power_well_descs_sz, 
desc_list, desc, inst)
-   if (!(BIT_ULL(inst->id) & skip_mask))
-   power_well_count++;
+   power_well_count++;
 
power_domains->power_well_count = power_well_count;
power_domains->power_wells =
@@ -1428,9 

[Intel-gfx] [PATCH v3 07/18] drm/i915: Sanitize the power well names

[Imre Deak]

Use the shortest descriptive name for all power wells for simplicity and
to use the same name for the same type of power wells on multiple
platforms.

Signed-off-by: Imre Deak 
Reviewed-by: Jouni Högander 
---
 .../i915/display/intel_display_power_map.c| 254 +-
 1 file changed, 127 insertions(+), 127 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c 
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index dc5be70a17813..42b813cf47dbf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -363,7 +363,7 @@ static const struct i915_power_well_desc skl_power_wells[] 
= {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
-   .name = "power well 1",
+   .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -374,7 +374,7 @@ static const struct i915_power_well_desc skl_power_wells[] 
= {
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
},
}, {
-   .name = "MISC IO power well",
+   .name = "MISC_IO",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -384,12 +384,12 @@ static const struct i915_power_well_desc 
skl_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
},
}, {
-   .name = "DC off",
+   .name = "DC_off",
.domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
-   .name = "power well 2",
+   .name = "PW_2",
.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_vga = true,
@@ -400,7 +400,7 @@ static const struct i915_power_well_desc skl_power_wells[] 
= {
.hsw.idx = SKL_PW_CTL_IDX_PW_2,
},
}, {
-   .name = "DDI A/E IO power well",
+   .name = "DDI_IO_A_E",
.domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -408,7 +408,7 @@ static const struct i915_power_well_desc skl_power_wells[] 
= {
.hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
},
}, {
-   .name = "DDI B IO power well",
+   .name = "DDI_IO_B",
.domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -416,7 +416,7 @@ static const struct i915_power_well_desc skl_power_wells[] 
= {
.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
},
}, {
-   .name = "DDI C IO power well",
+   .name = "DDI_IO_C",
.domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -424,7 +424,7 @@ static const struct i915_power_well_desc skl_power_wells[] 
= {
.hsw.idx = SKL_PW_CTL_IDX_DDI_C,
},
}, {
-   .name = "DDI D IO power well",
+   .name = "DDI_IO_D",
.domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -479,7 +479,7 @@ static const struct i915_power_well_desc bxt_power_wells[] 
= {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
-   .name = "power well 1",
+   .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -490,12 +490,12 @@ static const struct i915_power_well_desc 
bxt_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
},
}, {
-   .name = "DC off",
+   .name = "DC_off",
.domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
-   .name = "power well 2",
+   .name = "PW_2",
.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_vga = true,
@@ -589,7 +589,7 @@ static const struct i915_power_well_desc glk_power_wells[] 
= {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
-   .name = "power well 1",
+   .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -600,12 +600,12 @@ static cons

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2)
URL   : https://patchwork.freedesktop.org/series/101712/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22718


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22718 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22718, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22718/index.html

Participating hosts (42 -> 41)
--

  Additional (5): fi-tgl-u2 fi-skl-guc fi-cfl-8700k bat-adlp-4 fi-ivb-3770 
  Missing(6): fi-kbl-soraka shard-tglu fi-bsw-cyan fi-bdw-samus bat-jsl-2 
bat-jsl-1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22718:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gem_contexts:
- bat-dg1-6:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg1-6/igt@i915_selftest@live@gem_contexts.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22718/bat-dg1-6/igt@i915_selftest@live@gem_contexts.html

  * igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22718/bat-adlp-4/igt@run...@aborted.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@hugepages:
- {bat-rpls-2}:   [PASS][4] -> [DMESG-WARN][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-rpls-2/igt@i915_selftest@l...@hugepages.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22718/bat-rpls-2/igt@i915_selftest@l...@hugepages.html

  
Known issues


  Here are the changes found in Patchwork_22718 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#109315]) +17 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22718/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html

  * igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka:   NOTRUN -> [SKIP][7] ([fdo#109271]) +17 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22718/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-cfl-8700k:   NOTRUN -> [SKIP][8] ([fdo#109271]) +29 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22718/fi-cfl-8700k/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html

  * igt@gem_huc_copy@huc-copy:
- fi-tgl-u2:  NOTRUN -> [SKIP][9] ([i915#2190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22718/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html
- fi-cfl-8700k:   NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#2190])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22718/fi-cfl-8700k/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-skl-guc: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22718/fi-skl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-cfl-8700k:   NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22718/fi-cfl-8700k/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
- fi-ivb-3770:NOTRUN -> [SKIP][13] ([fdo#109271]) +36 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22718/fi-ivb-3770/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2:  NOTRUN -> [SKIP][14] ([i915#4613]) +3 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22718/fi-tgl-u2/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_ringfill@basic-all:
- bat-dg1-6:  [PASS][15] -> [TIMEOUT][16] ([i915#5199])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg1-6/igt@gem_ringf...@basic-all.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22718/bat-dg1-6/igt@gem_ringf...@basic-all.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-7567u:   [PASS][17] -> [DMESG-FAIL][18] ([i915#5334])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22718/fi-kbl-7567u/i

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dg2: Add Wa_22014226127 (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/dg2: Add Wa_22014226127 (rev4)
URL   : https://patchwork.freedesktop.org/series/101792/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2)
URL   : https://patchwork.freedesktop.org/series/101712/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/adlp: Fix register corruption after DDI clock enabling (rev2)
URL   : https://patchwork.freedesktop.org/series/101712/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: avoid concurrent writes to aux_inv (rev10)

[Yang, Fei]

> On 29/03/2022 03:30, Patchwork wrote:
>> *Patch Details*
>> *Series:*drm/i915: avoid concurrent writes to aux_inv (rev10)
>> *URL:*   https://patchwork.freedesktop.org/series/100772/ 
>> 
>> *State:* success
>> *Details:*
>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22704/index.html
>> 
>> 
>> 
>>   CI Bug Log - changes from CI_DRM_11415_full -> Patchwork_22704_full
>> 
>> 
>> Summary
>> 
>> *SUCCESS*
>> 
>> No regressions found.
>
> And pushed.
Thank you so much.

>
> Does this have any chance of fixing hangs in multiple simultaneous media 
> workloads?
I hope so. The hang fixed by this patch is pretty easy to reproduce on TGL with 
two parallel video decoding processes.

-Fei

> Regards,
>
> Tvrtko

Re: [Intel-gfx] [PATCH 22/23] drm/i915: drop bo->moving dependency

[Daniel Vetter]

On Mon, Mar 21, 2022 at 02:58:55PM +0100, Christian König wrote:
> That should now be handled by the common dma_resv framework.
> 
> Signed-off-by: Christian König 
> Cc: intel-gfx@lists.freedesktop.org

Reviewed-by: Daniel Vetter 

> ---
>  drivers/gpu/drm/i915/gem/i915_gem_object.c   | 29 ++--
>  drivers/gpu/drm/i915/gem/i915_gem_object.h   |  5 ++--
>  drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 15 +-
>  drivers/gpu/drm/i915/i915_vma.c  |  9 +-
>  4 files changed, 19 insertions(+), 39 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> index d87b508b59b1..fd240435ffef 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> @@ -742,18 +742,19 @@ static const struct drm_gem_object_funcs 
> i915_gem_object_funcs = {
>  /**
>   * i915_gem_object_get_moving_fence - Get the object's moving fence if any
>   * @obj: The object whose moving fence to get.
> + * @fence: The resulting fence
>   *
>   * A non-signaled moving fence means that there is an async operation
>   * pending on the object that needs to be waited on before setting up
>   * any GPU- or CPU PTEs to the object's pages.
>   *
> - * Return: A refcounted pointer to the object's moving fence if any,
> - * NULL otherwise.
> + * Return: Negative error code or 0 for success.
>   */
> -struct dma_fence *
> -i915_gem_object_get_moving_fence(struct drm_i915_gem_object *obj)
> +int i915_gem_object_get_moving_fence(struct drm_i915_gem_object *obj,
> +  struct dma_fence **fence)
>  {
> - return dma_fence_get(i915_gem_to_ttm(obj)->moving);
> + return dma_resv_get_singleton(obj->base.resv, DMA_RESV_USAGE_KERNEL,
> +   fence);
>  }
>  
>  /**
> @@ -771,23 +772,9 @@ i915_gem_object_get_moving_fence(struct 
> drm_i915_gem_object *obj)
>  int i915_gem_object_wait_moving_fence(struct drm_i915_gem_object *obj,
> bool intr)
>  {
> - struct dma_fence *fence = i915_gem_to_ttm(obj)->moving;
> - int ret;
> -
>   assert_object_held(obj);
> - if (!fence)
> - return 0;
> -
> - ret = dma_fence_wait(fence, intr);
> - if (ret)
> - return ret;
> -
> - if (fence->error)
> - return fence->error;
> -
> - i915_gem_to_ttm(obj)->moving = NULL;
> - dma_fence_put(fence);
> - return 0;
> + return dma_resv_wait_timeout(obj->base. resv, DMA_RESV_USAGE_KERNEL,
> +  intr, MAX_SCHEDULE_TIMEOUT);
>  }
>  
>  #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h 
> b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> index f66d46882ea7..be57af8bfb31 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> @@ -521,9 +521,8 @@ i915_gem_object_finish_access(struct drm_i915_gem_object 
> *obj)
>   i915_gem_object_unpin_pages(obj);
>  }
>  
> -struct dma_fence *
> -i915_gem_object_get_moving_fence(struct drm_i915_gem_object *obj);
> -
> +int i915_gem_object_get_moving_fence(struct drm_i915_gem_object *obj,
> +  struct dma_fence **fence);
>  int i915_gem_object_wait_moving_fence(struct drm_i915_gem_object *obj,
> bool intr);
>  
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> index e4a232e22f9d..4d5d0cd64f23 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> @@ -452,19 +452,6 @@ __i915_ttm_move(struct ttm_buffer_object *bo,
>   return fence;
>  }
>  
> -static int
> -prev_deps(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx,
> -   struct i915_deps *deps)
> -{
> - int ret;
> -
> - ret = i915_deps_add_dependency(deps, bo->moving, ctx);
> - if (!ret)
> - ret = i915_deps_add_resv(deps, bo->base.resv, ctx);
> -
> - return ret;
> -}
> -
>  /**
>   * i915_ttm_move - The TTM move callback used by i915.
>   * @bo: The buffer object.
> @@ -519,7 +506,7 @@ int i915_ttm_move(struct ttm_buffer_object *bo, bool 
> evict,
>   struct i915_deps deps;
>  
>   i915_deps_init(&deps, GFP_KERNEL | __GFP_NORETRY | 
> __GFP_NOWARN);
> - ret = prev_deps(bo, ctx, &deps);
> + ret = i915_deps_add_resv(&deps, bo->base.resv, ctx);
>   if (ret) {
>   i915_refct_sgt_put(dst_rsgt);
>   return ret;
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index 52fd6705a518..8737159f4706 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -1247,10 +1247,17 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct 
> i915_gem_ww_ctx *ww,
>   if (err)
> 

[Intel-gfx] [PATCH 07/11] drm/i915: Allow an arbitrary number of downclock modes

[Ville Syrjala]

From: Ville Syrjälä 

Remove the "two fixed modes only" limit and grab as many
downclock modes from the EDID as we can find.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_panel.c | 44 +++---
 1 file changed, 13 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_panel.c 
b/drivers/gpu/drm/i915/display/intel_panel.c
index 5d08b2bf27ec..d359c8050fdc 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -159,42 +159,24 @@ static bool is_downclock_mode(const struct 
drm_display_mode *downclock_mode,
downclock_mode->clock < fixed_mode->clock;
 }
 
-static void intel_panel_add_edid_downclock_mode(struct intel_connector 
*connector)
+static void intel_panel_add_edid_downclock_modes(struct intel_connector 
*connector)
 {
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
const struct drm_display_mode *fixed_mode =
intel_panel_preferred_fixed_mode(connector);
-   struct drm_display_mode *scan, *best_mode = NULL;
-   int best_clock = fixed_mode->clock;
+   struct drm_display_mode *mode, *next;
 
-   list_for_each_entry(scan, &connector->base.probed_modes, head) {
-   /*
-* If one mode has the same resolution with the fixed_panel
-* mode while they have the different refresh rate, it means
-* that the reduced downclock is found. In such
-* case we can set the different FPx0/1 to dynamically select
-* between low and high frequency.
-*/
-   if (is_downclock_mode(scan, fixed_mode) &&
-   scan->clock < best_clock) {
-   /*
-* The downclock is already found. But we
-* expect to find the lower downclock.
-*/
-   best_clock = scan->clock;
-   best_mode = scan;
-   }
+   list_for_each_entry_safe(mode, next, &connector->base.probed_modes, 
head) {
+   if (!is_downclock_mode(mode, fixed_mode))
+   continue;
+
+   drm_dbg_kms(&dev_priv->drm,
+   "[CONNECTOR:%d:%s] using EDID downclock mode: " 
DRM_MODE_FMT "\n",
+   connector->base.base.id, connector->base.name,
+   DRM_MODE_ARG(mode));
+
+   list_move_tail(&mode->head, &connector->panel.fixed_modes);
}
-
-   if (!best_mode)
-   return;
-
-   drm_dbg_kms(&dev_priv->drm,
-   "[CONNECTOR:%d:%s] using EDID downclock mode: " 
DRM_MODE_FMT "\n",
-   connector->base.base.id, connector->base.name,
-   DRM_MODE_ARG(best_mode));
-
-   list_move_tail(&best_mode->head, &connector->panel.fixed_modes);
 }
 
 static void intel_panel_add_edid_fixed_mode(struct intel_connector *connector)
@@ -243,7 +225,7 @@ void intel_panel_add_edid_fixed_modes(struct 
intel_connector *connector, bool ha
 {
intel_panel_add_edid_fixed_mode(connector);
if (intel_panel_preferred_fixed_mode(connector) && has_drrs)
-   intel_panel_add_edid_downclock_mode(connector);
+   intel_panel_add_edid_downclock_modes(connector);
intel_panel_destroy_probed_modes(connector);
 }
 
-- 
2.34.1

[Intel-gfx] [PATCH 10/11] drm/i915: Allow static DRRS on all eDP ports

[Ville Syrjala]

From: Ville Syrjälä 

Only seamless DRRS has specific hardware requirements so
we can allow static DRRS on any eDP port.

And we can replace these port checks and whatnot with
a simple check to make sure the transcoder(s) we're
about to use are capable of seamless DRRS.

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 54 +
 1 file changed, 20 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 92c0c24517b3..c2e1bcfefae6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1764,10 +1764,22 @@ intel_dp_compute_hdr_metadata_infoframe_sdp(struct 
intel_dp *intel_dp,
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
+static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
+   enum transcoder cpu_transcoder)
+{
+   /* M1/N1 is double buffered */
+   if (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
+   return true;
+
+   return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
+}
+
 static bool can_enable_drrs(struct intel_connector *connector,
const struct intel_crtc_state *pipe_config,
const struct drm_display_mode *downclock_mode)
 {
+   struct drm_i915_private *i915 = to_i915(connector->base.dev);
+
if (pipe_config->vrr.enable)
return false;
 
@@ -1780,6 +1792,13 @@ static bool can_enable_drrs(struct intel_connector 
*connector,
if (pipe_config->has_psr)
return false;
 
+   /* FIXME missing FDI M2/N2 etc. */
+   if (pipe_config->has_pch_encoder)
+   return false;
+
+   if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
+   return false;
+
return downclock_mode &&
intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
 }
@@ -5024,39 +5043,6 @@ intel_edp_add_properties(struct intel_dp *intel_dp)
   fixed_mode->vdisplay);
 }
 
-static bool
-intel_edp_has_drrs(struct intel_dp *intel_dp)
-{
-   struct intel_connector *connector = intel_dp->attached_connector;
-   struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
-   struct drm_i915_private *i915 = to_i915(connector->base.dev);
-
-   if (DISPLAY_VER(i915) < 5) {
-   drm_dbg_kms(&i915->drm,
-   "[CONNECTOR:%d:%s] DRRS not supported on 
platform\n",
-   connector->base.base.id, connector->base.name);
-   return false;
-   }
-
-   if ((DISPLAY_VER(i915) < 8 && !HAS_GMCH(i915)) &&
-   encoder->port != PORT_A) {
-   drm_dbg_kms(&i915->drm,
-   "[CONNECTOR:%d:%s] DRRS not supported on 
[ENCODER:%d:%s]\n",
-   connector->base.base.id, connector->base.name,
-   encoder->base.base.id, encoder->base.name);
-   return false;
-   }
-
-   if (i915->vbt.drrs_type == DRRS_TYPE_NONE) {
-   drm_dbg_kms(&i915->drm,
-   "[CONNECTOR:%d:%s] DRRS not supported according to 
VBT\n",
-   connector->base.base.id, connector->base.name);
-   return false;
-   }
-
-   return true;
-}
-
 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 struct intel_connector *intel_connector)
 {
@@ -5121,7 +5107,7 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
intel_connector->edid = edid;
 
intel_panel_add_edid_fixed_modes(intel_connector,
-intel_edp_has_drrs(intel_dp));
+dev_priv->vbt.drrs_type != 
DRRS_TYPE_NONE);
 
/* MSO requires information from the EDID */
intel_edp_mso_init(intel_dp);
-- 
2.34.1

[Intel-gfx] [PATCH 08/11] drm/i915: Allow higher refresh rate alternate fixed modes

[Ville Syrjala]

From: Ville Syrjälä 

We shouldn't restrict ourselves to just downclock modes with
lower refresh rate than the preferred mode. Laptops these
days can offer higher refresh rate modes as well.

Remove the arbitrary limit and allow all modes that, apart
from the clock, match the preferred mode.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/125
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_panel.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_panel.c 
b/drivers/gpu/drm/i915/display/intel_panel.c
index d359c8050fdc..f3e52e7413fe 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -149,29 +149,29 @@ int intel_panel_compute_config(struct intel_connector 
*connector,
return 0;
 }
 
-static bool is_downclock_mode(const struct drm_display_mode *downclock_mode,
- const struct drm_display_mode *fixed_mode)
+static bool is_alt_fixed_mode(const struct drm_display_mode *mode,
+ const struct drm_display_mode *preferred_mode)
 {
-   return drm_mode_match(downclock_mode, fixed_mode,
+   return drm_mode_match(mode, preferred_mode,
  DRM_MODE_MATCH_TIMINGS |
  DRM_MODE_MATCH_FLAGS |
  DRM_MODE_MATCH_3D_FLAGS) &&
-   downclock_mode->clock < fixed_mode->clock;
+   mode->clock != preferred_mode->clock;
 }
 
 static void intel_panel_add_edid_downclock_modes(struct intel_connector 
*connector)
 {
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
-   const struct drm_display_mode *fixed_mode =
+   const struct drm_display_mode *preferred_mode =
intel_panel_preferred_fixed_mode(connector);
struct drm_display_mode *mode, *next;
 
list_for_each_entry_safe(mode, next, &connector->base.probed_modes, 
head) {
-   if (!is_downclock_mode(mode, fixed_mode))
+   if (!is_alt_fixed_mode(mode, preferred_mode))
continue;
 
drm_dbg_kms(&dev_priv->drm,
-   "[CONNECTOR:%d:%s] using EDID downclock mode: " 
DRM_MODE_FMT "\n",
+   "[CONNECTOR:%d:%s] using alternate EDID fixed mode: 
" DRM_MODE_FMT "\n",
connector->base.base.id, connector->base.name,
DRM_MODE_ARG(mode));
 
@@ -179,7 +179,7 @@ static void intel_panel_add_edid_downclock_modes(struct 
intel_connector *connect
}
 }
 
-static void intel_panel_add_edid_fixed_mode(struct intel_connector *connector)
+static void intel_panel_add_edid_preferred_mode(struct intel_connector 
*connector)
 {
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct drm_display_mode *scan, *fixed_mode = NULL;
@@ -223,7 +223,7 @@ static void intel_panel_destroy_probed_modes(struct 
intel_connector *connector)
 
 void intel_panel_add_edid_fixed_modes(struct intel_connector *connector, bool 
has_drrs)
 {
-   intel_panel_add_edid_fixed_mode(connector);
+   intel_panel_add_edid_preferred_mode(connector);
if (intel_panel_preferred_fixed_mode(connector) && has_drrs)
intel_panel_add_edid_downclock_modes(connector);
intel_panel_destroy_probed_modes(connector);
-- 
2.34.1