[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/fbc: Do not apply WA 22014263786 to DG2 (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/display/fbc: Do not apply WA 22014263786 to DG2 (rev2)
URL   : https://patchwork.freedesktop.org/series/104678/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11726_full -> Patchwork_104678v2_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_104678v2_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_104678v2_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_104678v2_full:

### IGT changes ###

 Warnings 

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
- shard-kbl:  [DMESG-FAIL][1] ([i915#180]) -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-kbl6/igt@kms_hdr@bpc-switch-susp...@pipe-a-dp-1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/shard-kbl6/igt@kms_hdr@bpc-switch-susp...@pipe-a-dp-1.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_setmode@basic@pipe-a-edp-1:
- {shard-rkl}:NOTRUN -> [FAIL][3] +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/shard-rkl-6/igt@kms_setmode@ba...@pipe-a-edp-1.html

  
Known issues


  Here are the changes found in Patchwork_104678v2_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-skl:  ([PASS][4], [PASS][5], [PASS][6], [PASS][7], 
[PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], 
[PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], 
[PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> 
([FAIL][26], [FAIL][27], [PASS][28], [FAIL][29], [PASS][30], [PASS][31], 
[PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], 
[PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], 
[PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49]) 
([i915#5032])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl9/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl9/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl9/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl7/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl7/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl6/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl6/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl6/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl4/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl4/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl3/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl2/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl2/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl2/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl1/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl1/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl1/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl10/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl10/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-skl10/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/shard-skl3/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/shard-skl3/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/shard-skl2/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/shard-skl2/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/shard-skl1/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/shard-skl1/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/shard-skl1/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/fbc: Do not apply WA 22014263786 to DG2 (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/display/fbc: Do not apply WA 22014263786 to DG2 (rev2)
URL   : https://patchwork.freedesktop.org/series/104678/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11726 -> Patchwork_104678v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/index.html

Participating hosts (43 -> 44)
--

  Additional (2): bat-adln-1 fi-kbl-x1275 
  Missing(1): fi-rkl-11600 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_104678v2:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@hangcheck:
- {fi-ehl-2}: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_frontbuffer_tracking@basic:
- {bat-adln-1}:   NOTRUN -> [SKIP][3] +19 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/bat-adln-1/igt@kms_frontbuffer_track...@basic.html

  
Known issues


  Here are the changes found in Patchwork_104678v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-x1275:   NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-x1275/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-kbl-x1275:   NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-x1275/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-5:  [PASS][6] -> [DMESG-FAIL][7] ([i915#4494] / 
[i915#4957])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
- bat-dg1-6:  [PASS][8] -> [DMESG-FAIL][9] ([i915#4494] / 
[i915#4957])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [PASS][10] -> [DMESG-FAIL][11] ([i915#4528])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@reset:
- bat-adlp-4: [PASS][12] -> [DMESG-FAIL][13] ([i915#4983])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/bat-adlp-4/igt@i915_selftest@l...@reset.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/bat-adlp-4/igt@i915_selftest@l...@reset.html

  * igt@kms_addfb_basic@unused-pitches:
- fi-kbl-soraka:  [PASS][14] -> [INCOMPLETE][15] ([i915#5974])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-kbl-soraka/igt@kms_addfb_ba...@unused-pitches.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-soraka/igt@kms_addfb_ba...@unused-pitches.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-kbl-x1275:   NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-x1275/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-x1275:   NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-x1275/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_vgem@basic-userptr:
- fi-kbl-x1275:   NOTRUN -> [SKIP][18] ([fdo#109271]) +12 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-x1275/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][19] ([i915#4312])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/bat-adlp-4/igt@run...@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/fbc: Do not apply WA 22014263786 to DG2 (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/display/fbc: Do not apply WA 22014263786 to DG2 (rev2)
URL   : https://patchwork.freedesktop.org/series/104678/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11726 -> Patchwork_104678v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/index.html

Participating hosts (43 -> 44)
--

  Additional (2): bat-adln-1 fi-kbl-x1275 
  Missing(1): fi-rkl-11600 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_104678v2:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@hangcheck:
- {fi-ehl-2}: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_frontbuffer_tracking@basic:
- {bat-adln-1}:   NOTRUN -> [SKIP][3] +19 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/bat-adln-1/igt@kms_frontbuffer_track...@basic.html

  
Known issues


  Here are the changes found in Patchwork_104678v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-x1275:   NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-x1275/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-kbl-x1275:   NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-x1275/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-5:  [PASS][6] -> [DMESG-FAIL][7] ([i915#4494] / 
[i915#4957])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
- bat-dg1-6:  [PASS][8] -> [DMESG-FAIL][9] ([i915#4494] / 
[i915#4957])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [PASS][10] -> [DMESG-FAIL][11] ([i915#4528])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@reset:
- bat-adlp-4: [PASS][12] -> [DMESG-FAIL][13] ([i915#4983])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/bat-adlp-4/igt@i915_selftest@l...@reset.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/bat-adlp-4/igt@i915_selftest@l...@reset.html

  * igt@kms_addfb_basic@unused-pitches:
- fi-kbl-soraka:  [PASS][14] -> [INCOMPLETE][15] ([i915#5974])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-kbl-soraka/igt@kms_addfb_ba...@unused-pitches.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-soraka/igt@kms_addfb_ba...@unused-pitches.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-kbl-x1275:   NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-x1275/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-x1275:   NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-x1275/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_vgem@basic-userptr:
- fi-kbl-x1275:   NOTRUN -> [SKIP][18] ([fdo#109271]) +12 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-x1275/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][19] ([i915#4312])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/bat-adlp-4/igt@run...@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Parse more eDP link rate stuff from VBT (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Parse more eDP link rate stuff from VBT (rev4)
URL   : https://patchwork.freedesktop.org/series/104615/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11727 -> Patchwork_104615v4


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_104615v4 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_104615v4, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104615v4/index.html

Participating hosts (48 -> 45)
--

  Additional (2): bat-atsm-1 bat-jsl-1 
  Missing(5): fi-hsw-4200u bat-adlm-1 bat-dg2-9 fi-cfl-guc fi-ctg-p8600 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_104615v4:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gem:
- fi-bdw-gvtdvm:  [PASS][1] -> [DMESG-FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11727/fi-bdw-gvtdvm/igt@i915_selftest@l...@gem.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104615v4/fi-bdw-gvtdvm/igt@i915_selftest@l...@gem.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_suspend@basic-s0@smem:
- {bat-adln-1}:   [PASS][3] -> [DMESG-WARN][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11727/bat-adln-1/igt@gem_exec_suspend@basic...@smem.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104615v4/bat-adln-1/igt@gem_exec_suspend@basic...@smem.html

  
Known issues


  Here are the changes found in Patchwork_104615v4 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-5:  [PASS][5] -> [INCOMPLETE][6] ([i915#4418])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11727/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104615v4/bat-dg1-5/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][7] -> [INCOMPLETE][8] ([i915#4785])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11727/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104615v4/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- fi-snb-2600:[PASS][9] -> [INCOMPLETE][10] ([i915#3921])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11727/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104615v4/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u:   [PASS][11] -> [DMESG-WARN][12] ([i915#5904]) +12 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11727/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104615v4/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [PASS][13] -> [DMESG-FAIL][14] ([i915#4528])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11727/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104615v4/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][15] ([fdo#109271] / [i915#4312] / 
[i915#5594])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104615v4/fi-hsw-4770/igt@run...@aborted.html
- fi-bdw-gvtdvm:  NOTRUN -> [FAIL][16] ([i915#4312])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104615v4/fi-bdw-gvtdvm/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-adln-1}:   [DMESG-WARN][17] -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11727/bat-adln-1/igt@gem_exec_suspend@basic...@smem.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104615v4/bat-adln-1/igt@gem_exec_suspend@basic...@smem.html

  
 Warnings 

  * igt@i915_pm_rpm@basic-rte:
- fi-cfl-8109u:   [DMESG-WARN][19] ([i915#1888] / [i915#62]) -> 
[DMESG-WARN][20] ([i915#62])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11727/fi-cfl-8109u/igt@i915_pm_...@basic-rte.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104615v4/fi-cfl-8109u/igt@i915_pm_...@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [DMESG-WARN][21] ([i915#62]) -> [DMESG-FAIL][22] 
([i915#62])
   [21]

Re: [Intel-gfx] [RFC v3 1/3] drm/doc/rfc: VM_BIND feature design document

[Niranjana Vishwanathapura]

On Fri, Jun 03, 2022 at 10:20:25AM +0300, Lionel Landwerlin wrote:

  On 02/06/2022 23:35, Jason Ekstrand wrote:

On Thu, Jun 2, 2022 at 3:11 PM Niranjana Vishwanathapura
 wrote:

  On Wed, Jun 01, 2022 at 01:28:36PM -0700, Matthew Brost wrote:
  >On Wed, Jun 01, 2022 at 05:25:49PM +0300, Lionel Landwerlin wrote:
  >> On 17/05/2022 21:32, Niranjana Vishwanathapura wrote:
  >> > +VM_BIND/UNBIND ioctl will immediately start binding/unbinding
  the mapping in an
  >> > +async worker. The binding and unbinding will work like a special
  GPU engine.
  >> > +The binding and unbinding operations are serialized and will
  wait on specified
  >> > +input fences before the operation and will signal the output
  fences upon the
  >> > +completion of the operation. Due to serialization, completion of
  an operation
  >> > +will also indicate that all previous operations are also
  complete.
  >>
  >> I guess we should avoid saying "will immediately start
  binding/unbinding" if
  >> there are fences involved.
  >>
  >> And the fact that it's happening in an async worker seem to imply
  it's not
  >> immediate.
  >>

  Ok, will fix.
  This was added because in earlier design binding was deferred until
  next execbuff.
  But now it is non-deferred (immediate in that sense). But yah, this is
  confusing
  and will fix it.

  >>
  >> I have a question on the behavior of the bind operation when no
  input fence
  >> is provided. Let say I do :
  >>
  >> VM_BIND (out_fence=fence1)
  >>
  >> VM_BIND (out_fence=fence2)
  >>
  >> VM_BIND (out_fence=fence3)
  >>
  >>
  >> In what order are the fences going to be signaled?
  >>
  >> In the order of VM_BIND ioctls? Or out of order?
  >>
  >> Because you wrote "serialized I assume it's : in order
  >>

  Yes, in the order of VM_BIND/UNBIND ioctls. Note that bind and unbind
  will use
  the same queue and hence are ordered.

  >>
  >> One thing I didn't realize is that because we only get one
  "VM_BIND" engine,
  >> there is a disconnect from the Vulkan specification.
  >>
  >> In Vulkan VM_BIND operations are serialized but per engine.
  >>
  >> So you could have something like this :
  >>
  >> VM_BIND (engine=rcs0, in_fence=fence1, out_fence=fence2)
  >>
  >> VM_BIND (engine=ccs0, in_fence=fence3, out_fence=fence4)
  >>
  >>
  >> fence1 is not signaled
  >>
  >> fence3 is signaled
  >>
  >> So the second VM_BIND will proceed before the first VM_BIND.
  >>
  >>
  >> I guess we can deal with that scenario in userspace by doing the
  wait
  >> ourselves in one thread per engines.
  >>
  >> But then it makes the VM_BIND input fences useless.
  >>
  >>
  >> Daniel : what do you think? Should be rework this or just deal with
  wait
  >> fences in userspace?
  >>
  >
  >My opinion is rework this but make the ordering via an engine param
  optional.
  >
  >e.g. A VM can be configured so all binds are ordered within the VM
  >
  >e.g. A VM can be configured so all binds accept an engine argument
  (in
  >the case of the i915 likely this is a gem context handle) and binds
  >ordered with respect to that engine.
  >
  >This gives UMDs options as the later likely consumes more KMD
  resources
  >so if a different UMD can live with binds being ordered within the VM
  >they can use a mode consuming less resources.
  >

  I think we need to be careful here if we are looking for some out of
  (submission) order completion of vm_bind/unbind.
  In-order completion means, in a batch of binds and unbinds to be
  completed in-order, user only needs to specify in-fence for the
  first bind/unbind call and the our-fence for the last bind/unbind
  call. Also, the VA released by an unbind call can be re-used by
  any subsequent bind call in that in-order batch.

  These things will break if binding/unbinding were to be allowed to
  go out of order (of submission) and user need to be extra careful
  not to run into pre-mature triggereing of out-fence and bind failing
  as VA is still in use etc.

  Also, VM_BIND binds the provided mapping on the specified address
  space
  (VM). So, the uapi is not engine/context specific.

  We can however add a 'queue' to the uapi which can be one from the
  pre-defined queues,
  I915_VM_BIND_QUEUE_0
  I915_VM_BIND_QUEUE_1
  ...
  I915_VM_BIND_QUEUE_(N-1)

  KMD will spawn an async work queue for each queue which will only
  bind the mappings on that queue in the order of submission.
  User can assign the queue to per engine or anything like that.

  But again here, user need t

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: i915_drv.h & i915_gem.h header refactoring

[Patchwork]

== Series Details ==

Series: drm/i915: i915_drv.h & i915_gem.h header refactoring
URL   : https://patchwork.freedesktop.org/series/104725/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11726_full -> Patchwork_104725v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_104725v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_104725v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_104725v1_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_ctx_persistence@many-contexts:
- shard-iclb: [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-iclb5/igt@gem_ctx_persiste...@many-contexts.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/shard-iclb6/igt@gem_ctx_persiste...@many-contexts.html

  
Known issues


  Here are the changes found in Patchwork_104725v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_busy@close-race:
- shard-glk:  [PASS][3] -> [INCOMPLETE][4] ([i915#5753])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-glk3/igt@gem_b...@close-race.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/shard-glk6/igt@gem_b...@close-race.html

  * igt@gem_ctx_persistence@idempotent:
- shard-snb:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/shard-snb4/igt@gem_ctx_persiste...@idempotent.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][6] -> [SKIP][7] ([i915#4525]) +2 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-iclb1/igt@gem_exec_balan...@parallel-keep-in-fence.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/shard-iclb8/igt@gem_exec_balan...@parallel-keep-in-fence.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][8] ([i915#6141])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/shard-apl7/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-kbl:  NOTRUN -> [FAIL][9] ([i915#2842]) +3 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/shard-kbl6/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar 
issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-iclb8/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/shard-iclb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][12] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl:  [PASS][13] -> [FAIL][14] ([i915#2842]) +3 similar 
issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-kbl1/igt@gem_exec_fair@basic-p...@vecs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/shard-kbl7/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_flush@basic-wb-ro-before-default:
- shard-snb:  [PASS][15] -> [SKIP][16] ([fdo#109271])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-snb7/igt@gem_exec_fl...@basic-wb-ro-before-default.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/shard-snb6/igt@gem_exec_fl...@basic-wb-ro-before-default.html

  * igt@gem_huc_copy@huc-copy:
- shard-skl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/shard-skl10/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-kbl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/shard-kbl4/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html

  * igt@gem_pread@exhaustion:
- shard-kbl:  NOTRUN -> [WARN][19] ([i915#2658])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/shard-kbl7/igt@gem_pr...@exhaustion.html

  * igt@gem_userptr_blits@input-checking:
- shard-kbl:  NOTRUN -> [DMESG-WARN][20] ([i915#4991])
   [20]: 
https://int

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/fbc: Do not apply WA 22014263786 to DG2 (rev2)

[Souza, Jose]

Hi Lakshmi

Can you please help with this failures?
Current code is only doing a small change that would only affect DG2.

On Fri, 2022-06-03 at 20:09 +, Patchwork wrote:
Patch Details
Series: drm/i915/display/fbc: Do not apply WA 22014263786 to DG2 (rev2)
URL:https://patchwork.freedesktop.org/series/104678/
State:  failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/index.html
CI Bug Log - changes from CI_DRM_11726 -> Patchwork_104678v2
Summary

FAILURE

Serious unknown changes coming with Patchwork_104678v2 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_104678v2, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/index.html

Participating hosts (43 -> 44)

Additional (2): bat-adln-1 fi-kbl-x1275
Missing (1): fi-rkl-11600

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_104678v2:

IGT changes
Possible regressions

  *   igt@kms_addfb_basic@unused-pitches:
 *   fi-kbl-soraka: 
PASS
 -> 
INCOMPLETE

Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  *   igt@i915_selftest@live@hangcheck:

 *   {fi-ehl-2}: 
PASS
 -> 
INCOMPLETE
  *   igt@kms_frontbuffer_tracking@basic:

 *   {bat-adln-1}: NOTRUN -> 
SKIP
 +19 similar issues

Known issues

Here are the changes found in Patchwork_104678v2 that come from known issues:

IGT changes
Issues hit

  *   igt@gem_huc_copy@huc-copy:

 *   fi-kbl-x1275: NOTRUN -> 
SKIP
 (fdo#109271 / 
i915#2190)
  *   igt@gem_lmem_swapping@verify-random:

 *   fi-kbl-x1275: NOTRUN -> 
SKIP
 (fdo#109271 / 
i915#4613) +3 similar 
issues
  *   igt@i915_selftest@live@hangcheck:

 *   bat-dg1-5: 
PASS
 -> 
DMESG-FAIL
 (i915#4494 / 
i915#4957)

 *   bat-dg1-6: 
PASS
 -> 
DMESG-FAIL
 (i915#4494 / 
i915#4957)

  *   igt@i915_selftest@live@requests:

 *   fi-blb-e6850: 
PASS
 -> 
DMESG-FAIL
 (i915#4528)
  *   igt@i915_selftest@live@reset:

 *   bat-adlp-4: 
PASS
 -> 
DMESG-FAIL
 (i915#4983)
  *   igt@kms_chamelium@dp-hpd-fast:

 *   fi-kbl-x1275: NOTRUN -> 
SKIP
 (fdo#109271 / 
fdo#111827) +8 similar 
issues
  *   igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:

 *   fi-kbl-x1275: NOTRUN -> 
SKIP
 (fdo#109271

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/fbc: Do not apply WA 22014263786 to DG2 (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/display/fbc: Do not apply WA 22014263786 to DG2 (rev2)
URL   : https://patchwork.freedesktop.org/series/104678/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11726 -> Patchwork_104678v2


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_104678v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_104678v2, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/index.html

Participating hosts (43 -> 44)
--

  Additional (2): bat-adln-1 fi-kbl-x1275 
  Missing(1): fi-rkl-11600 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_104678v2:

### IGT changes ###

 Possible regressions 

  * igt@kms_addfb_basic@unused-pitches:
- fi-kbl-soraka:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-kbl-soraka/igt@kms_addfb_ba...@unused-pitches.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-soraka/igt@kms_addfb_ba...@unused-pitches.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@hangcheck:
- {fi-ehl-2}: [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_frontbuffer_tracking@basic:
- {bat-adln-1}:   NOTRUN -> [SKIP][5] +19 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/bat-adln-1/igt@kms_frontbuffer_track...@basic.html

  
Known issues


  Here are the changes found in Patchwork_104678v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-x1275:   NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-x1275/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-kbl-x1275:   NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-x1275/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-5:  [PASS][8] -> [DMESG-FAIL][9] ([i915#4494] / 
[i915#4957])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
- bat-dg1-6:  [PASS][10] -> [DMESG-FAIL][11] ([i915#4494] / 
[i915#4957])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [PASS][12] -> [DMESG-FAIL][13] ([i915#4528])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@reset:
- bat-adlp-4: [PASS][14] -> [DMESG-FAIL][15] ([i915#4983])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/bat-adlp-4/igt@i915_selftest@l...@reset.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/bat-adlp-4/igt@i915_selftest@l...@reset.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-kbl-x1275:   NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-x1275/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-x1275:   NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-x1275/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_vgem@basic-userptr:
- fi-kbl-x1275:   NOTRUN -> [SKIP][18] ([fdo#109271]) +12 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/fi-kbl-x1275/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][19] ([i915#4312])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104678v2/bat-adlp-4/igt@run

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: i915_drv.h & i915_gem.h header refactoring

[Patchwork]

== Series Details ==

Series: drm/i915: i915_drv.h & i915_gem.h header refactoring
URL   : https://patchwork.freedesktop.org/series/104725/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11726 -> Patchwork_104725v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/index.html

Participating hosts (43 -> 44)
--

  Additional (4): bat-adln-1 fi-kbl-x1275 bat-dg2-9 bat-atsm-1 
  Missing(3): bat-dg2-8 bat-jsl-2 fi-hsw-4770 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_104725v1:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_suspend@basic-s2idle-without-i915:
- {bat-adln-1}:   NOTRUN -> [DMESG-WARN][1] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/bat-adln-1/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@kms_frontbuffer_tracking@basic:
- {bat-adln-1}:   NOTRUN -> [SKIP][2] +19 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/bat-adln-1/igt@kms_frontbuffer_track...@basic.html

  
Known issues


  Here are the changes found in Patchwork_104725v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-x1275:   NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/fi-kbl-x1275/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-kbl-x1275:   NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/fi-kbl-x1275/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-6:  [PASS][5] -> [INCOMPLETE][6] ([i915#4418])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/bat-dg1-6/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-5:  [PASS][7] -> [DMESG-FAIL][8] ([i915#4494] / 
[i915#4957])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [PASS][9] -> [DMESG-FAIL][10] ([i915#4528])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-kbl-x1275:   NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/fi-kbl-x1275/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-x1275:   NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/fi-kbl-x1275/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_vgem@basic-userptr:
- fi-kbl-x1275:   NOTRUN -> [SKIP][13] ([fdo#109271]) +12 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104725v1/fi-kbl-x1275/igt@prime_v...@basic-userptr.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4077]: https://gitlab.fr

Re: [Intel-gfx] [PATCH v1 11/13] drm/edid: add HF-EEODB support to EDID read and allocation

[Ville Syrjälä]

On Tue, May 24, 2022 at 01:39:33PM +0300, Jani Nikula wrote:
> HDMI 2.1 section 10.3.6 defines an HDMI Forum EDID Extension Override
> Data Block, which may contain a different extension count than the base
> block claims. Add support for reading more EDID data if available. The
> extra blocks aren't parsed yet, though.
> 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/drm_edid.c | 81 --
>  1 file changed, 78 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 5e0a91da565e..ba0c880dc133 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -1581,6 +1581,15 @@ static bool version_greater(const struct drm_edid 
> *drm_edid,
>   (edid->version == version && edid->revision > revision);
>  }
>  
> +static int edid_hfeeodb_extension_block_count(const struct edid *edid);
> +
> +static int edid_hfeeodb_block_count(const struct edid *edid)
> +{
> + int eeodb = edid_hfeeodb_extension_block_count(edid);
> +
> + return eeodb ? eeodb + 1 : 0;
> +}
> +
>  static int edid_extension_block_count(const struct edid *edid)
>  {
>   return edid->extensions;
> @@ -2026,6 +2035,11 @@ static struct edid *edid_filter_invalid_blocks(struct 
> edid *edid,
>   struct edid *new;
>   int i, valid_blocks = 0;
>  
> + /*
> +  * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
> +  * back to regular extension count here. We don't want to start
> +  * modifying the HF-EEODB extension too.
> +  */
>   for (i = 0; i < edid_block_count(edid); i++) {
>   const void *src_block = edid_block_data(edid, i);
>  
> @@ -2235,7 +2249,7 @@ static struct edid *_drm_do_get_edid(struct 
> drm_connector *connector,
>size_t *size)
>  {
>   enum edid_block_status status;
> - int i, invalid_blocks = 0;
> + int i, num_blocks, invalid_blocks = 0;
>   struct edid *edid, *new;
>   size_t alloc_size = EDID_LENGTH;
>  
> @@ -2277,7 +2291,8 @@ static struct edid *_drm_do_get_edid(struct 
> drm_connector *connector,
>   goto fail;
>   edid = new;
>  
> - for (i = 1; i < edid_block_count(edid); i++) {
> + num_blocks = edid_block_count(edid);
> + for (i = 1; i < num_blocks; i++) {
>   void *block = (void *)edid_block_data(edid, i);
>  
>   status = edid_block_read(block, i, read_block, context);
> @@ -2288,11 +2303,31 @@ static struct edid *_drm_do_get_edid(struct 
> drm_connector *connector,
>   if (status == EDID_BLOCK_READ_FAIL)
>   goto fail;
>   invalid_blocks++;
> + } else if (i == 1) {
> + /*
> +  * If the first EDID extension is a CTA extension, and
> +  * the first Data Block is HF-EEODB, override the
> +  * extension block count.
> +  *
> +  * Note: HF-EEODB could specify a smaller extension
> +  * count too, but we can't risk allocating a smaller
> +  * amount.
> +  */
> + int eeodb = edid_hfeeodb_block_count(edid);
> +
> + if (eeodb > num_blocks) {
> + num_blocks = eeodb;
> + alloc_size = edid_size_by_blocks(num_blocks);
> + new = krealloc(edid, alloc_size, GFP_KERNEL);
> + if (!new)
> + goto fail;
> + edid = new;
> + }
>   }
>   }
>  
>   if (invalid_blocks) {
> - connector_bad_edid(connector, edid, edid_block_count(edid));
> + connector_bad_edid(connector, edid, num_blocks);
>  
>   edid = edid_filter_invalid_blocks(edid, &alloc_size);
>   }
> @@ -3825,6 +3860,7 @@ static int add_detailed_modes(struct drm_connector 
> *connector,
>  #define CTA_EXT_DB_HDR_STATIC_METADATA   6
>  #define CTA_EXT_DB_420_VIDEO_DATA14
>  #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
> +#define CTA_EXT_DB_HF_EEODB  0x78
>  #define CTA_EXT_DB_HF_SCDB   0x79
>  
>  #define EDID_BASIC_AUDIO (1 << 6)
> @@ -4868,6 +4904,12 @@ static bool cea_db_is_hdmi_forum_vsdb(const struct 
> cea_db *db)
>   cea_db_payload_len(db) >= 7;
>  }
>  
> +static bool cea_db_is_hdmi_forum_eeodb(const void *db)
> +{
> + return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
> + cea_db_payload_len(db) >= 2;
> +}
> +
>  static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
>  {
>   return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
> @@ -4902,6 +4944,39 @@ static bool cea_db_is_hdmi_hdr_metadata_block(const 
> struct cea_db *db)
>   cea_db_payload_len(db) >= 3;
> 

[Intel-gfx] [PATCH v2 1/3] drm/i915: Initialize eDP source rates after per-panel VBT parsing

[Ville Syrjala]

From: Ville Syrjälä 

We'll need to know the VBT panel_type before we can determine the
maximum link rate for eDP. To that end move
intel_dp_set_source_rates() & co. to be called after the per-panel
VBT parsing has been done.

intel_dp_mst_encoder_init() depends on the source rates so we'll
have to do it a bit later as well.

v2: Fix the intel_dp_mst_encoder_init() oops

Reviewed-by: Jani Nikula  #v1
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 19 ---
 1 file changed, 8 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index b8e2d3cd4d68..60b89a722bd8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2852,9 +2852,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
intel_dp_set_sink_rates(intel_dp);
intel_dp_set_max_sink_lane_count(intel_dp);
 
-   intel_dp_set_common_rates(intel_dp);
-   intel_dp_reset_max_link_params(intel_dp);
-
/* Read the eDP DSC DPCD registers */
if (DISPLAY_VER(dev_priv) >= 10)
intel_dp_get_dsc_sink_cap(intel_dp);
@@ -5342,11 +5339,8 @@ intel_dp_init_connector(struct intel_digital_port 
*dig_port,
type = DRM_MODE_CONNECTOR_DisplayPort;
}
 
-   intel_dp_set_source_rates(intel_dp);
intel_dp_set_default_sink_rates(intel_dp);
intel_dp_set_default_max_sink_lane_count(intel_dp);
-   intel_dp_set_common_rates(intel_dp);
-   intel_dp_reset_max_link_params(intel_dp);
 
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
@@ -5374,16 +5368,19 @@ intel_dp_init_connector(struct intel_digital_port 
*dig_port,
else
intel_connector->get_hw_state = intel_connector_get_hw_state;
 
-   /* init MST on ports that can support it */
-   intel_dp_mst_encoder_init(dig_port,
- intel_connector->base.base.id);
-
if (!intel_edp_init_connector(intel_dp, intel_connector)) {
intel_dp_aux_fini(intel_dp);
-   intel_dp_mst_encoder_cleanup(dig_port);
goto fail;
}
 
+   intel_dp_set_source_rates(intel_dp);
+   intel_dp_set_common_rates(intel_dp);
+   intel_dp_reset_max_link_params(intel_dp);
+
+   /* init MST on ports that can support it */
+   intel_dp_mst_encoder_init(dig_port,
+ intel_connector->base.base.id);
+
intel_dp_add_properties(intel_dp, connector);
 
if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
-- 
2.35.1

Re: [Intel-gfx] [PATCH 1/2] drm/i915/opregion: add function to check if headless sku

[Souza, Jose]

On Fri, 2022-06-03 at 13:14 +, Hogander, Jouni wrote:
> On Fri, 2022-06-03 at 15:43 +0300, Jani Nikula wrote:
> > On Fri, 03 Jun 2022, Jouni Högander  wrote:
> > > Export headless sku bit (bit 13) from opregion->header->pcon as an
> > > interface to check if our device is headless configuration.
> > > 
> > > Bspec: 53441
> > > Signed-off-by: Jouni Högander 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_opregion.c | 12 
> > >  drivers/gpu/drm/i915/display/intel_opregion.h |  7 +++
> > >  2 files changed, 19 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
> > > b/drivers/gpu/drm/i915/display/intel_opregion.c
> > > index f31e8c3f8ce0..eab3f2e6b786 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> > > @@ -53,6 +53,8 @@
> > >  #define MBOX_ASLE_EXTBIT(4)  /* Mailbox #5 */
> > >  #define MBOX_BACKLIGHT   BIT(5)  /* Mailbox #2
> > > (valid from v3.x) */
> > >  
> > > +#define PCON_HEADLESS_SKUBIT(13)
> > 
> > Here we go again.
> > 
> > What does headless mean here? The spec does not say. Does it have
> > display hardware? Apparently yes, since otherwise we wouldn't be
> > here.
> 
> This is for hybrid setup with several display hw and the panel wont be
> connected into device driven by i915 driver.
> 
> > We have INTEL_DISPLAY_ENABLED() which should do the right thing when
> > you
> > do have display hardware and have done output setup etc. but want to
> > force them disconnected, i.e. you take the hardware over properly,
> > but
> > put it to sleep for power savings.
> > 
> > Maybe we should bolt this opregion check in that macro?
> > 
> > Maybe we need to use INTEL_DISPLAY_ENABLED() also to prevent polling.
> 
> Thank you for pointing this out. HAS_DISPLAY I already notice and it's
> not suitable for what we want here. I think bolting this check into
> INTEL_DISPLAY_ENABLED as you suggested is enough. That will prevent
> waking up the hw into D0 state for polling.

A headless sku should not have any DDI ports enabled, much easier check for 
that.

> 
> > 
> > I certainly would not want to add another mode that's separate from
> > HAS_DISPLAY() and INTEL_DISPLAY_ENABLED().
> 
> No need for this. I think we can go with INTEL_DISPLAY_ENABLED.
> > 
> > > +
> > >  struct opregion_header {
> > >   u8 signature[16];
> > >   u32 size;
> > > @@ -1135,6 +1137,16 @@ struct edid *intel_opregion_get_edid(struct
> > > intel_connector *intel_connector)
> > >   return new_edid;
> > >  }
> > >  
> > > +bool intel_opregion_headless_sku(struct drm_i915_private *i915)
> > > +{
> > > + struct intel_opregion *opregion = &i915->opregion;
> > > +
> > > + if (!opregion->header)
> > > + return false;
> > > +
> > > + return opregion->header->pcon & PCON_HEADLESS_SKU;
> > 
> > We should probably start checking for opregion version for this stuff
> > too.
> > 
> 
> Yes, I will do this change.
> 
> > 
> > BR,
> > Jani.
> > 
> > > +}
> > > +
> > >  void intel_opregion_register(struct drm_i915_private *i915)
> > >  {
> > >   struct intel_opregion *opregion = &i915->opregion;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h
> > > b/drivers/gpu/drm/i915/display/intel_opregion.h
> > > index 82cc0ba34af7..5ad96e1d8278 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_opregion.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_opregion.h
> > > @@ -76,6 +76,8 @@ int intel_opregion_notify_adapter(struct
> > > drm_i915_private *dev_priv,
> > >  int intel_opregion_get_panel_type(struct drm_i915_private
> > > *dev_priv);
> > >  struct edid *intel_opregion_get_edid(struct intel_connector
> > > *connector);
> > >  
> > > +bool intel_opregion_headless_sku(struct drm_i915_private *i915);
> > > +
> > >  #else /* CONFIG_ACPI*/
> > >  
> > >  static inline int intel_opregion_setup(struct drm_i915_private
> > > *dev_priv)
> > > @@ -127,6 +129,11 @@ intel_opregion_get_edid(struct intel_connector
> > > *connector)
> > >   return NULL;
> > >  }
> > >  
> > > +bool intel_opregion_headless_sku(struct drm_i915_private *i915)
> > > +{
> > > + return false;
> > > +}
> > > +
> > >  #endif /* CONFIG_ACPI */
> > >  
> > >  #endif
> 

[Intel-gfx] [PATCH v5 i-g-t 2/3] tests/i915/query: Add descriptions to existing tests

[John . C . Harrison]

From: John Harrison 

None of the query tests had a description. So make some up.

Signed-off-by: John Harrison 
---
 tests/i915/i915_query.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 246a979af72a..35a91d245ec1 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -923,34 +923,41 @@ igt_main
devid = intel_get_drm_devid(fd);
}
 
+   igt_describe("Test reponse to an invalid query call");
igt_subtest("query-garbage")
test_query_garbage(fd);
 
+   igt_describe("Test response to invalid DRM_I915_QUERY_TOPOLOGY_INFO 
query");
igt_subtest("query-topology-garbage-items") {
igt_require(query_topology_supported(fd));
test_query_topology_garbage_items(fd);
}
 
+   igt_describe("Guardband test for DRM_I915_QUERY_TOPOLOGY_INFO query");
igt_subtest("query-topology-kernel-writes") {
igt_require(query_topology_supported(fd));
test_query_topology_kernel_writes(fd);
}
 
+   igt_describe("Verify DRM_I915_QUERY_TOPOLOGY_INFO query fails when it 
is not supported");
igt_subtest("query-topology-unsupported") {
igt_require(!query_topology_supported(fd));
test_query_topology_unsupported(fd);
}
 
+   igt_describe("Compare new DRM_I915_QUERY_TOPOLOGY_INFO query with 
legacy (sub)slice getparams");
igt_subtest("query-topology-coherent-slice-mask") {
igt_require(query_topology_supported(fd));
test_query_topology_coherent_slice_mask(fd);
}
 
+   igt_describe("More compare new DRM_I915_QUERY_TOPOLOGY_INFO query with 
legacy (sub)slice getparams");
igt_subtest("query-topology-matches-eu-total") {
igt_require(query_topology_supported(fd));
test_query_topology_matches_eu_total(fd);
}
 
+   igt_describe("Verify DRM_I915_QUERY_TOPOLOGY_INFO query against 
hardcoded known values for certain platforms");
igt_subtest("query-topology-known-pci-ids") {
igt_require(query_topology_supported(fd));
igt_require(IS_HASWELL(devid) || IS_BROADWELL(devid) ||
@@ -959,16 +966,19 @@ igt_main
test_query_topology_known_pci_ids(fd, devid);
}
 
+   igt_describe("Test DRM_I915_QUERY_GEOMETRY_SUBSLICES query");
igt_subtest("test-query-geometry-subslices") {
igt_require(query_geometry_subslices_supported(fd));
test_query_geometry_subslices(fd);
}
 
+   igt_describe("Dodgy returned data tests for 
DRM_I915_QUERY_MEMORY_REGIONS");
igt_subtest("query-regions-garbage-items") {
igt_require(query_regions_supported(fd));
test_query_regions_garbage_items(fd);
}
 
+   igt_describe("Basic tests for DRM_I915_QUERY_MEMORY_REGIONS");
igt_subtest("query-regions-sanity-check") {
igt_require(query_regions_supported(fd));
test_query_regions_sanity_check(fd);
@@ -979,9 +989,11 @@ igt_main
igt_require(query_engine_info_supported(fd));
}
 
+   igt_describe("Negative tests for DRM_I915_QUERY_ENGINE_INFO");
igt_subtest("engine-info-invalid")
engines_invalid(fd);
 
+   igt_describe("Positive tests for DRM_I915_QUERY_ENGINE_INFO");
igt_subtest("engine-info")
engines(fd);
}
-- 
2.36.0

[Intel-gfx] [PATCH v5 i-g-t 3/3] tests/i915/query: Query, parse and validate the hwconfig table

[John . C . Harrison]

From: Rodrigo Vivi 

Newer platforms have an embedded table giving details about that
platform's hardware configuration. This table can be retrieved from
the KMD via the existing query API. So add a test for it as both an
example of how to fetch the table and to validate the contents as much
as is possible.

Signed-off-by: Rodrigo Vivi 
Signed-off-by: John Harrison 
Cc: Slawomir Milczarek 
Reviewed-by: Matthew Brost 
---
 lib/intel_hwconfig_types.h | 118 
 tests/i915/i915_query.c| 180 +
 2 files changed, 298 insertions(+)
 create mode 100644 lib/intel_hwconfig_types.h

diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
new file mode 100644
index ..d5db217afba2
--- /dev/null
+++ b/lib/intel_hwconfig_types.h
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef _INTEL_HWCONFIG_TYPES_H_
+#define _INTEL_HWCONFIG_TYPES_H_
+
+#include "intel_chipset.h"
+
+/**
+ * enum intel_hwconfig - Global definition of hwconfig table attributes
+ *
+ * Intel devices provide a KLV (Key/Length/Value) table containing
+ * the static hardware configuration for that platform.
+ * This enum defines the current attribute keys for this KLV.
+ */
+enum intel_hwconfig {
+   INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
+   INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED,/* 2 */
+   INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS,  /* 3 */
+   INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
+   INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES,   /* 5 */
+   INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB,  /* 6 */
+   INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT,/* 7 */
+   INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
+   INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR,/* 9 */
+   INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
+   INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
+   INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
+   INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED,   /* 13 */
+   INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB,   /* 14 */
+   INTEL_HWCONFIG_NUM_THREADS_PER_EU,  /* 15 */
+   INTEL_HWCONFIG_TOTAL_VS_THREADS,/* 16 */
+   INTEL_HWCONFIG_TOTAL_GS_THREADS,/* 17 */
+   INTEL_HWCONFIG_TOTAL_HS_THREADS,/* 18 */
+   INTEL_HWCONFIG_TOTAL_DS_THREADS,/* 19 */
+   INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS,   /* 20 */
+   INTEL_HWCONFIG_TOTAL_PS_THREADS,/* 21 */
+   INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE,/* 22 */
+   INTEL_HWCONFIG_MAX_RCS, /* 23 */
+   INTEL_HWCONFIG_MAX_CCS, /* 24 */
+   INTEL_HWCONFIG_MAX_VCS, /* 25 */
+   INTEL_HWCONFIG_MAX_VECS,/* 26 */
+   INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
+   INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB,   /* 28 */
+   INTEL_HWCONFIG_MIN_VS_URB_ENTRIES,  /* 29 */
+   INTEL_HWCONFIG_MAX_VS_URB_ENTRIES,  /* 30 */
+   INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
+   INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
+   INTEL_HWCONFIG_MIN_HS_URB_ENTRIES,  /* 33 */
+   INTEL_HWCONFIG_MAX_HS_URB_ENTRIES,  /* 34 */
+   INTEL_HWCONFIG_MIN_GS_URB_ENTRIES,  /* 35 */
+   INTEL_HWCONFIG_MAX_GS_URB_ENTRIES,  /* 36 */
+   INTEL_HWCONFIG_MIN_DS_URB_ENTRIES,  /* 37 */
+   INTEL_HWCONFIG_MAX_DS_URB_ENTRIES,  /* 38 */
+   INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
+   INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE,/* 40 */
+   INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES,  /* 41 */
+   INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES,  /* 42 */
+   INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES,   /* 43 */
+   INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT,/* 44 */
+   INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT,/* 45 */
+   INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS,   /* 46 */
+   INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS,/* 47 */
+   INTEL_HWCONFIG_MIN_CS_URB_ENTRIES,  /* 48 */
+   INTEL_HWCONFIG_MAX_CS_URB_ENTRIES,  /* 49 */
+   INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB,   /* 50 */
+   INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST,  /* 51 */

[Intel-gfx] [PATCH v5 i-g-t 1/3] include/drm-uapi: Update to latest i915_drm.h

[John . C . Harrison]

From: John Harrison 

Update to the latest master version of the DRM UAPI header file from
git://anongit.freedesktop.org/git/drm/drm:
  c4955d9cd2fc Merge tag 'drm-intel-next-fixes-2022-05-24' of
  git://anongit.freedesktop.org/drm/drm-intel into drm-next

Signed-off-by: John Harrison 
---
 include/drm-uapi/i915_drm.h | 398 
 1 file changed, 312 insertions(+), 86 deletions(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 9c9e1afa61ba..b4efc96c2edc 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -154,25 +154,77 @@ enum i915_mocs_table_index {
I915_MOCS_CACHED,
 };
 
-/*
+/**
+ * enum drm_i915_gem_engine_class - uapi engine type enumeration
+ *
  * Different engines serve different roles, and there may be more than one
- * engine serving each role. enum drm_i915_gem_engine_class provides a
- * classification of the role of the engine, which may be used when requesting
- * operations to be performed on a certain subset of engines, or for providing
- * information about that group.
+ * engine serving each role.  This enum provides a classification of the role
+ * of the engine, which may be used when requesting operations to be performed
+ * on a certain subset of engines, or for providing information about that
+ * group.
  */
 enum drm_i915_gem_engine_class {
+   /**
+* @I915_ENGINE_CLASS_RENDER:
+*
+* Render engines support instructions used for 3D, Compute (GPGPU),
+* and programmable media workloads.  These instructions fetch data and
+* dispatch individual work items to threads that operate in parallel.
+* The threads run small programs (called "kernels" or "shaders") on
+* the GPU's execution units (EUs).
+*/
I915_ENGINE_CLASS_RENDER= 0,
+
+   /**
+* @I915_ENGINE_CLASS_COPY:
+*
+* Copy engines (also referred to as "blitters") support instructions
+* that move blocks of data from one location in memory to another,
+* or that fill a specified location of memory with fixed data.
+* Copy engines can perform pre-defined logical or bitwise operations
+* on the source, destination, or pattern data.
+*/
I915_ENGINE_CLASS_COPY  = 1,
+
+   /**
+* @I915_ENGINE_CLASS_VIDEO:
+*
+* Video engines (also referred to as "bit stream decode" (BSD) or
+* "vdbox") support instructions that perform fixed-function media
+* decode and encode.
+*/
I915_ENGINE_CLASS_VIDEO = 2,
+
+   /**
+* @I915_ENGINE_CLASS_VIDEO_ENHANCE:
+*
+* Video enhancement engines (also referred to as "vebox") support
+* instructions related to image enhancement.
+*/
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
 
-   /* should be kept compact */
+   /**
+* @I915_ENGINE_CLASS_COMPUTE:
+*
+* Compute engines support a subset of the instructions available
+* on render engines:  compute engines support Compute (GPGPU) and
+* programmable media workloads, but do not support the 3D pipeline.
+*/
+   I915_ENGINE_CLASS_COMPUTE   = 4,
+
+   /* Values in this enum should be kept compact. */
 
+   /**
+* @I915_ENGINE_CLASS_INVALID:
+*
+* Placeholder value to represent an invalid engine class assignment.
+*/
I915_ENGINE_CLASS_INVALID   = -1
 };
 
-/*
+/**
+ * struct i915_engine_class_instance - Engine class/instance identifier
+ *
  * There may be more than one engine fulfilling any role within the system.
  * Each engine of a class is given a unique instance number and therefore
  * any engine can be specified by its class:instance tuplet. APIs that allow
@@ -180,10 +232,21 @@ enum drm_i915_gem_engine_class {
  * for this identification.
  */
 struct i915_engine_class_instance {
-   __u16 engine_class; /* see enum drm_i915_gem_engine_class */
-   __u16 engine_instance;
+   /**
+* @engine_class:
+*
+* Engine class from enum drm_i915_gem_engine_class
+*/
+   __u16 engine_class;
 #define I915_ENGINE_CLASS_INVALID_NONE -1
 #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
+
+   /**
+* @engine_instance:
+*
+* Engine instance.
+*/
+   __u16 engine_instance;
 };
 
 /**
@@ -1118,10 +1181,16 @@ struct drm_i915_gem_exec_object2 {
/**
 * When the EXEC_OBJECT_PINNED flag is specified this is populated by
 * the user with the GTT offset at which this object will be pinned.
+*
 * When the I915_EXEC_NO_RELOC flag is specified this must contain the
 * presumed_offset of the object.
+*
 * During execbuffer2 the kernel populates it with the value of the
 * current GTT offset of the object, for future presumed_offset writes.
+*
+ 

[Intel-gfx] [PATCH v5 i-g-t 0/3] Update DRM UAPI and add test for new hw info query

[John . C . Harrison]

From: John Harrison 

Various UMDs require hardware configuration information about the
current platform. A new interface has been added to the KMD to return
this information. So, add a test for the new interface.

Also, update to the latest DRM UAPI header file that contains the new
query enums.

Lastly, none of the query tests had description entries. So made some
up.

v2: Rebased to newer baseline.
v3: Update UAPI header file.
v4: Use correct method for updating header file.
v5: Add descriptions to all the query tests.

Signed-off-by: John Harrison 


John Harrison (2):
  include/drm-uapi: Update to latest i915_drm.h
  tests/i915/query: Add descriptions to existing tests

Rodrigo Vivi (1):
  tests/i915/query: Query, parse and validate the hwconfig table

 include/drm-uapi/i915_drm.h | 398 
 lib/intel_hwconfig_types.h  | 118 +++
 tests/i915/i915_query.c | 192 +
 3 files changed, 622 insertions(+), 86 deletions(-)
 create mode 100644 lib/intel_hwconfig_types.h

-- 
2.36.0

[Intel-gfx] [PATCH v4 i-g-t 1/2] include/drm-uapi: Update to latest i915_drm.h

[John . C . Harrison]

From: John Harrison 

Update to the latest master version of the DRM UAPI header file from
git://anongit.freedesktop.org/git/drm/drm:
  c4955d9cd2fc Merge tag 'drm-intel-next-fixes-2022-05-24' of
  git://anongit.freedesktop.org/drm/drm-intel into drm-next

Signed-off-by: John Harrison 
---
 include/drm-uapi/i915_drm.h | 398 
 1 file changed, 312 insertions(+), 86 deletions(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 9c9e1afa61ba..b4efc96c2edc 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -154,25 +154,77 @@ enum i915_mocs_table_index {
I915_MOCS_CACHED,
 };
 
-/*
+/**
+ * enum drm_i915_gem_engine_class - uapi engine type enumeration
+ *
  * Different engines serve different roles, and there may be more than one
- * engine serving each role. enum drm_i915_gem_engine_class provides a
- * classification of the role of the engine, which may be used when requesting
- * operations to be performed on a certain subset of engines, or for providing
- * information about that group.
+ * engine serving each role.  This enum provides a classification of the role
+ * of the engine, which may be used when requesting operations to be performed
+ * on a certain subset of engines, or for providing information about that
+ * group.
  */
 enum drm_i915_gem_engine_class {
+   /**
+* @I915_ENGINE_CLASS_RENDER:
+*
+* Render engines support instructions used for 3D, Compute (GPGPU),
+* and programmable media workloads.  These instructions fetch data and
+* dispatch individual work items to threads that operate in parallel.
+* The threads run small programs (called "kernels" or "shaders") on
+* the GPU's execution units (EUs).
+*/
I915_ENGINE_CLASS_RENDER= 0,
+
+   /**
+* @I915_ENGINE_CLASS_COPY:
+*
+* Copy engines (also referred to as "blitters") support instructions
+* that move blocks of data from one location in memory to another,
+* or that fill a specified location of memory with fixed data.
+* Copy engines can perform pre-defined logical or bitwise operations
+* on the source, destination, or pattern data.
+*/
I915_ENGINE_CLASS_COPY  = 1,
+
+   /**
+* @I915_ENGINE_CLASS_VIDEO:
+*
+* Video engines (also referred to as "bit stream decode" (BSD) or
+* "vdbox") support instructions that perform fixed-function media
+* decode and encode.
+*/
I915_ENGINE_CLASS_VIDEO = 2,
+
+   /**
+* @I915_ENGINE_CLASS_VIDEO_ENHANCE:
+*
+* Video enhancement engines (also referred to as "vebox") support
+* instructions related to image enhancement.
+*/
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
 
-   /* should be kept compact */
+   /**
+* @I915_ENGINE_CLASS_COMPUTE:
+*
+* Compute engines support a subset of the instructions available
+* on render engines:  compute engines support Compute (GPGPU) and
+* programmable media workloads, but do not support the 3D pipeline.
+*/
+   I915_ENGINE_CLASS_COMPUTE   = 4,
+
+   /* Values in this enum should be kept compact. */
 
+   /**
+* @I915_ENGINE_CLASS_INVALID:
+*
+* Placeholder value to represent an invalid engine class assignment.
+*/
I915_ENGINE_CLASS_INVALID   = -1
 };
 
-/*
+/**
+ * struct i915_engine_class_instance - Engine class/instance identifier
+ *
  * There may be more than one engine fulfilling any role within the system.
  * Each engine of a class is given a unique instance number and therefore
  * any engine can be specified by its class:instance tuplet. APIs that allow
@@ -180,10 +232,21 @@ enum drm_i915_gem_engine_class {
  * for this identification.
  */
 struct i915_engine_class_instance {
-   __u16 engine_class; /* see enum drm_i915_gem_engine_class */
-   __u16 engine_instance;
+   /**
+* @engine_class:
+*
+* Engine class from enum drm_i915_gem_engine_class
+*/
+   __u16 engine_class;
 #define I915_ENGINE_CLASS_INVALID_NONE -1
 #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
+
+   /**
+* @engine_instance:
+*
+* Engine instance.
+*/
+   __u16 engine_instance;
 };
 
 /**
@@ -1118,10 +1181,16 @@ struct drm_i915_gem_exec_object2 {
/**
 * When the EXEC_OBJECT_PINNED flag is specified this is populated by
 * the user with the GTT offset at which this object will be pinned.
+*
 * When the I915_EXEC_NO_RELOC flag is specified this must contain the
 * presumed_offset of the object.
+*
 * During execbuffer2 the kernel populates it with the value of the
 * current GTT offset of the object, for future presumed_offset writes.
+*
+ 

[Intel-gfx] [PATCH v4 i-g-t 0/2] Update DRM UAPI and add test for new hw info query

[John . C . Harrison]

From: John Harrison 

Various UMDs require hardware configuration information about the
current platform. A new interface has been added to the KMD to return
this information. So, add a test for the new interface.

Also, update to the latest DRM UAPI header file that contains the new
query enums.

v2: Rebased to newer baseline.
v3: Update UAPI header file.
v4: Use correct method for updating header file.

Signed-off-by: John Harrison 


John Harrison (1):
  include/drm-uapi: Update to latest i915_drm.h

Rodrigo Vivi (1):
  tests/i915/query: Query, parse and validate the hwconfig table

 include/drm-uapi/i915_drm.h | 398 
 lib/intel_hwconfig_types.h  | 118 +++
 tests/i915/i915_query.c | 179 
 3 files changed, 609 insertions(+), 86 deletions(-)
 create mode 100644 lib/intel_hwconfig_types.h

-- 
2.36.0

[Intel-gfx] [PATCH v4 i-g-t 2/2] tests/i915/query: Query, parse and validate the hwconfig table

[John . C . Harrison]

From: Rodrigo Vivi 

Newer platforms have an embedded table giving details about that
platform's hardware configuration. This table can be retrieved from
the KMD via the existing query API. So add a test for it as both an
example of how to fetch the table and to validate the contents as much
as is possible.

Signed-off-by: Rodrigo Vivi 
Signed-off-by: John Harrison 
Cc: Slawomir Milczarek 
Reviewed-by: Matthew Brost 
---
 lib/intel_hwconfig_types.h | 118 
 tests/i915/i915_query.c| 179 +
 2 files changed, 297 insertions(+)
 create mode 100644 lib/intel_hwconfig_types.h

diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
new file mode 100644
index ..d5db217afba2
--- /dev/null
+++ b/lib/intel_hwconfig_types.h
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef _INTEL_HWCONFIG_TYPES_H_
+#define _INTEL_HWCONFIG_TYPES_H_
+
+#include "intel_chipset.h"
+
+/**
+ * enum intel_hwconfig - Global definition of hwconfig table attributes
+ *
+ * Intel devices provide a KLV (Key/Length/Value) table containing
+ * the static hardware configuration for that platform.
+ * This enum defines the current attribute keys for this KLV.
+ */
+enum intel_hwconfig {
+   INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
+   INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED,/* 2 */
+   INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS,  /* 3 */
+   INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
+   INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES,   /* 5 */
+   INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB,  /* 6 */
+   INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT,/* 7 */
+   INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
+   INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR,/* 9 */
+   INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
+   INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
+   INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
+   INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED,   /* 13 */
+   INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB,   /* 14 */
+   INTEL_HWCONFIG_NUM_THREADS_PER_EU,  /* 15 */
+   INTEL_HWCONFIG_TOTAL_VS_THREADS,/* 16 */
+   INTEL_HWCONFIG_TOTAL_GS_THREADS,/* 17 */
+   INTEL_HWCONFIG_TOTAL_HS_THREADS,/* 18 */
+   INTEL_HWCONFIG_TOTAL_DS_THREADS,/* 19 */
+   INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS,   /* 20 */
+   INTEL_HWCONFIG_TOTAL_PS_THREADS,/* 21 */
+   INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE,/* 22 */
+   INTEL_HWCONFIG_MAX_RCS, /* 23 */
+   INTEL_HWCONFIG_MAX_CCS, /* 24 */
+   INTEL_HWCONFIG_MAX_VCS, /* 25 */
+   INTEL_HWCONFIG_MAX_VECS,/* 26 */
+   INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
+   INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB,   /* 28 */
+   INTEL_HWCONFIG_MIN_VS_URB_ENTRIES,  /* 29 */
+   INTEL_HWCONFIG_MAX_VS_URB_ENTRIES,  /* 30 */
+   INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
+   INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
+   INTEL_HWCONFIG_MIN_HS_URB_ENTRIES,  /* 33 */
+   INTEL_HWCONFIG_MAX_HS_URB_ENTRIES,  /* 34 */
+   INTEL_HWCONFIG_MIN_GS_URB_ENTRIES,  /* 35 */
+   INTEL_HWCONFIG_MAX_GS_URB_ENTRIES,  /* 36 */
+   INTEL_HWCONFIG_MIN_DS_URB_ENTRIES,  /* 37 */
+   INTEL_HWCONFIG_MAX_DS_URB_ENTRIES,  /* 38 */
+   INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
+   INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE,/* 40 */
+   INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES,  /* 41 */
+   INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES,  /* 42 */
+   INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES,   /* 43 */
+   INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT,/* 44 */
+   INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT,/* 45 */
+   INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS,   /* 46 */
+   INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS,/* 47 */
+   INTEL_HWCONFIG_MIN_CS_URB_ENTRIES,  /* 48 */
+   INTEL_HWCONFIG_MAX_CS_URB_ENTRIES,  /* 49 */
+   INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB,   /* 50 */
+   INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST,  /* 51 */

Re: [Intel-gfx] [igt-dev] [PATCH v3 i-g-t 2/2] tests/i915/query: Query, parse and validate the hwconfig table

[Kamil Konieczny]

Hi John,

On 2022-06-02 at 17:54:04 -0700, john.c.harri...@intel.com wrote:
> From: Rodrigo Vivi 
> 
> Newer platforms have an embedded table giving details about that
> platform's hardware configuration. This table can be retrieved from
> the KMD via the existing query API. So add a test for it as both an
> example of how to fetch the table and to validate the contents as much
> as is possible.
> 
> Signed-off-by: Rodrigo Vivi 
> Signed-off-by: John Harrison 
> Cc: Slawomir Milczarek 
> Reviewed-by: Matthew Brost 
> ---
>  lib/intel_hwconfig_types.h | 118 
>  tests/i915/i915_query.c| 179 +
>  2 files changed, 297 insertions(+)
>  create mode 100644 lib/intel_hwconfig_types.h
> 
> diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
> new file mode 100644
> index ..d5db217afba2
> --- /dev/null
> +++ b/lib/intel_hwconfig_types.h
> @@ -0,0 +1,118 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef _INTEL_HWCONFIG_TYPES_H_
> +#define _INTEL_HWCONFIG_TYPES_H_
> +
> +#include "intel_chipset.h"
> +
> +/**
> + * enum intel_hwconfig - Global definition of hwconfig table attributes
> + *
> + * Intel devices provide a KLV (Key/Length/Value) table containing
> + * the static hardware configuration for that platform.
> + * This enum defines the current attribute keys for this KLV.
> + */
> +enum intel_hwconfig {
> + INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
> + INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED,/* 2 */
> + INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS,  /* 3 */
> + INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES,   /* 5 */
> + INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB,  /* 6 */
> + INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT,/* 7 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR,/* 9 */
> + INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
> + INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
> + INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
> + INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED,   /* 13 */
> + INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB,   /* 14 */
> + INTEL_HWCONFIG_NUM_THREADS_PER_EU,  /* 15 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS,/* 16 */
> + INTEL_HWCONFIG_TOTAL_GS_THREADS,/* 17 */
> + INTEL_HWCONFIG_TOTAL_HS_THREADS,/* 18 */
> + INTEL_HWCONFIG_TOTAL_DS_THREADS,/* 19 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS,   /* 20 */
> + INTEL_HWCONFIG_TOTAL_PS_THREADS,/* 21 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE,/* 22 */
> + INTEL_HWCONFIG_MAX_RCS, /* 23 */
> + INTEL_HWCONFIG_MAX_CCS, /* 24 */
> + INTEL_HWCONFIG_MAX_VCS, /* 25 */
> + INTEL_HWCONFIG_MAX_VECS,/* 26 */
> + INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
> + INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB,   /* 28 */
> + INTEL_HWCONFIG_MIN_VS_URB_ENTRIES,  /* 29 */
> + INTEL_HWCONFIG_MAX_VS_URB_ENTRIES,  /* 30 */
> + INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
> + INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
> + INTEL_HWCONFIG_MIN_HS_URB_ENTRIES,  /* 33 */
> + INTEL_HWCONFIG_MAX_HS_URB_ENTRIES,  /* 34 */
> + INTEL_HWCONFIG_MIN_GS_URB_ENTRIES,  /* 35 */
> + INTEL_HWCONFIG_MAX_GS_URB_ENTRIES,  /* 36 */
> + INTEL_HWCONFIG_MIN_DS_URB_ENTRIES,  /* 37 */
> + INTEL_HWCONFIG_MAX_DS_URB_ENTRIES,  /* 38 */
> + INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
> + INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE,/* 40 */
> + INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES,  /* 41 */
> + INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES,  /* 42 */
> + INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES,   /* 43 */
> + INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT,/* 44 */
> + INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT,/* 45 */
> + INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS,   /* 46 */
> + INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS,/* 47 */
> + INTEL_HWCONFIG_MIN_CS_URB_ENTRIES,  /* 48 */
> + INTEL_HWCONFIG_MAX_CS_URB_ENTRIES,

[Intel-gfx] ✗ Fi.CI.IGT: failure for Disable connector polling for a headless sku

[Patchwork]

== Series Details ==

Series: Disable connector polling for a headless sku
URL   : https://patchwork.freedesktop.org/series/104711/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11726_full -> Patchwork_104711v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_104711v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_104711v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_104711v1_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-tglb5/igt@gem_ctx_persiste...@many-contexts.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/shard-tglb5/igt@gem_ctx_persiste...@many-contexts.html

  * igt@gem_exec_suspend@basic-s4-devices@smem:
- shard-snb:  [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-snb2/igt@gem_exec_suspend@basic-s4-devi...@smem.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/shard-snb5/igt@gem_exec_suspend@basic-s4-devi...@smem.html

  * igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:
- shard-kbl:  [PASS][5] -> [FAIL][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-kbl6/igt@kms_hdr@bpc-switch-d...@pipe-a-dp-1.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/shard-kbl4/igt@kms_hdr@bpc-switch-d...@pipe-a-dp-1.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_flip@wf_vblank-ts-check@a-edp1:
- {shard-rkl}:NOTRUN -> [FAIL][7] +1 similar issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/shard-rkl-6/igt@kms_flip@wf_vblank-ts-ch...@a-edp1.html

  
Known issues


  Here are the changes found in Patchwork_104711v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@engines-hang@bcs0:
- shard-skl:  NOTRUN -> [SKIP][8] ([fdo#109271]) +111 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/shard-skl7/igt@gem_ctx_persistence@engines-h...@bcs0.html

  * igt@gem_ctx_persistence@idempotent:
- shard-snb:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/shard-snb4/igt@gem_ctx_persiste...@idempotent.html

  * igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][10] -> [TIMEOUT][11] ([i915#3070])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-iclb4/igt@gem_...@unwedge-stress.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/shard-iclb2/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][12] -> [SKIP][13] ([i915#4525])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-iclb1/igt@gem_exec_balan...@parallel-bb-first.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/shard-iclb3/igt@gem_exec_balan...@parallel-bb-first.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][14] ([i915#6141])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/shard-apl2/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar 
issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/shard-tglb2/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#2842]) +1 similar 
issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-iclb8/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/shard-iclb7/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_flush@basic-uc-ro-default:
- shard-snb:  [PASS][19] -> [SKIP][20] ([fdo#109271]) +2 similar 
issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-snb5/igt@gem_exec_fl...@basic-uc-ro-default.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/shard-snb6/igt@gem_exec_fl...@bas

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/pvc: Add register steering

[Matt Roper]

On Fri, Jun 03, 2022 at 03:50:38AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/pvc: Add register steering
> URL   : https://patchwork.freedesktop.org/series/104691/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_11724 -> Patchwork_104691v1
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_104691v1 absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_104691v1, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104691v1/index.html
> 
> Participating hosts (42 -> 39)
> --
> 
>   Additional (1): bat-adlm-1 
>   Missing(4): bat-dg2-8 fi-bdw-5557u bat-atsm-1 bat-dg2-9 
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_104691v1:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@gem_softpin@safe-alignment:
> - fi-bsw-n3050:   [PASS][1] -> [DMESG-WARN][2]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/fi-bsw-n3050/igt@gem_soft...@safe-alignment.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104691v1/fi-bsw-n3050/igt@gem_soft...@safe-alignment.html

Seems to be a GPF while releasing an object.  Would not be caused by this patch.

<4> [118.052900] general protection fault, probably for non-canonical address 
0x6b6b6b6b6b6b7c63:  [#1] PREEMPT SMP PTI
<4> [118.052935] CPU: 1 PID: 5108 Comm: gem_softpin Not tainted 
5.18.0-Patchwork_104691v1-gd85a4921e88b+ #1
<4> [118.052957] Hardware name:  /NUC5CPYB, BIOS 
PYBSWCEL.86A.0079.2020.0420.1316 04/20/2020
<4> [118.052973] RIP: 0010:__lock_acquire+0x612/0x2940
<4> [118.052993] Code: 88 09 00 00 83 f8 2f 0f 87 9c 00 00 00 3b 05 dd 55 0a 02 
41 bf 01 00 00 00 0f 86 cd 00 00 00 89 05 cb 55 0a 02 e9 c2 00 00 00 <48> 81 3f 
80 45 dc 82 41 bc 00 00 00 00 45 0f 45 e0 83 fe 01 0f 87
<4> [118.053026] RSP: 0018:c954bc88 EFLAGS: 00010002
<4> [118.053041] RAX:  RBX: 0001 RCX: 

<4> [118.053055] RDX:  RSI:  RDI: 
6b6b6b6b6b6b7c63
<4> [118.053070] RBP: 88811ba48040 R08: 0001 R09: 
0001
<4> [118.053084] R10: 0001 R11: ffa4eeb2 R12: 
0001
<4> [118.053098] R13:  R14:  R15: 
6b6b6b6b6b6b7c63
<4> [118.053113] FS:  7ff69c8d94c0() GS:88817b90() 
knlGS:
<4> [118.053130] CS:  0010 DS:  ES:  CR0: 80050033
<4> [118.053143] CR2: 7fffb2dc6fe8 CR3: 0001074a4000 CR4: 
001006e0
<4> [118.053157] Call Trace:
<4> [118.053165]  
<4> [118.053178]  lock_acquire+0xd3/0x310
<4> [118.053192]  ? release_references+0xb4/0x170 [i915]
<4> [118.053571]  ? _raw_spin_lock_irq+0x41/0x50
<4> [118.053588]  _raw_spin_lock_irq+0x32/0x50
<4> [118.053601]  ? release_references+0xb4/0x170 [i915]
<4> [118.053928]  release_references+0xb4/0x170 [i915]
<4> [118.054257]  __i915_gem_object_pages_fini+0x5c/0x200 [i915]
<4> [118.054575]  __i915_gem_free_objects+0x9a/0x150 [i915]
<4> [118.054894]  drm_file_free.part.14+0x1f5/0x240
<4> [118.054912]  drm_release_noglobal+0x16/0x60
<4> [118.054926]  __fput+0x96/0x250
<4> [118.054940]  task_work_run+0x6e/0xb0
<4> [118.054955]  exit_to_user_mode_prepare+0x19c/0x1b0
<4> [118.054970]  syscall_exit_to_user_mode+0x19/0x50
<4> [118.054986]  do_syscall_64+0x46/0x80
<4> [118.054998]  entry_SYSCALL_64_after_hwframe+0x44/0xae
<4> [118.055013] RIP: 0033:0x7ff69f0883d7


Matt

> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_104691v1 that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@i915_selftest@live@gem:
> - fi-pnv-d510:NOTRUN -> [DMESG-FAIL][3] ([i915#4528])
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104691v1/fi-pnv-d510/igt@i915_selftest@l...@gem.html
> 
>   * igt@i915_selftest@live@hangcheck:
> - bat-dg1-6:  NOTRUN -> [DMESG-FAIL][4] ([i915#4494] / 
> [i915#4957])
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104691v1/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
> 
>   * igt@i915_suspend@basic-s2idle-without-i915:
> - bat-dg1-6:  NOTRUN -> [INCOMPLETE][5] ([i915#6011])
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104691v1/bat-dg1-6/igt@i915_susp...@basic-s2idle-without-i915.html
> 
>   * igt@kms_chamelium@common-hpd-after-suspend:
> - fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104691v1/fi-hsw-4770/igt@kms_chamel.

[Intel-gfx] ✓ Fi.CI.IGT: success for Fixes integer overflow or integer truncation issues in page lookups, ttm place configuration and scatterlist creation (rev2)

[Patchwork]

== Series Details ==

Series: Fixes integer overflow or integer truncation issues in page lookups, 
ttm place configuration and scatterlist creation (rev2)
URL   : https://patchwork.freedesktop.org/series/104704/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11726_full -> Patchwork_104704v2_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_104704v2_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_properties@crtc-properties-legacy:
- {shard-rkl}:[PASS][1] -> [SKIP][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-rkl-6/igt@kms_propert...@crtc-properties-legacy.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/shard-rkl-6/igt@kms_propert...@crtc-properties-legacy.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- {shard-rkl}:[SKIP][3] ([i915#2920]) -> [FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-rkl-6/igt@kms_psr2...@overlay-primary-update-sf-dmg-area.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/shard-rkl-6/igt@kms_psr2...@overlay-primary-update-sf-dmg-area.html

  * igt@prime_self_import@reimport-vs-gem_close-race:
- {shard-rkl}:[PASS][5] -> [FAIL][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-rkl-1/igt@prime_self_import@reimport-vs-gem_close-race.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/shard-rkl-5/igt@prime_self_import@reimport-vs-gem_close-race.html

  
Known issues


  Here are the changes found in Patchwork_104704v2_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@engines-hang@bcs0:
- shard-skl:  NOTRUN -> [SKIP][7] ([fdo#109271]) +196 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/shard-skl9/igt@gem_ctx_persistence@engines-h...@bcs0.html

  * igt@gem_ctx_persistence@legacy-engines-mixed-process:
- shard-snb:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) +1 
similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-mixed-process.html

  * igt@gem_eio@kms:
- shard-tglb: NOTRUN -> [FAIL][9] ([i915#5784])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/shard-tglb2/igt@gem_...@kms.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][10] -> [SKIP][11] ([i915#4525]) +1 similar 
issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-iclb1/igt@gem_exec_balan...@parallel-keep-in-fence.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/shard-iclb8/igt@gem_exec_balan...@parallel-keep-in-fence.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][12] ([i915#6141])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/shard-apl4/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-kbl:  NOTRUN -> [FAIL][13] ([i915#2842]) +2 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-tglb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/shard-tglb6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2842]) +1 similar 
issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-iclb8/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/shard-iclb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl:  [PASS][18] -> [FAIL][19] ([i915#2842])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/shard-kbl1/igt@gem_exec_fair@basic-p...@vecs0.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  NOTRUN -> [FAIL][20] ([i915#2842])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html
- shard-iclb: NOTRU

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pvc: GuC depriv applies to PVC

[Matt Roper]

On Fri, Jun 03, 2022 at 03:54:36AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/pvc: GuC depriv applies to PVC
> URL   : https://patchwork.freedesktop.org/series/104688/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_11723_full -> Patchwork_104688v1_full
> 
> 
> Summary
> ---
> 
>   **SUCCESS**
> 
>   No regressions found.

Applied to drm-intel-gt-next.  Thanks Jose for the review.


Matt

> 
>   
> 
> Participating hosts (13 -> 13)
> --
> 
>   No changes in participating hosts
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_104688v1_full:
> 
> ### IGT changes ###
> 
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * 
> igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1:
> - {shard-rkl}:NOTRUN -> [SKIP][1] +1 similar issue
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104688v1/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-...@pipe-a-edp-1.html
> 
>   * igt@kms_setmode@basic@pipe-a-edp-1:
> - {shard-rkl}:NOTRUN -> [FAIL][2] +1 similar issue
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104688v1/shard-rkl-6/igt@kms_setmode@ba...@pipe-a-edp-1.html
> 
>   
> New tests
> -
> 
>   New tests have been introduced between CI_DRM_11723_full and 
> Patchwork_104688v1_full:
> 
> ### New IGT tests (1) ###
> 
>   * igt@kms_atomic_interruptible@legacy-setmode@hdmi-a-3-pipe-a:
> - Statuses : 1 pass(s)
> - Exec time: [6.14] s
> 
>   
> 
> Known issues
> 
> 
>   Here are the changes found in Patchwork_104688v1_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@gem_ctx_isolation@preservation-s3@vcs0:
> - shard-kbl:  [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +7 
> similar issues
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11723/shard-kbl1/igt@gem_ctx_isolation@preservation...@vcs0.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104688v1/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html
> 
>   * igt@gem_exec_balancer@parallel-contexts:
> - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525])
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11723/shard-iclb2/igt@gem_exec_balan...@parallel-contexts.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104688v1/shard-iclb6/igt@gem_exec_balan...@parallel-contexts.html
> 
>   * igt@gem_exec_endless@dispatch@vcs0:
> - shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([i915#3778])
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11723/shard-tglb1/igt@gem_exec_endless@dispa...@vcs0.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104688v1/shard-tglb5/igt@gem_exec_endless@dispa...@vcs0.html
> 
>   * igt@gem_exec_fair@basic-none-solo@rcs0:
> - shard-apl:  [PASS][9] -> [FAIL][10] ([i915#2842])
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11723/shard-apl8/igt@gem_exec_fair@basic-none-s...@rcs0.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104688v1/shard-apl2/igt@gem_exec_fair@basic-none-s...@rcs0.html
> 
>   * igt@gem_exec_fair@basic-pace-solo@rcs0:
> - shard-kbl:  [PASS][11] -> [FAIL][12] ([i915#2842]) +2 similar 
> issues
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11723/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104688v1/shard-kbl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
> 
>   * igt@gem_lmem_swapping@parallel-random:
> - shard-skl:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613])
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104688v1/shard-skl10/igt@gem_lmem_swapp...@parallel-random.html
> 
>   * igt@gem_lmem_swapping@parallel-random-verify-ccs:
> - shard-kbl:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613])
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104688v1/shard-kbl7/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html
> 
>   * igt@gem_lmem_swapping@verify-random:
> - shard-apl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) 
> +1 similar issue
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104688v1/shard-apl4/igt@gem_lmem_swapp...@verify-random.html
> 
>   * igt@gem_pread@exhaustion:
> - shard-kbl:  NOTRUN -> [WARN][16] ([i915#2658])
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104688v1/shard-kbl7/igt@gem_pr...@exhaustion.html
> 
>   * igt@i915_pm_dc@dc3co-vpb-simulation:
> - shard-apl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#658])
>[17]: 

Re: [Intel-gfx] [PATCH] drm/i915/pvc: GuC depriv applies to PVC

[Souza, Jose]

On Thu, 2022-06-02 at 16:30 -0700, Matt Roper wrote:
> We missed this setting in the initial device info patch's definition of
> XE_HPC_FEATURES.

Reviewed-by: José Roberto de Souza 

> 
> Signed-off-by: Matt Roper 
> ---
>  drivers/gpu/drm/i915/i915_pci.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 047a6e326031..a5a1a7647320 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1089,6 +1089,7 @@ static const struct intel_device_info ats_m_info = {
>   XE_HP_FEATURES, \
>   .dma_mask_size = 52, \
>   .has_3d_pipeline = 0, \
> + .has_guc_deprivilege = 1, \
>   .has_l3_ccs_read = 1, \
>   .has_one_eu_per_fuse_bit = 1
>  

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: i915_drv.h & i915_gem.h header refactoring

[Patchwork]

== Series Details ==

Series: drm/i915: i915_drv.h & i915_gem.h header refactoring
URL   : https://patchwork.freedesktop.org/series/104725/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: i915_drv.h & i915_gem.h header refactoring

[Patchwork]

== Series Details ==

Series: drm/i915: i915_drv.h & i915_gem.h header refactoring
URL   : https://patchwork.freedesktop.org/series/104725/
State : warning

== Summary ==

Error: dim checkpatch failed
a53c0ec4baf9 drm/i915/tasklet: separate local hacks around struct tasklet_struct
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 10, in 
import git
ModuleNotFoundError: No module named 'git'
-:86: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#86: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 99 lines checked
36fc7e4e5220 drm/i915/debug: add new i915_debug.h for debug asserts
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 10, in 
import git
ModuleNotFoundError: No module named 'git'
-:217: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#217: 
new file mode 100644

-:240: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & 
recovery code rather than BUG() or BUG_ON()
#240: FILE: drivers/gpu/drm/i915/i915_debug.h:19:
+#define __GEM_BUG(cond) BUG()

-:246: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'condition' - possible 
side-effects?
#246: FILE: drivers/gpu/drm/i915/i915_debug.h:25:
+#define GEM_BUG_ON(condition) do { if (unlikely((condition))) {\
+   GEM_TRACE_ERR("%s:%d GEM_BUG_ON(%s)\n", \
+ __func__, __LINE__, __stringify(condition)); \
+   GEM_TRACE_DUMP(); \
+   __GEM_BUG(condition); \
+   } \
+   } while(0)

-:252: ERROR:SPACING: space required before the open parenthesis '('
#252: FILE: drivers/gpu/drm/i915/i915_debug.h:31:
+   } while(0)

-:268: WARNING:TRACE_PRINTK: Do not use trace_printk() in production code (this 
can be ignored if built only with a debug config option)
#268: FILE: drivers/gpu/drm/i915/i915_debug.h:47:
+#define GEM_TRACE(...) trace_printk(__VA_ARGS__)

-:271: WARNING:TRACE_PRINTK: Do not use trace_printk() in production code (this 
can be ignored if built only with a debug config option)
#271: FILE: drivers/gpu/drm/i915/i915_debug.h:50:
+   trace_printk(__VA_ARGS__);  \

total: 1 errors, 4 warnings, 1 checks, 324 lines checked
0e80aecf3ea3 drm/i915: un-inline i915_gem_drain_* functions
-:100: WARNING:LINE_SPACING: Missing a blank line after declarations
#100: FILE: drivers/gpu/drm/i915/i915_gem.c:1118:
+   int pass = 3;
+   do {

total: 0 errors, 1 warnings, 0 checks, 89 lines checked
2eba81a7f23c drm/i915/gem: split out the gem stuff from i915_drv.h
7f30c36d225f drm/i915/drv: drop intel_bios.h include
7add9ee46d1c drm/i915/client: only include what's needed
994605eb20fd drm/i915/utils: throw out unused stuff

Re: [Intel-gfx] [PATCH 0/6] Fixes integer overflow or integer truncation issues in page lookups, ttm place configuration and scatterlist creation

[Jani Nikula]

On Fri, 03 Jun 2022, Gwan-gyeong Mun  wrote:
> This patch series fixes integer overflow or integer truncation issues in
> page lookups, ttm place configuration and scatterlist creation, etc.
> We need to check that we avoid integer overflows when looking up a page,
> and so fix all the instances where we have mistakenly used a plain integer
> instead of a more suitable long.

So when are we going to start moving the helpers, both existing and the
ones being added here, from i915_utils.h to proper kernel headers? We
just keep adding more and more. This needs to stop.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 1/2] drm/i915/opregion: add function to check if headless sku

[Hogander, Jouni]

On Fri, 2022-06-03 at 15:43 +0300, Jani Nikula wrote:
> On Fri, 03 Jun 2022, Jouni Högander  wrote:
> > Export headless sku bit (bit 13) from opregion->header->pcon as an
> > interface to check if our device is headless configuration.
> > 
> > Bspec: 53441
> > Signed-off-by: Jouni Högander 
> > ---
> >  drivers/gpu/drm/i915/display/intel_opregion.c | 12 
> >  drivers/gpu/drm/i915/display/intel_opregion.h |  7 +++
> >  2 files changed, 19 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
> > b/drivers/gpu/drm/i915/display/intel_opregion.c
> > index f31e8c3f8ce0..eab3f2e6b786 100644
> > --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> > +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> > @@ -53,6 +53,8 @@
> >  #define MBOX_ASLE_EXT  BIT(4)  /* Mailbox #5 */
> >  #define MBOX_BACKLIGHT BIT(5)  /* Mailbox #2
> > (valid from v3.x) */
> >  
> > +#define PCON_HEADLESS_SKU  BIT(13)
> 
> Here we go again.
> 
> What does headless mean here? The spec does not say. Does it have
> display hardware? Apparently yes, since otherwise we wouldn't be
> here.

This is for hybrid setup with several display hw and the panel wont be
connected into device driven by i915 driver.

> We have INTEL_DISPLAY_ENABLED() which should do the right thing when
> you
> do have display hardware and have done output setup etc. but want to
> force them disconnected, i.e. you take the hardware over properly,
> but
> put it to sleep for power savings.
> 
> Maybe we should bolt this opregion check in that macro?
> 
> Maybe we need to use INTEL_DISPLAY_ENABLED() also to prevent polling.

Thank you for pointing this out. HAS_DISPLAY I already notice and it's
not suitable for what we want here. I think bolting this check into
INTEL_DISPLAY_ENABLED as you suggested is enough. That will prevent
waking up the hw into D0 state for polling.

> 
> I certainly would not want to add another mode that's separate from
> HAS_DISPLAY() and INTEL_DISPLAY_ENABLED().

No need for this. I think we can go with INTEL_DISPLAY_ENABLED.
> 
> > +
> >  struct opregion_header {
> > u8 signature[16];
> > u32 size;
> > @@ -1135,6 +1137,16 @@ struct edid *intel_opregion_get_edid(struct
> > intel_connector *intel_connector)
> > return new_edid;
> >  }
> >  
> > +bool intel_opregion_headless_sku(struct drm_i915_private *i915)
> > +{
> > +   struct intel_opregion *opregion = &i915->opregion;
> > +
> > +   if (!opregion->header)
> > +   return false;
> > +
> > +   return opregion->header->pcon & PCON_HEADLESS_SKU;
> 
> We should probably start checking for opregion version for this stuff
> too.
> 

Yes, I will do this change.

> 
> BR,
> Jani.
> 
> > +}
> > +
> >  void intel_opregion_register(struct drm_i915_private *i915)
> >  {
> > struct intel_opregion *opregion = &i915->opregion;
> > diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h
> > b/drivers/gpu/drm/i915/display/intel_opregion.h
> > index 82cc0ba34af7..5ad96e1d8278 100644
> > --- a/drivers/gpu/drm/i915/display/intel_opregion.h
> > +++ b/drivers/gpu/drm/i915/display/intel_opregion.h
> > @@ -76,6 +76,8 @@ int intel_opregion_notify_adapter(struct
> > drm_i915_private *dev_priv,
> >  int intel_opregion_get_panel_type(struct drm_i915_private
> > *dev_priv);
> >  struct edid *intel_opregion_get_edid(struct intel_connector
> > *connector);
> >  
> > +bool intel_opregion_headless_sku(struct drm_i915_private *i915);
> > +
> >  #else /* CONFIG_ACPI*/
> >  
> >  static inline int intel_opregion_setup(struct drm_i915_private
> > *dev_priv)
> > @@ -127,6 +129,11 @@ intel_opregion_get_edid(struct intel_connector
> > *connector)
> > return NULL;
> >  }
> >  
> > +bool intel_opregion_headless_sku(struct drm_i915_private *i915)
> > +{
> > +   return false;
> > +}
> > +
> >  #endif /* CONFIG_ACPI */
> >  
> >  #endif

[Intel-gfx] [PATCH 3/7] drm/i915: un-inline i915_gem_drain_* functions

[Jani Nikula]

As best I can tell these aren't used in the kind of hotpaths that
mandate using static inline. They do make header cleanup harder, though,
so un-inline.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/i915_drv.h | 39 ++---
 drivers/gpu/drm/i915/i915_gem.c | 38 
 2 files changed, 40 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5d4607535f2a..c3b2cbf8bfb7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1364,43 +1364,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 void i915_gem_init_early(struct drm_i915_private *dev_priv);
 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
 
-static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
-{
-   /*
-* A single pass should suffice to release all the freed objects (along
-* most call paths) , but be a little more paranoid in that freeing
-* the objects does take a little amount of time, during which the rcu
-* callbacks could have added new objects into the freed list, and
-* armed the work again.
-*/
-   while (atomic_read(&i915->mm.free_count)) {
-   flush_delayed_work(&i915->mm.free_work);
-   flush_delayed_work(&i915->bdev.wq);
-   rcu_barrier();
-   }
-}
-
-static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
-{
-   /*
-* Similar to objects above (see i915_gem_drain_freed-objects), in
-* general we have workers that are armed by RCU and then rearm
-* themselves in their callbacks. To be paranoid, we need to
-* drain the workqueue a second time after waiting for the RCU
-* grace period so that we catch work queued via RCU from the first
-* pass. As neither drain_workqueue() nor flush_workqueue() report
-* a result, we make an assumption that we only don't require more
-* than 3 passes to catch all _recursive_ RCU delayed work.
-*
-*/
-   int pass = 3;
-   do {
-   flush_workqueue(i915->wq);
-   rcu_barrier();
-   i915_gem_drain_freed_objects(i915);
-   } while (--pass);
-   drain_workqueue(i915->wq);
-}
+void i915_gem_drain_freed_objects(struct drm_i915_private *i915);
+void i915_gem_drain_workqueue(struct drm_i915_private *i915);
 
 struct i915_vma * __must_check
 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 702e5b89be22..5a6bd2547f04 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1085,6 +1085,44 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void 
*data,
return err;
 }
 
+void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
+{
+   /*
+* A single pass should suffice to release all the freed objects (along
+* most call paths) , but be a little more paranoid in that freeing
+* the objects does take a little amount of time, during which the rcu
+* callbacks could have added new objects into the freed list, and
+* armed the work again.
+*/
+   while (atomic_read(&i915->mm.free_count)) {
+   flush_delayed_work(&i915->mm.free_work);
+   flush_delayed_work(&i915->bdev.wq);
+   rcu_barrier();
+   }
+}
+
+void i915_gem_drain_workqueue(struct drm_i915_private *i915)
+{
+   /*
+* Similar to objects above (see i915_gem_drain_freed-objects), in
+* general we have workers that are armed by RCU and then rearm
+* themselves in their callbacks. To be paranoid, we need to
+* drain the workqueue a second time after waiting for the RCU
+* grace period so that we catch work queued via RCU from the first
+* pass. As neither drain_workqueue() nor flush_workqueue() report
+* a result, we make an assumption that we only don't require more
+* than 3 passes to catch all _recursive_ RCU delayed work.
+*
+*/
+   int pass = 3;
+   do {
+   flush_workqueue(i915->wq);
+   rcu_barrier();
+   i915_gem_drain_freed_objects(i915);
+   } while (--pass);
+   drain_workqueue(i915->wq);
+}
+
 int i915_gem_init(struct drm_i915_private *dev_priv)
 {
int ret;
-- 
2.30.2

[Intel-gfx] [PATCH 4/7] drm/i915/gem: split out the gem stuff from i915_drv.h

[Jani Nikula]

Turn i915_gem.h into a useful header for declaring the functions in
i915_gem.c.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_dpt.c  |  1 +
 drivers/gpu/drm/i915/display/intel_dsb.c  |  1 +
 drivers/gpu/drm/i915/display/intel_overlay.c  |  1 +
 drivers/gpu/drm/i915/gem/i915_gem_domain.c|  1 +
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c|  1 +
 drivers/gpu/drm/i915/gem/i915_gem_mman.c  |  5 ++-
 drivers/gpu/drm/i915/gem/i915_gem_object.c|  1 +
 drivers/gpu/drm/i915/gem/i915_gem_phys.c  |  1 +
 drivers/gpu/drm/i915/gem/i915_gem_pm.c|  1 +
 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c  |  1 +
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c  |  1 +
 drivers/gpu/drm/i915/gem/i915_gem_userptr.c   |  1 +
 .../i915/gem/selftests/i915_gem_coherency.c   |  1 +
 .../drm/i915/gem/selftests/i915_gem_context.c |  1 +
 .../drm/i915/gem/selftests/i915_gem_mman.c|  1 +
 drivers/gpu/drm/i915/gt/intel_ggtt.c  | 10 ++---
 drivers/gpu/drm/i915/gt/selftest_migrate.c|  2 +
 drivers/gpu/drm/i915/gt/selftest_timeline.c   |  1 +
 drivers/gpu/drm/i915/gvt/scheduler.c  |  1 +
 drivers/gpu/drm/i915/i915_debugfs.c   |  1 +
 drivers/gpu/drm/i915/i915_driver.c|  3 +-
 drivers/gpu/drm/i915/i915_drv.h   | 38 
 drivers/gpu/drm/i915/i915_gem.c   |  1 +
 drivers/gpu/drm/i915/i915_gem.h   | 44 +++
 drivers/gpu/drm/i915/i915_perf.c  |  1 +
 drivers/gpu/drm/i915/intel_gvt.c  |  1 +
 .../gpu/drm/i915/selftests/i915_gem_evict.c   |  2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 +-
 .../gpu/drm/i915/selftests/i915_selftest.c|  1 +
 drivers/gpu/drm/i915/selftests/i915_vma.c |  2 +-
 .../drm/i915/selftests/intel_memory_region.c  |  1 +
 31 files changed, 82 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c 
b/drivers/gpu/drm/i915/display/intel_dpt.c
index fb0e7e79e0cd..9f374c964549 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -7,6 +7,7 @@
 #include "gt/gen8_ppgtt.h"
 
 #include "i915_drv.h"
+#include "i915_gem.h"
 #include "intel_display_types.h"
 #include "intel_dpt.h"
 #include "intel_fb.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c 
b/drivers/gpu/drm/i915/display/intel_dsb.c
index c4affcb216fd..b48fb10efb39 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -7,6 +7,7 @@
 #include "gem/i915_gem_internal.h"
 
 #include "i915_drv.h"
+#include "i915_gem.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
 
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c 
b/drivers/gpu/drm/i915/display/intel_overlay.c
index ee46561b5ae8..dab4cd42c91b 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -34,6 +34,7 @@
 #include "gt/intel_ring.h"
 
 #include "i915_drv.h"
+#include "i915_gem.h"
 #include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c 
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 3e5d6057b3ef..68d96fefb91b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -8,6 +8,7 @@
 #include "gt/intel_gt.h"
 
 #include "i915_drv.h"
+#include "i915_gem.h"
 #include "i915_gem_clflush.h"
 #include "i915_gem_domain.h"
 #include "i915_gem_gtt.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 30fe847c6664..eb7ed00bf9f6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -27,6 +27,7 @@
 #include "i915_cmd_parser.h"
 #include "i915_drv.h"
 #include "i915_file_private.h"
+#include "i915_gem.h"
 #include "i915_gem_clflush.h"
 #include "i915_gem_context.h"
 #include "i915_gem_evict.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c 
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 0c5c43852e24..ef36d1f72724 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -15,15 +15,16 @@
 #include "gt/intel_gt_requests.h"
 
 #include "i915_drv.h"
+#include "i915_gem.h"
 #include "i915_gem_evict.h"
 #include "i915_gem_gtt.h"
 #include "i915_gem_ioctls.h"
-#include "i915_gem_object.h"
 #include "i915_gem_mman.h"
+#include "i915_gem_object.h"
+#include "i915_gem_ttm.h"
 #include "i915_mm.h"
 #include "i915_trace.h"
 #include "i915_user_extensions.h"
-#include "i915_gem_ttm.h"
 #include "i915_vma.h"
 
 static inline bool
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 06b1b188ce5a..1a34a8057ab3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -32,6 +32,7 @@
 
 #include "i915_drv.h"
 #include "i915_file_private.h"
+

[Intel-gfx] [PATCH 2/7] drm/i915/debug: add new i915_debug.h for debug asserts

[Jani Nikula]

Move the various GEM_BUG_ON(), GEM_WARN_ON(), etc. debug macros to a
dedicated i915_debug.h file.

Unfortunately, the i915_debug.h needs to be included from some headers
that get included from i915_drv.h, so we don't really get much build
benefits here, other than getting rid of superfluous i915_gem.h
includes.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.h   |  1 -
 drivers/gpu/drm/i915/gem/i915_gem_internal.c  |  1 -
 drivers/gpu/drm/i915/gem/i915_gem_object.h|  5 +-
 drivers/gpu/drm/i915/gem/i915_gem_tiling.c|  1 -
 drivers/gpu/drm/i915/gt/gen8_engine_cs.h  |  2 +-
 drivers/gpu/drm/i915/gt/intel_engine_stats.h  |  2 +-
 drivers/gpu/drm/i915/gt/intel_engine_types.h  |  1 -
 drivers/gpu/drm/i915/gt/intel_gt.c|  1 +
 drivers/gpu/drm/i915/gt/intel_gt_sysfs.h  |  2 -
 drivers/gpu/drm/i915/gt/intel_renderstate.h   |  2 +-
 drivers/gpu/drm/i915/gt/intel_ring.h  |  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.h  |  5 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |  2 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.h|  1 -
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  |  1 -
 drivers/gpu/drm/i915/i915_debug.h | 63 +++
 drivers/gpu/drm/i915/i915_drm_client.c|  1 -
 drivers/gpu/drm/i915/i915_drv.h   |  1 -
 drivers/gpu/drm/i915/i915_gem.h   | 57 -
 drivers/gpu/drm/i915/i915_gpu_error.h |  1 -
 drivers/gpu/drm/i915/i915_ioctl.c |  1 -
 drivers/gpu/drm/i915/i915_request.h   |  1 -
 drivers/gpu/drm/i915/i915_scatterlist.h   |  2 +-
 drivers/gpu/drm/i915/i915_syncmap.c   |  5 +-
 drivers/gpu/drm/i915/i915_ttm_buddy_manager.c |  3 +-
 drivers/gpu/drm/i915/i915_vma_resource.h  |  1 -
 26 files changed, 80 insertions(+), 85 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_debug.h

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h 
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index e5b0f66ea1fe..0529bbf5f51c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -12,7 +12,6 @@
 #include "gt/intel_context.h"
 
 #include "i915_drv.h"
-#include "i915_gem.h"
 #include "i915_scheduler.h"
 #include "intel_device_info.h"
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c 
b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index c698f95af15f..9f4050933d6e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -9,7 +9,6 @@
 #include 
 
 #include "i915_drv.h"
-#include "i915_gem.h"
 #include "i915_gem_internal.h"
 #include "i915_gem_object.h"
 #include "i915_scatterlist.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index e11d82a9f7c3..9308f3ab9c98 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -12,11 +12,12 @@
 #include 
 
 #include "display/intel_frontbuffer.h"
-#include "intel_memory_region.h"
-#include "i915_gem_object_types.h"
+#include "i915_debug.h"
 #include "i915_gem_gtt.h"
+#include "i915_gem_object_types.h"
 #include "i915_gem_ww.h"
 #include "i915_vma_types.h"
+#include "intel_memory_region.h"
 
 enum intel_region_id;
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c 
b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index 80ac0db1ae8c..ef8767f3d432 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -8,7 +8,6 @@
 #include 
 
 #include "i915_drv.h"
-#include "i915_gem.h"
 #include "i915_gem_ioctls.h"
 #include "i915_gem_mman.h"
 #include "i915_gem_object.h"
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
index 32e3d2b831bb..1e693f1a924b 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
@@ -9,7 +9,7 @@
 #include 
 #include 
 
-#include "i915_gem.h" /* GEM_BUG_ON */
+#include "i915_debug.h"
 #include "intel_gt_regs.h"
 #include "intel_gpu_commands.h"
 
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_stats.h 
b/drivers/gpu/drm/i915/gt/intel_engine_stats.h
index 8e762d683e50..c7673af7bc01 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_stats.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_stats.h
@@ -10,7 +10,7 @@
 #include 
 #include 
 
-#include "i915_gem.h" /* GEM_BUG_ON */
+#include "i915_debug.h"
 #include "intel_engine.h"
 
 static inline void intel_engine_context_in(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h 
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 2286f96f5f87..5f6334bd6f41 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -17,7 +17,6 @@
 #include 
 #include 
 
-#include "i915_gem.h"
 #include "i915_pmu.h"
 #include "i915_priolist_types.h"
 #include "i915_selftest.h"
diff --git a/drivers/gpu/drm/i

[Intel-gfx] [PATCH 1/7] drm/i915/tasklet: separate local hacks around struct tasklet_struct

[Jani Nikula]

Add a dedicated file for the local functions around struct
tasklet_struct. Far from ideal, but better placed in a dedicated file
than i915_gem.h.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/TODO.txt |  2 +-
 drivers/gpu/drm/i915/i915_gem.h   | 33 
 drivers/gpu/drm/i915/i915_scheduler.h |  1 +
 drivers/gpu/drm/i915/i915_tasklet.h   | 43 +++
 4 files changed, 45 insertions(+), 34 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_tasklet.h

diff --git a/drivers/gpu/drm/i915/TODO.txt b/drivers/gpu/drm/i915/TODO.txt
index 81a82c9c203f..879b08ca32b3 100644
--- a/drivers/gpu/drm/i915/TODO.txt
+++ b/drivers/gpu/drm/i915/TODO.txt
@@ -37,5 +37,5 @@ Smaller things:
 
   https://lore.kernel.org/linux-mm/20210301083320.943079-1-...@lst.de/
 
-- tasklet helpers in i915_gem.h also look a bit misplaced and should
+- tasklet helpers in i915_tasklet.h also look a bit misplaced and should
   probably be moved to tasklet headers.
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index a2be323a4be5..68d8d52bd541 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -26,7 +26,6 @@
 #define __I915_GEM_H__
 
 #include 
-#include 
 
 #include 
 
@@ -85,36 +84,4 @@ struct drm_i915_private;
 
 #define I915_GEM_IDLE_TIMEOUT (HZ / 5)
 
-static inline void tasklet_lock(struct tasklet_struct *t)
-{
-   while (!tasklet_trylock(t))
-   cpu_relax();
-}
-
-static inline bool tasklet_is_locked(const struct tasklet_struct *t)
-{
-   return test_bit(TASKLET_STATE_RUN, &t->state);
-}
-
-static inline void __tasklet_disable_sync_once(struct tasklet_struct *t)
-{
-   if (!atomic_fetch_inc(&t->count))
-   tasklet_unlock_spin_wait(t);
-}
-
-static inline bool __tasklet_is_enabled(const struct tasklet_struct *t)
-{
-   return !atomic_read(&t->count);
-}
-
-static inline bool __tasklet_enable(struct tasklet_struct *t)
-{
-   return atomic_dec_and_test(&t->count);
-}
-
-static inline bool __tasklet_is_scheduled(struct tasklet_struct *t)
-{
-   return test_bit(TASKLET_STATE_SCHED, &t->state);
-}
-
 #endif /* __I915_GEM_H__ */
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h 
b/drivers/gpu/drm/i915/i915_scheduler.h
index 0b9b86af6c7f..c229c91071d7 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -12,6 +12,7 @@
 #include 
 
 #include "i915_scheduler_types.h"
+#include "i915_tasklet.h"
 
 struct drm_printer;
 
diff --git a/drivers/gpu/drm/i915/i915_tasklet.h 
b/drivers/gpu/drm/i915/i915_tasklet.h
new file mode 100644
index ..5d7069bdf2c0
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_tasklet.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __I915_TASKLET_H__
+#define __I915_TASKLET_H__
+
+#include 
+
+static inline void tasklet_lock(struct tasklet_struct *t)
+{
+   while (!tasklet_trylock(t))
+   cpu_relax();
+}
+
+static inline bool tasklet_is_locked(const struct tasklet_struct *t)
+{
+   return test_bit(TASKLET_STATE_RUN, &t->state);
+}
+
+static inline void __tasklet_disable_sync_once(struct tasklet_struct *t)
+{
+   if (!atomic_fetch_inc(&t->count))
+   tasklet_unlock_spin_wait(t);
+}
+
+static inline bool __tasklet_is_enabled(const struct tasklet_struct *t)
+{
+   return !atomic_read(&t->count);
+}
+
+static inline bool __tasklet_enable(struct tasklet_struct *t)
+{
+   return atomic_dec_and_test(&t->count);
+}
+
+static inline bool __tasklet_is_scheduled(struct tasklet_struct *t)
+{
+   return test_bit(TASKLET_STATE_SCHED, &t->state);
+}
+
+#endif /* __I915_TASKLET_H__ */
-- 
2.30.2

[Intel-gfx] [PATCH 7/7] drm/i915/utils: throw out unused stuff

[Jani Nikula]

Remove some of the unused helpers from i915_utils.h.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/i915_utils.h | 40 ---
 1 file changed, 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_utils.h 
b/drivers/gpu/drm/i915/i915_utils.h
index ea7648e3aa0e..c10d68cdc3ca 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -115,39 +115,6 @@ bool i915_error_injected(void);
 #define overflows_type(x, T) \
(sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T))
 
-static inline bool
-__check_struct_size(size_t base, size_t arr, size_t count, size_t *size)
-{
-   size_t sz;
-
-   if (check_mul_overflow(count, arr, &sz))
-   return false;
-
-   if (check_add_overflow(sz, base, &sz))
-   return false;
-
-   *size = sz;
-   return true;
-}
-
-/**
- * check_struct_size() - Calculate size of structure with trailing array.
- * @p: Pointer to the structure.
- * @member: Name of the array member.
- * @n: Number of elements in the array.
- * @sz: Total size of structure and array
- *
- * Calculates size of memory needed for structure @p followed by an
- * array of @n @member elements, like struct_size() but reports
- * whether it overflowed, and the resultant size in @sz
- *
- * Return: false if the calculation overflowed.
- */
-#define check_struct_size(p, member, n, sz) \
-   likely(__check_struct_size(sizeof(*(p)), \
-  sizeof(*(p)->member) + 
__must_be_array((p)->member), \
-  n, sz))
-
 #define ptr_mask_bits(ptr, n) ({   \
unsigned long __v = (unsigned long)(ptr);   \
(typeof(ptr))(__v & -BIT(n));   \
@@ -184,8 +151,6 @@ __check_struct_size(size_t base, size_t arr, size_t count, 
size_t *size)
 
 #define struct_member(T, member) (((T *)0)->member)
 
-#define ptr_offset(ptr, member) offsetof(typeof(*(ptr)), member)
-
 #define fetch_and_zero(ptr) ({ \
typeof(*ptr) __T = *(ptr);  \
*(ptr) = (typeof(*ptr))0;   \
@@ -228,11 +193,6 @@ static __always_inline ptrdiff_t ptrdiff(const void *a, 
const void *b)
get_user(mbz__, (U)) ? -EFAULT : mbz__ ? -EINVAL : 0;   \
 })
 
-static inline u64 ptr_to_u64(const void *ptr)
-{
-   return (uintptr_t)ptr;
-}
-
 #define u64_to_ptr(T, x) ({\
typecheck(u64, x);  \
(T *)(uintptr_t)(x);\
-- 
2.30.2

[Intel-gfx] [PATCH 6/7] drm/i915/client: only include what's needed

[Jani Nikula]

Only the uapi header is required.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/i915_drm_client.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drm_client.h 
b/drivers/gpu/drm/i915/i915_drm_client.h
index f796c5e8e060..69496af996d9 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.h
+++ b/drivers/gpu/drm/i915/i915_drm_client.h
@@ -11,7 +11,7 @@
 #include 
 #include 
 
-#include "gt/intel_engine_types.h"
+#include 
 
 #define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE
 
-- 
2.30.2

[Intel-gfx] [PATCH 5/7] drm/i915/drv: drop intel_bios.h include

[Jani Nikula]

No longer needed after panel data was moved.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/i915_drv.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fa8f208c8939..5093fe824789 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -37,7 +37,6 @@
 #include 
 #include 
 
-#include "display/intel_bios.h"
 #include "display/intel_cdclk.h"
 #include "display/intel_display.h"
 #include "display/intel_display_power.h"
-- 
2.30.2

[Intel-gfx] [PATCH 0/7] drm/i915: i915_drv.h & i915_gem.h header refactoring

[Jani Nikula]

Turn i915_gem.h into a useful header that contains stuff the name
implies, and clean up i915_drv.h a bit.

Jani Nikula (7):
  drm/i915/tasklet: separate local hacks around struct tasklet_struct
  drm/i915/debug: add new i915_debug.h for debug asserts
  drm/i915: un-inline i915_gem_drain_* functions
  drm/i915/gem: split out the gem stuff from i915_drv.h
  drm/i915/drv: drop intel_bios.h include
  drm/i915/client: only include what's needed
  drm/i915/utils: throw out unused stuff

 drivers/gpu/drm/i915/TODO.txt |   2 +-
 drivers/gpu/drm/i915/display/intel_dpt.c  |   1 +
 drivers/gpu/drm/i915/display/intel_dsb.c  |   1 +
 drivers/gpu/drm/i915/display/intel_overlay.c  |   1 +
 drivers/gpu/drm/i915/gem/i915_gem_context.h   |   1 -
 drivers/gpu/drm/i915/gem/i915_gem_domain.c|   1 +
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c|   1 +
 drivers/gpu/drm/i915/gem/i915_gem_internal.c  |   1 -
 drivers/gpu/drm/i915/gem/i915_gem_mman.c  |   5 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.c|   1 +
 drivers/gpu/drm/i915/gem/i915_gem_object.h|   5 +-
 drivers/gpu/drm/i915/gem/i915_gem_phys.c  |   1 +
 drivers/gpu/drm/i915/gem/i915_gem_pm.c|   1 +
 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c  |   1 +
 drivers/gpu/drm/i915/gem/i915_gem_tiling.c|   1 -
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c  |   1 +
 drivers/gpu/drm/i915/gem/i915_gem_userptr.c   |   1 +
 .../i915/gem/selftests/i915_gem_coherency.c   |   1 +
 .../drm/i915/gem/selftests/i915_gem_context.c |   1 +
 .../drm/i915/gem/selftests/i915_gem_mman.c|   1 +
 drivers/gpu/drm/i915/gt/gen8_engine_cs.h  |   2 +-
 drivers/gpu/drm/i915/gt/intel_engine_stats.h  |   2 +-
 drivers/gpu/drm/i915/gt/intel_engine_types.h  |   1 -
 drivers/gpu/drm/i915/gt/intel_ggtt.c  |  10 +-
 drivers/gpu/drm/i915/gt/intel_gt.c|   1 +
 drivers/gpu/drm/i915/gt/intel_gt_sysfs.h  |   2 -
 drivers/gpu/drm/i915/gt/intel_renderstate.h   |   2 +-
 drivers/gpu/drm/i915/gt/intel_ring.h  |   2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.h  |   5 +-
 drivers/gpu/drm/i915/gt/selftest_migrate.c|   2 +
 drivers/gpu/drm/i915/gt/selftest_timeline.c   |   1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   2 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.h|   1 -
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h  |   1 -
 drivers/gpu/drm/i915/gvt/scheduler.c  |   1 +
 drivers/gpu/drm/i915/i915_debug.h |  63 ++
 drivers/gpu/drm/i915/i915_debugfs.c   |   1 +
 drivers/gpu/drm/i915/i915_driver.c|   3 +-
 drivers/gpu/drm/i915/i915_drm_client.c|   1 -
 drivers/gpu/drm/i915/i915_drm_client.h|   2 +-
 drivers/gpu/drm/i915/i915_drv.h   |  75 
 drivers/gpu/drm/i915/i915_gem.c   |  39 ++
 drivers/gpu/drm/i915/i915_gem.h   | 114 ++
 drivers/gpu/drm/i915/i915_gpu_error.h |   1 -
 drivers/gpu/drm/i915/i915_ioctl.c |   1 -
 drivers/gpu/drm/i915/i915_perf.c  |   1 +
 drivers/gpu/drm/i915/i915_request.h   |   1 -
 drivers/gpu/drm/i915/i915_scatterlist.h   |   2 +-
 drivers/gpu/drm/i915/i915_scheduler.h |   1 +
 drivers/gpu/drm/i915/i915_syncmap.c   |   5 +-
 drivers/gpu/drm/i915/i915_tasklet.h   |  43 +++
 drivers/gpu/drm/i915/i915_ttm_buddy_manager.c |   3 +-
 drivers/gpu/drm/i915/i915_utils.h |  40 --
 drivers/gpu/drm/i915/i915_vma_resource.h  |   1 -
 drivers/gpu/drm/i915/intel_gvt.c  |   1 +
 .../gpu/drm/i915/selftests/i915_gem_evict.c   |   2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |   4 +-
 .../gpu/drm/i915/selftests/i915_selftest.c|   1 +
 drivers/gpu/drm/i915/selftests/i915_vma.c |   2 +-
 .../drm/i915/selftests/intel_memory_region.c  |   1 +
 60 files changed, 236 insertions(+), 236 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_debug.h
 create mode 100644 drivers/gpu/drm/i915/i915_tasklet.h

-- 
2.30.2

[Intel-gfx] ✓ Fi.CI.BAT: success for Disable connector polling for a headless sku

[Patchwork]

== Series Details ==

Series: Disable connector polling for a headless sku
URL   : https://patchwork.freedesktop.org/series/104711/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11726 -> Patchwork_104711v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/index.html

Participating hosts (43 -> 45)
--

  Additional (4): bat-adln-1 fi-kbl-x1275 bat-dg2-9 bat-atsm-1 
  Missing(2): bat-dg2-8 bat-jsl-2 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_104711v1:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-adln-1}:   NOTRUN -> [DMESG-WARN][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/bat-adln-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@kms_frontbuffer_tracking@basic:
- {bat-adln-1}:   NOTRUN -> [SKIP][2] +19 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/bat-adln-1/igt@kms_frontbuffer_track...@basic.html

  
Known issues


  Here are the changes found in Patchwork_104711v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-x1275:   NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/fi-kbl-x1275/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-kbl-x1275:   NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/fi-kbl-x1275/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@gem:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][5] ([i915#4528])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/fi-pnv-d510/igt@i915_selftest@l...@gem.html

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-5:  [PASS][6] -> [INCOMPLETE][7] ([i915#4418])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/bat-dg1-5/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [PASS][8] -> [DMESG-FAIL][9] ([i915#4528])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-kbl-x1275:   NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/fi-kbl-x1275/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-x1275:   NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/fi-kbl-x1275/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_vgem@basic-userptr:
- fi-kbl-x1275:   NOTRUN -> [SKIP][12] ([fdo#109271]) +12 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/fi-kbl-x1275/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- {fi-ehl-2}: [DMESG-WARN][13] ([i915#5122]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[DMESG-FAIL][15] ([i915#4528]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104711v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/

Re: [Intel-gfx] [PATCH 1/2] drm/i915/opregion: add function to check if headless sku

[Jani Nikula]

On Fri, 03 Jun 2022, Jouni Högander  wrote:
> Export headless sku bit (bit 13) from opregion->header->pcon as an
> interface to check if our device is headless configuration.
>
> Bspec: 53441
> Signed-off-by: Jouni Högander 
> ---
>  drivers/gpu/drm/i915/display/intel_opregion.c | 12 
>  drivers/gpu/drm/i915/display/intel_opregion.h |  7 +++
>  2 files changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c 
> b/drivers/gpu/drm/i915/display/intel_opregion.c
> index f31e8c3f8ce0..eab3f2e6b786 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> @@ -53,6 +53,8 @@
>  #define MBOX_ASLE_EXTBIT(4)  /* Mailbox #5 */
>  #define MBOX_BACKLIGHT   BIT(5)  /* Mailbox #2 (valid from v3.x) 
> */
>  
> +#define PCON_HEADLESS_SKUBIT(13)

Here we go again.

What does headless mean here? The spec does not say. Does it have
display hardware? Apparently yes, since otherwise we wouldn't be here.

We have INTEL_DISPLAY_ENABLED() which should do the right thing when you
do have display hardware and have done output setup etc. but want to
force them disconnected, i.e. you take the hardware over properly, but
put it to sleep for power savings.

Maybe we should bolt this opregion check in that macro?

Maybe we need to use INTEL_DISPLAY_ENABLED() also to prevent polling.

I certainly would not want to add another mode that's separate from
HAS_DISPLAY() and INTEL_DISPLAY_ENABLED().

> +
>  struct opregion_header {
>   u8 signature[16];
>   u32 size;
> @@ -1135,6 +1137,16 @@ struct edid *intel_opregion_get_edid(struct 
> intel_connector *intel_connector)
>   return new_edid;
>  }
>  
> +bool intel_opregion_headless_sku(struct drm_i915_private *i915)
> +{
> + struct intel_opregion *opregion = &i915->opregion;
> +
> + if (!opregion->header)
> + return false;
> +
> + return opregion->header->pcon & PCON_HEADLESS_SKU;

We should probably start checking for opregion version for this stuff
too.


BR,
Jani.

> +}
> +
>  void intel_opregion_register(struct drm_i915_private *i915)
>  {
>   struct intel_opregion *opregion = &i915->opregion;
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h 
> b/drivers/gpu/drm/i915/display/intel_opregion.h
> index 82cc0ba34af7..5ad96e1d8278 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.h
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.h
> @@ -76,6 +76,8 @@ int intel_opregion_notify_adapter(struct drm_i915_private 
> *dev_priv,
>  int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
>  struct edid *intel_opregion_get_edid(struct intel_connector *connector);
>  
> +bool intel_opregion_headless_sku(struct drm_i915_private *i915);
> +
>  #else /* CONFIG_ACPI*/
>  
>  static inline int intel_opregion_setup(struct drm_i915_private *dev_priv)
> @@ -127,6 +129,11 @@ intel_opregion_get_edid(struct intel_connector 
> *connector)
>   return NULL;
>  }
>  
> +bool intel_opregion_headless_sku(struct drm_i915_private *i915)
> +{
> + return false;
> +}
> +
>  #endif /* CONFIG_ACPI */
>  
>  #endif

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✓ Fi.CI.BAT: success for Fixes integer overflow or integer truncation issues in page lookups, ttm place configuration and scatterlist creation (rev2)

[Patchwork]

== Series Details ==

Series: Fixes integer overflow or integer truncation issues in page lookups, 
ttm place configuration and scatterlist creation (rev2)
URL   : https://patchwork.freedesktop.org/series/104704/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11726 -> Patchwork_104704v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/index.html

Participating hosts (43 -> 44)
--

  Additional (2): fi-kbl-x1275 bat-atsm-1 
  Missing(1): bat-jsl-2 

Known issues


  Here are the changes found in Patchwork_104704v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-x1275:   NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/fi-kbl-x1275/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-kbl-x1275:   NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/fi-kbl-x1275/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_pm_rpm@basic-rte:
- fi-cfl-8109u:   [PASS][3] -> [DMESG-WARN][4] ([i915#1888] / [i915#62])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-cfl-8109u/igt@i915_pm_...@basic-rte.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/fi-cfl-8109u/igt@i915_pm_...@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [PASS][5] -> [DMESG-FAIL][6] ([i915#62])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@gtt:
- fi-bdw-5557u:   [PASS][7] -> [DMESG-FAIL][8] ([i915#3674])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-5:  [PASS][9] -> [DMESG-FAIL][10] ([i915#4494] / 
[i915#4957])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u:   [PASS][11] -> [DMESG-WARN][12] ([i915#5904]) +12 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-kbl-x1275:   NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/fi-kbl-x1275/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u:   [PASS][14] -> [DMESG-WARN][15] ([i915#62]) +14 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11726/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-x1275:   NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/fi-kbl-x1275/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_vgem@basic-userptr:
- fi-kbl-x1275:   NOTRUN -> [SKIP][17] ([fdo#109271]) +12 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104704v2/fi-kbl-x1275/igt@prime_v...@basic-userptr.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
  [i915#3674]: https://gitlab.freedesktop.org/drm/intel/issues/3674
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/inte

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Disable connector polling for a headless sku

[Patchwork]

== Series Details ==

Series: Disable connector polling for a headless sku
URL   : https://patchwork.freedesktop.org/series/104711/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Fixes integer overflow or integer truncation issues in page lookups, ttm place configuration and scatterlist creation (rev2)

[Patchwork]

== Series Details ==

Series: Fixes integer overflow or integer truncation issues in page lookups, 
ttm place configuration and scatterlist creation (rev2)
URL   : https://patchwork.freedesktop.org/series/104704/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fixes integer overflow or integer truncation issues in page lookups, ttm place configuration and scatterlist creation (rev2)

[Patchwork]

== Series Details ==

Series: Fixes integer overflow or integer truncation issues in page lookups, 
ttm place configuration and scatterlist creation (rev2)
URL   : https://patchwork.freedesktop.org/series/104704/
State : warning

== Summary ==

Error: dim checkpatch failed
14fec565e6d1 drm/i915/gem: Typecheck page lookups
-:85: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'n' - possible side-effects?
#85: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.h:374:
+#define __i915_gem_object_get_sg(obj, it, n, offset) ({ \
+   exactly_pgoff_t(n); \
+   (__i915_gem_object_get_sg)(obj, it, n, offset); \
+})

-:100: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'n' - possible side-effects?
#100: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.h:386:
+#define i915_gem_object_get_sg(obj, n, offset) ({ \
+   exactly_pgoff_t(n); \
+   (i915_gem_object_get_sg)(obj, n, offset); \
+})

-:115: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'n' - possible side-effects?
#115: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.h:398:
+#define i915_gem_object_get_sg_dma(obj, n, offset) ({ \
+   exactly_pgoff_t(n); \
+   (i915_gem_object_get_sg_dma)(obj, n, offset); \
+})

-:125: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'n' - possible side-effects?
#125: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.h:406:
+#define i915_gem_object_get_page(obj, n) ({ \
+   exactly_pgoff_t(n); \
+   (i915_gem_object_get_page)(obj, n); \
+})

-:135: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'n' - possible side-effects?
#135: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.h:414:
+#define i915_gem_object_get_dirty_page(obj, n) ({ \
+   exactly_pgoff_t(n); \
+   (i915_gem_object_get_dirty_page)(obj, n); \
+})

-:146: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'n' - possible side-effects?
#146: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.h:423:
+#define i915_gem_object_get_dma_address_len(obj, n, len) ({ \
+   exactly_pgoff_t(n); \
+   (i915_gem_object_get_dma_address_len)(obj, n, len); \
+})

-:156: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'n' - possible side-effects?
#156: FILE: drivers/gpu/drm/i915/gem/i915_gem_object.h:431:
+#define i915_gem_object_get_dma_address(obj, n) ({ \
+   exactly_pgoff_t(n); \
+   (i915_gem_object_get_dma_address)(obj, n); \
+})

total: 0 errors, 0 warnings, 7 checks, 401 lines checked
134487384609 drm/i915: Check for integer truncation on scatterlist creation
-:196: WARNING:NEW_TYPEDEFS: do not add new typedefs
#196: FILE: drivers/gpu/drm/i915/i915_scatterlist.h:222:
+typedef unsigned int __sg_size_t; /* see linux/scatterlist.h */

-:197: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#197: FILE: drivers/gpu/drm/i915/i915_scatterlist.h:223:
+#define sg_alloc_table(sgt, nents, gfp) \
+   overflows_type(nents, __sg_size_t) ? -E2BIG : (sg_alloc_table)(sgt, 
(__sg_size_t)(nents), gfp)

-:197: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'nents' - possible 
side-effects?
#197: FILE: drivers/gpu/drm/i915/i915_scatterlist.h:223:
+#define sg_alloc_table(sgt, nents, gfp) \
+   overflows_type(nents, __sg_size_t) ? -E2BIG : (sg_alloc_table)(sgt, 
(__sg_size_t)(nents), gfp)

-:198: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#198: FILE: drivers/gpu/drm/i915/i915_scatterlist.h:224:
+   overflows_type(nents, __sg_size_t) ? -E2BIG : (sg_alloc_table)(sgt, 
(__sg_size_t)(nents), gfp)

-:200: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#200: FILE: drivers/gpu/drm/i915/i915_scatterlist.h:226:
+#define sg_alloc_table_from_pages_segment(sgt, pages, npages, offset, size, 
max_segment, gfp) \
+   overflows_type(npages, __sg_size_t) ? -E2BIG : 
(sg_alloc_table_from_pages_segment)(sgt, pages, (__sg_size_t)(npages), offset, 
size, max_segment, gfp)

-:200: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'npages' - possible 
side-effects?
#200: FILE: drivers/gpu/drm/i915/i915_scatterlist.h:226:
+#define sg_alloc_table_from_pages_segment(sgt, pages, npages, offset, size, 
max_segment, gfp) \
+   overflows_type(npages, __sg_size_t) ? -E2BIG : 
(sg_alloc_table_from_pages_segment)(sgt, pages, (__sg_size_t)(npages), offset, 
size, max_segment, gfp)

-:201: WARNING:LONG_LINE: line length of 157 exceeds 100 columns
#201: FILE: drivers/gpu/drm/i915/i915_scatterlist.h:227:
+   overflows_type(npages, __sg_size_t) ? -E2BIG : 
(sg_alloc_table_from_pages_segment)(sgt, pages, (__sg_size_t)(npages), offset, 
size, max_segment, gfp)

total: 2 errors, 3 warnings, 2 checks, 139 lines checked
8942107a19b2 drm/i915: Check for integer truncation on the configuration of ttm 
place
-:32: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ptr' - possible side-effects?
#32: FILE: drivers/gpu/drm/i915/gem/i915_gem_ttm.c:140:
+#define SAFE_CONVERSION(ptr, value) ({ \
+   if (!safe_conversion(ptr, value)) { \
+   GEM_BUG_ON(overflows_type(value, *ptr)); \
+   } \
+})

-:32: CHECK:MACRO_ARG_REUSE: M

Re: [Intel-gfx] [RFC PATCH 5/5] drm/i915/display/tgl+: Use PPS index from vbt

[Manna, Animesh]

> -Original Message-
> From: Nikula, Jani 
> Sent: Thursday, June 2, 2022 9:03 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: ville.syrj...@linux.intel.com; Shankar, Uma ;
> Varide, Nischal ; Manna, Animesh
> 
> Subject: Re: [RFC PATCH 5/5] drm/i915/display/tgl+: Use PPS index from vbt
> 
> On Thu, 02 Jun 2022, Animesh Manna  wrote:
> > From: Nischal Varide 
> >
> > Tigerlake and newer has two instances of PPS, to support up to two eDP
> > panels.
> >
> > Signed-off-by: Nischal Varide 
> > Signed-off-by: Animesh Manna 
> > ---
> >  drivers/gpu/drm/i915/display/intel_pps.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
> > b/drivers/gpu/drm/i915/display/intel_pps.c
> > index 1b21a341962f..52cb5be4e901 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> > @@ -365,7 +365,8 @@ static void intel_pps_get_registers(struct
> > intel_dp *intel_dp,
> >
> > memset(regs, 0, sizeof(*regs));
> >
> > -   if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> > +   if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
> > +   DISPLAY_VER(dev_priv) >= 12)
> > pps_idx = bxt_power_sequencer_idx(intel_dp);
> 
> There are two things that need to be checked, but I don't have the time right
> now:
> 
> - We'll probably need this *before* we've parsed the panel specific info
>   from VBT. Ville has looked into this somewhat with the PNPID panel
>   type stuff.

Currently intel_pps_init() get called before intel_bios_init_panel() where 
panel specific info in parsed from VBT.

> 
> - bxt_power_sequencer_idx() does pps_init_registers() which has always
>   struck me as a really odd place to do it. As if we don't know when the
>   first time we do it is, so we do it there just in case.

Will try to check on this.

Regards,
Animesh 
> 
> BR,
> Jani.
> 
> 
> 
> > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > pps_idx = vlv_power_sequencer_pipe(intel_dp);
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 2/2] drm/i915: do not start connector polling when headless sku

[Jouni Högander]

Connector polling is waking up the polled device. Polling
is unnecessary if our device is known to not have display.

Fix this and Save some power by disabling starting connector
polling when we are having headless sku. Use information from
opregion.

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_hotplug.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c 
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 8204126d17f9..555278ec7667 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -668,7 +668,8 @@ static void i915_hpd_poll_init_work(struct work_struct 
*work)
  */
 void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
 {
-   if (!HAS_DISPLAY(dev_priv))
+   if (!HAS_DISPLAY(dev_priv) ||
+   intel_opregion_headless_sku(dev_priv))
return;
 
WRITE_ONCE(dev_priv->hotplug.poll_enabled, true);
-- 
2.25.1

[Intel-gfx] [PATCH 1/2] drm/i915/opregion: add function to check if headless sku

[Jouni Högander]

Export headless sku bit (bit 13) from opregion->header->pcon as an
interface to check if our device is headless configuration.

Bspec: 53441
Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 12 
 drivers/gpu/drm/i915/display/intel_opregion.h |  7 +++
 2 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c 
b/drivers/gpu/drm/i915/display/intel_opregion.c
index f31e8c3f8ce0..eab3f2e6b786 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -53,6 +53,8 @@
 #define MBOX_ASLE_EXT  BIT(4)  /* Mailbox #5 */
 #define MBOX_BACKLIGHT BIT(5)  /* Mailbox #2 (valid from v3.x) */
 
+#define PCON_HEADLESS_SKU  BIT(13)
+
 struct opregion_header {
u8 signature[16];
u32 size;
@@ -1135,6 +1137,16 @@ struct edid *intel_opregion_get_edid(struct 
intel_connector *intel_connector)
return new_edid;
 }
 
+bool intel_opregion_headless_sku(struct drm_i915_private *i915)
+{
+   struct intel_opregion *opregion = &i915->opregion;
+
+   if (!opregion->header)
+   return false;
+
+   return opregion->header->pcon & PCON_HEADLESS_SKU;
+}
+
 void intel_opregion_register(struct drm_i915_private *i915)
 {
struct intel_opregion *opregion = &i915->opregion;
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h 
b/drivers/gpu/drm/i915/display/intel_opregion.h
index 82cc0ba34af7..5ad96e1d8278 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.h
+++ b/drivers/gpu/drm/i915/display/intel_opregion.h
@@ -76,6 +76,8 @@ int intel_opregion_notify_adapter(struct drm_i915_private 
*dev_priv,
 int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
 struct edid *intel_opregion_get_edid(struct intel_connector *connector);
 
+bool intel_opregion_headless_sku(struct drm_i915_private *i915);
+
 #else /* CONFIG_ACPI*/
 
 static inline int intel_opregion_setup(struct drm_i915_private *dev_priv)
@@ -127,6 +129,11 @@ intel_opregion_get_edid(struct intel_connector *connector)
return NULL;
 }
 
+bool intel_opregion_headless_sku(struct drm_i915_private *i915)
+{
+   return false;
+}
+
 #endif /* CONFIG_ACPI */
 
 #endif
-- 
2.25.1

[Intel-gfx] [PATCH 0/2] Disable connector polling for a headless sku

[Jouni Högander]

This patch set disables connector polling when entering runtime
suspend for headless sku to prevent waking it up again when poll
is performed.

Cc: Imre Deak 
Cc: Anshuman Gupta 

Jouni Högander (2):
  drm/i915/opregion: add function to check if headless sku
  drm/i915: do not start connector polling when headless sku

 drivers/gpu/drm/i915/display/intel_hotplug.c  |  3 ++-
 drivers/gpu/drm/i915/display/intel_opregion.c | 12 
 drivers/gpu/drm/i915/display/intel_opregion.h |  7 +++
 3 files changed, 21 insertions(+), 1 deletion(-)

-- 
2.25.1

Re: [Intel-gfx] [RFC PATCH 1/5] drm/i915/bios: calculate drrs mode using panel index for dual LFP

[Manna, Animesh]

> -Original Message-
> From: Nikula, Jani 
> Sent: Thursday, June 2, 2022 8:41 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: ville.syrj...@linux.intel.com; Shankar, Uma ;
> Manna, Animesh 
> Subject: Re: [RFC PATCH 1/5] drm/i915/bios: calculate drrs mode using panel
> index for dual LFP
> 
> On Thu, 02 Jun 2022, Jani Nikula  wrote:
> > On Thu, 02 Jun 2022, Animesh Manna  wrote:
> >> Dual LFP may have different panel and based on panel index respective
> >> 2 bits store the drrs mode info for each panel. So panel index is
> >> used for deriving drrs mode of the rspective panel.
> >>
> >> Signed-off-by: Animesh Manna 
> >> ---
> >>  drivers/gpu/drm/i915/display/icl_dsi.c|  2 +-
> >>  drivers/gpu/drm/i915/display/intel_bios.c | 45 +--
> >>  drivers/gpu/drm/i915/display/intel_bios.h |  3 +-
> >>  drivers/gpu/drm/i915/display/intel_dp.c   |  3 +-
> >>  drivers/gpu/drm/i915/display/intel_lvds.c |  3 +-
> >>  drivers/gpu/drm/i915/display/intel_sdvo.c |  2 +-
> >>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  4 ++
> >>  drivers/gpu/drm/i915/display/vlv_dsi.c|  2 +-
> >>  8 files changed, 52 insertions(+), 12 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> >> b/drivers/gpu/drm/i915/display/icl_dsi.c
> >> index 3b5305c219ba..b3aa430abd03 100644
> >> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> >> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> >> @@ -2050,7 +2050,7 @@ void icl_dsi_init(struct drm_i915_private
> *dev_priv)
> >>/* attach connector to encoder */
> >>intel_connector_attach_encoder(intel_connector, encoder);
> >>
> >> -  intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL);
> >> +  intel_bios_init_panel(dev_priv, intel_connector, NULL);
> >>
> >>mutex_lock(&dev->mode_config.mutex);
> >>intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
> >> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> >> b/drivers/gpu/drm/i915/display/intel_bios.c
> >> index 337277ae3dae..78eaf6255599 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> >> @@ -747,7 +747,8 @@ static int get_panel_type(struct drm_i915_private
> >> *i915,  static void  parse_panel_options(struct drm_i915_private
> >> *i915,
> >>struct intel_panel *panel,
> >> -  const struct edid *edid)
> >> +  const struct edid *edid,
> >> +  int panel_index)
> >>  {
> >>const struct bdb_lvds_options *lvds_options;
> >>int panel_type;
> >> @@ -764,7 +765,7 @@ parse_panel_options(struct drm_i915_private *i915,
> >>panel->vbt.panel_type = panel_type;
> >>
> >>drrs_mode = (lvds_options->dps_panel_type_bits
> >> -  >> (panel_type * 2)) & MODE_MASK;
> >> +  >> (panel_index * 2)) & MODE_MASK;
> >
> > It's the get_panel_type() call that needs to take the panel number
> > into account, and return the panel specific panel_type from there.
> > After that, it's stored in panel->vbt.panel_type and it'll be used
> > everywere. DRRS is not a special case.
> >
> >>/*
> >> * VBT has static DRRS = 0 and seamless DRRS = 2.
> >> * The below piece of code is required to adjust vbt.drrs_type @@
> >> -3069,13 +3070,49 @@ void intel_bios_init(struct drm_i915_private *i915)
> >>kfree(oprom_vbt);
> >>  }
> >>
> >> +static int
> >> +get_lfp_panel_index(struct drm_i915_private *i915, int
> >> +lfp_panel_instance) {
> >> +  const struct bdb_lvds_options *lvds_options;
> >> +
> >> +  lvds_options = find_section(i915, BDB_LVDS_OPTIONS);
> >> +  if (!lvds_options)
> >> +  return -1;
> >> +
> >> +  switch (lfp_panel_instance) {
> >> +  case 1:
> >> +  return lvds_options->panel_type;
> >> +  case 2:
> >> +  return lvds_options->panel_type2;
> >> +  default:
> >> +  break;
> >> +  }
> >> +
> >> +  return -1;
> >> +}
> >
> > Nah, it's not this simple. See get_panel_type(). Either of the
> > panel_type fields could be 0xff to indicate PNPID based lookup.
> >
> >> +
> >>  void intel_bios_init_panel(struct drm_i915_private *i915,
> >> - struct intel_panel *panel,
> >> + struct intel_connector *intel_connector,
> >>   const struct edid *edid)
> >>  {
> >> +  struct intel_panel *panel = &intel_connector->panel;
> >> +  struct intel_encoder *encoder = intel_connector->encoder;
> >> +  const struct intel_bios_encoder_data *devdata =
> >> +i915->vbt.ports[encoder->port];
> >
> > This might be NULL, we don't initialize ports for all platforms.
> >
> >
> >> +  int lfp_inst = 0, panel_index;
> >> +
> >>init_vbt_panel_defaults(panel);
> >>
> >> -  parse_panel_options(i915, panel, edid);
> >> +  if (devdata->child.handle == HANDLE_LFP_1)
> >> +  lfp_inst = 1;
> >> +  else if (devdata->child.handle == HANDLE_LFP_2)
> >> +  lfp_inst = 2;
> >> +
> >> +  if (lfp_ins

[Intel-gfx] [PATCH 6/6] drm/i915: Remove truncation warning for large objects

[Gwan-gyeong Mun]

From: Chris Wilson 

Having addressed the issues surrounding incorrect types for local
variables and potential integer truncation in using the scatterlist API,
we have closed all the loop holes we had previously identified with
dangerously large object creation. As such, we can eliminate the warning
put in place to remind us to complete the review.

Signed-off-by: Chris Wilson 
Signed-off-by: Gwan-gyeong Mun 
Cc: Tvrtko Ursulin 
Cc: Brian Welty 
Cc: Matthew Auld 
Cc: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_object.h | 15 ---
 1 file changed, 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 551e4293d19c..ef942dd7039f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -20,25 +20,10 @@
 
 enum intel_region_id;
 
-/*
- * XXX: There is a prevalence of the assumption that we fit the
- * object's page count inside a 32bit _signed_ variable. Let's document
- * this and catch if we ever need to fix it. In the meantime, if you do
- * spot such a local variable, please consider fixing!
- *
- * We can check for invalidly typed locals with typecheck(), see for example
- * i915_gem_object_get_sg().
- */
-#define GEM_CHECK_SIZE_OVERFLOW(sz) \
-   GEM_WARN_ON((sz) >> PAGE_SHIFT > INT_MAX)
-
 static inline bool i915_gem_object_size_2big(u64 size)
 {
struct drm_i915_gem_object *obj;
 
-   if (GEM_CHECK_SIZE_OVERFLOW(size))
-   return true;
-
if (overflows_type(size, obj->base.size))
return true;
 
-- 
2.34.1

[Intel-gfx] [PATCH 5/6] drm/i915: Use error code as -E2BIG when the size of gem ttm object is too large

[Gwan-gyeong Mun]

The ttm_bo_init_reserved() functions returns -ENOSPC if the size is too big
to add vma. The direct function that returns -ENOSPC is 
drm_mm_insert_node_in_range().
To handle the same error as other code returning -E2BIG when the size is
too large, it converts return value to -E2BIG.

Signed-off-by: Gwan-gyeong Mun 
Cc: Chris Wilson 
Cc: Matthew Auld 
Cc: Thomas Hellström 
Testcase: igt@gem_create@create-massive
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4991
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 8231a6fc5437..f162e2492cd3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -1243,6 +1243,17 @@ int __i915_gem_ttm_object_init(struct 
intel_memory_region *mem,
   bo_type, &i915_sys_placement,
   page_size >> PAGE_SHIFT,
   &ctx, NULL, NULL, i915_ttm_bo_destroy);
+
+   /*
+* XXX: The ttm_bo_init_reserved() functions returns -ENOSPC if the size
+* is too big to add vma. The direct function that returns -ENOSPC is
+* drm_mm_insert_node_in_range(). To handle the same error as other code
+* that returns -E2BIG when the size is too large, it converts -ENOSPC 
to
+* -E2BIG.
+*/
+   if (size >> PAGE_SHIFT > INT_MAX && ret == -ENOSPC)
+   ret = -E2BIG;
+
if (ret)
return i915_ttm_err_to_gem(ret);
 
-- 
2.34.1

[Intel-gfx] [PATCH 4/6] drm/i915: Check if the size is too big while creating shmem file

[Gwan-gyeong Mun]

The __shmem_file_setup() function returns -EINVAL if size is greater than
MAX_LFS_FILESIZE. To handle the same error as other code that returns
-E2BIG when the size is too large, it add a code that returns -E2BIG when
the size is larger than the size that can be handled.

Signed-off-by: Gwan-gyeong Mun 
Cc: Chris Wilson 
Cc: Matthew Auld 
Cc: Thomas Hellström 
Testcase: igt@gem_create@create-massive
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4991
---
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c 
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index e77f9ada31a3..b4ecca21277e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -542,6 +542,15 @@ static int __create_shmem(struct drm_i915_private *i915,
 
drm_gem_private_object_init(&i915->drm, obj, size);
 
+   /* XXX: The __shmem_file_setup() function returns -EINVAL if size is
+* greater than MAX_LFS_FILESIZE.
+* To handle the same error as other code that returns -E2BIG when
+* the size is too large, we add a code that returns -E2BIG when the
+* size is larger than the size that can be handled.
+*/
+   if (size > MAX_LFS_FILESIZE)
+   return -E2BIG;
+
if (i915->mm.gemfs)
filp = shmem_file_setup_with_mnt(i915->mm.gemfs, "i915", size,
 flags);
-- 
2.34.1

[Intel-gfx] [PATCH 3/6] drm/i915: Check for integer truncation on the configuration of ttm place

[Gwan-gyeong Mun]

There is an impedance mismatch between the first/last valid page
frame number of ttm place in unsigned and our memory/page accounting in
unsigned long.
As the object size is under the control of userspace, we have to be prudent
and catch the conversion errors.
To catch the implicit truncation as we switch from unsigned long to
unsigned, we use our overflows_type check and report E2BIG or overflow_type
prior to the operation.

Signed-off-by: Gwan-gyeong Mun 
Cc: Chris Wilson 
Cc: Matthew Auld 
Cc: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 12 +---
 drivers/gpu/drm/i915/intel_region_ttm.c | 16 +---
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 52f8c3f4d8a8..8231a6fc5437 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -137,19 +137,25 @@ i915_ttm_place_from_region(const struct 
intel_memory_region *mr,
if (mr->type == INTEL_MEMORY_SYSTEM)
return;
 
+#define SAFE_CONVERSION(ptr, value) ({ \
+   if (!safe_conversion(ptr, value)) { \
+   GEM_BUG_ON(overflows_type(value, *ptr)); \
+   } \
+})
if (flags & I915_BO_ALLOC_CONTIGUOUS)
place->flags |= TTM_PL_FLAG_CONTIGUOUS;
if (offset != I915_BO_INVALID_OFFSET) {
-   place->fpfn = offset >> PAGE_SHIFT;
-   place->lpfn = place->fpfn + (size >> PAGE_SHIFT);
+   SAFE_CONVERSION(&place->fpfn, offset >> PAGE_SHIFT);
+   SAFE_CONVERSION(&place->lpfn, place->fpfn + (size >> 
PAGE_SHIFT));
} else if (mr->io_size && mr->io_size < mr->total) {
if (flags & I915_BO_ALLOC_GPU_ONLY) {
place->flags |= TTM_PL_FLAG_TOPDOWN;
} else {
place->fpfn = 0;
-   place->lpfn = mr->io_size >> PAGE_SHIFT;
+   SAFE_CONVERSION(&place->lpfn, mr->io_size >> 
PAGE_SHIFT);
}
}
+#undef SAFE_CONVERSION
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c 
b/drivers/gpu/drm/i915/intel_region_ttm.c
index 62ff77445b01..8fcb8654b978 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -202,24 +202,34 @@ intel_region_ttm_resource_alloc(struct 
intel_memory_region *mem,
struct ttm_resource *res;
int ret;
 
+#define SAFE_CONVERSION(ptr, value) ({ \
+   if (!safe_conversion(ptr, value)) { \
+   GEM_BUG_ON(overflows_type(value, *ptr)); \
+   ret = -E2BIG; \
+   goto out; \
+   } \
+})
if (flags & I915_BO_ALLOC_CONTIGUOUS)
place.flags |= TTM_PL_FLAG_CONTIGUOUS;
if (offset != I915_BO_INVALID_OFFSET) {
-   place.fpfn = offset >> PAGE_SHIFT;
-   place.lpfn = place.fpfn + (size >> PAGE_SHIFT);
+   SAFE_CONVERSION(&place.fpfn, offset >> PAGE_SHIFT);
+   SAFE_CONVERSION(&place.lpfn, place.fpfn + (size >> PAGE_SHIFT));
} else if (mem->io_size && mem->io_size < mem->total) {
if (flags & I915_BO_ALLOC_GPU_ONLY) {
place.flags |= TTM_PL_FLAG_TOPDOWN;
} else {
place.fpfn = 0;
-   place.lpfn = mem->io_size >> PAGE_SHIFT;
+   SAFE_CONVERSION(&place.lpfn, mem->io_size >> 
PAGE_SHIFT);
}
}
+#undef SAFE_CONVERSION
 
mock_bo.base.size = size;
mock_bo.bdev = &mem->i915->bdev;
 
ret = man->func->alloc(man, &mock_bo, &place, &res);
+
+out:
if (ret == -ENOSPC)
ret = -ENXIO;
if (!ret)
-- 
2.34.1

[Intel-gfx] [PATCH 2/6] drm/i915: Check for integer truncation on scatterlist creation

[Gwan-gyeong Mun]

From: Chris Wilson 

There is an impedance mismatch between the scatterlist API using unsigned
int and our memory/page accounting in unsigned long. That is we may try
to create a scatterlist for a large object that overflows returning a
small table into which we try to fit very many pages. As the object size
is under control of userspace, we have to be prudent and catch the
conversion errors.

To catch the implicit truncation as we switch from unsigned long into the
scatterlist's unsigned int, we use our overflows_type check and report
E2BIG prior to the operation. This is already used in our create ioctls to
indicate if the uABI request is simply too large for the backing store.
Failing that type check, we have a second check at sg_alloc_table time
to make sure the values we are passing into the scatterlist API are not
truncated.

It uses pgoff_t for locals that are dealing with page indices, in this
case, the page count is the limit of the page index.
And it adds and uses safe_conversion() macro which performs a type
conversion (cast) of an integer value into a new variable, checking that
the destination is large enough to hold the source value.

Signed-off-by: Chris Wilson 
Signed-off-by: Gwan-gyeong Mun 
Cc: Tvrtko Ursulin 
Cc: Brian Welty 
Cc: Matthew Auld 
Cc: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_internal.c |  6 --
 drivers/gpu/drm/i915/gem/i915_gem_object.h   |  3 ---
 drivers/gpu/drm/i915/gem/i915_gem_phys.c |  4 
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c|  5 -
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c  |  4 
 drivers/gpu/drm/i915/gem/i915_gem_userptr.c  |  5 -
 drivers/gpu/drm/i915/gvt/dmabuf.c|  9 +
 drivers/gpu/drm/i915/i915_scatterlist.h  |  8 
 drivers/gpu/drm/i915/i915_utils.h| 12 
 9 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c 
b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index c698f95af15f..ff2e6e780631 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -37,10 +37,13 @@ static int i915_gem_object_get_pages_internal(struct 
drm_i915_gem_object *obj)
struct sg_table *st;
struct scatterlist *sg;
unsigned int sg_page_sizes;
-   unsigned int npages;
+   pgoff_t npages; /* restricted by sg_alloc_table */
int max_order;
gfp_t gfp;
 
+   if (!safe_conversion(&npages, obj->base.size >> PAGE_SHIFT))
+   return -E2BIG;
+
max_order = MAX_ORDER;
 #ifdef CONFIG_SWIOTLB
if (is_swiotlb_active(obj->base.dev->dev)) {
@@ -67,7 +70,6 @@ static int i915_gem_object_get_pages_internal(struct 
drm_i915_gem_object *obj)
if (!st)
return -ENOMEM;
 
-   npages = obj->base.size / PAGE_SIZE;
if (sg_alloc_table(st, npages, GFP_KERNEL)) {
kfree(st);
return -ENOMEM;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 22c4ba0cd106..551e4293d19c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -26,9 +26,6 @@ enum intel_region_id;
  * this and catch if we ever need to fix it. In the meantime, if you do
  * spot such a local variable, please consider fixing!
  *
- * Aside from our own locals (for which we have no excuse!):
- * - sg_table embeds unsigned int for nents
- *
  * We can check for invalidly typed locals with typecheck(), see for example
  * i915_gem_object_get_sg().
  */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c 
b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index 0d0e46dae559..88ba7266a3a5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -28,6 +28,10 @@ static int i915_gem_object_get_pages_phys(struct 
drm_i915_gem_object *obj)
void *dst;
int i;
 
+   /* Contiguous chunk, with a single scatterlist element */
+   if (overflows_type(obj->base.size, sg->length))
+   return -E2BIG;
+
if (GEM_WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
return -EINVAL;
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c 
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 955844f19193..e77f9ada31a3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -193,13 +193,16 @@ static int shmem_get_pages(struct drm_i915_gem_object 
*obj)
struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct intel_memory_region *mem = obj->mm.region;
struct address_space *mapping = obj->base.filp->f_mapping;
-   const unsigned long page_count = obj->base.size / PAGE_SIZE;
unsigned int max_segment = i915_sg_segment_size();
struct sg_table *st;
struct sgt_iter sgt_iter;
+   pgoff_t page_count;
struct page *page;
in

[Intel-gfx] [PATCH 1/6] drm/i915/gem: Typecheck page lookups

[Gwan-gyeong Mun]

From: Chris Wilson 

We need to check that we avoid integer overflows when looking up a page,
and so fix all the instances where we have mistakenly used a plain
integer instead of a more suitable long. Be pedantic and add integer
typechecking to the lookup so that we can be sure that we are safe.
And it also uses pgoff_t as our page lookups must remain compatible with
the page cache, pgoff_t is currently exactly unsigned long.

Signed-off-by: Chris Wilson 
Signed-off-by: Gwan-gyeong Mun 
Cc: Tvrtko Ursulin 
Cc: Matthew Auld 
Cc: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_object.c|  7 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.h| 67 ++-
 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 25 ---
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c   |  2 +-
 .../drm/i915/gem/selftests/i915_gem_context.c | 12 ++--
 .../drm/i915/gem/selftests/i915_gem_mman.c|  8 +--
 .../drm/i915/gem/selftests/i915_gem_object.c  |  8 +--
 drivers/gpu/drm/i915/i915_gem.c   | 18 +++--
 drivers/gpu/drm/i915/i915_utils.h |  6 ++
 drivers/gpu/drm/i915/i915_vma.c   |  8 +--
 10 files changed, 106 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 06b1b188ce5a..a5af74f78d57 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -421,10 +421,11 @@ void __i915_gem_object_invalidate_frontbuffer(struct 
drm_i915_gem_object *obj,
 static void
 i915_gem_object_read_from_page_kmap(struct drm_i915_gem_object *obj, u64 
offset, void *dst, int size)
 {
+   pgoff_t idx = offset >> PAGE_SHIFT;
void *src_map;
void *src_ptr;
 
-   src_map = kmap_atomic(i915_gem_object_get_page(obj, offset >> 
PAGE_SHIFT));
+   src_map = kmap_atomic(i915_gem_object_get_page(obj, idx));
 
src_ptr = src_map + offset_in_page(offset);
if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ))
@@ -437,9 +438,10 @@ i915_gem_object_read_from_page_kmap(struct 
drm_i915_gem_object *obj, u64 offset,
 static void
 i915_gem_object_read_from_page_iomap(struct drm_i915_gem_object *obj, u64 
offset, void *dst, int size)
 {
+   pgoff_t idx = offset >> PAGE_SHIFT;
+   dma_addr_t dma = i915_gem_object_get_dma_address(obj, idx);
void __iomem *src_map;
void __iomem *src_ptr;
-   dma_addr_t dma = i915_gem_object_get_dma_address(obj, offset >> 
PAGE_SHIFT);
 
src_map = io_mapping_map_wc(&obj->mm.region->iomap,
dma - obj->mm.region->region.start,
@@ -468,6 +470,7 @@ i915_gem_object_read_from_page_iomap(struct 
drm_i915_gem_object *obj, u64 offset
  */
 int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, u64 
offset, void *dst, int size)
 {
+   GEM_BUG_ON(overflows_type(offset >> PAGE_SHIFT, pgoff_t));
GEM_BUG_ON(offset >= obj->base.size);
GEM_BUG_ON(offset_in_page(offset) > PAGE_SIZE - size);
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index e11d82a9f7c3..22c4ba0cd106 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -27,8 +27,10 @@ enum intel_region_id;
  * spot such a local variable, please consider fixing!
  *
  * Aside from our own locals (for which we have no excuse!):
- * - sg_table embeds unsigned int for num_pages
- * - get_user_pages*() mixed ints with longs
+ * - sg_table embeds unsigned int for nents
+ *
+ * We can check for invalidly typed locals with typecheck(), see for example
+ * i915_gem_object_get_sg().
  */
 #define GEM_CHECK_SIZE_OVERFLOW(sz) \
GEM_WARN_ON((sz) >> PAGE_SHIFT > INT_MAX)
@@ -366,41 +368,70 @@ int i915_gem_object_set_tiling(struct drm_i915_gem_object 
*obj,
 struct scatterlist *
 __i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
 struct i915_gem_object_page_iter *iter,
-unsigned int n,
-unsigned int *offset, bool dma);
+pgoff_t  n,
+unsigned int *offset);
+
+#define __i915_gem_object_get_sg(obj, it, n, offset) ({ \
+   exactly_pgoff_t(n); \
+   (__i915_gem_object_get_sg)(obj, it, n, offset); \
+})
 
 static inline struct scatterlist *
-i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
-  unsigned int n,
+i915_gem_object_get_sg(struct drm_i915_gem_object *obj, pgoff_t n,
   unsigned int *offset)
 {
-   return __i915_gem_object_get_sg(obj, &obj->mm.get_page, n, offset, 
false);
+   return __i915_gem_object_get_sg(obj, &obj->mm.get_page, n, offset);
 }
 
+#define i915_gem_object_get_sg(obj, n, offset) ({ \
+   exactly_pgoff_t(n); \
+   (i915_gem_object_get_sg)(obj, n, offset); \
+})
+
 static inline struct scatterlist *

[Intel-gfx] [PATCH 0/6] Fixes integer overflow or integer truncation issues in page lookups, ttm place configuration and scatterlist creation

[Gwan-gyeong Mun]

This patch series fixes integer overflow or integer truncation issues in
page lookups, ttm place configuration and scatterlist creation, etc.
We need to check that we avoid integer overflows when looking up a page,
and so fix all the instances where we have mistakenly used a plain integer
instead of a more suitable long.
And there is an impedance mismatch between the scatterlist API using
unsigned int and our memory/page accounting in unsigned long. That is we
may try to create a scatterlist for a large object that overflows returning
a small table into which we try to fit very many pages. As the object size
is under the control of userspace, we have to be prudent and catch the
conversion errors. To catch the implicit truncation as we switch from
unsigned long into the scatterlist's unsigned int, we use our overflows_type
check and report E2BIG prior to the operation. This is already used in
our create ioctls to indicate if the uABI request is simply too large for
the backing store. 
And ttm place also has the same problem with scatterlist creation,
and we fix the integer truncation problem with the way approached by
scatterlist creation.
And It corrects the error code to return -E2BIG when creating gem objects
using ttm or shmem, if the size is too large in each case.

Testcase: igt@gem_create@create-massive
Testcase: igt@gem_userptr_blits@input-checking
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4991
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5411
Cc: Chris Wilson 
Cc: Matthew Auld 
Cc: Thomas Hellström 

Chris Wilson (3):
  drm/i915/gem: Typecheck page lookups
  drm/i915: Check for integer truncation on scatterlist creation
  drm/i915: Remove truncation warning for large objects

Gwan-gyeong Mun (3):
  drm/i915: Check for integer truncation on the configuration of ttm
place
  drm/i915: Check if the size is too big while creating shmem file
  drm/i915: Use error code as -E2BIG when the size of gem ttm object is
too large

 drivers/gpu/drm/i915/gem/i915_gem_internal.c  |  6 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.c|  7 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.h| 77 +++
 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 25 +++---
 drivers/gpu/drm/i915/gem/i915_gem_phys.c  |  4 +
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 14 +++-
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c   | 29 ++-
 drivers/gpu/drm/i915/gem/i915_gem_userptr.c   |  5 +-
 .../drm/i915/gem/selftests/i915_gem_context.c | 12 +--
 .../drm/i915/gem/selftests/i915_gem_mman.c|  8 +-
 .../drm/i915/gem/selftests/i915_gem_object.c  |  8 +-
 drivers/gpu/drm/i915/gvt/dmabuf.c |  9 ++-
 drivers/gpu/drm/i915/i915_gem.c   | 18 -
 drivers/gpu/drm/i915/i915_scatterlist.h   |  8 ++
 drivers/gpu/drm/i915/i915_utils.h | 18 +
 drivers/gpu/drm/i915/i915_vma.c   |  8 +-
 drivers/gpu/drm/i915/intel_region_ttm.c   | 16 +++-
 17 files changed, 189 insertions(+), 83 deletions(-)

-- 
2.34.1

[Intel-gfx] [PATCH 6/6] drm/i915: Remove truncation warning for large objects

[Gwan-gyeong Mun]

From: Chris Wilson 

Having addressed the issues surrounding incorrect types for local
variables and potential integer truncation in using the scatterlist API,
we have closed all the loop holes we had previously identified with
dangerously large object creation. As such, we can eliminate the warning
put in place to remind us to complete the review.

Signed-off-by: Chris Wilson 
Signed-off-by: Gwan-gyeong Mun 
Cc: Tvrtko Ursulin 
Cc: Brian Welty 
Cc: Matthew Auld 
Cc: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_object.h | 15 ---
 1 file changed, 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 551e4293d19c..ef942dd7039f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -20,25 +20,10 @@
 
 enum intel_region_id;
 
-/*
- * XXX: There is a prevalence of the assumption that we fit the
- * object's page count inside a 32bit _signed_ variable. Let's document
- * this and catch if we ever need to fix it. In the meantime, if you do
- * spot such a local variable, please consider fixing!
- *
- * We can check for invalidly typed locals with typecheck(), see for example
- * i915_gem_object_get_sg().
- */
-#define GEM_CHECK_SIZE_OVERFLOW(sz) \
-   GEM_WARN_ON((sz) >> PAGE_SHIFT > INT_MAX)
-
 static inline bool i915_gem_object_size_2big(u64 size)
 {
struct drm_i915_gem_object *obj;
 
-   if (GEM_CHECK_SIZE_OVERFLOW(size))
-   return true;
-
if (overflows_type(size, obj->base.size))
return true;
 
-- 
2.34.1

[Intel-gfx] [PATCH 3/6] drm/i915: Check for integer truncation on the configuration of ttm place

[Gwan-gyeong Mun]

There is an impedance mismatch between the first/last valid page
frame number of ttm place in unsigned and our memory/page accounting in
unsigned long.
As the object size is under the control of userspace, we have to be prudent
and catch the conversion errors.
To catch the implicit truncation as we switch from unsigned long to
unsigned, we use our overflows_type check and report E2BIG or overflow_type
prior to the operation.

Signed-off-by: Gwan-gyeong Mun 
Cc: Chris Wilson 
Cc: Matthew Auld 
Cc: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 12 +---
 drivers/gpu/drm/i915/intel_region_ttm.c | 16 +---
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 52f8c3f4d8a8..8231a6fc5437 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -137,19 +137,25 @@ i915_ttm_place_from_region(const struct 
intel_memory_region *mr,
if (mr->type == INTEL_MEMORY_SYSTEM)
return;
 
+#define SAFE_CONVERSION(ptr, value) ({ \
+   if (!safe_conversion(ptr, value)) { \
+   GEM_BUG_ON(overflows_type(value, *ptr)); \
+   } \
+})
if (flags & I915_BO_ALLOC_CONTIGUOUS)
place->flags |= TTM_PL_FLAG_CONTIGUOUS;
if (offset != I915_BO_INVALID_OFFSET) {
-   place->fpfn = offset >> PAGE_SHIFT;
-   place->lpfn = place->fpfn + (size >> PAGE_SHIFT);
+   SAFE_CONVERSION(&place->fpfn, offset >> PAGE_SHIFT);
+   SAFE_CONVERSION(&place->lpfn, place->fpfn + (size >> 
PAGE_SHIFT));
} else if (mr->io_size && mr->io_size < mr->total) {
if (flags & I915_BO_ALLOC_GPU_ONLY) {
place->flags |= TTM_PL_FLAG_TOPDOWN;
} else {
place->fpfn = 0;
-   place->lpfn = mr->io_size >> PAGE_SHIFT;
+   SAFE_CONVERSION(&place->lpfn, mr->io_size >> 
PAGE_SHIFT);
}
}
+#undef SAFE_CONVERSION
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c 
b/drivers/gpu/drm/i915/intel_region_ttm.c
index 62ff77445b01..8fcb8654b978 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -202,24 +202,34 @@ intel_region_ttm_resource_alloc(struct 
intel_memory_region *mem,
struct ttm_resource *res;
int ret;
 
+#define SAFE_CONVERSION(ptr, value) ({ \
+   if (!safe_conversion(ptr, value)) { \
+   GEM_BUG_ON(overflows_type(value, *ptr)); \
+   ret = -E2BIG; \
+   goto out; \
+   } \
+})
if (flags & I915_BO_ALLOC_CONTIGUOUS)
place.flags |= TTM_PL_FLAG_CONTIGUOUS;
if (offset != I915_BO_INVALID_OFFSET) {
-   place.fpfn = offset >> PAGE_SHIFT;
-   place.lpfn = place.fpfn + (size >> PAGE_SHIFT);
+   SAFE_CONVERSION(&place.fpfn, offset >> PAGE_SHIFT);
+   SAFE_CONVERSION(&place.lpfn, place.fpfn + (size >> PAGE_SHIFT));
} else if (mem->io_size && mem->io_size < mem->total) {
if (flags & I915_BO_ALLOC_GPU_ONLY) {
place.flags |= TTM_PL_FLAG_TOPDOWN;
} else {
place.fpfn = 0;
-   place.lpfn = mem->io_size >> PAGE_SHIFT;
+   SAFE_CONVERSION(&place.lpfn, mem->io_size >> 
PAGE_SHIFT);
}
}
+#undef SAFE_CONVERSION
 
mock_bo.base.size = size;
mock_bo.bdev = &mem->i915->bdev;
 
ret = man->func->alloc(man, &mock_bo, &place, &res);
+
+out:
if (ret == -ENOSPC)
ret = -ENXIO;
if (!ret)
-- 
2.34.1

[Intel-gfx] [PATCH 5/6] drm/i915: Use error code as -E2BIG when the size of gem ttm object is too large

[Gwan-gyeong Mun]

The ttm_bo_init_reserved() functions returns -ENOSPC if the size is too big
to add vma. The direct function that returns -ENOSPC is 
drm_mm_insert_node_in_range().
To handle the same error as other code returning -E2BIG when the size is
too large, it converts return value to -E2BIG.

Signed-off-by: Gwan-gyeong Mun 
Cc: Chris Wilson 
Cc: Matthew Auld 
Cc: Thomas Hellström 
Testcase: igt@gem_create@create-massive
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4991
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 8231a6fc5437..5617b100067a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -1243,6 +1243,17 @@ int __i915_gem_ttm_object_init(struct 
intel_memory_region *mem,
   bo_type, &i915_sys_placement,
   page_size >> PAGE_SHIFT,
   &ctx, NULL, NULL, i915_ttm_bo_destroy);
+
+   /*
+* XXX: The ttm_bo_init_reserved() functions returns -ENOSPC if the size
+* is too big to add vma. The direct function that returns -ENOSPC is
+* drm_mm_insert_node_in_range(). To handle the same error as other code
+* that returns -E2BIG when the size is too large, it converts -ENOSPC 
to
+* -E2BIG.
+*/
+   if (size >> PAGE_SHIFT > INT_MAX)
+   ret = -E2BIG;
+
if (ret)
return i915_ttm_err_to_gem(ret);
 
-- 
2.34.1

[Intel-gfx] [PATCH 4/6] drm/i915: Check if the size is too big while creating shmem file

[Gwan-gyeong Mun]

The __shmem_file_setup() function returns -EINVAL if size is greater than
MAX_LFS_FILESIZE. To handle the same error as other code that returns
-E2BIG when the size is too large, it add a code that returns -E2BIG when
the size is larger than the size that can be handled.

Signed-off-by: Gwan-gyeong Mun 
Cc: Chris Wilson 
Cc: Matthew Auld 
Cc: Thomas Hellström 
Testcase: igt@gem_create@create-massive
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4991
---
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c 
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index e77f9ada31a3..b4ecca21277e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -542,6 +542,15 @@ static int __create_shmem(struct drm_i915_private *i915,
 
drm_gem_private_object_init(&i915->drm, obj, size);
 
+   /* XXX: The __shmem_file_setup() function returns -EINVAL if size is
+* greater than MAX_LFS_FILESIZE.
+* To handle the same error as other code that returns -E2BIG when
+* the size is too large, we add a code that returns -E2BIG when the
+* size is larger than the size that can be handled.
+*/
+   if (size > MAX_LFS_FILESIZE)
+   return -E2BIG;
+
if (i915->mm.gemfs)
filp = shmem_file_setup_with_mnt(i915->mm.gemfs, "i915", size,
 flags);
-- 
2.34.1

[Intel-gfx] [PATCH 2/6] drm/i915: Check for integer truncation on scatterlist creation

[Gwan-gyeong Mun]

From: Chris Wilson 

There is an impedance mismatch between the scatterlist API using unsigned
int and our memory/page accounting in unsigned long. That is we may try
to create a scatterlist for a large object that overflows returning a
small table into which we try to fit very many pages. As the object size
is under control of userspace, we have to be prudent and catch the
conversion errors.

To catch the implicit truncation as we switch from unsigned long into the
scatterlist's unsigned int, we use our overflows_type check and report
E2BIG prior to the operation. This is already used in our create ioctls to
indicate if the uABI request is simply too large for the backing store.
Failing that type check, we have a second check at sg_alloc_table time
to make sure the values we are passing into the scatterlist API are not
truncated.

It uses pgoff_t for locals that are dealing with page indices, in this
case, the page count is the limit of the page index.
And it adds and uses safe_conversion() macro which performs a type
conversion (cast) of an integer value into a new variable, checking that
the destination is large enough to hold the source value.

Signed-off-by: Chris Wilson 
Signed-off-by: Gwan-gyeong Mun 
Cc: Tvrtko Ursulin 
Cc: Brian Welty 
Cc: Matthew Auld 
Cc: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_internal.c |  6 --
 drivers/gpu/drm/i915/gem/i915_gem_object.h   |  3 ---
 drivers/gpu/drm/i915/gem/i915_gem_phys.c |  4 
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c|  5 -
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c  |  4 
 drivers/gpu/drm/i915/gem/i915_gem_userptr.c  |  5 -
 drivers/gpu/drm/i915/gvt/dmabuf.c|  9 +
 drivers/gpu/drm/i915/i915_scatterlist.h  |  8 
 drivers/gpu/drm/i915/i915_utils.h| 12 
 9 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c 
b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index c698f95af15f..ff2e6e780631 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -37,10 +37,13 @@ static int i915_gem_object_get_pages_internal(struct 
drm_i915_gem_object *obj)
struct sg_table *st;
struct scatterlist *sg;
unsigned int sg_page_sizes;
-   unsigned int npages;
+   pgoff_t npages; /* restricted by sg_alloc_table */
int max_order;
gfp_t gfp;
 
+   if (!safe_conversion(&npages, obj->base.size >> PAGE_SHIFT))
+   return -E2BIG;
+
max_order = MAX_ORDER;
 #ifdef CONFIG_SWIOTLB
if (is_swiotlb_active(obj->base.dev->dev)) {
@@ -67,7 +70,6 @@ static int i915_gem_object_get_pages_internal(struct 
drm_i915_gem_object *obj)
if (!st)
return -ENOMEM;
 
-   npages = obj->base.size / PAGE_SIZE;
if (sg_alloc_table(st, npages, GFP_KERNEL)) {
kfree(st);
return -ENOMEM;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 22c4ba0cd106..551e4293d19c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -26,9 +26,6 @@ enum intel_region_id;
  * this and catch if we ever need to fix it. In the meantime, if you do
  * spot such a local variable, please consider fixing!
  *
- * Aside from our own locals (for which we have no excuse!):
- * - sg_table embeds unsigned int for nents
- *
  * We can check for invalidly typed locals with typecheck(), see for example
  * i915_gem_object_get_sg().
  */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c 
b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index 0d0e46dae559..88ba7266a3a5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -28,6 +28,10 @@ static int i915_gem_object_get_pages_phys(struct 
drm_i915_gem_object *obj)
void *dst;
int i;
 
+   /* Contiguous chunk, with a single scatterlist element */
+   if (overflows_type(obj->base.size, sg->length))
+   return -E2BIG;
+
if (GEM_WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
return -EINVAL;
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c 
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 955844f19193..e77f9ada31a3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -193,13 +193,16 @@ static int shmem_get_pages(struct drm_i915_gem_object 
*obj)
struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct intel_memory_region *mem = obj->mm.region;
struct address_space *mapping = obj->base.filp->f_mapping;
-   const unsigned long page_count = obj->base.size / PAGE_SIZE;
unsigned int max_segment = i915_sg_segment_size();
struct sg_table *st;
struct sgt_iter sgt_iter;
+   pgoff_t page_count;
struct page *page;
in

[Intel-gfx] [PATCH 1/6] drm/i915/gem: Typecheck page lookups

[Gwan-gyeong Mun]

From: Chris Wilson 

We need to check that we avoid integer overflows when looking up a page,
and so fix all the instances where we have mistakenly used a plain
integer instead of a more suitable long. Be pedantic and add integer
typechecking to the lookup so that we can be sure that we are safe.
And it also uses pgoff_t as our page lookups must remain compatible with
the page cache, pgoff_t is currently exactly unsigned long.

Signed-off-by: Chris Wilson 
Signed-off-by: Gwan-gyeong Mun 
Cc: Tvrtko Ursulin 
Cc: Matthew Auld 
Cc: Thomas Hellström 
---
 drivers/gpu/drm/i915/gem/i915_gem_object.c|  7 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.h| 67 ++-
 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 25 ---
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c   |  2 +-
 .../drm/i915/gem/selftests/i915_gem_context.c | 12 ++--
 .../drm/i915/gem/selftests/i915_gem_mman.c|  8 +--
 .../drm/i915/gem/selftests/i915_gem_object.c  |  8 +--
 drivers/gpu/drm/i915/i915_gem.c   | 18 +++--
 drivers/gpu/drm/i915/i915_utils.h |  6 ++
 drivers/gpu/drm/i915/i915_vma.c   |  8 +--
 10 files changed, 106 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 06b1b188ce5a..a5af74f78d57 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -421,10 +421,11 @@ void __i915_gem_object_invalidate_frontbuffer(struct 
drm_i915_gem_object *obj,
 static void
 i915_gem_object_read_from_page_kmap(struct drm_i915_gem_object *obj, u64 
offset, void *dst, int size)
 {
+   pgoff_t idx = offset >> PAGE_SHIFT;
void *src_map;
void *src_ptr;
 
-   src_map = kmap_atomic(i915_gem_object_get_page(obj, offset >> 
PAGE_SHIFT));
+   src_map = kmap_atomic(i915_gem_object_get_page(obj, idx));
 
src_ptr = src_map + offset_in_page(offset);
if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ))
@@ -437,9 +438,10 @@ i915_gem_object_read_from_page_kmap(struct 
drm_i915_gem_object *obj, u64 offset,
 static void
 i915_gem_object_read_from_page_iomap(struct drm_i915_gem_object *obj, u64 
offset, void *dst, int size)
 {
+   pgoff_t idx = offset >> PAGE_SHIFT;
+   dma_addr_t dma = i915_gem_object_get_dma_address(obj, idx);
void __iomem *src_map;
void __iomem *src_ptr;
-   dma_addr_t dma = i915_gem_object_get_dma_address(obj, offset >> 
PAGE_SHIFT);
 
src_map = io_mapping_map_wc(&obj->mm.region->iomap,
dma - obj->mm.region->region.start,
@@ -468,6 +470,7 @@ i915_gem_object_read_from_page_iomap(struct 
drm_i915_gem_object *obj, u64 offset
  */
 int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, u64 
offset, void *dst, int size)
 {
+   GEM_BUG_ON(overflows_type(offset >> PAGE_SHIFT, pgoff_t));
GEM_BUG_ON(offset >= obj->base.size);
GEM_BUG_ON(offset_in_page(offset) > PAGE_SIZE - size);
GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index e11d82a9f7c3..22c4ba0cd106 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -27,8 +27,10 @@ enum intel_region_id;
  * spot such a local variable, please consider fixing!
  *
  * Aside from our own locals (for which we have no excuse!):
- * - sg_table embeds unsigned int for num_pages
- * - get_user_pages*() mixed ints with longs
+ * - sg_table embeds unsigned int for nents
+ *
+ * We can check for invalidly typed locals with typecheck(), see for example
+ * i915_gem_object_get_sg().
  */
 #define GEM_CHECK_SIZE_OVERFLOW(sz) \
GEM_WARN_ON((sz) >> PAGE_SHIFT > INT_MAX)
@@ -366,41 +368,70 @@ int i915_gem_object_set_tiling(struct drm_i915_gem_object 
*obj,
 struct scatterlist *
 __i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
 struct i915_gem_object_page_iter *iter,
-unsigned int n,
-unsigned int *offset, bool dma);
+pgoff_t  n,
+unsigned int *offset);
+
+#define __i915_gem_object_get_sg(obj, it, n, offset) ({ \
+   exactly_pgoff_t(n); \
+   (__i915_gem_object_get_sg)(obj, it, n, offset); \
+})
 
 static inline struct scatterlist *
-i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
-  unsigned int n,
+i915_gem_object_get_sg(struct drm_i915_gem_object *obj, pgoff_t n,
   unsigned int *offset)
 {
-   return __i915_gem_object_get_sg(obj, &obj->mm.get_page, n, offset, 
false);
+   return __i915_gem_object_get_sg(obj, &obj->mm.get_page, n, offset);
 }
 
+#define i915_gem_object_get_sg(obj, n, offset) ({ \
+   exactly_pgoff_t(n); \
+   (i915_gem_object_get_sg)(obj, n, offset); \
+})
+
 static inline struct scatterlist *

[Intel-gfx] [PATCH 0/6] Fixes integer overflow or integer truncation issues in page lookups, ttm place configuration and scatterlist creation

[Gwan-gyeong Mun]

This patch series fixes integer overflow or integer truncation issues in
page lookups, ttm place configuration and scatterlist creation, etc.
We need to check that we avoid integer overflows when looking up a page,
and so fix all the instances where we have mistakenly used a plain integer
instead of a more suitable long.
And there is an impedance mismatch between the scatterlist API using
unsigned int and our memory/page accounting in unsigned long. That is we
may try to create a scatterlist for a large object that overflows returning
a small table into which we try to fit very many pages. As the object size
is under the control of userspace, we have to be prudent and catch the
conversion errors. To catch the implicit truncation as we switch from
unsigned long into the scatterlist's unsigned int, we use our overflows_type
check and report E2BIG prior to the operation. This is already used in
our create ioctls to indicate if the uABI request is simply too large for
the backing store. 
And ttm place also has the same problem with scatterlist creation,
and we fix the integer truncation problem with the way approached by
scatterlist creation.
And It corrects the error code to return -E2BIG when creating gem objects
using ttm or shmem, if the size is too large in each case.

Testcase: igt@gem_create@create-massive
Testcase: igt@gem_userptr_blits@input-checking
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4991
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5411
Cc: Chris Wilson 
Cc: Matthew Auld 
Cc: Thomas Hellström 

Chris Wilson (3):
  drm/i915/gem: Typecheck page lookups
  drm/i915: Check for integer truncation on scatterlist creation
  drm/i915: Remove truncation warning for large objects

Gwan-gyeong Mun (3):
  drm/i915: Check for integer truncation on the configuration of ttm
place
  drm/i915: Check if the size is too big while creating shmem file
  drm/i915: Use error code as -E2BIG when the size of gem ttm object is
too large

 drivers/gpu/drm/i915/gem/i915_gem_internal.c  |  6 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.c|  7 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.h| 77 +++
 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 25 +++---
 drivers/gpu/drm/i915/gem/i915_gem_phys.c  |  4 +
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 14 +++-
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c   | 29 ++-
 drivers/gpu/drm/i915/gem/i915_gem_userptr.c   |  5 +-
 .../drm/i915/gem/selftests/i915_gem_context.c | 12 +--
 .../drm/i915/gem/selftests/i915_gem_mman.c|  8 +-
 .../drm/i915/gem/selftests/i915_gem_object.c  |  8 +-
 drivers/gpu/drm/i915/gvt/dmabuf.c |  9 ++-
 drivers/gpu/drm/i915/i915_gem.c   | 18 -
 drivers/gpu/drm/i915/i915_scatterlist.h   |  8 ++
 drivers/gpu/drm/i915/i915_utils.h | 18 +
 drivers/gpu/drm/i915/i915_vma.c   |  8 +-
 drivers/gpu/drm/i915/intel_region_ttm.c   | 16 +++-
 17 files changed, 189 insertions(+), 83 deletions(-)

-- 
2.34.1

Re: [Intel-gfx] [PATCH] drm/i915/regs: split out intel audio register definitions

[Jani Nikula]

On Thu, 02 Jun 2022, Matt Roper  wrote:
> On Thu, Jun 02, 2022 at 12:45:42PM +0300, Jani Nikula wrote:
>> Split out audio registers to a header of its own to reduce the size of
>> i915_reg.h.
>> 
>> TODO: Remove direct audio register access from intel_ddi.c. However,
>> unification of audio get config is cumbersome due to the audio enable
>> bit being in the DP or HDMI registers on older platforms.
>> 
>> Signed-off-by: Jani Nikula 
>
> Reviewed-by: Matt Roper 

Thanks, pushed to drm-intel-next.

BR,
Jani.


>
>> ---
>>  drivers/gpu/drm/i915/display/intel_audio.c|   1 +
>>  .../gpu/drm/i915/display/intel_audio_regs.h   | 160 ++
>>  drivers/gpu/drm/i915/display/intel_ddi.c  |   1 +
>>  drivers/gpu/drm/i915/i915_reg.h   | 151 -
>>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |   2 +
>>  5 files changed, 164 insertions(+), 151 deletions(-)
>>  create mode 100644 drivers/gpu/drm/i915/display/intel_audio_regs.h
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
>> b/drivers/gpu/drm/i915/display/intel_audio.c
>> index f0f0dfce27ce..6c9ee905f132 100644
>> --- a/drivers/gpu/drm/i915/display/intel_audio.c
>> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
>> @@ -30,6 +30,7 @@
>>  #include "i915_drv.h"
>>  #include "intel_atomic.h"
>>  #include "intel_audio.h"
>> +#include "intel_audio_regs.h"
>>  #include "intel_cdclk.h"
>>  #include "intel_crtc.h"
>>  #include "intel_de.h"
>> diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h 
>> b/drivers/gpu/drm/i915/display/intel_audio_regs.h
>> new file mode 100644
>> index ..d1e5844e3484
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h
>> @@ -0,0 +1,160 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2022 Intel Corporation
>> + */
>> +
>> +#ifndef __INTEL_AUDIO_REGS_H__
>> +#define __INTEL_AUDIO_REGS_H__
>> +
>> +#include "i915_reg_defs.h"
>> +
>> +#define G4X_AUD_VID_DID 
>> _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
>> +#define   INTEL_AUDIO_DEVCL 0x808629FB
>> +#define   INTEL_AUDIO_DEVBLC0x80862801
>> +#define   INTEL_AUDIO_DEVCTG0x80862802
>> +
>> +#define G4X_AUD_CNTL_ST _MMIO(0x620B4)
>> +#define   G4X_ELDV_DEVCL_DEVBLC (1 << 13)
>> +#define   G4X_ELDV_DEVCTG   (1 << 14)
>> +#define   G4X_ELD_ADDR_MASK (0xf << 5)
>> +#define   G4X_ELD_ACK   (1 << 4)
>> +#define G4X_HDMIW_HDMIEDID  _MMIO(0x6210C)
>> +
>> +#define _IBX_HDMIW_HDMIEDID_A   0xE2050
>> +#define _IBX_HDMIW_HDMIEDID_B   0xE2150
>> +#define IBX_HDMIW_HDMIEDID(pipe)_MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, 
>> \
>> +  _IBX_HDMIW_HDMIEDID_B)
>> +#define _IBX_AUD_CNTL_ST_A  0xE20B4
>> +#define _IBX_AUD_CNTL_ST_B  0xE21B4
>> +#define IBX_AUD_CNTL_ST(pipe)   _MMIO_PIPE(pipe, 
>> _IBX_AUD_CNTL_ST_A, \
>> +  _IBX_AUD_CNTL_ST_B)
>> +#define   IBX_ELD_BUFFER_SIZE_MASK  (0x1f << 10)
>> +#define   IBX_ELD_ADDRESS_MASK  (0x1f << 5)
>> +#define   IBX_ELD_ACK   (1 << 4)
>> +#define IBX_AUD_CNTL_ST2_MMIO(0xE20C0)
>> +#define   IBX_CP_READY(port)((1 << 1) << (((port) - 1) * 4))
>> +#define   IBX_ELD_VALID(port)   ((1 << 0) << (((port) - 1) * 4))
>> +
>> +#define _CPT_HDMIW_HDMIEDID_A   0xE5050
>> +#define _CPT_HDMIW_HDMIEDID_B   0xE5150
>> +#define CPT_HDMIW_HDMIEDID(pipe)_MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, 
>> _CPT_HDMIW_HDMIEDID_B)
>> +#define _CPT_AUD_CNTL_ST_A  0xE50B4
>> +#define _CPT_AUD_CNTL_ST_B  0xE51B4
>> +#define CPT_AUD_CNTL_ST(pipe)   _MMIO_PIPE(pipe, 
>> _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
>> +#define CPT_AUD_CNTRL_ST2   _MMIO(0xE50C0)
>> +
>> +#define _VLV_HDMIW_HDMIEDID_A   (VLV_DISPLAY_BASE + 0x62050)
>> +#define _VLV_HDMIW_HDMIEDID_B   (VLV_DISPLAY_BASE + 0x62150)
>> +#define VLV_HDMIW_HDMIEDID(pipe)_MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, 
>> _VLV_HDMIW_HDMIEDID_B)
>> +#define _VLV_AUD_CNTL_ST_A  (VLV_DISPLAY_BASE + 0x620B4)
>> +#define _VLV_AUD_CNTL_ST_B  (VLV_DISPLAY_BASE + 0x621B4)
>> +#define VLV_AUD_CNTL_ST(pipe)   _MMIO_PIPE(pipe, 
>> _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
>> +#define VLV_AUD_CNTL_ST2_MMIO(VLV_DISPLAY_BASE + 0x620C0)
>> +
>> +#define _IBX_AUD_CONFIG_A   0xe2000
>> +#define _IBX_AUD_CONFIG_B   0xe2100
>> +#define IBX_AUD_CFG(pipe)   _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, 
>> _IBX_AUD_CONFIG_B)
>> +#define _CPT_AUD_CONFIG_A   0xe5000
>> +#define _CPT_AUD_CONFIG_B   0xe5100
>> +#define CPT_AUD_CFG(pipe)   _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, 
>> _CPT_AUD_CONFIG_B)
>> +#define _VLV_AUD_CONFIG_A   (VLV_DISPLAY_BASE + 0x62000

Re: [Intel-gfx] [PATCH v2 3/3] drm/i915: Parse max link rate from the eDP BDB block

[Jani Nikula]

On Thu, 02 Jun 2022, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> The eDP BDB block has gained yet another max link rate field.
> Let's parse it and consult it during the source rate filtering.
>
> v2: *20 instead of *2 to get the correct units (Jani)

Failed to mention the same issue here as in the previous patch, but
yeah. :)

BR,
Jani.

>
> Reviewed-by: Jani Nikula 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c |  4 
>  .../drm/i915/display/intel_display_types.h|  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c   | 23 +--
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  1 +
>  4 files changed, 27 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 425e91d8cd2f..aaea27fe5d16 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1461,6 +1461,10 @@ parse_edp(struct drm_i915_private *i915,
>  
>   panel->vbt.edp.drrs_msa_timing_delay =
>   (edp->sdrrs_msa_timing_delay >> (panel_type * 2)) & 3;
> +
> + if (i915->vbt.version >= 244)
> + panel->vbt.edp.max_link_rate =
> + edp->edp_max_port_link_rate[panel_type] * 20;
>  }
>  
>  static void
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9b44358e8d9e..8b0949b6dc75 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -300,6 +300,7 @@ struct intel_vbt_panel_data {
>   enum drrs_type drrs_type;
>  
>   struct {
> + int max_link_rate;
>   int rate;
>   int lanes;
>   int preemphasis;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 03af93ef9e93..8ff875ab3b37 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -408,6 +408,26 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp)
>   return 81;
>  }
>  
> +static int vbt_max_link_rate(struct intel_dp *intel_dp)
> +{
> + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + int max_rate;
> +
> + max_rate = intel_bios_dp_max_link_rate(encoder);
> +
> + if (intel_dp_is_edp(intel_dp)) {
> + struct intel_connector *connector = 
> intel_dp->attached_connector;
> + int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
> +
> + if (max_rate && edp_max_rate)
> + max_rate = min(max_rate, edp_max_rate);
> + else if (edp_max_rate)
> + max_rate = edp_max_rate;
> + }
> +
> + return max_rate;
> +}
> +
>  static void
>  intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
> @@ -429,7 +449,6 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>   162000, 27
>   };
>   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct intel_encoder *encoder = &dig_port->base;
>   struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>   const int *source_rates;
>   int size, max_rate = 0, vbt_max_rate;
> @@ -465,7 +484,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>   size = ARRAY_SIZE(g4x_rates);
>   }
>  
> - vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
> + vbt_max_rate = vbt_max_link_rate(intel_dp);
>   if (max_rate && vbt_max_rate)
>   max_rate = min(max_rate, vbt_max_rate);
>   else if (vbt_max_rate)
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 58aee0a040cf..f8e5097222f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -697,6 +697,7 @@ struct bdb_edp {
>   u16 apical_enable;  /* 203 */
>   struct edp_apical_params apical_params[16]; /* 203 */
>   u16 edp_fast_link_training_rate[16];/* 224 */
> + u16 edp_max_port_link_rate[16]; /* 244 */
>  } __packed;
>  
>  /*

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Update eDP fast link training link rate parsing

[Jani Nikula]

On Thu, 02 Jun 2022, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> We're not parsing the 5.4 Gbps value for the old eDP fast link
> training link rate, nor are we parsing the new fast link training
> link rate field. Remedy both.
>
> Also we'll now use the actual link rate instead of the DPCD BW
> register value.
>
> Note that we're not even using this information for anything
> currently, so should perhaps just nuke it all unless someone
> is planning on implementing fast link training finally...
>
> v2: Stop using the DPCD BW values (Jani)
> *20 instead of *2 to get the rate in correct units (Jani)
>
> Cc: Jani Nikula 
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Jani Nikula 

> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 32 ---
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  1 +
>  2 files changed, 21 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index c42b9e7d0dce..425e91d8cd2f 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1367,18 +1367,26 @@ parse_edp(struct drm_i915_private *i915,
>  
>   panel->vbt.edp.pps = *edp_pps;
>  
> - switch (edp_link_params->rate) {
> - case EDP_RATE_1_62:
> - panel->vbt.edp.rate = DP_LINK_BW_1_62;
> - break;
> - case EDP_RATE_2_7:
> - panel->vbt.edp.rate = DP_LINK_BW_2_7;
> - break;
> - default:
> - drm_dbg_kms(&i915->drm,
> - "VBT has unknown eDP link rate value %u\n",
> -  edp_link_params->rate);
> - break;
> + if (i915->vbt.version >= 224) {
> + panel->vbt.edp.rate =
> + edp->edp_fast_link_training_rate[panel_type] * 20;
> + } else {
> + switch (edp_link_params->rate) {
> + case EDP_RATE_1_62:
> + panel->vbt.edp.rate = 162000;
> + break;
> + case EDP_RATE_2_7:
> + panel->vbt.edp.rate = 27;
> + break;
> + case EDP_RATE_5_4:
> + panel->vbt.edp.rate = 54;
> + break;
> + default:
> + drm_dbg_kms(&i915->drm,
> + "VBT has unknown eDP link rate value %u\n",
> + edp_link_params->rate);
> + break;
> + }
>   }
>  
>   switch (edp_link_params->lanes) {
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 14f1e1cc92c5..58aee0a040cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -638,6 +638,7 @@ struct bdb_sdvo_panel_dtds {
>  #define EDP_30BPP2
>  #define EDP_RATE_1_620
>  #define EDP_RATE_2_7 1
> +#define EDP_RATE_5_4 2
>  #define EDP_LANE_1   0
>  #define EDP_LANE_2   1
>  #define EDP_LANE_4   3

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [igt-dev] [PATCH v3 i-g-t 1/2] include/drm-uapi: Update to latest i915_drm.h

[Petri Latvala]

On Thu, Jun 02, 2022 at 05:54:03PM -0700, john.c.harri...@intel.com wrote:
> From: John Harrison 
> 
> Update to the latest master version of the DRM UAPI header file.
> 
> NB: Had to remove '__user' keywords as they do not appear to be
> supported outside of kernel builds.
> 
> Signed-off-by: John Harrison 
> ---
>  include/drm-uapi/i915_drm.h | 410 
>  1 file changed, 318 insertions(+), 92 deletions(-)
> 
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index 9c9e1afa61ba..5d4166eb80a3 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -24,8 +24,8 @@
>   *
>   */
>  
> -#ifndef _I915_DRM_H_
> -#define _I915_DRM_H_
> +#ifndef _UAPI_I915_DRM_H_
> +#define _UAPI_I915_DRM_H_

This and the note about having to remove __user tells me you didn't
get this header through `make headers_install`.

Also please include the used kernel sha in the commit message.

I tried to replicate this with the current drm-tip version and there
are some differences. Most probably because of not using
headers_install for this patch. I don't know what branch 'master
version' refers to.


-- 
Petri Latvala



>  
>  #include "drm.h"
>  
> @@ -75,7 +75,7 @@ extern "C" {
>   * redefine the interface more easily than an ever growing struct of
>   * increasing complexity, and for large parts of that interface to be
>   * entirely optional. The downside is more pointer chasing; chasing across
> - * the boundary with pointers encapsulated inside u64.
> + * the __user boundary with pointers encapsulated inside u64.
>   *
>   * Example chaining:
>   *
> @@ -154,25 +154,77 @@ enum i915_mocs_table_index {
>   I915_MOCS_CACHED,
>  };
>  
> -/*
> +/**
> + * enum drm_i915_gem_engine_class - uapi engine type enumeration
> + *
>   * Different engines serve different roles, and there may be more than one
> - * engine serving each role. enum drm_i915_gem_engine_class provides a
> - * classification of the role of the engine, which may be used when 
> requesting
> - * operations to be performed on a certain subset of engines, or for 
> providing
> - * information about that group.
> + * engine serving each role.  This enum provides a classification of the role
> + * of the engine, which may be used when requesting operations to be 
> performed
> + * on a certain subset of engines, or for providing information about that
> + * group.
>   */
>  enum drm_i915_gem_engine_class {
> + /**
> +  * @I915_ENGINE_CLASS_RENDER:
> +  *
> +  * Render engines support instructions used for 3D, Compute (GPGPU),
> +  * and programmable media workloads.  These instructions fetch data and
> +  * dispatch individual work items to threads that operate in parallel.
> +  * The threads run small programs (called "kernels" or "shaders") on
> +  * the GPU's execution units (EUs).
> +  */
>   I915_ENGINE_CLASS_RENDER= 0,
> +
> + /**
> +  * @I915_ENGINE_CLASS_COPY:
> +  *
> +  * Copy engines (also referred to as "blitters") support instructions
> +  * that move blocks of data from one location in memory to another,
> +  * or that fill a specified location of memory with fixed data.
> +  * Copy engines can perform pre-defined logical or bitwise operations
> +  * on the source, destination, or pattern data.
> +  */
>   I915_ENGINE_CLASS_COPY  = 1,
> +
> + /**
> +  * @I915_ENGINE_CLASS_VIDEO:
> +  *
> +  * Video engines (also referred to as "bit stream decode" (BSD) or
> +  * "vdbox") support instructions that perform fixed-function media
> +  * decode and encode.
> +  */
>   I915_ENGINE_CLASS_VIDEO = 2,
> +
> + /**
> +  * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
> +  *
> +  * Video enhancement engines (also referred to as "vebox") support
> +  * instructions related to image enhancement.
> +  */
>   I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
>  
> - /* should be kept compact */
> + /**
> +  * @I915_ENGINE_CLASS_COMPUTE:
> +  *
> +  * Compute engines support a subset of the instructions available
> +  * on render engines:  compute engines support Compute (GPGPU) and
> +  * programmable media workloads, but do not support the 3D pipeline.
> +  */
> + I915_ENGINE_CLASS_COMPUTE   = 4,
> +
> + /* Values in this enum should be kept compact. */
>  
> + /**
> +  * @I915_ENGINE_CLASS_INVALID:
> +  *
> +  * Placeholder value to represent an invalid engine class assignment.
> +  */
>   I915_ENGINE_CLASS_INVALID   = -1
>  };
>  
> -/*
> +/**
> + * struct i915_engine_class_instance - Engine class/instance identifier
> + *
>   * There may be more than one engine fulfilling any role within the system.
>   * Each engine of a class is given a unique instance number and therefore
>   * any engine can be specified by its class:instance tuplet. APIs that allow
> @@ -180,10 +232,21 @@ en

Re: [Intel-gfx] [RFC v3 1/3] drm/doc/rfc: VM_BIND feature design document

[Lionel Landwerlin]

On 02/06/2022 23:35, Jason Ekstrand wrote:
On Thu, Jun 2, 2022 at 3:11 PM Niranjana Vishwanathapura 
 wrote:


On Wed, Jun 01, 2022 at 01:28:36PM -0700, Matthew Brost wrote:
>On Wed, Jun 01, 2022 at 05:25:49PM +0300, Lionel Landwerlin wrote:
>> On 17/05/2022 21:32, Niranjana Vishwanathapura wrote:
>> > +VM_BIND/UNBIND ioctl will immediately start
binding/unbinding the mapping in an
>> > +async worker. The binding and unbinding will work like a
special GPU engine.
>> > +The binding and unbinding operations are serialized and will
wait on specified
>> > +input fences before the operation and will signal the output
fences upon the
>> > +completion of the operation. Due to serialization,
completion of an operation
>> > +will also indicate that all previous operations are also
complete.
>>
>> I guess we should avoid saying "will immediately start
binding/unbinding" if
>> there are fences involved.
>>
>> And the fact that it's happening in an async worker seem to
imply it's not
>> immediate.
>>

Ok, will fix.
This was added because in earlier design binding was deferred
until next execbuff.
But now it is non-deferred (immediate in that sense). But yah,
this is confusing
and will fix it.

>>
>> I have a question on the behavior of the bind operation when no
input fence
>> is provided. Let say I do :
>>
>> VM_BIND (out_fence=fence1)
>>
>> VM_BIND (out_fence=fence2)
>>
>> VM_BIND (out_fence=fence3)
>>
>>
>> In what order are the fences going to be signaled?
>>
>> In the order of VM_BIND ioctls? Or out of order?
>>
>> Because you wrote "serialized I assume it's : in order
>>

Yes, in the order of VM_BIND/UNBIND ioctls. Note that bind and
unbind will use
the same queue and hence are ordered.

>>
>> One thing I didn't realize is that because we only get one
"VM_BIND" engine,
>> there is a disconnect from the Vulkan specification.
>>
>> In Vulkan VM_BIND operations are serialized but per engine.
>>
>> So you could have something like this :
>>
>> VM_BIND (engine=rcs0, in_fence=fence1, out_fence=fence2)
>>
>> VM_BIND (engine=ccs0, in_fence=fence3, out_fence=fence4)
>>
>>
>> fence1 is not signaled
>>
>> fence3 is signaled
>>
>> So the second VM_BIND will proceed before the first VM_BIND.
>>
>>
>> I guess we can deal with that scenario in userspace by doing
the wait
>> ourselves in one thread per engines.
>>
>> But then it makes the VM_BIND input fences useless.
>>
>>
>> Daniel : what do you think? Should be rework this or just deal
with wait
>> fences in userspace?
>>
>
>My opinion is rework this but make the ordering via an engine
param optional.
>
>e.g. A VM can be configured so all binds are ordered within the VM
>
>e.g. A VM can be configured so all binds accept an engine
argument (in
>the case of the i915 likely this is a gem context handle) and binds
>ordered with respect to that engine.
>
>This gives UMDs options as the later likely consumes more KMD
resources
>so if a different UMD can live with binds being ordered within the VM
>they can use a mode consuming less resources.
>

I think we need to be careful here if we are looking for some out of
(submission) order completion of vm_bind/unbind.
In-order completion means, in a batch of binds and unbinds to be
completed in-order, user only needs to specify in-fence for the
first bind/unbind call and the our-fence for the last bind/unbind
call. Also, the VA released by an unbind call can be re-used by
any subsequent bind call in that in-order batch.

These things will break if binding/unbinding were to be allowed to
go out of order (of submission) and user need to be extra careful
not to run into pre-mature triggereing of out-fence and bind failing
as VA is still in use etc.

Also, VM_BIND binds the provided mapping on the specified address
space
(VM). So, the uapi is not engine/context specific.

We can however add a 'queue' to the uapi which can be one from the
pre-defined queues,
I915_VM_BIND_QUEUE_0
I915_VM_BIND_QUEUE_1
...
I915_VM_BIND_QUEUE_(N-1)

KMD will spawn an async work queue for each queue which will only
bind the mappings on that queue in the order of submission.
User can assign the queue to per engine or anything like that.

But again here, user need to be careful and not deadlock these
queues with circular dependency of fences.

I prefer adding this later an as extension based on whether it
is really helping with the implementation.


I can tell you right now that having everything on a single in-order 
queue will not get us the perf we want. What vulkan r

Re: [Intel-gfx] [RFC PATCH 4/5] drm/i915/display: prepend connector name to the backlight

[Jani Nikula]

On Fri, 03 Jun 2022, "Murthy, Arun R"  wrote:
>> On Thu, 02 Jun 2022, Animesh Manna  wrote:
>> > From: Arun R Murthy 
>> >
>> > With the enablement of dual eDP, there will have to exist two entries
>> > of backlight sysfs file. In order to avoid sysfs file name
>> > duplication, the file names are prepended with the connector name.
>>
>> Fixed by 20f85ef89d94 ("drm/i915/backlight: use unique backlight device
>> names") about a year ago.
>>
> This patches checks if the return value is -EEXIST and then acts accordingly, 
> but -EEXIST is not returned.
> struct kernfs_node *__kernfs_create_file(struct kernfs_node *parent,
>  const char *name,
>  umode_t mode, kuid_t uid, kgid_t gid,
>  loff_t size,
>  const struct kernfs_ops *ops,
>  void *priv, const void *ns,
>  struct lock_class_key *key)
> {
> struct kernfs_node *kn;
> unsigned flags;
> int rc;
>
> flags = KERNFS_FILE;
>
> kn = kernfs_new_node(parent, name, (mode & S_IALLUGO) | S_IFREG,
>  uid, gid, flags);
> if (!kn)
> return ERR_PTR(-ENOMEM);
>
> So the condition check with not be satisfied and the backlight registration 
> will fail for the 2nd backlight device.

But the file isn't added by kernfs_new_node(), it just allocates the
node. See the kernfs_add_one() later in __kernfs_create_file().

BR,
Jani.

>
> Thanks and Regards,
> Arun R Murthy
> 

-- 
Jani Nikula, Intel Open Source Graphics Center