[Intel-gfx] ✓ Fi.CI.BAT: success for Drop version numbers from firmware files (rev4)
== Series Details ==
Series: Drop version numbers from firmware files (rev4)
URL : https://patchwork.freedesktop.org/series/107340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12035 -> Patchwork_107340v4
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v4/index.html
Participating hosts (42 -> 35)
--
Missing(7): fi-hsw-4200u bat-dg1-5 bat-adlp-4 fi-ctg-p8600 bat-rplp-1
bat-dg2-10 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_107340v4 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][1] -> [INCOMPLETE][2] ([i915#4785])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v4/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][3] -> [DMESG-FAIL][4] ([i915#4528])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v4/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-bdw-5557u: [PASS][5] -> [INCOMPLETE][6] ([i915#146] /
[i915#6598])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v4/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bsw-nick:NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v4/fi-bsw-nick/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-rkl-11600: NOTRUN -> [SKIP][8] ([fdo#111827])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v4/fi-rkl-11600/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-bsw-nick:NOTRUN -> [SKIP][9] ([fdo#109271])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v4/fi-bsw-nick/igt@kms_pipe_crc_ba...@suspend-read-crc.html
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][10] ([fdo#109271] / [i915#4312] /
[i915#5594] / [i915#6246])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v4/fi-hsw-4770/igt@run...@aborted.html
- fi-pnv-d510:NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#2403] /
[i915#4312])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v4/fi-pnv-d510/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[INCOMPLETE][12] ([i915#5847]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v4/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][14] ([i915#4494] / [i915#4957]) ->
[PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v4/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- {bat-rpls-1}: [INCOMPLETE][16] ([i915#6257] / [i915#6380]) ->
[PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/bat-rpls-1/igt@i915_selftest@l...@requests.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v4/bat-rpls-1/igt@i915_selftest@l...@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [INCOMPLETE][18] ([i915#5982]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v4/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4785]: http
Re: [Intel-gfx] [PATCH 03/11] drm/edid: s/monitor_rage/vrr_range/
On Sat, Aug 27, 2022 at 12:34:53AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename info->monitor_range to info->vrr_range to actually
> reflect its usage.
Okay makes sense.
Reviewed-by: Manasi Navare
Manasi
>
> Cc: Manasi Navare
> Cc: Nicholas Kazlauskas
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Rodrigo Siqueira
> Cc: amd-...@lists.freedesktop.org
> Signed-off-by: Ville Syrjälä
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 -
> drivers/gpu/drm/drm_debugfs.c | 4 +--
> drivers/gpu/drm/drm_edid.c| 26 +--
> drivers/gpu/drm/i915/display/intel_vrr.c | 6 ++---
> include/drm/drm_connector.h | 4 +--
> 5 files changed, 26 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index e702f0d72d53..928b5b6541db 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -9921,8 +9921,8 @@ void amdgpu_dm_update_freesync_caps(struct
> drm_connector *connector,
> amdgpu_dm_connector->min_vfreq = 0;
> amdgpu_dm_connector->max_vfreq = 0;
> amdgpu_dm_connector->pixel_clock_mhz = 0;
> - connector->display_info.monitor_range.min_vfreq = 0;
> - connector->display_info.monitor_range.max_vfreq = 0;
> + connector->display_info.vrr_range.min_vfreq = 0;
> + connector->display_info.vrr_range.max_vfreq = 0;
> freesync_capable = false;
>
> goto update;
> @@ -9970,8 +9970,8 @@ void amdgpu_dm_update_freesync_caps(struct
> drm_connector *connector,
> amdgpu_dm_connector->pixel_clock_mhz =
> range->pixel_clock_mhz * 10;
>
> - connector->display_info.monitor_range.min_vfreq
> = range->min_vfreq;
> - connector->display_info.monitor_range.max_vfreq
> = range->max_vfreq;
> + connector->display_info.vrr_range.min_vfreq =
> range->min_vfreq;
> + connector->display_info.vrr_range.max_vfreq =
> range->max_vfreq;
>
> break;
> }
> @@ -9993,8 +9993,8 @@ void amdgpu_dm_update_freesync_caps(struct
> drm_connector *connector,
> if (amdgpu_dm_connector->max_vfreq -
> amdgpu_dm_connector->min_vfreq > 10)
> freesync_capable = true;
>
> - connector->display_info.monitor_range.min_vfreq =
> vsdb_info.min_refresh_rate_hz;
> - connector->display_info.monitor_range.max_vfreq =
> vsdb_info.max_refresh_rate_hz;
> + connector->display_info.vrr_range.min_vfreq =
> vsdb_info.min_refresh_rate_hz;
> + connector->display_info.vrr_range.max_vfreq =
> vsdb_info.max_refresh_rate_hz;
> }
> }
>
> diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c
> index 01ee3febb813..1437c798b122 100644
> --- a/drivers/gpu/drm/drm_debugfs.c
> +++ b/drivers/gpu/drm/drm_debugfs.c
> @@ -377,8 +377,8 @@ static int vrr_range_show(struct seq_file *m, void *data)
> if (connector->status != connector_status_connected)
> return -ENODEV;
>
> - seq_printf(m, "Min: %u\n",
> connector->display_info.monitor_range.min_vfreq);
> - seq_printf(m, "Max: %u\n",
> connector->display_info.monitor_range.max_vfreq);
> + seq_printf(m, "Min: %u\n", connector->display_info.vrr_range.min_vfreq);
> + seq_printf(m, "Max: %u\n", connector->display_info.vrr_range.max_vfreq);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index ac662495635c..4355d73632c3 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -6020,11 +6020,11 @@ static void drm_parse_cea_ext(struct drm_connector
> *connector,
> }
>
> static
> -void get_monitor_range(const struct detailed_timing *timing, void *c)
> +void get_vrr_range(const struct detailed_timing *timing, void *c)
> {
> struct detailed_mode_closure *closure = c;
> struct drm_display_info *info = &closure->connector->display_info;
> - struct drm_monitor_range_info *monitor_range = &info->monitor_range;
> + struct drm_monitor_range_info *vrr_range = &info->vrr_range;
> const struct detailed_non_pixel *data = &timing->data.other_data;
> const struct detailed_data_monitor_range *range = &data->data.range;
> const struct edid *edid = closure->drm_edid->edid;
> @@ -6044,19 +6044,19 @@ void get_monitor_range(const struct detailed_timing
> *timing, void *c)
> if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
> return;
>
> - monitor_range->min_vfreq = range->min_vfreq;
> - m
Re: [Intel-gfx] [PATCH 02/11] drm/edid: Clarify why we only accept the "range limits only" descriptor
On Sat, Aug 27, 2022 at 12:34:52AM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > The current comment fails to clarify why we only accept > the "range limits only" variant of the range descriptor. > Reword it to make some actual sense. > Thanks Ville for adding this description for monitor_range Reviewed-by: Manasi Navare Manasi > Cc: Manasi Navare > Cc: Nicholas Kazlauskas > Cc: Harry Wentland > Cc: Leo Li > Cc: Rodrigo Siqueira > Cc: amd-...@lists.freedesktop.org > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/drm_edid.c | 11 +++ > 1 file changed, 7 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > index 4005dab6147d..ac662495635c 100644 > --- a/drivers/gpu/drm/drm_edid.c > +++ b/drivers/gpu/drm/drm_edid.c > @@ -6033,10 +6033,13 @@ void get_monitor_range(const struct detailed_timing > *timing, void *c) > return; > > /* > - * Check for flag range limits only. If flag == 1 then > - * no additional timing information provided. > - * Default GTF, GTF Secondary curve and CVT are not > - * supported > + * These limits are used to determine the VRR refresh > + * rate range. Only the "range limits only" variant > + * of the range descriptor seems to guarantee that > + * any and all timings are accepted by the sink, as > + * opposed to just timings conforming to the indicated > + * formula (GTF/GTF2/CVT). Thus other variants of the > + * range descriptor are not accepted here. >*/ > if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) > return; > -- > 2.35.1 >
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Drop version numbers from firmware files (rev4)
== Series Details == Series: Drop version numbers from firmware files (rev4) URL : https://patchwork.freedesktop.org/series/107340/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Drop version numbers from firmware files (rev4)
== Series Details == Series: Drop version numbers from firmware files (rev4) URL : https://patchwork.freedesktop.org/series/107340/ State : warning == Summary == Error: dim checkpatch failed 42d234dc1dfa drm/i915/uc: Support for version reduced and multiple firmware files -:172: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #172: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:74: +#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_maj, guc_mmp) \ + fw_def(DG2, 0, guc_mmp(dg2, 70, 4, 1)) \ + fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 70, 1, 1)) \ + fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 69, 0, 3)) \ + fw_def(ALDERLAKE_S, 0, guc_mmp(tgl, 70, 1, 1)) \ + fw_def(ALDERLAKE_S, 0, guc_mmp(tgl, 69, 0, 3)) \ + fw_def(DG1, 0, guc_mmp(dg1, 70, 1, 1)) \ + fw_def(ROCKETLAKE, 0, guc_mmp(tgl, 70, 1, 1)) \ + fw_def(TIGERLAKE,0, guc_mmp(tgl, 70, 1, 1)) \ + fw_def(JASPERLAKE, 0, guc_mmp(ehl, 70, 1, 1)) \ + fw_def(ELKHARTLAKE, 0, guc_mmp(ehl, 70, 1, 1)) \ + fw_def(ICELAKE, 0, guc_mmp(icl, 70, 1, 1)) \ + fw_def(COMETLAKE,5, guc_mmp(cml, 70, 1, 1)) \ + fw_def(COMETLAKE,0, guc_mmp(kbl, 70, 1, 1)) \ + fw_def(COFFEELAKE, 0, guc_mmp(kbl, 70, 1, 1)) \ + fw_def(GEMINILAKE, 0, guc_mmp(glk, 70, 1, 1)) \ + fw_def(KABYLAKE, 0, guc_mmp(kbl, 70, 1, 1)) \ + fw_def(BROXTON, 0, guc_mmp(bxt, 70, 1, 1)) \ + fw_def(SKYLAKE, 0, guc_mmp(skl, 70, 1, 1)) -:172: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fw_def' - possible side-effects? #172: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:74: +#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_maj, guc_mmp) \ + fw_def(DG2, 0, guc_mmp(dg2, 70, 4, 1)) \ + fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 70, 1, 1)) \ + fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 69, 0, 3)) \ + fw_def(ALDERLAKE_S, 0, guc_mmp(tgl, 70, 1, 1)) \ + fw_def(ALDERLAKE_S, 0, guc_mmp(tgl, 69, 0, 3)) \ + fw_def(DG1, 0, guc_mmp(dg1, 70, 1, 1)) \ + fw_def(ROCKETLAKE, 0, guc_mmp(tgl, 70, 1, 1)) \ + fw_def(TIGERLAKE,0, guc_mmp(tgl, 70, 1, 1)) \ + fw_def(JASPERLAKE, 0, guc_mmp(ehl, 70, 1, 1)) \ + fw_def(ELKHARTLAKE, 0, guc_mmp(ehl, 70, 1, 1)) \ + fw_def(ICELAKE, 0, guc_mmp(icl, 70, 1, 1)) \ + fw_def(COMETLAKE,5, guc_mmp(cml, 70, 1, 1)) \ + fw_def(COMETLAKE,0, guc_mmp(kbl, 70, 1, 1)) \ + fw_def(COFFEELAKE, 0, guc_mmp(kbl, 70, 1, 1)) \ + fw_def(GEMINILAKE, 0, guc_mmp(glk, 70, 1, 1)) \ + fw_def(KABYLAKE, 0, guc_mmp(kbl, 70, 1, 1)) \ + fw_def(BROXTON, 0, guc_mmp(bxt, 70, 1, 1)) \ + fw_def(SKYLAKE, 0, guc_mmp(skl, 70, 1, 1)) -:172: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'guc_mmp' - possible side-effects? #172: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:74: +#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_maj, guc_mmp) \ + fw_def(DG2, 0, guc_mmp(dg2, 70, 4, 1)) \ + fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 70, 1, 1)) \ + fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 69, 0, 3)) \ + fw_def(ALDERLAKE_S, 0, guc_mmp(tgl, 70, 1, 1)) \ + fw_def(ALDERLAKE_S, 0, guc_mmp(tgl, 69, 0, 3)) \ + fw_def(DG1, 0, guc_mmp(dg1, 70, 1, 1)) \ + fw_def(ROCKETLAKE, 0, guc_mmp(tgl, 70, 1, 1)) \ + fw_def(TIGERLAKE,0, guc_mmp(tgl, 70, 1, 1)) \ + fw_def(JASPERLAKE, 0, guc_mmp(ehl, 70, 1, 1)) \ + fw_def(ELKHARTLAKE, 0, guc_mmp(ehl, 70, 1, 1)) \ + fw_def(ICELAKE, 0, guc_mmp(icl, 70, 1, 1)) \ + fw_def(COMETLAKE,5, guc_mmp(cml, 70, 1, 1)) \ + fw_def(COMETLAKE,0, guc_mmp(kbl, 70, 1, 1)) \ + fw_def(COFFEELAKE, 0, guc_mmp(kbl, 70, 1, 1)) \ + fw_def(GEMINILAKE, 0, guc_mmp(glk, 70, 1, 1)) \ + fw_def(KABYLAKE, 0, guc_mmp(kbl, 70, 1, 1)) \ + fw_def(BROXTON, 0, guc_mmp(bxt, 70, 1, 1)) \ + fw_def(SKYLAKE, 0, guc_mmp(skl, 70, 1, 1)) -:192: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #192: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:94: +#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp) \ + fw_def(ALDERLAKE_P, 0, huc_mmp(tgl, 7, 9, 3)) \ + fw_def(ALDERLAKE_S, 0, huc_mmp(tgl, 7, 9, 3)) \ + fw_def(DG1, 0, huc_mmp(dg1, 7, 9, 3)) \ + fw_def(ROCKETLAKE, 0, huc_mmp(tgl, 7, 9, 3)) \ + fw_def(TIGERLAKE,0, huc_mmp(tgl, 7, 9, 3)) \ + fw_def(JASPERLAKE, 0, huc_mmp(ehl, 9, 0, 0)) \ + fw_def(ELKHARTLAKE, 0, huc_mmp(ehl, 9, 0, 0)) \ + fw_def(ICELAKE, 0, huc_mmp(icl, 9, 0, 0)) \ + fw_def(COMETLAKE,5, huc_mmp(cml, 4, 0, 0)) \ + fw_def(COMETLAKE,0, huc_mmp(kbl, 4, 0, 0)) \ + fw_def(COFFEELAKE, 0, huc_mmp(kbl, 4, 0, 0)) \ + fw_def(GEMINILAKE, 0, huc_mmp(glk, 4, 0, 0)) \ + fw_def(K
Re: [Intel-gfx] [PATCH 01/11] drm/edid: Handle EDID 1.4 range descriptor h/vfreq offsets
On Sat, Aug 27, 2022 at 12:34:51AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> EDID 1.4 introduced some extra flags in the range
> descriptor to support min/max h/vfreq >= 255. Consult them
> to correctly parse the vfreq limits.
>
> Note that some combinations of the flags are documented
> as "reserved" (as are some other values in the descriptor)
> but explicitly checking for those doesn't seem particularly
> worthwile since we end up with bogus results whether we
> decode them or not.
>
> v2: Increase the storage to u16 to make it work (Jani)
> Note the "reserved" values situation (Jani)
> v3: Document the EDID version number in the defines
> Drop some bogus (u8) casts
>
> Cc: sta...@vger.kernel.org
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6519
> Reviewed-by: Jani Nikula
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_debugfs.c | 4 ++--
> drivers/gpu/drm/drm_edid.c| 24 ++--
> include/drm/drm_connector.h | 4 ++--
> include/drm/drm_edid.h| 5 +
> 4 files changed, 27 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c
> index 493922069c90..01ee3febb813 100644
> --- a/drivers/gpu/drm/drm_debugfs.c
> +++ b/drivers/gpu/drm/drm_debugfs.c
> @@ -377,8 +377,8 @@ static int vrr_range_show(struct seq_file *m, void *data)
> if (connector->status != connector_status_connected)
> return -ENODEV;
>
> - seq_printf(m, "Min: %u\n",
> (u8)connector->display_info.monitor_range.min_vfreq);
> - seq_printf(m, "Max: %u\n",
> (u8)connector->display_info.monitor_range.max_vfreq);
> + seq_printf(m, "Min: %u\n",
> connector->display_info.monitor_range.min_vfreq);
> + seq_printf(m, "Max: %u\n",
> connector->display_info.monitor_range.max_vfreq);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 90a5e26eafa8..4005dab6147d 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -6020,12 +6020,14 @@ static void drm_parse_cea_ext(struct drm_connector
> *connector,
> }
>
> static
> -void get_monitor_range(const struct detailed_timing *timing,
> -void *info_monitor_range)
> +void get_monitor_range(const struct detailed_timing *timing, void *c)
> {
> - struct drm_monitor_range_info *monitor_range = info_monitor_range;
> + struct detailed_mode_closure *closure = c;
> + struct drm_display_info *info = &closure->connector->display_info;
> + struct drm_monitor_range_info *monitor_range = &info->monitor_range;
> const struct detailed_non_pixel *data = &timing->data.other_data;
> const struct detailed_data_monitor_range *range = &data->data.range;
> + const struct edid *edid = closure->drm_edid->edid;
>
> if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
> return;
> @@ -6041,18 +6043,28 @@ void get_monitor_range(const struct detailed_timing
> *timing,
>
> monitor_range->min_vfreq = range->min_vfreq;
> monitor_range->max_vfreq = range->max_vfreq;
> +
> + if (edid->revision >= 4) {
> + if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
> + monitor_range->min_vfreq += 255;
> + if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
> + monitor_range->max_vfreq += 255;
Yes this makes sense. This looks like added for supporting HRR (high
refresh rate) panels.
Do you think we should mention that in the commit message or in the
comment in the code itself?
Other than that looks good to me:
Reviewed-by: Manasi Navare
Manasi
> + }
> }
>
> static void drm_get_monitor_range(struct drm_connector *connector,
> const struct drm_edid *drm_edid)
> {
> - struct drm_display_info *info = &connector->display_info;
> + const struct drm_display_info *info = &connector->display_info;
> + struct detailed_mode_closure closure = {
> + .connector = connector,
> + .drm_edid = drm_edid,
> + };
>
> if (!version_greater(drm_edid, 1, 1))
> return;
>
> - drm_for_each_detailed_block(drm_edid, get_monitor_range,
> - &info->monitor_range);
> + drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
>
> DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
> info->monitor_range.min_vfreq,
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 248206bbd975..56aee949c6fa 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -319,8 +319,8 @@ enum drm_panel_orientation {
> * EDID's detailed monitor range
> */
> struct drm_monitor_range_info {
> - u8 min_vfreq;
> - u8 max_vfreq;
> + u16 min_vfreq;
> + u16 max_vfreq;
> };
>
> /**
> diff --git a/incl
Re: [Intel-gfx] [PATCH][next] drm/i915/guc: Fix spelling mistake "heatbeat" -> "heartbeat"
On 8/26/2022 01:10, Colin Ian King wrote:
There is a spelling mistake in a drm_err message. Fix it.
Signed-off-by: Colin Ian King
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
index 01f8cd3c3134..d7857cf7c08f 100644
--- a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
@@ -61,7 +61,7 @@ static int intel_hang_guc(void *arg)
old_beat = engine->props.heartbeat_interval_ms;
ret = intel_engine_set_heartbeat(engine, BEAT_INTERVAL);
if (ret) {
- drm_err(>->i915->drm, "Failed to boost heatbeat interval:
%d\n", ret);
+ drm_err(>->i915->drm, "Failed to boost heartbeat interval:
%d\n", ret);
goto err;
}
[Intel-gfx] [PATCH v3 1/3] drm/i915/uc: Support for version reduced and multiple firmware files
From: John Harrison
There was a misunderstanding in how firmware file compatibility should
be managed within i915. This has been clarified as:
i915 must support all existing firmware releases forever
new minor firmware releases should replace prior versions
only backwards compatibility breaking releases should be a new file
This patch cleans up the single fallback file support that was added
as a quick fix emergency effort. That is now removed in preference to
supporting arbitrary numbers of firmware files per platform.
The patch also adds support for having GuC firmware files that are
named by major version only (because the major version indicates
backwards breaking changes that affect the KMD) and for having HuC
firmware files with no version number at all (because the KMD has no
interface requirements with the HuC).
For GuC, the driver will report via dmesg if the found file is older than
expected. For HuC, the KMD will no longer require updating for any new
HuC release so will not be able to report what the latest expected
version is.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 442 --
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 33 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 16 +-
5 files changed, 319 insertions(+), 186 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0d56b615bf78e..04393932623c7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1868,7 +1868,7 @@ int intel_guc_submission_init(struct intel_guc *guc)
if (guc->submission_initialized)
return 0;
- if (guc->fw.major_ver_found < 70) {
+ if (guc->fw.file_selected.major_ver < 70) {
ret = guc_lrc_desc_pool_create_v69(guc);
if (ret)
return ret;
@@ -2303,7 +2303,7 @@ static int register_context(struct intel_context *ce,
bool loop)
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_register(ce);
- if (guc->fw.major_ver_found >= 70)
+ if (guc->fw.file_selected.major_ver >= 70)
ret = register_context_v70(guc, ce, loop);
else
ret = register_context_v69(guc, ce, loop);
@@ -2315,7 +2315,7 @@ static int register_context(struct intel_context *ce,
bool loop)
set_context_registered(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
- if (guc->fw.major_ver_found >= 70)
+ if (guc->fw.file_selected.major_ver >= 70)
guc_context_policy_init_v70(ce, loop);
}
@@ -2921,7 +2921,7 @@ static void __guc_context_set_preemption_timeout(struct
intel_guc *guc,
u16 guc_id,
u32 preemption_timeout)
{
- if (guc->fw.major_ver_found >= 70) {
+ if (guc->fw.file_selected.major_ver >= 70) {
struct context_policy policy;
__guc_context_policy_start_klv(&policy, guc_id);
@@ -3186,7 +3186,7 @@ static int guc_context_alloc(struct intel_context *ce)
static void __guc_context_set_prio(struct intel_guc *guc,
struct intel_context *ce)
{
- if (guc->fw.major_ver_found >= 70) {
+ if (guc->fw.file_selected.major_ver >= 70) {
struct context_policy policy;
__guc_context_policy_start_klv(&policy, ce->guc_id.id);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index f2e7c82985efd..d965ac4832d60 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -436,8 +436,8 @@ static void print_fw_ver(struct intel_uc *uc, struct
intel_uc_fw *fw)
struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
drm_info(&i915->drm, "%s firmware %s version %u.%u\n",
-intel_uc_fw_type_repr(fw->type), fw->path,
-fw->major_ver_found, fw->minor_ver_found);
+intel_uc_fw_type_repr(fw->type), fw->file_selected.path,
+fw->file_selected.major_ver, fw->file_selected.minor_ver);
}
static int __uc_init_hw(struct intel_uc *uc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 58547292efa0a..610f36f1b989a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -41,7 +41,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
"%s firmware -> %s\n",
intel_uc_fw_type_repr(uc_fw->type),
status == INTEL_UC_FIRMWARE_SELECTED ?
-
[Intel-gfx] [PATCH v3 3/3] drm/i915/uc: Enable version reduced firmware files for newest platforms
From: John Harrison Going forwards, the intention is for GuC firmware files to be named for their major version only and HuC firmware files to have no version number in the name at all. This patch adds those entries for DG1/2 and ADL-P/S. Signed-off-by: John Harrison --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index af425916cdf64..78b1198bcf39b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -72,11 +72,14 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, * security fixes, etc. to be enabled. */ #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_maj, guc_mmp) \ - fw_def(DG2, 0, guc_mmp(dg2, 70, 4, 1)) \ + fw_def(DG2, 0, guc_maj(dg2, 70, 4)) \ + fw_def(ALDERLAKE_P, 0, guc_maj(adlp, 70, 1)) \ fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 70, 1, 1)) \ fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 69, 0, 3)) \ + fw_def(ALDERLAKE_S, 0, guc_maj(tgl, 70, 1)) \ fw_def(ALDERLAKE_S, 0, guc_mmp(tgl, 70, 1, 1)) \ fw_def(ALDERLAKE_S, 0, guc_mmp(tgl, 69, 0, 3)) \ + fw_def(DG1, 0, guc_maj(dg1, 70, 1)) \ fw_def(DG1, 0, guc_mmp(dg1, 70, 1, 1)) \ fw_def(ROCKETLAKE, 0, guc_mmp(tgl, 70, 1, 1)) \ fw_def(TIGERLAKE,0, guc_mmp(tgl, 70, 1, 1)) \ @@ -92,8 +95,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, fw_def(SKYLAKE, 0, guc_mmp(skl, 70, 1, 1)) #define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp) \ + fw_def(ALDERLAKE_P, 0, huc_raw(tgl)) \ fw_def(ALDERLAKE_P, 0, huc_mmp(tgl, 7, 9, 3)) \ + fw_def(ALDERLAKE_S, 0, huc_raw(tgl)) \ fw_def(ALDERLAKE_S, 0, huc_mmp(tgl, 7, 9, 3)) \ + fw_def(DG1, 0, huc_raw(dg1)) \ fw_def(DG1, 0, huc_mmp(dg1, 7, 9, 3)) \ fw_def(ROCKETLAKE, 0, huc_mmp(tgl, 7, 9, 3)) \ fw_def(TIGERLAKE,0, huc_mmp(tgl, 7, 9, 3)) \ -- 2.37.2
[Intel-gfx] [PATCH v3 2/3] drm/i915/uc: Add patch level version number support
From: John Harrison
With the move to un-versioned filenames, it becomes more difficult to
know exactly what version of a given firmware is being used. So add
the patch level version number to the debugfs output.
Also, support matching by patch level when selecting code paths for
firmware compatibility. While a patch level change cannot be backwards
breaking, it is potentially possible that a new feature only works
from a given patch level onwards (even though it was theoretically
added in an earlier version that bumped the major or minor version).
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +++---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 36 ++-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 6
drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 8 +++--
5 files changed, 47 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 04393932623c7..64c4e83153f47 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1868,7 +1868,7 @@ int intel_guc_submission_init(struct intel_guc *guc)
if (guc->submission_initialized)
return 0;
- if (guc->fw.file_selected.major_ver < 70) {
+ if (GET_UC_VER(guc) < MAKE_UC_VER(70, 0, 0)) {
ret = guc_lrc_desc_pool_create_v69(guc);
if (ret)
return ret;
@@ -2303,7 +2303,7 @@ static int register_context(struct intel_context *ce,
bool loop)
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_register(ce);
- if (guc->fw.file_selected.major_ver >= 70)
+ if (GET_UC_VER(guc) >= MAKE_UC_VER(70, 0, 0))
ret = register_context_v70(guc, ce, loop);
else
ret = register_context_v69(guc, ce, loop);
@@ -2315,7 +2315,7 @@ static int register_context(struct intel_context *ce,
bool loop)
set_context_registered(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
- if (guc->fw.file_selected.major_ver >= 70)
+ if (GET_UC_VER(guc) >= MAKE_UC_VER(70, 0, 0))
guc_context_policy_init_v70(ce, loop);
}
@@ -2921,7 +2921,7 @@ static void __guc_context_set_preemption_timeout(struct
intel_guc *guc,
u16 guc_id,
u32 preemption_timeout)
{
- if (guc->fw.file_selected.major_ver >= 70) {
+ if (GET_UC_VER(guc) >= MAKE_UC_VER(70, 0, 0)) {
struct context_policy policy;
__guc_context_policy_start_klv(&policy, guc_id);
@@ -3186,7 +3186,7 @@ static int guc_context_alloc(struct intel_context *ce)
static void __guc_context_set_prio(struct intel_guc *guc,
struct intel_context *ce)
{
- if (guc->fw.file_selected.major_ver >= 70) {
+ if (GET_UC_VER(guc) >= MAKE_UC_VER(70, 0, 0)) {
struct context_policy policy;
__guc_context_policy_start_klv(&policy, ce->guc_id.id);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index d965ac4832d60..abf4e142596d0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -435,9 +435,11 @@ static void print_fw_ver(struct intel_uc *uc, struct
intel_uc_fw *fw)
{
struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
- drm_info(&i915->drm, "%s firmware %s version %u.%u\n",
+ drm_info(&i915->drm, "%s firmware %s version %u.%u.%u\n",
intel_uc_fw_type_repr(fw->type), fw->file_selected.path,
-fw->file_selected.major_ver, fw->file_selected.minor_ver);
+fw->file_selected.major_ver,
+fw->file_selected.minor_ver,
+fw->file_selected.patch_ver);
}
static int __uc_init_hw(struct intel_uc *uc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 610f36f1b989a..af425916cdf64 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -447,10 +447,12 @@ static int check_gsc_manifest(const struct firmware *fw,
struct intel_uc_fw *uc_fw)
{
u32 *dw = (u32 *)fw->data;
- u32 version = dw[HUC_GSC_VERSION_DW];
+ u32 version_hi = dw[HUC_GSC_VERSION_HI_DW];
+ u32 version_lo = dw[HUC_GSC_VERSION_LO_DW];
- uc_fw->file_selected.major_ver = FIELD_GET(HUC_GSC_MAJOR_VER_MASK,
version);
- uc_fw->file_selected.minor_ver = FIELD_GET(HUC_GSC_MINOR_VER_MASK,
version);
+ uc_fw->file_selected.major_ver = FIELD_GET(HUC_GSC_MAJOR_VER_HI_MASK,
version_hi);
+ uc_fw->file_selected.minor_ver = FI
[Intel-gfx] [PATCH v3 0/3] Drop version numbers from firmware files
From: John Harrison Upstream direction is to include the bare minimum of version numbers in firmware files and to replace them in the repo rather than accumulating them. For HuC, that means going completely versionless. For GuC, the major version needs to be kept as that indicates a break in backwards compatibility with the KMD. v2: Fix a bunch of issues and add better documentation (some found in code review by Daniele, other through more thorough testing). v3: Fix GSC HuC version field and a comment type (review feedback from Daniele). Signed-off-by: John Harrison CC: Daniele Ceraolo Spurio John Harrison (3): drm/i915/uc: Support for version reduced and multiple firmware files drm/i915/uc: Add patch level version number support drm/i915/uc: Enable version reduced firmware files for newest platforms .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 8 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 468 -- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 39 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 8 +- drivers/gpu/drm/i915/i915_gpu_error.c | 16 +- 6 files changed, 358 insertions(+), 191 deletions(-) -- 2.37.2
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Cancel GuC engine busyness worker synchronously (rev3)
== Series Details ==
Series: drm/i915/guc: Cancel GuC engine busyness worker synchronously (rev3)
URL : https://patchwork.freedesktop.org/series/106738/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12035 -> Patchwork_106738v3
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v3/index.html
Participating hosts (42 -> 35)
--
Missing(7): fi-hsw-4200u bat-dg1-5 bat-adlp-4 fi-ctg-p8600 bat-rplp-1
bat-dg2-10 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_106738v3:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live:
- {bat-jsl-3}:NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v3/bat-jsl-3/igt@i915_selft...@live.html
* igt@i915_selftest@live@hangcheck:
- {bat-dg2-8}:[PASS][2] -> [INCOMPLETE][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/bat-dg2-8/igt@i915_selftest@l...@hangcheck.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v3/bat-dg2-8/igt@i915_selftest@l...@hangcheck.html
Known issues
Here are the changes found in Patchwork_106738v3 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][4] -> [INCOMPLETE][5] ([i915#4785])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v3/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bsw-nick:NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v3/fi-bsw-nick/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-bsw-nick:NOTRUN -> [SKIP][7] ([fdo#109271])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v3/fi-bsw-nick/igt@kms_pipe_crc_ba...@suspend-read-crc.html
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#4312] /
[i915#5594] / [i915#6246])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v3/fi-hsw-4770/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[INCOMPLETE][9] ([i915#5847]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v3/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@requests:
- {bat-rpls-1}: [INCOMPLETE][11] ([i915#6257] / [i915#6380]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/bat-rpls-1/igt@i915_selftest@l...@requests.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v3/bat-rpls-1/igt@i915_selftest@l...@requests.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
[i915#5847]: https://gitlab.freedesktop.org/drm/intel/issues/5847
[i915#6246]: https://gitlab.freedesktop.org/drm/intel/issues/6246
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6380]: https://gitlab.freedesktop.org/drm/intel/issues/6380
Build changes
-
* Linux: CI_DRM_12035 -> Patchwork_106738v3
CI-20190529: 20190529
CI_DRM_12035: 94f8134b5320a43800ca3ca50d1c387d66f75c6a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6636: 1298b5f0e1b3e010657ffba41d2e775fab028e08 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_106738v3: 94f8134b5320a43800ca3ca50d1c387d66f75c6a @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
db57e48b09cb drm/i915/guc: Cancel GuC engine busyness worker synchronously
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v3/index.html
Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/uc: Add patch level version number support
On 8/26/2022 16:54, Ceraolo Spurio, Daniele wrote:
On 8/25/2022 8:05 PM, john.c.harri...@intel.com wrote:
From: John Harrison
With the move to un-versioned filenames, it becomes more difficult to
know exactly what version of a given firmware is being used. So add
the patch level version number to the debugfs output.
Also, support matching by patch level when selecting code paths for
firmware compatibility. While a patch level change cannot be backwards
breaking, it is potentially possible that a new feature only works
from a given patch level onwards (even though it was theoretically
added in an earlier version that bumped the major or minor version).
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +++---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 36 ++-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 6
drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 8 +++--
5 files changed, 47 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 04393932623c7..64c4e83153f47 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1868,7 +1868,7 @@ int intel_guc_submission_init(struct intel_guc
*guc)
if (guc->submission_initialized)
return 0;
- if (guc->fw.file_selected.major_ver < 70) {
+ if (GET_UC_VER(guc) < MAKE_UC_VER(70, 0, 0)) {
ret = guc_lrc_desc_pool_create_v69(guc);
if (ret)
return ret;
@@ -2303,7 +2303,7 @@ static int register_context(struct
intel_context *ce, bool loop)
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_register(ce);
- if (guc->fw.file_selected.major_ver >= 70)
+ if (GET_UC_VER(guc) >= MAKE_UC_VER(70, 0, 0))
ret = register_context_v70(guc, ce, loop);
else
ret = register_context_v69(guc, ce, loop);
@@ -2315,7 +2315,7 @@ static int register_context(struct
intel_context *ce, bool loop)
set_context_registered(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
- if (guc->fw.file_selected.major_ver >= 70)
+ if (GET_UC_VER(guc) >= MAKE_UC_VER(70, 0, 0))
guc_context_policy_init_v70(ce, loop);
}
@@ -2921,7 +2921,7 @@ static void
__guc_context_set_preemption_timeout(struct intel_guc *guc,
u16 guc_id,
u32 preemption_timeout)
{
- if (guc->fw.file_selected.major_ver >= 70) {
+ if (GET_UC_VER(guc) >= MAKE_UC_VER(70, 0, 0)) {
struct context_policy policy;
__guc_context_policy_start_klv(&policy, guc_id);
@@ -3186,7 +3186,7 @@ static int guc_context_alloc(struct
intel_context *ce)
static void __guc_context_set_prio(struct intel_guc *guc,
struct intel_context *ce)
{
- if (guc->fw.file_selected.major_ver >= 70) {
+ if (GET_UC_VER(guc) >= MAKE_UC_VER(70, 0, 0)) {
struct context_policy policy;
__guc_context_policy_start_klv(&policy, ce->guc_id.id);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index d965ac4832d60..abf4e142596d0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -435,9 +435,11 @@ static void print_fw_ver(struct intel_uc *uc,
struct intel_uc_fw *fw)
{
struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
- drm_info(&i915->drm, "%s firmware %s version %u.%u\n",
+ drm_info(&i915->drm, "%s firmware %s version %u.%u.%u\n",
intel_uc_fw_type_repr(fw->type), fw->file_selected.path,
- fw->file_selected.major_ver, fw->file_selected.minor_ver);
+ fw->file_selected.major_ver,
+ fw->file_selected.minor_ver,
+ fw->file_selected.patch_ver);
}
static int __uc_init_hw(struct intel_uc *uc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 94cf2d4a46e6f..7c45c097d6845 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -447,10 +447,12 @@ static int check_gsc_manifest(const struct
firmware *fw,
struct intel_uc_fw *uc_fw)
{
u32 *dw = (u32 *)fw->data;
- u32 version = dw[HUC_GSC_VERSION_DW];
+ u32 version_hi = dw[HUC_GSC_VERSION_HI_DW];
+ u32 version_lo = dw[HUC_GSC_VERSION_LO_DW];
- uc_fw->file_selected.major_ver =
FIELD_GET(HUC_GSC_MAJOR_VER_MASK, version);
- uc_fw->file_selected.minor_ver =
FIELD_GET(HUC_GSC_MINOR_VER_MASK, version);
+ uc_fw->file_selected.major_ver =
FIELD_GET(HUC_GSC_MAJOR_VER_HI_MASK, version_hi);
+ uc_fw->file_selected.minor_ver =
FIELD_GET(HUC_GSC_MINOR_VER_HI_MASK, version_hi);
+ uc_fw->file_selected.patch_ver =
FIELD_GET(HUC_GSC_PATCH_VER_LO_MASK, version
[Intel-gfx] [PATCH] drm/i915/guc: Cancel GuC engine busyness worker synchronously
The worker is canceled in gt_park path, but earlier it was assumed that
gt_park path cannot sleep and the cancel is asynchronous. This caused a
race with suspend flow where the worker runs after suspend and causes an
unclaimed register access warning. Cancel the worker synchronously since
the gt_park is indeed allowed to sleep.
v2: Fix author name and sign-off mismatch
Signed-off-by: Umesh Nerlige Ramappa
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4419
Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
pmu")
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0d56b615bf78..e6275380b253 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1438,7 +1438,12 @@ void intel_guc_busyness_park(struct intel_gt *gt)
if (!guc_submission_initialized(guc))
return;
- cancel_delayed_work(&guc->timestamp.work);
+ /*
+* There is a race with suspend flow where the worker runs after suspend
+* and causes an unclaimed register access warning. Cancel the worker
+* synchronously here.
+*/
+ cancel_delayed_work_sync(&guc->timestamp.work);
/*
* Before parking, we should sample engine busyness stats if we need to.
--
2.25.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Cancel GuC engine busyness worker synchronously (rev2)
== Series Details ==
Series: drm/i915/guc: Cancel GuC engine busyness worker synchronously (rev2)
URL : https://patchwork.freedesktop.org/series/106738/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12035 -> Patchwork_106738v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v2/index.html
Participating hosts (42 -> 33)
--
Missing(9): fi-jsl-1 bat-dg1-5 fi-hsw-4200u bat-adlp-4 fi-ctg-p8600
fi-glk-j4005 bat-rplp-1 bat-dg2-10 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_106738v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600: NOTRUN -> [FAIL][1] ([fdo#103375])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v2/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@execlists:
- fi-bdw-gvtdvm: [PASS][2] -> [INCOMPLETE][3] ([i915#2940])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-bdw-gvtdvm/igt@i915_selftest@l...@execlists.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v2/fi-bdw-gvtdvm/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][4] -> [INCOMPLETE][5] ([i915#4785])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v2/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][6] -> [DMESG-FAIL][7] ([i915#4528])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v2/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bsw-nick:NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v2/fi-bsw-nick/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-rkl-11600: NOTRUN -> [SKIP][9] ([fdo#111827])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v2/fi-rkl-11600/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-bsw-nick:NOTRUN -> [SKIP][10] ([fdo#109271])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v2/fi-bsw-nick/igt@kms_pipe_crc_ba...@suspend-read-crc.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-edp-1:
- fi-bsw-kefka: [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-bsw-kefka/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-edp-1.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v2/fi-bsw-kefka/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-edp-1.html
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][13] ([fdo#109271] / [i915#4312] /
[i915#5594] / [i915#6246])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v2/fi-hsw-4770/igt@run...@aborted.html
- fi-pnv-d510:NOTRUN -> [FAIL][14] ([fdo#109271] / [i915#2403] /
[i915#4312])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v2/fi-pnv-d510/igt@run...@aborted.html
- fi-bdw-gvtdvm: NOTRUN -> [FAIL][15] ([i915#4312])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v2/fi-bdw-gvtdvm/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[INCOMPLETE][16] ([i915#5847]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v2/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@requests:
- {bat-rpls-1}: [INCOMPLETE][18] ([i915#6257] / [i915#6380]) ->
[PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/bat-rpls-1/igt@i915_selftest@l...@requests.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v2/bat-rpls-1/igt@i915_selftest@l...@requests.html
Warnings
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [INCOMPLETE][20] ([i915#5982]) -> [FAIL][21]
([fdo#103375])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106738v2/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILUR
Re: [Intel-gfx] [PATCH v2 15/21] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox
On Thu, Aug 18, 2022 at 04:41:56PM -0700, Radhakrishna Sripada wrote:
> From Meteorlake, Latency Level, SAGV bloack time are read from
> LATENCY_SAGV register instead of the GT driver pcode mailbox. DDR type
> and QGV information are also to be read from Mem SS registers.
>
> v2:
> - Simplify MTL_MEM_SS_INFO_QGV_POINT macro(MattR)
> - Nit: Rearrange the bit def's from higher to lower(MattR)
> - Restore platform definition for ADL-P(MattR)
> - Move back intel_qgv_point def to intel_bw.c(Jani)
> Bspec: 64636, 64608
>
> Cc: Matt Roper
> Cc: Jani Nikula
> Original Author: Caz Yokoyama
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 42 ++---
> drivers/gpu/drm/i915/i915_reg.h | 16 ++
> drivers/gpu/drm/i915/intel_dram.c | 41 +++-
> drivers/gpu/drm/i915/intel_pm.c | 8 -
> 4 files changed, 100 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 79269d2c476b..46b63afd536a 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -137,6 +137,42 @@ int icl_pcode_restrict_qgv_points(struct
> drm_i915_private *dev_priv,
> return 0;
> }
>
> +static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
> +struct intel_qgv_point *sp, int point)
> +{
> + u32 val, val2;
> + u16 dclk;
> +
> + val = intel_uncore_read(&dev_priv->uncore,
> + MTL_MEM_SS_INFO_QGV_POINT_LOW(point));
> + val2 = intel_uncore_read(&dev_priv->uncore,
> + MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
> + dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
> + sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000);
> + sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
> + sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
> +
> + sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2);
> + sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2);
> +
> + sp->t_rc = sp->t_rp + sp->t_ras;
> +
> + return 0;
> +}
> +
> +static int
> +intel_read_qgv_point_info(struct drm_i915_private *dev_priv,
> + struct intel_qgv_point *sp,
> + int point)
> +{
> + if (DISPLAY_VER(dev_priv) >= 14)
> + return mtl_read_qgv_point_info(dev_priv, sp, point);
> + else if (IS_DG1(dev_priv))
> + return dg1_mchbar_read_qgv_point_info(dev_priv, sp, point);
> + else
> + return icl_pcode_read_qgv_point_info(dev_priv, sp, point);
> +}
> +
> static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> struct intel_qgv_info *qi,
> bool is_y_tile)
> @@ -193,11 +229,7 @@ static int icl_get_qgv_points(struct drm_i915_private
> *dev_priv,
> for (i = 0; i < qi->num_points; i++) {
> struct intel_qgv_point *sp = &qi->points[i];
>
> - if (IS_DG1(dev_priv))
> - ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i);
> - else
> - ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
> -
> + ret = intel_read_qgv_point_info(dev_priv, sp, i);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b2d5e1230c25..5245af8d0ea8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8397,4 +8397,20 @@ enum skl_power_gate {
> #define MTL_LATENCY_LEVEL0_2_4_MASK REG_GENMASK(12, 0)
> #define MTL_LATENCY_LEVEL1_3_5_MASK REG_GENMASK(28, 16)
>
> +#define MTL_LATENCY_SAGV _MMIO(0x4578c)
> +#define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0)
Minor nitpick: we usually have two additional spaces (for a total of
three) between the 'define' and the field name.
> +
> +#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
> +#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
> +#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
> +#define MTL_N_OF_ENABLED_QGV_POINTS_MASKREG_GENMASK(11, 8)
Another nitpick: we usually order fields from low to high (which is
also usually how the spec orders them).
> +
> +#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(0x45710 + (point) * 2)
> +#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(0x45714 +
> (point) * 2)
> +#define MTL_TRCD_MASK REG_GENMASK(31, 24)
> +#define MTL_TRP_MASKREG_GENMASK(23, 16)
> +#define MTL_TRAS_MASK REG_GENMASK(16, 8)
> +#define MTL_DCLK_MASK REG_GENMASK(15, 0)
> +#define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
It would be a bit cleaner to put the fields that are in the lower dword
Re: [Intel-gfx] [PATCH v2 2/3] drm/i915/uc: Add patch level version number support
On 8/25/2022 8:05 PM, john.c.harri...@intel.com wrote:
From: John Harrison
With the move to un-versioned filenames, it becomes more difficult to
know exactly what version of a given firmware is being used. So add
the patch level version number to the debugfs output.
Also, support matching by patch level when selecting code paths for
firmware compatibility. While a patch level change cannot be backwards
breaking, it is potentially possible that a new feature only works
from a given patch level onwards (even though it was theoretically
added in an earlier version that bumped the major or minor version).
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +++---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 36 ++-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 6
drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 8 +++--
5 files changed, 47 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 04393932623c7..64c4e83153f47 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1868,7 +1868,7 @@ int intel_guc_submission_init(struct intel_guc *guc)
if (guc->submission_initialized)
return 0;
- if (guc->fw.file_selected.major_ver < 70) {
+ if (GET_UC_VER(guc) < MAKE_UC_VER(70, 0, 0)) {
ret = guc_lrc_desc_pool_create_v69(guc);
if (ret)
return ret;
@@ -2303,7 +2303,7 @@ static int register_context(struct intel_context *ce,
bool loop)
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_register(ce);
- if (guc->fw.file_selected.major_ver >= 70)
+ if (GET_UC_VER(guc) >= MAKE_UC_VER(70, 0, 0))
ret = register_context_v70(guc, ce, loop);
else
ret = register_context_v69(guc, ce, loop);
@@ -2315,7 +2315,7 @@ static int register_context(struct intel_context *ce,
bool loop)
set_context_registered(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
- if (guc->fw.file_selected.major_ver >= 70)
+ if (GET_UC_VER(guc) >= MAKE_UC_VER(70, 0, 0))
guc_context_policy_init_v70(ce, loop);
}
@@ -2921,7 +2921,7 @@ static void __guc_context_set_preemption_timeout(struct intel_guc *guc,
u16 guc_id,
u32 preemption_timeout)
{
- if (guc->fw.file_selected.major_ver >= 70) {
+ if (GET_UC_VER(guc) >= MAKE_UC_VER(70, 0, 0)) {
struct context_policy policy;
__guc_context_policy_start_klv(&policy, guc_id);
@@ -3186,7 +3186,7 @@ static int guc_context_alloc(struct intel_context *ce)
static void __guc_context_set_prio(struct intel_guc *guc,
struct intel_context *ce)
{
- if (guc->fw.file_selected.major_ver >= 70) {
+ if (GET_UC_VER(guc) >= MAKE_UC_VER(70, 0, 0)) {
struct context_policy policy;
__guc_context_policy_start_klv(&policy, ce->guc_id.id);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index d965ac4832d60..abf4e142596d0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -435,9 +435,11 @@ static void print_fw_ver(struct intel_uc *uc, struct
intel_uc_fw *fw)
{
struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
- drm_info(&i915->drm, "%s firmware %s version %u.%u\n",
+ drm_info(&i915->drm, "%s firmware %s version %u.%u.%u\n",
intel_uc_fw_type_repr(fw->type), fw->file_selected.path,
-fw->file_selected.major_ver, fw->file_selected.minor_ver);
+fw->file_selected.major_ver,
+fw->file_selected.minor_ver,
+fw->file_selected.patch_ver);
}
static int __uc_init_hw(struct intel_uc *uc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 94cf2d4a46e6f..7c45c097d6845 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -447,10 +447,12 @@ static int check_gsc_manifest(const struct firmware *fw,
struct intel_uc_fw *uc_fw)
{
u32 *dw = (u32 *)fw->data;
- u32 version = dw[HUC_GSC_VERSION_DW];
+ u32 version_hi = dw[HUC_GSC_VERSION_HI_DW];
+ u32 version_lo = dw[HUC_GSC_VERSION_LO_DW];
- uc_fw->file_selected.major_ver = FIELD_GET(HUC_GSC_MAJOR_VER_MASK, version);
- uc_fw->file_selected.minor_ver = FIELD_GET(HUC_GSC_MINOR_VER_MASK,
version);
+ uc_fw->file_selected.major_ver = FIELD_GET(HUC_GSC_MAJOR_VER_HI_MASK,
version_hi);
+ uc_fw->
[Intel-gfx] [PATCH] drm/i915/guc: Cancel GuC engine busyness worker synchronously
The worker is canceled in gt_park path, but earlier it was assumed that gt_park path cannot sleep and the cancel is asynchronous. This caused a race with suspend flow where the worker runs after suspend and causes an unclaimed register access warning. Cancel the worker synchronously since the gt_park is indeed allowed to sleep. Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 0d56b615bf78..e6275380b253 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1438,7 +1438,12 @@ void intel_guc_busyness_park(struct intel_gt *gt) if (!guc_submission_initialized(guc)) return; - cancel_delayed_work(&guc->timestamp.work); + /* +* There is a race with suspend flow where the worker runs after suspend +* and causes an unclaimed register access warning. Cancel the worker +* synchronously here. +*/ + cancel_delayed_work_sync(&guc->timestamp.work); /* * Before parking, we should sample engine busyness stats if we need to. -- 2.25.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: Range descriptor stuff
== Series Details ==
Series: drm/edid: Range descriptor stuff
URL : https://patchwork.freedesktop.org/series/107824/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12035 -> Patchwork_107824v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107824v1/index.html
Participating hosts (42 -> 35)
--
Missing(7): fi-hsw-4200u bat-dg1-5 bat-adlp-4 fi-ctg-p8600 bat-rplp-1
bat-dg2-10 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107824v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_lrc:
- {bat-dg2-9}:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/bat-dg2-9/igt@i915_selftest@live@gt_lrc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107824v1/bat-dg2-9/igt@i915_selftest@live@gt_lrc.html
Known issues
Here are the changes found in Patchwork_107824v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][3] -> [INCOMPLETE][4] ([i915#4785])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107824v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-g3258: [PASS][5] -> [INCOMPLETE][6] ([i915#3303] /
[i915#4785])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107824v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][7] -> [DMESG-FAIL][8] ([i915#4528])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107824v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bsw-nick:NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107824v1/fi-bsw-nick/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-bsw-nick:NOTRUN -> [SKIP][10] ([fdo#109271])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107824v1/fi-bsw-nick/igt@kms_pipe_crc_ba...@suspend-read-crc.html
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#4312] /
[i915#5594] / [i915#6246])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107824v1/fi-hsw-4770/igt@run...@aborted.html
- fi-pnv-d510:NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#2403] /
[i915#4312])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107824v1/fi-pnv-d510/igt@run...@aborted.html
- fi-hsw-g3258: NOTRUN -> [FAIL][13] ([fdo#109271] / [i915#4312] /
[i915#6246])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107824v1/fi-hsw-g3258/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[INCOMPLETE][14] ([i915#5847]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107824v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
Warnings
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][16] ([i915#4494] / [i915#4957]) ->
[DMESG-FAIL][17] ([i915#4957])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107824v1/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5594]: h
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/edid: Range descriptor stuff
== Series Details == Series: drm/edid: Range descriptor stuff URL : https://patchwork.freedesktop.org/series/107824/ State : warning == Summary == Error: dim checkpatch failed f3a0ff9bb39c drm/edid: Handle EDID 1.4 range descriptor h/vfreq offsets a3b12a2f939d drm/edid: Clarify why we only accept the "range limits only" descriptor 1219cd9a4eb9 drm/edid: s/monitor_rage/vrr_range/ 565abe4b0f72 drm/edid: Define more flags -:22: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #22: FILE: drivers/gpu/drm/drm_edid.c:2987: + descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING) total: 0 errors, 1 warnings, 0 checks, 90 lines checked bbf158e55787 drm/edid: Only parse VRR range for continuous frequency displays 28022ddf1543 drm/edid: Extract drm_gtf2_mode() 5aaf2a783d91 drm/edid: Use GTF2 for inferred modes 23f8f68c2338 drm/edid: Use the correct formula for standard timings f5286c90de73 drm/edid: Unconfuse preferred timing stuff a bit afc26dcabe19 drm/edid: Make version checks less convoluted 607330ff2d5f drm/i915: Infer vrefresh range for eDP if the EDID omits it
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ats-m: Add thread execution tuning setting
== Series Details ==
Series: drm/i915/ats-m: Add thread execution tuning setting
URL : https://patchwork.freedesktop.org/series/107822/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12035 -> Patchwork_107822v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107822v1/index.html
Participating hosts (42 -> 34)
--
Missing(8): bat-dg1-5 fi-hsw-4200u bat-adlp-4 fi-ctg-p8600 bat-jsl-3
bat-rplp-1 bat-dg2-10 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_107822v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][1] -> [DMESG-FAIL][2] ([i915#4528])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107822v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bsw-nick:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107822v1/fi-bsw-nick/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-bsw-nick:NOTRUN -> [SKIP][4] ([fdo#109271])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107822v1/fi-bsw-nick/igt@kms_pipe_crc_ba...@suspend-read-crc.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][5] ([fdo#109271] / [i915#2403] /
[i915#4312])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107822v1/fi-pnv-d510/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[INCOMPLETE][6] ([i915#5847]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107822v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@requests:
- {bat-rpls-1}: [INCOMPLETE][8] ([i915#6257] / [i915#6380]) ->
[PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/bat-rpls-1/igt@i915_selftest@l...@requests.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107822v1/bat-rpls-1/igt@i915_selftest@l...@requests.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
[i915#5847]: https://gitlab.freedesktop.org/drm/intel/issues/5847
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6380]: https://gitlab.freedesktop.org/drm/intel/issues/6380
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
Build changes
-
* Linux: CI_DRM_12035 -> Patchwork_107822v1
CI-20190529: 20190529
CI_DRM_12035: 94f8134b5320a43800ca3ca50d1c387d66f75c6a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6636: 1298b5f0e1b3e010657ffba41d2e775fab028e08 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107822v1: 94f8134b5320a43800ca3ca50d1c387d66f75c6a @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
8f3a26f7fdc5 drm/i915/ats-m: Add thread execution tuning setting
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107822v1/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/ats-m: Add thread execution tuning setting
== Series Details == Series: drm/i915/ats-m: Add thread execution tuning setting URL : https://patchwork.freedesktop.org/series/107822/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"
== Series Details ==
Series: Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"
URL : https://patchwork.freedesktop.org/series/107818/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12035 -> Patchwork_107818v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107818v1/index.html
Participating hosts (42 -> 34)
--
Missing(8): bat-dg1-5 fi-hsw-4200u bat-adlp-4 fi-ctg-p8600 bat-rplp-1
bat-dg2-10 bat-dg2-11 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_107818v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][1] -> [DMESG-FAIL][2] ([i915#4528])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107818v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bsw-nick:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107818v1/fi-bsw-nick/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-bsw-nick:NOTRUN -> [SKIP][4] ([fdo#109271])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107818v1/fi-bsw-nick/igt@kms_pipe_crc_ba...@suspend-read-crc.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][5] ([fdo#109271] / [i915#2403] /
[i915#4312])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107818v1/fi-pnv-d510/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[INCOMPLETE][6] ([i915#5847]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107818v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@requests:
- {bat-rpls-1}: [INCOMPLETE][8] ([i915#6257] / [i915#6380]) ->
[PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/bat-rpls-1/igt@i915_selftest@l...@requests.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107818v1/bat-rpls-1/igt@i915_selftest@l...@requests.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#5847]: https://gitlab.freedesktop.org/drm/intel/issues/5847
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6380]: https://gitlab.freedesktop.org/drm/intel/issues/6380
[i915#6580]: https://gitlab.freedesktop.org/drm/intel/issues/6580
Build changes
-
* Linux: CI_DRM_12035 -> Patchwork_107818v1
CI-20190529: 20190529
CI_DRM_12035: 94f8134b5320a43800ca3ca50d1c387d66f75c6a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6636: 1298b5f0e1b3e010657ffba41d2e775fab028e08 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107818v1: 94f8134b5320a43800ca3ca50d1c387d66f75c6a @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
dccd6af4a178 Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107818v1/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"
== Series Details == Series: Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709" URL : https://patchwork.freedesktop.org/series/107818/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] [PATCH 11/11] drm/i915: Infer vrefresh range for eDP if the EDID omits it
From: Ville Syrjälä
A bunch of machines seem to have eDP panels where the EDID
indicates continuous frequency support but fails to actually
include the range descirptor. This violates the EDID 1.4
spec, but looks like the Windows driver just hacks around
this by just assuming that the panel supports a continuous
refresh rate range that covers all EDID reported modes.
Do the same so that we get VRR support on these machines.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6323
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 45 +
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 8d1559323412..1f3e4824d316 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5207,6 +5207,49 @@ intel_edp_add_properties(struct intel_dp *intel_dp)
fixed_mode->vdisplay);
}
+/*
+ * Some VRR eDP panels violate the EDID spec and neglect
+ * to include the monitor range descriptor in the EDID.
+ * Cook up the VRR refresh rate limits based on the modes
+ * reported by the panel.
+ */
+static void
+intel_edp_infer_vrr_range(struct intel_connector *connector)
+{
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct drm_display_info *info = &connector->base.display_info;
+ const struct edid *edid = connector->edid;
+ const struct drm_display_mode *mode;
+
+ if (!HAS_VRR(i915))
+ return;
+
+ if (!edid || edid->revision < 4 ||
+ !(edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) ||
+ info->vrr_range.min_vfreq || info->vrr_range.max_vfreq)
+ return;
+
+ if (list_empty(&connector->base.probed_modes))
+ return;
+
+ info->vrr_range.min_vfreq = ~0;
+ info->vrr_range.max_vfreq = 0;
+
+ list_for_each_entry(mode, &connector->base.probed_modes, head) {
+ int vrefresh = drm_mode_vrefresh(mode);
+
+ info->vrr_range.min_vfreq = min_t(int, vrefresh,
+ info->vrr_range.min_vfreq);
+ info->vrr_range.max_vfreq = max_t(int, vrefresh,
+ info->vrr_range.max_vfreq);
+ }
+
+ drm_dbg_kms(&i915->drm,
+ "[CONNECTOR:%d:%s] does not report refresh rate range,
assuming: %d Hz - %d Hz\n",
+ connector->base.base.id, connector->base.name,
+ info->vrr_range.min_vfreq, info->vrr_range.max_vfreq);
+}
+
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
struct intel_connector *intel_connector)
{
@@ -5271,6 +5314,8 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
}
intel_connector->edid = edid;
+ intel_edp_infer_vrr_range(intel_connector);
+
intel_bios_init_panel(dev_priv, &intel_connector->panel,
encoder->devdata, IS_ERR(edid) ? NULL : edid);
--
2.35.1
[Intel-gfx] [PATCH 09/11] drm/edid: Unconfuse preferred timing stuff a bit
From: Ville Syrjälä
For EDID 1.4 the first detailed timing is always preferred,
for older EDIDs there was a feature flag to indicate the same.
While correct, the code setting that up is rather confusing.
Restate it in a slightly more straightforward manner.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index c1c85b9e1208..0fe06e5fd6e0 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3952,13 +3952,14 @@ static int add_detailed_modes(struct drm_connector
*connector,
struct detailed_mode_closure closure = {
.connector = connector,
.drm_edid = drm_edid,
- .preferred = true,
.quirks = quirks,
};
- if (closure.preferred && !version_greater(drm_edid, 1, 3))
+ if (version_greater(drm_edid, 1, 3))
+ closure.preferred = true; /* first detailed timing is always
preferred */
+ else
closure.preferred =
- (drm_edid->edid->features &
DRM_EDID_FEATURE_PREFERRED_TIMING);
+ drm_edid->edid->features &
DRM_EDID_FEATURE_PREFERRED_TIMING;
drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
--
2.35.1
[Intel-gfx] [PATCH 10/11] drm/edid: Make version checks less convoluted
From: Ville Syrjälä
Get rid of the confusing version_greater() stuff and
simply compare edid->revision directly everwhere. Half
the places already did it this way, and since we actually
reject any EDID with edid->version!=1 it's a perfectly
sane thing to do.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 25 -
1 file changed, 8 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 0fe06e5fd6e0..e7f46260dfe7 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1572,15 +1572,6 @@ struct drm_edid {
const struct edid *edid;
};
-static bool version_greater(const struct drm_edid *drm_edid,
- u8 version, u8 revision)
-{
- const struct edid *edid = drm_edid->edid;
-
- return edid->version > version ||
- (edid->version == version && edid->revision > revision);
-}
-
static int edid_hfeeodb_extension_block_count(const struct edid *edid);
static int edid_hfeeodb_block_count(const struct edid *edid)
@@ -3652,7 +3643,7 @@ do_inferred_modes(const struct detailed_timing *timing,
void *c)
closure->drm_edid,
timing);
- if (!version_greater(closure->drm_edid, 1, 1))
+ if (closure->drm_edid->edid->revision < 2)
return; /* GTF not defined yet */
switch (range->flags) {
@@ -3667,7 +3658,7 @@ do_inferred_modes(const struct detailed_timing *timing,
void *c)
timing);
break;
case DRM_EDID_CVT_SUPPORT_FLAG:
- if (!version_greater(closure->drm_edid, 1, 3))
+ if (closure->drm_edid->edid->revision < 4)
break;
closure->modes += drm_cvt_modes_for_range(closure->connector,
@@ -3688,7 +3679,7 @@ static int add_inferred_modes(struct drm_connector
*connector,
.drm_edid = drm_edid,
};
- if (version_greater(drm_edid, 1, 0))
+ if (drm_edid->edid->revision >= 1)
drm_for_each_detailed_block(drm_edid, do_inferred_modes,
&closure);
return closure.modes;
@@ -3765,7 +3756,7 @@ static int add_established_modes(struct drm_connector
*connector,
}
}
- if (version_greater(drm_edid, 1, 0))
+ if (edid->revision >= 1)
drm_for_each_detailed_block(drm_edid, do_established_modes,
&closure);
@@ -3820,7 +3811,7 @@ static int add_standard_modes(struct drm_connector
*connector,
}
}
- if (version_greater(drm_edid, 1, 0))
+ if (drm_edid->edid->revision >= 1)
drm_for_each_detailed_block(drm_edid, do_standard_modes,
&closure);
@@ -3900,7 +3891,7 @@ add_cvt_modes(struct drm_connector *connector, const
struct drm_edid *drm_edid)
.drm_edid = drm_edid,
};
- if (version_greater(drm_edid, 1, 2))
+ if (drm_edid->edid->revision >= 3)
drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
/* XXX should also look for CVT codes in VTB blocks */
@@ -3955,7 +3946,7 @@ static int add_detailed_modes(struct drm_connector
*connector,
.quirks = quirks,
};
- if (version_greater(drm_edid, 1, 3))
+ if (drm_edid->edid->revision >= 4)
closure.preferred = true; /* first detailed timing is always
preferred */
else
closure.preferred =
@@ -6144,7 +6135,7 @@ static void drm_get_vrr_range(struct drm_connector
*connector,
.drm_edid = drm_edid,
};
- if (!version_greater(drm_edid, 1, 3))
+ if (drm_edid->edid->revision < 4)
return;
if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
--
2.35.1
[Intel-gfx] [PATCH 08/11] drm/edid: Use the correct formula for standard timings
From: Ville Syrjälä
Prefer the timing formula indicated by the range
descriptor for generating the non-DMT standard timings.
Previously we just used CVT for all EDID 1.4 continuous
frequency displays without even checking if the range
descriptor indicates otherwise. Now we check the range
descriptor first, and fall back to CVT if nothing else
was indicated. EDID 1.4 more or less deprecates GTF/GTF2
but there are still a lot of 1.4 EDIDs out there that
don't advertise CVT support, so seems safer to use the
formula the EDID actually reports as supported.
For EDID 1.3 we use GTF2 if indicated (as before), and for
EDID 1.2+ we now just use GTF without even checking the
feature flag. There seem to be quite a few EDIDs out there that
don't set the GTF feature flag but still include a GTF range
descriptor and non-DMT standard timings.
This to me seems to be roughly what appendix B of EDID 1.4
suggests should be done.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 49 +++---
1 file changed, 41 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index fed2bdd55c09..c1c85b9e1208 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3077,20 +3077,53 @@ drm_gtf2_2j(const struct drm_edid *drm_edid)
return descriptor ?
descriptor->data.other_data.data.range.formula.gtf2.j : 0;
}
+static void
+get_timing_level(const struct detailed_timing *descriptor, void *data)
+{
+ int *res = data;
+
+ if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
+ return;
+
+ BUILD_BUG_ON(offsetof(typeof(*descriptor),
data.other_data.data.range.flags) != 10);
+
+ switch (descriptor->data.other_data.data.range.flags) {
+ case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
+ *res = LEVEL_GTF;
+ break;
+ case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
+ *res = LEVEL_GTF2;
+ break;
+ case DRM_EDID_CVT_SUPPORT_FLAG:
+ *res = LEVEL_CVT;
+ break;
+ default:
+ break;
+ }
+}
+
/* Get standard timing level (CVT/GTF/DMT). */
static int standard_timing_level(const struct drm_edid *drm_edid)
{
const struct edid *edid = drm_edid->edid;
- if (edid->revision >= 2) {
- if (edid->revision >= 4 && (edid->features &
DRM_EDID_FEATURE_DEFAULT_GTF))
- return LEVEL_CVT;
- if (drm_gtf2_hbreak(drm_edid))
- return LEVEL_GTF2;
- if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
- return LEVEL_GTF;
+ if (edid->revision >= 4) {
+ /*
+* If the range descriptor doesn't
+* indicate otherwise default to CVT
+*/
+ int ret = LEVEL_CVT;
+
+ drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
+
+ return ret;
+ } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
+ return LEVEL_GTF2;
+ } else if (edid->revision >= 2) {
+ return LEVEL_GTF;
+ } else {
+ return LEVEL_DMT;
}
- return LEVEL_DMT;
}
/*
--
2.35.1
[Intel-gfx] [PATCH 07/11] drm/edid: Use GTF2 for inferred modes
From: Ville Syrjälä
For some resaon we only use the secondary GTF curve for the
standard timings. Use it for inferred modes as well.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 35 ++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 0c7cbe9b44f5..fed2bdd55c09 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3546,6 +3546,35 @@ static int drm_gtf_modes_for_range(struct drm_connector
*connector,
return modes;
}
+static int drm_gtf2_modes_for_range(struct drm_connector *connector,
+ const struct drm_edid *drm_edid,
+ const struct detailed_timing *timing)
+{
+ int i, modes = 0;
+ struct drm_display_mode *newmode;
+ struct drm_device *dev = connector->dev;
+
+ for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
+ const struct minimode *m = &extra_modes[i];
+
+ newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
+ if (!newmode)
+ return modes;
+
+ drm_mode_fixup_1366x768(newmode);
+ if (!mode_in_range(newmode, drm_edid, timing) ||
+ !valid_inferred_mode(connector, newmode)) {
+ drm_mode_destroy(dev, newmode);
+ continue;
+ }
+
+ drm_mode_probed_add(connector, newmode);
+ modes++;
+ }
+
+ return modes;
+}
+
static int drm_cvt_modes_for_range(struct drm_connector *connector,
const struct drm_edid *drm_edid,
const struct detailed_timing *timing)
@@ -3594,7 +3623,11 @@ do_inferred_modes(const struct detailed_timing *timing,
void *c)
return; /* GTF not defined yet */
switch (range->flags) {
- case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: /* XXX could do more */
+ case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
+ closure->modes += drm_gtf2_modes_for_range(closure->connector,
+ closure->drm_edid,
+ timing);
+ break;
case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
closure->modes += drm_gtf_modes_for_range(closure->connector,
closure->drm_edid,
--
2.35.1
[Intel-gfx] [PATCH 06/11] drm/edid: Extract drm_gtf2_mode()
From: Ville Syrjälä
Extract the GTF vs. GTF2 logic into a separate function.
We'll have a second user soon.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 47 --
1 file changed, 30 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index b459fdf12b58..0c7cbe9b44f5 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3113,6 +3113,35 @@ static int drm_mode_hsync(const struct drm_display_mode
*mode)
return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
}
+static struct drm_display_mode *
+drm_gtf2_mode(struct drm_device *dev,
+ const struct drm_edid *drm_edid,
+ int hsize, int vsize, int vrefresh_rate)
+{
+ struct drm_display_mode *mode;
+
+ /*
+* This is potentially wrong if there's ever a monitor with
+* more than one ranges section, each claiming a different
+* secondary GTF curve. Please don't do that.
+*/
+ mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
+ if (!mode)
+ return NULL;
+
+ if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
+ drm_mode_destroy(dev, mode);
+ mode = drm_gtf_mode_complex(dev, hsize, vsize,
+ vrefresh_rate, 0, 0,
+ drm_gtf2_m(drm_edid),
+ drm_gtf2_2c(drm_edid),
+ drm_gtf2_k(drm_edid),
+ drm_gtf2_2j(drm_edid));
+ }
+
+ return mode;
+}
+
/*
* Take the standard timing params (in this case width, aspect, and refresh)
* and convert them into a real mode using CVT/GTF/DMT.
@@ -3201,23 +3230,7 @@ static struct drm_display_mode *drm_mode_std(struct
drm_connector *connector,
mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
break;
case LEVEL_GTF2:
- /*
-* This is potentially wrong if there's ever a monitor with
-* more than one ranges section, each claiming a different
-* secondary GTF curve. Please don't do that.
-*/
- mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
- if (!mode)
- return NULL;
- if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
- drm_mode_destroy(dev, mode);
- mode = drm_gtf_mode_complex(dev, hsize, vsize,
- vrefresh_rate, 0, 0,
- drm_gtf2_m(drm_edid),
- drm_gtf2_2c(drm_edid),
- drm_gtf2_k(drm_edid),
- drm_gtf2_2j(drm_edid));
- }
+ mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize,
vrefresh_rate);
break;
case LEVEL_CVT:
mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
--
2.35.1
[Intel-gfx] [PATCH 05/11] drm/edid: Only parse VRR range for continuous frequency displays
From: Ville Syrjälä Since we only use the parsed vrefresh range to determine if VRR should be supported we should only accept continuous frequency displays here. Cc: Manasi Navare Cc: Nicholas Kazlauskas Cc: Harry Wentland Cc: Leo Li Cc: Rodrigo Siqueira Cc: amd-...@lists.freedesktop.org Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/drm_edid.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 856d304a1354..b459fdf12b58 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -6064,7 +6064,10 @@ static void drm_get_vrr_range(struct drm_connector *connector, .drm_edid = drm_edid, }; - if (!version_greater(drm_edid, 1, 1)) + if (!version_greater(drm_edid, 1, 3)) + return; + + if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)) return; drm_for_each_detailed_block(drm_edid, get_vrr_range, &closure); -- 2.35.1
[Intel-gfx] [PATCH 04/11] drm/edid: Define more flags
From: Ville Syrjälä
Replace a bunch of hex constants with proper definitions.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 18 +-
include/drm/drm_edid.h | 14 +-
2 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 4355d73632c3..856d304a1354 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2984,7 +2984,7 @@ is_rb(const struct detailed_timing *descriptor, void
*data)
BUILD_BUG_ON(offsetof(typeof(*descriptor),
data.other_data.data.range.formula.cvt.flags) != 15);
if (descriptor->data.other_data.data.range.flags ==
DRM_EDID_CVT_SUPPORT_FLAG &&
- descriptor->data.other_data.data.range.formula.cvt.flags & 0x10)
+ descriptor->data.other_data.data.range.formula.cvt.flags &
DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
*res = true;
}
@@ -3012,7 +3012,7 @@ find_gtf2(const struct detailed_timing *descriptor, void
*data)
BUILD_BUG_ON(offsetof(typeof(*descriptor),
data.other_data.data.range.flags) != 10);
- if (descriptor->data.other_data.data.range.flags == 0x02)
+ if (descriptor->data.other_data.data.range.flags ==
DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
*res = descriptor;
}
@@ -3415,7 +3415,7 @@ range_pixel_clock(const struct edid *edid, const u8 *t)
return 0;
/* 1.4 with CVT support gives us real precision, yay */
- if (edid->revision >= 4 && t[10] == 0x04)
+ if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
return (t[9] * 1) - ((t[12] >> 2) * 250);
/* 1.3 is pathetic, so fuzz up a bit */
@@ -3441,7 +3441,7 @@ static bool mode_in_range(const struct drm_display_mode
*mode,
return false;
/* 1.4 max horizontal check */
- if (edid->revision >= 4 && t[10] == 0x04)
+ if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3
return false;
@@ -3581,13 +3581,13 @@ do_inferred_modes(const struct detailed_timing *timing,
void *c)
return; /* GTF not defined yet */
switch (range->flags) {
- case 0x02: /* secondary gtf, XXX could do more */
- case 0x00: /* default gtf */
+ case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: /* XXX could do more */
+ case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
closure->modes += drm_gtf_modes_for_range(closure->connector,
closure->drm_edid,
timing);
break;
- case 0x04: /* cvt, only in 1.4+ */
+ case DRM_EDID_CVT_SUPPORT_FLAG:
if (!version_greater(closure->drm_edid, 1, 3))
break;
@@ -3595,7 +3595,7 @@ do_inferred_modes(const struct detailed_timing *timing,
void *c)
closure->drm_edid,
timing);
break;
- case 0x01: /* just the ranges, no formula */
+ case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
default:
break;
}
@@ -6393,7 +6393,7 @@ static int _drm_edid_connector_update(struct
drm_connector *connector,
num_modes += add_cea_modes(connector, drm_edid);
num_modes += add_alternate_cea_modes(connector, drm_edid);
num_modes += add_displayid_detailed_modes(connector, drm_edid);
- if (drm_edid->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
+ if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
num_modes += add_inferred_modes(connector, drm_edid);
if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 1ed61e2b30a4..429735b91f63 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -97,10 +97,13 @@ struct detailed_data_string {
#define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << 2) /* 1.4 */
#define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */
-#define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00
-#define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01
-#define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02
-#define DRM_EDID_CVT_SUPPORT_FLAG 0x04
+#define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00 /* 1.3 */
+#define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01 /* 1.4 */
+#define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02 /* 1.3 */
+#define DRM_EDID_CVT_SUPPORT_FLAG 0x04 /* 1.4 */
+
+#define DRM_EDID_CVT_FLAGS_STANDARD_BLANKING (1 << 3)
+#define DRM_EDID_CVT_FLAGS_REDUCED_BLANKING (1 << 4)
struct detailed_data_monitor_range {
u8 min_vfreq;
@@ -206,7 +209,8 @@ struct detailed_timing {
#define DRM_EDID_DIGITAL_TYPE_DP (5 << 0) /* 1.4 */
#de
[Intel-gfx] [PATCH 03/11] drm/edid: s/monitor_rage/vrr_range/
From: Ville Syrjälä
Rename info->monitor_range to info->vrr_range to actually
reflect its usage.
Cc: Manasi Navare
Cc: Nicholas Kazlauskas
Cc: Harry Wentland
Cc: Leo Li
Cc: Rodrigo Siqueira
Cc: amd-...@lists.freedesktop.org
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 -
drivers/gpu/drm/drm_debugfs.c | 4 +--
drivers/gpu/drm/drm_edid.c| 26 +--
drivers/gpu/drm/i915/display/intel_vrr.c | 6 ++---
include/drm/drm_connector.h | 4 +--
5 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e702f0d72d53..928b5b6541db 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -9921,8 +9921,8 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector
*connector,
amdgpu_dm_connector->min_vfreq = 0;
amdgpu_dm_connector->max_vfreq = 0;
amdgpu_dm_connector->pixel_clock_mhz = 0;
- connector->display_info.monitor_range.min_vfreq = 0;
- connector->display_info.monitor_range.max_vfreq = 0;
+ connector->display_info.vrr_range.min_vfreq = 0;
+ connector->display_info.vrr_range.max_vfreq = 0;
freesync_capable = false;
goto update;
@@ -9970,8 +9970,8 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector
*connector,
amdgpu_dm_connector->pixel_clock_mhz =
range->pixel_clock_mhz * 10;
- connector->display_info.monitor_range.min_vfreq
= range->min_vfreq;
- connector->display_info.monitor_range.max_vfreq
= range->max_vfreq;
+ connector->display_info.vrr_range.min_vfreq =
range->min_vfreq;
+ connector->display_info.vrr_range.max_vfreq =
range->max_vfreq;
break;
}
@@ -9993,8 +9993,8 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector
*connector,
if (amdgpu_dm_connector->max_vfreq -
amdgpu_dm_connector->min_vfreq > 10)
freesync_capable = true;
- connector->display_info.monitor_range.min_vfreq =
vsdb_info.min_refresh_rate_hz;
- connector->display_info.monitor_range.max_vfreq =
vsdb_info.max_refresh_rate_hz;
+ connector->display_info.vrr_range.min_vfreq =
vsdb_info.min_refresh_rate_hz;
+ connector->display_info.vrr_range.max_vfreq =
vsdb_info.max_refresh_rate_hz;
}
}
diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c
index 01ee3febb813..1437c798b122 100644
--- a/drivers/gpu/drm/drm_debugfs.c
+++ b/drivers/gpu/drm/drm_debugfs.c
@@ -377,8 +377,8 @@ static int vrr_range_show(struct seq_file *m, void *data)
if (connector->status != connector_status_connected)
return -ENODEV;
- seq_printf(m, "Min: %u\n",
connector->display_info.monitor_range.min_vfreq);
- seq_printf(m, "Max: %u\n",
connector->display_info.monitor_range.max_vfreq);
+ seq_printf(m, "Min: %u\n", connector->display_info.vrr_range.min_vfreq);
+ seq_printf(m, "Max: %u\n", connector->display_info.vrr_range.max_vfreq);
return 0;
}
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index ac662495635c..4355d73632c3 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6020,11 +6020,11 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
}
static
-void get_monitor_range(const struct detailed_timing *timing, void *c)
+void get_vrr_range(const struct detailed_timing *timing, void *c)
{
struct detailed_mode_closure *closure = c;
struct drm_display_info *info = &closure->connector->display_info;
- struct drm_monitor_range_info *monitor_range = &info->monitor_range;
+ struct drm_monitor_range_info *vrr_range = &info->vrr_range;
const struct detailed_non_pixel *data = &timing->data.other_data;
const struct detailed_data_monitor_range *range = &data->data.range;
const struct edid *edid = closure->drm_edid->edid;
@@ -6044,19 +6044,19 @@ void get_monitor_range(const struct detailed_timing
*timing, void *c)
if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
return;
- monitor_range->min_vfreq = range->min_vfreq;
- monitor_range->max_vfreq = range->max_vfreq;
+ vrr_range->min_vfreq = range->min_vfreq;
+ vrr_range->max_vfreq = range->max_vfreq;
if (edid->revision >= 4) {
if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
-
[Intel-gfx] [PATCH 02/11] drm/edid: Clarify why we only accept the "range limits only" descriptor
From: Ville Syrjälä The current comment fails to clarify why we only accept the "range limits only" variant of the range descriptor. Reword it to make some actual sense. Cc: Manasi Navare Cc: Nicholas Kazlauskas Cc: Harry Wentland Cc: Leo Li Cc: Rodrigo Siqueira Cc: amd-...@lists.freedesktop.org Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/drm_edid.c | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 4005dab6147d..ac662495635c 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -6033,10 +6033,13 @@ void get_monitor_range(const struct detailed_timing *timing, void *c) return; /* -* Check for flag range limits only. If flag == 1 then -* no additional timing information provided. -* Default GTF, GTF Secondary curve and CVT are not -* supported +* These limits are used to determine the VRR refresh +* rate range. Only the "range limits only" variant +* of the range descriptor seems to guarantee that +* any and all timings are accepted by the sink, as +* opposed to just timings conforming to the indicated +* formula (GTF/GTF2/CVT). Thus other variants of the +* range descriptor are not accepted here. */ if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) return; -- 2.35.1
[Intel-gfx] [PATCH 01/11] drm/edid: Handle EDID 1.4 range descriptor h/vfreq offsets
From: Ville Syrjälä
EDID 1.4 introduced some extra flags in the range
descriptor to support min/max h/vfreq >= 255. Consult them
to correctly parse the vfreq limits.
Note that some combinations of the flags are documented
as "reserved" (as are some other values in the descriptor)
but explicitly checking for those doesn't seem particularly
worthwile since we end up with bogus results whether we
decode them or not.
v2: Increase the storage to u16 to make it work (Jani)
Note the "reserved" values situation (Jani)
v3: Document the EDID version number in the defines
Drop some bogus (u8) casts
Cc: sta...@vger.kernel.org
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6519
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_debugfs.c | 4 ++--
drivers/gpu/drm/drm_edid.c| 24 ++--
include/drm/drm_connector.h | 4 ++--
include/drm/drm_edid.h| 5 +
4 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c
index 493922069c90..01ee3febb813 100644
--- a/drivers/gpu/drm/drm_debugfs.c
+++ b/drivers/gpu/drm/drm_debugfs.c
@@ -377,8 +377,8 @@ static int vrr_range_show(struct seq_file *m, void *data)
if (connector->status != connector_status_connected)
return -ENODEV;
- seq_printf(m, "Min: %u\n",
(u8)connector->display_info.monitor_range.min_vfreq);
- seq_printf(m, "Max: %u\n",
(u8)connector->display_info.monitor_range.max_vfreq);
+ seq_printf(m, "Min: %u\n",
connector->display_info.monitor_range.min_vfreq);
+ seq_printf(m, "Max: %u\n",
connector->display_info.monitor_range.max_vfreq);
return 0;
}
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 90a5e26eafa8..4005dab6147d 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6020,12 +6020,14 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
}
static
-void get_monitor_range(const struct detailed_timing *timing,
- void *info_monitor_range)
+void get_monitor_range(const struct detailed_timing *timing, void *c)
{
- struct drm_monitor_range_info *monitor_range = info_monitor_range;
+ struct detailed_mode_closure *closure = c;
+ struct drm_display_info *info = &closure->connector->display_info;
+ struct drm_monitor_range_info *monitor_range = &info->monitor_range;
const struct detailed_non_pixel *data = &timing->data.other_data;
const struct detailed_data_monitor_range *range = &data->data.range;
+ const struct edid *edid = closure->drm_edid->edid;
if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
return;
@@ -6041,18 +6043,28 @@ void get_monitor_range(const struct detailed_timing
*timing,
monitor_range->min_vfreq = range->min_vfreq;
monitor_range->max_vfreq = range->max_vfreq;
+
+ if (edid->revision >= 4) {
+ if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
+ monitor_range->min_vfreq += 255;
+ if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
+ monitor_range->max_vfreq += 255;
+ }
}
static void drm_get_monitor_range(struct drm_connector *connector,
const struct drm_edid *drm_edid)
{
- struct drm_display_info *info = &connector->display_info;
+ const struct drm_display_info *info = &connector->display_info;
+ struct detailed_mode_closure closure = {
+ .connector = connector,
+ .drm_edid = drm_edid,
+ };
if (!version_greater(drm_edid, 1, 1))
return;
- drm_for_each_detailed_block(drm_edid, get_monitor_range,
- &info->monitor_range);
+ drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
info->monitor_range.min_vfreq,
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 248206bbd975..56aee949c6fa 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -319,8 +319,8 @@ enum drm_panel_orientation {
* EDID's detailed monitor range
*/
struct drm_monitor_range_info {
- u8 min_vfreq;
- u8 max_vfreq;
+ u16 min_vfreq;
+ u16 max_vfreq;
};
/**
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 2181977ae683..1ed61e2b30a4 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -92,6 +92,11 @@ struct detailed_data_string {
u8 str[13];
} __attribute__((packed));
+#define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 << 0) /* 1.4 */
+#define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 << 1) /* 1.4 */
+#define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << 2) /* 1.4 */
+#define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.
[Intel-gfx] [PATCH 00/11] drm/edid: Range descriptor stuff
From: Ville Syrjälä Various improvements (mostly) related to the EDID range descriptor handling. Entire series available here: https://github.com/vsyrjala/linux.git edid_range_descriptor Ville Syrjälä (11): drm/edid: Handle EDID 1.4 range descriptor h/vfreq offsets drm/edid: Clarify why we only accept the "range limits only" descriptor drm/edid: s/monitor_rage/vrr_range/ drm/edid: Define more flags drm/edid: Only parse VRR range for continuous frequency displays drm/edid: Extract drm_gtf2_mode() drm/edid: Use GTF2 for inferred modes drm/edid: Use the correct formula for standard timings drm/edid: Unconfuse preferred timing stuff a bit drm/edid: Make version checks less convoluted drm/i915: Infer vrefresh range for eDP if the EDID omits it .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +- drivers/gpu/drm/drm_debugfs.c | 4 +- drivers/gpu/drm/drm_edid.c| 231 -- drivers/gpu/drm/i915/display/intel_dp.c | 45 drivers/gpu/drm/i915/display/intel_vrr.c | 6 +- include/drm/drm_connector.h | 8 +- include/drm/drm_edid.h| 19 +- 7 files changed, 234 insertions(+), 91 deletions(-) -- 2.35.1
[Intel-gfx] [PATCH] drm/i915/ats-m: Add thread execution tuning setting
On client DG2 platforms, optimal performance is achieved with the
hardware's default "age based" thread execution setting. However on
ATS-M, switching this to "round robin after dependencies" provides
better performance. We'll add a new "tuning" feature flag to the ATS-M
device info to enable/disable this setting.
Bspec: 68331
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h| 1 +
4 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 94f9ddcfb3a5..d414785003cc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1110,6 +1110,8 @@
#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
#define GEN11_DIS_PICK_2ND_EUREG_BIT(7)
#define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
+#define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
+#define THREAD_EX_ARB_MODE_RR_AFTER_DEP
REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3cdb8294e13f..ff8c3735abc9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2700,6 +2700,15 @@ add_render_compute_tuning_settings(struct
drm_i915_private *i915,
0 /* write-only, so skip validation */,
true);
}
+
+ /*
+* This tuning setting proves beneficial only on ATS-M designs; the
+* default "age based" setting is optimal on regular DG2 and other
+* platforms.
+*/
+ if (INTEL_INFO(i915)->tuning_thread_rr_after_dep)
+ wa_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
+ THREAD_EX_ARB_MODE_RR_AFTER_DEP);
}
/*
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 857e8bb6865c..26b25d9434d6 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1080,6 +1080,7 @@ static const struct intel_device_info ats_m_info = {
DG2_FEATURES,
.display = { 0 },
.require_force_probe = 1,
+ .tuning_thread_rr_after_dep = 1,
};
#define XE_HPC_FEATURES \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 0ccde94b225f..6904ad03ca19 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -171,6 +171,7 @@ enum intel_ppgtt_type {
func(has_runtime_pm); \
func(has_snoop); \
func(has_coherent_ggtt); \
+ func(tuning_thread_rr_after_dep); \
func(unfenced_needs_alignment); \
func(hws_needs_physical);
--
2.37.2
[Intel-gfx] [PATCH] Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"
This reverts commit ca6920811aa5428270dd78af0a7a36b10119065a.
The intent of Wa_14015141709 was to inform us that userspace can no
longer control object-level preemption as it has on past platforms
(i.e., by twiddling register bit CS_CHICKEN1[0]). The description of
the workaround in the spec wasn't terribly well-written, and when we
requested clarification from the hardware teams we were told that on the
kernel side we should also probably stop setting
FF_SLICE_CS_CHICKEN1[14], which is the register bit that directs the
hardware to honor the settings in per-context register CS_CHICKEN1. It
turns out that this guidance about FF_SLICE_CS_CHICKEN1[14] was a
mistake; even though CS_CHICKEN1[0] is non-operational and useless to
userspace, there are other bits in the register that do still work and
might need to be adjusted by userspace in the future (e.g., to implement
other workarounds that show up). If we don't set
FF_SLICE_CS_CHICKEN1[14] in i915, then those future workarounds would
not take effect.
This miscommunication came to light because another workaround
(Wa_16013994831) has now shown up that requires userspace to adjust the
value of CS_CHICKEN[10] in certain circumstances. To ensure userspace's
updates to this chicken bit are handled properly by the hardware, we
need to make sure that FF_SLICE_CS_CHICKEN1[14] is once again set by the
kernel.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 ---
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3cdb8294e13f..69a0c6a74474 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2389,7 +2389,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
FF_DOP_CLOCK_GATE_DISABLE);
}
- if (HAS_PERCTX_PREEMPT_CTRL(i915)) {
+ if (IS_GRAPHICS_VER(i915, 9, 12)) {
/*
FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
wa_masked_en(wal,
GEN7_FF_SLICE_CS_CHICKEN1,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2b00ef3626db..d6a1ab6f65de 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1352,9 +1352,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GUC_DEPRIVILEGE(dev_priv) \
(INTEL_INFO(dev_priv)->has_guc_deprivilege)
-#define HAS_PERCTX_PREEMPT_CTRL(i915) \
- ((GRAPHICS_VER(i915) >= 9) && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
-
#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
IS_ALDERLAKE_S(dev_priv))
--
2.37.2
Re: [Intel-gfx] [PATCH] drm/i915/slpc: Fix PCODE IA Freq requests when using SLPC
On Fri, 26 Aug 2022 10:44:34 -0700, Rodrigo Vivi wrote:
>
> Fixes: 7ba79a671568 ("drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled")
> Cc: # v5.15+
> Cc: Ashutosh Dixit
> Tested-by: Sushma Venkatesh Reddy
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/intel_llc.c | 24
> 1 file changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c
> b/drivers/gpu/drm/i915/gt/intel_llc.c
> index 14fe65812e42..2677d62573d9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_llc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_llc.c
> @@ -49,13 +49,28 @@ static unsigned int cpu_max_MHz(void)
> static bool get_ia_constants(struct intel_llc *llc,
>struct ia_constants *consts)
> {
> + struct intel_guc_slpc *slpc = &llc_to_gt(llc)->uc.guc.slpc;
> struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
> struct intel_rps *rps = &llc_to_gt(llc)->rps;
>
> if (!HAS_LLC(i915) || IS_DGFX(i915))
> return false;
>
> - if (rps->max_freq <= rps->min_freq)
> + if (intel_uc_uses_guc_slpc(&llc_to_gt(llc)->uc)) {
> + consts->min_gpu_freq = slpc->min_freq;
> + consts->max_gpu_freq = slpc->rp0_freq;
> + } else {
> + consts->min_gpu_freq = rps->min_freq;
> + consts->max_gpu_freq = rps->max_freq;
> + }
> +
> + if (GRAPHICS_VER(i915) >= 9) {
> + /* Convert GT frequency to 50 HZ units */
> + consts->min_gpu_freq /= GEN9_FREQ_SCALER;
> + consts->max_gpu_freq /= GEN9_FREQ_SCALER;
> + }
> +
> + if (consts->max_gpu_freq <= consts->min_gpu_freq)
> return false;
Hi Rodrigo, sorry, I missed this check previously too and the code is now
equivalent to the previous code.
But now, looking at the code in gen6_update_ring_freq, I am wondering if we
should return true in this case (i.e. remove the check) and we had a bug in
the previous code? Because if we return false, gen6_update_ring_freq will
skip the PCODE programming if 'max_gpu_freq == min_gpu_freq', but why
should we skip the PCODE programming if 'max_gpu_freq == min_gpu_freq'? The
case of 'max_gpu_freq < min_gpu_freq' is fine since the loop in
gen6_update_ring_freq is not entered in that case.
Thanks.
--
Ashutosh
Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/uc: Support for version reduced and multiple firmware files
On 8/26/2022 9:40 AM, John Harrison wrote:
On 8/26/2022 09:35, Ceraolo Spurio, Daniele wrote:
On 8/25/2022 8:05 PM, john.c.harri...@intel.com wrote:
From: John Harrison
There was a misunderstanding in how firmware file compatibility should
be managed within i915. This has been clarified as:
i915 must support all existing firmware releases forever
new minor firmware releases should replace prior versions
only backwards compatibility breaking releases should be a new file
This patch cleans up the single fallback file support that was added
as a quick fix emergency effort. That is now removed in preference to
supporting arbitrary numbers of firmware files per platform.
The patch also adds support for having GuC firmware files that are
named by major version only (because the major version indicates
backwards breaking changes that affect the KMD) and for having HuC
firmware files with no version number at all (because the KMD has no
interface requirements with the HuC).
For GuC, the driver will report via dmesg if the found file is older
than
expected. For HuC, the KMD will no longer require updating for any new
HuC release so will not be able to report what the latest expected
version is.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 442
--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 33 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 16 +-
5 files changed, 319 insertions(+), 186 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0d56b615bf78e..04393932623c7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1868,7 +1868,7 @@ int intel_guc_submission_init(struct intel_guc
*guc)
if (guc->submission_initialized)
return 0;
- if (guc->fw.major_ver_found < 70) {
+ if (guc->fw.file_selected.major_ver < 70) {
ret = guc_lrc_desc_pool_create_v69(guc);
if (ret)
return ret;
@@ -2303,7 +2303,7 @@ static int register_context(struct
intel_context *ce, bool loop)
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_register(ce);
- if (guc->fw.major_ver_found >= 70)
+ if (guc->fw.file_selected.major_ver >= 70)
ret = register_context_v70(guc, ce, loop);
else
ret = register_context_v69(guc, ce, loop);
@@ -2315,7 +2315,7 @@ static int register_context(struct
intel_context *ce, bool loop)
set_context_registered(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
- if (guc->fw.major_ver_found >= 70)
+ if (guc->fw.file_selected.major_ver >= 70)
guc_context_policy_init_v70(ce, loop);
}
@@ -2921,7 +2921,7 @@ static void
__guc_context_set_preemption_timeout(struct intel_guc *guc,
u16 guc_id,
u32 preemption_timeout)
{
- if (guc->fw.major_ver_found >= 70) {
+ if (guc->fw.file_selected.major_ver >= 70) {
struct context_policy policy;
__guc_context_policy_start_klv(&policy, guc_id);
@@ -3186,7 +3186,7 @@ static int guc_context_alloc(struct
intel_context *ce)
static void __guc_context_set_prio(struct intel_guc *guc,
struct intel_context *ce)
{
- if (guc->fw.major_ver_found >= 70) {
+ if (guc->fw.file_selected.major_ver >= 70) {
struct context_policy policy;
__guc_context_policy_start_klv(&policy, ce->guc_id.id);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index f2e7c82985efd..d965ac4832d60 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -436,8 +436,8 @@ static void print_fw_ver(struct intel_uc *uc,
struct intel_uc_fw *fw)
struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
drm_info(&i915->drm, "%s firmware %s version %u.%u\n",
- intel_uc_fw_type_repr(fw->type), fw->path,
- fw->major_ver_found, fw->minor_ver_found);
+ intel_uc_fw_type_repr(fw->type), fw->file_selected.path,
+ fw->file_selected.major_ver, fw->file_selected.minor_ver);
}
static int __uc_init_hw(struct intel_uc *uc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 58547292efa0a..94cf2d4a46e6f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -41,7 +41,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw
*uc_fw,
"%s firmware -> %s\n",
intel_uc_fw_type_repr(uc_fw->type),
status == INTEL_UC_FIRMWARE_SELECTED ?
- uc_fw->path : intel_uc_fw_status_repr(status));
+ uc_fw->file_selected.path : intel_uc_fw
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: add display sub-struct to drm_i915_private (rev2)
== Series Details == Series: drm/i915: add display sub-struct to drm_i915_private (rev2) URL : https://patchwork.freedesktop.org/series/107170/ State : success == Summary == CI Bug Log - changes from CI_DRM_12022_full -> Patchwork_107170v2_full Summary --- **SUCCESS** No regressions found. Participating hosts (12 -> 11) -- Missing(1): shard-rkl Known issues Here are the changes found in Patchwork_107170v2_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@kms: - shard-tglb: [PASS][1] -> [FAIL][2] ([i915#5784]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-tglb6/igt@gem_...@kms.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v2/shard-tglb5/igt@gem_...@kms.html * igt@gem_exec_balancer@parallel-bb-first: - shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-iclb2/igt@gem_exec_balan...@parallel-bb-first.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v2/shard-iclb6/igt@gem_exec_balan...@parallel-bb-first.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: NOTRUN -> [FAIL][5] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v2/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v2/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-kbl4/igt@gem_exec_fair@basic-p...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v2/shard-kbl4/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_lmem_swapping@heavy-verify-random-ccs: - shard-tglb: NOTRUN -> [SKIP][10] ([i915#4613]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v2/shard-tglb7/igt@gem_lmem_swapp...@heavy-verify-random-ccs.html * igt@gem_lmem_swapping@parallel-random: - shard-kbl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v2/shard-kbl1/igt@gem_lmem_swapp...@parallel-random.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-glk: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v2/shard-glk8/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_pxp@reject-modify-context-protection-off-2: - shard-tglb: NOTRUN -> [SKIP][13] ([i915#4270]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v2/shard-tglb7/igt@gem_...@reject-modify-context-protection-off-2.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][14] -> [DMESG-WARN][15] ([i915#180]) +4 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-kbl4/igt@gem_workarou...@suspend-resume-fd.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v2/shard-kbl1/igt@gem_workarou...@suspend-resume-fd.html - shard-apl: [PASS][16] -> [DMESG-WARN][17] ([i915#180]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-apl8/igt@gem_workarou...@suspend-resume-fd.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v2/shard-apl6/igt@gem_workarou...@suspend-resume-fd.html * igt@i915_query@test-query-geometry-subslices: - shard-tglb: NOTRUN -> [SKIP][18] ([i915#5723]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v2/shard-tglb7/igt@i915_qu...@test-query-geometry-subslices.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip: - shard-tglb: NOTRUN -> [SKIP][19] ([i915#5286]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v2/shard-tglb7/igt@kms_big...@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html * igt@kms_big_fb@y-tiled-64bpp-rotate-90: - shard-tglb: NOTRUN -> [SKIP][20] ([fdo#111614]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v2/shard-tglb7/igt@kms_big...@y-tiled-64bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow: - shard-tglb: NOTRUN -> [SKIP][21] ([fdo#111615]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v2/shard-tglb7/igt@kms_big...@yf-tiled-addfb-size-offset-overflow.html * igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_rc_ccs:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/slpc: Set rps' min and max frequencies even with SLPC. (rev5)
== Series Details ==
Series: drm/i915/slpc: Set rps' min and max frequencies even with SLPC. (rev5)
URL : https://patchwork.freedesktop.org/series/107766/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12035 -> Patchwork_107766v5
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_107766v5 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_107766v5, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v5/index.html
Participating hosts (42 -> 38)
--
Missing(4): fi-ctg-p8600 fi-hsw-4770 fi-bdw-samus fi-hsw-4200u
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107766v5:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gt_pm:
- fi-rkl-guc: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-rkl-guc/igt@i915_selftest@live@gt_pm.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v5/fi-rkl-guc/igt@i915_selftest@live@gt_pm.html
- bat-adlp-4: [PASS][3] -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/bat-adlp-4/igt@i915_selftest@live@gt_pm.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v5/bat-adlp-4/igt@i915_selftest@live@gt_pm.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_pm:
- {bat-rpls-1}: [PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/bat-rpls-1/igt@i915_selftest@live@gt_pm.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v5/bat-rpls-1/igt@i915_selftest@live@gt_pm.html
- {bat-rplp-1}: [PASS][7] -> [DMESG-FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/bat-rplp-1/igt@i915_selftest@live@gt_pm.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v5/bat-rplp-1/igt@i915_selftest@live@gt_pm.html
- {bat-adln-1}: [PASS][9] -> [DMESG-FAIL][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/bat-adln-1/igt@i915_selftest@live@gt_pm.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v5/bat-adln-1/igt@i915_selftest@live@gt_pm.html
Known issues
Here are the changes found in Patchwork_107766v5 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600: NOTRUN -> [FAIL][11] ([fdo#103375])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v5/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][12] -> [DMESG-FAIL][13] ([i915#4528])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v5/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-bdw-5557u: [PASS][14] -> [INCOMPLETE][15] ([i915#146] /
[i915#6598])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v5/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bsw-nick:NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v5/fi-bsw-nick/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-rkl-11600: NOTRUN -> [SKIP][17] ([fdo#111827])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v5/fi-rkl-11600/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: [PASS][18] -> [FAIL][19] ([i915#6298])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12035/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v5/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-bsw-nick:NOTRUN -> [SKIP][20] ([fdo#109271])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v5/fi-bsw-nick/igt@kms_pipe_crc_ba...@suspend-read-crc.html
* igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][21] ([i915#4312] / [i915#
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/kms: Stop registering multiple /sys/class/backlight devs for a single display
== Series Details == Series: drm/kms: Stop registering multiple /sys/class/backlight devs for a single display URL : https://patchwork.freedesktop.org/series/107674/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12022_full -> Patchwork_107674v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_107674v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_107674v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (12 -> 13) -- Additional (1): shard-dg1 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_107674v1_full: ### IGT changes ### Possible regressions * igt@kms_setmode@basic@pipe-a-edp-1: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-tglb2/igt@kms_setmode@ba...@pipe-a-edp-1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107674v1/shard-tglb8/igt@kms_setmode@ba...@pipe-a-edp-1.html Known issues Here are the changes found in Patchwork_107674v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@parallel-bb-first: - shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-iclb2/igt@gem_exec_balan...@parallel-bb-first.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107674v1/shard-iclb8/igt@gem_exec_balan...@parallel-bb-first.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: NOTRUN -> [FAIL][5] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107674v1/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107674v1/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +2 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-kbl4/igt@gem_exec_fair@basic-p...@vecs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107674v1/shard-kbl4/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_suspend@basic-s3@smem: - shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#5904] / [i915#62]) +4 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-apl8/igt@gem_exec_suspend@basic...@smem.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107674v1/shard-apl2/igt@gem_exec_suspend@basic...@smem.html * igt@gem_lmem_swapping@heavy-multi: - shard-kbl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107674v1/shard-kbl1/igt@gem_lmem_swapp...@heavy-multi.html * igt@gem_lmem_swapping@heavy-verify-random-ccs: - shard-tglb: NOTRUN -> [SKIP][13] ([i915#4613]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107674v1/shard-tglb5/igt@gem_lmem_swapp...@heavy-verify-random-ccs.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107674v1/shard-glk8/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_pxp@reject-modify-context-protection-off-2: - shard-tglb: NOTRUN -> [SKIP][15] ([i915#4270]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107674v1/shard-tglb5/igt@gem_...@reject-modify-context-protection-off-2.html * igt@i915_pm_dc@dc6-dpms: - shard-kbl: NOTRUN -> [FAIL][16] ([i915#454]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107674v1/shard-kbl1/igt@i915_pm...@dc6-dpms.html * igt@i915_query@test-query-geometry-subslices: - shard-tglb: NOTRUN -> [SKIP][17] ([i915#5723]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107674v1/shard-tglb5/igt@i915_qu...@test-query-geometry-subslices.html * igt@i915_suspend@sysfs-reader: - shard-kbl: [PASS][18] -> [DMESG-WARN][19] ([i915#180]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-kbl1/igt@i915_susp...@sysfs-reader.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107674v1/shard-kbl7/igt@i915_susp...@sysfs-reader.html * igt@kms_addfb_basic@master-rm
[Intel-gfx] [CI] PR for versionless GuC and HuC files
The following changes since commit 8413c63c7a539a912be8851ce941eea32dcd1786: Merge branch 'lenovo-thinkpad-x13s' of https://github.com/mrhpearson/linux-firmware (2022-08-15 09:02:17 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware guc_huc_nover for you to fetch changes up to e1fd8dd318f121dc32e889de1d43c408a00ccce9: i915: Add versionless GuC and HuC files (2022-08-25 15:55:48 -0700) John Harrison (1): i915: Add versionless GuC and HuC files WHENCE | 15 +++ i915/adlp_guc_70.bin | Bin 0 -> 289472 bytes i915/dg1_guc_70.bin | Bin 0 -> 265152 bytes i915/dg1_huc.bin | Bin 0 -> 589888 bytes i915/dg2_guc_70.bin | Bin 0 -> 369600 bytes i915/tgl_huc.bin | Bin 0 -> 589888 bytes 6 files changed, 15 insertions(+) create mode 100644 i915/adlp_guc_70.bin create mode 100644 i915/dg1_guc_70.bin create mode 100644 i915/dg1_huc.bin create mode 100644 i915/dg2_guc_70.bin create mode 100644 i915/tgl_huc.bin
[Intel-gfx] ✗ Fi.CI.IGT: failure for Enable Pipewriteback (rev2)
== Series Details ==
Series: Enable Pipewriteback (rev2)
URL : https://patchwork.freedesktop.org/series/107440/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12022_full -> Patchwork_107440v2_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_107440v2_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_107440v2_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (12 -> 12)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107440v2_full:
### IGT changes ###
Possible regressions
* igt@device_reset@unbind-reset-rebind:
- shard-tglb: [PASS][1] -> [DMESG-WARN][2] +3 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-tglb3/igt@device_re...@unbind-reset-rebind.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v2/shard-tglb2/igt@device_re...@unbind-reset-rebind.html
* igt@kms_atomic_transition@modeset-transition-nonblocking@1x-outputs:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-tglb3/igt@kms_atomic_transition@modeset-transition-nonblock...@1x-outputs.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v2/shard-tglb8/igt@kms_atomic_transition@modeset-transition-nonblock...@1x-outputs.html
Warnings
* igt@kms_writeback@writeback-check-output:
- shard-tglb: [SKIP][5] ([i915#2437]) -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-tglb6/igt@kms_writeb...@writeback-check-output.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v2/shard-tglb1/igt@kms_writeb...@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-tglb: [SKIP][7] ([i915#2437]) -> [FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-tglb5/igt@kms_writeb...@writeback-fb-id.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v2/shard-tglb7/igt@kms_writeb...@writeback-fb-id.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@device_reset@unbind-reset-rebind:
- {shard-tglu}: NOTRUN -> [DMESG-WARN][9] +2 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v2/shard-tglu-4/igt@device_re...@unbind-reset-rebind.html
* igt@kms_prime@basic-crc-vgem@second-to-first:
- {shard-tglu}: [PASS][10] -> [FAIL][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-tglu-4/igt@kms_prime@basic-crc-v...@second-to-first.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v2/shard-tglu-4/igt@kms_prime@basic-crc-v...@second-to-first.html
* igt@kms_writeback@writeback-check-output:
- {shard-tglu}: NOTRUN -> [DMESG-FAIL][12]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v2/shard-tglu-4/igt@kms_writeb...@writeback-check-output.html
Known issues
Here are the changes found in Patchwork_107440v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][13] -> [SKIP][14] ([i915#4525]) +2 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-iclb2/igt@gem_exec_balan...@parallel-bb-first.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v2/shard-iclb7/igt@gem_exec_balan...@parallel-bb-first.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [PASS][15] -> [FAIL][16] ([i915#2846])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-kbl1/igt@gem_exec_f...@basic-deadline.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v2/shard-kbl7/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][17] -> [FAIL][18] ([i915#2842]) +1 similar
issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-tglb5/igt@gem_exec_fair@basic-f...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v2/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][19] ([i915#2842])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v2/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#4613]
[Intel-gfx] [PATCH] drm/i915/slpc: Fix PCODE IA Freq requests when using SLPC
We need to inform PCODE of a desired ring frequencies so PCODE update
the memory frequencies to us. rps->min_freq and rps->max_freq are the
frequencies used in that request. However they were unset when SLPC was
enabled and PCODE never updated the memory freq.
v2 (as Suggested by Ashutosh): if SLPC is in use, let's pick the right
frequencies from the get_ia_constants instead of the fake init of
rps' min and max.
v3: don't forget the max <= min return
Fixes: 7ba79a671568 ("drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled")
Cc: # v5.15+
Cc: Ashutosh Dixit
Tested-by: Sushma Venkatesh Reddy
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_llc.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c
b/drivers/gpu/drm/i915/gt/intel_llc.c
index 14fe65812e42..2677d62573d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_llc.c
+++ b/drivers/gpu/drm/i915/gt/intel_llc.c
@@ -49,13 +49,28 @@ static unsigned int cpu_max_MHz(void)
static bool get_ia_constants(struct intel_llc *llc,
struct ia_constants *consts)
{
+ struct intel_guc_slpc *slpc = &llc_to_gt(llc)->uc.guc.slpc;
struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
struct intel_rps *rps = &llc_to_gt(llc)->rps;
if (!HAS_LLC(i915) || IS_DGFX(i915))
return false;
- if (rps->max_freq <= rps->min_freq)
+ if (intel_uc_uses_guc_slpc(&llc_to_gt(llc)->uc)) {
+ consts->min_gpu_freq = slpc->min_freq;
+ consts->max_gpu_freq = slpc->rp0_freq;
+ } else {
+ consts->min_gpu_freq = rps->min_freq;
+ consts->max_gpu_freq = rps->max_freq;
+ }
+
+ if (GRAPHICS_VER(i915) >= 9) {
+ /* Convert GT frequency to 50 HZ units */
+ consts->min_gpu_freq /= GEN9_FREQ_SCALER;
+ consts->max_gpu_freq /= GEN9_FREQ_SCALER;
+ }
+
+ if (consts->max_gpu_freq <= consts->min_gpu_freq)
return false;
consts->max_ia_freq = cpu_max_MHz();
@@ -65,13 +80,6 @@ static bool get_ia_constants(struct intel_llc *llc,
/* convert DDR frequency from units of 266.6MHz to bandwidth */
consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3);
- consts->min_gpu_freq = rps->min_freq;
- consts->max_gpu_freq = rps->max_freq;
- if (GRAPHICS_VER(i915) >= 9) {
- /* Convert GT frequency to 50 HZ units */
- consts->min_gpu_freq /= GEN9_FREQ_SCALER;
- consts->max_gpu_freq /= GEN9_FREQ_SCALER;
- }
return true;
}
--
2.37.1
Re: [Intel-gfx] [PATCH 1/1] drm/i915/dgfx: Release mmap on rpm suspend
On 25/08/2022 11:54, Anshuman Gupta wrote:
Release all mmap mapping for all lmem objects which are associated
with userfault such that, while pcie function in D3hot, any access
to memory mappings will raise a userfault.
Runtime resume the dgpu(when gem object lies in lmem).
This will transition the dgpu graphics function to D0
state if it was in D3 in order to access the mmap memory
mappings.
v2:
- Squashes the patches. [Matt Auld]
- Add adequate locking for lmem_userfault_list addition. [Matt Auld]
- Reused obj->userfault_count to avoid double addition. [Matt Auld]
- Added i915_gem_object_lock to check
i915_gem_object_is_lmem. [Matt Auld]
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6331
Just double checking, this is needed for DG1 and DG2, right? Are there
any BSpec links we can add here?
Cc: Matthew Auld
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 48 ---
drivers/gpu/drm/i915/gt/intel_gt.c| 2 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/i915_gem.c | 8
5 files changed, 57 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 9f6b14ec189a..40305e2bcd49 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -298,7 +298,8 @@ struct drm_i915_gem_object {
};
/**
-* Whether the object is currently in the GGTT mmap.
+* Whether the object is currently in the GGTT or any other supported
+* fake offset mmap backed by lmem.
*/
unsigned int userfault_count;
struct list_head userfault_link;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 5a5cf332d8a5..6532a634bd20 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -1014,12 +1014,29 @@ static void i915_ttm_delayed_free(struct
drm_i915_gem_object *obj)
ttm_bo_put(i915_gem_to_ttm(obj));
}
+static intel_wakeref_t
+i915_gem_ttm_get_lmem_obj_wakeref(struct drm_i915_gem_object *obj)
+{
+ intel_wakeref_t wakeref = 0;
+
+ if (i915_gem_object_lock_interruptible(obj, NULL))
+ return 0;
+
+ if (i915_gem_object_is_lmem(obj))
+ wakeref =
intel_runtime_pm_get(&to_i915(obj->base.dev)->runtime_pm);
+
+ i915_gem_object_unlock(obj);
+
+ return wakeref;
+}
+
static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
{
struct vm_area_struct *area = vmf->vma;
struct ttm_buffer_object *bo = area->vm_private_data;
struct drm_device *dev = bo->base.dev;
struct drm_i915_gem_object *obj;
+ intel_wakeref_t wakeref = 0;
vm_fault_t ret;
int idx;
@@ -1027,18 +1044,23 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
if (!obj)
return VM_FAULT_SIGBUS;
+ wakeref = i915_gem_ttm_get_lmem_obj_wakeref(obj);
We shouldn't drop the lock here (also failing to acquire the lock should
be fatal), since the object can in thoery transition to/from lmem
inbetween dropping the object lock here and re-acquiring it again below,
which means we might skip grabbing the wakeref here, but then later
touch the list, if say it moves to lmem.
+
/* Sanity check that we allow writing into this object */
if (unlikely(i915_gem_object_is_readonly(obj) &&
-area->vm_flags & VM_WRITE))
- return VM_FAULT_SIGBUS;
+area->vm_flags & VM_WRITE)) {
+ ret = VM_FAULT_SIGBUS;
+ goto out_rpm;
+ }
ret = ttm_bo_vm_reserve(bo, vmf); > if (ret)
- return ret;
+ goto out_rpm;
if (obj->mm.madv != I915_MADV_WILLNEED) {
dma_resv_unlock(bo->base.resv);
- return VM_FAULT_SIGBUS;
+ ret = VM_FAULT_SIGBUS;
+ goto out_rpm;
}
if (!i915_ttm_resource_mappable(bo->resource)) {
@@ -1062,7 +1084,8 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
if (err) {
drm_dbg(dev, "Unable to make resource CPU
accessible\n");
dma_resv_unlock(bo->base.resv);
- return VM_FAULT_SIGBUS;
+ ret = VM_FAULT_SIGBUS;
+ goto out_rpm;
}
}
@@ -1073,12 +1096,25 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
} else {
ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot);
}
+
+ /* ttm_bo_vm_reserve() already has dma_resv_lock */
+ if (!ret && i915_gem_object_is_lmem(obj) && !obj->userfault_count++) {
This might increment userfault_count
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: HuC loading for DG2 (rev2)
== Series Details ==
Series: drm/i915: HuC loading for DG2 (rev2)
URL : https://patchwork.freedesktop.org/series/107477/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12022_full -> Patchwork_107477v2_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_107477v2_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_107477v2_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (12 -> 12)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107477v2_full:
### IGT changes ###
Possible regressions
* igt@gem_exec_suspend@basic-s0@smem:
- shard-glk: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v2/shard-glk8/igt@gem_exec_suspend@basic...@smem.html
* {igt@gem_huc_copy@huc-copy-after-reset} (NEW):
- shard-iclb: NOTRUN -> [SKIP][2] +1 similar issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v2/shard-iclb8/igt@gem_huc_c...@huc-copy-after-reset.html
* igt@i915_pm_rpm@system-suspend-devices:
- shard-iclb: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-iclb3/igt@i915_pm_...@system-suspend-devices.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v2/shard-iclb5/igt@i915_pm_...@system-suspend-devices.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5:
- {shard-rkl}:NOTRUN -> [SKIP][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v2/shard-rkl-5/igt@kms_plane_scal...@plane-downscale-with-modifiers-factor-0-5.html
New tests
-
New tests have been introduced between CI_DRM_12022_full and
Patchwork_107477v2_full:
### New IGT tests (2) ###
* igt@gem_huc_copy@huc-copy-after-reset:
- Statuses : 1 pass(s) 5 skip(s)
- Exec time: [0.0, 0.13] s
* igt@gem_huc_copy@huc-copy-after-suspend-resume:
- Statuses : 6 skip(s)
- Exec time: [0.0, 2.10] s
Known issues
Here are the changes found in Patchwork_107477v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@api_intel_bb@crc32:
- shard-iclb: NOTRUN -> [SKIP][6] ([i915#6230])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v2/shard-iclb3/igt@api_intel...@crc32.html
* igt@drm_buddy@all:
- shard-iclb: NOTRUN -> [SKIP][7] ([i915#6433])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v2/shard-iclb5/igt@drm_bu...@all.html
* igt@feature_discovery@display-2x:
- shard-iclb: NOTRUN -> [SKIP][8] ([i915#1839])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v2/shard-iclb6/igt@feature_discov...@display-2x.html
* igt@gem_create@create-ext-cpu-access-sanity-check:
- shard-iclb: NOTRUN -> [SKIP][9] ([i915#6335])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v2/shard-iclb3/igt@gem_cre...@create-ext-cpu-access-sanity-check.html
* igt@gem_create@create-massive:
- shard-snb: NOTRUN -> [DMESG-WARN][10] ([i915#4991])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v2/shard-snb6/igt@gem_cre...@create-massive.html
- shard-apl: NOTRUN -> [DMESG-WARN][11] ([i915#4991])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v2/shard-apl3/igt@gem_cre...@create-massive.html
- shard-glk: NOTRUN -> [DMESG-WARN][12] ([i915#4991])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v2/shard-glk6/igt@gem_cre...@create-massive.html
- shard-iclb: NOTRUN -> [DMESG-WARN][13] ([i915#4991])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v2/shard-iclb6/igt@gem_cre...@create-massive.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: [PASS][14] -> [DMESG-WARN][15] ([i915#180]) +5
similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12022/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v2/shard-kbl7/igt@gem_ctx_isolation@preservation...@vcs0.html
* igt@gem_ctx_persistence@hostile:
- shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1099]) +2
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v2/shard-snb2/igt@gem_ctx_persiste...@hostile.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-i
Re: [Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness
On Thu, Aug 25, 2022 at 06:44:50PM -0700, Dixit, Ashutosh wrote:
On Thu, 04 Aug 2022 16:21:25 -0700, Umesh Nerlige Ramappa wrote:
Hi Umesh, I am fairly new to this code so some questions will be below will
be newbie questions, thanks for bearing with me.
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 654a092ed3d6..e2d70a9fdac0 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -576,16 +576,24 @@ void intel_context_bind_parent_child(struct intel_context
*parent,
child->parallel.parent = parent;
}
-u64 intel_context_get_total_runtime_ns(const struct intel_context *ce)
+u64 intel_context_get_total_runtime_ns(struct intel_context *ce)
{
u64 total, active;
+ if (ce->ops->update_stats)
+ ce->ops->update_stats(ce);
+
total = ce->stats.runtime.total;
if (ce->ops->flags & COPS_RUNTIME_CYCLES)
total *= ce->engine->gt->clock_period_ns;
active = READ_ONCE(ce->stats.active);
- if (active)
+ /*
+* When COPS_RUNTIME_ACTIVE_TOTAL is set for ce->cops, the backend
+* already provides the total active time of the context, so skip this
+* calculation when this flag is set.
+*/
+ if (active && !(ce->ops->flags & COPS_RUNTIME_ACTIVE_TOTAL))
active = intel_context_clock() - active;
return total + active;
/snip/
@@ -1396,6 +1399,10 @@ static void guc_timestamp_ping(struct work_struct *wrk)
with_intel_runtime_pm(>->i915->runtime_pm, wakeref)
__update_guc_busyness_stats(guc);
+ /* adjust context stats for overflow */
+ xa_for_each(&guc->context_lookup, index, ce)
+ __guc_context_update_clks(ce);
What is the reason for calling __guc_context_update_clks() periodically
from guc_timestamp_ping() since it appears we should just be able to call
__guc_context_update_clks() from intel_context_get_total_runtime_ns() to
update 'active'? Is the reason for calling __guc_context_update_clks()
periodically that the calculations in __guc_context_update_clks() become
invalid if the counters overflow?
Correct, these are 32-bit counters and the worker just tracks overflow.
+
intel_gt_reset_unlock(gt, srcu);
mod_delayed_work(system_highpri_wq, &guc->timestamp.work,
@@ -1469,6 +1476,56 @@ void intel_guc_busyness_unpark(struct intel_gt *gt)
guc->timestamp.ping_delay);
}
+static void __guc_context_update_clks(struct intel_context *ce)
+{
+ struct intel_guc *guc = ce_to_guc(ce);
+ struct intel_gt *gt = ce->engine->gt;
+ u32 *pphwsp, last_switch, engine_id;
+ u64 start_gt_clk, active;
+ unsigned long flags;
+ ktime_t unused;
+
+ spin_lock_irqsave(&guc->timestamp.lock, flags);
+
+ /*
+* GPU updates ce->lrc_reg_state[CTX_TIMESTAMP] when context is switched
+* out, however GuC updates PPHWSP offsets below. Hence KMD (CPU)
+* relies on GuC and GPU for busyness calculations. Due to this, A
+* potential race was highlighted in an earlier review that can lead to
+* double accounting of busyness. While the solution to this is a wip,
+* busyness is still usable for platforms running GuC submission.
+*/
+ pphwsp = ((void *)ce->lrc_reg_state) - LRC_STATE_OFFSET;
+ last_switch = READ_ONCE(pphwsp[PPHWSP_GUC_CONTEXT_USAGE_STAMP_LO]);
+ engine_id = READ_ONCE(pphwsp[PPHWSP_GUC_CONTEXT_USAGE_ENGINE_ID]);
+
+ guc_update_pm_timestamp(guc, &unused);
+
+ if (engine_id != 0x && last_switch) {
+ start_gt_clk = READ_ONCE(ce->stats.runtime.start_gt_clk);
+ __extend_last_switch(guc, &start_gt_clk, last_switch);
+ active = intel_gt_clock_interval_to_ns(gt,
guc->timestamp.gt_stamp - start_gt_clk);
+ WRITE_ONCE(ce->stats.runtime.start_gt_clk, start_gt_clk);
+ WRITE_ONCE(ce->stats.active, active);
Should not need WRITE_ONCE to update regular memory. Not even sure we need
READ_ONCE above.
Not sure I checked what they do. I was thinking these are needed for the
memory ordering (as in be sure that start_gt_clk is updated before
active).
+ } else {
+ lrc_update_runtime(ce);
As was being discussed, should not need this here in this function. See
below too.
In short, I added this here so that a query for busyness following idle
can be obtained immediately. For GuC backend, the context is unpinned
after disabling scheduling on that context and that is asynchronous.
Also if there are more requests on that context, the scheduling may not
be disabled and unpin may not happen, so updated runtime would only be
seen much much later.
It is still safe to call from here because we know that the context is
not active and has switched out. If it did switch in while we were
reading
Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/uc: Support for version reduced and multiple firmware files
On 8/26/2022 09:35, Ceraolo Spurio, Daniele wrote:
On 8/25/2022 8:05 PM, john.c.harri...@intel.com wrote:
From: John Harrison
There was a misunderstanding in how firmware file compatibility should
be managed within i915. This has been clarified as:
i915 must support all existing firmware releases forever
new minor firmware releases should replace prior versions
only backwards compatibility breaking releases should be a new file
This patch cleans up the single fallback file support that was added
as a quick fix emergency effort. That is now removed in preference to
supporting arbitrary numbers of firmware files per platform.
The patch also adds support for having GuC firmware files that are
named by major version only (because the major version indicates
backwards breaking changes that affect the KMD) and for having HuC
firmware files with no version number at all (because the KMD has no
interface requirements with the HuC).
For GuC, the driver will report via dmesg if the found file is older
than
expected. For HuC, the KMD will no longer require updating for any new
HuC release so will not be able to report what the latest expected
version is.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 442 --
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 33 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 16 +-
5 files changed, 319 insertions(+), 186 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0d56b615bf78e..04393932623c7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1868,7 +1868,7 @@ int intel_guc_submission_init(struct intel_guc
*guc)
if (guc->submission_initialized)
return 0;
- if (guc->fw.major_ver_found < 70) {
+ if (guc->fw.file_selected.major_ver < 70) {
ret = guc_lrc_desc_pool_create_v69(guc);
if (ret)
return ret;
@@ -2303,7 +2303,7 @@ static int register_context(struct
intel_context *ce, bool loop)
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_register(ce);
- if (guc->fw.major_ver_found >= 70)
+ if (guc->fw.file_selected.major_ver >= 70)
ret = register_context_v70(guc, ce, loop);
else
ret = register_context_v69(guc, ce, loop);
@@ -2315,7 +2315,7 @@ static int register_context(struct
intel_context *ce, bool loop)
set_context_registered(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
- if (guc->fw.major_ver_found >= 70)
+ if (guc->fw.file_selected.major_ver >= 70)
guc_context_policy_init_v70(ce, loop);
}
@@ -2921,7 +2921,7 @@ static void
__guc_context_set_preemption_timeout(struct intel_guc *guc,
u16 guc_id,
u32 preemption_timeout)
{
- if (guc->fw.major_ver_found >= 70) {
+ if (guc->fw.file_selected.major_ver >= 70) {
struct context_policy policy;
__guc_context_policy_start_klv(&policy, guc_id);
@@ -3186,7 +3186,7 @@ static int guc_context_alloc(struct
intel_context *ce)
static void __guc_context_set_prio(struct intel_guc *guc,
struct intel_context *ce)
{
- if (guc->fw.major_ver_found >= 70) {
+ if (guc->fw.file_selected.major_ver >= 70) {
struct context_policy policy;
__guc_context_policy_start_klv(&policy, ce->guc_id.id);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index f2e7c82985efd..d965ac4832d60 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -436,8 +436,8 @@ static void print_fw_ver(struct intel_uc *uc,
struct intel_uc_fw *fw)
struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
drm_info(&i915->drm, "%s firmware %s version %u.%u\n",
- intel_uc_fw_type_repr(fw->type), fw->path,
- fw->major_ver_found, fw->minor_ver_found);
+ intel_uc_fw_type_repr(fw->type), fw->file_selected.path,
+ fw->file_selected.major_ver, fw->file_selected.minor_ver);
}
static int __uc_init_hw(struct intel_uc *uc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 58547292efa0a..94cf2d4a46e6f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -41,7 +41,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw
*uc_fw,
"%s firmware -> %s\n",
intel_uc_fw_type_repr(uc_fw->type),
status == INTEL_UC_FIRMWARE_SELECTED ?
- uc_fw->path : intel_uc_fw_status_repr(status));
+ uc_fw->file_selected.path : intel_uc_fw_status_repr(status));
}
#endif
@@ -51,84 +
Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/uc: Support for version reduced and multiple firmware files
On 8/25/2022 8:05 PM, john.c.harri...@intel.com wrote:
From: John Harrison
There was a misunderstanding in how firmware file compatibility should
be managed within i915. This has been clarified as:
i915 must support all existing firmware releases forever
new minor firmware releases should replace prior versions
only backwards compatibility breaking releases should be a new file
This patch cleans up the single fallback file support that was added
as a quick fix emergency effort. That is now removed in preference to
supporting arbitrary numbers of firmware files per platform.
The patch also adds support for having GuC firmware files that are
named by major version only (because the major version indicates
backwards breaking changes that affect the KMD) and for having HuC
firmware files with no version number at all (because the KMD has no
interface requirements with the HuC).
For GuC, the driver will report via dmesg if the found file is older than
expected. For HuC, the KMD will no longer require updating for any new
HuC release so will not be able to report what the latest expected
version is.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 442 --
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 33 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 16 +-
5 files changed, 319 insertions(+), 186 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0d56b615bf78e..04393932623c7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1868,7 +1868,7 @@ int intel_guc_submission_init(struct intel_guc *guc)
if (guc->submission_initialized)
return 0;
- if (guc->fw.major_ver_found < 70) {
+ if (guc->fw.file_selected.major_ver < 70) {
ret = guc_lrc_desc_pool_create_v69(guc);
if (ret)
return ret;
@@ -2303,7 +2303,7 @@ static int register_context(struct intel_context *ce,
bool loop)
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_register(ce);
- if (guc->fw.major_ver_found >= 70)
+ if (guc->fw.file_selected.major_ver >= 70)
ret = register_context_v70(guc, ce, loop);
else
ret = register_context_v69(guc, ce, loop);
@@ -2315,7 +2315,7 @@ static int register_context(struct intel_context *ce,
bool loop)
set_context_registered(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
- if (guc->fw.major_ver_found >= 70)
+ if (guc->fw.file_selected.major_ver >= 70)
guc_context_policy_init_v70(ce, loop);
}
@@ -2921,7 +2921,7 @@ static void __guc_context_set_preemption_timeout(struct intel_guc *guc,
u16 guc_id,
u32 preemption_timeout)
{
- if (guc->fw.major_ver_found >= 70) {
+ if (guc->fw.file_selected.major_ver >= 70) {
struct context_policy policy;
__guc_context_policy_start_klv(&policy, guc_id);
@@ -3186,7 +3186,7 @@ static int guc_context_alloc(struct intel_context *ce)
static void __guc_context_set_prio(struct intel_guc *guc,
struct intel_context *ce)
{
- if (guc->fw.major_ver_found >= 70) {
+ if (guc->fw.file_selected.major_ver >= 70) {
struct context_policy policy;
__guc_context_policy_start_klv(&policy, ce->guc_id.id);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index f2e7c82985efd..d965ac4832d60 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -436,8 +436,8 @@ static void print_fw_ver(struct intel_uc *uc, struct
intel_uc_fw *fw)
struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
drm_info(&i915->drm, "%s firmware %s version %u.%u\n",
-intel_uc_fw_type_repr(fw->type), fw->path,
-fw->major_ver_found, fw->minor_ver_found);
+intel_uc_fw_type_repr(fw->type), fw->file_selected.path,
+fw->file_selected.major_ver, fw->file_selected.minor_ver);
}
static int __uc_init_hw(struct intel_uc *uc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 58547292efa0a..94cf2d4a46e6f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -41,7 +41,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
"%s firmware -> %s\n",
intel_uc_fw_type_repr(uc_fw->type),
status == INTEL_UC_FIRMWARE_SELECTED ?
-
Re: [Intel-gfx] [PATCH v2] drm/i915/guc: Remove log size module parameters
On Fri, Aug 26, 2022 at 12:23:43PM +0300, Joonas Lahtinen wrote:
> Remove the module parameters for configuring GuC log size.
>
> We should instead rely on tuning the defaults to be usable for
> reporting bugs.
>
> v2:
> - Use correct 1M unit
>
> Fixes: 8ad0152afb1b ("drm/i915/guc: Make GuC log sizes runtime configurable")
> Signed-off-by: Joonas Lahtinen
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
> Cc: Tvrtko Ursulin
> Cc: John Harrison
> Cc: Alan Previn
> Reviewed-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 7 +++
> drivers/gpu/drm/i915/i915_params.c | 12
> drivers/gpu/drm/i915/i915_params.h | 3 ---
> 3 files changed, 3 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> index 3a2243b4ac9f..55d4b8f8e33e 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> @@ -79,9 +79,9 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
> }
> };
> s32 params[GUC_LOG_SECTIONS_LIMIT] = {
> - i915->params.guc_log_size_crash,
> - i915->params.guc_log_size_debug,
> - i915->params.guc_log_size_capture,
> + GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE / SZ_1M,
> + GUC_LOG_DEFAULT_DEBUG_BUFFER_SIZE / SZ_1M,
> + GUC_LOG_DEFAULT_CAPTURE_BUFFER_SIZE / SZ_1M,
> };
> int i;
>
> @@ -90,7 +90,6 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
>
> /* If debug size > 1MB then bump default crash size to keep the same
> units */
> if (log->sizes[GUC_LOG_SECTIONS_DEBUG].bytes >= SZ_1M &&
> - (i915->params.guc_log_size_crash == -1) &&
> GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE < SZ_1M)
> log->sizes[GUC_LOG_SECTIONS_CRASH].bytes = SZ_1M;
>
> diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> index 06ca5b822111..6fc475a5db61 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -171,18 +171,6 @@ i915_param_named(guc_log_level, int, 0400,
> "GuC firmware logging level. Requires GuC to be loaded. "
> "(-1=auto [default], 0=disable, 1..4=enable with verbosity min..max)");
>
> -i915_param_named(guc_log_size_crash, int, 0400,
> - "GuC firmware logging buffer size for crash dumps (in MB)"
> - "(-1=auto [default], NB: max = 4, other restrictions apply)");
> -
> -i915_param_named(guc_log_size_debug, int, 0400,
> - "GuC firmware logging buffer size for debug logs (in MB)"
> - "(-1=auto [default], NB: max = 16, other restrictions apply)");
> -
> -i915_param_named(guc_log_size_capture, int, 0400,
> - "GuC error capture register dump buffer size (in MB)"
> - "(-1=auto [default], NB: max = 4, other restrictions apply)");
> -
> i915_param_named_unsafe(guc_firmware_path, charp, 0400,
> "GuC firmware path to use instead of the default one");
>
> diff --git a/drivers/gpu/drm/i915/i915_params.h
> b/drivers/gpu/drm/i915/i915_params.h
> index f684d1ab8707..2733cb6cfe09 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -61,9 +61,6 @@ struct drm_printer;
> param(int, invert_brightness, 0, 0600) \
> param(int, enable_guc, -1, 0400) \
> param(int, guc_log_level, -1, 0400) \
> - param(int, guc_log_size_crash, -1, 0400) \
> - param(int, guc_log_size_debug, -1, 0400) \
> - param(int, guc_log_size_capture, -1, 0400) \
> param(char *, guc_firmware_path, NULL, 0400) \
> param(char *, huc_firmware_path, NULL, 0400) \
> param(char *, dmc_firmware_path, NULL, 0400) \
> --
> 2.37.2
>
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg2: Incorporate Wa_16014892111 into DRAW_WATERMARK tuning
On Thu, Aug 25, 2022 at 02:45:05AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/dg2: Incorporate Wa_16014892111 into DRAW_WATERMARK tuning > URL : https://patchwork.freedesktop.org/series/107638/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_12017_full -> Patchwork_107638v1_full > > > Summary > --- > > **SUCCESS** > > No regressions found. Applied to drm-intel-gt-next. Thanks Bala for the review. Matt > > > > Participating hosts (12 -> 11) > -- > > Missing(1): shard-rkl > > Known issues > > > Here are the changes found in Patchwork_107638v1_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_eio@in-flight-contexts-10ms: > - shard-glk: [PASS][1] -> [TIMEOUT][2] ([i915#3063]) >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12017/shard-glk3/igt@gem_...@in-flight-contexts-10ms.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107638v1/shard-glk2/igt@gem_...@in-flight-contexts-10ms.html > > * igt@gem_exec_balancer@parallel-out-fence: > - shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525]) +1 similar > issue >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12017/shard-iclb1/igt@gem_exec_balan...@parallel-out-fence.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107638v1/shard-iclb5/igt@gem_exec_balan...@parallel-out-fence.html > > * igt@gem_exec_fair@basic-none-share@rcs0: > - shard-iclb: [PASS][5] -> [FAIL][6] ([i915#2842]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12017/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107638v1/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html > > * igt@gem_huc_copy@huc-copy: > - shard-apl: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107638v1/shard-apl3/igt@gem_huc_c...@huc-copy.html > > * igt@gem_lmem_swapping@parallel-random-engines: > - shard-kbl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107638v1/shard-kbl4/igt@gem_lmem_swapp...@parallel-random-engines.html > > * igt@i915_pm_dc@dc6-psr: > - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#454]) >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12017/shard-iclb7/igt@i915_pm...@dc6-psr.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107638v1/shard-iclb8/igt@i915_pm...@dc6-psr.html > > * igt@i915_selftest@live@hangcheck: > - shard-snb: [PASS][11] -> [INCOMPLETE][12] ([i915#3921]) >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12017/shard-snb5/igt@i915_selftest@l...@hangcheck.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107638v1/shard-snb5/igt@i915_selftest@l...@hangcheck.html > > * igt@i915_suspend@fence-restore-untiled: > - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12017/shard-apl1/igt@i915_susp...@fence-restore-untiled.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107638v1/shard-apl8/igt@i915_susp...@fence-restore-untiled.html > > * igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_ccs: > - shard-kbl: NOTRUN -> [SKIP][15] ([fdo#109271]) +57 similar > issues >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107638v1/shard-kbl7/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_ccs.html > > * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs: > - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3886]) > +4 similar issues >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107638v1/shard-kbl4/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html > > * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc: > - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#3886]) >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107638v1/shard-apl3/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html > > * igt@kms_chamelium@dp-crc-single: > - shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) > +1 similar issue >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107638v1/shard-apl3/igt@kms_chamel...@dp-crc-single.html > > * igt@kms_chamelium@dp-hpd-enable-disable-mode: > - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) > +3 similar issues >[19]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107638v1/shard-kbl4/igt@kms_chamel...@dp-hpd-enable-disable-mode.html > > * igt@kms_chamelium@vga-hpd-enable-disab
Re: [Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness
On Wed, Aug 24, 2022 at 06:17:19PM -0700, Dixit, Ashutosh wrote: On Fri, 05 Aug 2022 08:18:48 -0700, Umesh Nerlige Ramappa wrote: On Fri, Aug 05, 2022 at 10:45:30AM +0100, Tvrtko Ursulin wrote: > > On 05/08/2022 00:21, Umesh Nerlige Ramappa wrote: >> -static inline struct intel_guc *ce_to_guc(struct intel_context *ce) >> +static inline struct intel_guc *ce_to_guc(const struct intel_context *ce) > > This is odd since the helper now takes away constness. I can't really > figure out why the change is needed? Hi Umesh, I am also wondering about this, I think you missed answering this question from Tvrtko. This helper 'adds' constness, so wasn't sure if the comment was intended for this helper. Thanks, Umesh Thanks. -- Ashutosh
Re: [Intel-gfx] ✓ Fi.CI.BAT: success for Drop version numbers from firmware files (rev3)
On 8/25/2022 20:49, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* Drop version numbers from firmware files (rev3)
*URL:* https://patchwork.freedesktop.org/series/107340/
*State:*success
*Details:*
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v3/index.html
CI Bug Log - changes from CI_DRM_12029 -> Patchwork_107340v3
Summary
*SUCCESS*
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v3/index.html
Participating hosts (33 -> 32)
Missing (1): fi-kbl-soraka
Possible new issues
Here are the unknown changes that may have been introduced in
Patchwork_107340v3:
IGT changes
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
*
igt@i915_module_load@load:
o
{bat-dg2-9}: PASS
-> FAIL
o
{bat-dg2-8}: PASS
-> FAIL
These are expected. Patch 3/3 sets DG2 to only allow the new style file
name and the new files are not yet pushed to the repo. This was
intentional to see that the load would fail as expected.
The DG1, ADL-S and RPL-S results shows that it tried to load the new
style files, failed to find them (as expected), dropped back to the old
style and successfully loaded those and ran with them:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v3/bat-dg1-6/igt@i915_module_l...@load.html
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v3/fi-adl-ddr5/igt@i915_module_l...@load.html
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107340v3/bat-rpls-1/igt@i915_module_l...@load.html
Unfortunately, the ADL-P and ADL-M results are invalid because they are
apparently failing to run due to IOMMU issues that do not appear to be
i915 related. KBL and APL are showing the same failures.
John.
*
o
*
igt@i915_selftest@live@ring_submission:
o {fi-ehl-2}: PASS
-> INCOMPLETE
Known issues
Here are the changes found in Patchwork_107340v3 that come from known
issues:
IGT changes
Issues hit
*
igt@i915_selftest@live@hangcheck:
o
fi-hsw-4770: PASS
-> INCOMPLETE
(i915#4785 )
o
fi-hsw-g3258: PASS
-> INCOMPLETE
(i915#3303
/
i915#4785 )
*
igt@i915_selftest@live@requests:
o fi-pnv-d510: PASS
-> DMESG-FAIL
(i915#4528 )
*
igt@runner@aborted:
o
fi-pnv-d510: NOTRUN -> FAIL
(fdo#109271
/
i915#2403
/
i915#4312 )
o
fi-hsw-g3258: NOTRUN -> FAIL
(fdo#109271
/
i915#4312
/
i915#6246 )
{name}: This element is suppressed. This means it is ignored when
computing
the status of the di
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: stop HPD workers before display driver unregister (rev15)
== Series Details ==
Series: drm/i915/display: stop HPD workers before display driver unregister
(rev15)
URL : https://patchwork.freedesktop.org/series/105557/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12034 -> Patchwork_105557v15
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/index.html
Participating hosts (40 -> 35)
--
Additional (2): fi-kbl-soraka fi-pnv-d510
Missing(7): fi-rkl-11600 fi-hsw-4200u bat-dg2-8 fi-ctg-p8600 fi-hsw-4770
bat-dg2-10 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_105557v15:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_lrc:
- {bat-dg2-9}:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12034/bat-dg2-9/igt@i915_selftest@live@gt_lrc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/bat-dg2-9/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@slpc:
- {bat-rpls-1}: NOTRUN -> [INCOMPLETE][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/bat-rpls-1/igt@i915_selftest@l...@slpc.html
Known issues
Here are the changes found in Patchwork_105557v15 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: NOTRUN -> [DMESG-FAIL][4] ([i915#4494] / [i915#4957])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][5] ([i915#4528])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-dg1-6: NOTRUN -> [INCOMPLETE][6] ([i915#6011])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/bat-dg1-6/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_psr@primary_page_flip:
- fi-pnv-d510:NOTRUN -> [SKIP][7] ([fdo#109271]) +42 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/fi-pnv-d510/igt@kms_psr@primary_page_flip.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#2403] /
[i915#4312])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/fi-pnv-d510/igt@run...@aborted.html
- fi-kbl-soraka: NOTRUN -> [FAIL][9] ([i915#6219])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/fi-kbl-soraka/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}: [DMESG-WARN][10] ([i915#2867]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12034/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-6: [INCOMPLETE][12] ([i915#4418]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12034/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][14] ([i915#4494] / [i915#4957]) ->
[PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12034/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][16] ([i915#4983]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12034/bat-rpls-1/igt@i915_selftest@l...@reset.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [DMESG-WARN][18] ([i915#62]) -> [PASS][19] +13
similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12034/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-2:
- fi-bdw-5557u: [INCOMPLETE][20] ([i915#146] / [i915#6598]) ->
[PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12034/fi-bdw-5557u/igt@kms_pipe_crc_basic@suspend-read-...@pi
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: stop HPD workers before display driver unregister (rev15)
== Series Details == Series: drm/i915/display: stop HPD workers before display driver unregister (rev15) URL : https://patchwork.freedesktop.org/series/105557/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:223:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:225:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:104:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:106:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:110:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:110:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:110:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:111:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:111:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:120:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:127:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:152:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:154:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:155:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:156:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:158:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:158:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:158:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:27:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:29:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:32:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:32:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:36:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:38:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:41:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:41:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:54:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:56:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:59:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:59:15: warning: unreplaced symbol 'mask' +./include/asm-generic/bitop
Re: [Intel-gfx] [PATCH] drm/i915/dg2: Incorporate Wa_16014892111 into DRAW_WATERMARK tuning
On 23.08.2022 13:24, Matt Roper wrote:
> Although register tuning settings are generally implemented via the
> workaround infrastructure, it turns out that the DRAW_WATERMARK register
> is not properly saved/restored by hardware around power events (i.e.,
> RC6 entry) so updates to the value cannot be applied in the usual
> manner. New workaround Wa_16014892111 informs us that any tuning
> updates to this register must instead be applied via an INDIRECT_CTX
> batch buffer. This will ensure that the necessary value is re-applied
> when a context begins running, even if an RC6 entry had wiped the
> register back to hardware defaults since the last context ran.
>
> Fixes: 6dc85721df74 ("drm/i915/dg2: Add additional tuning settings")
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6642
> Signed-off-by: Matt Roper
Reviewed-by: Balasubramani Vivekanandan
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 21 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 --
> 2 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index eec73c66406c..070cec4ff8a4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1242,6 +1242,23 @@ dg2_emit_rcs_hang_wabb(const struct intel_context *ce,
> u32 *cs)
> return cs;
> }
>
> +/*
> + * The bspec's tuning guide asks us to program a vertical watermark value of
> + * 0x3FF. However this register is not saved/restored properly by the
> + * hardware, so we're required to apply the desired value via INDIRECT_CTX
> + * batch buffer to ensure the value takes effect properly. All other bits
> + * in this register should remain at 0 (the hardware default).
> + */
> +static u32 *
> +dg2_emit_draw_watermark_setting(u32 *cs)
> +{
> + *cs++ = MI_LOAD_REGISTER_IMM(1);
> + *cs++ = i915_mmio_reg_offset(DRAW_WATERMARK);
> + *cs++ = REG_FIELD_PREP(VERT_WM_VAL, 0x3FF);
> +
> + return cs;
> +}
> +
> static u32 *
> gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
> {
> @@ -1263,6 +1280,10 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context
> *ce, u32 *cs)
> if (!HAS_FLAT_CCS(ce->engine->i915))
> cs = gen12_emit_aux_table_inv(cs, GEN12_GFX_CCS_AUX_NV);
>
> + /* Wa_16014892111 */
> + if (IS_DG2(ce->engine->i915))
> + cs = dg2_emit_draw_watermark_setting(cs);
> +
> return cs;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 31e129329fb0..3cdb8294e13f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2685,8 +2685,6 @@ add_render_compute_tuning_settings(struct
> drm_i915_private *i915,
> if (IS_DG2(i915)) {
> wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
> wa_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
> - wa_write_clr_set(wal, DRAW_WATERMARK, VERT_WM_VAL,
> - REG_FIELD_PREP(VERT_WM_VAL, 0x3FF));
>
> /*
>* This is also listed as Wa_22012654132 for certain DG2
> --
> 2.37.2
>
[Intel-gfx] ✗ Fi.CI.IGT: failure for Fixes integer overflow or integer truncation issues in page lookups, ttm place configuration and scatterlist creation
== Series Details == Series: Fixes integer overflow or integer truncation issues in page lookups, ttm place configuration and scatterlist creation URL : https://patchwork.freedesktop.org/series/107318/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12021_full -> Patchwork_107318v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_107318v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_107318v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 12) -- Additional (2): shard-rkl shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_107318v1_full: ### IGT changes ### Possible regressions * igt@perf_pmu@rc6-suspend: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-iclb3/igt@perf_...@rc6-suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107318v1/shard-iclb2/igt@perf_...@rc6-suspend.html Warnings * igt@kms_psr@suspend: - shard-iclb: [INCOMPLETE][3] ([i915#6598]) -> [INCOMPLETE][4] +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-iclb5/igt@kms_...@suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107318v1/shard-iclb7/igt@kms_...@suspend.html Known issues Here are the changes found in Patchwork_107318v1_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-apl: ([PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29]) -> ([PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [FAIL][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54]) ([i915#4386]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl8/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl8/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl8/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl8/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl7/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl7/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl7/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl7/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl7/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl6/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl6/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl6/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl6/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl3/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl3/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl3/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl3/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl2/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl1/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl1/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl2/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl1/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl1/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl2/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107318v1/shard-apl3/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107318v1/shard-apl3/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107318v1/shard-apl3/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107318v1/shard-apl6/boot.html [34]: https
[Intel-gfx] [PATCH v7 2/3] drm/i915/fbdev: suspend HPD before fbdev unregistration
HPD event after fbdev unregistration can cause registration of deferred fbdev which will not be unregistered later, causing use-after-free. To avoid it HPD handling should be suspended before fbdev unregistration. It should fix following GPF: [272.634530] general protection fault, probably for non-canonical address 0x6b6b6b6b6b6b6b6b: [#1] PREEMPT SMP NOPTI [272.634536] CPU: 0 PID: 6030 Comm: i915_selftest Tainted: G U 5.18.0-rc5-CI_DRM_11603-g12dccf4f5eef+ #1 [272.634541] Hardware name: Intel Corporation Raptor Lake Client Platform/RPL-S ADP-S DDR5 UDIMM CRB, BIOS RPLSFWI1.R00.2397.A01.2109300731 09/30/2021 [272.634545] RIP: 0010:fb_do_apertures_overlap.part.14+0x26/0x60 ... [272.634582] Call Trace: [272.634583] [272.634585] do_remove_conflicting_framebuffers+0x59/0xa0 [272.634589] remove_conflicting_framebuffers+0x2d/0xc0 [272.634592] remove_conflicting_pci_framebuffers+0xc8/0x110 [272.634595] drm_aperture_remove_conflicting_pci_framebuffers+0x52/0x70 [272.634604] i915_driver_probe+0x63a/0xdd0 [i915] Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5329 Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5510 Signed-off-by: Andrzej Hajda Reviewed-by: Arun R Murthy Reviewed-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_fbdev.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 221336178991f0..2903b9cfa0f834 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -573,7 +573,8 @@ void intel_fbdev_unregister(struct drm_i915_private *dev_priv) if (!ifbdev) return; - cancel_work_sync(&dev_priv->fbdev_suspend_work); + intel_fbdev_set_suspend(&dev_priv->drm, FBINFO_STATE_SUSPENDED, true); + if (!current_is_async()) intel_fbdev_sync(ifbdev); @@ -618,7 +619,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous struct fb_info *info; if (!ifbdev || !ifbdev->vma) - return; + goto set_suspend; info = ifbdev->helper.fbdev; @@ -661,6 +662,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous drm_fb_helper_set_suspend(&ifbdev->helper, state); console_unlock(); +set_suspend: intel_fbdev_hpd_set_suspend(dev_priv, state); } -- 2.25.1
[Intel-gfx] [PATCH v7 3/3] drm/i915/fbdev: do not create fbdev if HPD is suspended
In case of deferred FB setup core can try to create new
framebuffer. Disallow it if hpd_suspended flag is set.
Signed-off-by: Andrzej Hajda
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 2903b9cfa0f834..f287362dbdc68a 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -210,6 +210,12 @@ static int intelfb_create(struct drm_fb_helper *helper,
struct drm_i915_gem_object *obj;
int ret;
+ mutex_lock(&ifbdev->hpd_lock);
+ ret = ifbdev->hpd_suspended ? -EAGAIN : 0;
+ mutex_unlock(&ifbdev->hpd_lock);
+ if (ret)
+ return ret;
+
if (intel_fb &&
(sizes->fb_width > intel_fb->base.width ||
sizes->fb_height > intel_fb->base.height)) {
--
2.25.1
[Intel-gfx] [PATCH v7 1/3] drm/i915/hpd: suspend MST at the end of intel_modeset_driver_remove
i915->hotplug.dig_port_work can be queued from intel_hpd_irq_handler called by IRQ handler or by intel_hpd_trigger_irq called from dp_mst. Since dp_mst is suspended after irq handler uninstall, a cleaner approach is to cancel hpd work after intel_dp_mst_suspend, otherwise we risk use-after-free. It should fix following WARNINGS: [283.405824] cpu_latency_qos_update_request called for unknown object [283.405866] WARNING: CPU: 2 PID: 240 at kernel/power/qos.c:296 cpu_latency_qos_update_request+0x2d/0x100 [283.405912] CPU: 2 PID: 240 Comm: kworker/u64:9 Not tainted 5.18.0-rc6-Patchwork_103738v3-g1672d1c43e43+ #1 [283.405915] Hardware name: Intel Corporation Raptor Lake Client Platform/RPL-S ADP-S DDR5 UDIMM CRB, BIOS RPLSFWI1.R00.2397.A01.2109300731 09/30/2021 [283.405916] Workqueue: i915-dp i915_digport_work_func [i915] [283.406020] RIP: 0010:cpu_latency_qos_update_request+0x2d/0x100 ... [283.406040] Call Trace: [283.406041] [283.406044] intel_dp_aux_xfer+0x60e/0x8e0 [i915] [283.406131] ? finish_swait+0x80/0x80 [283.406139] intel_dp_aux_transfer+0xc5/0x2b0 [i915] [283.406218] drm_dp_dpcd_access+0x79/0x130 [drm_display_helper] [283.406227] drm_dp_dpcd_read+0xe2/0xf0 [drm_display_helper] [283.406233] intel_dp_hpd_pulse+0x134/0x570 [i915] [283.406308] ? __down_killable+0x70/0x140 [283.406313] i915_digport_work_func+0xba/0x150 [i915] Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4586 Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5558 Signed-off-by: Andrzej Hajda Reviewed-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_display.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a0f84cbe974fc3..524c4580ae6bc9 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -9000,6 +9000,13 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915) flush_work(&i915->atomic_helper.free_work); drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); + + /* +* MST topology needs to be suspended so we don't have any calls to +* fbdev after it's finalized. MST will be destroyed later as part of +* drm_mode_config_cleanup() +*/ + intel_dp_mst_suspend(i915); } /* part #2: call after irq uninstall */ @@ -9014,13 +9021,6 @@ void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) */ intel_hpd_poll_fini(i915); - /* -* MST topology needs to be suspended so we don't have any calls to -* fbdev after it's finalized. MST will be destroyed later as part of -* drm_mode_config_cleanup() -*/ - intel_dp_mst_suspend(i915); - /* poll work can call into fbdev, hence clean that up afterwards */ intel_fbdev_fini(i915); -- 2.25.1
[Intel-gfx] [PATCH v7 0/3] drm/i915/display: stop HPD workers before display driver unregister
Hi Imre, Jani, Ville, Arun, This patchset is replacement of patch "drm/i915/display: disable HPD workers before display driver unregister" [1]. Ive decided to split patch into two parts - fbdev and MST, there are different issues. Ive also dropped shutdown path, as it has slightly different requirements, and more importantly I am not able to test properly. v2 (thx Arun for review): - reword of commit message (Arun) - intel_fbdev_hpd_set_suspend replaced with intel_fbdev_set_suspend (Arun) v3: - new patch adding suspended flag, to handle https://gitlab.freedesktop.org/drm/intel/-/issues/5950 v4: - check suspend flag also in i915_digport_work_func v5: - added patch blocking FB creation in case HPD is supended, - added R-B from Arun to patch 3, thx v6: - finally, after getting direct access to bat-rpls-2, I have found the source of last WARN, intel_fbdev_hpd_set_suspend was not called in case of deferred setup, fixed in patch 2. v7: - addresed comments from Imre and Jani, - removed patch adding suspended flag [1]: https://patchwork.freedesktop.org/series/103811/ Regards Andrzej Andrzej Hajda (3): drm/i915/hpd: suspend MST at the end of intel_modeset_driver_remove drm/i915/fbdev: suspend HPD before fbdev unregistration drm/i915/fbdev: do not create fbdev if HPD is suspended drivers/gpu/drm/i915/display/intel_display.c | 14 +++--- drivers/gpu/drm/i915/display/intel_fbdev.c | 12 ++-- 2 files changed, 17 insertions(+), 9 deletions(-) -- 2.25.1
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/mtl: Added restriction for plane downscaling
== Series Details ==
Series: series starting with [1/2] drm/i915/mtl: Added restriction for plane
downscaling
URL : https://patchwork.freedesktop.org/series/107800/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12034 -> Patchwork_107800v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107800v1/index.html
Participating hosts (40 -> 37)
--
Additional (2): fi-kbl-soraka fi-pnv-d510
Missing(5): fi-hsw-4200u bat-dg2-8 fi-ctg-p8600 bat-jsl-3 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_107800v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@requests:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][1] ([i915#4528])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107800v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-dg1-6: NOTRUN -> [INCOMPLETE][2] ([i915#6011])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107800v1/bat-dg1-6/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_psr@primary_page_flip:
- fi-pnv-d510:NOTRUN -> [SKIP][3] ([fdo#109271]) +42 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107800v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][4] ([fdo#109271] / [i915#2403] /
[i915#4312])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107800v1/fi-pnv-d510/igt@run...@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][5] ([i915#4312])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107800v1/fi-bdw-5557u/igt@run...@aborted.html
- fi-kbl-soraka: NOTRUN -> [FAIL][6] ([i915#6219])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107800v1/fi-kbl-soraka/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}: [DMESG-WARN][7] ([i915#2867]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12034/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107800v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-6: [INCOMPLETE][9] ([i915#4418]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12034/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107800v1/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][11] ([i915#4983]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12034/bat-rpls-1/igt@i915_selftest@l...@reset.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107800v1/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [DMESG-WARN][13] ([i915#62]) -> [PASS][14] +13
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12034/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107800v1/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#6219]: https://gitlab.freedesktop.org/drm/intel/issues/6219
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6643]: https://gitlab.freedesktop.org/drm/intel/issues/6643
Build changes
-
* Linux: CI_DRM_12034 -> Patchwork_107800v1
CI-20190529: 20190529
CI_DRM_12034: b34ca8196b34f318d0d46cb282fd44fc748d5bbf @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6636: 1298b5f0e1b3e010657ffba41d2e775fab028e08 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107800v1: b34ca8196b34f318d0d46cb282fd44fc748d5bbf @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
6ef29be32c05 drm/i915/mtl: Limit scaler input to 4k in plane scaling
f2ce85d597ba drm/i915/mtl: Added restriction for plane dow
Re: [Intel-gfx] [PATCH v9 1/8] overflow: Move and add few utility macros into overflow
On 25.08.2022 18:47, Kees Cook wrote:
On Wed, Aug 24, 2022 at 05:45:07PM +0900, Gwan-gyeong Mun wrote:
It moves overflows_type utility macro into overflow header from i915_utils
header. The overflows_type can be used to catch the truncaion (overflow)
between different data types. And it adds check_assign() macro which
performs an assigning source value into destination ptr along with an
overflow check. overflow_type macro has been improved to handle the signbit
by gcc's built-in overflow check function. And it adds overflows_ptr()
helper macro for checking the overflows between a value and a pointer
type/value.
v3: Add is_type_unsigned() macro (Mauro)
Modify overflows_type() macro to consider signed data types (Mauro)
Fix the problem that safe_conversion() macro always returns true
v4: Fix kernel-doc markups
v6: Move macro addition location so that it can be used by other than drm
subsystem (Jani, Mauro, Andi)
Change is_type_unsigned to is_unsigned_type to have the same name form
as is_signed_type macro
v8: Add check_assign() and remove safe_conversion() (Kees)
Fix overflows_type() to use gcc's built-in overflow function (Andrzej)
Add overflows_ptr() to allow overflow checking when assigning a value
into a pointer variable (G.G.)
v9: Fix overflows_type() to use __builtin_add_overflow() instead of
__builtin_add_overflow_p() (Andrzej)
Fix overflows_ptr() to use overflows_type() with the unsigned long type
(Andrzej)
Signed-off-by: Gwan-gyeong Mun
Cc: Thomas Hellström
Cc: Matthew Auld
Cc: Nirmoy Das
Cc: Jani Nikula
Cc: Andi Shyti
Cc: Andrzej Hajda
Cc: Mauro Carvalho Chehab
Cc: Kees Cook
Reviewed-by: Mauro Carvalho Chehab (v5)
---
drivers/gpu/drm/i915/i915_user_extensions.c | 3 +-
drivers/gpu/drm/i915/i915_utils.h | 5 +-
include/linux/overflow.h| 62 +
3 files changed, 64 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_user_extensions.c
b/drivers/gpu/drm/i915/i915_user_extensions.c
index c822d0aafd2d..6f6b5b910968 100644
--- a/drivers/gpu/drm/i915/i915_user_extensions.c
+++ b/drivers/gpu/drm/i915/i915_user_extensions.c
@@ -50,8 +50,7 @@ int i915_user_extensions(struct i915_user_extension __user
*ext,
if (err)
return err;
- if (get_user(next, &ext->next_extension) ||
- overflows_type(next, ext))
+ if (get_user(next, &ext->next_extension) || overflows_ptr(next))
return -EFAULT;
ext = u64_to_user_ptr(next);
I continue to dislike the layers of macros and specialization here.
This is just a fancy version of check_assign():
if (get_user(next, &ext->next_extension) || check_assign(next, &ext))
return -EFAULT;
However, the __builtin_*_overflow() family only wants to work on
integral types, so this needs to be slightly expanded:
uintptr_t kptr;
...
if (get_user(next, &ext->next_extension) || check_assign(next, &kptr))
return -EFAULT;
ext = (void * __user)kptr;
But, it does seem like the actual problem here is that u64_to_user_ptr()
is not performing the checking? It's used heavily in the drm code.
Is a check_assign_user_ptr() needed?
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drivers/gpu/drm/i915/i915_utils.h
index c10d68cdc3ca..eb0ded23fa9c 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -32,6 +32,7 @@
#include
#include
#include
+#include
#ifdef CONFIG_X86
#include
@@ -111,10 +112,6 @@ bool i915_error_injected(void);
#define range_overflows_end_t(type, start, size, max) \
range_overflows_end((type)(start), (type)(size), (type)(max))
-/* Note we don't consider signbits :| */
-#define overflows_type(x, T) \
- (sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T))
-
#define ptr_mask_bits(ptr, n) ({ \
unsigned long __v = (unsigned long)(ptr); \
(typeof(ptr))(__v & -BIT(n)); \
diff --git a/include/linux/overflow.h b/include/linux/overflow.h
index f1221d11f8e5..6af9df1d67a1 100644
--- a/include/linux/overflow.h
+++ b/include/linux/overflow.h
@@ -52,6 +52,68 @@ static inline bool __must_check __must_check_overflow(bool
overflow)
return unlikely(overflow);
}
+/**
+ * overflows_type - helper for checking the overflows between data types or
+ * values
+ *
+ * @x: Source value or data type for overflow check
+ * @T: Destination value or data type for overflow check
+ *
+ * It compares the values or data type between the first and second argument to
+ * check whether overflow can occur when assigning the first argument to the
+ * variable of the second argument. Source and Destination can be singned or
+ * unsigned data types. Source and Destination can be different d
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/dp: add drm_dp_phy_name() and use it in i915
== Series Details == Series: drm/dp: add drm_dp_phy_name() and use it in i915 URL : https://patchwork.freedesktop.org/series/107266/ State : success == Summary == CI Bug Log - changes from CI_DRM_12021_full -> Patchwork_107266v1_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_107266v1_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_107266v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 11) -- Additional (1): shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_107266v1_full: ### IGT changes ### Warnings * igt@kms_psr@suspend: - shard-iclb: [INCOMPLETE][1] ([i915#6598]) -> [INCOMPLETE][2] +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-iclb5/igt@kms_...@suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107266v1/shard-iclb2/igt@kms_...@suspend.html Known issues Here are the changes found in Patchwork_107266v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@parallel-bb-first: - shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-iclb1/igt@gem_exec_balan...@parallel-bb-first.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107266v1/shard-iclb8/igt@gem_exec_balan...@parallel-bb-first.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: [PASS][5] -> [FAIL][6] ([i915#2842]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-kbl4/igt@gem_exec_fair@basic-n...@vecs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107266v1/shard-kbl1/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: NOTRUN -> [FAIL][7] ([i915#2842]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107266v1/shard-kbl1/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][8] -> [SKIP][9] ([i915#2190]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-tglb5/igt@gem_huc_c...@huc-copy.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107266v1/shard-tglb6/igt@gem_huc_c...@huc-copy.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][10] -> [DMESG-WARN][11] ([i915#180]) +4 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-kbl7/igt@gem_workarou...@suspend-resume-fd.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107266v1/shard-kbl7/igt@gem_workarou...@suspend-resume-fd.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp: - shard-kbl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1937]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107266v1/shard-kbl1/igt@i915_pm_lpsp@kms-l...@kms-lpsp-dp.html * igt@i915_suspend@forcewake: - shard-kbl: [PASS][13] -> [INCOMPLETE][14] ([i915#3614] / [i915#4817] / [i915#6598]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-kbl1/igt@i915_susp...@forcewake.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107266v1/shard-kbl4/igt@i915_susp...@forcewake.html * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc: - shard-glk: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3886]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107266v1/shard-glk9/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc: - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3886]) +6 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107266v1/shard-kbl1/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html * igt@kms_chamelium@hdmi-audio: - shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107266v1/shard-kbl4/igt@kms_chamel...@hdmi-audio.html * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode: - shard-iclb: NOTRUN -> [SKIP][18] ([i915#2672]) +5 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107266v1/shard-iclb6/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscal...@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][19] ([i915#3
Re: [Intel-gfx] [PATCH 1/7] drm/i915/hwmon: Add HWMON infrastructure
On Thu, Aug 25, 2022 at 06:51:12PM +0530, Badal Nilawar wrote:
> From: Dale B Stimson
>
> The i915 HWMON module will be used to expose voltage, power and energy
> values for dGfx. Here we set up i915 hwmon infrastructure including i915
> hwmon registration, basic data structures and functions.
>
> v2:
> - Create HWMON infra patch (Ashutosh)
> - Fixed review comments (Jani)
> - Remove "select HWMON" from i915/Kconfig (Jani)
> v3: Use hwm_ prefix for static functions (Ashutosh)
> v4: s/#ifdef CONFIG_HWMON/#if IS_REACHABLE(CONFIG_HWMON)/ since the former
> doesn't work if hwmon is compiled as a module (Guenter)
> v5: Fixed review comments (Jani)
>
> Cc: Guenter Roeck
> Signed-off-by: Dale B Stimson
> Signed-off-by: Ashutosh Dixit
> Signed-off-by: Riana Tauro
> Signed-off-by: Badal Nilawar
Acked-by: Guenter Roeck
> ---
> drivers/gpu/drm/i915/Makefile | 3 +
> drivers/gpu/drm/i915/i915_driver.c | 5 ++
> drivers/gpu/drm/i915/i915_drv.h| 2 +
> drivers/gpu/drm/i915/i915_hwmon.c | 136 +
> drivers/gpu/drm/i915/i915_hwmon.h | 20 +
> 5 files changed, 166 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/i915_hwmon.c
> create mode 100644 drivers/gpu/drm/i915/i915_hwmon.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 522ef9b4aff3..2b235f747490 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -208,6 +208,9 @@ i915-y += gt/uc/intel_uc.o \
> # graphics system controller (GSC) support
> i915-y += gt/intel_gsc.o
>
> +# graphics hardware monitoring (HWMON) support
> +i915-$(CONFIG_HWMON) += i915_hwmon.o
> +
> # modesetting core code
> i915-y += \
> display/hsw_ips.o \
> diff --git a/drivers/gpu/drm/i915/i915_driver.c
> b/drivers/gpu/drm/i915/i915_driver.c
> index 1332c70370a6..248deecd26a5 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -80,6 +80,7 @@
> #include "i915_drm_client.h"
> #include "i915_drv.h"
> #include "i915_getparam.h"
> +#include "i915_hwmon.h"
> #include "i915_ioc32.h"
> #include "i915_ioctl.h"
> #include "i915_irq.h"
> @@ -736,6 +737,8 @@ static void i915_driver_register(struct drm_i915_private
> *dev_priv)
>
> intel_gt_driver_register(to_gt(dev_priv));
>
> + i915_hwmon_register(dev_priv);
> +
> intel_display_driver_register(dev_priv);
>
> intel_power_domains_enable(dev_priv);
> @@ -762,6 +765,8 @@ static void i915_driver_unregister(struct
> drm_i915_private *dev_priv)
>
> intel_display_driver_unregister(dev_priv);
>
> + i915_hwmon_unregister(dev_priv);
> +
> intel_gt_driver_unregister(to_gt(dev_priv));
>
> i915_perf_unregister(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 69ce6db6a7c1..7b5b10df3404 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -705,6 +705,8 @@ struct drm_i915_private {
>
> struct i915_perf perf;
>
> + struct i915_hwmon *hwmon;
> +
> /* Abstract the submission mechanism (legacy ringbuffer or execlists)
> away */
> struct intel_gt gt0;
>
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c
> b/drivers/gpu/drm/i915/i915_hwmon.c
> new file mode 100644
> index ..103dd543a214
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> @@ -0,0 +1,136 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#include
> +#include
> +#include
> +
> +#include "i915_drv.h"
> +#include "i915_hwmon.h"
> +#include "i915_reg.h"
> +#include "intel_mchbar_regs.h"
> +
> +struct hwm_reg {
> +};
> +
> +struct hwm_drvdata {
> + struct i915_hwmon *hwmon;
> + struct intel_uncore *uncore;
> + struct device *hwmon_dev;
> + char name[12];
> +};
> +
> +struct i915_hwmon {
> + struct hwm_drvdata ddat;
> + struct mutex hwmon_lock;/* counter overflow logic and
> rmw */
> + struct hwm_reg rg;
> +};
> +
> +static const struct hwmon_channel_info *hwm_info[] = {
> + NULL
> +};
> +
> +static umode_t
> +hwm_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> +u32 attr, int channel)
> +{
> + switch (type) {
> + default:
> + return 0;
> + }
> +}
> +
> +static int
> +hwm_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> + int channel, long *val)
> +{
> + switch (type) {
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static int
> +hwm_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> + int channel, long val)
> +{
> + switch (type) {
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static const struct hwmon_ops hwm_ops = {
> + .is_visible = hwm_is_visible,
> + .read = hwm_read,
> + .write = hwm_write,
> +};
> +
> +static const struct hwmon_chip_info hwm
Re: [Intel-gfx] [PATCH] drm/i915/slpc: Fix PCODE IA Freq requests when using SLPC
On Fri, 26 Aug 2022 03:13:18 -0700, Rodrigo Vivi wrote:
>
> We need to inform PCODE of a desired ring frequencies so PCODE update
> the memory frequencies to us. rps->min_freq and rps->max_freq are the
> frequencies used in that request. However they were unset when SLPC was
> enabled and PCODE never updated the memory freq.
>
> v2 (as Suggested by Ashutosh): if SLPC is in use, let's pick the right
>frequencies from the get_ia_constants instead of the fake init of
>rps' min and max.
Reviewed-by: Ashutosh Dixit
>
> Fixes: 7ba79a671568 ("drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled")
> Cc: # v5.15+
> Cc: Ashutosh Dixit
> Tested-by: Sushma Venkatesh Reddy
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/intel_llc.c | 10 --
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c
> b/drivers/gpu/drm/i915/gt/intel_llc.c
> index 14fe65812e42..766f9526da99 100644
> --- a/drivers/gpu/drm/i915/gt/intel_llc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_llc.c
> @@ -49,6 +49,7 @@ static unsigned int cpu_max_MHz(void)
> static bool get_ia_constants(struct intel_llc *llc,
>struct ia_constants *consts)
> {
> + struct intel_guc_slpc *slpc = &llc_to_gt(llc)->uc.guc.slpc;
> struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
> struct intel_rps *rps = &llc_to_gt(llc)->rps;
>
> @@ -65,8 +66,13 @@ static bool get_ia_constants(struct intel_llc *llc,
> /* convert DDR frequency from units of 266.6MHz to bandwidth */
> consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3);
>
> - consts->min_gpu_freq = rps->min_freq;
> - consts->max_gpu_freq = rps->max_freq;
> + if (intel_uc_uses_guc_slpc(&llc_to_gt(llc)->uc)) {
> + consts->min_gpu_freq = slpc->min_freq;
> + consts->max_gpu_freq = slpc->rp0_freq;
> + } else {
> + consts->min_gpu_freq = rps->min_freq;
> + consts->max_gpu_freq = rps->max_freq;
> + }
> if (GRAPHICS_VER(i915) >= 9) {
> /* Convert GT frequency to 50 HZ units */
> consts->min_gpu_freq /= GEN9_FREQ_SCALER;
> --
> 2.37.1
>
[Intel-gfx] ✓ Fi.CI.IGT: success for Fixes integer overflow or integer truncation issues in page lookups, ttm place configuration and scatterlist creation
== Series Details == Series: Fixes integer overflow or integer truncation issues in page lookups, ttm place configuration and scatterlist creation URL : https://patchwork.freedesktop.org/series/107231/ State : success == Summary == CI Bug Log - changes from CI_DRM_12021_full -> Patchwork_107231v1_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_107231v1_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_107231v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 12) -- Additional (2): shard-rkl shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_107231v1_full: ### IGT changes ### Warnings * igt@kms_psr@suspend: - shard-iclb: [INCOMPLETE][1] ([i915#6598]) -> [INCOMPLETE][2] +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-iclb5/igt@kms_...@suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107231v1/shard-iclb3/igt@kms_...@suspend.html Known issues Here are the changes found in Patchwork_107231v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglb: [PASS][3] -> [FAIL][4] ([i915#6268]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-tglb5/igt@gem_ctx_e...@basic-nohangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107231v1/shard-tglb5/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107231v1/shard-kbl7/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107231v1/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-kbl1/igt@gem_exec_fair@basic-pace-s...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107231v1/shard-kbl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_lmem_swapping@heavy-multi: - shard-kbl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107231v1/shard-kbl4/igt@gem_lmem_swapp...@heavy-multi.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][12] -> [DMESG-WARN][13] ([i915#180]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl3/igt@gem_workarou...@suspend-resume-context.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107231v1/shard-apl8/igt@gem_workarou...@suspend-resume-context.html * igt@gen9_exec_parse@batch-without-end: - shard-tglb: NOTRUN -> [SKIP][14] ([i915#2527] / [i915#2856]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107231v1/shard-tglb5/igt@gen9_exec_pa...@batch-without-end.html * igt@i915_pm_dc@dc9-dpms: - shard-iclb: [PASS][15] -> [SKIP][16] ([i915#4281]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-iclb5/igt@i915_pm...@dc9-dpms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107231v1/shard-iclb3/igt@i915_pm...@dc9-dpms.html * igt@i915_selftest@live@hangcheck: - shard-snb: [PASS][17] -> [INCOMPLETE][18] ([i915#3921]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-snb6/igt@i915_selftest@l...@hangcheck.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107231v1/shard-snb6/igt@i915_selftest@l...@hangcheck.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180: - shard-tglb: NOTRUN -> [SKIP][19] ([i915#5286]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107231v1/shard-tglb5/igt@kms_big...@4-tiled-max-hw-stride-32bpp-rotate-180.html * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc: - shard-glk: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3886]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107231v1/shard-glk2/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-b-bad-rotation-90-y_t
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave and Daniel, Sorry for the delay here. I hope we still have time for these. But no big deal if this needs to wait until next week. Here goes drm-intel-fixes-2022-08-26: - GVT fixes including fix for a CommetLake regression in mmio table and misc doc and typo fixes - Fix CCS handling (Matt) - Fix for guc requests after reset (Daniele) - Display DSI related fixes (Jani) - Display backlight related fixes (Arun, Jouni) Thanks, Rodrigo. The following changes since commit 1c23f9e627a7b412978b4e852793c5e3c3efc555: Linux 6.0-rc2 (2022-08-21 17:32:54 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2022-08-26 for you to fetch changes up to 6067c82c576af13a6b1c892b42ac4a189aced8ee: drm/i915/backlight: Disable pps power hook for aux based backlight (2022-08-23 21:27:25 -0400) - GVT fixes including fix for a CommetLake regression in mmio table and misc doc and typo fixes - Fix CCS handling (Matt) - Fix for guc requests after reset (Daniele) - Display DSI related fixes (Jani) - Display backlight related fixes (Arun, Jouni) Alex Williamson (1): drm/i915/gvt: Fix Comet Lake Arun R Murthy (1): drm/i915/display: avoid warnings when registering dual panel backlight Colin Ian King (1): drm/i915/reg: Fix spelling mistake "Unsupport" -> "Unsupported" Daniele Ceraolo Spurio (1): drm/i915/guc: clear stalled request after a reset Jani Nikula (2): drm/i915/dsi: filter invalid backlight and CABC ports drm/i915/dsi: fix dual-link DSI backlight and CABC ports for display 11+ Jiapeng Chong (3): drm/i915/gvt: Fix kernel-doc drm/i915/gvt: Fix kernel-doc drm/i915/gvt: Fix kernel-doc Jouni Högander (1): drm/i915/backlight: Disable pps power hook for aux based backlight Julia Lawall (1): drm/i915/gvt: fix typo in comment Matthew Auld (1): drm/i915/ttm: fix CCS handling Rodrigo Vivi (1): Merge tag 'gvt-fixes-2022-08-22' of https://github.com/intel/gvt-linux into drm-intel-fixes drivers/gpu/drm/i915/display/icl_dsi.c| 7 drivers/gpu/drm/i915/display/intel_backlight.c| 37 ++- drivers/gpu/drm/i915/display/intel_bios.c | 10 +++--- drivers/gpu/drm/i915/display/intel_dp.c | 2 -- drivers/gpu/drm/i915/display/vlv_dsi.c| 7 drivers/gpu/drm/i915/gt/intel_migrate.c | 44 +++ drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 7 drivers/gpu/drm/i915/gvt/aperture_gm.c| 4 +-- drivers/gpu/drm/i915/gvt/gtt.c| 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 4 +-- drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 3 +- 12 files changed, 76 insertions(+), 53 deletions(-)
[Intel-gfx] [PATCH 1/2] drm/i915/mtl: Added restriction for plane downscaling
The second Scaler (i.e. Scaler 2) does not support vertical downscaling (i.e. it's vertical scale factor must not be greater than 1.0). So, vertical plane downscaling is not supported on MTL, scale factor modified accordingly. Cc: Ville Syrjälä Cc: Manasi Navare Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index bcfde81e4d08..6bfcda748e7b 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1464,9 +1464,12 @@ static int skl_plane_max_scale(struct drm_i915_private *dev_priv, * whether we can use the HQ scaler mode. Assume * the best case. * FIXME need to properly check this later. +* FIXME On MTL, adjust specific scaler's downscaling capability. */ - if (DISPLAY_VER(dev_priv) >= 10 || - !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) + if (IS_METEORLAKE(dev_priv)) + return 0x1; + else if (DISPLAY_VER(dev_priv) >= 10 || +!intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) return 0x3 - 1; else return 0x2 - 1; -- 2.29.0
[Intel-gfx] [PATCH 2/2] drm/i915/mtl: Limit scaler input to 4k in plane scaling
As part of die area reduction max input source modified to 4096
for MTL so modified range check logic of scaler.
Cc: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/skl_scaler.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c
b/drivers/gpu/drm/i915/display/skl_scaler.c
index 4092679be21e..bb40b639ff5d 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -158,10 +158,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
bool force_detach,
/* range checks */
if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
- (DISPLAY_VER(dev_priv) >= 11 &&
+ (DISPLAY_VER(dev_priv) >= 11 && !IS_METEORLAKE(dev_priv) &&
(src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
- (DISPLAY_VER(dev_priv) < 11 &&
+ ((DISPLAY_VER(dev_priv) < 11 && IS_METEORLAKE(dev_priv)) &&
(src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
drm_dbg_kms(&dev_priv->drm,
--
2.29.0
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/slpc: Set rps' min and max frequencies even with SLPC. (rev4)
== Series Details ==
Series: drm/i915/slpc: Set rps' min and max frequencies even with SLPC. (rev4)
URL : https://patchwork.freedesktop.org/series/107766/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12031 -> Patchwork_107766v4
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/index.html
Participating hosts (38 -> 39)
--
Additional (2): bat-adln-1 bat-dg1-5
Missing(1): bat-rpls-2
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107766v4:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rps@basic-api:
- {bat-adln-1}: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/bat-adln-1/igt@i915_pm_...@basic-api.html
* igt@i915_selftest@live@vma:
- {bat-dg2-10}: [PASS][2] -> [DMESG-FAIL][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12031/bat-dg2-10/igt@i915_selftest@l...@vma.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/bat-dg2-10/igt@i915_selftest@l...@vma.html
Known issues
Here are the changes found in Patchwork_107766v4 that come from known issues:
### IGT changes ###
Issues hit
* igt@fbdev@read:
- bat-dg1-5: NOTRUN -> [SKIP][4] ([i915#2582]) +4 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/bat-dg1-5/igt@fb...@read.html
* igt@gem_mmap@basic:
- bat-dg1-5: NOTRUN -> [SKIP][5] ([i915#4083])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/bat-dg1-5/igt@gem_m...@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-5: NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-5: NOTRUN -> [SKIP][7] ([i915#4079]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/bat-dg1-5/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-5: NOTRUN -> [SKIP][8] ([i915#1155])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-5: NOTRUN -> [SKIP][9] ([i915#6621])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/bat-dg1-5/igt@i915_pm_...@basic-api.html
* igt@i915_selftest@live@execlists:
- fi-glk-j4005: [PASS][10] -> [INCOMPLETE][11] ([i915#6443])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12031/fi-glk-j4005/igt@i915_selftest@l...@execlists.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/fi-glk-j4005/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@gem:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][12] ([i915#4528])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/fi-pnv-d510/igt@i915_selftest@l...@gem.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: NOTRUN -> [DMESG-FAIL][13] ([i915#4957])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-dg1-5: NOTRUN -> [INCOMPLETE][14] ([i915#6011])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/bat-dg1-5/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [PASS][15] -> [INCOMPLETE][16] ([i915#5982])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12031/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][17] ([i915#4212]) +7 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/bat-dg1-5/igt@kms_addfb_ba...@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][18] ([i915#4215])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/bat-dg1-5/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
* igt@kms_busy@basic:
- bat-dg1-5: NOTRUN -> [SKIP][19] ([i915#1845] / [i915#4303])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107766v4/bat-dg1-5/igt@kms_b...@basic.html
* igt@kms_chamelium@hdmi-hpd-fast:
- bat-dg1-5: NOTRUN -> [SKIP][20] ([fdo#111827]) +7 similar issues
[20]:
htt
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Replace kmap() with kmap_local_page()
== Series Details == Series: drm/i915: Replace kmap() with kmap_local_page() URL : https://patchwork.freedesktop.org/series/107277/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12021_full -> Patchwork_107277v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_107277v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_107277v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 11) -- Additional (1): shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_107277v1_full: ### IGT changes ### Possible regressions * igt@gem_busy@close-race: - shard-snb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-snb2/igt@gem_b...@close-race.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107277v1/shard-snb2/igt@gem_b...@close-race.html * igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled: - shard-glk: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-glk9/igt@kms_draw_...@draw-method-xrgb2101010-blt-ytiled.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107277v1/shard-glk7/igt@kms_draw_...@draw-method-xrgb2101010-blt-ytiled.html Warnings * igt@kms_psr@suspend: - shard-iclb: [INCOMPLETE][5] ([i915#6598]) -> [INCOMPLETE][6] +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-iclb5/igt@kms_...@suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107277v1/shard-iclb1/igt@kms_...@suspend.html Known issues Here are the changes found in Patchwork_107277v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#6268]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-tglb5/igt@gem_ctx_e...@basic-nohangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107277v1/shard-tglb5/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_eio@in-flight-contexts-1us: - shard-apl: [PASS][9] -> [TIMEOUT][10] ([i915#3063]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-apl7/igt@gem_...@in-flight-contexts-1us.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107277v1/shard-apl3/igt@gem_...@in-flight-contexts-1us.html * igt@gem_exec_balancer@parallel-bb-first: - shard-iclb: [PASS][11] -> [SKIP][12] ([i915#4525]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-iclb1/igt@gem_exec_balan...@parallel-bb-first.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107277v1/shard-iclb8/igt@gem_exec_balan...@parallel-bb-first.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +5 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-kbl4/igt@gem_exec_fair@basic-n...@vecs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107277v1/shard-kbl7/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: NOTRUN -> [FAIL][15] ([i915#2842]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107277v1/shard-kbl1/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_fair@basic-sync@rcs0: - shard-kbl: [PASS][16] -> [SKIP][17] ([fdo#109271]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-kbl7/igt@gem_exec_fair@basic-s...@rcs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107277v1/shard-kbl1/igt@gem_exec_fair@basic-s...@rcs0.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp: - shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#1937]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107277v1/shard-kbl1/igt@i915_pm_lpsp@kms-l...@kms-lpsp-dp.html * igt@i915_suspend@forcewake: - shard-kbl: [PASS][19] -> [INCOMPLETE][20] ([i915#3614] / [i915#4817] / [i915#6598]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-kbl1/igt@i915_susp...@forcewake.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107277v1/shard-kbl4/igt@i915_susp...@forcewake.html * igt@i915_suspend@sysfs-reader: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12021/shard-kbl7/igt@i915_susp...@sysfs-reader.html [22]: https://intel-gfx-
Re: [Intel-gfx] [PATCH 2/5] drm/i915/dpll: replace BUG_ON() with drm_WARN_ON()
On Fri, Aug 26, 2022 at 11:38:14AM +0300, Jani Nikula wrote:
> Avoid BUG_ON(). Actually check the dpll count and bail out loudly with
> drm_WARN_ON() from the loop before overflowing
> i915->dpll.shared_dplls[].
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 118598c9a809..8dd405553cfa 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4199,6 +4199,10 @@ void intel_shared_dpll_init(struct drm_i915_private
> *dev_priv)
> dpll_info = dpll_mgr->dpll_info;
>
> for (i = 0; dpll_info[i].name; i++) {
> + if (drm_WARN_ON(&dev_priv->drm,
> + i >= ARRAY_SIZE(dev_priv->dpll.shared_dplls)))
> + break;
Shame we can't neatly use a BUILD_BUG_ON() when assigning .dpll_info.
For patches 2-5
Reviewed-by: Ville Syrjälä
> +
> drm_WARN_ON(&dev_priv->drm, i != dpll_info[i].id);
> dev_priv->dpll.shared_dplls[i].info = &dpll_info[i];
> }
> @@ -4206,8 +4210,6 @@ void intel_shared_dpll_init(struct drm_i915_private
> *dev_priv)
> dev_priv->dpll.mgr = dpll_mgr;
> dev_priv->dpll.num_shared_dpll = i;
> mutex_init(&dev_priv->dpll.lock);
> -
> - BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS);
> }
>
> /**
> --
> 2.34.1
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 1/5] drm/i915/crt: replace BUG_ON() with drm_WARN_ON()
On Fri, Aug 26, 2022 at 11:38:13AM +0300, Jani Nikula wrote: > Avoid BUG_ON(). Replace with drm_WARN_ON() and early return. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_crt.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_crt.c > b/drivers/gpu/drm/i915/display/intel_crt.c > index 6a3893c8ff22..b92e2d0d14ea 100644 > --- a/drivers/gpu/drm/i915/display/intel_crt.c > +++ b/drivers/gpu/drm/i915/display/intel_crt.c > @@ -643,7 +643,8 @@ static bool intel_crt_detect_ddc(struct drm_connector > *connector) > struct i2c_adapter *i2c; > bool ret = false; > > - BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); > + if (drm_WARN_ON(&dev_priv->drm, crt->base.type != INTEL_OUTPUT_ANALOG)) > + return false; I'd just rip that out entirely. We don't have such checks anywhere else eitheer. > > i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); > edid = intel_crt_get_edid(connector, i2c); > -- > 2.34.1 -- Ville Syrjälä Intel
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Remove log size module parameters (rev2)
== Series Details ==
Series: drm/i915/guc: Remove log size module parameters (rev2)
URL : https://patchwork.freedesktop.org/series/107780/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12031 -> Patchwork_107780v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/index.html
Participating hosts (38 -> 37)
--
Additional (2): bat-adln-1 bat-dg1-5
Missing(3): fi-hsw-4770 bat-rpls-2 bat-dg2-10
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107780v2:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rps@basic-api:
- {bat-adln-1}: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/bat-adln-1/igt@i915_pm_...@basic-api.html
Known issues
Here are the changes found in Patchwork_107780v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@fbdev@read:
- bat-dg1-5: NOTRUN -> [SKIP][2] ([i915#2582]) +4 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/bat-dg1-5/igt@fb...@read.html
* igt@gem_mmap@basic:
- bat-dg1-5: NOTRUN -> [SKIP][3] ([i915#4083])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/bat-dg1-5/igt@gem_m...@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-5: NOTRUN -> [SKIP][4] ([i915#4077]) +2 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-5: NOTRUN -> [SKIP][5] ([i915#4079]) +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/bat-dg1-5/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-5: NOTRUN -> [SKIP][6] ([i915#1155])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-5: NOTRUN -> [SKIP][7] ([i915#6621])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/bat-dg1-5/igt@i915_pm_...@basic-api.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-5: NOTRUN -> [INCOMPLETE][8] ([i915#4418])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [PASS][9] -> [INCOMPLETE][10] ([i915#5982])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12031/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][11] ([i915#4212]) +7 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/bat-dg1-5/igt@kms_addfb_ba...@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][12] ([i915#4215])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/bat-dg1-5/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
* igt@kms_busy@basic:
- bat-dg1-5: NOTRUN -> [SKIP][13] ([i915#1845] / [i915#4303])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/bat-dg1-5/igt@kms_b...@basic.html
* igt@kms_chamelium@hdmi-hpd-fast:
- bat-dg1-5: NOTRUN -> [SKIP][14] ([fdo#111827]) +7 similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/bat-dg1-5/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-5: NOTRUN -> [SKIP][15] ([fdo#109285])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/bat-dg1-5/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_pipe_crc_basic@nonblocking-crc:
- bat-dg1-5: NOTRUN -> [SKIP][16] ([i915#4078]) +13 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/bat-dg1-5/igt@kms_pipe_crc_ba...@nonblocking-crc.html
* igt@kms_psr@sprite_plane_onoff:
- bat-dg1-5: NOTRUN -> [SKIP][17] ([i915#1072] / [i915#4078]) +3
similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/bat-dg1-5/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-5: NOTRUN -> [SKIP][18] ([i915#3555])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v2/bat-dg1-5/igt@kms_setm...@basic-clone-single-crtc.html
* igt@prime_vgem@basi
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Remove log size module parameters (rev2)
== Series Details == Series: drm/i915/guc: Remove log size module parameters (rev2) URL : https://patchwork.freedesktop.org/series/107780/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: some BUG_ON() removals
== Series Details == Series: drm/i915: some BUG_ON() removals URL : https://patchwork.freedesktop.org/series/107785/ State : success == Summary == CI Bug Log - changes from CI_DRM_12031 -> Patchwork_107785v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/index.html Participating hosts (38 -> 38) -- Additional (1): bat-dg1-5 Missing(1): bat-rpls-2 Known issues Here are the changes found in Patchwork_107785v1 that come from known issues: ### IGT changes ### Issues hit * igt@fbdev@read: - bat-dg1-5: NOTRUN -> [SKIP][1] ([i915#2582]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/bat-dg1-5/igt@fb...@read.html * igt@gem_mmap@basic: - bat-dg1-5: NOTRUN -> [SKIP][2] ([i915#4083]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/bat-dg1-5/igt@gem_m...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg1-5: NOTRUN -> [SKIP][3] ([i915#4077]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-5: NOTRUN -> [SKIP][4] ([i915#4079]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/bat-dg1-5/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-5: NOTRUN -> [SKIP][5] ([i915#1155]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-dg1-5: NOTRUN -> [SKIP][6] ([i915#6621]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/bat-dg1-5/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[PASS][7] -> [INCOMPLETE][8] ([i915#4785]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12031/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html - bat-dg1-5: NOTRUN -> [DMESG-FAIL][9] ([i915#4957]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html * igt@i915_suspend@basic-s2idle-without-i915: - bat-dg1-5: NOTRUN -> [INCOMPLETE][10] ([i915#6011]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/bat-dg1-5/igt@i915_susp...@basic-s2idle-without-i915.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: [PASS][11] -> [INCOMPLETE][12] ([i915#5982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12031/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@basic-x-tiled-legacy: - bat-dg1-5: NOTRUN -> [SKIP][13] ([i915#4212]) +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/bat-dg1-5/igt@kms_addfb_ba...@basic-x-tiled-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-5: NOTRUN -> [SKIP][14] ([i915#4215]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/bat-dg1-5/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_busy@basic: - bat-dg1-5: NOTRUN -> [SKIP][15] ([i915#1845] / [i915#4303]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/bat-dg1-5/igt@kms_b...@basic.html * igt@kms_chamelium@hdmi-hpd-fast: - bat-dg1-5: NOTRUN -> [SKIP][16] ([fdo#111827]) +7 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/bat-dg1-5/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg1-5: NOTRUN -> [SKIP][17] ([fdo#109285]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/bat-dg1-5/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@nonblocking-crc: - bat-dg1-5: NOTRUN -> [SKIP][18] ([i915#4078]) +13 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/bat-dg1-5/igt@kms_pipe_crc_ba...@nonblocking-crc.html * igt@kms_psr@sprite_plane_onoff: - bat-dg1-5: NOTRUN -> [SKIP][19] ([i915#1072] / [i915#4078]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/bat-dg1-5/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg1-5: NOTRUN -> [SKIP][20] ([i915#3555]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107785v1/bat-dg1-5/igt@kms_setm...@basic-clone-single-crtc.html * igt@prim
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Add DP MST DSC support to i915 (rev8)
== Series Details == Series: Add DP MST DSC support to i915 (rev8) URL : https://patchwork.freedesktop.org/series/101492/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/101492/revisions/8/mbox/ not applied Applying: drm: Add missing DP DSC extended capability definitions. Applying: drm/i915: Fix intel_dp_mst_compute_link_config Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_dp_mst.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_dp_mst.c Applying: drm/i915: Add DSC support to MST path Applying: drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate function error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_dp_mst.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0004 drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate function When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".
[Intel-gfx] [PATCH] drm/i915/slpc: Fix PCODE IA Freq requests when using SLPC
We need to inform PCODE of a desired ring frequencies so PCODE update
the memory frequencies to us. rps->min_freq and rps->max_freq are the
frequencies used in that request. However they were unset when SLPC was
enabled and PCODE never updated the memory freq.
v2 (as Suggested by Ashutosh): if SLPC is in use, let's pick the right
frequencies from the get_ia_constants instead of the fake init of
rps' min and max.
Fixes: 7ba79a671568 ("drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled")
Cc: # v5.15+
Cc: Ashutosh Dixit
Tested-by: Sushma Venkatesh Reddy
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_llc.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c
b/drivers/gpu/drm/i915/gt/intel_llc.c
index 14fe65812e42..766f9526da99 100644
--- a/drivers/gpu/drm/i915/gt/intel_llc.c
+++ b/drivers/gpu/drm/i915/gt/intel_llc.c
@@ -49,6 +49,7 @@ static unsigned int cpu_max_MHz(void)
static bool get_ia_constants(struct intel_llc *llc,
struct ia_constants *consts)
{
+ struct intel_guc_slpc *slpc = &llc_to_gt(llc)->uc.guc.slpc;
struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
struct intel_rps *rps = &llc_to_gt(llc)->rps;
@@ -65,8 +66,13 @@ static bool get_ia_constants(struct intel_llc *llc,
/* convert DDR frequency from units of 266.6MHz to bandwidth */
consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3);
- consts->min_gpu_freq = rps->min_freq;
- consts->max_gpu_freq = rps->max_freq;
+ if (intel_uc_uses_guc_slpc(&llc_to_gt(llc)->uc)) {
+ consts->min_gpu_freq = slpc->min_freq;
+ consts->max_gpu_freq = slpc->rp0_freq;
+ } else {
+ consts->min_gpu_freq = rps->min_freq;
+ consts->max_gpu_freq = rps->max_freq;
+ }
if (GRAPHICS_VER(i915) >= 9) {
/* Convert GT frequency to 50 HZ units */
consts->min_gpu_freq /= GEN9_FREQ_SCALER;
--
2.37.1
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: some BUG_ON() removals
== Series Details == Series: drm/i915: some BUG_ON() removals URL : https://patchwork.freedesktop.org/series/107785/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH] drm/i915/slpc: Set rps' min and max frequencies even with SLPC.
On Thu, 2022-08-25 at 16:59 -0700, Dixit, Ashutosh wrote:
On Thu, 25 Aug 2022 15:23:15 -0700, Rodrigo Vivi wrote:
We need to inform PCODE of a desired ring frequencies so PCODE update
the memory frequencies to us. rps->min_freq and rps->max_freq are the
frequencies used in that request. However they were unset when SLPC was
enabled and PCODE never updated the memory freq.
Let's at least for now get these freq set up so we can inform PCODE.
Hi Rodrigo,
Great find. Though may I propose a more direct patch below for fixing this:
+
diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c
b/drivers/gpu/drm/i915/gt/intel_llc.c
index 14fe65812e42..a1791b6c7e04 100644
--- a/drivers/gpu/drm/i915/gt/intel_llc.c
+++ b/drivers/gpu/drm/i915/gt/intel_llc.c
@@ -49,6 +49,7 @@ static unsigned int cpu_max_MHz(void)
static bool get_ia_constants(struct intel_llc *llc,
struct ia_constants *consts)
{
+ struct intel_guc_slpc *slpc = &llc_to_gt(llc)->uc.guc.slpc;
struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
struct intel_rps *rps = &llc_to_gt(llc)->rps;
@@ -65,8 +66,14 @@ static bool get_ia_constants(struct intel_llc *llc,
/* convert DDR frequency from units of 266.6MHz to bandwidth */
consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3);
- consts->min_gpu_freq = rps->min_freq;
- consts->max_gpu_freq = rps->max_freq;
+ if (intel_uc_uses_guc_slpc(&llc_to_gt(llc)->uc)) {
+ consts->min_gpu_freq = slpc->min_freq;
+ consts->max_gpu_freq = slpc->rp0_freq;
+ } else {
+ consts->min_gpu_freq = rps->min_freq;
+ consts->max_gpu_freq = rps->max_freq;
+ }
+
if (GRAPHICS_VER(i915) >= 9) {
/* Convert GT frequency to 50 HZ units */
consts->min_gpu_freq /= GEN9_FREQ_SCALER;
+
I have only compile tested the patch but it looks like everything is set up
so the patch above should work. The call stack for slpc initialization is
the following (I am writing here due to the rather opaque uc macros):
intel_gt_resume
-> intel_gt_init_hw
-> intel_uc_init_hw/__uc_init_hw
-> intel_guc_slpc_enable
-> slpc_get_rp_values
As we can see intel_llc_enable() is called after intel_gt_init_hw() in
intel_gt_resume() so SLPC params should be set up.
Yeap, I took that path worried about timing, but you are right this should
be there already and it would be cleaner.
What you have is fine too, I can R-b that if you prefer that.
Your is better and cleaner. Let me try that first here and then I will resend
it.
Thank you!
Thanks.
--
Ashutosh
Cc: Ashutosh Dixit mailto:ashutosh.di...@intel.com>>
Tested-by: Sushma Venkatesh Reddy
mailto:sushma.venkatesh.re...@intel.com>>
Signed-off-by: Rodrigo Vivi
mailto:rodrigo.v...@intel.com>>
---
drivers/gpu/drm/i915/gt/intel_rps.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 8c289a032103..58a82978d5df 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1128,6 +1128,20 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps,
struct intel_rps_freq_caps *c
}
}
+static void rps_basic_init_for_slpc(struct intel_rps *rps)
+{
+ struct intel_rps_freq_caps caps;
+
+ /*
+* Even with SLPC we need to initialize at least a basic min and max
+* frequency so we can inform pcode a desired IA ring frequency in
+* gen6_update_ring_freq
+*/
+ gen6_rps_get_freq_caps(rps, &caps);
+ rps->min_freq = caps.min_freq;
+ rps->max_freq = caps.rp0_freq;
+}
+
static void gen6_rps_init(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
@@ -1970,8 +1984,10 @@ void intel_rps_init(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
- if (rps_uses_slpc(rps))
+ if (rps_uses_slpc(rps)) {
+ rps_basic_init_for_slpc(rps);
return;
+ }
if (IS_CHERRYVIEW(i915))
chv_rps_init(rps);
--
2.37.1
[Intel-gfx] [PATCH v2] drm/i915/guc: Remove log size module parameters
Remove the module parameters for configuring GuC log size.
We should instead rely on tuning the defaults to be usable for
reporting bugs.
v2:
- Use correct 1M unit
Fixes: 8ad0152afb1b ("drm/i915/guc: Make GuC log sizes runtime configurable")
Signed-off-by: Joonas Lahtinen
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: John Harrison
Cc: Alan Previn
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 7 +++
drivers/gpu/drm/i915/i915_params.c | 12
drivers/gpu/drm/i915/i915_params.h | 3 ---
3 files changed, 3 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 3a2243b4ac9f..55d4b8f8e33e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -79,9 +79,9 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
}
};
s32 params[GUC_LOG_SECTIONS_LIMIT] = {
- i915->params.guc_log_size_crash,
- i915->params.guc_log_size_debug,
- i915->params.guc_log_size_capture,
+ GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE / SZ_1M,
+ GUC_LOG_DEFAULT_DEBUG_BUFFER_SIZE / SZ_1M,
+ GUC_LOG_DEFAULT_CAPTURE_BUFFER_SIZE / SZ_1M,
};
int i;
@@ -90,7 +90,6 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
/* If debug size > 1MB then bump default crash size to keep the same
units */
if (log->sizes[GUC_LOG_SECTIONS_DEBUG].bytes >= SZ_1M &&
- (i915->params.guc_log_size_crash == -1) &&
GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE < SZ_1M)
log->sizes[GUC_LOG_SECTIONS_CRASH].bytes = SZ_1M;
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 06ca5b822111..6fc475a5db61 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -171,18 +171,6 @@ i915_param_named(guc_log_level, int, 0400,
"GuC firmware logging level. Requires GuC to be loaded. "
"(-1=auto [default], 0=disable, 1..4=enable with verbosity min..max)");
-i915_param_named(guc_log_size_crash, int, 0400,
- "GuC firmware logging buffer size for crash dumps (in MB)"
- "(-1=auto [default], NB: max = 4, other restrictions apply)");
-
-i915_param_named(guc_log_size_debug, int, 0400,
- "GuC firmware logging buffer size for debug logs (in MB)"
- "(-1=auto [default], NB: max = 16, other restrictions apply)");
-
-i915_param_named(guc_log_size_capture, int, 0400,
- "GuC error capture register dump buffer size (in MB)"
- "(-1=auto [default], NB: max = 4, other restrictions apply)");
-
i915_param_named_unsafe(guc_firmware_path, charp, 0400,
"GuC firmware path to use instead of the default one");
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index f684d1ab8707..2733cb6cfe09 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -61,9 +61,6 @@ struct drm_printer;
param(int, invert_brightness, 0, 0600) \
param(int, enable_guc, -1, 0400) \
param(int, guc_log_level, -1, 0400) \
- param(int, guc_log_size_crash, -1, 0400) \
- param(int, guc_log_size_debug, -1, 0400) \
- param(int, guc_log_size_capture, -1, 0400) \
param(char *, guc_firmware_path, NULL, 0400) \
param(char *, huc_firmware_path, NULL, 0400) \
param(char *, dmc_firmware_path, NULL, 0400) \
--
2.37.2
[Intel-gfx] [RFC v1 0/1] Enabling Smooth Sync Feature.
When async flips are enabled to reduce latency, onscreen tears caused by the immediate transition from an older image to a newer image within a frame can be observable.The Smooth Sync feature uses both blending and dithering to smoothly transition from the old image to the new image over a programmable number of scanlines. Nischal Varide (1): INTEL_DII: drm/i915/display: Enabling Smooth Sync Feature. drivers/gpu/drm/i915/display/intel_display.c | 66 ++- .../drm/i915/display/intel_display_types.h| 3 + .../drm/i915/display/skl_universal_plane.c| 31 +++-- .../drm/i915/display/skl_universal_plane.h| 3 + 4 files changed, 97 insertions(+), 6 deletions(-) -- 2.36.0
[Intel-gfx] [PATCH 4/4] drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate function
We are using almost same code to loop through bpps while calling
drm_dp_atomic_find_vcpi_slots - lets remove this duplication by
introducing a new function intel_dp_mst_find_vcpi_slots_for_bpp
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 85 +++--
1 file changed, 44 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 630450bd22a2..b393c97f3fb8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -44,10 +44,14 @@
#include "intel_hotplug.h"
#include "skl_scaler.h"
-static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
- struct intel_crtc_state *crtc_state,
- struct drm_connector_state
*conn_state,
- struct link_config_limits *limits)
+static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
+ struct intel_crtc_state
*crtc_state,
+ int max_bpp,
+ int min_bpp,
+ struct link_config_limits
*limits,
+ struct drm_connector_state
*conn_state,
+ int step,
+ bool dsc)
{
struct drm_atomic_state *state = crtc_state->uapi.state;
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
@@ -57,26 +61,26 @@ static int intel_dp_mst_compute_link_config(struct
intel_encoder *encoder,
struct drm_i915_private *i915 = to_i915(connector->base.dev);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
- bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
DP_DPCD_QUIRK_CONSTANT_N);
int bpp, slots = -EINVAL;
int ret = 0;
crtc_state->lane_count = limits->max_lane_count;
crtc_state->port_clock = limits->max_rate;
- for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
+ for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
crtc_state->pipe_bpp = bpp;
crtc_state->pbn =
drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
- crtc_state->pipe_bpp,
- false);
+ dsc ? bpp << 4 :
crtc_state->pipe_bpp,
+ dsc);
slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr,
connector->port,
crtc_state->pbn,
-
drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
-
crtc_state->port_clock,
-
crtc_state->lane_count));
+ !dsc ?
drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
+
crtc_state->port_clock,
+
crtc_state->lane_count)
+ : 0);
if (slots == -EDEADLK)
return slots;
if (slots >= 0) {
@@ -94,11 +98,32 @@ static int intel_dp_mst_compute_link_config(struct
intel_encoder *encoder,
if (ret && slots >= 0)
slots = ret;
- if (slots < 0) {
+ if (slots < 0)
drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",
slots);
+
+ return slots;
+}
+
+
+static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ struct drm_connector_state
*conn_state,
+ struct link_config_limits *limits)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
+ struct intel_dp *intel_dp = &intel_mst->primary->dp;
+ bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
DP_DPCD_QUIRK_CONSTANT_N);
+ int slots = -EINVAL;
+
+ slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
limits->max_bpp,
+l
[Intel-gfx] [PATCH 1/4] drm: Add missing DP DSC extended capability definitions.
Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning v3: - Removed function which is not yet used(Jani Nikula) Reviewed-by: Vinod Govindapillai Signed-off-by: Stanislav Lisovskiy --- include/drm/display/drm_dp.h | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 9e3aff7e68bb..0d05e3172f96 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -239,6 +239,9 @@ #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP(1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -277,12 +280,15 @@ #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -344,11 +350,13 @@ # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_10x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED1 -- 2.24.1.485.gad05a3d8e5
[Intel-gfx] [PATCH 3/4] drm/i915: Add DSC support to MST path
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
v2: Removed intel_dp_mst_dsc_compute_config and refactored
intel_dp_dsc_compute_config to support timeslots as a
parameter(Ville Syrjälä)
v3: - Rebased
- Added a debug to see that we at least try reserving
VCPI slots using DSC, because currently its not visible
from the logs, thus making debugging more tricky.
- Moved timeslots to numerator, where it should be.
v4: - Call drm_dp_mst_atomic_check already during link
config computation, because we need to know already
by this moment if uncompressed amount of VCPI slots
needed can fit, otherwise we need to use DSC.
(thanks to Vinod Govindapillai for pointing this out)
v5: - Put pipe_config->bigjoiner_pipes back to original
condition in intel_dp_dsc_compute_config
(don't remember when I lost it)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 73 -
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 157
3 files changed, 205 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index db5f536bde05..7e1176aea2ed 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -116,7 +116,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
}
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -687,11 +686,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
return 6144 * 8;
}
-static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp)
+u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -702,8 +702,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
* for SST -> TimeSlotsPerMTP is 1,
* for MST -> TimeSlotsPerMTP has to be calculated
*/
- bits_per_pixel = (link_clock * lane_count * 8) /
+ bits_per_pixel = (link_clock * lane_count * 8) * timeslots /
intel_dp_mode_to_fec_clock(mode_clock);
+ drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
@@ -752,9 +753,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
return bits_per_pixel << 4;
}
-static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
- int mode_clock, int mode_hdisplay,
- bool bigjoiner)
+u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 min_slice_count, i;
@@ -961,8 +962,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
return MODE_OK;
}
-static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
- int hdisplay, int clock)
+bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
+int hdisplay, int clock)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1049,7 +1050,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
target_clock,
mode->hdisplay,
bigjoiner,
- pipe_bpp) >> 4;
+ pipe_bpp, 1) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1354,7 +1355,7 @@ intel_dp_compute_link_config_wide(struct intel_dp
[Intel-gfx] [PATCH 2/4] drm/i915: Fix intel_dp_mst_compute_link_config
We currently always exit that bpp loop because drm_dp_atomic_find_vcpi_slots
doesn't care if we actually can fit those or not.
I think that wasn't the initial intention here, especially when
we keep trying with lower bpps, we are supposed to keep trying
until we actually find some _working_ configuration, which isn't the
case here.
So added that drm_dp_mst_check here, so that we can make sure
that try all the bpps before we fail.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 14d2a64193b2..c61fd8b39c27 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -59,6 +59,7 @@ static int intel_dp_mst_compute_link_config(struct
intel_encoder *encoder,
&crtc_state->hw.adjusted_mode;
bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
DP_DPCD_QUIRK_CONSTANT_N);
int bpp, slots = -EINVAL;
+ int ret = 0;
crtc_state->lane_count = limits->max_lane_count;
crtc_state->port_clock = limits->max_rate;
@@ -78,10 +79,21 @@ static int intel_dp_mst_compute_link_config(struct
intel_encoder *encoder,
crtc_state->lane_count));
if (slots == -EDEADLK)
return slots;
- if (slots >= 0)
- break;
+ if (slots >= 0) {
+ ret = drm_dp_mst_atomic_check(state);
+ /*
+* If we got slots >= 0 and we can fit those based on
check
+* then we can exit the loop. Otherwise keep trying.
+*/
+ if (!ret)
+ break;
+ }
}
+ /* Despite slots are non-zero, we still failed the atomic check */
+ if (ret && slots >= 0)
+ slots = ret;
+
if (slots < 0) {
drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",
slots);
--
2.24.1.485.gad05a3d8e5
[Intel-gfx] [PATCH 0/4] Add DP MST DSC support to i915
Currently we have only DSC support for DP SST. Stanislav Lisovskiy (4): drm: Add missing DP DSC extended capability definitions. drm/i915: Fix intel_dp_mst_compute_link_config drm/i915: Add DSC support to MST path drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate function drivers/gpu/drm/i915/display/intel_dp.c | 73 +++ drivers/gpu/drm/i915/display/intel_dp.h | 17 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 202 ++-- include/drm/display/drm_dp.h| 10 +- 4 files changed, 244 insertions(+), 58 deletions(-) -- 2.24.1.485.gad05a3d8e5
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Fix spelling mistake "heatbeat" -> "heartbeat"
== Series Details == Series: drm/i915/guc: Fix spelling mistake "heatbeat" -> "heartbeat" URL : https://patchwork.freedesktop.org/series/107784/ State : success == Summary == CI Bug Log - changes from CI_DRM_12030 -> Patchwork_107784v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/index.html Participating hosts (33 -> 38) -- Additional (5): bat-dg2-10 bat-adlp-4 bat-jsl-3 bat-rplp-1 bat-rpls-2 Known issues Here are the changes found in Patchwork_107784v1 that come from known issues: ### IGT changes ### Issues hit * igt@fbdev@read: - bat-adlp-4: NOTRUN -> [SKIP][1] ([i915#2582]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/bat-adlp-4/igt@fb...@read.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-adlp-4: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/bat-adlp-4/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_tiled_pread_basic: - bat-adlp-4: NOTRUN -> [SKIP][3] ([i915#3282]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/bat-adlp-4/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-adlp-4: NOTRUN -> [SKIP][4] ([i915#1155]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/bat-adlp-4/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-adlp-4: NOTRUN -> [SKIP][5] ([i915#6621]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/bat-adlp-4/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[PASS][6] -> [INCOMPLETE][7] ([i915#4785]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12030/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html - bat-dg1-6: [PASS][8] -> [DMESG-FAIL][9] ([i915#4494] / [i915#4957]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12030/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@dp-crc-fast: - bat-adlp-4: NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/bat-adlp-4/igt@kms_chamel...@dp-crc-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size: - fi-bsw-kefka: [PASS][11] -> [FAIL][12] ([i915#6298]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12030/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html * igt@kms_flip@basic-flip-vs-wf_vblank: - bat-adlp-4: NOTRUN -> [SKIP][13] ([i915#3637]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/bat-adlp-4/igt@kms_flip@basic-flip-vs-wf_vblank.html * igt@kms_force_connector_basic@force-load-detect: - bat-adlp-4: NOTRUN -> [SKIP][14] ([i915#4093]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/bat-adlp-4/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_frontbuffer_tracking@basic: - bat-adlp-4: NOTRUN -> [SKIP][15] ([i915#4342]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/bat-adlp-4/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@read-crc-frame-sequence: - bat-adlp-4: NOTRUN -> [SKIP][16] ([i915#3546]) +10 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/bat-adlp-4/igt@kms_pipe_crc_ba...@read-crc-frame-sequence.html * igt@kms_psr@sprite_plane_onoff: - bat-adlp-4: NOTRUN -> [SKIP][17] ([i915#1072]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/bat-adlp-4/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-adlp-4: NOTRUN -> [SKIP][18] ([i915#3555] / [i915#4579]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/bat-adlp-4/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - bat-adlp-4: NOTRUN -> [SKIP][19] ([fdo#109295] / [i915#3546] / [i915#3708]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107784v1/bat-adlp-4/igt@prime_v...@basic-fence-flip.html * igt@prime_vgem@basic-userptr: - bat-adlp-4: NOTRUN ->
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc: Fix spelling mistake "heatbeat" -> "heartbeat"
== Series Details == Series: drm/i915/guc: Fix spelling mistake "heatbeat" -> "heartbeat" URL : https://patchwork.freedesktop.org/series/107784/ State : warning == Summary == Error: dim checkpatch failed 5a0ea1b0f38f drm/i915/guc: Fix spelling mistake "heatbeat" -> "heartbeat" -:22: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Colin Ian King ' != 'Signed-off-by: Colin Ian King ' total: 0 errors, 1 warnings, 0 checks, 8 lines checked
[Intel-gfx] [PATCH 3/5] drm/i915/pch: replace BUG_ON() with drm_WARN_ON()
Avoid BUG_ON(). Replace with drm_WARN_ON(). Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_pch_refclk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c index 9934c8a9e240..38608efd5749 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c @@ -654,7 +654,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) } } - BUG_ON(val != final); + drm_WARN_ON(&dev_priv->drm, val != final); } /* -- 2.34.1
[Intel-gfx] [PATCH 5/5] drm/i915/fence: replace BUG_ON() with BUILD_BUG_ON()
Avoid BUG_ON(). Since __i915_sw_fence_init() is always called via a
wrapper macro, we can replace it with a compile time BUILD_BUG_ON().
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_sw_fence.c | 2 --
drivers/gpu/drm/i915/i915_sw_fence.h | 6 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c
b/drivers/gpu/drm/i915/i915_sw_fence.c
index ae984c66c48a..6fc0d1b89690 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -241,8 +241,6 @@ void __i915_sw_fence_init(struct i915_sw_fence *fence,
const char *name,
struct lock_class_key *key)
{
- BUG_ON(!fn);
-
__init_waitqueue_head(&fence->wait, name, key);
fence->fn = fn;
#ifdef CONFIG_DRM_I915_SW_FENCE_CHECK_DAG
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.h
b/drivers/gpu/drm/i915/i915_sw_fence.h
index a7c603bc1b01..619fc5a22f0c 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.h
+++ b/drivers/gpu/drm/i915/i915_sw_fence.h
@@ -48,11 +48,15 @@ void __i915_sw_fence_init(struct i915_sw_fence *fence,
do { \
static struct lock_class_key __key; \
\
+ BUILD_BUG_ON((fn) == NULL); \
__i915_sw_fence_init((fence), (fn), #fence, &__key);\
} while (0)
#else
#define i915_sw_fence_init(fence, fn) \
- __i915_sw_fence_init((fence), (fn), NULL, NULL)
+do { \
+ BUILD_BUG_ON((fn) == NULL); \
+ __i915_sw_fence_init((fence), (fn), NULL, NULL);\
+} while (0)
#endif
void i915_sw_fence_reinit(struct i915_sw_fence *fence);
--
2.34.1
[Intel-gfx] [PATCH 4/5] drm/i915/perf: replace BUG_ON() with WARN_ON()
Avoid BUG_ON(). Replace with WARN_ON() and early return.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_perf.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index f3c23fe9ad9c..0defbb43ceea 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1376,7 +1376,8 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
{
struct i915_perf *perf = stream->perf;
- BUG_ON(stream != perf->exclusive_stream);
+ if (WARN_ON(stream != perf->exclusive_stream))
+ return;
/*
* Unset exclusive_stream first, it will be checked while disabling
--
2.34.1
[Intel-gfx] [PATCH 1/5] drm/i915/crt: replace BUG_ON() with drm_WARN_ON()
Avoid BUG_ON(). Replace with drm_WARN_ON() and early return. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_crt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 6a3893c8ff22..b92e2d0d14ea 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -643,7 +643,8 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector) struct i2c_adapter *i2c; bool ret = false; - BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); + if (drm_WARN_ON(&dev_priv->drm, crt->base.type != INTEL_OUTPUT_ANALOG)) + return false; i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); edid = intel_crt_get_edid(connector, i2c); -- 2.34.1
[Intel-gfx] [PATCH 2/5] drm/i915/dpll: replace BUG_ON() with drm_WARN_ON()
Avoid BUG_ON(). Actually check the dpll count and bail out loudly with
drm_WARN_ON() from the loop before overflowing
i915->dpll.shared_dplls[].
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 118598c9a809..8dd405553cfa 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4199,6 +4199,10 @@ void intel_shared_dpll_init(struct drm_i915_private
*dev_priv)
dpll_info = dpll_mgr->dpll_info;
for (i = 0; dpll_info[i].name; i++) {
+ if (drm_WARN_ON(&dev_priv->drm,
+ i >= ARRAY_SIZE(dev_priv->dpll.shared_dplls)))
+ break;
+
drm_WARN_ON(&dev_priv->drm, i != dpll_info[i].id);
dev_priv->dpll.shared_dplls[i].info = &dpll_info[i];
}
@@ -4206,8 +4210,6 @@ void intel_shared_dpll_init(struct drm_i915_private
*dev_priv)
dev_priv->dpll.mgr = dpll_mgr;
dev_priv->dpll.num_shared_dpll = i;
mutex_init(&dev_priv->dpll.lock);
-
- BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS);
}
/**
--
2.34.1
[Intel-gfx] [PATCH 0/5] drm/i915: some BUG_ON() removals
Avoid BUG_ON(). Remove some of the low-hanging fruit. Jani Nikula (5): drm/i915/crt: replace BUG_ON() with drm_WARN_ON() drm/i915/dpll: replace BUG_ON() with drm_WARN_ON() drm/i915/pch: replace BUG_ON() with drm_WARN_ON() drm/i915/perf: replace BUG_ON() with WARN_ON() drm/i915/fence: replace BUG_ON() with BUILD_BUG_ON() drivers/gpu/drm/i915/display/intel_crt.c| 3 ++- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 -- drivers/gpu/drm/i915/display/intel_pch_refclk.c | 2 +- drivers/gpu/drm/i915/i915_perf.c| 3 ++- drivers/gpu/drm/i915/i915_sw_fence.c| 2 -- drivers/gpu/drm/i915/i915_sw_fence.h| 6 +- 6 files changed, 14 insertions(+), 8 deletions(-) -- 2.34.1
[Intel-gfx] [PATCH][next] drm/i915/guc: Fix spelling mistake "heatbeat" -> "heartbeat"
There is a spelling mistake in a drm_err message. Fix it.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
index 01f8cd3c3134..d7857cf7c08f 100644
--- a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c
@@ -61,7 +61,7 @@ static int intel_hang_guc(void *arg)
old_beat = engine->props.heartbeat_interval_ms;
ret = intel_engine_set_heartbeat(engine, BEAT_INTERVAL);
if (ret) {
- drm_err(>->i915->drm, "Failed to boost heatbeat interval:
%d\n", ret);
+ drm_err(>->i915->drm, "Failed to boost heartbeat interval:
%d\n", ret);
goto err;
}
--
2.37.1
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc: Remove log size module parameters
== Series Details ==
Series: drm/i915/guc: Remove log size module parameters
URL : https://patchwork.freedesktop.org/series/107780/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12030 -> Patchwork_107780v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_107780v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_107780v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v1/index.html
Participating hosts (33 -> 36)
--
Additional (4): bat-rplp-1 bat-dg2-10 bat-adlp-4 bat-jsl-3
Missing(1): fi-rkl-11600
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_107780v1:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@guc:
- fi-adl-ddr5:[PASS][1] -> [DMESG-WARN][2] +41 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12030/fi-adl-ddr5/igt@i915_selftest@l...@guc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v1/fi-adl-ddr5/igt@i915_selftest@l...@guc.html
* igt@i915_selftest@live@ring_submission:
- bat-adlp-4: NOTRUN -> [DMESG-WARN][3] +41 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v1/bat-adlp-4/igt@i915_selftest@live@ring_submission.html
* igt@i915_selftest@live@slpc:
- fi-cfl-guc: [PASS][4] -> [DMESG-WARN][5] +41 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12030/fi-cfl-guc/igt@i915_selftest@l...@slpc.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v1/fi-cfl-guc/igt@i915_selftest@l...@slpc.html
* igt@i915_selftest@live@vma:
- fi-rkl-guc: [PASS][6] -> [DMESG-WARN][7] +41 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12030/fi-rkl-guc/igt@i915_selftest@l...@vma.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v1/fi-rkl-guc/igt@i915_selftest@l...@vma.html
- bat-dg1-6: [PASS][8] -> [DMESG-WARN][9] +38 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12030/bat-dg1-6/igt@i915_selftest@l...@vma.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v1/bat-dg1-6/igt@i915_selftest@l...@vma.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@load:
- {bat-dg2-10}: NOTRUN -> [DMESG-WARN][10]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v1/bat-dg2-10/igt@i915_module_l...@load.html
* igt@i915_selftest@live@client:
- {bat-dg2-8}:[PASS][11] -> [DMESG-WARN][12] +39 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12030/bat-dg2-8/igt@i915_selftest@l...@client.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v1/bat-dg2-8/igt@i915_selftest@l...@client.html
* igt@i915_selftest@live@coherency:
- {bat-dg2-9}:[PASS][13] -> [DMESG-WARN][14] +40 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12030/bat-dg2-9/igt@i915_selftest@l...@coherency.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v1/bat-dg2-9/igt@i915_selftest@l...@coherency.html
* igt@i915_selftest@live@perf:
- {bat-dg2-11}: [PASS][15] -> [DMESG-WARN][16] +37 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12030/bat-dg2-11/igt@i915_selftest@l...@perf.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v1/bat-dg2-11/igt@i915_selftest@l...@perf.html
* igt@i915_selftest@live@sanitycheck:
- {bat-rplp-1}: NOTRUN -> [DMESG-WARN][17] +41 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v1/bat-rplp-1/igt@i915_selftest@l...@sanitycheck.html
* igt@i915_selftest@live@workarounds:
- {bat-rpls-1}: [PASS][18] -> [DMESG-WARN][19] +27 similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12030/bat-rpls-1/igt@i915_selftest@l...@workarounds.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v1/bat-rpls-1/igt@i915_selftest@l...@workarounds.html
Known issues
Here are the changes found in Patchwork_107780v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@fbdev@read:
- bat-adlp-4: NOTRUN -> [SKIP][20] ([i915#2582]) +4 similar issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107780v1/bat-adlp-4/igt@fb...@read.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adlp-4: NOTRUN -> [SKIP][21] ([i915#4613]) +3 similar
