[Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: freq caps and perf_limit_reasons changes for MTL (rev2)

[Patchwork]

== Series Details ==

Series: i915: freq caps and perf_limit_reasons changes for MTL (rev2)
URL   : https://patchwork.freedesktop.org/series/108091/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: freq caps and perf_limit_reasons changes for MTL (rev2)

[Patchwork]

== Series Details ==

Series: i915: freq caps and perf_limit_reasons changes for MTL (rev2)
URL   : https://patchwork.freedesktop.org/series/108091/
State : warning

== Summary ==

Error: dim checkpatch failed
7c1612061058 drm/i915: Prepare more multi-GT initialization
-:22: WARNING:TYPO_SPELLING: 'forseeable' may be misspelled - perhaps 
'foreseeable'?
#22: 
   forseeable future.  (Jani)
   ^^

-:77: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written 
"gtdef->name"
#77: FILE: drivers/gpu/drm/i915/gt/intel_gt.c:859:
+gtdef->name != NULL;

total: 0 errors, 1 warnings, 1 checks, 154 lines checked
48b942c1a84c drm/i915: Rename and expose common GT early init routine
823b9373f852 drm/i915/uncore: Add GSI offset to uncore
cefd9dfae66a drm/i915/xelpmp: Expose media as another GT
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:87: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#87: 
new file mode 100644

-:123: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written 
"!uncore->regs"
#123: FILE: drivers/gpu/drm/i915/gt/intel_sa_media.c:32:
+   if (drm_WARN_ON(>drm, uncore->regs == NULL))

total: 0 errors, 1 warnings, 1 checks, 130 lines checked
a155005ece00 drm/i915/gt: Fix perf limit reasons bit positions
bd6797adb94f drm/i915/debugfs: Add perf_limit_reasons in debugfs
-:33: CHECK:SPACING: spaces preferred around that '*' (ctx:ExV)
#33: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:664:
+   *val = intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS);
^

total: 0 errors, 0 warnings, 1 checks, 50 lines checked
a6302c2a5d25 drm/i915/mtl: PERF_LIMIT_REASONS changes for MTL
-:52: CHECK:SPACING: spaces preferred around that '*' (ctx:ExV)
#52: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:664:
+   *val = intel_uncore_read(gt->uncore, 
intel_gt_perf_limit_reasons_reg(gt));
^

total: 0 errors, 0 warnings, 1 checks, 66 lines checked
8c2310e08f2a drm/i915/rps: Freq caps for MTL

Re: [Intel-gfx] [PATCH 4/6] drm/i915/debugfs: Add perf_limit_reasons in debugfs

[Dixit, Ashutosh]

On Tue, 06 Sep 2022 07:13:03 -0700, Rodrigo Vivi wrote:
>

Hi Rodrigo,

> On Fri, Sep 02, 2022 at 04:53:00PM -0700, Ashutosh Dixit wrote:
> > From: Tilak Tangudu 
> >
> > Add perf_limit_reasons in debugfs. Unlike the lower 16 perf_limit_reasons
> > status bits, the upper 16 log bits remain set until cleared, thereby
> > ensuring the throttling occurrence is not missed. The clear fop clears
> > the upper 16 log bits, the get fop gets all 32 log and status bits.
> >
> > Signed-off-by: Tilak Tangudu 
> > ---
> >  drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 27 +++
> >  drivers/gpu/drm/i915/i915_reg.h   |  1 +
> >  2 files changed, 28 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c 
> > b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > index 108b9e76c32e..5c95cba5e5df 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > @@ -655,6 +655,32 @@ static bool rps_eval(void *data)
> >
> >  DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost);
> >
> > +static int perf_limit_reasons_get(void *data, u64 *val)
> > +{
> > +   struct intel_gt *gt = data;
> > +   intel_wakeref_t wakeref;
> > +
> > +   with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> > +   *val = intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS);
> > +
> > +   return 0;
> > +}
> > +
> > +static int perf_limit_reasons_clear(void *data, u64 val)
> > +{
> > +   struct intel_gt *gt = data;
> > +   intel_wakeref_t wakeref;
> > +
> > +   /* Clear the upper 16 log bits, the lower 16 status bits are read-only 
> > */
> > +   with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> > +   intel_uncore_rmw(gt->uncore, GT0_PERF_LIMIT_REASONS,
> > +GT0_PERF_LIMIT_REASONS_LOG_MASK, 0);
> > +
> > +   return 0;
> > +}
> > +DEFINE_SIMPLE_ATTRIBUTE(perf_limit_reasons_fops, perf_limit_reasons_get,
> > +   perf_limit_reasons_clear, "%llu\n");
> > +
> >  void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root)
> >  {
> > static const struct intel_gt_debugfs_file files[] = {
> > @@ -664,6 +690,7 @@ void intel_gt_pm_debugfs_register(struct intel_gt *gt, 
> > struct dentry *root)
> > { "forcewake_user", _user_fops, NULL},
> > { "llc", _fops, llc_eval },
> > { "rps_boost", _boost_fops, rps_eval },
> > +   { "perf_limit_reasons", _limit_reasons_fops, NULL },
> > };
> >
> > intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 5e6239864c35..10126995e1f6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1802,6 +1802,7 @@
> >  #define   POWER_LIMIT_4_MASK   REG_BIT(9)
> >  #define   POWER_LIMIT_1_MASK   REG_BIT(11)
> >  #define   POWER_LIMIT_2_MASK   REG_BIT(12)
> > +#define   GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
>
> Is this valid for all platforms?

Yes, looks like it.

> What does the bits are really telling us?

The v1 commit message above hinted at what was happening, I've clarified
the commit message in v2 as follows:

Add perf_limit_reasons in debugfs. The upper 16 perf_limit_reasons RW "log"
bits are identical to the lower 16 RO "status" bits except that the "log"
bits remain set until cleared, thereby ensuring the throttling occurrence
is not missed. The clear fop clears the upper 16 "log" bits, the get fop
gets all 32 "log" and "status" bits.

I've also expanded the comment in perf_limit_reasons_clear() to explain this.

> Could we expand the reasons? The previous bits we know exactly
> what kind of limits we are dealing of, but with this combined
> one without any explanation I'm afraid this will bring more
> confusion than help. We will get bugged by many folks trying
> to debug this out there when bit 13, for instance, is set.
> "What does bit 13 mean?" will be a recurrent question with
> only a tribal knowledge kind of answer.

I think the new commit message above and comment has the answer to this
now. Also, won't there be a public copy of the Bspec where someone can look
up the bit definitions?

Also, are these "log" bits useful enough to expose them in sysfs like we
have the lower "status" bits exposed today but that is probably the
question for a different patch.

Thanks.
--
Ashutosh

Re: [Intel-gfx] [PATCH 5/6] drm/i915/mtl: PERF_LIMIT_REASONS changes for MTL

[Dixit, Ashutosh]

On Mon, 05 Sep 2022 02:30:45 -0700, Jani Nikula wrote:
>
> On Fri, 02 Sep 2022, Ashutosh Dixit  wrote:
> > PERF_LIMIT_REASONS register for MTL media gt is different now.
> >
> > Cc: Badal Nilawar 
> > Signed-off-by: Ashutosh Dixit 
> > ---
> >  drivers/gpu/drm/i915/gt/intel_gt.h| 8 
> >  drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 4 ++--
> >  drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c   | 6 +++---
> >  drivers/gpu/drm/i915/i915_reg.h   | 1 +
> >  4 files changed, 14 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h 
> > b/drivers/gpu/drm/i915/gt/intel_gt.h
> > index c9a359f35d0f..7286d47113ee 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> > @@ -9,6 +9,7 @@
> >  #include "intel_engine_types.h"
> >  #include "intel_gt_types.h"
> >  #include "intel_reset.h"
> > +#include "i915_reg.h"
> >
> >  struct drm_i915_private;
> >  struct drm_printer;
> > @@ -86,6 +87,13 @@ static inline bool intel_gt_is_wedged(const struct 
> > intel_gt *gt)
> > return unlikely(test_bit(I915_WEDGED, >reset.flags));
> >  }
> >
> > +static inline
> > +i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt)
> > +{
> > +   return gt->type == GT_MEDIA ?
> > +   MTL_MEDIA_PERF_LIMIT_REASONS : GT0_PERF_LIMIT_REASONS;
> > +}
>
> Nowadays, I pretty much think of everything from the standpoint of
> setting the example for future changes. Is this what we want people to
> copy? Because that's what we do, look for examples for what we want to
> achieve, and emulate.
>
> Do we want this to be duplicated for other registers? Choose register
> offset based on platform/engine/fusing/whatever parameter? Is this a
> register definition that should be in a _regs.h file?
>
> I don't know.

MTL_MEDIA_PERF_LIMIT_REASONS is an actual register so I'd think it needs to
be in a _regs.h file. And here we need to choose the register offset at
runtime based on the gt. So I don't see any way round what's happening
above unless you have other suggestions.

> I've also grown to dislike static inlines a lot, and this one's the
> worst because it actually can't be static inline because its passed as a
> function pointer.

Based on your feedback I've eliminated the static inline and moved the
function definition to a .c in v2 (though gcc allows taking addresses of
static inline's in .h files).

Thanks.
--
Ashutosh

>
>
> BR,
> Jani.
>
>
>
> > +
> >  int intel_gt_probe_all(struct drm_i915_private *i915);
> >  int intel_gt_tiles_init(struct drm_i915_private *i915);
> >  void intel_gt_release_all(struct drm_i915_private *i915);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c 
> > b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > index 5c95cba5e5df..fe0091f953c1 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> > @@ -661,7 +661,7 @@ static int perf_limit_reasons_get(void *data, u64 *val)
> > intel_wakeref_t wakeref;
> >
> > with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> > -   *val = intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS);
> > +   *val = intel_uncore_read(gt->uncore, 
> > intel_gt_perf_limit_reasons_reg(gt));
> >
> > return 0;
> >  }
> > @@ -673,7 +673,7 @@ static int perf_limit_reasons_clear(void *data, u64 val)
> >
> > /* Clear the upper 16 log bits, the lower 16 status bits are read-only 
> > */
> > with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> > -   intel_uncore_rmw(gt->uncore, GT0_PERF_LIMIT_REASONS,
> > +   intel_uncore_rmw(gt->uncore, 
> > intel_gt_perf_limit_reasons_reg(gt),
> >  GT0_PERF_LIMIT_REASONS_LOG_MASK, 0);
> >
> > return 0;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c 
> > b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> > index e066cc33d9f2..54deae45d81f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> > @@ -510,7 +510,7 @@ struct intel_gt_bool_throttle_attr {
> > struct attribute attr;
> > ssize_t (*show)(struct device *dev, struct device_attribute *attr,
> > char *buf);
> > -   i915_reg_t reg32;
> > +   i915_reg_t (*reg32)(struct intel_gt *gt);
> > u32 mask;
> >  };
> >
> > @@ -521,7 +521,7 @@ static ssize_t throttle_reason_bool_show(struct device 
> > *dev,
> > struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
> > struct intel_gt_bool_throttle_attr *t_attr =
> > (struct intel_gt_bool_throttle_attr *) attr;
> > -   bool val = rps_read_mask_mmio(>rps, t_attr->reg32, t_attr->mask);
> > +   bool val = rps_read_mask_mmio(>rps, t_attr->reg32(gt), 
> > t_attr->mask);
> >
> > return sysfs_emit(buff, "%u\n", val);
> >  }
> > @@ -530,7 +530,7 @@ static ssize_t throttle_reason_bool_show(struct device 
> > *dev,
> >  struct intel_gt_bool_throttle_attr 

Re: [Intel-gfx] [PATCH 6/6] drm/i915/rps: Freq caps for MTL

[Dixit, Ashutosh]

On Mon, 05 Sep 2022 02:40:08 -0700, Jani Nikula wrote:
> On Fri, 02 Sep 2022, Ashutosh Dixit  wrote:
> > For MTL, when reading from HW, RP0, RP1 (actuall RPe) and RPn freq use an
> > entirely different set of registers with different fields, bitwidths and
> > units.
> >
> > Cc: Badal Nilawar 
> > Signed-off-by: Ashutosh Dixit 
> > ---
> >  drivers/gpu/drm/i915/gt/intel_rps.c | 20 
> >  drivers/gpu/drm/i915/i915_reg.h |  9 +
> >  2 files changed, 29 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
> > b/drivers/gpu/drm/i915/gt/intel_rps.c
> > index 579ae9ac089c..e7ab172698e3 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> > @@ -1085,6 +1085,23 @@ static u32 intel_rps_read_state_cap(struct intel_rps 
> > *rps)
> > return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
> >  }
> >
> > +static void
> > +mtl_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps)
> > +{
> > +   struct intel_uncore *uncore = rps_to_uncore(rps);
> > +   u32 rp_state_cap = rps_to_gt(rps)->type == GT_MEDIA ?
> > +   intel_uncore_read(uncore, MTL_MEDIAP_STATE_CAP) 
> > :
> > +   intel_uncore_read(uncore, MTL_RP_STATE_CAP);
> > +   u32 rpe = rps_to_gt(rps)->type == GT_MEDIA ?
> > +   intel_uncore_read(uncore, MTL_MPE_FREQUENCY) :
> > +   intel_uncore_read(uncore, MTL_GT_RPE_FREQUENCY);
> > +
> > +   /* MTL values are in units of 16.67 MHz */
> > +   caps->rp0_freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, rp_state_cap);
> > +   caps->min_freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, rp_state_cap);
> > +   caps->rp1_freq = REG_FIELD_GET(MTL_RPE_MASK, rpe);
> > +}
> > +
> >  /**
> >   * gen6_rps_get_freq_caps - Get freq caps exposed by HW
> >   * @rps: the intel_rps structure
> > @@ -1098,6 +1115,9 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, 
> > struct intel_rps_freq_caps *c
> > struct drm_i915_private *i915 = rps_to_i915(rps);
> > u32 rp_state_cap;
> >
> > +   if (IS_METEORLAKE(i915))
> > +   return mtl_get_freq_caps(rps, caps);
> > +
>
> Please make gen6_rps_get_freq_caps() static, and add
>
> intel_rps_get_freq_caps()
> {
>   if (IS_METEORLAKE(i915))
>   return mtl_get_freq_caps(rps, caps);
>   else
>   return gen6_rps_get_freq_caps(rps, caps);
> }
>
> Or something.

A general name like intel_rps_get_freq_caps name does not sit well with the
current code. intel_rps_get_freq_caps was actually used in earlier versions
of the patch:

https://patchwork.freedesktop.org/patch/479179/?series=101606=3

but was later changed to gen6_rps_get_freq_caps based on review
comments. Afaiu in i915 a name such as gen6_rps_get_freq_caps implies "Gen6
and later" and the gen6_rps_get_freq_caps name has actually proved quite
useful in reminding people that there are earlier/other generations not
covered by the function. See intel_rps_init.

Further the call stack is:

intel_rps_init -> gen6_rps_init -> gen6_rps_get_freq_caps

So it would look odd if we called intel_rps_get_freq_caps from
gen6_rps_init.

Therefore what I have done in v2 is:

s/gen6_rps_get_freq_caps/__gen6_rps_get_freq_caps/

and then

gen6_rps_get_freq_caps()
{
if (IS_METEORLAKE(i915))
return mtl_get_freq_caps(rps, caps);
else
return __gen6_rps_get_freq_caps(rps, caps);
}

Thanks.
--
Ashutosh

> > rp_state_cap = intel_rps_read_state_cap(rps);
> >
> > /* static values from HW: RP0 > RP1 > RPn (min_freq) */
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 06d555321651..d78f9675aa57 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1792,6 +1792,15 @@
> >  #define XEHPSDV_RP_STATE_CAP   _MMIO(0x250014)
> >  #define PVC_RP_STATE_CAP   _MMIO(0x281014)
> >
> > +#define MTL_RP_STATE_CAP   _MMIO(0x138000)
> > +#define MTL_MEDIAP_STATE_CAP   _MMIO(0x138020)
> > +#define   MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
> > +#define   MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
> > +
> > +#define MTL_GT_RPE_FREQUENCY   _MMIO(0x13800c)
> > +#define MTL_MPE_FREQUENCY  _MMIO(0x13802c)
> > +#define   MTL_RPE_MASK REG_GENMASK(8, 0)
> > +
> >  #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
> >  #define   GT0_PERF_LIMIT_REASONS_MASK  0xde3
> >  #define   PROCHOT_MASK REG_BIT(1)
>
> --
> Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 8/8] drm/i915/rps: Freq caps for MTL

[Ashutosh Dixit]

For MTL, when reading from HW, RP0, RP1 (actuall RPe) and RPn freq use an
entirely different set of registers with different fields, bitwidths and
units.

v2: Move MTL check into a separate function (Jani)

Cc: Jani Nikula 
Cc: Badal Nilawar 
Signed-off-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_rps.c | 46 +++--
 drivers/gpu/drm/i915/i915_reg.h |  9 ++
 2 files changed, 46 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 6fadde4ee7bf..234c69e2ca03 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1085,15 +1085,25 @@ static u32 intel_rps_read_state_cap(struct intel_rps 
*rps)
return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
 }
 
-/**
- * gen6_rps_get_freq_caps - Get freq caps exposed by HW
- * @rps: the intel_rps structure
- * @caps: returned freq caps
- *
- * Returned "caps" frequencies should be converted to MHz using
- * intel_gpu_freq()
- */
-void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps 
*caps)
+static void
+mtl_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps)
+{
+   struct intel_uncore *uncore = rps_to_uncore(rps);
+   u32 rp_state_cap = rps_to_gt(rps)->type == GT_MEDIA ?
+   intel_uncore_read(uncore, MTL_MEDIAP_STATE_CAP) 
:
+   intel_uncore_read(uncore, MTL_RP_STATE_CAP);
+   u32 rpe = rps_to_gt(rps)->type == GT_MEDIA ?
+   intel_uncore_read(uncore, MTL_MPE_FREQUENCY) :
+   intel_uncore_read(uncore, MTL_GT_RPE_FREQUENCY);
+
+   /* MTL values are in units of 16.67 MHz */
+   caps->rp0_freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, rp_state_cap);
+   caps->min_freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, rp_state_cap);
+   caps->rp1_freq = REG_FIELD_GET(MTL_RPE_MASK, rpe);
+}
+
+static void
+__gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps 
*caps)
 {
struct drm_i915_private *i915 = rps_to_i915(rps);
u32 rp_state_cap;
@@ -1128,6 +1138,24 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, 
struct intel_rps_freq_caps *c
}
 }
 
+/**
+ * gen6_rps_get_freq_caps - Get freq caps exposed by HW
+ * @rps: the intel_rps structure
+ * @caps: returned freq caps
+ *
+ * Returned "caps" frequencies should be converted to MHz using
+ * intel_gpu_freq()
+ */
+void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps 
*caps)
+{
+   struct drm_i915_private *i915 = rps_to_i915(rps);
+
+   if (IS_METEORLAKE(i915))
+   return mtl_get_freq_caps(rps, caps);
+   else
+   return __gen6_rps_get_freq_caps(rps, caps);
+}
+
 static void gen6_rps_init(struct intel_rps *rps)
 {
struct drm_i915_private *i915 = rps_to_i915(rps);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10a89d869b00..f008367a3433 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1792,6 +1792,15 @@
 #define XEHPSDV_RP_STATE_CAP   _MMIO(0x250014)
 #define PVC_RP_STATE_CAP   _MMIO(0x281014)
 
+#define MTL_RP_STATE_CAP   _MMIO(0x138000)
+#define MTL_MEDIAP_STATE_CAP   _MMIO(0x138020)
+#define   MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
+#define   MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
+
+#define MTL_GT_RPE_FREQUENCY   _MMIO(0x13800c)
+#define MTL_MPE_FREQUENCY  _MMIO(0x13802c)
+#define   MTL_RPE_MASK REG_GENMASK(8, 0)
+
 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
 #define   GT0_PERF_LIMIT_REASONS_MASK  0xde3
 #define   PROCHOT_MASK REG_BIT(0)
-- 
2.34.1

[Intel-gfx] [PATCH 7/8] drm/i915/mtl: PERF_LIMIT_REASONS changes for MTL

[Ashutosh Dixit]

PERF_LIMIT_REASONS register for MTL media gt is different now.

v2: Avoid static inline for intel_gt_perf_limit_reasons_reg() (Jani)

Cc: Jani Nikula 
Cc: Badal Nilawar 
Signed-off-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_gt.c| 6 ++
 drivers/gpu/drm/i915/gt/intel_gt.h| 1 +
 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 4 ++--
 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c   | 6 +++---
 drivers/gpu/drm/i915/i915_reg.h   | 1 +
 5 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 070068524a19..602d711d3c9e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -224,6 +224,12 @@ static void gen6_clear_engine_error_register(struct 
intel_engine_cs *engine)
GEN6_RING_FAULT_REG_POSTING_READ(engine);
 }
 
+i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt)
+{
+   return gt->type == GT_MEDIA ?
+   MTL_MEDIA_PERF_LIMIT_REASONS : GT0_PERF_LIMIT_REASONS;
+}
+
 void
 intel_gt_clear_error_registers(struct intel_gt *gt,
   intel_engine_mask_t engine_mask)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h 
b/drivers/gpu/drm/i915/gt/intel_gt.h
index c9a359f35d0f..b6509d3e8804 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -60,6 +60,7 @@ void intel_gt_driver_late_release_all(struct drm_i915_private 
*i915);
 int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
 
 void intel_gt_check_and_clear_faults(struct intel_gt *gt);
+i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt);
 void intel_gt_clear_error_registers(struct intel_gt *gt,
intel_engine_mask_t engine_mask);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c 
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index a009cf69103a..68310881a793 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -661,7 +661,7 @@ static int perf_limit_reasons_get(void *data, u64 *val)
intel_wakeref_t wakeref;
 
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
-   *val = intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS);
+   *val = intel_uncore_read(gt->uncore, 
intel_gt_perf_limit_reasons_reg(gt));
 
return 0;
 }
@@ -677,7 +677,7 @@ static int perf_limit_reasons_clear(void *data, u64 val)
 * "status" bits except that the "log" bits remain set until cleared.
 */
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
-   intel_uncore_rmw(gt->uncore, GT0_PERF_LIMIT_REASONS,
+   intel_uncore_rmw(gt->uncore, 
intel_gt_perf_limit_reasons_reg(gt),
 GT0_PERF_LIMIT_REASONS_LOG_MASK, 0);
 
return 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c 
b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index e066cc33d9f2..54deae45d81f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -510,7 +510,7 @@ struct intel_gt_bool_throttle_attr {
struct attribute attr;
ssize_t (*show)(struct device *dev, struct device_attribute *attr,
char *buf);
-   i915_reg_t reg32;
+   i915_reg_t (*reg32)(struct intel_gt *gt);
u32 mask;
 };
 
@@ -521,7 +521,7 @@ static ssize_t throttle_reason_bool_show(struct device *dev,
struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
struct intel_gt_bool_throttle_attr *t_attr =
(struct intel_gt_bool_throttle_attr *) attr;
-   bool val = rps_read_mask_mmio(>rps, t_attr->reg32, t_attr->mask);
+   bool val = rps_read_mask_mmio(>rps, t_attr->reg32(gt), 
t_attr->mask);
 
return sysfs_emit(buff, "%u\n", val);
 }
@@ -530,7 +530,7 @@ static ssize_t throttle_reason_bool_show(struct device *dev,
 struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
.attr = { .name = __stringify(sysfs_func__), .mode = 0444 }, \
.show = throttle_reason_bool_show, \
-   .reg32 = GT0_PERF_LIMIT_REASONS, \
+   .reg32 = intel_gt_perf_limit_reasons_reg, \
.mask = mask__, \
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9492f8f43b25..10a89d869b00 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1803,6 +1803,7 @@
 #define   POWER_LIMIT_1_MASK   REG_BIT(10)
 #define   POWER_LIMIT_2_MASK   REG_BIT(11)
 #define   GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
+#define MTL_MEDIA_PERF_LIMIT_REASONS   _MMIO(0x138030)
 
 #define CHV_CLK_CTL1   _MMIO(0x101100)
 #define VLV_CLK_CTL2   _MMIO(0x101104)
-- 
2.34.1

[Intel-gfx] [PATCH 6/8] drm/i915/debugfs: Add perf_limit_reasons in debugfs

[Ashutosh Dixit]

From: Tilak Tangudu 

Add perf_limit_reasons in debugfs. The upper 16 perf_limit_reasons RW "log"
bits are identical to the lower 16 RO "status" bits except that the "log"
bits remain set until cleared, thereby ensuring the throttling occurrence
is not missed. The clear fop clears the upper 16 "log" bits, the get fop
gets all 32 "log" and "status" bits.

v2: Expand commit message and clarify "log" and "status" bits in
comment (Rodrigo)

Cc: Rodrigo Vivi 
Signed-off-by: Ashutosh Dixit 
Signed-off-by: Tilak Tangudu 
---
 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 31 +++
 drivers/gpu/drm/i915/i915_reg.h   |  1 +
 2 files changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c 
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 108b9e76c32e..a009cf69103a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -655,6 +655,36 @@ static bool rps_eval(void *data)
 
 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost);
 
+static int perf_limit_reasons_get(void *data, u64 *val)
+{
+   struct intel_gt *gt = data;
+   intel_wakeref_t wakeref;
+
+   with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+   *val = intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS);
+
+   return 0;
+}
+
+static int perf_limit_reasons_clear(void *data, u64 val)
+{
+   struct intel_gt *gt = data;
+   intel_wakeref_t wakeref;
+
+   /*
+* Clear the upper 16 "log" bits, the lower 16 "status" bits are
+* read-only. The upper 16 "log" bits are identical to the lower 16
+* "status" bits except that the "log" bits remain set until cleared.
+*/
+   with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+   intel_uncore_rmw(gt->uncore, GT0_PERF_LIMIT_REASONS,
+GT0_PERF_LIMIT_REASONS_LOG_MASK, 0);
+
+   return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(perf_limit_reasons_fops, perf_limit_reasons_get,
+   perf_limit_reasons_clear, "%llu\n");
+
 void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root)
 {
static const struct intel_gt_debugfs_file files[] = {
@@ -664,6 +694,7 @@ void intel_gt_pm_debugfs_register(struct intel_gt *gt, 
struct dentry *root)
{ "forcewake_user", _user_fops, NULL},
{ "llc", _fops, llc_eval },
{ "rps_boost", _boost_fops, rps_eval },
+   { "perf_limit_reasons", _limit_reasons_fops, NULL },
};
 
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24009786f88b..9492f8f43b25 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1802,6 +1802,7 @@
 #define   POWER_LIMIT_4_MASK   REG_BIT(8)
 #define   POWER_LIMIT_1_MASK   REG_BIT(10)
 #define   POWER_LIMIT_2_MASK   REG_BIT(11)
+#define   GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
 
 #define CHV_CLK_CTL1   _MMIO(0x101100)
 #define VLV_CLK_CTL2   _MMIO(0x101104)
-- 
2.34.1

[Intel-gfx] [PATCH 5/8] drm/i915/gt: Fix perf limit reasons bit positions

[Ashutosh Dixit]

Perf limit reasons bit positions were off by one.

Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces")
Cc: sta...@vger.kernel.org # v5.18+
Cc: Sujaritha Sundaresan 
Cc: Andi Shyti 
Signed-off-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_reg.h | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c413eec3373f..24009786f88b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1794,14 +1794,14 @@
 
 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
 #define   GT0_PERF_LIMIT_REASONS_MASK  0xde3
-#define   PROCHOT_MASK REG_BIT(1)
-#define   THERMAL_LIMIT_MASK   REG_BIT(2)
-#define   RATL_MASKREG_BIT(6)
-#define   VR_THERMALERT_MASK   REG_BIT(7)
-#define   VR_TDC_MASK  REG_BIT(8)
-#define   POWER_LIMIT_4_MASK   REG_BIT(9)
-#define   POWER_LIMIT_1_MASK   REG_BIT(11)
-#define   POWER_LIMIT_2_MASK   REG_BIT(12)
+#define   PROCHOT_MASK REG_BIT(0)
+#define   THERMAL_LIMIT_MASK   REG_BIT(1)
+#define   RATL_MASKREG_BIT(5)
+#define   VR_THERMALERT_MASK   REG_BIT(6)
+#define   VR_TDC_MASK  REG_BIT(7)
+#define   POWER_LIMIT_4_MASK   REG_BIT(8)
+#define   POWER_LIMIT_1_MASK   REG_BIT(10)
+#define   POWER_LIMIT_2_MASK   REG_BIT(11)
 
 #define CHV_CLK_CTL1   _MMIO(0x101100)
 #define VLV_CLK_CTL2   _MMIO(0x101104)
-- 
2.34.1

[Intel-gfx] [PATCH 3/8] drm/i915/uncore: Add GSI offset to uncore

[Ashutosh Dixit]

From: Matt Roper 

DO NOT REVIEW, FOR COMPILING ONLY

GT non-engine registers (referred to as "GSI" registers by the spec)
have the same relative offsets on standalone media as they do on the
primary GT, just with an additional "GSI offset" added to their MMIO
address.  If we store this GSI offset in the standalone media's
intel_uncore structure, it can be automatically applied to all GSI reg
reads/writes that happen on that GT, allowing us to re-use our existing
GT code with minimal changes.

Forcewake and shadowed register tables for the media GT (which will be
added in a future patch) are listed as final addresses that already
include the GSI offset, so we also need to add the GSI offset before
doing lookups of registers in one of those tables.

Cc: Daniele Ceraolo Spurio 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_gt_types.h |  1 +
 drivers/gpu/drm/i915/intel_uncore.c  | 10 --
 drivers/gpu/drm/i915/intel_uncore.h  | 22 --
 3 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 0e139f7d75ed..82dc28643572 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -274,6 +274,7 @@ struct intel_gt_definition {
enum intel_gt_type type;
char *name;
u32 mapping_base;
+   u32 gsi_offset;
intel_engine_mask_t engine_mask;
 };
 
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 9b81b2543ce2..5b258b57ca02 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -918,6 +918,9 @@ find_fw_domain(struct intel_uncore *uncore, u32 offset)
 {
const struct intel_forcewake_range *entry;
 
+   if (IS_GSI_REG(offset))
+   offset += uncore->gsi_offset;
+
entry = BSEARCH(offset,
uncore->fw_domains_table,
uncore->fw_domains_table_entries,
@@ -1133,6 +1136,9 @@ static bool is_shadowed(struct intel_uncore *uncore, u32 
offset)
if (drm_WARN_ON(>i915->drm, !uncore->shadowed_reg_table))
return false;
 
+   if (IS_GSI_REG(offset))
+   offset += uncore->gsi_offset;
+
return BSEARCH(offset,
   uncore->shadowed_reg_table,
   uncore->shadowed_reg_table_entries,
@@ -1985,8 +1991,8 @@ static int __fw_domain_init(struct intel_uncore *uncore,
 
d->uncore = uncore;
d->wake_count = 0;
-   d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
-   d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
+   d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set) + 
uncore->gsi_offset;
+   d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack) + 
uncore->gsi_offset;
 
d->id = domain_id;
 
diff --git a/drivers/gpu/drm/i915/intel_uncore.h 
b/drivers/gpu/drm/i915/intel_uncore.h
index b1fa912a65e7..23fb8bcd2792 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -135,6 +135,16 @@ struct intel_uncore {
 
spinlock_t lock; /** lock is also taken in irq contexts. */
 
+   /*
+* Do we need to apply an additional offset to reach the beginning
+* of the basic non-engine GT registers (referred to as "GSI" on
+* newer platforms, or "GT block" on older platforms)?  If so, we'll
+* track that here and apply it transparently to registers in the
+* appropriate range to maintain compatibility with our existing
+* register definitions and GT code.
+*/
+   u32 gsi_offset;
+
unsigned int flags;
 #define UNCORE_HAS_FORCEWAKE   BIT(0)
 #define UNCORE_HAS_FPGA_DBG_UNCLAIMED  BIT(1)
@@ -294,19 +304,27 @@ intel_wait_for_register_fw(struct intel_uncore *uncore,
2, timeout_ms, NULL);
 }
 
+#define IS_GSI_REG(reg) ((reg) < 0x4)
+
 /* register access functions */
 #define __raw_read(x__, s__) \
 static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, 
\
i915_reg_t reg) \
 { \
-   return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
+   u32 offset = i915_mmio_reg_offset(reg); \
+   if (IS_GSI_REG(offset)) \
+   offset += uncore->gsi_offset; \
+   return read##s__(uncore->regs + offset); \
 }
 
 #define __raw_write(x__, s__) \
 static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
   i915_reg_t reg, u##x__ val) \
 { \
-   write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
+   u32 offset = i915_mmio_reg_offset(reg); \
+   if (IS_GSI_REG(offset)) \
+   offset += uncore->gsi_offset; \
+   write##s__(val, uncore->regs + offset); \
 }
 __raw_read(8, b)
 __raw_read(16, w)
-- 

[Intel-gfx] [PATCH 2/8] drm/i915: Rename and expose common GT early init routine

[Ashutosh Dixit]

From: Matt Roper 

DO NOT REVIEW, FOR COMPILING ONLY

The common early GT init is needed for initialization of all GT types
(root/primary, remote tile, standalone media).  Since standalone media
(coming in a future patch) will be implemented in a separate file,
rename and expose the function for use.

Signed-off-by: Matt Roper 
Reviewed-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/gt/intel_gt.c | 6 +++---
 drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 530637e102c0..4b408c9d0d81 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -35,7 +35,7 @@
 #include "intel_uncore.h"
 #include "shmem_utils.h"
 
-static void __intel_gt_init_early(struct intel_gt *gt)
+void intel_gt_common_init_early(struct intel_gt *gt)
 {
spin_lock_init(>irq_lock);
 
@@ -65,7 +65,7 @@ void intel_root_gt_init_early(struct drm_i915_private *i915)
gt->i915 = i915;
gt->uncore = >uncore;
 
-   __intel_gt_init_early(gt);
+   intel_gt_common_init_early(gt);
 }
 
 static int intel_gt_probe_lmem(struct intel_gt *gt)
@@ -797,7 +797,7 @@ static int intel_gt_tile_setup(struct intel_gt *gt, 
phys_addr_t phys_addr)
gt->uncore = uncore;
gt->uncore->debug = mmio_debug;
 
-   __intel_gt_init_early(gt);
+   intel_gt_common_init_early(gt);
}
 
intel_uncore_init_early(gt->uncore, gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h 
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 4d8779529cc2..c9a359f35d0f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -44,6 +44,7 @@ static inline struct intel_gt *gsc_to_gt(struct intel_gsc 
*gsc)
return container_of(gsc, struct intel_gt, gsc);
 }
 
+void intel_gt_common_init_early(struct intel_gt *gt);
 void intel_root_gt_init_early(struct drm_i915_private *i915);
 int intel_gt_assign_ggtt(struct intel_gt *gt);
 int intel_gt_init_mmio(struct intel_gt *gt);
-- 
2.34.1

[Intel-gfx] [PATCH 4/8] drm/i915/xelpmp: Expose media as another GT

[Ashutosh Dixit]

From: Matt Roper 

DO NOT REVIEW, FOR COMPILING ONLY

Xe_LPM+ platforms have "standalone media."  I.e., the media unit is
designed as an additional GT with its own engine list, GuC, forcewake,
etc.  Let's allow platforms to include media GTs in their device info.

v2:
 - Simplify GSI register handling and split it out to a separate patch
   for ease of review.  (Daniele)

Cc: Aravind Iddamsetty 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Matt Roper 
Reviewed-by: Aravind Iddamsetty 
---
 drivers/gpu/drm/i915/Makefile|  1 +
 drivers/gpu/drm/i915/gt/intel_gt.c   |  6 
 drivers/gpu/drm/i915/gt/intel_gt_regs.h  |  8 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h |  1 +
 drivers/gpu/drm/i915/gt/intel_sa_media.c | 39 
 drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 +
 drivers/gpu/drm/i915/i915_pci.c  | 14 +
 7 files changed, 84 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 522ef9b4aff3..e83e4cd46968 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -123,6 +123,7 @@ gt-y += \
gt/intel_ring.o \
gt/intel_ring_submission.o \
gt/intel_rps.o \
+   gt/intel_sa_media.o \
gt/intel_sseu.o \
gt/intel_sseu_debugfs.o \
gt/intel_timeline.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 4b408c9d0d81..070068524a19 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -31,6 +31,7 @@
 #include "intel_rc6.h"
 #include "intel_renderstate.h"
 #include "intel_rps.h"
+#include "intel_sa_media.h"
 #include "intel_gt_sysfs.h"
 #include "intel_uncore.h"
 #include "shmem_utils.h"
@@ -884,6 +885,11 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
ret = intel_gt_tile_setup(gt, phys_addr + 
gtdef->mapping_base);
break;
 
+   case GT_MEDIA:
+   ret = intel_sa_mediagt_setup(gt, phys_addr + 
gtdef->mapping_base,
+gtdef->gsi_offset);
+   break;
+
case GT_PRIMARY:
/* Primary GT should not appear in extra GT list */
default:
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index d414785003cc..fb2c56777480 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1578,4 +1578,12 @@
 
 #define GEN12_SFC_DONE(n)  _MMIO(0x1cc000 + (n) * 0x1000)
 
+/*
+ * Standalone Media's non-engine GT registers are located at their regular GT
+ * offsets plus 0x38.  This extra offset is stored inside the intel_uncore
+ * structure so that the existing code can be used for both GTs without
+ * modification.
+ */
+#define MTL_MEDIA_GSI_BASE 0x38
+
 #endif /* __INTEL_GT_REGS__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 82dc28643572..726695936a79 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -84,6 +84,7 @@ struct gt_defaults {
 enum intel_gt_type {
GT_PRIMARY,
GT_TILE,
+   GT_MEDIA,
 };
 
 struct intel_gt {
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c 
b/drivers/gpu/drm/i915/gt/intel_sa_media.c
new file mode 100644
index ..8c5c519457cc
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include 
+
+#include "i915_drv.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_sa_media.h"
+
+int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
+  u32 gsi_offset)
+{
+   struct drm_i915_private *i915 = gt->i915;
+   struct intel_uncore *uncore;
+
+   uncore = drmm_kzalloc(>drm, sizeof(*uncore), GFP_KERNEL);
+   if (!uncore)
+   return -ENOMEM;
+
+   uncore->gsi_offset = gsi_offset;
+
+   intel_gt_common_init_early(gt);
+   intel_uncore_init_early(uncore, gt);
+
+   /*
+* Standalone media shares the general MMIO space with the primary
+* GT.  We'll re-use the primary GT's mapping.
+*/
+   uncore->regs = i915->uncore.regs;
+   if (drm_WARN_ON(>drm, uncore->regs == NULL))
+   return -EIO;
+
+   gt->uncore = uncore;
+   gt->phys_addr = phys_addr;
+
+   return 0;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.h 
b/drivers/gpu/drm/i915/gt/intel_sa_media.h
new file mode 100644
index ..3afb310de932
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_sa_media.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*

[Intel-gfx] [PATCH 1/8] drm/i915: Prepare more multi-GT initialization

[Ashutosh Dixit]

From: Matt Roper 

DO NOT REVIEW, FOR COMPILING ONLY

We're going to introduce an additional intel_gt for MTL's media unit
soon.  Let's provide a bit more multi-GT initialization framework in
preparation for that.  The initialization will pull the list of GTs for
a platform from the device info structure.  Although necessary for the
immediate MTL media enabling, this same framework will also be used
farther down the road when we enable remote tiles on xehpsdv and pvc.

v2:
 - Re-add missing test for !HAS_EXTRA_GT_LIST in intel_gt_probe_all().

v3:
 - Move intel_gt_definition struct to intel_gt_types.h.  (Jani)
 - Drop gtdef->setup().  For now we'll just use a switch() based on GT
   type since we don't have too many different handlers for the
   forseeable future.  (Jani)

Cc: Aravind Iddamsetty 
Cc: Jani Nikula 
Signed-off-by: Matt Roper 
Reviewed-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt.c| 59 ++-
 drivers/gpu/drm/i915/gt/intel_gt.h|  1 -
 drivers/gpu/drm/i915/gt/intel_gt_types.h  | 15 +
 drivers/gpu/drm/i915/i915_drv.h   |  2 +
 drivers/gpu/drm/i915/intel_device_info.h  |  3 +
 .../gpu/drm/i915/selftests/mock_gem_device.c  |  1 +
 7 files changed, 80 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 275ad72940c1..41acc285e8bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -736,7 +736,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt 
*gt)
u16 vdbox_mask;
u16 vebox_mask;
 
-   info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+   GEM_BUG_ON(!info->engine_mask);
 
if (GRAPHICS_VER(i915) < 11)
return info->engine_mask;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index e4bac2431e41..530637e102c0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -827,8 +827,10 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
 {
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct intel_gt *gt = >gt0;
+   const struct intel_gt_definition *gtdef;
phys_addr_t phys_addr;
unsigned int mmio_bar;
+   unsigned int i;
int ret;
 
mmio_bar = GRAPHICS_VER(i915) == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
@@ -839,14 +841,69 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
 * and it has been already initialized early during probe
 * in i915_driver_probe()
 */
+   gt->i915 = i915;
+   gt->name = "Primary GT";
+   gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+
+   drm_dbg(>drm, "Setting up %s\n", gt->name);
ret = intel_gt_tile_setup(gt, phys_addr);
if (ret)
return ret;
 
i915->gt[0] = gt;
 
-   /* TODO: add more tiles */
+   if (!HAS_EXTRA_GT_LIST(i915))
+   return 0;
+
+   for (i = 1, gtdef = _INFO(i915)->extra_gt_list[i - 1];
+gtdef->name != NULL;
+i++, gtdef = _INFO(i915)->extra_gt_list[i - 1]) {
+   gt = drmm_kzalloc(>drm, sizeof(*gt), GFP_KERNEL);
+   if (!gt) {
+   ret = -ENOMEM;
+   goto err;
+   }
+
+   gt->i915 = i915;
+   gt->name = gtdef->name;
+   gt->type = gtdef->type;
+   gt->info.engine_mask = gtdef->engine_mask;
+   gt->info.id = i;
+
+   drm_dbg(>drm, "Setting up %s\n", gt->name);
+   if (GEM_WARN_ON(range_overflows_t(resource_size_t,
+ gtdef->mapping_base,
+ SZ_16M,
+ pci_resource_len(pdev, 
mmio_bar {
+   ret = -ENODEV;
+   goto err;
+   }
+
+   switch (gtdef->type) {
+   case GT_TILE:
+   ret = intel_gt_tile_setup(gt, phys_addr + 
gtdef->mapping_base);
+   break;
+
+   case GT_PRIMARY:
+   /* Primary GT should not appear in extra GT list */
+   default:
+   MISSING_CASE(gtdef->type);
+   ret = -ENODEV;
+   }
+
+   if (ret)
+   goto err;
+
+   i915->gt[i] = gt;
+   }
+
return 0;
+
+err:
+   i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name, 
ret);
+   intel_gt_release_all(i915);
+
+   return ret;
 }
 
 int intel_gt_tiles_init(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h 
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 

[Intel-gfx] [PATCH 0/8] i915: freq caps and perf_limit_reasons changes for MTL

[Ashutosh Dixit]

This series includes freq caps and perf_limit_reasons changes for MTL. The
series depends on:

https://patchwork.freedesktop.org/series/107908/

We have included 4 patches from from the above series as part of this
series in order for this series to compile. These are the first 4 patches
authored by Matt Roper. Please do not review these first 4 patches. Only
patches 5 through 8 need review.

Cc: Badal Nilawar 

Ashutosh Dixit (3):
  drm/i915/gt: Fix perf limit reasons bit positions
  drm/i915/mtl: PERF_LIMIT_REASONS changes for MTL
  drm/i915/rps: Freq caps for MTL

Matt Roper (4):
  drm/i915: Prepare more multi-GT initialization
  drm/i915: Rename and expose common GT early init routine
  drm/i915/uncore: Add GSI offset to uncore
  drm/i915/xelpmp: Expose media as another GT

Tilak Tangudu (1):
  drm/i915/debugfs: Add perf_limit_reasons in debugfs

 drivers/gpu/drm/i915/Makefile |  1 +
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt.c| 77 ++-
 drivers/gpu/drm/i915/gt/intel_gt.h|  3 +-
 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 31 
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   |  8 ++
 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c   |  6 +-
 drivers/gpu/drm/i915/gt/intel_gt_types.h  | 17 
 drivers/gpu/drm/i915/gt/intel_rps.c   | 46 ---
 drivers/gpu/drm/i915/gt/intel_sa_media.c  | 39 ++
 drivers/gpu/drm/i915/gt/intel_sa_media.h  | 15 
 drivers/gpu/drm/i915/i915_drv.h   |  2 +
 drivers/gpu/drm/i915/i915_pci.c   | 14 
 drivers/gpu/drm/i915/i915_reg.h   | 27 +--
 drivers/gpu/drm/i915/intel_device_info.h  |  3 +
 drivers/gpu/drm/i915/intel_uncore.c   | 10 ++-
 drivers/gpu/drm/i915/intel_uncore.h   | 22 +-
 .../gpu/drm/i915/selftests/mock_gem_device.c  |  1 +
 18 files changed, 294 insertions(+), 30 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h

-- 
2.34.1

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Document and future-proof preemption control policy

[Patchwork]

== Series Details ==

Series: drm/i915: Document and future-proof preemption control policy
URL   : https://patchwork.freedesktop.org/series/108275/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12090_full -> Patchwork_108275v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_108275v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@display-2x:
- shard-iclb: NOTRUN -> [SKIP][1] ([i915#1839])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/shard-iclb1/igt@feature_discov...@display-2x.html

  * igt@gem_eio@in-flight-contexts-10ms:
- shard-iclb: [PASS][2] -> [TIMEOUT][3] ([i915#3070])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb6/igt@gem_...@in-flight-contexts-10ms.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/shard-iclb3/igt@gem_...@in-flight-contexts-10ms.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [PASS][4] -> [SKIP][5] ([i915#4525])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb2/igt@gem_exec_balan...@parallel-keep-submit-fence.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/shard-iclb5/igt@gem_exec_balan...@parallel-keep-submit-fence.html

  * igt@gem_exec_capture@capture-recoverable:
- shard-iclb: NOTRUN -> [SKIP][6] ([i915#6344])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/shard-iclb1/igt@gem_exec_capt...@capture-recoverable.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][7] -> [FAIL][8] ([i915#2846])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk2/igt@gem_exec_f...@basic-deadline.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/shard-glk3/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][9] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar 
issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb8/igt@gem_exec_fair@basic-throt...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_lmem_swapping@verify-ccs:
- shard-iclb: NOTRUN -> [SKIP][14] ([i915#4613])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/shard-iclb1/igt@gem_lmem_swapp...@verify-ccs.html

  * igt@gem_lmem_swapping@verify-random:
- shard-apl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/shard-apl4/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_pread@exhaustion:
- shard-apl:  NOTRUN -> [WARN][16] ([i915#2658])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/shard-apl7/igt@gem_pr...@exhaustion.html

  * igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#4270])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/shard-iclb1/igt@gem_...@verify-pxp-stale-ctx-execution.html

  * igt@gem_userptr_blits@vma-merge:
- shard-iclb: NOTRUN -> [FAIL][18] ([i915#3318])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/shard-iclb1/igt@gem_userptr_bl...@vma-merge.html

  * igt@gen9_exec_parse@batch-without-end:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#2856])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/shard-iclb1/igt@gen9_exec_pa...@batch-without-end.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#5286])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/shard-iclb1/igt@kms_big...@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@linear-16bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][21] ([fdo#110725] / [fdo#111614])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/shard-iclb1/igt@kms_big...@linear-16bpp-rotate-270.html

  * 

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/gt: Use MEDIA_VER() when handling 
media fuses
URL   : https://patchwork.freedesktop.org/series/108269/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12090_full -> Patchwork_108269v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_108269v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_108269v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 12)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_108269v1_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_module_load@reload-with-fault-injection:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-tglb2/igt@i915_module_l...@reload-with-fault-injection.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-tglb3/igt@i915_module_l...@reload-with-fault-injection.html

  
Known issues


  Here are the changes found in Patchwork_108269v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@display-2x:
- shard-iclb: NOTRUN -> [SKIP][3] ([i915#1839])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@feature_discov...@display-2x.html

  * igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][4] -> [SKIP][5] ([i915#4525]) +2 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb4/igt@gem_exec_balan...@parallel-out-fence.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb7/igt@gem_exec_balan...@parallel-out-fence.html

  * igt@gem_exec_capture@capture-recoverable:
- shard-iclb: NOTRUN -> [SKIP][6] ([i915#6344])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@gem_exec_capt...@capture-recoverable.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][7] -> [FAIL][8] ([i915#2846])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk2/igt@gem_exec_f...@basic-deadline.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-glk7/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][9] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar 
issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar 
issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb8/igt@gem_exec_fair@basic-throt...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb8/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_suspend@basic-s3@smem:
- shard-apl:  [PASS][14] -> [DMESG-WARN][15] ([i915#180]) +3 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-apl1/igt@gem_exec_suspend@basic...@smem.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-apl8/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_lmem_swapping@verify-ccs:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#4613])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@gem_lmem_swapp...@verify-ccs.html

  * igt@gem_lmem_swapping@verify-random:
- shard-apl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-apl1/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_pread@exhaustion:
- shard-apl:  NOTRUN -> [WARN][18] ([i915#2658])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-apl6/igt@gem_pr...@exhaustion.html

  * igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#4270])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/shard-iclb3/igt@gem_...@verify-pxp-stale-ctx-execution.html

  * igt@gem_userptr_blits@vma-merge:
- shard-iclb: 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Invert if/else ladder for frequency read

[Patchwork]

== Series Details ==

Series: drm/i915: Invert if/else ladder for frequency read
URL   : https://patchwork.freedesktop.org/series/108268/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12090_full -> Patchwork_108268v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_108268v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_108268v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 12)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_108268v1_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_module_load@reload-with-fault-injection:
- shard-snb:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-snb4/igt@i915_module_l...@reload-with-fault-injection.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-snb5/igt@i915_module_l...@reload-with-fault-injection.html

  
Known issues


  Here are the changes found in Patchwork_108268v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@display-2x:
- shard-iclb: NOTRUN -> [SKIP][3] ([i915#1839])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@feature_discov...@display-2x.html

  * igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [PASS][4] -> [SKIP][5] ([i915#4525])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb4/igt@gem_exec_balan...@parallel-contexts.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb7/igt@gem_exec_balan...@parallel-contexts.html

  * igt@gem_exec_capture@capture-recoverable:
- shard-iclb: NOTRUN -> [SKIP][6] ([i915#6344])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@gem_exec_capt...@capture-recoverable.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][7] -> [FAIL][8] ([i915#2846])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk2/igt@gem_exec_f...@basic-deadline.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-glk7/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842]) +1 similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][12] -> [FAIL][13] ([i915#2842]) +3 similar 
issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_lmem_swapping@verify-ccs:
- shard-iclb: NOTRUN -> [SKIP][14] ([i915#4613])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@gem_lmem_swapp...@verify-ccs.html

  * igt@gem_lmem_swapping@verify-random:
- shard-apl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl7/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-snb:  [PASS][16] -> [FAIL][17] ([i915#4998])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/shard-snb2/igt@gem_pp...@blt-vs-render-ctxn.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-snb6/igt@gem_pp...@blt-vs-render-ctxn.html

  * igt@gem_pread@exhaustion:
- shard-apl:  NOTRUN -> [WARN][18] ([i915#2658])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-apl6/igt@gem_pr...@exhaustion.html

  * igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#4270])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/shard-iclb3/igt@gem_...@verify-pxp-stale-ctx-execution.html

  * igt@gem_userptr_blits@vma-merge:
- shard-iclb: NOTRUN -> [FAIL][20] ([i915#3318])
   [20]: 

Re: [Intel-gfx] [PATCH v3 13/15] drm/i915/huc: better define HuC status getparam possible return values.

[Teres Alexis, Alan Previn]

Yup - simple stuff - LGTM:

Reviewed-by: Alan Previn 

On Fri, 2022-08-19 at 15:53 -0700, Daniele Ceraolo Spurio wrote:
> The current HuC status getparam return values are a bit confusing in
> regards to what happens in some scenarios. In particular, most of the
> error cases cause the ioctl to return an error, but a couple of them,
> INIT_FAIL and LOAD_FAIL, are not explicitly handled and neither is
> their expected return value documented; these 2 error cases therefore
> end up into the catch-all umbrella of the "HuC not loaded" case, with
> this case therefore including both some error scenarios and the load
> in progress one.
> 
> The updates included in this patch change the handling so that all
> error cases behave the same way, i.e. return an errno code, and so
> that the HuC load in progress case is unambiguous.
> 
> The patch also includes a small change to the FW init path to make sure
> we always transition to an error state if something goes wrong.
> 
> Signed-off-by: Daniele Ceraolo Spurio 
> Cc: Tvrtko Ursulin 
> Cc: Tony Ye 
> Acked-by: Tvrtko Ursulin 
> Acked-by: Tony Ye 
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c   |  1 +
>  drivers/gpu/drm/i915/gt/uc/intel_huc.c   | 14 +++---
>  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c |  1 -
>  include/uapi/drm/i915_drm.h  | 16 
>  4 files changed, 24 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 01f2705cb94a..10b2da810a8f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -443,6 +443,7 @@ int intel_guc_init(struct intel_guc *guc)
>  err_fw:
>   intel_uc_fw_fini(>fw);
>  out:
> + intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_INIT_FAIL);
>   i915_probe_error(gt->i915, "failed with %d\n", ret);
>   return ret;
>  }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index 9a97b8cc90c7..1a34c902d081 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -284,6 +284,7 @@ int intel_huc_init(struct intel_huc *huc)
>   return 0;
>  
>  out:
> + intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_INIT_FAIL);
>   drm_info(>drm, "HuC init failed with %d\n", err);
>   return err;
>  }
> @@ -403,13 +404,8 @@ bool intel_huc_is_authenticated(struct intel_huc *huc)
>   * This function reads status register to verify if HuC
>   * firmware was successfully loaded.
>   *
> - * Returns:
> - *  * -ENODEV if HuC is not present on this platform,
> - *  * -EOPNOTSUPP if HuC firmware is disabled,
> - *  * -ENOPKG if HuC firmware was not installed,
> - *  * -ENOEXEC if HuC firmware is invalid or mismatched,
> - *  * 0 if HuC firmware is not running,
> - *  * 1 if HuC firmware is authenticated and running.
> + * The return values match what is expected for the I915_PARAM_HUC_STATUS
> + * getparam.
>   */
>  int intel_huc_check_status(struct intel_huc *huc)
>  {
> @@ -422,6 +418,10 @@ int intel_huc_check_status(struct intel_huc *huc)
>   return -ENOPKG;
>   case INTEL_UC_FIRMWARE_ERROR:
>   return -ENOEXEC;
> + case INTEL_UC_FIRMWARE_INIT_FAIL:
> + return -ENOMEM;
> + case INTEL_UC_FIRMWARE_LOAD_FAIL:
> + return -EIO;
>   default:
>   break;
>   }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index 58547292efa0..cec6bf6bad3f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -749,7 +749,6 @@ int intel_uc_fw_init(struct intel_uc_fw *uc_fw)
>  out_unpin:
>   i915_gem_object_unpin_pages(uc_fw->obj);
>  out:
> - intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_INIT_FAIL);
>   return err;
>  }
>  
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 520ad2691a99..629198f1d8d8 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -645,6 +645,22 @@ typedef struct drm_i915_irq_wait {
>   */
>  #define   I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)
>  
> +/*
> + * Query the status of HuC load.
> + *
> + * The query can fail in the following scenarios with the listed error codes:
> + *  -ENODEV if HuC is not present on this platform,
> + *  -EOPNOTSUPP if HuC firmware usage is disabled,
> + *  -ENOPKG if HuC firmware fetch failed,
> + *  -ENOEXEC if HuC firmware is invalid or mismatched,
> + *  -ENOMEM if i915 failed to prepare the FW objects for transfer to the uC,
> + *  -EIO if the FW transfer or the FW authentication failed.
> + *
> + * If the IOCTL is successful, the returned parameter will be set to one of 
> the
> + * following values:
> + *  * 0 if HuC firmware load is not complete,
> + *  * 1 if HuC firmware is authenticated and running.
> + */
>  #define I915_PARAM_HUC_STATUS 

[Intel-gfx] ✓ Fi.CI.BAT: success for Initial Meteorlake Support (rev8)

[Patchwork]

== Series Details ==

Series: Initial Meteorlake Support (rev8)
URL   : https://patchwork.freedesktop.org/series/106786/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12091 -> Patchwork_106786v8


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v8/index.html

Participating hosts (39 -> 38)
--

  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_106786v8 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][1] -> [INCOMPLETE][2] ([i915#3921])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12091/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v8/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick:[PASS][3] -> [DMESG-FAIL][4] ([i915#3428] / 
[i915#6217])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12091/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v8/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-bdw-5557u:   [PASS][5] -> [INCOMPLETE][6] ([i915#146] / 
[i915#6598] / [i915#6712])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12091/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v8/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v8/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-skl-6600u:   NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v8/fi-skl-6600u/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#4312])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v8/fi-bsw-nick/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- fi-skl-6600u:   [INCOMPLETE][10] -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12091/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v8/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][12] ([i915#4785]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12091/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v8/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [FAIL][14] ([i915#6298]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12091/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v8/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html

  
 Warnings 

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [FAIL][16] ([fdo#103375]) -> [INCOMPLETE][17] 
([i915#5982])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12091/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v8/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
  [i915#6217]: https://gitlab.freedesktop.org/drm/intel/issues/6217
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
  [i915#6598]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Initial Meteorlake Support (rev8)

[Patchwork]

== Series Details ==

Series: Initial Meteorlake Support (rev8)
URL   : https://patchwork.freedesktop.org/series/106786/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Initial Meteorlake Support (rev8)

[Patchwork]

== Series Details ==

Series: Initial Meteorlake Support (rev8)
URL   : https://patchwork.freedesktop.org/series/106786/
State : warning

== Summary ==

Error: dim checkpatch failed
4b29e4a0d695 drm/i915: Move display and media IP version to runtime info
-:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#34: FILE: drivers/gpu/drm/i915/i915_drv.h:471:
+#define GRAPHICS_VER_FULL(i915)
IP_VER(RUNTIME_INFO(i915)->graphics.version.ver, \
+  
RUNTIME_INFO(i915)->graphics.version.rel)

-:43: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#43: FILE: drivers/gpu/drm/i915/i915_drv.h:477:
+#define MEDIA_VER_FULL(i915)   
IP_VER(RUNTIME_INFO(i915)->media.version.ver, \
+  
RUNTIME_INFO(i915)->media.version.rel)

-:168: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#168: FILE: drivers/gpu/drm/i915/i915_pci.c:1284:
+   int gttmmaddr_bar = intel_info->__runtime.graphics.version.ver == 2 ? 
GEN2_GTTMMADR_BAR : GTTMMADR_BAR;

total: 0 errors, 1 warnings, 2 checks, 210 lines checked
6a2c41b22e56 drm/i915: Read graphics/media/display arch version from hw
79280c5d5e17 drm/i915: Parse and set stepping for platforms with GMD
42e768a03bc4 drm/i915/mtl: Define engine context layouts
-:75: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#75: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:643:
+   NOP(1),$

-:76: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#76: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:644:
+   LRI(13, POSTED),$

-:77: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#77: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:645:
+   REG16(0x244),$

-:78: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#78: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:646:
+   REG(0x034),$

-:79: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#79: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:647:
+   REG(0x030),$

-:80: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#80: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:648:
+   REG(0x038),$

-:81: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#81: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:649:
+   REG(0x03c),$

-:82: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#82: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:650:
+   REG(0x168),$

-:83: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#83: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:651:
+   REG(0x140),$

-:84: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#84: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:652:
+   REG(0x110),$

-:85: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#85: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:653:
+   REG(0x1c0),$

-:86: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#86: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:654:
+   REG(0x1c4),$

-:87: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#87: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:655:
+   REG(0x1c8),$

-:88: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#88: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:656:
+   REG(0x180),$

-:89: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#89: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:657:
+   REG16(0x2b4),$

-:91: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#91: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:659:
+   NOP(1),$

-:92: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#92: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:660:
+   LRI(9, POSTED),$

-:93: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#93: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:661:
+   REG16(0x3a8),$

-:94: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#94: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:662:
+   REG16(0x28c),$

-:95: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#95: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:663:
+   REG16(0x288),$

-:96: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#96: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:664:
+   REG16(0x284),$

-:97: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#97: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:665:
+   REG16(0x280),$

-:98: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#98: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:666:
+   REG16(0x27c),$

-:99: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#99: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:667:
+   REG16(0x278),$

-:100: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#100: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:668:
+   REG16(0x274),$

-:101: 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Set correct domains values at _i915_vma_move_to_active

[Patchwork]

== Series Details ==

Series: drm/i915: Set correct domains values at _i915_vma_move_to_active
URL   : https://patchwork.freedesktop.org/series/108258/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12089_full -> Patchwork_108258v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_108258v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_108258v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 12)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_108258v1_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_module_load@reload-with-fault-injection:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-tglb6/igt@i915_module_l...@reload-with-fault-injection.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/shard-tglb5/igt@i915_module_l...@reload-with-fault-injection.html

  * igt@i915_pm_rps@engine-order:
- shard-apl:  [PASS][3] -> [FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl1/igt@i915_pm_...@engine-order.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/shard-apl7/igt@i915_pm_...@engine-order.html

  
Known issues


  Here are the changes found in Patchwork_108258v1_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-apl:  ([PASS][5], [PASS][6], [PASS][7], [PASS][8], 
[PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], 
[PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], 
[PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], 
[PASS][27], [PASS][28], [PASS][29]) -> ([FAIL][30], [PASS][31], [PASS][32], 
[PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], 
[PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], 
[PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], 
[PASS][51], [PASS][52], [PASS][53], [PASS][54]) ([i915#4386])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl8/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl8/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl8/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl7/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl7/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl7/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl7/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl6/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl6/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl6/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl6/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl4/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl4/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl4/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl3/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl3/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl3/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl2/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl2/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl2/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl1/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl1/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl1/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/shard-apl1/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/shard-apl1/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/shard-apl1/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/shard-apl1/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/shard-apl1/boot.html
   [34]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915/dg2: extend Wa_1409120013 to DG2" (rev2)

[Patchwork]

== Series Details ==

Series: Revert "drm/i915/dg2: extend Wa_1409120013 to DG2" (rev2)
URL   : https://patchwork.freedesktop.org/series/108266/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12091 -> Patchwork_108266v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v2/index.html

Participating hosts (39 -> 38)
--

  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_108266v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_suspend@basic-s3-without-i915:
- fi-bdw-5557u:   [PASS][1] -> [INCOMPLETE][2] ([i915#146] / 
[i915#6598] / [i915#6712])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12091/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v2/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v2/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-skl-6600u:   NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v2/fi-skl-6600u/igt@kms_chamel...@common-hpd-after-suspend.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- fi-skl-6600u:   [INCOMPLETE][5] -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12091/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v2/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][7] ([i915#4785]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12091/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v2/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@slpc:
- {bat-rpls-1}:   [DMESG-FAIL][9] ([i915#6367]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12091/bat-rpls-1/igt@i915_selftest@l...@slpc.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v2/bat-rpls-1/igt@i915_selftest@l...@slpc.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [FAIL][11] ([i915#6298]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12091/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v2/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html

  
 Warnings 

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [FAIL][13] ([fdo#103375]) -> [INCOMPLETE][14] 
([i915#5982])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12091/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v2/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
  [i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6598]: https://gitlab.freedesktop.org/drm/intel/issues/6598
  [i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
  [i915#6712]: https://gitlab.freedesktop.org/drm/intel/issues/6712
  [i915#6730]: https://gitlab.freedesktop.org/drm/intel/issues/6730


Build changes
-

  * Linux: CI_DRM_12091 -> Patchwork_108266v2

  CI-20190529: 20190529
  CI_DRM_12091: 09caa2a40c9e377e8386ffbc48c26884cc4b00bc @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6648: 3c9079c0b97445fbfc903b9c5a1d69707b80af80 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_108266v2: 09caa2a40c9e377e8386ffbc48c26884cc4b00bc @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

4cf91272f174 Revert 

Re: [Intel-gfx] [PATCH v9 15/16] drm/i915/gsc: allocate extended operational memory in LMEM

[Teres Alexis, Alan Previn]

I had provided rb on vers 7 and i see the only difference here in v9 is the 
usage of I915_BO_ALLOC_CPU_CLEAR in
gsc_ext_om_alloc saving us a few lines for free. Thus:

Reviewed-by: Alan Previn 



On Thu, 2022-09-08 at 00:51 +0300, Winkler, Tomas wrote:
> GSC requires more operational memory than available on chip.
> Reserve 4M of LMEM for GSC operation. The memory is provided to the
> GSC as struct resource to the auxiliary data of the child device.
> 
> Cc: Alan Previn 
> Cc: Matthew Auld 
> Signed-off-by: Tomas Winkler 
> Signed-off-by: Alexander Usyskin 
> Signed-off-by: Daniele Ceraolo Spurio 
> ---
> V9: Use I915_BO_ALLOC_CPU_CLEAR to clear the allocated memory
> instead of doing a manual memset (Matt)
> 
>  drivers/gpu/drm/i915/gt/intel_gsc.c | 79 ++---
>  drivers/gpu/drm/i915/gt/intel_gsc.h |  3 ++
>  2 files changed, 75 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c 
> b/drivers/gpu/drm/i915/gt/intel_gsc.c
> index e1040c8f2fd3..7af6db3194dd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gsc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
> @@ -7,6 +7,7 @@
>  #include 
>  #include "i915_drv.h"
>  #include "i915_reg.h"
> +#include "gem/i915_gem_region.h"
>  #include "gt/intel_gsc.h"
>  #include "gt/intel_gt.h"
>  
> @@ -36,12 +37,56 @@ static int gsc_irq_init(int irq)
>   return irq_set_chip_data(irq, NULL);
>  }
>  
> +static int
> +gsc_ext_om_alloc(struct intel_gsc *gsc, struct intel_gsc_intf *intf, size_t 
> size)
> +{
> + struct intel_gt *gt = gsc_to_gt(gsc);
> + struct drm_i915_gem_object *obj;
> + int err;
> +
> + obj = i915_gem_object_create_lmem(gt->i915, size,
> +   I915_BO_ALLOC_CONTIGUOUS |
> +   I915_BO_ALLOC_CPU_CLEAR);
> + if (IS_ERR(obj)) {
> + drm_err(>i915->drm, "Failed to allocate gsc memory\n");
> + return PTR_ERR(obj);
> + }
> +
> + err = i915_gem_object_pin_pages_unlocked(obj);
> + if (err) {
> + drm_err(>i915->drm, "Failed to pin pages for gsc memory\n");
> + goto out_put;
> + }
> +
> + intf->gem_obj = obj;
> +
> + return 0;
> +
> +out_put:
> + i915_gem_object_put(obj);
> + return err;
> +}
> +
> +static void gsc_ext_om_destroy(struct intel_gsc_intf *intf)
> +{
> + struct drm_i915_gem_object *obj = fetch_and_zero(>gem_obj);
> +
> + if (!obj)
> + return;
> +
> + if (i915_gem_object_has_pinned_pages(obj))
> + i915_gem_object_unpin_pages(obj);
> +
> + i915_gem_object_put(obj);
> +}
> +
>  struct gsc_def {
>   const char *name;
>   unsigned long bar;
>   size_t bar_size;
>   bool use_polling;
>   bool slow_firmware;
> + size_t lmem_size;
>  };
>  
>  /* gsc resources and definitions (HECI1 and HECI2) */
> @@ -74,6 +119,7 @@ static const struct gsc_def gsc_def_dg2[] = {
>   .name = "mei-gsc",
>   .bar = DG2_GSC_HECI1_BASE,
>   .bar_size = GSC_BAR_LENGTH,
> + .lmem_size = SZ_4M,
>   },
>   {
>   .name = "mei-gscfi",
> @@ -90,26 +136,32 @@ static void gsc_release_dev(struct device *dev)
>   kfree(adev);
>  }
>  
> -static void gsc_destroy_one(struct intel_gsc_intf *intf)
> +static void gsc_destroy_one(struct drm_i915_private *i915,
> + struct intel_gsc *gsc, unsigned int intf_id)
>  {
> + struct intel_gsc_intf *intf = >intf[intf_id];
> +
>   if (intf->adev) {
>   auxiliary_device_delete(>adev->aux_dev);
>   auxiliary_device_uninit(>adev->aux_dev);
>   intf->adev = NULL;
>   }
> +
>   if (intf->irq >= 0)
>   irq_free_desc(intf->irq);
>   intf->irq = -1;
> +
> + gsc_ext_om_destroy(intf);
>  }
>  
> -static void gsc_init_one(struct drm_i915_private *i915,
> -  struct intel_gsc_intf *intf,
> +static void gsc_init_one(struct drm_i915_private *i915, struct intel_gsc 
> *gsc,
>unsigned int intf_id)
>  {
>   struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>   struct mei_aux_device *adev;
>   struct auxiliary_device *aux_dev;
>   const struct gsc_def *def;
> + struct intel_gsc_intf *intf = >intf[intf_id];
>   int ret;
>  
>   intf->irq = -1;
> @@ -141,7 +193,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
>   intf->irq = irq_alloc_desc(0);
>   if (intf->irq < 0) {
>   drm_err(>drm, "gsc irq error %d\n", intf->irq);
> - return;
> + goto fail;
>   }
>  
>   ret = gsc_irq_init(intf->irq);
> @@ -155,6 +207,19 @@ static void gsc_init_one(struct drm_i915_private *i915,
>   if (!adev)
>   goto fail;
>  
> + if (def->lmem_size) {
> + drm_dbg(>drm, "setting up GSC lmem\n");
> +
> + if (gsc_ext_om_alloc(gsc, intf, def->lmem_size)) {
> + 

Re: [Intel-gfx] [PATCH v9 10/16] mei: mkhi: add memory ready command

[Ceraolo Spurio, Daniele]

On 9/7/2022 2:51 PM, Tomas Winkler wrote:

Add GSC memory ready command.
The command indicates to the firmware that extend operation
memory was setup and the firmware may enter PXP mode.

CC: Daniele Ceraolo Spurio 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 


Reviewed-by: Daniele Ceraolo Spurio 

Daniele


---
V9: Fix duplicated defines caused by wrong --amend

  drivers/misc/mei/mkhi.h | 12 
  1 file changed, 12 insertions(+)

diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
index c3fa3c5d5cb6..1473ea489666 100644
--- a/drivers/misc/mei/mkhi.h
+++ b/drivers/misc/mei/mkhi.h
@@ -16,6 +16,13 @@
  #define MKHI_GEN_GROUP_ID 0xFF
  #define MKHI_GEN_GET_FW_VERSION_CMD 0x2
  
+#define MKHI_GROUP_ID_GFX  0x30

+#define MKHI_GFX_RESET_WARN_CMD_REQ0x0
+#define MKHI_GFX_MEMORY_READY_CMD_REQ  0x1
+
+/* Allow transition to PXP mode without approval */
+#define MKHI_GFX_MEM_READY_PXP_ALLOWED  0x1
+
  struct mkhi_rule_id {
__le16 rule_type;
u8 feature_id;
@@ -40,4 +47,9 @@ struct mkhi_msg {
u8 data[];
  } __packed;
  
+struct mkhi_gfx_mem_ready {

+   struct mkhi_msg_hdr hdr;
+   u32flags;
+} __packed;
+
  #endif /* _MEI_MKHI_H_ */

Re: [Intel-gfx] [PATCH v9 09/16] mei: bus: export common mkhi definitions into a separate header

[Ceraolo Spurio, Daniele]

On 9/7/2022 2:51 PM, Tomas Winkler wrote:

From: Vitaly Lubart 

Exported common mkhi definitions from bus-fixup.c into a separate
header file mkhi.h for other driver usage.


Signed-off-by: Vitaly Lubart 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 


Reviewed-by: Daniele Ceraolo Spurio 

Daniele


---
V8:
1.  is enough for mkhi header.
2. drop MCHI_GROUP_ID definition it is not used
V9:
1. Fix duplicated definition caused by wrong --ammend

  drivers/misc/mei/bus-fixup.c | 31 +-
  drivers/misc/mei/mkhi.h  | 43 
  2 files changed, 44 insertions(+), 30 deletions(-)
  create mode 100644 drivers/misc/mei/mkhi.h

diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 344598fcf8e9..c4e527803299 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -15,6 +15,7 @@
  
  #include "mei_dev.h"

  #include "client.h"
+#include "mkhi.h"
  
  #define MEI_UUID_NFC_INFO UUID_LE(0xd2de1625, 0x382d, 0x417d, \

0x48, 0xa4, 0xef, 0xab, 0xba, 0x8a, 0x12, 0x06)
@@ -89,20 +90,6 @@ struct mei_os_ver {
u8  reserved2;
  } __packed;
  
-#define MKHI_FEATURE_PTT 0x10

-
-struct mkhi_rule_id {
-   __le16 rule_type;
-   u8 feature_id;
-   u8 reserved;
-} __packed;
-
-struct mkhi_fwcaps {
-   struct mkhi_rule_id id;
-   u8 len;
-   u8 data[];
-} __packed;
-
  struct mkhi_fw_ver_block {
u16 minor;
u8 major;
@@ -115,22 +102,6 @@ struct mkhi_fw_ver {
struct mkhi_fw_ver_block ver[MEI_MAX_FW_VER_BLOCKS];
  } __packed;
  
-#define MKHI_FWCAPS_GROUP_ID 0x3

-#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
-#define MKHI_GEN_GROUP_ID 0xFF
-#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
-struct mkhi_msg_hdr {
-   u8  group_id;
-   u8  command;
-   u8  reserved;
-   u8  result;
-} __packed;
-
-struct mkhi_msg {
-   struct mkhi_msg_hdr hdr;
-   u8 data[];
-} __packed;
-
  #define MKHI_OSVER_BUF_LEN (sizeof(struct mkhi_msg_hdr) + \
sizeof(struct mkhi_fwcaps) + \
sizeof(struct mei_os_ver))
diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
new file mode 100644
index ..c3fa3c5d5cb6
--- /dev/null
+++ b/drivers/misc/mei/mkhi.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ */
+
+#ifndef _MEI_MKHI_H_
+#define _MEI_MKHI_H_
+
+#include 
+
+#define MKHI_FEATURE_PTT 0x10
+
+#define MKHI_FWCAPS_GROUP_ID 0x3
+#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
+#define MKHI_GEN_GROUP_ID 0xFF
+#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
+
+struct mkhi_rule_id {
+   __le16 rule_type;
+   u8 feature_id;
+   u8 reserved;
+} __packed;
+
+struct mkhi_fwcaps {
+   struct mkhi_rule_id id;
+   u8 len;
+   u8 data[];
+} __packed;
+
+struct mkhi_msg_hdr {
+   u8  group_id;
+   u8  command;
+   u8  reserved;
+   u8  result;
+} __packed;
+
+struct mkhi_msg {
+   struct mkhi_msg_hdr hdr;
+   u8 data[];
+} __packed;
+
+#endif /* _MEI_MKHI_H_ */

Re: [Intel-gfx] [PATCH v9 08/16] mei: extend timeouts on slow devices

[Ceraolo Spurio, Daniele]

On 9/7/2022 2:51 PM, Tomas Winkler wrote:

From: Alexander Usyskin

Parametrize operational timeouts in order
to support slow firmware on some graphics devices.


Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler


|Reviewed-by: Daniele Ceraolo Spurio  
Daniele |




---
V8:
1. Update copyright date
2. Fix pgi->d0i3 timeout in mei_me_d0i3_enter_sync()
V9:
1. Revert mei_me_d0i3_enter_sync() fix
2. Fix pgi->d0i3 timeout in mei_me_d0i3_exit_sync()

  drivers/misc/mei/bus-fixup.c |  5 ++---
  drivers/misc/mei/client.c| 16 
  drivers/misc/mei/gsc-me.c|  2 +-
  drivers/misc/mei/hbm.c   | 14 +++---
  drivers/misc/mei/hw-me.c | 30 --
  drivers/misc/mei/hw-me.h |  2 +-
  drivers/misc/mei/hw-txe.c|  4 ++--
  drivers/misc/mei/hw.h|  7 ++-
  drivers/misc/mei/init.c  | 19 ++-
  drivers/misc/mei/main.c  |  4 ++--
  drivers/misc/mei/mei_dev.h   | 18 +-
  drivers/misc/mei/pci-me.c|  4 ++--
  12 files changed, 82 insertions(+), 43 deletions(-)

diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 59506ba6fc48..344598fcf8e9 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -1,6 +1,6 @@
  // SPDX-License-Identifier: GPL-2.0
  /*
- * Copyright (c) 2013-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2013-2022, Intel Corporation. All rights reserved.
   * Intel Management Engine Interface (Intel MEI) Linux driver
   */
  
@@ -164,7 +164,6 @@ static int mei_osver(struct mei_cl_device *cldev)

sizeof(struct mkhi_fw_ver))
  #define MKHI_FWVER_LEN(__num) (sizeof(struct mkhi_msg_hdr) + \
   sizeof(struct mkhi_fw_ver_block) * (__num))
-#define MKHI_RCV_TIMEOUT 500 /* receive timeout in msec */
  static int mei_fwver(struct mei_cl_device *cldev)
  {
char buf[MKHI_FWVER_BUF_LEN];
@@ -187,7 +186,7 @@ static int mei_fwver(struct mei_cl_device *cldev)
  
  	ret = 0;

bytes_recv = __mei_cl_recv(cldev->cl, buf, sizeof(buf), NULL, 0,
-  MKHI_RCV_TIMEOUT);
+  cldev->bus->timeouts.mkhi_recv);
if (bytes_recv < 0 || (size_t)bytes_recv < MKHI_FWVER_LEN(1)) {
/*
 * Should be at least one version block,
diff --git a/drivers/misc/mei/client.c b/drivers/misc/mei/client.c
index 31264ab2eb13..0b2fbe1335a7 100644
--- a/drivers/misc/mei/client.c
+++ b/drivers/misc/mei/client.c
@@ -1,6 +1,6 @@
  // SPDX-License-Identifier: GPL-2.0
  /*
- * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
   * Intel Management Engine Interface (Intel MEI) Linux driver
   */
  
@@ -870,7 +870,7 @@ static int mei_cl_send_disconnect(struct mei_cl *cl, struct mei_cl_cb *cb)

}
  
  	list_move_tail(>list, >ctrl_rd_list);

-   cl->timer_count = MEI_CONNECT_TIMEOUT;
+   cl->timer_count = dev->timeouts.connect;
mei_schedule_stall_timer(dev);
  
  	return 0;

@@ -945,7 +945,7 @@ static int __mei_cl_disconnect(struct mei_cl *cl)
wait_event_timeout(cl->wait,
   cl->state == MEI_FILE_DISCONNECT_REPLY ||
   cl->state == MEI_FILE_DISCONNECTED,
-  mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+  dev->timeouts.cl_connect);
mutex_lock(>device_lock);
  
  	rets = cl->status;

@@ -1065,7 +1065,7 @@ static int mei_cl_send_connect(struct mei_cl *cl, struct 
mei_cl_cb *cb)
}
  
  	list_move_tail(>list, >ctrl_rd_list);

-   cl->timer_count = MEI_CONNECT_TIMEOUT;
+   cl->timer_count = dev->timeouts.connect;
mei_schedule_stall_timer(dev);
return 0;
  }
@@ -1164,7 +1164,7 @@ int mei_cl_connect(struct mei_cl *cl, struct 
mei_me_client *me_cl,
 cl->state == MEI_FILE_DISCONNECTED ||
 cl->state == MEI_FILE_DISCONNECT_REQUIRED ||
 cl->state == MEI_FILE_DISCONNECT_REPLY),
-   mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+   dev->timeouts.cl_connect);
mutex_lock(>device_lock);
  
  	if (!mei_cl_is_connected(cl)) {

@@ -1562,7 +1562,7 @@ int mei_cl_notify_request(struct mei_cl *cl,
   cl->notify_en == request ||
   cl->status ||
   !mei_cl_is_connected(cl),
-  mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+  dev->timeouts.cl_connect);
mutex_lock(>device_lock);
  
  	if (cl->notify_en != request && !cl->status)

@@ -2336,7 +2336,7 @@ int mei_cl_dma_alloc_and_map(struct mei_cl *cl, const 
struct file *fp,
mutex_unlock(>device_lock);
wait_event_timeout(cl->wait,
   cl->dma_mapped || 

Re: [Intel-gfx] [v2][PATCH 1/1] drm/i915/dsc: convert dsc debugfs entry from output_bpp to input_bpc

[Navare, Manasi]

On Sat, Sep 03, 2022 at 12:36:58AM +0530, Swati Sharma wrote:
> Convert dsc debugfs entry from output_bpp to input_bpc. The rationale
> is to validate different input bpc across various platforms.
> 
> v2: -improved commit message (Jani N)
> -styling fixes (Jani N)
> 
> Signed-off-by: Swati Sharma 

Thanks for the patch Swati.
This makes sense to test different input bpcs from IGT rather than
forcing compressed bpp so that we leave the proper compressed bpp
calculation to the driver which is the right way.

Make sure this patch and corresponding IGT change gets merged at the
same time else IGT will throw err

Reviewed-by: Manasi Navare 

Manasi

> ---
>  .../drm/i915/display/intel_display_debugfs.c  | 27 +--
>  .../drm/i915/display/intel_display_types.h|  2 +-
>  drivers/gpu/drm/i915/display/intel_dp.c   | 21 ---
>  3 files changed, 19 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 5dc364e9db49..0bd916fd9fec 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2140,7 +2140,7 @@ static const struct file_operations 
> i915_dsc_fec_support_fops = {
>   .write = i915_dsc_fec_support_write
>  };
>  
> -static int i915_dsc_bpp_show(struct seq_file *m, void *data)
> +static int i915_dsc_bpc_show(struct seq_file *m, void *data)
>  {
>   struct drm_connector *connector = m->private;
>   struct drm_device *dev = connector->dev;
> @@ -2163,14 +2163,14 @@ static int i915_dsc_bpp_show(struct seq_file *m, void 
> *data)
>   }
>  
>   crtc_state = to_intel_crtc_state(crtc->state);
> - seq_printf(m, "Compressed_BPP: %d\n", crtc_state->dsc.compressed_bpp);
> + seq_printf(m, "Input_BPC: %d\n", 
> crtc_state->dsc.config.bits_per_component);
>  
>  out: drm_modeset_unlock(>mode_config.connection_mutex);
>  
>   return ret;
>  }
>  
> -static ssize_t i915_dsc_bpp_write(struct file *file,
> +static ssize_t i915_dsc_bpc_write(struct file *file,
> const char __user *ubuf,
> size_t len, loff_t *offp)
>  {
> @@ -2178,33 +2178,32 @@ static ssize_t i915_dsc_bpp_write(struct file *file,
>   ((struct seq_file *)file->private_data)->private;
>   struct intel_encoder *encoder = 
> intel_attached_encoder(to_intel_connector(connector));
>   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> - int dsc_bpp = 0;
> + int dsc_bpc = 0;
>   int ret;
>  
> - ret = kstrtoint_from_user(ubuf, len, 0, _bpp);
> + ret = kstrtoint_from_user(ubuf, len, 0, _bpc);
>   if (ret < 0)
>   return ret;
>  
> - intel_dp->force_dsc_bpp = dsc_bpp;
> + intel_dp->force_dsc_bpc = dsc_bpc;
>   *offp += len;
>  
>   return len;
>  }
>  
> -static int i915_dsc_bpp_open(struct inode *inode,
> +static int i915_dsc_bpc_open(struct inode *inode,
>struct file *file)
>  {
> - return single_open(file, i915_dsc_bpp_show,
> -inode->i_private);
> + return single_open(file, i915_dsc_bpc_show, inode->i_private);
>  }
>  
> -static const struct file_operations i915_dsc_bpp_fops = {
> +static const struct file_operations i915_dsc_bpc_fops = {
>   .owner = THIS_MODULE,
> - .open = i915_dsc_bpp_open,
> + .open = i915_dsc_bpc_open,
>   .read = seq_read,
>   .llseek = seq_lseek,
>   .release = single_release,
> - .write = i915_dsc_bpp_write
> + .write = i915_dsc_bpc_write
>  };
>  
>  /*
> @@ -2274,8 +2273,8 @@ void intel_connector_debugfs_add(struct intel_connector 
> *intel_connector)
>   debugfs_create_file("i915_dsc_fec_support", 0644, root,
>   connector, _dsc_fec_support_fops);
>  
> - debugfs_create_file("i915_dsc_bpp", 0644, root,
> - connector, _dsc_bpp_fops);
> + debugfs_create_file("i915_dsc_bpc", 0644, root,
> + connector, _dsc_bpc_fops);
>   }
>  
>   if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 0da9b208d56e..dbda845030bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1712,7 +1712,7 @@ struct intel_dp {
>  
>   /* Display stream compression testing */
>   bool force_dsc_en;
> - int force_dsc_bpp;
> + int force_dsc_bpc;
>  
>   bool hobl_failed;
>   bool hobl_active;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index d4e037450ac5..c4e1ceb5743f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Noop lrc_init_wa_ctx() on recent/future platforms

[Patchwork]

== Series Details ==

Series: drm/i915: Noop lrc_init_wa_ctx() on recent/future platforms
URL   : https://patchwork.freedesktop.org/series/108278/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12090 -> Patchwork_108278v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108278v1/index.html

Participating hosts (43 -> 36)
--

  Additional (1): fi-snb-2600 
  Missing(8): fi-jsl-1 bat-dg1-5 bat-dg2-8 bat-adlp-6 bat-adlp-4 bat-rplp-1 
fi-ehl-2 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_108278v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_rpm@module-reload:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +20 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108278v1/fi-snb-2600/igt@i915_pm_...@module-reload.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-pnv-d510:NOTRUN -> [SKIP][2] ([fdo#109271])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108278v1/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@vga-hpd-fast:
- fi-snb-2600:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108278v1/fi-snb-2600/igt@kms_chamel...@vga-hpd-fast.html

  * igt@runner@aborted:
- fi-bdw-5557u:   NOTRUN -> [FAIL][4] ([i915#4312])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108278v1/fi-bdw-5557u/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[DMESG-FAIL][5] ([i915#4528]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108278v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@workarounds:
- {bat-rpls-1}:   [DMESG-FAIL][7] -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/bat-rpls-1/igt@i915_selftest@l...@workarounds.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108278v1/bat-rpls-1/igt@i915_selftest@l...@workarounds.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528


Build changes
-

  * Linux: CI_DRM_12090 -> Patchwork_108278v1

  CI-20190529: 20190529
  CI_DRM_12090: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6648: 3c9079c0b97445fbfc903b9c5a1d69707b80af80 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_108278v1: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

c14d73c13e5a drm/i915: Noop lrc_init_wa_ctx() on recent/future platforms

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108278v1/index.html

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/vdsc: Set VDSC PIC_HEIGHT before using for DP DSC

[Matt Roper]

On Fri, Sep 02, 2022 at 06:43:12PM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/vdsc: Set VDSC PIC_HEIGHT before using for DP DSC
> URL   : https://patchwork.freedesktop.org/series/108076/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_12064_full -> Patchwork_108076v1_full
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_108076v1_full absolutely need 
> to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_108076v1_full, please notify your bug team to allow 
> them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (11 -> 12)
> --
> 
>   Additional (1): shard-rkl 
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_108076v1_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@drm_import_export@prime:
> - shard-tglb: [PASS][1] -> [INCOMPLETE][2]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12064/shard-tglb1/igt@drm_import_exp...@prime.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108076v1/shard-tglb5/igt@drm_import_exp...@prime.html
> 
>   * igt@i915_module_load@reload-with-fault-injection:
> - shard-snb:  [PASS][3] -> [INCOMPLETE][4]
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12064/shard-snb4/igt@i915_module_l...@reload-with-fault-injection.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108076v1/shard-snb2/igt@i915_module_l...@reload-with-fault-injection.html

Both of the failures here appear to be random mid-test incompletes,
unrelated to the patch being tested.

Applied to drm-intel-next.  Thanks for the patch and review.


Matt

> 
>   
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * {igt@kms_cursor_crc@cursor-onscreen-512x512}:
> - {shard-tglu}:   NOTRUN -> [SKIP][5] +14 similar issues
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108076v1/shard-tglu-6/igt@kms_cursor_...@cursor-onscreen-512x512.html
> 
>   * {igt@kms_cursor_crc@cursor-rapid-movement-512x512}:
> - shard-iclb: NOTRUN -> [SKIP][6]
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108076v1/shard-iclb2/igt@kms_cursor_...@cursor-rapid-movement-512x512.html
> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_108076v1_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@feature_discovery@psr2:
> - shard-iclb: [PASS][7] -> [SKIP][8] ([i915#658])
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12064/shard-iclb2/igt@feature_discov...@psr2.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108076v1/shard-iclb7/igt@feature_discov...@psr2.html
> 
>   * igt@gem_eio@unwedge-stress:
> - shard-iclb: [PASS][9] -> [TIMEOUT][10] ([i915#3070])
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12064/shard-iclb7/igt@gem_...@unwedge-stress.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108076v1/shard-iclb8/igt@gem_...@unwedge-stress.html
> 
>   * igt@gem_exec_balancer@parallel-out-fence:
> - shard-iclb: [PASS][11] -> [SKIP][12] ([i915#4525]) +1 similar 
> issue
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12064/shard-iclb1/igt@gem_exec_balan...@parallel-out-fence.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108076v1/shard-iclb7/igt@gem_exec_balan...@parallel-out-fence.html
> 
>   * igt@gem_exec_fair@basic-none@vecs0:
> - shard-glk:  [PASS][13] -> [FAIL][14] ([i915#2842])
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12064/shard-glk3/igt@gem_exec_fair@basic-n...@vecs0.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108076v1/shard-glk6/igt@gem_exec_fair@basic-n...@vecs0.html
> 
>   * igt@gem_exec_fair@basic-pace@vcs1:
> - shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842])
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108076v1/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html
> 
>   * igt@gem_exec_params@rsvd2-dirt:
> - shard-iclb: NOTRUN -> [SKIP][16] ([fdo#109283])
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108076v1/shard-iclb2/igt@gem_exec_par...@rsvd2-dirt.html
> 
>   * igt@gem_exec_params@secure-non-root:
> - shard-iclb: NOTRUN -> [SKIP][17] ([fdo#112283])
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108076v1/shard-iclb2/igt@gem_exec_par...@secure-non-root.html
> 
>   * igt@gem_lmem_swapping@parallel-random:
> - 

[Intel-gfx] [PATCH v4.1] drm/i915/mtl: Define engine context layouts

[Radhakrishna Sripada]

From: Matt Roper 

The part of the media and blitter engine contexts that we care about for
setting up an initial state are the same on MTL as they were on DG2
(and PVC), so we need to update the driver conditions to re-use the DG2
context table.

For render/compute engines, the part of the context images are nearly
the same, although the layout had a very slight change --- one POSH
register was removed and the placement of some LRI/noops adjusted
slightly to compensate.

v2:
 - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
 - Drop unused registers in mtl rcs offsets.(Bala)
 - Add missing nop in xcs offsets(Bala)

Bspec: 46261, 46260, 45585
Cc: Balasubramani Vivekanandan 
Signed-off-by: Matt Roper 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 82 -
 1 file changed, 80 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 070cec4ff8a4..a2247d39bdb7 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
END
 };
 
+static const u8 mtl_xcs_offsets[] = {
+   NOP(1),
+   LRI(13, POSTED),
+   REG16(0x244),
+   REG(0x034),
+   REG(0x030),
+   REG(0x038),
+   REG(0x03c),
+   REG(0x168),
+   REG(0x140),
+   REG(0x110),
+   REG(0x1c0),
+   REG(0x1c4),
+   REG(0x1c8),
+   REG(0x180),
+   REG16(0x2b4),
+   NOP(1),
+
+   NOP(1),
+   LRI(9, POSTED),
+   REG16(0x3a8),
+   REG16(0x28c),
+   REG16(0x288),
+   REG16(0x284),
+   REG16(0x280),
+   REG16(0x27c),
+   REG16(0x278),
+   REG16(0x274),
+   REG16(0x270),
+
+   END
+};
+
 static const u8 gen8_rcs_offsets[] = {
NOP(1),
LRI(14, POSTED),
@@ -606,6 +639,47 @@ static const u8 dg2_rcs_offsets[] = {
END
 };
 
+static const u8 mtl_rcs_offsets[] = {
+   NOP(1),
+   LRI(13, POSTED),
+   REG16(0x244),
+   REG(0x034),
+   REG(0x030),
+   REG(0x038),
+   REG(0x03c),
+   REG(0x168),
+   REG(0x140),
+   REG(0x110),
+   REG(0x1c0),
+   REG(0x1c4),
+   REG(0x1c8),
+   REG(0x180),
+   REG16(0x2b4),
+
+   NOP(1),
+   LRI(9, POSTED),
+   REG16(0x3a8),
+   REG16(0x28c),
+   REG16(0x288),
+   REG16(0x284),
+   REG16(0x280),
+   REG16(0x27c),
+   REG16(0x278),
+   REG16(0x274),
+   REG16(0x270),
+
+   NOP(2),
+   LRI(2, POSTED),
+   REG16(0x5a8),
+   REG16(0x5ac),
+
+   NOP(6),
+   LRI(1, 0),
+   REG(0x0c8),
+
+   END
+};
+
 #undef END
 #undef REG16
 #undef REG
@@ -624,7 +698,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs 
*engine)
   !intel_engine_has_relative_mmio(engine));
 
if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
-   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+   return mtl_rcs_offsets;
+   else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_rcs_offsets;
else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
return xehp_rcs_offsets;
@@ -637,7 +713,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs 
*engine)
else
return gen8_rcs_offsets;
} else {
-   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
+   return mtl_xcs_offsets;
+   else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
return dg2_xcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_xcs_offsets;
-- 
2.34.1

[Intel-gfx] [PATCH v4.1] drm/i915: Read graphics/media/display arch version from hw

[Radhakrishna Sripada]

From: Matt Roper 

Going forward, the hardware teams no longer consider new platforms to
have a "generation" in the way we've defined it for past platforms.
Instead, each IP block (graphics, media, display) will have their own
architecture major.minor versions and stepping ID's which should be read
directly from a register in the MMIO space.  New hardware programming
styles, features, and workarounds should be conditional solely on the
architecture version, and should no longer be derived from the PCI
device ID, revision ID, or platform-specific feature flags.

Bspec: 63361, 64111

v2:
  - Move the IP version readout to intel_device_info.c
  - Convert the macro into a function

v3:
  - Move subplatform init to runtime early init
  - Cache runtime ver, release info to compare with hardware values.
  - Use IP_VER for snaity check(MattR)

Signed-off-by: Matt Roper 
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h  |  2 +
 drivers/gpu/drm/i915/i915_driver.c   |  3 +-
 drivers/gpu/drm/i915/i915_drv.h  |  2 +
 drivers/gpu/drm/i915/i915_pci.c  |  1 +
 drivers/gpu/drm/i915/i915_reg.h  |  7 +++
 drivers/gpu/drm/i915/intel_device_info.c | 74 +++-
 drivers/gpu/drm/i915/intel_device_info.h | 12 +++-
 7 files changed, 98 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index d414785003cc..579da62158c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -39,6 +39,8 @@
 #define FORCEWAKE_ACK_RENDER_GEN9  _MMIO(0xd84)
 #define FORCEWAKE_ACK_MEDIA_GEN9   _MMIO(0xd88)
 
+#define GMD_ID_GRAPHICS_MMIO(0xd8c)
+
 #define MCFG_MCR_SELECTOR  _MMIO(0xfd0)
 #define SF_MCR_SELECTOR_MMIO(0xfd8)
 #define GEN8_MCR_SELECTOR  _MMIO(0xfdc)
diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index 56a2bcddb2af..a1ab49521d19 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -323,7 +323,8 @@ static int i915_driver_early_probe(struct drm_i915_private 
*dev_priv)
if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
 
-   intel_device_info_subplatform_init(dev_priv);
+   intel_device_info_runtime_init_early(dev_priv);
+
intel_step_init(dev_priv);
 
intel_uncore_mmio_debug_init_early(_priv->mmio_debug);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2702e3dbed53..bfb69b65ad67 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -936,6 +936,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
 
+#define HAS_GMD_ID(i915)   INTEL_INFO(i915)->has_gmd_id
+
 #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
 
 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f6aaf938c53c..4672894f4bc1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1129,6 +1129,7 @@ static const struct intel_device_info mtl_info = {
PLATFORM(INTEL_METEORLAKE),
.display.has_modular_fia = 1,
.has_flat_ccs = 0,
+   .has_gmd_id = 1,
.has_snoop = 1,
.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c413eec3373f..885ff4598fd4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5798,6 +5798,11 @@
 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz  (1 << 29)
 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz  (2 << 29)
 
+#define GMD_ID_DISPLAY _MMIO(0x510a0)
+#define   GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
+#define   GMD_ID_RELEASE_MASK  REG_GENMASK(21, 14)
+#define   GMD_ID_STEP  REG_GENMASK(5, 0)
+
 /*GEN11 chicken */
 #define _PIPEA_CHICKEN 0x70038
 #define _PIPEB_CHICKEN 0x71038
@@ -8298,4 +8303,6 @@ enum skl_power_gate {
 #define  MTL_LATENCY_LEVEL_EVEN_MASK   REG_GENMASK(12, 0)
 #define  MTL_LATENCY_LEVEL_ODD_MASKREG_GENMASK(28, 16)
 
+#define MTL_MEDIA_GSI_BASE 0x38
+
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 56f19683dd55..f7472f40ab51 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -29,6 +29,7 @@
 
 #include "display/intel_cdclk.h"
 #include "display/intel_de.h"

[Intel-gfx] [PATCH v2] Revert "drm/i915/dg2: extend Wa_1409120013 to DG2"

[Lucas De Marchi]

This reverts commit 487970e8bb776c989013bb59d6cbb22e45b9afc6.

Updated bspec and workaround database note Wa_1409120013 is not needed
for DG2 (or any Xe_LPD) platform. Simply check by display version 12.

v2: Simplify condition check to display version (Matt Roper)

Cc: Matt Atwood 
Cc: Clint Taylor 
Signed-off-by: Lucas De Marchi 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/intel_pm.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 210c1f78cc90..eb9c54bbf51f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7614,9 +7614,8 @@ static void icl_init_clock_gating(struct drm_i915_private 
*dev_priv)
 
 static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-   /* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */
-   if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
-   IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))
+   /* Wa_1409120013 */
+   if (DISPLAY_VER(dev_priv) == 12)
intel_uncore_write(_priv->uncore, 
ILK_DPFC_CHICKEN(INTEL_FBC_A),
   DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
-- 
2.37.2

Re: [Intel-gfx] [PATCH] drm/i915: Invert if/else ladder for frequency read

[Matt Roper]

On Wed, Sep 07, 2022 at 01:30:41PM -0700, Lucas De Marchi wrote:
> Continue converting the driver to the convention of last version first,
> extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
> be handled by the first branch.
> 
> With the new ranges it's easier to see what platform a branch started to
> be taken. Besides the >= 11 change, the branch taken for GRAPHICS_VER == 10
> is also different, but currently there is no such platform in i915.
> 
> Cc: Matt Roper 
> Signed-off-by: Lucas De Marchi 

Reviewed-by: Matt Roper 

> ---
>  .../gpu/drm/i915/gt/intel_gt_clock_utils.c| 77 +--
>  1 file changed, 37 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c 
> b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> index d5d1b04dbcad..93608c9349fd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> @@ -78,77 +78,74 @@ static u32 read_clock_frequency(struct intel_uncore 
> *uncore)
>   u32 f19_2_mhz = 1920;
>   u32 f24_mhz = 2400;
>  
> - if (GRAPHICS_VER(uncore->i915) <= 4) {
> - /*
> -  * PRMs say:
> -  *
> -  * "The value in this register increments once every 16
> -  *  hclks." (through the “Clocking Configuration”
> -  *  (“CLKCFG”) MCHBAR register)
> -  */
> - return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
> - } else if (GRAPHICS_VER(uncore->i915) <= 8) {
> - /*
> -  * PRMs say:
> -  *
> -  * "The PCU TSC counts 10ns increments; this timestamp
> -  *  reflects bits 38:3 of the TSC (i.e. 80ns granularity,
> -  *  rolling over every 1.5 hours).
> -  */
> - return f12_5_mhz;
> - } else if (GRAPHICS_VER(uncore->i915) <= 9) {
> + if (GRAPHICS_VER(uncore->i915) >= 11) {
>   u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
>   u32 freq = 0;
>  
> + /*
> +  * First figure out the reference frequency. There are 2 ways
> +  * we can compute the frequency, either through the
> +  * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
> +  * tells us which one we should use.
> +  */
>   if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == 
> CTC_SOURCE_DIVIDE_LOGIC) {
>   freq = read_reference_ts_freq(uncore);
>   } else {
> - freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
> + u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
> +
> + if (GRAPHICS_VER(uncore->i915) >= 11)
> + freq = gen11_get_crystal_clock_freq(uncore, c0);
> + else
> + freq = gen9_get_crystal_clock_freq(uncore, c0);
>  
>   /*
>* Now figure out how the command stream's timestamp
>* register increments from this frequency (it might
>* increment only every few clock cycle).
>*/
> - freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
> -   CTC_SHIFT_PARAMETER_SHIFT);
> + freq >>= 3 - ((c0 & 
> GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
> +   
> GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
>   }
>  
>   return freq;
> - } else if (GRAPHICS_VER(uncore->i915) <= 12) {
> + } else if (GRAPHICS_VER(uncore->i915) >= 9) {
>   u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
>   u32 freq = 0;
>  
> - /*
> -  * First figure out the reference frequency. There are 2 ways
> -  * we can compute the frequency, either through the
> -  * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
> -  * tells us which one we should use.
> -  */
>   if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == 
> CTC_SOURCE_DIVIDE_LOGIC) {
>   freq = read_reference_ts_freq(uncore);
>   } else {
> - u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
> -
> - if (GRAPHICS_VER(uncore->i915) >= 11)
> - freq = gen11_get_crystal_clock_freq(uncore, c0);
> - else
> - freq = gen9_get_crystal_clock_freq(uncore, c0);
> + freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
>  
>   /*
>* Now figure out how the command stream's timestamp
>* register increments from this frequency (it might
>* 

Re: [Intel-gfx] [PATCH] Revert "drm/i915/dg2: extend Wa_1409120013 to DG2"

[Lucas De Marchi]

On Wed, Sep 07, 2022 at 03:28:30PM -0700, Matt Roper wrote:

On Wed, Sep 07, 2022 at 01:26:06PM -0700, Lucas De Marchi wrote:

This reverts commit 487970e8bb776c989013bb59d6cbb22e45b9afc6.

Updated bspec and workaround database note Wa_1409120013 is not needed
for DG2 (or any Display 13) platform.


This should probably say "Xe_LPD" to use standard terminology.



Cc: Matt Roper 
Cc: Matt Atwood 
Cc: Clint Taylor 
Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 210c1f78cc90..6ff0b80e69ac 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7614,9 +7614,9 @@ static void icl_init_clock_gating(struct drm_i915_private 
*dev_priv)

 static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-   /* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */
+   /* Wa_1409120013:tgl,rkl,adl-s,dg1 */


When adding new workarounds lately I've been dropping the platform
trailers since it's obvious enough from the next few lines of code (and
it's easy for the comments to get out of sync with the code).  I'd be
tempted to just shorten this to "/* Wa_1409120013 */" but up to you.


if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
-   IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))
+   IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv))


We could also go with

   if (DISPLAY_VER(dev_priv) == 12)

to simplify.


indeed, that is better. I will send a new version.

thanks
Lucas De Marchi



Anway, both of the code suggestions are optional; up to you whether you
think they're worth incorporating or not.

Reviewed-by: Matt Roper 

with the small commit message tweak.


Matt


intel_uncore_write(_priv->uncore, 
ILK_DPFC_CHICKEN(INTEL_FBC_A),
   DPFC_CHICKEN_COMP_DUMMY_PIXEL);

--
2.37.2



--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

[Intel-gfx] [PATCH] drm/i915: Noop lrc_init_wa_ctx() on recent/future platforms

[Lucas De Marchi]

Except for graphics version 8 and 9, nothing is done in
lrc_init_wa_ctx(). Assume this won't be needed on future platforms as
well and remove the warning.

Note that this function is not called for anything below version 8 since
those don't use either guc or execlist, i.e. HAS_EXECLISTS() is false.

Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 16 
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 070cec4ff8a4..43fa7b3422c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1695,24 +1695,16 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
unsigned int i;
int err;
 
-   if (!(engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
+   if (GRAPHICS_VER(engine->i915) >= 11 ||
+   !(engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
return;
 
-   switch (GRAPHICS_VER(engine->i915)) {
-   case 12:
-   case 11:
-   return;
-   case 9:
+   if (GRAPHICS_VER(engine->i915) == 9) {
wa_bb_fn[0] = gen9_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
-   break;
-   case 8:
+   } else if (GRAPHICS_VER(engine->i915) == 8) {
wa_bb_fn[0] = gen8_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
-   break;
-   default:
-   MISSING_CASE(GRAPHICS_VER(engine->i915));
-   return;
}
 
err = lrc_create_wa_ctx(engine);
-- 
2.37.2

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Fix perf limit reasons bit positions

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Fix perf limit reasons bit positions
URL   : https://patchwork.freedesktop.org/series/108277/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12090 -> Patchwork_108277v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v1/index.html

Participating hosts (43 -> 42)
--

  Additional (1): fi-snb-2600 
  Missing(2): fi-icl-u2 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_108277v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_rpm@module-reload:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +20 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v1/fi-snb-2600/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][2] -> [INCOMPLETE][3] ([i915#5847])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html

  * igt@kms_chamelium@vga-hpd-fast:
- fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v1/fi-snb-2600/igt@kms_chamel...@vga-hpd-fast.html

  * igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][5] ([fdo#109271] / [i915#4312])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v1/fi-bsw-nick/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][6] ([i915#2867]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@workarounds:
- {bat-rpls-1}:   [DMESG-FAIL][8] -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/bat-rpls-1/igt@i915_selftest@l...@workarounds.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v1/bat-rpls-1/igt@i915_selftest@l...@workarounds.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#5847]: https://gitlab.freedesktop.org/drm/intel/issues/5847
  [i915#6503]: https://gitlab.freedesktop.org/drm/intel/issues/6503


Build changes
-

  * Linux: CI_DRM_12090 -> Patchwork_108277v1

  CI-20190529: 20190529
  CI_DRM_12090: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6648: 3c9079c0b97445fbfc903b9c5a1d69707b80af80 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_108277v1: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

b09ef0ba027b drm/i915/gt: Fix perf limit reasons bit positions

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v1/index.html

Re: [Intel-gfx] [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw

[Sripada, Radhakrishna]

Hi Lucas/Matt,

> -Original Message-
> From: De Marchi, Lucas 
> Sent: Wednesday, September 7, 2022 3:21 PM
> To: Roper, Matthew D 
> Cc: Sripada, Radhakrishna ; intel-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; Vivi, Rodrigo
> 
> Subject: Re: [Intel-gfx] [PATCH v4 02/11] drm/i915: Read 
> graphics/media/display
> arch version from hw
> 
> On Wed, Sep 07, 2022 at 03:13:31PM -0700, Matt Roper wrote:
> >On Wed, Sep 07, 2022 at 01:49:25PM -0700, Lucas De Marchi wrote:
> >> On Thu, Sep 01, 2022 at 11:03:33PM -0700, Radhakrishna Sripada wrote:
> >> > From: Matt Roper 
> >> >
> >> > Going forward, the hardware teams no longer consider new platforms to
> >> > have a "generation" in the way we've defined it for past platforms.
> >> > Instead, each IP block (graphics, media, display) will have their own
> >> > architecture major.minor versions and stepping ID's which should be read
> >> > directly from a register in the MMIO space.  New hardware programming
> >> > styles, features, and workarounds should be conditional solely on the
> >> > architecture version, and should no longer be derived from the PCI
> >> > device ID, revision ID, or platform-specific feature flags.
> >> >
> >> > Bspec: 63361, 64111
> >> >
> >> > v2:
> >> >  - Move the IP version readout to intel_device_info.c
> >> >  - Convert the macro into a function
> >> >
> >> > v3:
> >> >  - Move subplatform init to runtime early init
> >> >  - Cache runtime ver, release info to compare with hardware values.
> >> >
> >> > Signed-off-by: Matt Roper 
> >> > Signed-off-by: Rodrigo Vivi 
> >> > Signed-off-by: Radhakrishna Sripada 
> >> > ---
> >> > drivers/gpu/drm/i915/gt/intel_gt_regs.h  |  2 +
> >> > drivers/gpu/drm/i915/i915_driver.c   |  3 +-
> >> > drivers/gpu/drm/i915/i915_drv.h  |  2 +
> >> > drivers/gpu/drm/i915/i915_pci.c  |  1 +
> >> > drivers/gpu/drm/i915/i915_reg.h  |  7 +++
> >> > drivers/gpu/drm/i915/intel_device_info.c | 74
> +++-
> >> > drivers/gpu/drm/i915/intel_device_info.h | 12 +++-
> >> > 7 files changed, 98 insertions(+), 3 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> >> > index d414785003cc..579da62158c4 100644
> >> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> >> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> >> > @@ -39,6 +39,8 @@
> >> > #define FORCEWAKE_ACK_RENDER_GEN9_MMIO(0xd84)
> >> > #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88)
> >> >
> >> > +#define GMD_ID_GRAPHICS
>   _MMIO(0xd8c)
> >> > +
> >> > #define MCFG_MCR_SELECTOR_MMIO(0xfd0)
> >> > #define SF_MCR_SELECTOR  _MMIO(0xfd8)
> >> > #define GEN8_MCR_SELECTOR_MMIO(0xfdc)
> >> > diff --git a/drivers/gpu/drm/i915/i915_driver.c
> b/drivers/gpu/drm/i915/i915_driver.c
> >> > index 56a2bcddb2af..a1ab49521d19 100644
> >> > --- a/drivers/gpu/drm/i915/i915_driver.c
> >> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> >> > @@ -323,7 +323,8 @@ static int i915_driver_early_probe(struct
> drm_i915_private *dev_priv)
> >> >  if (i915_inject_probe_failure(dev_priv))
> >> >  return -ENODEV;
> >> >
> >> > -intel_device_info_subplatform_init(dev_priv);
> >> > +intel_device_info_runtime_init_early(dev_priv);
> >> > +
> >> >  intel_step_init(dev_priv);
> >> >
> >> >  intel_uncore_mmio_debug_init_early(_priv->mmio_debug);
> >> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> >> > index f85a470397a5..405b59b8c05c 100644
> >> > --- a/drivers/gpu/drm/i915/i915_drv.h
> >> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> > @@ -936,6 +936,8 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
> >> >
> >> > #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
> >> >
> >> > +#define HAS_GMD_ID(i915)INTEL_INFO(i915)->has_gmd_id
> >> > +
> >> > #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
> >> >
> >> > #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
> >> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c
> >> > index f6aaf938c53c..4672894f4bc1 100644
> >> > --- a/drivers/gpu/drm/i915/i915_pci.c
> >> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> >> > @@ -1129,6 +1129,7 @@ static const struct intel_device_info mtl_info = {
> >> >  PLATFORM(INTEL_METEORLAKE),
> >> >  .display.has_modular_fia = 1,
> >> >  .has_flat_ccs = 0,
> >> > +.has_gmd_id = 1,
> >> >  .has_snoop = 1,
> >> >  .__runtime.memory_regions = REGION_SMEM |
> REGION_STOLEN_LMEM,
> >> >  .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
> >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> >> > index 5e6239864c35..e02e461a4b5d 100644
> >> > --- a/drivers/gpu/drm/i915/i915_reg.h
> >> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> > @@ -5798,6 +5798,11 @@
> >> > #define 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/ttm: cleanup the resource of ghost objects after locking them

[Patchwork]

== Series Details ==

Series: drm/ttm: cleanup the resource of ghost objects after locking them
URL   : https://patchwork.freedesktop.org/series/108252/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12088_full -> Patchwork_108252v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_108252v1_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-1:
- {shard-tglu}:   NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108252v1/shard-tglu-2/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-hdmi-a-1.html

  
New tests
-

  New tests have been introduced between CI_DRM_12088_full and 
Patchwork_108252v1_full:

### New IGT tests (2) ###

  * 
igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.15] s

  * 
igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.39] s

  

Known issues


  Here are the changes found in Patchwork_108252v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-apl:  [PASS][2] -> [DMESG-WARN][3] ([i915#180])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12088/shard-apl8/igt@gem_ctx_isolation@preservation...@vecs0.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108252v1/shard-apl8/igt@gem_ctx_isolation@preservation...@vecs0.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12088/shard-tglb1/igt@gem_...@unwedge-stress.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108252v1/shard-tglb6/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][6] -> [SKIP][7] ([i915#4525])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12088/shard-iclb2/igt@gem_exec_balan...@parallel-bb-first.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108252v1/shard-iclb5/igt@gem_exec_balan...@parallel-bb-first.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl:  [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12088/shard-apl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108252v1/shard-apl6/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk:  [PASS][10] -> [FAIL][11] ([i915#2842]) +2 similar 
issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12088/shard-glk2/igt@gem_exec_fair@basic-p...@vcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108252v1/shard-glk2/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][12] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108252v1/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-apl:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#3886]) +2 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108252v1/shard-apl2/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-frame-dump:
- shard-snb:  NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +1 
similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108252v1/shard-snb6/igt@kms_chamel...@dp-frame-dump.html

  * igt@kms_chamelium@hdmi-edid-read:
- shard-apl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +1 
similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108252v1/shard-apl2/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_flip@flip-vs-expired-vblank@a-dp1:
- shard-apl:  [PASS][16] -> [FAIL][17] ([i915#79])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12088/shard-apl1/igt@kms_flip@flip-vs-expired-vbl...@a-dp1.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108252v1/shard-apl2/igt@kms_flip@flip-vs-expired-vbl...@a-dp1.html

  * 
igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#3555]) +1 similar issue
   [18]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for GSC support for XeHP SDV and DG2 (rev5)

[Patchwork]

== Series Details ==

Series: GSC support for XeHP SDV and DG2 (rev5)
URL   : https://patchwork.freedesktop.org/series/106638/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12090 -> Patchwork_106638v5


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v5/index.html

Participating hosts (43 -> 42)
--

  Additional (1): fi-snb-2600 
  Missing(2): fi-icl-u2 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_106638v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_rpm@module-reload:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +20 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v5/fi-snb-2600/igt@i915_pm_...@module-reload.html

  * igt@kms_chamelium@vga-hpd-fast:
- fi-snb-2600:NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v5/fi-snb-2600/igt@kms_chamel...@vga-hpd-fast.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-hdmi-a2:
- fi-glk-j4005:   [PASS][3] -> [FAIL][4] ([i915#2122])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/fi-glk-j4005/igt@kms_flip@basic-flip-vs-wf_vbl...@a-hdmi-a2.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v5/fi-glk-j4005/igt@kms_flip@basic-flip-vs-wf_vbl...@a-hdmi-a2.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][5] ([i915#2867]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v5/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@workarounds:
- {bat-rpls-1}:   [DMESG-FAIL][7] -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/bat-rpls-1/igt@i915_selftest@l...@workarounds.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v5/bat-rpls-1/igt@i915_selftest@l...@workarounds.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
  [i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599


Build changes
-

  * Linux: CI_DRM_12090 -> Patchwork_106638v5

  CI-20190529: 20190529
  CI_DRM_12090: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6648: 3c9079c0b97445fbfc903b9c5a1d69707b80af80 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_106638v5: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

a63803c66a78 HAX: drm/i915: force INTEL_MEI_GSC on for CI
402c3e20cbdd drm/i915/gsc: allocate extended operational memory in LMEM
b25094c8076a mei: debugfs: add pxp mode to devstate in debugfs
11d655b45a5f mei: drop ready bits check after start
45193212b6ee mei: gsc: add transition to PXP mode in resume flow
50fac72d19e9 mei: gsc: setup gsc extended operational memory
2c68ab21d63f mei: mkhi: add memory ready command
234ef1881ac1 mei: bus: export common mkhi definitions into a separate header
25f9cebddf21 mei: extend timeouts on slow devices
70c4474c5e3f mei: gsc: wait for reset thread on stop
2d942f896f65 mei: gsc: use polling instead of interrupts
4527f3b23a42 drm/i915/gsc: add GSC XeHP SDV platform definition
56ebb784089d drm/i915/gsc: add slow_firmware flag to the gsc device definition
2363a6f205dd mei: add slow_firmware flag to the mei auxiliary device
5cd044e2817e mei: add kdoc for struct mei_aux_device
1f01faa03715 drm/i915/gsc: skip irq initialization if using polling

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v5/index.html

Re: [Intel-gfx] [PATCH] Revert "drm/i915/dg2: extend Wa_1409120013 to DG2"

[Matt Roper]

On Wed, Sep 07, 2022 at 01:26:06PM -0700, Lucas De Marchi wrote:
> This reverts commit 487970e8bb776c989013bb59d6cbb22e45b9afc6.
> 
> Updated bspec and workaround database note Wa_1409120013 is not needed
> for DG2 (or any Display 13) platform.

This should probably say "Xe_LPD" to use standard terminology.

> 
> Cc: Matt Roper 
> Cc: Matt Atwood 
> Cc: Clint Taylor 
> Signed-off-by: Lucas De Marchi 
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 210c1f78cc90..6ff0b80e69ac 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7614,9 +7614,9 @@ static void icl_init_clock_gating(struct 
> drm_i915_private *dev_priv)
>  
>  static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
> - /* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */
> + /* Wa_1409120013:tgl,rkl,adl-s,dg1 */

When adding new workarounds lately I've been dropping the platform
trailers since it's obvious enough from the next few lines of code (and
it's easy for the comments to get out of sync with the code).  I'd be
tempted to just shorten this to "/* Wa_1409120013 */" but up to you.

>   if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
> - IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))
> + IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv))

We could also go with

if (DISPLAY_VER(dev_priv) == 12)

to simplify.

Anway, both of the code suggestions are optional; up to you whether you
think they're worth incorporating or not.

Reviewed-by: Matt Roper 

with the small commit message tweak.


Matt

>   intel_uncore_write(_priv->uncore, 
> ILK_DPFC_CHICKEN(INTEL_FBC_A),
>  DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>  
> -- 
> 2.37.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses

[Lucas De Marchi]

On Wed, Sep 07, 2022 at 03:18:00PM -0700, Matt Roper wrote:

On Wed, Sep 07, 2022 at 01:39:10PM -0700, Lucas De Marchi wrote:

Check for media IP version instead of graphics since this is figuring
out the media engines' configuration. Currently the only platform with
non-matching graphics/media version is Meteor Lake: update the check in
gen11_vdbox_has_sfc() so it considers not only version 12, but also any
later version which then includes that platform.

Cc: Matt Roper 
Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 275ad72940c1..5cddee7c2f1d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -654,13 +654,14 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
 */
if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
return false;
-   else if (GRAPHICS_VER(i915) == 12)
+   else if (MEDIA_VER(i915) >= 12)
return (physical_vdbox % 2 == 0) ||
!(BIT(physical_vdbox - 1) & vdbox_mask);
-   else if (GRAPHICS_VER(i915) == 11)
+   else if (MEDIA_VER(i915) == 11)
return logical_vdbox % 2 == 0;

-   MISSING_CASE(GRAPHICS_VER(i915));
+   MISSING_CASE(MEDIA_VER(i915));


Do we even still need the MISSING_CASE given that we now have an
open-ended upper bound above and this is a "gen11" function that doesn't
get called at all on old platforms?

Personally I'd axe it, but up to you.  Either way,

Reviewed-by: Matt Roper 


yeah, I will remove it

thanks
Lucas De Marchi




+
return false;
 }

@@ -747,14 +748,14 @@ static intel_engine_mask_t init_engine_mask(struct 
intel_gt *gt)
 * and bits have disable semantices.
 */
media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
-   if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+   if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
media_fuse = ~media_fuse;

vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
  GEN11_GT_VEBOX_DISABLE_SHIFT;

-   if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+   if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
} else {
--
2.37.2



--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw

[Lucas De Marchi]

On Wed, Sep 07, 2022 at 03:13:31PM -0700, Matt Roper wrote:

On Wed, Sep 07, 2022 at 01:49:25PM -0700, Lucas De Marchi wrote:

On Thu, Sep 01, 2022 at 11:03:33PM -0700, Radhakrishna Sripada wrote:
> From: Matt Roper 
>
> Going forward, the hardware teams no longer consider new platforms to
> have a "generation" in the way we've defined it for past platforms.
> Instead, each IP block (graphics, media, display) will have their own
> architecture major.minor versions and stepping ID's which should be read
> directly from a register in the MMIO space.  New hardware programming
> styles, features, and workarounds should be conditional solely on the
> architecture version, and should no longer be derived from the PCI
> device ID, revision ID, or platform-specific feature flags.
>
> Bspec: 63361, 64111
>
> v2:
>  - Move the IP version readout to intel_device_info.c
>  - Convert the macro into a function
>
> v3:
>  - Move subplatform init to runtime early init
>  - Cache runtime ver, release info to compare with hardware values.
>
> Signed-off-by: Matt Roper 
> Signed-off-by: Rodrigo Vivi 
> Signed-off-by: Radhakrishna Sripada 
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h  |  2 +
> drivers/gpu/drm/i915/i915_driver.c   |  3 +-
> drivers/gpu/drm/i915/i915_drv.h  |  2 +
> drivers/gpu/drm/i915/i915_pci.c  |  1 +
> drivers/gpu/drm/i915/i915_reg.h  |  7 +++
> drivers/gpu/drm/i915/intel_device_info.c | 74 +++-
> drivers/gpu/drm/i915/intel_device_info.h | 12 +++-
> 7 files changed, 98 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index d414785003cc..579da62158c4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -39,6 +39,8 @@
> #define FORCEWAKE_ACK_RENDER_GEN9  _MMIO(0xd84)
> #define FORCEWAKE_ACK_MEDIA_GEN9   _MMIO(0xd88)
>
> +#define GMD_ID_GRAPHICS   _MMIO(0xd8c)
> +
> #define MCFG_MCR_SELECTOR  _MMIO(0xfd0)
> #define SF_MCR_SELECTOR_MMIO(0xfd8)
> #define GEN8_MCR_SELECTOR  _MMIO(0xfdc)
> diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
> index 56a2bcddb2af..a1ab49521d19 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -323,7 +323,8 @@ static int i915_driver_early_probe(struct 
drm_i915_private *dev_priv)
>if (i915_inject_probe_failure(dev_priv))
>return -ENODEV;
>
> -  intel_device_info_subplatform_init(dev_priv);
> +  intel_device_info_runtime_init_early(dev_priv);
> +
>intel_step_init(dev_priv);
>
>intel_uncore_mmio_debug_init_early(_priv->mmio_debug);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f85a470397a5..405b59b8c05c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -936,6 +936,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
>
> +#define HAS_GMD_ID(i915)  INTEL_INFO(i915)->has_gmd_id
> +
> #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
>
> #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index f6aaf938c53c..4672894f4bc1 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1129,6 +1129,7 @@ static const struct intel_device_info mtl_info = {
>PLATFORM(INTEL_METEORLAKE),
>.display.has_modular_fia = 1,
>.has_flat_ccs = 0,
> +  .has_gmd_id = 1,
>.has_snoop = 1,
>.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
>.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5e6239864c35..e02e461a4b5d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5798,6 +5798,11 @@
> #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz  (1 << 29)
> #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz  (2 << 29)
>
> +#define GMD_ID_DISPLAY_MMIO(0x510a0)
> +#define   GMD_ID_ARCH_MASKREG_GENMASK(31, 22)
> +#define   GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
> +#define   GMD_ID_STEP REG_GENMASK(5, 0)
> +
> /*GEN11 chicken */
> #define _PIPEA_CHICKEN 0x70038
> #define _PIPEB_CHICKEN 0x71038
> @@ -8298,4 +8303,6 @@ enum skl_power_gate {
> #define  MTL_LATENCY_LEVEL_EVEN_MASK   REG_GENMASK(12, 0)
> #define  MTL_LATENCY_LEVEL_ODD_MASKREG_GENMASK(28, 16)
>
> +#define MTL_MEDIA_GSI_BASE0x38
> +
> #endif /* _I915_REG_H_ */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c 

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Extract function to apply media fuses

[Matt Roper]

On Wed, Sep 07, 2022 at 01:39:11PM -0700, Lucas De Marchi wrote:
> Just like is done for compute and copy engines, extract a function to
> handle media engines. While at it, be consistent on using or not the
> uncore/gt/info variable aliases.
> 
> Cc: Matt Roper 
> Signed-off-by: Lucas De Marchi 

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c | 136 --
>  1 file changed, 72 insertions(+), 64 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 5cddee7c2f1d..5b9dfa0cd467 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -665,6 +665,74 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
>   return false;
>  }
>  
> +static void engine_mask_apply_media_fuses(struct intel_gt *gt)
> +{
> + struct drm_i915_private *i915 = gt->i915;
> + unsigned int logical_vdbox = 0;
> + unsigned int i;
> + u32 media_fuse, fuse1;
> + u16 vdbox_mask;
> + u16 vebox_mask;
> +
> + if (MEDIA_VER(gt->i915) < 11)
> + return;
> +
> + /*
> +  * On newer platforms the fusing register is called 'enable' and has
> +  * enable semantics, while on older platforms it is called 'disable'
> +  * and bits have disable semantices.
> +  */
> + media_fuse = intel_uncore_read(gt->uncore, 
> GEN11_GT_VEBOX_VDBOX_DISABLE);
> + if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
> + media_fuse = ~media_fuse;
> +
> + vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> + vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> +   GEN11_GT_VEBOX_DISABLE_SHIFT;
> +
> + if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
> + fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
> + gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
> + } else {
> + gt->info.sfc_mask = ~0;
> + }
> +
> + for (i = 0; i < I915_MAX_VCS; i++) {
> + if (!HAS_ENGINE(gt, _VCS(i))) {
> + vdbox_mask &= ~BIT(i);
> + continue;
> + }
> +
> + if (!(BIT(i) & vdbox_mask)) {
> + gt->info.engine_mask &= ~BIT(_VCS(i));
> + drm_dbg(>drm, "vcs%u fused off\n", i);
> + continue;
> + }
> +
> + if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
> + gt->info.vdbox_sfc_access |= BIT(i);
> + logical_vdbox++;
> + }
> + drm_dbg(>drm, "vdbox enable: %04x, instances: %04lx\n",
> + vdbox_mask, VDBOX_MASK(gt));
> + GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
> +
> + for (i = 0; i < I915_MAX_VECS; i++) {
> + if (!HAS_ENGINE(gt, _VECS(i))) {
> + vebox_mask &= ~BIT(i);
> + continue;
> + }
> +
> + if (!(BIT(i) & vebox_mask)) {
> + gt->info.engine_mask &= ~BIT(_VECS(i));
> + drm_dbg(>drm, "vecs%u fused off\n", i);
> + }
> + }
> + drm_dbg(>drm, "vebox enable: %04x, instances: %04lx\n",
> + vebox_mask, VEBOX_MASK(gt));
> + GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
> +}
> +
>  static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
>  {
>   struct drm_i915_private *i915 = gt->i915;
> @@ -673,6 +741,9 @@ static void engine_mask_apply_compute_fuses(struct 
> intel_gt *gt)
>   unsigned long ccs_mask;
>   unsigned int i;
>  
> + if (GRAPHICS_VER(i915) < 11)
> + return;
> +
>   if (hweight32(CCS_MASK(gt)) <= 1)
>   return;
>  
> @@ -730,73 +801,10 @@ static intel_engine_mask_t init_engine_mask(struct 
> intel_gt *gt)
>  {
>   struct drm_i915_private *i915 = gt->i915;
>   struct intel_gt_info *info = >info;
> - struct intel_uncore *uncore = gt->uncore;
> - unsigned int logical_vdbox = 0;
> - unsigned int i;
> - u32 media_fuse, fuse1;
> - u16 vdbox_mask;
> - u16 vebox_mask;
>  
>   info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
>  
> - if (GRAPHICS_VER(i915) < 11)
> - return info->engine_mask;
> -
> - /*
> -  * On newer platforms the fusing register is called 'enable' and has
> -  * enable semantics, while on older platforms it is called 'disable'
> -  * and bits have disable semantices.
> -  */
> - media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> - if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
> - media_fuse = ~media_fuse;
> -
> - vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> - vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> -   GEN11_GT_VEBOX_DISABLE_SHIFT;
> -
> - if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
> - fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for GSC support for XeHP SDV and DG2 (rev5)

[Patchwork]

== Series Details ==

Series: GSC support for XeHP SDV and DG2 (rev5)
URL   : https://patchwork.freedesktop.org/series/106638/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GSC support for XeHP SDV and DG2 (rev5)

[Patchwork]

== Series Details ==

Series: GSC support for XeHP SDV and DG2 (rev5)
URL   : https://patchwork.freedesktop.org/series/106638/
State : warning

== Summary ==

Error: dim checkpatch failed
7c7d317c2214 drm/i915/gsc: skip irq initialization if using polling
f704e2c4045b mei: add kdoc for struct mei_aux_device
a48d8453e36b mei: add slow_firmware flag to the mei auxiliary device
3b70304d1d8f drm/i915/gsc: add slow_firmware flag to the gsc device definition
845780516c12 drm/i915/gsc: add GSC XeHP SDV platform definition
189bf1bbb32e mei: gsc: use polling instead of interrupts
f3e9a50271ef mei: gsc: wait for reset thread on stop
b978dbd357db mei: extend timeouts on slow devices
cf23d51175bf mei: bus: export common mkhi definitions into a separate header
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
-:71: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#71: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 92 lines checked
747d3b74de77 mei: mkhi: add memory ready command
743555c95965 mei: gsc: setup gsc extended operational memory
d800090ab1ff mei: gsc: add transition to PXP mode in resume flow
e16d72283cd2 mei: drop ready bits check after start
814624d7616d mei: debugfs: add pxp mode to devstate in debugfs
-:35: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#35: FILE: drivers/misc/mei/debugfs.c:91:
+#define MEI_PXP_MODE(state) case MEI_DEV_PXP_##state: return #state

total: 1 errors, 0 warnings, 0 checks, 36 lines checked
612c537b0421 drm/i915/gsc: allocate extended operational memory in LMEM
a0d43c9feac4 HAX: drm/i915: force INTEL_MEI_GSC on for CI

Re: [Intel-gfx] [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses

[Matt Roper]

On Wed, Sep 07, 2022 at 01:39:10PM -0700, Lucas De Marchi wrote:
> Check for media IP version instead of graphics since this is figuring
> out the media engines' configuration. Currently the only platform with
> non-matching graphics/media version is Meteor Lake: update the check in
> gen11_vdbox_has_sfc() so it considers not only version 12, but also any
> later version which then includes that platform.
> 
> Cc: Matt Roper 
> Signed-off-by: Lucas De Marchi 
> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++-
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 275ad72940c1..5cddee7c2f1d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -654,13 +654,14 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
>*/
>   if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
>   return false;
> - else if (GRAPHICS_VER(i915) == 12)
> + else if (MEDIA_VER(i915) >= 12)
>   return (physical_vdbox % 2 == 0) ||
>   !(BIT(physical_vdbox - 1) & vdbox_mask);
> - else if (GRAPHICS_VER(i915) == 11)
> + else if (MEDIA_VER(i915) == 11)
>   return logical_vdbox % 2 == 0;
>  
> - MISSING_CASE(GRAPHICS_VER(i915));
> + MISSING_CASE(MEDIA_VER(i915));

Do we even still need the MISSING_CASE given that we now have an
open-ended upper bound above and this is a "gen11" function that doesn't
get called at all on old platforms?

Personally I'd axe it, but up to you.  Either way,

Reviewed-by: Matt Roper 

> +
>   return false;
>  }
>  
> @@ -747,14 +748,14 @@ static intel_engine_mask_t init_engine_mask(struct 
> intel_gt *gt)
>* and bits have disable semantices.
>*/
>   media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> - if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> + if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
>   media_fuse = ~media_fuse;
>  
>   vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
>   vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> GEN11_GT_VEBOX_DISABLE_SHIFT;
>  
> - if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
> + if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
>   fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
>   gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
>   } else {
> -- 
> 2.37.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw

[Matt Roper]

On Wed, Sep 07, 2022 at 01:49:25PM -0700, Lucas De Marchi wrote:
> On Thu, Sep 01, 2022 at 11:03:33PM -0700, Radhakrishna Sripada wrote:
> > From: Matt Roper 
> > 
> > Going forward, the hardware teams no longer consider new platforms to
> > have a "generation" in the way we've defined it for past platforms.
> > Instead, each IP block (graphics, media, display) will have their own
> > architecture major.minor versions and stepping ID's which should be read
> > directly from a register in the MMIO space.  New hardware programming
> > styles, features, and workarounds should be conditional solely on the
> > architecture version, and should no longer be derived from the PCI
> > device ID, revision ID, or platform-specific feature flags.
> > 
> > Bspec: 63361, 64111
> > 
> > v2:
> >  - Move the IP version readout to intel_device_info.c
> >  - Convert the macro into a function
> > 
> > v3:
> >  - Move subplatform init to runtime early init
> >  - Cache runtime ver, release info to compare with hardware values.
> > 
> > Signed-off-by: Matt Roper 
> > Signed-off-by: Rodrigo Vivi 
> > Signed-off-by: Radhakrishna Sripada 
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h  |  2 +
> > drivers/gpu/drm/i915/i915_driver.c   |  3 +-
> > drivers/gpu/drm/i915/i915_drv.h  |  2 +
> > drivers/gpu/drm/i915/i915_pci.c  |  1 +
> > drivers/gpu/drm/i915/i915_reg.h  |  7 +++
> > drivers/gpu/drm/i915/intel_device_info.c | 74 +++-
> > drivers/gpu/drm/i915/intel_device_info.h | 12 +++-
> > 7 files changed, 98 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
> > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index d414785003cc..579da62158c4 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -39,6 +39,8 @@
> > #define FORCEWAKE_ACK_RENDER_GEN9   _MMIO(0xd84)
> > #define FORCEWAKE_ACK_MEDIA_GEN9_MMIO(0xd88)
> > 
> > +#define GMD_ID_GRAPHICS_MMIO(0xd8c)
> > +
> > #define MCFG_MCR_SELECTOR   _MMIO(0xfd0)
> > #define SF_MCR_SELECTOR _MMIO(0xfd8)
> > #define GEN8_MCR_SELECTOR   _MMIO(0xfdc)
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c 
> > b/drivers/gpu/drm/i915/i915_driver.c
> > index 56a2bcddb2af..a1ab49521d19 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -323,7 +323,8 @@ static int i915_driver_early_probe(struct 
> > drm_i915_private *dev_priv)
> > if (i915_inject_probe_failure(dev_priv))
> > return -ENODEV;
> > 
> > -   intel_device_info_subplatform_init(dev_priv);
> > +   intel_device_info_runtime_init_early(dev_priv);
> > +
> > intel_step_init(dev_priv);
> > 
> > intel_uncore_mmio_debug_init_early(_priv->mmio_debug);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index f85a470397a5..405b59b8c05c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -936,6 +936,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > 
> > #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
> > 
> > +#define HAS_GMD_ID(i915)   INTEL_INFO(i915)->has_gmd_id
> > +
> > #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
> > 
> > #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c 
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index f6aaf938c53c..4672894f4bc1 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -1129,6 +1129,7 @@ static const struct intel_device_info mtl_info = {
> > PLATFORM(INTEL_METEORLAKE),
> > .display.has_modular_fia = 1,
> > .has_flat_ccs = 0,
> > +   .has_gmd_id = 1,
> > .has_snoop = 1,
> > .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
> > .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 5e6239864c35..e02e461a4b5d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5798,6 +5798,11 @@
> > #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz   (1 << 29)
> > #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz   (2 << 29)
> > 
> > +#define GMD_ID_DISPLAY _MMIO(0x510a0)
> > +#define   GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
> > +#define   GMD_ID_RELEASE_MASK  REG_GENMASK(21, 14)
> > +#define   GMD_ID_STEP  REG_GENMASK(5, 0)
> > +
> > /*GEN11 chicken */
> > #define _PIPEA_CHICKEN  0x70038
> > #define _PIPEB_CHICKEN  0x71038
> > @@ -8298,4 +8303,6 @@ enum skl_power_gate {
> > #define  MTL_LATENCY_LEVEL_EVEN_MASKREG_GENMASK(12, 0)
> > #define  

[Intel-gfx] [PATCH] drm/i915/gt: Fix perf limit reasons bit positions

[Ashutosh Dixit]

Perf limit reasons bit positions were off by one.

Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces")
Cc: Sujaritha Sundaresan 
Cc: Andi Shyti 
Signed-off-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_reg.h | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c413eec3373f..24009786f88b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1794,14 +1794,14 @@
 
 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
 #define   GT0_PERF_LIMIT_REASONS_MASK  0xde3
-#define   PROCHOT_MASK REG_BIT(1)
-#define   THERMAL_LIMIT_MASK   REG_BIT(2)
-#define   RATL_MASKREG_BIT(6)
-#define   VR_THERMALERT_MASK   REG_BIT(7)
-#define   VR_TDC_MASK  REG_BIT(8)
-#define   POWER_LIMIT_4_MASK   REG_BIT(9)
-#define   POWER_LIMIT_1_MASK   REG_BIT(11)
-#define   POWER_LIMIT_2_MASK   REG_BIT(12)
+#define   PROCHOT_MASK REG_BIT(0)
+#define   THERMAL_LIMIT_MASK   REG_BIT(1)
+#define   RATL_MASKREG_BIT(5)
+#define   VR_THERMALERT_MASK   REG_BIT(6)
+#define   VR_TDC_MASK  REG_BIT(7)
+#define   POWER_LIMIT_4_MASK   REG_BIT(8)
+#define   POWER_LIMIT_1_MASK   REG_BIT(10)
+#define   POWER_LIMIT_2_MASK   REG_BIT(11)
 
 #define CHV_CLK_CTL1   _MMIO(0x101100)
 #define VLV_CLK_CTL2   _MMIO(0x101104)
-- 
2.34.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Document and future-proof preemption control policy

[Patchwork]

== Series Details ==

Series: drm/i915: Document and future-proof preemption control policy
URL   : https://patchwork.freedesktop.org/series/108275/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12090 -> Patchwork_108275v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/index.html

Participating hosts (43 -> 43)
--

  Additional (1): fi-snb-2600 
  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_108275v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@gem:
- fi-blb-e6850:   NOTRUN -> [DMESG-FAIL][1] ([i915#4528])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/fi-blb-e6850/igt@i915_selftest@l...@gem.html
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][2] ([i915#4528])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/fi-pnv-d510/igt@i915_selftest@l...@gem.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/fi-snb-2600/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u:   [PASS][4] -> [DMESG-WARN][5] ([i915#62]) +12 similar 
issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_psr@primary_page_flip:
- fi-snb-2600:NOTRUN -> [SKIP][6] ([fdo#109271]) +20 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/fi-snb-2600/igt@kms_psr@primary_page_flip.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][7] ([i915#2867]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[DMESG-FAIL][9] ([i915#4528]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html
- fi-blb-e6850:   [DMESG-FAIL][11] ([i915#4528]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@workarounds:
- {bat-rpls-1}:   [DMESG-FAIL][13] -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/bat-rpls-1/igt@i915_selftest@l...@workarounds.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/bat-rpls-1/igt@i915_selftest@l...@workarounds.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62


Build changes
-

  * Linux: CI_DRM_12090 -> Patchwork_108275v1

  CI-20190529: 20190529
  CI_DRM_12090: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6648: 3c9079c0b97445fbfc903b9c5a1d69707b80af80 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_108275v1: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

e03fb1544131 drm/i915: Document and future-proof preemption control policy

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108275v1/index.html

[Intel-gfx] [PATCH v9 16/16] HAX: drm/i915: force INTEL_MEI_GSC on for CI

[Tomas Winkler]

From: Daniele Ceraolo Spurio 

After the new config option is merged we'll enable it by default in the
CI config, but for now just force it on via the i915 Kconfig so we can
get pre-merge CI results for it.

Signed-off-by: Daniele Ceraolo Spurio 
Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 
---
V9: Rebase
 drivers/gpu/drm/i915/Kconfig.debug | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/Kconfig.debug 
b/drivers/gpu/drm/i915/Kconfig.debug
index e7fd3e76f8a2..be4ef485d6c1 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -48,6 +48,7 @@ config DRM_I915_DEBUG
select DRM_I915_DEBUG_RUNTIME_PM
select DRM_I915_SW_FENCE_DEBUG_OBJECTS
select DRM_I915_SELFTEST
+   select INTEL_MEI_GSC
select BROKEN # for prototype uAPI
default n
help
-- 
2.37.2

[Intel-gfx] [PATCH v9 13/16] mei: drop ready bits check after start

[Tomas Winkler]

From: Alexander Usyskin 

The check that hardware and host ready bits are set after start
is redundant and may fail and disable driver if there is
back-to-back link reset issued right after start.
This happens during pxp mode transitions when firmware
undergo reset. Remove these checks to eliminate such failures.

Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 
Reviewed-by: Daniele Ceraolo Spurio 
---
V8: New in the series
V9: Rebase

 drivers/misc/mei/init.c | 10 --
 1 file changed, 10 deletions(-)

diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
index 1b4d5d7870b9..bac8852aad51 100644
--- a/drivers/misc/mei/init.c
+++ b/drivers/misc/mei/init.c
@@ -218,16 +218,6 @@ int mei_start(struct mei_device *dev)
goto err;
}
 
-   if (!mei_host_is_ready(dev)) {
-   dev_err(dev->dev, "host is not ready.\n");
-   goto err;
-   }
-
-   if (!mei_hw_is_ready(dev)) {
-   dev_err(dev->dev, "ME is not ready.\n");
-   goto err;
-   }
-
if (!mei_hbm_version_is_supported(dev)) {
dev_dbg(dev->dev, "MEI start failed.\n");
goto err;
-- 
2.37.2

[Intel-gfx] [PATCH v9 14/16] mei: debugfs: add pxp mode to devstate in debugfs

[Tomas Winkler]

Add pxp mode devstate to debugfs to monitor pxp state machine progress.
This is useful to debug issues in scenarios in which the pxp state
needs to be re-initialized, like during power transitions such as
suspend/resume. With this debugfs the state could be monitored
to ensure that pxp is in the ready state.

CC: Vitaly Lubart 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 
Reviewed-by: Daniele Ceraolo Spurio 
---
V9: Rebase
 drivers/misc/mei/debugfs.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/mei/debugfs.c b/drivers/misc/mei/debugfs.c
index 1ce61e9e24fc..3b098d4c8e3d 100644
--- a/drivers/misc/mei/debugfs.c
+++ b/drivers/misc/mei/debugfs.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) 2012-2016, Intel Corporation. All rights reserved
+ * Copyright (c) 2012-2022, Intel Corporation. All rights reserved
  * Intel Management Engine Interface (Intel MEI) Linux driver
  */
 
@@ -86,6 +86,20 @@ static int mei_dbgfs_active_show(struct seq_file *m, void 
*unused)
 }
 DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_active);
 
+static const char *mei_dev_pxp_mode_str(enum mei_dev_pxp_mode state)
+{
+#define MEI_PXP_MODE(state) case MEI_DEV_PXP_##state: return #state
+   switch (state) {
+   MEI_PXP_MODE(DEFAULT);
+   MEI_PXP_MODE(INIT);
+   MEI_PXP_MODE(SETUP);
+   MEI_PXP_MODE(READY);
+   default:
+   return "unknown";
+   }
+#undef MEI_PXP_MODE
+}
+
 static int mei_dbgfs_devstate_show(struct seq_file *m, void *unused)
 {
struct mei_device *dev = m->private;
@@ -112,6 +126,9 @@ static int mei_dbgfs_devstate_show(struct seq_file *m, void 
*unused)
seq_printf(m, "pg:  %s, %s\n",
   mei_pg_is_enabled(dev) ? "ENABLED" : "DISABLED",
   mei_pg_state_str(mei_pg_state(dev)));
+
+   seq_printf(m, "pxp: %s\n", mei_dev_pxp_mode_str(dev->pxp_mode));
+
return 0;
 }
 DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_devstate);
-- 
2.37.2

[Intel-gfx] [PATCH v9 15/16] drm/i915/gsc: allocate extended operational memory in LMEM

[Tomas Winkler]

GSC requires more operational memory than available on chip.
Reserve 4M of LMEM for GSC operation. The memory is provided to the
GSC as struct resource to the auxiliary data of the child device.

Cc: Alan Previn 
Cc: Matthew Auld 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 
Signed-off-by: Daniele Ceraolo Spurio 
---
V9: Use I915_BO_ALLOC_CPU_CLEAR to clear the allocated memory
instead of doing a manual memset (Matt)

 drivers/gpu/drm/i915/gt/intel_gsc.c | 79 ++---
 drivers/gpu/drm/i915/gt/intel_gsc.h |  3 ++
 2 files changed, 75 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c 
b/drivers/gpu/drm/i915/gt/intel_gsc.c
index e1040c8f2fd3..7af6db3194dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -7,6 +7,7 @@
 #include 
 #include "i915_drv.h"
 #include "i915_reg.h"
+#include "gem/i915_gem_region.h"
 #include "gt/intel_gsc.h"
 #include "gt/intel_gt.h"
 
@@ -36,12 +37,56 @@ static int gsc_irq_init(int irq)
return irq_set_chip_data(irq, NULL);
 }
 
+static int
+gsc_ext_om_alloc(struct intel_gsc *gsc, struct intel_gsc_intf *intf, size_t 
size)
+{
+   struct intel_gt *gt = gsc_to_gt(gsc);
+   struct drm_i915_gem_object *obj;
+   int err;
+
+   obj = i915_gem_object_create_lmem(gt->i915, size,
+ I915_BO_ALLOC_CONTIGUOUS |
+ I915_BO_ALLOC_CPU_CLEAR);
+   if (IS_ERR(obj)) {
+   drm_err(>i915->drm, "Failed to allocate gsc memory\n");
+   return PTR_ERR(obj);
+   }
+
+   err = i915_gem_object_pin_pages_unlocked(obj);
+   if (err) {
+   drm_err(>i915->drm, "Failed to pin pages for gsc memory\n");
+   goto out_put;
+   }
+
+   intf->gem_obj = obj;
+
+   return 0;
+
+out_put:
+   i915_gem_object_put(obj);
+   return err;
+}
+
+static void gsc_ext_om_destroy(struct intel_gsc_intf *intf)
+{
+   struct drm_i915_gem_object *obj = fetch_and_zero(>gem_obj);
+
+   if (!obj)
+   return;
+
+   if (i915_gem_object_has_pinned_pages(obj))
+   i915_gem_object_unpin_pages(obj);
+
+   i915_gem_object_put(obj);
+}
+
 struct gsc_def {
const char *name;
unsigned long bar;
size_t bar_size;
bool use_polling;
bool slow_firmware;
+   size_t lmem_size;
 };
 
 /* gsc resources and definitions (HECI1 and HECI2) */
@@ -74,6 +119,7 @@ static const struct gsc_def gsc_def_dg2[] = {
.name = "mei-gsc",
.bar = DG2_GSC_HECI1_BASE,
.bar_size = GSC_BAR_LENGTH,
+   .lmem_size = SZ_4M,
},
{
.name = "mei-gscfi",
@@ -90,26 +136,32 @@ static void gsc_release_dev(struct device *dev)
kfree(adev);
 }
 
-static void gsc_destroy_one(struct intel_gsc_intf *intf)
+static void gsc_destroy_one(struct drm_i915_private *i915,
+   struct intel_gsc *gsc, unsigned int intf_id)
 {
+   struct intel_gsc_intf *intf = >intf[intf_id];
+
if (intf->adev) {
auxiliary_device_delete(>adev->aux_dev);
auxiliary_device_uninit(>adev->aux_dev);
intf->adev = NULL;
}
+
if (intf->irq >= 0)
irq_free_desc(intf->irq);
intf->irq = -1;
+
+   gsc_ext_om_destroy(intf);
 }
 
-static void gsc_init_one(struct drm_i915_private *i915,
-struct intel_gsc_intf *intf,
+static void gsc_init_one(struct drm_i915_private *i915, struct intel_gsc *gsc,
 unsigned int intf_id)
 {
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct mei_aux_device *adev;
struct auxiliary_device *aux_dev;
const struct gsc_def *def;
+   struct intel_gsc_intf *intf = >intf[intf_id];
int ret;
 
intf->irq = -1;
@@ -141,7 +193,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
intf->irq = irq_alloc_desc(0);
if (intf->irq < 0) {
drm_err(>drm, "gsc irq error %d\n", intf->irq);
-   return;
+   goto fail;
}
 
ret = gsc_irq_init(intf->irq);
@@ -155,6 +207,19 @@ static void gsc_init_one(struct drm_i915_private *i915,
if (!adev)
goto fail;
 
+   if (def->lmem_size) {
+   drm_dbg(>drm, "setting up GSC lmem\n");
+
+   if (gsc_ext_om_alloc(gsc, intf, def->lmem_size)) {
+   drm_err(>drm, "setting up gsc extended 
operational memory failed\n");
+   kfree(adev);
+   goto fail;
+   }
+
+   adev->ext_op_mem.start = 
i915_gem_object_get_dma_address(intf->gem_obj, 0);
+   adev->ext_op_mem.end = adev->ext_op_mem.start + def->lmem_size;
+   }
+
adev->irq = intf->irq;
adev->bar.parent = 

[Intel-gfx] [PATCH v9 12/16] mei: gsc: add transition to PXP mode in resume flow

[Tomas Winkler]

From: Vitaly Lubart 

Added transition to PXP mode in resume flow.

CC: Daniele Ceraolo Spurio 
Signed-off-by: Vitaly Lubart 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 
Reviewed-by: Daniele Ceraolo Spurio 
---
V9: rebase

 drivers/misc/mei/gsc-me.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index 6b22726aed55..75765e4df4ed 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -182,11 +182,22 @@ static int __maybe_unused mei_gsc_pm_suspend(struct 
device *device)
 static int __maybe_unused mei_gsc_pm_resume(struct device *device)
 {
struct mei_device *dev = dev_get_drvdata(device);
+   struct auxiliary_device *aux_dev;
+   struct mei_aux_device *adev;
int err;
+   struct mei_me_hw *hw;
 
if (!dev)
return -ENODEV;
 
+   hw = to_me_hw(dev);
+   aux_dev = to_auxiliary_dev(device);
+   adev = auxiliary_dev_to_mei_aux_dev(aux_dev);
+   if (adev->ext_op_mem.start) {
+   mei_gsc_set_ext_op_mem(hw, >ext_op_mem);
+   dev->pxp_mode = MEI_DEV_PXP_INIT;
+   }
+
err = mei_restart(dev);
if (err)
return err;
-- 
2.37.2

[Intel-gfx] [PATCH v9 11/16] mei: gsc: setup gsc extended operational memory

[Tomas Winkler]

1. Retrieve extended operational memory physical pointers from the
   auxiliary device info.
2. Setup memory registers.
3. Notify firmware that the memory is ready by sending the memory
   ready command.
4. Disable PXP device if GSC is not in PXP mode.

CC: Daniele Ceraolo Spurio 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 
Reviewed-by: Daniele Ceraolo Spurio 
---
V7:
1. Add kdoc to mei_aux
2. rename pxp_isready() to pxp_is_ready()
V8:
1. Setup default PXP state
2. Add PXP mode kdoc
3. Fix copyright date
V9: Rebase

 drivers/misc/mei/bus-fixup.c  | 70 ++-
 drivers/misc/mei/gsc-me.c | 16 
 drivers/misc/mei/hw-me-regs.h |  9 -
 drivers/misc/mei/hw-me.c  | 28 +-
 drivers/misc/mei/init.c   |  2 +
 drivers/misc/mei/mei_dev.h| 17 +
 include/linux/mei_aux.h   |  3 ++
 7 files changed, 141 insertions(+), 4 deletions(-)

diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index c4e527803299..79305e4acce2 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -188,6 +188,19 @@ static int mei_fwver(struct mei_cl_device *cldev)
return ret;
 }
 
+static int mei_gfx_memory_ready(struct mei_cl_device *cldev)
+{
+   struct mkhi_gfx_mem_ready req = {0};
+   unsigned int mode = MEI_CL_IO_TX_INTERNAL;
+
+   req.hdr.group_id = MKHI_GROUP_ID_GFX;
+   req.hdr.command = MKHI_GFX_MEMORY_READY_CMD_REQ;
+   req.flags = MKHI_GFX_MEM_READY_PXP_ALLOWED;
+
+   dev_dbg(>dev, "Sending memory ready command\n");
+   return __mei_cl_send(cldev->cl, (u8 *), sizeof(req), 0, mode);
+}
+
 static void mei_mkhi_fix(struct mei_cl_device *cldev)
 {
int ret;
@@ -234,6 +247,39 @@ static void mei_gsc_mkhi_ver(struct mei_cl_device *cldev)
dev_err(>dev, "FW version command failed %d\n", ret);
mei_cldev_disable(cldev);
 }
+
+static void mei_gsc_mkhi_fix_ver(struct mei_cl_device *cldev)
+{
+   int ret;
+
+   /* No need to enable the client if nothing is needed from it */
+   if (!cldev->bus->fw_f_fw_ver_supported &&
+   cldev->bus->pxp_mode != MEI_DEV_PXP_INIT)
+   return;
+
+   ret = mei_cldev_enable(cldev);
+   if (ret)
+   return;
+
+   if (cldev->bus->pxp_mode == MEI_DEV_PXP_INIT) {
+   ret = mei_gfx_memory_ready(cldev);
+   if (ret < 0)
+   dev_err(>dev, "memory ready command failed 
%d\n", ret);
+   else
+   dev_dbg(>dev, "memory ready command sent\n");
+   /* we go to reset after that */
+   cldev->bus->pxp_mode = MEI_DEV_PXP_SETUP;
+   goto out;
+   }
+
+   ret = mei_fwver(cldev);
+   if (ret < 0)
+   dev_err(>dev, "FW version command failed %d\n",
+   ret);
+out:
+   mei_cldev_disable(cldev);
+}
+
 /**
  * mei_wd - wd client on the bus, change protocol version
  *   as the API has changed.
@@ -473,6 +519,26 @@ static void vt_support(struct mei_cl_device *cldev)
cldev->do_match = 1;
 }
 
+/**
+ * pxp_is_ready - enable bus client if pxp is ready
+ *
+ * @cldev: me clients device
+ */
+static void pxp_is_ready(struct mei_cl_device *cldev)
+{
+   struct mei_device *bus = cldev->bus;
+
+   switch (bus->pxp_mode) {
+   case MEI_DEV_PXP_READY:
+   case MEI_DEV_PXP_DEFAULT:
+   cldev->do_match = 1;
+   break;
+   default:
+   cldev->do_match = 0;
+   break;
+   }
+}
+
 #define MEI_FIXUP(_uuid, _hook) { _uuid, _hook }
 
 static struct mei_fixup {
@@ -486,10 +552,10 @@ static struct mei_fixup {
MEI_FIXUP(MEI_UUID_WD, mei_wd),
MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix),
MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver),
-   MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_ver),
+   MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_fix_ver),
MEI_FIXUP(MEI_UUID_HDCP, whitelist),
MEI_FIXUP(MEI_UUID_ANY, vt_support),
-   MEI_FIXUP(MEI_UUID_PAVP, whitelist),
+   MEI_FIXUP(MEI_UUID_PAVP, pxp_is_ready),
 };
 
 /**
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index bfa6154b93e2..6b22726aed55 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -32,6 +32,17 @@ static int mei_gsc_read_hfs(const struct mei_device *dev, 
int where, u32 *val)
return 0;
 }
 
+static void mei_gsc_set_ext_op_mem(const struct mei_me_hw *hw, struct resource 
*mem)
+{
+   u32 low = lower_32_bits(mem->start);
+   u32 hi  = upper_32_bits(mem->start);
+   u32 limit = (resource_size(mem) / SZ_4K) | GSC_EXT_OP_MEM_VALID;
+
+   iowrite32(low, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG);
+   iowrite32(hi, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG);
+   iowrite32(limit, hw->mem_addr + H_GSC_EXT_OP_MEM_LIMIT_REG);
+}
+
 static int mei_gsc_probe(struct auxiliary_device 

[Intel-gfx] [PATCH v9 10/16] mei: mkhi: add memory ready command

[Tomas Winkler]

Add GSC memory ready command.
The command indicates to the firmware that extend operation
memory was setup and the firmware may enter PXP mode.

CC: Daniele Ceraolo Spurio 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 
---
V9: Fix duplicated defines caused by wrong --amend

 drivers/misc/mei/mkhi.h | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
index c3fa3c5d5cb6..1473ea489666 100644
--- a/drivers/misc/mei/mkhi.h
+++ b/drivers/misc/mei/mkhi.h
@@ -16,6 +16,13 @@
 #define MKHI_GEN_GROUP_ID 0xFF
 #define MKHI_GEN_GET_FW_VERSION_CMD 0x2
 
+#define MKHI_GROUP_ID_GFX  0x30
+#define MKHI_GFX_RESET_WARN_CMD_REQ0x0
+#define MKHI_GFX_MEMORY_READY_CMD_REQ  0x1
+
+/* Allow transition to PXP mode without approval */
+#define MKHI_GFX_MEM_READY_PXP_ALLOWED  0x1
+
 struct mkhi_rule_id {
__le16 rule_type;
u8 feature_id;
@@ -40,4 +47,9 @@ struct mkhi_msg {
u8 data[];
 } __packed;
 
+struct mkhi_gfx_mem_ready {
+   struct mkhi_msg_hdr hdr;
+   u32flags;
+} __packed;
+
 #endif /* _MEI_MKHI_H_ */
-- 
2.37.2

[Intel-gfx] [PATCH v9 09/16] mei: bus: export common mkhi definitions into a separate header

[Tomas Winkler]

From: Vitaly Lubart 

Exported common mkhi definitions from bus-fixup.c into a separate
header file mkhi.h for other driver usage.


Signed-off-by: Vitaly Lubart 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 
---
V8:
1.  is enough for mkhi header.
2. drop MCHI_GROUP_ID definition it is not used
V9:
1. Fix duplicated definition caused by wrong --ammend

 drivers/misc/mei/bus-fixup.c | 31 +-
 drivers/misc/mei/mkhi.h  | 43 
 2 files changed, 44 insertions(+), 30 deletions(-)
 create mode 100644 drivers/misc/mei/mkhi.h

diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 344598fcf8e9..c4e527803299 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -15,6 +15,7 @@
 
 #include "mei_dev.h"
 #include "client.h"
+#include "mkhi.h"
 
 #define MEI_UUID_NFC_INFO UUID_LE(0xd2de1625, 0x382d, 0x417d, \
0x48, 0xa4, 0xef, 0xab, 0xba, 0x8a, 0x12, 0x06)
@@ -89,20 +90,6 @@ struct mei_os_ver {
u8  reserved2;
 } __packed;
 
-#define MKHI_FEATURE_PTT 0x10
-
-struct mkhi_rule_id {
-   __le16 rule_type;
-   u8 feature_id;
-   u8 reserved;
-} __packed;
-
-struct mkhi_fwcaps {
-   struct mkhi_rule_id id;
-   u8 len;
-   u8 data[];
-} __packed;
-
 struct mkhi_fw_ver_block {
u16 minor;
u8 major;
@@ -115,22 +102,6 @@ struct mkhi_fw_ver {
struct mkhi_fw_ver_block ver[MEI_MAX_FW_VER_BLOCKS];
 } __packed;
 
-#define MKHI_FWCAPS_GROUP_ID 0x3
-#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
-#define MKHI_GEN_GROUP_ID 0xFF
-#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
-struct mkhi_msg_hdr {
-   u8  group_id;
-   u8  command;
-   u8  reserved;
-   u8  result;
-} __packed;
-
-struct mkhi_msg {
-   struct mkhi_msg_hdr hdr;
-   u8 data[];
-} __packed;
-
 #define MKHI_OSVER_BUF_LEN (sizeof(struct mkhi_msg_hdr) + \
sizeof(struct mkhi_fwcaps) + \
sizeof(struct mei_os_ver))
diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
new file mode 100644
index ..c3fa3c5d5cb6
--- /dev/null
+++ b/drivers/misc/mei/mkhi.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ */
+
+#ifndef _MEI_MKHI_H_
+#define _MEI_MKHI_H_
+
+#include 
+
+#define MKHI_FEATURE_PTT 0x10
+
+#define MKHI_FWCAPS_GROUP_ID 0x3
+#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
+#define MKHI_GEN_GROUP_ID 0xFF
+#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
+
+struct mkhi_rule_id {
+   __le16 rule_type;
+   u8 feature_id;
+   u8 reserved;
+} __packed;
+
+struct mkhi_fwcaps {
+   struct mkhi_rule_id id;
+   u8 len;
+   u8 data[];
+} __packed;
+
+struct mkhi_msg_hdr {
+   u8  group_id;
+   u8  command;
+   u8  reserved;
+   u8  result;
+} __packed;
+
+struct mkhi_msg {
+   struct mkhi_msg_hdr hdr;
+   u8 data[];
+} __packed;
+
+#endif /* _MEI_MKHI_H_ */
-- 
2.37.2

[Intel-gfx] [PATCH v9 08/16] mei: extend timeouts on slow devices

[Tomas Winkler]

From: Alexander Usyskin 

Parametrize operational timeouts in order
to support slow firmware on some graphics devices.


Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 
---
V8:
1. Update copyright date
2. Fix pgi->d0i3 timeout in mei_me_d0i3_enter_sync()
V9:
1. Revert mei_me_d0i3_enter_sync() fix
2. Fix pgi->d0i3 timeout in mei_me_d0i3_exit_sync()

 drivers/misc/mei/bus-fixup.c |  5 ++---
 drivers/misc/mei/client.c| 16 
 drivers/misc/mei/gsc-me.c|  2 +-
 drivers/misc/mei/hbm.c   | 14 +++---
 drivers/misc/mei/hw-me.c | 30 --
 drivers/misc/mei/hw-me.h |  2 +-
 drivers/misc/mei/hw-txe.c|  4 ++--
 drivers/misc/mei/hw.h|  7 ++-
 drivers/misc/mei/init.c  | 19 ++-
 drivers/misc/mei/main.c  |  4 ++--
 drivers/misc/mei/mei_dev.h   | 18 +-
 drivers/misc/mei/pci-me.c|  4 ++--
 12 files changed, 82 insertions(+), 43 deletions(-)

diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 59506ba6fc48..344598fcf8e9 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) 2013-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2013-2022, Intel Corporation. All rights reserved.
  * Intel Management Engine Interface (Intel MEI) Linux driver
  */
 
@@ -164,7 +164,6 @@ static int mei_osver(struct mei_cl_device *cldev)
sizeof(struct mkhi_fw_ver))
 #define MKHI_FWVER_LEN(__num) (sizeof(struct mkhi_msg_hdr) + \
   sizeof(struct mkhi_fw_ver_block) * (__num))
-#define MKHI_RCV_TIMEOUT 500 /* receive timeout in msec */
 static int mei_fwver(struct mei_cl_device *cldev)
 {
char buf[MKHI_FWVER_BUF_LEN];
@@ -187,7 +186,7 @@ static int mei_fwver(struct mei_cl_device *cldev)
 
ret = 0;
bytes_recv = __mei_cl_recv(cldev->cl, buf, sizeof(buf), NULL, 0,
-  MKHI_RCV_TIMEOUT);
+  cldev->bus->timeouts.mkhi_recv);
if (bytes_recv < 0 || (size_t)bytes_recv < MKHI_FWVER_LEN(1)) {
/*
 * Should be at least one version block,
diff --git a/drivers/misc/mei/client.c b/drivers/misc/mei/client.c
index 31264ab2eb13..0b2fbe1335a7 100644
--- a/drivers/misc/mei/client.c
+++ b/drivers/misc/mei/client.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
  * Intel Management Engine Interface (Intel MEI) Linux driver
  */
 
@@ -870,7 +870,7 @@ static int mei_cl_send_disconnect(struct mei_cl *cl, struct 
mei_cl_cb *cb)
}
 
list_move_tail(>list, >ctrl_rd_list);
-   cl->timer_count = MEI_CONNECT_TIMEOUT;
+   cl->timer_count = dev->timeouts.connect;
mei_schedule_stall_timer(dev);
 
return 0;
@@ -945,7 +945,7 @@ static int __mei_cl_disconnect(struct mei_cl *cl)
wait_event_timeout(cl->wait,
   cl->state == MEI_FILE_DISCONNECT_REPLY ||
   cl->state == MEI_FILE_DISCONNECTED,
-  mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+  dev->timeouts.cl_connect);
mutex_lock(>device_lock);
 
rets = cl->status;
@@ -1065,7 +1065,7 @@ static int mei_cl_send_connect(struct mei_cl *cl, struct 
mei_cl_cb *cb)
}
 
list_move_tail(>list, >ctrl_rd_list);
-   cl->timer_count = MEI_CONNECT_TIMEOUT;
+   cl->timer_count = dev->timeouts.connect;
mei_schedule_stall_timer(dev);
return 0;
 }
@@ -1164,7 +1164,7 @@ int mei_cl_connect(struct mei_cl *cl, struct 
mei_me_client *me_cl,
 cl->state == MEI_FILE_DISCONNECTED ||
 cl->state == MEI_FILE_DISCONNECT_REQUIRED ||
 cl->state == MEI_FILE_DISCONNECT_REPLY),
-   mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+   dev->timeouts.cl_connect);
mutex_lock(>device_lock);
 
if (!mei_cl_is_connected(cl)) {
@@ -1562,7 +1562,7 @@ int mei_cl_notify_request(struct mei_cl *cl,
   cl->notify_en == request ||
   cl->status ||
   !mei_cl_is_connected(cl),
-  mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+  dev->timeouts.cl_connect);
mutex_lock(>device_lock);
 
if (cl->notify_en != request && !cl->status)
@@ -2336,7 +2336,7 @@ int mei_cl_dma_alloc_and_map(struct mei_cl *cl, const 
struct file *fp,
mutex_unlock(>device_lock);
wait_event_timeout(cl->wait,
   cl->dma_mapped || cl->status,
-  mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ 

[Intel-gfx] [PATCH v9 06/16] mei: gsc: use polling instead of interrupts

[Tomas Winkler]

A work-around for a HW issue in XEHPSDV that manifests itself when SW reads
a gsc register when gsc is sending an interrupt. The work-around is
to disable interrupts and to use polling instead.


Cc: James Ausmus 
Signed-off-by: Vitaly Lubart 
Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 
Reviewed-by: Daniele Ceraolo Spurio 
---
V8: Add kdoc and comments to mei_me_polling_thread()
V9: Rebase
 drivers/misc/mei/gsc-me.c | 48 ++-
 drivers/misc/mei/hw-me.c  | 80 ---
 drivers/misc/mei/hw-me.h  | 15 +++-
 3 files changed, 128 insertions(+), 15 deletions(-)

diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index c8145e9b62b6..2caba3a9ac35 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "mei_dev.h"
 #include "hw-me.h"
@@ -66,13 +67,28 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
 
dev_set_drvdata(device, dev);
 
-   ret = devm_request_threaded_irq(device, hw->irq,
-   mei_me_irq_quick_handler,
-   mei_me_irq_thread_handler,
-   IRQF_ONESHOT, KBUILD_MODNAME, dev);
-   if (ret) {
-   dev_err(device, "irq register failed %d\n", ret);
-   goto err;
+   /* use polling */
+   if (mei_me_hw_use_polling(hw)) {
+   mei_disable_interrupts(dev);
+   mei_clear_interrupts(dev);
+   init_waitqueue_head(>wait_active);
+   hw->is_active = true; /* start in active mode for 
initialization */
+   hw->polling_thread = kthread_run(mei_me_polling_thread, dev,
+"kmegscirqd/%s", 
dev_name(device));
+   if (IS_ERR(hw->polling_thread)) {
+   ret = PTR_ERR(hw->polling_thread);
+   dev_err(device, "unable to create kernel thread: %d\n", 
ret);
+   goto err;
+   }
+   } else {
+   ret = devm_request_threaded_irq(device, hw->irq,
+   mei_me_irq_quick_handler,
+   mei_me_irq_thread_handler,
+   IRQF_ONESHOT, KBUILD_MODNAME, 
dev);
+   if (ret) {
+   dev_err(device, "irq register failed %d\n", ret);
+   goto err;
+   }
}
 
pm_runtime_get_noresume(device);
@@ -98,7 +114,8 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
 
 register_err:
mei_stop(dev);
-   devm_free_irq(device, hw->irq, dev);
+   if (!mei_me_hw_use_polling(hw))
+   devm_free_irq(device, hw->irq, dev);
 
 err:
dev_err(device, "probe failed: %d\n", ret);
@@ -119,12 +136,17 @@ static void mei_gsc_remove(struct auxiliary_device 
*aux_dev)
 
mei_stop(dev);
 
+   hw = to_me_hw(dev);
+   if (mei_me_hw_use_polling(hw))
+   kthread_stop(hw->polling_thread);
+
mei_deregister(dev);
 
pm_runtime_disable(_dev->dev);
 
mei_disable_interrupts(dev);
-   devm_free_irq(_dev->dev, hw->irq, dev);
+   if (!mei_me_hw_use_polling(hw))
+   devm_free_irq(_dev->dev, hw->irq, dev);
 }
 
 static int __maybe_unused mei_gsc_pm_suspend(struct device *device)
@@ -185,6 +207,9 @@ static int  __maybe_unused 
mei_gsc_pm_runtime_suspend(struct device *device)
if (mei_write_is_idle(dev)) {
hw = to_me_hw(dev);
hw->pg_state = MEI_PG_ON;
+
+   if (mei_me_hw_use_polling(hw))
+   hw->is_active = false;
ret = 0;
} else {
ret = -EAGAIN;
@@ -209,6 +234,11 @@ static int __maybe_unused mei_gsc_pm_runtime_resume(struct 
device *device)
hw = to_me_hw(dev);
hw->pg_state = MEI_PG_OFF;
 
+   if (mei_me_hw_use_polling(hw)) {
+   hw->is_active = true;
+   wake_up(>wait_active);
+   }
+
mutex_unlock(>device_lock);
 
irq_ret = mei_me_irq_thread_handler(1, dev);
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index 3a95fe7d4e33..23ad53efbcb7 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
  * Intel Management Engine Interface (Intel MEI) Linux driver
  */
 
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "mei_dev.h"
 #include "hbm.h"
@@ -327,9 +328,12 @@ static void mei_me_intr_clear(struct mei_device *dev)
  */
 static void mei_me_intr_enable(struct mei_device *dev)
 {
-   u32 hcsr = mei_hcsr_read(dev);
+   

[Intel-gfx] [PATCH v9 07/16] mei: gsc: wait for reset thread on stop

[Tomas Winkler]

From: Alexander Usyskin 

Wait for reset work to complete before initiating
stop reset flow sequence.

Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 
Reviewed-by: Daniele Ceraolo Spurio 
---
V9: Rebase

 drivers/misc/mei/init.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
index eb052005ca86..bc054baf496c 100644
--- a/drivers/misc/mei/init.c
+++ b/drivers/misc/mei/init.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) 2012-2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2012-2022, Intel Corporation. All rights reserved.
  * Intel Management Engine Interface (Intel MEI) Linux driver
  */
 
@@ -320,6 +320,8 @@ void mei_stop(struct mei_device *dev)
 
mei_clear_interrupts(dev);
mei_synchronize_irq(dev);
+   /* to catch HW-initiated reset */
+   mei_cancel_work(dev);
 
mutex_lock(>device_lock);
 
-- 
2.37.2

[Intel-gfx] [PATCH v9 05/16] drm/i915/gsc: add GSC XeHP SDV platform definition

[Tomas Winkler]

From: Alexander Usyskin 

Define GSC on XeHP SDV (Intel(R) dGPU without display)

XeHP SDV uses the same hardware settings as DG1, but uses polling
instead of interrupts and runs the firmware in slow pace due to
hardware limitations.

Signed-off-by: Vitaly Lubart 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 
Reviewed-by: Daniele Ceraolo Spurio 
---
V9: Rebase

 drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c 
b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 73498c2574c8..e1040c8f2fd3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] = {
}
 };
 
+static const struct gsc_def gsc_def_xehpsdv[] = {
+   {
+   /* HECI1 not enabled on the device. */
+   },
+   {
+   .name = "mei-gscfi",
+   .bar = DG1_GSC_HECI2_BASE,
+   .bar_size = GSC_BAR_LENGTH,
+   .use_polling = true,
+   .slow_firmware = true,
+   }
+};
+
 static const struct gsc_def gsc_def_dg2[] = {
{
.name = "mei-gsc",
@@ -107,6 +120,8 @@ static void gsc_init_one(struct drm_i915_private *i915,
 
if (IS_DG1(i915)) {
def = _def_dg1[intf_id];
+   } else if (IS_XEHPSDV(i915)) {
+   def = _def_xehpsdv[intf_id];
} else if (IS_DG2(i915)) {
def = _def_dg2[intf_id];
} else {
-- 
2.37.2

[Intel-gfx] [PATCH v9 04/16] drm/i915/gsc: add slow_firmware flag to the gsc device definition

[Tomas Winkler]

From: Alexander Usyskin 

Add slow_firmware flag to the gsc device definition
and pass it to mei auxiliary device, this instructs
the driver to use longer operation timeouts.

Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 
Reviewed-by: Daniele Ceraolo Spurio 
---
V9: Rebase

 drivers/gpu/drm/i915/gt/intel_gsc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c 
b/drivers/gpu/drm/i915/gt/intel_gsc.c
index e0236ff1d072..73498c2574c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -41,6 +41,7 @@ struct gsc_def {
unsigned long bar;
size_t bar_size;
bool use_polling;
+   bool slow_firmware;
 };
 
 /* gsc resources and definitions (HECI1 and HECI2) */
@@ -145,6 +146,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
adev->bar.end = adev->bar.start + def->bar_size - 1;
adev->bar.flags = IORESOURCE_MEM;
adev->bar.desc = IORES_DESC_NONE;
+   adev->slow_firmware = def->slow_firmware;
 
aux_dev = >aux_dev;
aux_dev->name = def->name;
-- 
2.37.2

[Intel-gfx] [PATCH v9 03/16] mei: add slow_firmware flag to the mei auxiliary device

[Tomas Winkler]

Add slow_firmware flag to the mei auxiliary device info
to inform the mei driver about slow underlying firmware.
Such firmware will require to use larger operation timeouts.

Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 
Reviewed-by: Daniele Ceraolo Spurio 
---
V9: Rebase

 include/linux/mei_aux.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
index a0cb587006d5..4894d8bf4159 100644
--- a/include/linux/mei_aux.h
+++ b/include/linux/mei_aux.h
@@ -12,11 +12,14 @@
  * @aux_dev: - auxiliary device object
  * @irq: interrupt driving the mei auxiliary device
  * @bar: mmio resource bar reserved to mei auxiliary device
+ * @slow_firmware: The device has slow underlying firmware.
+ * Such firmware will require to use larger operation timeouts.
  */
 struct mei_aux_device {
struct auxiliary_device aux_dev;
int irq;
struct resource bar;
+   bool slow_firmware;
 };
 
 #define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \
-- 
2.37.2

[Intel-gfx] [PATCH v8 00/16] GSC support for XeHP SDV and DG2

[Tomas Winkler]

Add GSC support for XeHP SDV and DG2 platforms.

The series includes changes for the mei driver:
- add ability to use polling instead of interrupts
- add ability to use extended timeouts
- setup extended operational memory for GSC

The series includes changes for the i915 driver:
- allocate extended operational memory for GSC
- GSC on XeHP SDV offsets and definitions

This patch set should be merged via gfx tree as
the auxiliary device belongs there.

Acked-by: Greg Kroah-Hartman 

V2: rebase over merged DG1 series and DG2 enablement patch,
fix commit messages

V3: rebase over latest tip

V4: add missed changelog in pxp dbugfs patch

V5: rebase over latest tip
fix changelog in pxp dbugfs patch
put HAX patch last to the ease of merging
reorder patches in the series

V6: change prefix from 'drm/i915/gsc:' to 'mei' in patch:
mei: add slow_fw flag to the mei auxiliary device
Address following checkpatch warnings:
CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t'
FILE: drivers/misc/mei/mkhi.h:54:
+   uint32_t flags; 

-:51: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 
'cldev->bus->pxp_mode != MEI_DEV_PXP_INIT'
#51: FILE: drivers/misc/mei/bus-fixup.c:257:
+   if (!cldev->bus->fw_f_fw_ver_supported &&
+   (cldev->bus->pxp_mode != MEI_DEV_PXP_INIT)

Remove some spurious code formatting changes in:
drm/i915/gsc: allocate extended operational memory in LMEM

V7: Add new patch to add kdoc for mei_aux_device structure.
Rename slow_fw to slow_firmware flag.
Use drm_dbg/err() functions instead of dev_dbg/err() in i195
codebase.

V8:
   1. Update copyright dates
   1. Add kdoc and comments to mei_me_polling_thread()
   2. Fix pgi->d0i3 timeout in mei_me_d0i3_enter_sync()
   3.  is enough for mkhi header.
   4. drop MCHI_GROUP_ID definition it is not used
   5. Setup default PXP state
   6. Add PXP mode kdoc
   7. Add new patch mei: drop ready bits check after start
V9:
   1. Fix pgi->d0i3 timeout in mei_me_d0i3_exit_sync()
   2. Fix mismatch in the patch "mei: mkhi: add memory ready command"
   3. Use I915_BO_ALLOC_CPU_CLEAR to clear the allocated memory

Alexander Usyskin (5):
  drm/i915/gsc: add slow_firmware flag to the gsc device definition
  drm/i915/gsc: add GSC XeHP SDV platform definition
  mei: gsc: wait for reset thread on stop
  mei: extend timeouts on slow devices
  mei: drop ready bits check after start

Daniele Ceraolo Spurio (1):
  HAX: drm/i915: force INTEL_MEI_GSC on for CI

Tomas Winkler (7):
  mei: add kdoc for struct mei_aux_device
  mei: add slow_firmware flag to the mei auxiliary device
  mei: gsc: use polling instead of interrupts
  mei: mkhi: add memory ready command
  mei: gsc: setup gsc extended operational memory
  mei: debugfs: add pxp mode to devstate in debugfs
  drm/i915/gsc: allocate extended operational memory in LMEM

Vitaly Lubart (3):
  drm/i915/gsc: skip irq initialization if using polling
  mei: bus: export common mkhi definitions into a separate header
  mei: gsc: add transition to PXP mode in resume flow

 drivers/gpu/drm/i915/Kconfig.debug  |   1 +
 drivers/gpu/drm/i915/gt/intel_gsc.c | 106 +++--
 drivers/gpu/drm/i915/gt/intel_gsc.h |   3 +
 drivers/misc/mei/bus-fixup.c| 106 ++---
 drivers/misc/mei/client.c   |  16 ++--
 drivers/misc/mei/debugfs.c  |  19 +++-
 drivers/misc/mei/gsc-me.c   |  77 ++--
 drivers/misc/mei/hbm.c  |  14 +--
 drivers/misc/mei/hw-me-regs.h   |   9 +-
 drivers/misc/mei/hw-me.c| 138 
 drivers/misc/mei/hw-me.h|  17 +++-
 drivers/misc/mei/hw-txe.c   |   4 +-
 drivers/misc/mei/hw.h   |   7 +-
 drivers/misc/mei/init.c |  35 ---
 drivers/misc/mei/main.c |   4 +-
 drivers/misc/mei/mei_dev.h  |  35 ++-
 drivers/misc/mei/mkhi.h |  55 +++
 drivers/misc/mei/pci-me.c   |   4 +-
 include/linux/mei_aux.h |  12 +++
 19 files changed, 548 insertions(+), 114 deletions(-)
 create mode 100644 drivers/misc/mei/mkhi.h

-- 
2.37.2

[Intel-gfx] [PATCH v9 02/16] mei: add kdoc for struct mei_aux_device

[Tomas Winkler]

struct mei_aux_device is an interface structure
requires proper documenation.

Signed-off-by: Tomas Winkler 
Reviewed-by: Daniele Ceraolo Spurio 
---
V9: Rebase

 include/linux/mei_aux.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
index 587f25128848..a0cb587006d5 100644
--- a/include/linux/mei_aux.h
+++ b/include/linux/mei_aux.h
@@ -7,6 +7,12 @@
 
 #include 
 
+/**
+ * struct mei_aux_device - mei auxiliary device
+ * @aux_dev: - auxiliary device object
+ * @irq: interrupt driving the mei auxiliary device
+ * @bar: mmio resource bar reserved to mei auxiliary device
+ */
 struct mei_aux_device {
struct auxiliary_device aux_dev;
int irq;
-- 
2.37.2

[Intel-gfx] [PATCH v9 01/16] drm/i915/gsc: skip irq initialization if using polling

[Tomas Winkler]

From: Vitaly Lubart 

Some platforms require the host to poll on the
GSC registers instead of relaying on the interrupts.
For those platforms, irq initialization should be skipped


Signed-off-by: Vitaly Lubart 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 
Reviewed-by: Daniele Ceraolo Spurio 
---
V9: Rebase

 drivers/gpu/drm/i915/gt/intel_gsc.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c 
b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 0e494028b81d..e0236ff1d072 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -40,6 +40,7 @@ struct gsc_def {
const char *name;
unsigned long bar;
size_t bar_size;
+   bool use_polling;
 };
 
 /* gsc resources and definitions (HECI1 and HECI2) */
@@ -117,6 +118,10 @@ static void gsc_init_one(struct drm_i915_private *i915,
return;
}
 
+   /* skip irq initialization */
+   if (def->use_polling)
+   goto add_device;
+
intf->irq = irq_alloc_desc(0);
if (intf->irq < 0) {
drm_err(>drm, "gsc irq error %d\n", intf->irq);
@@ -129,6 +134,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
goto fail;
}
 
+add_device:
adev = kzalloc(sizeof(*adev), GFP_KERNEL);
if (!adev)
goto fail;
@@ -182,10 +188,8 @@ static void gsc_irq_handler(struct intel_gt *gt, unsigned 
int intf_id)
return;
}
 
-   if (gt->gsc.intf[intf_id].irq < 0) {
-   drm_err_ratelimited(>i915->drm, "GSC irq: irq not set");
+   if (gt->gsc.intf[intf_id].irq < 0)
return;
-   }
 
ret = generic_handle_irq(gt->gsc.intf[intf_id].irq);
if (ret)
-- 
2.37.2

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/dp_mst: Avoid deleting payloads for connectors staying enabled

[Patchwork]

== Series Details ==

Series: drm/dp_mst: Avoid deleting payloads for connectors staying enabled
URL   : https://patchwork.freedesktop.org/series/108250/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12088_full -> Patchwork_108250v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 11)
--

  Missing(1): shard-rkl 

New tests
-

  New tests have been introduced between CI_DRM_12088_full and 
Patchwork_108250v1_full:

### New IGT tests (2) ###

  * 
igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.14] s

  * 
igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.38] s

  

Known issues


  Here are the changes found in Patchwork_108250v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][1] -> [SKIP][2] ([i915#4525])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12088/shard-iclb1/igt@gem_exec_balan...@parallel.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108250v1/shard-iclb5/igt@gem_exec_balan...@parallel.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][3] -> [FAIL][4] ([i915#2842]) +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12088/shard-apl8/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108250v1/shard-apl8/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-glk:  [PASS][5] -> [FAIL][6] ([i915#2842])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12088/shard-glk1/igt@gem_exec_fair@basic-n...@vcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108250v1/shard-glk6/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][7] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108250v1/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@i915_suspend@forcewake:
- shard-apl:  NOTRUN -> [DMESG-WARN][8] ([i915#180])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108250v1/shard-apl8/igt@i915_susp...@forcewake.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-apl:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#3886]) +2 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108250v1/shard-apl8/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-frame-dump:
- shard-snb:  NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +1 
similar issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108250v1/shard-snb6/igt@kms_chamel...@dp-frame-dump.html

  * igt@kms_chamelium@hdmi-edid-read:
- shard-apl:  NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +1 
similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108250v1/shard-apl8/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1:
- shard-apl:  [PASS][12] -> [DMESG-WARN][13] ([i915#180]) +1 
similar issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12088/shard-apl4/igt@kms_cursor_crc@cursor-susp...@pipe-c-dp-1.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108250v1/shard-apl3/igt@kms_cursor_crc@cursor-susp...@pipe-c-dp-1.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
- shard-glk:  [PASS][14] -> [FAIL][15] ([i915#79])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12088/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vbl...@bc-hdmi-a1-hdmi-a2.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108250v1/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vbl...@bc-hdmi-a1-hdmi-a2.html

  * 
igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#2672] / [i915#3555])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108250v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscal...@pipe-a-default-mode.html

  * 
igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#2672]) +5 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108250v1/shard-iclb4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscal...@pipe-a-valid-mode.html

  * 
igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#3555])
  

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/gt: Use MEDIA_VER() when handling 
media fuses
URL   : https://patchwork.freedesktop.org/series/108269/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12090 -> Patchwork_108269v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/index.html

Participating hosts (43 -> 42)
--

  Additional (1): fi-snb-2600 
  Missing(2): fi-icl-u2 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_108269v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_rpm@module-reload:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +20 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/fi-snb-2600/igt@i915_pm_...@module-reload.html

  * igt@kms_chamelium@vga-hpd-fast:
- fi-snb-2600:NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/fi-snb-2600/igt@kms_chamel...@vga-hpd-fast.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][3] ([i915#2867]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@workarounds:
- {bat-rpls-1}:   [DMESG-FAIL][5] -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/bat-rpls-1/igt@i915_selftest@l...@workarounds.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/bat-rpls-1/igt@i915_selftest@l...@workarounds.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867


Build changes
-

  * Linux: CI_DRM_12090 -> Patchwork_108269v1

  CI-20190529: 20190529
  CI_DRM_12090: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6648: 3c9079c0b97445fbfc903b9c5a1d69707b80af80 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_108269v1: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

e0373a376ab4 drm/i915/gt: Extract function to apply media fuses
51a895dcc7ed drm/i915/gt: Use MEDIA_VER() when handling media fuses

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108269v1/index.html

[Intel-gfx] [PATCH] drm/i915: Document and future-proof preemption control policy

[Matt Roper]

Intel hardware allows some preemption settings to be controlled either
by the kernel-mode driver exclusively, or placed under control of the
user-mode drivers; on Linux we always select the userspace control
option.  The various registers involved in this are not documented very
clearly; let's add some clarifying comments to help explain how this all
works and provide some history on why our Linux drivers take the
approach they do (which I believe differs from the path taken by certain
other operating systems' drivers).

While we're at it, let's also remove the graphics version 12 upper bound
on this programming.  As described, we don't have any plans to move away
from UMD control of preemption settings on future platforms, and there's
currently no reason to believe that the hardware will fundamentally
change how these registers and settings work after version 12.

Bspec: 45921, 45858, 45863
Cc: Joonas Lahtinen 
Cc: Jordan Justen 
Cc: Lionel Landwerlin 
Suggested-by: Joonas Lahtinen 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 58 +++--
 1 file changed, 55 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6d2003d598e6..3e5a41378e81 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2389,12 +2389,64 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
 FF_DOP_CLOCK_GATE_DISABLE);
}
 
-   if (IS_GRAPHICS_VER(i915, 9, 12)) {
-   /* 
FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
+   /*
+* Intel platforms that support fine-grained preemption (i.e., gen9 and
+* beyond) allow the kernel-mode driver to choose between two different
+* options for controlling preemption granularity and behavior.
+*
+* Option 1 (hardware default):
+*   Preemption settings are controlled in a global manner via
+*   kernel-only register CS_DEBUG_MODE1 (0x20EC).  Any granularity
+*   and settings chosen by the kernel-mode driver will apply to all
+*   userspace clients.
+*
+* Option 2:
+*   Preemption settings are controlled on a per-context basis via
+*   register CS_CHICKEN1 (0x2580).  CS_CHICKEN1 is saved/restored on
+*   context switch and is writable by userspace (e.g., via
+*   MI_LOAD_REGISTER_IMMEDIATE instructions placed in a batch buffer)
+*   which allows different userspace drivers/clients to select
+*   different settings, or to change those settings on the fly in
+*   response to runtime needs.  This option was known by name
+*   "FtrPerCtxtPreemptionGranularityControl" at one time, although
+*   that name is somewhat misleading as other non-granularity
+*   preemption settings are also impacted by this decision.
+*
+* On Linux, our policy has always been to let userspace drivers
+* control preemption granularity/settings (Option 2).  This was
+* originally mandatory on gen9 to prevent ABI breakage (old gen9
+* userspace developed before object-level preemption was enabled would
+* not behave well if i915 were to go with Option 1 and enable that
+* preemption in a global manner).  On gen9 each context would have
+* object-level preemption disabled by default (see
+* WaDisable3DMidCmdPreemption in gen9_ctx_workarounds_init), but
+* userspace drivers could opt-in to object-level preemption as they
+* saw fit.  For post-gen9 platforms, we continue to utilize Option 2;
+* even though it is no longer necessary for ABI compatibility when
+* enabling a new platform, it does ensure that userspace will be able
+* to implement any workarounds that show up requiring temporary
+* adjustments to preemption behavior at runtime.
+*
+* Notes/Workarounds:
+*  - Wa_14015141709:  On DG2 and early steppings of MTL,
+*  CS_CHICKEN1[0] does not disable object-level preemption as
+*  it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been
+*  using Option 1).  Effectively this means userspace is unable
+*  to disable object-level preemption on these platforms/steppings
+*  despite the setting here.
+*
+*  - Wa_16013994831:  May require that userspace program
+*  CS_CHICKEN1[10] when certain runtime conditions are true.
+*  Userspace requires Option 2 to be in effect for their update of
+*  CS_CHICKEN1[10] to be effective.
+*
+* Other workarounds may appear in the future that will also require
+* Option 2 behavior to allow proper userspace implementation.
+*/
+   if (GRAPHICS_VER(i915) 

Re: [Intel-gfx] [PATCH v8 13/16] mei: drop ready bits check after start

[Ceraolo Spurio, Daniele]

On 9/7/2022 8:58 AM, Tomas Winkler wrote:

From: Alexander Usyskin 

The check that hardware and host ready bits are set after start
is redundant and may fail and disable driver if there is
back-to-back link reset issued right after start.
This happens during pxp mode transitions when firmware
undergo reset. Remove these checks to eliminate such failures.

Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 


Reviewed-by: Daniele Ceraolo Spurio 

Daniele


---
  drivers/misc/mei/init.c | 10 --
  1 file changed, 10 deletions(-)

diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
index 1b4d5d7870b9..bac8852aad51 100644
--- a/drivers/misc/mei/init.c
+++ b/drivers/misc/mei/init.c
@@ -218,16 +218,6 @@ int mei_start(struct mei_device *dev)
goto err;
}
  
-	if (!mei_host_is_ready(dev)) {

-   dev_err(dev->dev, "host is not ready.\n");
-   goto err;
-   }
-
-   if (!mei_hw_is_ready(dev)) {
-   dev_err(dev->dev, "ME is not ready.\n");
-   goto err;
-   }
-
if (!mei_hbm_version_is_supported(dev)) {
dev_dbg(dev->dev, "MEI start failed.\n");
goto err;

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Invert if/else ladder for frequency read

[Patchwork]

== Series Details ==

Series: drm/i915: Invert if/else ladder for frequency read
URL   : https://patchwork.freedesktop.org/series/108268/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12090 -> Patchwork_108268v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/index.html

Participating hosts (43 -> 42)
--

  Additional (1): fi-snb-2600 
  Missing(2): fi-rkl-11600 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_108268v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_rpm@module-reload:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +20 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/fi-snb-2600/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@gem:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][2] ([i915#4528])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/fi-pnv-d510/igt@i915_selftest@l...@gem.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:NOTRUN -> [INCOMPLETE][3] ([i915#3921])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_addfb_basic@addfb25-yf-tiled-legacy:
- fi-icl-u2:  [PASS][4] -> [DMESG-WARN][5] ([i915#4890])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/fi-icl-u2/igt@kms_addfb_ba...@addfb25-yf-tiled-legacy.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/fi-icl-u2/igt@kms_addfb_ba...@addfb25-yf-tiled-legacy.html

  * igt@kms_chamelium@vga-hpd-fast:
- fi-snb-2600:NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/fi-snb-2600/igt@kms_chamel...@vga-hpd-fast.html

  * igt@runner@aborted:
- fi-icl-u2:  NOTRUN -> [FAIL][7] ([i915#4312] / [i915#6599])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/fi-icl-u2/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[DMESG-FAIL][8] ([i915#4528]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@workarounds:
- {bat-rpls-1}:   [DMESG-FAIL][10] -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/bat-rpls-1/igt@i915_selftest@l...@workarounds.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/bat-rpls-1/igt@i915_selftest@l...@workarounds.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890
  [i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599


Build changes
-

  * Linux: CI_DRM_12090 -> Patchwork_108268v1

  CI-20190529: 20190529
  CI_DRM_12090: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6648: 3c9079c0b97445fbfc903b9c5a1d69707b80af80 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_108268v1: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

27d82f283738 drm/i915: Invert if/else ladder for frequency read

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108268v1/index.html

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Invert if/else ladder for frequency read

[Patchwork]

== Series Details ==

Series: drm/i915: Invert if/else ladder for frequency read
URL   : https://patchwork.freedesktop.org/series/108268/
State : warning

== Summary ==

Error: dim checkpatch failed
39d3d3166a72 drm/i915: Invert if/else ladder for frequency read
-:120: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or 
return
#120: FILE: drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c:139:
+   return f12_5_mhz;
+   } else {

total: 0 errors, 1 warnings, 0 checks, 114 lines checked

[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915/dg2: extend Wa_1409120013 to DG2"

[Patchwork]

== Series Details ==

Series: Revert "drm/i915/dg2: extend Wa_1409120013 to DG2"
URL   : https://patchwork.freedesktop.org/series/108266/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12090 -> Patchwork_108266v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v1/index.html

Participating hosts (43 -> 41)
--

  Additional (1): fi-snb-2600 
  Missing(3): fi-rkl-11600 fi-icl-u2 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_108266v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_rpm@module-reload:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +20 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v1/fi-snb-2600/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@gem:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][2] ([i915#4528])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v1/fi-pnv-d510/igt@i915_selftest@l...@gem.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [PASS][3] -> [INCOMPLETE][4] ([i915#3303] / 
[i915#4785])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@vga-hpd-fast:
- fi-snb-2600:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v1/fi-snb-2600/igt@kms_chamel...@vga-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [PASS][6] -> [FAIL][7] ([i915#6298])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html

  * igt@runner@aborted:
- fi-hsw-g3258:   NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#4312] / 
[i915#6246])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v1/fi-hsw-g3258/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][9] ([i915#2867]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[DMESG-FAIL][11] ([i915#4528]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@workarounds:
- {bat-rpls-1}:   [DMESG-FAIL][13] -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12090/bat-rpls-1/igt@i915_selftest@l...@workarounds.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108266v1/bat-rpls-1/igt@i915_selftest@l...@workarounds.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6106]: https://gitlab.freedesktop.org/drm/intel/issues/6106
  [i915#6246]: https://gitlab.freedesktop.org/drm/intel/issues/6246
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
  [i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599


Build changes
-

  * Linux: CI_DRM_12090 -> Patchwork_108266v1

  CI-20190529: 20190529
  CI_DRM_12090: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6648: 3c9079c0b97445fbfc903b9c5a1d69707b80af80 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_108266v1: 7710b0d1501fc279a2f0e8571a48500017b6a4d3 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

6355bd71d308 Revert "drm/i915/dg2: extend Wa_1409120013 to DG2"

== Logs ==

For 

Re: [Intel-gfx] [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw

[Lucas De Marchi]

On Thu, Sep 01, 2022 at 11:03:33PM -0700, Radhakrishna Sripada wrote:

From: Matt Roper 

Going forward, the hardware teams no longer consider new platforms to
have a "generation" in the way we've defined it for past platforms.
Instead, each IP block (graphics, media, display) will have their own
architecture major.minor versions and stepping ID's which should be read
directly from a register in the MMIO space.  New hardware programming
styles, features, and workarounds should be conditional solely on the
architecture version, and should no longer be derived from the PCI
device ID, revision ID, or platform-specific feature flags.

Bspec: 63361, 64111

v2:
 - Move the IP version readout to intel_device_info.c
 - Convert the macro into a function

v3:
 - Move subplatform init to runtime early init
 - Cache runtime ver, release info to compare with hardware values.

Signed-off-by: Matt Roper 
Signed-off-by: Rodrigo Vivi 
Signed-off-by: Radhakrishna Sripada 
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h  |  2 +
drivers/gpu/drm/i915/i915_driver.c   |  3 +-
drivers/gpu/drm/i915/i915_drv.h  |  2 +
drivers/gpu/drm/i915/i915_pci.c  |  1 +
drivers/gpu/drm/i915/i915_reg.h  |  7 +++
drivers/gpu/drm/i915/intel_device_info.c | 74 +++-
drivers/gpu/drm/i915/intel_device_info.h | 12 +++-
7 files changed, 98 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index d414785003cc..579da62158c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -39,6 +39,8 @@
#define FORCEWAKE_ACK_RENDER_GEN9   _MMIO(0xd84)
#define FORCEWAKE_ACK_MEDIA_GEN9_MMIO(0xd88)

+#define GMD_ID_GRAPHICS_MMIO(0xd8c)
+
#define MCFG_MCR_SELECTOR   _MMIO(0xfd0)
#define SF_MCR_SELECTOR _MMIO(0xfd8)
#define GEN8_MCR_SELECTOR   _MMIO(0xfdc)
diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index 56a2bcddb2af..a1ab49521d19 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -323,7 +323,8 @@ static int i915_driver_early_probe(struct drm_i915_private 
*dev_priv)
if (i915_inject_probe_failure(dev_priv))
return -ENODEV;

-   intel_device_info_subplatform_init(dev_priv);
+   intel_device_info_runtime_init_early(dev_priv);
+
intel_step_init(dev_priv);

intel_uncore_mmio_debug_init_early(_priv->mmio_debug);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f85a470397a5..405b59b8c05c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -936,6 +936,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,

#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)

+#define HAS_GMD_ID(i915)   INTEL_INFO(i915)->has_gmd_id
+
#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))

#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f6aaf938c53c..4672894f4bc1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1129,6 +1129,7 @@ static const struct intel_device_info mtl_info = {
PLATFORM(INTEL_METEORLAKE),
.display.has_modular_fia = 1,
.has_flat_ccs = 0,
+   .has_gmd_id = 1,
.has_snoop = 1,
.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e6239864c35..e02e461a4b5d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5798,6 +5798,11 @@
#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz   (1 << 29)
#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz   (2 << 29)

+#define GMD_ID_DISPLAY _MMIO(0x510a0)
+#define   GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
+#define   GMD_ID_RELEASE_MASK  REG_GENMASK(21, 14)
+#define   GMD_ID_STEP  REG_GENMASK(5, 0)
+
/*GEN11 chicken */
#define _PIPEA_CHICKEN  0x70038
#define _PIPEB_CHICKEN  0x71038
@@ -8298,4 +8303,6 @@ enum skl_power_gate {
#define  MTL_LATENCY_LEVEL_EVEN_MASKREG_GENMASK(12, 0)
#define  MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)

+#define MTL_MEDIA_GSI_BASE 0x38
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 56f19683dd55..a5bafc9be1fa 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -29,6 +29,7 @@

#include "display/intel_cdclk.h"
#include "display/intel_de.h"
+#include 

[Intel-gfx] [PATCH 2/2] drm/i915/gt: Extract function to apply media fuses

[Lucas De Marchi]

Just like is done for compute and copy engines, extract a function to
handle media engines. While at it, be consistent on using or not the
uncore/gt/info variable aliases.

Cc: Matt Roper 
Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 136 --
 1 file changed, 72 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 5cddee7c2f1d..5b9dfa0cd467 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -665,6 +665,74 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
return false;
 }
 
+static void engine_mask_apply_media_fuses(struct intel_gt *gt)
+{
+   struct drm_i915_private *i915 = gt->i915;
+   unsigned int logical_vdbox = 0;
+   unsigned int i;
+   u32 media_fuse, fuse1;
+   u16 vdbox_mask;
+   u16 vebox_mask;
+
+   if (MEDIA_VER(gt->i915) < 11)
+   return;
+
+   /*
+* On newer platforms the fusing register is called 'enable' and has
+* enable semantics, while on older platforms it is called 'disable'
+* and bits have disable semantices.
+*/
+   media_fuse = intel_uncore_read(gt->uncore, 
GEN11_GT_VEBOX_VDBOX_DISABLE);
+   if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
+   media_fuse = ~media_fuse;
+
+   vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
+   vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
+ GEN11_GT_VEBOX_DISABLE_SHIFT;
+
+   if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
+   fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
+   gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
+   } else {
+   gt->info.sfc_mask = ~0;
+   }
+
+   for (i = 0; i < I915_MAX_VCS; i++) {
+   if (!HAS_ENGINE(gt, _VCS(i))) {
+   vdbox_mask &= ~BIT(i);
+   continue;
+   }
+
+   if (!(BIT(i) & vdbox_mask)) {
+   gt->info.engine_mask &= ~BIT(_VCS(i));
+   drm_dbg(>drm, "vcs%u fused off\n", i);
+   continue;
+   }
+
+   if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
+   gt->info.vdbox_sfc_access |= BIT(i);
+   logical_vdbox++;
+   }
+   drm_dbg(>drm, "vdbox enable: %04x, instances: %04lx\n",
+   vdbox_mask, VDBOX_MASK(gt));
+   GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
+
+   for (i = 0; i < I915_MAX_VECS; i++) {
+   if (!HAS_ENGINE(gt, _VECS(i))) {
+   vebox_mask &= ~BIT(i);
+   continue;
+   }
+
+   if (!(BIT(i) & vebox_mask)) {
+   gt->info.engine_mask &= ~BIT(_VECS(i));
+   drm_dbg(>drm, "vecs%u fused off\n", i);
+   }
+   }
+   drm_dbg(>drm, "vebox enable: %04x, instances: %04lx\n",
+   vebox_mask, VEBOX_MASK(gt));
+   GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
+}
+
 static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
 {
struct drm_i915_private *i915 = gt->i915;
@@ -673,6 +741,9 @@ static void engine_mask_apply_compute_fuses(struct intel_gt 
*gt)
unsigned long ccs_mask;
unsigned int i;
 
+   if (GRAPHICS_VER(i915) < 11)
+   return;
+
if (hweight32(CCS_MASK(gt)) <= 1)
return;
 
@@ -730,73 +801,10 @@ static intel_engine_mask_t init_engine_mask(struct 
intel_gt *gt)
 {
struct drm_i915_private *i915 = gt->i915;
struct intel_gt_info *info = >info;
-   struct intel_uncore *uncore = gt->uncore;
-   unsigned int logical_vdbox = 0;
-   unsigned int i;
-   u32 media_fuse, fuse1;
-   u16 vdbox_mask;
-   u16 vebox_mask;
 
info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
 
-   if (GRAPHICS_VER(i915) < 11)
-   return info->engine_mask;
-
-   /*
-* On newer platforms the fusing register is called 'enable' and has
-* enable semantics, while on older platforms it is called 'disable'
-* and bits have disable semantices.
-*/
-   media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
-   if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
-   media_fuse = ~media_fuse;
-
-   vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
-   vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
- GEN11_GT_VEBOX_DISABLE_SHIFT;
-
-   if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
-   fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
-   gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
-   } else {
-   gt->info.sfc_mask = ~0;
-   }
-
-   for (i = 0; i < I915_MAX_VCS; 

[Intel-gfx] [PATCH 1/2] drm/i915/gt: Use MEDIA_VER() when handling media fuses

[Lucas De Marchi]

Check for media IP version instead of graphics since this is figuring
out the media engines' configuration. Currently the only platform with
non-matching graphics/media version is Meteor Lake: update the check in
gen11_vdbox_has_sfc() so it considers not only version 12, but also any
later version which then includes that platform.

Cc: Matt Roper 
Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 275ad72940c1..5cddee7c2f1d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -654,13 +654,14 @@ bool gen11_vdbox_has_sfc(struct intel_gt *gt,
 */
if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
return false;
-   else if (GRAPHICS_VER(i915) == 12)
+   else if (MEDIA_VER(i915) >= 12)
return (physical_vdbox % 2 == 0) ||
!(BIT(physical_vdbox - 1) & vdbox_mask);
-   else if (GRAPHICS_VER(i915) == 11)
+   else if (MEDIA_VER(i915) == 11)
return logical_vdbox % 2 == 0;
 
-   MISSING_CASE(GRAPHICS_VER(i915));
+   MISSING_CASE(MEDIA_VER(i915));
+
return false;
 }
 
@@ -747,14 +748,14 @@ static intel_engine_mask_t init_engine_mask(struct 
intel_gt *gt)
 * and bits have disable semantices.
 */
media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
-   if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+   if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
media_fuse = ~media_fuse;
 
vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
  GEN11_GT_VEBOX_DISABLE_SHIFT;
 
-   if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+   if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
} else {
-- 
2.37.2

[Intel-gfx] [PATCH] drm/i915: Invert if/else ladder for frequency read

[Lucas De Marchi]

Continue converting the driver to the convention of last version first,
extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
be handled by the first branch.

With the new ranges it's easier to see what platform a branch started to
be taken. Besides the >= 11 change, the branch taken for GRAPHICS_VER == 10
is also different, but currently there is no such platform in i915.

Cc: Matt Roper 
Signed-off-by: Lucas De Marchi 
---
 .../gpu/drm/i915/gt/intel_gt_clock_utils.c| 77 +--
 1 file changed, 37 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c 
b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index d5d1b04dbcad..93608c9349fd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -78,77 +78,74 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
u32 f19_2_mhz = 1920;
u32 f24_mhz = 2400;
 
-   if (GRAPHICS_VER(uncore->i915) <= 4) {
-   /*
-* PRMs say:
-*
-* "The value in this register increments once every 16
-*  hclks." (through the “Clocking Configuration”
-*  (“CLKCFG”) MCHBAR register)
-*/
-   return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
-   } else if (GRAPHICS_VER(uncore->i915) <= 8) {
-   /*
-* PRMs say:
-*
-* "The PCU TSC counts 10ns increments; this timestamp
-*  reflects bits 38:3 of the TSC (i.e. 80ns granularity,
-*  rolling over every 1.5 hours).
-*/
-   return f12_5_mhz;
-   } else if (GRAPHICS_VER(uncore->i915) <= 9) {
+   if (GRAPHICS_VER(uncore->i915) >= 11) {
u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
u32 freq = 0;
 
+   /*
+* First figure out the reference frequency. There are 2 ways
+* we can compute the frequency, either through the
+* TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
+* tells us which one we should use.
+*/
if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == 
CTC_SOURCE_DIVIDE_LOGIC) {
freq = read_reference_ts_freq(uncore);
} else {
-   freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
+   u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
+
+   if (GRAPHICS_VER(uncore->i915) >= 11)
+   freq = gen11_get_crystal_clock_freq(uncore, c0);
+   else
+   freq = gen9_get_crystal_clock_freq(uncore, c0);
 
/*
 * Now figure out how the command stream's timestamp
 * register increments from this frequency (it might
 * increment only every few clock cycle).
 */
-   freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
- CTC_SHIFT_PARAMETER_SHIFT);
+   freq >>= 3 - ((c0 & 
GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
+ 
GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
}
 
return freq;
-   } else if (GRAPHICS_VER(uncore->i915) <= 12) {
+   } else if (GRAPHICS_VER(uncore->i915) >= 9) {
u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
u32 freq = 0;
 
-   /*
-* First figure out the reference frequency. There are 2 ways
-* we can compute the frequency, either through the
-* TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
-* tells us which one we should use.
-*/
if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == 
CTC_SOURCE_DIVIDE_LOGIC) {
freq = read_reference_ts_freq(uncore);
} else {
-   u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
-
-   if (GRAPHICS_VER(uncore->i915) >= 11)
-   freq = gen11_get_crystal_clock_freq(uncore, c0);
-   else
-   freq = gen9_get_crystal_clock_freq(uncore, c0);
+   freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
 
/*
 * Now figure out how the command stream's timestamp
 * register increments from this frequency (it might
 * increment only every few clock cycle).
 */
-   freq >>= 3 - ((c0 & 
GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
-   

[Intel-gfx] [PATCH] Revert "drm/i915/dg2: extend Wa_1409120013 to DG2"

[Lucas De Marchi]

This reverts commit 487970e8bb776c989013bb59d6cbb22e45b9afc6.

Updated bspec and workaround database note Wa_1409120013 is not needed
for DG2 (or any Display 13) platform.

Cc: Matt Roper 
Cc: Matt Atwood 
Cc: Clint Taylor 
Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 210c1f78cc90..6ff0b80e69ac 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7614,9 +7614,9 @@ static void icl_init_clock_gating(struct drm_i915_private 
*dev_priv)
 
 static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-   /* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */
+   /* Wa_1409120013:tgl,rkl,adl-s,dg1 */
if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
-   IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))
+   IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv))
intel_uncore_write(_priv->uncore, 
ILK_DPFC_CHICKEN(INTEL_FBC_A),
   DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
-- 
2.37.2

Re: [Intel-gfx] [PATCH] drm/i915: Set correct domains values at _i915_vma_move_to_active

[Andrzej Hajda]

On 07.09.2022 19:26, Nirmoy Das wrote:

Fix regression introduced by commit:
"drm/i915: Individualize fences before adding to dma_resv obj"
which sets obj->read_domains to 0 for both read and write paths.
Also set obj->write_domain to 0 on read path which was removed by
the commit.

References: https://gitlab.freedesktop.org/drm/intel/-/issues/6639
Fixes: 842d9346b2fd ("drm/i915: Individualize fences before adding to dma_resv 
obj")
Signed-off-by: Nirmoy Das 
Cc:  # v5.16+
Cc: Matthew Auld 
Cc: Andrzej Hajda 


Reviewed-by: Andrzej Hajda 

Regards
Andrzej

---
  drivers/gpu/drm/i915/i915_vma.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 260371716490..373582cfd8f3 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1882,12 +1882,13 @@ int _i915_vma_move_to_active(struct i915_vma *vma,
enum dma_resv_usage usage;
int idx;
  
-		obj->read_domains = 0;

if (flags & EXEC_OBJECT_WRITE) {
usage = DMA_RESV_USAGE_WRITE;
obj->write_domain = I915_GEM_DOMAIN_RENDER;
+   obj->read_domains = 0;
} else {
usage = DMA_RESV_USAGE_READ;
+   obj->write_domain = 0;
}
  
  		dma_fence_array_for_each(curr, idx, fence)

Re: [Intel-gfx] [PATCH v8 09/16] mei: bus: export common mkhi definitions into a separate header

[Winkler, Tomas]

> 
> 
> 
> On 9/7/2022 8:58 AM, Tomas Winkler wrote:
> > From: Vitaly Lubart 
> >
> > Exported common mkhi definitions from bus-fixup.c into a separate
> > header file mkhi.h for other driver usage.
> >
> > Signed-off-by: Vitaly Lubart 
> > Signed-off-by: Tomas Winkler 
> > Signed-off-by: Alexander Usyskin 
> > ---
> >   drivers/misc/mei/bus-fixup.c | 31 +---
> >   drivers/misc/mei/mkhi.h  | 57
> 
> >   2 files changed, 58 insertions(+), 30 deletions(-)
> >   create mode 100644 drivers/misc/mei/mkhi.h
> >
> > diff --git a/drivers/misc/mei/bus-fixup.c
> > b/drivers/misc/mei/bus-fixup.c index 344598fcf8e9..c4e527803299 100644
> > --- a/drivers/misc/mei/bus-fixup.c
> > +++ b/drivers/misc/mei/bus-fixup.c
> > @@ -15,6 +15,7 @@
> >
> >   #include "mei_dev.h"
> >   #include "client.h"
> > +#include "mkhi.h"
> >
> >   #define MEI_UUID_NFC_INFO UUID_LE(0xd2de1625, 0x382d, 0x417d, \
> > 0x48, 0xa4, 0xef, 0xab, 0xba, 0x8a, 0x12, 0x06) @@ -
> 89,20 +90,6
> > @@ struct mei_os_ver {
> > u8  reserved2;
> >   } __packed;
> >
> > -#define MKHI_FEATURE_PTT 0x10
> > -
> > -struct mkhi_rule_id {
> > -   __le16 rule_type;
> > -   u8 feature_id;
> > -   u8 reserved;
> > -} __packed;
> > -
> > -struct mkhi_fwcaps {
> > -   struct mkhi_rule_id id;
> > -   u8 len;
> > -   u8 data[];
> > -} __packed;
> > -
> >   struct mkhi_fw_ver_block {
> > u16 minor;
> > u8 major;
> > @@ -115,22 +102,6 @@ struct mkhi_fw_ver {
> > struct mkhi_fw_ver_block ver[MEI_MAX_FW_VER_BLOCKS];
> >   } __packed;
> >
> > -#define MKHI_FWCAPS_GROUP_ID 0x3
> > -#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6 -#define
> > MKHI_GEN_GROUP_ID 0xFF -#define
> MKHI_GEN_GET_FW_VERSION_CMD 0x2
> > -struct mkhi_msg_hdr {
> > -   u8  group_id;
> > -   u8  command;
> > -   u8  reserved;
> > -   u8  result;
> > -} __packed;
> > -
> > -struct mkhi_msg {
> > -   struct mkhi_msg_hdr hdr;
> > -   u8 data[];
> > -} __packed;
> > -
> >   #define MKHI_OSVER_BUF_LEN (sizeof(struct mkhi_msg_hdr) + \
> > sizeof(struct mkhi_fwcaps) + \
> > sizeof(struct mei_os_ver))
> > diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h new
> > file mode 100644 index ..43cadfb1b990
> > --- /dev/null
> > +++ b/drivers/misc/mei/mkhi.h
> > @@ -0,0 +1,57 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
> > + * Intel Management Engine Interface (Intel MEI) Linux driver  */
> > +
> > +#ifndef _MEI_MKHI_H_
> > +#define _MEI_MKHI_H_
> > +
> > +#include 
> > +
> > +#define MKHI_FEATURE_PTT 0x10
> > +
> > +#define MKHI_FWCAPS_GROUP_ID 0x3
> > +#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6 #define
> > +MKHI_GEN_GROUP_ID 0xFF #define
> MKHI_GEN_GET_FW_VERSION_CMD 0x2
> > +
> > +#define MKHI_GROUP_ID_GFX  0x30
> > +#define MKHI_GFX_RESET_WARN_CMD_REQ0x0
> > +#define MKHI_GFX_MEMORY_READY_CMD_REQ  0x1
> > +
> > +/* Allow transition to PXP mode without approval */ #define
> > +MKHI_GFX_MEM_READY_PXP_ALLOWED  0x1
> > +
> > +#define MKHI_GROUP_ID_GFX  0x30
> > +#define MKHI_GFX_RESET_WARN_CMD_REQ0x0
> > +#define MKHI_GFX_MEMORY_READY_CMD_REQ  0x1
> > +
> > +/* Allow transition to PXP mode without approval */ #define
> > +MKHI_GFX_MEM_READY_PXP_ALLOWED  0x1
> 
> Something weird is happening here. Those defs were added by the next
> patch in the previous rev, while now they're added here twice and then still
> added once more in the next patch, so they're defined 3 times. IMO leaving
> it to the next patch is better, so they should just be dropped from this one.

You are right, bad --amend :(
> 
> Daniele
> 
> > +
> > +struct mkhi_rule_id {
> > +   __le16 rule_type;
> > +   u8 feature_id;
> > +   u8 reserved;
> > +} __packed;
> > +
> > +struct mkhi_fwcaps {
> > +   struct mkhi_rule_id id;
> > +   u8 len;
> > +   u8 data[];
> > +} __packed;
> > +
> > +struct mkhi_msg_hdr {
> > +   u8  group_id;
> > +   u8  command;
> > +   u8  reserved;
> > +   u8  result;
> > +} __packed;
> > +
> > +struct mkhi_msg {
> > +   struct mkhi_msg_hdr hdr;
> > +   u8 data[];
> > +} __packed;
> > +
> > +#endif /* _MEI_MKHI_H_ */

Re: [Intel-gfx] [PATCH v2 14/15] vfio: Rename vfio_device_put() and vfio_device_try_get()

[Eric Auger]

On 9/1/22 16:37, Kevin Tian wrote:
> With the addition of vfio_put_device() now the names become confusing.
>
> vfio_put_device() is clear from object life cycle p.o.v given kref.
>
> vfio_device_put()/vfio_device_try_get() are helpers for tracking
> users on a registered device.
>
> Now rename them:
>
>  - vfio_device_put() -> vfio_device_put_registration()
>  - vfio_device_try_get() -> vfio_device_try_get_registration()
>
> Signed-off-by: Kevin Tian 
> Reviewed-by: Jason Gunthorpe 
Reviewed-by: Eric Auger 

Eric
> ---
>  drivers/vfio/vfio_main.c | 17 +
>  1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
> index 957d9f286550..bfa675d314ab 100644
> --- a/drivers/vfio/vfio_main.c
> +++ b/drivers/vfio/vfio_main.c
> @@ -451,13 +451,13 @@ static void vfio_group_get(struct vfio_group *group)
>   * Device objects - create, release, get, put, search
>   */
>  /* Device reference always implies a group reference */
> -static void vfio_device_put(struct vfio_device *device)
> +static void vfio_device_put_registration(struct vfio_device *device)
>  {
>   if (refcount_dec_and_test(>refcount))
>   complete(>comp);
>  }
>  
> -static bool vfio_device_try_get(struct vfio_device *device)
> +static bool vfio_device_try_get_registration(struct vfio_device *device)
>  {
>   return refcount_inc_not_zero(>refcount);
>  }
> @@ -469,7 +469,8 @@ static struct vfio_device *vfio_group_get_device(struct 
> vfio_group *group,
>  
>   mutex_lock(>device_lock);
>   list_for_each_entry(device, >device_list, group_next) {
> - if (device->dev == dev && vfio_device_try_get(device)) {
> + if (device->dev == dev &&
> + vfio_device_try_get_registration(device)) {
>   mutex_unlock(>device_lock);
>   return device;
>   }
> @@ -671,7 +672,7 @@ static int __vfio_register_dev(struct vfio_device *device,
>   if (existing_device) {
>   dev_WARN(device->dev, "Device already exists on group %d\n",
>iommu_group_id(group->iommu_group));
> - vfio_device_put(existing_device);
> + vfio_device_put_registration(existing_device);
>   if (group->type == VFIO_NO_IOMMU ||
>   group->type == VFIO_EMULATED_IOMMU)
>   iommu_group_remove_device(device->dev);
> @@ -730,7 +731,7 @@ static struct vfio_device 
> *vfio_device_get_from_name(struct vfio_group *group,
>   ret = !strcmp(dev_name(it->dev), buf);
>   }
>  
> - if (ret && vfio_device_try_get(it)) {
> + if (ret && vfio_device_try_get_registration(it)) {
>   device = it;
>   break;
>   }
> @@ -750,7 +751,7 @@ void vfio_unregister_group_dev(struct vfio_device *device)
>   bool interrupted = false;
>   long rc;
>  
> - vfio_device_put(device);
> + vfio_device_put_registration(device);
>   rc = try_wait_for_completion(>comp);
>   while (rc <= 0) {
>   if (device->ops->request)
> @@ -1286,7 +1287,7 @@ static int vfio_group_get_device_fd(struct vfio_group 
> *group, char *buf)
>  err_put_fdno:
>   put_unused_fd(fdno);
>  err_put_device:
> - vfio_device_put(device);
> + vfio_device_put_registration(device);
>   return ret;
>  }
>  
> @@ -1461,7 +1462,7 @@ static int vfio_device_fops_release(struct inode 
> *inode, struct file *filep)
>  
>   vfio_device_unassign_container(device);
>  
> - vfio_device_put(device);
> + vfio_device_put_registration(device);
>  
>   return 0;
>  }

Re: [Intel-gfx] [PATCH v2 12/15] vfio/amba: Use the new device life cycle helpers

[Eric Auger]

Hi Kevin,

On 9/1/22 16:37, Kevin Tian wrote:
> Implement amba's own vfio_device_ops.
>
> Remove vfio_platform_probe/remove_common() given no user now.
>
> Signed-off-by: Kevin Tian 
> Reviewed-by: Jason Gunthorpe 
> ---
>  drivers/vfio/platform/vfio_amba.c | 72 ++-
>  drivers/vfio/platform/vfio_platform_common.c  | 60 
>  drivers/vfio/platform/vfio_platform_private.h |  3 -
>  3 files changed, 55 insertions(+), 80 deletions(-)
>
> diff --git a/drivers/vfio/platform/vfio_amba.c 
> b/drivers/vfio/platform/vfio_amba.c
> index 1aaa4f721bd2..6cdcc8905198 100644
> --- a/drivers/vfio/platform/vfio_amba.c
> +++ b/drivers/vfio/platform/vfio_amba.c
> @@ -7,6 +7,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  
>  #include "vfio_platform_private.h"
> @@ -40,20 +41,16 @@ static int get_amba_irq(struct vfio_platform_device 
> *vdev, int i)
>   return ret ? ret : -ENXIO;
>  }
>  
> -static int vfio_amba_probe(struct amba_device *adev, const struct amba_id 
> *id)
> +static int vfio_amba_init_dev(struct vfio_device *core_vdev)
>  {
> - struct vfio_platform_device *vdev;
> + struct vfio_platform_device *vdev =
> + container_of(core_vdev, struct vfio_platform_device, vdev);
> + struct amba_device *adev = to_amba_device(core_vdev->dev);
>   int ret;
>  
> - vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
> - if (!vdev)
> - return -ENOMEM;
> -
>   vdev->name = kasprintf(GFP_KERNEL, "vfio-amba-%08x", adev->periphid);
> - if (!vdev->name) {
> - kfree(vdev);
> + if (!vdev->name)
>   return -ENOMEM;
> - }
>  
>   vdev->opaque = (void *) adev;
>   vdev->flags = VFIO_DEVICE_FLAGS_AMBA;
> @@ -61,26 +58,67 @@ static int vfio_amba_probe(struct amba_device *adev, 
> const struct amba_id *id)
>   vdev->get_irq = get_amba_irq;
>   vdev->reset_required = false;
>  
> - ret = vfio_platform_probe_common(vdev, >dev);
> - if (ret) {
> + ret = vfio_platform_init_common(vdev);
> + if (ret)
>   kfree(vdev->name);
> - kfree(vdev);
> - return ret;
> - }
> + return ret;
> +}
> +
> +static const struct vfio_device_ops vfio_amba_ops;
> +static int vfio_amba_probe(struct amba_device *adev, const struct amba_id 
> *id)
> +{
> + struct vfio_platform_device *vdev;
> + int ret;
> +
> + vdev = vfio_alloc_device(vfio_platform_device, vdev, >dev,
> +  _amba_ops);
> + if (IS_ERR(vdev))
> + return PTR_ERR(vdev);
>  
> + ret = vfio_register_group_dev(>vdev);
> + if (ret)
> + goto out_put_vdev;
> +
> + pm_runtime_enable(>dev);
>   dev_set_drvdata(>dev, vdev);
>   return 0;
> +
> +out_put_vdev:
> + vfio_put_device(>vdev);
> + return ret;
> +}
> +
> +static void vfio_amba_release_dev(struct vfio_device *core_vdev)
> +{
> + struct vfio_platform_device *vdev =
> + container_of(core_vdev, struct vfio_platform_device, vdev);
> +
> + vfio_platform_release_common(vdev);
> + kfree(vdev->name);
> + vfio_free_device(core_vdev);
>  }
>  
>  static void vfio_amba_remove(struct amba_device *adev)
>  {
>   struct vfio_platform_device *vdev = dev_get_drvdata(>dev);
>  
> - vfio_platform_remove_common(vdev);
> - kfree(vdev->name);
> - kfree(vdev);
> + vfio_unregister_group_dev(>vdev);
> + pm_runtime_disable(vdev->device);
> + vfio_put_device(>vdev);
>  }
>  
> +static const struct vfio_device_ops vfio_amba_ops= {
> + .name   = "vfio-amba",
> + .init   = vfio_amba_init_dev,
> + .release= vfio_amba_release_dev,
> + .open_device= vfio_platform_open_device,
> + .close_device   = vfio_platform_close_device,
> + .ioctl  = vfio_platform_ioctl,
> + .read   = vfio_platform_read,
> + .write  = vfio_platform_write,
> + .mmap   = vfio_platform_mmap,
> +};
> +
>  static const struct amba_id pl330_ids[] = {
>   { 0, 0 },
>  };
> diff --git a/drivers/vfio/platform/vfio_platform_common.c 
> b/drivers/vfio/platform/vfio_platform_common.c
> index 4c01bf0adebb..55dc4f43c31e 100644
> --- a/drivers/vfio/platform/vfio_platform_common.c
> +++ b/drivers/vfio/platform/vfio_platform_common.c
> @@ -605,16 +605,6 @@ int vfio_platform_mmap(struct vfio_device *core_vdev, 
> struct vm_area_struct *vma
>  }
>  EXPORT_SYMBOL_GPL(vfio_platform_mmap);
>  
> -static const struct vfio_device_ops vfio_platform_ops = {
> - .name   = "vfio-platform",
> - .open_device= vfio_platform_open_device,
> - .close_device   = vfio_platform_close_device,
> - .ioctl  = vfio_platform_ioctl,
> - .read   = vfio_platform_read,
> - .write  = vfio_platform_write,
> - .mmap   = vfio_platform_mmap,
> -};
> -
>  static int vfio_platform_of_probe(struct vfio_platform_device *vdev,
>   

Re: [Intel-gfx] [PATCH v2 01/15] vfio: Add helpers for unifying vfio_device life cycle

[Eric Auger]

Hi Kevin,
On 9/1/22 16:37, Kevin Tian wrote:
> The idea is to let vfio core manage the vfio_device life cycle instead
> of duplicating the logic cross drivers. This is also a preparatory
> step for adding struct device into vfio_device.
>
> New pair of helpers together with a kref in vfio_device:
>
>  - vfio_alloc_device()
>  - vfio_put_device()
>
> Drivers can register @init/@release callbacks to manage any priviate
private
> state wrapping the vfio_device.
>
> However vfio-ccw doesn't fit this model due to a life cycle mess
> that its private structure mixes both parent and mdev info hence must
> be allocated/freed outside of the life cycle of vfio device.
>
> Per prior discussions this won't be fixed in short term by IBM folks.
>
> Instead of waiting introduce another helper vfio_init_device() so ccw
s/waiting/waiting for those modifications,
> can call it to initialize a pre-allocated vfio_device.
>
> Further implication of the ccw trick is that vfio_device cannot be
> freed uniformly in vfio core. Instead, require *EVERY* driver to
> implement @release and free vfio_device inside. Then ccw can choose
> to delay the free at its own discretion.
>
> Another trick down the road is that kvzalloc() is used to accommodate
> the need of gvt which uses vzalloc() while all others use kzalloc().
> So drivers should call a helper vfio_free_device() to free the
> vfio_device instead of assuming that kfree() or vfree() is appliable.
>
> Later once the ccw mess is fixed we can remove those tricks and
> fully handle structure alloc/free in vfio core.
>
> Existing vfio_{un}init_group_dev() will be deprecated after all
> existing usages are converted to the new model.
>
> Suggested-by: Jason Gunthorpe 
> Co-developed-by: Yi Liu 
> Signed-off-by: Yi Liu 
> Signed-off-by: Kevin Tian 
> Reviewed-by: Tony Krowiak 
> Reviewed-by: Jason Gunthorpe 
> ---
>  drivers/vfio/vfio_main.c | 92 
>  include/linux/vfio.h | 25 ++-
>  2 files changed, 116 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
> index 7cb56c382c97..c9d982131265 100644
> --- a/drivers/vfio/vfio_main.c
> +++ b/drivers/vfio/vfio_main.c
> @@ -496,6 +496,98 @@ void vfio_uninit_group_dev(struct vfio_device *device)
>  }
>  EXPORT_SYMBOL_GPL(vfio_uninit_group_dev);
>  
> +/* Release helper called by vfio_put_device() */
> +void vfio_device_release(struct kref *kref)
> +{
> + struct vfio_device *device =
> + container_of(kref, struct vfio_device, kref);
> +
> + vfio_uninit_group_dev(device);
> +
> + /*
> +  * kvfree() cannot be done here due to a life cycle mess in
> +  * vfio-ccw. Before the ccw part is fixed all drivers are
> +  * required to support @release and call vfio_free_device()
> +  * from there.
> +  */
> + device->ops->release(device);
> +}
> +EXPORT_SYMBOL_GPL(vfio_device_release);
> +
> +/*
> + * Alloc and initialize vfio_device so it can be registered to vfio
> + * core.
> + *
> + * Drivers should use the wrapper vfio_alloc_device() for allocation.
> + * @size is the size of the structure to be allocated, including any
> + * private data used by the driver.
> + *
> + * Driver may provide an @init callback to cover device private data.
nit: this comment may rather relate to the vfio_init_device function
> + *
> + * Use vfio_put_device() to release the structure after success return.
> + */
> +struct vfio_device *_vfio_alloc_device(size_t size, struct device *dev,
> +const struct vfio_device_ops *ops)
> +{
> + struct vfio_device *device;
> + int ret;
> +
> + if (WARN_ON(size < sizeof(struct vfio_device)))
> + return ERR_PTR(-EINVAL);
> +
> + device = kvzalloc(size, GFP_KERNEL);
> + if (!device)
> + return ERR_PTR(-ENOMEM);
> +
> + ret = vfio_init_device(device, dev, ops);
> + if (ret)
> + goto out_free;
> + return device;
> +
> +out_free:
> + kvfree(device);
> + return ERR_PTR(ret);
> +}
> +EXPORT_SYMBOL_GPL(_vfio_alloc_device);
> +
> +/*
> + * Initialize a vfio_device so it can be registered to vfio core.
> + *
> + * Only vfio-ccw driver should call this interface.
> + */
> +int vfio_init_device(struct vfio_device *device, struct device *dev,
> +  const struct vfio_device_ops *ops)
> +{
> + int ret;
> +
> + vfio_init_group_dev(device, dev, ops);
> +
> + if (ops->init) {
> + ret = ops->init(device);
> + if (ret)
> + goto out_uninit;
> + }
> +
> + kref_init(>kref);
> + return 0;
> +
> +out_uninit:
> + vfio_uninit_group_dev(device);
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(vfio_init_device);
> +
> +/*
> + * The helper called by driver @release callback to free the device
> + * structure. Drivers which don't have private data to clean can
> + * simply use this helper as its @release.
> + */
> +void 

Re: [Intel-gfx] [PATCH v2 11/15] vfio/platform: Use the new device life cycle helpers

[Eric Auger]

Hi kevin,

On 9/1/22 16:37, Kevin Tian wrote:
> Move vfio_device_ops from platform core to platform drivers so device
> specific init/cleanup can be added.
>
> Introduce two new helpers vfio_platform_init/release_common() for the
> use in driver @init/@release.
>
> vfio_platform_probe/remove_common() will be deprecated.
>
> Signed-off-by: Kevin Tian 
> Reviewed-by: Jason Gunthorpe 
> ---
>  drivers/vfio/platform/vfio_platform.c | 66 +++
>  drivers/vfio/platform/vfio_platform_common.c  | 53 ---
>  drivers/vfio/platform/vfio_platform_private.h | 15 +
>  3 files changed, 111 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/vfio/platform/vfio_platform.c 
> b/drivers/vfio/platform/vfio_platform.c
> index 04f40c5acfd6..82cedcebfd90 100644
> --- a/drivers/vfio/platform/vfio_platform.c
> +++ b/drivers/vfio/platform/vfio_platform.c
> @@ -7,6 +7,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  
>  #include "vfio_platform_private.h"
> @@ -36,14 +37,11 @@ static int get_platform_irq(struct vfio_platform_device 
> *vdev, int i)
>   return platform_get_irq_optional(pdev, i);
>  }
>  
> -static int vfio_platform_probe(struct platform_device *pdev)
> +static int vfio_platform_init_dev(struct vfio_device *core_vdev)
>  {
> - struct vfio_platform_device *vdev;
> - int ret;
> -
> - vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
> - if (!vdev)
> - return -ENOMEM;
> + struct vfio_platform_device *vdev =
> + container_of(core_vdev, struct vfio_platform_device, vdev);
> + struct platform_device *pdev = to_platform_device(core_vdev->dev);
>  
>   vdev->opaque = (void *) pdev;
>   vdev->name = pdev->name;
> @@ -52,24 +50,64 @@ static int vfio_platform_probe(struct platform_device 
> *pdev)
>   vdev->get_irq = get_platform_irq;
>   vdev->reset_required = reset_required;
>  
> - ret = vfio_platform_probe_common(vdev, >dev);
> - if (ret) {
> - kfree(vdev);
> - return ret;
> - }
> + return vfio_platform_init_common(vdev);
> +}
> +
> +static const struct vfio_device_ops vfio_platform_ops;
> +static int vfio_platform_probe(struct platform_device *pdev)
> +{
> + struct vfio_platform_device *vdev;
> + int ret;
> +
> + vdev = vfio_alloc_device(vfio_platform_device, vdev, >dev,
> +  _platform_ops);
> + if (IS_ERR(vdev))
> + return PTR_ERR(vdev);
> +
> + ret = vfio_register_group_dev(>vdev);
> + if (ret)
> + goto out_put_vdev;
> +
> + pm_runtime_enable(>dev);
>   dev_set_drvdata(>dev, vdev);
>   return 0;
> +
> +out_put_vdev:
> + vfio_put_device(>vdev);
> + return ret;
> +}
> +
> +static void vfio_platform_release_dev(struct vfio_device *core_vdev)
> +{
> + struct vfio_platform_device *vdev =
> + container_of(core_vdev, struct vfio_platform_device, vdev);
> +
> + vfio_platform_release_common(vdev);
> + vfio_free_device(core_vdev);
>  }
>  
>  static int vfio_platform_remove(struct platform_device *pdev)
>  {
>   struct vfio_platform_device *vdev = dev_get_drvdata(>dev);
>  
> - vfio_platform_remove_common(vdev);
> - kfree(vdev);
> + vfio_unregister_group_dev(>vdev);
> + pm_runtime_disable(vdev->device);
> + vfio_put_device(>vdev);
>   return 0;
>  }
>  
> +static const struct vfio_device_ops vfio_platform_ops = {
> + .name   = "vfio-platform",
> + .init   = vfio_platform_init_dev,
> + .release= vfio_platform_release_dev,
> + .open_device= vfio_platform_open_device,
> + .close_device   = vfio_platform_close_device,
> + .ioctl  = vfio_platform_ioctl,
> + .read   = vfio_platform_read,
> + .write  = vfio_platform_write,
> + .mmap   = vfio_platform_mmap,
> +};
> +
>  static struct platform_driver vfio_platform_driver = {
>   .probe  = vfio_platform_probe,
>   .remove = vfio_platform_remove,
> diff --git a/drivers/vfio/platform/vfio_platform_common.c 
> b/drivers/vfio/platform/vfio_platform_common.c
> index 256f55b84e70..4c01bf0adebb 100644
> --- a/drivers/vfio/platform/vfio_platform_common.c
> +++ b/drivers/vfio/platform/vfio_platform_common.c
> @@ -218,7 +218,7 @@ static int vfio_platform_call_reset(struct 
> vfio_platform_device *vdev,
>   return -EINVAL;
>  }
>  
> -static void vfio_platform_close_device(struct vfio_device *core_vdev)
> +void vfio_platform_close_device(struct vfio_device *core_vdev)
>  {
>   struct vfio_platform_device *vdev =
>   container_of(core_vdev, struct vfio_platform_device, vdev);
> @@ -236,8 +236,9 @@ static void vfio_platform_close_device(struct vfio_device 
> *core_vdev)
>   vfio_platform_regions_cleanup(vdev);
>   vfio_platform_irq_cleanup(vdev);
>  }
> +EXPORT_SYMBOL_GPL(vfio_platform_close_device);
>  
> -static int vfio_platform_open_device(struct 

Re: [Intel-gfx] [PATCH v8 14/16] mei: debugfs: add pxp mode to devstate in debugfs

[Ceraolo Spurio, Daniele]

On 9/7/2022 8:58 AM, Tomas Winkler wrote:

Add pxp mode devstate to debugfs to monitor pxp state machine progress.
This is useful to debug issues in scenarios in which the pxp state
needs to be re-initialized, like during power transitions such as
suspend/resume. With this debugfs the state could be monitored
to ensure that pxp is in the ready state.

CC: Vitaly Lubart 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 


This is unchanged from the previously reviewed rev (apart from the 
header update), so this still applies:


Reviewed-by: Daniele Ceraolo Spurio 

Daniele


---
  drivers/misc/mei/debugfs.c | 19 ++-
  1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/mei/debugfs.c b/drivers/misc/mei/debugfs.c
index 1ce61e9e24fc..3b098d4c8e3d 100644
--- a/drivers/misc/mei/debugfs.c
+++ b/drivers/misc/mei/debugfs.c
@@ -1,6 +1,6 @@
  // SPDX-License-Identifier: GPL-2.0
  /*
- * Copyright (c) 2012-2016, Intel Corporation. All rights reserved
+ * Copyright (c) 2012-2022, Intel Corporation. All rights reserved
   * Intel Management Engine Interface (Intel MEI) Linux driver
   */
  
@@ -86,6 +86,20 @@ static int mei_dbgfs_active_show(struct seq_file *m, void *unused)

  }
  DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_active);
  
+static const char *mei_dev_pxp_mode_str(enum mei_dev_pxp_mode state)

+{
+#define MEI_PXP_MODE(state) case MEI_DEV_PXP_##state: return #state
+   switch (state) {
+   MEI_PXP_MODE(DEFAULT);
+   MEI_PXP_MODE(INIT);
+   MEI_PXP_MODE(SETUP);
+   MEI_PXP_MODE(READY);
+   default:
+   return "unknown";
+   }
+#undef MEI_PXP_MODE
+}
+
  static int mei_dbgfs_devstate_show(struct seq_file *m, void *unused)
  {
struct mei_device *dev = m->private;
@@ -112,6 +126,9 @@ static int mei_dbgfs_devstate_show(struct seq_file *m, void 
*unused)
seq_printf(m, "pg:  %s, %s\n",
   mei_pg_is_enabled(dev) ? "ENABLED" : "DISABLED",
   mei_pg_state_str(mei_pg_state(dev)));
+
+   seq_printf(m, "pxp: %s\n", mei_dev_pxp_mode_str(dev->pxp_mode));
+
return 0;
  }
  DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_devstate);

Re: [Intel-gfx] [PATCH v8 12/16] mei: gsc: add transition to PXP mode in resume flow

[Ceraolo Spurio, Daniele]

On 9/7/2022 8:58 AM, Tomas Winkler wrote:

From: Vitaly Lubart 

Added transition to PXP mode in resume flow.

CC: Daniele Ceraolo Spurio 
Signed-off-by: Vitaly Lubart 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 


This is unchanged from the previously reviewed rev, so this still applies:

Reviewed-by: Daniele Ceraolo Spurio 

Daniele


---
  drivers/misc/mei/gsc-me.c | 11 +++
  1 file changed, 11 insertions(+)

diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index 6b22726aed55..75765e4df4ed 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -182,11 +182,22 @@ static int __maybe_unused mei_gsc_pm_suspend(struct 
device *device)
  static int __maybe_unused mei_gsc_pm_resume(struct device *device)
  {
struct mei_device *dev = dev_get_drvdata(device);
+   struct auxiliary_device *aux_dev;
+   struct mei_aux_device *adev;
int err;
+   struct mei_me_hw *hw;
  
  	if (!dev)

return -ENODEV;
  
+	hw = to_me_hw(dev);

+   aux_dev = to_auxiliary_dev(device);
+   adev = auxiliary_dev_to_mei_aux_dev(aux_dev);
+   if (adev->ext_op_mem.start) {
+   mei_gsc_set_ext_op_mem(hw, >ext_op_mem);
+   dev->pxp_mode = MEI_DEV_PXP_INIT;
+   }
+
err = mei_restart(dev);
if (err)
return err;

Re: [Intel-gfx] [PATCH v8 11/16] mei: gsc: setup gsc extended operational memory

[Ceraolo Spurio, Daniele]

On 9/7/2022 8:58 AM, Tomas Winkler wrote:

1. Retrieve extended operational memory physical pointers from the
auxiliary device info.
2. Setup memory registers.
3. Notify firmware that the memory is ready by sending the memory
ready command.
4. Disable PXP device if GSC is not in PXP mode.

CC: Daniele Ceraolo Spurio 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 


only minor changes from the previously reviewed rev and they LGTM, so my 
r-b stands:


Reviewed-by: Daniele Ceraolo Spurio 

Daniele


---
  drivers/misc/mei/bus-fixup.c  | 70 ++-
  drivers/misc/mei/gsc-me.c | 16 
  drivers/misc/mei/hw-me-regs.h |  9 -
  drivers/misc/mei/hw-me.c  | 28 +-
  drivers/misc/mei/init.c   |  2 +
  drivers/misc/mei/mei_dev.h| 17 +
  include/linux/mei_aux.h   |  3 ++
  7 files changed, 141 insertions(+), 4 deletions(-)

diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index c4e527803299..79305e4acce2 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -188,6 +188,19 @@ static int mei_fwver(struct mei_cl_device *cldev)
return ret;
  }
  
+static int mei_gfx_memory_ready(struct mei_cl_device *cldev)

+{
+   struct mkhi_gfx_mem_ready req = {0};
+   unsigned int mode = MEI_CL_IO_TX_INTERNAL;
+
+   req.hdr.group_id = MKHI_GROUP_ID_GFX;
+   req.hdr.command = MKHI_GFX_MEMORY_READY_CMD_REQ;
+   req.flags = MKHI_GFX_MEM_READY_PXP_ALLOWED;
+
+   dev_dbg(>dev, "Sending memory ready command\n");
+   return __mei_cl_send(cldev->cl, (u8 *), sizeof(req), 0, mode);
+}
+
  static void mei_mkhi_fix(struct mei_cl_device *cldev)
  {
int ret;
@@ -234,6 +247,39 @@ static void mei_gsc_mkhi_ver(struct mei_cl_device *cldev)
dev_err(>dev, "FW version command failed %d\n", ret);
mei_cldev_disable(cldev);
  }
+
+static void mei_gsc_mkhi_fix_ver(struct mei_cl_device *cldev)
+{
+   int ret;
+
+   /* No need to enable the client if nothing is needed from it */
+   if (!cldev->bus->fw_f_fw_ver_supported &&
+   cldev->bus->pxp_mode != MEI_DEV_PXP_INIT)
+   return;
+
+   ret = mei_cldev_enable(cldev);
+   if (ret)
+   return;
+
+   if (cldev->bus->pxp_mode == MEI_DEV_PXP_INIT) {
+   ret = mei_gfx_memory_ready(cldev);
+   if (ret < 0)
+   dev_err(>dev, "memory ready command failed 
%d\n", ret);
+   else
+   dev_dbg(>dev, "memory ready command sent\n");
+   /* we go to reset after that */
+   cldev->bus->pxp_mode = MEI_DEV_PXP_SETUP;
+   goto out;
+   }
+
+   ret = mei_fwver(cldev);
+   if (ret < 0)
+   dev_err(>dev, "FW version command failed %d\n",
+   ret);
+out:
+   mei_cldev_disable(cldev);
+}
+
  /**
   * mei_wd - wd client on the bus, change protocol version
   *   as the API has changed.
@@ -473,6 +519,26 @@ static void vt_support(struct mei_cl_device *cldev)
cldev->do_match = 1;
  }
  
+/**

+ * pxp_is_ready - enable bus client if pxp is ready
+ *
+ * @cldev: me clients device
+ */
+static void pxp_is_ready(struct mei_cl_device *cldev)
+{
+   struct mei_device *bus = cldev->bus;
+
+   switch (bus->pxp_mode) {
+   case MEI_DEV_PXP_READY:
+   case MEI_DEV_PXP_DEFAULT:
+   cldev->do_match = 1;
+   break;
+   default:
+   cldev->do_match = 0;
+   break;
+   }
+}
+
  #define MEI_FIXUP(_uuid, _hook) { _uuid, _hook }
  
  static struct mei_fixup {

@@ -486,10 +552,10 @@ static struct mei_fixup {
MEI_FIXUP(MEI_UUID_WD, mei_wd),
MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix),
MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver),
-   MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_ver),
+   MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_fix_ver),
MEI_FIXUP(MEI_UUID_HDCP, whitelist),
MEI_FIXUP(MEI_UUID_ANY, vt_support),
-   MEI_FIXUP(MEI_UUID_PAVP, whitelist),
+   MEI_FIXUP(MEI_UUID_PAVP, pxp_is_ready),
  };
  
  /**

diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index bfa6154b93e2..6b22726aed55 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -32,6 +32,17 @@ static int mei_gsc_read_hfs(const struct mei_device *dev, 
int where, u32 *val)
return 0;
  }
  
+static void mei_gsc_set_ext_op_mem(const struct mei_me_hw *hw, struct resource *mem)

+{
+   u32 low = lower_32_bits(mem->start);
+   u32 hi  = upper_32_bits(mem->start);
+   u32 limit = (resource_size(mem) / SZ_4K) | GSC_EXT_OP_MEM_VALID;
+
+   iowrite32(low, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG);
+   iowrite32(hi, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG);
+   iowrite32(limit, hw->mem_addr + H_GSC_EXT_OP_MEM_LIMIT_REG);
+}
+
  static int 

Re: [Intel-gfx] [PATCH v8 09/16] mei: bus: export common mkhi definitions into a separate header

[Ceraolo Spurio, Daniele]

On 9/7/2022 8:58 AM, Tomas Winkler wrote:

From: Vitaly Lubart 

Exported common mkhi definitions from bus-fixup.c into a separate
header file mkhi.h for other driver usage.

Signed-off-by: Vitaly Lubart 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 
---
  drivers/misc/mei/bus-fixup.c | 31 +---
  drivers/misc/mei/mkhi.h  | 57 
  2 files changed, 58 insertions(+), 30 deletions(-)
  create mode 100644 drivers/misc/mei/mkhi.h

diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 344598fcf8e9..c4e527803299 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -15,6 +15,7 @@
  
  #include "mei_dev.h"

  #include "client.h"
+#include "mkhi.h"
  
  #define MEI_UUID_NFC_INFO UUID_LE(0xd2de1625, 0x382d, 0x417d, \

0x48, 0xa4, 0xef, 0xab, 0xba, 0x8a, 0x12, 0x06)
@@ -89,20 +90,6 @@ struct mei_os_ver {
u8  reserved2;
  } __packed;
  
-#define MKHI_FEATURE_PTT 0x10

-
-struct mkhi_rule_id {
-   __le16 rule_type;
-   u8 feature_id;
-   u8 reserved;
-} __packed;
-
-struct mkhi_fwcaps {
-   struct mkhi_rule_id id;
-   u8 len;
-   u8 data[];
-} __packed;
-
  struct mkhi_fw_ver_block {
u16 minor;
u8 major;
@@ -115,22 +102,6 @@ struct mkhi_fw_ver {
struct mkhi_fw_ver_block ver[MEI_MAX_FW_VER_BLOCKS];
  } __packed;
  
-#define MKHI_FWCAPS_GROUP_ID 0x3

-#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
-#define MKHI_GEN_GROUP_ID 0xFF
-#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
-struct mkhi_msg_hdr {
-   u8  group_id;
-   u8  command;
-   u8  reserved;
-   u8  result;
-} __packed;
-
-struct mkhi_msg {
-   struct mkhi_msg_hdr hdr;
-   u8 data[];
-} __packed;
-
  #define MKHI_OSVER_BUF_LEN (sizeof(struct mkhi_msg_hdr) + \
sizeof(struct mkhi_fwcaps) + \
sizeof(struct mei_os_ver))
diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
new file mode 100644
index ..43cadfb1b990
--- /dev/null
+++ b/drivers/misc/mei/mkhi.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ */
+
+#ifndef _MEI_MKHI_H_
+#define _MEI_MKHI_H_
+
+#include 
+
+#define MKHI_FEATURE_PTT 0x10
+
+#define MKHI_FWCAPS_GROUP_ID 0x3
+#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
+#define MKHI_GEN_GROUP_ID 0xFF
+#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
+
+#define MKHI_GROUP_ID_GFX  0x30
+#define MKHI_GFX_RESET_WARN_CMD_REQ0x0
+#define MKHI_GFX_MEMORY_READY_CMD_REQ  0x1
+
+/* Allow transition to PXP mode without approval */
+#define MKHI_GFX_MEM_READY_PXP_ALLOWED  0x1
+
+#define MKHI_GROUP_ID_GFX  0x30
+#define MKHI_GFX_RESET_WARN_CMD_REQ0x0
+#define MKHI_GFX_MEMORY_READY_CMD_REQ  0x1
+
+/* Allow transition to PXP mode without approval */
+#define MKHI_GFX_MEM_READY_PXP_ALLOWED  0x1


Something weird is happening here. Those defs were added by the next 
patch in the previous rev, while now they're added here twice and then 
still added once more in the next patch, so they're defined 3 times. IMO 
leaving it to the next patch is better, so they should just be dropped 
from this one.


Daniele


+
+struct mkhi_rule_id {
+   __le16 rule_type;
+   u8 feature_id;
+   u8 reserved;
+} __packed;
+
+struct mkhi_fwcaps {
+   struct mkhi_rule_id id;
+   u8 len;
+   u8 data[];
+} __packed;
+
+struct mkhi_msg_hdr {
+   u8  group_id;
+   u8  command;
+   u8  reserved;
+   u8  result;
+} __packed;
+
+struct mkhi_msg {
+   struct mkhi_msg_hdr hdr;
+   u8 data[];
+} __packed;
+
+#endif /* _MEI_MKHI_H_ */

Re: [Intel-gfx] [PATCH v8 08/16] mei: extend timeouts on slow devices.

[Ceraolo Spurio, Daniele]

On 9/7/2022 8:58 AM, Tomas Winkler wrote:

From: Alexander Usyskin 

Parametrize operational timeouts in order
to support slow firmware on some graphics devices.

Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 
---
  drivers/misc/mei/bus-fixup.c |  5 ++---
  drivers/misc/mei/client.c| 16 
  drivers/misc/mei/gsc-me.c|  2 +-
  drivers/misc/mei/hbm.c   | 14 +++---
  drivers/misc/mei/hw-me.c | 30 --
  drivers/misc/mei/hw-me.h |  2 +-
  drivers/misc/mei/hw-txe.c|  4 ++--
  drivers/misc/mei/hw.h|  7 ++-
  drivers/misc/mei/init.c  | 19 ++-
  drivers/misc/mei/main.c  |  4 ++--
  drivers/misc/mei/mei_dev.h   | 18 +-
  drivers/misc/mei/pci-me.c|  4 ++--
  12 files changed, 82 insertions(+), 43 deletions(-)

diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 59506ba6fc48..344598fcf8e9 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -1,6 +1,6 @@
  // SPDX-License-Identifier: GPL-2.0
  /*
- * Copyright (c) 2013-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2013-2022, Intel Corporation. All rights reserved.
   * Intel Management Engine Interface (Intel MEI) Linux driver
   */
  
@@ -164,7 +164,6 @@ static int mei_osver(struct mei_cl_device *cldev)

sizeof(struct mkhi_fw_ver))
  #define MKHI_FWVER_LEN(__num) (sizeof(struct mkhi_msg_hdr) + \
   sizeof(struct mkhi_fw_ver_block) * (__num))
-#define MKHI_RCV_TIMEOUT 500 /* receive timeout in msec */
  static int mei_fwver(struct mei_cl_device *cldev)
  {
char buf[MKHI_FWVER_BUF_LEN];
@@ -187,7 +186,7 @@ static int mei_fwver(struct mei_cl_device *cldev)
  
  	ret = 0;

bytes_recv = __mei_cl_recv(cldev->cl, buf, sizeof(buf), NULL, 0,
-  MKHI_RCV_TIMEOUT);
+  cldev->bus->timeouts.mkhi_recv);
if (bytes_recv < 0 || (size_t)bytes_recv < MKHI_FWVER_LEN(1)) {
/*
 * Should be at least one version block,
diff --git a/drivers/misc/mei/client.c b/drivers/misc/mei/client.c
index 31264ab2eb13..0b2fbe1335a7 100644
--- a/drivers/misc/mei/client.c
+++ b/drivers/misc/mei/client.c
@@ -1,6 +1,6 @@
  // SPDX-License-Identifier: GPL-2.0
  /*
- * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
   * Intel Management Engine Interface (Intel MEI) Linux driver
   */
  
@@ -870,7 +870,7 @@ static int mei_cl_send_disconnect(struct mei_cl *cl, struct mei_cl_cb *cb)

}
  
  	list_move_tail(>list, >ctrl_rd_list);

-   cl->timer_count = MEI_CONNECT_TIMEOUT;
+   cl->timer_count = dev->timeouts.connect;
mei_schedule_stall_timer(dev);
  
  	return 0;

@@ -945,7 +945,7 @@ static int __mei_cl_disconnect(struct mei_cl *cl)
wait_event_timeout(cl->wait,
   cl->state == MEI_FILE_DISCONNECT_REPLY ||
   cl->state == MEI_FILE_DISCONNECTED,
-  mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+  dev->timeouts.cl_connect);
mutex_lock(>device_lock);
  
  	rets = cl->status;

@@ -1065,7 +1065,7 @@ static int mei_cl_send_connect(struct mei_cl *cl, struct 
mei_cl_cb *cb)
}
  
  	list_move_tail(>list, >ctrl_rd_list);

-   cl->timer_count = MEI_CONNECT_TIMEOUT;
+   cl->timer_count = dev->timeouts.connect;
mei_schedule_stall_timer(dev);
return 0;
  }
@@ -1164,7 +1164,7 @@ int mei_cl_connect(struct mei_cl *cl, struct 
mei_me_client *me_cl,
 cl->state == MEI_FILE_DISCONNECTED ||
 cl->state == MEI_FILE_DISCONNECT_REQUIRED ||
 cl->state == MEI_FILE_DISCONNECT_REPLY),
-   mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+   dev->timeouts.cl_connect);
mutex_lock(>device_lock);
  
  	if (!mei_cl_is_connected(cl)) {

@@ -1562,7 +1562,7 @@ int mei_cl_notify_request(struct mei_cl *cl,
   cl->notify_en == request ||
   cl->status ||
   !mei_cl_is_connected(cl),
-  mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+  dev->timeouts.cl_connect);
mutex_lock(>device_lock);
  
  	if (cl->notify_en != request && !cl->status)

@@ -2336,7 +2336,7 @@ int mei_cl_dma_alloc_and_map(struct mei_cl *cl, const 
struct file *fp,
mutex_unlock(>device_lock);
wait_event_timeout(cl->wait,
   cl->dma_mapped || cl->status,
-  mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+  dev->timeouts.cl_connect);
mutex_lock(>device_lock);
  
  	if (!cl->dma_mapped && !cl->status)

@@ -2415,7 +2415,7 

[Intel-gfx] ✓ Fi.CI.BAT: success for GSC support for XeHP SDV and DG2 (rev4)

[Patchwork]

== Series Details ==

Series: GSC support for XeHP SDV and DG2 (rev4)
URL   : https://patchwork.freedesktop.org/series/106638/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12089 -> Patchwork_106638v4


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/index.html

Participating hosts (31 -> 43)
--

  Additional (13): fi-rkl-11600 bat-dg1-5 bat-dg2-8 bat-adlm-1 bat-dg2-9 
bat-adlp-6 bat-adlp-4 bat-adln-1 fi-pnv-d510 bat-rplp-1 bat-rpls-1 bat-rpls-2 
bat-dg2-11 
  Missing(1): fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_106638v4 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@fbdev@nullptr:
- bat-dg1-5:  NOTRUN -> [SKIP][1] ([i915#2582]) +4 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/bat-dg1-5/igt@fb...@nullptr.html

  * igt@fbdev@read:
- bat-adlp-4: NOTRUN -> [SKIP][2] ([i915#2582]) +4 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/bat-adlp-4/igt@fb...@read.html

  * igt@gem_exec_basic@basic@rcs0-lmem0:
- bat-dg1-5:  NOTRUN -> [DMESG-WARN][3] ([i915#6744])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/bat-dg1-5/igt@gem_exec_basic@ba...@rcs0-lmem0.html

  * igt@gem_huc_copy@huc-copy:
- fi-rkl-11600:   NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/fi-rkl-11600/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-adlp-4: NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/bat-adlp-4/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][7] ([i915#3282])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/fi-rkl-11600/igt@gem_tiled_pread_basic.html
- bat-adlp-4: NOTRUN -> [SKIP][8] ([i915#3282])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/bat-adlp-4/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-adlp-4: NOTRUN -> [SKIP][9] ([i915#1155])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/bat-adlp-4/igt@i915_pm_backli...@basic-brightness.html
- fi-rkl-11600:   NOTRUN -> [SKIP][10] ([i915#3012])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rps@basic-api:
- bat-adlp-4: NOTRUN -> [SKIP][11] ([i915#6621])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/bat-adlp-4/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][12] -> [INCOMPLETE][13] ([i915#4785])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-g3258:   [PASS][14] -> [INCOMPLETE][15] ([i915#3303] / 
[i915#4785])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   NOTRUN -> [INCOMPLETE][16] ([i915#5982])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@dp-crc-fast:
- bat-adlp-4: NOTRUN -> [SKIP][17] ([fdo#111827]) +8 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/bat-adlp-4/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-edid-read:
- fi-rkl-11600:   NOTRUN -> [SKIP][18] ([fdo#111827]) +7 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/fi-rkl-11600/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-rkl-11600:   NOTRUN -> [SKIP][19] ([i915#4103])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v4/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
- bat-adlp-4: NOTRUN -> [SKIP][20] ([i915#3637]) +3 similar issues
   [20]: 

Re: [Intel-gfx] [PATCH v8 07/16] mei: gsc: wait for reset thread on stop

[Ceraolo Spurio, Daniele]

On 9/7/2022 8:58 AM, Tomas Winkler wrote:

From: Alexander Usyskin 

Wait for reset work to complete before initiating
stop reset flow sequence.

Signed-off-by: Alexander Usyskin 
Signed-off-by: Tomas Winkler 


This is unchanged from the previously reviewed rev (apart from the fixed 
date in the header), so this still applies:


Reviewed-by: Daniele Ceraolo Spurio 

Daniele


---
  drivers/misc/mei/init.c | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
index eb052005ca86..bc054baf496c 100644
--- a/drivers/misc/mei/init.c
+++ b/drivers/misc/mei/init.c
@@ -1,6 +1,6 @@
  // SPDX-License-Identifier: GPL-2.0
  /*
- * Copyright (c) 2012-2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2012-2022, Intel Corporation. All rights reserved.
   * Intel Management Engine Interface (Intel MEI) Linux driver
   */
  
@@ -320,6 +320,8 @@ void mei_stop(struct mei_device *dev)
  
  	mei_clear_interrupts(dev);

mei_synchronize_irq(dev);
+   /* to catch HW-initiated reset */
+   mei_cancel_work(dev);
  
  	mutex_lock(>device_lock);
  

Re: [Intel-gfx] [PATCH v8 06/16] mei: gsc: use polling instead of interrupts

[Ceraolo Spurio, Daniele]

On 9/7/2022 8:58 AM, Tomas Winkler wrote:

A work-around for a HW issue in XEHPSDV that manifests itself when SW reads
a gsc register when gsc is sending an interrupt. The work-around is
to disable interrupts and to use polling instead.

Cc: James Ausmus 
Signed-off-by: Vitaly Lubart 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 


The only changes from the previously reviewed rev are extra comments and 
doc. Those look good, so my r-b stands:


Reviewed-by: Daniele Ceraolo Spurio 

Daniele


---
  drivers/misc/mei/gsc-me.c | 48 ++-
  drivers/misc/mei/hw-me.c  | 80 ---
  drivers/misc/mei/hw-me.h  | 15 +++-
  3 files changed, 128 insertions(+), 15 deletions(-)

diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index c8145e9b62b6..2caba3a9ac35 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -13,6 +13,7 @@
  #include 
  #include 
  #include 
+#include 
  
  #include "mei_dev.h"

  #include "hw-me.h"
@@ -66,13 +67,28 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
  
  	dev_set_drvdata(device, dev);
  
-	ret = devm_request_threaded_irq(device, hw->irq,

-   mei_me_irq_quick_handler,
-   mei_me_irq_thread_handler,
-   IRQF_ONESHOT, KBUILD_MODNAME, dev);
-   if (ret) {
-   dev_err(device, "irq register failed %d\n", ret);
-   goto err;
+   /* use polling */
+   if (mei_me_hw_use_polling(hw)) {
+   mei_disable_interrupts(dev);
+   mei_clear_interrupts(dev);
+   init_waitqueue_head(>wait_active);
+   hw->is_active = true; /* start in active mode for 
initialization */
+   hw->polling_thread = kthread_run(mei_me_polling_thread, dev,
+"kmegscirqd/%s", 
dev_name(device));
+   if (IS_ERR(hw->polling_thread)) {
+   ret = PTR_ERR(hw->polling_thread);
+   dev_err(device, "unable to create kernel thread: %d\n", 
ret);
+   goto err;
+   }
+   } else {
+   ret = devm_request_threaded_irq(device, hw->irq,
+   mei_me_irq_quick_handler,
+   mei_me_irq_thread_handler,
+   IRQF_ONESHOT, KBUILD_MODNAME, 
dev);
+   if (ret) {
+   dev_err(device, "irq register failed %d\n", ret);
+   goto err;
+   }
}
  
  	pm_runtime_get_noresume(device);

@@ -98,7 +114,8 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
  
  register_err:

mei_stop(dev);
-   devm_free_irq(device, hw->irq, dev);
+   if (!mei_me_hw_use_polling(hw))
+   devm_free_irq(device, hw->irq, dev);
  
  err:

dev_err(device, "probe failed: %d\n", ret);
@@ -119,12 +136,17 @@ static void mei_gsc_remove(struct auxiliary_device 
*aux_dev)
  
  	mei_stop(dev);
  
+	hw = to_me_hw(dev);

+   if (mei_me_hw_use_polling(hw))
+   kthread_stop(hw->polling_thread);
+
mei_deregister(dev);
  
  	pm_runtime_disable(_dev->dev);
  
  	mei_disable_interrupts(dev);

-   devm_free_irq(_dev->dev, hw->irq, dev);
+   if (!mei_me_hw_use_polling(hw))
+   devm_free_irq(_dev->dev, hw->irq, dev);
  }
  
  static int __maybe_unused mei_gsc_pm_suspend(struct device *device)

@@ -185,6 +207,9 @@ static int  __maybe_unused 
mei_gsc_pm_runtime_suspend(struct device *device)
if (mei_write_is_idle(dev)) {
hw = to_me_hw(dev);
hw->pg_state = MEI_PG_ON;
+
+   if (mei_me_hw_use_polling(hw))
+   hw->is_active = false;
ret = 0;
} else {
ret = -EAGAIN;
@@ -209,6 +234,11 @@ static int __maybe_unused mei_gsc_pm_runtime_resume(struct 
device *device)
hw = to_me_hw(dev);
hw->pg_state = MEI_PG_OFF;
  
+	if (mei_me_hw_use_polling(hw)) {

+   hw->is_active = true;
+   wake_up(>wait_active);
+   }
+
mutex_unlock(>device_lock);
  
  	irq_ret = mei_me_irq_thread_handler(1, dev);

diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index 3a95fe7d4e33..23ad53efbcb7 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -1,6 +1,6 @@
  // SPDX-License-Identifier: GPL-2.0
  /*
- * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
   * Intel Management Engine Interface (Intel MEI) Linux driver
   */
  
@@ -10,6 +10,7 @@

  #include 
  #include 
  #include 
+#include 
  
  #include "mei_dev.h"

  #include "hbm.h"
@@ -327,9 +328,12 @@ static void mei_me_intr_clear(struct mei_device *dev)
  

Re: [Intel-gfx] [PATCH v8 05/16] drm/i915/gsc: add GSC XeHP SDV platform definition

[Ceraolo Spurio, Daniele]

On 9/7/2022 8:58 AM, Tomas Winkler wrote:

From: Alexander Usyskin 

Define GSC on XeHP SDV (Intel(R) dGPU without display)

XeHP SDV uses the same hardware settings as DG1, but uses polling
instead of interrupts and runs the firmware in slow pace due to
hardware limitations.

Signed-off-by: Vitaly Lubart 
Signed-off-by: Tomas Winkler 
Signed-off-by: Alexander Usyskin 


This is unchanged from the previously reviewed rev, so this still applies:

Reviewed-by: Daniele Ceraolo Spurio 

Daniele


---
  drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++
  1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c 
b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 73498c2574c8..e1040c8f2fd3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] = {
}
  };
  
+static const struct gsc_def gsc_def_xehpsdv[] = {

+   {
+   /* HECI1 not enabled on the device. */
+   },
+   {
+   .name = "mei-gscfi",
+   .bar = DG1_GSC_HECI2_BASE,
+   .bar_size = GSC_BAR_LENGTH,
+   .use_polling = true,
+   .slow_firmware = true,
+   }
+};
+
  static const struct gsc_def gsc_def_dg2[] = {
{
.name = "mei-gsc",
@@ -107,6 +120,8 @@ static void gsc_init_one(struct drm_i915_private *i915,
  
  	if (IS_DG1(i915)) {

def = _def_dg1[intf_id];
+   } else if (IS_XEHPSDV(i915)) {
+   def = _def_xehpsdv[intf_id];
} else if (IS_DG2(i915)) {
def = _def_dg2[intf_id];
} else {

Re: [Intel-gfx] [PATCH v8 02/16] mei: add kdoc for struct mei_aux_device

[Ceraolo Spurio, Daniele]

On 9/7/2022 8:57 AM, Tomas Winkler wrote:

struct mei_aux_device is an interface structure
requires proper documenation.

Signed-off-by: Tomas Winkler 


This is unchanged from the previously reviewed rev, so this still applies:

Reviewed-by: Daniele Ceraolo Spurio 

Daniele


---
  include/linux/mei_aux.h | 6 ++
  1 file changed, 6 insertions(+)

diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
index 587f25128848..a0cb587006d5 100644
--- a/include/linux/mei_aux.h
+++ b/include/linux/mei_aux.h
@@ -7,6 +7,12 @@
  
  #include 
  
+/**

+ * struct mei_aux_device - mei auxiliary device
+ * @aux_dev: - auxiliary device object
+ * @irq: interrupt driving the mei auxiliary device
+ * @bar: mmio resource bar reserved to mei auxiliary device
+ */
  struct mei_aux_device {
struct auxiliary_device aux_dev;
int irq;

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for GSC support for XeHP SDV and DG2 (rev4)

[Patchwork]

== Series Details ==

Series: GSC support for XeHP SDV and DG2 (rev4)
URL   : https://patchwork.freedesktop.org/series/106638/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GSC support for XeHP SDV and DG2 (rev4)

[Patchwork]

== Series Details ==

Series: GSC support for XeHP SDV and DG2 (rev4)
URL   : https://patchwork.freedesktop.org/series/106638/
State : warning

== Summary ==

Error: dim checkpatch failed
a6d157c243b5 drm/i915/gsc: skip irq initialization if using polling
f33aa591ecde mei: add kdoc for struct mei_aux_device
8dec02344065 mei: add slow_firmware flag to the mei auxiliary device
55dd4dfeed6b drm/i915/gsc: add slow_firmware flag to the gsc device definition
604fed434ce9 drm/i915/gsc: add GSC XeHP SDV platform definition
d3e659f047ae mei: gsc: use polling instead of interrupts
032acd9005c3 mei: gsc: wait for reset thread on stop
1438bdcfd1cb mei: extend timeouts on slow devices.
4a69d0b86e86 mei: bus: export common mkhi definitions into a separate header
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
-:71: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#71: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 106 lines checked
f5fbdd916a5e mei: mkhi: add memory ready command
25250fb00f7a mei: gsc: setup gsc extended operational memory
e9c85b31d6bf mei: gsc: add transition to PXP mode in resume flow
af40f92c8c90 mei: drop ready bits check after start
8393a31429b0 mei: debugfs: add pxp mode to devstate in debugfs
-:34: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#34: FILE: drivers/misc/mei/debugfs.c:91:
+#define MEI_PXP_MODE(state) case MEI_DEV_PXP_##state: return #state

total: 1 errors, 0 warnings, 0 checks, 36 lines checked
db50a0d373af drm/i915/gsc: allocate extended operational memory in LMEM
4e58910c7f4e HAX: drm/i915: force INTEL_MEI_GSC on for CI

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Set correct domains values at _i915_vma_move_to_active

[Patchwork]

== Series Details ==

Series: drm/i915: Set correct domains values at _i915_vma_move_to_active
URL   : https://patchwork.freedesktop.org/series/108258/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12089 -> Patchwork_108258v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/index.html

Participating hosts (31 -> 42)
--

  Additional (13): fi-rkl-11600 bat-dg1-5 bat-dg2-8 bat-adlm-1 bat-dg2-9 
bat-adlp-6 bat-adlp-4 bat-adln-1 fi-pnv-d510 bat-rplp-1 bat-rpls-1 bat-rpls-2 
bat-dg2-11 
  Missing(2): fi-icl-u2 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_108258v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@fbdev@nullptr:
- bat-dg1-5:  NOTRUN -> [SKIP][1] ([i915#2582]) +4 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/bat-dg1-5/igt@fb...@nullptr.html

  * igt@fbdev@read:
- bat-adlp-4: NOTRUN -> [SKIP][2] ([i915#2582]) +4 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/bat-adlp-4/igt@fb...@read.html

  * igt@gem_exec_basic@basic@rcs0-lmem0:
- bat-dg1-5:  NOTRUN -> [DMESG-WARN][3] ([i915#6744])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/bat-dg1-5/igt@gem_exec_basic@ba...@rcs0-lmem0.html

  * igt@gem_huc_copy@huc-copy:
- fi-rkl-11600:   NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/fi-rkl-11600/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-adlp-4: NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/bat-adlp-4/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][7] ([i915#3282])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html
- bat-adlp-4: NOTRUN -> [SKIP][8] ([i915#3282])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/bat-adlp-4/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-adlp-4: NOTRUN -> [SKIP][9] ([i915#1155])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/bat-adlp-4/igt@i915_pm_backli...@basic-brightness.html
- fi-rkl-11600:   NOTRUN -> [SKIP][10] ([i915#3012])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [PASS][11] -> [DMESG-FAIL][12] ([i915#62])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_pm_rps@basic-api:
- bat-adlp-4: NOTRUN -> [SKIP][13] ([i915#6621])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/bat-adlp-4/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u:   [PASS][14] -> [DMESG-WARN][15] ([i915#5904]) +30 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][16] ([i915#4528])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u:   [PASS][17] -> [DMESG-WARN][18] ([i915#5904] / 
[i915#62])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12089/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   NOTRUN -> [INCOMPLETE][19] ([i915#5982])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@dp-crc-fast:
- bat-adlp-4: NOTRUN -> [SKIP][20] ([fdo#111827]) +8 similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108258v1/bat-adlp-4/igt@kms_chamel...@dp-crc-fast.html

  * 

[Intel-gfx] [PATCH] drm/i915/gsc: allocate extended operational memory in LMEM

[Daniele Ceraolo Spurio]

From: Tomas Winkler 

GSC requires more operational memory than available on chip.
Reserve 4M of LMEM for GSC operation. The memory is provided to the
GSC as struct resource to the auxiliary data of the child device.

v2: use I915_BO_ALLOC_CPU_CLEAR to clear the allocated memory instead of
doing a manual memset (Matt)

Cc: Alan Previn 
Cc: Matthew Auld 
Signed-off-by: Tomas Winkler 
Signed-off-by: Daniele Ceraolo Spurio 
Signed-off-by: Alexander Usyskin 
---
 drivers/gpu/drm/i915/gt/intel_gsc.c | 79 ++---
 drivers/gpu/drm/i915/gt/intel_gsc.h |  3 ++
 2 files changed, 75 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c 
b/drivers/gpu/drm/i915/gt/intel_gsc.c
index e1040c8f2fd3..7af6db3194dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -7,6 +7,7 @@
 #include 
 #include "i915_drv.h"
 #include "i915_reg.h"
+#include "gem/i915_gem_region.h"
 #include "gt/intel_gsc.h"
 #include "gt/intel_gt.h"
 
@@ -36,12 +37,56 @@ static int gsc_irq_init(int irq)
return irq_set_chip_data(irq, NULL);
 }
 
+static int
+gsc_ext_om_alloc(struct intel_gsc *gsc, struct intel_gsc_intf *intf, size_t 
size)
+{
+   struct intel_gt *gt = gsc_to_gt(gsc);
+   struct drm_i915_gem_object *obj;
+   int err;
+
+   obj = i915_gem_object_create_lmem(gt->i915, size,
+ I915_BO_ALLOC_CONTIGUOUS |
+ I915_BO_ALLOC_CPU_CLEAR);
+   if (IS_ERR(obj)) {
+   drm_err(>i915->drm, "Failed to allocate gsc memory\n");
+   return PTR_ERR(obj);
+   }
+
+   err = i915_gem_object_pin_pages_unlocked(obj);
+   if (err) {
+   drm_err(>i915->drm, "Failed to pin pages for gsc memory\n");
+   goto out_put;
+   }
+
+   intf->gem_obj = obj;
+
+   return 0;
+
+out_put:
+   i915_gem_object_put(obj);
+   return err;
+}
+
+static void gsc_ext_om_destroy(struct intel_gsc_intf *intf)
+{
+   struct drm_i915_gem_object *obj = fetch_and_zero(>gem_obj);
+
+   if (!obj)
+   return;
+
+   if (i915_gem_object_has_pinned_pages(obj))
+   i915_gem_object_unpin_pages(obj);
+
+   i915_gem_object_put(obj);
+}
+
 struct gsc_def {
const char *name;
unsigned long bar;
size_t bar_size;
bool use_polling;
bool slow_firmware;
+   size_t lmem_size;
 };
 
 /* gsc resources and definitions (HECI1 and HECI2) */
@@ -74,6 +119,7 @@ static const struct gsc_def gsc_def_dg2[] = {
.name = "mei-gsc",
.bar = DG2_GSC_HECI1_BASE,
.bar_size = GSC_BAR_LENGTH,
+   .lmem_size = SZ_4M,
},
{
.name = "mei-gscfi",
@@ -90,26 +136,32 @@ static void gsc_release_dev(struct device *dev)
kfree(adev);
 }
 
-static void gsc_destroy_one(struct intel_gsc_intf *intf)
+static void gsc_destroy_one(struct drm_i915_private *i915,
+   struct intel_gsc *gsc, unsigned int intf_id)
 {
+   struct intel_gsc_intf *intf = >intf[intf_id];
+
if (intf->adev) {
auxiliary_device_delete(>adev->aux_dev);
auxiliary_device_uninit(>adev->aux_dev);
intf->adev = NULL;
}
+
if (intf->irq >= 0)
irq_free_desc(intf->irq);
intf->irq = -1;
+
+   gsc_ext_om_destroy(intf);
 }
 
-static void gsc_init_one(struct drm_i915_private *i915,
-struct intel_gsc_intf *intf,
+static void gsc_init_one(struct drm_i915_private *i915, struct intel_gsc *gsc,
 unsigned int intf_id)
 {
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct mei_aux_device *adev;
struct auxiliary_device *aux_dev;
const struct gsc_def *def;
+   struct intel_gsc_intf *intf = >intf[intf_id];
int ret;
 
intf->irq = -1;
@@ -141,7 +193,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
intf->irq = irq_alloc_desc(0);
if (intf->irq < 0) {
drm_err(>drm, "gsc irq error %d\n", intf->irq);
-   return;
+   goto fail;
}
 
ret = gsc_irq_init(intf->irq);
@@ -155,6 +207,19 @@ static void gsc_init_one(struct drm_i915_private *i915,
if (!adev)
goto fail;
 
+   if (def->lmem_size) {
+   drm_dbg(>drm, "setting up GSC lmem\n");
+
+   if (gsc_ext_om_alloc(gsc, intf, def->lmem_size)) {
+   drm_err(>drm, "setting up gsc extended 
operational memory failed\n");
+   kfree(adev);
+   goto fail;
+   }
+
+   adev->ext_op_mem.start = 
i915_gem_object_get_dma_address(intf->gem_obj, 0);
+   adev->ext_op_mem.end = adev->ext_op_mem.start + def->lmem_size;
+   }
+
adev->irq = intf->irq;

Re: [Intel-gfx] [PATCH] drm/dp_mst: Avoid deleting payloads for connectors staying enabled

[Lyude Paul]

Surprised this didn't come up on Intel's CI (or at least it certainly didn't
when the series that introduced this was tested), thanks for the catch!

Reviewed-by: Lyude Paul 

On Wed, 2022-09-07 at 17:25 +0300, Imre Deak wrote:
> When an MST connector stays enabled during a commit the connector's MST
> state needs to be added to the atomic state, but the corresponding MST
> payload allocation shouldn't be set for deletion; fix such modesets by
> ensuring the above even if the connector was already enabled before the
> modeset.
> 
> The issue led to the following:
> [  761.992923] i915 :00:02.0: drm_WARN_ON(payload->delete)
> [  761.992949] WARNING: CPU: 6 PID: 1401 at 
> drivers/gpu/drm/display/drm_dp_mst_topology.c:4221 
> drm_dp_atomic_find_time_slots+0x236/0x280 [drm_display_helper]
> [  761.992955] Modules linked in: snd_hda_intel i915 drm_buddy 
> drm_display_helper drm_kms_helper ttm drm snd_hda_codec_hdmi snd_intel_dspcfg 
> snd_hda_codec snd_hwdep snd_hda_core snd_pcm prime_numbers i2c_algo_bit 
> syscopyarea sysfillrect sysimgblt fb_sys_fops x86_pkg_temp_thermal cdc_ether 
> coretemp crct10dif_pclmul usbnet crc32_pclmul mii ghash_clmulni_intel e1000e 
> mei_me ptp i2c_i801 pps_core mei i2c_smbus intel_lpss_pci fuse [last 
> unloaded: drm]
> [  761.992986] CPU: 6 PID: 1401 Comm: testdisplay Tainted: G U
>  6.0.0-rc4-imre+ #565
> [  761.992989] Hardware name: Intel Corporation Alder Lake Client 
> Platform/AlderLake-P DDR5 RVP, BIOS ADLPFWI1.R00.3135.A00.2203251419 
> 03/25/2022
> [  761.992990] RIP: 0010:drm_dp_atomic_find_time_slots+0x236/0x280 
> [drm_display_helper]
> [  761.992994] Code: 4c 8b 67 50 4d 85 e4 75 03 4c 8b 27 e8 03 28 4e e1 48 c7 
> c1 8b 26 2c a0 4c 89 e2 48 c7 c7 a8 26 2c a0 48 89 c6 e8 31 d5 88 e1 <0f> 0b 
> 49 8b 85 d0 00 00 00 4c 89 fa 48 c7 c6 a0 41 2c a0 48 8b 78
> [  761.992995] RSP: 0018:c9000177ba60 EFLAGS: 00010286
> [  761.992998] RAX:  RBX: 88810d2f1540 RCX: 
> 
> [  761.992999] RDX: 0001 RSI: 82368a25 RDI: 
> 
> [  761.993000] RBP: 888142299d80 R08: 8884adbfdfe8 R09: 
> ffef
> [  761.993001] R10: 8884a6bfe000 R11: 8884ac443c30 R12: 
> 888102972f90
> [  761.993002] R13: 8881163e2cf0 R14: 03ac R15: 
> 88810c501000
> [  761.993003] FS:  7f81e4c459c0() GS:88849650() 
> knlGS:
> [  761.993004] CS:  0010 DS:  ES:  CR0: 80050033
> [  761.993005] CR2: 555dac962a98 CR3: 000123a34006 CR4: 
> 00770ee0
> [  761.993006] PKRU: 5554
> [  761.993007] Call Trace:
> [  761.993009]  
> [  761.993012]  intel_dp_mst_compute_config+0x19a/0x350 [i915]
> [  761.993090]  intel_atomic_check+0xf37/0x3180 [i915]
> [  761.993168]  drm_atomic_check_only+0x5d3/0xa60 [drm]
> [  761.993182]  drm_atomic_commit+0x56/0xc0 [drm]
> [  761.993192]  ? drm_plane_get_damage_clips.cold+0x1c/0x1c [drm]
> [  761.993204]  drm_atomic_helper_set_config+0x78/0xc0 [drm_kms_helper]
> [  761.993214]  drm_mode_setcrtc+0x1ed/0x750 [drm]
> [  761.993232]  ? drm_mode_getcrtc+0x180/0x180 [drm]
> [  761.993241]  drm_ioctl_kernel+0xb5/0x150 [drm]
> [  761.993252]  drm_ioctl+0x203/0x3d0 [drm]
> [  761.993261]  ? drm_mode_getcrtc+0x180/0x180 [drm]
> [  761.993276]  __x64_sys_ioctl+0x8a/0xb0
> [  761.993281]  do_syscall_64+0x38/0x90
> [  761.993285]  entry_SYSCALL_64_after_hwframe+0x63/0xcd
> [  761.993287] RIP: 0033:0x7f81e551aaff
> [  761.993288] Code: 00 48 89 44 24 18 31 c0 48 8d 44 24 60 c7 04 24 10 00 00 
> 00 48 89 44 24 08 48 8d 44 24 20 48 89 44 24 10 b8 10 00 00 00 0f 05 <41> 89 
> c0 3d 00 f0 ff ff 77 1f 48 8b 44 24 18 64 48 2b 04 25 28 00
> [  761.993290] RSP: 002b:7fff4304af10 EFLAGS: 0246 ORIG_RAX: 
> 0010
> [  761.993292] RAX: ffda RBX: 7fff4304afa0 RCX: 
> 7f81e551aaff
> [  761.993293] RDX: 7fff4304afa0 RSI: c06864a2 RDI: 
> 0004
> [  761.993294] RBP: c06864a2 R08:  R09: 
> 555dac8a9c68
> [  761.993294] R10:  R11: 0246 R12: 
> 08c4
> [  761.993295] R13: 0004 R14: 555dac8a9c68 R15: 
> 7fff4304b098
> [  761.993301]  
> 
> Fixes: 083351e96386 ("drm/display/dp_mst: Fix modeset tracking in 
> drm_dp_atomic_release_vcpi_slots()")
> Testcase: igt@testdisplay
> Cc: Lyude Paul 
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/display/drm_dp_mst_topology.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c 
> b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index 1de438151cc39..4442cc5602d45 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -4322,6 +4322,9 @@ int drm_dp_atomic_release_time_slots(struct 
> drm_atomic_state *state,
>   return -EINVAL;
>   }
>  
> + if (new_conn_state->crtc)
> +