[Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Add "standalone media" support for MTL (rev5)
== Series Details == Series: i915: Add "standalone media" support for MTL (rev5) URL : https://patchwork.freedesktop.org/series/107908/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12101_full -> Patchwork_107908v5_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_107908v5_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_107908v5_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 9) -- Missing(1): shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_107908v5_full: ### IGT changes ### Possible regressions * igt@i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12101/shard-tglb1/igt@i915_module_l...@reload-with-fault-injection.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/shard-tglb2/igt@i915_module_l...@reload-with-fault-injection.html Known issues Here are the changes found in Patchwork_107908v5_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@reset-stress: - shard-tglb: [PASS][3] -> [FAIL][4] ([i915#5784]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12101/shard-tglb3/igt@gem_...@reset-stress.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/shard-tglb2/igt@gem_...@reset-stress.html * igt@gem_exec_balancer@parallel-balancer: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12101/shard-iclb2/igt@gem_exec_balan...@parallel-balancer.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/shard-iclb6/igt@gem_exec_balan...@parallel-balancer.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12101/shard-glk8/igt@gem_exec_fair@basic-pace-s...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/shard-glk1/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12101/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/shard-iclb2/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_userptr_blits@input-checking: - shard-tglb: NOTRUN -> [DMESG-WARN][11] ([i915#4991]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/shard-tglb7/igt@gem_userptr_bl...@input-checking.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][12] -> [FAIL][13] ([i915#454]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12101/shard-iclb7/igt@i915_pm...@dc6-dpms.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/shard-iclb3/igt@i915_pm...@dc6-dpms.html * igt@i915_selftest@live@hangcheck: - shard-tglb: [PASS][14] -> [DMESG-WARN][15] ([i915#5591]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12101/shard-tglb6/igt@i915_selftest@l...@hangcheck.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/shard-tglb2/igt@i915_selftest@l...@hangcheck.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][16] -> [DMESG-WARN][17] ([i915#180]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12101/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/shard-apl7/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [PASS][18] -> [FAIL][19] ([i915#72]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12101/shard-glk7/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/shard-glk6/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size: - shard-glk: [PASS][20] -> [FAIL][21] ([i915#2346]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12101/shard-glk9/igt@kms_cursor_legacy@flip-vs-cur...@atomic-transitions-varying-size.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/shard-glk3/igt@kms_cursor_legacy@flip-vs-cur...@atomic-transitions-varying-size.html *
Re: [Intel-gfx] [PATCH v3 02/15] mei: add support to GSC extended header
On Thu, Sep 08, 2022 at 09:24:07PM +, Winkler, Tomas wrote: > > > > > On Fri, Aug 19, 2022 at 03:53:22PM -0700, Daniele Ceraolo Spurio wrote: > > > --- a/drivers/misc/mei/hw-me.c > > > +++ b/drivers/misc/mei/hw-me.c > > > @@ -590,7 +590,10 @@ static int mei_me_hbuf_write(struct mei_device > > *dev, > > > u32 dw_cnt; > > > int empty_slots; > > > > > > - if (WARN_ON(!hdr || !data || hdr_len & 0x3)) > > > + if (WARN_ON(!hdr || hdr_len & 0x3)) > > > + return -EINVAL; > > > + > > > + if (WARN_ON(!data && data_len)) > > > > Do not add more WARN_ON() calls, please just handle this properly and do > > not reboot people's machines for a coding error :( > > As far as I understand WARN_ON() will produce solely a backtrace , Except when you have panic_on_warn() enabled in your systems, as many do :( > This particular condition should never ever happen in theory, Then don't check it! > anyhow we can use dev_err() here as well. That would be best. thanks, greg k-h
Re: [Intel-gfx] [PATCHv3] drm/i915: Support Async Flip on Linear buffers
Gentle Reminder!
> -Original Message-
> From: Murthy, Arun R
> Sent: Tuesday, September 6, 2022 9:18 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: ville.syrj...@linux.intel.com; Murthy, Arun R
> Subject: [PATCHv3] drm/i915: Support Async Flip on Linear buffers
>
> Starting from Gen12 Async Flip is supported on linear buffers.
> This patch enables support for async on linear buffer.
>
> UseCase: In Hybrid graphics, for hardware unsupported pixel formats it will
> be converted to linear memory and then composed.
>
> v2: Added use case
> v3: Added FIXME for ICL indicating the restrictions
>
> Signed-off-by: Arun R Murthy
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index be7cff722196..1880cfe70a7d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6610,6 +6610,20 @@ static int intel_async_flip_check_hw(struct
> intel_atomic_state *state, struct in
>* this selectively if required.
>*/
> switch (new_plane_state->hw.fb->modifier) {
> + case DRM_FORMAT_MOD_LINEAR:
> + /*
> + * FIXME: Async on Linear buffer is supported on ICL
> as
> + * but with additional alignment and fbc restrictions
> + * need to be taken care of. These aren't applicable
> for
> + * gen12+.
> + */
> + if (DISPLAY_VER(i915) < 12) {
> + drm_dbg_kms(>drm,
> + "[PLANE:%d:%s] Modifier does not
> support async flips\n",
> + plane->base.base.id, plane-
> >base.name);
> + return -EINVAL;
> + }
> +
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> --
> 2.25.1
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: A couple of if/else ladder refactors
== Series Details == Series: drm/i915: A couple of if/else ladder refactors URL : https://patchwork.freedesktop.org/series/108315/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12100_full -> Patchwork_108315v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_108315v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_108315v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 11) -- Additional (1): shard-rkl Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_108315v1_full: ### IGT changes ### Possible regressions * igt@kms_panel_fitting@atomic-fastset@pipe-b-edp-1: - shard-iclb: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/shard-iclb7/igt@kms_panel_fitting@atomic-fast...@pipe-b-edp-1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/shard-iclb2/igt@kms_panel_fitting@atomic-fast...@pipe-b-edp-1.html Known issues Here are the changes found in Patchwork_108315v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@detached-shared-gtt: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/shard-snb6/igt@gem_ctx_sha...@detached-shared-gtt.html * igt@gem_eio@kms: - shard-tglb: [PASS][4] -> [FAIL][5] ([i915#5784]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/shard-tglb6/igt@gem_...@kms.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/shard-tglb2/igt@gem_...@kms.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][6] -> [TIMEOUT][7] ([i915#3063]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/shard-tglb3/igt@gem_...@unwedge-stress.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/shard-tglb1/igt@gem_...@unwedge-stress.html * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/shard-iclb1/igt@gem_exec_balan...@parallel.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/shard-iclb6/igt@gem_exec_balan...@parallel.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/shard-apl2/igt@gem_exec_fair@basic-none-s...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][12] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/shard-iclb5/igt@gem_exec_fair@basic-p...@bcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/shard-iclb3/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/shard-glk5/igt@gem_exec_fair@basic-throt...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/shard-glk8/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_params@no-bsd: - shard-iclb: NOTRUN -> [SKIP][17] ([fdo#109283]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/shard-iclb4/igt@gem_exec_par...@no-bsd.html * igt@gem_lmem_swapping@heavy-verify-random-ccs: - shard-iclb: NOTRUN -> [SKIP][18] ([i915#4613]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/shard-iclb4/igt@gem_lmem_swapp...@heavy-verify-random-ccs.html * igt@gem_pxp@verify-pxp-stale-buf-optout-execution: - shard-iclb: NOTRUN -> [SKIP][19] ([i915#4270]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/shard-iclb4/igt@gem_...@verify-pxp-stale-buf-optout-execution.html * igt@gen3_render_tiledy_blits: - shard-iclb: NOTRUN -> [SKIP][20] ([fdo#109289]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/shard-iclb4/igt@gen3_render_tiledy_blits.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][21] -> [FAIL][22] ([i915#454])
[Intel-gfx] ✓ Fi.CI.BAT: success for i915: CAGF and RC6 changes for MTL (rev3)
== Series Details == Series: i915: CAGF and RC6 changes for MTL (rev3) URL : https://patchwork.freedesktop.org/series/108156/ State : success == Summary == CI Bug Log - changes from CI_DRM_12102 -> Patchwork_108156v3 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/index.html Participating hosts (40 -> 39) -- Missing(1): fi-bdw-samus Known issues Here are the changes found in Patchwork_108156v3 that come from known issues: ### IGT changes ### Possible fixes * igt@kms_busy@basic@flip: - fi-glk-dsi: [DMESG-WARN][1] -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/fi-glk-dsi/igt@kms_busy@ba...@flip.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/fi-glk-dsi/igt@kms_busy@ba...@flip.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size: - fi-bsw-kefka: [FAIL][3] ([i915#6298]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12102/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298 Build changes - * Linux: CI_DRM_12102 -> Patchwork_108156v3 CI-20190529: 20190529 CI_DRM_12102: 6085ea6ed71fd1317b644b898d22371bf715f450 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6649: 7d91a6952dadaa9001b662ed60c08ccb8364929d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_108156v3: 6085ea6ed71fd1317b644b898d22371bf715f450 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits cbf664ead393 drm/i915/mtl: Add C6 residency support for MTL SAMedia a9ae6a14a279 drm/i915/mtl: Modify CAGF functions for MTL 776fb460f689 drm/i915: Use GEN12 RPSTAT register c3a738c0d899 drm/i915/xelpmp: Expose media as another GT e13422c54e46 drm/i915: Rename and expose common GT early init routine ebfdf4bea986 drm/i915: Prepare more multi-GT initialization == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v3/index.html
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Tidy up vfio_device life cycle (rev6)
== Series Details == Series: Tidy up vfio_device life cycle (rev6) URL : https://patchwork.freedesktop.org/series/107838/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/107838/revisions/6/mbox/ not applied Applying: vfio: Add helpers for unifying vfio_device life cycle Applying: vfio/pci: Use the new device life cycle helpers Applying: vfio/mlx5: Use the new device life cycle helpers error: sha1 information is lacking or useless (drivers/vfio/pci/mlx5/main.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0003 vfio/mlx5: Use the new device life cycle helpers When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: CAGF and RC6 changes for MTL (rev3)
== Series Details == Series: i915: CAGF and RC6 changes for MTL (rev3) URL : https://patchwork.freedesktop.org/series/108156/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: CAGF and RC6 changes for MTL (rev3)
== Series Details == Series: i915: CAGF and RC6 changes for MTL (rev3) URL : https://patchwork.freedesktop.org/series/108156/ State : warning == Summary == Error: dim checkpatch failed fe6011b91b65 drm/i915: Prepare more multi-GT initialization -:79: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "gtdef->setup" #79: FILE: drivers/gpu/drm/i915/gt/intel_gt.c:853: +gtdef->setup != NULL; total: 0 errors, 0 warnings, 1 checks, 148 lines checked d5f7643cf88d drm/i915: Rename and expose common GT early init routine ab6b4b22253c drm/i915/xelpmp: Expose media as another GT Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:83: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #83: new file mode 100644 -:119: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!uncore->regs" #119: FILE: drivers/gpu/drm/i915/gt/intel_sa_media.c:32: + if (drm_WARN_ON(>drm, uncore->regs == NULL)) total: 0 errors, 1 warnings, 1 checks, 233 lines checked 2343a96e7807 drm/i915: Use GEN12 RPSTAT register b74e84ff6b00 drm/i915/mtl: Modify CAGF functions for MTL d993f6987b09 drm/i915/mtl: Add C6 residency support for MTL SAMedia
Re: [Intel-gfx] [PATCH v2 15/15] vfio: Add struct device to vfio_device
> From: Jason Gunthorpe > Sent: Thursday, September 8, 2022 8:37 PM > > On Thu, Sep 08, 2022 at 11:39:07AM +0200, Eric Auger wrote: > > > >> I am not totally clear about remaining 'struct device *dev;' in > > >> vfio_device struct. I see it used in some places. Is it supposed to > > >> disappear at some point? > > > > > > no, Eric. *dev will not disappear, it stores the dev pointet passed in by > > > caller of vfio_init_device(). > > > > yeah I see but you have device->device.parent = device->dev; > > IIRC we have a number of these redundancies now, often the drivers > store another copy of the dev too. > > A significant use of dev is for printing things, what should be done > here is to create a subsystem wide vfio_warn/etc that takes in the > vfio_device, and then print properly from there. Now that we have a > struct device all the prints should also include the VFIO struct > device name, and then the PCI device perhaps in brackets. > Let me handle it in a separate patch (after this series).
[Intel-gfx] [PATCH v3 15/15] vfio: Add struct device to vfio_device
From: Yi Liu
and replace kref. With it a 'vfio-dev/vfioX' node is created under the
sysfs path of the parent, indicating the device is bound to a vfio
driver, e.g.:
/sys/devices/pci\:6f/\:6f\:01.0/vfio-dev/vfio0
It is also a preparatory step toward adding cdev for supporting future
device-oriented uAPI.
Add Documentation/ABI/testing/sysfs-devices-vfio-dev.
Also take this chance to rename chardev 'vfio' to 'vfio-group' in
/proc/devices.
Suggested-by: Jason Gunthorpe
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
---
.../ABI/testing/sysfs-devices-vfio-dev| 8 +++
MAINTAINERS | 1 +
drivers/vfio/vfio_main.c | 67 +++
include/linux/vfio.h | 6 +-
4 files changed, 67 insertions(+), 15 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-devices-vfio-dev
diff --git a/Documentation/ABI/testing/sysfs-devices-vfio-dev
b/Documentation/ABI/testing/sysfs-devices-vfio-dev
new file mode 100644
index ..e21424fd9666
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-devices-vfio-dev
@@ -0,0 +1,8 @@
+What: /sys/...//vfio-dev/vfioX/
+Date: September 2022
+Contact:Yi Liu
+Description:
+This directory is created when the device is bound to a
+vfio driver. The layout under this directory matches what
+exists for a standard 'struct device'. 'X' is a unique
+index marking this device in vfio.
diff --git a/MAINTAINERS b/MAINTAINERS
index d30f26e07cd3..02c8f11b1c17 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21312,6 +21312,7 @@ R: Cornelia Huck
L: k...@vger.kernel.org
S: Maintained
T: git git://github.com/awilliam/linux-vfio.git
+F: Documentation/ABI/testing/sysfs-devices-vfio-dev
F: Documentation/driver-api/vfio.rst
F: drivers/vfio/
F: include/linux/vfio.h
diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index 37cbd10f3faf..cd23d35c878c 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -49,6 +49,8 @@ static struct vfio {
struct mutexgroup_lock; /* locks group_list */
struct ida group_ida;
dev_t group_devt;
+ struct class*device_class;
+ struct ida device_ida;
} vfio;
struct vfio_iommu_driver {
@@ -485,12 +487,13 @@ static struct vfio_device *vfio_group_get_device(struct
vfio_group *group,
* VFIO driver API
*/
/* Release helper called by vfio_put_device() */
-void vfio_device_release(struct kref *kref)
+static void vfio_device_release(struct device *dev)
{
struct vfio_device *device =
- container_of(kref, struct vfio_device, kref);
+ container_of(dev, struct vfio_device, device);
vfio_release_device_set(device);
+ ida_free(_ida, device->index);
/*
* kvfree() cannot be done here due to a life cycle mess in
@@ -500,7 +503,6 @@ void vfio_device_release(struct kref *kref)
*/
device->ops->release(device);
}
-EXPORT_SYMBOL_GPL(vfio_device_release);
/*
* Alloc and initialize vfio_device so it can be registered to vfio
@@ -548,6 +550,13 @@ int vfio_init_device(struct vfio_device *device, struct
device *dev,
{
int ret;
+ ret = ida_alloc_max(_ida, MINORMASK, GFP_KERNEL);
+ if (ret < 0) {
+ dev_dbg(dev, "Error to alloc index\n");
+ return ret;
+ }
+
+ device->index = ret;
init_completion(>comp);
device->dev = dev;
device->ops = ops;
@@ -558,11 +567,15 @@ int vfio_init_device(struct vfio_device *device, struct
device *dev,
goto out_uninit;
}
- kref_init(>kref);
+ device_initialize(>device);
+ device->device.release = vfio_device_release;
+ device->device.class = vfio.device_class;
+ device->device.parent = device->dev;
return 0;
out_uninit:
vfio_release_device_set(device);
+ ida_free(_ida, device->index);
return ret;
}
EXPORT_SYMBOL_GPL(vfio_init_device);
@@ -659,6 +672,7 @@ static int __vfio_register_dev(struct vfio_device *device,
struct vfio_group *group)
{
struct vfio_device *existing_device;
+ int ret;
if (IS_ERR(group))
return PTR_ERR(group);
@@ -675,16 +689,21 @@ static int __vfio_register_dev(struct vfio_device *device,
dev_WARN(device->dev, "Device already exists on group %d\n",
iommu_group_id(group->iommu_group));
vfio_device_put_registration(existing_device);
- if (group->type == VFIO_NO_IOMMU ||
- group->type == VFIO_EMULATED_IOMMU)
-
[Intel-gfx] [PATCH v3 14/15] vfio: Rename vfio_device_put() and vfio_device_try_get()
With the addition of vfio_put_device() now the names become confusing.
vfio_put_device() is clear from object life cycle p.o.v given kref.
vfio_device_put()/vfio_device_try_get() are helpers for tracking
users on a registered device.
Now rename them:
- vfio_device_put() -> vfio_device_put_registration()
- vfio_device_try_get() -> vfio_device_try_get_registration()
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
Reviewed-by: Eric Auger
---
drivers/vfio/vfio_main.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index 5bc221730d7b..37cbd10f3faf 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -453,13 +453,13 @@ static void vfio_group_get(struct vfio_group *group)
* Device objects - create, release, get, put, search
*/
/* Device reference always implies a group reference */
-static void vfio_device_put(struct vfio_device *device)
+static void vfio_device_put_registration(struct vfio_device *device)
{
if (refcount_dec_and_test(>refcount))
complete(>comp);
}
-static bool vfio_device_try_get(struct vfio_device *device)
+static bool vfio_device_try_get_registration(struct vfio_device *device)
{
return refcount_inc_not_zero(>refcount);
}
@@ -471,7 +471,8 @@ static struct vfio_device *vfio_group_get_device(struct
vfio_group *group,
mutex_lock(>device_lock);
list_for_each_entry(device, >device_list, group_next) {
- if (device->dev == dev && vfio_device_try_get(device)) {
+ if (device->dev == dev &&
+ vfio_device_try_get_registration(device)) {
mutex_unlock(>device_lock);
return device;
}
@@ -673,7 +674,7 @@ static int __vfio_register_dev(struct vfio_device *device,
if (existing_device) {
dev_WARN(device->dev, "Device already exists on group %d\n",
iommu_group_id(group->iommu_group));
- vfio_device_put(existing_device);
+ vfio_device_put_registration(existing_device);
if (group->type == VFIO_NO_IOMMU ||
group->type == VFIO_EMULATED_IOMMU)
iommu_group_remove_device(device->dev);
@@ -731,7 +732,7 @@ static struct vfio_device *vfio_device_get_from_name(struct
vfio_group *group,
ret = !strcmp(dev_name(it->dev), buf);
}
- if (ret && vfio_device_try_get(it)) {
+ if (ret && vfio_device_try_get_registration(it)) {
device = it;
break;
}
@@ -751,7 +752,7 @@ void vfio_unregister_group_dev(struct vfio_device *device)
bool interrupted = false;
long rc;
- vfio_device_put(device);
+ vfio_device_put_registration(device);
rc = try_wait_for_completion(>comp);
while (rc <= 0) {
if (device->ops->request)
@@ -1311,7 +1312,7 @@ static int vfio_group_ioctl_get_device_fd(struct
vfio_group *group,
err_put_fdno:
put_unused_fd(fdno);
err_put_device:
- vfio_device_put(device);
+ vfio_device_put_registration(device);
return ret;
}
@@ -1493,7 +1494,7 @@ static int vfio_device_fops_release(struct inode *inode,
struct file *filep)
vfio_device_unassign_container(device);
- vfio_device_put(device);
+ vfio_device_put_registration(device);
return 0;
}
--
2.21.3
[Intel-gfx] [PATCH v3 13/15] vfio/ccw: Use the new device life cycle helpers
ccw is the only exception which cannot use vfio_alloc_device() because
its private device structure is designed to serve both mdev and parent.
Life cycle of the parent is managed by css_driver so vfio_ccw_private
must be allocated/freed in css_driver probe/remove path instead of
conforming to vfio core life cycle for mdev.
Given that use a wait/completion scheme so the mdev remove path waits
after vfio_put_device() until receiving a completion notification from
@release. The completion indicates that all active references on
vfio_device have been released.
After that point although free of vfio_ccw_private is delayed to
css_driver it's at least guaranteed to have no parallel reference on
released vfio device part from other code paths.
memset() in @probe is removed. vfio_device is either already cleared
when probed for the first time or cleared in @release from last probe.
The right fix is to introduce separate structures for mdev and parent,
but this won't happen in short term per prior discussions.
Remove vfio_init/uninit_group_dev() as no user now.
Suggested-by: Jason Gunthorpe
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
Reviewed-by: Eric Farman
---
drivers/s390/cio/vfio_ccw_ops.c | 52 +
drivers/s390/cio/vfio_ccw_private.h | 3 ++
drivers/vfio/vfio_main.c| 23 +++--
include/linux/vfio.h| 3 --
4 files changed, 53 insertions(+), 28 deletions(-)
diff --git a/drivers/s390/cio/vfio_ccw_ops.c b/drivers/s390/cio/vfio_ccw_ops.c
index 4a806a2273b5..9f8486c0d3d3 100644
--- a/drivers/s390/cio/vfio_ccw_ops.c
+++ b/drivers/s390/cio/vfio_ccw_ops.c
@@ -87,6 +87,15 @@ static struct attribute_group *mdev_type_groups[] = {
NULL,
};
+static int vfio_ccw_mdev_init_dev(struct vfio_device *vdev)
+{
+ struct vfio_ccw_private *private =
+ container_of(vdev, struct vfio_ccw_private, vdev);
+
+ init_completion(>release_comp);
+ return 0;
+}
+
static int vfio_ccw_mdev_probe(struct mdev_device *mdev)
{
struct vfio_ccw_private *private = dev_get_drvdata(mdev->dev.parent);
@@ -98,9 +107,9 @@ static int vfio_ccw_mdev_probe(struct mdev_device *mdev)
if (atomic_dec_if_positive(>avail) < 0)
return -EPERM;
- memset(>vdev, 0, sizeof(private->vdev));
- vfio_init_group_dev(>vdev, >dev,
- _ccw_dev_ops);
+ ret = vfio_init_device(>vdev, >dev, _ccw_dev_ops);
+ if (ret)
+ return ret;
VFIO_CCW_MSG_EVENT(2, "sch %x.%x.%04x: create\n",
private->sch->schid.cssid,
@@ -109,16 +118,33 @@ static int vfio_ccw_mdev_probe(struct mdev_device *mdev)
ret = vfio_register_emulated_iommu_dev(>vdev);
if (ret)
- goto err_atomic;
+ goto err_put_vdev;
dev_set_drvdata(>dev, private);
return 0;
-err_atomic:
- vfio_uninit_group_dev(>vdev);
+err_put_vdev:
+ vfio_put_device(>vdev);
atomic_inc(>avail);
return ret;
}
+static void vfio_ccw_mdev_release_dev(struct vfio_device *vdev)
+{
+ struct vfio_ccw_private *private =
+ container_of(vdev, struct vfio_ccw_private, vdev);
+
+ /*
+* We cannot free vfio_ccw_private here because it includes
+* parent info which must be free'ed by css driver.
+*
+* Use a workaround by memset'ing the core device part and
+* then notifying the remove path that all active references
+* to this device have been released.
+*/
+ memset(vdev, 0, sizeof(*vdev));
+ complete(>release_comp);
+}
+
static void vfio_ccw_mdev_remove(struct mdev_device *mdev)
{
struct vfio_ccw_private *private = dev_get_drvdata(mdev->dev.parent);
@@ -130,7 +156,17 @@ static void vfio_ccw_mdev_remove(struct mdev_device *mdev)
vfio_unregister_group_dev(>vdev);
- vfio_uninit_group_dev(>vdev);
+ vfio_put_device(>vdev);
+ /*
+* Wait for all active references on mdev are released so it
+* is safe to defer kfree() to a later point.
+*
+* TODO: the clean fix is to split parent/mdev info from ccw
+* private structure so each can be managed in its own life
+* cycle.
+*/
+ wait_for_completion(>release_comp);
+
atomic_inc(>avail);
}
@@ -592,6 +628,8 @@ static void vfio_ccw_mdev_request(struct vfio_device *vdev,
unsigned int count)
}
static const struct vfio_device_ops vfio_ccw_dev_ops = {
+ .init = vfio_ccw_mdev_init_dev,
+ .release = vfio_ccw_mdev_release_dev,
.open_device = vfio_ccw_mdev_open_device,
.close_device = vfio_ccw_mdev_close_device,
.read = vfio_ccw_mdev_read,
diff --git a/drivers/s390/cio/vfio_ccw_private.h
b/drivers/s390/cio/vfio_ccw_private.h
index cd24b7fada91..63d9202b29c7 100644
--- a/drivers/s390/cio/vfio_ccw_private.h
+++ b/drivers/s390/cio/vfio_ccw_private.h
[Intel-gfx] [PATCH v3 12/15] vfio/amba: Use the new device life cycle helpers
Implement amba's own vfio_device_ops.
Remove vfio_platform_probe/remove_common() given no user now.
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
Reviewed-by: Eric Auger
---
drivers/vfio/platform/vfio_amba.c | 72 ++-
drivers/vfio/platform/vfio_platform_common.c | 60
drivers/vfio/platform/vfio_platform_private.h | 3 -
3 files changed, 55 insertions(+), 80 deletions(-)
diff --git a/drivers/vfio/platform/vfio_amba.c
b/drivers/vfio/platform/vfio_amba.c
index 1aaa4f721bd2..eaea63e5294c 100644
--- a/drivers/vfio/platform/vfio_amba.c
+++ b/drivers/vfio/platform/vfio_amba.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include
#include "vfio_platform_private.h"
@@ -40,20 +41,16 @@ static int get_amba_irq(struct vfio_platform_device *vdev,
int i)
return ret ? ret : -ENXIO;
}
-static int vfio_amba_probe(struct amba_device *adev, const struct amba_id *id)
+static int vfio_amba_init_dev(struct vfio_device *core_vdev)
{
- struct vfio_platform_device *vdev;
+ struct vfio_platform_device *vdev =
+ container_of(core_vdev, struct vfio_platform_device, vdev);
+ struct amba_device *adev = to_amba_device(core_vdev->dev);
int ret;
- vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
- if (!vdev)
- return -ENOMEM;
-
vdev->name = kasprintf(GFP_KERNEL, "vfio-amba-%08x", adev->periphid);
- if (!vdev->name) {
- kfree(vdev);
+ if (!vdev->name)
return -ENOMEM;
- }
vdev->opaque = (void *) adev;
vdev->flags = VFIO_DEVICE_FLAGS_AMBA;
@@ -61,26 +58,67 @@ static int vfio_amba_probe(struct amba_device *adev, const
struct amba_id *id)
vdev->get_irq = get_amba_irq;
vdev->reset_required = false;
- ret = vfio_platform_probe_common(vdev, >dev);
- if (ret) {
+ ret = vfio_platform_init_common(vdev);
+ if (ret)
kfree(vdev->name);
- kfree(vdev);
- return ret;
- }
+ return ret;
+}
+
+static const struct vfio_device_ops vfio_amba_ops;
+static int vfio_amba_probe(struct amba_device *adev, const struct amba_id *id)
+{
+ struct vfio_platform_device *vdev;
+ int ret;
+
+ vdev = vfio_alloc_device(vfio_platform_device, vdev, >dev,
+_amba_ops);
+ if (IS_ERR(vdev))
+ return PTR_ERR(vdev);
+ ret = vfio_register_group_dev(>vdev);
+ if (ret)
+ goto out_put_vdev;
+
+ pm_runtime_enable(>dev);
dev_set_drvdata(>dev, vdev);
return 0;
+
+out_put_vdev:
+ vfio_put_device(>vdev);
+ return ret;
+}
+
+static void vfio_amba_release_dev(struct vfio_device *core_vdev)
+{
+ struct vfio_platform_device *vdev =
+ container_of(core_vdev, struct vfio_platform_device, vdev);
+
+ vfio_platform_release_common(vdev);
+ kfree(vdev->name);
+ vfio_free_device(core_vdev);
}
static void vfio_amba_remove(struct amba_device *adev)
{
struct vfio_platform_device *vdev = dev_get_drvdata(>dev);
- vfio_platform_remove_common(vdev);
- kfree(vdev->name);
- kfree(vdev);
+ vfio_unregister_group_dev(>vdev);
+ pm_runtime_disable(vdev->device);
+ vfio_put_device(>vdev);
}
+static const struct vfio_device_ops vfio_amba_ops = {
+ .name = "vfio-amba",
+ .init = vfio_amba_init_dev,
+ .release= vfio_amba_release_dev,
+ .open_device= vfio_platform_open_device,
+ .close_device = vfio_platform_close_device,
+ .ioctl = vfio_platform_ioctl,
+ .read = vfio_platform_read,
+ .write = vfio_platform_write,
+ .mmap = vfio_platform_mmap,
+};
+
static const struct amba_id pl330_ids[] = {
{ 0, 0 },
};
diff --git a/drivers/vfio/platform/vfio_platform_common.c
b/drivers/vfio/platform/vfio_platform_common.c
index 4c01bf0adebb..55dc4f43c31e 100644
--- a/drivers/vfio/platform/vfio_platform_common.c
+++ b/drivers/vfio/platform/vfio_platform_common.c
@@ -605,16 +605,6 @@ int vfio_platform_mmap(struct vfio_device *core_vdev,
struct vm_area_struct *vma
}
EXPORT_SYMBOL_GPL(vfio_platform_mmap);
-static const struct vfio_device_ops vfio_platform_ops = {
- .name = "vfio-platform",
- .open_device= vfio_platform_open_device,
- .close_device = vfio_platform_close_device,
- .ioctl = vfio_platform_ioctl,
- .read = vfio_platform_read,
- .write = vfio_platform_write,
- .mmap = vfio_platform_mmap,
-};
-
static int vfio_platform_of_probe(struct vfio_platform_device *vdev,
struct device *dev)
{
@@ -674,56 +664,6 @@ void vfio_platform_release_common(struct
vfio_platform_device *vdev)
}
[Intel-gfx] [PATCH v3 05/15] vfio/mdpy: Use the new device life cycle helpers
From: Yi Liu
and manage mdpy_count inside @init/@release.
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
---
samples/vfio-mdev/mdpy.c | 81 +++-
1 file changed, 47 insertions(+), 34 deletions(-)
diff --git a/samples/vfio-mdev/mdpy.c b/samples/vfio-mdev/mdpy.c
index e8c46eb2e246..a07dac16d873 100644
--- a/samples/vfio-mdev/mdpy.c
+++ b/samples/vfio-mdev/mdpy.c
@@ -216,61 +216,77 @@ static int mdpy_reset(struct mdev_state *mdev_state)
return 0;
}
-static int mdpy_probe(struct mdev_device *mdev)
+static int mdpy_init_dev(struct vfio_device *vdev)
{
+ struct mdev_state *mdev_state =
+ container_of(vdev, struct mdev_state, vdev);
+ struct mdev_device *mdev = to_mdev_device(vdev->dev);
const struct mdpy_type *type =
_types[mdev_get_type_group_id(mdev)];
- struct device *dev = mdev_dev(mdev);
- struct mdev_state *mdev_state;
u32 fbsize;
- int ret;
+ int ret = -ENOMEM;
if (mdpy_count >= max_devices)
- return -ENOMEM;
-
- mdev_state = kzalloc(sizeof(struct mdev_state), GFP_KERNEL);
- if (mdev_state == NULL)
- return -ENOMEM;
- vfio_init_group_dev(_state->vdev, >dev, _dev_ops);
+ return ret;
mdev_state->vconfig = kzalloc(MDPY_CONFIG_SPACE_SIZE, GFP_KERNEL);
- if (mdev_state->vconfig == NULL) {
- ret = -ENOMEM;
- goto err_state;
- }
+ if (!mdev_state->vconfig)
+ return ret;
fbsize = roundup_pow_of_two(type->width * type->height * type->bytepp);
mdev_state->memblk = vmalloc_user(fbsize);
- if (!mdev_state->memblk) {
- ret = -ENOMEM;
- goto err_vconfig;
- }
- dev_info(dev, "%s: %s (%dx%d)\n", __func__, type->name, type->width,
-type->height);
+ if (!mdev_state->memblk)
+ goto out_vconfig;
mutex_init(_state->ops_lock);
mdev_state->mdev = mdev;
- mdev_state->type= type;
+ mdev_state->type = type;
mdev_state->memsize = fbsize;
mdpy_create_config_space(mdev_state);
mdpy_reset(mdev_state);
+ dev_info(vdev->dev, "%s: %s (%dx%d)\n", __func__, type->name,
type->width,
+type->height);
+
mdpy_count++;
+ return 0;
+
+out_vconfig:
+ kfree(mdev_state->vconfig);
+ return ret;
+}
+
+static int mdpy_probe(struct mdev_device *mdev)
+{
+ struct mdev_state *mdev_state;
+ int ret;
+
+ mdev_state = vfio_alloc_device(mdev_state, vdev, >dev,
+ _dev_ops);
+ if (IS_ERR(mdev_state))
+ return PTR_ERR(mdev_state);
ret = vfio_register_emulated_iommu_dev(_state->vdev);
if (ret)
- goto err_mem;
+ goto err_put_vdev;
dev_set_drvdata(>dev, mdev_state);
return 0;
-err_mem:
+
+err_put_vdev:
+ vfio_put_device(_state->vdev);
+ return ret;
+}
+
+static void mdpy_release_dev(struct vfio_device *vdev)
+{
+ struct mdev_state *mdev_state =
+ container_of(vdev, struct mdev_state, vdev);
+
vfree(mdev_state->memblk);
-err_vconfig:
kfree(mdev_state->vconfig);
-err_state:
- vfio_uninit_group_dev(_state->vdev);
- kfree(mdev_state);
- return ret;
+ vfio_free_device(vdev);
+ mdpy_count--;
}
static void mdpy_remove(struct mdev_device *mdev)
@@ -280,12 +296,7 @@ static void mdpy_remove(struct mdev_device *mdev)
dev_info(>dev, "%s\n", __func__);
vfio_unregister_group_dev(_state->vdev);
- vfree(mdev_state->memblk);
- kfree(mdev_state->vconfig);
- vfio_uninit_group_dev(_state->vdev);
- kfree(mdev_state);
-
- mdpy_count--;
+ vfio_put_device(_state->vdev);
}
static ssize_t mdpy_read(struct vfio_device *vdev, char __user *buf,
@@ -708,6 +719,8 @@ static struct attribute_group *mdev_type_groups[] = {
};
static const struct vfio_device_ops mdpy_dev_ops = {
+ .init = mdpy_init_dev,
+ .release = mdpy_release_dev,
.read = mdpy_read,
.write = mdpy_write,
.ioctl = mdpy_ioctl,
--
2.21.3
[Intel-gfx] [PATCH v3 11/15] vfio/platform: Use the new device life cycle helpers
Move vfio_device_ops from platform core to platform drivers so device
specific init/cleanup can be added.
Introduce two new helpers vfio_platform_init/release_common() for the
use in driver @init/@release.
vfio_platform_probe/remove_common() will be deprecated.
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
Reviewed-by: Eric Auger
Tested-by: Eric Auger
---
drivers/vfio/platform/vfio_platform.c | 66 +++
drivers/vfio/platform/vfio_platform_common.c | 53 ---
drivers/vfio/platform/vfio_platform_private.h | 15 +
3 files changed, 111 insertions(+), 23 deletions(-)
diff --git a/drivers/vfio/platform/vfio_platform.c
b/drivers/vfio/platform/vfio_platform.c
index 04f40c5acfd6..82cedcebfd90 100644
--- a/drivers/vfio/platform/vfio_platform.c
+++ b/drivers/vfio/platform/vfio_platform.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include
#include "vfio_platform_private.h"
@@ -36,14 +37,11 @@ static int get_platform_irq(struct vfio_platform_device
*vdev, int i)
return platform_get_irq_optional(pdev, i);
}
-static int vfio_platform_probe(struct platform_device *pdev)
+static int vfio_platform_init_dev(struct vfio_device *core_vdev)
{
- struct vfio_platform_device *vdev;
- int ret;
-
- vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
- if (!vdev)
- return -ENOMEM;
+ struct vfio_platform_device *vdev =
+ container_of(core_vdev, struct vfio_platform_device, vdev);
+ struct platform_device *pdev = to_platform_device(core_vdev->dev);
vdev->opaque = (void *) pdev;
vdev->name = pdev->name;
@@ -52,24 +50,64 @@ static int vfio_platform_probe(struct platform_device *pdev)
vdev->get_irq = get_platform_irq;
vdev->reset_required = reset_required;
- ret = vfio_platform_probe_common(vdev, >dev);
- if (ret) {
- kfree(vdev);
- return ret;
- }
+ return vfio_platform_init_common(vdev);
+}
+
+static const struct vfio_device_ops vfio_platform_ops;
+static int vfio_platform_probe(struct platform_device *pdev)
+{
+ struct vfio_platform_device *vdev;
+ int ret;
+
+ vdev = vfio_alloc_device(vfio_platform_device, vdev, >dev,
+_platform_ops);
+ if (IS_ERR(vdev))
+ return PTR_ERR(vdev);
+
+ ret = vfio_register_group_dev(>vdev);
+ if (ret)
+ goto out_put_vdev;
+
+ pm_runtime_enable(>dev);
dev_set_drvdata(>dev, vdev);
return 0;
+
+out_put_vdev:
+ vfio_put_device(>vdev);
+ return ret;
+}
+
+static void vfio_platform_release_dev(struct vfio_device *core_vdev)
+{
+ struct vfio_platform_device *vdev =
+ container_of(core_vdev, struct vfio_platform_device, vdev);
+
+ vfio_platform_release_common(vdev);
+ vfio_free_device(core_vdev);
}
static int vfio_platform_remove(struct platform_device *pdev)
{
struct vfio_platform_device *vdev = dev_get_drvdata(>dev);
- vfio_platform_remove_common(vdev);
- kfree(vdev);
+ vfio_unregister_group_dev(>vdev);
+ pm_runtime_disable(vdev->device);
+ vfio_put_device(>vdev);
return 0;
}
+static const struct vfio_device_ops vfio_platform_ops = {
+ .name = "vfio-platform",
+ .init = vfio_platform_init_dev,
+ .release= vfio_platform_release_dev,
+ .open_device= vfio_platform_open_device,
+ .close_device = vfio_platform_close_device,
+ .ioctl = vfio_platform_ioctl,
+ .read = vfio_platform_read,
+ .write = vfio_platform_write,
+ .mmap = vfio_platform_mmap,
+};
+
static struct platform_driver vfio_platform_driver = {
.probe = vfio_platform_probe,
.remove = vfio_platform_remove,
diff --git a/drivers/vfio/platform/vfio_platform_common.c
b/drivers/vfio/platform/vfio_platform_common.c
index 256f55b84e70..4c01bf0adebb 100644
--- a/drivers/vfio/platform/vfio_platform_common.c
+++ b/drivers/vfio/platform/vfio_platform_common.c
@@ -218,7 +218,7 @@ static int vfio_platform_call_reset(struct
vfio_platform_device *vdev,
return -EINVAL;
}
-static void vfio_platform_close_device(struct vfio_device *core_vdev)
+void vfio_platform_close_device(struct vfio_device *core_vdev)
{
struct vfio_platform_device *vdev =
container_of(core_vdev, struct vfio_platform_device, vdev);
@@ -236,8 +236,9 @@ static void vfio_platform_close_device(struct vfio_device
*core_vdev)
vfio_platform_regions_cleanup(vdev);
vfio_platform_irq_cleanup(vdev);
}
+EXPORT_SYMBOL_GPL(vfio_platform_close_device);
-static int vfio_platform_open_device(struct vfio_device *core_vdev)
+int vfio_platform_open_device(struct vfio_device *core_vdev)
{
struct vfio_platform_device *vdev =
[Intel-gfx] [PATCH v3 08/15] drm/i915/gvt: Use the new device life cycle helpers
Move vfio_device to the start of intel_vgpu as required by the new
helpers.
Change intel_gvt_create_vgpu() to use intel_vgpu as the first param
as other vgpu helpers do.
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
Reviewed-by: Zhenyu Wang
---
drivers/gpu/drm/i915/gvt/gvt.h | 5 ++-
drivers/gpu/drm/i915/gvt/kvmgt.c | 52 ++--
drivers/gpu/drm/i915/gvt/vgpu.c | 33
3 files changed, 50 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 705689e64011..89fab7896fc6 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -172,6 +172,7 @@ struct intel_vgpu_submission {
#define KVMGT_DEBUGFS_FILENAME "kvmgt_nr_cache_entries"
struct intel_vgpu {
+ struct vfio_device vfio_device;
struct intel_gvt *gvt;
struct mutex vgpu_lock;
int id;
@@ -211,7 +212,6 @@ struct intel_vgpu {
u32 scan_nonprivbb;
- struct vfio_device vfio_device;
struct vfio_region *region;
int num_regions;
struct eventfd_ctx *intx_trigger;
@@ -494,8 +494,7 @@ void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt);
struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt);
void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu);
-struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
-struct intel_vgpu_type *type);
+int intel_gvt_create_vgpu(struct intel_vgpu *vgpu, struct intel_vgpu_type
*type);
void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);
void intel_gvt_release_vgpu(struct intel_vgpu *vgpu);
void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index e3cd58946477..41bba40feef8 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -1546,7 +1546,33 @@ static const struct attribute_group *intel_vgpu_groups[]
= {
NULL,
};
+static int intel_vgpu_init_dev(struct vfio_device *vfio_dev)
+{
+ struct mdev_device *mdev = to_mdev_device(vfio_dev->dev);
+ struct device *pdev = mdev_parent_dev(mdev);
+ struct intel_gvt *gvt = kdev_to_i915(pdev)->gvt;
+ struct intel_vgpu_type *type;
+ struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev);
+
+ type = >types[mdev_get_type_group_id(mdev)];
+ if (!type)
+ return -EINVAL;
+
+ vgpu->gvt = gvt;
+ return intel_gvt_create_vgpu(vgpu, type);
+}
+
+static void intel_vgpu_release_dev(struct vfio_device *vfio_dev)
+{
+ struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev);
+
+ intel_gvt_destroy_vgpu(vgpu);
+ vfio_free_device(vfio_dev);
+}
+
static const struct vfio_device_ops intel_vgpu_dev_ops = {
+ .init = intel_vgpu_init_dev,
+ .release= intel_vgpu_release_dev,
.open_device= intel_vgpu_open_device,
.close_device = intel_vgpu_close_device,
.read = intel_vgpu_read,
@@ -1558,35 +1584,28 @@ static const struct vfio_device_ops intel_vgpu_dev_ops
= {
static int intel_vgpu_probe(struct mdev_device *mdev)
{
- struct device *pdev = mdev_parent_dev(mdev);
- struct intel_gvt *gvt = kdev_to_i915(pdev)->gvt;
- struct intel_vgpu_type *type;
struct intel_vgpu *vgpu;
int ret;
- type = >types[mdev_get_type_group_id(mdev)];
- if (!type)
- return -EINVAL;
-
- vgpu = intel_gvt_create_vgpu(gvt, type);
+ vgpu = vfio_alloc_device(intel_vgpu, vfio_device, >dev,
+_vgpu_dev_ops);
if (IS_ERR(vgpu)) {
gvt_err("failed to create intel vgpu: %ld\n", PTR_ERR(vgpu));
return PTR_ERR(vgpu);
}
- vfio_init_group_dev(>vfio_device, >dev,
- _vgpu_dev_ops);
-
dev_set_drvdata(>dev, vgpu);
ret = vfio_register_emulated_iommu_dev(>vfio_device);
- if (ret) {
- intel_gvt_destroy_vgpu(vgpu);
- return ret;
- }
+ if (ret)
+ goto out_put_vdev;
gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n",
dev_name(mdev_dev(mdev)));
return 0;
+
+out_put_vdev:
+ vfio_put_device(>vfio_device);
+ return ret;
}
static void intel_vgpu_remove(struct mdev_device *mdev)
@@ -1595,7 +1614,8 @@ static void intel_vgpu_remove(struct mdev_device *mdev)
if (WARN_ON_ONCE(vgpu->attached))
return;
- intel_gvt_destroy_vgpu(vgpu);
+
+ vfio_put_device(>vfio_device);
}
static struct mdev_driver intel_vgpu_mdev_driver = {
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 46da19b3225d..5c533fbc2c8d 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -302,8 +302,6 @@
[Intel-gfx] [PATCH v3 10/15] vfio/fsl-mc: Use the new device life cycle helpers
From: Yi Liu
Also add a comment to mark that vfio core releases device_set if @init
fails.
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
---
drivers/vfio/fsl-mc/vfio_fsl_mc.c | 85 ++-
1 file changed, 49 insertions(+), 36 deletions(-)
diff --git a/drivers/vfio/fsl-mc/vfio_fsl_mc.c
b/drivers/vfio/fsl-mc/vfio_fsl_mc.c
index 42b344bd7cd5..b16874e913e4 100644
--- a/drivers/vfio/fsl-mc/vfio_fsl_mc.c
+++ b/drivers/vfio/fsl-mc/vfio_fsl_mc.c
@@ -418,16 +418,7 @@ static int vfio_fsl_mc_mmap(struct vfio_device *core_vdev,
return vfio_fsl_mc_mmap_mmio(vdev->regions[index], vma);
}
-static const struct vfio_device_ops vfio_fsl_mc_ops = {
- .name = "vfio-fsl-mc",
- .open_device= vfio_fsl_mc_open_device,
- .close_device = vfio_fsl_mc_close_device,
- .ioctl = vfio_fsl_mc_ioctl,
- .read = vfio_fsl_mc_read,
- .write = vfio_fsl_mc_write,
- .mmap = vfio_fsl_mc_mmap,
-};
-
+static const struct vfio_device_ops vfio_fsl_mc_ops;
static int vfio_fsl_mc_bus_notifier(struct notifier_block *nb,
unsigned long action, void *data)
{
@@ -518,35 +509,43 @@ static void vfio_fsl_uninit_device(struct
vfio_fsl_mc_device *vdev)
bus_unregister_notifier(_mc_bus_type, >nb);
}
-static int vfio_fsl_mc_probe(struct fsl_mc_device *mc_dev)
+static int vfio_fsl_mc_init_dev(struct vfio_device *core_vdev)
{
- struct vfio_fsl_mc_device *vdev;
- struct device *dev = _dev->dev;
+ struct vfio_fsl_mc_device *vdev =
+ container_of(core_vdev, struct vfio_fsl_mc_device, vdev);
+ struct fsl_mc_device *mc_dev = to_fsl_mc_device(core_vdev->dev);
int ret;
- vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
- if (!vdev)
- return -ENOMEM;
-
- vfio_init_group_dev(>vdev, dev, _fsl_mc_ops);
vdev->mc_dev = mc_dev;
mutex_init(>igate);
if (is_fsl_mc_bus_dprc(mc_dev))
- ret = vfio_assign_device_set(>vdev, _dev->dev);
+ ret = vfio_assign_device_set(core_vdev, _dev->dev);
else
- ret = vfio_assign_device_set(>vdev, mc_dev->dev.parent);
- if (ret)
- goto out_uninit;
+ ret = vfio_assign_device_set(core_vdev, mc_dev->dev.parent);
- ret = vfio_fsl_mc_init_device(vdev);
if (ret)
- goto out_uninit;
+ return ret;
+
+ /* device_set is released by vfio core if @init fails */
+ return vfio_fsl_mc_init_device(vdev);
+}
+
+static int vfio_fsl_mc_probe(struct fsl_mc_device *mc_dev)
+{
+ struct vfio_fsl_mc_device *vdev;
+ struct device *dev = _dev->dev;
+ int ret;
+
+ vdev = vfio_alloc_device(vfio_fsl_mc_device, vdev, dev,
+_fsl_mc_ops);
+ if (IS_ERR(vdev))
+ return PTR_ERR(vdev);
ret = vfio_register_group_dev(>vdev);
if (ret) {
dev_err(dev, "VFIO_FSL_MC: Failed to add to vfio group\n");
- goto out_device;
+ goto out_put_vdev;
}
ret = vfio_fsl_mc_scan_container(mc_dev);
@@ -557,30 +556,44 @@ static int vfio_fsl_mc_probe(struct fsl_mc_device *mc_dev)
out_group_dev:
vfio_unregister_group_dev(>vdev);
-out_device:
- vfio_fsl_uninit_device(vdev);
-out_uninit:
- vfio_uninit_group_dev(>vdev);
- kfree(vdev);
+out_put_vdev:
+ vfio_put_device(>vdev);
return ret;
}
+static void vfio_fsl_mc_release_dev(struct vfio_device *core_vdev)
+{
+ struct vfio_fsl_mc_device *vdev =
+ container_of(core_vdev, struct vfio_fsl_mc_device, vdev);
+
+ vfio_fsl_uninit_device(vdev);
+ mutex_destroy(>igate);
+ vfio_free_device(core_vdev);
+}
+
static int vfio_fsl_mc_remove(struct fsl_mc_device *mc_dev)
{
struct device *dev = _dev->dev;
struct vfio_fsl_mc_device *vdev = dev_get_drvdata(dev);
vfio_unregister_group_dev(>vdev);
- mutex_destroy(>igate);
-
dprc_remove_devices(mc_dev, NULL, 0);
- vfio_fsl_uninit_device(vdev);
-
- vfio_uninit_group_dev(>vdev);
- kfree(vdev);
+ vfio_put_device(>vdev);
return 0;
}
+static const struct vfio_device_ops vfio_fsl_mc_ops = {
+ .name = "vfio-fsl-mc",
+ .init = vfio_fsl_mc_init_dev,
+ .release= vfio_fsl_mc_release_dev,
+ .open_device= vfio_fsl_mc_open_device,
+ .close_device = vfio_fsl_mc_close_device,
+ .ioctl = vfio_fsl_mc_ioctl,
+ .read = vfio_fsl_mc_read,
+ .write = vfio_fsl_mc_write,
+ .mmap = vfio_fsl_mc_mmap,
+};
+
static struct fsl_mc_driver vfio_fsl_mc_driver = {
.probe = vfio_fsl_mc_probe,
.remove = vfio_fsl_mc_remove,
--
2.21.3
[Intel-gfx] [PATCH v3 07/15] vfio/mbochs: Use the new device life cycle helpers
From: Yi Liu
and manage avail_mbytes inside @init/@release.
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
---
samples/vfio-mdev/mbochs.c | 73 --
1 file changed, 46 insertions(+), 27 deletions(-)
diff --git a/samples/vfio-mdev/mbochs.c b/samples/vfio-mdev/mbochs.c
index 344c2901a82b..df95f25fbc0e 100644
--- a/samples/vfio-mdev/mbochs.c
+++ b/samples/vfio-mdev/mbochs.c
@@ -505,13 +505,14 @@ static int mbochs_reset(struct mdev_state *mdev_state)
return 0;
}
-static int mbochs_probe(struct mdev_device *mdev)
+static int mbochs_init_dev(struct vfio_device *vdev)
{
- int avail_mbytes = atomic_read(_avail_mbytes);
+ struct mdev_state *mdev_state =
+ container_of(vdev, struct mdev_state, vdev);
+ struct mdev_device *mdev = to_mdev_device(vdev->dev);
const struct mbochs_type *type =
_types[mdev_get_type_group_id(mdev)];
- struct device *dev = mdev_dev(mdev);
- struct mdev_state *mdev_state;
+ int avail_mbytes = atomic_read(_avail_mbytes);
int ret = -ENOMEM;
do {
@@ -520,14 +521,9 @@ static int mbochs_probe(struct mdev_device *mdev)
} while (!atomic_try_cmpxchg(_avail_mbytes, _mbytes,
avail_mbytes - type->mbytes));
- mdev_state = kzalloc(sizeof(struct mdev_state), GFP_KERNEL);
- if (mdev_state == NULL)
- goto err_avail;
- vfio_init_group_dev(_state->vdev, >dev, _dev_ops);
-
mdev_state->vconfig = kzalloc(MBOCHS_CONFIG_SPACE_SIZE, GFP_KERNEL);
- if (mdev_state->vconfig == NULL)
- goto err_mem;
+ if (!mdev_state->vconfig)
+ goto err_avail;
mdev_state->memsize = type->mbytes * 1024 * 1024;
mdev_state->pagecount = mdev_state->memsize >> PAGE_SHIFT;
@@ -535,10 +531,7 @@ static int mbochs_probe(struct mdev_device *mdev)
sizeof(struct page *),
GFP_KERNEL);
if (!mdev_state->pages)
- goto err_mem;
-
- dev_info(dev, "%s: %s, %d MB, %ld pages\n", __func__,
-type->name, type->mbytes, mdev_state->pagecount);
+ goto err_vconfig;
mutex_init(_state->ops_lock);
mdev_state->mdev = mdev;
@@ -553,19 +546,47 @@ static int mbochs_probe(struct mdev_device *mdev)
mbochs_create_config_space(mdev_state);
mbochs_reset(mdev_state);
+ dev_info(vdev->dev, "%s: %s, %d MB, %ld pages\n", __func__,
+type->name, type->mbytes, mdev_state->pagecount);
+ return 0;
+
+err_vconfig:
+ kfree(mdev_state->vconfig);
+err_avail:
+ atomic_add(type->mbytes, _avail_mbytes);
+ return ret;
+}
+
+static int mbochs_probe(struct mdev_device *mdev)
+{
+ struct mdev_state *mdev_state;
+ int ret = -ENOMEM;
+
+ mdev_state = vfio_alloc_device(mdev_state, vdev, >dev,
+ _dev_ops);
+ if (IS_ERR(mdev_state))
+ return PTR_ERR(mdev_state);
+
ret = vfio_register_emulated_iommu_dev(_state->vdev);
if (ret)
- goto err_mem;
+ goto err_put_vdev;
dev_set_drvdata(>dev, mdev_state);
return 0;
-err_mem:
- vfio_uninit_group_dev(_state->vdev);
+
+err_put_vdev:
+ vfio_put_device(_state->vdev);
+ return ret;
+}
+
+static void mbochs_release_dev(struct vfio_device *vdev)
+{
+ struct mdev_state *mdev_state =
+ container_of(vdev, struct mdev_state, vdev);
+
kfree(mdev_state->pages);
kfree(mdev_state->vconfig);
- kfree(mdev_state);
-err_avail:
- atomic_add(type->mbytes, _avail_mbytes);
- return ret;
+ vfio_free_device(vdev);
+ atomic_add(mdev_state->type->mbytes, _avail_mbytes);
}
static void mbochs_remove(struct mdev_device *mdev)
@@ -573,11 +594,7 @@ static void mbochs_remove(struct mdev_device *mdev)
struct mdev_state *mdev_state = dev_get_drvdata(>dev);
vfio_unregister_group_dev(_state->vdev);
- vfio_uninit_group_dev(_state->vdev);
- atomic_add(mdev_state->type->mbytes, _avail_mbytes);
- kfree(mdev_state->pages);
- kfree(mdev_state->vconfig);
- kfree(mdev_state);
+ vfio_put_device(_state->vdev);
}
static ssize_t mbochs_read(struct vfio_device *vdev, char __user *buf,
@@ -1397,6 +1414,8 @@ static struct attribute_group *mdev_type_groups[] = {
static const struct vfio_device_ops mbochs_dev_ops = {
.close_device = mbochs_close_device,
+ .init = mbochs_init_dev,
+ .release = mbochs_release_dev,
.read = mbochs_read,
.write = mbochs_write,
.ioctl = mbochs_ioctl,
--
2.21.3
[Intel-gfx] [PATCH v3 03/15] vfio/mlx5: Use the new device life cycle helpers
From: Yi Liu
mlx5 has its own @init/@release for handling migration cap.
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
---
drivers/vfio/pci/mlx5/main.c | 50 ++--
1 file changed, 36 insertions(+), 14 deletions(-)
diff --git a/drivers/vfio/pci/mlx5/main.c b/drivers/vfio/pci/mlx5/main.c
index 759a5f5f7b3f..fd6ccb8454a2 100644
--- a/drivers/vfio/pci/mlx5/main.c
+++ b/drivers/vfio/pci/mlx5/main.c
@@ -585,8 +585,35 @@ static const struct vfio_log_ops mlx5vf_pci_log_ops = {
.log_read_and_clear = mlx5vf_tracker_read_and_clear,
};
+static int mlx5vf_pci_init_dev(struct vfio_device *core_vdev)
+{
+ struct mlx5vf_pci_core_device *mvdev = container_of(core_vdev,
+ struct mlx5vf_pci_core_device, core_device.vdev);
+ int ret;
+
+ ret = vfio_pci_core_init_dev(core_vdev);
+ if (ret)
+ return ret;
+
+ mlx5vf_cmd_set_migratable(mvdev, _pci_mig_ops,
+ _pci_log_ops);
+
+ return 0;
+}
+
+static void mlx5vf_pci_release_dev(struct vfio_device *core_vdev)
+{
+ struct mlx5vf_pci_core_device *mvdev = container_of(core_vdev,
+ struct mlx5vf_pci_core_device, core_device.vdev);
+
+ mlx5vf_cmd_remove_migratable(mvdev);
+ vfio_pci_core_release_dev(core_vdev);
+}
+
static const struct vfio_device_ops mlx5vf_pci_ops = {
.name = "mlx5-vfio-pci",
+ .init = mlx5vf_pci_init_dev,
+ .release = mlx5vf_pci_release_dev,
.open_device = mlx5vf_pci_open_device,
.close_device = mlx5vf_pci_close_device,
.ioctl = vfio_pci_core_ioctl,
@@ -604,22 +631,19 @@ static int mlx5vf_pci_probe(struct pci_dev *pdev,
struct mlx5vf_pci_core_device *mvdev;
int ret;
- mvdev = kzalloc(sizeof(*mvdev), GFP_KERNEL);
- if (!mvdev)
- return -ENOMEM;
- vfio_pci_core_init_device(>core_device, pdev, _pci_ops);
- mlx5vf_cmd_set_migratable(mvdev, _pci_mig_ops,
- _pci_log_ops);
+ mvdev = vfio_alloc_device(mlx5vf_pci_core_device, core_device.vdev,
+ >dev, _pci_ops);
+ if (IS_ERR(mvdev))
+ return PTR_ERR(mvdev);
+
dev_set_drvdata(>dev, >core_device);
ret = vfio_pci_core_register_device(>core_device);
if (ret)
- goto out_free;
+ goto out_put_vdev;
return 0;
-out_free:
- mlx5vf_cmd_remove_migratable(mvdev);
- vfio_pci_core_uninit_device(>core_device);
- kfree(mvdev);
+out_put_vdev:
+ vfio_put_device(>core_device.vdev);
return ret;
}
@@ -628,9 +652,7 @@ static void mlx5vf_pci_remove(struct pci_dev *pdev)
struct mlx5vf_pci_core_device *mvdev = mlx5vf_drvdata(pdev);
vfio_pci_core_unregister_device(>core_device);
- mlx5vf_cmd_remove_migratable(mvdev);
- vfio_pci_core_uninit_device(>core_device);
- kfree(mvdev);
+ vfio_put_device(>core_device.vdev);
}
static const struct pci_device_id mlx5vf_pci_table[] = {
--
2.21.3
[Intel-gfx] [PATCH v3 09/15] vfio/ap: Use the new device life cycle helpers
From: Yi Liu
and manage available_instances inside @init/@release.
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Tony Krowiak
Reviewed-by: Jason Gunthorpe
---
drivers/s390/crypto/vfio_ap_ops.c | 50 ++-
1 file changed, 29 insertions(+), 21 deletions(-)
diff --git a/drivers/s390/crypto/vfio_ap_ops.c
b/drivers/s390/crypto/vfio_ap_ops.c
index 6c8c41fac4e1..803aadfd0876 100644
--- a/drivers/s390/crypto/vfio_ap_ops.c
+++ b/drivers/s390/crypto/vfio_ap_ops.c
@@ -684,42 +684,44 @@ static bool vfio_ap_mdev_filter_matrix(unsigned long
*apm, unsigned long *aqm,
AP_DOMAINS);
}
-static int vfio_ap_mdev_probe(struct mdev_device *mdev)
+static int vfio_ap_mdev_init_dev(struct vfio_device *vdev)
{
- struct ap_matrix_mdev *matrix_mdev;
- int ret;
+ struct ap_matrix_mdev *matrix_mdev =
+ container_of(vdev, struct ap_matrix_mdev, vdev);
if ((atomic_dec_if_positive(_dev->available_instances) < 0))
return -EPERM;
- matrix_mdev = kzalloc(sizeof(*matrix_mdev), GFP_KERNEL);
- if (!matrix_mdev) {
- ret = -ENOMEM;
- goto err_dec_available;
- }
- vfio_init_group_dev(_mdev->vdev, >dev,
- _ap_matrix_dev_ops);
-
- matrix_mdev->mdev = mdev;
+ matrix_mdev->mdev = to_mdev_device(vdev->dev);
vfio_ap_matrix_init(_dev->info, _mdev->matrix);
matrix_mdev->pqap_hook = handle_pqap;
vfio_ap_matrix_init(_dev->info, _mdev->shadow_apcb);
hash_init(matrix_mdev->qtable.queues);
+ return 0;
+}
+
+static int vfio_ap_mdev_probe(struct mdev_device *mdev)
+{
+ struct ap_matrix_mdev *matrix_mdev;
+ int ret;
+
+ matrix_mdev = vfio_alloc_device(ap_matrix_mdev, vdev, >dev,
+ _ap_matrix_dev_ops);
+ if (IS_ERR(matrix_mdev))
+ return PTR_ERR(matrix_mdev);
+
ret = vfio_register_emulated_iommu_dev(_mdev->vdev);
if (ret)
- goto err_list;
+ goto err_put_vdev;
dev_set_drvdata(>dev, matrix_mdev);
mutex_lock(_dev->mdevs_lock);
list_add(_mdev->node, _dev->mdev_list);
mutex_unlock(_dev->mdevs_lock);
return 0;
-err_list:
- vfio_uninit_group_dev(_mdev->vdev);
- kfree(matrix_mdev);
-err_dec_available:
- atomic_inc(_dev->available_instances);
+err_put_vdev:
+ vfio_put_device(_mdev->vdev);
return ret;
}
@@ -766,6 +768,12 @@ static void vfio_ap_mdev_unlink_fr_queues(struct
ap_matrix_mdev *matrix_mdev)
}
}
+static void vfio_ap_mdev_release_dev(struct vfio_device *vdev)
+{
+ vfio_free_device(vdev);
+ atomic_inc(_dev->available_instances);
+}
+
static void vfio_ap_mdev_remove(struct mdev_device *mdev)
{
struct ap_matrix_mdev *matrix_mdev = dev_get_drvdata(>dev);
@@ -779,9 +787,7 @@ static void vfio_ap_mdev_remove(struct mdev_device *mdev)
list_del(_mdev->node);
mutex_unlock(_dev->mdevs_lock);
mutex_unlock(_dev->guests_lock);
- vfio_uninit_group_dev(_mdev->vdev);
- kfree(matrix_mdev);
- atomic_inc(_dev->available_instances);
+ vfio_put_device(_mdev->vdev);
}
static ssize_t name_show(struct mdev_type *mtype,
@@ -1794,6 +1800,8 @@ static const struct attribute_group vfio_queue_attr_group
= {
};
static const struct vfio_device_ops vfio_ap_matrix_dev_ops = {
+ .init = vfio_ap_mdev_init_dev,
+ .release = vfio_ap_mdev_release_dev,
.open_device = vfio_ap_mdev_open_device,
.close_device = vfio_ap_mdev_close_device,
.ioctl = vfio_ap_mdev_ioctl,
--
2.21.3
[Intel-gfx] [PATCH v3 06/15] vfio/mtty: Use the new device life cycle helpers
From: Yi Liu
and manage available ports inside @init/@release.
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
---
samples/vfio-mdev/mtty.c | 67 +++-
1 file changed, 39 insertions(+), 28 deletions(-)
diff --git a/samples/vfio-mdev/mtty.c b/samples/vfio-mdev/mtty.c
index f42a59ed2e3f..41301d50b247 100644
--- a/samples/vfio-mdev/mtty.c
+++ b/samples/vfio-mdev/mtty.c
@@ -703,9 +703,11 @@ static ssize_t mdev_access(struct mdev_state *mdev_state,
u8 *buf, size_t count,
return ret;
}
-static int mtty_probe(struct mdev_device *mdev)
+static int mtty_init_dev(struct vfio_device *vdev)
{
- struct mdev_state *mdev_state;
+ struct mdev_state *mdev_state =
+ container_of(vdev, struct mdev_state, vdev);
+ struct mdev_device *mdev = to_mdev_device(vdev->dev);
int nr_ports = mdev_get_type_group_id(mdev) + 1;
int avail_ports = atomic_read(_avail_ports);
int ret;
@@ -716,58 +718,65 @@ static int mtty_probe(struct mdev_device *mdev)
} while (!atomic_try_cmpxchg(_avail_ports,
_ports, avail_ports - nr_ports));
- mdev_state = kzalloc(sizeof(struct mdev_state), GFP_KERNEL);
- if (mdev_state == NULL) {
- ret = -ENOMEM;
- goto err_nr_ports;
- }
-
- vfio_init_group_dev(_state->vdev, >dev, _dev_ops);
-
mdev_state->nr_ports = nr_ports;
mdev_state->irq_index = -1;
mdev_state->s[0].max_fifo_size = MAX_FIFO_SIZE;
mdev_state->s[1].max_fifo_size = MAX_FIFO_SIZE;
mutex_init(_state->rxtx_lock);
- mdev_state->vconfig = kzalloc(MTTY_CONFIG_SPACE_SIZE, GFP_KERNEL);
- if (mdev_state->vconfig == NULL) {
+ mdev_state->vconfig = kzalloc(MTTY_CONFIG_SPACE_SIZE, GFP_KERNEL);
+ if (!mdev_state->vconfig) {
ret = -ENOMEM;
- goto err_state;
+ goto err_nr_ports;
}
mutex_init(_state->ops_lock);
mdev_state->mdev = mdev;
-
mtty_create_config_space(mdev_state);
+ return 0;
+
+err_nr_ports:
+ atomic_add(nr_ports, _avail_ports);
+ return ret;
+}
+
+static int mtty_probe(struct mdev_device *mdev)
+{
+ struct mdev_state *mdev_state;
+ int ret;
+
+ mdev_state = vfio_alloc_device(mdev_state, vdev, >dev,
+ _dev_ops);
+ if (IS_ERR(mdev_state))
+ return PTR_ERR(mdev_state);
ret = vfio_register_emulated_iommu_dev(_state->vdev);
if (ret)
- goto err_vconfig;
+ goto err_put_vdev;
dev_set_drvdata(>dev, mdev_state);
return 0;
-err_vconfig:
- kfree(mdev_state->vconfig);
-err_state:
- vfio_uninit_group_dev(_state->vdev);
- kfree(mdev_state);
-err_nr_ports:
- atomic_add(nr_ports, _avail_ports);
+err_put_vdev:
+ vfio_put_device(_state->vdev);
return ret;
}
+static void mtty_release_dev(struct vfio_device *vdev)
+{
+ struct mdev_state *mdev_state =
+ container_of(vdev, struct mdev_state, vdev);
+
+ kfree(mdev_state->vconfig);
+ vfio_free_device(vdev);
+ atomic_add(mdev_state->nr_ports, _avail_ports);
+}
+
static void mtty_remove(struct mdev_device *mdev)
{
struct mdev_state *mdev_state = dev_get_drvdata(>dev);
- int nr_ports = mdev_state->nr_ports;
vfio_unregister_group_dev(_state->vdev);
-
- kfree(mdev_state->vconfig);
- vfio_uninit_group_dev(_state->vdev);
- kfree(mdev_state);
- atomic_add(nr_ports, _avail_ports);
+ vfio_put_device(_state->vdev);
}
static int mtty_reset(struct mdev_state *mdev_state)
@@ -1287,6 +1296,8 @@ static struct attribute_group *mdev_type_groups[] = {
static const struct vfio_device_ops mtty_dev_ops = {
.name = "vfio-mtty",
+ .init = mtty_init_dev,
+ .release = mtty_release_dev,
.read = mtty_read,
.write = mtty_write,
.ioctl = mtty_ioctl,
--
2.21.3
[Intel-gfx] [PATCH v3 01/15] vfio: Add helpers for unifying vfio_device life cycle
The idea is to let vfio core manage the vfio_device life cycle instead
of duplicating the logic cross drivers. This is also a preparatory
step for adding struct device into vfio_device.
New pair of helpers together with a kref in vfio_device:
- vfio_alloc_device()
- vfio_put_device()
Drivers can register @init/@release callbacks to manage any private
state wrapping the vfio_device.
However vfio-ccw doesn't fit this model due to a life cycle mess
that its private structure mixes both parent and mdev info hence must
be allocated/freed outside of the life cycle of vfio device.
Per prior discussions this won't be fixed in short term by IBM folks.
Instead of waiting for those modifications introduce another helper
vfio_init_device() so ccw can call it to initialize a pre-allocated
vfio_device.
Further implication of the ccw trick is that vfio_device cannot be
freed uniformly in vfio core. Instead, require *EVERY* driver to
implement @release and free vfio_device inside. Then ccw can choose
to delay the free at its own discretion.
Another trick down the road is that kvzalloc() is used to accommodate
the need of gvt which uses vzalloc() while all others use kzalloc().
So drivers should call a helper vfio_free_device() to free the
vfio_device instead of assuming that kfree() or vfree() is appliable.
Later once the ccw mess is fixed we can remove those tricks and
fully handle structure alloc/free in vfio core.
Existing vfio_{un}init_group_dev() will be deprecated after all
existing usages are converted to the new model.
Suggested-by: Jason Gunthorpe
Co-developed-by: Yi Liu
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Tony Krowiak
Reviewed-by: Jason Gunthorpe
Reviewed-by: Eric Auger
---
drivers/vfio/vfio_main.c | 92
include/linux/vfio.h | 25 ++-
2 files changed, 116 insertions(+), 1 deletion(-)
diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index 27d9186f35d5..adc1b697bb78 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -498,6 +498,98 @@ void vfio_uninit_group_dev(struct vfio_device *device)
}
EXPORT_SYMBOL_GPL(vfio_uninit_group_dev);
+/* Release helper called by vfio_put_device() */
+void vfio_device_release(struct kref *kref)
+{
+ struct vfio_device *device =
+ container_of(kref, struct vfio_device, kref);
+
+ vfio_uninit_group_dev(device);
+
+ /*
+* kvfree() cannot be done here due to a life cycle mess in
+* vfio-ccw. Before the ccw part is fixed all drivers are
+* required to support @release and call vfio_free_device()
+* from there.
+*/
+ device->ops->release(device);
+}
+EXPORT_SYMBOL_GPL(vfio_device_release);
+
+/*
+ * Alloc and initialize vfio_device so it can be registered to vfio
+ * core.
+ *
+ * Drivers should use the wrapper vfio_alloc_device() for allocation.
+ * @size is the size of the structure to be allocated, including any
+ * private data used by the driver.
+ *
+ * Driver may provide an @init callback to cover device private data.
+ *
+ * Use vfio_put_device() to release the structure after success return.
+ */
+struct vfio_device *_vfio_alloc_device(size_t size, struct device *dev,
+ const struct vfio_device_ops *ops)
+{
+ struct vfio_device *device;
+ int ret;
+
+ if (WARN_ON(size < sizeof(struct vfio_device)))
+ return ERR_PTR(-EINVAL);
+
+ device = kvzalloc(size, GFP_KERNEL);
+ if (!device)
+ return ERR_PTR(-ENOMEM);
+
+ ret = vfio_init_device(device, dev, ops);
+ if (ret)
+ goto out_free;
+ return device;
+
+out_free:
+ kvfree(device);
+ return ERR_PTR(ret);
+}
+EXPORT_SYMBOL_GPL(_vfio_alloc_device);
+
+/*
+ * Initialize a vfio_device so it can be registered to vfio core.
+ *
+ * Only vfio-ccw driver should call this interface.
+ */
+int vfio_init_device(struct vfio_device *device, struct device *dev,
+const struct vfio_device_ops *ops)
+{
+ int ret;
+
+ vfio_init_group_dev(device, dev, ops);
+
+ if (ops->init) {
+ ret = ops->init(device);
+ if (ret)
+ goto out_uninit;
+ }
+
+ kref_init(>kref);
+ return 0;
+
+out_uninit:
+ vfio_uninit_group_dev(device);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(vfio_init_device);
+
+/*
+ * The helper called by driver @release callback to free the device
+ * structure. Drivers which don't have private data to clean can
+ * simply use this helper as its @release.
+ */
+void vfio_free_device(struct vfio_device *device)
+{
+ kvfree(device);
+}
+EXPORT_SYMBOL_GPL(vfio_free_device);
+
static struct vfio_group *vfio_noiommu_group_alloc(struct device *dev,
enum vfio_group_type type)
{
diff --git a/include/linux/vfio.h b/include/linux/vfio.h
index 0e2826559091..f67cac700e6f
[Intel-gfx] [PATCH v3 00/15] Tidy up vfio_device life cycle
The idea is to let vfio core manage the vfio_device life cycle instead of duplicating the logic cross drivers. Besides cleaner code in driver side this also allows adding struct device to vfio_device as the first step toward adding cdev uAPI in the future. Another benefit is that user can now look at sysfs to decide whether a device is bound to vfio [1], e.g.: /sys/devices/pci\:6f/\:6f\:01.0/vfio-dev/vfio0 Though most drivers can fit the new model naturally: - vfio_alloc_device() to allocate and initialize vfio_device - vfio_put_device() to release vfio_device - dev_ops->init() for driver private initialization - dev_ops->release() for driver private cleanup vfio-ccw is the only exception due to a life cycle mess that its private structure mixes both parent and mdev info hence must be alloc/freed outside of the life cycle of vfio device. Per prior discussions this won't be fixed in short term by IBM folks [2]. Instead of waiting this series introduces a few tricks to move forward: - vfio_init_device() to initialize a pre-allocated device structure; - require *EVERY* driver to implement @release and free vfio_device inside. Then vfio-ccw can use a completion mechanism to delay the free to css driver; The second trick is not a real burden to other drivers because they all require a @release for private cleanup anyay. Later once the ccw mess is fixed a simple cleanup can be done by moving free from @release to vfio core. Thanks Kevin [1] https://listman.redhat.com/archives/libvir-list/2022-August/233482.html [2] https://lore.kernel.org/all/0ee29bd6583f17f0ee4ec0769fa50e8ea6703623.ca...@linux.ibm.com/ v3: - rebase to vfio-next after resolving conflicts with Yishai's series - add missing fixes for two checkpatch errors - fix grammar issues (Eric Auger) - add more r-b's v2: - https://lore.kernel.org/lkml/20220901143747.32858-1-kevin.t...@intel.com/ - rebase to 6.0-rc3 - fix build warnings (lkp) - patch1: remove unnecessary forward reference (Jason) - patch10: leave device_set released by vfio core (Jason) - patch13: add Suggested-by - patch15: add ABI file sysfs-devices-vfio-dev (Alex) - patch15: rename 'vfio' to 'vfio_group' in procfs (Jason) v1: https://lore.kernel.org/lkml/20220827171037.30297-1-kevin.t...@intel.com/ Kevin Tian (6): vfio: Add helpers for unifying vfio_device life cycle drm/i915/gvt: Use the new device life cycle helpers vfio/platform: Use the new device life cycle helpers vfio/amba: Use the new device life cycle helpers vfio/ccw: Use the new device life cycle helpers vfio: Rename vfio_device_put() and vfio_device_try_get() Yi Liu (9): vfio/pci: Use the new device life cycle helpers vfio/mlx5: Use the new device life cycle helpers vfio/hisi_acc: Use the new device life cycle helpers vfio/mdpy: Use the new device life cycle helpers vfio/mtty: Use the new device life cycle helpers vfio/mbochs: Use the new device life cycle helpers vfio/ap: Use the new device life cycle helpers vfio/fsl-mc: Use the new device life cycle helpers vfio: Add struct device to vfio_device .../ABI/testing/sysfs-devices-vfio-dev| 8 + MAINTAINERS | 1 + drivers/gpu/drm/i915/gvt/gvt.h| 5 +- drivers/gpu/drm/i915/gvt/kvmgt.c | 52 -- drivers/gpu/drm/i915/gvt/vgpu.c | 33 ++-- drivers/s390/cio/vfio_ccw_ops.c | 52 +- drivers/s390/cio/vfio_ccw_private.h | 3 + drivers/s390/crypto/vfio_ap_ops.c | 50 +++--- drivers/vfio/fsl-mc/vfio_fsl_mc.c | 85 + .../vfio/pci/hisilicon/hisi_acc_vfio_pci.c| 80 - drivers/vfio/pci/mlx5/main.c | 50 -- drivers/vfio/pci/vfio_pci.c | 20 +-- drivers/vfio/pci/vfio_pci_core.c | 23 ++- drivers/vfio/platform/vfio_amba.c | 72 ++-- drivers/vfio/platform/vfio_platform.c | 66 +-- drivers/vfio/platform/vfio_platform_common.c | 71 +++- drivers/vfio/platform/vfio_platform_private.h | 18 +- drivers/vfio/vfio_main.c | 167 +++--- include/linux/vfio.h | 28 ++- include/linux/vfio_pci_core.h | 6 +- samples/vfio-mdev/mbochs.c| 73 +--- samples/vfio-mdev/mdpy.c | 81 + samples/vfio-mdev/mtty.c | 67 --- 23 files changed, 730 insertions(+), 381 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-devices-vfio-dev base-commit: f39856aacb078c1c93acef011a37121b17d54fe0 -- 2.21.3
[Intel-gfx] [PATCH v3 04/15] vfio/hisi_acc: Use the new device life cycle helpers
From: Yi Liu
Tidy up @probe so all migration specific initialization logic is moved
to migration specific @init callback.
Remove vfio_pci_core_{un}init_device() given no user now.
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
Reviewed-by: Shameer Kolothum
---
.../vfio/pci/hisilicon/hisi_acc_vfio_pci.c| 80 +--
drivers/vfio/pci/vfio_pci_core.c | 30 ---
include/linux/vfio_pci_core.h | 4 -
3 files changed, 37 insertions(+), 77 deletions(-)
diff --git a/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c
b/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c
index 258cae0863ea..47174e2b61bd 100644
--- a/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c
+++ b/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c
@@ -1213,8 +1213,28 @@ static const struct vfio_migration_ops
hisi_acc_vfio_pci_migrn_state_ops = {
.migration_get_state = hisi_acc_vfio_pci_get_device_state,
};
+static int hisi_acc_vfio_pci_migrn_init_dev(struct vfio_device *core_vdev)
+{
+ struct hisi_acc_vf_core_device *hisi_acc_vdev = container_of(core_vdev,
+ struct hisi_acc_vf_core_device, core_device.vdev);
+ struct pci_dev *pdev = to_pci_dev(core_vdev->dev);
+ struct hisi_qm *pf_qm = hisi_acc_get_pf_qm(pdev);
+
+ hisi_acc_vdev->vf_id = pci_iov_vf_id(pdev) + 1;
+ hisi_acc_vdev->pf_qm = pf_qm;
+ hisi_acc_vdev->vf_dev = pdev;
+ mutex_init(_acc_vdev->state_mutex);
+
+ core_vdev->migration_flags = VFIO_MIGRATION_STOP_COPY;
+ core_vdev->mig_ops = _acc_vfio_pci_migrn_state_ops;
+
+ return vfio_pci_core_init_dev(core_vdev);
+}
+
static const struct vfio_device_ops hisi_acc_vfio_pci_migrn_ops = {
.name = "hisi-acc-vfio-pci-migration",
+ .init = hisi_acc_vfio_pci_migrn_init_dev,
+ .release = vfio_pci_core_release_dev,
.open_device = hisi_acc_vfio_pci_open_device,
.close_device = hisi_acc_vfio_pci_close_device,
.ioctl = hisi_acc_vfio_pci_ioctl,
@@ -1228,6 +1248,8 @@ static const struct vfio_device_ops
hisi_acc_vfio_pci_migrn_ops = {
static const struct vfio_device_ops hisi_acc_vfio_pci_ops = {
.name = "hisi-acc-vfio-pci",
+ .init = vfio_pci_core_init_dev,
+ .release = vfio_pci_core_release_dev,
.open_device = hisi_acc_vfio_pci_open_device,
.close_device = vfio_pci_core_close_device,
.ioctl = vfio_pci_core_ioctl,
@@ -1239,63 +1261,36 @@ static const struct vfio_device_ops
hisi_acc_vfio_pci_ops = {
.match = vfio_pci_core_match,
};
-static int
-hisi_acc_vfio_pci_migrn_init(struct hisi_acc_vf_core_device *hisi_acc_vdev,
-struct pci_dev *pdev, struct hisi_qm *pf_qm)
-{
- int vf_id;
-
- vf_id = pci_iov_vf_id(pdev);
- if (vf_id < 0)
- return vf_id;
-
- hisi_acc_vdev->vf_id = vf_id + 1;
- hisi_acc_vdev->core_device.vdev.migration_flags =
- VFIO_MIGRATION_STOP_COPY;
- hisi_acc_vdev->pf_qm = pf_qm;
- hisi_acc_vdev->vf_dev = pdev;
- mutex_init(_acc_vdev->state_mutex);
-
- return 0;
-}
-
static int hisi_acc_vfio_pci_probe(struct pci_dev *pdev, const struct
pci_device_id *id)
{
struct hisi_acc_vf_core_device *hisi_acc_vdev;
+ const struct vfio_device_ops *ops = _acc_vfio_pci_ops;
struct hisi_qm *pf_qm;
+ int vf_id;
int ret;
- hisi_acc_vdev = kzalloc(sizeof(*hisi_acc_vdev), GFP_KERNEL);
- if (!hisi_acc_vdev)
- return -ENOMEM;
-
pf_qm = hisi_acc_get_pf_qm(pdev);
if (pf_qm && pf_qm->ver >= QM_HW_V3) {
- ret = hisi_acc_vfio_pci_migrn_init(hisi_acc_vdev, pdev, pf_qm);
- if (!ret) {
- vfio_pci_core_init_device(_acc_vdev->core_device,
pdev,
- _acc_vfio_pci_migrn_ops);
- hisi_acc_vdev->core_device.vdev.mig_ops =
- _acc_vfio_pci_migrn_state_ops;
- } else {
+ vf_id = pci_iov_vf_id(pdev);
+ if (vf_id >= 0)
+ ops = _acc_vfio_pci_migrn_ops;
+ else
pci_warn(pdev, "migration support failed, continue with
generic interface\n");
- vfio_pci_core_init_device(_acc_vdev->core_device,
pdev,
- _acc_vfio_pci_ops);
- }
- } else {
- vfio_pci_core_init_device(_acc_vdev->core_device, pdev,
- _acc_vfio_pci_ops);
}
+ hisi_acc_vdev = vfio_alloc_device(hisi_acc_vf_core_device,
+ core_device.vdev, >dev, ops);
+ if (IS_ERR(hisi_acc_vdev))
+ return PTR_ERR(hisi_acc_vdev);
+
dev_set_drvdata(>dev, _acc_vdev->core_device);
ret =
[Intel-gfx] [PATCH v3 02/15] vfio/pci: Use the new device life cycle helpers
From: Yi Liu
Also introduce two pci core helpers as @init/@release for pci drivers:
- vfio_pci_core_init_dev()
- vfio_pci_core_release_dev()
Signed-off-by: Yi Liu
Signed-off-by: Kevin Tian
Reviewed-by: Jason Gunthorpe
---
drivers/vfio/pci/vfio_pci.c | 20 +-
drivers/vfio/pci/vfio_pci_core.c | 35
include/linux/vfio_pci_core.h| 2 ++
3 files changed, 47 insertions(+), 10 deletions(-)
diff --git a/drivers/vfio/pci/vfio_pci.c b/drivers/vfio/pci/vfio_pci.c
index d9b5c03f8d5b..1d4919edfbde 100644
--- a/drivers/vfio/pci/vfio_pci.c
+++ b/drivers/vfio/pci/vfio_pci.c
@@ -127,6 +127,8 @@ static int vfio_pci_open_device(struct vfio_device
*core_vdev)
static const struct vfio_device_ops vfio_pci_ops = {
.name = "vfio-pci",
+ .init = vfio_pci_core_init_dev,
+ .release= vfio_pci_core_release_dev,
.open_device= vfio_pci_open_device,
.close_device = vfio_pci_core_close_device,
.ioctl = vfio_pci_core_ioctl,
@@ -146,20 +148,19 @@ static int vfio_pci_probe(struct pci_dev *pdev, const
struct pci_device_id *id)
if (vfio_pci_is_denylisted(pdev))
return -EINVAL;
- vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
- if (!vdev)
- return -ENOMEM;
- vfio_pci_core_init_device(vdev, pdev, _pci_ops);
+ vdev = vfio_alloc_device(vfio_pci_core_device, vdev, >dev,
+_pci_ops);
+ if (IS_ERR(vdev))
+ return PTR_ERR(vdev);
dev_set_drvdata(>dev, vdev);
ret = vfio_pci_core_register_device(vdev);
if (ret)
- goto out_free;
+ goto out_put_vdev;
return 0;
-out_free:
- vfio_pci_core_uninit_device(vdev);
- kfree(vdev);
+out_put_vdev:
+ vfio_put_device(>vdev);
return ret;
}
@@ -168,8 +169,7 @@ static void vfio_pci_remove(struct pci_dev *pdev)
struct vfio_pci_core_device *vdev = dev_get_drvdata(>dev);
vfio_pci_core_unregister_device(vdev);
- vfio_pci_core_uninit_device(vdev);
- kfree(vdev);
+ vfio_put_device(>vdev);
}
static int vfio_pci_sriov_configure(struct pci_dev *pdev, int nr_virtfn)
diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c
index 0a801aee2f2d..77d33739c6e8 100644
--- a/drivers/vfio/pci/vfio_pci_core.c
+++ b/drivers/vfio/pci/vfio_pci_core.c
@@ -2078,6 +2078,41 @@ static void vfio_pci_vga_uninit(struct
vfio_pci_core_device *vdev)
VGA_RSRC_LEGACY_MEM);
}
+int vfio_pci_core_init_dev(struct vfio_device *core_vdev)
+{
+ struct vfio_pci_core_device *vdev =
+ container_of(core_vdev, struct vfio_pci_core_device, vdev);
+
+ vdev->pdev = to_pci_dev(core_vdev->dev);
+ vdev->irq_type = VFIO_PCI_NUM_IRQS;
+ mutex_init(>igate);
+ spin_lock_init(>irqlock);
+ mutex_init(>ioeventfds_lock);
+ INIT_LIST_HEAD(>dummy_resources_list);
+ INIT_LIST_HEAD(>ioeventfds_list);
+ mutex_init(>vma_lock);
+ INIT_LIST_HEAD(>vma_list);
+ INIT_LIST_HEAD(>sriov_pfs_item);
+ init_rwsem(>memory_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(vfio_pci_core_init_dev);
+
+void vfio_pci_core_release_dev(struct vfio_device *core_vdev)
+{
+ struct vfio_pci_core_device *vdev =
+ container_of(core_vdev, struct vfio_pci_core_device, vdev);
+
+ mutex_destroy(>igate);
+ mutex_destroy(>ioeventfds_lock);
+ mutex_destroy(>vma_lock);
+ kfree(vdev->region);
+ kfree(vdev->pm_save);
+ vfio_free_device(core_vdev);
+}
+EXPORT_SYMBOL_GPL(vfio_pci_core_release_dev);
+
void vfio_pci_core_init_device(struct vfio_pci_core_device *vdev,
struct pci_dev *pdev,
const struct vfio_device_ops *vfio_pci_ops)
diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h
index 089b603bcfdc..0499ea836058 100644
--- a/include/linux/vfio_pci_core.h
+++ b/include/linux/vfio_pci_core.h
@@ -109,6 +109,8 @@ void vfio_pci_core_close_device(struct vfio_device
*core_vdev);
void vfio_pci_core_init_device(struct vfio_pci_core_device *vdev,
struct pci_dev *pdev,
const struct vfio_device_ops *vfio_pci_ops);
+int vfio_pci_core_init_dev(struct vfio_device *core_vdev);
+void vfio_pci_core_release_dev(struct vfio_device *core_vdev);
int vfio_pci_core_register_device(struct vfio_pci_core_device *vdev);
void vfio_pci_core_uninit_device(struct vfio_pci_core_device *vdev);
void vfio_pci_core_unregister_device(struct vfio_pci_core_device *vdev);
--
2.21.3
[Intel-gfx] [PATCH 4/6] drm/i915: Use GEN12 RPSTAT register
From: Don Hiatt
On GEN12, use the correct GEN12 RPSTAT register mask/shift.
HSD: 1409538411
Cc: Don Hiatt
Cc: Andi Shyti
Signed-off-by: Don Hiatt
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +
drivers/gpu/drm/i915/gt/intel_rps.c | 17 -
drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
drivers/gpu/drm/i915/i915_pmu.c | 3 +--
5 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 108b9e76c32e..96c03a1258e1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -380,7 +380,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct
drm_printer *p)
rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
- rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
+ rpstat = intel_rps_read_rpstat(rps);
rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) &
GEN6_CURICONT_MASK;
rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) &
GEN6_CURBSYTAVG_MASK;
rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) &
GEN6_CURBSYTAVG_MASK;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index fb2c56777480..dac59c3e68db 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1510,6 +1510,11 @@
#define VLV_RENDER_C0_COUNT_MMIO(0x138118)
#define VLV_MEDIA_C0_COUNT _MMIO(0x13811c)
+#define GEN12_RPSTAT1 _MMIO(0x1381b4)
+#define GEN12_CAGF_SHIFT 11
+#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
+#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
+
#define GEN11_GT_INTR_DW(x)_MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
#define GEN11_GUNIT (28)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 6fadde4ee7bf..341f96f536e8 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2040,6 +2040,19 @@ void intel_rps_sanitize(struct intel_rps *rps)
rps_disable_interrupts(rps);
}
+u32 intel_rps_read_rpstat(struct intel_rps *rps)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ u32 rpstat;
+
+ if (GRAPHICS_VER(i915) >= 12)
+ rpstat = intel_uncore_read(rps_to_gt(rps)->uncore,
GEN12_RPSTAT1);
+ else
+ rpstat = intel_uncore_read(rps_to_gt(rps)->uncore,
GEN6_RPSTAT1);
+
+ return rpstat;
+}
+
u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
@@ -2047,6 +2060,8 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
cagf = (rpstat >> 8) & 0xff;
+ else if (GRAPHICS_VER(i915) >= 12)
+ cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT;
else if (GRAPHICS_VER(i915) >= 9)
cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
@@ -2071,7 +2086,7 @@ static u32 read_cagf(struct intel_rps *rps)
freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
vlv_punit_put(i915);
} else if (GRAPHICS_VER(i915) >= 6) {
- freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
+ freq = intel_rps_read_rpstat(rps);
} else {
freq = intel_uncore_read(uncore, MEMSTAT_ILK);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h
b/drivers/gpu/drm/i915/gt/intel_rps.h
index 4509dfdc52e0..08bae6d97870 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -47,6 +47,7 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
u32 intel_rps_read_punit_req(struct intel_rps *rps);
u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
+u32 intel_rps_read_rpstat(struct intel_rps *rps);
void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps
*caps);
void intel_rps_raise_unslice(struct intel_rps *rps);
void intel_rps_lower_unslice(struct intel_rps *rps);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 958b37123bf1..a24704ec2c18 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -371,7 +371,6 @@ static void
frequency_sample(struct intel_gt *gt, unsigned int period_ns)
{
struct
[Intel-gfx] [PATCH 2/6] drm/i915: Rename and expose common GT early init routine
From: Matt Roper
The common early GT init is needed for initialization of all GT types
(root/primary, remote tile, standalone media). Since standalone media
(coming in the next patch) will be implemented in a separate file,
rename and expose the function for use.
Signed-off-by: Matt Roper
Reviewed-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/gt/intel_gt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5b4263c708cc..57a6488c0e14 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -35,7 +35,7 @@
#include "intel_uncore.h"
#include "shmem_utils.h"
-static void __intel_gt_init_early(struct intel_gt *gt)
+void intel_gt_common_init_early(struct intel_gt *gt)
{
spin_lock_init(>irq_lock);
@@ -65,7 +65,7 @@ void intel_root_gt_init_early(struct drm_i915_private *i915)
gt->i915 = i915;
gt->uncore = >uncore;
- __intel_gt_init_early(gt);
+ intel_gt_common_init_early(gt);
}
static int intel_gt_probe_lmem(struct intel_gt *gt)
@@ -797,7 +797,7 @@ static int intel_gt_tile_setup(struct intel_gt *gt,
phys_addr_t phys_addr)
gt->uncore = uncore;
gt->uncore->debug = mmio_debug;
- __intel_gt_init_early(gt);
+ intel_gt_common_init_early(gt);
}
intel_uncore_init_early(gt->uncore, gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 4d8779529cc2..c9a359f35d0f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -44,6 +44,7 @@ static inline struct intel_gt *gsc_to_gt(struct intel_gsc
*gsc)
return container_of(gsc, struct intel_gt, gsc);
}
+void intel_gt_common_init_early(struct intel_gt *gt);
void intel_root_gt_init_early(struct drm_i915_private *i915);
int intel_gt_assign_ggtt(struct intel_gt *gt);
int intel_gt_init_mmio(struct intel_gt *gt);
--
2.25.1
[Intel-gfx] [PATCH 3/6] drm/i915/xelpmp: Expose media as another GT
From: Matt Roper
Xe_LPM+ platforms have "standalone media." I.e., the media unit is
designed as an additional GT with its own engine list, GuC, forcewake,
etc. Let's allow platforms to include media GTs in their device info.
Cc: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +
drivers/gpu/drm/i915/gt/intel_sa_media.c | 39
drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 +
drivers/gpu/drm/i915/i915_pci.c | 15 +
drivers/gpu/drm/i915/intel_device_info.h | 5 ++-
drivers/gpu/drm/i915/intel_uncore.c | 16 --
drivers/gpu/drm/i915/intel_uncore.h | 20 ++--
9 files changed, 123 insertions(+), 8 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 522ef9b4aff3..e83e4cd46968 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -123,6 +123,7 @@ gt-y += \
gt/intel_ring.o \
gt/intel_ring_submission.o \
gt/intel_rps.o \
+ gt/intel_sa_media.o \
gt/intel_sseu.o \
gt/intel_sseu_debugfs.o \
gt/intel_timeline.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 57a6488c0e14..bfe77d01f747 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -776,10 +776,15 @@ void intel_gt_driver_late_release_all(struct
drm_i915_private *i915)
}
}
-static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
+static int intel_gt_tile_setup(struct intel_gt *gt,
+ phys_addr_t phys_addr,
+ u32 gsi_offset)
{
int ret;
+ /* GSI offset is only applicable for media GTs */
+ drm_WARN_ON(>i915->drm, gsi_offset);
+
if (!gt_is_root(gt)) {
struct intel_uncore_mmio_debug *mmio_debug;
struct intel_uncore *uncore;
@@ -840,7 +845,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
drm_dbg(>drm, "Setting up %s\n", gt->name);
- ret = intel_gt_tile_setup(gt, phys_addr);
+ ret = intel_gt_tile_setup(gt, phys_addr, 0);
if (ret)
return ret;
@@ -873,7 +878,8 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
goto err;
}
- ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base);
+ ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base,
+ gtdef->gsi_offset);
if (ret)
goto err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index d414785003cc..fb2c56777480 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1578,4 +1578,12 @@
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
+/*
+ * Standalone Media's non-engine GT registers are located at their regular GT
+ * offsets plus 0x38. This extra offset is stored inside the intel_uncore
+ * structure so that the existing code can be used for both GTs without
+ * modification.
+ */
+#define MTL_MEDIA_GSI_BASE 0x38
+
#endif /* __INTEL_GT_REGS__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c
b/drivers/gpu/drm/i915/gt/intel_sa_media.c
new file mode 100644
index ..8c5c519457cc
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include
+
+#include "i915_drv.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_sa_media.h"
+
+int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
+ u32 gsi_offset)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore;
+
+ uncore = drmm_kzalloc(>drm, sizeof(*uncore), GFP_KERNEL);
+ if (!uncore)
+ return -ENOMEM;
+
+ uncore->gsi_offset = gsi_offset;
+
+ intel_gt_common_init_early(gt);
+ intel_uncore_init_early(uncore, gt);
+
+ /*
+* Standalone media shares the general MMIO space with the primary
+* GT. We'll re-use the primary GT's mapping.
+*/
+ uncore->regs = i915->uncore.regs;
+ if (drm_WARN_ON(>drm, uncore->regs == NULL))
+ return -EIO;
+
+ gt->uncore = uncore;
+ gt->phys_addr = phys_addr;
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.h
b/drivers/gpu/drm/i915/gt/intel_sa_media.h
new file mode 100644
index
[Intel-gfx] [PATCH 5/6] drm/i915/mtl: Modify CAGF functions for MTL
Updated the CAGF functions to get actual resolved frequency of 3D and SAMedia Bspec: 66300 Cc: Vinay Belgaumkar Cc: Ashutosh Dixit Signed-off-by: Badal Nilawar --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 drivers/gpu/drm/i915/gt/intel_rps.c | 7 ++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index dac59c3e68db..ab9a5e66ab34 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1515,6 +1515,14 @@ #define GEN12_CAGF_MASK REG_GENMASK(19, 11) #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0) +/* + * MTL: Workpoint reg to get Core C state and act freq of 3D, SAMedia/ + * 3D - 0x0C60 , SAMedia - 0x380C60 + * Intel uncore handler redirects transactions for SAMedia to MTL_MEDIA_GSI_BASE + */ +#define MTL_MIRROR_TARGET_WP1 _MMIO(0x0C60) +#define MTL_CAGF_MASKREG_GENMASK(8, 0) + #define GEN11_GT_INTR_DW(x)_MMIO(0x190018 + ((x) * 4)) #define GEN11_CSME (31) #define GEN11_GUNIT (28) diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 341f96f536e8..3e4abc25f139 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -2045,7 +2045,10 @@ u32 intel_rps_read_rpstat(struct intel_rps *rps) struct drm_i915_private *i915 = rps_to_i915(rps); u32 rpstat; - if (GRAPHICS_VER(i915) >= 12) + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) + rpstat = intel_uncore_read(rps_to_gt(rps)->uncore, + MTL_MIRROR_TARGET_WP1); + else if (GRAPHICS_VER(i915) >= 12) rpstat = intel_uncore_read(rps_to_gt(rps)->uncore, GEN12_RPSTAT1); else rpstat = intel_uncore_read(rps_to_gt(rps)->uncore, GEN6_RPSTAT1); @@ -2060,6 +2063,8 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) cagf = (rpstat >> 8) & 0xff; + else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) + cagf = rpstat & MTL_CAGF_MASK; else if (GRAPHICS_VER(i915) >= 12) cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; else if (GRAPHICS_VER(i915) >= 9) -- 2.25.1
[Intel-gfx] [PATCH 6/6] drm/i915/mtl: Add C6 residency support for MTL SAMedia
For MTL SAMedia updated relevant functions and places in the code to get
Media C6 residency.
Cc: Vinay Belgaumkar
Cc: Ashutosh Dixit
Cc: Chris Wilson
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 56 +++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 10
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 9 ++-
drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +-
drivers/gpu/drm/i915/gt/selftest_rc6.c| 9 ++-
drivers/gpu/drm/i915/i915_pmu.c | 8 ++-
6 files changed, 93 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 96c03a1258e1..6913c0a2ba33 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -269,6 +269,60 @@ static int ilk_drpc(struct seq_file *m)
return 0;
}
+static int mtl_drpc(struct seq_file *m)
+{
+ struct intel_gt *gt = m->private;
+ struct intel_uncore *uncore = gt->uncore;
+ u32 gt_core_status, rcctl1;
+ u32 mtl_powergate_enable = 0, mtl_powergate_status = 0;
+ i915_reg_t reg;
+
+ gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
+
+ rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
+ mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE);
+ mtl_powergate_status = intel_uncore_read(uncore,
+GEN9_PWRGT_DOMAIN_STATUS);
+
+ seq_printf(m, "RC6 Enabled: %s\n",
+ str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
+ if (gt->type == GT_MEDIA) {
+ seq_printf(m, "Media Well Gating Enabled: %s\n",
+ str_yes_no(mtl_powergate_enable &
GEN9_MEDIA_PG_ENABLE));
+ } else {
+ seq_printf(m, "Render Well Gating Enabled: %s\n",
+ str_yes_no(mtl_powergate_enable &
GEN9_RENDER_PG_ENABLE));
+ }
+
+ seq_puts(m, "Current RC state: ");
+
+ switch ((gt_core_status & MTL_CC_MASK) >> MTL_CC_SHIFT) {
+ case MTL_CC0:
+ seq_puts(m, "on\n");
+ break;
+ case MTL_CC6:
+ seq_puts(m, "RC6\n");
+ break;
+ default:
+ seq_puts(m, "Unknown\n");
+ break;
+ }
+
+ if (gt->type == GT_MEDIA)
+ seq_printf(m, "Media Power Well: %s\n",
+ (mtl_powergate_status &
+ GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
+ else
+ seq_printf(m, "Render Power Well: %s\n",
+ (mtl_powergate_status &
+ GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
+
+ reg = (gt->type == GT_MEDIA) ? MTL_MEDIA_MC6 : GEN6_GT_GFX_RC6;
+ print_rc6_res(m, "RC6 residency since boot:", reg);
+
+ return fw_domains_show(m, NULL);
+}
+
static int drpc_show(struct seq_file *m, void *unused)
{
struct intel_gt *gt = m->private;
@@ -279,6 +333,8 @@ static int drpc_show(struct seq_file *m, void *unused)
with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
err = vlv_drpc(m);
+ else if (MEDIA_VER(i915) >= 13)
+ err = mtl_drpc(m);
else if (GRAPHICS_VER(i915) >= 6)
err = gen6_drpc(m);
else
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index ab9a5e66ab34..2c6cf29888e0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1522,6 +1522,16 @@
*/
#define MTL_MIRROR_TARGET_WP1 _MMIO(0x0C60)
#define MTL_CAGF_MASKREG_GENMASK(8, 0)
+#define MTL_CC0 0x0
+#define MTL_CC6 0x3
+#define MTL_CC_SHIFT 9
+#define MTL_CC_MASK (0xf << MTL_CC_SHIFT)
+
+/*
+ * MTL: This register contains the total MC6 residency time that SAMedia was
+ * since boot
+ */
+#define MTL_MEDIA_MC6 _MMIO(0x138048)
#define GEN11_GT_INTR_DW(x)_MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index e066cc33d9f2..fb2cf8ee2eeb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -138,7 +138,14 @@ static ssize_t rc6_residency_ms_show(struct device *dev,
static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
{
- return get_residency(gt, GEN6_GT_GFX_RC6p);
+ i915_reg_t reg;
+
+ if (gt->type == GT_MEDIA)
+ reg = MTL_MEDIA_MC6;
+ else
+ reg = GEN6_GT_GFX_RC6;
+
+ return
[Intel-gfx] [PATCH 1/6] drm/i915: Prepare more multi-GT initialization
From: Matt Roper
We're going to introduce an additional intel_gt for MTL's media unit
soon. Let's provide a bit more multi-GT initialization framework in
preparation for that. The initialization will pull the list of GTs for
a platform from the device info structure. Although necessary for the
immediate MTL media enabling, this same framework will also be used
farther down the road when we enable remote tiles on xehpsdv and pvc.
v2:
- Re-add missing test for !HAS_EXTRA_GT_LIST in intel_gt_probe_all().
Cc: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 54 ---
drivers/gpu/drm/i915/gt/intel_gt.h| 1 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_device_info.h | 16 ++
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
7 files changed, 70 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 275ad72940c1..41acc285e8bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -736,7 +736,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt
*gt)
u16 vdbox_mask;
u16 vebox_mask;
- info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+ GEM_BUG_ON(!info->engine_mask);
if (GRAPHICS_VER(i915) < 11)
return info->engine_mask;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index e4bac2431e41..5b4263c708cc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -815,20 +815,16 @@ static void
intel_gt_tile_cleanup(struct intel_gt *gt)
{
intel_uncore_cleanup_mmio(gt->uncore);
-
- if (!gt_is_root(gt)) {
- kfree(gt->uncore->debug);
- kfree(gt->uncore);
- kfree(gt);
- }
}
int intel_gt_probe_all(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct intel_gt *gt = >gt0;
+ const struct intel_gt_definition *gtdef;
phys_addr_t phys_addr;
unsigned int mmio_bar;
+ unsigned int i;
int ret;
mmio_bar = GRAPHICS_VER(i915) == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
@@ -839,14 +835,58 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
* and it has been already initialized early during probe
* in i915_driver_probe()
*/
+ gt->i915 = i915;
+ gt->name = "Primary GT";
+ gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+
+ drm_dbg(>drm, "Setting up %s\n", gt->name);
ret = intel_gt_tile_setup(gt, phys_addr);
if (ret)
return ret;
i915->gt[0] = gt;
- /* TODO: add more tiles */
+ if (!HAS_EXTRA_GT_LIST(i915))
+ return 0;
+
+ for (i = 1, gtdef = _INFO(i915)->extra_gt_list[i - 1];
+gtdef->setup != NULL;
+i++, gtdef = _INFO(i915)->extra_gt_list[i - 1]) {
+ gt = drmm_kzalloc(>drm, sizeof(*gt), GFP_KERNEL);
+ if (!gt) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ gt->i915 = i915;
+ gt->name = gtdef->name;
+ gt->type = gtdef->type;
+ gt->info.engine_mask = gtdef->engine_mask;
+ gt->info.id = i;
+
+ drm_dbg(>drm, "Setting up %s\n", gt->name);
+ if (GEM_WARN_ON(range_overflows_t(resource_size_t,
+ gtdef->mapping_base,
+ SZ_16M,
+ pci_resource_len(pdev,
mmio_bar {
+ ret = -ENODEV;
+ goto err;
+ }
+
+ ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base);
+ if (ret)
+ goto err;
+
+ i915->gt[i] = gt;
+ }
+
return 0;
+
+err:
+ i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name,
ret);
+ intel_gt_release_all(i915);
+
+ return ret;
}
int intel_gt_tiles_init(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 40b06adf509a..4d8779529cc2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -54,7 +54,6 @@ void intel_gt_driver_register(struct intel_gt *gt);
void intel_gt_driver_unregister(struct intel_gt *gt);
void intel_gt_driver_remove(struct intel_gt *gt);
void intel_gt_driver_release(struct intel_gt *gt);
-
void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
int
[Intel-gfx] [PATCH 0/6] i915: CAGF and RC6 changes for MTL
This series includes the code changes to get CAGF, RC State and C6 Residency of MTL. The series depends on: https://patchwork.freedesktop.org/series/107908/ We have included 3 patches from from the above series as part of this series in order for this series to compile. These are the first 3 patches authored by Matt Roper. Please do not review these first 3 patches. Only patch 4 and 6 needs review. v2: Included "Use GEN12 RPSTAT register" patch Cc: Ashutosh Dixit Badal Nilawar (2): drm/i915/mtl: Modify CAGF functions for MTL drm/i915/mtl: Add C6 residency support for MTL SAMedia Don Hiatt (1): drm/i915: Use GEN12 RPSTAT register Matt Roper (3): drm/i915: Prepare more multi-GT initialization drm/i915: Rename and expose common GT early init routine drm/i915/xelpmp: Expose media as another GT drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c| 70 +++ drivers/gpu/drm/i915/gt/intel_gt.h| 2 +- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 58 ++- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 31 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 9 ++- drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +- drivers/gpu/drm/i915/gt/intel_rps.c | 22 +- drivers/gpu/drm/i915/gt/intel_rps.h | 1 + drivers/gpu/drm/i915/gt/intel_sa_media.c | 39 +++ drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 drivers/gpu/drm/i915/gt/selftest_rc6.c| 9 ++- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_pci.c | 15 drivers/gpu/drm/i915/i915_pmu.c | 11 ++- drivers/gpu/drm/i915/intel_device_info.h | 19 + drivers/gpu/drm/i915/intel_uncore.c | 16 - drivers/gpu/drm/i915/intel_uncore.h | 20 +- .../gpu/drm/i915/selftests/mock_gem_device.c | 1 + 21 files changed, 325 insertions(+), 26 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h -- 2.25.1
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Move skl+ wm code into its own file
== Series Details == Series: drm/i915: Move skl+ wm code into its own file URL : https://patchwork.freedesktop.org/series/108313/ State : success == Summary == CI Bug Log - changes from CI_DRM_12100_full -> Patchwork_108313v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 11) -- Additional (1): shard-rkl Known issues Here are the changes found in Patchwork_108313v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@parallel-balancer: - shard-iclb: NOTRUN -> [SKIP][1] ([i915#4525]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/shard-iclb8/igt@gem_exec_balan...@parallel-balancer.html * igt@gem_exec_balancer@parallel-keep-in-fence: - shard-iclb: [PASS][2] -> [SKIP][3] ([i915#4525]) +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/shard-iclb2/igt@gem_exec_balan...@parallel-keep-in-fence.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/shard-iclb8/igt@gem_exec_balan...@parallel-keep-in-fence.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-iclb: [PASS][4] -> [FAIL][5] ([i915#2842]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/shard-iclb5/igt@gem_exec_fair@basic-p...@bcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/shard-iclb2/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/shard-glk5/igt@gem_exec_fair@basic-throt...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_params@no-bsd: - shard-iclb: NOTRUN -> [SKIP][9] ([fdo#109283]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/shard-iclb8/igt@gem_exec_par...@no-bsd.html * igt@gem_lmem_swapping@heavy-verify-random-ccs: - shard-iclb: NOTRUN -> [SKIP][10] ([i915#4613]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/shard-iclb8/igt@gem_lmem_swapp...@heavy-verify-random-ccs.html * igt@gem_mmap_gtt@fault-concurrent-y: - shard-snb: [PASS][11] -> [INCOMPLETE][12] ([i915#5161]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/shard-snb4/igt@gem_mmap_...@fault-concurrent-y.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/shard-snb7/igt@gem_mmap_...@fault-concurrent-y.html * igt@gem_pxp@verify-pxp-stale-buf-optout-execution: - shard-iclb: NOTRUN -> [SKIP][13] ([i915#4270]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/shard-iclb8/igt@gem_...@verify-pxp-stale-buf-optout-execution.html * igt@gem_workarounds@suspend-resume: - shard-apl: [PASS][14] -> [DMESG-WARN][15] ([i915#180]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/shard-apl2/igt@gem_workarou...@suspend-resume.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/shard-apl3/igt@gem_workarou...@suspend-resume.html * igt@gen3_render_tiledy_blits: - shard-iclb: NOTRUN -> [SKIP][16] ([fdo#109289]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/shard-iclb8/igt@gen3_render_tiledy_blits.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip: - shard-iclb: NOTRUN -> [SKIP][17] ([i915#5286]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/shard-iclb8/igt@kms_big...@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html * igt@kms_big_fb@yf-tiled-8bpp-rotate-0: - shard-iclb: NOTRUN -> [SKIP][18] ([fdo#110723]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/shard-iclb8/igt@kms_big...@yf-tiled-8bpp-rotate-0.html * igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_dg2_rc_ccs: - shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109278]) +7 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/shard-iclb8/igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_dg2_rc_ccs.html * igt@kms_chamelium@dp-mode-timings: - shard-iclb: NOTRUN -> [SKIP][20] ([fdo#109284] / [fdo#111827]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/shard-iclb8/igt@kms_chamel...@dp-mode-timings.html * igt@kms_content_protection@srm: - shard-iclb: NOTRUN -> [SKIP][21]
Re: [Intel-gfx] [PATCH v2 13/15] vfio/ccw: Use the new device life cycle helpers
> From: Eric Farman > Sent: Friday, September 9, 2022 4:51 AM > > On Thu, 2022-09-08 at 07:19 +, Tian, Kevin wrote: > > ping @Eric Farman. > > > > ccw is the only tricky player in this series. Please help take a look > > in case of > > any oversight here. > > Apologies, I had started looking at v1 before I left on holiday, and > only returned today. > > > > > > From: Tian, Kevin > > > Sent: Thursday, September 1, 2022 10:38 PM > > > > > > ccw is the only exception which cannot use vfio_alloc_device() > > > because > > > its private device structure is designed to serve both mdev and > > > parent. > > > Life cycle of the parent is managed by css_driver so > > > vfio_ccw_private > > > must be allocated/freed in css_driver probe/remove path instead of > > > conforming to vfio core life cycle for mdev. > > > > > > Given that use a wait/completion scheme so the mdev remove path > > > waits > > > after vfio_put_device() until receiving a completion notification > > > from > > > @release. The completion indicates that all active references on > > > vfio_device have been released. > > > > > > After that point although free of vfio_ccw_private is delayed to > > > css_driver it's at least guaranteed to have no parallel reference > > > on > > > released vfio device part from other code paths. > > > > > > memset() in @probe is removed. vfio_device is either already > > > cleared > > > when probed for the first time or cleared in @release from last > > > probe. > > > > > > The right fix is to introduce separate structures for mdev and > > > parent, > > > but this won't happen in short term per prior discussions. > > I did start looking at the above, while the mdev series is outstanding. > Will try to get back to that sooner rather than later, but for the > purposes of this series this patch looks/works fine to me. > > Reviewed-by: Eric Farman > Thanks!
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: HuC loading for DG2 (rev3)
== Series Details == Series: drm/i915: HuC loading for DG2 (rev3) URL : https://patchwork.freedesktop.org/series/107477/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: HuC loading for DG2 (rev3)
== Series Details == Series: drm/i915: HuC loading for DG2 (rev3) URL : https://patchwork.freedesktop.org/series/107477/ State : warning == Summary == Error: dim checkpatch failed 489f4c218bd4 mei: add support to GSC extended header 727f7def9db4 mei: bus: enable sending gsc commands 10aa5255ef38 mei: adjust extended header kdocs 950871b7918e mei: bus: extend bus API to support command streamer API 9c3dc73a2303 mei: pxp: add command streamer API to the PXP driver 6b17e119a8f9 mei: pxp: support matching with a gfx discrete card 88273f48a829 drm/i915/pxp: load the pxp module when we have a gsc-loaded huc 0d57efefcd9f drm/i915/pxp: implement function for sending tee stream command 3ce8cf8e7aba drm/i915/pxp: add huc authentication and loading command Traceback (most recent call last): File "scripts/spdxcheck.py", line 11, in import git ModuleNotFoundError: No module named 'git' Traceback (most recent call last): File "scripts/spdxcheck.py", line 11, in import git ModuleNotFoundError: No module named 'git' -:33: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #33: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 131 lines checked 03ab2c8a165b drm/i915/dg2: setup HuC loading via GSC 333589b269f3 drm/i915/huc: track delayed HuC load with a fence -:222: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around '>adev->aux_dev.dev != dev' #222: FILE: drivers/gpu/drm/i915/gt/uc/intel_huc.c:159: + if (!intf->adev || (>adev->aux_dev.dev != dev)) total: 0 errors, 0 warnings, 1 checks, 334 lines checked 1aa70916376f drm/i915/huc: stall media submission until HuC is loaded bc2a869b7bf5 drm/i915/huc: better define HuC status getparam possible return values. 9bece8713529 drm/i915/huc: define gsc-compatible HuC fw for DG2 -:28: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #28: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:94: +#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp, huc_gsc) \ + fw_def(DG2, 0, huc_gsc(dg2)) \ fw_def(ALDERLAKE_P, 0, huc_mmp(tgl, 7, 9, 3)) \ fw_def(ALDERLAKE_S, 0, huc_mmp(tgl, 7, 9, 3)) \ fw_def(DG1, 0, huc_mmp(dg1, 7, 9, 3)) \ -:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fw_def' - possible side-effects? #28: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:94: +#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp, huc_gsc) \ + fw_def(DG2, 0, huc_gsc(dg2)) \ fw_def(ALDERLAKE_P, 0, huc_mmp(tgl, 7, 9, 3)) \ fw_def(ALDERLAKE_S, 0, huc_mmp(tgl, 7, 9, 3)) \ fw_def(DG1, 0, huc_mmp(dg1, 7, 9, 3)) \ -:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'huc_mmp' - possible side-effects? #28: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:94: +#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp, huc_gsc) \ + fw_def(DG2, 0, huc_gsc(dg2)) \ fw_def(ALDERLAKE_P, 0, huc_mmp(tgl, 7, 9, 3)) \ fw_def(ALDERLAKE_S, 0, huc_mmp(tgl, 7, 9, 3)) \ fw_def(DG1, 0, huc_mmp(dg1, 7, 9, 3)) \ -:48: WARNING:LONG_LINE: line length of 111 exceeds 100 columns #48: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:156: +INTEL_HUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_HUC_FW_PATH_BLANK, MAKE_HUC_FW_PATH_MMP, MAKE_HUC_FW_PATH_GSC) total: 1 errors, 1 warnings, 2 checks, 83 lines checked f30edbe59419 HAX: drm/i915: force INTEL_MEI_GSC and INTEL_MEI_PXP on for CI
Re: [Intel-gfx] [PATCH v4 15/15] HAX: drm/i915: force INTEL_MEI_GSC and INTEL_MEI_PXP on for CI
I've submitted a merge request to have those flags turned on by default in our CI builds: https://gitlab.freedesktop.org/gfx-ci/i915-infra/-/merge_requests/116 Daniele On 9/8/2022 5:16 PM, Daniele Ceraolo Spurio wrote: Both are required for HuC loading. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Kconfig.debug | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug index e7fd3e76f8a2..a6576ffbc4dc 100644 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -48,6 +48,8 @@ config DRM_I915_DEBUG select DRM_I915_DEBUG_RUNTIME_PM select DRM_I915_SW_FENCE_DEBUG_OBJECTS select DRM_I915_SELFTEST + select INTEL_MEI_GSC + select INTEL_MEI_PXP select BROKEN # for prototype uAPI default n help
[Intel-gfx] [PATCH v4 15/15] HAX: drm/i915: force INTEL_MEI_GSC and INTEL_MEI_PXP on for CI
Both are required for HuC loading. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Kconfig.debug | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug index e7fd3e76f8a2..a6576ffbc4dc 100644 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -48,6 +48,8 @@ config DRM_I915_DEBUG select DRM_I915_DEBUG_RUNTIME_PM select DRM_I915_SW_FENCE_DEBUG_OBJECTS select DRM_I915_SELFTEST + select INTEL_MEI_GSC + select INTEL_MEI_PXP select BROKEN # for prototype uAPI default n help -- 2.37.2
[Intel-gfx] [PATCH v4 12/15] drm/i915/huc: stall media submission until HuC is loaded
Wait on the fence to be signalled to avoid the submissions finding HuC
not yet loaded.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Tony Ye
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 6 ++
drivers/gpu/drm/i915/i915_request.c| 24
2 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index 915d281c1c72..52db03620c60 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -81,6 +81,12 @@ static inline bool intel_huc_is_loaded_by_gsc(const struct
intel_huc *huc)
return huc->fw.loaded_via_gsc;
}
+static inline bool intel_huc_wait_required(struct intel_huc *huc)
+{
+ return intel_huc_is_used(huc) && intel_huc_is_loaded_by_gsc(huc) &&
+ !intel_huc_is_authenticated(huc);
+}
+
void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p);
#endif
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 62fad16a55e8..77f45a3cb01f 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1621,6 +1621,20 @@ i915_request_await_object(struct i915_request *to,
return ret;
}
+static void i915_request_await_huc(struct i915_request *rq)
+{
+ struct intel_huc *huc = >context->engine->gt->uc.huc;
+
+ /* don't stall kernel submissions! */
+ if (!rcu_access_pointer(rq->context->gem_context))
+ return;
+
+ if (intel_huc_wait_required(huc))
+ i915_sw_fence_await_sw_fence(>submit,
+>delayed_load.fence,
+>submitq);
+}
+
static struct i915_request *
__i915_request_ensure_parallel_ordering(struct i915_request *rq,
struct intel_timeline *timeline)
@@ -1702,6 +1716,16 @@ __i915_request_add_to_timeline(struct i915_request *rq)
struct intel_timeline *timeline = i915_request_timeline(rq);
struct i915_request *prev;
+ /*
+* Media workloads may require HuC, so stall them until HuC loading is
+* complete. Note that HuC not being loaded when a user submission
+* arrives can only happen when HuC is loaded via GSC and in that case
+* we still expect the window between us starting to accept submissions
+* and HuC loading completion to be small (a few hundred ms).
+*/
+ if (rq->engine->class == VIDEO_DECODE_CLASS)
+ i915_request_await_huc(rq);
+
/*
* Dependency tracking and request ordering along the timeline
* is special cased so that we can eliminate redundant ordering
--
2.37.2
[Intel-gfx] [PATCH v4 11/15] drm/i915/huc: track delayed HuC load with a fence
Given that HuC load is delayed on DG2, this patch adds support for a fence
that can be used to wait for load completion. No waiters are added in this
patch (they're coming up in the next one), to keep the focus of the
patch on the tracking logic.
The full HuC loading flow on boot DG2 is as follows:
1) i915 exports the GSC as an aux device;
2) the mei-gsc driver is loaded on the aux device;
3) the mei-pxp component is loaded;
4) mei-pxp calls back into i915 and we load the HuC.
Between steps 1 and 2 there can be several seconds of gap, mainly due to
the kernel doing other work during the boot.
The resume flow is slightly different, because we don't need to
re-expose or re-probe the aux device, so we go directly to step 3 once
i915 and mei-gsc have completed their resume flow.
Here's an example of the boot timing, captured with some logs added to
i915:
[ 17.908307] [drm] adding GSC device
[ 17.915717] [drm] i915 probe done
[ 22.282917] [drm] mei-gsc bound
[ 22.938153] [drm] HuC authenticated
Also to note is that if something goes wrong during GSC HW init the
mei-gsc driver will still bind, but steps 3 and 4 will not happen.
The status tracking is done by registering a bus_notifier to receive a
callback when the mei-gsc driver binds, with a large enough timeout to
account for delays. Once mei-gsc is bound, we switch to a smaller
timeout to wait for the mei-pxp component to load.
The fence is signalled on HuC load complete or if anything goes wrong in
any of the tracking steps. Timeout are enforced via hrtimer callbacks.
v2: fix includes (Jani)
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Alan Previn #v1
---
drivers/gpu/drm/i915/gt/intel_gsc.c| 22 ++-
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 199 +
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 23 +++
3 files changed, 241 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c
b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 7af6db3194dd..f544f70401f8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -142,8 +142,14 @@ static void gsc_destroy_one(struct drm_i915_private *i915,
struct intel_gsc_intf *intf = >intf[intf_id];
if (intf->adev) {
- auxiliary_device_delete(>adev->aux_dev);
- auxiliary_device_uninit(>adev->aux_dev);
+ struct auxiliary_device *aux_dev = >adev->aux_dev;
+
+ if (intf_id == 0)
+
intel_huc_unregister_gsc_notifier(_to_gt(gsc)->uc.huc,
+ aux_dev->dev.bus);
+
+ auxiliary_device_delete(aux_dev);
+ auxiliary_device_uninit(aux_dev);
intf->adev = NULL;
}
@@ -242,14 +248,24 @@ static void gsc_init_one(struct drm_i915_private *i915,
struct intel_gsc *gsc,
goto fail;
}
+ intf->adev = adev; /* needed by the notifier */
+
+ if (intf_id == 0)
+ intel_huc_register_gsc_notifier(_to_gt(gsc)->uc.huc,
+ aux_dev->dev.bus);
+
ret = auxiliary_device_add(aux_dev);
if (ret < 0) {
drm_err(>drm, "gsc aux add failed %d\n", ret);
+ if (intf_id == 0)
+
intel_huc_unregister_gsc_notifier(_to_gt(gsc)->uc.huc,
+ aux_dev->dev.bus);
+ intf->adev = NULL;
+
/* adev will be freed with the put_device() and .release
sequence */
auxiliary_device_uninit(aux_dev);
goto fail;
}
- intf->adev = adev;
return;
fail:
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index f0188931d8e4..13d93e69766f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -10,6 +10,9 @@
#include "intel_huc.h"
#include "i915_drv.h"
+#include
+#include
+
/**
* DOC: HuC
*
@@ -42,6 +45,164 @@
* HuC-specific commands.
*/
+/*
+ * MEI-GSC load is an async process. The probing of the exposed aux device
+ * (see intel_gsc.c) usually happens a few seconds after i915 probe, depending
+ * on when the kernel schedules it. Unless something goes terribly wrong, we're
+ * guaranteed for this to happen during boot, so the big timeout is a safety
net
+ * that we never expect to need.
+ * MEI-PXP + HuC load usually takes ~300ms, but if the GSC needs to be resumed
+ * and/or reset, this can take longer.
+ */
+#define GSC_INIT_TIMEOUT_MS 1
+#define PXP_INIT_TIMEOUT_MS 2000
+
+static int sw_fence_dummy_notify(struct i915_sw_fence *sf,
+enum i915_sw_fence_notify state)
+{
+ return NOTIFY_DONE;
+}
+
+static void __delayed_huc_load_complete(struct intel_huc *huc)
+{
+ if (!i915_sw_fence_done(>delayed_load.fence))
+
[Intel-gfx] [PATCH v4 08/15] drm/i915/pxp: implement function for sending tee stream command
From: Vitaly Lubart
Command to be sent via the stream interface are written to a local
memory page, whose address is then provided to the GSC.
The interface supports providing a full sg with multiple pages for both
input and output messages, but since for now we only aim to support short
and synchronous messages we can use a single page for both input and
output.
Note that the mei interface expects an sg of 4k pages, while our lmem pages
are 64k. If we ever need to support more than 4k we'll need to convert.
Added a TODO comment to the code to record this.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Cc: Alan Previn
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 114 -
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 6 ++
3 files changed, 124 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 2c1fc49ecec1..e0d09455a92e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -7,6 +7,7 @@
#include
#include
+#include "gem/i915_gem_region.h"
#include "i915_drv.h"
#include "intel_pxp.h"
@@ -69,6 +70,47 @@ static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
return ret;
}
+int intel_pxp_tee_stream_message(struct intel_pxp *pxp,
+u8 client_id, u32 fence_id,
+void *msg_in, size_t msg_in_len,
+void *msg_out, size_t msg_out_len)
+{
+ /* TODO: for bigger objects we need to use a sg of 4k pages */
+ const size_t max_msg_size = PAGE_SIZE;
+ struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+ struct i915_pxp_component *pxp_component = pxp->pxp_component;
+ unsigned int offset = 0;
+ struct scatterlist *sg;
+ int ret;
+
+ if (msg_in_len > max_msg_size || msg_out_len > max_msg_size)
+ return -ENOSPC;
+
+ mutex_lock(>tee_mutex);
+
+ if (unlikely(!pxp_component || !pxp_component->ops->gsc_command)) {
+ ret = -ENODEV;
+ goto unlock;
+ }
+
+ GEM_BUG_ON(!pxp->stream_cmd.obj);
+
+ sg = i915_gem_object_get_sg_dma(pxp->stream_cmd.obj, 0, );
+
+ memcpy(pxp->stream_cmd.vaddr, msg_in, msg_in_len);
+
+ ret = pxp_component->ops->gsc_command(pxp_component->tee_dev, client_id,
+ fence_id, sg, msg_in_len, sg);
+ if (ret < 0)
+ drm_err(>drm, "Failed to send PXP TEE gsc command\n");
+ else
+ memcpy(msg_out, pxp->stream_cmd.vaddr, msg_out_len);
+
+unlock:
+ mutex_unlock(>tee_mutex);
+ return ret;
+}
+
/**
* i915_pxp_tee_component_bind - bind function to pass the function pointers
to pxp_tee
* @i915_kdev: pointer to i915 kernel device
@@ -126,6 +168,66 @@ static const struct component_ops
i915_pxp_tee_component_ops = {
.unbind = i915_pxp_tee_component_unbind,
};
+static int alloc_streaming_command(struct intel_pxp *pxp)
+{
+ struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+ struct drm_i915_gem_object *obj = NULL;
+ void *cmd;
+ int err;
+
+ pxp->stream_cmd.obj = NULL;
+ pxp->stream_cmd.vaddr = NULL;
+
+ if (!IS_DGFX(i915))
+ return 0;
+
+ /* allocate lmem object of one page for PXP command memory and store it
*/
+ obj = i915_gem_object_create_lmem(i915, PAGE_SIZE,
I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ drm_err(>drm, "Failed to allocate pxp streaming
command!\n");
+ return PTR_ERR(obj);
+ }
+
+ err = i915_gem_object_pin_pages_unlocked(obj);
+ if (err) {
+ drm_err(>drm, "Failed to pin gsc message page!\n");
+ goto out_put;
+ }
+
+ /* map the lmem into the virtual memory pointer */
+ cmd = i915_gem_object_pin_map_unlocked(obj,
i915_coherent_map_type(i915, obj, true));
+ if (IS_ERR(cmd)) {
+ drm_err(>drm, "Failed to map gsc message page!\n");
+ err = PTR_ERR(cmd);
+ goto out_unpin;
+ }
+
+ memset(cmd, 0, obj->base.size);
+
+ pxp->stream_cmd.obj = obj;
+ pxp->stream_cmd.vaddr = cmd;
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+ return err;
+}
+
+static void free_streaming_command(struct intel_pxp *pxp)
+{
+ struct drm_i915_gem_object *obj = fetch_and_zero(>stream_cmd.obj);
+
+ if (!obj)
+ return;
+
+ i915_gem_object_unpin_map(obj);
+ i915_gem_object_unpin_pages(obj);
+ i915_gem_object_put(obj);
+}
+
int intel_pxp_tee_component_init(struct intel_pxp *pxp)
{
int ret;
@@ -134,16 +236,24 @@ int
[Intel-gfx] [PATCH v4 07/15] drm/i915/pxp: load the pxp module when we have a gsc-loaded huc
The mei_pxp module is required to send the command to load authenticate
the HuC to the GSC even if pxp is not in use for protected content
management.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile| 10 +++---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 32 +---
drivers/gpu/drm/i915/pxp/intel_pxp.h | 32
drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 8 +
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 8 -
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 11 +--
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 10 --
7 files changed, 57 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 522ef9b4aff3..589823ad62ed 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -307,15 +307,17 @@ i915-y += \
i915-y += i915_perf.o
-# Protected execution platform (PXP) support
-i915-$(CONFIG_DRM_I915_PXP) += \
+# Protected execution platform (PXP) support. Base support is required for HuC
+i915-y += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_tee.o
+
+i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_debugfs.o \
pxp/intel_pxp_irq.o \
pxp/intel_pxp_pm.o \
- pxp/intel_pxp_session.o \
- pxp/intel_pxp_tee.o
+ pxp/intel_pxp_session.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 17109c513259..b0bcc25bf1ce 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -103,19 +103,15 @@ static int create_vcs_context(struct intel_pxp *pxp)
static void destroy_vcs_context(struct intel_pxp *pxp)
{
- intel_engine_destroy_pinned_context(fetch_and_zero(>ce));
+ if (pxp->ce)
+ intel_engine_destroy_pinned_context(fetch_and_zero(>ce));
}
-void intel_pxp_init(struct intel_pxp *pxp)
+static void pxp_init_full(struct intel_pxp *pxp)
{
struct intel_gt *gt = pxp_to_gt(pxp);
int ret;
- if (!HAS_PXP(gt->i915))
- return;
-
- mutex_init(>tee_mutex);
-
/*
* we'll use the completion to check if there is a termination pending,
* so we start it as completed and we reinit it when a termination
@@ -124,8 +120,7 @@ void intel_pxp_init(struct intel_pxp *pxp)
init_completion(>termination);
complete_all(>termination);
- mutex_init(>arb_mutex);
- INIT_WORK(>session_work, intel_pxp_session_work);
+ intel_pxp_session_management_init(pxp);
ret = create_vcs_context(pxp);
if (ret)
@@ -143,11 +138,26 @@ void intel_pxp_init(struct intel_pxp *pxp)
destroy_vcs_context(pxp);
}
-void intel_pxp_fini(struct intel_pxp *pxp)
+void intel_pxp_init(struct intel_pxp *pxp)
{
- if (!intel_pxp_is_enabled(pxp))
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
+ /* we rely on the mei PXP module */
+ if (!IS_ENABLED(CONFIG_INTEL_MEI_PXP))
return;
+ /*
+* If HuC is loaded by GSC but PXP is disabled, we can skip the init of
+* the full PXP session/object management and just init the tee channel.
+*/
+ if (HAS_PXP(gt->i915))
+ pxp_init_full(pxp);
+ else if (intel_huc_is_loaded_by_gsc(>uc.huc) &&
intel_uc_uses_huc(>uc))
+ intel_pxp_tee_component_init(pxp);
+}
+
+void intel_pxp_fini(struct intel_pxp *pxp)
+{
pxp->arb_is_valid = false;
intel_pxp_tee_component_fini(pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 73847e535cab..2da309088c6d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -12,7 +12,6 @@
struct intel_pxp;
struct drm_i915_gem_object;
-#ifdef CONFIG_DRM_I915_PXP
struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp);
bool intel_pxp_is_enabled(const struct intel_pxp *pxp);
bool intel_pxp_is_active(const struct intel_pxp *pxp);
@@ -32,36 +31,5 @@ int intel_pxp_key_check(struct intel_pxp *pxp,
bool assign);
void intel_pxp_invalidate(struct intel_pxp *pxp);
-#else
-static inline void intel_pxp_init(struct intel_pxp *pxp)
-{
-}
-
-static inline void intel_pxp_fini(struct intel_pxp *pxp)
-{
-}
-
-static inline int intel_pxp_start(struct intel_pxp *pxp)
-{
- return -ENODEV;
-}
-
-static inline bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
-{
- return false;
-}
-
-static inline bool intel_pxp_is_active(const struct intel_pxp *pxp)
-{
- return false;
-}
-
-static inline int intel_pxp_key_check(struct intel_pxp *pxp,
- struct drm_i915_gem_object *obj,
- bool
[Intel-gfx] [PATCH v4 09/15] drm/i915/pxp: add huc authentication and loading command
From: Tomas Winkler
Add support for loading HuC via a pxp stream command.
V4:
1. Remove unnecessary include in intel_pxp_huc.h (Jani)
2. Adjust copyright year to 2022
Signed-off-by: Tomas Winkler
Signed-off-by: Vitaly Lubart
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp_huc.c | 69 +++
drivers/gpu/drm/i915/pxp/intel_pxp_huc.h | 13
.../drm/i915/pxp/intel_pxp_tee_interface.h| 23 ++-
4 files changed, 106 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_huc.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 589823ad62ed..5bee787d3c2a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -310,7 +310,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support. Base support is required for HuC
i915-y += \
pxp/intel_pxp.o \
- pxp/intel_pxp_tee.o
+ pxp/intel_pxp_tee.o \
+ pxp/intel_pxp_huc.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_cmd.o \
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
new file mode 100644
index ..7ec36d94e758
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2021-2022, Intel Corporation. All rights reserved.
+ */
+
+#include "drm/i915_drm.h"
+#include "i915_drv.h"
+
+#include "gem/i915_gem_region.h"
+#include "gt/intel_gt.h"
+
+#include "intel_pxp.h"
+#include "intel_pxp_huc.h"
+#include "intel_pxp_tee.h"
+#include "intel_pxp_types.h"
+#include "intel_pxp_tee_interface.h"
+
+int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ struct intel_huc *huc = >uc.huc;
+ struct pxp_tee_start_huc_auth_in huc_in = {0};
+ struct pxp_tee_start_huc_auth_out huc_out = {0};
+ dma_addr_t huc_phys_addr;
+ u8 client_id = 0;
+ u8 fence_id = 0;
+ int err;
+
+ if (!pxp->pxp_component)
+ return -ENODEV;
+
+ huc_phys_addr = i915_gem_object_get_dma_address(huc->fw.obj, 0);
+
+ /* write the PXP message into the lmem (the sg list) */
+ huc_in.header.api_version = PXP_TEE_43_APIVER;
+ huc_in.header.command_id = PXP_TEE_43_START_HUC_AUTH;
+ huc_in.header.status = 0;
+ huc_in.header.buffer_len = sizeof(huc_in.huc_base_address);
+ huc_in.huc_base_address = huc_phys_addr;
+
+ err = intel_pxp_tee_stream_message(pxp, client_id, fence_id,
+ _in, sizeof(huc_in),
+ _out, sizeof(huc_out));
+ if (err < 0) {
+ drm_err(>i915->drm,
+ "Failed to send HuC load and auth command to GSC
[%d]!\n",
+ err);
+ return err;
+ }
+
+ /*
+* HuC does sometimes survive suspend/resume (it depends on how "deep"
+* a sleep state the device reaches) so we can end up here on resume
+* with HuC already loaded, in which case the GSC will return
+* PXP_STATUS_OP_NOT_PERMITTED. We can therefore consider the GuC
+* correctly transferred in this scenario; if the same error is ever
+* returned with HuC not loaded we'll still catch it when we check the
+* authentication bit later.
+*/
+ if (huc_out.header.status != PXP_STATUS_SUCCESS &&
+ huc_out.header.status != PXP_STATUS_OP_NOT_PERMITTED) {
+ drm_err(>i915->drm,
+ "HuC load failed with GSC error = 0x%x\n",
+ huc_out.header.status);
+ return -EPROTO;
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_huc.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.h
new file mode 100644
index ..e40847a91c39
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_huc.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2021-2022, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_HUC_H__
+#define __INTEL_PXP_HUC_H__
+
+struct intel_pxp;
+
+int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp);
+
+#endif /* __INTEL_PXP_HUC_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
index 36e9b0868f5c..7edc1760f142 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */
/*
- * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ * Copyright(c) 2020-2022, Intel Corporation. All rights reserved.
*/
#ifndef __INTEL_PXP_TEE_INTERFACE_H__
@@ -9,8 +9,20
[Intel-gfx] [PATCH v4 13/15] drm/i915/huc: better define HuC status getparam possible return values.
The current HuC status getparam return values are a bit confusing in
regards to what happens in some scenarios. In particular, most of the
error cases cause the ioctl to return an error, but a couple of them,
INIT_FAIL and LOAD_FAIL, are not explicitly handled and neither is
their expected return value documented; these 2 error cases therefore
end up into the catch-all umbrella of the "HuC not loaded" case, with
this case therefore including both some error scenarios and the load
in progress one.
The updates included in this patch change the handling so that all
error cases behave the same way, i.e. return an errno code, and so
that the HuC load in progress case is unambiguous.
The patch also includes a small change to the FW init path to make sure
we always transition to an error state if something goes wrong.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Tony Ye
Acked-by: Tvrtko Ursulin
Acked-by: Tony Ye
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 14 +++---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 -
include/uapi/drm/i915_drm.h | 16
4 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 24451d000a6a..bfc5a8d3d603 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -441,6 +441,7 @@ int intel_guc_init(struct intel_guc *guc)
err_fw:
intel_uc_fw_fini(>fw);
out:
+ intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_INIT_FAIL);
i915_probe_error(gt->i915, "failed with %d\n", ret);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 13d93e69766f..529ddd1e9c06 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -285,6 +285,7 @@ int intel_huc_init(struct intel_huc *huc)
return 0;
out:
+ intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_INIT_FAIL);
drm_info(>drm, "HuC init failed with %d\n", err);
return err;
}
@@ -404,13 +405,8 @@ bool intel_huc_is_authenticated(struct intel_huc *huc)
* This function reads status register to verify if HuC
* firmware was successfully loaded.
*
- * Returns:
- * * -ENODEV if HuC is not present on this platform,
- * * -EOPNOTSUPP if HuC firmware is disabled,
- * * -ENOPKG if HuC firmware was not installed,
- * * -ENOEXEC if HuC firmware is invalid or mismatched,
- * * 0 if HuC firmware is not running,
- * * 1 if HuC firmware is authenticated and running.
+ * The return values match what is expected for the I915_PARAM_HUC_STATUS
+ * getparam.
*/
int intel_huc_check_status(struct intel_huc *huc)
{
@@ -423,6 +419,10 @@ int intel_huc_check_status(struct intel_huc *huc)
return -ENOPKG;
case INTEL_UC_FIRMWARE_ERROR:
return -ENOEXEC;
+ case INTEL_UC_FIRMWARE_INIT_FAIL:
+ return -ENOMEM;
+ case INTEL_UC_FIRMWARE_LOAD_FAIL:
+ return -EIO;
default:
break;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index af425916cdf6..4792960d9c04 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -890,7 +890,6 @@ int intel_uc_fw_init(struct intel_uc_fw *uc_fw)
out_unpin:
i915_gem_object_unpin_pages(uc_fw->obj);
out:
- intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_INIT_FAIL);
return err;
}
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 520ad2691a99..629198f1d8d8 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -645,6 +645,22 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)
+/*
+ * Query the status of HuC load.
+ *
+ * The query can fail in the following scenarios with the listed error codes:
+ * -ENODEV if HuC is not present on this platform,
+ * -EOPNOTSUPP if HuC firmware usage is disabled,
+ * -ENOPKG if HuC firmware fetch failed,
+ * -ENOEXEC if HuC firmware is invalid or mismatched,
+ * -ENOMEM if i915 failed to prepare the FW objects for transfer to the uC,
+ * -EIO if the FW transfer or the FW authentication failed.
+ *
+ * If the IOCTL is successful, the returned parameter will be set to one of the
+ * following values:
+ * * 0 if HuC firmware load is not complete,
+ * * 1 if HuC firmware is authenticated and running.
+ */
#define I915_PARAM_HUC_STATUS 42
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
--
2.37.2
[Intel-gfx] [PATCH v4 06/15] mei: pxp: support matching with a gfx discrete card
From: Tomas Winkler
With on-boards graphics card, both i915 and MEI
are in the same device hierarchy with the same parent,
while for discrete gfx card the MEI is its child device.
Adjust the match function for that scenario
by matching MEI parent device with i915.
V2:
1. More detailed commit message
2. Check for dev is not null before it is accessed.
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Vitaly Lubart
Cc: Greg Kroah-Hartman
Reviewed-by: Alan Previn
---
drivers/misc/mei/pxp/mei_pxp.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
index 17c5d201603f..afc047627800 100644
--- a/drivers/misc/mei/pxp/mei_pxp.c
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -159,17 +159,24 @@ static int mei_pxp_component_match(struct device *dev,
int subcomponent,
{
struct device *base = data;
+ if (!dev)
+ return 0;
+
if (!dev->driver || strcmp(dev->driver->name, "i915") ||
subcomponent != I915_COMPONENT_PXP)
return 0;
base = base->parent;
- if (!base)
+ if (!base) /* mei device */
return 0;
- base = base->parent;
- dev = dev->parent;
+ base = base->parent; /* pci device */
+ /* for dgfx */
+ if (base && dev == base)
+ return 1;
+ /* for pch */
+ dev = dev->parent;
return (base && dev && dev == base);
}
--
2.37.2
[Intel-gfx] [PATCH v4 02/15] mei: bus: enable sending gsc commands
From: Tomas Winkler
GSC command is and extended header containing a scatter gather
list and without a data buffer. Using MEI_CL_IO_SGL flag,
the caller send the GSC command as a data and the function internally
moves it to the extended header.
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Vitaly Lubart
Cc: Greg Kroah-Hartman
---
drivers/misc/mei/bus.c | 20 ++--
drivers/misc/mei/mei_dev.h | 4
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/mei/bus.c b/drivers/misc/mei/bus.c
index 46aa3554e97b..225f0b04c021 100644
--- a/drivers/misc/mei/bus.c
+++ b/drivers/misc/mei/bus.c
@@ -100,9 +100,18 @@ ssize_t __mei_cl_send(struct mei_cl *cl, const u8 *buf,
size_t length, u8 vtag,
cb->internal = !!(mode & MEI_CL_IO_TX_INTERNAL);
cb->blocking = !!(mode & MEI_CL_IO_TX_BLOCKING);
memcpy(cb->buf.data, buf, length);
+ /* hack we point data to header */
+ if (mode & MEI_CL_IO_SGL) {
+ cb->ext_hdr = (struct mei_ext_hdr *)cb->buf.data;
+ cb->buf.data = NULL;
+ cb->buf.size = 0;
+ }
rets = mei_cl_write(cl, cb);
+ if (mode & MEI_CL_IO_SGL && rets == 0)
+ rets = length;
+
out:
mutex_unlock(>device_lock);
@@ -205,9 +214,16 @@ ssize_t __mei_cl_recv(struct mei_cl *cl, u8 *buf, size_t
length, u8 *vtag,
goto free;
}
- r_length = min_t(size_t, length, cb->buf_idx);
- memcpy(buf, cb->buf.data, r_length);
+ /* for the GSC type - copy the extended header to the buffer */
+ if (cb->ext_hdr && cb->ext_hdr->type == MEI_EXT_HDR_GSC) {
+ r_length = min_t(size_t, length, cb->ext_hdr->length *
sizeof(u32));
+ memcpy(buf, cb->ext_hdr, r_length);
+ } else {
+ r_length = min_t(size_t, length, cb->buf_idx);
+ memcpy(buf, cb->buf.data, r_length);
+ }
rets = r_length;
+
if (vtag)
*vtag = cb->vtag;
diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h
index 31784bbc2d2a..8d8018428d9d 100644
--- a/drivers/misc/mei/mei_dev.h
+++ b/drivers/misc/mei/mei_dev.h
@@ -116,12 +116,16 @@ enum mei_cb_file_ops {
* @MEI_CL_IO_TX_INTERNAL: internal communication between driver and FW
*
* @MEI_CL_IO_RX_NONBLOCK: recv is non-blocking
+ *
+ * @MEI_CL_IO_SGL: send command with sgl list.
*/
enum mei_cl_io_mode {
MEI_CL_IO_TX_BLOCKING = BIT(0),
MEI_CL_IO_TX_INTERNAL = BIT(1),
MEI_CL_IO_RX_NONBLOCK = BIT(2),
+
+ MEI_CL_IO_SGL = BIT(3),
};
/*
--
2.37.2
[Intel-gfx] [PATCH v4 05/15] mei: pxp: add command streamer API to the PXP driver
From: Vitaly Lubart
The discrete graphics card with GSC firmware
using command streamer API hence it requires to enhance
pxp module with the new gsc_command() handler.
The handler is implemented via mei_pxp_gsc_command() which is
just a thin wrapper around mei_cldev_send_gsc_command()
V2:
1. More detailed commit message
2. Fix typo in the comments
V3: Rebase
V4:
1. Use forward declaration for struct scatterlist (Jani)
2. Drop double 'just' in the commit message
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Greg Kroah-Hartman
Reviewed-by: Alan Previn
---
drivers/misc/mei/pxp/mei_pxp.c | 28
include/drm/i915_pxp_tee_interface.h | 5 +
2 files changed, 33 insertions(+)
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
index 5c39457e3f53..17c5d201603f 100644
--- a/drivers/misc/mei/pxp/mei_pxp.c
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -77,10 +77,38 @@ mei_pxp_receive_message(struct device *dev, void *buffer,
size_t size)
return byte;
}
+/**
+ * mei_pxp_gsc_command() - sends a gsc command, by sending
+ * a sgl mei message to gsc and receiving reply from gsc
+ *
+ * @dev: device corresponding to the mei_cl_device
+ * @client_id: client id to send the command to
+ * @fence_id: fence id to send the command to
+ * @sg_in: scatter gather list containing addresses for rx message buffer
+ * @total_in_len: total length of data in 'in' sg, can be less than the sum of
buffers sizes
+ * @sg_out: scatter gather list containing addresses for tx message buffer
+ *
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static ssize_t mei_pxp_gsc_command(struct device *dev, u8 client_id, u32
fence_id,
+ struct scatterlist *sg_in, size_t
total_in_len,
+ struct scatterlist *sg_out)
+{
+ struct mei_cl_device *cldev;
+
+ if (!dev || !sg_in || !sg_out)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ return mei_cldev_send_gsc_command(cldev, client_id, fence_id, sg_in,
total_in_len, sg_out);
+}
+
static const struct i915_pxp_component_ops mei_pxp_ops = {
.owner = THIS_MODULE,
.send = mei_pxp_send_message,
.recv = mei_pxp_receive_message,
+ .gsc_command = mei_pxp_gsc_command,
};
static int mei_component_master_bind(struct device *dev)
diff --git a/include/drm/i915_pxp_tee_interface.h
b/include/drm/i915_pxp_tee_interface.h
index af593ec64469..a702b6ec17f7 100644
--- a/include/drm/i915_pxp_tee_interface.h
+++ b/include/drm/i915_pxp_tee_interface.h
@@ -8,6 +8,7 @@
#include
#include
+struct scatterlist;
/**
* struct i915_pxp_component_ops - ops for PXP services.
@@ -23,6 +24,10 @@ struct i915_pxp_component_ops {
int (*send)(struct device *dev, const void *message, size_t size);
int (*recv)(struct device *dev, void *buffer, size_t size);
+ ssize_t (*gsc_command)(struct device *dev, u8 client_id, u32 fence_id,
+ struct scatterlist *sg_in, size_t total_in_len,
+ struct scatterlist *sg_out);
+
};
/**
--
2.37.2
[Intel-gfx] [PATCH v4 04/15] mei: bus: extend bus API to support command streamer API
From: Vitaly Lubart
Add mei bus API for sending gsc commands: mei_cldev_send_gsc_command()
The GSC commands are originated in the graphics stack
and are in form of SGL DMA buffers.
The GSC commands are synchronous, the response is received
in the same call on the out sg list buffers.
The function setups pointers for in and out sg lists in the
mei sgl extended header and sends it to the firmware.
V2:
1. More detailed commit message
2. Fix typo in the comments
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Greg Kroah-Hartman
---
drivers/misc/mei/bus.c | 125 +
include/linux/mei_cl_bus.h | 6 ++
2 files changed, 131 insertions(+)
diff --git a/drivers/misc/mei/bus.c b/drivers/misc/mei/bus.c
index 225f0b04c021..fc885ba94b36 100644
--- a/drivers/misc/mei/bus.c
+++ b/drivers/misc/mei/bus.c
@@ -838,6 +838,131 @@ int mei_cldev_disable(struct mei_cl_device *cldev)
}
EXPORT_SYMBOL_GPL(mei_cldev_disable);
+/**
+ * mei_cldev_send_gsc_command - sends a gsc command, by sending
+ * a gsl mei message to gsc and receiving reply from gsc
+ *
+ * @cldev: me client device
+ * @client_id: client id to send the command to
+ * @fence_id: fence id to send the command to
+ * @sg_in: scatter gather list containing addresses for rx message buffer
+ * @total_in_len: total length of data in 'in' sg, can be less than the sum of
buffers sizes
+ * @sg_out: scatter gather list containing addresses for tx message buffer
+ *
+ * Return:
+ * * written size in bytes
+ * * < 0 on error
+ */
+ssize_t mei_cldev_send_gsc_command(struct mei_cl_device *cldev,
+ u8 client_id, u32 fence_id,
+ struct scatterlist *sg_in,
+ size_t total_in_len,
+ struct scatterlist *sg_out)
+{
+ struct mei_cl *cl;
+ struct mei_device *bus;
+ ssize_t ret = 0;
+
+ struct mei_ext_hdr_gsc_h2f *ext_hdr;
+ size_t buf_sz = sizeof(struct mei_ext_hdr_gsc_h2f);
+ int sg_out_nents, sg_in_nents;
+ int i;
+ struct scatterlist *sg;
+ struct mei_ext_hdr_gsc_f2h rx_msg;
+ unsigned int sg_len;
+
+ if (!cldev || !sg_in || !sg_out)
+ return -EINVAL;
+
+ cl = cldev->cl;
+ bus = cldev->bus;
+
+ dev_dbg(bus->dev, "client_id %u, fence_id %u\n", client_id, fence_id);
+
+ if (!bus->hbm_f_gsc_supported)
+ return -EOPNOTSUPP;
+
+ sg_out_nents = sg_nents(sg_out);
+ sg_in_nents = sg_nents(sg_in);
+ /* at least one entry in tx and rx sgls must be present */
+ if (sg_out_nents <= 0 || sg_in_nents <= 0)
+ return -EINVAL;
+
+ buf_sz += (sg_out_nents + sg_in_nents) * sizeof(struct mei_gsc_sgl);
+ ext_hdr = kzalloc(buf_sz, GFP_KERNEL);
+ if (!ext_hdr)
+ return -ENOMEM;
+
+ /* construct the GSC message */
+ ext_hdr->hdr.type = MEI_EXT_HDR_GSC;
+ ext_hdr->hdr.length = buf_sz / sizeof(u32); /* length is in dw */
+
+ ext_hdr->client_id = client_id;
+ ext_hdr->addr_type = GSC_ADDRESS_TYPE_PHYSICAL_SGL;
+ ext_hdr->fence_id = fence_id;
+ ext_hdr->input_address_count = sg_in_nents;
+ ext_hdr->output_address_count = sg_out_nents;
+ ext_hdr->reserved[0] = 0;
+ ext_hdr->reserved[1] = 0;
+
+ /* copy in-sgl to the message */
+ for (i = 0, sg = sg_in; i < sg_in_nents; i++, sg++) {
+ ext_hdr->sgl[i].low = lower_32_bits(sg_dma_address(sg));
+ ext_hdr->sgl[i].high = upper_32_bits(sg_dma_address(sg));
+ sg_len = min_t(unsigned int, sg_dma_len(sg), PAGE_SIZE);
+ ext_hdr->sgl[i].length = (sg_len <= total_in_len) ? sg_len :
total_in_len;
+ total_in_len -= ext_hdr->sgl[i].length;
+ }
+
+ /* copy out-sgl to the message */
+ for (i = sg_in_nents, sg = sg_out; i < sg_in_nents + sg_out_nents; i++,
sg++) {
+ ext_hdr->sgl[i].low = lower_32_bits(sg_dma_address(sg));
+ ext_hdr->sgl[i].high = upper_32_bits(sg_dma_address(sg));
+ sg_len = min_t(unsigned int, sg_dma_len(sg), PAGE_SIZE);
+ ext_hdr->sgl[i].length = sg_len;
+ }
+
+ /* send the message to GSC */
+ ret = __mei_cl_send(cl, (u8 *)ext_hdr, buf_sz, 0, MEI_CL_IO_SGL);
+ if (ret < 0) {
+ dev_err(bus->dev, "__mei_cl_send failed, returned %zd\n", ret);
+ goto end;
+ }
+ if (ret != buf_sz) {
+ dev_err(bus->dev, "__mei_cl_send returned %zd instead of
expected %zd\n",
+ ret, buf_sz);
+ ret = -EIO;
+ goto end;
+ }
+
+ /* receive the reply from GSC, note that at this point sg_in should
contain the reply */
+ ret = __mei_cl_recv(cl, (u8 *)_msg, sizeof(rx_msg), NULL,
MEI_CL_IO_SGL, 0);
+
+ if (ret
[Intel-gfx] [PATCH v4 14/15] drm/i915/huc: define gsc-compatible HuC fw for DG2
The fw name is different and we need to record the fact that the blob is
gsc-loaded, so add a new macro to help.
Note: A-step DG2 G10 does not support HuC loading via GSC and would
require a separate firmware to be loaded the legacy way, but that's
not a production stepping so we're not going to bother.
v2: rebase on new fw fetch logic
Signed-off-by: Daniele Ceraolo Spurio
Cc: Tony Ye
Reviewed-by: Alan Previn #v1
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 4792960d9c04..09e06ac8bcf1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -91,7 +91,8 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
fw_def(BROXTON, 0, guc_mmp(bxt, 70, 1, 1)) \
fw_def(SKYLAKE, 0, guc_mmp(skl, 70, 1, 1))
-#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp) \
+#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp, huc_gsc) \
+ fw_def(DG2, 0, huc_gsc(dg2)) \
fw_def(ALDERLAKE_P, 0, huc_mmp(tgl, 7, 9, 3)) \
fw_def(ALDERLAKE_S, 0, huc_mmp(tgl, 7, 9, 3)) \
fw_def(DG1, 0, huc_mmp(dg1, 7, 9, 3)) \
@@ -137,6 +138,9 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
#define MAKE_HUC_FW_PATH_BLANK(prefix_) \
__MAKE_UC_FW_PATH_BLANK(prefix_, "_huc")
+#define MAKE_HUC_FW_PATH_GSC(prefix_) \
+ __MAKE_UC_FW_PATH_BLANK(prefix_, "_huc_gsc")
+
#define MAKE_HUC_FW_PATH_MMP(prefix_, major_, minor_, patch_) \
__MAKE_UC_FW_PATH_MMP(prefix_, "_huc_", major_, minor_, patch_)
@@ -149,7 +153,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
MODULE_FIRMWARE(uc_);
INTEL_GUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH_MAJOR,
MAKE_GUC_FW_PATH_MMP)
-INTEL_HUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_HUC_FW_PATH_BLANK,
MAKE_HUC_FW_PATH_MMP)
+INTEL_HUC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_HUC_FW_PATH_BLANK,
MAKE_HUC_FW_PATH_MMP, MAKE_HUC_FW_PATH_GSC)
/*
* The next expansion of the table macros (in __uc_fw_auto_select below)
provides
@@ -164,6 +168,7 @@ struct __packed uc_fw_blob {
u8 major;
u8 minor;
u8 patch;
+ bool loaded_via_gsc;
};
#define UC_FW_BLOB_BASE(major_, minor_, patch_, path_) \
@@ -172,16 +177,16 @@ struct __packed uc_fw_blob {
.patch = patch_, \
.path = path_,
-#define UC_FW_BLOB_NEW(major_, minor_, patch_, path_) \
+#define UC_FW_BLOB_NEW(major_, minor_, patch_, gsc_, path_) \
{ UC_FW_BLOB_BASE(major_, minor_, patch_, path_) \
- .legacy = false }
+ .legacy = false, .loaded_via_gsc = gsc_ }
#define UC_FW_BLOB_OLD(major_, minor_, patch_, path_) \
{ UC_FW_BLOB_BASE(major_, minor_, patch_, path_) \
.legacy = true }
#define GUC_FW_BLOB(prefix_, major_, minor_) \
- UC_FW_BLOB_NEW(major_, minor_, 0, \
+ UC_FW_BLOB_NEW(major_, minor_, 0, false, \
MAKE_GUC_FW_PATH_MAJOR(prefix_, major_, minor_))
#define GUC_FW_BLOB_MMP(prefix_, major_, minor_, patch_) \
@@ -189,12 +194,15 @@ struct __packed uc_fw_blob {
MAKE_GUC_FW_PATH_MMP(prefix_, major_, minor_, patch_))
#define HUC_FW_BLOB(prefix_) \
- UC_FW_BLOB_NEW(0, 0, 0, MAKE_HUC_FW_PATH_BLANK(prefix_))
+ UC_FW_BLOB_NEW(0, 0, 0, false, MAKE_HUC_FW_PATH_BLANK(prefix_))
#define HUC_FW_BLOB_MMP(prefix_, major_, minor_, patch_) \
UC_FW_BLOB_OLD(major_, minor_, patch_, \
MAKE_HUC_FW_PATH_MMP(prefix_, major_, minor_, patch_))
+#define HUC_FW_BLOB_GSC(prefix_) \
+ UC_FW_BLOB_NEW(0, 0, 0, true, MAKE_HUC_FW_PATH_GSC(prefix_))
+
struct __packed uc_fw_platform_requirement {
enum intel_platform p;
u8 rev; /* first platform rev using this FW */
@@ -220,7 +228,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct
intel_uc_fw *uc_fw)
INTEL_GUC_FIRMWARE_DEFS(MAKE_FW_LIST, GUC_FW_BLOB,
GUC_FW_BLOB_MMP)
};
static const struct uc_fw_platform_requirement blobs_huc[] = {
- INTEL_HUC_FIRMWARE_DEFS(MAKE_FW_LIST, HUC_FW_BLOB,
HUC_FW_BLOB_MMP)
+ INTEL_HUC_FIRMWARE_DEFS(MAKE_FW_LIST, HUC_FW_BLOB,
HUC_FW_BLOB_MMP, HUC_FW_BLOB_GSC)
};
static const struct fw_blobs_by_type blobs_all[INTEL_UC_FW_NUM_TYPES] =
{
[INTEL_UC_FW_TYPE_GUC] = { blobs_guc, ARRAY_SIZE(blobs_guc) },
@@ -266,6 +274,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct
intel_uc_fw *uc_fw)
uc_fw->file_wanted.path = blob->path;
uc_fw->file_wanted.major_ver = blob->major;
uc_fw->file_wanted.minor_ver = blob->minor;
+ uc_fw->loaded_via_gsc = blob->loaded_via_gsc;
break;
}
--
2.37.2
[Intel-gfx] [PATCH v4 10/15] drm/i915/dg2: setup HuC loading via GSC
The GSC will perform both the load and the authentication, so we just
need to check the auth bit after the GSC has replied.
Since we require the PXP module to load the HuC, the earliest we can
trigger the load is during the pxp_bind operation.
Note that GSC-loaded HuC survives GT reset, so we need to just mark it
as ready when we re-init the GT HW.
V2: move setting of HuC fw error state to the failure path of the HuC
auth function, so it covers both the legacy and new auth flows
V4:
1. Fix typo in the commit message
2. style fix in intel_huc_wait_for_auth_complete()
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
Reviewed-by: Alan Previn #v2
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 41 +++
drivers/gpu/drm/i915/gt/uc/intel_huc.h| 2 ++
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 34 +++
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 14 +++-
5 files changed, 77 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 3bb8838e325a..f0188931d8e4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -125,6 +125,28 @@ void intel_huc_fini(struct intel_huc *huc)
intel_uc_fw_fini(>fw);
}
+int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
+{
+ struct intel_gt *gt = huc_to_gt(huc);
+ int ret;
+
+ ret = __intel_wait_for_register(gt->uncore,
+ huc->status.reg,
+ huc->status.mask,
+ huc->status.value,
+ 2, 50, NULL);
+
+ if (ret) {
+ drm_err(>i915->drm, "HuC: Firmware not verified %d\n", ret);
+ intel_uc_fw_change_status(>fw,
INTEL_UC_FIRMWARE_LOAD_FAIL);
+ return ret;
+ }
+
+ intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_RUNNING);
+ drm_info(>i915->drm, "HuC authenticated\n");
+ return 0;
+}
+
/**
* intel_huc_auth() - Authenticate HuC uCode
* @huc: intel_huc structure
@@ -161,27 +183,18 @@ int intel_huc_auth(struct intel_huc *huc)
}
/* Check authentication status, it should be done by now */
- ret = __intel_wait_for_register(gt->uncore,
- huc->status.reg,
- huc->status.mask,
- huc->status.value,
- 2, 50, NULL);
- if (ret) {
- DRM_ERROR("HuC: Firmware not verified %d\n", ret);
+ ret = intel_huc_wait_for_auth_complete(huc);
+ if (ret)
goto fail;
- }
- intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_RUNNING);
- drm_info(>i915->drm, "HuC authenticated\n");
return 0;
fail:
i915_probe_error(gt->i915, "HuC: Authentication failed %d\n", ret);
- intel_uc_fw_change_status(>fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
return ret;
}
-static bool huc_is_authenticated(struct intel_huc *huc)
+bool intel_huc_is_authenticated(struct intel_huc *huc)
{
struct intel_gt *gt = huc_to_gt(huc);
intel_wakeref_t wakeref;
@@ -223,7 +236,7 @@ int intel_huc_check_status(struct intel_huc *huc)
break;
}
- return huc_is_authenticated(huc);
+ return intel_huc_is_authenticated(huc);
}
void intel_huc_update_auth_status(struct intel_huc *huc)
@@ -231,7 +244,7 @@ void intel_huc_update_auth_status(struct intel_huc *huc)
if (!intel_uc_fw_is_loadable(>fw))
return;
- if (huc_is_authenticated(huc))
+ if (intel_huc_is_authenticated(huc))
intel_uc_fw_change_status(>fw,
INTEL_UC_FIRMWARE_RUNNING);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index d7e25b6e879e..51f9d96a3ca3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -26,8 +26,10 @@ void intel_huc_init_early(struct intel_huc *huc);
int intel_huc_init(struct intel_huc *huc);
void intel_huc_fini(struct intel_huc *huc);
int intel_huc_auth(struct intel_huc *huc);
+int intel_huc_wait_for_auth_complete(struct intel_huc *huc);
int intel_huc_check_status(struct intel_huc *huc);
void intel_huc_update_auth_status(struct intel_huc *huc);
+bool intel_huc_is_authenticated(struct intel_huc *huc);
static inline int intel_huc_sanitize(struct intel_huc *huc)
{
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 9d6ab1e01639..4f246416db17 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -3,9 +3,43 @@
* Copyright © 2014-2019 Intel Corporation
*/
[Intel-gfx] [PATCH v4 01/15] mei: add support to GSC extended header
From: Tomas Winkler
GSC extend header is of variable size and data
is provided in a sgl list inside the header
and not in the data buffers, need to enable the path.
V2:
1. Add missing kdoc for mei_cl_cb
2. In mei_me_hbuf_write()
use dev_err() when validationg parameters instead of WARN_ON()
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Vitaly Lubart
Cc: Greg Kroah-Hartman
---
drivers/misc/mei/client.c| 55 --
drivers/misc/mei/hbm.c | 13
drivers/misc/mei/hw-me.c | 7 -
drivers/misc/mei/hw.h| 57
drivers/misc/mei/interrupt.c | 47 -
drivers/misc/mei/mei_dev.h | 4 +++
6 files changed, 160 insertions(+), 23 deletions(-)
diff --git a/drivers/misc/mei/client.c b/drivers/misc/mei/client.c
index 0b2fbe1335a7..6c8b71ae32c8 100644
--- a/drivers/misc/mei/client.c
+++ b/drivers/misc/mei/client.c
@@ -322,6 +322,7 @@ void mei_io_cb_free(struct mei_cl_cb *cb)
list_del(>list);
kfree(cb->buf.data);
+ kfree(cb->ext_hdr);
kfree(cb);
}
@@ -401,6 +402,7 @@ static struct mei_cl_cb *mei_io_cb_init(struct mei_cl *cl,
cb->buf_idx = 0;
cb->fop_type = type;
cb->vtag = 0;
+ cb->ext_hdr = NULL;
return cb;
}
@@ -1740,6 +1742,17 @@ static inline u8 mei_ext_hdr_set_vtag(void *ext, u8 vtag)
return vtag_hdr->hdr.length;
}
+static inline bool mei_ext_hdr_is_gsc(struct mei_ext_hdr *ext)
+{
+ return ext && ext->type == MEI_EXT_HDR_GSC;
+}
+
+static inline u8 mei_ext_hdr_set_gsc(struct mei_ext_hdr *ext, struct
mei_ext_hdr *gsc_hdr)
+{
+ memcpy(ext, gsc_hdr, mei_ext_hdr_len(gsc_hdr));
+ return ext->length;
+}
+
/**
* mei_msg_hdr_init - allocate and initialize mei message header
*
@@ -1752,14 +1765,17 @@ static struct mei_msg_hdr *mei_msg_hdr_init(const
struct mei_cl_cb *cb)
size_t hdr_len;
struct mei_ext_meta_hdr *meta;
struct mei_msg_hdr *mei_hdr;
- bool is_ext, is_vtag;
+ bool is_ext, is_hbm, is_gsc, is_vtag;
+ struct mei_ext_hdr *next_ext;
if (!cb)
return ERR_PTR(-EINVAL);
/* Extended header for vtag is attached only on the first fragment */
is_vtag = (cb->vtag && cb->buf_idx == 0);
- is_ext = is_vtag;
+ is_hbm = cb->cl->me_cl->client_id == 0;
+ is_gsc = ((!is_hbm) && cb->cl->dev->hbm_f_gsc_supported &&
mei_ext_hdr_is_gsc(cb->ext_hdr));
+ is_ext = is_vtag || is_gsc;
/* Compute extended header size */
hdr_len = sizeof(*mei_hdr);
@@ -1771,6 +1787,9 @@ static struct mei_msg_hdr *mei_msg_hdr_init(const struct
mei_cl_cb *cb)
if (is_vtag)
hdr_len += sizeof(struct mei_ext_hdr_vtag);
+ if (is_gsc)
+ hdr_len += mei_ext_hdr_len(cb->ext_hdr);
+
setup_hdr:
mei_hdr = kzalloc(hdr_len, GFP_KERNEL);
if (!mei_hdr)
@@ -1785,10 +1804,20 @@ static struct mei_msg_hdr *mei_msg_hdr_init(const
struct mei_cl_cb *cb)
goto out;
meta = (struct mei_ext_meta_hdr *)mei_hdr->extension;
+ meta->size = 0;
+ next_ext = (struct mei_ext_hdr *)meta->hdrs;
if (is_vtag) {
meta->count++;
- meta->size += mei_ext_hdr_set_vtag(meta->hdrs, cb->vtag);
+ meta->size += mei_ext_hdr_set_vtag(next_ext, cb->vtag);
+ next_ext = mei_ext_next(next_ext);
+ }
+
+ if (is_gsc) {
+ meta->count++;
+ meta->size += mei_ext_hdr_set_gsc(next_ext, cb->ext_hdr);
+ next_ext = mei_ext_next(next_ext);
}
+
out:
mei_hdr->length = hdr_len - sizeof(*mei_hdr);
return mei_hdr;
@@ -1812,14 +1841,14 @@ int mei_cl_irq_write(struct mei_cl *cl, struct
mei_cl_cb *cb,
struct mei_msg_hdr *mei_hdr = NULL;
size_t hdr_len;
size_t hbuf_len, dr_len;
- size_t buf_len;
+ size_t buf_len = 0;
size_t data_len;
int hbuf_slots;
u32 dr_slots;
u32 dma_len;
int rets;
bool first_chunk;
- const void *data;
+ const void *data = NULL;
if (WARN_ON(!cl || !cl->dev))
return -ENODEV;
@@ -1839,8 +1868,10 @@ int mei_cl_irq_write(struct mei_cl *cl, struct mei_cl_cb
*cb,
return 0;
}
- buf_len = buf->size - cb->buf_idx;
- data = buf->data + cb->buf_idx;
+ if (buf->data) {
+ buf_len = buf->size - cb->buf_idx;
+ data = buf->data + cb->buf_idx;
+ }
hbuf_slots = mei_hbuf_empty_slots(dev);
if (hbuf_slots < 0) {
rets = -EOVERFLOW;
@@ -1858,9 +1889,6 @@ int mei_cl_irq_write(struct mei_cl *cl, struct mei_cl_cb
*cb,
goto err;
}
- cl_dbg(dev, cl, "Extended Header %d vtag = %d\n",
- mei_hdr->extended, cb->vtag);
-
hdr_len =
[Intel-gfx] [PATCH v4 03/15] mei: adjust extended header kdocs
From: Tomas Winkler
Fix kdoc for struct mei_ext_hdr and mei_ext_begin().
V4: New in the series
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Greg Kroah-Hartman
---
drivers/misc/mei/hw.h | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/misc/mei/hw.h b/drivers/misc/mei/hw.h
index 14f89d96216b..25bfdd28cf3f 100644
--- a/drivers/misc/mei/hw.h
+++ b/drivers/misc/mei/hw.h
@@ -247,8 +247,7 @@ enum mei_ext_hdr_type {
* struct mei_ext_hdr - extend header descriptor (TLV)
* @type: enum mei_ext_hdr_type
* @length: length excluding descriptor
- * @ext_payload: payload of the specific extended header
- * @hdr: place holder for actual header
+ * @data: the extended header payload
*/
struct mei_ext_hdr {
u8 type;
@@ -287,12 +286,11 @@ struct mei_ext_hdr_vtag {
* Extended header iterator functions
*/
/**
- * mei_ext_hdr - extended header iterator begin
+ * mei_ext_begin - extended header iterator begin
*
* @meta: meta header of the extended header list
*
- * Return:
- * The first extended header
+ * Return: The first extended header
*/
static inline struct mei_ext_hdr *mei_ext_begin(struct mei_ext_meta_hdr *meta)
{
--
2.37.2
[Intel-gfx] [PATCH v4 00/15] drm/i915: HuC loading for DG2
On DG2, HuC loading is performed by the GSC, via a PXP command. The load operation itself is relatively simple (just send a message to the GSC with the physical address of the HuC in LMEM), but there are timing changes that requires special attention. In particular, to send a PXP command we need to first export the GSC as an aux device and then wait for the mei-gsc and mei-pxp modules to start, which means that HuC load will complete after i915 load is complete. This means that there is a small window of time after i915 is registered and before HuC is loaded during which userspace could submit and/or check the HuC load status, although this is quite unlikely to happen (HuC is usually loaded before kernel init/resume completes). We've consulted with the media team in regards to how to handle this and they've asked us to stall all userspace VCS submission until HuC is loaded. Stalls are expected to be very rare (if any), due to the fact that HuC is usually loaded before kernel init/resume is completed. Timeouts are in place to ensure all submissions are unlocked in case something goes wrong. Since we need to monitor the status of the mei driver to know what's happening and when to time out, a notifier has been added so we get a callback when the status of the mei driver changes. Note that this series includes several mei patches that add support for sending the HuC loading command via mei-gsc. We plan to merge those patches through the drm tree because i915 is the sole user. v2: address review comments, Reporting HuC loading still in progress while we wait for mei-gsc init to complete, rebase on latest mei-gsc series. v3: fix cc list in mei patches. v4: update mei patches, fix includes, rebase on new FW fetch logic and merged mei-gsc support. Test-with: 20220818224216.3920822-1-daniele.ceraolospu...@intel.com Cc: Alan Previn Cc: Tony Ye Cc: Alexander Usyskin Cc: Tomas Winkler Cc: Greg Kroah-Hartman Daniele Ceraolo Spurio (7): drm/i915/pxp: load the pxp module when we have a gsc-loaded huc drm/i915/dg2: setup HuC loading via GSC drm/i915/huc: track delayed HuC load with a fence drm/i915/huc: stall media submission until HuC is loaded drm/i915/huc: better define HuC status getparam possible return values. drm/i915/huc: define gsc-compatible HuC fw for DG2 HAX: drm/i915: force INTEL_MEI_GSC and INTEL_MEI_PXP on for CI Tomas Winkler (5): mei: add support to GSC extended header mei: bus: enable sending gsc commands mei: adjust extended header kdocs mei: pxp: support matching with a gfx discrete card drm/i915/pxp: add huc authentication and loading command Vitaly Lubart (3): mei: bus: extend bus API to support command streamer API mei: pxp: add command streamer API to the PXP driver drm/i915/pxp: implement function for sending tee stream command drivers/gpu/drm/i915/Kconfig.debug| 2 + drivers/gpu/drm/i915/Makefile | 11 +- drivers/gpu/drm/i915/gt/intel_gsc.c | 22 +- drivers/gpu/drm/i915/gt/uc/intel_guc.c| 1 + drivers/gpu/drm/i915/gt/uc/intel_huc.c| 254 -- drivers/gpu/drm/i915/gt/uc/intel_huc.h| 31 +++ drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 34 +++ drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h | 1 + drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 24 +- drivers/gpu/drm/i915/i915_request.c | 24 ++ drivers/gpu/drm/i915/pxp/intel_pxp.c | 32 ++- drivers/gpu/drm/i915/pxp/intel_pxp.h | 32 --- drivers/gpu/drm/i915/pxp/intel_pxp_huc.c | 69 + drivers/gpu/drm/i915/pxp/intel_pxp_huc.h | 13 + drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 8 + drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 8 +- drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 11 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 138 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 5 + .../drm/i915/pxp/intel_pxp_tee_interface.h| 23 +- drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 6 + drivers/misc/mei/bus.c| 145 +- drivers/misc/mei/client.c | 55 ++-- drivers/misc/mei/hbm.c| 13 + drivers/misc/mei/hw-me.c | 7 +- drivers/misc/mei/hw.h | 65 - drivers/misc/mei/interrupt.c | 47 +++- drivers/misc/mei/mei_dev.h| 8 + drivers/misc/mei/pxp/mei_pxp.c| 41 ++- include/drm/i915_pxp_tee_interface.h | 5 + include/linux/mei_cl_bus.h| 6 + include/uapi/drm/i915_drm.h | 16 ++ 32 files changed, 1035 insertions(+), 122 deletions(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_huc.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_huc.h -- 2.37.2
Re: [Intel-gfx] [PATCH v4 00/15]
Please ignore this cover letter, I've only realized I was missing a title and aborted the git-send after sending it. Proper series coming in a couple of mins. Daniele On 9/8/2022 5:10 PM, Daniele Ceraolo Spurio wrote: On DG2, HuC loading is performed by the GSC, via a PXP command. The load operation itself is relatively simple (just send a message to the GSC with the physical address of the HuC in LMEM), but there are timing changes that requires special attention. In particular, to send a PXP command we need to first export the GSC as an aux device and then wait for the mei-gsc and mei-pxp modules to start, which means that HuC load will complete after i915 load is complete. This means that there is a small window of time after i915 is registered and before HuC is loaded during which userspace could submit and/or check the HuC load status, although this is quite unlikely to happen (HuC is usually loaded before kernel init/resume completes). We've consulted with the media team in regards to how to handle this and they've asked us to stall all userspace VCS submission until HuC is loaded. Stalls are expected to be very rare (if any), due to the fact that HuC is usually loaded before kernel init/resume is completed. Timeouts are in place to ensure all submissions are unlocked in case something goes wrong. Since we need to monitor the status of the mei driver to know what's happening and when to time out, a notifier has been added so we get a callback when the status of the mei driver changes. Note that this series includes several mei patches that add support for sending the HuC loading command via mei-gsc. We plan to merge those patches through the drm tree because i915 is the sole user. v2: address review comments, Reporting HuC loading still in progress while we wait for mei-gsc init to complete, rebase on latest mei-gsc series. v3: fix cc list in mei patches. v4: update mei patches, fix includes, rebase on new FW fetch logic and merged mei-gsc support. Test-with: 20220818224216.3920822-1-daniele.ceraolospu...@intel.com Cc: Alan Previn Cc: Tony Ye Cc: Alexander Usyskin Cc: Tomas Winkler Cc: Greg Kroah-Hartman Daniele Ceraolo Spurio (7): drm/i915/pxp: load the pxp module when we have a gsc-loaded huc drm/i915/dg2: setup HuC loading via GSC drm/i915/huc: track delayed HuC load with a fence drm/i915/huc: stall media submission until HuC is loaded drm/i915/huc: better define HuC status getparam possible return values. drm/i915/huc: define gsc-compatible HuC fw for DG2 HAX: drm/i915: force INTEL_MEI_GSC and INTEL_MEI_PXP on for CI Tomas Winkler (5): mei: add support to GSC extended header mei: bus: enable sending gsc commands mei: adjust extended header kdocs mei: pxp: support matching with a gfx discrete card drm/i915/pxp: add huc authentication and loading command Vitaly Lubart (3): mei: bus: extend bus API to support command streamer API mei: pxp: add command streamer API to the PXP driver drm/i915/pxp: implement function for sending tee stream command drivers/gpu/drm/i915/Kconfig.debug| 2 + drivers/gpu/drm/i915/Makefile | 11 +- drivers/gpu/drm/i915/gt/intel_gsc.c | 22 +- drivers/gpu/drm/i915/gt/uc/intel_guc.c| 1 + drivers/gpu/drm/i915/gt/uc/intel_huc.c| 254 -- drivers/gpu/drm/i915/gt/uc/intel_huc.h| 31 +++ drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 34 +++ drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h | 1 + drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 24 +- drivers/gpu/drm/i915/i915_request.c | 24 ++ drivers/gpu/drm/i915/pxp/intel_pxp.c | 32 ++- drivers/gpu/drm/i915/pxp/intel_pxp.h | 32 --- drivers/gpu/drm/i915/pxp/intel_pxp_huc.c | 69 + drivers/gpu/drm/i915/pxp/intel_pxp_huc.h | 13 + drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 8 + drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 8 +- drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 11 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 138 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 5 + .../drm/i915/pxp/intel_pxp_tee_interface.h| 23 +- drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 6 + drivers/misc/mei/bus.c| 145 +- drivers/misc/mei/client.c | 55 ++-- drivers/misc/mei/hbm.c| 13 + drivers/misc/mei/hw-me.c | 7 +- drivers/misc/mei/hw.h | 65 - drivers/misc/mei/interrupt.c | 47 +++- drivers/misc/mei/mei_dev.h| 8 + drivers/misc/mei/pxp/mei_pxp.c| 41 ++- include/drm/i915_pxp_tee_interface.h | 5 + include/linux/mei_cl_bus.h| 6 + include/uapi/drm/i915_drm.h | 16 ++ 32 files changed, 1035 insertions(+), 122 deletions(-)
[Intel-gfx] [PATCH v4 00/15]
On DG2, HuC loading is performed by the GSC, via a PXP command. The load operation itself is relatively simple (just send a message to the GSC with the physical address of the HuC in LMEM), but there are timing changes that requires special attention. In particular, to send a PXP command we need to first export the GSC as an aux device and then wait for the mei-gsc and mei-pxp modules to start, which means that HuC load will complete after i915 load is complete. This means that there is a small window of time after i915 is registered and before HuC is loaded during which userspace could submit and/or check the HuC load status, although this is quite unlikely to happen (HuC is usually loaded before kernel init/resume completes). We've consulted with the media team in regards to how to handle this and they've asked us to stall all userspace VCS submission until HuC is loaded. Stalls are expected to be very rare (if any), due to the fact that HuC is usually loaded before kernel init/resume is completed. Timeouts are in place to ensure all submissions are unlocked in case something goes wrong. Since we need to monitor the status of the mei driver to know what's happening and when to time out, a notifier has been added so we get a callback when the status of the mei driver changes. Note that this series includes several mei patches that add support for sending the HuC loading command via mei-gsc. We plan to merge those patches through the drm tree because i915 is the sole user. v2: address review comments, Reporting HuC loading still in progress while we wait for mei-gsc init to complete, rebase on latest mei-gsc series. v3: fix cc list in mei patches. v4: update mei patches, fix includes, rebase on new FW fetch logic and merged mei-gsc support. Test-with: 20220818224216.3920822-1-daniele.ceraolospu...@intel.com Cc: Alan Previn Cc: Tony Ye Cc: Alexander Usyskin Cc: Tomas Winkler Cc: Greg Kroah-Hartman Daniele Ceraolo Spurio (7): drm/i915/pxp: load the pxp module when we have a gsc-loaded huc drm/i915/dg2: setup HuC loading via GSC drm/i915/huc: track delayed HuC load with a fence drm/i915/huc: stall media submission until HuC is loaded drm/i915/huc: better define HuC status getparam possible return values. drm/i915/huc: define gsc-compatible HuC fw for DG2 HAX: drm/i915: force INTEL_MEI_GSC and INTEL_MEI_PXP on for CI Tomas Winkler (5): mei: add support to GSC extended header mei: bus: enable sending gsc commands mei: adjust extended header kdocs mei: pxp: support matching with a gfx discrete card drm/i915/pxp: add huc authentication and loading command Vitaly Lubart (3): mei: bus: extend bus API to support command streamer API mei: pxp: add command streamer API to the PXP driver drm/i915/pxp: implement function for sending tee stream command drivers/gpu/drm/i915/Kconfig.debug| 2 + drivers/gpu/drm/i915/Makefile | 11 +- drivers/gpu/drm/i915/gt/intel_gsc.c | 22 +- drivers/gpu/drm/i915/gt/uc/intel_guc.c| 1 + drivers/gpu/drm/i915/gt/uc/intel_huc.c| 254 -- drivers/gpu/drm/i915/gt/uc/intel_huc.h| 31 +++ drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 34 +++ drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h | 1 + drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 24 +- drivers/gpu/drm/i915/i915_request.c | 24 ++ drivers/gpu/drm/i915/pxp/intel_pxp.c | 32 ++- drivers/gpu/drm/i915/pxp/intel_pxp.h | 32 --- drivers/gpu/drm/i915/pxp/intel_pxp_huc.c | 69 + drivers/gpu/drm/i915/pxp/intel_pxp_huc.h | 13 + drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 8 + drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 8 +- drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 11 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 138 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 5 + .../drm/i915/pxp/intel_pxp_tee_interface.h| 23 +- drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 6 + drivers/misc/mei/bus.c| 145 +- drivers/misc/mei/client.c | 55 ++-- drivers/misc/mei/hbm.c| 13 + drivers/misc/mei/hw-me.c | 7 +- drivers/misc/mei/hw.h | 65 - drivers/misc/mei/interrupt.c | 47 +++- drivers/misc/mei/mei_dev.h| 8 + drivers/misc/mei/pxp/mei_pxp.c| 41 ++- include/drm/i915_pxp_tee_interface.h | 5 + include/linux/mei_cl_bus.h| 6 + include/uapi/drm/i915_drm.h | 16 ++ 32 files changed, 1035 insertions(+), 122 deletions(-) create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_huc.c create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_huc.h -- 2.37.2
[Intel-gfx] [CI] PR for new HuC binary
The following changes since commit 2f2f0181581d3e35bfdb9fc65f609ee9d3fbaeb7: Mellanox: Add new mlxsw_spectrum firmware xx.2010.3146 (2022-09-02 07:28:59 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware dg2_huc_7.10.6 for you to fetch changes up to c48676c87dc380899a2c900ab86ff082a1a1bb66: i915: add HuC 7.10.6 for DG2 (2022-09-08 16:49:21 -0700) Daniele Ceraolo Spurio (1): i915: add HuC 7.10.6 for DG2 WHENCE | 3 +++ i915/dg2_huc_gsc.bin | Bin 0 -> 626688 bytes 2 files changed, 3 insertions(+) create mode 100755 i915/dg2_huc_gsc.bin
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dsb: hide struct intel_dsb better
== Series Details == Series: drm/i915/dsb: hide struct intel_dsb better URL : https://patchwork.freedesktop.org/series/108310/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12099_full -> Patchwork_108310v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_108310v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_108310v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_108310v1_full: ### IGT changes ### Possible regressions * igt@gem_exec_schedule@wide@rcs0: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12099/shard-tglb3/igt@gem_exec_schedule@w...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/shard-tglb5/igt@gem_exec_schedule@w...@rcs0.html * igt@i915_pm_rps@engine-order: - shard-apl: [PASS][3] -> [FAIL][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12099/shard-apl4/igt@i915_pm_...@engine-order.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/shard-apl4/igt@i915_pm_...@engine-order.html Known issues Here are the changes found in Patchwork_108310v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-contexts-10ms: - shard-iclb: [PASS][5] -> [TIMEOUT][6] ([i915#3070]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12099/shard-iclb6/igt@gem_...@in-flight-contexts-10ms.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/shard-iclb5/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_eio@kms: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#5784]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12099/shard-tglb6/igt@gem_...@kms.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/shard-tglb3/igt@gem_...@kms.html * igt@gem_exec_balancer@parallel-keep-in-fence: - shard-iclb: [PASS][9] -> [SKIP][10] ([i915#4525]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12099/shard-iclb2/igt@gem_exec_balan...@parallel-keep-in-fence.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/shard-iclb3/igt@gem_exec_balan...@parallel-keep-in-fence.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12099/shard-glk5/igt@gem_exec_fair@basic-throt...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/shard-apl1/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_softpin@evict-single-offset: - shard-apl: NOTRUN -> [FAIL][14] ([i915#4171]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/shard-apl7/igt@gem_soft...@evict-single-offset.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#454]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12099/shard-iclb8/igt@i915_pm...@dc6-psr.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/shard-iclb7/igt@i915_pm...@dc6-psr.html * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs: - shard-glk: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#3886]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/shard-glk8/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3886]) +4 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/shard-apl3/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_ccs: - shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271]) +113 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/shard-apl7/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_ccs.html * igt@kms_chamelium@hdmi-edid-read: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +6 similar issues [20]:
[Intel-gfx] ✓ Fi.CI.BAT: success for i915: Add "standalone media" support for MTL (rev5)
== Series Details ==
Series: i915: Add "standalone media" support for MTL (rev5)
URL : https://patchwork.freedesktop.org/series/107908/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12101 -> Patchwork_107908v5
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/index.html
Participating hosts (42 -> 29)
--
Missing(13): fi-rkl-11600 fi-bdw-5557u bat-dg1-5 bat-dg2-8 bat-adlm-1
bat-dg2-9 bat-adlp-6 bat-adlp-4 bat-rplp-1 bat-rpls-1 bat-rpls-2 bat-dg2-11
fi-bdw-samus
Known issues
Here are the changes found in Patchwork_107908v5 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gem:
- fi-blb-e6850: NOTRUN -> [DMESG-FAIL][1] ([i915#4528])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/fi-blb-e6850/igt@i915_selftest@l...@gem.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-pnv-d510:NOTRUN -> [SKIP][2] ([fdo#109271])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html
Possible fixes
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [DMESG-FAIL][3] ([i915#4528]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12101/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/fi-blb-e6850/igt@i915_selftest@l...@requests.html
- fi-pnv-d510:[DMESG-FAIL][5] ([i915#4528]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12101/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: [FAIL][7] ([i915#6298]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12101/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
Build changes
-
* Linux: CI_DRM_12101 -> Patchwork_107908v5
CI-20190529: 20190529
CI_DRM_12101: c8ca9239200ae0e5e53ae5a2f0d0a7411aef40c1 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6649: 7d91a6952dadaa9001b662ed60c08ccb8364929d @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107908v5: c8ca9239200ae0e5e53ae5a2f0d0a7411aef40c1 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
5ebdb9d9bef8 drm/i915/mtl: Hook up interrupts for standalone media
c5634336af9a drm/i915/mtl: Use primary GT's irq lock for media GT
132192a3942f drm/i915/xelpmp: Expose media as another GT
c4bae87e5d9f drm/i915/mtl: Add gsi_offset when emitting aux table invalidation
9b6161c8632f drm/i915/uncore: Add GSI offset to uncore
fe607cccaa26 drm/i915: Handle each GT on init/release and suspend/resume
a86da8bb224e drm/i915: Initialize MMIO access for each GT
96015664d5d7 drm/i915: Use a DRM-managed action to release the PCI bridge device
c046ed8ed2de drm/i915: Rename and expose common GT early init routine
64b9f2cf52ea drm/i915: Prepare more multi-GT initialization
6c71c5973dda drm/i915: Drop intel_gt_tile_cleanup()
85deb0621c44 drm/i915: Use managed allocations for extra uncore objects
b43c85921f61 drm/i915: Only hook up uncore->debug for primary uncore
d33d6584c08d drm/i915: Move locking and unclaimed check into
mmio_debug_{suspend, resume}
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107908v5/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Add "standalone media" support for MTL (rev5)
== Series Details == Series: i915: Add "standalone media" support for MTL (rev5) URL : https://patchwork.freedesktop.org/series/107908/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Add "standalone media" support for MTL (rev5)
== Series Details ==
Series: i915: Add "standalone media" support for MTL (rev5)
URL : https://patchwork.freedesktop.org/series/107908/
State : warning
== Summary ==
Error: dim checkpatch failed
6c1062d5ca5c drm/i915: Move locking and unclaimed check into
mmio_debug_{suspend, resume}
7177653099aa drm/i915: Only hook up uncore->debug for primary uncore
b8d94f04c11c drm/i915: Use managed allocations for extra uncore objects
e00663c87b21 drm/i915: Drop intel_gt_tile_cleanup()
40d07a66a0bc drm/i915: Prepare more multi-GT initialization
-:20: WARNING:TYPO_SPELLING: 'forseeable' may be misspelled - perhaps
'foreseeable'?
#20:
forseeable future. (Jani)
^^
-:76: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written
"gtdef->name"
#76: FILE: drivers/gpu/drm/i915/gt/intel_gt.c:839:
+gtdef->name != NULL;
total: 0 errors, 1 warnings, 1 checks, 154 lines checked
007ad6461e71 drm/i915: Rename and expose common GT early init routine
01c3e55744fd drm/i915: Use a DRM-managed action to release the PCI bridge device
1a7a252e05ce drm/i915: Initialize MMIO access for each GT
d6c997444feb drm/i915: Handle each GT on init/release and suspend/resume
ff941b5b951f drm/i915/uncore: Add GSI offset to uncore
efbcfb77e435 drm/i915/mtl: Add gsi_offset when emitting aux table invalidation
4dcce833b95f drm/i915/xelpmp: Expose media as another GT
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:86: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#86:
new file mode 100644
-:122: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written
"!uncore->regs"
#122: FILE: drivers/gpu/drm/i915/gt/intel_sa_media.c:32:
+ if (drm_WARN_ON(>drm, uncore->regs == NULL))
total: 0 errors, 1 warnings, 1 checks, 130 lines checked
03860f169e2f drm/i915/mtl: Use primary GT's irq lock for media GT
-:86: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#86: FILE: drivers/gpu/drm/i915/gt/intel_gt.c:791:
+ spinlock_t *irq_lock;
-:232: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#232: FILE: drivers/gpu/drm/i915/gt/intel_gt_types.h:166:
+ spinlock_t *irq_lock;
total: 0 errors, 0 warnings, 2 checks, 477 lines checked
5b0125fed70d drm/i915/mtl: Hook up interrupts for standalone media
Re: [Intel-gfx] [PATCH 04/19] drm/i915/perf: Determine gen12 oa ctx offset at runtime
On Thu, Sep 08, 2022 at 09:32:12PM +0300, Lionel Landwerlin wrote:
On 06/09/2022 23:35, Umesh Nerlige Ramappa wrote:
On Tue, Sep 06, 2022 at 10:48:50PM +0300, Lionel Landwerlin wrote:
On 23/08/2022 23:41, Umesh Nerlige Ramappa wrote:
Some SKUs of same gen12 platform may have different oactxctrl
offsets. For gen12, determine oactxctrl offsets at runtime.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 149 ++-
drivers/gpu/drm/i915/i915_perf_oa_regs.h | 2 +-
2 files changed, 120 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c
b/drivers/gpu/drm/i915/i915_perf.c
index 3526693d64fa..efa7eda83edd 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1363,6 +1363,67 @@ static int
gen12_get_render_context_id(struct i915_perf_stream *stream)
return 0;
}
+#define MI_OPCODE(x) (((x) >> 23) & 0x3f)
+#define IS_MI_LRI_CMD(x) (MI_OPCODE(x) ==
MI_OPCODE(MI_INSTR(0x22, 0)))
+#define MI_LRI_LEN(x) (((x) & 0xff) + 1)
Maybe you want to put this in intel_gpu_commands.h
+#define __valid_oactxctrl_offset(x) ((x) && (x) != U32_MAX)
+static bool __find_reg_in_lri(u32 *state, u32 reg, u32 *offset)
+{
+ u32 idx = *offset;
+ u32 len = MI_LRI_LEN(state[idx]) + idx;
+
+ idx++;
+ for (; idx < len; idx += 2)
+ if (state[idx] == reg)
+ break;
+
+ *offset = idx;
+ return state[idx] == reg;
+}
+
+static u32 __context_image_offset(struct intel_context *ce, u32 reg)
+{
+ u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
+ u32 *state = ce->lrc_reg_state;
+
+ for (offset = 0; offset < len; ) {
+ if (IS_MI_LRI_CMD(state[offset])) {
I'm a bit concerned you might find other matches with this.
Because let's say you run into a 3DSTATE_SUBSLICE_HASH_TABLE
instruction, you'll iterate the instruction dword by dword because
you don't know how to read its length and skip to the next one.
Now some of the fields can be programmed from userspace to look
like an MI_LRI header, so you start to read data in the wrong way.
Unfortunately I don't have a better solution. My only ask is that
you make __find_reg_in_lri() take the context image size in
parameter so it NEVER goes over the the context image.
To limit the risk you should run this function only one at driver
initialization and store the found offset.
Hmm, didn't know that there may be non-LRI commands in the context
image or user could add to the context image somehow. Does using the
context image size alone address these issues?
Even after including the size in the logic, any reason you think we
would be much more safer to do this from init? Is it because context
image is not touched by user yet?
The format of the image (commands in there and their offset) is fixed
per HW generation.
Only the date in each of the commands will vary per context.
In the case of MI_LRI, the register offsets are the same for all
context, but the value programmed will vary per context.
So executing once should be enough to find the right offset, rather
than every time we open the i915-perf stream.
In the current logic, the context image is traversed only once per
driver load (even though the first time it happens is when a stream is
opened). see saved_offset below.
I think once you have the logic to make sure you never read outside
the image it should be alright.
ok, I will check that __find_reg_in_lri() does not go over the context
image size.
Thanks,
Umesh
-Lionel
Thanks,
Umesh
Thanks,
-Lionel
+ if (__find_reg_in_lri(state, reg, ))
+ break;
+ } else {
+ offset++;
+ }
+ }
+
+ return offset < len ? offset : U32_MAX;
+}
+
+static int __set_oa_ctx_ctrl_offset(struct intel_context *ce)
+{
+ i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);
+ struct i915_perf *perf = >engine->i915->perf;
+ u32 saved_offset = perf->ctx_oactxctrl_offset;
+ u32 offset;
+
+ /* Do this only once. Failure is stored as offset of U32_MAX */
+ if (saved_offset)
+ return 0;
+
+ offset = __context_image_offset(ce, i915_mmio_reg_offset(reg));
+ perf->ctx_oactxctrl_offset = offset;
+
+ drm_dbg(>engine->i915->drm,
+ "%s oa ctx control at 0x%08x dword offset\n",
+ ce->engine->name, offset);
+
+ return __valid_oactxctrl_offset(offset) ? 0 : -ENODEV;
+}
+
+static bool engine_supports_mi_query(struct intel_engine_cs *engine)
+{
+ return engine->class == RENDER_CLASS;
+}
+
/**
* oa_get_render_ctx_id - determine and hold ctx hw id
* @stream: An i915-perf stream opened for OA metrics
@@ -1382,6 +1443,17 @@ static int oa_get_render_ctx_id(struct
i915_perf_stream *stream)
if (IS_ERR(ce))
return PTR_ERR(ce);
+ if (engine_supports_mi_query(stream->engine)) {
+ ret = __set_oa_ctx_ctrl_offset(ce);
+ if (ret && !(stream->sample_flags &
Re: [Intel-gfx] [PATCH v3.1 10/14] drm/i915/uncore: Add GSI offset to uncore
On 9/8/2022 3:45 PM, Matt Roper wrote:
GT non-engine registers (referred to as "GSI" registers by the spec)
have the same relative offsets on standalone media as they do on the
primary GT, just with an additional "GSI offset" added to their MMIO
address. If we store this GSI offset in the standalone media's
intel_uncore structure, it can be automatically applied to all GSI reg
reads/writes that happen on that GT, allowing us to re-use our existing
GT code with minimal changes.
Forcewake and shadowed register tables for the media GT (which will be
added in a future patch) are listed as final addresses that already
include the GSI offset, so we also need to add the GSI offset before
doing lookups of registers in one of those tables.
v2:
- Add comment on raw_reg_*() macros explaining why we don't bother with
GSI offsets in them. (Daniele)
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 10 +--
drivers/gpu/drm/i915/intel_uncore.h | 34 ++--
3 files changed, 41 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 0e139f7d75ed..82dc28643572 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -274,6 +274,7 @@ struct intel_gt_definition {
enum intel_gt_type type;
char *name;
u32 mapping_base;
+ u32 gsi_offset;
intel_engine_mask_t engine_mask;
};
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 452b3a31e965..5cd423c7b646 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -928,6 +928,9 @@ find_fw_domain(struct intel_uncore *uncore, u32 offset)
{
const struct intel_forcewake_range *entry;
+ if (IS_GSI_REG(offset))
+ offset += uncore->gsi_offset;
+
entry = BSEARCH(offset,
uncore->fw_domains_table,
uncore->fw_domains_table_entries,
@@ -1143,6 +1146,9 @@ static bool is_shadowed(struct intel_uncore *uncore, u32
offset)
if (drm_WARN_ON(>i915->drm, !uncore->shadowed_reg_table))
return false;
+ if (IS_GSI_REG(offset))
+ offset += uncore->gsi_offset;
+
return BSEARCH(offset,
uncore->shadowed_reg_table,
uncore->shadowed_reg_table_entries,
@@ -1995,8 +2001,8 @@ static int __fw_domain_init(struct intel_uncore *uncore,
d->uncore = uncore;
d->wake_count = 0;
- d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
- d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
+ d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set) +
uncore->gsi_offset;
+ d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack) +
uncore->gsi_offset;
d->id = domain_id;
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 4acb78a03233..5022bac80b67 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -136,6 +136,16 @@ struct intel_uncore {
spinlock_t lock; /** lock is also taken in irq contexts. */
+ /*
+* Do we need to apply an additional offset to reach the beginning
+* of the basic non-engine GT registers (referred to as "GSI" on
+* newer platforms, or "GT block" on older platforms)? If so, we'll
+* track that here and apply it transparently to registers in the
+* appropriate range to maintain compatibility with our existing
+* register definitions and GT code.
+*/
+ u32 gsi_offset;
+
unsigned int flags;
#define UNCORE_HAS_FORCEWAKE BIT(0)
#define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
@@ -294,19 +304,27 @@ intel_wait_for_register_fw(struct intel_uncore *uncore,
2, timeout_ms, NULL);
}
+#define IS_GSI_REG(reg) ((reg) < 0x4)
+
/* register access functions */
#define __raw_read(x__, s__) \
static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore
*uncore, \
i915_reg_t reg) \
{ \
- return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
+ u32 offset = i915_mmio_reg_offset(reg); \
+ if (IS_GSI_REG(offset)) \
+ offset += uncore->gsi_offset; \
+ return read##s__(uncore->regs + offset); \
}
#define __raw_write(x__, s__) \
static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore,
\
i915_reg_t reg, u##x__ val) \
{ \
- write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
+ u32 offset = i915_mmio_reg_offset(reg); \
+ if
[Intel-gfx] [PATCH v3.1 10/14] drm/i915/uncore: Add GSI offset to uncore
GT non-engine registers (referred to as "GSI" registers by the spec)
have the same relative offsets on standalone media as they do on the
primary GT, just with an additional "GSI offset" added to their MMIO
address. If we store this GSI offset in the standalone media's
intel_uncore structure, it can be automatically applied to all GSI reg
reads/writes that happen on that GT, allowing us to re-use our existing
GT code with minimal changes.
Forcewake and shadowed register tables for the media GT (which will be
added in a future patch) are listed as final addresses that already
include the GSI offset, so we also need to add the GSI offset before
doing lookups of registers in one of those tables.
v2:
- Add comment on raw_reg_*() macros explaining why we don't bother with
GSI offsets in them. (Daniele)
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 10 +--
drivers/gpu/drm/i915/intel_uncore.h | 34 ++--
3 files changed, 41 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 0e139f7d75ed..82dc28643572 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -274,6 +274,7 @@ struct intel_gt_definition {
enum intel_gt_type type;
char *name;
u32 mapping_base;
+ u32 gsi_offset;
intel_engine_mask_t engine_mask;
};
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 452b3a31e965..5cd423c7b646 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -928,6 +928,9 @@ find_fw_domain(struct intel_uncore *uncore, u32 offset)
{
const struct intel_forcewake_range *entry;
+ if (IS_GSI_REG(offset))
+ offset += uncore->gsi_offset;
+
entry = BSEARCH(offset,
uncore->fw_domains_table,
uncore->fw_domains_table_entries,
@@ -1143,6 +1146,9 @@ static bool is_shadowed(struct intel_uncore *uncore, u32
offset)
if (drm_WARN_ON(>i915->drm, !uncore->shadowed_reg_table))
return false;
+ if (IS_GSI_REG(offset))
+ offset += uncore->gsi_offset;
+
return BSEARCH(offset,
uncore->shadowed_reg_table,
uncore->shadowed_reg_table_entries,
@@ -1995,8 +2001,8 @@ static int __fw_domain_init(struct intel_uncore *uncore,
d->uncore = uncore;
d->wake_count = 0;
- d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
- d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
+ d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set) +
uncore->gsi_offset;
+ d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack) +
uncore->gsi_offset;
d->id = domain_id;
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gpu/drm/i915/intel_uncore.h
index 4acb78a03233..5022bac80b67 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -136,6 +136,16 @@ struct intel_uncore {
spinlock_t lock; /** lock is also taken in irq contexts. */
+ /*
+* Do we need to apply an additional offset to reach the beginning
+* of the basic non-engine GT registers (referred to as "GSI" on
+* newer platforms, or "GT block" on older platforms)? If so, we'll
+* track that here and apply it transparently to registers in the
+* appropriate range to maintain compatibility with our existing
+* register definitions and GT code.
+*/
+ u32 gsi_offset;
+
unsigned int flags;
#define UNCORE_HAS_FORCEWAKE BIT(0)
#define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
@@ -294,19 +304,27 @@ intel_wait_for_register_fw(struct intel_uncore *uncore,
2, timeout_ms, NULL);
}
+#define IS_GSI_REG(reg) ((reg) < 0x4)
+
/* register access functions */
#define __raw_read(x__, s__) \
static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore,
\
i915_reg_t reg) \
{ \
- return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
+ u32 offset = i915_mmio_reg_offset(reg); \
+ if (IS_GSI_REG(offset)) \
+ offset += uncore->gsi_offset; \
+ return read##s__(uncore->regs + offset); \
}
#define __raw_write(x__, s__) \
static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
i915_reg_t reg, u##x__ val) \
{ \
- write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
+ u32 offset = i915_mmio_reg_offset(reg); \
+ if (IS_GSI_REG(offset)) \
+ offset += uncore->gsi_offset; \
+ write##s__(val, uncore->regs
Re: [Intel-gfx] [PATCH v3 10/14] drm/i915/uncore: Add GSI offset to uncore
On Thu, Sep 08, 2022 at 02:16:27PM -0700, Ceraolo Spurio, Daniele wrote:
>
>
> On 9/6/2022 4:49 PM, Matt Roper wrote:
> > GT non-engine registers (referred to as "GSI" registers by the spec)
> > have the same relative offsets on standalone media as they do on the
> > primary GT, just with an additional "GSI offset" added to their MMIO
> > address. If we store this GSI offset in the standalone media's
> > intel_uncore structure, it can be automatically applied to all GSI reg
> > reads/writes that happen on that GT, allowing us to re-use our existing
> > GT code with minimal changes.
> >
> > Forcewake and shadowed register tables for the media GT (which will be
> > added in a future patch) are listed as final addresses that already
> > include the GSI offset, so we also need to add the GSI offset before
> > doing lookups of registers in one of those tables.
> >
> > Cc: Daniele Ceraolo Spurio
> > Signed-off-by: Matt Roper
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
> > drivers/gpu/drm/i915/intel_uncore.c | 10 --
> > drivers/gpu/drm/i915/intel_uncore.h | 22 --
> > 3 files changed, 29 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> > b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> > index 0e139f7d75ed..82dc28643572 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> > @@ -274,6 +274,7 @@ struct intel_gt_definition {
> > enum intel_gt_type type;
> > char *name;
> > u32 mapping_base;
> > + u32 gsi_offset;
> > intel_engine_mask_t engine_mask;
> > };
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> > b/drivers/gpu/drm/i915/intel_uncore.c
> > index 452b3a31e965..5cd423c7b646 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -928,6 +928,9 @@ find_fw_domain(struct intel_uncore *uncore, u32 offset)
> > {
> > const struct intel_forcewake_range *entry;
> > + if (IS_GSI_REG(offset))
> > + offset += uncore->gsi_offset;
> > +
> > entry = BSEARCH(offset,
> > uncore->fw_domains_table,
> > uncore->fw_domains_table_entries,
> > @@ -1143,6 +1146,9 @@ static bool is_shadowed(struct intel_uncore *uncore,
> > u32 offset)
> > if (drm_WARN_ON(>i915->drm, !uncore->shadowed_reg_table))
> > return false;
> > + if (IS_GSI_REG(offset))
> > + offset += uncore->gsi_offset;
> > +
> > return BSEARCH(offset,
> >uncore->shadowed_reg_table,
> >uncore->shadowed_reg_table_entries,
> > @@ -1995,8 +2001,8 @@ static int __fw_domain_init(struct intel_uncore
> > *uncore,
> > d->uncore = uncore;
> > d->wake_count = 0;
> > - d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
> > - d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
> > + d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set) +
> > uncore->gsi_offset;
> > + d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack) +
> > uncore->gsi_offset;
> > d->id = domain_id;
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.h
> > b/drivers/gpu/drm/i915/intel_uncore.h
> > index 4acb78a03233..7f1d7903a8f3 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.h
> > +++ b/drivers/gpu/drm/i915/intel_uncore.h
> > @@ -136,6 +136,16 @@ struct intel_uncore {
> > spinlock_t lock; /** lock is also taken in irq contexts. */
> > + /*
> > +* Do we need to apply an additional offset to reach the beginning
> > +* of the basic non-engine GT registers (referred to as "GSI" on
> > +* newer platforms, or "GT block" on older platforms)? If so, we'll
> > +* track that here and apply it transparently to registers in the
> > +* appropriate range to maintain compatibility with our existing
> > +* register definitions and GT code.
> > +*/
> > + u32 gsi_offset;
> > +
> > unsigned int flags;
> > #define UNCORE_HAS_FORCEWAKE BIT(0)
> > #define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
> > @@ -294,19 +304,27 @@ intel_wait_for_register_fw(struct intel_uncore
> > *uncore,
> > 2, timeout_ms, NULL);
> > }
> > +#define IS_GSI_REG(reg) ((reg) < 0x4)
> > +
> > /* register access functions */
> > #define __raw_read(x__, s__) \
> > static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore
> > *uncore, \
> > i915_reg_t reg) \
> > { \
> > - return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
> > + u32 offset = i915_mmio_reg_offset(reg); \
> > + if (IS_GSI_REG(offset)) \
> > + offset += uncore->gsi_offset; \
> > + return read##s__(uncore->regs + offset); \
> > }
> > #define __raw_write(x__, s__) \
> > static inline void __raw_uncore_write##x__(const struct intel_uncore
> > *uncore, \
> >
Re: [Intel-gfx] [PATCH v3 02/15] mei: add support to GSC extended header
> > On Fri, Aug 19, 2022 at 03:53:22PM -0700, Daniele Ceraolo Spurio wrote: > > --- a/drivers/misc/mei/hw-me.c > > +++ b/drivers/misc/mei/hw-me.c > > @@ -590,7 +590,10 @@ static int mei_me_hbuf_write(struct mei_device > *dev, > > u32 dw_cnt; > > int empty_slots; > > > > - if (WARN_ON(!hdr || !data || hdr_len & 0x3)) > > + if (WARN_ON(!hdr || hdr_len & 0x3)) > > + return -EINVAL; > > + > > + if (WARN_ON(!data && data_len)) > > Do not add more WARN_ON() calls, please just handle this properly and do > not reboot people's machines for a coding error :( As far as I understand WARN_ON() will produce solely a backtrace , This particular condition should never ever happen in theory, anyhow we can use dev_err() here as well. Thanks Tomas
Re: [Intel-gfx] [PATCH v3 13/14] drm/i915/mtl: Use primary GT's irq lock for media GT
On 9/6/2022 4:49 PM, Matt Roper wrote:
When we hook up interrupts (in the next patch), interrupts for the media
GT are still processed as part of the primary GT's interrupt flow. As
such, we should share the same IRQ lock with the primary GT. Let's
convert gt->irq_lock into a pointer and just point the media GT's
instance at the same lock the primary GT is using.
v2:
- Point media's gt->irq_lock at the primary GT lock properly. (Daniele)
- Fix jump target for intel_root_gt_init_early errors. (Daniele)
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 +++---
drivers/gpu/drm/i915/gt/intel_gt.c| 15 +--
drivers/gpu/drm/i915/gt/intel_gt.h| 2 +-
drivers/gpu/drm/i915/gt/intel_gt_irq.c| 16 ++--
drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 8 +++---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 26 +--
drivers/gpu/drm/i915/gt/intel_sa_media.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 24 -
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +--
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +--
drivers/gpu/drm/i915/i915_driver.c| 5 +++-
drivers/gpu/drm/i915/i915_irq.c | 4 +--
drivers/gpu/drm/i915/pxp/intel_pxp.c | 4 +--
drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 4 +--
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 14 +-
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 4 +--
17 files changed, 80 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 41acc285e8bf..6e0122b3dca2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1688,9 +1688,9 @@ bool intel_engine_irq_enable(struct intel_engine_cs
*engine)
return false;
/* Caller disables interrupts */
- spin_lock(>gt->irq_lock);
+ spin_lock(engine->gt->irq_lock);
engine->irq_enable(engine);
- spin_unlock(>gt->irq_lock);
+ spin_unlock(engine->gt->irq_lock);
return true;
}
@@ -1701,9 +1701,9 @@ void intel_engine_irq_disable(struct intel_engine_cs
*engine)
return;
/* Caller disables interrupts */
- spin_lock(>gt->irq_lock);
+ spin_lock(engine->gt->irq_lock);
engine->irq_disable(engine);
- spin_unlock(>gt->irq_lock);
+ spin_unlock(engine->gt->irq_lock);
}
void intel_engines_reset_default_submission(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 9b9c0ea73b7f..b59fb03ed274 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -38,7 +38,7 @@
void intel_gt_common_init_early(struct intel_gt *gt)
{
- spin_lock_init(>irq_lock);
+ spin_lock_init(gt->irq_lock);
INIT_LIST_HEAD(>closed_vma);
spin_lock_init(>closed_lock);
@@ -59,14 +59,19 @@ void intel_gt_common_init_early(struct intel_gt *gt)
}
/* Preliminary initialization of Tile 0 */
-void intel_root_gt_init_early(struct drm_i915_private *i915)
+int intel_root_gt_init_early(struct drm_i915_private *i915)
{
struct intel_gt *gt = to_gt(i915);
gt->i915 = i915;
gt->uncore = >uncore;
+ gt->irq_lock = drmm_kzalloc(>drm, sizeof(*gt->irq_lock),
GFP_KERNEL);
+ if (!gt->irq_lock)
+ return -ENOMEM;
intel_gt_common_init_early(gt);
+
+ return 0;
}
static int intel_gt_probe_lmem(struct intel_gt *gt)
@@ -783,12 +788,18 @@ static int intel_gt_tile_setup(struct intel_gt *gt,
phys_addr_t phys_addr)
if (!gt_is_root(gt)) {
struct intel_uncore *uncore;
+ spinlock_t *irq_lock;
uncore = drmm_kzalloc(>i915->drm, sizeof(*uncore), GFP_KERNEL);
if (!uncore)
return -ENOMEM;
+ irq_lock = drmm_kzalloc(>i915->drm, sizeof(*irq_lock), GFP_KERNEL);
+ if (!irq_lock)
+ return -ENOMEM;
+
gt->uncore = uncore;
+ gt->irq_lock = irq_lock;
intel_gt_common_init_early(gt);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index c9a359f35d0f..2ee582e287c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -45,7 +45,7 @@ static inline struct intel_gt *gsc_to_gt(struct intel_gsc
*gsc)
}
void intel_gt_common_init_early(struct intel_gt *gt);
-void intel_root_gt_init_early(struct drm_i915_private *i915);
+int intel_root_gt_init_early(struct drm_i915_private *i915);
int intel_gt_assign_ggtt(struct intel_gt *gt);
int intel_gt_init_mmio(struct intel_gt *gt);
int __must_check
Re: [Intel-gfx] [PATCH v3 10/14] drm/i915/uncore: Add GSI offset to uncore
On 9/6/2022 4:49 PM, Matt Roper wrote:
GT non-engine registers (referred to as "GSI" registers by the spec)
have the same relative offsets on standalone media as they do on the
primary GT, just with an additional "GSI offset" added to their MMIO
address. If we store this GSI offset in the standalone media's
intel_uncore structure, it can be automatically applied to all GSI reg
reads/writes that happen on that GT, allowing us to re-use our existing
GT code with minimal changes.
Forcewake and shadowed register tables for the media GT (which will be
added in a future patch) are listed as final addresses that already
include the GSI offset, so we also need to add the GSI offset before
doing lookups of registers in one of those tables.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 10 --
drivers/gpu/drm/i915/intel_uncore.h | 22 --
3 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 0e139f7d75ed..82dc28643572 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -274,6 +274,7 @@ struct intel_gt_definition {
enum intel_gt_type type;
char *name;
u32 mapping_base;
+ u32 gsi_offset;
intel_engine_mask_t engine_mask;
};
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 452b3a31e965..5cd423c7b646 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -928,6 +928,9 @@ find_fw_domain(struct intel_uncore *uncore, u32 offset)
{
const struct intel_forcewake_range *entry;
+ if (IS_GSI_REG(offset))
+ offset += uncore->gsi_offset;
+
entry = BSEARCH(offset,
uncore->fw_domains_table,
uncore->fw_domains_table_entries,
@@ -1143,6 +1146,9 @@ static bool is_shadowed(struct intel_uncore *uncore, u32
offset)
if (drm_WARN_ON(>i915->drm, !uncore->shadowed_reg_table))
return false;
+ if (IS_GSI_REG(offset))
+ offset += uncore->gsi_offset;
+
return BSEARCH(offset,
uncore->shadowed_reg_table,
uncore->shadowed_reg_table_entries,
@@ -1995,8 +2001,8 @@ static int __fw_domain_init(struct intel_uncore *uncore,
d->uncore = uncore;
d->wake_count = 0;
- d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
- d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
+ d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set) +
uncore->gsi_offset;
+ d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack) +
uncore->gsi_offset;
d->id = domain_id;
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 4acb78a03233..7f1d7903a8f3 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -136,6 +136,16 @@ struct intel_uncore {
spinlock_t lock; /** lock is also taken in irq contexts. */
+ /*
+* Do we need to apply an additional offset to reach the beginning
+* of the basic non-engine GT registers (referred to as "GSI" on
+* newer platforms, or "GT block" on older platforms)? If so, we'll
+* track that here and apply it transparently to registers in the
+* appropriate range to maintain compatibility with our existing
+* register definitions and GT code.
+*/
+ u32 gsi_offset;
+
unsigned int flags;
#define UNCORE_HAS_FORCEWAKE BIT(0)
#define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
@@ -294,19 +304,27 @@ intel_wait_for_register_fw(struct intel_uncore *uncore,
2, timeout_ms, NULL);
}
+#define IS_GSI_REG(reg) ((reg) < 0x4)
+
/* register access functions */
#define __raw_read(x__, s__) \
static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore
*uncore, \
i915_reg_t reg) \
{ \
- return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
+ u32 offset = i915_mmio_reg_offset(reg); \
+ if (IS_GSI_REG(offset)) \
+ offset += uncore->gsi_offset; \
+ return read##s__(uncore->regs + offset); \
}
#define __raw_write(x__, s__) \
static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore,
\
i915_reg_t reg, u##x__ val) \
{ \
- write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
+ u32 offset = i915_mmio_reg_offset(reg); \
+ if (IS_GSI_REG(offset)) \
+ offset += uncore->gsi_offset; \
+ write##s__(val, uncore->regs + offset); \
}
__raw_read(8, b)
__raw_read(16, w)
Do we also
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: A couple of if/else ladder refactors
== Series Details ==
Series: drm/i915: A couple of if/else ladder refactors
URL : https://patchwork.freedesktop.org/series/108315/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12100 -> Patchwork_108315v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/index.html
Participating hosts (42 -> 41)
--
Missing(1): fi-bdw-samus
Known issues
Here are the changes found in Patchwork_108315v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: NOTRUN -> [DMESG-FAIL][1] ([i915#4494] / [i915#4957])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][2] -> [DMESG-FAIL][3] ([i915#4528])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html
- fi-pnv-d510:[PASS][4] -> [DMESG-FAIL][5] ([i915#4528])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-dg1-5: NOTRUN -> [INCOMPLETE][6] ([i915#6011])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/bat-dg1-5/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#2403] /
[i915#4312])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/fi-pnv-d510/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_engines:
- bat-dg1-5: [INCOMPLETE][9] ([i915#4418]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][11] ([i915#4785]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-skl-6700k2: [INCOMPLETE][13] ([i915#6598]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
*
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [FAIL][15] ([i915#6298]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6598]: https://gitlab.freedesktop.org/drm/intel/issues/6598
Build changes
-
* Linux: CI_DRM_12100 -> Patchwork_108315v1
CI-20190529: 20190529
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: A couple of if/else ladder refactors
== Series Details == Series: drm/i915: A couple of if/else ladder refactors URL : https://patchwork.freedesktop.org/series/108315/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: A couple of if/else ladder refactors
== Series Details ==
Series: drm/i915: A couple of if/else ladder refactors
URL : https://patchwork.freedesktop.org/series/108315/
State : warning
== Summary ==
Error: dim checkpatch failed
8e2c6bd18bc2 drm/i915: Invert if/else ladder for frequency read
-:120: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#120: FILE: drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c:139:
+ return f12_5_mhz;
+ } else {
total: 0 errors, 1 warnings, 0 checks, 114 lines checked
bf4f7785d356 drm/i915/gt: Extract per-platform function for frequency read
a7ec6551bb03 drm/i915: Invert if/else ladder for stolen init
Re: [Intel-gfx] [PATCH v3 09/14] drm/i915: Handle each GT on init/release and suspend/resume
On 9/6/2022 4:49 PM, Matt Roper wrote:
In preparation for enabling a second GT, there are a number of GT/uncore
operations that happen during initialization or suspend flows that need
to be performed on each GT, not just the primary,
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Daniele Ceraolo Spurio
Daniele
---
drivers/gpu/drm/i915/i915_driver.c | 59 +-
1 file changed, 42 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index bb9ba1aed1bb..e5c3cf5045d4 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -310,8 +310,13 @@ static void intel_detect_preproduction_hw(struct
drm_i915_private *dev_priv)
static void sanitize_gpu(struct drm_i915_private *i915)
{
- if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
- __intel_gt_reset(to_gt(i915), ALL_ENGINES);
+ if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) {
+ struct intel_gt *gt;
+ unsigned int i;
+
+ for_each_gt(gt, i915, i)
+ __intel_gt_reset(gt, ALL_ENGINES);
+ }
}
/**
@@ -730,6 +735,8 @@ static void i915_driver_hw_remove(struct drm_i915_private
*dev_priv)
static void i915_driver_register(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = _priv->drm;
+ struct intel_gt *gt;
+ unsigned int i;
i915_gem_driver_register(dev_priv);
i915_pmu_register(dev_priv);
@@ -749,7 +756,8 @@ static void i915_driver_register(struct drm_i915_private
*dev_priv)
/* Depends on sysfs having been initialized */
i915_perf_register(dev_priv);
- intel_gt_driver_register(to_gt(dev_priv));
+ for_each_gt(gt, dev_priv, i)
+ intel_gt_driver_register(gt);
intel_display_driver_register(dev_priv);
@@ -768,6 +776,9 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
*/
static void i915_driver_unregister(struct drm_i915_private *dev_priv)
{
+ struct intel_gt *gt;
+ unsigned int i;
+
i915_switcheroo_unregister(dev_priv);
intel_unregister_dsm_handler();
@@ -777,7 +788,8 @@ static void i915_driver_unregister(struct drm_i915_private
*dev_priv)
intel_display_driver_unregister(dev_priv);
- intel_gt_driver_unregister(to_gt(dev_priv));
+ for_each_gt(gt, dev_priv, i)
+ intel_gt_driver_unregister(gt);
i915_perf_unregister(dev_priv);
i915_pmu_unregister(dev_priv);
@@ -799,6 +811,8 @@ static void i915_welcome_messages(struct drm_i915_private
*dev_priv)
{
if (drm_debug_enabled(DRM_UT_DRIVER)) {
struct drm_printer p = drm_debug_printer("i915 device info:");
+ struct intel_gt *gt;
+ unsigned int i;
drm_printf(, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
INTEL_DEVID(dev_priv),
@@ -811,7 +825,8 @@ static void i915_welcome_messages(struct drm_i915_private
*dev_priv)
intel_device_info_print(INTEL_INFO(dev_priv),
RUNTIME_INFO(dev_priv), );
i915_print_iommu_status(dev_priv, );
- intel_gt_info_print(_gt(dev_priv)->info, );
+ for_each_gt(gt, dev_priv, i)
+ intel_gt_info_print(>info, );
}
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
@@ -1230,13 +1245,15 @@ static int i915_drm_suspend_late(struct drm_device
*dev, bool hibernation)
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
struct intel_runtime_pm *rpm = _priv->runtime_pm;
- int ret;
+ struct intel_gt *gt;
+ int ret, i;
disable_rpm_wakeref_asserts(rpm);
i915_gem_suspend_late(dev_priv);
- intel_uncore_suspend(_priv->uncore);
+ for_each_gt(gt, dev_priv, i)
+ intel_uncore_suspend(gt->uncore);
intel_power_domains_suspend(dev_priv,
get_suspend_mode(dev_priv, hibernation));
@@ -1368,7 +1385,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
- int ret;
+ struct intel_gt *gt;
+ int ret, i;
/*
* We have a resume ordering issue with the snd-hda driver also
@@ -1422,9 +1440,10 @@ static int i915_drm_resume_early(struct drm_device *dev)
drm_err(_priv->drm,
"Resume prepare failed: %d, continuing anyway\n", ret);
- intel_uncore_resume_early(_priv->uncore);
-
- intel_gt_check_and_clear_faults(to_gt(dev_priv));
+ for_each_gt(gt, dev_priv, i) {
+ intel_uncore_resume_early(gt->uncore);
+ intel_gt_check_and_clear_faults(gt);
+ }
Re: [Intel-gfx] [PATCH v3 08/14] drm/i915: Initialize MMIO access for each GT
On 9/6/2022 4:49 PM, Matt Roper wrote:
In a multi-GT system we need to initialize MMIO access for each GT, not
just the primary GT.
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
Daniele
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_driver.c | 27 ++-
drivers/gpu/drm/i915/intel_uncore.c | 5 -
drivers/gpu/drm/i915/intel_uncore.h | 3 ++-
3 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index 1f46dd1ffaf7..bb9ba1aed1bb 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -431,7 +431,8 @@ static void i915_driver_late_release(struct
drm_i915_private *dev_priv)
*/
static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
{
- int ret;
+ struct intel_gt *gt;
+ int ret, i;
if (i915_inject_probe_failure(dev_priv))
return -ENODEV;
@@ -440,17 +441,27 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
if (ret < 0)
return ret;
- ret = intel_uncore_init_mmio(_priv->uncore);
- if (ret)
- return ret;
+ for_each_gt(gt, dev_priv, i) {
+ ret = intel_uncore_init_mmio(gt->uncore);
+ if (ret)
+ return ret;
+
+ ret = drmm_add_action_or_reset(_priv->drm,
+ intel_uncore_fini_mmio,
+ gt->uncore);
+ if (ret)
+ return ret;
+ }
/* Try to make sure MCHBAR is enabled before poking at it */
intel_setup_mchbar(dev_priv);
intel_device_info_runtime_init(dev_priv);
- ret = intel_gt_init_mmio(to_gt(dev_priv));
- if (ret)
- goto err_uncore;
+ for_each_gt(gt, dev_priv, i) {
+ ret = intel_gt_init_mmio(gt);
+ if (ret)
+ goto err_uncore;
+ }
/* As early as possible, scrub existing GPU state before clobbering */
sanitize_gpu(dev_priv);
@@ -459,7 +470,6 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
err_uncore:
intel_teardown_mchbar(dev_priv);
- intel_uncore_fini_mmio(_priv->uncore);
return ret;
}
@@ -471,7 +481,6 @@ static int i915_driver_mmio_probe(struct drm_i915_private
*dev_priv)
static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
{
intel_teardown_mchbar(dev_priv);
- intel_uncore_fini_mmio(_priv->uncore);
}
/**
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 2a32f8a65f34..452b3a31e965 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2455,8 +2455,11 @@ void intel_uncore_prune_engine_fw_domains(struct
intel_uncore *uncore,
}
}
-void intel_uncore_fini_mmio(struct intel_uncore *uncore)
+/* Called via drm-managed action */
+void intel_uncore_fini_mmio(struct drm_device *dev, void *data)
{
+ struct intel_uncore *uncore = data;
+
if (intel_uncore_has_forcewake(uncore)) {
iosf_mbi_punit_acquire();
iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gpu/drm/i915/intel_uncore.h
index 6100d0f4498a..4acb78a03233 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -33,6 +33,7 @@
#include "i915_reg_defs.h"
+struct drm_device;
struct drm_i915_private;
struct intel_runtime_pm;
struct intel_uncore;
@@ -220,7 +221,7 @@ void intel_uncore_prune_engine_fw_domains(struct
intel_uncore *uncore,
bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
void intel_uncore_cleanup_mmio(struct intel_uncore *uncore);
-void intel_uncore_fini_mmio(struct intel_uncore *uncore);
+void intel_uncore_fini_mmio(struct drm_device *dev, void *data);
void intel_uncore_suspend(struct intel_uncore *uncore);
void intel_uncore_resume_early(struct intel_uncore *uncore);
void intel_uncore_runtime_resume(struct intel_uncore *uncore);
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Fix perf limit reasons bit positions (rev2)
== Series Details == Series: drm/i915/gt: Fix perf limit reasons bit positions (rev2) URL : https://patchwork.freedesktop.org/series/108277/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12098_full -> Patchwork_108277v2_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_108277v2_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_108277v2_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_108277v2_full: ### IGT changes ### Possible regressions * igt@i915_pm_rps@engine-order: - shard-apl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-apl6/igt@i915_pm_...@engine-order.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v2/shard-apl4/igt@i915_pm_...@engine-order.html Known issues Here are the changes found in Patchwork_108277v2_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-glk: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [FAIL][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52]) ([i915#4392]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk1/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk1/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk1/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk2/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk2/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk2/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk3/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk3/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk3/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk3/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk5/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk5/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk5/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk6/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk6/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk6/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk7/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk7/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk7/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk8/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk8/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk8/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk9/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk9/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12098/shard-glk9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v2/shard-glk1/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v2/shard-glk1/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v2/shard-glk1/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v2/shard-glk2/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v2/shard-glk2/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v2/shard-glk2/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v2/shard-glk3/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108277v2/shard-glk3/boot.html [36]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Fix a potential UAF at device unload
== Series Details == Series: series starting with [1/2] drm/i915: Fix a potential UAF at device unload URL : https://patchwork.freedesktop.org/series/108314/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12100 -> Patchwork_108314v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_108314v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_108314v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108314v1/index.html Participating hosts (42 -> 41) -- Missing(1): fi-bdw-samus Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_108314v1: ### IGT changes ### Possible regressions * igt@i915_selftest@live@mman: - fi-rkl-guc: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-rkl-guc/igt@i915_selftest@l...@mman.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108314v1/fi-rkl-guc/igt@i915_selftest@l...@mman.html Known issues Here are the changes found in Patchwork_108314v1 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@hangcheck: - fi-hsw-g3258: [PASS][3] -> [INCOMPLETE][4] ([i915#3303] / [i915#4785]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108314v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html - bat-dg1-5: NOTRUN -> [DMESG-FAIL][5] ([i915#4494] / [i915#4957]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108314v1/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html - fi-snb-2600:[PASS][6] -> [INCOMPLETE][7] ([i915#3921]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108314v1/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@i915_suspend@basic-s2idle-without-i915: - bat-dg1-5: NOTRUN -> [INCOMPLETE][8] ([i915#6011]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108314v1/bat-dg1-5/igt@i915_susp...@basic-s2idle-without-i915.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108314v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html - fi-blb-e6850: NOTRUN -> [SKIP][10] ([fdo#109271]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108314v1/fi-blb-e6850/igt@kms_chamel...@common-hpd-after-suspend.html * igt@runner@aborted: - fi-hsw-g3258: NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#4312] / [i915#6246]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108314v1/fi-hsw-g3258/igt@run...@aborted.html Possible fixes * igt@i915_selftest@live@gem: - fi-blb-e6850: [DMESG-FAIL][12] ([i915#4528]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-blb-e6850/igt@i915_selftest@l...@gem.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108314v1/fi-blb-e6850/igt@i915_selftest@l...@gem.html * igt@i915_selftest@live@gt_engines: - bat-dg1-5: [INCOMPLETE][14] ([i915#4418]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/bat-dg1-5/igt@i915_selftest@live@gt_engines.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108314v1/bat-dg1-5/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[INCOMPLETE][16] ([i915#4785]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108314v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-skl-6700k2: [INCOMPLETE][18] ([i915#6598]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108314v1/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size: - fi-bsw-kefka: [FAIL][20] ([i915#6298]) -> [PASS][21] [20]:
Re: [Intel-gfx] [PATCH v4 10/11] drm/i915/mtl: Update CHICKEN_TRANS* register addresses
On Thu, Sep 01, 2022 at 11:03:41PM -0700, Radhakrishna Sripada wrote:
> From: Madhumitha Tolakanahalli Pradeep
>
>
> In Display version 14, Transcoder Chicken Registers have updated address.
> This patch performs checks to use the right register when required.
>
> v2: Omit display version check in i915_reg.h(Jani)
>
> Bspec: 34387, 50054
> Cc: Jani Nikula
> Signed-off-by: Madhumitha Tolakanahalli Pradeep
>
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 14 ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++-
> drivers/gpu/drm/i915/display/intel_psr.c | 6 +++--
> drivers/gpu/drm/i915/i915_reg.h | 25 +++-
> 4 files changed, 38 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index be7cff722196..a3d0d12084a9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -618,7 +618,10 @@ void intel_disable_transcoder(const struct
> intel_crtc_state *old_crtc_state)
> if (!IS_I830(dev_priv))
> val &= ~PIPECONF_ENABLE;
>
> - if (DISPLAY_VER(dev_priv) >= 12)
> + if (DISPLAY_VER(dev_priv) >= 14)
> + intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder),
> + FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
> + else if (DISPLAY_VER(dev_priv) >= 12)
> intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
>FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
>
> @@ -1838,7 +1841,9 @@ static void hsw_set_frame_start_delay(const struct
> intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
> + enum transcoder transcoder = crtc_state->cpu_transcoder;
> + i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ?
> MTL_CHICKEN_TRANS(transcoder) :
> + CHICKEN_TRANS(transcoder);
> u32 val;
>
> val = intel_de_read(dev_priv, reg);
> @@ -4033,6 +4038,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_display_power_domain_set power_domain_set = { };
> + i915_reg_t reg;
> bool active;
> u32 tmp;
>
> @@ -4124,7 +4130,9 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> }
>
> if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> - tmp = intel_de_read(dev_priv,
> CHICKEN_TRANS(pipe_config->cpu_transcoder));
> + reg = DISPLAY_VER(dev_priv) >= 14 ?
> MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) :
> + CHICKEN_TRANS(pipe_config->cpu_transcoder);
> + tmp = intel_de_read(dev_priv, reg);
>
> pipe_config->framestart_delay =
> REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
> } else {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 13abe2b2170e..298004cae5a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -568,7 +568,10 @@ static void intel_mst_enable_dp(struct
> intel_atomic_state *state,
> drm_dp_add_payload_part2(_dp->mst_mgr, >base,
>drm_atomic_get_mst_payload_state(mst_state,
> connector->port));
>
> - if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable)
> + if (DISPLAY_VER(dev_priv) >= 14 && pipe_config->fec_enable)
> + intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(trans), 0,
> + FECSTALL_DIS_DPTSTREAM_DPTTG);
> + else if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable)
> intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0,
>FECSTALL_DIS_DPTSTREAM_DPTTG);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 079b7d3d0c53..da2d0661b630 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1139,7 +1139,8 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
>
> if (intel_dp->psr.psr2_enabled) {
> if (DISPLAY_VER(dev_priv) == 9)
> - intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
> + intel_de_rmw(dev_priv,
> + CHICKEN_TRANS(cpu_transcoder), 0,
This whitespace-only change on a non-MTL codepath doesn't look
necessary.
>PSR2_VSC_ENABLE_PROG_HEADER |
>PSR2_ADD_VERTICAL_LINE_COUNT);
>
> @@ -1149,7 +1150,8 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
[Intel-gfx] [PATCH v1 2/3] drm/i915/gt: Extract per-platform function for frequency read
Instead of calling read_clock_frequency() to walk the if/else ladder
per platform, move the ladder to intel_gt_init_clock_frequency() and
use one function per branch.
With the new logic, it's now clear the call to
gen9_get_crystal_clock_freq() was just dead code, as gen9 is handled by
another function and there is no version 10. Remove that function and
the caller.
Cc: Ville Syrjälä
Signed-off-by: Lucas De Marchi
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index 93608c9349fd..ebddbf7542bc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -26,26 +26,6 @@ static u32 read_reference_ts_freq(struct intel_uncore
*uncore)
return base_freq + frac_freq;
}
-static u32 gen9_get_crystal_clock_freq(struct intel_uncore *uncore,
- u32 rpm_config_reg)
-{
- u32 f19_2_mhz = 1920;
- u32 f24_mhz = 2400;
- u32 crystal_clock =
- (rpm_config_reg & GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
- GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
-
- switch (crystal_clock) {
- case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
- return f19_2_mhz;
- case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
- return f24_mhz;
- default:
- MISSING_CASE(crystal_clock);
- return 0;
- }
-}
-
static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore,
u32 rpm_config_reg)
{
@@ -72,95 +52,101 @@ static u32 gen11_get_crystal_clock_freq(struct
intel_uncore *uncore,
}
}
-static u32 read_clock_frequency(struct intel_uncore *uncore)
+static u32 gen11_read_clock_frequency(struct intel_uncore *uncore)
{
- u32 f12_5_mhz = 1250;
- u32 f19_2_mhz = 1920;
- u32 f24_mhz = 2400;
+ u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
+ u32 freq = 0;
- if (GRAPHICS_VER(uncore->i915) >= 11) {
- u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
- u32 freq = 0;
+ /*
+* Note that on gen11+, the clock frequency may be reconfigured.
+* We do not, and we assume nobody else does.
+*
+* First figure out the reference frequency. There are 2 ways
+* we can compute the frequency, either through the
+* TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
+* tells us which one we should use.
+*/
+ if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
+ freq = read_reference_ts_freq(uncore);
+ } else {
+ u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
+
+ freq = gen11_get_crystal_clock_freq(uncore, c0);
/*
-* First figure out the reference frequency. There are 2 ways
-* we can compute the frequency, either through the
-* TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
-* tells us which one we should use.
-*/
- if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) ==
CTC_SOURCE_DIVIDE_LOGIC) {
- freq = read_reference_ts_freq(uncore);
- } else {
- u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
-
- if (GRAPHICS_VER(uncore->i915) >= 11)
- freq = gen11_get_crystal_clock_freq(uncore, c0);
- else
- freq = gen9_get_crystal_clock_freq(uncore, c0);
-
- /*
-* Now figure out how the command stream's timestamp
-* register increments from this frequency (it might
-* increment only every few clock cycle).
-*/
- freq >>= 3 - ((c0 &
GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
-
GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
- }
-
- return freq;
- } else if (GRAPHICS_VER(uncore->i915) >= 9) {
- u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
- u32 freq = 0;
-
- if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) ==
CTC_SOURCE_DIVIDE_LOGIC) {
- freq = read_reference_ts_freq(uncore);
- } else {
- freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
-
- /*
-* Now figure out how the command stream's timestamp
-* register increments from this frequency (it might
-* increment only every few clock cycle).
-*/
- freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
-
[Intel-gfx] [PATCH v1 1/3] drm/i915: Invert if/else ladder for frequency read
Continue converting the driver to the convention of last version first,
extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
be handled by the first branch.
With the new ranges it's easier to see what platform a branch started to
be taken. Besides the >= 11 change, the branch taken for GRAPHICS_VER == 10
is also different, but currently there is no such platform in i915.
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index d5d1b04dbcad..93608c9349fd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -78,77 +78,74 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
u32 f19_2_mhz = 1920;
u32 f24_mhz = 2400;
- if (GRAPHICS_VER(uncore->i915) <= 4) {
- /*
-* PRMs say:
-*
-* "The value in this register increments once every 16
-* hclks." (through the “Clocking Configuration”
-* (“CLKCFG”) MCHBAR register)
-*/
- return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
- } else if (GRAPHICS_VER(uncore->i915) <= 8) {
- /*
-* PRMs say:
-*
-* "The PCU TSC counts 10ns increments; this timestamp
-* reflects bits 38:3 of the TSC (i.e. 80ns granularity,
-* rolling over every 1.5 hours).
-*/
- return f12_5_mhz;
- } else if (GRAPHICS_VER(uncore->i915) <= 9) {
+ if (GRAPHICS_VER(uncore->i915) >= 11) {
u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
u32 freq = 0;
+ /*
+* First figure out the reference frequency. There are 2 ways
+* we can compute the frequency, either through the
+* TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
+* tells us which one we should use.
+*/
if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) ==
CTC_SOURCE_DIVIDE_LOGIC) {
freq = read_reference_ts_freq(uncore);
} else {
- freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
+ u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
+
+ if (GRAPHICS_VER(uncore->i915) >= 11)
+ freq = gen11_get_crystal_clock_freq(uncore, c0);
+ else
+ freq = gen9_get_crystal_clock_freq(uncore, c0);
/*
* Now figure out how the command stream's timestamp
* register increments from this frequency (it might
* increment only every few clock cycle).
*/
- freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
- CTC_SHIFT_PARAMETER_SHIFT);
+ freq >>= 3 - ((c0 &
GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
+
GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
}
return freq;
- } else if (GRAPHICS_VER(uncore->i915) <= 12) {
+ } else if (GRAPHICS_VER(uncore->i915) >= 9) {
u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
u32 freq = 0;
- /*
-* First figure out the reference frequency. There are 2 ways
-* we can compute the frequency, either through the
-* TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
-* tells us which one we should use.
-*/
if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) ==
CTC_SOURCE_DIVIDE_LOGIC) {
freq = read_reference_ts_freq(uncore);
} else {
- u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
-
- if (GRAPHICS_VER(uncore->i915) >= 11)
- freq = gen11_get_crystal_clock_freq(uncore, c0);
- else
- freq = gen9_get_crystal_clock_freq(uncore, c0);
+ freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
/*
* Now figure out how the command stream's timestamp
* register increments from this frequency (it might
* increment only every few clock cycle).
*/
- freq >>= 3 - ((c0 &
GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
-
GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
+ freq >>= 3 -
[Intel-gfx] [PATCH v1 3/3] drm/i915: Invert if/else ladder for stolen init
Continue converting the driver to the convention of last version first,
extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
be handled by the first branch.
Signed-off-by: Lucas De Marchi
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 4f4c9461a23b..acc561c0f0aa 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -430,48 +430,29 @@ static int i915_gem_init_stolen(struct
intel_memory_region *mem)
reserved_base = stolen_top;
reserved_size = 0;
- switch (GRAPHICS_VER(i915)) {
- case 2:
- case 3:
- break;
- case 4:
- if (!IS_G4X(i915))
- break;
- fallthrough;
- case 5:
- g4x_get_stolen_reserved(i915, uncore,
+ if (GRAPHICS_VER(i915) >= 11) {
+ icl_get_stolen_reserved(i915, uncore,
_base, _size);
- break;
- case 6:
- gen6_get_stolen_reserved(i915, uncore,
-_base, _size);
- break;
- case 7:
- if (IS_VALLEYVIEW(i915))
- vlv_get_stolen_reserved(i915, uncore,
- _base, _size);
- else
- gen7_get_stolen_reserved(i915, uncore,
-_base,
_size);
- break;
- case 8:
- case 9:
+ } else if (GRAPHICS_VER(i915) >= 8) {
if (IS_LP(i915))
chv_get_stolen_reserved(i915, uncore,
_base, _size);
else
bdw_get_stolen_reserved(i915, uncore,
_base, _size);
- break;
- default:
- MISSING_CASE(GRAPHICS_VER(i915));
- fallthrough;
- case 11:
- case 12:
- icl_get_stolen_reserved(i915, uncore,
- _base,
- _size);
- break;
+ } else if (GRAPHICS_VER(i915) >= 7) {
+ if (IS_VALLEYVIEW(i915))
+ vlv_get_stolen_reserved(i915, uncore,
+ _base, _size);
+ else
+ gen7_get_stolen_reserved(i915, uncore,
+_base,
_size);
+ } else if (GRAPHICS_VER(i915) >= 6) {
+ gen6_get_stolen_reserved(i915, uncore,
+_base, _size);
+ } else if (GRAPHICS_VER(i915) >= 5 || IS_G4X(i915)) {
+ g4x_get_stolen_reserved(i915, uncore,
+ _base, _size);
}
/*
--
b4 0.10.0-dev-df873
[Intel-gfx] [PATCH v1 0/3] drm/i915: A couple of if/else ladder refactors
Refactor code to follow the same convention as last platform first. This series includes one patch that had already been reviewed, for frequency read and 2 more refactors. Signed-off-by: Lucas De Marchi --- Lucas De Marchi (3): drm/i915: Invert if/else ladder for frequency read drm/i915/gt: Extract per-platform function for frequency read drm/i915: Invert if/else ladder for stolen init drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 51 +++- drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 171 +++-- 2 files changed, 93 insertions(+), 129 deletions(-) --- base-commit: adc57f2b82896fed07bc8e34956c15bb1448fca2 change-id: 20220908-if-ladder-df33a06d4f4e Best regards, -- Lucas De Marchi
[Intel-gfx] [PATCH 2/2] drm/i915: remove excessive i915_gem_drain_freed_objects
i915_gem_drain_workqueue() call i915_gem_drain_freed_objects() so no need to call that again. Signed-off-by: Nirmoy Das --- drivers/gpu/drm/i915/i915_gem.c | 2 -- drivers/gpu/drm/i915/selftests/mock_gem_device.c | 1 - 2 files changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e8a053eaaa89..e16718d79533 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1217,8 +1217,6 @@ void i915_gem_driver_remove(struct drm_i915_private *dev_priv) /* Flush any outstanding unpin_work. */ i915_gem_drain_workqueue(dev_priv); - - i915_gem_drain_freed_objects(dev_priv); } void i915_gem_driver_release(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index f5904e659ef2..5d02346c43a2 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -67,7 +67,6 @@ static void mock_device_release(struct drm_device *dev) intel_gt_driver_remove(to_gt(i915)); i915_gem_drain_workqueue(i915); - i915_gem_drain_freed_objects(i915); mock_fini_ggtt(to_gt(i915)->ggtt); destroy_workqueue(i915->wq); -- 2.37.3
[Intel-gfx] [PATCH 1/2] drm/i915: Fix a potential UAF at device unload
i915_gem_drain_freed_objects() might not be enough to
free all the objects and RCU delayed work might get
scheduled after the i915 device struct gets freed.
Call i915_gem_drain_workqueue() to catch all RCU delayed work.
Suggested-by: Chris Wilson
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0f49ec9d494a..e8a053eaaa89 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1254,7 +1254,7 @@ void i915_gem_init_early(struct drm_i915_private
*dev_priv)
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
{
- i915_gem_drain_freed_objects(dev_priv);
+ i915_gem_drain_workqueue(dev_priv);
GEM_BUG_ON(!llist_empty(_priv->mm.free_list));
GEM_BUG_ON(atomic_read(_priv->mm.free_count));
drm_WARN_ON(_priv->drm, dev_priv->mm.shrink_count);
--
2.37.3
Re: [Intel-gfx] [PATCH v4 09/11] drm/i915/mtl: Update MBUS_DBOX credits
On Thu, Sep 01, 2022 at 11:03:40PM -0700, Radhakrishna Sripada wrote:
> Display version 14 platforms have different credits values
> compared to ADL-P. Update the credits based on pipe usage.
>
> v2: Simplify DBOX BW Credit definition(MattR)
>
> Bspec: 49213
>
> Cc: Jose Roberto de Souza
> Cc: Matt Roper
> Original Author: Caz Yokoyama
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 +++
> drivers/gpu/drm/i915/intel_pm.c | 47 ++---
> 2 files changed, 47 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d22fabe35a0c..f9237586ab4f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1125,8 +1125,12 @@
> #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */
> #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14)
> #define MBUS_DBOX_BW_CREDIT(x)
> REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x)
> +#define MBUS_DBOX_BW_4CREDITS_MTL
> REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2)
> +#define MBUS_DBOX_BW_8CREDITS_MTL
> REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3)
> #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8)
> #define MBUS_DBOX_B_CREDIT(x)
> REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x)
> +#define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5)
> +#define MBUS_DBOX_I_CREDIT(x)
> REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x)
> #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0)
> #define MBUS_DBOX_A_CREDIT(x)
> REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ebce6171ccef..b19a1ecb010e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8448,6 +8448,27 @@ void intel_dbuf_post_plane_update(struct
> intel_atomic_state *state)
> new_dbuf_state->enabled_slices);
> }
>
> +static bool xelpdp_is_one_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
Bikeshed: s/one/only/ might be slightly more clear?
> +{
> + switch (pipe) {
> + case PIPE_A:
> + case PIPE_D:
> + if (is_power_of_2(active_pipes & (BIT(PIPE_A) | BIT(PIPE_D
Bikeshed: writing this with hweight might be more intuitive than
power_of_2? Or even just a direct check of the other pipe like
case PIPE_A:
return !(active_pipes & BIT(PIPE_D))
case PIPE_D:
return !(active_pipes & BIT(PIPE_A))
...
> + return true;
> + break;
> + case PIPE_B:
> + case PIPE_C:
> + if (is_power_of_2(active_pipes & (BIT(PIPE_B) | BIT(PIPE_C
> + return true;
> + break;
> + default: /* to suppress compiler warning */
> + MISSING_CASE(pipe);
> + break;
> + }
> +
> + return false;
> +}
> +
> void intel_mbus_dbox_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> @@ -8467,20 +8488,28 @@ void intel_mbus_dbox_update(struct intel_atomic_state
> *state)
>new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
> return;
>
> + if (DISPLAY_VER(i915) >= 14)
> + val |= MBUS_DBOX_I_CREDIT(2);
> +
> if (DISPLAY_VER(i915) >= 12) {
> val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
> val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
> val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
> }
>
> - /* Wa_22010947358:adl-p */
> - if (IS_ALDERLAKE_P(i915))
> + if (DISPLAY_VER(i915) >= 14)
> + val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) :
> + MBUS_DBOX_A_CREDIT(8);
> + else if (IS_ALDERLAKE_P(i915))
> + /* Wa_22010947358:adl-p */
> val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
>MBUS_DBOX_A_CREDIT(4);
> else
> val |= MBUS_DBOX_A_CREDIT(2);
>
> - if (IS_ALDERLAKE_P(i915)) {
> + if (DISPLAY_VER(i915) >= 14) {
> + val |= MBUS_DBOX_B_CREDIT(0xA);
> + } else if (IS_ALDERLAKE_P(i915)) {
> val |= MBUS_DBOX_BW_CREDIT(2);
> val |= MBUS_DBOX_B_CREDIT(8);
> } else if (DISPLAY_VER(i915) >= 12) {
> @@ -8492,10 +8521,20 @@ void intel_mbus_dbox_update(struct intel_atomic_state
> *state)
> }
>
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> + u32 pipe_val = val;
> +
> if (!new_crtc_state->hw.active ||
>
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move skl+ wm code into its own file
== Series Details ==
Series: drm/i915: Move skl+ wm code into its own file
URL : https://patchwork.freedesktop.org/series/108313/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12100 -> Patchwork_108313v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/index.html
Participating hosts (42 -> 41)
--
Missing(1): fi-bdw-samus
Known issues
Here are the changes found in Patchwork_108313v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u: [PASS][1] -> [DMESG-FAIL][2] ([i915#62])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-blb-e6850: NOTRUN -> [SKIP][4] ([fdo#109271])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/fi-blb-e6850/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [PASS][5] -> [DMESG-WARN][6] ([i915#62]) +12 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@i915_selftest@live@gem:
- fi-blb-e6850: [DMESG-FAIL][7] ([i915#4528]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-blb-e6850/igt@i915_selftest@l...@gem.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/fi-blb-e6850/igt@i915_selftest@l...@gem.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][9] ([i915#4785]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-skl-6700k2: [INCOMPLETE][11] ([i915#6598]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
*
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [FAIL][13] ([i915#6298]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12100/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108313v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#5886]: https://gitlab.freedesktop.org/drm/intel/issues/5886
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6598]: https://gitlab.freedesktop.org/drm/intel/issues/6598
[i915#6670]: https://gitlab.freedesktop.org/drm/intel/issues/6670
Build changes
-
* Linux: CI_DRM_12100 -> Patchwork_108313v1
CI-20190529: 20190529
CI_DRM_12100: 97f3651d0cd43a46f8065e7f64107f76bb9f704b @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6648: 3c9079c0b97445fbfc903b9c5a1d69707b80af80 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108313v1: 97f3651d0cd43a46f8065e7f64107f76bb9f704b @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
426f3fdfcefe drm/i915: Use REG_FIELD_GET() to extract skl+ wm latencies
433df39046bd drm/i915: Extract skl_watermark.c
acf50422e5b0 drm/i915: Split intel_read_wm_latency() into per-platform versions
== Logs
Re: [Intel-gfx] [PATCH] drm/i915: Kick rcu harder to free objects
On 9/8/2022 5:11 PM, Ville Syrjälä wrote:
On Thu, Sep 08, 2022 at 04:32:56PM +0200, Das, Nirmoy wrote:
Hi Ville,
I fixed a similar issue in DII but I couldn't reproduce it in drm
http://intel-gfx-pw.fi.intel.com/patch/228850/?series=15910=2.
I wonder if that fixes the problem you are facing then I can send that
to drm.
CI can tell you. It has been complaining about this for ages
Could you please share a url/failed test name. I must be searching the
wrong hw/test(https://intel-gfx-ci.01.org/tree/drm-tip/fi-ivb-3770.html).
Thanks,
Nirmoy
without
anyone doing anything about it.
diff --git a/drivers/gpu/drm/i915/i915_gem.c
b/drivers/gpu/drm/i915/i915_gem.c
index 7809be3a6840..5438e9277924 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1213,7 +1213,7 @@ void i915_gem_init_early(struct drm_i915_private
*dev_priv)
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
{
- i915_gem_drain_freed_objects(dev_priv);
+ i915_gem_drain_workqueue(dev_priv);
GEM_BUG_ON(!llist_empty(_priv->mm.free_list));
GEM_BUG_ON(atomic_read(_priv->mm.free_count));
drm_WARN_ON(_priv->drm, dev_priv->mm.shrink_count);
Regards,
Nirmoy
On 9/6/2022 7:46 PM, Ville Syrjala wrote:
From: Ville Syrjälä
On gen3 the selftests are pretty much always tripping this:
<4> [383.822424] pci :00:02.0: drm_WARN_ON(dev_priv->mm.shrink_count)
<4> [383.822546] WARNING: CPU: 2 PID: 3560 at
drivers/gpu/drm/i915/i915_gem.c:1223 i915_gem_cleanup_early+0x96/0xb0 [i915]
Looks to be due to the status page object lingering on the
purge_list. Call synchronize_rcu() ahead of it to make more
sure all objects have been freed.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_gem.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0f49ec9d494a..5b61f7ad6473 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1098,6 +1098,7 @@ void i915_gem_drain_freed_objects(struct drm_i915_private
*i915)
flush_delayed_work(>bdev.wq);
rcu_barrier();
}
+ synchronize_rcu();
}
/*
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Move skl+ wm code into its own file
== Series Details == Series: drm/i915: Move skl+ wm code into its own file URL : https://patchwork.freedesktop.org/series/108313/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Move skl+ wm code into its own file
== Series Details ==
Series: drm/i915: Move skl+ wm code into its own file
URL : https://patchwork.freedesktop.org/series/108313/
State : warning
== Summary ==
Error: dim checkpatch failed
eff551e7ad3c drm/i915: Split intel_read_wm_latency() into per-platform versions
129d570bf892 drm/i915: Extract skl_watermark.c
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:183: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#183:
new file mode 100644
-:544: ERROR:OPEN_BRACE: that open brace { should be on the previous line
#544: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:357:
+ for (level = ilk_wm_max_level(i915);
+!wm->wm[level].enable; --level)
+{ }
-:2805: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#2805: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:2618:
+ enast(old_wm->sagv.trans_wm.ignore_lines),
old_wm->sagv.trans_wm.lines,
-:2816: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#2816: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:2629:
+ enast(new_wm->sagv.trans_wm.ignore_lines),
new_wm->sagv.trans_wm.lines);
-:3011: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#3011: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:2824:
+ val = intel_uncore_read(>uncore,
PLANE_WM(pipe, plane_id, level));
-:3730: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'state' - possible
side-effects?
#3730: FILE: drivers/gpu/drm/i915/display/skl_watermark.h:67:
+#define intel_atomic_get_old_dbuf_state(state) \
+ to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state,
_i915(state->base.dev)->display.dbuf.obj))
-:3731: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#3731: FILE: drivers/gpu/drm/i915/display/skl_watermark.h:68:
+ to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state,
_i915(state->base.dev)->display.dbuf.obj))
-:3732: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'state' - possible
side-effects?
#3732: FILE: drivers/gpu/drm/i915/display/skl_watermark.h:69:
+#define intel_atomic_get_new_dbuf_state(state) \
+ to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state,
_i915(state->base.dev)->display.dbuf.obj))
-:3733: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#3733: FILE: drivers/gpu/drm/i915/display/skl_watermark.h:70:
+ to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state,
_i915(state->base.dev)->display.dbuf.obj))
total: 1 errors, 6 warnings, 2 checks, 7467 lines checked
1249118bce2e drm/i915: Use REG_FIELD_GET() to extract skl+ wm latencies
Re: [Intel-gfx] [PATCH] drm/i915: Kick rcu harder to free objects
On 9/8/2022 4:55 PM, Tvrtko Ursulin wrote:
On 08/09/2022 15:32, Das, Nirmoy wrote:
Hi Ville,
I fixed a similar issue in DII but I couldn't reproduce it in drm
http://intel-gfx-pw.fi.intel.com/patch/228850/?series=15910=2.
I wonder if that fixes the problem you are facing then I can send
that to drm.
diff --git a/drivers/gpu/drm/i915/i915_gem.c
b/drivers/gpu/drm/i915/i915_gem.c
index 7809be3a6840..5438e9277924 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1213,7 +1213,7 @@ void i915_gem_init_early(struct
drm_i915_private *dev_priv)
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
{
- i915_gem_drain_freed_objects(dev_priv);
+ i915_gem_drain_workqueue(dev_priv);
GEM_BUG_ON(!llist_empty(_priv->mm.free_list));
GEM_BUG_ON(atomic_read(_priv->mm.free_count));
drm_WARN_ON(_priv->drm, dev_priv->mm.shrink_count);
Yes why not, more black magic (count to three) but if it works... :) I
also spy the general area has been a bit neglected. Like:
Not sure what should be the correct solution here. I wonder if we might
have to change this because of
https://lwn.net/Articles/906975/ ?
i915_gem_driver_remove:
...
i915_gem_drain_workqueue
i915_gem_drain_freed_objects
While i915_gem_drain_workqueue:
...
i915_gem_drain_freed_objects
So i915_gem_drain_freed_objects in i915_gem_driver_remove is redundant
already.
Should i915_gem_drain_freed_objects be unexported and all callers made
just call i915_gem_drain_workqueue after your patch? Or if "drain free
objects" is considered more self descriptive it could be made as an
alias to i915_gem_drain_workqueue.
We are using i915_gem_drain_freed_objects() in many places and replacing
that with i915_gem_drain_workqueue() might have performance implication.
Nirmoy
Regards,
Tvrtko
Regards,
Nirmoy
On 9/6/2022 7:46 PM, Ville Syrjala wrote:
From: Ville Syrjälä
On gen3 the selftests are pretty much always tripping this:
<4> [383.822424] pci :00:02.0:
drm_WARN_ON(dev_priv->mm.shrink_count)
<4> [383.822546] WARNING: CPU: 2 PID: 3560 at
drivers/gpu/drm/i915/i915_gem.c:1223
i915_gem_cleanup_early+0x96/0xb0 [i915]
Looks to be due to the status page object lingering on the
purge_list. Call synchronize_rcu() ahead of it to make more
sure all objects have been freed.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_gem.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c
b/drivers/gpu/drm/i915/i915_gem.c
index 0f49ec9d494a..5b61f7ad6473 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1098,6 +1098,7 @@ void i915_gem_drain_freed_objects(struct
drm_i915_private *i915)
flush_delayed_work(>bdev.wq);
rcu_barrier();
}
+ synchronize_rcu();
}
/*
[Intel-gfx] [PATCH 3/3] drm/i915: Use REG_FIELD_GET() to extract skl+ wm latencies
From: Ville Syrjälä Replace the hand rolled stuff with REG_FIELD_GET() for reading out the skl+ watermark latencies. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/skl_watermark.c | 22 +++- drivers/gpu/drm/i915/i915_reg.h | 8 +++ 2 files changed, 12 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 25ca92ae8958..cb297725d5b9 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3239,13 +3239,10 @@ static void skl_read_wm_latency(struct drm_i915_private *i915, u16 wm[]) return; } - wm[0] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult; - wm[1] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & -GEN9_MEM_LATENCY_LEVEL_MASK) * mult; - wm[2] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & -GEN9_MEM_LATENCY_LEVEL_MASK) * mult; - wm[3] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & -GEN9_MEM_LATENCY_LEVEL_MASK) * mult; + wm[0] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult; + wm[1] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult; + wm[2] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult; + wm[3] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult; /* read the second set of memory latencies[4:7] */ val = 1; /* data0 to be programmed to 1 for second set */ @@ -3255,13 +3252,10 @@ static void skl_read_wm_latency(struct drm_i915_private *i915, u16 wm[]) return; } - wm[4] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult; - wm[5] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & -GEN9_MEM_LATENCY_LEVEL_MASK) * mult; - wm[6] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & -GEN9_MEM_LATENCY_LEVEL_MASK) * mult; - wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & -GEN9_MEM_LATENCY_LEVEL_MASK) * mult; + wm[4] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult; + wm[5] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult; + wm[6] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult; + wm[7] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult; adjust_wm_latency(i915, wm, max_level, read_latency); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c413eec3373f..7289e2b7da2c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6551,10 +6551,10 @@ #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ0x18 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 -#define GEN9_MEM_LATENCY_LEVEL_MASK0xFF -#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 -#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 -#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 +#define GEN9_MEM_LATENCY_LEVEL_3_7_MASKREG_GENMASK(31, 24) +#define GEN9_MEM_LATENCY_LEVEL_2_6_MASKREG_GENMASK(23, 16) +#define GEN9_MEM_LATENCY_LEVEL_1_5_MASKREG_GENMASK(15, 8) +#define GEN9_MEM_LATENCY_LEVEL_0_4_MASKREG_GENMASK(7, 0) #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 #define SKL_PCODE_CDCLK_CONTROL 0x7 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 -- 2.35.1
[Intel-gfx] [PATCH 1/3] drm/i915: Split intel_read_wm_latency() into per-platform versions
From: Ville Syrjälä
No reaon to have this humongous if ladder in intel_read_wm_latency().
Just split it into nicer per-platforms functions.
Also do the s/dev_priv/i915/ while touching all of this code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 201 +---
1 file changed, 110 insertions(+), 91 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 210c1f78cc90..096c311ed29f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2905,97 +2905,107 @@ adjust_wm_latency(struct drm_i915_private *i915,
wm[0] += 1;
}
-static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
- u16 wm[])
+static void mtl_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
{
- struct intel_uncore *uncore = _priv->uncore;
- int max_level = ilk_wm_max_level(dev_priv);
-
- if (DISPLAY_VER(dev_priv) >= 14) {
- u32 val;
-
- val = intel_uncore_read(uncore, MTL_LATENCY_LP0_LP1);
- wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
- wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
- val = intel_uncore_read(uncore, MTL_LATENCY_LP2_LP3);
- wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
- wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
- val = intel_uncore_read(uncore, MTL_LATENCY_LP4_LP5);
- wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
- wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
-
- adjust_wm_latency(dev_priv, wm, max_level, 6);
- } else if (DISPLAY_VER(dev_priv) >= 9) {
- int read_latency = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
- int mult = IS_DG2(dev_priv) ? 2 : 1;
- u32 val;
- int ret;
-
- /* read the first set of memory latencies[0:3] */
- val = 0; /* data0 to be programmed to 0 for first set */
- ret = snb_pcode_read(_priv->uncore,
GEN9_PCODE_READ_MEM_LATENCY,
-, NULL);
-
- if (ret) {
- drm_err(_priv->drm,
- "SKL Mailbox read error = %d\n", ret);
- return;
- }
-
- wm[0] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
- wm[1] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
- GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
- wm[2] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
- GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
- wm[3] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
- GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
-
- /* read the second set of memory latencies[4:7] */
- val = 1; /* data0 to be programmed to 1 for second set */
- ret = snb_pcode_read(_priv->uncore,
GEN9_PCODE_READ_MEM_LATENCY,
-, NULL);
- if (ret) {
- drm_err(_priv->drm,
- "SKL Mailbox read error = %d\n", ret);
- return;
- }
-
- wm[4] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
- wm[5] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
- GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
- wm[6] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
- GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
- wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
- GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
-
- adjust_wm_latency(dev_priv, wm, max_level, read_latency);
- } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
-
- wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
- if (wm[0] == 0)
- wm[0] = REG_FIELD_GET64(SSKPD_OLD_WM0_MASK_HSW, sskpd);
- wm[1] = REG_FIELD_GET64(SSKPD_WM1_MASK_HSW, sskpd);
- wm[2] = REG_FIELD_GET64(SSKPD_WM2_MASK_HSW, sskpd);
- wm[3] = REG_FIELD_GET64(SSKPD_WM3_MASK_HSW, sskpd);
- wm[4] = REG_FIELD_GET64(SSKPD_WM4_MASK_HSW, sskpd);
- } else if (DISPLAY_VER(dev_priv) >= 6) {
- u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
-
- wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd);
- wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd);
- wm[2] = REG_FIELD_GET(SSKPD_WM2_MASK_SNB, sskpd);
- wm[3] = REG_FIELD_GET(SSKPD_WM3_MASK_SNB, sskpd);
- } else if (DISPLAY_VER(dev_priv) >= 5) {
- u32 mltr =
[Intel-gfx] [PATCH 0/3] drm/i915: Move skl+ wm code into its own file
From: Ville Syrjälä Hoist all the skl+ wm related stuff from intel_pm.c into its own file. Ville Syrjälä (3): drm/i915: Split intel_read_wm_latency() into per-platform versions drm/i915: Extract skl_watermark.c drm/i915: Use REG_FIELD_GET() to extract skl+ wm latencies drivers/gpu/drm/i915/Makefile |3 +- .../gpu/drm/i915/display/intel_atomic_plane.c |2 +- drivers/gpu/drm/i915/display/intel_bw.c |4 +- drivers/gpu/drm/i915/display/intel_cursor.c |2 +- drivers/gpu/drm/i915/display/intel_display.c |1 + .../drm/i915/display/intel_display_debugfs.c |1 + .../drm/i915/display/intel_display_power.c|2 +- .../i915/display/intel_display_power_well.c |2 +- .../drm/i915/display/intel_modeset_setup.c|1 + .../drm/i915/display/intel_modeset_verify.c |2 +- .../drm/i915/display/skl_universal_plane.c|2 +- drivers/gpu/drm/i915/display/skl_watermark.c | 3464 drivers/gpu/drm/i915/display/skl_watermark.h | 78 + drivers/gpu/drm/i915/i915_driver.c|1 + drivers/gpu/drm/i915/i915_reg.h |8 +- drivers/gpu/drm/i915/intel_pm.c | 3528 + drivers/gpu/drm/i915/intel_pm.h | 65 +- 17 files changed, 3609 insertions(+), 3557 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/skl_watermark.c create mode 100644 drivers/gpu/drm/i915/display/skl_watermark.h -- 2.35.1
Re: [Intel-gfx] [PATCH 04/19] drm/i915/perf: Determine gen12 oa ctx offset at runtime
On 06/09/2022 23:35, Umesh Nerlige Ramappa wrote:
On Tue, Sep 06, 2022 at 10:48:50PM +0300, Lionel Landwerlin wrote:
On 23/08/2022 23:41, Umesh Nerlige Ramappa wrote:
Some SKUs of same gen12 platform may have different oactxctrl
offsets. For gen12, determine oactxctrl offsets at runtime.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 149 ++-
drivers/gpu/drm/i915/i915_perf_oa_regs.h | 2 +-
2 files changed, 120 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c
b/drivers/gpu/drm/i915/i915_perf.c
index 3526693d64fa..efa7eda83edd 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1363,6 +1363,67 @@ static int gen12_get_render_context_id(struct
i915_perf_stream *stream)
return 0;
}
+#define MI_OPCODE(x) (((x) >> 23) & 0x3f)
+#define IS_MI_LRI_CMD(x) (MI_OPCODE(x) == MI_OPCODE(MI_INSTR(0x22,
0)))
+#define MI_LRI_LEN(x) (((x) & 0xff) + 1)
Maybe you want to put this in intel_gpu_commands.h
+#define __valid_oactxctrl_offset(x) ((x) && (x) != U32_MAX)
+static bool __find_reg_in_lri(u32 *state, u32 reg, u32 *offset)
+{
+ u32 idx = *offset;
+ u32 len = MI_LRI_LEN(state[idx]) + idx;
+
+ idx++;
+ for (; idx < len; idx += 2)
+ if (state[idx] == reg)
+ break;
+
+ *offset = idx;
+ return state[idx] == reg;
+}
+
+static u32 __context_image_offset(struct intel_context *ce, u32 reg)
+{
+ u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
+ u32 *state = ce->lrc_reg_state;
+
+ for (offset = 0; offset < len; ) {
+ if (IS_MI_LRI_CMD(state[offset])) {
I'm a bit concerned you might find other matches with this.
Because let's say you run into a 3DSTATE_SUBSLICE_HASH_TABLE
instruction, you'll iterate the instruction dword by dword because
you don't know how to read its length and skip to the next one.
Now some of the fields can be programmed from userspace to look like
an MI_LRI header, so you start to read data in the wrong way.
Unfortunately I don't have a better solution. My only ask is that you
make __find_reg_in_lri() take the context image size in parameter so
it NEVER goes over the the context image.
To limit the risk you should run this function only one at driver
initialization and store the found offset.
Hmm, didn't know that there may be non-LRI commands in the context
image or user could add to the context image somehow. Does using the
context image size alone address these issues?
Even after including the size in the logic, any reason you think we
would be much more safer to do this from init? Is it because context
image is not touched by user yet?
The format of the image (commands in there and their offset) is fixed
per HW generation.
Only the date in each of the commands will vary per context.
In the case of MI_LRI, the register offsets are the same for all
context, but the value programmed will vary per context.
So executing once should be enough to find the right offset, rather
than every time we open the i915-perf stream.
I think once you have the logic to make sure you never read outside the
image it should be alright.
-Lionel
Thanks,
Umesh
Thanks,
-Lionel
+ if (__find_reg_in_lri(state, reg, ))
+ break;
+ } else {
+ offset++;
+ }
+ }
+
+ return offset < len ? offset : U32_MAX;
+}
+
+static int __set_oa_ctx_ctrl_offset(struct intel_context *ce)
+{
+ i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);
+ struct i915_perf *perf = >engine->i915->perf;
+ u32 saved_offset = perf->ctx_oactxctrl_offset;
+ u32 offset;
+
+ /* Do this only once. Failure is stored as offset of U32_MAX */
+ if (saved_offset)
+ return 0;
+
+ offset = __context_image_offset(ce, i915_mmio_reg_offset(reg));
+ perf->ctx_oactxctrl_offset = offset;
+
+ drm_dbg(>engine->i915->drm,
+ "%s oa ctx control at 0x%08x dword offset\n",
+ ce->engine->name, offset);
+
+ return __valid_oactxctrl_offset(offset) ? 0 : -ENODEV;
+}
+
+static bool engine_supports_mi_query(struct intel_engine_cs *engine)
+{
+ return engine->class == RENDER_CLASS;
+}
+
/**
* oa_get_render_ctx_id - determine and hold ctx hw id
* @stream: An i915-perf stream opened for OA metrics
@@ -1382,6 +1443,17 @@ static int oa_get_render_ctx_id(struct
i915_perf_stream *stream)
if (IS_ERR(ce))
return PTR_ERR(ce);
+ if (engine_supports_mi_query(stream->engine)) {
+ ret = __set_oa_ctx_ctrl_offset(ce);
+ if (ret && !(stream->sample_flags & SAMPLE_OA_REPORT)) {
+ intel_context_unpin(ce);
+ drm_err(>perf->i915->drm,
+ "Enabling perf query failed for %s\n",
+ stream->engine->name);
+ return ret;
+ }
+ }
+
switch (GRAPHICS_VER(ce->engine->i915)) {
case 7: {
/*
@@ -2412,10 +2484,11 @@ static int
Re: [Intel-gfx] [PATCH] drm/i915/dsb: hide struct intel_dsb better
On Thu, 08 Sep 2022, Ville Syrjälä wrote:
> On Thu, Sep 08, 2022 at 07:57:02PM +0300, Jani Nikula wrote:
>> struct intel_dsb can be an opaque type, hidden in intel_dsb.c. Make it
>> so. Reduce related includes while at it.
>>
>> Signed-off-by: Jani Nikula
>
> One thing I was mildly worried about with dsb is the cost
> of creating the batch (updating LUTs involves writing some
> thousands of dwords). So I was pondering whether that should
> be inlined as opposed to being a function call per dword.
> But as it stands it's already a function call, and
> I've not actually measured how fast/slow it really is.
> So can't really argue against this sort of stuff, for the
> moment at least :)
I'm also on a mission to kill useless static inlines. ;)
Anything that requires pulling in additional headers or exposing the
guts of the implementation are suspect and need proper justification.
> Reviewed-by: Ville Syrjälä
Thanks,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/display/intel_color.c | 1 +
>> drivers/gpu/drm/i915/display/intel_display.c | 1 +
>> drivers/gpu/drm/i915/display/intel_dsb.c | 30
>> drivers/gpu/drm/i915/display/intel_dsb.h | 28 --
>> drivers/gpu/drm/i915/i915_drv.h | 1 -
>> 5 files changed, 32 insertions(+), 29 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
>> b/drivers/gpu/drm/i915/display/intel_color.c
>> index ed98c732b24e..6bda4274eae9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_color.c
>> +++ b/drivers/gpu/drm/i915/display/intel_color.c
>> @@ -26,6 +26,7 @@
>> #include "intel_de.h"
>> #include "intel_display_types.h"
>> #include "intel_dpll.h"
>> +#include "intel_dsb.h"
>> #include "vlv_dsi_pll.h"
>>
>> struct intel_color_funcs {
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index 2b6bb5ee7698..296cbcd1352c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -91,6 +91,7 @@
>> #include "intel_dmc.h"
>> #include "intel_dp_link_training.h"
>> #include "intel_dpt.h"
>> +#include "intel_dsb.h"
>> #include "intel_fbc.h"
>> #include "intel_fbdev.h"
>> #include "intel_fdi.h"
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
>> b/drivers/gpu/drm/i915/display/intel_dsb.c
>> index c4affcb216fd..fc9c3e41c333 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>> @@ -9,6 +9,36 @@
>> #include "i915_drv.h"
>> #include "intel_de.h"
>> #include "intel_display_types.h"
>> +#include "intel_dsb.h"
>> +
>> +struct i915_vma;
>> +
>> +enum dsb_id {
>> +INVALID_DSB = -1,
>> +DSB1,
>> +DSB2,
>> +DSB3,
>> +MAX_DSB_PER_PIPE
>> +};
>> +
>> +struct intel_dsb {
>> +enum dsb_id id;
>> +u32 *cmd_buf;
>> +struct i915_vma *vma;
>> +
>> +/*
>> + * free_pos will point the first free entry position
>> + * and help in calculating tail of command buffer.
>> + */
>> +int free_pos;
>> +
>> +/*
>> + * ins_start_offset will help to store start address of the dsb
>> + * instuction and help in identifying the batch of auto-increment
>> + * register.
>> + */
>> +u32 ins_start_offset;
>> +};
>>
>> #define DSB_BUF_SIZE(2 * PAGE_SIZE)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
>> b/drivers/gpu/drm/i915/display/intel_dsb.h
>> index 6cb9c580cdca..74dd2b3343bb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
>> @@ -11,34 +11,6 @@
>> #include "i915_reg_defs.h"
>>
>> struct intel_crtc_state;
>> -struct i915_vma;
>> -
>> -enum dsb_id {
>> -INVALID_DSB = -1,
>> -DSB1,
>> -DSB2,
>> -DSB3,
>> -MAX_DSB_PER_PIPE
>> -};
>> -
>> -struct intel_dsb {
>> -enum dsb_id id;
>> -u32 *cmd_buf;
>> -struct i915_vma *vma;
>> -
>> -/*
>> - * free_pos will point the first free entry position
>> - * and help in calculating tail of command buffer.
>> - */
>> -int free_pos;
>> -
>> -/*
>> - * ins_start_offset will help to store start address of the dsb
>> - * instuction and help in identifying the batch of auto-increment
>> - * register.
>> - */
>> -u32 ins_start_offset;
>> -};
>>
>> void intel_dsb_prepare(struct intel_crtc_state *crtc_state);
>> void intel_dsb_cleanup(struct intel_crtc_state *crtc_state);
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 76aad81c014b..be201ba5e9ab 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -38,7 +38,6 @@
>>
>> #include "display/intel_display.h"
>> #include "display/intel_display_core.h"
>> -#include "display/intel_dsb.h"
>>
>> #include "gem/i915_gem_context_types.h"
>> #include "gem/i915_gem_lmem.h"
>> --
>> 2.34.1
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v4 07/11] drm/i915/mtl: Add DP AUX support on TypeC ports
On Thu, Sep 01, 2022 at 11:03:38PM -0700, Radhakrishna Sripada wrote:
> From: Imre Deak
>
> On MTL TypeC ports the AUX_CH_CTL and AUX_CH_DATA addresses have
> changed wrt. previous platforms, adjust the code accordingly.
>
> Signed-off-by: Imre Deak
> Signed-off-by: Radhakrishna Sripada
As noted on the previous patch, the _XELPDP_USBC1_AUX_CH_DATA*
definitions aren't used until this patch so they should probably move
into this one. Aside from that,
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 45 -
> drivers/gpu/drm/i915/i915_reg.h | 9 +
> 2 files changed, 53 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index 98bd33645b43..48c375c65a41 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -637,6 +637,46 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp
> *intel_dp, int index)
> }
> }
>
> +static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + switch (aux_ch) {
> + case AUX_CH_A:
> + case AUX_CH_B:
> + case AUX_CH_USBC1:
> + case AUX_CH_USBC2:
> + case AUX_CH_USBC3:
> + case AUX_CH_USBC4:
> + return XELPDP_DP_AUX_CH_CTL(aux_ch);
> + default:
> + MISSING_CASE(aux_ch);
> + return XELPDP_DP_AUX_CH_CTL(AUX_CH_A);
> + }
> +}
> +
> +static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + switch (aux_ch) {
> + case AUX_CH_A:
> + case AUX_CH_B:
> + case AUX_CH_USBC1:
> + case AUX_CH_USBC2:
> + case AUX_CH_USBC3:
> + case AUX_CH_USBC4:
> + return XELPDP_DP_AUX_CH_DATA(aux_ch, index);
> + default:
> + MISSING_CASE(aux_ch);
> + return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index);
> + }
> +}
> +
> void intel_dp_aux_fini(struct intel_dp *intel_dp)
> {
> if (cpu_latency_qos_request_active(_dp->pm_qos))
> @@ -652,7 +692,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
> struct intel_encoder *encoder = _port->base;
> enum aux_ch aux_ch = dig_port->aux_ch;
>
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
> + intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
> + } else if (DISPLAY_VER(dev_priv) >= 12) {
> intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
> intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
> } else if (DISPLAY_VER(dev_priv) >= 9) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 99b2cd2abca4..4ec6a3dd1f2b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3470,6 +3470,15 @@
>
> _XELPDP_USBC3_AUX_CH_CTL, \
>
> _XELPDP_USBC4_AUX_CH_CTL))
>
> +#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
> +_DPA_AUX_CH_DATA1, \
> +_DPB_AUX_CH_DATA1, \
> +0, /* port/aux_ch C is
> non-existent */ \
> +
> _XELPDP_USBC1_AUX_CH_DATA1, \
> +
> _XELPDP_USBC2_AUX_CH_DATA1, \
> +
> _XELPDP_USBC3_AUX_CH_DATA1, \
> +
> _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
> +
> #define DP_AUX_CH_CTL_SEND_BUSY(1 << 31)
> #define DP_AUX_CH_CTL_DONE (1 << 30)
> #define DP_AUX_CH_CTL_INTERRUPT(1 << 29)
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v4 06/11] drm/i915/mtl: Add display power wells
On Thu, Sep 08, 2022 at 11:07:16AM -0700, Matt Roper wrote:
> On Thu, Sep 01, 2022 at 11:03:37PM -0700, Radhakrishna Sripada wrote:
> > From: Imre Deak
> >
> > Add support for display power wells on MTL. The differences from XE_LPD:
> > - The AUX HW block is moved to the PICA block, where the registers are on
> > an always-on power well and the functionality needs to be powered on/off
> > via the AUX_CH_CTL register: [1], [2]
> > - The DDI IO power on/off programming sequence is moved to the PHY PLL
> > enable/disable sequence. [3], [4], [5]
> >
> > Bspec: [1] 49233, [2] 65247, [3] 64568, [4] 65451, [5] 65450
> >
> > v2:
> > - Update the comment in aux power well enable
> > - Reuse the noop sync fn for aux sync.
> > - Use REG_BIT for new register bit definitions
> >
> > Signed-off-by: Imre Deak
> > Signed-off-by: Radhakrishna Sripada
>
> Reviewed-by: Matt Roper
Oops, one very minor comment down at the bottom.
>
> > ---
> > .../i915/display/intel_display_power_map.c| 115 +-
> > .../i915/display/intel_display_power_well.c | 44 +++
> > .../i915/display/intel_display_power_well.h | 4 +
> > drivers/gpu/drm/i915/display/intel_dp_aux.c | 8 ++
> > drivers/gpu/drm/i915/i915_reg.h | 21
> > 5 files changed, 191 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > index 5ddd1b93751c..dc04afc6cc8f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > @@ -1350,6 +1350,117 @@ static const struct i915_power_well_desc_list
> > xelpd_power_wells[] = {
> > I915_PW_DESCRIPTORS(xelpd_power_wells_main),
> > };
> >
> > +/*
> > + * MTL is based on XELPD power domains with the exception of power gating
> > for:
> > + * - DDI_IO (moved to PLL logic)
> > + * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA
> > always-on)
> > + */
> > +#define XELPDP_PW_2_POWER_DOMAINS \
> > + XELPD_PW_B_POWER_DOMAINS, \
> > + XELPD_PW_C_POWER_DOMAINS, \
> > + XELPD_PW_D_POWER_DOMAINS, \
> > + POWER_DOMAIN_AUDIO_PLAYBACK, \
> > + POWER_DOMAIN_VGA, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC1, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC2, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC3, \
> > + POWER_DOMAIN_PORT_DDI_LANES_TC4
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2,
> > + XELPDP_PW_2_POWER_DOMAINS,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
> > + XELPDP_PW_2_POWER_DOMAINS,
> > + POWER_DOMAIN_AUDIO_MMIO,
> > + POWER_DOMAIN_MODESET,
> > + POWER_DOMAIN_AUX_A,
> > + POWER_DOMAIN_AUX_B,
> > + POWER_DOMAIN_INIT);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1,
> > + POWER_DOMAIN_AUX_USBC1,
> > + POWER_DOMAIN_AUX_TBT1);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2,
> > + POWER_DOMAIN_AUX_USBC2,
> > + POWER_DOMAIN_AUX_TBT2);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3,
> > + POWER_DOMAIN_AUX_USBC3,
> > + POWER_DOMAIN_AUX_TBT3);
> > +
> > +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4,
> > + POWER_DOMAIN_AUX_USBC4,
> > + POWER_DOMAIN_AUX_TBT4);
> > +
> > +static const struct i915_power_well_desc xelpdp_power_wells_main[] = {
> > + {
> > + .instances = _PW_INSTANCES(
> > + I915_PW("DC_off", _pwdoms_dc_off,
> > + .id = SKL_DISP_DC_OFF),
> > + ),
> > + .ops = _dc_off_power_well_ops,
> > + }, {
> > + .instances = _PW_INSTANCES(
> > + I915_PW("PW_2", _pwdoms_pw_2,
> > + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> > + .id = SKL_DISP_PW_2),
> > + ),
> > + .ops = _power_well_ops,
> > + .has_vga = true,
> > + .has_fuses = true,
> > + }, {
> > + .instances = _PW_INSTANCES(
> > + I915_PW("PW_A", _pwdoms_pw_a,
> > + .hsw.idx = XELPD_PW_CTL_IDX_PW_A),
> > + ),
> > + .ops = _power_well_ops,
> > + .irq_pipe_mask = BIT(PIPE_A),
> > + .has_fuses = true,
> > + }, {
> > + .instances = _PW_INSTANCES(
> > + I915_PW("PW_B", _pwdoms_pw_b,
> > + .hsw.idx = XELPD_PW_CTL_IDX_PW_B),
> > + ),
> > + .ops = _power_well_ops,
> > + .irq_pipe_mask = BIT(PIPE_B),
> > + .has_fuses = true,
> > + }, {
> > + .instances = _PW_INSTANCES(
> > + I915_PW("PW_C", _pwdoms_pw_c,
> > + .hsw.idx = XELPD_PW_CTL_IDX_PW_C),
> > + ),
> > + .ops = _power_well_ops,
> > + .irq_pipe_mask = BIT(PIPE_C),
> > + .has_fuses = true,
> > + }, {
> > + .instances = _PW_INSTANCES(
> > + I915_PW("PW_D",
Re: [Intel-gfx] [PATCH v4 06/11] drm/i915/mtl: Add display power wells
On Thu, Sep 01, 2022 at 11:03:37PM -0700, Radhakrishna Sripada wrote:
> From: Imre Deak
>
> Add support for display power wells on MTL. The differences from XE_LPD:
> - The AUX HW block is moved to the PICA block, where the registers are on
> an always-on power well and the functionality needs to be powered on/off
> via the AUX_CH_CTL register: [1], [2]
> - The DDI IO power on/off programming sequence is moved to the PHY PLL
> enable/disable sequence. [3], [4], [5]
>
> Bspec: [1] 49233, [2] 65247, [3] 64568, [4] 65451, [5] 65450
>
> v2:
> - Update the comment in aux power well enable
> - Reuse the noop sync fn for aux sync.
> - Use REG_BIT for new register bit definitions
>
> Signed-off-by: Imre Deak
> Signed-off-by: Radhakrishna Sripada
Reviewed-by: Matt Roper
> ---
> .../i915/display/intel_display_power_map.c| 115 +-
> .../i915/display/intel_display_power_well.c | 44 +++
> .../i915/display/intel_display_power_well.h | 4 +
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 8 ++
> drivers/gpu/drm/i915/i915_reg.h | 21
> 5 files changed, 191 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index 5ddd1b93751c..dc04afc6cc8f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -1350,6 +1350,117 @@ static const struct i915_power_well_desc_list
> xelpd_power_wells[] = {
> I915_PW_DESCRIPTORS(xelpd_power_wells_main),
> };
>
> +/*
> + * MTL is based on XELPD power domains with the exception of power gating
> for:
> + * - DDI_IO (moved to PLL logic)
> + * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA
> always-on)
> + */
> +#define XELPDP_PW_2_POWER_DOMAINS \
> + XELPD_PW_B_POWER_DOMAINS, \
> + XELPD_PW_C_POWER_DOMAINS, \
> + XELPD_PW_D_POWER_DOMAINS, \
> + POWER_DOMAIN_AUDIO_PLAYBACK, \
> + POWER_DOMAIN_VGA, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC1, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC2, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC3, \
> + POWER_DOMAIN_PORT_DDI_LANES_TC4
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2,
> + XELPDP_PW_2_POWER_DOMAINS,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
> + XELPDP_PW_2_POWER_DOMAINS,
> + POWER_DOMAIN_AUDIO_MMIO,
> + POWER_DOMAIN_MODESET,
> + POWER_DOMAIN_AUX_A,
> + POWER_DOMAIN_AUX_B,
> + POWER_DOMAIN_INIT);
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1,
> + POWER_DOMAIN_AUX_USBC1,
> + POWER_DOMAIN_AUX_TBT1);
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2,
> + POWER_DOMAIN_AUX_USBC2,
> + POWER_DOMAIN_AUX_TBT2);
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3,
> + POWER_DOMAIN_AUX_USBC3,
> + POWER_DOMAIN_AUX_TBT3);
> +
> +I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4,
> + POWER_DOMAIN_AUX_USBC4,
> + POWER_DOMAIN_AUX_TBT4);
> +
> +static const struct i915_power_well_desc xelpdp_power_wells_main[] = {
> + {
> + .instances = _PW_INSTANCES(
> + I915_PW("DC_off", _pwdoms_dc_off,
> + .id = SKL_DISP_DC_OFF),
> + ),
> + .ops = _dc_off_power_well_ops,
> + }, {
> + .instances = _PW_INSTANCES(
> + I915_PW("PW_2", _pwdoms_pw_2,
> + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> + .id = SKL_DISP_PW_2),
> + ),
> + .ops = _power_well_ops,
> + .has_vga = true,
> + .has_fuses = true,
> + }, {
> + .instances = _PW_INSTANCES(
> + I915_PW("PW_A", _pwdoms_pw_a,
> + .hsw.idx = XELPD_PW_CTL_IDX_PW_A),
> + ),
> + .ops = _power_well_ops,
> + .irq_pipe_mask = BIT(PIPE_A),
> + .has_fuses = true,
> + }, {
> + .instances = _PW_INSTANCES(
> + I915_PW("PW_B", _pwdoms_pw_b,
> + .hsw.idx = XELPD_PW_CTL_IDX_PW_B),
> + ),
> + .ops = _power_well_ops,
> + .irq_pipe_mask = BIT(PIPE_B),
> + .has_fuses = true,
> + }, {
> + .instances = _PW_INSTANCES(
> + I915_PW("PW_C", _pwdoms_pw_c,
> + .hsw.idx = XELPD_PW_CTL_IDX_PW_C),
> + ),
> + .ops = _power_well_ops,
> + .irq_pipe_mask = BIT(PIPE_C),
> + .has_fuses = true,
> + }, {
> + .instances = _PW_INSTANCES(
> + I915_PW("PW_D", _pwdoms_pw_d,
> + .hsw.idx = XELPD_PW_CTL_IDX_PW_D),
> + ),
> + .ops = _power_well_ops,
> + .irq_pipe_mask = BIT(PIPE_D),
> + .has_fuses = true,
> + }, {
> +
Re: [Intel-gfx] [PATCH v4 05/11] drm/i915/mtl: Add gmbus and gpio support
On Thu, Sep 01, 2022 at 11:03:36PM -0700, Radhakrishna Sripada wrote:
> Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
> From spec we have registers GPIO_CTL[1-5] mapped to native display phys and
> GPIO_CTL[9-12] are mapped to TC ports.
>
> v2:
> - Drop unused GPIO pins(MattR)
>
> BSpec: 49306
>
> Cc: Matt Roper
> Original Author: Brian J Lovin
> Signed-off-by: Radhakrishna Sripada
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +++
> drivers/gpu/drm/i915/display/intel_gmbus.h | 1 +
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
> b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 6f6cfccad477..74443f57f62d 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -117,6 +117,18 @@ static const struct gmbus_pin gmbus_pins_dg2[] = {
> [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> };
>
> +static const struct gmbus_pin gmbus_pins_mtp[] = {
> + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> + [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> + [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> + [GMBUS_PIN_5_MTP] = { "dpe", GPIOF },
> + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> +};
> +
> static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
>unsigned int pin)
> {
> @@ -129,6 +141,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct
> drm_i915_private *i915,
> } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
> pins = gmbus_pins_dg1;
> size = ARRAY_SIZE(gmbus_pins_dg1);
> + } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) {
> + pins = gmbus_pins_mtp;
> + size = ARRAY_SIZE(gmbus_pins_mtp);
> } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
> pins = gmbus_pins_icp;
> size = ARRAY_SIZE(gmbus_pins_icp);
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h
> b/drivers/gpu/drm/i915/display/intel_gmbus.h
> index 8edc2e99cf53..20f704bd4e70 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.h
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
> @@ -24,6 +24,7 @@ struct i2c_adapter;
> #define GMBUS_PIN_2_BXT 2
> #define GMBUS_PIN_3_BXT 3
> #define GMBUS_PIN_4_CNP 4
> +#define GMBUS_PIN_5_MTP 5
> #define GMBUS_PIN_9_TC1_ICP 9
> #define GMBUS_PIN_10_TC2_ICP 10
> #define GMBUS_PIN_11_TC3_ICP 11
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v4.1] drm/i915/mtl: Define engine context layouts
On Wed, Sep 07, 2022 at 04:33:17PM -0700, Radhakrishna Sripada wrote:
> From: Matt Roper
>
> The part of the media and blitter engine contexts that we care about for
> setting up an initial state are the same on MTL as they were on DG2
> (and PVC), so we need to update the driver conditions to re-use the DG2
> context table.
>
> For render/compute engines, the part of the context images are nearly
> the same, although the layout had a very slight change --- one POSH
> register was removed and the placement of some LRI/noops adjusted
> slightly to compensate.
>
> v2:
> - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala)
> - Drop unused registers in mtl rcs offsets.(Bala)
> - Add missing nop in xcs offsets(Bala)
>
> Bspec: 46261, 46260, 45585
> Cc: Balasubramani Vivekanandan
> Signed-off-by: Matt Roper
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 82 -
> 1 file changed, 80 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 070cec4ff8a4..a2247d39bdb7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = {
> END
> };
>
> +static const u8 mtl_xcs_offsets[] = {
> + NOP(1),
> + LRI(13, POSTED),
> + REG16(0x244),
> + REG(0x034),
> + REG(0x030),
> + REG(0x038),
> + REG(0x03c),
> + REG(0x168),
> + REG(0x140),
> + REG(0x110),
> + REG(0x1c0),
> + REG(0x1c4),
> + REG(0x1c8),
> + REG(0x180),
> + REG16(0x2b4),
> + NOP(1),
Shouldn't this be NOP(4)?
Matt
> +
> + NOP(1),
> + LRI(9, POSTED),
> + REG16(0x3a8),
> + REG16(0x28c),
> + REG16(0x288),
> + REG16(0x284),
> + REG16(0x280),
> + REG16(0x27c),
> + REG16(0x278),
> + REG16(0x274),
> + REG16(0x270),
> +
> + END
> +};
> +
> static const u8 gen8_rcs_offsets[] = {
> NOP(1),
> LRI(14, POSTED),
> @@ -606,6 +639,47 @@ static const u8 dg2_rcs_offsets[] = {
> END
> };
>
> +static const u8 mtl_rcs_offsets[] = {
> + NOP(1),
> + LRI(13, POSTED),
> + REG16(0x244),
> + REG(0x034),
> + REG(0x030),
> + REG(0x038),
> + REG(0x03c),
> + REG(0x168),
> + REG(0x140),
> + REG(0x110),
> + REG(0x1c0),
> + REG(0x1c4),
> + REG(0x1c8),
> + REG(0x180),
> + REG16(0x2b4),
> +
> + NOP(1),
> + LRI(9, POSTED),
> + REG16(0x3a8),
> + REG16(0x28c),
> + REG16(0x288),
> + REG16(0x284),
> + REG16(0x280),
> + REG16(0x27c),
> + REG16(0x278),
> + REG16(0x274),
> + REG16(0x270),
> +
> + NOP(2),
> + LRI(2, POSTED),
> + REG16(0x5a8),
> + REG16(0x5ac),
> +
> + NOP(6),
> + LRI(1, 0),
> + REG(0x0c8),
> +
> + END
> +};
> +
> #undef END
> #undef REG16
> #undef REG
> @@ -624,7 +698,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs
> *engine)
> !intel_engine_has_relative_mmio(engine));
>
> if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
> + return mtl_rcs_offsets;
> + else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> return dg2_rcs_offsets;
> else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> return xehp_rcs_offsets;
> @@ -637,7 +713,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs
> *engine)
> else
> return gen8_rcs_offsets;
> } else {
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
> + return mtl_xcs_offsets;
> + else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> return dg2_xcs_offsets;
> else if (GRAPHICS_VER(engine->i915) >= 12)
> return gen12_xcs_offsets;
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH] drm/i915/dsb: hide struct intel_dsb better
On Thu, Sep 08, 2022 at 07:57:02PM +0300, Jani Nikula wrote:
> struct intel_dsb can be an opaque type, hidden in intel_dsb.c. Make it
> so. Reduce related includes while at it.
>
> Signed-off-by: Jani Nikula
One thing I was mildly worried about with dsb is the cost
of creating the batch (updating LUTs involves writing some
thousands of dwords). So I was pondering whether that should
be inlined as opposed to being a function call per dword.
But as it stands it's already a function call, and
I've not actually measured how fast/slow it really is.
So can't really argue against this sort of stuff, for the
moment at least :)
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_dsb.c | 30
> drivers/gpu/drm/i915/display/intel_dsb.h | 28 --
> drivers/gpu/drm/i915/i915_drv.h | 1 -
> 5 files changed, 32 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index ed98c732b24e..6bda4274eae9 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -26,6 +26,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_dpll.h"
> +#include "intel_dsb.h"
> #include "vlv_dsi_pll.h"
>
> struct intel_color_funcs {
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 2b6bb5ee7698..296cbcd1352c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -91,6 +91,7 @@
> #include "intel_dmc.h"
> #include "intel_dp_link_training.h"
> #include "intel_dpt.h"
> +#include "intel_dsb.h"
> #include "intel_fbc.h"
> #include "intel_fbdev.h"
> #include "intel_fdi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index c4affcb216fd..fc9c3e41c333 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -9,6 +9,36 @@
> #include "i915_drv.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
> +#include "intel_dsb.h"
> +
> +struct i915_vma;
> +
> +enum dsb_id {
> + INVALID_DSB = -1,
> + DSB1,
> + DSB2,
> + DSB3,
> + MAX_DSB_PER_PIPE
> +};
> +
> +struct intel_dsb {
> + enum dsb_id id;
> + u32 *cmd_buf;
> + struct i915_vma *vma;
> +
> + /*
> + * free_pos will point the first free entry position
> + * and help in calculating tail of command buffer.
> + */
> + int free_pos;
> +
> + /*
> + * ins_start_offset will help to store start address of the dsb
> + * instuction and help in identifying the batch of auto-increment
> + * register.
> + */
> + u32 ins_start_offset;
> +};
>
> #define DSB_BUF_SIZE(2 * PAGE_SIZE)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
> b/drivers/gpu/drm/i915/display/intel_dsb.h
> index 6cb9c580cdca..74dd2b3343bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -11,34 +11,6 @@
> #include "i915_reg_defs.h"
>
> struct intel_crtc_state;
> -struct i915_vma;
> -
> -enum dsb_id {
> - INVALID_DSB = -1,
> - DSB1,
> - DSB2,
> - DSB3,
> - MAX_DSB_PER_PIPE
> -};
> -
> -struct intel_dsb {
> - enum dsb_id id;
> - u32 *cmd_buf;
> - struct i915_vma *vma;
> -
> - /*
> - * free_pos will point the first free entry position
> - * and help in calculating tail of command buffer.
> - */
> - int free_pos;
> -
> - /*
> - * ins_start_offset will help to store start address of the dsb
> - * instuction and help in identifying the batch of auto-increment
> - * register.
> - */
> - u32 ins_start_offset;
> -};
>
> void intel_dsb_prepare(struct intel_crtc_state *crtc_state);
> void intel_dsb_cleanup(struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 76aad81c014b..be201ba5e9ab 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -38,7 +38,6 @@
>
> #include "display/intel_display.h"
> #include "display/intel_display_core.h"
> -#include "display/intel_dsb.h"
>
> #include "gem/i915_gem_context_types.h"
> #include "gem/i915_gem_lmem.h"
> --
> 2.34.1
--
Ville Syrjälä
Intel
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsb: hide struct intel_dsb better
== Series Details ==
Series: drm/i915/dsb: hide struct intel_dsb better
URL : https://patchwork.freedesktop.org/series/108310/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12099 -> Patchwork_108310v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/index.html
Participating hosts (39 -> 40)
--
Additional (2): bat-dg2-8 fi-kbl-guc
Missing(1): fi-bdw-samus
Known issues
Here are the changes found in Patchwork_108310v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: NOTRUN -> [DMESG-FAIL][1] ([i915#4957])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-dg1-5: NOTRUN -> [INCOMPLETE][2] ([i915#6011])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/bat-dg1-5/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bdw-5557u: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/fi-bdw-5557u/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@runner@aborted:
- fi-kbl-guc: NOTRUN -> [FAIL][4] ([i915#6219])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/fi-kbl-guc/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_engines:
- bat-dg1-5: [INCOMPLETE][5] ([i915#4418]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12099/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][7] ([i915#4983]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12099/bat-rpls-1/igt@i915_selftest@l...@reset.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/bat-rpls-1/igt@i915_selftest@l...@reset.html
Warnings
* igt@runner@aborted:
- fi-pnv-d510:[FAIL][9] ([fdo#109271] / [i915#2403] / [i915#4312])
-> [FAIL][10] ([i915#2403] / [i915#4312])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12099/fi-pnv-d510/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108310v1/fi-pnv-d510/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
[i915#6219]: https://gitlab.freedesktop.org/drm/intel/issues/6219
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
Build changes
-
* Linux:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dsb: hide struct intel_dsb better
== Series Details == Series: drm/i915/dsb: hide struct intel_dsb better URL : https://patchwork.freedesktop.org/series/108310/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
