[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: A couple of if/else ladder refactors (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: A couple of if/else ladder refactors (rev2)
URL   : https://patchwork.freedesktop.org/series/108315/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12132_full -> Patchwork_108315v2_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 12)
--

  Additional (1): shard-dg1 

New tests
-

  New tests have been introduced between CI_DRM_12132_full and 
Patchwork_108315v2_full:

### New IGT tests (12) ###

  * igt@kms_cursor_crc@cursor-offscreen-128x128@pipe-a-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [2.50] s

  * igt@kms_cursor_crc@cursor-offscreen-128x128@pipe-b-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [2.40] s

  * igt@kms_cursor_crc@cursor-offscreen-128x128@pipe-c-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [2.40] s

  * igt@kms_cursor_crc@cursor-offscreen-128x128@pipe-d-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [2.43] s

  * igt@kms_cursor_crc@cursor-sliding-128x128@pipe-a-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [5.59] s

  * igt@kms_cursor_crc@cursor-sliding-128x128@pipe-b-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [5.61] s

  * igt@kms_cursor_crc@cursor-sliding-128x128@pipe-c-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [5.71] s

  * igt@kms_cursor_crc@cursor-sliding-128x128@pipe-d-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [5.50] s

  * igt@kms_flip@basic-flip-vs-modeset@a-hdmi-a4:
- Statuses : 1 pass(s)
- Exec time: [0.74] s

  * igt@kms_flip@basic-flip-vs-modeset@b-hdmi-a4:
- Statuses : 1 pass(s)
- Exec time: [0.65] s

  * igt@kms_flip@basic-flip-vs-modeset@c-hdmi-a4:
- Statuses : 1 pass(s)
- Exec time: [0.63] s

  * igt@kms_flip@basic-flip-vs-modeset@d-hdmi-a4:
- Statuses : 1 pass(s)
- Exec time: [0.61] s

  

Known issues


  Here are the changes found in Patchwork_108315v2_full that come from known 
issues:

### CI changes ###

 Possible fixes 

  * boot:
- shard-apl:  ([FAIL][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24], [PASS][25]) ([i915#4386]) -> ([PASS][26], [PASS][27], [PASS][28], 
[PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], 
[PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], 
[PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], 
[PASS][47], [PASS][48], [PASS][49], [PASS][50])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl3/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl3/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl3/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl4/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl4/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl7/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl7/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl7/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl8/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl8/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl8/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v2/shard-apl2/boot.html
   [27]: 

Re: [Intel-gfx] [topic/core-for-CI] Revert "iommu/dma: Fix race condition during iova_domain initialization"

[Karolina Drobnik]

On 14.09.2022 17:01, Lucas De Marchi wrote:

On Wed, Sep 14, 2022 at 02:40:45PM +0200, Karolina Drobnik wrote:

This reverts commit ac9a5d522bb80be50ea84965699e1c8257d745ce.

This change introduces a regression on Alder Lake that completely
blocks testing. To enable CI and avoid possible circular locking
warning, revert the patch.


We are already on rc5. Are iommu authors involved aware of this issue?
We could do this in our "for CI only" branch, but it's equally important
that this is fixed for 6.0


I planned to reach out to them after merging this revert on "CI only" 
branch (hence the topic tag) with more justification. And yes, I'm fully 
aware we're quite late in the cycle, so that's also why I went with this 
patch first.


Many thanks,
Karolina


Cc'ing them.

thanks
Lucas De Marchi



kernel log:

==
WARNING: possible circular locking dependency detected
6.0.0-rc5-CI_DRM_12132-g6c93e979e542+ #1 Not tainted
--
cpuhp/0/15 is trying to acquire lock:
8881013df278 (&(>bus_notifier)->rwsem){}-{3:3}, at: 
blocking_notifier_call_chain+0x20/0x50

 but task is already holding lock:
826490c0 (cpuhp_state-up){+.+.}-{0:0}, at: 
cpuhp_thread_fun+0x48/0x1f0

 which lock already depends on the new loc
 the existing dependency chain (in reverse order) is:
 -> #3 (cpuhp_state-up){+.+.}-{0:0}:
  lock_acquire+0xd3/0x310
  cpuhp_thread_fun+0xa6/0x1f0
  smpboot_thread_fn+0x1b5/0x260
  kthread+0xed/0x120
  ret_from_fork+0x1f/0x30
 -> #2 (cpu_hotplug_lock){}-{0:0}:
  lock_acquire+0xd3/0x310
  __cpuhp_state_add_instance+0x43/0x1c0
  iova_domain_init_rcaches+0x199/0x1c0
  iommu_setup_dma_ops+0x130/0x440
  bus_iommu_probe+0x26a/0x2d0
  bus_set_iommu+0x82/0xd0
  intel_iommu_init+0xe33/0x1039
  pci_iommu_init+0x9/0x31
  do_one_initcall+0x53/0x2f0
  kernel_init_freeable+0x18f/0x1e1
  kernel_init+0x11/0x120
  ret_from_fork+0x1f/0x30
 -> #1 (>iova_cookie->mutex){+.+.}-{3:3}:
  lock_acquire+0xd3/0x310
  __mutex_lock+0x97/0xf10
  iommu_setup_dma_ops+0xd7/0x440
  iommu_probe_device+0xa4/0x180
  iommu_bus_notifier+0x2d/0x40
  notifier_call_chain+0x31/0x90
  blocking_notifier_call_chain+0x3a/0x50
  device_add+0x3c1/0x900
  pci_device_add+0x255/0x580
  pci_scan_single_device+0xa6/0xd0
  pci_scan_slot+0x7a/0x1b0
  pci_scan_child_bus_extend+0x35/0x2a0
  vmd_probe+0x5cd/0x970
  pci_device_probe+0x95/0x110
  really_probe+0xd6/0x350
  __driver_probe_device+0x73/0x170
  driver_probe_device+0x1a/0x90
  __driver_attach+0xbc/0x190
  bus_for_each_dev+0x72/0xc0
  bus_add_driver+0x1bb/0x210
  driver_register+0x66/0xc0
  do_one_initcall+0x53/0x2f0
  kernel_init_freeable+0x18f/0x1e1
  kernel_init+0x11/0x120
  ret_from_fork+0x1f/0x30
 -> #0 (&(>bus_notifier)->rwsem){}-{3:3}:
  validate_chain+0xb3f/0x2000
  __lock_acquire+0x5a4/0xb70
  lock_acquire+0xd3/0x310
  down_read+0x39/0x140
  blocking_notifier_call_chain+0x20/0x50
  device_add+0x3c1/0x900
  platform_device_add+0x108/0x240
  coretemp_cpu_online+0xe1/0x15e [coretemp]
  cpuhp_invoke_callback+0x181/0x8a0
  cpuhp_thread_fun+0x188/0x1f0
  smpboot_thread_fn+0x1b5/0x260
  kthread+0xed/0x120
  ret_from_fork+0x1f/0x30
 other info that might help us debug thi
Chain exists of &(>bus_notifier)->rwsem --> 
cpu_hotplug_lock --> cpuhp_state-

Possible unsafe locking scenari
  CPU0    CPU1
      
 lock(cpuhp_state-up);
  lock(cpu_hotplug_lock);
  lock(cpuhp_state-up);
 lock(&(>bus_notifier)->rwsem);
  *** DEADLOCK *
2 locks held by cpuhp/0/15:
#0: 82648f10 (cpu_hotplug_lock){}-{0:0}, at: 
cpuhp_thread_fun+0x48/0x1f0
#1: 826490c0 (cpuhp_state-up){+.+.}-{0:0}, at: 
cpuhp_thread_fun+0x48/0x1f0

 stack backtrace:
CPU: 0 PID: 15 Comm: cpuhp/0 Not tainted 
6.0.0-rc5-CI_DRM_12132-g6c93e979e542+ #1
Hardware name: Intel Corporation Alder Lake Client 
Platform/AlderLake-P DDR4 RVP, BIOS ADLPFWI1.R00.3135.A00.2203251419 
03/25/2022

Call Trace:

dump_stack_lvl+0x56/0x7f
check_noncircular+0x132/0x150
validate_chain+0xb3f/0x2000
__lock_acquire+0x5a4/0xb70
lock_acquire+0xd3/0x310
? blocking_notifier_call_chain+0x20/0x50
down_read+0x39/0x140
? blocking_notifier_call_chain+0x20/0x50
blocking_notifier_call_chain+0x20/0x50
device_add+0x3c1/0x900
? dev_set_name+0x4e/0x70
platform_device_add+0x108/0x240
coretemp_cpu_online+0xe1/0x15e [coretemp]
? create_core_data+0x550/0x550 [coretemp]
cpuhp_invoke_callback+0x181/0x8a0
cpuhp_thread_fun+0x188/0x1f0
? smpboot_thread_fn+0x1e/0x260
smpboot_thread_fn+0x1b5/0x260
? sort_range+0x20/0x20

[Intel-gfx] ✓ Fi.CI.BAT: success for Delay disabling GuC scheduling of an idle context

[Patchwork]

== Series Details ==

Series: Delay disabling GuC scheduling of an idle context
URL   : https://patchwork.freedesktop.org/series/108587/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12139 -> Patchwork_108587v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108587v1/index.html

Participating hosts (39 -> 42)
--

  Additional (4): bat-rplp-1 bat-dg2-8 fi-icl-u2 fi-hsw-4770 
  Missing(1): fi-ctg-p8600 

Known issues


  Here are the changes found in Patchwork_108587v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600:   [PASS][1] -> [FAIL][2] ([fdo#103375])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12139/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108587v1/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108587v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108587v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#3012])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108587v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [PASS][6] -> [DMESG-FAIL][7] ([i915#62])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12139/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108587v1/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][8] -> [DMESG-FAIL][9] ([i915#4528])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12139/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108587v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@ring_submission:
- fi-cfl-8109u:   [PASS][10] -> [DMESG-WARN][11] ([i915#5904]) +30 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12139/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108587v1/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u:   [PASS][12] -> [DMESG-WARN][13] ([i915#5904] / 
[i915#62])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12139/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108587v1/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271]) +9 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108587v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108587v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][16] ([fdo#111827]) +8 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108587v1/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-icl-u2:  NOTRUN -> [SKIP][17] ([i915#4103])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108587v1/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [PASS][18] -> [FAIL][19] ([i915#6298])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12139/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108587v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html

  * igt@kms_force_connector_basic@force-connector-state:
- fi-icl-u2:  NOTRUN -> [WARN][20] ([i915#6008])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108587v1/fi-icl-u2/igt@kms_force_connector_ba...@force-connector-state.html

  * igt@kms_force_connector_basic@force-load-detect:
- 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Delay disabling GuC scheduling of an idle context

[Patchwork]

== Series Details ==

Series: Delay disabling GuC scheduling of an idle context
URL   : https://patchwork.freedesktop.org/series/108587/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for New GuC and new GuC/HuC names

[Patchwork]

== Series Details ==

Series: New GuC and new GuC/HuC names
URL   : https://patchwork.freedesktop.org/series/108582/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12139 -> Patchwork_108582v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108582v1/index.html

Participating hosts (39 -> 40)
--

  Additional (2): bat-rplp-1 bat-dg2-8 
  Missing(1): fi-ctg-p8600 

Known issues


  Here are the changes found in Patchwork_108582v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@gem:
- fi-pnv-d510:[PASS][1] -> [DMESG-FAIL][2] ([i915#4528])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12139/fi-pnv-d510/igt@i915_selftest@l...@gem.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108582v1/fi-pnv-d510/igt@i915_selftest@l...@gem.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [PASS][3] -> [INCOMPLETE][4] ([i915#5982])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12139/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108582v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][5] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108582v1/fi-pnv-d510/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_ringfill@basic-all:
- {bat-dg2-9}:[FAIL][6] ([i915#5886]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12139/bat-dg2-9/igt@gem_ringf...@basic-all.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108582v1/bat-dg2-9/igt@gem_ringf...@basic-all.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-5:  [DMESG-FAIL][8] ([i915#4494] / [i915#4957]) -> 
[PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12139/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108582v1/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html

  * 
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka:   [FAIL][10] ([i915#6298]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12139/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108582v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4093]: https://gitlab.freedesktop.org/drm/intel/issues/4093
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for Further multi-gt handling

[Patchwork]

== Series Details ==

Series: Further multi-gt handling
URL   : https://patchwork.freedesktop.org/series/108577/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12139 -> Patchwork_108577v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108577v1/index.html

Participating hosts (39 -> 41)
--

  Additional (3): bat-rplp-1 bat-dg2-8 fi-hsw-4770 
  Missing(1): fi-ctg-p8600 

Known issues


  Here are the changes found in Patchwork_108577v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#3012])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108577v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][2] ([i915#4785])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108577v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][3] -> [DMESG-FAIL][4] ([i915#4528])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12139/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108577v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [PASS][5] -> [INCOMPLETE][6] ([i915#5982])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12139/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108577v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271]) +9 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108577v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108577v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1072]) +3 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108577v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][10] ([fdo#109271] / [i915#4312] / 
[i915#5594] / [i915#6246])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108577v1/fi-hsw-4770/igt@run...@aborted.html
- fi-pnv-d510:NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108577v1/fi-pnv-d510/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_ringfill@basic-all:
- {bat-dg2-9}:[FAIL][12] ([i915#5886]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12139/bat-dg2-9/igt@gem_ringf...@basic-all.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108577v1/bat-dg2-9/igt@gem_ringf...@basic-all.html

  * 
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka:   [FAIL][14] ([i915#6298]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12139/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108577v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3595]: 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Further multi-gt handling

[Patchwork]

== Series Details ==

Series: Further multi-gt handling
URL   : https://patchwork.freedesktop.org/series/108577/
State : warning

== Summary ==

Error: dim checkpatch failed
7cda801d9e36 drm/i915/gt: Cleanup partial engine discovery failures
-:43: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written 
"!engine->release"
#43: FILE: drivers/gpu/drm/i915/gt/intel_engine_cs.c:1289:
+   GEM_BUG_ON(engine->release == NULL);

-:56: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address 
mismatch: 'From: Chris Wilson ' != 'Signed-off-by: 
Chris Wilson '

total: 0 errors, 1 warnings, 1 checks, 35 lines checked
f6b63c25ea92 drm/i915: Make GEM resume all engines
c19f4077a5e6 drm/i915: Make GEM suspend all GTs
261248f1b8f7 drm/i915: Handle all GTs on driver (un)load paths
-:88: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#88: FILE: drivers/gpu/drm/i915/i915_gem.c:1199:
+   i915_probe_error(dev_priv,
+   "Failed to initialize GPU, 
declaring it wedged!\n");

total: 0 errors, 0 warnings, 1 checks, 95 lines checked

[Intel-gfx] [PATCH 0/1] Delay disabling GuC scheduling of an idle context

[Alan Previn]

This series adds a delay before disabling scheduling of the guc-context
when a context has become idle to avoid costly re-registration that may
occur immediately after. The 2nd patch should explain it quite well.

The origin of this series was posted by Matthew Brost back in Oct 2021
(https://patchwork.freedesktop.org/series/96167/). However no real
world workload performance impact was available until recently proving
it's intended results.

This series is a redo of a prior patch that was reverted:
2ccddb758079d0c62ce03e69ee8929bb212f7799 drm/i915/guc: Add delay to
disable scheduling after pin count goes to zero

The cause for the reversion is now fixed here (was not caught due to
issues with CI reporting at that time). Two additional changes included
in this redo:
 - Resolve race between guc_request_alloc and guc_context_close in
completing the delayed disable-guc-scheduling worker.
 - GT Reset flow properly closing contexts that were pending for the

Matthew Brost (1):
  drm/i915/guc: Delay disabling guc_id scheduling for better hysteresis

 drivers/gpu/drm/i915/gem/i915_gem_context.c   |   2 +-
 drivers/gpu/drm/i915/gt/intel_context.h   |   8 +
 drivers/gpu/drm/i915/gt/intel_context_types.h |   7 +
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  16 ++
 .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c|  60 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 220 +++---
 drivers/gpu/drm/i915/i915_selftest.h  |   2 +
 7 files changed, 288 insertions(+), 27 deletions(-)


base-commit: 37b0cd34584fab54ae910bffd0f148c8ceb2a9c7
-- 
2.25.1

[Intel-gfx] [PATCH 1/1] drm/i915/guc: Delay disabling guc_id scheduling for better hysteresis

[Alan Previn]

From: Matthew Brost 

Add a delay, configurable via debugfs (default 34ms), to disable
scheduling of a context after the pin count goes to zero. Disable
scheduling is a costly operation as it requires synchronizing with
the GuC. So the idea is that a delay allows the user to resubmit
something before doing this operation. This delay is only done if
the context isn't closed and less than a given threshold
(default is 3/4) of the guc_ids are in use.

Alan Previn: Matt Brost first introduced this patch back in Oct 2021.
However no real world workload with measured performance impact was
available to prove the intended results. Today, this series is being
republished in response to a real world workload that benefited greatly
from it along with measured performance improvement.

Workload description: 36 containers were created on a DG2 device where
each container was performing a combination of 720p 3d game rendering
and 30fps video encoding. The workload density was configured in a way
that guaranteed each container to ALWAYS be able to render and
encode no less than 30fps with a predefined maximum render + encode
latency time. That means the totality of all 36 containers and their
workloads were not saturating the engines to their max (in order to
maintain just enough headrooom to meet the min fps and max latencies
of incoming container submissions).

Problem statement: It was observed that the CPU core processing the i915
soft IRQ work was experiencing severe load. Using tracelogs and an
instrumentation patch to count specific i915 IRQ events, it was confirmed
that the majority of the CPU cycles were caused by the
gen11_other_irq_handler() -> guc_irq_handler() code path. The vast
majority of the cycles was determined to be processing a specific G2H
IRQ: i.e. INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE. These IRQs are sent
by GuC in response to i915 KMD sending H2G requests:
INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_SET. Those H2G requests are sent
whenever a context goes idle so that we can unpin the context from GuC.
The high CPU utilization % symptom was limiting density scaling.

Root Cause Analysis: Because the incoming execution buffers were spread
across 36 different containers (each with multiple contexts) but the
system in totality was NOT saturated to the max, it was assumed that each
context was constantly idling between submissions. This was causing
a thrashing of unpinning contexts from GuC at one moment, followed quickly
by repinning them due to incoming workload the very next moment. These
event-pairs were being triggered across multiple contexts per container,
across all containers at the rate of > 30 times per sec per context.

Metrics: When running this workload without this patch, we measured an
average of ~69K INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE events every 10
seconds or ~10 million times over ~25+ mins. With this patch, the count
reduced to ~480 every 10 seconds or about ~28K over ~10 mins. The
improvement observed is ~99% for the average counts per 10 seconds.

Design awareness: Selftest impact.
As temporary WA disable this feature for the selftests. Selftests are
very timing sensitive and any change in timing can cause failure. A
follow up patch will fixup the selftests to understand this delay.

Design awareness: Race between guc_request_alloc and guc_context_close.
If a context close is issued while there is a request submission in
flight and a delayed schedule disable is pending, guc_context_close
and guc_request_alloc will race to cancel the delayed disable.
To close the race, make sure that guc_request_alloc waits for
guc_context_close to finish running before checking any state.

Design awareness: GT Reset event.
If a gt reset is triggered, as preparation steps, add an additional step
to ensure all contexts that have a pending delay-disable-schedule task
be flushed of it. Move them directly into the closed state after cancelling
the worker. This is okay because the existing flow flushes all
yet-to-arrive G2H's dropping them anyway.

Signed-off-by: Matthew Brost 
Signed-off-by: Alan Previn 
Signed-off-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |   2 +-
 drivers/gpu/drm/i915/gt/intel_context.h   |   8 +
 drivers/gpu/drm/i915/gt/intel_context_types.h |   7 +
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  16 ++
 .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c|  60 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 220 +++---
 drivers/gpu/drm/i915/i915_selftest.h  |   2 +
 7 files changed, 288 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index dabdfe09f5e5..df7fd1b019ec 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1454,7 +1454,7 @@ static void engines_idle_release(struct i915_gem_context 
*ctx,
int err;
 
/* serialises with execbuf */
- 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix return type of mode_valid function hook

[Patchwork]

== Series Details ==

Series: drm/i915: Fix return type of mode_valid function hook
URL   : https://patchwork.freedesktop.org/series/108553/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12133_full -> Patchwork_108553v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_108553v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_108553v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_108553v1_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12133/shard-glk5/igt@gem_pp...@flink-and-close-vma-leak.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/shard-glk7/igt@gem_pp...@flink-and-close-vma-leak.html

  
Known issues


  Here are the changes found in Patchwork_108553v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525]) +2 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12133/shard-iclb4/igt@gem_exec_balan...@parallel-out-fence.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/shard-iclb5/igt@gem_exec_balan...@parallel-out-fence.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][5] -> [FAIL][6] ([i915#2842])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12133/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][7] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][8] -> [SKIP][9] ([i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12133/shard-tglb5/igt@gem_huc_c...@huc-copy.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/shard-tglb7/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
- shard-apl:  NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/shard-apl4/igt@gem_lmem_swapp...@heavy-verify-multi.html

  * igt@gem_workarounds@suspend-resume-context:
- shard-apl:  [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1 
similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12133/shard-apl1/igt@gem_workarou...@suspend-resume-context.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/shard-apl1/igt@gem_workarou...@suspend-resume-context.html

  * igt@gen9_exec_parse@allowed-single:
- shard-apl:  [PASS][13] -> [DMESG-WARN][14] ([i915#5566] / 
[i915#716])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12133/shard-apl2/igt@gen9_exec_pa...@allowed-single.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/shard-apl4/igt@gen9_exec_pa...@allowed-single.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#1937])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/shard-apl4/igt@i915_pm_lpsp@kms-l...@kms-lpsp-dp.html

  * igt@i915_pm_rpm@debugfs-forcewake-user:
- shard-apl:  [PASS][16] -> [DMESG-WARN][17] ([i915#165] / 
[i915#62]) +4 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12133/shard-apl6/igt@i915_pm_...@debugfs-forcewake-user.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/shard-apl4/igt@i915_pm_...@debugfs-forcewake-user.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-tglb: [PASS][18] -> [FAIL][19] ([i915#3743]) +1 similar 
issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12133/shard-tglb1/igt@kms_big...@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/shard-tglb2/igt@kms_big...@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3886]) +4 
similar issues
   [20]: 

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Handle all GTs on driver (un)load paths

[Ceraolo Spurio, Daniele]

On 9/14/2022 3:04 PM, Matt Roper wrote:

From: Tvrtko Ursulin 

This, along with the changes already landed in commit 1c66a12ab431
("drm/i915: Handle each GT on init/release and suspend/resume") makes
engines from all GTs actually known to the driver.

To accomplish this we need to sprinkle a lot of for_each_gt calls around
but is otherwise pretty un-eventuful.

Cc: Daniele Ceraolo Spurio 
Signed-off-by: Tvrtko Ursulin 
Signed-off-by: Matt Roper 
---
  drivers/gpu/drm/i915/i915_driver.c |  3 +-
  drivers/gpu/drm/i915/i915_gem.c| 46 ++
  2 files changed, 36 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index c459eb362c47..9d1fc2477f80 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1661,7 +1661,8 @@ static int intel_runtime_suspend(struct device *kdev)
  
  		intel_runtime_pm_enable_interrupts(dev_priv);
  
-		intel_gt_runtime_resume(to_gt(dev_priv));

+   for_each_gt(gt, dev_priv, i)
+   intel_gt_runtime_resume(gt);
  
  		enable_rpm_wakeref_asserts(rpm);
  
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c

index f18cc6270b2b..0bf71082f21a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1128,6 +1128,8 @@ void i915_gem_drain_workqueue(struct drm_i915_private 
*i915)
  
  int i915_gem_init(struct drm_i915_private *dev_priv)

  {
+   struct intel_gt *gt;
+   unsigned int i;
int ret;
  
  	/* We need to fallback to 4K pages if host doesn't support huge gtt. */

@@ -1158,9 +1160,11 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 */
intel_init_clock_gating(dev_priv);
  
-	ret = intel_gt_init(to_gt(dev_priv));

-   if (ret)
-   goto err_unlock;
+   for_each_gt(gt, dev_priv, i) {
+   ret = intel_gt_init(gt);
+   if (ret)
+   goto err_unlock;
+   }
  
  	return 0;
  
@@ -1173,8 +1177,15 @@ int i915_gem_init(struct drm_i915_private *dev_priv)

  err_unlock:
i915_gem_drain_workqueue(dev_priv);
  
-	if (ret != -EIO)

-   intel_uc_cleanup_firmwares(_gt(dev_priv)->uc);
+   if (ret != -EIO) {
+   for_each_gt(gt, dev_priv, i) {
+   intel_gt_driver_remove(gt);
+   intel_gt_driver_release(gt);
+   }
+
+   for_each_gt(gt, dev_priv, i)
+   intel_uc_cleanup_firmwares(>uc);


Any reason not to have the uc_cleanup in the same loop as the gt functions?
Also, you're looping intel_uc_cleanup_firmwares but not 
intel_uc_fetch_firmwares(). Not an issue since the cleanup function will 
skip if the fetch was not done, but I though it was worth mentioning. I 
can include the loop for the fetch as part of the support for the media 
GuC (which I'll send after this is merged).



+   }
  
  	if (ret == -EIO) {

/*
@@ -1182,10 +1193,12 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 * as wedged. But we only want to do this when the GPU is angry,
 * for all other failure, such as an allocation failure, bail.
 */
-   if (!intel_gt_is_wedged(to_gt(dev_priv))) {
-   i915_probe_error(dev_priv,
-"Failed to initialize GPU, declaring it 
wedged!\n");
-   intel_gt_set_wedged(to_gt(dev_priv));
+   for_each_gt(gt, dev_priv, i) {
+   if (!intel_gt_is_wedged(gt)) {
+   i915_probe_error(dev_priv,
+   "Failed to initialize GPU, declaring 
it wedged!\n");
+   intel_gt_set_wedged(gt);
+   }
}
  
  		/* Minimal basic recovery for KMS */

@@ -1213,10 +1226,14 @@ void i915_gem_driver_unregister(struct drm_i915_private 
*i915)
  
  void i915_gem_driver_remove(struct drm_i915_private *dev_priv)

  {
+   struct intel_gt *gt;
+   unsigned int i;
+
intel_wakeref_auto_fini(_gt(dev_priv)->userfault_wakeref);
  
  	i915_gem_suspend_late(dev_priv);

-   intel_gt_driver_remove(to_gt(dev_priv));
+   for_each_gt(gt, dev_priv, i)
+   intel_gt_driver_remove(gt);
dev_priv->uabi_engines = RB_ROOT;
  
  	/* Flush any outstanding unpin_work. */

@@ -1227,9 +1244,14 @@ void i915_gem_driver_remove(struct drm_i915_private 
*dev_priv)
  
  void i915_gem_driver_release(struct drm_i915_private *dev_priv)

  {
-   intel_gt_driver_release(to_gt(dev_priv));
+   struct intel_gt *gt;
+   unsigned int i;
+
+   for_each_gt(gt, dev_priv, i)
+   intel_gt_driver_release(gt);
  
-	intel_uc_cleanup_firmwares(_gt(dev_priv)->uc);

+   for_each_gt(gt, dev_priv, i)
+   intel_uc_cleanup_firmwares(>uc);


Same 

Re: [Intel-gfx] [PATCH 1/1] drm/i915/uc: Update to latest GuC and use new-format GuC/HuC names

[Ceraolo Spurio, Daniele]

On 9/14/2022 4:46 PM, john.c.harri...@intel.com wrote:

From: John Harrison 

Going forwards, the intention is for GuC firmware files to be named
for their major version only and HuC firmware files to have no version
number in the name at all. This patch adds those entries for all
platforms that are officially GuC/HuC enabled.

Also, update the expected GuC version numbers to the latest firmware
release for those platforms.


You didn't record that this is a v2 (the patch name is different but it 
is the same patch ;) ).

The changes LGTM:

Reviewed-by: Daniele Ceraolo Spurio 

Daniele



Signed-off-by: John Harrison 
---
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 10 +++---
  1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 1169e2a09da24..b91ad4aede1f7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -72,12 +72,14 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
   * security fixes, etc. to be enabled.
   */
  #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_maj, guc_mmp) \
-   fw_def(DG2,  0, guc_mmp(dg2,  70, 4, 1)) \
+   fw_def(DG2,  0, guc_maj(dg2,  70, 5)) \
+   fw_def(ALDERLAKE_P,  0, guc_maj(adlp, 70, 5)) \
fw_def(ALDERLAKE_P,  0, guc_mmp(adlp, 70, 1, 1)) \
fw_def(ALDERLAKE_P,  0, guc_mmp(adlp, 69, 0, 3)) \
+   fw_def(ALDERLAKE_S,  0, guc_maj(tgl,  70, 5)) \
fw_def(ALDERLAKE_S,  0, guc_mmp(tgl,  70, 1, 1)) \
fw_def(ALDERLAKE_S,  0, guc_mmp(tgl,  69, 0, 3)) \
-   fw_def(DG1,  0, guc_mmp(dg1,  70, 1, 1)) \
+   fw_def(DG1,  0, guc_maj(dg1,  70, 5)) \
fw_def(ROCKETLAKE,   0, guc_mmp(tgl,  70, 1, 1)) \
fw_def(TIGERLAKE,0, guc_mmp(tgl,  70, 1, 1)) \
fw_def(JASPERLAKE,   0, guc_mmp(ehl,  70, 1, 1)) \
@@ -92,9 +94,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
fw_def(SKYLAKE,  0, guc_mmp(skl,  70, 1, 1))
  
  #define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp) \

+   fw_def(ALDERLAKE_P,  0, huc_raw(tgl)) \
fw_def(ALDERLAKE_P,  0, huc_mmp(tgl,  7, 9, 3)) \
+   fw_def(ALDERLAKE_S,  0, huc_raw(tgl)) \
fw_def(ALDERLAKE_S,  0, huc_mmp(tgl,  7, 9, 3)) \
-   fw_def(DG1,  0, huc_mmp(dg1,  7, 9, 3)) \
+   fw_def(DG1,  0, huc_raw(dg1)) \
fw_def(ROCKETLAKE,   0, huc_mmp(tgl,  7, 9, 3)) \
fw_def(TIGERLAKE,0, huc_mmp(tgl,  7, 9, 3)) \
fw_def(JASPERLAKE,   0, huc_mmp(ehl,  9, 0, 0)) \

Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Fix release build bug in 'remove log size module parameters'

[Ceraolo Spurio, Daniele]

On 9/12/2022 6:09 PM, john.c.harri...@intel.com wrote:

From: John Harrison 

A patch was merged to remove the GuC log size override module
parameters. That patch was broken and caused kernel error messages on
boot in non CONFIG_DEBUG_GUC|GEM builds:
[   12.085121] i915 :00:02.0: [drm] *ERROR* Zero GuC log crash dump size!
[   12.092035] i915 :00:02.0: [drm] *ERROR* Zero GuC log debug size!

So fit it.

Fixes: f54e515c9180 ("drm/i915/guc: Remove log size module parameters")
Cc: Joonas Lahtinen 
Cc: Jani Nikula 
Cc: Rodrigo Vivi 
Cc: Tvrtko Ursulin 
Cc: Alan Previn 
Cc: Jani Nikula 
Cc: Lucas De Marchi 
Cc: Matthew Brost 
Cc: Julia Lawall 
Cc: Chris Wilson 
Signed-off-by: John Harrison 
---
  drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 25 +-
  1 file changed, 1 insertion(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index b071973ac41c1..55d3ef93e86f8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -36,24 +36,6 @@ struct guc_log_section {
const char *name;
  };
  
-static s32 scale_log_param(struct intel_guc_log *log, const struct guc_log_section *section,

-  s32 param)
-{
-   /* -1 means default */
-   if (param < 0)
-   return section->default_val;
-
-   /* Check for 32-bit overflow */
-   if (param >= SZ_4K) {
-   drm_err(_to_gt(log_to_guc(log))->i915->drm, "Size too large for 
GuC %s log: %dMB!",
-   section->name, param);
-   return section->default_val;
-   }
-
-   /* Param units are 1MB */
-   return param * SZ_1M;
-}
-
  static void _guc_log_init_sizes(struct intel_guc_log *log)
  {
struct intel_guc *guc = log_to_guc(log);
@@ -78,15 +60,10 @@ static void _guc_log_init_sizes(struct intel_guc_log *log)
"capture",
}
};
-   s32 params[GUC_LOG_SECTIONS_LIMIT] = {
-   GUC_LOG_DEFAULT_CRASH_BUFFER_SIZE / SZ_1M,
-   GUC_LOG_DEFAULT_DEBUG_BUFFER_SIZE / SZ_1M,
-   GUC_LOG_DEFAULT_CAPTURE_BUFFER_SIZE / SZ_1M,
-   };
int i;
  
  	for (i = 0; i < GUC_LOG_SECTIONS_LIMIT; i++)

-   log->sizes[i].bytes = scale_log_param(log, sections + i, 
params[i]);
+   log->sizes[i].bytes = sections[i].default_val;
  
  	/* If debug size > 1MB then bump default crash size to keep the same units */

if (log->sizes[GUC_LOG_SECTIONS_DEBUG].bytes >= SZ_1M &&


If the user can't tweak the values anymore then we can guarantee that 
the sizes use the same units and change this if to a BUILD_BUG_ON() to 
check that.

Not a blocker for the fix.

Reviewed-by: Daniele Ceraolo Spurio 

Daniele

Re: [Intel-gfx] [PATCH 05/19] drm/i915/perf: Enable commands per clock reporting in OA

[Umesh Nerlige Ramappa]

On Tue, Sep 13, 2022 at 05:19:24PM -0700, Dixit, Ashutosh wrote:

On Tue, 23 Aug 2022 13:41:41 -0700, Umesh Nerlige Ramappa wrote:




Hi Umesh,


XEHPSDV and DG2 provide a way to configure bytes per clock vs commands
per clock reporting. Enable command per clock setting on enabling OA.


should be: Enable bytes per clock setting


What is the reason for selecting commands per clock vs bytes per clock?
Also probably mention Bspec: 51762 in the commit message too.


It's a default configuration used to interpret the A36/A37 counters here 
- Bspec: 52201





diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index efa7eda83edd..6fc4f0d8fc5a 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2745,10 +2745,12 @@ static int
 gen12_enable_metric_set(struct i915_perf_stream *stream,
struct i915_active *active)
 {
+   struct drm_i915_private *i915 = stream->perf->i915;
struct intel_uncore *uncore = stream->uncore;
struct i915_oa_config *oa_config = stream->oa_config;
bool periodic = stream->periodic;
u32 period_exponent = stream->period_exponent;
+   u32 sqcnt1;
int ret;

intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG,
@@ -2767,6 +2769,16 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
(period_exponent << 
GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT))
: 0);

+   /*
+* Initialize Super Queue Internal Cnt Register
+* Set PMON Enable in order to collect valid metrics.
+* Enable commands per clock reporting in OA for XEHPSDV onward.
+*/
+   sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
+(HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);


Also from Bspec 0:Unitsof4cmd and 1:Unitsof128B so looks like bit 29 should
be set to 0 for commands per clock setting? Or I am wrong?


I know bit 29 has to be set for DG2. I think the commit message is 
wrong. Nice catch, thanks





+
+   intel_uncore_rmw(uncore, GEN12_SQCNT1, 0, sqcnt1);
+
/*
 * Update all contexts prior writing the mux configurations as we need
 * to make sure all slices/subslices are ON before writing to NOA
@@ -2816,6 +2828,8 @@ static void gen11_disable_metric_set(struct 
i915_perf_stream *stream)
 static void gen12_disable_metric_set(struct i915_perf_stream *stream)
 {
struct intel_uncore *uncore = stream->uncore;
+   struct drm_i915_private *i915 = stream->perf->i915;
+   u32 sqcnt1;

/* Reset all contexts' slices/subslices configurations. */
gen12_configure_all_contexts(stream, NULL, NULL);
@@ -2826,6 +2840,12 @@ static void gen12_disable_metric_set(struct 
i915_perf_stream *stream)

/* Make sure we disable noa to save power. */
intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
+
+   sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
+(HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
+
+   /* Reset PMON Enable to save power. */
+   intel_uncore_rmw(uncore, GEN12_SQCNT1, sqcnt1, 0);
 }

 static void gen7_oa_enable(struct i915_perf_stream *stream)
diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h 
b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
index 0ef3562ff4aa..381d94101610 100644
--- a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
+++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
@@ -134,4 +134,8 @@
 #define GDT_CHICKEN_BITS_MMIO(0x9840)
 #define   GT_NOA_ENABLE0x0080

+#define GEN12_SQCNT1   _MMIO(0x8718)
+#define   GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
+#define   GEN12_SQCNT1_OABPC   REG_BIT(29)
+
 #endif /* __INTEL_PERF_OA_REGS__ */

[Intel-gfx] ✓ Fi.CI.IGT: success for Enable Pipewriteback (rev4)

[Patchwork]

== Series Details ==

Series: Enable Pipewriteback (rev4)
URL   : https://patchwork.freedesktop.org/series/107440/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12132_full -> Patchwork_107440v4_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_107440v4_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_107440v4_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 10)
--

  Missing(1): shard-rkl 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_107440v4_full:

### IGT changes ###

 Warnings 

  * igt@kms_writeback@writeback-check-output:
- shard-tglb: [SKIP][1] ([i915#2437]) -> [DMESG-FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglb5/igt@kms_writeb...@writeback-check-output.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglb3/igt@kms_writeb...@writeback-check-output.html

  * igt@kms_writeback@writeback-fb-id:
- shard-tglb: [SKIP][3] ([i915#2437]) -> [FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglb7/igt@kms_writeb...@writeback-fb-id.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglb5/igt@kms_writeb...@writeback-fb-id.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_schedule@wide@rcs0:
- {shard-tglu}:   [PASS][5] -> [INCOMPLETE][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglu-2/igt@gem_exec_schedule@w...@rcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglu-6/igt@gem_exec_schedule@w...@rcs0.html

  * igt@kms_prime@basic-crc-vgem@second-to-first:
- {shard-tglu}:   NOTRUN -> [FAIL][7]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglu-4/igt@kms_prime@basic-crc-v...@second-to-first.html

  * igt@kms_writeback@writeback-check-output:
- {shard-tglu}:   [SKIP][8] ([i915#2437]) -> [DMESG-FAIL][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglu-4/igt@kms_writeb...@writeback-check-output.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglu-3/igt@kms_writeb...@writeback-check-output.html

  * igt@kms_writeback@writeback-fb-id:
- {shard-tglu}:   [SKIP][10] ([i915#2437]) -> [FAIL][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-tglu-2/igt@kms_writeb...@writeback-fb-id.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107440v4/shard-tglu-3/igt@kms_writeb...@writeback-fb-id.html

  
Known issues


  Here are the changes found in Patchwork_107440v4_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-skl:  ([PASS][12], [PASS][13], [PASS][14], [PASS][15], 
[PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], 
[PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], 
[PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], 
[PASS][34], [PASS][35]) -> ([PASS][36], [PASS][37], [PASS][38], [PASS][39], 
[PASS][40], [PASS][41], [FAIL][42], [PASS][43], [PASS][44], [PASS][45], 
[PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], 
[PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], 
[PASS][58], [PASS][59], [PASS][60]) ([i915#5032])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl9/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl9/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl9/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl9/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl9/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl7/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl7/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl7/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl7/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl7/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl7/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl6/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-skl6/boot.html
   [25]: 

[Intel-gfx] [PATCH 1/1] drm/i915/uc: Update to latest GuC and use new-format GuC/HuC names

[John . C . Harrison]

From: John Harrison 

Going forwards, the intention is for GuC firmware files to be named
for their major version only and HuC firmware files to have no version
number in the name at all. This patch adds those entries for all
platforms that are officially GuC/HuC enabled.

Also, update the expected GuC version numbers to the latest firmware
release for those platforms.

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 1169e2a09da24..b91ad4aede1f7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -72,12 +72,14 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  * security fixes, etc. to be enabled.
  */
 #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_maj, guc_mmp) \
-   fw_def(DG2,  0, guc_mmp(dg2,  70, 4, 1)) \
+   fw_def(DG2,  0, guc_maj(dg2,  70, 5)) \
+   fw_def(ALDERLAKE_P,  0, guc_maj(adlp, 70, 5)) \
fw_def(ALDERLAKE_P,  0, guc_mmp(adlp, 70, 1, 1)) \
fw_def(ALDERLAKE_P,  0, guc_mmp(adlp, 69, 0, 3)) \
+   fw_def(ALDERLAKE_S,  0, guc_maj(tgl,  70, 5)) \
fw_def(ALDERLAKE_S,  0, guc_mmp(tgl,  70, 1, 1)) \
fw_def(ALDERLAKE_S,  0, guc_mmp(tgl,  69, 0, 3)) \
-   fw_def(DG1,  0, guc_mmp(dg1,  70, 1, 1)) \
+   fw_def(DG1,  0, guc_maj(dg1,  70, 5)) \
fw_def(ROCKETLAKE,   0, guc_mmp(tgl,  70, 1, 1)) \
fw_def(TIGERLAKE,0, guc_mmp(tgl,  70, 1, 1)) \
fw_def(JASPERLAKE,   0, guc_mmp(ehl,  70, 1, 1)) \
@@ -92,9 +94,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
fw_def(SKYLAKE,  0, guc_mmp(skl,  70, 1, 1))
 
 #define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp) \
+   fw_def(ALDERLAKE_P,  0, huc_raw(tgl)) \
fw_def(ALDERLAKE_P,  0, huc_mmp(tgl,  7, 9, 3)) \
+   fw_def(ALDERLAKE_S,  0, huc_raw(tgl)) \
fw_def(ALDERLAKE_S,  0, huc_mmp(tgl,  7, 9, 3)) \
-   fw_def(DG1,  0, huc_mmp(dg1,  7, 9, 3)) \
+   fw_def(DG1,  0, huc_raw(dg1)) \
fw_def(ROCKETLAKE,   0, huc_mmp(tgl,  7, 9, 3)) \
fw_def(TIGERLAKE,0, huc_mmp(tgl,  7, 9, 3)) \
fw_def(JASPERLAKE,   0, huc_mmp(ehl,  9, 0, 0)) \
-- 
2.37.3

[Intel-gfx] [PATCH 0/1] New GuC and new GuC/HuC names

[John . C . Harrison]

From: John Harrison 

Update the GuC version numbers to expect the latest release. Also
start using GuC/HuC firmware files with reduced version information in
the file name.

Signed-off-by: John Harrison 


John Harrison (1):
  drm/i915/uc: Update to latest GuC and use new-format GuC/HuC names

 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

-- 
2.37.3

Re: [Intel-gfx] [PATCH 01/19] drm/i915/perf: Fix OA filtering logic for GuC mode

[Umesh Nerlige Ramappa]

On Mon, Sep 12, 2022 at 08:08:33PM -0700, Dixit, Ashutosh wrote:

On Fri, 09 Sep 2022 16:47:36 -0700, Dixit, Ashutosh wrote:


On Tue, 23 Aug 2022 13:41:37 -0700, Umesh Nerlige Ramappa wrote:
>

Hi Umesh,

> With GuC mode of submission, GuC is in control of defining the context id 
field
> that is part of the OA reports. To filter reports, UMD and KMD must know what 
sw
> context id was chosen by GuC. There is not interface between KMD and GuC to
> determine this, so read the upper-dword of EXECLIST_STATUS to filter/squash OA
> reports for the specific context.

Do you think it is worth defining an interface for GuC to return the sw
ctx_id it will be using for a ctx, say at ctx registration time?


Umesh, I came across these in GuC documentation:

guc_pcv1_context_parameters_set_h2g_data_t::context_id
guc_pcv2_context_parameters_set_h2g_data_t::context_id

Also in the code we have in prepare_context_registration_info_v70 'ctx_id =
ce->guc_id.id' which seems to be assigned in new_guc_id. So wondering if
this is what we need and we already have it?


this id is different from what GuC programs into the lrca.

Thanks,
Umesh


Thanks.
--
Ashutosh

Re: [Intel-gfx] [PATCH 01/19] drm/i915/perf: Fix OA filtering logic for GuC mode

[Umesh Nerlige Ramappa]

On Fri, Sep 09, 2022 at 04:47:36PM -0700, Dixit, Ashutosh wrote:

On Tue, 23 Aug 2022 13:41:37 -0700, Umesh Nerlige Ramappa wrote:




Hi Umesh,


With GuC mode of submission, GuC is in control of defining the context id field
that is part of the OA reports. To filter reports, UMD and KMD must know what sw
context id was chosen by GuC. There is not interface between KMD and GuC to
determine this, so read the upper-dword of EXECLIST_STATUS to filter/squash OA
reports for the specific context.


Do you think it is worth defining an interface for GuC to return the sw
ctx_id it will be using for a ctx, say at ctx registration time?

The scheme implemented in this patch to read the ctx_id is certainly very
clever, at least to me. But as Lionel was saying is it a agreed upon
immutable interface? If it is, we can go with this patch.

(Though even then we will need to maintain this code even if in the future
GuC FW is changed to return the ctx_id in order to preserve backwards
comptability with previous GuC versions. So maybe better to have a real
interface between GuC and KMD earlier rather than later?).


Agree, ideally this should be obtained from GuC and properly 
synchronized with kmd. OR GuC should provide a way to pin the context id 
for such cases so that the id is not stolen/unpinned. Anyways, we need 
to follow this up as a JIRA.


I may drop this patch and add a message that OA buffer filtering may be 
broken if a gem context is passed.




Also a couple of general comments below.



Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/gt/intel_lrc.h |   2 +
 drivers/gpu/drm/i915/i915_perf.c| 141 
 2 files changed, 124 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h 
b/drivers/gpu/drm/i915/gt/intel_lrc.h
index a390f0813c8b..7111bae759f3 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -110,6 +110,8 @@ enum {
 #define XEHP_SW_CTX_ID_WIDTH   16
 #define XEHP_SW_COUNTER_SHIFT  58
 #define XEHP_SW_COUNTER_WIDTH  6
+#define GEN12_GUC_SW_CTX_ID_SHIFT  39
+#define GEN12_GUC_SW_CTX_ID_WIDTH  16

 static inline void lrc_runtime_start(struct intel_context *ce)
 {
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index f3c23fe9ad9c..735244a3aedd 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1233,6 +1233,125 @@ static struct intel_context *oa_pin_context(struct 
i915_perf_stream *stream)
return stream->pinned_ctx;
 }

+static int
+__store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)
+{
+   u32 *cs, cmd;
+
+   cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
+   if (GRAPHICS_VER(rq->engine->i915) >= 8)
+   cmd++;
+
+   cs = intel_ring_begin(rq, 4);
+   if (IS_ERR(cs))
+   return PTR_ERR(cs);
+
+   *cs++ = cmd;
+   *cs++ = i915_mmio_reg_offset(reg);
+   *cs++ = ggtt_offset;
+   *cs++ = 0;
+
+   intel_ring_advance(rq, cs);
+
+   return 0;
+}
+
+static int
+__read_reg(struct intel_context *ce, i915_reg_t reg, u32 ggtt_offset)
+{
+   struct i915_request *rq;
+   int err;
+
+   rq = i915_request_create(ce);
+   if (IS_ERR(rq))
+   return PTR_ERR(rq);
+
+   i915_request_get(rq);
+
+   err = __store_reg_to_mem(rq, reg, ggtt_offset);
+
+   i915_request_add(rq);
+   if (!err && i915_request_wait(rq, 0, HZ / 2) < 0)
+   err = -ETIME;
+
+   i915_request_put(rq);
+
+   return err;
+}
+
+static int
+gen12_guc_sw_ctx_id(struct intel_context *ce, u32 *ctx_id)
+{
+   struct i915_vma *scratch;
+   u32 *val;
+   int err;
+
+   scratch = 
__vm_create_scratch_for_read_pinned(>engine->gt->ggtt->vm, 4);
+   if (IS_ERR(scratch))
+   return PTR_ERR(scratch);
+
+   err = i915_vma_sync(scratch);
+   if (err)
+   goto err_scratch;
+
+   err = __read_reg(ce, RING_EXECLIST_STATUS_HI(ce->engine->mmio_base),
+i915_ggtt_offset(scratch));


Actually the RING_EXECLIST_STATUS_HI is MMIO so can be read using say
ENGINE_READ/intel_uncore_read. The only issue is how to read it when this
ctx is scheduled which is cleverly solved by the scheme above. But I am not
sure if there is any other simpler way to do it.


+   if (err)
+   goto err_scratch;
+
+   val = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);
+   if (IS_ERR(val)) {
+   err = PTR_ERR(val);
+   goto err_scratch;
+   }
+
+   *ctx_id = *val;
+   i915_gem_object_unpin_map(scratch->obj);
+
+err_scratch:
+   i915_vma_unpin_and_release(, 0);
+   return err;
+}
+
+/*
+ * For execlist mode of submission, pick an unused context id
+ * 0 - (NUM_CONTEXT_TAG -1) are used by other contexts
+ * XXX_MAX_CONTEXT_HW_ID is 

Re: [Intel-gfx] [PATCH 01/19] drm/i915/perf: Fix OA filtering logic for GuC mode

[Umesh Nerlige Ramappa]

On Wed, Sep 14, 2022 at 03:26:15PM -0700, Umesh Nerlige Ramappa wrote:

On Tue, Sep 06, 2022 at 09:39:33PM +0300, Lionel Landwerlin wrote:

On 06/09/2022 20:39, Umesh Nerlige Ramappa wrote:

On Tue, Sep 06, 2022 at 05:33:00PM +0300, Lionel Landwerlin wrote:

On 23/08/2022 23:41, Umesh Nerlige Ramappa wrote:
With GuC mode of submission, GuC is in control of defining the 
context id field
that is part of the OA reports. To filter reports, UMD and KMD 
must know what sw
context id was chosen by GuC. There is not interface between 
KMD and GuC to
determine this, so read the upper-dword of EXECLIST_STATUS to 
filter/squash OA

reports for the specific context.

Signed-off-by: Umesh Nerlige Ramappa 



I assume you checked with GuC that this doesn't change as the 
context is running?


Correct.



With i915/execlist submission mode, we had to ask i915 to pin 
the sw_id/ctx_id.




From GuC perspective, the context id can change once KMD 
de-registers the context and that will not happen while the 
context is in use.


Thanks,
Umesh



Thanks Umesh,


Maybe I should have been more precise in my question :


Can the ID change while the i915-perf stream is opened?

Because the ID not changing while the context is running makes sense.

But since the number of available IDs is limited to 2k or something 
on Gfx12, it's possible the GuC has to reuse IDs if too many apps 
want to run during the period of time while i915-perf is active and 
filtering.




available guc ids are 64k with 4k reserved for multi-lrc, so GuC may 
have to reuse ids once 60k ids are used up.


Spoke to the GuC team again and if there are a lot of contexts (> 60K) 
running, there is a possibility of the context id being recycled. In 
that case, the capture would be broken. I would track this as a separate 
JIRA and follow up on a solution.


From OA use case perspective, are we interested in monitoring just one 
hardware context? If we make sure this context is not stolen, are we 
good? 


Thanks,
Umesh



Thanks,
Umesh



-Lionel






If that's not the case then filtering is broken.


-Lionel



---
 drivers/gpu/drm/i915/gt/intel_lrc.h |   2 +
 drivers/gpu/drm/i915/i915_perf.c    | 141 
 2 files changed, 124 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h 
b/drivers/gpu/drm/i915/gt/intel_lrc.h

index a390f0813c8b..7111bae759f3 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -110,6 +110,8 @@ enum {
 #define XEHP_SW_CTX_ID_WIDTH    16
 #define XEHP_SW_COUNTER_SHIFT    58
 #define XEHP_SW_COUNTER_WIDTH    6
+#define GEN12_GUC_SW_CTX_ID_SHIFT    39
+#define GEN12_GUC_SW_CTX_ID_WIDTH    16
 static inline void lrc_runtime_start(struct intel_context *ce)
 {
diff --git a/drivers/gpu/drm/i915/i915_perf.c 
b/drivers/gpu/drm/i915/i915_perf.c

index f3c23fe9ad9c..735244a3aedd 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1233,6 +1233,125 @@ static struct intel_context 
*oa_pin_context(struct i915_perf_stream *stream)

 return stream->pinned_ctx;
 }
+static int
+__store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, 
u32 ggtt_offset)

+{
+    u32 *cs, cmd;
+
+    cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
+    if (GRAPHICS_VER(rq->engine->i915) >= 8)
+    cmd++;
+
+    cs = intel_ring_begin(rq, 4);
+    if (IS_ERR(cs))
+    return PTR_ERR(cs);
+
+    *cs++ = cmd;
+    *cs++ = i915_mmio_reg_offset(reg);
+    *cs++ = ggtt_offset;
+    *cs++ = 0;
+
+    intel_ring_advance(rq, cs);
+
+    return 0;
+}
+
+static int
+__read_reg(struct intel_context *ce, i915_reg_t reg, u32 ggtt_offset)
+{
+    struct i915_request *rq;
+    int err;
+
+    rq = i915_request_create(ce);
+    if (IS_ERR(rq))
+    return PTR_ERR(rq);
+
+    i915_request_get(rq);
+
+    err = __store_reg_to_mem(rq, reg, ggtt_offset);
+
+    i915_request_add(rq);
+    if (!err && i915_request_wait(rq, 0, HZ / 2) < 0)
+    err = -ETIME;
+
+    i915_request_put(rq);
+
+    return err;
+}
+
+static int
+gen12_guc_sw_ctx_id(struct intel_context *ce, u32 *ctx_id)
+{
+    struct i915_vma *scratch;
+    u32 *val;
+    int err;
+
+    scratch = 
__vm_create_scratch_for_read_pinned(>engine->gt->ggtt->vm, 
4);

+    if (IS_ERR(scratch))
+    return PTR_ERR(scratch);
+
+    err = i915_vma_sync(scratch);
+    if (err)
+    goto err_scratch;
+
+    err = __read_reg(ce, 
RING_EXECLIST_STATUS_HI(ce->engine->mmio_base),

+ i915_ggtt_offset(scratch));
+    if (err)
+    goto err_scratch;
+
+    val = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);
+    if (IS_ERR(val)) {
+    err = PTR_ERR(val);
+    goto err_scratch;
+    }
+
+    *ctx_id = *val;
+    i915_gem_object_unpin_map(scratch->obj);
+
+err_scratch:
+    i915_vma_unpin_and_release(, 0);
+    return err;
+}
+
+/*
+ * For execlist mode of submission, pick an unused context id
+ * 0 - (NUM_CONTEXT_TAG 

Re: [Intel-gfx] [PATCH 01/19] drm/i915/perf: Fix OA filtering logic for GuC mode

[Umesh Nerlige Ramappa]

On Tue, Sep 06, 2022 at 09:39:33PM +0300, Lionel Landwerlin wrote:

On 06/09/2022 20:39, Umesh Nerlige Ramappa wrote:

On Tue, Sep 06, 2022 at 05:33:00PM +0300, Lionel Landwerlin wrote:

On 23/08/2022 23:41, Umesh Nerlige Ramappa wrote:
With GuC mode of submission, GuC is in control of defining the 
context id field
that is part of the OA reports. To filter reports, UMD and KMD 
must know what sw
context id was chosen by GuC. There is not interface between KMD 
and GuC to
determine this, so read the upper-dword of EXECLIST_STATUS to 
filter/squash OA

reports for the specific context.

Signed-off-by: Umesh Nerlige Ramappa 



I assume you checked with GuC that this doesn't change as the 
context is running?


Correct.



With i915/execlist submission mode, we had to ask i915 to pin the 
sw_id/ctx_id.




From GuC perspective, the context id can change once KMD 
de-registers the context and that will not happen while the context 
is in use.


Thanks,
Umesh



Thanks Umesh,


Maybe I should have been more precise in my question :


Can the ID change while the i915-perf stream is opened?

Because the ID not changing while the context is running makes sense.

But since the number of available IDs is limited to 2k or something on 
Gfx12, it's possible the GuC has to reuse IDs if too many apps want to 
run during the period of time while i915-perf is active and filtering.




available guc ids are 64k with 4k reserved for multi-lrc, so GuC may 
have to reuse ids once 60k ids are used up.


Thanks,
Umesh



-Lionel






If that's not the case then filtering is broken.


-Lionel



---
 drivers/gpu/drm/i915/gt/intel_lrc.h |   2 +
 drivers/gpu/drm/i915/i915_perf.c    | 141 
 2 files changed, 124 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h 
b/drivers/gpu/drm/i915/gt/intel_lrc.h

index a390f0813c8b..7111bae759f3 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -110,6 +110,8 @@ enum {
 #define XEHP_SW_CTX_ID_WIDTH    16
 #define XEHP_SW_COUNTER_SHIFT    58
 #define XEHP_SW_COUNTER_WIDTH    6
+#define GEN12_GUC_SW_CTX_ID_SHIFT    39
+#define GEN12_GUC_SW_CTX_ID_WIDTH    16
 static inline void lrc_runtime_start(struct intel_context *ce)
 {
diff --git a/drivers/gpu/drm/i915/i915_perf.c 
b/drivers/gpu/drm/i915/i915_perf.c

index f3c23fe9ad9c..735244a3aedd 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1233,6 +1233,125 @@ static struct intel_context 
*oa_pin_context(struct i915_perf_stream *stream)

 return stream->pinned_ctx;
 }
+static int
+__store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 
ggtt_offset)

+{
+    u32 *cs, cmd;
+
+    cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
+    if (GRAPHICS_VER(rq->engine->i915) >= 8)
+    cmd++;
+
+    cs = intel_ring_begin(rq, 4);
+    if (IS_ERR(cs))
+    return PTR_ERR(cs);
+
+    *cs++ = cmd;
+    *cs++ = i915_mmio_reg_offset(reg);
+    *cs++ = ggtt_offset;
+    *cs++ = 0;
+
+    intel_ring_advance(rq, cs);
+
+    return 0;
+}
+
+static int
+__read_reg(struct intel_context *ce, i915_reg_t reg, u32 ggtt_offset)
+{
+    struct i915_request *rq;
+    int err;
+
+    rq = i915_request_create(ce);
+    if (IS_ERR(rq))
+    return PTR_ERR(rq);
+
+    i915_request_get(rq);
+
+    err = __store_reg_to_mem(rq, reg, ggtt_offset);
+
+    i915_request_add(rq);
+    if (!err && i915_request_wait(rq, 0, HZ / 2) < 0)
+    err = -ETIME;
+
+    i915_request_put(rq);
+
+    return err;
+}
+
+static int
+gen12_guc_sw_ctx_id(struct intel_context *ce, u32 *ctx_id)
+{
+    struct i915_vma *scratch;
+    u32 *val;
+    int err;
+
+    scratch = 
__vm_create_scratch_for_read_pinned(>engine->gt->ggtt->vm, 
4);

+    if (IS_ERR(scratch))
+    return PTR_ERR(scratch);
+
+    err = i915_vma_sync(scratch);
+    if (err)
+    goto err_scratch;
+
+    err = __read_reg(ce, 
RING_EXECLIST_STATUS_HI(ce->engine->mmio_base),

+ i915_ggtt_offset(scratch));
+    if (err)
+    goto err_scratch;
+
+    val = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);
+    if (IS_ERR(val)) {
+    err = PTR_ERR(val);
+    goto err_scratch;
+    }
+
+    *ctx_id = *val;
+    i915_gem_object_unpin_map(scratch->obj);
+
+err_scratch:
+    i915_vma_unpin_and_release(, 0);
+    return err;
+}
+
+/*
+ * For execlist mode of submission, pick an unused context id
+ * 0 - (NUM_CONTEXT_TAG -1) are used by other contexts
+ * XXX_MAX_CONTEXT_HW_ID is used by idle context
+ *
+ * For GuC mode of submission read context id from the upper 
dword of the

+ * EXECLIST_STATUS register.
+ */
+static int gen12_get_render_context_id(struct i915_perf_stream 
*stream)

+{
+    u32 ctx_id, mask;
+    int ret;
+
+    if (intel_engine_uses_guc(stream->engine)) {
+    ret = gen12_guc_sw_ctx_id(stream->pinned_ctx, _id);
+    if (ret)
+    return ret;
+
+    mask = ((1U << 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: A couple of if/else ladder refactors (rev2)

[Lucas De Marchi]

On Wed, Sep 14, 2022 at 03:34:12PM +, Patchwork wrote:

== Series Details ==

Series: drm/i915: A couple of if/else ladder refactors (rev2)
URL   : https://patchwork.freedesktop.org/series/108315/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12132_full -> Patchwork_108315v2_full


Summary
---

 **FAILURE**

 Serious unknown changes coming with Patchwork_108315v2_full absolutely need to 
be
 verified manually.

 If you think the reported changes have nothing to do with the changes
 introduced in Patchwork_108315v2_full, please notify your bug team to allow 
them
 to document this new failure mode, which will reduce false positives in CI.



Participating hosts (11 -> 11)
--

 No changes in participating hosts

Possible new issues
---

 Here are the unknown changes that may have been introduced in 
Patchwork_108315v2_full:

### IGT changes ###

 Possible regressions 

 * igt@gen9_exec_parse@bb-large:
   - shard-apl:  [PASS][1] -> [TIMEOUT][2]
  [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/igt@gen9_exec_pa...@bb-large.html
  [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v2/shard-apl2/igt@gen9_exec_pa...@bb-large.html



unrelated to this change and also failed recently in drm-tip:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-apl7/igt@gen9_exec_pa...@bb-large.html

pushed, thanks for reviews.

Lucas De Marchi

[Intel-gfx] [PATCH 4/4] drm/i915: Handle all GTs on driver (un)load paths

[Matt Roper]

From: Tvrtko Ursulin 

This, along with the changes already landed in commit 1c66a12ab431
("drm/i915: Handle each GT on init/release and suspend/resume") makes
engines from all GTs actually known to the driver.

To accomplish this we need to sprinkle a lot of for_each_gt calls around
but is otherwise pretty un-eventuful.

Cc: Daniele Ceraolo Spurio 
Signed-off-by: Tvrtko Ursulin 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/i915_driver.c |  3 +-
 drivers/gpu/drm/i915/i915_gem.c| 46 ++
 2 files changed, 36 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index c459eb362c47..9d1fc2477f80 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1661,7 +1661,8 @@ static int intel_runtime_suspend(struct device *kdev)
 
intel_runtime_pm_enable_interrupts(dev_priv);
 
-   intel_gt_runtime_resume(to_gt(dev_priv));
+   for_each_gt(gt, dev_priv, i)
+   intel_gt_runtime_resume(gt);
 
enable_rpm_wakeref_asserts(rpm);
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f18cc6270b2b..0bf71082f21a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1128,6 +1128,8 @@ void i915_gem_drain_workqueue(struct drm_i915_private 
*i915)
 
 int i915_gem_init(struct drm_i915_private *dev_priv)
 {
+   struct intel_gt *gt;
+   unsigned int i;
int ret;
 
/* We need to fallback to 4K pages if host doesn't support huge gtt. */
@@ -1158,9 +1160,11 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 */
intel_init_clock_gating(dev_priv);
 
-   ret = intel_gt_init(to_gt(dev_priv));
-   if (ret)
-   goto err_unlock;
+   for_each_gt(gt, dev_priv, i) {
+   ret = intel_gt_init(gt);
+   if (ret)
+   goto err_unlock;
+   }
 
return 0;
 
@@ -1173,8 +1177,15 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 err_unlock:
i915_gem_drain_workqueue(dev_priv);
 
-   if (ret != -EIO)
-   intel_uc_cleanup_firmwares(_gt(dev_priv)->uc);
+   if (ret != -EIO) {
+   for_each_gt(gt, dev_priv, i) {
+   intel_gt_driver_remove(gt);
+   intel_gt_driver_release(gt);
+   }
+
+   for_each_gt(gt, dev_priv, i)
+   intel_uc_cleanup_firmwares(>uc);
+   }
 
if (ret == -EIO) {
/*
@@ -1182,10 +1193,12 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 * as wedged. But we only want to do this when the GPU is angry,
 * for all other failure, such as an allocation failure, bail.
 */
-   if (!intel_gt_is_wedged(to_gt(dev_priv))) {
-   i915_probe_error(dev_priv,
-"Failed to initialize GPU, declaring 
it wedged!\n");
-   intel_gt_set_wedged(to_gt(dev_priv));
+   for_each_gt(gt, dev_priv, i) {
+   if (!intel_gt_is_wedged(gt)) {
+   i915_probe_error(dev_priv,
+   "Failed to initialize GPU, 
declaring it wedged!\n");
+   intel_gt_set_wedged(gt);
+   }
}
 
/* Minimal basic recovery for KMS */
@@ -1213,10 +1226,14 @@ void i915_gem_driver_unregister(struct drm_i915_private 
*i915)
 
 void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
 {
+   struct intel_gt *gt;
+   unsigned int i;
+
intel_wakeref_auto_fini(_gt(dev_priv)->userfault_wakeref);
 
i915_gem_suspend_late(dev_priv);
-   intel_gt_driver_remove(to_gt(dev_priv));
+   for_each_gt(gt, dev_priv, i)
+   intel_gt_driver_remove(gt);
dev_priv->uabi_engines = RB_ROOT;
 
/* Flush any outstanding unpin_work. */
@@ -1227,9 +1244,14 @@ void i915_gem_driver_remove(struct drm_i915_private 
*dev_priv)
 
 void i915_gem_driver_release(struct drm_i915_private *dev_priv)
 {
-   intel_gt_driver_release(to_gt(dev_priv));
+   struct intel_gt *gt;
+   unsigned int i;
+
+   for_each_gt(gt, dev_priv, i)
+   intel_gt_driver_release(gt);
 
-   intel_uc_cleanup_firmwares(_gt(dev_priv)->uc);
+   for_each_gt(gt, dev_priv, i)
+   intel_uc_cleanup_firmwares(>uc);
 
i915_gem_drain_freed_objects(dev_priv);
 
-- 
2.37.3

[Intel-gfx] [PATCH 2/4] drm/i915: Make GEM resume all engines

[Matt Roper]

From: Tvrtko Ursulin 

Walk all GTs from i915_gem_resume when resuming engines.

Cc: Andi Shyti 
Signed-off-by: Tvrtko Ursulin 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gem/i915_gem_pm.c | 22 --
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 3428f735e786..2c80cc8362b6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -212,7 +212,8 @@ int i915_gem_freeze_late(struct drm_i915_private *i915)
 
 void i915_gem_resume(struct drm_i915_private *i915)
 {
-   int ret;
+   struct intel_gt *gt;
+   int ret, i, j;
 
GEM_TRACE("%s\n", dev_name(i915->drm.dev));
 
@@ -224,8 +225,25 @@ void i915_gem_resume(struct drm_i915_private *i915)
 * guarantee that the context image is complete. So let's just reset
 * it and start again.
 */
-   intel_gt_resume(to_gt(i915));
+   for_each_gt(gt, i915, i)
+   if (intel_gt_resume(gt))
+   goto err_wedged;
 
ret = lmem_restore(i915, I915_TTM_BACKUP_ALLOW_GPU);
GEM_WARN_ON(ret);
+
+   return;
+
+err_wedged:
+   for_each_gt(gt, i915, j) {
+   if (!intel_gt_is_wedged(gt)) {
+   dev_err(i915->drm.dev,
+   "Failed to re-initialize GPU[%u], declaring it 
wedged!\n",
+   j);
+   intel_gt_set_wedged(gt);
+   }
+
+   if (j == i)
+   break;
+   }
 }
-- 
2.37.3

[Intel-gfx] [PATCH 3/4] drm/i915: Make GEM suspend all GTs

[Matt Roper]

From: Tvrtko Ursulin 

Walk all GTs when suspending.

Signed-off-by: Tvrtko Ursulin 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gem/i915_gem_pm.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 2c80cc8362b6..e5bfb6be9f7a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -22,6 +22,9 @@
 
 void i915_gem_suspend(struct drm_i915_private *i915)
 {
+   struct intel_gt *gt;
+   unsigned int i;
+
GEM_TRACE("%s\n", dev_name(i915->drm.dev));
 
intel_wakeref_auto(_gt(i915)->userfault_wakeref, 0);
@@ -36,7 +39,8 @@ void i915_gem_suspend(struct drm_i915_private *i915)
 * state. Fortunately, the kernel_context is disposable and we do
 * not rely on its state.
 */
-   intel_gt_suspend_prepare(to_gt(i915));
+   for_each_gt(gt, i915, i)
+   intel_gt_suspend_prepare(gt);
 
i915_gem_drain_freed_objects(i915);
 }
@@ -131,7 +135,9 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
>mm.purge_list,
NULL
}, **phase;
+   struct intel_gt *gt;
unsigned long flags;
+   unsigned int i;
bool flush = false;
 
/*
@@ -154,7 +160,8 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
 * machine in an unusable condition.
 */
 
-   intel_gt_suspend_late(to_gt(i915));
+   for_each_gt(gt, i915, i)
+   intel_gt_suspend_late(gt);
 
spin_lock_irqsave(>mm.obj_lock, flags);
for (phase = phases; *phase; phase++) {
-- 
2.37.3

[Intel-gfx] [PATCH 1/4] drm/i915/gt: Cleanup partial engine discovery failures

[Matt Roper]

From: Chris Wilson 

If we abort driver initialisation in the middle of gt/engine discovery,
some engines will be fully setup and some not. Those incompletely setup
engines only have 'engine->release == NULL' and so will leak any of the
common objects allocated.

Signed-off-by: Chris Wilson 
Cc: Janusz Krzysztofik 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 16 +---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1f7188129cd1..bff12b4ec314 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1196,6 +1196,12 @@ void intel_engine_destroy_pinned_context(struct 
intel_context *ce)
intel_context_put(ce);
 }
 
+static void destroy_pinned_context(struct intel_context *ce)
+{
+   if (ce)
+   intel_engine_destroy_pinned_context(ce);
+}
+
 static struct intel_context *
 create_kernel_context(struct intel_engine_cs *engine)
 {
@@ -1274,8 +1280,13 @@ int intel_engines_init(struct intel_gt *gt)
return err;
 
err = setup(engine);
-   if (err)
+   if (err) {
+   intel_engine_cleanup_common(engine);
return err;
+   }
+
+   /* The backend should now be responsible for cleanup */
+   GEM_BUG_ON(engine->release == NULL);
 
err = engine_init_common(engine);
if (err)
@@ -1307,8 +1318,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs 
*engine)
if (engine->default_state)
fput(engine->default_state);
 
-   if (engine->kernel_context)
-   intel_engine_destroy_pinned_context(engine->kernel_context);
+   destroy_pinned_context(engine->kernel_context);
 
GEM_BUG_ON(!llist_empty(>barrier_tasks));
cleanup_status_page(engine);
-- 
2.37.3

[Intel-gfx] [PATCH 0/4] Further multi-gt handling

[Matt Roper]

Now that MTL is going to start providing two GTs, there are a few more
places in the driver that need to iterate over each GT instead of
operating directly on gt0.  Also some more deliberate cleanup is needed,
in cases where we fail GT/engine initialization after the first GT has
been fully setup.

Cc: Daniele Ceraolo Spurio 

Chris Wilson (1):
  drm/i915/gt: Cleanup partial engine discovery failures

Tvrtko Ursulin (3):
  drm/i915: Make GEM resume all engines
  drm/i915: Make GEM suspend all GTs
  drm/i915: Handle all GTs on driver (un)load paths

 drivers/gpu/drm/i915/gem/i915_gem_pm.c| 33 ++--
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 16 ++--
 drivers/gpu/drm/i915/i915_driver.c|  3 +-
 drivers/gpu/drm/i915/i915_gem.c   | 46 +--
 4 files changed, 78 insertions(+), 20 deletions(-)

-- 
2.37.3

Re: [Intel-gfx] [PATCH 1/4] drm/i915/display: Add CDCLK actions to intel_cdclk_state

[Srivatsa, Anusha]

> -Original Message-
> From: Ville Syrjälä 
> Sent: Wednesday, September 14, 2022 2:43 PM
> To: Srivatsa, Anusha 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/display: Add CDCLK actions to
> intel_cdclk_state
> 
> On Thu, Sep 15, 2022 at 12:22:53AM +0300, Ville Syrjälä wrote:
> > On Fri, Aug 19, 2022 at 05:58:19PM -0700, Anusha Srivatsa wrote:
> > > This is a prep patch for what the rest of the series does.
> > >
> > > Add existing actions that change cdclk - squash, crawl, modeset to
> > > intel_cdclk_state so we have access to the cdclk values that are in
> > > transition.
> > >
> > > Cc: Jani Nikula 
> > > Signed-off-by: Anusha Srivatsa 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_cdclk.h | 13 +
> > >  1 file changed, 13 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
> > > b/drivers/gpu/drm/i915/display/intel_cdclk.h
> > > index b535cf6a7d9e..43835688ee02 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> > > @@ -15,6 +15,14 @@ struct drm_i915_private;  struct
> > > intel_atomic_state;  struct intel_crtc_state;
> > >
> > > +enum cdclk_actions {
> > > + INTEL_CDCLK_MODESET = 0,
> > > + INTEL_CDCLK_SQUASH,
> > > + INTEL_CDCLK_CRAWL,
> > > + INTEL_CDCLK_NOOP,
> > > + MAX_CDCLK_ACTIONS
> > > +};
> >
> > This whole actions thing feels overly complicated to me.
> > I think we should only need something like this:
> >
> > if (new.squash > old.squash) {
> > mid.vco = old.vco;
> > mid.squash = new.squash;
> > } else {
> > mid.vco = new.vco;
> > mid.squash = old.squash;
> > }
> > /*
> >  * bunch of asserts here to make sure
> >  * the mid state looks sane.
> >  */
> > set_cdclk(mid);
> > set_cdclk(new);
> >
> > And perhaps the current set_cdclk needs to get chunked up into smaller
> > pieces so we don't do all the pre/post stuff more than once
> > needlessly.
> 
> One idea might be to pass just a pair of flags to set_cdclk() whether to skip
> the pre/post steps.

This is all considering that the new struct cdclk_step is embedded in 
cdclk_config and not cdclk_state. I am not understanding why cdclk-state is not 
accessible from bxt_set_cdclk. 
What if I add cdclk_state to the dev_priv? bxt_set_cdclk() anyway has dev_priv. 

Anusha 
> --
> Ville Syrjälä
> Intel

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Fix bug in version reduced firmware update (rev2)

[John Harrison]

On 9/14/2022 10:07, Patchwork wrote:

Project List - Patchwork *Patch Details*
*Series:*   Fix bug in version reduced firmware update (rev2)
*URL:*  https://patchwork.freedesktop.org/series/108461/
*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v2/index.html



  CI Bug Log - changes from CI_DRM_12132_full -> Patchwork_108461v2_full


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_108461v2_full absolutely 
need to be

verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108461v2_full, please notify your bug team to 
allow them
to document this new failure mode, which will reduce false positives 
in CI.



Participating hosts (11 -> 11)

No changes in participating hosts


Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_108461v2_full:



  IGT changes


Possible regressions

  * igt@i915_pm_sseu@full-enable:
  o shard-apl: NOTRUN -> FAIL



Failure is unrelated. This platform is running with GuC completely 
disabled and the patch only affects GuC loading.


John.


 *


Known issues

Here are the changes found in Patchwork_108461v2_full that come from 
known issues:



  CI changes


Possible fixes

 *

boot:

 o

shard-apl: (FAIL

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

)
(i915#4386
) ->
(PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

,
PASS

[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915: Force compilation with intel-iommu for CI validation"

[Patchwork]

== Series Details ==

Series: Revert "drm/i915: Force compilation with intel-iommu for CI validation"
URL   : https://patchwork.freedesktop.org/series/108576/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12136 -> Patchwork_108576v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108576v1/index.html

Participating hosts (41 -> 42)
--

  Additional (2): bat-dg2-9 bat-adlp-6 
  Missing(1): fi-ctg-p8600 

Known issues


  Here are the changes found in Patchwork_108576v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#111827])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108576v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-rkl-11600:   NOTRUN -> [SKIP][2] ([fdo#111827])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108576v1/fi-rkl-11600/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-pnv-d510:NOTRUN -> [SKIP][3] ([fdo#109271])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108576v1/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-dp2:
- fi-icl-u2:  [PASS][4] -> [DMESG-WARN][5] ([i915#4890])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12136/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@c-dp2.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108576v1/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@c-dp2.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-2:
- fi-bdw-5557u:   [PASS][6] -> [INCOMPLETE][7] ([i915#146])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12136/fi-bdw-5557u/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-hdmi-a-2.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108576v1/fi-bdw-5557u/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-hdmi-a-2.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][8] ([i915#2867] / [i915#6842]) -> 
[PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12136/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108576v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@gem:
- fi-pnv-d510:[DMESG-FAIL][10] ([i915#4528]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12136/fi-pnv-d510/igt@i915_selftest@l...@gem.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108576v1/fi-pnv-d510/igt@i915_selftest@l...@gem.html

  * igt@i915_selftest@live@gt_engines:
- {bat-rpls-1}:   [INCOMPLETE][12] ([i915#6503]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12136/bat-rpls-1/igt@i915_selftest@live@gt_engines.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108576v1/bat-rpls-1/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][14] ([i915#4785]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12136/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108576v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [INCOMPLETE][16] ([i915#5982]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12136/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108576v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: 

Re: [Intel-gfx] [PATCH 1/4] drm/i915/display: Add CDCLK actions to intel_cdclk_state

[Ville Syrjälä]

On Thu, Sep 15, 2022 at 12:22:53AM +0300, Ville Syrjälä wrote:
> On Fri, Aug 19, 2022 at 05:58:19PM -0700, Anusha Srivatsa wrote:
> > This is a prep patch for what the rest of the series does.
> > 
> > Add existing actions that change cdclk - squash, crawl, modeset to
> > intel_cdclk_state so we have access to the cdclk values
> > that are in transition.
> > 
> > Cc: Jani Nikula 
> > Signed-off-by: Anusha Srivatsa 
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.h | 13 +
> >  1 file changed, 13 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h 
> > b/drivers/gpu/drm/i915/display/intel_cdclk.h
> > index b535cf6a7d9e..43835688ee02 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> > @@ -15,6 +15,14 @@ struct drm_i915_private;
> >  struct intel_atomic_state;
> >  struct intel_crtc_state;
> >  
> > +enum cdclk_actions {
> > +   INTEL_CDCLK_MODESET = 0,
> > +   INTEL_CDCLK_SQUASH,
> > +   INTEL_CDCLK_CRAWL,
> > +   INTEL_CDCLK_NOOP,
> > +   MAX_CDCLK_ACTIONS
> > +};
> 
> This whole actions thing feels overly complicated to me.
> I think we should only need something like this:
> 
> if (new.squash > old.squash) {
>   mid.vco = old.vco;
>   mid.squash = new.squash;
> } else {
>   mid.vco = new.vco;
>   mid.squash = old.squash;
> }
> /*
>  * bunch of asserts here to make sure
>  * the mid state looks sane.
>  */
> set_cdclk(mid);
> set_cdclk(new);
> 
> And perhaps the current set_cdclk needs to get chunked up
> into smaller pieces so we don't do all the pre/post stuff
> more than once needlessly.

One idea might be to pass just a pair of flags to set_cdclk()
whether to skip the pre/post steps.

-- 
Ville Syrjälä
Intel

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Revert "drm/i915: Force compilation with intel-iommu for CI validation"

[Patchwork]

== Series Details ==

Series: Revert "drm/i915: Force compilation with intel-iommu for CI validation"
URL   : https://patchwork.freedesktop.org/series/108576/
State : warning

== Summary ==

Error: dim checkpatch failed
e51c64216129 Revert "drm/i915: Force compilation with intel-iommu for CI 
validation"
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#11: 
(https://gitlab.freedesktop.org/gfx-ci/i915-infra/-/blob/master/kconfig/debug),

total: 0 errors, 1 warnings, 0 checks, 14 lines checked

Re: [Intel-gfx] [PATCH 1/4] drm/i915/display: Add CDCLK actions to intel_cdclk_state

[Ville Syrjälä]

On Fri, Aug 19, 2022 at 05:58:19PM -0700, Anusha Srivatsa wrote:
> This is a prep patch for what the rest of the series does.
> 
> Add existing actions that change cdclk - squash, crawl, modeset to
> intel_cdclk_state so we have access to the cdclk values
> that are in transition.
> 
> Cc: Jani Nikula 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.h | 13 +
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h 
> b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index b535cf6a7d9e..43835688ee02 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -15,6 +15,14 @@ struct drm_i915_private;
>  struct intel_atomic_state;
>  struct intel_crtc_state;
>  
> +enum cdclk_actions {
> + INTEL_CDCLK_MODESET = 0,
> + INTEL_CDCLK_SQUASH,
> + INTEL_CDCLK_CRAWL,
> + INTEL_CDCLK_NOOP,
> + MAX_CDCLK_ACTIONS
> +};

This whole actions thing feels overly complicated to me.
I think we should only need something like this:

if (new.squash > old.squash) {
mid.vco = old.vco;
mid.squash = new.squash;
} else {
mid.vco = new.vco;
mid.squash = old.squash;
}
/*
 * bunch of asserts here to make sure
 * the mid state looks sane.
 */
set_cdclk(mid);
set_cdclk(new);

And perhaps the current set_cdclk needs to get chunked up
into smaller pieces so we don't do all the pre/post stuff
more than once needlessly.

> +
>  struct intel_cdclk_config {
>   unsigned int cdclk, vco, ref, bypass;
>   u8 voltage_level;
> @@ -51,6 +59,11 @@ struct intel_cdclk_state {
>  
>   /* bitmask of active pipes */
>   u8 active_pipes;
> +
> + struct cdclk_step {
> + enum cdclk_actions action;
> + u32 cdclk;
> + } steps[MAX_CDCLK_ACTIONS];
>  };
>  
>  int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
> -- 
> 2.25.1

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 02/19] drm/i915/perf: Add OA formats for DG2

[Dixit, Ashutosh]

On Wed, 14 Sep 2022 13:54:34 -0700, Umesh Nerlige Ramappa wrote:
>
> On Tue, Sep 13, 2022 at 08:40:22AM -0700, Dixit, Ashutosh wrote:
> > On Tue, 23 Aug 2022 13:41:38 -0700, Umesh Nerlige Ramappa wrote:
> >>
> >> Add new OA formats for DG2.
> >
> > Should we change the patch title and commit message a bit to 'Add OAR and
> > OAG formats for DG2'?
>
> Hmm, I assumed OAR was also part of TGL, but looks like it's not. I can
> change the title as suggested.

By 'Add OAR and OAG formats for DG2' I meant we are only adding OAR and OAG
formats and not including other DG2 formats ;)

[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "HAX iommu/intel: Ignore igfx_off"

[Patchwork]

== Series Details ==

Series: Revert "HAX iommu/intel: Ignore igfx_off"
URL   : https://patchwork.freedesktop.org/series/108575/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12136 -> Patchwork_108575v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108575v1/index.html

Participating hosts (41 -> 41)
--

  Additional (2): bat-dg2-9 bat-adlp-6 
  Missing(2): fi-ctg-p8600 fi-icl-u2 

Known issues


  Here are the changes found in Patchwork_108575v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][1] -> [DMESG-FAIL][2] ([i915#4528])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12136/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108575v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108575v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][4] ([i915#2867] / [i915#6842]) -> 
[PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12136/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108575v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@gt_engines:
- {bat-rpls-1}:   [INCOMPLETE][6] ([i915#6503]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12136/bat-rpls-1/igt@i915_selftest@live@gt_engines.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108575v1/bat-rpls-1/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][8] ([i915#4785]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12136/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108575v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#6503]: https://gitlab.freedesktop.org/drm/intel/issues/6503
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6641]: https://gitlab.freedesktop.org/drm/intel/issues/6641
  [i915#6842]: https://gitlab.freedesktop.org/drm/intel/issues/6842


Build changes
-

  * Linux: CI_DRM_12136 -> Patchwork_108575v1

  CI-20190529: 20190529
  CI_DRM_12136: 37b0cd34584fab54ae910bffd0f148c8ceb2a9c7 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6656: 24100c4e181c50e3678aeca9c641b8a43555ad73 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_108575v1: 37b0cd34584fab54ae910bffd0f148c8ceb2a9c7 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

cd4eef1e096b Revert "HAX iommu/intel: Ignore igfx_off"

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108575v1/index.html

Re: [Intel-gfx] [PATCH 02/19] drm/i915/perf: Add OA formats for DG2

[Umesh Nerlige Ramappa]

On Tue, Sep 13, 2022 at 08:40:22AM -0700, Dixit, Ashutosh wrote:

On Tue, 23 Aug 2022 13:41:38 -0700, Umesh Nerlige Ramappa wrote:


Add new OA formats for DG2.


Should we change the patch title and commit message a bit to 'Add OAR and
OAG formats for DG2'?


Hmm, I assumed OAR was also part of TGL, but looks like it's not. I can 
change the title as suggested.





Some of the newer OA formats are not
multples of 64 bytes and are not powers of 2. For those formats, adjust
hw_tail accordingly when checking for new reports.

Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/i915_perf.c | 63 
 include/uapi/drm/i915_drm.h  |  6 +++
 2 files changed, 46 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 735244a3aedd..c8331b549d31 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -306,7 +306,8 @@ static u32 i915_oa_max_sample_rate = 10;

 /* XXX: beware if future OA HW adds new report formats that the current
  * code assumes all reports have a power-of-two size and ~(size - 1) can
- * be used as a mask to align the OA tail pointer.
+ * be used as a mask to align the OA tail pointer. In some of the
+ * formats, R is used to denote reserved field.
  */
 static const struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = {
[I915_OA_FORMAT_A13]= { 0, 64 },
@@ -320,6 +321,10 @@ static const struct i915_oa_format 
oa_formats[I915_OA_FORMAT_MAX] = {
[I915_OA_FORMAT_A12]= { 0, 64 },
[I915_OA_FORMAT_A12_B8_C8]  = { 2, 128 },
[I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
+   [I915_OAR_FORMAT_A32u40_A4u32_B8_C8]= { 5, 256 },
+   [I915_OA_FORMAT_A24u40_A14u32_B8_C8]= { 5, 256 },
+   [I915_OAR_FORMAT_A36u64_B8_C8]  = { 1, 384 },
+   [I915_OA_FORMAT_A38u64_R2u64_B8_C8] = { 1, 448 },


Isn't the size for this last one 416 (or 400)? Bspec: 52198. Unless the
size has to be a multiple of 64?


Format size is multiple of 64 bytes, so it is rounded up.



Looks like Lionel's R-b is not showing up on Patchwork, might need to be
manually added. For now this is:

Acked-by: Ashutosh Dixit 


Thanks,
Umesh

[Intel-gfx] [PATCH] Revert "drm/i915: Force compilation with intel-iommu for CI validation"

[Lucas De Marchi]

This reverts commit 9e54866e25e7919ab9704a7680bd8df0c9ee9cdd.

To be removed from topic/core-for-CI branch. If I got the location right
for the CI config
(https://gitlab.freedesktop.org/gfx-ci/i915-infra/-/blob/master/kconfig/debug),
it should be safe to remove this as it already has
CONFIG_INTEL_IOMMU_DEFAULT_ON=y. And if it's somewhere else and my
premise is false, we will know from the CI execution of this patch.

Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/Kconfig.debug | 8 
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.debug 
b/drivers/gpu/drm/i915/Kconfig.debug
index e7fd3e76f8a2..93dfb7ed9705 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -21,14 +21,6 @@ config DRM_I915_DEBUG
depends on DRM_I915
depends on EXPERT # only for developers
depends on !COMPILE_TEST # never built by robots
-   select PCI_MSI # ... for iommu enabled by default
-   select IOMMU_API
-   select IOMMU_IOVA
-   select IOMMU_SUPPORT
-   select NEED_DMA_MAP_STATE
-   select DMAR_TABLE
-   select INTEL_IOMMU
-   select INTEL_IOMMU_DEFAULT_ON
select DEBUG_FS
select PREEMPT_COUNT
select I2C_CHARDEV
-- 
2.37.3

Re: [Intel-gfx] [PATCH 11/19] drm/i915/perf: Store a pointer to oa_format in oa_buffer

[Dixit, Ashutosh]

On Tue, 23 Aug 2022 13:41:47 -0700, Umesh Nerlige Ramappa wrote:
>
> @@ -3184,15 +3184,12 @@ static int i915_oa_stream_init(struct 
> i915_perf_stream *stream,
>   stream->sample_flags = props->sample_flags;
>   stream->sample_size += format_size;
>
> - stream->oa_buffer.format_size = format_size;
> - if (drm_WARN_ON(>drm, stream->oa_buffer.format_size == 0))
> + stream->oa_buffer.format = >oa_formats[props->oa_format];
> + if (drm_WARN_ON(>drm, stream->oa_buffer.format->size == 0))
>   return -EINVAL;

I would also move these 3 lines before the two lines on the top, eliminate
the format_size variable and assignment and just use
stream->oa_buffer.format->size. Otherwise:

Reviewed-by: Ashutosh Dixit 

>   stream->hold_preemption = props->hold_preemption;
>
> - stream->oa_buffer.format =
> - perf->oa_formats[props->oa_format].format;
> -
>   stream->periodic = props->oa_periodic;
>   if (stream->periodic)
>   stream->period_exponent = props->oa_period_exponent;
> diff --git a/drivers/gpu/drm/i915/i915_perf_types.h 
> b/drivers/gpu/drm/i915/i915_perf_types.h
> index dc9bfd8086cf..e0c96b44eda8 100644
> --- a/drivers/gpu/drm/i915/i915_perf_types.h
> +++ b/drivers/gpu/drm/i915/i915_perf_types.h
> @@ -250,11 +250,10 @@ struct i915_perf_stream {
>* @oa_buffer: State of the OA buffer.
>*/
>   struct {
> + const struct i915_oa_format *format;
>   struct i915_vma *vma;
>   u8 *vaddr;
>   u32 last_ctx_id;
> - int format;
> - int format_size;
>   int size_exponent;
>

[Intel-gfx] [PATCH] Revert "HAX iommu/intel: Ignore igfx_off"

[Lucas De Marchi]

This reverts commit 58f44e349cfc10a4f2208fd806829c8fd046480b.

To be removed from the topic/core-for-CI branch. If CI's config is
setting that, it just shouldn't do it. Looking at a random current CI
execution, the command line is:

Command line: BOOT_IMAGE=/boot/drm_intel root=/dev/nvme0n1p2 \
rootwait fsck.repair=yes nmi_watchdog=panic,auto panic=5 \
softdog.soft_panic=5 drm.debug=0xe log_buf_len=1M trace_clock=global 3 \
modprobe.blacklist=i915,snd_hda_intel ro

So it should be safe to remove this commit.

Signed-off-by: Lucas De Marchi 
---
 drivers/iommu/intel/iommu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 598c9b86dfd8..1f2cd43cf9bc 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -323,6 +323,8 @@ static int __init intel_iommu_setup(char *str)
no_platform_optin = 1;
pr_info("IOMMU disabled\n");
} else if (!strncmp(str, "igfx_off", 8)) {
+   dmar_map_gfx = 0;
+   pr_info("Disable GFX device mapping\n");
} else if (!strncmp(str, "forcedac", 8)) {
pr_warn("intel_iommu=forcedac deprecated; use 
iommu.forcedac instead\n");
iommu_dma_forcedac = true;
-- 
2.37.3

Re: [Intel-gfx] [PATCH 2/4] drm/i915/squash: s/intel_cdclk_can_squash/intel_cdclk_squash

[Navare, Manasi]

On Fri, Aug 19, 2022 at 05:58:20PM -0700, Anusha Srivatsa wrote:
> Apart from checking if squashing can be performed,
> accommodate accessing in-flight cdclk state for any changes
> that are needed during commit phase.
> 
> v2: Move squashing bits to switch case.(Anusha)
> 
> Cc: Jani Nikula 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 62 ++
>  1 file changed, 40 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 86a22c3766e5..f98fd48fe905 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1693,12 +1693,18 @@ static void bxt_set_cdclk(struct drm_i915_private 
> *dev_priv,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
>  {
> + struct intel_cdclk_state *cdclk_state = 
> to_intel_cdclk_state(dev_priv->cdclk.obj.state);
> + struct intel_atomic_state *state = cdclk_state->base.state;
> + struct intel_cdclk_state *new_cdclk_state = 
> intel_atomic_get_new_cdclk_state(state);

This will not work, make cdclk steps as part of cdlck_config struct and
access that through the passed cdclk_config

This already gets passed from the calling function intel_set_cdclk()
which is getting called from intel_set_cdclk_post_plane_update() from
commit_tail()
This is the correct way of programming req HW registers from cdclk state



Manasi

> + struct cdclk_step *cdclk_steps = new_cdclk_state->steps;
>   int cdclk = cdclk_config->cdclk;
>   int vco = cdclk_config->vco;
> + u32 squash_ctl = 0;
>   u32 val;
>   u16 waveform;
>   int clock;
>   int ret;
> + int i;
>  
>   /* Inform power controller of upcoming frequency change. */
>   if (DISPLAY_VER(dev_priv) >= 11)
> @@ -1742,21 +1748,27 @@ static void bxt_set_cdclk(struct drm_i915_private 
> *dev_priv,
>  
>   waveform = cdclk_squash_waveform(dev_priv, cdclk);
>  
> - if (waveform)
> + if (waveform && has_cdclk_squasher(dev_priv)) {
>   clock = vco / 2;
> - else
> + for (i = 0; i < MAX_CDCLK_ACTIONS; i++) {
> + switch (cdclk_steps[i].action) {
> + case INTEL_CDCLK_SQUASH:
> + waveform =  cdclk_squash_waveform(dev_priv, 
> cdclk_steps[i].cdclk);
> + squash_ctl = CDCLK_SQUASH_ENABLE |
> +  CDCLK_SQUASH_WINDOW_SIZE(0xf) | 
> waveform;
> + intel_de_write(dev_priv, CDCLK_SQUASH_CTL, 
> squash_ctl);
> + break;
> + case INTEL_CDCLK_NOOP:
> + case INTEL_CDCLK_CRAWL:
> + case INTEL_CDCLK_MODESET:
> + break;
> + default:
> + break;
> + }
> + }
> + } else
>   clock = cdclk;
>  
> - if (has_cdclk_squasher(dev_priv)) {
> - u32 squash_ctl = 0;
> -
> - if (waveform)
> - squash_ctl = CDCLK_SQUASH_ENABLE |
> - CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> -
> - intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
> - }
> -
>   val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
>   bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
>   skl_cdclk_decimal(cdclk);
> @@ -1966,10 +1978,11 @@ static bool intel_cdclk_can_crawl(struct 
> drm_i915_private *dev_priv,
>   a->ref == b->ref;
>  }
>  
> -static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
> -const struct intel_cdclk_config *a,
> -const struct intel_cdclk_config *b)
> +static bool intel_cdclk_squash(struct drm_i915_private *dev_priv,
> +const struct intel_cdclk_state *a,
> +struct intel_cdclk_state *b)
>  {
> + struct cdclk_step *cdclk_transition = b->steps;
>   /*
>* FIXME should store a bit more state in intel_cdclk_config
>* to differentiate squasher vs. cd2x divider properly. For
> @@ -1978,11 +1991,16 @@ static bool intel_cdclk_can_squash(struct 
> drm_i915_private *dev_priv,
>*/
>   if (!has_cdclk_squasher(dev_priv))
>   return false;
> + 
> + cdclk_transition[0].action = INTEL_CDCLK_SQUASH;
> + cdclk_transition[0].cdclk = b->actual.cdclk;
> + cdclk_transition[1].action = INTEL_CDCLK_NOOP;
> + cdclk_transition[1].cdclk = b->actual.cdclk;
>  
> - return a->cdclk != b->cdclk &&
> - a->vco != 0 &&
> - a->vco == b->vco &&
> - a->ref == b->ref;
> + return a->actual.cdclk != b->actual.cdclk &&
> + a->actual.vco != 0 

Re: [Intel-gfx] [PATCH 1/4] drm/i915/display: Add CDCLK actions to intel_cdclk_state

[Navare, Manasi]

On Fri, Aug 19, 2022 at 05:58:19PM -0700, Anusha Srivatsa wrote:
> This is a prep patch for what the rest of the series does.
> 
> Add existing actions that change cdclk - squash, crawl, modeset to
> intel_cdclk_state so we have access to the cdclk values
> that are in transition.
> 
> Cc: Jani Nikula 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.h | 13 +
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h 
> b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index b535cf6a7d9e..43835688ee02 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -15,6 +15,14 @@ struct drm_i915_private;
>  struct intel_atomic_state;
>  struct intel_crtc_state;
>  
> +enum cdclk_actions {
> + INTEL_CDCLK_MODESET = 0,
> + INTEL_CDCLK_SQUASH,
> + INTEL_CDCLK_CRAWL,
> + INTEL_CDCLK_NOOP,
> + MAX_CDCLK_ACTIONS
> +};
> +
>  struct intel_cdclk_config {
>   unsigned int cdclk, vco, ref, bypass;
>   u8 voltage_level;
> @@ -51,6 +59,11 @@ struct intel_cdclk_state {
>  
>   /* bitmask of active pipes */
>   u8 active_pipes;
> +
> + struct cdclk_step {
> + enum cdclk_actions action;
> + u32 cdclk;
> + } steps[MAX_CDCLK_ACTIONS];

If this is what you need to access later in bxt_set_cdclk , you needto
add this to intel_cdclk_config which is then part of cdclk_state and
that is what will get programmed in atomic_check and it gets sent to
bxt_set_cdclk in atomic_commit_tail.

This is the way ypu can access it in bxt_set_cdclk, you cannot access
the new_cdclk_state there, you need to use cdclk_config that is already
getting passed to it

Manasi

>  };
>  
>  int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
> -- 
> 2.25.1
> 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: move i915_fence_{context_, }timeout() to i915_sw_fence.[ch]

[Patchwork]

== Series Details ==

Series: drm/i915: move i915_fence_{context_, }timeout() to i915_sw_fence.[ch]
URL   : https://patchwork.freedesktop.org/series/108571/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12136 -> Patchwork_108571v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108571v1/index.html

Participating hosts (41 -> 41)
--

  Additional (2): bat-dg2-9 bat-adlp-6 
  Missing(2): fi-ctg-p8600 fi-icl-u2 

Known issues


  Here are the changes found in Patchwork_108571v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][1] -> [DMESG-FAIL][2] ([i915#4528])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12136/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108571v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108571v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][4] ([i915#2867] / [i915#6842]) -> 
[PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12136/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108571v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@gt_engines:
- {bat-rpls-1}:   [INCOMPLETE][6] ([i915#6503]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12136/bat-rpls-1/igt@i915_selftest@live@gt_engines.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108571v1/bat-rpls-1/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][8] ([i915#4785]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12136/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108571v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6503]: https://gitlab.freedesktop.org/drm/intel/issues/6503
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6641]: https://gitlab.freedesktop.org/drm/intel/issues/6641
  [i915#6842]: https://gitlab.freedesktop.org/drm/intel/issues/6842


Build changes
-

  * Linux: CI_DRM_12136 -> Patchwork_108571v1

  CI-20190529: 20190529
  CI_DRM_12136: 37b0cd34584fab54ae910bffd0f148c8ceb2a9c7 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6656: 24100c4e181c50e3678aeca9c641b8a43555ad73 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_108571v1: 37b0cd34584fab54ae910bffd0f148c8ceb2a9c7 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

6415442e1eed drm/i915: move i915_fence_{context_, }timeout() to 
i915_sw_fence.[ch]

== 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: move i915_fence_{context_, }timeout() to i915_sw_fence.[ch]

[Patchwork]

== Series Details ==

Series: drm/i915: move i915_fence_{context_, }timeout() to i915_sw_fence.[ch]
URL   : https://patchwork.freedesktop.org/series/108571/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: move i915_fence_{context_, }timeout() to i915_sw_fence.[ch]

[Patchwork]

== Series Details ==

Series: drm/i915: move i915_fence_{context_, }timeout() to i915_sw_fence.[ch]
URL   : https://patchwork.freedesktop.org/series/108571/
State : warning

== Summary ==

Error: dim checkpatch failed
2e046376e4d1 drm/i915: move i915_fence_{context_, }timeout() to 
i915_sw_fence.[ch]
-:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#30: 
deleted file mode 100644

total: 0 errors, 1 warnings, 0 checks, 66 lines checked

Re: [Intel-gfx] [PATCH 06/19] drm/i915/perf: Use helpers to process reports w.r.t. OA buffer size

[Dixit, Ashutosh]

On Wed, 14 Sep 2022 11:19:30 -0700, Umesh Nerlige Ramappa wrote:
>
> On Wed, Sep 14, 2022 at 09:04:10AM -0700, Dixit, Ashutosh wrote:
> > On Tue, 23 Aug 2022 13:41:42 -0700, Umesh Nerlige Ramappa wrote:
> >>
> >
> > Hi Umesh,
> >
> >> diff --git a/drivers/gpu/drm/i915/i915_perf.c 
> >> b/drivers/gpu/drm/i915/i915_perf.c
> >> index 6fc4f0d8fc5a..bbf1c574f393 100644
> >> --- a/drivers/gpu/drm/i915/i915_perf.c
> >> +++ b/drivers/gpu/drm/i915/i915_perf.c
> >> @@ -385,6 +385,21 @@ static struct ctl_table_header *sysctl_header;
> >>
> >>  static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer 
> >> *hrtimer);
> >>
> >> +static u32 _oa_taken(struct i915_perf_stream * stream, u32 tail, u32 head)
> >
> > nit: no space between * and stream.
> >
> >> +{
> >> +  u32 size = stream->oa_buffer.vma->size;
> >> +
> >> +  return tail >= head ? tail - head : size - (head - tail);
> >> +}
> >
> > If we are doing this we should probably eliminate references to OA_TAKEN
> > which serves an identical purpose (I think there is one remaining
> > reference) and also delete OA_TAKEN #define.
> >
> >> +
> >> +static u32 _rewind_tail(struct i915_perf_stream * stream, u32 
> >> relative_hw_tail,
> >> +  u32 rewind_delta)
> >> +{
> >> +  return rewind_delta > relative_hw_tail ?
> >> + stream->oa_buffer.vma->size - (rewind_delta - relative_hw_tail) :
> >> + relative_hw_tail - rewind_delta;
> >> +}
> >
> > Also are we really saying here that we are supporting non-power-of-2 OA
> > buffer sizes? Because if we stayed with power-of-2 sizes the expression
> > above are nice and elegant and actually closer to the previous code being
> > changed in this patch. For example:
> >
> > #include 
> >
> > static u32 _oa_taken(struct i915_perf_stream *stream, u32 tail, u32 head)
> > {
> > return CIRC_CNT(tail, head, stream->oa_buffer.vma->size);
> > }
> >
> > static u32 _rewind_tail(struct i915_perf_stream *stream, u32 
> > relative_hw_tail,
> > u32 rewind_delta)
> > {
> > return CIRC_CNT(relative_hw_tail, rewind_delta, 
> > stream->oa_buffer.vma->size);
> > }
> >
> > Note that for power-of-2 sizes the two functions above are identical but we
> > should keep them separate for clarity (as is done in the patch) since they
> > are serving two different functions in the OA code.
> >
> > Also another assumption in the code seems to be:
> >
> > stream->oa_buffer.vma->size == OA_BUFFER_SIZE
> >
> > which I am pretty sure will not hold for arbitrary non-power-of-2 OA buffer
> > sizes? So we might as well stick with power-of-2 sizes and change later in
> > a separate patch only if needed?
>
> Most changes here are related to the OA buffer size issue and that is
> specific to xehpsdv where the size is not a power of 2. I am thinking of
> dropping these changes in the next revision since DG2 is fixed and OA
> buffer sizes are power of 2.

In the code stream->oa_buffer.vma->size and OA_BUFFER_SIZE are both used,
if we want to clean that up and only use stream->oa_buffer.vma->size, we
could still do soemthing like I suggested with just power-of-2 sizes and
keep this patch. If we ever have to support non-power-of-2 sizes in the
future we'll just need to change _oa_taken and _rewind_tail
functions. Anyway your call.

Thanks.
--
Ashutosh

Re: [Intel-gfx] [PATCH 09/19] drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops

[Dixit, Ashutosh]

On Tue, 23 Aug 2022 13:41:45 -0700, Umesh Nerlige Ramappa wrote:
>
> With multi-gt, user can access multiple OA buffers concurrently. Use
> stream->lock instead of gt->perf.lock to serialize file operations.

Ok, will come in handy for multiple streams per gt:

Reviewed-by: Ashutosh Dixit 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: move i915_coherent_map_type() to i915_gem_pages.c and un-inline

[Patchwork]

== Series Details ==

Series: drm/i915: move i915_coherent_map_type() to i915_gem_pages.c and 
un-inline
URL   : https://patchwork.freedesktop.org/series/108569/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12135 -> Patchwork_108569v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108569v1/index.html

Participating hosts (44 -> 41)
--

  Missing(3): fi-ctg-p8600 bat-dg2-11 bat-jsl-3 

Known issues


  Here are the changes found in Patchwork_108569v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [PASS][1] -> [INCOMPLETE][2] ([i915#3303] / 
[i915#4785])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12135/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108569v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][3] -> [DMESG-FAIL][4] ([i915#4528])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12135/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108569v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html
- fi-blb-e6850:   [PASS][5] -> [DMESG-FAIL][6] ([i915#4528])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12135/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108569v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108569v1/fi-pnv-d510/igt@run...@aborted.html
- fi-hsw-g3258:   NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#4312] / 
[i915#6246])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108569v1/fi-hsw-g3258/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}:   [DMESG-WARN][9] ([i915#2867] / [i915#6842]) -> 
[PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12135/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108569v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@reset:
- {bat-adln-1}:   [DMESG-FAIL][11] ([i915#4983]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12135/bat-adln-1/igt@i915_selftest@l...@reset.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108569v1/bat-adln-1/igt@i915_selftest@l...@reset.html

  * igt@i915_selftest@live@slpc:
- {bat-rpls-1}:   [DMESG-FAIL][13] ([i915#6367]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12135/bat-rpls-1/igt@i915_selftest@l...@slpc.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108569v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6246]: https://gitlab.freedesktop.org/drm/intel/issues/6246
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6842]: https://gitlab.freedesktop.org/drm/intel/issues/6842


Build changes
-

  * Linux: CI_DRM_12135 -> Patchwork_108569v1

  CI-20190529: 20190529
  CI_DRM_12135: 9ba4c45313414a567e0b4a6d5f5c3dc27d86592e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6656: 24100c4e181c50e3678aeca9c641b8a43555ad73 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_108569v1: 9ba4c45313414a567e0b4a6d5f5c3dc27d86592e @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

08030c53454c drm/i915: move i915_coherent_map_type() to i915_gem_pages.c and 
un-inline

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108569v1/index.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: move i915_coherent_map_type() to i915_gem_pages.c and un-inline

[Patchwork]

== Series Details ==

Series: drm/i915: move i915_coherent_map_type() to i915_gem_pages.c and 
un-inline
URL   : https://patchwork.freedesktop.org/series/108569/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BAT: failure for Update to version reduced firmware file names

[Patchwork]

== Series Details ==

Series: Update to version reduced firmware file names
URL   : https://patchwork.freedesktop.org/series/108568/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12135 -> Patchwork_108568v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_108568v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_108568v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108568v1/index.html

Participating hosts (44 -> 41)
--

  Missing(3): fi-ctg-p8600 bat-dg2-11 bat-jsl-3 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_108568v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@mman:
- fi-rkl-guc: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12135/fi-rkl-guc/igt@i915_selftest@l...@mman.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108568v1/fi-rkl-guc/igt@i915_selftest@l...@mman.html

  
Known issues


  Here are the changes found in Patchwork_108568v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][3] -> [INCOMPLETE][4] ([i915#4785])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12135/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108568v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][5] -> [DMESG-FAIL][6] ([i915#4528])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12135/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108568v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html
- fi-blb-e6850:   [PASS][7] -> [DMESG-FAIL][8] ([i915#4528])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12135/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108568v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108568v1/fi-pnv-d510/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}:   [DMESG-WARN][10] ([i915#2867] / [i915#6842]) -> 
[PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12135/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108568v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-5:  [DMESG-FAIL][12] ([i915#4494] / [i915#4957]) -> 
[PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12135/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108568v1/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@reset:
- {bat-adln-1}:   [DMESG-FAIL][14] ([i915#4983]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12135/bat-adln-1/igt@i915_selftest@l...@reset.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108568v1/bat-adln-1/igt@i915_selftest@l...@reset.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
  [i915#6380]: https://gitlab.freedesktop.org/drm/intel/issues/6380
  [i915#6842]: https://gitlab.freedesktop.org/drm/intel/issues/6842


Build changes
-

  * Linux: CI_DRM_12135 -> Patchwork_108568v1

  CI-20190529: 20190529
  CI_DRM_12135: 9ba4c45313414a567e0b4a6d5f5c3dc27d86592e @ 

Re: [Intel-gfx] [PATCH 08/19] drm/i915/perf: Move gt-specific data from i915->perf to gt->perf

[Dixit, Ashutosh]

On Tue, 23 Aug 2022 13:41:44 -0700, Umesh Nerlige Ramappa wrote:
>
> Make perf part of gt as the OAG buffer is specific to a gt. The refactor
> eventually simplifies programming the right OA buffer and the right HW
> registers when supporting multiple gts.

Reviewed-by: Ashutosh Dixit 

Re: [Intel-gfx] [PATCH 06/19] drm/i915/perf: Use helpers to process reports w.r.t. OA buffer size

[Umesh Nerlige Ramappa]

On Wed, Sep 14, 2022 at 09:04:10AM -0700, Dixit, Ashutosh wrote:

On Tue, 23 Aug 2022 13:41:42 -0700, Umesh Nerlige Ramappa wrote:




Hi Umesh,


diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 6fc4f0d8fc5a..bbf1c574f393 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -385,6 +385,21 @@ static struct ctl_table_header *sysctl_header;

 static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);

+static u32 _oa_taken(struct i915_perf_stream * stream, u32 tail, u32 head)


nit: no space between * and stream.


+{
+   u32 size = stream->oa_buffer.vma->size;
+
+   return tail >= head ? tail - head : size - (head - tail);
+}


If we are doing this we should probably eliminate references to OA_TAKEN
which serves an identical purpose (I think there is one remaining
reference) and also delete OA_TAKEN #define.


+
+static u32 _rewind_tail(struct i915_perf_stream * stream, u32 relative_hw_tail,
+   u32 rewind_delta)
+{
+   return rewind_delta > relative_hw_tail ?
+  stream->oa_buffer.vma->size - (rewind_delta - relative_hw_tail) :
+  relative_hw_tail - rewind_delta;
+}


Also are we really saying here that we are supporting non-power-of-2 OA
buffer sizes? Because if we stayed with power-of-2 sizes the expression
above are nice and elegant and actually closer to the previous code being
changed in this patch. For example:

#include 

static u32 _oa_taken(struct i915_perf_stream *stream, u32 tail, u32 head)
{
return CIRC_CNT(tail, head, stream->oa_buffer.vma->size);
}

static u32 _rewind_tail(struct i915_perf_stream *stream, u32 relative_hw_tail,
u32 rewind_delta)
{
return CIRC_CNT(relative_hw_tail, rewind_delta, 
stream->oa_buffer.vma->size);
}

Note that for power-of-2 sizes the two functions above are identical but we
should keep them separate for clarity (as is done in the patch) since they
are serving two different functions in the OA code.

Also another assumption in the code seems to be:

stream->oa_buffer.vma->size == OA_BUFFER_SIZE

which I am pretty sure will not hold for arbitrary non-power-of-2 OA buffer
sizes? So we might as well stick with power-of-2 sizes and change later in
a separate patch only if needed?


Most changes here are related to the OA buffer size issue and that is 
specific to xehpsdv where the size is not a power of 2. I am thinking of 
dropping these changes in the next revision since DG2 is fixed and OA 
buffer sizes are power of 2.


Thanks,
Umesh



Thanks.
--
Ashutosh

Re: [Intel-gfx] [PATCH v5 00/15] drm/i915: HuC loading for DG2

[Greg Kroah-Hartman]

On Wed, Sep 14, 2022 at 04:51:03PM +, Winkler, Tomas wrote:
> > 
> > On DG2, HuC loading is performed by the GSC, via a PXP command. The load
> > operation itself is relatively simple (just send a message to the GSC with 
> > the
> > physical address of the HuC in LMEM), but there are timing changes that
> > requires special attention. In particular, to send a PXP command we need to
> > first export the GSC as an aux device and then wait for the mei-gsc and mei-
> > pxp modules to start, which means that HuC load will complete after i915
> > load is complete. This means that there is a small window of time after 
> > i915 is
> > registered and before HuC is loaded during which userspace could submit
> > and/or check the HuC load status, although this is quite unlikely to happen
> > (HuC is usually loaded before kernel init/resume completes).
> > We've consulted with the media team in regards to how to handle this and
> > they've asked us to stall all userspace VCS submission until HuC is loaded.
> > Stalls are expected to be very rare (if any), due to the fact that HuC is 
> > usually
> > loaded before kernel init/resume is completed.
> > 
> > Timeouts are in place to ensure all submissions are unlocked in case
> > something goes wrong. Since we need to monitor the status of the mei
> > driver to know what's happening and when to time out, a notifier has been
> > added so we get a callback when the status of the mei driver changes.
> > 
> > Note that this series includes several mei patches that add support for
> > sending the HuC loading command via mei-gsc. We plan to merge those
> > patches through the drm tree because i915 is the sole user.
> > 
> > v2: address review comments, Reporting HuC loading still in progress while
> > we wait for mei-gsc init to complete, rebase on latest mei-gsc series.
> > 
> > v3: fix cc list in mei patches.
> > 
> > v4: update mei patches, fix includes, rebase on new FW fetch logic and
> > merged mei-gsc support.
> > 
> > v5: update mei patches
> 
> Greg,  I hope I've addressed most of your comments.
> Can you please check if the mei patches are in acceptable state or anything 
> else can be improved with this series.  Appreciated. 

These were sent 2 days ago, in the middle of a conference travel.
Please relax, there's no special rush needed here, you know better.

In the mean time, if you are just waiting for my review, please take the
time to review other pending patches from other developers to help
lighten the load on me, and other maintainers.

thanks,

greg k-h

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gem: Really move i915_gem_context.link under ref protection

[Andi Shyti]

Hi,

[...]

> > struct i915_address_space *vm;
> > +   unsigned long flags;
> > trace_i915_context_free(ctx);
> > GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
> > +   spin_lock_irqsave(>i915->gem.contexts.lock, flags);
> 
> Why irqsave and the conversion to irq safe elsewhere? Worker context does
> not require it and I don't see the connection to the change of list_del
> location.

yah! I think there is no reason, this is just inherited from
other code.

Andi

> Regards,
> 
> Tvrtko
> 
> > +   list_del(>link);
> > +   spin_unlock_irqrestore(>i915->gem.contexts.lock, flags);
> > +
> > if (ctx->syncobj)
> > drm_syncobj_put(ctx->syncobj);

...

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915/uc: Fix issues with overriding firmware files

[Ceraolo Spurio, Daniele]

On 9/13/2022 5:58 PM, john.c.harri...@intel.com wrote:

From: John Harrison 

The earlier update to support reduced versioning of firmware files
introduced an issue with the firmware override module parameter. If an
invalid file was specified then an infinite loop could occur trying to
find a backup firmware.

The fix is that if an explicit override has been set, then don't scan
for backup options because there is no point anyway. The user wanted X
and if X is not available, that's their problem.

This patch also fixes up the scanning loop code so that if an invalid
file is passed in, it will exit rather than loop forever. So if the
impossible situation did somehow occur in the future, it wouldn't be
such a big problem.

v2: Also remove ANSI colour codes that accidentally got left in an
error message in the original patch.


With the commit message updated to include what you mentioned in your 
reply, this is:


Reviewed-by: Daniele Ceraolo Spurio 

Daniele



Fixes: 665ae9c9ca79 ("drm/i915/uc: Support for version reduced and multiple
firmware files")
Cc: Daniele Ceraolo Spurio 
Cc: Jani Nikula 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
Cc: Tvrtko Ursulin 
Cc: Matthew Brost 
Cc: Umesh Nerlige Ramappa 
Cc: Matthew Auld 
Cc: Alan Previn 
Cc: Matt Roper 
Cc: Lucas De Marchi 
Cc: Vinay Belgaumkar 
Cc: "Thomas Hellström" 
Cc: Venkata Sandeep Dhanalakota 
Signed-off-by: John Harrison 
---
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 20 +++-
  1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index af425916cdf64..1169e2a09da24 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -232,6 +232,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct 
intel_uc_fw *uc_fw)
u32 fw_count;
u8 rev = INTEL_REVID(i915);
int i;
+   bool found;
  
  	/*

 * The only difference between the ADL GuC FWs is the HWConfig support.
@@ -246,6 +247,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct 
intel_uc_fw *uc_fw)
fw_blobs = blobs_all[uc_fw->type].blobs;
fw_count = blobs_all[uc_fw->type].count;
  
+	found = false;

for (i = 0; i < fw_count && p <= fw_blobs[i].p; i++) {
const struct uc_fw_blob *blob = _blobs[i].blob;
  
@@ -266,9 +268,15 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw)

uc_fw->file_wanted.path = blob->path;
uc_fw->file_wanted.major_ver = blob->major;
uc_fw->file_wanted.minor_ver = blob->minor;
+   found = true;
break;
}
  
+	if (!found && uc_fw->file_selected.path) {

+   /* Failed to find a match for the last attempt?! */
+   uc_fw->file_selected.path = NULL;
+   }
+
/* make sure the list is ordered as expected */
if (IS_ENABLED(CONFIG_DRM_I915_SELFTEST) && !verified) {
verified = true;
@@ -322,7 +330,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct 
intel_uc_fw *uc_fw)
continue;
  
  bad:

-   drm_err(>drm, "\x1B[35;1mInvalid FW blob order: %s r%u 
%s%d.%d.%d comes before %s r%u %s%d.%d.%d\n",
+   drm_err(>drm, "Invalid FW blob order: %s r%u 
%s%d.%d.%d comes before %s r%u %s%d.%d.%d\n",
intel_platform_name(fw_blobs[i - 1].p), 
fw_blobs[i - 1].rev,
fw_blobs[i - 1].blob.legacy ? "L" : "v",
fw_blobs[i - 1].blob.major,
@@ -553,10 +561,14 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
  
  	err = firmware_request_nowarn(, uc_fw->file_selected.path, dev);

memcpy(_ideal, _fw->file_wanted, sizeof(file_ideal));
-   if (!err || intel_uc_fw_is_overridden(uc_fw))
-   goto done;
+
+   /* Any error is terminal if overriding. Don't bother searching for 
older versions */
+   if (err && intel_uc_fw_is_overridden(uc_fw))
+   goto fail;
  
  	while (err == -ENOENT) {

+   old_ver = true;
+
__uc_fw_auto_select(i915, uc_fw);
if (!uc_fw->file_selected.path) {
/*
@@ -576,8 +588,6 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
if (err)
goto fail;
  
-	old_ver = true;

-done:
if (uc_fw->loaded_via_gsc)
err = check_gsc_manifest(fw, uc_fw);
else

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm (rev3)
URL   : https://patchwork.freedesktop.org/series/108477/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12134 -> Patchwork_108477v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v3/index.html

Participating hosts (40 -> 43)
--

  Additional (5): fi-icl-u2 bat-dg2-9 bat-adln-1 bat-rplp-1 bat-dg2-11 
  Missing(2): fi-ctg-p8600 fi-tgl-dsi 

Known issues


  Here are the changes found in Patchwork_108477v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][1] ([i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v3/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v3/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@i915_pm_rpm@module-reload:
- bat-dg1-5:  [PASS][3] -> [SKIP][4] ([i915#6844]) +2 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/bat-dg1-5/igt@i915_pm_...@module-reload.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v3/bat-dg1-5/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][5] -> [DMESG-FAIL][6] ([i915#4528])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v3/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-bdw-5557u:   NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v3/fi-bdw-5557u/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][8] ([fdo#111827]) +8 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v3/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-icl-u2:  NOTRUN -> [SKIP][9] ([i915#4103])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v3/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-connector-state:
- fi-icl-u2:  NOTRUN -> [WARN][10] ([i915#6008])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v3/fi-icl-u2/igt@kms_force_connector_ba...@force-connector-state.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][11] ([fdo#109285])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v3/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][12] ([i915#3555])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v3/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-icl-u2:  NOTRUN -> [SKIP][13] ([fdo#109295] / [i915#3301])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v3/fi-icl-u2/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@i915_selftest@live@guc:
- {bat-rpls-1}:   [DMESG-WARN][14] ([i915#6471]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/bat-rpls-1/igt@i915_selftest@l...@guc.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v3/bat-rpls-1/igt@i915_selftest@l...@guc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
  

[Intel-gfx] ✗ Fi.CI.IGT: failure for Fix bug in version reduced firmware update (rev2)

[Patchwork]

== Series Details ==

Series: Fix bug in version reduced firmware update (rev2)
URL   : https://patchwork.freedesktop.org/series/108461/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12132_full -> Patchwork_108461v2_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_108461v2_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_108461v2_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_108461v2_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_sseu@full-enable:
- shard-apl:  NOTRUN -> [FAIL][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v2/shard-apl4/igt@i915_pm_s...@full-enable.html

  
Known issues


  Here are the changes found in Patchwork_108461v2_full that come from known 
issues:

### CI changes ###

 Possible fixes 

  * boot:
- shard-apl:  ([FAIL][2], [PASS][3], [PASS][4], [PASS][5], 
[PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], 
[PASS][25], [PASS][26]) ([i915#4386]) -> ([PASS][27], [PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], 
[PASS][48], [PASS][49], [PASS][50], [PASS][51])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl3/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl3/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl3/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl4/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl7/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl7/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl7/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl8/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl8/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl8/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v2/shard-apl1/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v2/shard-apl1/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v2/shard-apl1/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v2/shard-apl1/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v2/shard-apl2/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v2/shard-apl2/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v2/shard-apl2/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v2/shard-apl3/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v2/shard-apl3/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108461v2/shard-apl3/boot.html

[Intel-gfx] [PATCH] drm/i915: move i915_fence_{context_, }timeout() to i915_sw_fence.[ch]

[Jani Nikula]

Maybe there was a grand plan with i915_fence_timeout() and
i915_fence_context_timeout() and i915_config.c, but that seems to have
been lost a bit.

Just move the functions to i915_sw_fence.[ch] from i915_drv.h and
i915_config.c, and remove the latter.

Cc: Tvrtko Ursulin 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/Makefile|  1 -
 drivers/gpu/drm/i915/i915_config.c   | 15 ---
 drivers/gpu/drm/i915/i915_drv.h  |  9 -
 drivers/gpu/drm/i915/i915_sw_fence.c | 15 +++
 drivers/gpu/drm/i915/i915_sw_fence.h |  5 +
 5 files changed, 20 insertions(+), 25 deletions(-)
 delete mode 100644 drivers/gpu/drm/i915/i915_config.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a26edcdadc21..0221682d3a0f 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -34,7 +34,6 @@ subdir-ccflags-y += -I$(srctree)/$(src)
 # core driver code
 i915-y += i915_driver.o \
  i915_drm_client.o \
- i915_config.o \
  i915_getparam.o \
  i915_ioctl.o \
  i915_irq.o \
diff --git a/drivers/gpu/drm/i915/i915_config.c 
b/drivers/gpu/drm/i915/i915_config.c
deleted file mode 100644
index afb828dab53b..
--- a/drivers/gpu/drm/i915/i915_config.c
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: MIT
-/*
- * Copyright © 2020 Intel Corporation
- */
-
-#include "i915_drv.h"
-
-unsigned long
-i915_fence_context_timeout(const struct drm_i915_private *i915, u64 context)
-{
-   if (CONFIG_DRM_I915_FENCE_TIMEOUT && context)
-   return msecs_to_jiffies_timeout(CONFIG_DRM_I915_FENCE_TIMEOUT);
-
-   return 0;
-}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 524b5ee495be..02956385d32d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -167,15 +167,6 @@ struct i915_gem_mm {
 
 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
 
-unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
-u64 context);
-
-static inline unsigned long
-i915_fence_timeout(const struct drm_i915_private *i915)
-{
-   return i915_fence_context_timeout(i915, U64_MAX);
-}
-
 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
 
 struct i915_virtual_gpu {
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c 
b/drivers/gpu/drm/i915/i915_sw_fence.c
index 6fc0d1b89690..2a90987799e7 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -11,6 +11,7 @@
 
 #include "i915_sw_fence.h"
 #include "i915_selftest.h"
+#include "i915_utils.h"
 
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
 #define I915_SW_FENCE_BUG_ON(expr) BUG_ON(expr)
@@ -471,6 +472,20 @@ static void irq_i915_sw_fence_work(struct irq_work *wrk)
kfree_rcu(cb, rcu);
 }
 
+unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
+u64 context)
+{
+   if (CONFIG_DRM_I915_FENCE_TIMEOUT && context)
+   return msecs_to_jiffies_timeout(CONFIG_DRM_I915_FENCE_TIMEOUT);
+
+   return 0;
+}
+
+unsigned long i915_fence_timeout(const struct drm_i915_private *i915)
+{
+   return i915_fence_context_timeout(i915, U64_MAX);
+}
+
 int i915_sw_fence_await_dma_fence(struct i915_sw_fence *fence,
  struct dma_fence *dma,
  unsigned long timeout,
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.h 
b/drivers/gpu/drm/i915/i915_sw_fence.h
index 619fc5a22f0c..cdef7dabafbd 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.h
+++ b/drivers/gpu/drm/i915/i915_sw_fence.h
@@ -17,6 +17,7 @@
 
 struct completion;
 struct dma_resv;
+struct drm_i915_private;
 struct i915_sw_fence;
 
 enum i915_sw_fence_notify {
@@ -81,6 +82,10 @@ struct i915_sw_dma_fence_cb {
struct i915_sw_fence *fence;
 };
 
+unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
+u64 context);
+unsigned long i915_fence_timeout(const struct drm_i915_private *i915);
+
 int __i915_sw_fence_await_dma_fence(struct i915_sw_fence *fence,
struct dma_fence *dma,
struct i915_sw_dma_fence_cb *cb);
-- 
2.34.1

Re: [Intel-gfx] [GIT PULL] Immutable backlight-detect-refactor branch between acpi, drm-* and pdx86

[Hans de Goede]

Hi,

On 9/14/22 12:29, Maxime Ripard wrote:
> Hi Hans,
> 
> On Mon, Sep 05, 2022 at 10:35:47AM +0200, Hans de Goede wrote:
>> Hi All,
>>
>> Now that all patches have been reviewed/acked here is an immutable 
>> backlight-detect-refactor
>> branch with 6.0-rc1 + the v5 patch-set, for merging into the relevant (acpi, 
>> drm-* and pdx86)
>> subsystems.
>>
>> Please pull this branch into the relevant subsystems.
>>
>> I will merge this into the review-hans branch of the pdx86 git tree today and
>> from there it will move to for-next once the builders have successfully 
>> build-tested
>> the merge.
> 
> I merged it into drm-misc-next, thanks!

Great, thank you!

Regards,

Hans

Re: [Intel-gfx] [PATCH v5 00/15] drm/i915: HuC loading for DG2

[Winkler, Tomas]

> 
> On DG2, HuC loading is performed by the GSC, via a PXP command. The load
> operation itself is relatively simple (just send a message to the GSC with the
> physical address of the HuC in LMEM), but there are timing changes that
> requires special attention. In particular, to send a PXP command we need to
> first export the GSC as an aux device and then wait for the mei-gsc and mei-
> pxp modules to start, which means that HuC load will complete after i915
> load is complete. This means that there is a small window of time after i915 
> is
> registered and before HuC is loaded during which userspace could submit
> and/or check the HuC load status, although this is quite unlikely to happen
> (HuC is usually loaded before kernel init/resume completes).
> We've consulted with the media team in regards to how to handle this and
> they've asked us to stall all userspace VCS submission until HuC is loaded.
> Stalls are expected to be very rare (if any), due to the fact that HuC is 
> usually
> loaded before kernel init/resume is completed.
> 
> Timeouts are in place to ensure all submissions are unlocked in case
> something goes wrong. Since we need to monitor the status of the mei
> driver to know what's happening and when to time out, a notifier has been
> added so we get a callback when the status of the mei driver changes.
> 
> Note that this series includes several mei patches that add support for
> sending the HuC loading command via mei-gsc. We plan to merge those
> patches through the drm tree because i915 is the sole user.
> 
> v2: address review comments, Reporting HuC loading still in progress while
> we wait for mei-gsc init to complete, rebase on latest mei-gsc series.
> 
> v3: fix cc list in mei patches.
> 
> v4: update mei patches, fix includes, rebase on new FW fetch logic and
> merged mei-gsc support.
> 
> v5: update mei patches

Greg,  I hope I've addressed most of your comments.
Can you please check if the mei patches are in acceptable state or anything 
else can be improved with this series.  Appreciated. 
Thanks
Tomas


> 
> Cc: Alan Previn 
> Cc: Tony Ye 
> Cc: Alexander Usyskin 
> Cc: Tomas Winkler 
> Cc: Greg Kroah-Hartman 
> 
> Daniele Ceraolo Spurio (7):
>   drm/i915/pxp: load the pxp module when we have a gsc-loaded huc
>   drm/i915/dg2: setup HuC loading via GSC
>   drm/i915/huc: track delayed HuC load with a fence
>   drm/i915/huc: stall media submission until HuC is loaded
>   drm/i915/huc: better define HuC status getparam possible return
> values.
>   drm/i915/huc: define gsc-compatible HuC fw for DG2
>   HAX: drm/i915: force INTEL_MEI_GSC and INTEL_MEI_PXP on for CI
> 
> Tomas Winkler (5):
>   mei: add support to GSC extended header
>   mei: bus: enable sending gsc commands
>   mei: adjust extended header kdocs
>   mei: pxp: support matching with a gfx discrete card
>   drm/i915/pxp: add huc authentication and loading command
> 
> Vitaly Lubart (3):
>   mei: bus: extend bus API to support command streamer API
>   mei: pxp: add command streamer API to the PXP driver
>   drm/i915/pxp: implement function for sending tee stream command
> 
>  drivers/gpu/drm/i915/Kconfig.debug|   2 +
>  drivers/gpu/drm/i915/Makefile |  11 +-
>  drivers/gpu/drm/i915/gt/intel_gsc.c   |  22 +-
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c|   1 +
>  drivers/gpu/drm/i915/gt/uc/intel_huc.c| 254 --
>  drivers/gpu/drm/i915/gt/uc/intel_huc.h|  31 +++
>  drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c |  34 +++
>  drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h |   1 +
>  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  |  24 +-
>  drivers/gpu/drm/i915/i915_request.c   |  24 ++
>  drivers/gpu/drm/i915/pxp/intel_pxp.c  |  32 ++-
>  drivers/gpu/drm/i915/pxp/intel_pxp.h  |  32 ---
>  drivers/gpu/drm/i915/pxp/intel_pxp_huc.c  |  69 +
>  drivers/gpu/drm/i915/pxp/intel_pxp_huc.h  |  13 +
>  drivers/gpu/drm/i915/pxp/intel_pxp_irq.h  |   8 +
>  drivers/gpu/drm/i915/pxp/intel_pxp_session.c  |   8 +-
>  drivers/gpu/drm/i915/pxp/intel_pxp_session.h  |  11 +-
>  drivers/gpu/drm/i915/pxp/intel_pxp_tee.c  | 138 +-
>  drivers/gpu/drm/i915/pxp/intel_pxp_tee.h  |   5 +
>  .../drm/i915/pxp/intel_pxp_tee_interface.h|  23 +-
>  drivers/gpu/drm/i915/pxp/intel_pxp_types.h|   6 +
>  drivers/misc/mei/bus.c| 146 +-
>  drivers/misc/mei/client.c |  55 ++--
>  drivers/misc/mei/hbm.c|  13 +
>  drivers/misc/mei/hw-me.c  |   7 +-
>  drivers/misc/mei/hw.h |  89 +-
>  drivers/misc/mei/interrupt.c  |  47 +++-
>  drivers/misc/mei/mei_dev.h|   8 +
>  drivers/misc/mei/pxp/mei_pxp.c|  38 ++-
>  include/drm/i915_pxp_tee_interface.h  |   5 +
>  include/linux/mei_cl_bus.h|   6 +
>  include/uapi/drm/i915_drm.h

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915/uc: Fix issues with overriding firmware files

[John Harrison]

On 9/13/2022 17:58, john.c.harri...@intel.com wrote:

From: John Harrison 

The earlier update to support reduced versioning of firmware files
introduced an issue with the firmware override module parameter. If an
invalid file was specified then an infinite loop could occur trying to
find a backup firmware.

The above not entirely correct - got myself confused while typing it up.

A self test would specify an invalid file name (invalid meaning not in 
the table) both with and without setting the override flag. The 
*non-override* case would cause the infinite loop. I.e. a situation that 
is impossible to hit outside of the selftest because either the file 
name has come from the table in first place or it came from an override. 
However, the override case was still broken in that it would bypass some 
of the later processing.




The fix is that if an explicit override has been set, then don't scan
for backup options because there is no point anyway. The user wanted X
and if X is not available, that's their problem.

This patch also fixes up the scanning loop code so that if an invalid
file is passed in, it will exit rather than loop forever. So if the
impossible situation did somehow occur in the future, it wouldn't be
such a big problem.
It also flips the logic on the override early exit to be negative rather 
than positive so as not to skip code that still needs to be run.


John.



v2: Also remove ANSI colour codes that accidentally got left in an
error message in the original patch.

Fixes: 665ae9c9ca79 ("drm/i915/uc: Support for version reduced and multiple
firmware files")
Cc: Daniele Ceraolo Spurio 
Cc: Jani Nikula 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
Cc: Tvrtko Ursulin 
Cc: Matthew Brost 
Cc: Umesh Nerlige Ramappa 
Cc: Matthew Auld 
Cc: Alan Previn 
Cc: Matt Roper 
Cc: Lucas De Marchi 
Cc: Vinay Belgaumkar 
Cc: "Thomas Hellström" 
Cc: Venkata Sandeep Dhanalakota 
Signed-off-by: John Harrison 
---
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 20 +++-
  1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index af425916cdf64..1169e2a09da24 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -232,6 +232,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct 
intel_uc_fw *uc_fw)
u32 fw_count;
u8 rev = INTEL_REVID(i915);
int i;
+   bool found;
  
  	/*

 * The only difference between the ADL GuC FWs is the HWConfig support.
@@ -246,6 +247,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct 
intel_uc_fw *uc_fw)
fw_blobs = blobs_all[uc_fw->type].blobs;
fw_count = blobs_all[uc_fw->type].count;
  
+	found = false;

for (i = 0; i < fw_count && p <= fw_blobs[i].p; i++) {
const struct uc_fw_blob *blob = _blobs[i].blob;
  
@@ -266,9 +268,15 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw)

uc_fw->file_wanted.path = blob->path;
uc_fw->file_wanted.major_ver = blob->major;
uc_fw->file_wanted.minor_ver = blob->minor;
+   found = true;
break;
}
  
+	if (!found && uc_fw->file_selected.path) {

+   /* Failed to find a match for the last attempt?! */
+   uc_fw->file_selected.path = NULL;
+   }
+
/* make sure the list is ordered as expected */
if (IS_ENABLED(CONFIG_DRM_I915_SELFTEST) && !verified) {
verified = true;
@@ -322,7 +330,7 @@ __uc_fw_auto_select(struct drm_i915_private *i915, struct 
intel_uc_fw *uc_fw)
continue;
  
  bad:

-   drm_err(>drm, "\x1B[35;1mInvalid FW blob order: %s r%u 
%s%d.%d.%d comes before %s r%u %s%d.%d.%d\n",
+   drm_err(>drm, "Invalid FW blob order: %s r%u 
%s%d.%d.%d comes before %s r%u %s%d.%d.%d\n",
intel_platform_name(fw_blobs[i - 1].p), 
fw_blobs[i - 1].rev,
fw_blobs[i - 1].blob.legacy ? "L" : "v",
fw_blobs[i - 1].blob.major,
@@ -553,10 +561,14 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
  
  	err = firmware_request_nowarn(, uc_fw->file_selected.path, dev);

memcpy(_ideal, _fw->file_wanted, sizeof(file_ideal));
-   if (!err || intel_uc_fw_is_overridden(uc_fw))
-   goto done;
+
+   /* Any error is terminal if overriding. Don't bother searching for 
older versions */
+   if (err && intel_uc_fw_is_overridden(uc_fw))
+   goto fail;
  
  	while (err == -ENOENT) {

+   old_ver = true;
+
__uc_fw_auto_select(i915, uc_fw);
if (!uc_fw->file_selected.path) {
/*
@@ -576,8 +588,6 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
if (err)
goto fail;
  
-	

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gem: Really move i915_gem_context.link under ref protection (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/gem: Really move i915_gem_context.link under ref protection 
(rev2)
URL   : https://patchwork.freedesktop.org/series/105975/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12131_full -> Patchwork_105975v2_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_105975v2_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-skl:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24]) -> ([PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [FAIL][32], [PASS][33], [PASS][34], [PASS][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], 
[PASS][48]) ([i915#5032])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl6/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl6/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl4/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl4/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl4/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl6/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl6/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl6/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl10/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl10/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl10/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl10/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl10/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl3/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl9/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl9/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl9/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl9/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl10/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl10/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl10/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl10/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl10/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl10/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl3/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl3/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl3/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl6/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl6/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl6/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl6/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl6/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl7/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl7/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl7/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl7/boot.html
   [43]: 

[Intel-gfx] [PATCH] drm/i915: move i915_coherent_map_type() to i915_gem_pages.c and un-inline

[Jani Nikula]

The inline function has no place in i915_drv.h. Move it away, un-inline,
and untangle some header dependencies while at it.

Cc: Matthew Auld 
Cc: Tvrtko Ursulin 
Signed-off-by: Jani Nikula 

---

I don't know where this belongs, I just know it doesn't belong in
i915_drv.h.

I first tried moving it as inline, but it's really annoying as an inline
because it needs to pull in i915_drv.h, i915_gem_lmem.h, and
i915_gem_object_types.h.
---
 drivers/gpu/drm/i915/display/intel_dpt.c   |  1 +
 drivers/gpu/drm/i915/gem/i915_gem_object.h |  4 
 drivers/gpu/drm/i915/gem/i915_gem_pages.c  | 12 
 drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c |  1 +
 drivers/gpu/drm/i915/gt/intel_gsc.c|  1 +
 drivers/gpu/drm/i915/gt/intel_migrate.c|  1 +
 drivers/gpu/drm/i915/gt/selftest_migrate.c |  1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c |  1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c  |  1 +
 drivers/gpu/drm/i915/i915_drv.h| 13 -
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c  |  1 +
 11 files changed, 24 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c 
b/drivers/gpu/drm/i915/display/intel_dpt.c
index ac587647e1f5..ad1a37b515fb 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -5,6 +5,7 @@
 
 #include "gem/i915_gem_domain.h"
 #include "gem/i915_gem_internal.h"
+#include "gem/i915_gem_lmem.h"
 #include "gt/gen8_ppgtt.h"
 
 #include "i915_drv.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 7317d4102955..a3b7551a57fc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -482,6 +482,10 @@ void *__must_check i915_gem_object_pin_map(struct 
drm_i915_gem_object *obj,
 void *__must_check i915_gem_object_pin_map_unlocked(struct drm_i915_gem_object 
*obj,
enum i915_map_type type);
 
+enum i915_map_type i915_coherent_map_type(struct drm_i915_private *i915,
+ struct drm_i915_gem_object *obj,
+ bool always_coherent);
+
 void __i915_gem_object_flush_map(struct drm_i915_gem_object *obj,
 unsigned long offset,
 unsigned long size);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c 
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 4df50b049cea..16f845663ff2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -466,6 +466,18 @@ void *i915_gem_object_pin_map_unlocked(struct 
drm_i915_gem_object *obj,
return ret;
 }
 
+enum i915_map_type i915_coherent_map_type(struct drm_i915_private *i915,
+ struct drm_i915_gem_object *obj,
+ bool always_coherent)
+{
+   if (i915_gem_object_is_lmem(obj))
+   return I915_MAP_WC;
+   if (HAS_LLC(i915) || always_coherent)
+   return I915_MAP_WB;
+   else
+   return I915_MAP_WC;
+}
+
 void __i915_gem_object_flush_map(struct drm_i915_gem_object *obj,
 unsigned long offset,
 unsigned long size)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index b73c91aa5450..1cae24349a96 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -8,6 +8,7 @@
 #include 
 
 #include "gem/i915_gem_internal.h"
+#include "gem/i915_gem_lmem.h"
 #include "gem/i915_gem_region.h"
 #include "gem/i915_gem_ttm.h"
 #include "gem/i915_gem_ttm_move.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c 
b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 7af6db3194dd..d56f75b605d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -7,6 +7,7 @@
 #include 
 #include "i915_drv.h"
 #include "i915_reg.h"
+#include "gem/i915_gem_lmem.h"
 #include "gem/i915_gem_region.h"
 #include "gt/intel_gsc.h"
 #include "gt/intel_gt.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c 
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index aaaf1906026c..b405a04135ca 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -10,6 +10,7 @@
 #include "intel_gtt.h"
 #include "intel_migrate.h"
 #include "intel_ring.h"
+#include "gem/i915_gem_lmem.h"
 
 struct insert_pte_data {
u64 offset;
diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c 
b/drivers/gpu/drm/i915/gt/selftest_migrate.c
index 2b0c8749..0dc5309c90a4 100644
--- a/drivers/gpu/drm/i915/gt/selftest_migrate.c
+++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c
@@ -6,6 +6,7 @@
 #include 
 
 #include 

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm (rev2)

[Vudum, Lakshminarayana]

https://gitlab.freedesktop.org/drm/intel/-/issues/6844
[DG1][DG2] igt@i915_pm_rpm@.* - skip - Test requirement: has_runtime_pm, Last 
errno: 5, Input/output error, SKIP

Issue closed as expected and re-reported.

Lakshmi.

-Original Message-
From: Gupta, Anshuman  
Sent: Wednesday, September 14, 2022 9:10 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 
; Vivi, Rodrigo 
Subject: RE: ✗ Fi.CI.BAT: failure for drm/i915/DG{1, 2}: FIXME Temporary hammer 
to disable rpm (rev2)



> -Original Message-
> From: Gupta, Anshuman
> Sent: Wednesday, September 14, 2022 9:36 PM
> To: intel-gfx@lists.freedesktop.org; ", 
> lakshminarayana.vudum"@intel.com; ",rodrigo.vivi"@intel.com
> Subject: Re: ✗ Fi.CI.BAT: failure for drm/i915/DG{1, 2}: FIXME 
> Temporary hammer to disable rpm (rev2)
> 
> 
> 
> On 9/14/2022 9:13 PM, Patchwork wrote:
> > *Patch Details*
> > *Series:*   drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm
> (rev2)
> > *URL:*  https://patchwork.freedesktop.org/series/108477/
> > 
> > *State:*failure
> > *Details:*
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/index.ht
> > ml 
> >  > tm
> > l>
> >
> >
> >   CI Bug Log - changes from CI_DRM_12134 -> Patchwork_108477v2
> >
> >
> > Summary
> >
> > *FAILURE*
> >
> > Serious unknown changes coming with Patchwork_108477v2 absolutely 
> > need to be verified manually.
> >
> > If you think the reported changes have nothing to do with the 
> > changes introduced in Patchwork_108477v2, please notify your bug 
> > team to allow them to document this new failure mode, which will 
> > reduce false positives in
> CI.
> >
> > External URL:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/index.ht
> > ml
> >
> >
> > Participating hosts (40 -> 41)
> >
> > Additional (5): fi-icl-u2 bat-dg2-9 bat-adln-1 bat-rplp-1 bat-jsl-1 
> > Missing (4): fi-ctg-p8600 fi-hsw-4770 fi-rkl-11600 fi-tgl-dsi
> >
> >
> > Possible new issues
> >
> > Here are the unknown changes that may have been introduced in
> > Patchwork_108477v2:
> >
> >
> >   IGT changes
> >
> >
> > Possible regressions
> >
> >   * igt@i915_pm_rpm@module-reload:
> >   o bat-dg1-5: PASS
> >
> >  > @i 915_pm_...@module-reload.html> -> SKIP
> >  > -5 /igt@i915_pm_...@module-reload.html> +2 similar issues
> Hi Lakshmi ,
> With this series i915_pm_rpm test are expected to fail  on DG1/DG2 as 
> this patch disables runtime PM.
> Could you please re-report the result so that BAT can resume.
> Thanks,
> Anshuman Gupta.
> >
> >
> > Suppressed
> >
> > The following results come from untrusted machines, tests, or statuses.
> > They do not affect the overall result.
> >
> >   *
> >
> > igt@i915_pm_rpm@basic-pci-d3-state:
> >
> >   o {bat-dg2-8}: PASS
> > 
> >  8/igt@i915_pm_...@basic-pci-d3-state.html> -> SKIP  ci.01.org/tree/drm-tip/Patchwork_108477v2/bat-dg2-
> 8/igt@i915_pm_...@basic-pci-d3-state.html> +2 similar issues
> >   *
> >
> > igt@i915_pm_rpm@basic-rte:
> >
> >   o {bat-dg2-9}: NOTRUN -> SKIP
> >
> >  > -9 /igt@i915_pm_...@basic-rte.html> +2 similar issues
> >
> >
> > Known issues
> >
> > Here are the changes found in Patchwork_108477v2 that come from 
> > known
> > issues:
> >
> >
> >   IGT changes
> >
> >
> > Issues hit
> >
> >   *
> >
> > igt@gem_huc_copy@huc-copy:
> >
> >   o fi-icl-u2: NOTRUN -> SKIP
> > 
> >  u2/igt@gem_huc_c...@huc-copy.html> (i915#2190
> )
> >   *
> >
> > igt@gem_lmem_swapping@random-engines:
> >
> >   o fi-icl-u2: NOTRUN -> SKIP
> > 
> >  u2/igt@gem_lmem_swapp...@random-engines.html> (i915#4613
> ) +3 similar 
> issues
> >   *
> >
> > igt@i915_pm_rpm@module-reload:
> >
> >   o fi-cfl-8109u: PASS
> > 
> >  8109u/igt@i915_pm_...@module-reload.html> -> DMESG-FAIL 
>  gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-cfl-
> 8109u/igt@i915_pm_...@module-reload.html> (i915#62
> )
> >   *
> >
> > igt@i915_selftest@live@ring_submission:
> >
> >   o fi-cfl-8109u: PASS
> > 
> >  8109u/igt@i915_selftest@live@ring_submission.html> -> DMESG-WARN
> 

[Intel-gfx] [PATCH 0/1] Update to version reduced firmware file names

[John . C . Harrison]

From: John Harrison 

Start using GuC/HuC firmware files with reduced version information in
the file name.

Signed-off-by: John Harrison 


John Harrison (1):
  drm/i915/uc: Enable version reduced firmware files for newest
platforms

 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

-- 
2.37.3

[Intel-gfx] [PATCH 1/1] drm/i915/uc: Enable version reduced firmware files for newest platforms

[John . C . Harrison]

From: John Harrison 

Going forwards, the intention is for GuC firmware files to be named
for their major version only and HuC firmware files to have no version
number in the name at all. This patch adds those entries for all
platforms that are officially GuC/HuC enabled.

Also, update the expected version numbers to the latest firmware
release for those platforms.

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index af425916cdf64..57faba11029ac 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -72,13 +72,18 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  * security fixes, etc. to be enabled.
  */
 #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_maj, guc_mmp) \
-   fw_def(DG2,  0, guc_mmp(dg2,  70, 4, 1)) \
+   fw_def(DG2,  0, guc_maj(dg2,  70, 5)) \
+   fw_def(ALDERLAKE_P,  0, guc_maj(adlp, 70, 5)) \
fw_def(ALDERLAKE_P,  0, guc_mmp(adlp, 70, 1, 1)) \
fw_def(ALDERLAKE_P,  0, guc_mmp(adlp, 69, 0, 3)) \
+   fw_def(ALDERLAKE_S,  0, guc_maj(tgl,  70, 5)) \
fw_def(ALDERLAKE_S,  0, guc_mmp(tgl,  70, 1, 1)) \
fw_def(ALDERLAKE_S,  0, guc_mmp(tgl,  69, 0, 3)) \
+   fw_def(DG1,  0, guc_maj(dg1,  70, 5)) \
fw_def(DG1,  0, guc_mmp(dg1,  70, 1, 1)) \
+   fw_def(ROCKETLAKE,   0, guc_maj(tgl,  70, 5)) \
fw_def(ROCKETLAKE,   0, guc_mmp(tgl,  70, 1, 1)) \
+   fw_def(TIGERLAKE,0, guc_maj(tgl,  70, 5)) \
fw_def(TIGERLAKE,0, guc_mmp(tgl,  70, 1, 1)) \
fw_def(JASPERLAKE,   0, guc_mmp(ehl,  70, 1, 1)) \
fw_def(ELKHARTLAKE,  0, guc_mmp(ehl,  70, 1, 1)) \
@@ -92,10 +97,15 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
fw_def(SKYLAKE,  0, guc_mmp(skl,  70, 1, 1))
 
 #define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp) \
+   fw_def(ALDERLAKE_P,  0, huc_raw(tgl)) \
fw_def(ALDERLAKE_P,  0, huc_mmp(tgl,  7, 9, 3)) \
+   fw_def(ALDERLAKE_S,  0, huc_raw(tgl)) \
fw_def(ALDERLAKE_S,  0, huc_mmp(tgl,  7, 9, 3)) \
+   fw_def(DG1,  0, huc_raw(dg1)) \
fw_def(DG1,  0, huc_mmp(dg1,  7, 9, 3)) \
+   fw_def(ROCKETLAKE,   0, huc_raw(tgl)) \
fw_def(ROCKETLAKE,   0, huc_mmp(tgl,  7, 9, 3)) \
+   fw_def(TIGERLAKE,0, huc_raw(tgl)) \
fw_def(TIGERLAKE,0, huc_mmp(tgl,  7, 9, 3)) \
fw_def(JASPERLAKE,   0, huc_mmp(ehl,  9, 0, 0)) \
fw_def(ELKHARTLAKE,  0, huc_mmp(ehl,  9, 0, 0)) \
-- 
2.37.3

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm (rev2)
URL   : https://patchwork.freedesktop.org/series/108477/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12134 -> Patchwork_108477v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/index.html

Participating hosts (40 -> 41)
--

  Additional (5): fi-icl-u2 bat-dg2-9 bat-adln-1 bat-rplp-1 bat-jsl-1 
  Missing(4): fi-ctg-p8600 fi-hsw-4770 fi-rkl-11600 fi-tgl-dsi 

Known issues


  Here are the changes found in Patchwork_108477v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][1] ([i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@i915_pm_rpm@module-reload:
- bat-dg1-5:  [PASS][3] -> [SKIP][4] ([i915#6844]) +2 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/bat-dg1-5/igt@i915_pm_...@module-reload.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/bat-dg1-5/igt@i915_pm_...@module-reload.html
- fi-cfl-8109u:   [PASS][5] -> [DMESG-FAIL][6] ([i915#62])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@ring_submission:
- fi-cfl-8109u:   [PASS][7] -> [DMESG-WARN][8] ([i915#5904]) +30 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u:   [PASS][9] -> [DMESG-WARN][10] ([i915#5904] / 
[i915#62])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-bdw-5557u:   NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-bdw-5557u/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][12] ([fdo#111827]) +8 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-icl-u2:  NOTRUN -> [SKIP][13] ([i915#4103])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-connector-state:
- fi-icl-u2:  NOTRUN -> [WARN][14] ([i915#6008])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-icl-u2/igt@kms_force_connector_ba...@force-connector-state.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][15] ([fdo#109285])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u:   [PASS][16] -> [DMESG-WARN][17] ([i915#62]) +12 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][18] ([i915#3555])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-icl-u2:  NOTRUN -> [SKIP][19] ([fdo#109295] / [i915#3301])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-icl-u2/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@i915_selftest@live@guc:
- {bat-rpls-1}:   [DMESG-WARN][20] ([i915#6471]) -> [PASS][21]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/bat-rpls-1/igt@i915_selftest@l...@guc.html
   [21]: 

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gem: Really move i915_gem_context.link under ref protection

[Janusz Krzysztofik]

Hi Tvrtko,

Thanks for review.

On Wednesday, 14 September 2022 17:37:19 CEST Tvrtko Ursulin wrote:
> 
> On 13/09/2022 17:10, Janusz Krzysztofik wrote:
> > From: Chris Wilson 
> > 
> > i915_perf assumes that it can use the i915_gem_context reference to
> > protect its i915->gem.contexts.list iteration. However, this requires
> > that we do not remove the context from the list until after we drop the
> > final reference and release the struct. If, as currently, we remove the
> > context from the list during context_close(), the link.next pointer may
> > be poisoned while we are holding the context reference and cause a GPF:
> > 
> > [ 4070.573157] i915 :00:02.0: [drm:i915_perf_open_ioctl [i915]] 
> > filtering on ctx_id=0x1f ctx_id_mask=0x1f
> > [ 4070.574881] general protection fault, probably for non-canonical address 
> > 0xdead0100:  [#1] PREEMPT SMP
> > [ 4070.574897] CPU: 1 PID: 284392 Comm: amd_performance Tainted: G  
> >   E 5.17.9 #180
> > [ 4070.574903] Hardware name: Intel Corporation NUC7i5BNK/NUC7i5BNB, BIOS 
> > BNKBL357.86A.0052.2017.0918.1346 09/18/2017
> > [ 4070.574907] RIP: 0010:oa_configure_all_contexts.isra.0+0x222/0x350 [i915]
> > [ 4070.574982] Code: 08 e8 32 6e 10 e1 4d 8b 6d 50 b8 ff ff ff ff 49 83 ed 
> > 50 f0 41 0f c1 04 24 83 f8 01 0f 84 e3 00 00 00 85 c0 0f 8e fa 00 00 00 
> > <49> 8b 45 50 48 8d 70 b0 49 8d 45 50 48 39 44 24 10 0f 85 34 fe ff
> > [ 4070.574990] RSP: 0018:c90002077b78 EFLAGS: 00010202
> > [ 4070.574995] RAX: 0002 RBX: 0002 RCX: 
> > 
> > [ 4070.575000] RDX: 0001 RSI: c90002077b20 RDI: 
> > 88810ddc7c68
> > [ 4070.575004] RBP: 0001 R08: 888103242648 R09: 
> > fffc
> > [ 4070.575008] R10: 82c50bc0 R11: 00025c80 R12: 
> > 888101bf1860
> > [ 4070.575012] R13: dead00b0 R14: c90002077c04 R15: 
> > 88810be5cabc
> > [ 4070.575016] FS:  7f1ed50c0780() GS:5ec8() 
> > knlGS:
> > [ 4070.575021] CS:  0010 DS:  ES:  CR0: 80050033
> > [ 4070.575025] CR2: 7f1ed5590280 CR3: 00010ef6f005 CR4: 
> > 003706e0
> > [ 4070.575029] Call Trace:
> > [ 4070.575033]  
> > [ 4070.575037]  lrc_configure_all_contexts+0x13e/0x150 [i915]
> > [ 4070.575103]  gen8_enable_metric_set+0x4d/0x90 [i915]
> > [ 4070.575164]  i915_perf_open_ioctl+0xbc0/0x1500 [i915]
> > [ 4070.575224]  ? asm_common_interrupt+0x1e/0x40
> > [ 4070.575232]  ? i915_oa_init_reg_state+0x110/0x110 [i915]
> > [ 4070.575290]  drm_ioctl_kernel+0x85/0x110
> > [ 4070.575296]  ? update_load_avg+0x5f/0x5e0
> > [ 4070.575302]  drm_ioctl+0x1d3/0x370
> > [ 4070.575307]  ? i915_oa_init_reg_state+0x110/0x110 [i915]
> > [ 4070.575382]  ? gen8_gt_irq_handler+0x46/0x130 [i915]
> > [ 4070.575445]  __x64_sys_ioctl+0x3c4/0x8d0
> > [ 4070.575451]  ? __do_softirq+0xaa/0x1d2
> > [ 4070.575456]  do_syscall_64+0x35/0x80
> > [ 4070.575461]  entry_SYSCALL_64_after_hwframe+0x44/0xae
> > [ 4070.575467] RIP: 0033:0x7f1ed5c10397
> > [ 4070.575471] Code: 3c 1c e8 1c ff ff ff 85 c0 79 87 49 c7 c4 ff ff ff ff 
> > 5b 5d 4c 89 e0 41 5c c3 66 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 
> > <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d a9 da 0d 00 f7 d8 64 89 01 48
> > [ 4070.575478] RSP: 002b:7ffd65c8d7a8 EFLAGS: 0246 ORIG_RAX: 
> > 0010
> > [ 4070.575484] RAX: ffda RBX: 0006 RCX: 
> > 7f1ed5c10397
> > [ 4070.575488] RDX: 7ffd65c8d7c0 RSI: 40106476 RDI: 
> > 0006
> > [ 4070.575492] RBP: 5620972f9c60 R08: 000a R09: 
> > 0005
> > [ 4070.575496] R10: 000d R11: 0246 R12: 
> > 000a
> > [ 4070.575500] R13: 000d R14:  R15: 
> > 7ffd65c8d7c0
> > [ 4070.575505]  
> > [ 4070.575507] Modules linked in: nls_ascii(E) nls_cp437(E) vfat(E) fat(E) 
> > i915(E) x86_pkg_temp_thermal(E) intel_powerclamp(E) crct10dif_pclmul(E) 
> > crc32_pclmul(E) crc32c_intel(E) aesni_intel(E) crypto_simd(E) intel_gtt(E) 
> > cryptd(E) ttm(E) rapl(E) intel_cstate(E) drm_kms_helper(E) cfbfillrect(E) 
> > syscopyarea(E) cfbimgblt(E) intel_uncore(E) sysfillrect(E) mei_me(E) 
> > sysimgblt(E) i2c_i801(E) fb_sys_fops(E) mei(E) intel_pch_thermal(E) 
> > i2c_smbus(E) cfbcopyarea(E) video(E) button(E) efivarfs(E) autofs4(E)
> > [ 4070.575549] ---[ end trace  ]---
> > 
> > Reported-by: Mark Janes 
> > Closes: https://gitlab.freedesktop.org/drm/intel/issues/6222
> > References: a4e7ccdac38e ("drm/i915: Move context management under GEM")
> > Fixes: f8246cf4d9a9 ("drm/i915/gem: Drop free_work for GEM contexts")
> > Signed-off-by: Chris Wilson 
> > Reviewed-by: Andi Shyti 
> > Signed-off-by: Andi Shyti 
> > Signed-off-by: Janusz Krzysztofik 
> > Cc: Tvrtko Ursulin 
> > Cc:  # v5.12+
> > ---
> >   drivers/gpu/drm/i915/gem/i915_gem_context.c | 14 +++---
> >   drivers/gpu/drm/i915/i915_perf.c

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: HuC loading for DG2 (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915: HuC loading for DG2 (rev7)
URL   : https://patchwork.freedesktop.org/series/107477/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12132_full -> Patchwork_107477v7_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_107477v7_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_107477v7_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_107477v7_full:

### IGT changes ###

 Possible regressions 

  * igt@gen9_exec_parse@bb-large:
- shard-apl:  [PASS][1] -> [TIMEOUT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/igt@gen9_exec_pa...@bb-large.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v7/shard-apl4/igt@gen9_exec_pa...@bb-large.html

  
Known issues


  Here are the changes found in Patchwork_107477v7_full that come from known 
issues:

### CI changes ###

 Possible fixes 

  * boot:
- shard-apl:  ([FAIL][3], [PASS][4], [PASS][5], [PASS][6], 
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], 
[PASS][25], [PASS][26], [PASS][27]) ([i915#4386]) -> ([PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], 
[PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl3/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl3/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl3/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl4/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl7/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl7/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl7/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl8/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl8/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl8/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v7/shard-apl3/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v7/shard-apl4/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v7/shard-apl4/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v7/shard-apl4/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v7/shard-apl6/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v7/shard-apl6/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v7/shard-apl6/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107477v7/shard-apl6/boot.html
   [36]: 

[Intel-gfx] [PATCH v2] drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm

[Anshuman Gupta]

DG1 and DG2 has lmem, and cpu can access the lmem objects
via mmap and i915 internal i915_gem_object_pin_map() for
i915 own usages. Both of these methods has pre-requisite
requirement to keep GFX PCI endpoint in D0 for a supported
iomem transaction over PCI link. (Refer PCIe specs 5.3.1.4.1)

Both DG1/DG2 have a hardware bug that violates the PCIe specs
and support the iomem read write transaction over PCIe bus despite
endpoint is D3 state.
Due to above H/W bug, we had never observed any issue with i915 runtime
PM versus lmem access.
But this issue becomes visible when PCIe gfx endpoint's upstream
bridge enters to D3, at this point any lmem read/write access will be
returned as unsupported request. But again this issue is not observed
on every platform because it has been observed on few host machines
DG1/DG2 endpoint's upstream bridge does not bind with pcieport driver.
which really disables the PCIe poer power savings and leaves the bridge
at D0 state.

TODO:
With respect to i915_gem_object_pin_map(), every caller
has to grab a wakeref if gem object lies in lmem.

Till we fix all issues related to runtime PM, we need
to keep runtime PM disable on both DG1 and DG2.

V2:
- Keep a smaller FIXME code comment for both DG1/DG2.

Cc: Matthew Auld 
Cc: Rodrigo Vivi 
Reviewed-by: Rodrigo Vivi 
Reviewed-by: Andi Shyti 
Signed-off-by: Anshuman Gupta 
---
 drivers/gpu/drm/i915/i915_pci.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 77e7df21f539..4a7d226b074f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -931,6 +931,14 @@ static const struct intel_device_info dg1_info = {
BIT(VCS0) | BIT(VCS2),
/* Wa_16011227922 */
.__runtime.ppgtt_size = 47,
+
+   /*
+*  FIXME: Temporary hammer to disable rpm.
+*  As per PCIe specs 5.3.1.4.1, all iomem read write request over a 
PCIe
+*  function will be unsupported in case PCIe endpoint function is in 
D3.
+*  Let's disable i915 rpm till we fix all known issue with lmem access 
in D3.
+*/
+   .has_runtime_pm = 0,
 };
 
 static const struct intel_device_info adl_s_info = {
@@ -1076,6 +1084,13 @@ static const struct intel_device_info dg2_info = {
XE_LPD_FEATURES,
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
   BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+   /*
+*  FIXME: Temporary hammer to disable rpm.
+*  As per PCIe specs 5.3.1.4.1, all iomem read write request over a 
PCIe
+*  function will be unsupported in case PCIe endpoint function is in 
D3.
+*  Let's disable i915 rpm till we fix all known issue with lmem access 
in D3.
+*/
+   .has_runtime_pm = 0,
.require_force_probe = 1,
 };
 
-- 
2.26.2

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Use GEN12 RPSTAT register

[Dixit, Ashutosh]

On Wed, 14 Sep 2022 02:56:26 -0700, Nilawar, Badal wrote:
>
> On 13-09-2022 13:17, Tvrtko Ursulin wrote:
> >
> > On 13/09/2022 01:09, Dixit, Ashutosh wrote:
> >> On Mon, 12 Sep 2022 04:29:38 -0700, Nilawar, Badal wrote:
> >>>
> > diff --git a/drivers/gpu/drm/i915/i915_pmu.c
> > b/drivers/gpu/drm/i915/i915_pmu.c
> > index 958b37123bf1..a24704ec2c18 100644
> > --- a/drivers/gpu/drm/i915/i915_pmu.c
> > +++ b/drivers/gpu/drm/i915/i915_pmu.c
> > @@ -371,7 +371,6 @@ static void
> >    frequency_sample(struct intel_gt *gt, unsigned int period_ns)
> >    {
> > struct drm_i915_private *i915 = gt->i915;
> > -    struct intel_uncore *uncore = gt->uncore;
> > struct i915_pmu *pmu = >pmu;
> > struct intel_rps *rps = >rps;
> >
> > @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned
> > int period_ns)
> >  * case we assume the system is running at the intended
> >  * frequency. Fortunately, the read should rarely fail!
> >  */
> > -    val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
> > +    val = intel_rps_read_rpstat(rps);
> 
>  Hmm, we got rid of _fw which the comment above refers to. Maybe we
>  need a
>  fw flag to intel_rps_read_rpstat?
> >>>
> >>> Above function before reading rpstat it checks if gt is awake.
> >>
> >> Ok, so you are referring to intel_gt_pm_get_if_awake check in
> >> frequency_sample.
> >>
> >>> So when gt is awake shouldn't matter if we read GEN6_RPSTAT1 with
> >>> forcewake.In that case we can remove above comment.  Let me know your
> >>> thoughts on this.
> >>
> >> I am not entirely sure about this. For example in c1c82d267ae8
> >> intel_uncore_read_fw was introduced with the same
> >> intel_gt_pm_get_if_awake
> >> check. So this would mean even if gt is awake not taking forcewake makes
> >> a
> >> difference. The same code pattern was retained in b66ecd0438bf. Maybe
> >> it's
> >> because there are no locks?
> >
> > Its about power. As c1c82d267ae8 ("drm/i915/pmu: Cheat when reading the
> > actual frequency to avoid fw") explains the _fw variant is to avoid
> > preventing RC6, and so increased GPU power draw, just because someone has
> > PMU open. (Because of the 200Hz sampling timer that is needed for PMU
> > frequency reporting.)
> >
> >> Under the circumstances I think we could do one of two things:
> >> 1. If we want to drop _fw, we should do it as a separate patch with its
> >> own
> >>     justification so it can be reviewed separately.
> >> 2. Otherwise as I mentioned we should retain the _fw and add a fw flag to
> >>     intel_rps_read_rpstat.
> >
> > Agreed. Or instead of the flag, the usual pattern of having
> > intel_rps_read_rpstat_fw and make intel_rps_read_rpsstat get the
> > forcewake.
> >
> > Also, may I ask, this patch is in the MTL enablement series but the
> > commit message and patch content seem like it is fixing a wider Gen12
> > issue? What is the extent of incorrect behaviour without it? Should it be
> > tagged for stable for first Tigerlake supporting kernel?
>
> GEN6_RPSTAT1(0xa01c) and GEN12_RPSTAT1(0x1381b4) both are supported by
> gen12 and above. The difference between two is GEN6_RPSTAT1 falls under
> RENDER forcewake domain and GEN12_RPSTAT1 does not require forcewake to
> access. GEN12_RPSTAT1 is punit register and when GT is in RC6 it will give
> frequency as 0.

Correct, so no changes needed for stable kernels. But going forward Badal
is proposing (which I sort of agree with but may need some discussion) that
we change i915 behavior to return 0 freq (instead of cur_freq or RPn) when
GT is idle or in RC6 (so we don't take forcewake to read freq when GT is in
RC6).

> Reason for clubbing this patch with MTL series is due to common function
> intel_rps_read_rpstat. I think I should send this patch in separate series.

Agree!

Thanks.
--
Ashutosh

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm (rev2)

[Gupta, Anshuman]

> -Original Message-
> From: Gupta, Anshuman
> Sent: Wednesday, September 14, 2022 9:36 PM
> To: intel-gfx@lists.freedesktop.org; ", lakshminarayana.vudum"@intel.com;
> ",rodrigo.vivi"@intel.com
> Subject: Re: ✗ Fi.CI.BAT: failure for drm/i915/DG{1, 2}: FIXME Temporary
> hammer to disable rpm (rev2)
> 
> 
> 
> On 9/14/2022 9:13 PM, Patchwork wrote:
> > *Patch Details*
> > *Series:*   drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm
> (rev2)
> > *URL:*  https://patchwork.freedesktop.org/series/108477/
> > 
> > *State:*failure
> > *Details:*
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/index.html
> >  > l>
> >
> >
> >   CI Bug Log - changes from CI_DRM_12134 -> Patchwork_108477v2
> >
> >
> > Summary
> >
> > *FAILURE*
> >
> > Serious unknown changes coming with Patchwork_108477v2 absolutely need
> > to be verified manually.
> >
> > If you think the reported changes have nothing to do with the changes
> > introduced in Patchwork_108477v2, please notify your bug team to allow
> > them to document this new failure mode, which will reduce false positives in
> CI.
> >
> > External URL:
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/index.html
> >
> >
> > Participating hosts (40 -> 41)
> >
> > Additional (5): fi-icl-u2 bat-dg2-9 bat-adln-1 bat-rplp-1 bat-jsl-1
> > Missing (4): fi-ctg-p8600 fi-hsw-4770 fi-rkl-11600 fi-tgl-dsi
> >
> >
> > Possible new issues
> >
> > Here are the unknown changes that may have been introduced in
> > Patchwork_108477v2:
> >
> >
> >   IGT changes
> >
> >
> > Possible regressions
> >
> >   * igt@i915_pm_rpm@module-reload:
> >   o bat-dg1-5: PASS
> >
> >  > 915_pm_...@module-reload.html> -> SKIP
> >  > /igt@i915_pm_...@module-reload.html> +2 similar issues
> Hi Lakshmi ,
> With this series i915_pm_rpm test are expected to fail  on DG1/DG2 as this
> patch disables runtime PM.
> Could you please re-report the result so that BAT can resume.
> Thanks,
> Anshuman Gupta.
> >
> >
> > Suppressed
> >
> > The following results come from untrusted machines, tests, or statuses.
> > They do not affect the overall result.
> >
> >   *
> >
> > igt@i915_pm_rpm@basic-pci-d3-state:
> >
> >   o {bat-dg2-8}: PASS
> >  8/igt@i915_pm_...@basic-pci-d3-state.html> -> SKIP  ci.01.org/tree/drm-tip/Patchwork_108477v2/bat-dg2-
> 8/igt@i915_pm_...@basic-pci-d3-state.html> +2 similar issues
> >   *
> >
> > igt@i915_pm_rpm@basic-rte:
> >
> >   o {bat-dg2-9}: NOTRUN -> SKIP
> >
> >  > /igt@i915_pm_...@basic-rte.html> +2 similar issues
> >
> >
> > Known issues
> >
> > Here are the changes found in Patchwork_108477v2 that come from known
> > issues:
> >
> >
> >   IGT changes
> >
> >
> > Issues hit
> >
> >   *
> >
> > igt@gem_huc_copy@huc-copy:
> >
> >   o fi-icl-u2: NOTRUN -> SKIP
> >  u2/igt@gem_huc_c...@huc-copy.html> (i915#2190
> )
> >   *
> >
> > igt@gem_lmem_swapping@random-engines:
> >
> >   o fi-icl-u2: NOTRUN -> SKIP
> >  u2/igt@gem_lmem_swapp...@random-engines.html> (i915#4613
> ) +3 similar issues
> >   *
> >
> > igt@i915_pm_rpm@module-reload:
> >
> >   o fi-cfl-8109u: PASS
> >  8109u/igt@i915_pm_...@module-reload.html> -> DMESG-FAIL  gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-cfl-
> 8109u/igt@i915_pm_...@module-reload.html> (i915#62
> )
> >   *
> >
> > igt@i915_selftest@live@ring_submission:
> >
> >   o fi-cfl-8109u: PASS
> >  8109u/igt@i915_selftest@live@ring_submission.html> -> DMESG-WARN
>  8109u/igt@i915_selftest@live@ring_submission.html> (i915#5904
> ) +30 similar issues
> >   *
> >
> > igt@i915_suspend@basic-s2idle-without-i915:
> >
> >   o fi-cfl-8109u: PASS
> >  8109u/igt@i915_susp...@basic-s2idle-without-i915.html> -> DMESG-WARN
>  

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gem: Really move i915_gem_context.link under ref protection

[Janusz Krzysztofik]

On Wednesday, 14 September 2022 17:15:02 CEST Andi Shyti wrote:
> Hi Krzysztofik,
> 
> if you are going to resend it, I just have a little thing if you
> don't mind,
> 
> On Tue, Sep 13, 2022 at 06:10:39PM +0200, Janusz Krzysztofik wrote:
> > From: Chris Wilson 
> > 
> > i915_perf assumes that it can use the i915_gem_context reference to
> > protect its i915->gem.contexts.list iteration. However, this requires
> > that we do not remove the context from the list until after we drop the
> > final reference and release the struct. If, as currently, we remove the
> > context from the list during context_close(), the link.next pointer may
> > be poisoned while we are holding the context reference and cause a GPF:
> > 
> > [ 4070.573157] i915 :00:02.0: [drm:i915_perf_open_ioctl [i915]] 
> > filtering on ctx_id=0x1f ctx_id_mask=0x1f
> > [ 4070.574881] general protection fault, probably for non-canonical address 
> > 0xdead0100:  [#1] PREEMPT SMP
> > [ 4070.574897] CPU: 1 PID: 284392 Comm: amd_performance Tainted: G  
> >   E 5.17.9 #180
> > [ 4070.574903] Hardware name: Intel Corporation NUC7i5BNK/NUC7i5BNB, BIOS 
> > BNKBL357.86A.0052.2017.0918.1346 09/18/2017
> > [ 4070.574907] RIP: 0010:oa_configure_all_contexts.isra.0+0x222/0x350 [i915]
> > [ 4070.574982] Code: 08 e8 32 6e 10 e1 4d 8b 6d 50 b8 ff ff ff ff 49 83 ed 
> > 50 f0 41 0f c1 04 24 83 f8 01 0f 84 e3 00 00 00 85 c0 0f 8e fa 00 00 00 
> > <49> 8b 45 50 48 8d 70 b0 49 8d 45 50 48 39 44 24 10 0f 85 34 fe ff
> > [ 4070.574990] RSP: 0018:c90002077b78 EFLAGS: 00010202
> > [ 4070.574995] RAX: 0002 RBX: 0002 RCX: 
> > 
> > [ 4070.575000] RDX: 0001 RSI: c90002077b20 RDI: 
> > 88810ddc7c68
> > [ 4070.575004] RBP: 0001 R08: 888103242648 R09: 
> > fffc
> > [ 4070.575008] R10: 82c50bc0 R11: 00025c80 R12: 
> > 888101bf1860
> > [ 4070.575012] R13: dead00b0 R14: c90002077c04 R15: 
> > 88810be5cabc
> > [ 4070.575016] FS:  7f1ed50c0780() GS:5ec8() 
> > knlGS:
> > [ 4070.575021] CS:  0010 DS:  ES:  CR0: 80050033
> > [ 4070.575025] CR2: 7f1ed5590280 CR3: 00010ef6f005 CR4: 
> > 003706e0
> > [ 4070.575029] Call Trace:
> > [ 4070.575033]  
> > [ 4070.575037]  lrc_configure_all_contexts+0x13e/0x150 [i915]
> > [ 4070.575103]  gen8_enable_metric_set+0x4d/0x90 [i915]
> > [ 4070.575164]  i915_perf_open_ioctl+0xbc0/0x1500 [i915]
> > [ 4070.575224]  ? asm_common_interrupt+0x1e/0x40
> > [ 4070.575232]  ? i915_oa_init_reg_state+0x110/0x110 [i915]
> > [ 4070.575290]  drm_ioctl_kernel+0x85/0x110
> > [ 4070.575296]  ? update_load_avg+0x5f/0x5e0
> > [ 4070.575302]  drm_ioctl+0x1d3/0x370
> > [ 4070.575307]  ? i915_oa_init_reg_state+0x110/0x110 [i915]
> > [ 4070.575382]  ? gen8_gt_irq_handler+0x46/0x130 [i915]
> > [ 4070.575445]  __x64_sys_ioctl+0x3c4/0x8d0
> > [ 4070.575451]  ? __do_softirq+0xaa/0x1d2
> > [ 4070.575456]  do_syscall_64+0x35/0x80
> > [ 4070.575461]  entry_SYSCALL_64_after_hwframe+0x44/0xae
> > [ 4070.575467] RIP: 0033:0x7f1ed5c10397
> > [ 4070.575471] Code: 3c 1c e8 1c ff ff ff 85 c0 79 87 49 c7 c4 ff ff ff ff 
> > 5b 5d 4c 89 e0 41 5c c3 66 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 
> > <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d a9 da 0d 00 f7 d8 64 89 01 48
> > [ 4070.575478] RSP: 002b:7ffd65c8d7a8 EFLAGS: 0246 ORIG_RAX: 
> > 0010
> > [ 4070.575484] RAX: ffda RBX: 0006 RCX: 
> > 7f1ed5c10397
> > [ 4070.575488] RDX: 7ffd65c8d7c0 RSI: 40106476 RDI: 
> > 0006
> > [ 4070.575492] RBP: 5620972f9c60 R08: 000a R09: 
> > 0005
> > [ 4070.575496] R10: 000d R11: 0246 R12: 
> > 000a
> > [ 4070.575500] R13: 000d R14:  R15: 
> > 7ffd65c8d7c0
> > [ 4070.575505]  
> > [ 4070.575507] Modules linked in: nls_ascii(E) nls_cp437(E) vfat(E) fat(E) 
> > i915(E) x86_pkg_temp_thermal(E) intel_powerclamp(E) crct10dif_pclmul(E) 
> > crc32_pclmul(E) crc32c_intel(E) aesni_intel(E) crypto_simd(E) intel_gtt(E) 
> > cryptd(E) ttm(E) rapl(E) intel_cstate(E) drm_kms_helper(E) cfbfillrect(E) 
> > syscopyarea(E) cfbimgblt(E) intel_uncore(E) sysfillrect(E) mei_me(E) 
> > sysimgblt(E) i2c_i801(E) fb_sys_fops(E) mei(E) intel_pch_thermal(E) 
> > i2c_smbus(E) cfbcopyarea(E) video(E) button(E) efivarfs(E) autofs4(E)
> > [ 4070.575549] ---[ end trace  ]---
> > 
> > Reported-by: Mark Janes 
> > Closes: https://gitlab.freedesktop.org/drm/intel/issues/6222
> > References: a4e7ccdac38e ("drm/i915: Move context management under GEM")
> > Fixes: f8246cf4d9a9 ("drm/i915/gem: Drop free_work for GEM contexts")
> > Signed-off-by: Chris Wilson 
> > Reviewed-by: Andi Shyti 
> > Signed-off-by: Andi Shyti 
> > Signed-off-by: Janusz Krzysztofik 
> > Cc: Tvrtko Ursulin 
> > Cc:  # v5.12+
> > ---
> >  

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm (rev2)

[Gupta, Anshuman]

On 9/14/2022 9:13 PM, Patchwork wrote:

*Patch Details*
*Series:*   drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm (rev2)
*URL:*	https://patchwork.freedesktop.org/series/108477/ 


*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/index.html 




  CI Bug Log - changes from CI_DRM_12134 -> Patchwork_108477v2


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_108477v2 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108477v2, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/index.html



Participating hosts (40 -> 41)

Additional (5): fi-icl-u2 bat-dg2-9 bat-adln-1 bat-rplp-1 bat-jsl-1
Missing (4): fi-ctg-p8600 fi-hsw-4770 fi-rkl-11600 fi-tgl-dsi


Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_108477v2:



  IGT changes


Possible regressions

  * igt@i915_pm_rpm@module-reload:
  o bat-dg1-5: PASS


 -> SKIP 

 +2 similar issues

Hi Lakshmi ,
With this series i915_pm_rpm test are expected to fail  on DG1/DG2 as 
this patch disables runtime PM.

Could you please re-report the result so that BAT can resume.
Thanks,
Anshuman Gupta.



Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  *

igt@i915_pm_rpm@basic-pci-d3-state:

  o {bat-dg2-8}: PASS


 -> SKIP 

 +2 similar issues
  *

igt@i915_pm_rpm@basic-rte:

  o {bat-dg2-9}: NOTRUN -> SKIP


 +2 similar issues


Known issues

Here are the changes found in Patchwork_108477v2 that come from known 
issues:



  IGT changes


Issues hit

  *

igt@gem_huc_copy@huc-copy:

  o fi-icl-u2: NOTRUN -> SKIP


 (i915#2190 )
  *

igt@gem_lmem_swapping@random-engines:

  o fi-icl-u2: NOTRUN -> SKIP


 (i915#4613 ) +3 similar issues
  *

igt@i915_pm_rpm@module-reload:

  o fi-cfl-8109u: PASS


 -> DMESG-FAIL 

 (i915#62 )
  *

igt@i915_selftest@live@ring_submission:

  o fi-cfl-8109u: PASS


 -> DMESG-WARN 

 (i915#5904 ) +30 similar issues
  *

igt@i915_suspend@basic-s2idle-without-i915:

  o fi-cfl-8109u: PASS


 -> DMESG-WARN 

 (i915#5904  / i915#62 
)
  *

igt@kms_chamelium@common-hpd-after-suspend:

  o fi-bdw-5557u: NOTRUN -> SKIP


 (fdo#109271  / fdo#111827 
)
  *

igt@kms_chamelium@hdmi-hpd-fast:

  o fi-icl-u2: NOTRUN -> SKIP


 (fdo#111827 

Re: [Intel-gfx] [PATCH 06/19] drm/i915/perf: Use helpers to process reports w.r.t. OA buffer size

[Dixit, Ashutosh]

On Tue, 23 Aug 2022 13:41:42 -0700, Umesh Nerlige Ramappa wrote:
>

Hi Umesh,

> diff --git a/drivers/gpu/drm/i915/i915_perf.c 
> b/drivers/gpu/drm/i915/i915_perf.c
> index 6fc4f0d8fc5a..bbf1c574f393 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -385,6 +385,21 @@ static struct ctl_table_header *sysctl_header;
>
>  static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
>
> +static u32 _oa_taken(struct i915_perf_stream * stream, u32 tail, u32 head)

nit: no space between * and stream.

> +{
> + u32 size = stream->oa_buffer.vma->size;
> +
> + return tail >= head ? tail - head : size - (head - tail);
> +}

If we are doing this we should probably eliminate references to OA_TAKEN
which serves an identical purpose (I think there is one remaining
reference) and also delete OA_TAKEN #define.

> +
> +static u32 _rewind_tail(struct i915_perf_stream * stream, u32 
> relative_hw_tail,
> + u32 rewind_delta)
> +{
> + return rewind_delta > relative_hw_tail ?
> +stream->oa_buffer.vma->size - (rewind_delta - relative_hw_tail) :
> +relative_hw_tail - rewind_delta;
> +}

Also are we really saying here that we are supporting non-power-of-2 OA
buffer sizes? Because if we stayed with power-of-2 sizes the expression
above are nice and elegant and actually closer to the previous code being
changed in this patch. For example:

#include 

static u32 _oa_taken(struct i915_perf_stream *stream, u32 tail, u32 head)
{
return CIRC_CNT(tail, head, stream->oa_buffer.vma->size);
}

static u32 _rewind_tail(struct i915_perf_stream *stream, u32 relative_hw_tail,
u32 rewind_delta)
{
return CIRC_CNT(relative_hw_tail, rewind_delta, 
stream->oa_buffer.vma->size);
}

Note that for power-of-2 sizes the two functions above are identical but we
should keep them separate for clarity (as is done in the patch) since they
are serving two different functions in the OA code.

Also another assumption in the code seems to be:

stream->oa_buffer.vma->size == OA_BUFFER_SIZE

which I am pretty sure will not hold for arbitrary non-power-of-2 OA buffer
sizes? So we might as well stick with power-of-2 sizes and change later in
a separate patch only if needed?

Thanks.
--
Ashutosh

> +
>  void i915_oa_config_release(struct kref *ref)
>  {
>   struct i915_oa_config *oa_config =
> @@ -487,12 +502,14 @@ static bool oa_buffer_check_unlocked(struct 
> i915_perf_stream *stream)
>* sizes need not be integral multiples or 64 or powers of 2.
>* Compute potentially partially landed report in the OA buffer
>*/
> - partial_report_size = OA_TAKEN(hw_tail, stream->oa_buffer.tail);
> + partial_report_size =
> + _oa_taken(stream, hw_tail, stream->oa_buffer.tail);
>   partial_report_size %= report_size;
>
>   /* Subtract partial amount off the tail */
> - hw_tail = gtt_offset + ((hw_tail - partial_report_size) &
> - (stream->oa_buffer.vma->size - 1));
> + hw_tail = gtt_offset + _rewind_tail(stream,
> + hw_tail - gtt_offset,
> + partial_report_size);
>
>   now = ktime_get_mono_fast_ns();
>
> @@ -527,16 +544,16 @@ static bool oa_buffer_check_unlocked(struct 
> i915_perf_stream *stream)
>* memory in the order they were written to.
>* If not : (╯°□°）╯︵ ┻━┻
>*/
> - while (OA_TAKEN(tail, aged_tail) >= report_size) {
> + while (_oa_taken(stream, tail, aged_tail) >= report_size) {
>   u32 *report32 = (void *)(stream->oa_buffer.vaddr + 
> tail);
>
>   if (report32[0] != 0 || report32[1] != 0)
>   break;
>
> - tail = (tail - report_size) & (OA_BUFFER_SIZE - 1);
> + tail = _rewind_tail(stream, tail, report_size);
>   }
>
> - if (OA_TAKEN(hw_tail, tail) > report_size &&
> + if (_oa_taken(stream, hw_tail, tail) > report_size &&
>   __ratelimit(>perf->tail_pointer_race))
>   DRM_NOTE("unlanded report(s) head=0x%x "
>"tail=0x%x hw_tail=0x%x\n",
> @@ -547,8 +564,9 @@ static bool oa_buffer_check_unlocked(struct 
> i915_perf_stream *stream)
>   stream->oa_buffer.aging_timestamp = now;
>   }
>
> - pollin = OA_TAKEN(stream->oa_buffer.tail - gtt_offset,
> -   stream->oa_buffer.head - gtt_offset) >= report_size;
> + pollin = _oa_taken(stream,
> +stream->oa_buffer.tail,
> +stream->oa_buffer.head) >= report_size;
>
>   spin_unlock_irqrestore(>oa_buffer.ptr_lock, flags);
>
> @@ -679,11 +697,9 @@ static int gen8_append_oa_reports(struct 
> i915_perf_stream *stream,
>   int report_size = 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: Really move i915_gem_context.link under ref protection (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/gem: Really move i915_gem_context.link under ref protection 
(rev2)
URL   : https://patchwork.freedesktop.org/series/105975/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12131_full -> Patchwork_105975v2_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_105975v2_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_105975v2_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105975v2_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-iclb: [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  
Known issues


  Here are the changes found in Patchwork_105975v2_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-skl:  ([PASS][3], [PASS][4], [PASS][5], [PASS][6], 
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], 
[PASS][25], [PASS][26]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], 
[PASS][31], [PASS][32], [PASS][33], [FAIL][34], [PASS][35], [PASS][36], 
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], 
[PASS][49], [PASS][50]) ([i915#5032])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl9/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl9/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl9/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl9/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl6/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl6/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl6/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl6/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl6/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl4/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl4/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl4/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl3/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl10/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl10/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl10/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl10/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl10/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl10/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl10/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl10/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl10/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl10/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl10/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl3/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl3/boot.html
   [35]: 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm (rev2)
URL   : https://patchwork.freedesktop.org/series/108477/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12134 -> Patchwork_108477v2


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_108477v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_108477v2, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/index.html

Participating hosts (40 -> 41)
--

  Additional (5): fi-icl-u2 bat-dg2-9 bat-adln-1 bat-rplp-1 bat-jsl-1 
  Missing(4): fi-ctg-p8600 fi-hsw-4770 fi-rkl-11600 fi-tgl-dsi 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_108477v2:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rpm@module-reload:
- bat-dg1-5:  [PASS][1] -> [SKIP][2] +2 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/bat-dg1-5/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/bat-dg1-5/igt@i915_pm_...@module-reload.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rpm@basic-pci-d3-state:
- {bat-dg2-8}:[PASS][3] -> [SKIP][4] +2 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/bat-dg2-8/igt@i915_pm_...@basic-pci-d3-state.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/bat-dg2-8/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_pm_rpm@basic-rte:
- {bat-dg2-9}:NOTRUN -> [SKIP][5] +2 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/bat-dg2-9/igt@i915_pm_...@basic-rte.html

  
Known issues


  Here are the changes found in Patchwork_108477v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][6] ([i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][7] ([i915#4613]) +3 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [PASS][8] -> [DMESG-FAIL][9] ([i915#62])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@ring_submission:
- fi-cfl-8109u:   [PASS][10] -> [DMESG-WARN][11] ([i915#5904]) +30 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u:   [PASS][12] -> [DMESG-WARN][13] ([i915#5904] / 
[i915#62])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-bdw-5557u:   NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-bdw-5557u/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][15] ([fdo#111827]) +8 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-icl-u2:  NOTRUN -> [SKIP][16] ([i915#4103])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-connector-state:
- fi-icl-u2:  NOTRUN -> [WARN][17] ([i915#6008])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108477v2/fi-icl-u2/igt@kms_force_connector_ba...@force-connector-state.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][18] ([fdo#109285])
   [18]: 

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gem: Really move i915_gem_context.link under ref protection

[Tvrtko Ursulin]

On 13/09/2022 17:10, Janusz Krzysztofik wrote:

From: Chris Wilson 

i915_perf assumes that it can use the i915_gem_context reference to
protect its i915->gem.contexts.list iteration. However, this requires
that we do not remove the context from the list until after we drop the
final reference and release the struct. If, as currently, we remove the
context from the list during context_close(), the link.next pointer may
be poisoned while we are holding the context reference and cause a GPF:

[ 4070.573157] i915 :00:02.0: [drm:i915_perf_open_ioctl [i915]] filtering 
on ctx_id=0x1f ctx_id_mask=0x1f
[ 4070.574881] general protection fault, probably for non-canonical address 
0xdead0100:  [#1] PREEMPT SMP
[ 4070.574897] CPU: 1 PID: 284392 Comm: amd_performance Tainted: GE 
5.17.9 #180
[ 4070.574903] Hardware name: Intel Corporation NUC7i5BNK/NUC7i5BNB, BIOS 
BNKBL357.86A.0052.2017.0918.1346 09/18/2017
[ 4070.574907] RIP: 0010:oa_configure_all_contexts.isra.0+0x222/0x350 [i915]
[ 4070.574982] Code: 08 e8 32 6e 10 e1 4d 8b 6d 50 b8 ff ff ff ff 49 83 ed 50 f0 41 
0f c1 04 24 83 f8 01 0f 84 e3 00 00 00 85 c0 0f 8e fa 00 00 00 <49> 8b 45 50 48 
8d 70 b0 49 8d 45 50 48 39 44 24 10 0f 85 34 fe ff
[ 4070.574990] RSP: 0018:c90002077b78 EFLAGS: 00010202
[ 4070.574995] RAX: 0002 RBX: 0002 RCX: 
[ 4070.575000] RDX: 0001 RSI: c90002077b20 RDI: 88810ddc7c68
[ 4070.575004] RBP: 0001 R08: 888103242648 R09: fffc
[ 4070.575008] R10: 82c50bc0 R11: 00025c80 R12: 888101bf1860
[ 4070.575012] R13: dead00b0 R14: c90002077c04 R15: 88810be5cabc
[ 4070.575016] FS:  7f1ed50c0780() GS:5ec8() 
knlGS:
[ 4070.575021] CS:  0010 DS:  ES:  CR0: 80050033
[ 4070.575025] CR2: 7f1ed5590280 CR3: 00010ef6f005 CR4: 003706e0
[ 4070.575029] Call Trace:
[ 4070.575033]  
[ 4070.575037]  lrc_configure_all_contexts+0x13e/0x150 [i915]
[ 4070.575103]  gen8_enable_metric_set+0x4d/0x90 [i915]
[ 4070.575164]  i915_perf_open_ioctl+0xbc0/0x1500 [i915]
[ 4070.575224]  ? asm_common_interrupt+0x1e/0x40
[ 4070.575232]  ? i915_oa_init_reg_state+0x110/0x110 [i915]
[ 4070.575290]  drm_ioctl_kernel+0x85/0x110
[ 4070.575296]  ? update_load_avg+0x5f/0x5e0
[ 4070.575302]  drm_ioctl+0x1d3/0x370
[ 4070.575307]  ? i915_oa_init_reg_state+0x110/0x110 [i915]
[ 4070.575382]  ? gen8_gt_irq_handler+0x46/0x130 [i915]
[ 4070.575445]  __x64_sys_ioctl+0x3c4/0x8d0
[ 4070.575451]  ? __do_softirq+0xaa/0x1d2
[ 4070.575456]  do_syscall_64+0x35/0x80
[ 4070.575461]  entry_SYSCALL_64_after_hwframe+0x44/0xae
[ 4070.575467] RIP: 0033:0x7f1ed5c10397
[ 4070.575471] Code: 3c 1c e8 1c ff ff ff 85 c0 79 87 49 c7 c4 ff ff ff ff 5b 5d 4c 
89 e0 41 5c c3 66 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff 
ff 73 01 c3 48 8b 0d a9 da 0d 00 f7 d8 64 89 01 48
[ 4070.575478] RSP: 002b:7ffd65c8d7a8 EFLAGS: 0246 ORIG_RAX: 
0010
[ 4070.575484] RAX: ffda RBX: 0006 RCX: 7f1ed5c10397
[ 4070.575488] RDX: 7ffd65c8d7c0 RSI: 40106476 RDI: 0006
[ 4070.575492] RBP: 5620972f9c60 R08: 000a R09: 0005
[ 4070.575496] R10: 000d R11: 0246 R12: 000a
[ 4070.575500] R13: 000d R14:  R15: 7ffd65c8d7c0
[ 4070.575505]  
[ 4070.575507] Modules linked in: nls_ascii(E) nls_cp437(E) vfat(E) fat(E) 
i915(E) x86_pkg_temp_thermal(E) intel_powerclamp(E) crct10dif_pclmul(E) 
crc32_pclmul(E) crc32c_intel(E) aesni_intel(E) crypto_simd(E) intel_gtt(E) 
cryptd(E) ttm(E) rapl(E) intel_cstate(E) drm_kms_helper(E) cfbfillrect(E) 
syscopyarea(E) cfbimgblt(E) intel_uncore(E) sysfillrect(E) mei_me(E) 
sysimgblt(E) i2c_i801(E) fb_sys_fops(E) mei(E) intel_pch_thermal(E) 
i2c_smbus(E) cfbcopyarea(E) video(E) button(E) efivarfs(E) autofs4(E)
[ 4070.575549] ---[ end trace  ]---

Reported-by: Mark Janes 
Closes: https://gitlab.freedesktop.org/drm/intel/issues/6222
References: a4e7ccdac38e ("drm/i915: Move context management under GEM")
Fixes: f8246cf4d9a9 ("drm/i915/gem: Drop free_work for GEM contexts")
Signed-off-by: Chris Wilson 
Reviewed-by: Andi Shyti 
Signed-off-by: Andi Shyti 
Signed-off-by: Janusz Krzysztofik 
Cc: Tvrtko Ursulin 
Cc:  # v5.12+
---
  drivers/gpu/drm/i915/gem/i915_gem_context.c | 14 +++---
  drivers/gpu/drm/i915/i915_perf.c| 18 ++
  drivers/gpu/drm/i915/i915_sysfs.c   |  8 
  3 files changed, 21 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index dabdfe09f5e51..9d7142ab63c05 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1133,7 +1133,6 @@ static struct i915_gem_engines *default_engines(struct 

Re: [Intel-gfx] [PATCH] drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm

[Andi Shyti]

Hi Anshuman,

[...]

> > > > +*  which really disables the PCIe power savings and leaves the 
> > > > bridge to
> > D0
> > > > +*  state.
> > > > +*  Let's disable i915 rpm till we fix all known issue with 
> > > > lmem access in
> > D3.
> > > > +*/
> > > > +   .has_runtime_pm = 0,
> > > >  };
> > > >
> > > >  static const struct intel_device_info adl_s_info = { @@ -1076,6
> > > > +1096,7 @@ static const struct intel_device_info dg2_info = {
> > > > XE_LPD_FEATURES,
> > > > .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) |
> > BIT(TRANSCODER_B) |
> > > >BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> > > > +   .has_runtime_pm = 0,
> > >
> > > The FIXME msg can be smaller, but it also needs to be here.
> > 
> > I actually like the comment, is very clear and helps understanding the 
> > issue :)
> Shall I move the comment to commit log , and keep a smaller comment for both 
> DG1 and DG2 ?
> With that I can address your comment and Rodrigo comment as well.
> Keeping such a big comment at two places will not make any sense.

OK for me!

Thanks!
Andi

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: A couple of if/else ladder refactors (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: A couple of if/else ladder refactors (rev2)
URL   : https://patchwork.freedesktop.org/series/108315/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12132_full -> Patchwork_108315v2_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_108315v2_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_108315v2_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_108315v2_full:

### IGT changes ###

 Possible regressions 

  * igt@gen9_exec_parse@bb-large:
- shard-apl:  [PASS][1] -> [TIMEOUT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/igt@gen9_exec_pa...@bb-large.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v2/shard-apl2/igt@gen9_exec_pa...@bb-large.html

  
Known issues


  Here are the changes found in Patchwork_108315v2_full that come from known 
issues:

### CI changes ###

 Possible fixes 

  * boot:
- shard-apl:  ([FAIL][3], [PASS][4], [PASS][5], [PASS][6], 
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], 
[PASS][25], [PASS][26], [PASS][27]) ([i915#4386]) -> ([PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], 
[PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl1/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl2/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl3/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl3/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl3/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl4/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl6/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl7/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl7/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl7/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl8/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl8/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12132/shard-apl8/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v2/shard-apl8/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v2/shard-apl8/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v2/shard-apl8/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v2/shard-apl8/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v2/shard-apl7/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v2/shard-apl7/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v2/shard-apl7/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108315v2/shard-apl7/boot.html
   [36]: 

Re: [Intel-gfx] [PATCH 2/2] drm/i915/gem: Really move i915_gem_context.link under ref protection

[Andi Shyti]

Hi Krzysztofik,

if you are going to resend it, I just have a little thing if you
don't mind,

On Tue, Sep 13, 2022 at 06:10:39PM +0200, Janusz Krzysztofik wrote:
> From: Chris Wilson 
> 
> i915_perf assumes that it can use the i915_gem_context reference to
> protect its i915->gem.contexts.list iteration. However, this requires
> that we do not remove the context from the list until after we drop the
> final reference and release the struct. If, as currently, we remove the
> context from the list during context_close(), the link.next pointer may
> be poisoned while we are holding the context reference and cause a GPF:
> 
> [ 4070.573157] i915 :00:02.0: [drm:i915_perf_open_ioctl [i915]] filtering 
> on ctx_id=0x1f ctx_id_mask=0x1f
> [ 4070.574881] general protection fault, probably for non-canonical address 
> 0xdead0100:  [#1] PREEMPT SMP
> [ 4070.574897] CPU: 1 PID: 284392 Comm: amd_performance Tainted: G
> E 5.17.9 #180
> [ 4070.574903] Hardware name: Intel Corporation NUC7i5BNK/NUC7i5BNB, BIOS 
> BNKBL357.86A.0052.2017.0918.1346 09/18/2017
> [ 4070.574907] RIP: 0010:oa_configure_all_contexts.isra.0+0x222/0x350 [i915]
> [ 4070.574982] Code: 08 e8 32 6e 10 e1 4d 8b 6d 50 b8 ff ff ff ff 49 83 ed 50 
> f0 41 0f c1 04 24 83 f8 01 0f 84 e3 00 00 00 85 c0 0f 8e fa 00 00 00 <49> 8b 
> 45 50 48 8d 70 b0 49 8d 45 50 48 39 44 24 10 0f 85 34 fe ff
> [ 4070.574990] RSP: 0018:c90002077b78 EFLAGS: 00010202
> [ 4070.574995] RAX: 0002 RBX: 0002 RCX: 
> 
> [ 4070.575000] RDX: 0001 RSI: c90002077b20 RDI: 
> 88810ddc7c68
> [ 4070.575004] RBP: 0001 R08: 888103242648 R09: 
> fffc
> [ 4070.575008] R10: 82c50bc0 R11: 00025c80 R12: 
> 888101bf1860
> [ 4070.575012] R13: dead00b0 R14: c90002077c04 R15: 
> 88810be5cabc
> [ 4070.575016] FS:  7f1ed50c0780() GS:5ec8() 
> knlGS:
> [ 4070.575021] CS:  0010 DS:  ES:  CR0: 80050033
> [ 4070.575025] CR2: 7f1ed5590280 CR3: 00010ef6f005 CR4: 
> 003706e0
> [ 4070.575029] Call Trace:
> [ 4070.575033]  
> [ 4070.575037]  lrc_configure_all_contexts+0x13e/0x150 [i915]
> [ 4070.575103]  gen8_enable_metric_set+0x4d/0x90 [i915]
> [ 4070.575164]  i915_perf_open_ioctl+0xbc0/0x1500 [i915]
> [ 4070.575224]  ? asm_common_interrupt+0x1e/0x40
> [ 4070.575232]  ? i915_oa_init_reg_state+0x110/0x110 [i915]
> [ 4070.575290]  drm_ioctl_kernel+0x85/0x110
> [ 4070.575296]  ? update_load_avg+0x5f/0x5e0
> [ 4070.575302]  drm_ioctl+0x1d3/0x370
> [ 4070.575307]  ? i915_oa_init_reg_state+0x110/0x110 [i915]
> [ 4070.575382]  ? gen8_gt_irq_handler+0x46/0x130 [i915]
> [ 4070.575445]  __x64_sys_ioctl+0x3c4/0x8d0
> [ 4070.575451]  ? __do_softirq+0xaa/0x1d2
> [ 4070.575456]  do_syscall_64+0x35/0x80
> [ 4070.575461]  entry_SYSCALL_64_after_hwframe+0x44/0xae
> [ 4070.575467] RIP: 0033:0x7f1ed5c10397
> [ 4070.575471] Code: 3c 1c e8 1c ff ff ff 85 c0 79 87 49 c7 c4 ff ff ff ff 5b 
> 5d 4c 89 e0 41 5c c3 66 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 
> 01 f0 ff ff 73 01 c3 48 8b 0d a9 da 0d 00 f7 d8 64 89 01 48
> [ 4070.575478] RSP: 002b:7ffd65c8d7a8 EFLAGS: 0246 ORIG_RAX: 
> 0010
> [ 4070.575484] RAX: ffda RBX: 0006 RCX: 
> 7f1ed5c10397
> [ 4070.575488] RDX: 7ffd65c8d7c0 RSI: 40106476 RDI: 
> 0006
> [ 4070.575492] RBP: 5620972f9c60 R08: 000a R09: 
> 0005
> [ 4070.575496] R10: 000d R11: 0246 R12: 
> 000a
> [ 4070.575500] R13: 000d R14:  R15: 
> 7ffd65c8d7c0
> [ 4070.575505]  
> [ 4070.575507] Modules linked in: nls_ascii(E) nls_cp437(E) vfat(E) fat(E) 
> i915(E) x86_pkg_temp_thermal(E) intel_powerclamp(E) crct10dif_pclmul(E) 
> crc32_pclmul(E) crc32c_intel(E) aesni_intel(E) crypto_simd(E) intel_gtt(E) 
> cryptd(E) ttm(E) rapl(E) intel_cstate(E) drm_kms_helper(E) cfbfillrect(E) 
> syscopyarea(E) cfbimgblt(E) intel_uncore(E) sysfillrect(E) mei_me(E) 
> sysimgblt(E) i2c_i801(E) fb_sys_fops(E) mei(E) intel_pch_thermal(E) 
> i2c_smbus(E) cfbcopyarea(E) video(E) button(E) efivarfs(E) autofs4(E)
> [ 4070.575549] ---[ end trace  ]---
> 
> Reported-by: Mark Janes 
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/6222
> References: a4e7ccdac38e ("drm/i915: Move context management under GEM")
> Fixes: f8246cf4d9a9 ("drm/i915/gem: Drop free_work for GEM contexts")
> Signed-off-by: Chris Wilson 
> Reviewed-by: Andi Shyti 
> Signed-off-by: Andi Shyti 
> Signed-off-by: Janusz Krzysztofik 
> Cc: Tvrtko Ursulin 
> Cc:  # v5.12+
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_context.c | 14 +++---
>  drivers/gpu/drm/i915/i915_perf.c| 18 ++
>  drivers/gpu/drm/i915/i915_sysfs.c   |  8 
>  3 files changed, 21 insertions(+), 19 deletions(-)
> 
> diff --git 

Re: [Intel-gfx] [topic/core-for-CI] Revert "iommu/dma: Fix race condition during iova_domain initialization"

[Lucas De Marchi]

On Wed, Sep 14, 2022 at 02:40:45PM +0200, Karolina Drobnik wrote:

This reverts commit ac9a5d522bb80be50ea84965699e1c8257d745ce.

This change introduces a regression on Alder Lake that completely
blocks testing. To enable CI and avoid possible circular locking
warning, revert the patch.


We are already on rc5. Are iommu authors involved aware of this issue?
We could do this in our "for CI only" branch, but it's equally important
that this is fixed for 6.0

Cc'ing them.

thanks
Lucas De Marchi



kernel log:

==
WARNING: possible circular locking dependency detected
6.0.0-rc5-CI_DRM_12132-g6c93e979e542+ #1 Not tainted
--
cpuhp/0/15 is trying to acquire lock:
8881013df278 (&(>bus_notifier)->rwsem){}-{3:3}, at: 
blocking_notifier_call_chain+0x20/0x50
 but task is already holding lock:
826490c0 (cpuhp_state-up){+.+.}-{0:0}, at: cpuhp_thread_fun+0x48/0x1f0
 which lock already depends on the new loc
 the existing dependency chain (in reverse order) is:
 -> #3 (cpuhp_state-up){+.+.}-{0:0}:
  lock_acquire+0xd3/0x310
  cpuhp_thread_fun+0xa6/0x1f0
  smpboot_thread_fn+0x1b5/0x260
  kthread+0xed/0x120
  ret_from_fork+0x1f/0x30
 -> #2 (cpu_hotplug_lock){}-{0:0}:
  lock_acquire+0xd3/0x310
  __cpuhp_state_add_instance+0x43/0x1c0
  iova_domain_init_rcaches+0x199/0x1c0
  iommu_setup_dma_ops+0x130/0x440
  bus_iommu_probe+0x26a/0x2d0
  bus_set_iommu+0x82/0xd0
  intel_iommu_init+0xe33/0x1039
  pci_iommu_init+0x9/0x31
  do_one_initcall+0x53/0x2f0
  kernel_init_freeable+0x18f/0x1e1
  kernel_init+0x11/0x120
  ret_from_fork+0x1f/0x30
 -> #1 (>iova_cookie->mutex){+.+.}-{3:3}:
  lock_acquire+0xd3/0x310
  __mutex_lock+0x97/0xf10
  iommu_setup_dma_ops+0xd7/0x440
  iommu_probe_device+0xa4/0x180
  iommu_bus_notifier+0x2d/0x40
  notifier_call_chain+0x31/0x90
  blocking_notifier_call_chain+0x3a/0x50
  device_add+0x3c1/0x900
  pci_device_add+0x255/0x580
  pci_scan_single_device+0xa6/0xd0
  pci_scan_slot+0x7a/0x1b0
  pci_scan_child_bus_extend+0x35/0x2a0
  vmd_probe+0x5cd/0x970
  pci_device_probe+0x95/0x110
  really_probe+0xd6/0x350
  __driver_probe_device+0x73/0x170
  driver_probe_device+0x1a/0x90
  __driver_attach+0xbc/0x190
  bus_for_each_dev+0x72/0xc0
  bus_add_driver+0x1bb/0x210
  driver_register+0x66/0xc0
  do_one_initcall+0x53/0x2f0
  kernel_init_freeable+0x18f/0x1e1
  kernel_init+0x11/0x120
  ret_from_fork+0x1f/0x30
 -> #0 (&(>bus_notifier)->rwsem){}-{3:3}:
  validate_chain+0xb3f/0x2000
  __lock_acquire+0x5a4/0xb70
  lock_acquire+0xd3/0x310
  down_read+0x39/0x140
  blocking_notifier_call_chain+0x20/0x50
  device_add+0x3c1/0x900
  platform_device_add+0x108/0x240
  coretemp_cpu_online+0xe1/0x15e [coretemp]
  cpuhp_invoke_callback+0x181/0x8a0
  cpuhp_thread_fun+0x188/0x1f0
  smpboot_thread_fn+0x1b5/0x260
  kthread+0xed/0x120
  ret_from_fork+0x1f/0x30
 other info that might help us debug thi
Chain exists of &(>bus_notifier)->rwsem --> cpu_hotplug_lock 
--> cpuhp_state-
Possible unsafe locking scenari
  CPU0CPU1
  
 lock(cpuhp_state-up);
  lock(cpu_hotplug_lock);
  lock(cpuhp_state-up);
 lock(&(>bus_notifier)->rwsem);
  *** DEADLOCK *
2 locks held by cpuhp/0/15:
#0: 82648f10 (cpu_hotplug_lock){}-{0:0}, at: 
cpuhp_thread_fun+0x48/0x1f0
#1: 826490c0 (cpuhp_state-up){+.+.}-{0:0}, at: 
cpuhp_thread_fun+0x48/0x1f0
 stack backtrace:
CPU: 0 PID: 15 Comm: cpuhp/0 Not tainted 6.0.0-rc5-CI_DRM_12132-g6c93e979e542+ 
#1
Hardware name: Intel Corporation Alder Lake Client Platform/AlderLake-P DDR4 
RVP, BIOS ADLPFWI1.R00.3135.A00.2203251419 03/25/2022
Call Trace:

dump_stack_lvl+0x56/0x7f
check_noncircular+0x132/0x150
validate_chain+0xb3f/0x2000
__lock_acquire+0x5a4/0xb70
lock_acquire+0xd3/0x310
? blocking_notifier_call_chain+0x20/0x50
down_read+0x39/0x140
? blocking_notifier_call_chain+0x20/0x50
blocking_notifier_call_chain+0x20/0x50
device_add+0x3c1/0x900
? dev_set_name+0x4e/0x70
platform_device_add+0x108/0x240
coretemp_cpu_online+0xe1/0x15e [coretemp]
? create_core_data+0x550/0x550 [coretemp]
cpuhp_invoke_callback+0x181/0x8a0
cpuhp_thread_fun+0x188/0x1f0
? smpboot_thread_fn+0x1e/0x260
smpboot_thread_fn+0x1b5/0x260
? sort_range+0x20/0x20
kthread+0xed/0x120
? kthread_complete_and_exit+0x20/0x20
ret_from_fork+0x1f/0x30


Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6641

Signed-off-by: Karolina Drobnik 
Cc: Lucas De Marchi 
---
drivers/iommu/dma-iommu.c | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)

diff 

Re: [Intel-gfx] [PATCH] drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm

[Gupta, Anshuman]

> -Original Message-
> From: Andi Shyti 
> Sent: Wednesday, September 14, 2022 8:13 PM
> To: Vivi, Rodrigo 
> Cc: Gupta, Anshuman ; intel-
> g...@lists.freedesktop.org; joonas.lahti...@linux.intel.com; Ewins, Jon
> ; andi.sh...@linux.intel.com; Auld, Matthew
> 
> Subject: Re: [PATCH] drm/i915/DG{1,2}: FIXME Temporary hammer to disable
> rpm
> 
> Hi Anshuman,
> 
> On Wed, Sep 14, 2022 at 10:33:15AM -0400, Rodrigo Vivi wrote:
> > On Wed, Sep 14, 2022 at 07:45:53PM +0530, Anshuman Gupta wrote:
> > > DG1 and DG2 has lmem, and cpu can access the lmem objects via mmap
> > > and i915 internal i915_gem_object_pin_map() for
> > > i915 own usages. Both of these methods has pre-requisite requirement
> > > to keep GFX PCI endpoint in D0 for a supported iomem transaction
> > > over PCI link. (Refer PCIe specs 5.3.1.4.1)
> > >
> > > TODO:
> > > With respect to i915_gem_object_pin_map(), every caller has to grab
> > > a wakeref if gem object lies in lmem.
> > >
> > > Till we fix all issues related to runtime PM, we need to keep
> > > runtime PM disable on both DG1 and DG2.
> > >
> > > Cc: Matthew Auld 
> > > Cc: Rodrigo Vivi 
> > > Signed-off-by: Anshuman Gupta 
> > > ---
> > >  drivers/gpu/drm/i915/i915_pci.c | 21 +
> > >  1 file changed, 21 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > > b/drivers/gpu/drm/i915/i915_pci.c index 77e7df21f539..f31d7f5399cc
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -931,6 +931,26 @@ static const struct intel_device_info dg1_info = {
> > >   BIT(VCS0) | BIT(VCS2),
> > >   /* Wa_16011227922 */
> > >   .__runtime.ppgtt_size = 47,
> > > +
> > > + /*
> > > +  *  FIXME: Temporary hammer to disable rpm.
> > > +  *  As per PCIe specs 5.3.1.4.1, all iomem read write request over a 
> > > PCIe
> > > +  *  function will be unsupported in case PCIe endpoint function is in 
> > > D3.
> > > +  *  But both DG1/DG2 has a hardware bug that violates the PCIe
> > > +specs
> 
> /has/have/
> 
> > > +  *  and supports the iomem read write transaction over PCIe bus
> > > +despite
> 
> /supports/support/
> 
> > > +  *  endpoint is D3 state.
> > > +  *  Due to above H/W bug, we had never observed any issue with i915
> runtime
> > > +  *  PM versus lmem access.
> > > +  *  But this issue gets discover when PCIe gfx endpoint's upstream
> 
> /gets discover/becomes visible/
> 
> > > +  *  bridge enters to D3, at this point any lmem read/write access will 
> > > be
> > > +  *  returned as unsupported request. But again this issue is not 
> > > observed
> > > +  *  on every platform because it has been observed on few host
> machines
> > > +  *  DG1/DG2 endpoint's upstream bridge does not binds with pcieport
> driver.
> 
> /binds/bind/
> 
> > > +  *  which really disables the PCIe power savings and leaves the bridge 
> > > to
> D0
> > > +  *  state.
> > > +  *  Let's disable i915 rpm till we fix all known issue with lmem access 
> > > in
> D3.
> > > +  */
> > > + .has_runtime_pm = 0,
> > >  };
> > >
> > >  static const struct intel_device_info adl_s_info = { @@ -1076,6
> > > +1096,7 @@ static const struct intel_device_info dg2_info = {
> > >   XE_LPD_FEATURES,
> > >   .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) |
> BIT(TRANSCODER_B) |
> > >  BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> > > + .has_runtime_pm = 0,
> >
> > The FIXME msg can be smaller, but it also needs to be here.
> 
> I actually like the comment, is very clear and helps understanding the issue 
> :)
Shall I move the comment to commit log , and keep a smaller comment for both 
DG1 and DG2 ?
With that I can address your comment and Rodrigo comment as well.
Keeping such a big comment at two places will not make any sense.
Thanks,
Anshuman Gupta.
> 
> Thanks again for addressing the issue and with the hope to see the proper fix
> soon:
> 
> Reviewed-by: Andi Shyti 
> 
> Thanks,
> Andi
> 
> > With this in place fell free to use:
> >
> > Reviewed-by: Rodrigo Vivi 
> >
> > Since the proper solution might take a while let's protect from this
> > case, regardless of any other on going discussion about the force_probe
> protection.
> >
> >
> > >   .require_force_probe = 1,
> > >  };
> > >
> > > --
> > > 2.26.2
> > >

Re: [Intel-gfx] [PATCH] drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm

[Andi Shyti]

Hi Anshuman,

On Wed, Sep 14, 2022 at 10:33:15AM -0400, Rodrigo Vivi wrote:
> On Wed, Sep 14, 2022 at 07:45:53PM +0530, Anshuman Gupta wrote:
> > DG1 and DG2 has lmem, and cpu can access the lmem objects
> > via mmap and i915 internal i915_gem_object_pin_map() for
> > i915 own usages. Both of these methods has pre-requisite
> > requirement to keep GFX PCI endpoint in D0 for a supported
> > iomem transaction over PCI link. (Refer PCIe specs 5.3.1.4.1)
> > 
> > TODO:
> > With respect to i915_gem_object_pin_map(), every caller
> > has to grab a wakeref if gem object lies in lmem.
> > 
> > Till we fix all issues related to runtime PM, we need
> > to keep runtime PM disable on both DG1 and DG2.
> > 
> > Cc: Matthew Auld 
> > Cc: Rodrigo Vivi 
> > Signed-off-by: Anshuman Gupta 
> > ---
> >  drivers/gpu/drm/i915/i915_pci.c | 21 +
> >  1 file changed, 21 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c 
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index 77e7df21f539..f31d7f5399cc 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -931,6 +931,26 @@ static const struct intel_device_info dg1_info = {
> > BIT(VCS0) | BIT(VCS2),
> > /* Wa_16011227922 */
> > .__runtime.ppgtt_size = 47,
> > +
> > +   /*
> > +*  FIXME: Temporary hammer to disable rpm.
> > +*  As per PCIe specs 5.3.1.4.1, all iomem read write request over a 
> > PCIe
> > +*  function will be unsupported in case PCIe endpoint function is in 
> > D3.
> > +*  But both DG1/DG2 has a hardware bug that violates the PCIe specs

/has/have/

> > +*  and supports the iomem read write transaction over PCIe bus despite

/supports/support/

> > +*  endpoint is D3 state.
> > +*  Due to above H/W bug, we had never observed any issue with i915 
> > runtime
> > +*  PM versus lmem access.
> > +*  But this issue gets discover when PCIe gfx endpoint's upstream

/gets discover/becomes visible/

> > +*  bridge enters to D3, at this point any lmem read/write access will 
> > be
> > +*  returned as unsupported request. But again this issue is not 
> > observed
> > +*  on every platform because it has been observed on few host machines
> > +*  DG1/DG2 endpoint's upstream bridge does not binds with pcieport 
> > driver.

/binds/bind/

> > +*  which really disables the PCIe power savings and leaves the bridge 
> > to D0
> > +*  state.
> > +*  Let's disable i915 rpm till we fix all known issue with lmem access 
> > in D3.
> > +*/
> > +   .has_runtime_pm = 0,
> >  };
> >  
> >  static const struct intel_device_info adl_s_info = {
> > @@ -1076,6 +1096,7 @@ static const struct intel_device_info dg2_info = {
> > XE_LPD_FEATURES,
> > .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> >BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> > +   .has_runtime_pm = 0,
> 
> The FIXME msg can be smaller, but it also needs to be here.

I actually like the comment, is very clear and helps
understanding the issue :)

Thanks again for addressing the issue and with the hope to see
the proper fix soon:

Reviewed-by: Andi Shyti 

Thanks,
Andi

> With this in place fell free to use:
> 
> Reviewed-by: Rodrigo Vivi 
> 
> Since the proper solution might take a while let's protect from this case,
> regardless of any other on going discussion about the force_probe protection.
> 
> 
> > .require_force_probe = 1,
> >  };
> >  
> > -- 
> > 2.26.2
> > 

Re: [Intel-gfx] [PATCH] drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm

[Rodrigo Vivi]

On Wed, Sep 14, 2022 at 07:45:53PM +0530, Anshuman Gupta wrote:
> DG1 and DG2 has lmem, and cpu can access the lmem objects
> via mmap and i915 internal i915_gem_object_pin_map() for
> i915 own usages. Both of these methods has pre-requisite
> requirement to keep GFX PCI endpoint in D0 for a supported
> iomem transaction over PCI link. (Refer PCIe specs 5.3.1.4.1)
> 
> TODO:
> With respect to i915_gem_object_pin_map(), every caller
> has to grab a wakeref if gem object lies in lmem.
> 
> Till we fix all issues related to runtime PM, we need
> to keep runtime PM disable on both DG1 and DG2.
> 
> Cc: Matthew Auld 
> Cc: Rodrigo Vivi 
> Signed-off-by: Anshuman Gupta 
> ---
>  drivers/gpu/drm/i915/i915_pci.c | 21 +
>  1 file changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 77e7df21f539..f31d7f5399cc 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -931,6 +931,26 @@ static const struct intel_device_info dg1_info = {
>   BIT(VCS0) | BIT(VCS2),
>   /* Wa_16011227922 */
>   .__runtime.ppgtt_size = 47,
> +
> + /*
> +  *  FIXME: Temporary hammer to disable rpm.
> +  *  As per PCIe specs 5.3.1.4.1, all iomem read write request over a 
> PCIe
> +  *  function will be unsupported in case PCIe endpoint function is in 
> D3.
> +  *  But both DG1/DG2 has a hardware bug that violates the PCIe specs
> +  *  and supports the iomem read write transaction over PCIe bus despite
> +  *  endpoint is D3 state.
> +  *  Due to above H/W bug, we had never observed any issue with i915 
> runtime
> +  *  PM versus lmem access.
> +  *  But this issue gets discover when PCIe gfx endpoint's upstream
> +  *  bridge enters to D3, at this point any lmem read/write access will 
> be
> +  *  returned as unsupported request. But again this issue is not 
> observed
> +  *  on every platform because it has been observed on few host machines
> +  *  DG1/DG2 endpoint's upstream bridge does not binds with pcieport 
> driver.
> +  *  which really disables the PCIe power savings and leaves the bridge 
> to D0
> +  *  state.
> +  *  Let's disable i915 rpm till we fix all known issue with lmem access 
> in D3.
> +  */
> + .has_runtime_pm = 0,
>  };
>  
>  static const struct intel_device_info adl_s_info = {
> @@ -1076,6 +1096,7 @@ static const struct intel_device_info dg2_info = {
>   XE_LPD_FEATURES,
>   .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>  BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> + .has_runtime_pm = 0,

The FIXME msg can be smaller, but it also needs to be here.

With this in place fell free to use:

Reviewed-by: Rodrigo Vivi 

Since the proper solution might take a while let's protect from this case,
regardless of any other on going discussion about the force_probe protection.


>   .require_force_probe = 1,
>  };
>  
> -- 
> 2.26.2
> 

[Intel-gfx] [PATCH] drm/i915/DG{1, 2}: FIXME Temporary hammer to disable rpm

[Anshuman Gupta]

DG1 and DG2 has lmem, and cpu can access the lmem objects
via mmap and i915 internal i915_gem_object_pin_map() for
i915 own usages. Both of these methods has pre-requisite
requirement to keep GFX PCI endpoint in D0 for a supported
iomem transaction over PCI link. (Refer PCIe specs 5.3.1.4.1)

TODO:
With respect to i915_gem_object_pin_map(), every caller
has to grab a wakeref if gem object lies in lmem.

Till we fix all issues related to runtime PM, we need
to keep runtime PM disable on both DG1 and DG2.

Cc: Matthew Auld 
Cc: Rodrigo Vivi 
Signed-off-by: Anshuman Gupta 
---
 drivers/gpu/drm/i915/i915_pci.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 77e7df21f539..f31d7f5399cc 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -931,6 +931,26 @@ static const struct intel_device_info dg1_info = {
BIT(VCS0) | BIT(VCS2),
/* Wa_16011227922 */
.__runtime.ppgtt_size = 47,
+
+   /*
+*  FIXME: Temporary hammer to disable rpm.
+*  As per PCIe specs 5.3.1.4.1, all iomem read write request over a 
PCIe
+*  function will be unsupported in case PCIe endpoint function is in 
D3.
+*  But both DG1/DG2 has a hardware bug that violates the PCIe specs
+*  and supports the iomem read write transaction over PCIe bus despite
+*  endpoint is D3 state.
+*  Due to above H/W bug, we had never observed any issue with i915 
runtime
+*  PM versus lmem access.
+*  But this issue gets discover when PCIe gfx endpoint's upstream
+*  bridge enters to D3, at this point any lmem read/write access will 
be
+*  returned as unsupported request. But again this issue is not 
observed
+*  on every platform because it has been observed on few host machines
+*  DG1/DG2 endpoint's upstream bridge does not binds with pcieport 
driver.
+*  which really disables the PCIe power savings and leaves the bridge 
to D0
+*  state.
+*  Let's disable i915 rpm till we fix all known issue with lmem access 
in D3.
+*/
+   .has_runtime_pm = 0,
 };
 
 static const struct intel_device_info adl_s_info = {
@@ -1076,6 +1096,7 @@ static const struct intel_device_info dg2_info = {
XE_LPD_FEATURES,
.__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
   BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+   .has_runtime_pm = 0,
.require_force_probe = 1,
 };
 
-- 
2.26.2

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: Really move i915_gem_context.link under ref protection (rev2)

[Andi Shyti]

Hi,

> Possible new issues
> 
>Here are the unknown changes that may have been introduced in
>Patchwork_105975v2_full:
> 
>   IGT changes
> 
> Possible regressions
> 
>  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc
>:
>   + shard-iclb: [3]PASS -> [4]DMESG-WARN
>  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-edp-1:
>   + shard-iclb: [5]PASS -> [6]INCOMPLETE

this looks unrelated to the patch.

Andi

Re: [Intel-gfx] [PATCH 1/2] drm/i915/gem: Flush contexts on driver release

[Andi Shyti]

Hi Krzysztofik,

On Tue, Sep 13, 2022 at 06:10:38PM +0200, Janusz Krzysztofik wrote:
> Due to i915_perf assuming that it can use the i915_gem_context reference
> to protect its i915->gem.contexts.list iteration, we need to defer removal
> of the context from the list until last reference to the context is put.
> However, there is a risk of triggering kernel warning on contexts list not
> empty at driver release time if we deleagate that task to a worker for
> i915_gem_context_release_work(), unless that work is flushed first.
> Unfortunately, it is not flushed on driver release.  Fix it.
> 
> Instead of additionally calling flush_workqueue(), either directly of via
> a new dedicated wrapper around it, replace last call to
> i915_gem_drain_freed_objects() with existing i915_gem_drain_workqueue()
> that performs both tasks.
> 
> Fixes: 75eefd82581f ("drm/i915: Release i915_gem_context from a worker")
> Suggested-by: Chris Wilson 
> Signed-off-by: Janusz Krzysztofik 
> Cc: sta...@kernel.org # v5.16+

Thanks for the fix and for taking this on you!

Reviewed-by: Andi Shyti 

Andi

> ---
>  drivers/gpu/drm/i915/i915_gem.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index a3373699835d7..31c197f2d8cb9 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1191,7 +1191,8 @@ void i915_gem_driver_release(struct drm_i915_private 
> *dev_priv)
>  
>   intel_uc_cleanup_firmwares(_gt(dev_priv)->uc);
>  
> - i915_gem_drain_freed_objects(dev_priv);
> + /* Flush any outstanding work, including i915_gem_context.release_work. 
> */
> + i915_gem_drain_workqueue(dev_priv);
>  
>   drm_WARN_ON(_priv->drm, !list_empty(_priv->gem.contexts.list));
>  }
> -- 
> 2.25.1

Re: [Intel-gfx] [PATCH] drm/i915: Fix return type of mode_valid function hook

[Andrzej Hajda]

On 13.09.2022 22:55, Nathan Huckleberry wrote:

All of the functions used for intel_dvo_dev_ops.mode_valid have a return
type of enum drm_mode_status, but the mode_valid field in the struct
definition has a return type of int.

The mismatched return type breaks forward edge kCFI since the underlying
function definitions do not match the function hook definition.

The return type of the mode_valid field should be changed from int to
enum drm_mode_status.

Reported-by: Dan Carpenter 
Link: https://github.com/ClangBuiltLinux/linux/issues/1703
Cc: l...@lists.linux.dev
Signed-off-by: Nathan Huckleberry 


Reviewed-by: Andrzej Hajda 

Regards
Andrzej


---
  drivers/gpu/drm/i915/display/intel_dvo_dev.h | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dvo_dev.h 
b/drivers/gpu/drm/i915/display/intel_dvo_dev.h
index d96c3cc46e50..50205f064d93 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo_dev.h
+++ b/drivers/gpu/drm/i915/display/intel_dvo_dev.h
@@ -75,8 +75,8 @@ struct intel_dvo_dev_ops {
 *
 * \return MODE_OK if the mode is valid, or another MODE_* otherwise.
 */
-   int (*mode_valid)(struct intel_dvo_device *dvo,
- struct drm_display_mode *mode);
+   enum drm_mode_status (*mode_valid)(struct intel_dvo_device *dvo,
+  struct drm_display_mode *mode);
  
  	/*

 * Callback for preparing mode changes on an output

[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "iommu/dma: Fix race condition during iova_domain initialization"

[Patchwork]

== Series Details ==

Series: Revert "iommu/dma: Fix race condition during iova_domain initialization"
URL   : https://patchwork.freedesktop.org/series/108557/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12134 -> Patchwork_108557v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108557v1/index.html

Participating hosts (40 -> 41)
--

  Additional (3): bat-adln-1 fi-icl-u2 bat-dg2-9 
  Missing(2): fi-ctg-p8600 fi-tgl-dsi 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_108557v1:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rps@basic-api:
- {bat-adlm-1}:   NOTRUN -> [SKIP][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108557v1/bat-adlm-1/igt@i915_pm_...@basic-api.html

  
Known issues


  Here are the changes found in Patchwork_108557v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][2] ([i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108557v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108557v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[PASS][4] -> [DMESG-FAIL][5] ([i915#4528])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108557v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-bdw-5557u:   NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108557v1/fi-bdw-5557u/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][7] ([fdo#111827]) +8 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108557v1/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-icl-u2:  NOTRUN -> [SKIP][8] ([i915#4103])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108557v1/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * 
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka:   [PASS][9] -> [FAIL][10] ([i915#6298])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108557v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html

  * igt@kms_force_connector_basic@force-connector-state:
- fi-icl-u2:  NOTRUN -> [WARN][11] ([i915#6008])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108557v1/fi-icl-u2/igt@kms_force_connector_ba...@force-connector-state.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][12] ([fdo#109285])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108557v1/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][13] ([i915#3555])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108557v1/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-icl-u2:  NOTRUN -> [SKIP][14] ([fdo#109295] / [i915#3301])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108557v1/fi-icl-u2/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@i915_selftest@live@guc:
- {bat-rpls-1}:   [DMESG-WARN][15] ([i915#6471]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12134/bat-rpls-1/igt@i915_selftest@l...@guc.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108557v1/bat-rpls-1/igt@i915_selftest@l...@guc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for DGFX mmap with rpm (rev5)

[Gupta, Anshuman]

On 9/14/2022 4:53 PM, Patchwork wrote:

*Patch Details*
*Series:*   DGFX mmap with rpm (rev5)
*URL:*	https://patchwork.freedesktop.org/series/107400/ 


*State:*success
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v5/index.html 


Pushed to drm-intel-gt-next.
Thanks for review.
Br,
Anshuman.



  CI Bug Log - changes from CI_DRM_12131_full -> Patchwork_107400v5_full


Summary

*SUCCESS*

No regressions found.


Participating hosts (11 -> 10)

Missing (1): shard-rkl


Known issues

Here are the changes found in Patchwork_107400v5_full that come from 
known issues:



  IGT changes


Issues hit

  *

igt@gem_ctx_exec@basic-nohangcheck:

  o shard-tglb: PASS


 -> FAIL 

 (i915#6268 )
  *

igt@gem_eio@kms:

  o shard-tglb: PASS

 -> 
FAIL 
 
(i915#5784 )
  *

igt@gem_exec_balancer@parallel:

  o shard-iclb: PASS


 -> SKIP 

 (i915#4525 )
  *

igt@gem_exec_balancer@parallel-keep-submit-fence:

  o shard-iclb: NOTRUN -> SKIP


 (i915#4525 )
  *

igt@gem_exec_fair@basic-pace-solo@rcs0:

  o shard-glk: NOTRUN -> FAIL


 (i915#2842 )
  *

igt@gem_exec_fair@basic-pace@vcs1:

  o shard-iclb: NOTRUN -> FAIL


 (i915#2842 )
  *

igt@gem_huc_copy@huc-copy:

  o shard-tglb: PASS


 -> SKIP 

 (i915#2190 )
  *

igt@gem_lmem_swapping@parallel-random:

  o shard-apl: NOTRUN -> SKIP


 (fdo#109271  / i915#4613 
)
  *

igt@gem_lmem_swapping@verify-ccs:

  o shard-glk: NOTRUN -> SKIP


 (fdo#109271  / i915#4613 
)
  *

igt@gem_softpin@evict-snoop-interruptible:

  o shard-iclb: NOTRUN -> SKIP


 (fdo#109312 )
  *

igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:

  o shard-iclb: NOTRUN -> SKIP


 (i915#5286 ) +1 similar issue
  *

igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:

  o shard-glk: NOTRUN -> SKIP


 (fdo#109271  / i915#3886 
) +3 similar issues
  *

igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs:

  o shard-iclb: NOTRUN -> SKIP

[Intel-gfx] ✓ Fi.CI.IGT: success for Initial Meteorlake Support (rev9)

[Patchwork]

== Series Details ==

Series: Initial Meteorlake Support (rev9)
URL   : https://patchwork.freedesktop.org/series/106786/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12131_full -> Patchwork_106786v9_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_106786v9_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@kms:
- shard-tglb: [PASS][1] -> [FAIL][2] ([i915#5784])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-tglb7/igt@gem_...@kms.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v9/shard-tglb3/igt@gem_...@kms.html

  * igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-iclb4/igt@gem_exec_balan...@parallel-balancer.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v9/shard-iclb8/igt@gem_exec_balan...@parallel-balancer.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v9/shard-tglb6/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-iclb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v9/shard-iclb2/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk:  NOTRUN -> [FAIL][9] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v9/shard-glk7/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_lmem_swapping@verify-ccs:
- shard-glk:  NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v9/shard-glk7/igt@gem_lmem_swapp...@verify-ccs.html

  * igt@gem_softpin@evict-snoop-interruptible:
- shard-iclb: NOTRUN -> [SKIP][11] ([fdo#109312])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v9/shard-iclb1/igt@gem_soft...@evict-snoop-interruptible.html

  * igt@gem_workarounds@suspend-resume:
- shard-apl:  NOTRUN -> [DMESG-WARN][12] ([i915#180])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v9/shard-apl3/igt@gem_workarou...@suspend-resume.html

  * igt@gen9_exec_parse@allowed-single:
- shard-apl:  [PASS][13] -> [DMESG-WARN][14] ([i915#5566] / 
[i915#716])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-apl7/igt@gen9_exec_pa...@allowed-single.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v9/shard-apl7/igt@gen9_exec_pa...@allowed-single.html

  * igt@i915_selftest@live@hangcheck:
- shard-tglb: [PASS][15] -> [DMESG-WARN][16] ([i915#5591])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-tglb5/igt@i915_selftest@l...@hangcheck.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v9/shard-tglb5/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#5286]) +1 similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v9/shard-iclb1/igt@kms_big...@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-glk:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3886]) +3 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v9/shard-glk7/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109278]) +3 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v9/shard-iclb1/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs.html

  * igt@kms_chamelium@hdmi-audio:
- shard-apl:  NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v9/shard-apl3/igt@kms_chamel...@hdmi-audio.html

  * igt@kms_color_chamelium@ctm-blue-to-red:
- shard-iclb: NOTRUN -> [SKIP][21] ([fdo#109284] / [fdo#111827])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106786v9/shard-iclb1/igt@kms_color_chamel...@ctm-blue-to-red.html

  * 

[Intel-gfx] [topic/core-for-CI] Revert "iommu/dma: Fix race condition during iova_domain initialization"

[Karolina Drobnik]

This reverts commit ac9a5d522bb80be50ea84965699e1c8257d745ce.

This change introduces a regression on Alder Lake that completely
blocks testing. To enable CI and avoid possible circular locking
warning, revert the patch.

kernel log:

==
WARNING: possible circular locking dependency detected
6.0.0-rc5-CI_DRM_12132-g6c93e979e542+ #1 Not tainted
--
cpuhp/0/15 is trying to acquire lock:
8881013df278 (&(>bus_notifier)->rwsem){}-{3:3}, at: 
blocking_notifier_call_chain+0x20/0x50
  but task is already holding lock:
826490c0 (cpuhp_state-up){+.+.}-{0:0}, at: cpuhp_thread_fun+0x48/0x1f0
  which lock already depends on the new loc
  the existing dependency chain (in reverse order) is:
  -> #3 (cpuhp_state-up){+.+.}-{0:0}:
   lock_acquire+0xd3/0x310
   cpuhp_thread_fun+0xa6/0x1f0
   smpboot_thread_fn+0x1b5/0x260
   kthread+0xed/0x120
   ret_from_fork+0x1f/0x30
  -> #2 (cpu_hotplug_lock){}-{0:0}:
   lock_acquire+0xd3/0x310
   __cpuhp_state_add_instance+0x43/0x1c0
   iova_domain_init_rcaches+0x199/0x1c0
   iommu_setup_dma_ops+0x130/0x440
   bus_iommu_probe+0x26a/0x2d0
   bus_set_iommu+0x82/0xd0
   intel_iommu_init+0xe33/0x1039
   pci_iommu_init+0x9/0x31
   do_one_initcall+0x53/0x2f0
   kernel_init_freeable+0x18f/0x1e1
   kernel_init+0x11/0x120
   ret_from_fork+0x1f/0x30
  -> #1 (>iova_cookie->mutex){+.+.}-{3:3}:
   lock_acquire+0xd3/0x310
   __mutex_lock+0x97/0xf10
   iommu_setup_dma_ops+0xd7/0x440
   iommu_probe_device+0xa4/0x180
   iommu_bus_notifier+0x2d/0x40
   notifier_call_chain+0x31/0x90
   blocking_notifier_call_chain+0x3a/0x50
   device_add+0x3c1/0x900
   pci_device_add+0x255/0x580
   pci_scan_single_device+0xa6/0xd0
   pci_scan_slot+0x7a/0x1b0
   pci_scan_child_bus_extend+0x35/0x2a0
   vmd_probe+0x5cd/0x970
   pci_device_probe+0x95/0x110
   really_probe+0xd6/0x350
   __driver_probe_device+0x73/0x170
   driver_probe_device+0x1a/0x90
   __driver_attach+0xbc/0x190
   bus_for_each_dev+0x72/0xc0
   bus_add_driver+0x1bb/0x210
   driver_register+0x66/0xc0
   do_one_initcall+0x53/0x2f0
   kernel_init_freeable+0x18f/0x1e1
   kernel_init+0x11/0x120
   ret_from_fork+0x1f/0x30
  -> #0 (&(>bus_notifier)->rwsem){}-{3:3}:
   validate_chain+0xb3f/0x2000
   __lock_acquire+0x5a4/0xb70
   lock_acquire+0xd3/0x310
   down_read+0x39/0x140
   blocking_notifier_call_chain+0x20/0x50
   device_add+0x3c1/0x900
   platform_device_add+0x108/0x240
   coretemp_cpu_online+0xe1/0x15e [coretemp]
   cpuhp_invoke_callback+0x181/0x8a0
   cpuhp_thread_fun+0x188/0x1f0
   smpboot_thread_fn+0x1b5/0x260
   kthread+0xed/0x120
   ret_from_fork+0x1f/0x30
  other info that might help us debug thi
Chain exists of &(>bus_notifier)->rwsem --> 
cpu_hotplug_lock --> cpuhp_state-
 Possible unsafe locking scenari
   CPU0CPU1
   
  lock(cpuhp_state-up);
   lock(cpu_hotplug_lock);
   lock(cpuhp_state-up);
  lock(&(>bus_notifier)->rwsem);
   *** DEADLOCK *
2 locks held by cpuhp/0/15:
 #0: 82648f10 (cpu_hotplug_lock){}-{0:0}, at: 
cpuhp_thread_fun+0x48/0x1f0
 #1: 826490c0 (cpuhp_state-up){+.+.}-{0:0}, at: 
cpuhp_thread_fun+0x48/0x1f0
  stack backtrace:
CPU: 0 PID: 15 Comm: cpuhp/0 Not tainted 6.0.0-rc5-CI_DRM_12132-g6c93e979e542+ 
#1
Hardware name: Intel Corporation Alder Lake Client Platform/AlderLake-P DDR4 
RVP, BIOS ADLPFWI1.R00.3135.A00.2203251419 03/25/2022
Call Trace:
 
 dump_stack_lvl+0x56/0x7f
 check_noncircular+0x132/0x150
 validate_chain+0xb3f/0x2000
 __lock_acquire+0x5a4/0xb70
 lock_acquire+0xd3/0x310
 ? blocking_notifier_call_chain+0x20/0x50
 down_read+0x39/0x140
 ? blocking_notifier_call_chain+0x20/0x50
 blocking_notifier_call_chain+0x20/0x50
 device_add+0x3c1/0x900
 ? dev_set_name+0x4e/0x70
 platform_device_add+0x108/0x240
 coretemp_cpu_online+0xe1/0x15e [coretemp]
 ? create_core_data+0x550/0x550 [coretemp]
 cpuhp_invoke_callback+0x181/0x8a0
 cpuhp_thread_fun+0x188/0x1f0
 ? smpboot_thread_fn+0x1e/0x260
 smpboot_thread_fn+0x1b5/0x260
 ? sort_range+0x20/0x20
 kthread+0xed/0x120
 ? kthread_complete_and_exit+0x20/0x20
 ret_from_fork+0x1f/0x30
 

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6641

Signed-off-by: Karolina Drobnik 
Cc: Lucas De Marchi 
---
 drivers/iommu/dma-iommu.c | 17 -
 1 file changed, 4 insertions(+), 13 deletions(-)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index 17dd683b2fce..9616b473e4c7 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -65,7 +65,6 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: Really move i915_gem_context.link under ref protection (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/gem: Really move i915_gem_context.link under ref protection 
(rev2)
URL   : https://patchwork.freedesktop.org/series/105975/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12131_full -> Patchwork_105975v2_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_105975v2_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_105975v2_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105975v2_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-iclb: [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-edp-1:
- shard-iclb: [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-iclb8/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-edp-1.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-iclb6/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-edp-1.html

  
Known issues


  Here are the changes found in Patchwork_105975v2_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-skl:  ([PASS][5], [PASS][6], [PASS][7], [PASS][8], 
[PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], 
[PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], 
[PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], 
[PASS][27], [PASS][28]) -> ([PASS][29], [PASS][30], [PASS][31], [PASS][32], 
[PASS][33], [PASS][34], [PASS][35], [FAIL][36], [PASS][37], [PASS][38], 
[PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], 
[PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], 
[PASS][51], [PASS][52]) ([i915#5032])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl6/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl6/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl4/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl4/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl4/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl6/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl6/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl6/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl10/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl10/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl10/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl10/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl10/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl3/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl9/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl9/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl9/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl9/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-skl7/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl10/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl10/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105975v2/shard-skl10/boot.html
   [32]: 

Re: [Intel-gfx] [PATCH v5 0/4] lrc selftest fixes

[Andi Shyti]

On Tue, Sep 13, 2022 at 05:21:47PM +0200, Karolina Drobnik wrote:
> Few bug fixes for lrc selftest.
> 
> v5:
>   - Add Reviewed-by tag to "drm/i915/selftests: Check
> for incomplete LRI from the context image" patch, as
> it got reviewed in different series:
> https://patchwork.freedesktop.org/series/108487/
> 
> Chris Wilson (4):
>   drm/i915/gt: Explicitly clear BB_OFFSET for new contexts
>   drm/i915/selftests: Check for incomplete LRI from the context image
>   drm/i915/selftest: Always cancel semaphore on error
>   drm/i915/selftest: Clear the output buffers before GPU writes

Pushed, Thanks!

Andi

>  drivers/gpu/drm/i915/gt/intel_engine_regs.h |   1 +
>  drivers/gpu/drm/i915/gt/intel_lrc.c |  20 
>  drivers/gpu/drm/i915/gt/selftest_lrc.c  | 115 
>  3 files changed, 116 insertions(+), 20 deletions(-)
> 
> --
> 2.25.1

Re: [Intel-gfx] [GIT PULL] Immutable backlight-detect-refactor branch between acpi, drm-* and pdx86

[Maxime Ripard]

Hi Hans,

On Mon, Sep 05, 2022 at 10:35:47AM +0200, Hans de Goede wrote:
> Hi All,
> 
> Now that all patches have been reviewed/acked here is an immutable 
> backlight-detect-refactor
> branch with 6.0-rc1 + the v5 patch-set, for merging into the relevant (acpi, 
> drm-* and pdx86)
> subsystems.
> 
> Please pull this branch into the relevant subsystems.
> 
> I will merge this into the review-hans branch of the pdx86 git tree today and
> from there it will move to for-next once the builders have successfully 
> build-tested
> the merge.

I merged it into drm-misc-next, thanks!
Maxime


signature.asc
Description: PGP signature

[Intel-gfx] ✓ Fi.CI.IGT: success for DGFX mmap with rpm (rev5)

[Patchwork]

== Series Details ==

Series: DGFX mmap with rpm (rev5)
URL   : https://patchwork.freedesktop.org/series/107400/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12131_full -> Patchwork_107400v5_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 10)
--

  Missing(1): shard-rkl 

Known issues


  Here are the changes found in Patchwork_107400v5_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][1] -> [FAIL][2] ([i915#6268])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-tglb1/igt@gem_ctx_e...@basic-nohangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v5/shard-tglb1/igt@gem_ctx_e...@basic-nohangcheck.html

  * igt@gem_eio@kms:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#5784])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-tglb7/igt@gem_...@kms.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v5/shard-tglb5/igt@gem_...@kms.html

  * igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-iclb4/igt@gem_exec_balan...@parallel.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v5/shard-iclb7/igt@gem_exec_balan...@parallel.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: NOTRUN -> [SKIP][7] ([i915#4525])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v5/shard-iclb8/igt@gem_exec_balan...@parallel-keep-submit-fence.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk:  NOTRUN -> [FAIL][8] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v5/shard-glk8/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][9] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v5/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][10] -> [SKIP][11] ([i915#2190])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-tglb5/igt@gem_huc_c...@huc-copy.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v5/shard-tglb7/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-apl:  NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v5/shard-apl8/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@verify-ccs:
- shard-glk:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v5/shard-glk8/igt@gem_lmem_swapp...@verify-ccs.html

  * igt@gem_softpin@evict-snoop-interruptible:
- shard-iclb: NOTRUN -> [SKIP][14] ([fdo#109312])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v5/shard-iclb8/igt@gem_soft...@evict-snoop-interruptible.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][15] ([i915#5286]) +1 similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v5/shard-iclb8/igt@kms_big...@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-glk:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3886]) +3 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v5/shard-glk8/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][17] ([fdo#109278]) +3 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v5/shard-iclb8/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs.html

  * igt@kms_chamelium@hdmi-audio:
- shard-apl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +1 
similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v5/shard-apl8/igt@kms_chamel...@hdmi-audio.html

  * igt@kms_color_chamelium@ctm-blue-to-red:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109284] / [fdo#111827])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107400v5/shard-iclb8/igt@kms_color_chamel...@ctm-blue-to-red.html

  * igt@kms_cursor_legacy@flip-vs-cursor@varying-size:
- shard-iclb: [PASS][20] -> [FAIL][21] ([i915#2346]) +2 similar 
issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-iclb4/igt@kms_cursor_legacy@flip-vs-cur...@varying-size.html
   [21]: 

Re: [Intel-gfx] [PATCH v5 0/4] lrc selftest fixes

[Andi Shyti]

For all the series,

Reviewed-by: Andi Shyti 

Thanks,
Andi

On Tue, Sep 13, 2022 at 05:21:47PM +0200, Karolina Drobnik wrote:
> Few bug fixes for lrc selftest.
> 
> v5:
>   - Add Reviewed-by tag to "drm/i915/selftests: Check
> for incomplete LRI from the context image" patch, as
> it got reviewed in different series:
> https://patchwork.freedesktop.org/series/108487/
> 
> Chris Wilson (4):
>   drm/i915/gt: Explicitly clear BB_OFFSET for new contexts
>   drm/i915/selftests: Check for incomplete LRI from the context image
>   drm/i915/selftest: Always cancel semaphore on error
>   drm/i915/selftest: Clear the output buffers before GPU writes
> 
>  drivers/gpu/drm/i915/gt/intel_engine_regs.h |   1 +
>  drivers/gpu/drm/i915/gt/intel_lrc.c |  20 
>  drivers/gpu/drm/i915/gt/selftest_lrc.c  | 115 
>  3 files changed, 116 insertions(+), 20 deletions(-)
> 
> --
> 2.25.1

Re: [Intel-gfx] [PATCHv3] drm/i915: Support Async Flip on Linear buffers

[Murthy, Arun R]

Gentle Reminder!
Any comments?

Thanks and Regards,
Arun R Murthy


> -Original Message-
> From: Intel-gfx  On Behalf Of
> Murthy, Arun R
> Sent: Friday, September 9, 2022 9:17 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Syrjala, Ville 
> Subject: Re: [Intel-gfx] [PATCHv3] drm/i915: Support Async Flip on Linear
> buffers
> 
> Gentle Reminder!
> 
> > -Original Message-
> > From: Murthy, Arun R 
> > Sent: Tuesday, September 6, 2022 9:18 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: ville.syrj...@linux.intel.com; Murthy, Arun R
> > 
> > Subject: [PATCHv3] drm/i915: Support Async Flip on Linear buffers
> >
> > Starting from Gen12 Async Flip is supported on linear buffers.
> > This patch enables support for async on linear buffer.
> >
> > UseCase: In Hybrid graphics, for hardware unsupported pixel formats it
> > will be converted to linear memory and then composed.
> >
> > v2: Added use case
> > v3: Added FIXME for ICL indicating the restrictions
> >
> > Signed-off-by: Arun R Murthy 
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 14 ++
> >  1 file changed, 14 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index be7cff722196..1880cfe70a7d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6610,6 +6610,20 @@ static int intel_async_flip_check_hw(struct
> > intel_atomic_state *state, struct in
> >  * this selectively if required.
> >  */
> > switch (new_plane_state->hw.fb->modifier) {
> > +   case DRM_FORMAT_MOD_LINEAR:
> > +   /*
> > +* FIXME: Async on Linear buffer is supported on ICL
> > as
> > +* but with additional alignment and fbc restrictions
> > +* need to be taken care of. These aren't applicable
> > for
> > +* gen12+.
> > +*/
> > +   if (DISPLAY_VER(i915) < 12) {
> > +   drm_dbg_kms(>drm,
> > +   "[PLANE:%d:%s] Modifier does not
> > support async flips\n",
> > +   plane->base.base.id, plane-
> > >base.name);
> > +   return -EINVAL;
> > +   }
> > +
> > case I915_FORMAT_MOD_X_TILED:
> > case I915_FORMAT_MOD_Y_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > --
> > 2.25.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix return type of mode_valid function hook

[Patchwork]

== Series Details ==

Series: drm/i915: Fix return type of mode_valid function hook
URL   : https://patchwork.freedesktop.org/series/108553/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12133 -> Patchwork_108553v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/index.html

Participating hosts (42 -> 38)
--

  Additional (1): fi-icl-u2 
  Missing(5): fi-ctg-p8600 fi-hsw-4770 bat-adln-1 bat-jsl-1 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_108553v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_parallel@engines@basic:
- fi-icl-u2:  NOTRUN -> [INCOMPLETE][1] ([i915#4890])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/fi-icl-u2/igt@gem_exec_parallel@engi...@basic.html

  * igt@i915_selftest@live@gem:
- fi-blb-e6850:   NOTRUN -> [DMESG-FAIL][2] ([i915#4528])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/fi-blb-e6850/igt@i915_selftest@l...@gem.html

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-5:  [PASS][3] -> [INCOMPLETE][4] ([i915#4418])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12133/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/bat-dg1-5/igt@i915_selftest@live@gt_engines.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-bdw-5557u:   [PASS][5] -> [INCOMPLETE][6] ([i915#146] / 
[i915#6598] / [i915#6712])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12133/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-snb-2600:NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/fi-snb-2600/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@runner@aborted:
- fi-icl-u2:  NOTRUN -> [FAIL][8] ([i915#4312] / [i915#6599])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/fi-icl-u2/igt@run...@aborted.html
- bat-dg1-5:  NOTRUN -> [FAIL][9] ([i915#4312] / [i915#5257])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/bat-dg1-5/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [DMESG-FAIL][10] ([i915#4528]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12133/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890
  [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
  [i915#6598]: https://gitlab.freedesktop.org/drm/intel/issues/6598
  [i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
  [i915#6712]: https://gitlab.freedesktop.org/drm/intel/issues/6712


Build changes
-

  * Linux: CI_DRM_12133 -> Patchwork_108553v1

  CI-20190529: 20190529
  CI_DRM_12133: 81bd7da6c37f2197b9767a9c45091273ca688bdb @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6655: 1c26b484df1d07ddb403883c88b8b82db7d63877 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_108553v1: 81bd7da6c37f2197b9767a9c45091273ca688bdb @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

387591e74632 drm/i915: Fix return type of mode_valid function hook

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108553v1/index.html

[Intel-gfx] ✓ Fi.CI.IGT: success for lrc selftest fixes (rev7)

[Patchwork]

== Series Details ==

Series: lrc selftest fixes (rev7)
URL   : https://patchwork.freedesktop.org/series/101353/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12131_full -> Patchwork_101353v7_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_101353v7_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@kms:
- shard-tglb: [PASS][1] -> [FAIL][2] ([i915#5784])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-tglb7/igt@gem_...@kms.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101353v7/shard-tglb5/igt@gem_...@kms.html

  * igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-iclb4/igt@gem_exec_balan...@parallel-balancer.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101353v7/shard-iclb6/igt@gem_exec_balan...@parallel-balancer.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: NOTRUN -> [SKIP][5] ([i915#4525])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101353v7/shard-iclb8/igt@gem_exec_balan...@parallel-keep-submit-fence.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101353v7/shard-tglb2/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk:  NOTRUN -> [FAIL][8] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101353v7/shard-glk9/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][9] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101353v7/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-apl:  NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101353v7/shard-apl8/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@verify-ccs:
- shard-glk:  NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101353v7/shard-glk9/igt@gem_lmem_swapp...@verify-ccs.html

  * igt@gem_softpin@evict-snoop-interruptible:
- shard-iclb: NOTRUN -> [SKIP][12] ([fdo#109312])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101353v7/shard-iclb8/igt@gem_soft...@evict-snoop-interruptible.html

  * igt@i915_module_load@reload-with-fault-injection:
- shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([i915#6725] / 
[i915#6783])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12131/shard-tglb7/igt@i915_module_l...@reload-with-fault-injection.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101353v7/shard-tglb3/igt@i915_module_l...@reload-with-fault-injection.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][15] ([i915#5286]) +1 similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101353v7/shard-iclb8/igt@kms_big...@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-glk:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3886]) +3 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101353v7/shard-glk9/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][17] ([fdo#109278]) +3 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101353v7/shard-iclb8/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs.html

  * igt@kms_chamelium@hdmi-audio:
- shard-apl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +1 
similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101353v7/shard-apl8/igt@kms_chamel...@hdmi-audio.html

  * igt@kms_color_chamelium@ctm-blue-to-red:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109284] / [fdo#111827])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101353v7/shard-iclb8/igt@kms_color_chamel...@ctm-blue-to-red.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk:  [PASS][20] -> [FAIL][21] ([i915#2346]) +1 similar 
issue
   [20]: