[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode

[Patchwork]

== Series Details ==

Series: drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode
URL   : https://patchwork.freedesktop.org/series/110130/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12294_full -> Patchwork_110130v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110130v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110130v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110130v1_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-tglb3/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/shard-tglb8/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html

  
 Warnings 

  * igt@runner@aborted:
- shard-skl:  ([FAIL][3], [FAIL][4], [FAIL][5], [FAIL][6], 
[FAIL][7], [FAIL][8], [FAIL][9]) ([i915#3002] / [i915#4312] / [i915#6949]) -> 
([FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15], 
[FAIL][16]) ([i915#3002] / [i915#4312])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-skl9/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-skl7/igt@run...@aborted.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-skl9/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-skl6/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-skl7/igt@run...@aborted.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-skl6/igt@run...@aborted.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-skl4/igt@run...@aborted.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/shard-skl4/igt@run...@aborted.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/shard-skl10/igt@run...@aborted.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/shard-skl9/igt@run...@aborted.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/shard-skl9/igt@run...@aborted.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/shard-skl4/igt@run...@aborted.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/shard-skl7/igt@run...@aborted.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/shard-skl4/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_110130v1_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-snb:  ([PASS][17], [PASS][18], [PASS][19], [PASS][20], 
[PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], 
[PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], 
[PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], 
[PASS][39], [PASS][40], [PASS][41]) -> ([PASS][42], [PASS][43], [PASS][44], 
[PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], 
[PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [FAIL][56], 
[PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], 
[PASS][63], [PASS][64], [PASS][65], [PASS][66]) ([i915#4338])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-snb7/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-snb7/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-snb7/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-snb7/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-snb7/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-snb6/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-snb6/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-snb6/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-snb6/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-snb6/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-snb5/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/shard-snb5/boot.html
   [29]: 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/xelp: Add Wa_1806527549 (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/xelp: Add Wa_1806527549 (rev2)
URL   : https://patchwork.freedesktop.org/series/109885/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12261_full -> Patchwork_109885v2_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_109885v2_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_109885v2_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 12)
--

  Additional (3): shard-rkl shard-dg1 shard-tglu 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109885v2_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_cursor_legacy@cursor-vs-flip@atomic:
- shard-skl:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-skl4/igt@kms_cursor_legacy@cursor-vs-f...@atomic.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_pwrite@basic-exhaustion:
- {shard-rkl}:NOTRUN -> [INCOMPLETE][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-rkl-5/igt@gem_pwr...@basic-exhaustion.html

  * igt@kms_big_fb@linear-64bpp-rotate-0:
- {shard-dg1}:NOTRUN -> [FAIL][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-dg1-13/igt@kms_big...@linear-64bpp-rotate-0.html

  
Known issues


  Here are the changes found in Patchwork_109885v2_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-glk:  ([PASS][4], [PASS][5], [PASS][6], [PASS][7], 
[PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], 
[PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], 
[PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], 
[PASS][26], [PASS][27], [PASS][28]) -> ([PASS][29], [PASS][30], [PASS][31], 
[PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], 
[PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], 
[PASS][44], [FAIL][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], 
[PASS][50], [PASS][51], [PASS][52], [PASS][53]) ([i915#4392])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk3/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk9/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk9/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk9/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk9/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk8/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk8/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk8/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk7/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk7/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk6/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk6/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk6/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk5/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk5/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk1/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk1/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk1/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk2/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk2/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk5/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk3/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk3/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk2/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk2/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-glk9/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-glk9/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-glk8/boot.html
   [32]: 

Re: [Intel-gfx] mm/huge_memory: do not clobber swp_entry_t during THP split

[Hugh Dickins]

On Tue, 25 Oct 2022, Andrew Morton wrote:
> On Tue, 25 Oct 2022 11:03:38 +0100 Mel Gorman  
> wrote:
> 
> > > If so I
> > > can temporarily put it in until it arrives via the next rc - assuming that
> > > would be the flow from upstream pov?
> > > 
> > 
> > I expect it to. It's currently in the akpm/mm.git branch
> > mm/mm-hotfixes-unstable where I expect it to flow to mm/mm-hotfixes-stable
> > in due course before sending to Linus. I can't make promises about the
> > timing as that's determined by Andrew.
> 
> This is now in mainline, 71e2d666ef85.

No, that one is Mel's commit, which GregKH already picked up for stable.
But what we're waiting for here is my fix to the warning that brings,
my fix currently lurking in mm-hotfixes-unstable as
45ba9c269874 ("mm: prep_compound_tail() clear page->private")

Hugh

Re: [Intel-gfx] mm/huge_memory: do not clobber swp_entry_t during THP split

[Andrew Morton]

On Tue, 25 Oct 2022 11:03:38 +0100 Mel Gorman  
wrote:

> > If so I
> > can temporarily put it in until it arrives via the next rc - assuming that
> > would be the flow from upstream pov?
> > 
> 
> I expect it to. It's currently in the akpm/mm.git branch
> mm/mm-hotfixes-unstable where I expect it to flow to mm/mm-hotfixes-stable
> in due course before sending to Linus. I can't make promises about the
> timing as that's determined by Andrew.

This is now in mainline, 71e2d666ef85.

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/slpc: Use platform limits for min/max frequency (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/slpc: Use platform limits for min/max frequency (rev5)
URL   : https://patchwork.freedesktop.org/series/109632/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109632v5_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_109632v5_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_109632v5_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109632v5_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_capture@pi@vecs0:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb2/igt@gem_exec_capture@p...@vecs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/shard-iclb8/igt@gem_exec_capture@p...@vecs0.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_create@create-clear@smem0:
- {shard-rkl}:NOTRUN -> [INCOMPLETE][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/shard-rkl-5/igt@gem_create@create-cl...@smem0.html

  * igt@sysfs_preempt_timeout@idempotent@rcs0:
- {shard-dg1}:NOTRUN -> [FAIL][4] +4 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/shard-dg1-12/igt@sysfs_preempt_timeout@idempot...@rcs0.html

  
Known issues


  Here are the changes found in Patchwork_109632v5_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#6268])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb2/igt@gem_ctx_e...@basic-nohangcheck.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/shard-tglb7/igt@gem_ctx_e...@basic-nohangcheck.html

  * igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#4525])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb1/igt@gem_exec_balan...@parallel.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/shard-iclb7/igt@gem_exec_balan...@parallel.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][11] -> [SKIP][12] ([i915#2190])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb2/igt@gem_huc_c...@huc-copy.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/shard-tglb7/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/shard-skl10/igt@gem_lmem_swapp...@parallel-random.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
- shard-skl:  [PASS][14] -> [FAIL][15] ([i915#2521])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@kms_async_flips@alternate-sync-async-f...@pipe-a-edp-1.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/shard-skl4/igt@kms_async_flips@alternate-sync-async-f...@pipe-a-edp-1.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl:  NOTRUN -> [SKIP][16] ([fdo#109271]) +44 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/shard-skl10/igt@kms_big...@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-180:
- shard-glk:  [PASS][17] -> [DMESG-FAIL][18] ([i915#118] / 
[i915#5138])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk1/igt@kms_big...@y-tiled-32bpp-rotate-180.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/shard-glk5/igt@kms_big...@y-tiled-32bpp-rotate-180.html

  * igt@kms_color_chamelium@ctm-limited-range:
- shard-skl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +2 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/shard-skl10/igt@kms_color_chamel...@ctm-limited-range.html

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Handle wopcm per-GT and limit calculations.

[John Harrison]

On 10/24/2022 15:26, Daniele Ceraolo Spurio wrote:

From: Aravind Iddamsetty 

With MTL standalone media architecture the wopcm layout has changed,
with separate partitioning in WOPCM for the root GT GuC and the media
GT GuC. The size of WOPCM is 4MB with the lower 2MB reserved for the
media GT and the upper 2MB for the root GT.

Given that MTL has GuC deprivilege, the WOPCM registers are pre-locked
by the bios. Therefore, we can skip all the math for the partitioning
and just limit ourselves to sanity-checking the values.

v2: fix makefile file ordering (Jani)
v3: drop XELPM_SAMEDIA_WOPCM_SIZE, check huc instead of VDBOX (John)
v4: further clarify commit message, remove blank line (John)

Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Daniele Ceraolo Spurio 
Cc: Matt Roper 
Cc: John Harrison 
Cc: Alan Previn 
Cc: Jani Nikula 

Reviewed-by: John Harrison 


---
  Documentation/gpu/i915.rst  |  2 +-
  drivers/gpu/drm/i915/Makefile   |  5 ++-
  drivers/gpu/drm/i915/gt/intel_ggtt.c|  2 +-
  drivers/gpu/drm/i915/gt/intel_gt.c  |  1 +
  drivers/gpu/drm/i915/gt/intel_gt_types.h|  2 +
  drivers/gpu/drm/i915/{ => gt}/intel_wopcm.c | 43 ++---
  drivers/gpu/drm/i915/{ => gt}/intel_wopcm.h |  0
  drivers/gpu/drm/i915/gt/uc/intel_uc.c   |  4 +-
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c| 14 ---
  drivers/gpu/drm/i915/i915_driver.c  |  2 -
  drivers/gpu/drm/i915/i915_drv.h |  3 --
  drivers/gpu/drm/i915/i915_gem.c |  5 ++-
  12 files changed, 51 insertions(+), 32 deletions(-)
  rename drivers/gpu/drm/i915/{ => gt}/intel_wopcm.c (87%)
  rename drivers/gpu/drm/i915/{ => gt}/intel_wopcm.h (100%)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 4e59db1cfb00..60ea21734902 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -494,7 +494,7 @@ WOPCM
  WOPCM Layout
  
  
-.. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c

+.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_wopcm.c
 :doc: WOPCM Layout
  
  GuC

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 2535593ab379..cf3a96b3cd58 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -127,9 +127,11 @@ gt-y += \
gt/intel_sseu.o \
gt/intel_sseu_debugfs.o \
gt/intel_timeline.o \
+   gt/intel_wopcm.o \
gt/intel_workarounds.o \
gt/shmem_utils.o \
gt/sysfs_engines.o
+
  # x86 intel-gtt module support
  gt-$(CONFIG_X86) += gt/intel_ggtt_gmch.o
  # autogenerated null render state
@@ -183,8 +185,7 @@ i915-y += \
  i915_trace_points.o \
  i915_ttm_buddy_manager.o \
  i915_vma.o \
- i915_vma_resource.o \
- intel_wopcm.o
+ i915_vma_resource.o
  
  # general-purpose microcontroller (GuC) support

  i915-y += gt/uc/intel_uc.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 6b58c95ad6a0..9263f10ecd28 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -560,7 +560,7 @@ static int init_ggtt(struct i915_ggtt *ggtt)
 * why.
 */
ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
-  intel_wopcm_guc_size(>vm.i915->wopcm));
+  intel_wopcm_guc_size(>vm.gt->wopcm));
  
  	ret = intel_vgt_balloon(ggtt);

if (ret)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 27dbb9e4bd6c..8c751314df3d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -56,6 +56,7 @@ void intel_gt_common_init_early(struct intel_gt *gt)
seqcount_mutex_init(>tlb.seqno, >tlb.invalidate_lock);
intel_gt_pm_init_early(gt);
  
+	intel_wopcm_init_early(>wopcm);

intel_uc_init_early(>uc);
intel_rps_init_early(>rps);
  }
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 64aa2ba624fc..2d18fd9ab11f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -30,6 +30,7 @@
  #include "intel_migrate_types.h"
  #include "intel_wakeref.h"
  #include "pxp/intel_pxp_types.h"
+#include "intel_wopcm.h"
  
  struct drm_i915_private;

  struct i915_ggtt;
@@ -100,6 +101,7 @@ struct intel_gt {
  
  	struct intel_uc uc;

struct intel_gsc gsc;
+   struct intel_wopcm wopcm;
  
  	struct {

/* Serialize global tlb invalidations */
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c 
b/drivers/gpu/drm/i915/gt/intel_wopcm.c
similarity index 87%
rename from drivers/gpu/drm/i915/intel_wopcm.c
rename to drivers/gpu/drm/i915/gt/intel_wopcm.c
index 322fb9eeb880..7ebbcc191c2d 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/gt/intel_wopcm.c
@@ -64,9 +64,9 @@
  #define GEN9_GUC_FW_RESERVED  SZ_128K
  

[Intel-gfx] ✓ Fi.CI.BAT: success for Delay disabling GuC scheduling of an idle context (rev2)

[Patchwork]

== Series Details ==

Series: Delay disabling GuC scheduling of an idle context (rev2)
URL   : https://patchwork.freedesktop.org/series/109466/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12295 -> Patchwork_109466v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/index.html

Participating hosts (41 -> 39)
--

  Missing(2): fi-ctg-p8600 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_109466v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#111827])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-bdw-5557u:   NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#111827])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/fi-bdw-5557u/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-rkl-guc: NOTRUN -> [SKIP][3] ([fdo#111827])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/fi-rkl-guc/igt@kms_chamel...@common-hpd-after-suspend.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}:   [DMESG-WARN][4] ([i915#2867]) -> [PASS][5] +1 similar 
issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
- fi-bdw-5557u:   [DMESG-WARN][6] -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-adlm-1}:   [DMESG-WARN][8] ([i915#2867]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html
- {bat-rpls-1}:   [DMESG-WARN][10] ([i915#6687]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}:   [WARN][12] -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/bat-rpls-2/igt@i915_pm_...@module-reload.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/bat-rpls-2/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@gt_engines:
- fi-rkl-guc: [INCOMPLETE][14] ([i915#4418]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-bdw-5557u:   [DMESG-FAIL][16] ([i915#5334]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][18] ([i915#4785]) -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109466v2/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687


Build changes
-

  * Linux: CI_DRM_12295 -> Patchwork_109466v2

  CI-20190529: 20190529
  CI_DRM_12295: 3844a56a09225527d7d9148d7e05ef5a99ac282f @ 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/ttm: rework on ttm_resource to use size_t type

[Patchwork]

== Series Details ==

Series: drm/ttm: rework on ttm_resource to use size_t type
URL   : https://patchwork.freedesktop.org/series/110129/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_110129v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110129v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110129v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110129v1_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_plane@plane-position-hole-dpms@pipe-b-planes:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb6/igt@kms_plane@plane-position-hole-d...@pipe-b-planes.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/shard-tglb8/igt@kms_plane@plane-position-hole-d...@pipe-b-planes.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@sysfs_timeslice_duration@idempotent@vcs0:
- {shard-dg1}:NOTRUN -> [FAIL][3] +9 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/shard-dg1-15/igt@sysfs_timeslice_duration@idempot...@vcs0.html

  
Known issues


  Here are the changes found in Patchwork_110129v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][4] -> [SKIP][5] ([i915#4525])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb1/igt@gem_exec_balan...@parallel-out-fence.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/shard-iclb8/igt@gem_exec_balan...@parallel-out-fence.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/shard-apl6/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][8] -> [SKIP][9] ([i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb2/igt@gem_huc_c...@huc-copy.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/shard-tglb6/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/shard-skl10/igt@gem_lmem_swapp...@parallel-random.html

  * igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#3989] / [i915#454])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb5/igt@i915_pm...@dc6-dpms.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/shard-iclb3/igt@i915_pm...@dc6-dpms.html

  * igt@i915_suspend@sysfs-reader:
- shard-apl:  [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +3 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl7/igt@i915_susp...@sysfs-reader.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/shard-apl2/igt@i915_susp...@sysfs-reader.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-1:
- shard-glk:  [PASS][15] -> [FAIL][16] ([i915#2521])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk6/igt@kms_async_flips@alternate-sync-async-f...@pipe-b-hdmi-a-1.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/shard-glk6/igt@kms_async_flips@alternate-sync-async-f...@pipe-b-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl:  NOTRUN -> [SKIP][17] ([fdo#109271]) +44 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/shard-skl10/igt@kms_big...@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_color_chamelium@ctm-limited-range:
- shard-skl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +2 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/shard-skl10/igt@kms_color_chamel...@ctm-limited-range.html

  * igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl:  [PASS][19] -> [INCOMPLETE][20] ([i915#180])
   [19]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Delay disabling GuC scheduling of an idle context (rev2)

[Patchwork]

== Series Details ==

Series: Delay disabling GuC scheduling of an idle context (rev2)
URL   : https://patchwork.freedesktop.org/series/109466/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/display: Change terminology for cdclk actions

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/4] drm/i915/display: Change terminology for 
cdclk actions
URL   : https://patchwork.freedesktop.org/series/110145/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12295 -> Patchwork_110145v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110145v1/index.html

Participating hosts (41 -> 38)
--

  Missing(3): fi-ctg-p8600 fi-hsw-4770 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_110145v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-bdw-5557u:   NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#111827])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110145v1/fi-bdw-5557u/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-rkl-guc: NOTRUN -> [SKIP][2] ([fdo#111827])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110145v1/fi-rkl-guc/igt@kms_chamel...@common-hpd-after-suspend.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}:   [DMESG-WARN][3] ([i915#2867]) -> [PASS][4] +1 similar 
issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110145v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
- fi-bdw-5557u:   [DMESG-WARN][5] -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110145v1/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
- {bat-adlm-1}:   [DMESG-WARN][7] ([i915#2867]) -> [PASS][8] +1 similar 
issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110145v1/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@gt_engines:
- fi-rkl-guc: [INCOMPLETE][9] ([i915#4418]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110145v1/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-bdw-5557u:   [DMESG-FAIL][11] ([i915#5334]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12295/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110145v1/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
  [i915#6559]: https://gitlab.freedesktop.org/drm/intel/issues/6559
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997


Build changes
-

  * Linux: CI_DRM_12295 -> Patchwork_110145v1

  CI-20190529: 20190529
  CI_DRM_12295: 3844a56a09225527d7d9148d7e05ef5a99ac282f @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7026: ce0f97e7e0aa54c40049a8365b3d61773c92e588 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_110145v1: 3844a56a09225527d7d9148d7e05ef5a99ac282f @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

5cb045452a50 drm/i915/display: Move squash_ctl register programming to its own 
function
7648083862c8 drm/i915/display: Move chunks of code out of bxt_set_cdclk()
385785866ef4 drm/i915/display: Introduce HAS_CDCLK_SQUASH macro
74b58136c2f4 drm/i915/display: Change terminology for cdclk actions

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110145v1/index.html

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Fix Guc-Err-Capture sizing warning (rev2)

[Patchwork]

== Series Details ==

Series: Fix Guc-Err-Capture sizing warning (rev2)
URL   : https://patchwork.freedesktop.org/series/109439/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/109439/revisions/2/mbox/ not 
applied
Applying: drm/i915/guc: Fix GuC error capture sizing estimation and reporting
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
CONFLICT (content): Merge conflict in 
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915/guc: Fix GuC error capture sizing estimation and 
reporting
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/kms: Stop registering multiple /sys/class/backlight devs for a single display (rev4)

[Patchwork]

== Series Details ==

Series: drm/kms: Stop registering multiple /sys/class/backlight devs for a 
single display (rev4)
URL   : https://patchwork.freedesktop.org/series/107755/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/107755/revisions/4/mbox/ not 
applied
Applying: ACPI: video: Add acpi_video_backlight_use_native() helper
Using index info to reconstruct a base tree...
M   drivers/acpi/video_detect.c
M   include/acpi/video.h
Falling back to patching base and 3-way merge...
Auto-merging include/acpi/video.h
CONFLICT (content): Merge conflict in include/acpi/video.h
Auto-merging drivers/acpi/video_detect.c
CONFLICT (content): Merge conflict in drivers/acpi/video_detect.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 ACPI: video: Add acpi_video_backlight_use_native() helper
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Fix a build error used with clang compiler

[Andi Shyti]

Hi Ashutosh,

> On Tue, 25 Oct 2022 02:25:06 -0700, Andi Shyti wrote:
> >
> > Hi Ashutosh,
> 
> Hi Andi :)
> 
> > > > If a non-constant variable is used as the first argument of the 
> > > > FIELD_PREP
> > > > macro, a build error occurs when using the clang compiler.
> 
> A "non-constant variable" does not seem to be the cause of the compile
> error with clang, see below.
> 
> >
> > > > drivers/gpu/drm/i915/i915_hwmon.c:115:16: error: result of comparison 
> > > > of constant 18446744073709551615 with expression of type 'typeof 
> > > > (_Generic((field_msk), char: (unsigned char)0, unsigned char: (unsigned 
> > > > char)0, signed char: (unsigned char)0, unsigned short: (unsigned 
> > > > short)0, short: (unsigned short)0, unsigned int: (unsigned int)0, int: 
> > > > (unsigned int)0, unsigned long: (unsigned long)0, long: (unsigned 
> > > > long)0, unsigned long long: (unsigned long long)0, long long: (unsigned 
> > > > long long)0, default: (field_msk)))' (aka 'unsigned int') is always 
> > > > false [-Werror,-Wtautological-constant-out-of-range-compare]
> > >
> > > What is 18446744073709551615? You may want to limit the length of this 
> > > line
> > > or checkpatch doesn't complain?
> >
> > yeah! I am not a clang user, and this must be some ugly error
> > output. I don't think it makes sense to break it, though.
> 
> 18446744073709551615 == ~0ull (see use in __BF_FIELD_CHECK).

I just wonder, then, where this number comes from, looks to me
like an ill formatted constant coming from the compiler
(definitely bigger than a ull).

> >
> > > > bits_to_set = FIELD_PREP(field_msk, nval);
> > > >   ^~~
> > > > ./include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP'
> > > > __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: ");
> > > > \
> > > > ^~~
> > > > ./include/linux/bitfield.h:71:53: note: expanded from macro 
> > > > '__BF_FIELD_CHECK'
> > > > BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > 
> > > > \
> 
> So clang seems to break here at this line in __BF_FIELD_CHECK (note ~0ull
> also occurs here):
> 
>   BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
>__bf_cast_unsigned(_reg, ~0ull),   \
>_pfx "type of reg too small for mask"); \
> 
> So it goes through previous checks including the "mask is not constant"
> check. As Nick Desaulniers mentions "__builtin_constant_p is evaluated
> after most optimizations have run" so by that time both compilers (gcc and
> clang) have figured out that even though _mask is coming in as function
> argument it is really the constant below:
> 
> #define   PKG_PWR_LIM_1   REG_GENMASK(14, 0)

I also thought that the compiler should have figured it out, but
then why we got that error, and I don't see how
"bf_cast_unsigned(_reg, ~0ull)" could fail.

> But it is not clear why clang chokes on this "type of reg too small for
> mask" check (and gcc doesn't) since everything is u32.
> 
> It is for this reason I want someone from llvm to chime in.
> 
> > > > 
> > > > ~~^~~
> > > > ./include/linux/build_bug.h:39:58: note: expanded from macro 
> > > > 'BUILD_BUG_ON_MSG'
> > > > ~^~~
> > > > ./include/linux/compiler_types.h:357:22: note: expanded from macro 
> > > > 'compiletime_assert'
> > > > _compiletime_assert(condition, msg, __compiletime_assert_, 
> > > > __COUNTER__)
> > > > 
> > > > ^~~
> > > > ./include/linux/compiler_types.h:345:23: note: expanded from macro 
> > > > '_compiletime_assert'
> > > > __compiletime_assert(condition, msg, prefix, suffix)
> > > > ~^~~
> > > > ./include/linux/compiler_types.h:337:9: note: expanded from macro 
> > > > '__compiletime_assert'
> > > > if (!(condition))   
> > > > \
> > > >
> > > > Fixes: 99f55efb7911 ("drm/i915/hwmon: Power PL1 limit and TDP setting")
> > > > Cc: Ashutosh Dixit 
> > > > Cc: Anshuman Gupta 
> > > > Cc: Andi Shyti 
> > > > Signed-off-by: Gwan-gyeong Mun 
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_hwmon.c | 12 +++-
> > > >  1 file changed, 3 insertions(+), 9 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c 
> > > > b/drivers/gpu/drm/i915/i915_hwmon.c
> > > > index 9e9781493025..782a621b1928 100644
> > > > --- a/drivers/gpu/drm/i915/i915_hwmon.c
> > > > +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> > > > @@ -101,21 +101,16 @@ hwm_field_read_and_scale(struct hwm_drvdata 
> > > > *ddat, i915_reg_t rgadr,
> > > >
> > > >  static void
> > > >  hwm_field_scale_and_write(struct hwm_drvdata *ddat, 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/4] drm/i915/display: Change terminology for cdclk actions

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/4] drm/i915/display: Change terminology for 
cdclk actions
URL   : https://patchwork.freedesktop.org/series/110145/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

[Matthew Garrett]

On Wed, Oct 26, 2022 at 01:27:25AM +0200, Hans de Goede wrote:

> this code should actually set the ACPI_VIDEO_BACKLIGHT flag:
> drivers/acpi/scan.c:
> 
> static acpi_status
> acpi_backlight_cap_match(acpi_handle handle, u32 level, void *context,
>   void **return_value)
> {
> long *cap = context;
> 
> if (acpi_has_method(handle, "_BCM") &&
> acpi_has_method(handle, "_BCL")) {
> acpi_handle_debug(handle, "Found generic backlight 
> support\n");
> *cap |= ACPI_VIDEO_BACKLIGHT;
> /* We have backlight support, no need to scan further */
> return AE_CTRL_TERMINATE;
> }
> return 0;
> }

Ah, yeah, my local tree no longer matches the upstream behaviour because 
I've hacked the EC firmware to remove the backlight trigger because it 
had an extremely poor brightness curve and also automatically changed it 
on AC events - as a result I removed the backlight code from the DSDT 
and just fell back to the native control. Like I said I'm a long way 
from the normal setup, but this did previously work.

The "right" logic here seems pretty simple: if ACPI backlight control is 
expected to work, use it. If it isn't, but there's a vendor interface, 
use it. If there's no vendor interface, use the native interface. The 
problem you're dealing with is that the knowledge of whether or not 
there's a vendor interface isn't something the core kernel code knows 
about. What you're proposing here is effectively for us to expose 
additional information about whether or not there's a vendor interface 
in the system firmware, but since we're talking in some cases about 
hardware that's almost 20 years old, we're not realistically going to 
get those old machines fixed. So, it feels like there's two choices:

1) Make a default policy decision, but then allow that decision to be 
altered later on (eg, when a vendor-specific platform driver has been 
loaded) - you've said this poses additional complexities.

2) Move the knowledge of whether or not there's a vendor interface into 
the core code. Basically take every platform driver that exposes a 
vendor interface, and move the detection code into the core.

I think any other approach is going to result in machines that 
previously worked no longer working (and you can't just make the 
vendor/native split dependent on the Coreboot DMI BIOS string, because 
there are some Coreboot platforms that implement the vendor interface 
for compatibility, and you also can't ask all Coreboot users to update 
their firmware to fix things)

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: stop abusing swiotlb_max_segment (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: stop abusing swiotlb_max_segment (rev6)
URL   : https://patchwork.freedesktop.org/series/109946/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109946v6_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_109946v6_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_109946v6_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109946v6_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_ctx_persistence@many-contexts:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb8/igt@gem_ctx_persiste...@many-contexts.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/shard-iclb2/igt@gem_ctx_persiste...@many-contexts.html

  * igt@kms_flip@flip-vs-suspend@a-edp1:
- shard-skl:  [PASS][3] -> [DMESG-WARN][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@kms_flip@flip-vs-susp...@a-edp1.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/shard-skl7/igt@kms_flip@flip-vs-susp...@a-edp1.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl:  [PASS][5] -> [INCOMPLETE][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl6/igt@kms_frontbuffer_track...@psr-suspend.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/shard-skl6/igt@kms_frontbuffer_track...@psr-suspend.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@sysfs_timeslice_duration@idempotent@vcs0:
- {shard-dg1}:NOTRUN -> [FAIL][7] +9 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/shard-dg1-18/igt@sysfs_timeslice_duration@idempot...@vcs0.html

  
Known issues


  Here are the changes found in Patchwork_109946v6_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) +1 similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb1/igt@gem_exec_balan...@parallel-out-fence.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/shard-iclb6/igt@gem_exec_balan...@parallel-out-fence.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][12] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/shard-skl7/igt@gem_lmem_swapp...@parallel-random.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl:  NOTRUN -> [SKIP][14] ([fdo#109271]) +44 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/shard-skl7/igt@kms_big...@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_color_chamelium@ctm-limited-range:
- shard-skl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +2 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/shard-skl7/igt@kms_color_chamel...@ctm-limited-range.html

  * igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl:  [PASS][16] -> [INCOMPLETE][17] ([i915#180] / 
[i915#1982])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl6/igt@kms_fbcon_...@fbc-suspend.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/shard-apl8/igt@kms_fbcon_...@fbc-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl:  [PASS][18] -> [FAIL][19] ([i915#79]) +1 similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html
   [19]: 

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

[Hans de Goede]

Hi,

On 10/25/22 22:40, Matthew Garrett wrote:
> On Tue, Oct 25, 2022 at 10:25:33PM +0200, Hans de Goede wrote:
> 
>> Having the native driver come and then go and be replaced
>> with the vendor driver would also be quite inconvenient
>> for these planned changes.
> 
> I understand that it would be inconvenient, but you've broken existing 
> working setups.

I fully acknowledge that I have broken existing working setups
and I definitely want to see this fixed before say 6.1-rc6!

I'm not convinced (at all) that any solutions which re-introduce
acpi_video_get_backlight_type() return-s value changing
half way the boot, with some backlight interface getting
registered and then unregistered again later because
it turns out to be the wrong one is a good fix here.

The whole goal of the refactor was to leave these sorts
of shenanigans behind us.

>> Can you perhaps explain a bit in what way your laptop
>> is weird ?
> 
> It's a Chinese replacement motherboard for a Thinkpad X201, running my 
> own port of Coreboot. Its DMI strings look like an actual Thinkpad in 
> order to ensure that thinkpad_acpi can bind for hotkey suport, so it's 
> hard to quirk. It'll actually be fixed by your proposed patch to fall 
> back to native rather than vendor, but that patch will break any older 
> machines that offer a vendor interface and don't have the native control 
> hooked up (pretty sure at least the Thinkpad X40 falls into that 
> category).

So looking at:

https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src/mainboard/51nb/x210/acpi/graphics.asl

this code should actually set the ACPI_VIDEO_BACKLIGHT flag:
drivers/acpi/scan.c:

static acpi_status
acpi_backlight_cap_match(acpi_handle handle, u32 level, void *context,
  void **return_value)
{
long *cap = context;

if (acpi_has_method(handle, "_BCM") &&
acpi_has_method(handle, "_BCL")) {
acpi_handle_debug(handle, "Found generic backlight support\n");
*cap |= ACPI_VIDEO_BACKLIGHT;
/* We have backlight support, no need to scan further */
return AE_CTRL_TERMINATE;
}
return 0;
}

What does seem to be missing compared to a "normal" DSDT
is a call to _OSI("Windows 2012") so I would expect this code
in acpi_video_get_backlight_type():

/* On systems with ACPI video use either native or ACPI video. */
if (video_caps & ACPI_VIDEO_BACKLIGHT) {
/*
 * Windows 8 and newer no longer use the ACPI video interface,
 * so it often does not work. If the ACPI tables are written
 * for win8 and native brightness ctl is available, use that.
 *
 * The native check deliberately is inside the if acpi-video
 * block on older devices without acpi-video support native
 * is usually not the best choice.
 */
if (acpi_osi_is_win8() && native_available)
return acpi_backlight_native;
else
return acpi_backlight_video;
}

To enter the "return acpi_backlight_video" path since acpi_osi_is_win8()
will return false.

And then the ACPI backlight methods from:
https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src/mainboard/51nb/x210/acpi/graphics.asl

should get called when changing the backlight brightness,
so assuming that those methods work then things should work fine.

What does "ls /sys/class/backlight" output on the X210 / NB51 board
with a 6.0 kernel? And what does it output with the 6.1-rc? kernels?

IOW which backlight device / control method is being selected
and which one do you want / which one(s) do actually work?

I have been thinking about maybe doing something with 
a dmi_get_bios_year() check (see below), but that will cause
native to get prefered over vendor on old ThinkPads with
coreboot (and thus a new enough year in DMI_BIOS_DATE), which
will likely break backlight control there (if i915 offers
backlight control on those that is).

Also I wonder if it would be possible to set DMI_BIOS_VENDOR
to "Coreboot" so that we can use that? Note that thinkpad_acpi
does not care about the DMI_BIOS_VENDOR value, at least
not on models which start their DMI_PRODUCT_VERSION with
either "ThinkPad" or "Lenovo".

###

Looking more at this I notice that coreboot has a
drivers_intel_gma_displays_ssdt_generate() which seems to
at least always generate ACPI video bus ASL including
backlight control bits.

So the only reason why the current heurstics are not
returning native is the acpi_osi_is_win8() check.

So maybe that beeds to become:

if ((acpi_osi_is_win8() || dmi_get_bios_year() >= 2018) && 
native_available)
return acpi_backlight_native;
else
return acpi_backlight_video;

Although I think that will result 

[Intel-gfx] [CI 4/4] drm/i915/display: Move squash_ctl register programming to its own function

[Anusha Srivatsa]

No functional change. Introduce dg2_cdclk_squash_program and
move squash_ctl register programming bits to this.

v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)

Cc: Jani Nikula 
Cc: Balasubramani Vivekanandan 
Cc: Ville Syrjälä 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Balasubramani Vivekanandan 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +-
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9cd02b85ee51..eada931cb1c8 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1704,6 +1704,18 @@ static void bxt_cdclk_pll_update(struct drm_i915_private 
*i915, int vco)
bxt_de_pll_enable(i915, vco);
 }
 
+static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
+u16 waveform)
+{
+   u32 squash_ctl = 0;
+
+   if (waveform)
+   squash_ctl = CDCLK_SQUASH_ENABLE |
+CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
+
+   intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
+}
+
 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
  const struct intel_cdclk_config *cdclk_config,
  enum pipe pipe)
@@ -1751,15 +1763,8 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
else
clock = cdclk;
 
-   if (HAS_CDCLK_SQUASH(dev_priv)) {
-   u32 squash_ctl = 0;
-
-   if (waveform)
-   squash_ctl = CDCLK_SQUASH_ENABLE |
-   CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
-
-   intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
-   }
+   if (HAS_CDCLK_SQUASH(dev_priv))
+   dg2_cdclk_squash_program(dev_priv, waveform);
 
val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
-- 
2.25.1

[Intel-gfx] [CI 3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk()

[Anusha Srivatsa]

No functional change. Moving segments out to simplify
bxt_set_cdlck()

v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani)

Cc: Jani Nikula 
Cc: Balasubramani Vivekanandan 
Cc: Ville Syrjälä 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Balasubramani Vivekanandan 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 39 +-
 1 file changed, 24 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 45babbc6290f..9cd02b85ee51 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1684,6 +1684,26 @@ static u32 cdclk_squash_waveform(struct drm_i915_private 
*dev_priv,
return 0x;
 }
 
+static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco)
+{
+   if (i915->display.cdclk.hw.vco != 0 &&
+   i915->display.cdclk.hw.vco != vco)
+   icl_cdclk_pll_disable(i915);
+
+   if (i915->display.cdclk.hw.vco != vco)
+   icl_cdclk_pll_enable(i915, vco);
+}
+
+static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
+{
+   if (i915->display.cdclk.hw.vco != 0 &&
+   i915->display.cdclk.hw.vco != vco)
+   bxt_de_pll_disable(i915);
+
+   if (i915->display.cdclk.hw.vco != vco)
+   bxt_de_pll_enable(i915, vco);
+}
+
 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
  const struct intel_cdclk_config *cdclk_config,
  enum pipe pipe)
@@ -1719,21 +1739,10 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && 
vco > 0) {
if (dev_priv->display.cdclk.hw.vco != vco)
adlp_cdclk_pll_crawl(dev_priv, vco);
-   } else if (DISPLAY_VER(dev_priv) >= 11) {
-   if (dev_priv->display.cdclk.hw.vco != 0 &&
-   dev_priv->display.cdclk.hw.vco != vco)
-   icl_cdclk_pll_disable(dev_priv);
-
-   if (dev_priv->display.cdclk.hw.vco != vco)
-   icl_cdclk_pll_enable(dev_priv, vco);
-   } else {
-   if (dev_priv->display.cdclk.hw.vco != 0 &&
-   dev_priv->display.cdclk.hw.vco != vco)
-   bxt_de_pll_disable(dev_priv);
-
-   if (dev_priv->display.cdclk.hw.vco != vco)
-   bxt_de_pll_enable(dev_priv, vco);
-   }
+   } else if (DISPLAY_VER(dev_priv) >= 11)
+   icl_cdclk_pll_update(dev_priv, vco);
+   else
+   bxt_cdclk_pll_update(dev_priv, vco);
 
waveform = cdclk_squash_waveform(dev_priv, cdclk);
 
-- 
2.25.1

[Intel-gfx] [CI 1/4] drm/i915/display: Change terminology for cdclk actions

[Anusha Srivatsa]

No functional changes. Changing terminology in some
print statements. s/has_cdclk_squasher/has_cdclk_squash,
s/crawler/crawl and s/squasher/squash.

Cc: Balasubramani Vivekanandan 
Cc: Ville Syrjälä 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Balasubramani Vivekanandan 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ad401357ab66..0f5add2fc51b 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1220,7 +1220,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private 
*dev_priv)
skl_set_cdclk(dev_priv, _config, INVALID_PIPE);
 }
 
-static bool has_cdclk_squasher(struct drm_i915_private *i915)
+static bool has_cdclk_squash(struct drm_i915_private *i915)
 {
return IS_DG2(i915);
 }
@@ -1520,7 +1520,7 @@ static void bxt_get_cdclk(struct drm_i915_private 
*dev_priv,
return;
}
 
-   if (has_cdclk_squasher(dev_priv))
+   if (has_cdclk_squash(dev_priv))
squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
 
if (squash_ctl & CDCLK_SQUASH_ENABLE) {
@@ -1747,7 +1747,7 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
else
clock = cdclk;
 
-   if (has_cdclk_squasher(dev_priv)) {
+   if (has_cdclk_squash(dev_priv)) {
u32 squash_ctl = 0;
 
if (waveform)
@@ -1845,7 +1845,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private 
*dev_priv)
expected = skl_cdclk_decimal(cdclk);
 
/* Figure out what CD2X divider we should be using for this cdclk */
-   if (has_cdclk_squasher(dev_priv))
+   if (has_cdclk_squash(dev_priv))
clock = dev_priv->display.cdclk.hw.vco / 2;
else
clock = dev_priv->display.cdclk.hw.cdclk;
@@ -1976,7 +1976,7 @@ static bool intel_cdclk_can_squash(struct 
drm_i915_private *dev_priv,
 * the moment all platforms with squasher use a fixed cd2x
 * divider.
 */
-   if (!has_cdclk_squasher(dev_priv))
+   if (!has_cdclk_squash(dev_priv))
return false;
 
return a->cdclk != b->cdclk &&
@@ -2028,7 +2028,7 @@ static bool intel_cdclk_can_cd2x_update(struct 
drm_i915_private *dev_priv,
 * the moment all platforms with squasher use a fixed cd2x
 * divider.
 */
-   if (has_cdclk_squasher(dev_priv))
+   if (has_cdclk_squash(dev_priv))
return false;
 
return a->cdclk != b->cdclk &&
@@ -2754,12 +2754,12 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state 
*state)
   _cdclk_state->actual,
   _cdclk_state->actual)) {
drm_dbg_kms(_priv->drm,
-   "Can change cdclk via squasher\n");
+   "Can change cdclk via squashing\n");
} else if (intel_cdclk_can_crawl(dev_priv,
 _cdclk_state->actual,
 _cdclk_state->actual)) {
drm_dbg_kms(_priv->drm,
-   "Can change cdclk via crawl\n");
+   "Can change cdclk via crawling\n");
} else if (pipe != INVALID_PIPE) {
new_cdclk_state->pipe = pipe;
 
-- 
2.25.1

[Intel-gfx] [CI 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro

[Anusha Srivatsa]

Driver had discrepancy in how cdclk squash and crawl support
were checked. Like crawl, add squash as a 1 bit feature flag
to the display section of DG2.

Cc: Balasubramani Vivekanandan 
Cc: Ville Syrjälä 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Balasubramani Vivekanandan 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +--
 drivers/gpu/drm/i915/i915_drv.h|  1 +
 drivers/gpu/drm/i915/i915_pci.c|  1 +
 drivers/gpu/drm/i915/intel_device_info.h   |  1 +
 4 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0f5add2fc51b..45babbc6290f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1220,11 +1220,6 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private 
*dev_priv)
skl_set_cdclk(dev_priv, _config, INVALID_PIPE);
 }
 
-static bool has_cdclk_squash(struct drm_i915_private *i915)
-{
-   return IS_DG2(i915);
-}
-
 struct intel_cdclk_vals {
u32 cdclk;
u16 refclk;
@@ -1520,7 +1515,7 @@ static void bxt_get_cdclk(struct drm_i915_private 
*dev_priv,
return;
}
 
-   if (has_cdclk_squash(dev_priv))
+   if (HAS_CDCLK_SQUASH(dev_priv))
squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
 
if (squash_ctl & CDCLK_SQUASH_ENABLE) {
@@ -1747,7 +1742,7 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
else
clock = cdclk;
 
-   if (has_cdclk_squash(dev_priv)) {
+   if (HAS_CDCLK_SQUASH(dev_priv)) {
u32 squash_ctl = 0;
 
if (waveform)
@@ -1845,7 +1840,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private 
*dev_priv)
expected = skl_cdclk_decimal(cdclk);
 
/* Figure out what CD2X divider we should be using for this cdclk */
-   if (has_cdclk_squash(dev_priv))
+   if (HAS_CDCLK_SQUASH(dev_priv))
clock = dev_priv->display.cdclk.hw.vco / 2;
else
clock = dev_priv->display.cdclk.hw.cdclk;
@@ -1976,7 +1971,7 @@ static bool intel_cdclk_can_squash(struct 
drm_i915_private *dev_priv,
 * the moment all platforms with squasher use a fixed cd2x
 * divider.
 */
-   if (!has_cdclk_squash(dev_priv))
+   if (!HAS_CDCLK_SQUASH(dev_priv))
return false;
 
return a->cdclk != b->cdclk &&
@@ -2028,7 +2023,7 @@ static bool intel_cdclk_can_cd2x_update(struct 
drm_i915_private *dev_priv,
 * the moment all platforms with squasher use a fixed cd2x
 * divider.
 */
-   if (has_cdclk_squash(dev_priv))
+   if (HAS_CDCLK_SQUASH(dev_priv))
return false;
 
return a->cdclk != b->cdclk &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d7b8eb9d4117..db51050e3ba2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -869,6 +869,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)  (DISPLAY_VER(dev_priv) >= 9 || 
IS_BROADWELL(dev_priv))
 
 #define HAS_CDCLK_CRAWL(dev_priv)   
(INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
+#define HAS_CDCLK_SQUASH(dev_priv)  
(INTEL_INFO(dev_priv)->display.has_cdclk_squash)
 #define HAS_DDI(dev_priv)   (INTEL_INFO(dev_priv)->display.has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) 
(INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 #define HAS_PSR(dev_priv)   (INTEL_INFO(dev_priv)->display.has_psr)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 19bf5ef6a20d..a88e1439a426 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1064,6 +1064,7 @@ static const struct intel_device_info xehpsdv_info = {
.has_guc_deprivilege = 1, \
.has_heci_pxp = 1, \
.has_media_ratio_mode = 1, \
+   .display.has_cdclk_squash = 1, \
.__runtime.platform_engine_mask = \
BIT(RCS0) | BIT(BCS0) | \
BIT(VECS0) | BIT(VECS1) | \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index cdf78728dcad..67d8759c802c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -180,6 +180,7 @@ enum intel_ppgtt_type {
/* Keep in alphabetical order */ \
func(cursor_needs_physical); \
func(has_cdclk_crawl); \
+   func(has_cdclk_squash); \
func(has_ddi); \
func(has_dp_mst); \
func(has_dsb); \
-- 
2.25.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/slpc: Optmize waitboost for SLPC (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915/slpc: Optmize waitboost for SLPC (rev7)
URL   : https://patchwork.freedesktop.org/series/109840/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12294 -> Patchwork_109840v7


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v7/index.html

Participating hosts (40 -> 37)
--

  Additional (1): fi-skl-guc 
  Missing(4): fi-ctg-p8600 fi-hsw-4770 fi-icl-u2 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_109840v7 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[PASS][1] -> [FAIL][2] ([i915#7229])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v7/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_lmem_swapping@basic:
- fi-skl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v7/fi-skl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-guc: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v7/fi-skl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-skl-guc: NOTRUN -> [SKIP][5] ([fdo#109271]) +10 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v7/fi-skl-guc/igt@kms_setm...@basic-clone-single-crtc.html

  
 Possible fixes 

  * igt@fbdev@read:
- {bat-rpls-2}:   [SKIP][6] ([i915#2582]) -> [PASS][7] +4 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-2/igt@fb...@read.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v7/bat-rpls-2/igt@fb...@read.html

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-adlm-1}:   [DMESG-WARN][8] ([i915#2867]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v7/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html
- {bat-rpls-1}:   [DMESG-WARN][10] ([i915#6687]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v7/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@slpc:
- {bat-rpls-1}:   [DMESG-FAIL][12] ([i915#6367]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-1/igt@i915_selftest@l...@slpc.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v7/bat-rpls-1/igt@i915_selftest@l...@slpc.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [FAIL][14] ([i915#6298]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v7/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7029]: https://gitlab.freedesktop.org/drm/intel/issues/7029
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229


Build changes
-

  * Linux: CI_DRM_12294 -> Patchwork_109840v7

  CI-20190529: 20190529
  CI_DRM_12294: fca30d6149441ff19df784c0554b8c20a29c7f53 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7026: ce0f97e7e0aa54c40049a8365b3d61773c92e588 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_109840v7: fca30d6149441ff19df784c0554b8c20a29c7f53 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

26d7ed1dac45 drm/i915/slpc: 

[Intel-gfx] ✓ Fi.CI.BAT: success for Add DG2 OA support (rev10)

[Patchwork]

== Series Details ==

Series: Add DG2 OA support (rev10)
URL   : https://patchwork.freedesktop.org/series/107584/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12294 -> Patchwork_107584v10


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v10/index.html

Participating hosts (40 -> 40)
--

  Additional (2): fi-skl-guc fi-tgl-dsi 
  Missing(2): fi-ctg-p8600 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_107584v10:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-edp-1:
- {bat-jsl-1}:[PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-jsl-1/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-edp-1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v10/bat-jsl-1/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-edp-1.html

  
Known issues


  Here are the changes found in Patchwork_107584v10 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-skl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v10/fi-skl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v10/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v10/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-icl-u2:  NOTRUN -> [SKIP][6] ([fdo#111827])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v10/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-guc: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v10/fi-skl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][8] ([fdo#109285])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v10/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-skl-guc: NOTRUN -> [SKIP][9] ([fdo#109271]) +10 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v10/fi-skl-guc/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([i915#3555])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v10/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-icl-u2:  NOTRUN -> [SKIP][11] ([fdo#109295] / [i915#3301])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v10/fi-icl-u2/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-adlm-1}:   [DMESG-WARN][12] ([i915#2867]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v10/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [INCOMPLETE][14] ([i915#3303] / [i915#4785]) -> 
[PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v10/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * 
igt@kms_cursor_legacy@basic-flip-after-cursor@atomic-transitions-varying-size:
- fi-icl-u2:  [DMESG-WARN][16] ([i915#4890]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cur...@atomic-transitions-varying-size.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v10/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cur...@atomic-transitions-varying-size.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109284]: 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/xelp: Add Wa_1806527549 (rev2)

[Gustavo Sousa]

On Thu, Oct 20, 2022 at 01:00:27AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/xelp: Add Wa_1806527549 (rev2)
> URL   : https://patchwork.freedesktop.org/series/109885/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_12261_full -> Patchwork_109885v2_full
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_109885v2_full absolutely need 
> to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_109885v2_full, please notify your bug team to allow 
> them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (9 -> 12)
> --
> 
>   Additional (3): shard-rkl shard-dg1 shard-tglu 
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_109885v2_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@i915_selftest@live@mman:
> - shard-skl:  NOTRUN -> [INCOMPLETE][1] +1 similar issue
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-skl2/igt@i915_selftest@l...@mman.html

Not related to this patch, as the workaround does not target this platform.

> 
>   * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
> - shard-iclb: [PASS][2] -> [FAIL][3]
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-iclb8/igt@kms_big...@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-iclb2/igt@kms_big...@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

Existing issue: http://gfx-ci.fi.intel.com/cibuglog-ng/issue/7783

> 
>   * igt@kms_plane_lowres@tiling-none@pipe-b-hdmi-a-1:
> - shard-glk:  [PASS][4] -> [FAIL][5]
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-glk9/igt@kms_plane_lowres@tiling-n...@pipe-b-hdmi-a-1.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-glk3/igt@kms_plane_lowres@tiling-n...@pipe-b-hdmi-a-1.html

Maybe related to http://gfx-ci.fi.intel.com/cibuglog-ng/issue/7841 ?

Nevertheless, not related to this patch, as the workaround does not target this 
platform.

> 
>   
>  Warnings 
> 
>   * igt@runner@aborted:
> - shard-skl:  ([FAIL][6], [FAIL][7], [FAIL][8], [FAIL][9], 
> [FAIL][10]) ([i915#3002] / [i915#4312] / [i915#6949]) -> ([FAIL][11], 
> [FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15], [FAIL][16], [FAIL][17], 
> [FAIL][18]) ([i915#3002] / [i915#4312])
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-skl4/igt@run...@aborted.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-skl6/igt@run...@aborted.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-skl2/igt@run...@aborted.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-skl6/igt@run...@aborted.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12261/shard-skl10/igt@run...@aborted.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-skl5/igt@run...@aborted.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-skl5/igt@run...@aborted.html
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-skl10/igt@run...@aborted.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-skl7/igt@run...@aborted.html
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-skl10/igt@run...@aborted.html
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-skl4/igt@run...@aborted.html
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-skl1/igt@run...@aborted.html
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-skl2/igt@run...@aborted.html
> 
>   
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * igt@gem_pwrite@basic-exhaustion:
> - {shard-rkl}:NOTRUN -> [INCOMPLETE][19]
>[19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-rkl-5/igt@gem_pwr...@basic-exhaustion.html
> 
>   * igt@kms_big_fb@linear-64bpp-rotate-0:
> - {shard-dg1}:NOTRUN -> [FAIL][20]
>[20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109885v2/shard-dg1-13/igt@kms_big...@linear-64bpp-rotate-0.html
> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_109885v2_full that come from known 
> issues:
> 
> ### CI changes ###
> 
>  Issues hit 
> 
>   * boot:
> - shard-glk:  ([PASS][21], [PASS][22], 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Prep work for finishing (de)gamma readout (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Prep work for finishing (de)gamma readout (rev3)
URL   : https://patchwork.freedesktop.org/series/109229/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109229v3_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_109229v3_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_109229v3_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109229v3_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_ctx_isolation@preservation-s3@vcs1:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb5/igt@gem_ctx_isolation@preservation...@vcs1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/shard-tglb5/igt@gem_ctx_isolation@preservation...@vcs1.html

  * igt@kms_cursor_legacy@flip-vs-cursor@varying-size:
- shard-skl:  [PASS][3] -> [FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl6/igt@kms_cursor_legacy@flip-vs-cur...@varying-size.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/shard-skl6/igt@kms_cursor_legacy@flip-vs-cur...@varying-size.html

  
 Warnings 

  * igt@runner@aborted:
- shard-skl:  ([FAIL][5], [FAIL][6], [FAIL][7], [FAIL][8], 
[FAIL][9], [FAIL][10]) ([i915#3002] / [i915#4312] / [i915#6949]) -> 
([FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15], [FAIL][16]) 
([i915#3002] / [i915#4312])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl7/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@run...@aborted.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl7/igt@run...@aborted.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@run...@aborted.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@run...@aborted.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/shard-skl7/igt@run...@aborted.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/shard-skl10/igt@run...@aborted.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/shard-skl6/igt@run...@aborted.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/shard-skl9/igt@run...@aborted.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/shard-skl9/igt@run...@aborted.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/shard-skl10/igt@run...@aborted.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@sysfs_timeslice_duration@idempotent@vcs0:
- {shard-dg1}:NOTRUN -> [FAIL][17] +9 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/shard-dg1-15/igt@sysfs_timeslice_duration@idempot...@vcs0.html

  
Known issues


  Here are the changes found in Patchwork_109229v3_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][18] -> [FAIL][19] ([i915#6268])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb2/igt@gem_ctx_e...@basic-nohangcheck.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/shard-tglb7/igt@gem_ctx_e...@basic-nohangcheck.html

  * igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][20] -> [SKIP][21] ([i915#4525]) +1 similar 
issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb1/igt@gem_exec_balan...@parallel-out-fence.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/shard-iclb6/igt@gem_exec_balan...@parallel-out-fence.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][22] -> [FAIL][23] ([i915#2842])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/shard-apl3/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][24] -> [FAIL][25] ([i915#2842])
   [24]: 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DG2 OA support (rev10)

[Patchwork]

== Series Details ==

Series: Add DG2 OA support (rev10)
URL   : https://patchwork.freedesktop.org/series/107584/
State : warning

== Summary ==

Error: dim checkpatch failed
f49ce1a759c5 drm/i915/perf: Fix OA filtering logic for GuC mode
5e811f8d8045 drm/i915/perf: Add 32-bit OAG and OAR formats for DG2
f2a0f8c599db drm/i915/perf: Fix noa wait predication for DG2
4c9bee347d42 drm/i915/perf: Determine gen12 oa ctx offset at runtime
800eb9bbcb4d drm/i915/perf: Enable bytes per clock reporting in OA
15c429e4a3e7 drm/i915/perf: Simply use stream->ctx
d7a5269e6445 drm/i915/perf: Move gt-specific data from i915->perf to gt->perf
98fa8eb88966 drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops
276c535aa192 drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers
cd3045fcbfd0 drm/i915/perf: Store a pointer to oa_format in oa_buffer
f44a92bea371 drm/i915/perf: Add Wa_1508761755:dg2
-:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#50: FILE: drivers/gpu/drm/i915/i915_perf.c:2786:
+   intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
+  
_MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));

-:68: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#68: FILE: drivers/gpu/drm/i915/i915_perf.c:2875:
+   intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
+  
_MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));

total: 0 errors, 0 warnings, 2 checks, 49 lines checked
fe2dbc205304 drm/i915/perf: Apply Wa_18013179988
a4b7e46b4cd2 drm/i915/perf: Save/restore EU flex counters across reset
5eb41a815bbb drm/i915/guc: Support OA when Wa_16011777198 is enabled
-:72: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#72: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c:208:
+   GEM_BUG_ON(id >= SLPC_MAX_PARAM);

total: 0 errors, 1 warnings, 0 checks, 151 lines checked
2e3fe9aba6f6 drm/i915/perf: complete programming whitelisting for XEHPSDV
883cba29d24f drm/i915/perf: Enable OA for DG2

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix CFI violations in gt_sysfs (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix CFI violations in gt_sysfs (rev5)
URL   : https://patchwork.freedesktop.org/series/108917/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12294 -> Patchwork_108917v5


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v5/index.html

Participating hosts (40 -> 39)
--

  Additional (1): fi-skl-guc 
  Missing(2): fi-ctg-p8600 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_108917v5:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-5:
- {bat-rpls-2}:   [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-2/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-dp-5.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v5/bat-rpls-2/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-dp-5.html

  
Known issues


  Here are the changes found in Patchwork_108917v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[PASS][3] -> [FAIL][4] ([i915#7229])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v5/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_lmem_swapping@basic:
- fi-skl-guc: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v5/fi-skl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [PASS][6] -> [INCOMPLETE][7] ([i915#7056])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v5/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v5/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v5/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-guc: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v5/fi-skl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * 
igt@kms_cursor_legacy@basic-flip-before-cursor@atomic-transitions-varying-size:
- fi-icl-u2:  NOTRUN -> [DMESG-WARN][11] ([i915#4890])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v5/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cur...@atomic-transitions-varying-size.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-skl-guc: NOTRUN -> [SKIP][12] ([fdo#109271]) +10 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v5/fi-skl-guc/igt@kms_psr@sprite_plane_onoff.html

  
 Possible fixes 

  * igt@fbdev@read:
- {bat-rpls-2}:   [SKIP][13] ([i915#2582]) -> [PASS][14] +4 similar 
issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-2/igt@fb...@read.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v5/bat-rpls-2/igt@fb...@read.html

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-adlm-1}:   [DMESG-WARN][15] ([i915#2867]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v5/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][17] ([i915#4785]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v5/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-g3258:   [INCOMPLETE][19] ([i915#3303] / [i915#4785]) -> 
[PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108917v5/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix CFI violations in gt_sysfs (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix CFI violations in gt_sysfs (rev5)
URL   : https://patchwork.freedesktop.org/series/108917/
State : warning

== Summary ==

Error: dim checkpatch failed
e2d4c2e70109 drm/i915: Fix CFI violations in gt_sysfs
-:125: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#125: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs.c:61:
 }
+static struct kobj_attribute attr_id = __ATTR_RO(id);

-:268: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_name' - possible 
side-effects?
#268: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:155:
+#define INTEL_GT_DUAL_ATTR_RW(_name) \
+   static struct device_attribute dev_attr_##_name = __ATTR(_name, 0644,   
\
+
_name##_dev_show,  \
+
_name##_dev_store);\
+   INTEL_GT_ATTR_RW(_name)

-:274: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_name' - possible 
side-effects?
#274: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:161:
+#define INTEL_GT_DUAL_ATTR_RO(_name) \
+   static struct device_attribute dev_attr_##_name = __ATTR(_name, 0444,   
\
+
_name##_dev_show,  \
+NULL); 
\
+   INTEL_GT_ATTR_RO(_name)

-:656: CHECK:CAMELCASE: Avoid CamelCase: 
#656: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:405:
+INTEL_GT_SYSFS_SHOW_MAX(RPn_freq_mhz);

-:664: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_mode' - possible 
side-effects?
#664: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:413:
+#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store, _show_dev, 
_store_dev)\
+   static struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, 
_mode,  \
+   _show_dev, 
_store_dev); \
+   static struct kobj_attribute attr_rps_##_name = __ATTR(rps_##_name, 
_mode,  \
+  _show, _store)

-:705: CHECK:CAMELCASE: Avoid CamelCase: 
#705: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:445:
+   ##attr_##s##_RPn_freq_mhz.attr, \

-:842: CHECK:CAMELCASE: Avoid CamelCase: 
#842: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:675:
+INTEL_GT_ATTR_RO(media_RPn_freq_mhz);

-:852: CHECK:CAMELCASE: Avoid CamelCase: 
#852: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:681:
+   _media_RPn_freq_mhz.attr,

total: 0 errors, 0 warnings, 8 checks, 785 lines checked

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/kms: Stop registering multiple /sys/class/backlight devs for a single display (rev3)

[Patchwork]

== Series Details ==

Series: drm/kms: Stop registering multiple /sys/class/backlight devs for a 
single display (rev3)
URL   : https://patchwork.freedesktop.org/series/107755/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/107755/revisions/3/mbox/ not 
applied
Applying: ACPI: video: Add acpi_video_backlight_use_native() helper
Using index info to reconstruct a base tree...
M   drivers/acpi/video_detect.c
M   include/acpi/video.h
Falling back to patching base and 3-way merge...
Auto-merging include/acpi/video.h
CONFLICT (content): Merge conflict in include/acpi/video.h
Auto-merging drivers/acpi/video_detect.c
CONFLICT (content): Merge conflict in drivers/acpi/video_detect.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 ACPI: video: Add acpi_video_backlight_use_native() helper
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Connect VFIO to IOMMUFD

[Patchwork]

== Series Details ==

Series: Connect VFIO to IOMMUFD
URL   : https://patchwork.freedesktop.org/series/110133/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/110133/revisions/1/mbox/ not 
applied
Applying: vfio: Move vfio_device driver open/close code to a function
Applying: vfio: Move vfio_device_assign_container() into 
vfio_device_first_open()
Applying: vfio: Rename vfio_device_assign/unassign_container()
Applying: vfio: Move storage of allow_unsafe_interrupts to vfio_main.c
Applying: vfio: Use IOMMU_CAP_ENFORCE_CACHE_COHERENCY for 
vfio_file_enforced_coherent()
Applying: vfio-iommufd: Allow iommufd to be used in place of a container fd
Applying: vfio-iommufd: Support iommufd for physical VFIO devices
Applying: vfio-iommufd: Support iommufd for emulated VFIO devices
Applying: vfio: Make vfio_container optionally compiled
Applying: iommufd: Allow iommufd to supply /dev/vfio/vfio
error: sha1 information is lacking or useless (drivers/iommu/iommufd/Kconfig).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0010 iommufd: Allow iommufd to supply /dev/vfio/vfio
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

[Matthew Garrett]

On Tue, Oct 25, 2022 at 10:25:33PM +0200, Hans de Goede wrote:

> Having the native driver come and then go and be replaced
> with the vendor driver would also be quite inconvenient
> for these planned changes.

I understand that it would be inconvenient, but you've broken existing 
working setups.
 
> Can you perhaps explain a bit in what way your laptop
> is weird ?

It's a Chinese replacement motherboard for a Thinkpad X201, running my 
own port of Coreboot. Its DMI strings look like an actual Thinkpad in 
order to ensure that thinkpad_acpi can bind for hotkey suport, so it's 
hard to quirk. It'll actually be fixed by your proposed patch to fall 
back to native rather than vendor, but that patch will break any older 
machines that offer a vendor interface and don't have the native control 
hooked up (pretty sure at least the Thinkpad X40 falls into that 
category).

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

[Hans de Goede]

Hi (again),

On 10/25/22 22:25, Hans de Goede wrote:
> Hi Matthew,
> 
> On 10/25/22 21:32, Matthew Garrett wrote:
>> On Tue, Oct 25, 2022 at 08:50:54PM +0200, Hans de Goede wrote:
>>
>>> That is a valid point, but keep in mind that this is only used on ACPI
>>> platforms and then only on devices with a builtin LCD panel and then
>>> only by GPU drivers which actually call acpi_video_get_backlight_type(),
>>> so e.g. not by all the ARM specific display drivers.
>>>
>>> So I believe that Chromebooks quite likely are the only devices with
>>> this issue.
>>
>> My laptop is, uh, weird, but it falls into this category.
>>  
 I think for this to work correctly you need to have 
 the infrastructure be aware of whether or not a vendor interface exists, 
 which means having to handle cleanup if a vendor-specific module gets 
 loaded later.
>>>
>>> Getting rid of the whole ping-ponging of which backlight drivers
>>> get loaded during boot was actually one of the goals of the rework
>>> which landed in 6.1 this actually allowed us to remove some quirks
>>> because some hw/firmware did not like us changing our mind and
>>> switching backlight interfaces after first poking another one.
>>> So we definitely don't want to go back to the ping-pong thing.
>>
>> Defaulting to native but then having a vendor driver be able to disable 
>> native drivers seems easiest? It shouldn't be a regression over the 
>> previous state of affairs since both drivers were being loaded already.
> 
> Part of the reason for the ACPI backlight detect refactor is
> because of a planned new backlight uAPI where the brightness
> control becomes a property on the drm connector object, for a
> RFC including the rationale behind this planned uAPI change see:
> https://lore.kernel.org/dri-devel/b61d3eeb-6213-afac-2e70-7b9791c86...@redhat.com/
> 
> These plans require that there is only 1 backlight device
> registered (per panel).
> 
> Having the native driver come and then go and be replaced
> with the vendor driver would also be quite inconvenient
> for these planned changes.
> 
> As such I would rather find a solution for your "weird"
> laptop so that acpi_video_get_backlight_type() just always
> returns vendor there.

I just realized that your have vendor driver unregister
the native one is suggested as an alternative for
the new behavior where the i915 driver no longer
registers its native backlight in cases where
acpi_video_get_backlight_type() does not return native,
and that you probably actually want the native backlight
device, right ?

So the above should read:

"so that acpi_video_get_backlight_type() just always
returns native there."

> Note that drivers/acpi/video_detect.c already has a DMI
> quirk tables for models where the heuristics from
> acpi_video_get_backlight_type() don't work. In general
> we (mostly me) try to make it so that the heuristics
> work on most models, to avoid needing to add every model
> under the sun to the DMI quirk table, but if your laptop
> is somehow special then adding a DMI quirk for it should
> be fine ?
> 
> Can you perhaps explain a bit in what way your laptop
> is weird ?

I guess it is weird in that it does not have the ACPI video,
or at least does not offer ACPI video bus backlight control
in its ACPI tables?

Can you perhaps email me an acpidump of the laptop ?

> Note that technically if the native backlight does not work,
> then the GPU driver really should not even try to register
> it. But sometimes the video-bios-tables claim the backlight
> pwm input is attached to the GPU while it is not and things
> have evolved in such a way that the DMI quirks for that
> live in acpi/video_detect.c rather then in the GPU driver.

And this bit can be ignored then because it certainly
is not relevant if you actually want the native driver.

Regards,

Hans

Re: [Intel-gfx] [PATCH] drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode

[Ville Syrjälä]

On Tue, Oct 25, 2022 at 08:47:32PM +0300, Jani Nikula wrote:
> On Tue, 25 Oct 2022, Ville Syrjala  wrote:
> > From: Ville Syrjälä 
> >
> > If we can't dig out a fixed mode for LVDS from the VBT or EDID
> > let's fall back to using the current output timings. This should
> > work as long as the BIOS has (somehow) enabled the output.
> >
> > In this case we are dealing with the some kind of BLB based POS
> > machine (Toshiba SurePOS 500) where neither the OpRegion mailbox
> > nor the vbios ROM contain a valid VBT. And no EDID anywhere we
> > could find either.
> >
> > Cc:  # v5.19+
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7301
> > Signed-off-by: Ville Syrjälä 
> 
> Reviewed-by: Jani Nikula 
> 
> But they're saying it's a regression between 4.19 and 5.10...

Yeah. I can't actually figure out how it could have worked even
with 4.19.

Hmm. Actually now that I look at some of the hints in the logs it
does look like it maybe did find an EDID after all. What confused
me was that all the modes very much like the _noedid stuff.

Ah, it looks like we fail to fully initialize the DDC stuff
before setting up the outputs, which I guess explains why the
EDID read fails there. Previously there was this funky feedback
loop in that .get_modes() actually filled in the fixed_mode,
so until you called that (after everything else was fully set
up) you didn't have a fixed mode.

And while looking at this stuff more I can see that the whole
multi output support is still very much snafu :/

I'll see if I can make a fairly minimal fix for now...

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

[Hans de Goede]

Hi Matthew,

On 10/25/22 21:32, Matthew Garrett wrote:
> On Tue, Oct 25, 2022 at 08:50:54PM +0200, Hans de Goede wrote:
> 
>> That is a valid point, but keep in mind that this is only used on ACPI
>> platforms and then only on devices with a builtin LCD panel and then
>> only by GPU drivers which actually call acpi_video_get_backlight_type(),
>> so e.g. not by all the ARM specific display drivers.
>>
>> So I believe that Chromebooks quite likely are the only devices with
>> this issue.
> 
> My laptop is, uh, weird, but it falls into this category.
>  
>>> I think for this to work correctly you need to have 
>>> the infrastructure be aware of whether or not a vendor interface exists, 
>>> which means having to handle cleanup if a vendor-specific module gets 
>>> loaded later.
>>
>> Getting rid of the whole ping-ponging of which backlight drivers
>> get loaded during boot was actually one of the goals of the rework
>> which landed in 6.1 this actually allowed us to remove some quirks
>> because some hw/firmware did not like us changing our mind and
>> switching backlight interfaces after first poking another one.
>> So we definitely don't want to go back to the ping-pong thing.
> 
> Defaulting to native but then having a vendor driver be able to disable 
> native drivers seems easiest? It shouldn't be a regression over the 
> previous state of affairs since both drivers were being loaded already.

Part of the reason for the ACPI backlight detect refactor is
because of a planned new backlight uAPI where the brightness
control becomes a property on the drm connector object, for a
RFC including the rationale behind this planned uAPI change see:
https://lore.kernel.org/dri-devel/b61d3eeb-6213-afac-2e70-7b9791c86...@redhat.com/

These plans require that there is only 1 backlight device
registered (per panel).

Having the native driver come and then go and be replaced
with the vendor driver would also be quite inconvenient
for these planned changes.

As such I would rather find a solution for your "weird"
laptop so that acpi_video_get_backlight_type() just always
returns vendor there.

Note that drivers/acpi/video_detect.c already has a DMI
quirk tables for models where the heuristics from
acpi_video_get_backlight_type() don't work. In general
we (mostly me) try to make it so that the heuristics
work on most models, to avoid needing to add every model
under the sun to the DMI quirk table, but if your laptop
is somehow special then adding a DMI quirk for it should
be fine ?

Can you perhaps explain a bit in what way your laptop
is weird ?

Note that technically if the native backlight does not work,
then the GPU driver really should not even try to register
it. But sometimes the video-bios-tables claim the backlight
pwm input is attached to the GPU while it is not and things
have evolved in such a way that the DMI quirks for that
live in acpi/video_detect.c rather then in the GPU driver.

Regards,

Hans

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/display: Change terminology for cdclk actions

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/display: Change terminology for 
cdclk actions
URL   : https://patchwork.freedesktop.org/series/110135/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12294 -> Patchwork_110135v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110135v1/index.html

Participating hosts (40 -> 39)
--

  Additional (1): fi-skl-guc 
  Missing(2): fi-ctg-p8600 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110135v1:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}:   [WARN][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-2/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110135v1/bat-rpls-2/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@hangcheck:
- {bat-dg2-9}:[PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-dg2-9/igt@i915_selftest@l...@hangcheck.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110135v1/bat-dg2-9/igt@i915_selftest@l...@hangcheck.html

  
Known issues


  Here are the changes found in Patchwork_110135v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-skl-guc: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110135v1/fi-skl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110135v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][7] -> [DMESG-FAIL][8] ([i915#5334])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110135v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110135v1/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110135v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-icl-u2:  NOTRUN -> [SKIP][11] ([fdo#111827])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110135v1/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-guc: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110135v1/fi-skl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][13] ([fdo#109285])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110135v1/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-skl-guc: NOTRUN -> [SKIP][14] ([fdo#109271]) +10 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110135v1/fi-skl-guc/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][15] ([i915#3555])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110135v1/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-icl-u2:  NOTRUN -> [SKIP][16] ([fdo#109295] / [i915#3301])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110135v1/fi-icl-u2/igt@prime_v...@basic-userptr.html

  
 Possible fixes 

  * igt@fbdev@read:
- {bat-rpls-2}:   [SKIP][17] ([i915#2582]) -> [PASS][18] +4 similar 
issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-2/igt@fb...@read.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110135v1/bat-rpls-2/igt@fb...@read.html

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rpls-1}:   [DMESG-WARN][19] ([i915#6687]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
   [20]: 

[Intel-gfx] [PATCH v5 09/16] drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers

[Umesh Nerlige Ramappa]

User passes uabi engine class and instance to the perf OA interface. Use
gt corresponding to the engine to pin the buffers to the right ggtt.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_perf.c | 21 +++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 9a00398ae25f..2c8727253f0d 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1754,6 +1754,7 @@ static void gen12_init_oa_buffer(struct i915_perf_stream 
*stream)
 static int alloc_oa_buffer(struct i915_perf_stream *stream)
 {
struct drm_i915_private *i915 = stream->perf->i915;
+   struct intel_gt *gt = stream->engine->gt;
struct drm_i915_gem_object *bo;
struct i915_vma *vma;
int ret;
@@ -1773,11 +1774,22 @@ static int alloc_oa_buffer(struct i915_perf_stream 
*stream)
i915_gem_object_set_cache_coherency(bo, I915_CACHE_LLC);
 
/* PreHSW required 512K alignment, HSW requires 16M */
-   vma = i915_gem_object_ggtt_pin(bo, NULL, 0, SZ_16M, 0);
+   vma = i915_vma_instance(bo, >ggtt->vm, NULL);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
goto err_unref;
}
+
+   /*
+* PreHSW required 512K alignment.
+* HSW and onwards, align to requested size of OA buffer.
+*/
+   ret = i915_vma_pin(vma, 0, SZ_16M, PIN_GLOBAL | PIN_HIGH);
+   if (ret) {
+   drm_err(>i915->drm, "Failed to pin OA buffer %d\n", ret);
+   goto err_unref;
+   }
+
stream->oa_buffer.vma = vma;
 
stream->oa_buffer.vaddr =
@@ -1827,6 +1839,7 @@ static u32 *save_restore_register(struct i915_perf_stream 
*stream, u32 *cs,
 static int alloc_noa_wait(struct i915_perf_stream *stream)
 {
struct drm_i915_private *i915 = stream->perf->i915;
+   struct intel_gt *gt = stream->engine->gt;
struct drm_i915_gem_object *bo;
struct i915_vma *vma;
const u64 delay_ticks = 0x -
@@ -1867,12 +1880,16 @@ static int alloc_noa_wait(struct i915_perf_stream 
*stream)
 * multiple OA config BOs will have a jump to this address and it
 * needs to be fixed during the lifetime of the i915/perf stream.
 */
-   vma = i915_gem_object_ggtt_pin_ww(bo, , NULL, 0, 0, PIN_HIGH);
+   vma = i915_vma_instance(bo, >ggtt->vm, NULL);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
goto out_ww;
}
 
+   ret = i915_vma_pin_ww(vma, , 0, 0, PIN_GLOBAL | PIN_HIGH);
+   if (ret)
+   goto out_ww;
+
batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
if (IS_ERR(batch)) {
ret = PTR_ERR(batch);
-- 
2.25.1

[Intel-gfx] [PATCH v5 01/16] drm/i915/perf: Fix OA filtering logic for GuC mode

[Umesh Nerlige Ramappa]

With GuC mode of submission, GuC is in control of defining the context
id field that is part of the OA reports. To filter reports, UMD and KMD
must know what sw context id was chosen by GuC. There is not interface
between KMD and GuC to determine this, so read the upper-dword of
EXECLIST_STATUS to filter/squash OA reports for the specific context.

v2: Explain guc id stealing w.r.t OA use case

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_lrc.h |   2 +
 drivers/gpu/drm/i915/i915_perf.c| 144 
 2 files changed, 127 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h 
b/drivers/gpu/drm/i915/gt/intel_lrc.h
index a390f0813c8b..7111bae759f3 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -110,6 +110,8 @@ enum {
 #define XEHP_SW_CTX_ID_WIDTH   16
 #define XEHP_SW_COUNTER_SHIFT  58
 #define XEHP_SW_COUNTER_WIDTH  6
+#define GEN12_GUC_SW_CTX_ID_SHIFT  39
+#define GEN12_GUC_SW_CTX_ID_WIDTH  16
 
 static inline void lrc_runtime_start(struct intel_context *ce)
 {
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 15816df916c7..255335868b6a 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1231,6 +1231,128 @@ static struct intel_context *oa_pin_context(struct 
i915_perf_stream *stream)
return stream->pinned_ctx;
 }
 
+static int
+__store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)
+{
+   u32 *cs, cmd;
+
+   cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
+   if (GRAPHICS_VER(rq->engine->i915) >= 8)
+   cmd++;
+
+   cs = intel_ring_begin(rq, 4);
+   if (IS_ERR(cs))
+   return PTR_ERR(cs);
+
+   *cs++ = cmd;
+   *cs++ = i915_mmio_reg_offset(reg);
+   *cs++ = ggtt_offset;
+   *cs++ = 0;
+
+   intel_ring_advance(rq, cs);
+
+   return 0;
+}
+
+static int
+__read_reg(struct intel_context *ce, i915_reg_t reg, u32 ggtt_offset)
+{
+   struct i915_request *rq;
+   int err;
+
+   rq = i915_request_create(ce);
+   if (IS_ERR(rq))
+   return PTR_ERR(rq);
+
+   i915_request_get(rq);
+
+   err = __store_reg_to_mem(rq, reg, ggtt_offset);
+
+   i915_request_add(rq);
+   if (!err && i915_request_wait(rq, 0, HZ / 2) < 0)
+   err = -ETIME;
+
+   i915_request_put(rq);
+
+   return err;
+}
+
+static int
+gen12_guc_sw_ctx_id(struct intel_context *ce, u32 *ctx_id)
+{
+   struct i915_vma *scratch;
+   u32 *val;
+   int err;
+
+   scratch = 
__vm_create_scratch_for_read_pinned(>engine->gt->ggtt->vm, 4);
+   if (IS_ERR(scratch))
+   return PTR_ERR(scratch);
+
+   err = i915_vma_sync(scratch);
+   if (err)
+   goto err_scratch;
+
+   err = __read_reg(ce, RING_EXECLIST_STATUS_HI(ce->engine->mmio_base),
+i915_ggtt_offset(scratch));
+   if (err)
+   goto err_scratch;
+
+   val = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);
+   if (IS_ERR(val)) {
+   err = PTR_ERR(val);
+   goto err_scratch;
+   }
+
+   *ctx_id = *val;
+   i915_gem_object_unpin_map(scratch->obj);
+
+err_scratch:
+   i915_vma_unpin_and_release(, 0);
+   return err;
+}
+
+/*
+ * For execlist mode of submission, pick an unused context id
+ * 0 - (NUM_CONTEXT_TAG -1) are used by other contexts
+ * XXX_MAX_CONTEXT_HW_ID is used by idle context
+ *
+ * For GuC mode of submission read context id from the upper dword of the
+ * EXECLIST_STATUS register. Note that we read this value only once and expect
+ * that the value stays fixed for the entire OA use case. There are cases where
+ * GuC KMD implementation may deregister a context to reuse it's context id, 
but
+ * we prevent that from happening to the OA context by pinning it.
+ */
+static int gen12_get_render_context_id(struct i915_perf_stream *stream)
+{
+   u32 ctx_id, mask;
+   int ret;
+
+   if (intel_engine_uses_guc(stream->engine)) {
+   ret = gen12_guc_sw_ctx_id(stream->pinned_ctx, _id);
+   if (ret)
+   return ret;
+
+   mask = ((1U << GEN12_GUC_SW_CTX_ID_WIDTH) - 1) <<
+   (GEN12_GUC_SW_CTX_ID_SHIFT - 32);
+   } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 50)) {
+   ctx_id = (XEHP_MAX_CONTEXT_HW_ID - 1) <<
+   (XEHP_SW_CTX_ID_SHIFT - 32);
+
+   mask = ((1U << XEHP_SW_CTX_ID_WIDTH) - 1) <<
+   (XEHP_SW_CTX_ID_SHIFT - 32);
+   } else {
+   ctx_id = (GEN12_MAX_CONTEXT_HW_ID - 1) <<
+(GEN11_SW_CTX_ID_SHIFT - 32);
+
+   mask = ((1U << GEN11_SW_CTX_ID_WIDTH) - 1) <<
+

[Intel-gfx] [PATCH v5 11/16] drm/i915/perf: Add Wa_1508761755:dg2

[Umesh Nerlige Ramappa]

Disable Clock gating in EU when gathering the events so that EU events
are not lost.

v2: Fix checkpatch issues
v3: User MCR helpers to write to MC reg

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h |  1 +
 drivers/gpu/drm/i915/i915_perf.c| 24 
 2 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 36d95b79022c..b101e31df61c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1164,6 +1164,7 @@
 #define   GEN12_DISABLE_EARLY_READ REG_BIT(14)
 #define   GEN12_ENABLE_LARGE_GRF_MODE  REG_BIT(12)
 #define   GEN12_PUSH_CONST_DEREF_HOLD_DIS  REG_BIT(8)
+#define   GEN12_DISABLE_DOP_GATING  REG_BIT(0)
 
 #define RT_CTRLMCR_REG(0xe530)
 #define   DIS_NULL_QUERY   REG_BIT(10)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 585079ae5f03..18619eb19769 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -204,6 +204,7 @@
 #include "gt/intel_gpu_commands.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_clock_utils.h"
+#include "gt/intel_gt_mcr.h"
 #include "gt/intel_gt_regs.h"
 #include "gt/intel_lrc.h"
 #include "gt/intel_lrc_reg.h"
@@ -2775,6 +2776,18 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
u32 sqcnt1;
int ret;
 
+   /*
+* Wa_1508761755:xehpsdv, dg2
+* EU NOA signals behave incorrectly if EU clock gating is enabled.
+* Disable thread stall DOP gating and EU DOP gating.
+*/
+   if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
+   intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
+  
_MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
+   intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
+  
_MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING));
+   }
+
intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG,
   /* Disable clk ratio reports, like previous Gens. */
   
_MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
@@ -2853,6 +2866,17 @@ static void gen12_disable_metric_set(struct 
i915_perf_stream *stream)
struct drm_i915_private *i915 = stream->perf->i915;
u32 sqcnt1;
 
+   /*
+* Wa_1508761755:xehpsdv, dg2
+* Enable thread stall DOP gating and EU DOP gating.
+*/
+   if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
+   intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
+  
_MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));
+   intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
+  
_MASKED_BIT_DISABLE(GEN12_DISABLE_DOP_GATING));
+   }
+
/* Reset all contexts' slices/subslices configurations. */
gen12_configure_all_contexts(stream, NULL, NULL);
 
-- 
2.25.1

[Intel-gfx] [PATCH v5 08/16] drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops

[Umesh Nerlige Ramappa]

With multi-gt, user can access multiple OA buffers concurrently. Use
stream->lock instead of gt->perf.lock to serialize file operations.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_perf.c   | 31 --
 drivers/gpu/drm/i915/i915_perf_types.h |  5 +
 2 files changed, 19 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 83c5dc043261..9a00398ae25f 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3231,6 +3231,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
stream->poll_check_timer.function = oa_poll_check_timer_cb;
init_waitqueue_head(>poll_wq);
spin_lock_init(>oa_buffer.ptr_lock);
+   mutex_init(>lock);
 
return 0;
 
@@ -3294,7 +3295,6 @@ static ssize_t i915_perf_read(struct file *file,
  loff_t *ppos)
 {
struct i915_perf_stream *stream = file->private_data;
-   struct intel_gt *gt = stream->engine->gt;
size_t offset = 0;
int ret;
 
@@ -3318,14 +3318,14 @@ static ssize_t i915_perf_read(struct file *file,
if (ret)
return ret;
 
-   mutex_lock(>perf.lock);
+   mutex_lock(>lock);
ret = stream->ops->read(stream, buf, count, );
-   mutex_unlock(>perf.lock);
+   mutex_unlock(>lock);
} while (!offset && !ret);
} else {
-   mutex_lock(>perf.lock);
+   mutex_lock(>lock);
ret = stream->ops->read(stream, buf, count, );
-   mutex_unlock(>perf.lock);
+   mutex_unlock(>lock);
}
 
/* We allow the poll checking to sometimes report false positive EPOLLIN
@@ -3372,9 +3372,6 @@ static enum hrtimer_restart oa_poll_check_timer_cb(struct 
hrtimer *hrtimer)
  * _perf_stream_ops->poll_wait to call poll_wait() with a wait queue that
  * will be woken for new stream data.
  *
- * Note: The >perf.lock mutex has been taken to serialize
- * with any non-file-operation driver hooks.
- *
  * Returns: any poll events that are ready without sleeping
  */
 static __poll_t i915_perf_poll_locked(struct i915_perf_stream *stream,
@@ -3413,12 +3410,11 @@ static __poll_t i915_perf_poll_locked(struct 
i915_perf_stream *stream,
 static __poll_t i915_perf_poll(struct file *file, poll_table *wait)
 {
struct i915_perf_stream *stream = file->private_data;
-   struct intel_gt *gt = stream->engine->gt;
__poll_t ret;
 
-   mutex_lock(>perf.lock);
+   mutex_lock(>lock);
ret = i915_perf_poll_locked(stream, file, wait);
-   mutex_unlock(>perf.lock);
+   mutex_unlock(>lock);
 
return ret;
 }
@@ -3517,9 +3513,6 @@ static long i915_perf_config_locked(struct 
i915_perf_stream *stream,
  * @cmd: the ioctl request
  * @arg: the ioctl data
  *
- * Note: The >perf.lock mutex has been taken to serialize
- * with any non-file-operation driver hooks.
- *
  * Returns: zero on success or a negative error code. Returns -EINVAL for
  * an unknown ioctl request.
  */
@@ -3557,12 +3550,11 @@ static long i915_perf_ioctl(struct file *file,
unsigned long arg)
 {
struct i915_perf_stream *stream = file->private_data;
-   struct intel_gt *gt = stream->engine->gt;
long ret;
 
-   mutex_lock(>perf.lock);
+   mutex_lock(>lock);
ret = i915_perf_ioctl_locked(stream, cmd, arg);
-   mutex_unlock(>perf.lock);
+   mutex_unlock(>lock);
 
return ret;
 }
@@ -3608,6 +3600,11 @@ static int i915_perf_release(struct inode *inode, struct 
file *file)
struct i915_perf *perf = stream->perf;
struct intel_gt *gt = stream->engine->gt;
 
+   /*
+* Within this call, we know that the fd is being closed and we have no
+* other user of stream->lock. Use the perf lock to destroy the stream
+* here.
+*/
mutex_lock(>perf.lock);
i915_perf_destroy_locked(stream);
mutex_unlock(>perf.lock);
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h 
b/drivers/gpu/drm/i915/i915_perf_types.h
index e888bfab478f..dc9bfd8086cf 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -146,6 +146,11 @@ struct i915_perf_stream {
 */
struct intel_engine_cs *engine;
 
+   /*
+* Lock associated with operations on stream
+*/
+   struct mutex lock;
+
/**
 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
 * properties given when opening a stream, representing the contents
-- 
2.25.1

[Intel-gfx] [PATCH v5 15/16] drm/i915/perf: complete programming whitelisting for XEHPSDV

[Umesh Nerlige Ramappa]

From: Lionel Landwerlin 

We have an additional register to select which slices contribute to
OAG/OAG counter increments.

Signed-off-by: Lionel Landwerlin 
Signed-off-by: Matt Roper 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_drv.h  |  2 ++
 drivers/gpu/drm/i915/i915_pci.c  |  1 +
 drivers/gpu/drm/i915/i915_perf.c | 13 +
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 4 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 438aebeea103..3bbcd726c2da 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -900,6 +900,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_OA_BPC_REPORTING(dev_priv) \
(INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
+#define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
+   (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
 
 /*
  * Set this flag, when platform requires 64K GTT page sizes or larger for
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index cbced3f3db17..3f505ee15d66 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1024,6 +1024,7 @@ static const struct intel_device_info adl_p_info = {
.has_logical_ring_elsq = 1, \
.has_mslice_steering = 1, \
.has_oa_bpc_reporting = 1, \
+   .has_oa_slice_contrib_limits = 1, \
.has_rc6 = 1, \
.has_reset_engine = 1, \
.has_rps = 1, \
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index bc0c486cf7d4..176442d5e57e 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4261,6 +4261,11 @@ static const struct i915_range gen12_oa_b_counters[] = {
{}
 };
 
+static const struct i915_range xehp_oa_b_counters[] = {
+   { .start = 0xdc48, .end = 0xdc48 }, /* OAA_ENABLE_REG */
+   { .start = 0xdd00, .end = 0xdd48 }, /* OAG_LCE0_0 - OAA_LENABLE_REG 
*/
+};
+
 static const struct i915_range gen7_oa_mux_regs[] = {
{ .start = 0x91b8, .end = 0x91cc }, /* OA_PERFCNT[1-2], 
OA_PERFMATRIX */
{ .start = 0x9800, .end = 0x9888 }, /* MICRO_BP0_0 - NOA_WRITE */
@@ -4335,6 +4340,12 @@ static bool gen12_is_valid_b_counter_addr(struct 
i915_perf *perf, u32 addr)
return reg_in_range_table(addr, gen12_oa_b_counters);
 }
 
+static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
+{
+   return reg_in_range_table(addr, xehp_oa_b_counters) ||
+   reg_in_range_table(addr, gen12_oa_b_counters);
+}
+
 static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
 {
return reg_in_range_table(addr, gen12_oa_mux_regs);
@@ -4847,6 +4858,8 @@ void i915_perf_init(struct drm_i915_private *i915)
perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
} else if (GRAPHICS_VER(i915) == 12) {
perf->ops.is_valid_b_counter_reg =
+   HAS_OA_SLICE_CONTRIB_LIMITS(i915) ?
+   xehp_is_valid_b_counter_addr :
gen12_is_valid_b_counter_addr;
perf->ops.is_valid_mux_reg =
gen12_is_valid_mux_addr;
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 42218c8d85f2..e292c1ee7c93 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -165,6 +165,7 @@ enum intel_ppgtt_type {
func(has_media_ratio_mode); \
func(has_mslice_steering); \
func(has_oa_bpc_reporting); \
+   func(has_oa_slice_contrib_limits); \
func(has_one_eu_per_fuse_bit); \
func(has_pxp); \
func(has_rc6); \
-- 
2.25.1

[Intel-gfx] [PATCH v5 14/16] drm/i915/guc: Support OA when Wa_16011777198 is enabled

[Umesh Nerlige Ramappa]

From: Vinay Belgaumkar 

On DG2, a w/a resets RCS/CCS before it goes into RC6. This breaks OA
since OA does not expect engine resets during its use. Fix it by
disabling RC6.

v2: (Ashutosh)
- Bring back slpc_unset_param helper
- Update commit msg
- Use with_intel_runtime_pm helper for set/unset

v3: (Ashutosh)
- Just use intel_uc_uses_guc_rc

Signed-off-by: Vinay Belgaumkar 
Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h |  9 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   | 66 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h   |  2 +
 drivers/gpu/drm/i915/i915_perf.c  | 27 
 4 files changed, 104 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
index 4c840a2639dc..811add10c30d 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
@@ -128,6 +128,15 @@ enum slpc_media_ratio_mode {
SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO = 2,
 };
 
+enum slpc_gucrc_mode {
+   SLPC_GUCRC_MODE_HW = 0,
+   SLPC_GUCRC_MODE_GUCRC_NO_RC6 = 1,
+   SLPC_GUCRC_MODE_GUCRC_STATIC_TIMEOUT = 2,
+   SLPC_GUCRC_MODE_GUCRC_DYNAMIC_HYSTERESIS = 3,
+
+   SLPC_GUCRC_MODE_MAX,
+};
+
 enum slpc_event_id {
SLPC_EVENT_RESET = 0,
SLPC_EVENT_SHUTDOWN = 1,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index fdd895f73f9f..b3a4fb9e021f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -137,6 +137,17 @@ static int guc_action_slpc_set_param(struct intel_guc 
*guc, u8 id, u32 value)
return ret > 0 ? -EPROTO : ret;
 }
 
+static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)
+{
+   u32 request[] = {
+   GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
+   SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1),
+   id,
+   };
+
+   return intel_guc_send(guc, request, ARRAY_SIZE(request));
+}
+
 static bool slpc_is_running(struct intel_guc_slpc *slpc)
 {
return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
@@ -190,6 +201,15 @@ static int slpc_set_param(struct intel_guc_slpc *slpc, u8 
id, u32 value)
return ret;
 }
 
+static int slpc_unset_param(struct intel_guc_slpc *slpc, u8 id)
+{
+   struct intel_guc *guc = slpc_to_guc(slpc);
+
+   GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+
+   return guc_action_slpc_unset_param(guc, id);
+}
+
 static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
 {
struct drm_i915_private *i915 = slpc_to_i915(slpc);
@@ -610,6 +630,52 @@ static void slpc_get_rp_values(struct intel_guc_slpc *slpc)
slpc->boost_freq = slpc->rp0_freq;
 }
 
+/**
+ * intel_guc_slpc_override_gucrc_mode() - override GUCRC mode
+ * @slpc: pointer to intel_guc_slpc.
+ * @mode: new value of the mode.
+ *
+ * This function will override the GUCRC mode.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode)
+{
+   int ret;
+   struct drm_i915_private *i915 = slpc_to_i915(slpc);
+   intel_wakeref_t wakeref;
+
+   if (mode >= SLPC_GUCRC_MODE_MAX)
+   return -EINVAL;
+
+   with_intel_runtime_pm(>runtime_pm, wakeref) {
+   ret = slpc_set_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE, mode);
+   if (ret)
+   drm_err(>drm,
+   "Override gucrc mode %d failed %d\n",
+   mode, ret);
+   }
+
+   return ret;
+}
+
+int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc)
+{
+   struct drm_i915_private *i915 = slpc_to_i915(slpc);
+   intel_wakeref_t wakeref;
+   int ret = 0;
+
+   with_intel_runtime_pm(>runtime_pm, wakeref) {
+   ret = slpc_unset_param(slpc, SLPC_PARAM_PWRGATE_RC_MODE);
+   if (ret)
+   drm_err(>drm,
+   "Unsetting gucrc mode failed %d\n",
+   ret);
+   }
+
+   return ret;
+}
+
 /*
  * intel_guc_slpc_enable() - Start SLPC
  * @slpc: pointer to intel_guc_slpc.
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index 82a98f78f96c..ccf483730d9d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -42,5 +42,7 @@ int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc 
*slpc, u32 val);
 void intel_guc_pm_intrmsk_enable(struct intel_gt *gt);
 void intel_guc_slpc_boost(struct intel_guc_slpc *slpc);
 void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc);
+int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc);
+int intel_guc_slpc_override_gucrc_mode(struct 

[Intel-gfx] [PATCH v5 16/16] drm/i915/perf: Enable OA for DG2

[Umesh Nerlige Ramappa]

OA was disabled for DG2 as support was missing. Enable it back now.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_perf.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 176442d5e57e..3438cff13f38 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4798,12 +4798,6 @@ void i915_perf_init(struct drm_i915_private *i915)
 {
struct i915_perf *perf = >perf;
 
-   /* XXX const struct i915_perf_ops! */
-
-   /* i915_perf is not enabled for DG2 yet */
-   if (IS_DG2(i915))
-   return;
-
perf->oa_formats = oa_formats;
if (IS_HASWELL(i915)) {
perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr;
-- 
2.25.1

[Intel-gfx] [PATCH v5 05/16] drm/i915/perf: Enable bytes per clock reporting in OA

[Umesh Nerlige Ramappa]

XEHPSDV and DG2 provide a way to configure bytes per clock vs commands
per clock reporting. Enable bytes per clock setting on enabling OA.

Bspec: 51762
Bspec: 52201

v2:
- Fix commit msg (Ashutosh)
- Fix checkpatch issues

v3:
- s/commands/bytes/ in code comment and commmit msg

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_drv.h  |  3 +++
 drivers/gpu/drm/i915/i915_pci.c  |  1 +
 drivers/gpu/drm/i915/i915_perf.c | 20 
 drivers/gpu/drm/i915/i915_perf_oa_regs.h |  4 
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 5 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7c64f8a17493..438aebeea103 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -898,6 +898,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
 
+#define HAS_OA_BPC_REPORTING(dev_priv) \
+   (INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
+
 /*
  * Set this flag, when platform requires 64K GTT page sizes or larger for
  * device local memory access.
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 496df0f547f4..cbced3f3db17 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1023,6 +1023,7 @@ static const struct intel_device_info adl_p_info = {
.has_logical_ring_contexts = 1, \
.has_logical_ring_elsq = 1, \
.has_mslice_steering = 1, \
+   .has_oa_bpc_reporting = 1, \
.has_rc6 = 1, \
.has_reset_engine = 1, \
.has_rps = 1, \
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index b71b5cf21176..d11cc949c9be 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2748,10 +2748,12 @@ static int
 gen12_enable_metric_set(struct i915_perf_stream *stream,
struct i915_active *active)
 {
+   struct drm_i915_private *i915 = stream->perf->i915;
struct intel_uncore *uncore = stream->uncore;
struct i915_oa_config *oa_config = stream->oa_config;
bool periodic = stream->periodic;
u32 period_exponent = stream->period_exponent;
+   u32 sqcnt1;
int ret;
 
intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG,
@@ -2770,6 +2772,16 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
(period_exponent << 
GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT))
: 0);
 
+   /*
+* Initialize Super Queue Internal Cnt Register
+* Set PMON Enable in order to collect valid metrics.
+* Enable byets per clock reporting in OA for XEHPSDV onward.
+*/
+   sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
+(HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
+
+   intel_uncore_rmw(uncore, GEN12_SQCNT1, 0, sqcnt1);
+
/*
 * Update all contexts prior writing the mux configurations as we need
 * to make sure all slices/subslices are ON before writing to NOA
@@ -2819,6 +2831,8 @@ static void gen11_disable_metric_set(struct 
i915_perf_stream *stream)
 static void gen12_disable_metric_set(struct i915_perf_stream *stream)
 {
struct intel_uncore *uncore = stream->uncore;
+   struct drm_i915_private *i915 = stream->perf->i915;
+   u32 sqcnt1;
 
/* Reset all contexts' slices/subslices configurations. */
gen12_configure_all_contexts(stream, NULL, NULL);
@@ -2829,6 +2843,12 @@ static void gen12_disable_metric_set(struct 
i915_perf_stream *stream)
 
/* Make sure we disable noa to save power. */
intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
+
+   sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
+(HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
+
+   /* Reset PMON Enable to save power. */
+   intel_uncore_rmw(uncore, GEN12_SQCNT1, sqcnt1, 0);
 }
 
 static void gen7_oa_enable(struct i915_perf_stream *stream)
diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h 
b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
index 0ef3562ff4aa..381d94101610 100644
--- a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
+++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
@@ -134,4 +134,8 @@
 #define GDT_CHICKEN_BITS_MMIO(0x9840)
 #define   GT_NOA_ENABLE0x0080
 
+#define GEN12_SQCNT1   _MMIO(0x8718)
+#define   GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
+#define   GEN12_SQCNT1_OABPC   REG_BIT(29)
+
 #endif /* __INTEL_PERF_OA_REGS__ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index cdf78728dcad..42218c8d85f2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ 

[Intel-gfx] [PATCH v5 06/16] drm/i915/perf: Simply use stream->ctx

[Umesh Nerlige Ramappa]

Earlier code used exclusive_stream to check for user passed context.
Simplify this by accessing stream->ctx.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Lionel Landwerlin 
---
 drivers/gpu/drm/i915/i915_perf.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index d11cc949c9be..75d320b2c1f8 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -776,7 +776,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream 
*stream,
 * switches since it's not-uncommon for periodic samples to
 * identify a switch before any 'context switch' report.
 */
-   if (!stream->perf->exclusive_stream->ctx ||
+   if (!stream->ctx ||
stream->specific_ctx_id == ctx_id ||
stream->oa_buffer.last_ctx_id == stream->specific_ctx_id ||
reason & OAREPORT_REASON_CTX_SWITCH) {
@@ -785,7 +785,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream 
*stream,
 * While filtering for a single context we avoid
 * leaking the IDs of other contexts.
 */
-   if (stream->perf->exclusive_stream->ctx &&
+   if (stream->ctx &&
stream->specific_ctx_id != ctx_id) {
report32[2] = INVALID_CTX_ID;
}
-- 
2.25.1

[Intel-gfx] [PATCH v5 04/16] drm/i915/perf: Determine gen12 oa ctx offset at runtime

[Umesh Nerlige Ramappa]

Some SKUs of same gen12 platform may have different oactxctrl
offsets. For gen12, determine oactxctrl offsets at runtime.

v2: (Lionel)
- Move MI definitions to intel_gpu_commands.h
- Ensure __find_reg_in_lri does read past context image size

v3: (Ashutosh)
- Drop unnecessary use of double underscores
- fix find_reg_in_lri
- Return error if oa context offset is U32_MAX
- Error out if oa_ctx_ctrl_offset does not find offset

v4: (Ashutosh)
- Warn on odd MI LRI_LEN
- Remove unnecessary check for valid_oactxctrl_offset
- Drop valid_oactxctrl_offset macro

v5: Drop unrelated comment

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h |   4 +
 drivers/gpu/drm/i915/i915_perf.c | 146 ---
 drivers/gpu/drm/i915/i915_perf_oa_regs.h |   2 +-
 3 files changed, 127 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h 
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index d4e9702d3c8e..f50ea92910d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -187,6 +187,10 @@
 #define   MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
 #define   MI_BATCH_PREDICATE REG_BIT(15) /* HSW+ on RCS only*/
 
+#define MI_OPCODE(x)   (((x) >> 23) & 0x3f)
+#define IS_MI_LRI_CMD(x)   (MI_OPCODE(x) == MI_OPCODE(MI_INSTR(0x22, 0)))
+#define MI_LRI_LEN(x)  (((x) & 0xff) + 1)
+
 /*
  * 3D instructions used by the kernel
  */
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e68666b44a72..b71b5cf21176 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1356,6 +1356,74 @@ static int gen12_get_render_context_id(struct 
i915_perf_stream *stream)
return 0;
 }
 
+static bool oa_find_reg_in_lri(u32 *state, u32 reg, u32 *offset, u32 end)
+{
+   u32 idx = *offset;
+   u32 len = min(MI_LRI_LEN(state[idx]) + idx, end);
+   bool found = false;
+
+   idx++;
+   for (; idx < len; idx += 2) {
+   if (state[idx] == reg) {
+   found = true;
+   break;
+   }
+   }
+
+   *offset = idx;
+   return found;
+}
+
+static u32 oa_context_image_offset(struct intel_context *ce, u32 reg)
+{
+   u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
+   u32 *state = ce->lrc_reg_state;
+
+   for (offset = 0; offset < len; ) {
+   if (IS_MI_LRI_CMD(state[offset])) {
+   /*
+* We expect reg-value pairs in MI_LRI command, so
+* MI_LRI_LEN() should be even, if not, issue a warning.
+*/
+   drm_WARN_ON(>engine->i915->drm,
+   MI_LRI_LEN(state[offset]) & 0x1);
+
+   if (oa_find_reg_in_lri(state, reg, , len))
+   break;
+   } else {
+   offset++;
+   }
+   }
+
+   return offset < len ? offset : U32_MAX;
+}
+
+static int set_oa_ctx_ctrl_offset(struct intel_context *ce)
+{
+   i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);
+   struct i915_perf *perf = >engine->i915->perf;
+   u32 offset = perf->ctx_oactxctrl_offset;
+
+   /* Do this only once. Failure is stored as offset of U32_MAX */
+   if (offset)
+   goto exit;
+
+   offset = oa_context_image_offset(ce, i915_mmio_reg_offset(reg));
+   perf->ctx_oactxctrl_offset = offset;
+
+   drm_dbg(>engine->i915->drm,
+   "%s oa ctx control at 0x%08x dword offset\n",
+   ce->engine->name, offset);
+
+exit:
+   return offset && offset != U32_MAX ? 0 : -ENODEV;
+}
+
+static bool engine_supports_mi_query(struct intel_engine_cs *engine)
+{
+   return engine->class == RENDER_CLASS;
+}
+
 /**
  * oa_get_render_ctx_id - determine and hold ctx hw id
  * @stream: An i915-perf stream opened for OA metrics
@@ -1375,6 +1443,21 @@ static int oa_get_render_ctx_id(struct i915_perf_stream 
*stream)
if (IS_ERR(ce))
return PTR_ERR(ce);
 
+   if (engine_supports_mi_query(stream->engine)) {
+   /*
+* We are enabling perf query here. If we don't find the context
+* offset here, just return an error.
+*/
+   ret = set_oa_ctx_ctrl_offset(ce);
+   if (ret) {
+   intel_context_unpin(ce);
+   drm_err(>perf->i915->drm,
+   "Enabling perf query failed for %s\n",
+   stream->engine->name);
+   return ret;
+   }
+   }
+
switch (GRAPHICS_VER(ce->engine->i915)) {
case 7: {
/*
@@ -2406,10 +2489,11 @@ static int gen12_configure_oar_context(struct 
i915_perf_stream 

[Intel-gfx] [PATCH v5 07/16] drm/i915/perf: Move gt-specific data from i915->perf to gt->perf

[Umesh Nerlige Ramappa]

Make perf part of gt as the OAG buffer is specific to a gt. The refactor
eventually simplifies programming the right OA buffer and the right HW
registers when supporting multiple gts.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Lionel Landwerlin 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_gt_types.h   |  3 +
 drivers/gpu/drm/i915/gt/intel_sseu.c   |  4 +-
 drivers/gpu/drm/i915/i915_perf.c   | 75 +-
 drivers/gpu/drm/i915/i915_perf_types.h | 39 +--
 drivers/gpu/drm/i915/selftests/i915_perf.c | 16 +++--
 5 files changed, 80 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 64aa2ba624fc..6f686a4244f0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -20,6 +20,7 @@
 #include "intel_gsc.h"
 
 #include "i915_vma.h"
+#include "i915_perf_types.h"
 #include "intel_engine_types.h"
 #include "intel_gt_buffer_pool_types.h"
 #include "intel_hwconfig.h"
@@ -289,6 +290,8 @@ struct intel_gt {
/* sysfs defaults per gt */
struct gt_defaults defaults;
struct kobject *sysfs_defaults;
+
+   struct i915_perf_gt perf;
 };
 
 struct intel_gt_definition {
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c 
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 66f21c735d54..6c6198a257ac 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -677,8 +677,8 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
 * If i915/perf is active, we want a stable powergating configuration
 * on the system. Use the configuration pinned by i915/perf.
 */
-   if (i915->perf.exclusive_stream)
-   req_sseu = >perf.sseu;
+   if (gt->perf.exclusive_stream)
+   req_sseu = >perf.sseu;
 
slices = hweight8(req_sseu->slice_mask);
subslices = hweight8(req_sseu->subslice_mask);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 75d320b2c1f8..83c5dc043261 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1565,8 +1565,9 @@ free_noa_wait(struct i915_perf_stream *stream)
 static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
 {
struct i915_perf *perf = stream->perf;
+   struct intel_gt *gt = stream->engine->gt;
 
-   if (WARN_ON(stream != perf->exclusive_stream))
+   if (WARN_ON(stream != gt->perf.exclusive_stream))
return;
 
/*
@@ -1575,7 +1576,7 @@ static void i915_oa_stream_destroy(struct 
i915_perf_stream *stream)
 *
 * See i915_oa_init_reg_state() and lrc_configure_all_contexts()
 */
-   WRITE_ONCE(perf->exclusive_stream, NULL);
+   WRITE_ONCE(gt->perf.exclusive_stream, NULL);
perf->ops.disable_metric_set(stream);
 
free_oa_buffer(stream);
@@ -2566,10 +2567,11 @@ oa_configure_all_contexts(struct i915_perf_stream 
*stream,
 {
struct drm_i915_private *i915 = stream->perf->i915;
struct intel_engine_cs *engine;
+   struct intel_gt *gt = stream->engine->gt;
struct i915_gem_context *ctx, *cn;
int err;
 
-   lockdep_assert_held(>perf->lock);
+   lockdep_assert_held(>perf.lock);
 
/*
 * The OA register config is setup through the context image. This image
@@ -3090,6 +3092,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
 {
struct drm_i915_private *i915 = stream->perf->i915;
struct i915_perf *perf = stream->perf;
+   struct intel_gt *gt;
int format_size;
int ret;
 
@@ -3098,6 +3101,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
"OA engine not specified\n");
return -EINVAL;
}
+   gt = props->engine->gt;
 
/*
 * If the sysfs metrics/ directory wasn't registered for some
@@ -3128,7 +3132,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
 * counter reports and marshal to the appropriate client
 * we currently only allow exclusive access
 */
-   if (perf->exclusive_stream) {
+   if (gt->perf.exclusive_stream) {
drm_dbg(>perf->i915->drm,
"OA unit already in use\n");
return -EBUSY;
@@ -3208,8 +3212,8 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
 
stream->ops = _oa_stream_ops;
 
-   perf->sseu = props->sseu;
-   WRITE_ONCE(perf->exclusive_stream, stream);
+   stream->engine->gt->perf.sseu = props->sseu;
+   WRITE_ONCE(gt->perf.exclusive_stream, stream);
 
ret = i915_perf_stream_enable_sync(stream);
if (ret) {
@@ -3231,7 +3235,7 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
return 0;
 
 err_enable:
-   WRITE_ONCE(perf->exclusive_stream, NULL);
+   

[Intel-gfx] [PATCH v5 10/16] drm/i915/perf: Store a pointer to oa_format in oa_buffer

[Umesh Nerlige Ramappa]

DG2 introduces OA reports with 64 bit report header fields. Perf OA
would need more information about the OA format in order to process such
reports. Store all OA format info in oa_buffer instead of just the size
and format-id.

v2: Drop format_size variable (Ashutosh)

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Lionel Landwerlin 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_perf.c   | 30 +++---
 drivers/gpu/drm/i915/i915_perf_types.h |  3 +--
 2 files changed, 13 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2c8727253f0d..585079ae5f03 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -465,7 +465,7 @@ static u32 gen7_oa_hw_tail_read(struct i915_perf_stream 
*stream)
 static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
 {
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
-   int report_size = stream->oa_buffer.format_size;
+   int report_size = stream->oa_buffer.format->size;
unsigned long flags;
bool pollin;
u32 hw_tail;
@@ -602,7 +602,7 @@ static int append_oa_sample(struct i915_perf_stream *stream,
size_t *offset,
const u8 *report)
 {
-   int report_size = stream->oa_buffer.format_size;
+   int report_size = stream->oa_buffer.format->size;
struct drm_i915_perf_record_header header;
 
header.type = DRM_I915_PERF_RECORD_SAMPLE;
@@ -652,7 +652,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream 
*stream,
  size_t *offset)
 {
struct intel_uncore *uncore = stream->uncore;
-   int report_size = stream->oa_buffer.format_size;
+   int report_size = stream->oa_buffer.format->size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
u32 mask = (OA_BUFFER_SIZE - 1);
@@ -945,7 +945,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream 
*stream,
  size_t *offset)
 {
struct intel_uncore *uncore = stream->uncore;
-   int report_size = stream->oa_buffer.format_size;
+   int report_size = stream->oa_buffer.format->size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
u32 mask = (OA_BUFFER_SIZE - 1);
@@ -2506,7 +2506,7 @@ static int gen12_configure_oar_context(struct 
i915_perf_stream *stream,
 {
int err;
struct intel_context *ce = stream->pinned_ctx;
-   u32 format = stream->oa_buffer.format;
+   u32 format = stream->oa_buffer.format->format;
u32 offset = stream->perf->ctx_oactxctrl_offset;
struct flex regs_context[] = {
{
@@ -2877,7 +2877,7 @@ static void gen7_oa_enable(struct i915_perf_stream 
*stream)
u32 ctx_id = stream->specific_ctx_id;
bool periodic = stream->periodic;
u32 period_exponent = stream->period_exponent;
-   u32 report_format = stream->oa_buffer.format;
+   u32 report_format = stream->oa_buffer.format->format;
 
/*
 * Reset buf pointers so we don't forward reports from before now.
@@ -2903,7 +2903,7 @@ static void gen7_oa_enable(struct i915_perf_stream 
*stream)
 static void gen8_oa_enable(struct i915_perf_stream *stream)
 {
struct intel_uncore *uncore = stream->uncore;
-   u32 report_format = stream->oa_buffer.format;
+   u32 report_format = stream->oa_buffer.format->format;
 
/*
 * Reset buf pointers so we don't forward reports from before now.
@@ -2929,7 +2929,7 @@ static void gen8_oa_enable(struct i915_perf_stream 
*stream)
 static void gen12_oa_enable(struct i915_perf_stream *stream)
 {
struct intel_uncore *uncore = stream->uncore;
-   u32 report_format = stream->oa_buffer.format;
+   u32 report_format = stream->oa_buffer.format->format;
 
/*
 * If we don't want OA reports from the OA buffer, then we don't even
@@ -3110,7 +3110,6 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
struct drm_i915_private *i915 = stream->perf->i915;
struct i915_perf *perf = stream->perf;
struct intel_gt *gt;
-   int format_size;
int ret;
 
if (!props->engine) {
@@ -3166,20 +3165,15 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
 
stream->sample_size = sizeof(struct drm_i915_perf_record_header);
 
-   format_size = perf->oa_formats[props->oa_format].size;
+   stream->oa_buffer.format = >oa_formats[props->oa_format];
+   if (drm_WARN_ON(>drm, stream->oa_buffer.format->size == 0))
+   return -EINVAL;
 
stream->sample_flags = props->sample_flags;
-   stream->sample_size += format_size;
-
-   stream->oa_buffer.format_size = format_size;
-   if (drm_WARN_ON(>drm, 

[Intel-gfx] [PATCH v5 13/16] drm/i915/perf: Save/restore EU flex counters across reset

[Umesh Nerlige Ramappa]

If a drm client is killed, then hw contexts used by the client are reset
immediately. This reset clears the EU flex counter configuration. If an
OA use case is running in parallel, it would start seeing zeroed eu
counter values following the reset even if the drm client is restarted.
Save/restore the EU flex counter config so that the EU counters can be
monitored continuously across resets.

v2:
- Save/restore eu flex config only for gen12, as for pre-gen12, these
  are saved and restored in the context image.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 34ef4f36e660..a419d60166c8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -392,6 +392,16 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
else
ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), 
false);
 
+   if (GRAPHICS_VER(engine->i915) >= 12) {
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL0, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL1, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL2, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL3, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL4, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL5, false);
+   ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL6, false);
+   }
+
return ret ? -1 : 0;
 }
 
-- 
2.25.1

[Intel-gfx] [PATCH v5 12/16] drm/i915/perf: Apply Wa_18013179988

[Umesh Nerlige Ramappa]

OA reports in the OA buffer contain an OA timestamp field that helps
user calculate delta between 2 OA reports. The calculation relies on the
CS timestamp frequency to convert the timestamp value to nanoseconds.
The CS timestamp frequency is a function of the CTC_SHIFT value in
RPM_CONFIG0.

In DG2, OA unit assumes that the CTC_SHIFT is 3, instead of using the
actual value from RPM_CONFIG0. At the user level, this results in an
error in calculating delta between 2 OA reports since the OA timestamp
is not shifted in the same manner as CS timestamp. Also the periodicity
of the reports is different from what the user configured because of
mismatch in the CS and OA frequencies.

The issue also affects MI_REPORT_PERF_COUNT command.

To resolve this, return actual OA timestamp frequency to the user in
i915_getparam_ioctl, so that user can calculate the right OA exponent as
well as interpret the reports correctly.

MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893

v2:
- Use REG_FIELD_GET (Ashutosh)
- Update commit msg

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_getparam.c |  3 +++
 drivers/gpu/drm/i915/i915_perf.c | 30 ++--
 drivers/gpu/drm/i915/i915_perf.h |  2 ++
 include/uapi/drm/i915_drm.h  |  6 ++
 4 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_getparam.c 
b/drivers/gpu/drm/i915/i915_getparam.c
index 342c8ca6414e..3047e80e1163 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -175,6 +175,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_PERF_REVISION:
value = i915_perf_ioctl_version();
break;
+   case I915_PARAM_OA_TIMESTAMP_FREQUENCY:
+   value = i915_perf_oa_timestamp_frequency(i915);
+   break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 18619eb19769..8540eb6156e4 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3109,6 +3109,30 @@ get_sseu_config(struct intel_sseu *out_sseu,
return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu);
 }
 
+/*
+ * OA timestamp frequency = CS timestamp frequency in most platforms. On some
+ * platforms OA unit ignores the CTC_SHIFT and the 2 timestamps differ. In such
+ * cases, return the adjusted CS timestamp frequency to the user.
+ */
+u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
+{
+   /* Wa_18013179988:dg2 */
+   if (IS_DG2(i915)) {
+   intel_wakeref_t wakeref;
+   u32 reg, shift;
+
+   with_intel_runtime_pm(to_gt(i915)->uncore->rpm, wakeref)
+   reg = intel_uncore_read(to_gt(i915)->uncore, 
RPM_CONFIG0);
+
+   shift = 
REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK,
+ reg);
+
+   return to_gt(i915)->clock_frequency << (3 - shift);
+   }
+
+   return to_gt(i915)->clock_frequency;
+}
+
 /**
  * i915_oa_stream_init - validate combined props for OA stream and init
  * @stream: An i915 perf stream
@@ -3830,8 +3854,10 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
 
 static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
 {
-   return intel_gt_clock_interval_to_ns(to_gt(perf->i915),
-2ULL << exponent);
+   u64 nom = (2ULL << exponent) * NSEC_PER_SEC;
+   u32 den = i915_perf_oa_timestamp_frequency(perf->i915);
+
+   return div_u64(nom + den - 1, den);
 }
 
 static __always_inline bool
diff --git a/drivers/gpu/drm/i915/i915_perf.h b/drivers/gpu/drm/i915/i915_perf.h
index 1d1329e5af3a..f96e09a4af04 100644
--- a/drivers/gpu/drm/i915/i915_perf.h
+++ b/drivers/gpu/drm/i915/i915_perf.h
@@ -57,4 +57,6 @@ static inline void i915_oa_config_put(struct i915_oa_config 
*oa_config)
kref_put(_config->ref, i915_oa_config_release);
 }
 
+u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915);
+
 #endif /* __I915_PERF_H__ */
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 158b35fb28f3..c346b1923d11 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -765,6 +765,12 @@ typedef struct drm_i915_irq_wait {
 /* Query if the kernel supports the I915_USERPTR_PROBE flag. */
 #define I915_PARAM_HAS_USERPTR_PROBE 56
 
+/*
+ * Frequency of the timestamps in OA reports. This used to be the same as the 
CS
+ * timestamp frequency, but differs on some platforms.
+ */
+#define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57
+
 /* Must be kept compact -- no holes and well documented */
 
 /**
-- 
2.25.1

[Intel-gfx] [PATCH v5 03/16] drm/i915/perf: Fix noa wait predication for DG2

[Umesh Nerlige Ramappa]

Predication for batch buffer commands changed in XEHPSDV.
MI_BATCH_BUFFER_START predicates based on MI_SET_PREDICATE_RESULT
register. The MI_SET_PREDICATE_RESULT register can only be modified
with MI_SET_PREDICATE command. When configured, the MI_SET_PREDICATE
command sets MI_SET_PREDICATE_RESULT based on bit 0 of
MI_PREDICATE_RESULT_2. Use this to configure predication in noa_wait.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_engine_regs.h |  1 +
 drivers/gpu/drm/i915/i915_perf.c| 24 +
 2 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h 
b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index fe1a0d5fd4b1..ee3efd06ee54 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -201,6 +201,7 @@
 #define RING_CONTEXT_STATUS_PTR(base)  _MMIO((base) + 0x3a0)
 #define RING_CTX_TIMESTAMP(base)   _MMIO((base) + 0x3a8) /* gen8+ 
*/
 #define RING_PREDICATE_RESULT(base)_MMIO((base) + 0x3b8)
+#define MI_PREDICATE_RESULT_2_ENGINE(base) _MMIO((base) + 0x3bc)
 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 
4)
 #define   RING_FORCE_TO_NONPRIV_DENY   REG_BIT(30)
 #define   RING_FORCE_TO_NONPRIV_ADDRESS_MASK   REG_GENMASK(25, 2)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2b772a6b1cd6..e68666b44a72 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -286,6 +286,7 @@ static u32 i915_perf_stream_paranoid = true;
 #define OAREPORT_REASON_CTX_SWITCH (1<<3)
 #define OAREPORT_REASON_CLK_RATIO  (1<<5)
 
+#define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
 
 /* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
  *
@@ -1760,6 +1761,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
DELTA_TARGET,
N_CS_GPR
};
+   i915_reg_t mi_predicate_result = HAS_MI_SET_PREDICATE(i915) ?
+ MI_PREDICATE_RESULT_2_ENGINE(base) :
+ 
MI_PREDICATE_RESULT_1(RENDER_RING_BASE);
 
bo = i915_gem_object_create_internal(i915, 4096);
if (IS_ERR(bo)) {
@@ -1797,7 +1801,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
stream, cs, true /* save */, CS_GPR(i),
INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
cs = save_restore_register(
-   stream, cs, true /* save */, 
MI_PREDICATE_RESULT_1(RENDER_RING_BASE),
+   stream, cs, true /* save */, mi_predicate_result,
INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
 
/* First timestamp snapshot location. */
@@ -1851,7 +1855,10 @@ static int alloc_noa_wait(struct i915_perf_stream 
*stream)
 */
*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
-   *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE));
+   *cs++ = i915_mmio_reg_offset(mi_predicate_result);
+
+   if (HAS_MI_SET_PREDICATE(i915))
+   *cs++ = MI_SET_PREDICATE | 1;
 
/* Restart from the beginning if we had timestamps roll over. */
*cs++ = (GRAPHICS_VER(i915) < 8 ?
@@ -1861,6 +1868,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
*cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;
*cs++ = 0;
 
+   if (HAS_MI_SET_PREDICATE(i915))
+   *cs++ = MI_SET_PREDICATE;
+
/*
 * Now add the diff between to previous timestamps and add it to :
 *  (((1 * << 64) - 1) - delay_ns)
@@ -1888,7 +1898,10 @@ static int alloc_noa_wait(struct i915_perf_stream 
*stream)
 */
*cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
*cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
-   *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE));
+   *cs++ = i915_mmio_reg_offset(mi_predicate_result);
+
+   if (HAS_MI_SET_PREDICATE(i915))
+   *cs++ = MI_SET_PREDICATE | 1;
 
/* Predicate the jump.  */
*cs++ = (GRAPHICS_VER(i915) < 8 ?
@@ -1898,13 +1911,16 @@ static int alloc_noa_wait(struct i915_perf_stream 
*stream)
*cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;
*cs++ = 0;
 
+   if (HAS_MI_SET_PREDICATE(i915))
+   *cs++ = MI_SET_PREDICATE;
+
/* Restore registers. */
for (i = 0; i < N_CS_GPR; i++)
cs = save_restore_register(
stream, cs, false /* restore */, CS_GPR(i),
INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
cs = save_restore_register(
-   stream, cs, false /* restore */, 
MI_PREDICATE_RESULT_1(RENDER_RING_BASE),
+   stream, cs, 

[Intel-gfx] [PATCH v5 02/16] drm/i915/perf: Add 32-bit OAG and OAR formats for DG2

[Umesh Nerlige Ramappa]

Add new OA formats for DG2.

MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893

v2:
- Update commit title (Ashutosh)
- Coding style fixes (Lionel)
- 64 bit OA formats need UMD changes in GPUvis, drop for now and send in a
  separate series with UMD changes

v3:
- Update commit message to drop 64 bit related description

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Lionel Landwerlin  #1
---
 drivers/gpu/drm/i915/i915_perf.c | 7 +++
 include/uapi/drm/i915_drm.h  | 4 
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 255335868b6a..2b772a6b1cd6 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -320,6 +320,8 @@ static const struct i915_oa_format 
oa_formats[I915_OA_FORMAT_MAX] = {
[I915_OA_FORMAT_A12]= { 0, 64 },
[I915_OA_FORMAT_A12_B8_C8]  = { 2, 128 },
[I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
+   [I915_OAR_FORMAT_A32u40_A4u32_B8_C8]= { 5, 256 },
+   [I915_OA_FORMAT_A24u40_A14u32_B8_C8]= { 5, 256 },
 };
 
 #define SAMPLE_OA_REPORT  (1<<0)
@@ -4515,6 +4517,11 @@ static void oa_init_supported_formats(struct i915_perf 
*perf)
oa_format_add(perf, I915_OA_FORMAT_C4_B8);
break;
 
+   case INTEL_DG2:
+   oa_format_add(perf, I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
+   oa_format_add(perf, I915_OA_FORMAT_A24u40_A14u32_B8_C8);
+   break;
+
default:
MISSING_CASE(platform);
}
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 2e613109356b..158b35fb28f3 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2666,6 +2666,10 @@ enum drm_i915_oa_format {
I915_OA_FORMAT_A12_B8_C8,
I915_OA_FORMAT_A32u40_A4u32_B8_C8,
 
+   /* DG2 */
+   I915_OAR_FORMAT_A32u40_A4u32_B8_C8,
+   I915_OA_FORMAT_A24u40_A14u32_B8_C8,
+
I915_OA_FORMAT_MAX  /* non-ABI */
 };
 
-- 
2.25.1

[Intel-gfx] [PATCH v5 00/16] Add DG2 OA support

[Umesh Nerlige Ramappa]

Add OA format support for DG2 and various fixes for DG2.

This series has 2 uapi changes listed below:

1) drm/i915/perf: Add OAG and OAR formats for DG2

DG2 has new OA formats defined that can be selected by the
user. The UMD changes that are consumed by GPUvis are:
https://patchwork.freedesktop.org/patch/504456/?series=107633=5

Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893

2) drm/i915/perf: Apply Wa_18013179988

DG2 has a bug where the OA timestamp does not tick at the CS timestamp
frequency. Instead it ticks at a multiple that is determined from the
CTC_SHIFT value in RPM_CONFIG. Since the timestamp is used by UMD to
make sense of all the counters in the report, expose the OA timestamp
frequency to the user. The interface is generic and applies to all
platforms. On platforms where the bug is not present, this returns the
CS timestamp frequency. UMD specific changes consumed by GPUvis are:
https://patchwork.freedesktop.org/patch/504464/?series=107633=5

Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893

v2:
- Add review comments
- Update uapi changes in cover letter
- Drop patches for non-production platforms
drm/i915/perf: Use helpers to process reports w.r.t. OA buffer size
drm/i915/perf: Add Wa_16010703925:dg2

- Drop 64-bit OA format changes for now
drm/i915/perf: Parse 64bit report header formats correctly
drm/i915/perf: Add Wa_1608133521:dg2

v3:
- Add review comments to patches 02, 04, 05, 14
- Drop Acks

v4:
- Add review comments to patch 04
- Update R-bs
- Add MR links to patches 02 and 12

v5:
- Drop unrelated comment
- Rebase and fix MCR reg write
- On pre-gen12, EU flex config is saved/restored in the context image, so
  save/restore EU flex config only for gen12.

Test-with: 20221025200709.83314-1-umesh.nerlige.rama...@intel.com
Signed-off-by: Umesh Nerlige Ramappa 

Lionel Landwerlin (1):
  drm/i915/perf: complete programming whitelisting for XEHPSDV

Umesh Nerlige Ramappa (14):
  drm/i915/perf: Fix OA filtering logic for GuC mode
  drm/i915/perf: Add 32-bit OAG and OAR formats for DG2
  drm/i915/perf: Fix noa wait predication for DG2
  drm/i915/perf: Determine gen12 oa ctx offset at runtime
  drm/i915/perf: Enable bytes per clock reporting in OA
  drm/i915/perf: Simply use stream->ctx
  drm/i915/perf: Move gt-specific data from i915->perf to gt->perf
  drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops
  drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers
  drm/i915/perf: Store a pointer to oa_format in oa_buffer
  drm/i915/perf: Add Wa_1508761755:dg2
  drm/i915/perf: Apply Wa_18013179988
  drm/i915/perf: Save/restore EU flex counters across reset
  drm/i915/perf: Enable OA for DG2

Vinay Belgaumkar (1):
  drm/i915/guc: Support OA when Wa_16011777198 is enabled

 drivers/gpu/drm/i915/gt/intel_engine_regs.h   |   1 +
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h  |   4 +
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   |   1 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h  |   3 +
 drivers/gpu/drm/i915/gt/intel_lrc.h   |   2 +
 drivers/gpu/drm/i915/gt/intel_sseu.c  |   4 +-
 .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h |   9 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c|  10 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   |  66 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h   |   2 +
 drivers/gpu/drm/i915/i915_drv.h   |   5 +
 drivers/gpu/drm/i915/i915_getparam.c  |   3 +
 drivers/gpu/drm/i915/i915_pci.c   |   2 +
 drivers/gpu/drm/i915/i915_perf.c  | 576 ++
 drivers/gpu/drm/i915/i915_perf.h  |   2 +
 drivers/gpu/drm/i915/i915_perf_oa_regs.h  |   6 +-
 drivers/gpu/drm/i915/i915_perf_types.h|  47 +-
 drivers/gpu/drm/i915/intel_device_info.h  |   2 +
 drivers/gpu/drm/i915/selftests/i915_perf.c|  16 +-
 include/uapi/drm/i915_drm.h   |  10 +
 20 files changed, 630 insertions(+), 141 deletions(-)

-- 
2.25.1

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)
URL   : https://patchwork.freedesktop.org/series/109963/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109963v5_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_109963v5_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_109963v5_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109963v5_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1:
- shard-skl:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl7/igt@kms_cursor_crc@cursor-susp...@pipe-b-edp-1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl9/igt@kms_cursor_crc@cursor-susp...@pipe-b-edp-1.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@sysfs_preempt_timeout@idempotent@rcs0:
- {shard-dg1}:NOTRUN -> [FAIL][3] +4 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-dg1-15/igt@sysfs_preempt_timeout@idempot...@rcs0.html

  
Known issues


  Here are the changes found in Patchwork_109963v5_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb5/igt@gem_...@in-flight-contexts-10ms.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-tglb6/igt@gem_...@in-flight-contexts-10ms.html

  * igt@gem_eio@in-flight-suspend:
- shard-skl:  [PASS][6] -> [INCOMPLETE][7] ([i915#7112])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl10/igt@gem_...@in-flight-suspend.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl6/igt@gem_...@in-flight-suspend.html

  * igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb1/igt@gem_exec_balan...@parallel.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb5/igt@gem_exec_balan...@parallel.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl:  [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-apl6/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@gem_lmem_swapp...@parallel-random.html

  * igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][15] -> [FAIL][16] ([i915#3989] / [i915#454])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb5/igt@i915_pm...@dc6-dpms.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-iclb3/igt@i915_pm...@dc6-dpms.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl:  NOTRUN -> [SKIP][17] ([fdo#109271]) +43 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_big...@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_color_chamelium@ctm-limited-range:
- shard-skl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +2 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/shard-skl7/igt@kms_color_chamel...@ctm-limited-range.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl:  [PASS][19] -> [FAIL][20] ([i915#79]) +1 similar issue
   [19]: 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/display: Change terminology for cdclk actions

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/display: Change terminology for 
cdclk actions
URL   : https://patchwork.freedesktop.org/series/110135/
State : warning

== Summary ==

Error: dim checkpatch failed
4061a06bfea9 drm/i915/display: Change terminology for cdclk actions
cefbd65ae44b drm/i915/display: Introduce HAS_CDCLK_SQUASH macro
07489e559d80 drm/i915/display: Move chunks of code out of bxt_set_cdclk()
-:47: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#47: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1706:
+
+}

total: 0 errors, 0 warnings, 1 checks, 52 lines checked
94213e1b427f drm/i915/display: Move squash_ctl register programming to its own 
function
-:30: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#30: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1709:
+static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
+u16 waveform)

total: 0 errors, 0 warnings, 1 checks, 35 lines checked

[Intel-gfx] [PATCH v3] drm/i915: Fix CFI violations in gt_sysfs

[Andi Shyti]

From: Nathan Chancellor 

When booting with CONFIG_CFI_CLANG, there are numerous violations when
accessing the files under
/sys/devices/pci:00/:00:02.0/drm/card0/gt/gt0:

  $ cd /sys/devices/pci:00/:00:02.0/drm/card0/gt/gt0

  $ grep . *
  id:0
  punit_req_freq_mhz:350
  rc6_enable:1
  rc6_residency_ms:214934
  rps_act_freq_mhz:1300
  rps_boost_freq_mhz:1300
  rps_cur_freq_mhz:350
  rps_max_freq_mhz:1300
  rps_min_freq_mhz:350
  rps_RP0_freq_mhz:1300
  rps_RP1_freq_mhz:350
  rps_RPn_freq_mhz:350
  throttle_reason_pl1:0
  throttle_reason_pl2:0
  throttle_reason_pl4:0
  throttle_reason_prochot:0
  throttle_reason_ratl:0
  throttle_reason_status:0
  throttle_reason_thermal:0
  throttle_reason_vr_tdc:0
  throttle_reason_vr_thermalert:0

  $ sudo dmesg &| grep "CFI failure at"
  [  214.595903] CFI failure at kobj_attr_show+0x19/0x30 (target: 
id_show+0x0/0x70 [i915]; expected type: 0xc527b809)
  [  214.596064] CFI failure at kobj_attr_show+0x19/0x30 (target: 
punit_req_freq_mhz_show+0x0/0x40 [i915]; expected type: 0xc527b809)
  [  214.596407] CFI failure at kobj_attr_show+0x19/0x30 (target: 
rc6_enable_show+0x0/0x40 [i915]; expected type: 0xc527b809)
  [  214.596528] CFI failure at kobj_attr_show+0x19/0x30 (target: 
rc6_residency_ms_show+0x0/0x270 [i915]; expected type: 0xc527b809)
  [  214.596682] CFI failure at kobj_attr_show+0x19/0x30 (target: 
act_freq_mhz_show+0x0/0xe0 [i915]; expected type: 0xc527b809)
  [  214.596792] CFI failure at kobj_attr_show+0x19/0x30 (target: 
boost_freq_mhz_show+0x0/0xe0 [i915]; expected type: 0xc527b809)
  [  214.596893] CFI failure at kobj_attr_show+0x19/0x30 (target: 
cur_freq_mhz_show+0x0/0xe0 [i915]; expected type: 0xc527b809)
  [  214.596996] CFI failure at kobj_attr_show+0x19/0x30 (target: 
max_freq_mhz_show+0x0/0xe0 [i915]; expected type: 0xc527b809)
  [  214.597099] CFI failure at kobj_attr_show+0x19/0x30 (target: 
min_freq_mhz_show+0x0/0xe0 [i915]; expected type: 0xc527b809)
  [  214.597198] CFI failure at kobj_attr_show+0x19/0x30 (target: 
RP0_freq_mhz_show+0x0/0xe0 [i915]; expected type: 0xc527b809)
  [  214.597301] CFI failure at kobj_attr_show+0x19/0x30 (target: 
RP1_freq_mhz_show+0x0/0xe0 [i915]; expected type: 0xc527b809)
  [  214.597405] CFI failure at kobj_attr_show+0x19/0x30 (target: 
RPn_freq_mhz_show+0x0/0xe0 [i915]; expected type: 0xc527b809)
  [  214.597538] CFI failure at kobj_attr_show+0x19/0x30 (target: 
throttle_reason_bool_show+0x0/0x50 [i915]; expected type: 0xc527b809)
  [  214.597701] CFI failure at kobj_attr_show+0x19/0x30 (target: 
throttle_reason_bool_show+0x0/0x50 [i915]; expected type: 0xc527b809)
  [  214.597836] CFI failure at kobj_attr_show+0x19/0x30 (target: 
throttle_reason_bool_show+0x0/0x50 [i915]; expected type: 0xc527b809)
  [  214.597952] CFI failure at kobj_attr_show+0x19/0x30 (target: 
throttle_reason_bool_show+0x0/0x50 [i915]; expected type: 0xc527b809)
  [  214.598071] CFI failure at kobj_attr_show+0x19/0x30 (target: 
throttle_reason_bool_show+0x0/0x50 [i915]; expected type: 0xc527b809)
  [  214.598177] CFI failure at kobj_attr_show+0x19/0x30 (target: 
throttle_reason_bool_show+0x0/0x50 [i915]; expected type: 0xc527b809)
  [  214.598307] CFI failure at kobj_attr_show+0x19/0x30 (target: 
throttle_reason_bool_show+0x0/0x50 [i915]; expected type: 0xc527b809)
  [  214.598439] CFI failure at kobj_attr_show+0x19/0x30 (target: 
throttle_reason_bool_show+0x0/0x50 [i915]; expected type: 0xc527b809)
  [  214.598542] CFI failure at kobj_attr_show+0x19/0x30 (target: 
throttle_reason_bool_show+0x0/0x50 [i915]; expected type: 0xc527b809)

With kCFI, indirect calls are validated against their expected type
versus actual type and failures occur when the two types do not match.
The ultimate issue is that these sysfs functions are expecting to be
called via dev_attr_show() but they may also be called via
kobj_attr_show(), as certain files are created under two different
kobjects that have two different sysfs_ops in intel_gt_sysfs_register(),
hence the warnings above. When accessing the gt_ files under
/sys/devices/pci:00/:00:02.0/drm/card0, which are using the same
sysfs functions, there are no violations, meaning the functions are
being called with the proper type.

To make everything work properly, adjust certain functions to match the
type of the ->show() and ->store() members in 'struct kobj_attribute'.
Add a macro to generate functions for that can be called via both
dev_attr_{show,store}() or kobj_attr_{show,store}() so that they can be
called through both kobject locations without violating kCFI and adjust
the attribute groups to account for this.

Link: https://github.com/ClangBuiltLinux/linux/issues/1716
Reviewed-by: Andi Shyti 
Reviewed-by: Andrzej Hajda 
Reviewed-by: Kees Cook 
Signed-off-by: Nathan Chancellor 
Signed-off-by: Andi Shyti 
Link: 
https://patchwork.freedesktop.org/patch/msgid/20221013205909.1282545-1-nat...@kernel.org
---
Hi,

just respinning this patch as we got a failure from CI and I wanted to
be 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/slpc: Optmize waitboost for SLPC (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/slpc: Optmize waitboost for SLPC (rev6)
URL   : https://patchwork.freedesktop.org/series/109840/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12294 -> Patchwork_109840v6


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_109840v6 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_109840v6, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/index.html

Participating hosts (40 -> 39)
--

  Additional (1): fi-skl-guc 
  Missing(2): fi-ctg-p8600 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109840v6:

### IGT changes ###

 Possible regressions 

  * igt@i915_suspend@basic-s3-without-i915:
- fi-kbl-7567u:   [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-kbl-7567u/igt@i915_susp...@basic-s3-without-i915.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-kbl-7567u/igt@i915_susp...@basic-s3-without-i915.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@reset:
- {bat-rpls-2}:   [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-2/igt@i915_selftest@l...@reset.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/bat-rpls-2/igt@i915_selftest@l...@reset.html

  
Known issues


  Here are the changes found in Patchwork_109840v6 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-skl-guc: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-skl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@i915_selftest@live@guc_multi_lrc:
- fi-cfl-8109u:   [PASS][7] -> [DMESG-WARN][8] ([i915#5904] / 
[i915#7174]) +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-cfl-8109u/igt@i915_selftest@live@guc_multi_lrc.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-cfl-8109u/igt@i915_selftest@live@guc_multi_lrc.html

  * igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u:   [PASS][9] -> [DMESG-WARN][10] ([i915#5904]) +32 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u:   [PASS][11] -> [DMESG-WARN][12] ([i915#5904] / 
[i915#62]) +3 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-icl-u2:  NOTRUN -> [SKIP][15] ([fdo#111827])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-guc: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-skl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][17] ([fdo#109285])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u:   [PASS][18] -> [DMESG-WARN][19] ([i915#165] / 
[i915#62]) +14 similar issues
   [18]: 

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

[Matthew Garrett]

On Tue, Oct 25, 2022 at 08:50:54PM +0200, Hans de Goede wrote:

> That is a valid point, but keep in mind that this is only used on ACPI
> platforms and then only on devices with a builtin LCD panel and then
> only by GPU drivers which actually call acpi_video_get_backlight_type(),
> so e.g. not by all the ARM specific display drivers.
> 
> So I believe that Chromebooks quite likely are the only devices with
> this issue.

My laptop is, uh, weird, but it falls into this category.
 
> > I think for this to work correctly you need to have 
> > the infrastructure be aware of whether or not a vendor interface exists, 
> > which means having to handle cleanup if a vendor-specific module gets 
> > loaded later.
> 
> Getting rid of the whole ping-ponging of which backlight drivers
> get loaded during boot was actually one of the goals of the rework
> which landed in 6.1 this actually allowed us to remove some quirks
> because some hw/firmware did not like us changing our mind and
> switching backlight interfaces after first poking another one.
> So we definitely don't want to go back to the ping-pong thing.

Defaulting to native but then having a vendor driver be able to disable 
native drivers seems easiest? It shouldn't be a regression over the 
previous state of affairs since both drivers were being loaded already.

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

[Vudum, Lakshminarayana]

Regression failures are related to 
https://gitlab.freedesktop.org/drm/intel/-/issues/7311
Re-reported.

Lakshmi.
-Original Message-
From: Auld, Matthew  
Sent: Tuesday, October 25, 2022 2:09 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 

Subject: Re: ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT 
alignment"

On 24/10/2022 12:55, Patchwork wrote:
> *Patch Details*
> *Series:* Revert "drm/i915/uapi: expose GTT alignment"
> *URL:*https://patchwork.freedesktop.org/series/110041/ 
> 
> *State:*  failure
> *Details:*
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html
>  l>
> 
> 
>   CI Bug Log - changes from CI_DRM_12284 -> Patchwork_110041v1
> 
> 
> Summary
> 
> *FAILURE*
> 
> Serious unknown changes coming with Patchwork_110041v1 absolutely need 
> to be verified manually.
> 
> If you think the reported changes have nothing to do with the changes 
> introduced in Patchwork_110041v1, please notify your bug team to allow 
> them to document this new failure mode, which will reduce false positives in 
> CI.
> 
> External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html
> 
> 
> Participating hosts (41 -> 41)
> 
> Additional (3): fi-hsw-4770 fi-icl-u2 bat-atsm-1 Missing (3): 
> fi-ctg-p8600 fi-bdw-samus fi-tgl-dsi
> 
> 
> Possible new issues
> 
> Here are the unknown changes that may have been introduced in
> Patchwork_110041v1:
> 
> 
>   IGT changes
> 
> 
> Possible regressions
> 
>   *
> 
> igt@i915_selftest@live@hugepages:
> 
>   o
> 
> fi-glk-j4005: PASS
> 
>  t@i915_selftest@l...@hugepages.html> -> DMESG-FAIL 
>  005/igt@i915_selftest@l...@hugepages.html>
> 
>   o
> 
> fi-rkl-guc: PASS
> 
>  i915_selftest@l...@hugepages.html> -> DMESG-FAIL 
>  c/igt@i915_selftest@l...@hugepages.html>
> 
>   o
> 
> fi-icl-u2: NOTRUN -> DMESG-FAIL
> 
>  /igt@i915_selftest@l...@hugepages.html>
> 

These failures are unrelated. 
https://gitlab.freedesktop.org/drm/intel/-/issues/7311

> 
> Suppressed
> 
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
> 
>   * igt@gem_exec_parallel@engines@contexts:
>   o {fi-ehl-2}: PASS
> 
>  m_exec_parallel@engi...@contexts.html> -> INCOMPLETE 
>  igt@gem_exec_parallel@engi...@contexts.html>
> 
> 
> Known issues
> 
> Here are the changes found in Patchwork_110041v1 that come from known
> issues:
> 
> 
>   IGT changes
> 
> 
> Issues hit
> 
>   *
> 
> igt@gem_exec_gttfill@basic:
> 
>   o fi-pnv-d510: PASS
> 
> 
>  -> FAIL 
> 
>  (i915#7229 )
>   *
> 
> igt@gem_huc_copy@huc-copy:
> 
>   o fi-icl-u2: NOTRUN -> SKIP
> 
> 
>  (i915#2190 )
>   *
> 
> igt@gem_lmem_swapping@random-engines:
> 
>   o fi-icl-u2: NOTRUN -> SKIP
> 
> 
>  (i915#4613 ) +3 
> similar issues
>   *
> 
> igt@gem_render_tiled_blits@basic:
> 
>   o fi-apl-guc: PASS
> 
> 
>  -> INCOMPLETE 
> 
>  (i915#7056 )
>   *
> 
> igt@gem_softpin@allocator-basic-reserve:
> 
>   o fi-hsw-4770: NOTRUN -> SKIP
> 
> 
>  (fdo#109271 ) +9 
> similar issues
>   *
> 
> igt@i915_pm_backlight@basic-brightness:
> 
>   o fi-hsw-4770: NOTRUN -> SKIP
> 
> 

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dg2: Introduce Wa_18018764978

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/dg2: Introduce Wa_18018764978
URL   : https://patchwork.freedesktop.org/series/110131/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12294 -> Patchwork_110131v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/index.html

Participating hosts (40 -> 38)
--

  Additional (1): fi-skl-guc 
  Missing(3): fi-ctg-p8600 fi-icl-u2 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_110131v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-skl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/fi-skl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][2] -> [DMESG-FAIL][3] ([i915#5334])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-guc: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/fi-skl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-skl-guc: NOTRUN -> [SKIP][6] ([fdo#109271]) +10 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/fi-skl-guc/igt@kms_psr@sprite_plane_onoff.html

  
 Possible fixes 

  * igt@fbdev@read:
- {bat-rpls-2}:   [SKIP][7] ([i915#2582]) -> [PASS][8] +4 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-2/igt@fb...@read.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/bat-rpls-2/igt@fb...@read.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [INCOMPLETE][9] ([i915#3303] / [i915#4785]) -> 
[PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@slpc:
- {bat-rpls-1}:   [DMESG-FAIL][11] ([i915#6367]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-1/igt@i915_selftest@l...@slpc.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [FAIL][13] ([i915#6298]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997


Build changes
-

  * Linux: CI_DRM_12294 -> Patchwork_110131v1

  CI-20190529: 20190529
  CI_DRM_12294: fca30d6149441ff19df784c0554b8c20a29c7f53 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7026: ce0f97e7e0aa54c40049a8365b3d61773c92e588 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_110131v1: fca30d6149441ff19df784c0554b8c20a29c7f53 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

fd1f4c786109 drm/i915/dg2: Introduce Wa_18019271663
7eae151085da drm/i915/dg2: Introduce Wa_18018764978

== Logs ==

For more details see: 

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

[Hans de Goede]

Hi,

On 10/24/22 22:30, Matthew Garrett wrote:
> On Tue, Sep 27, 2022 at 01:04:52PM +0200, Hans de Goede wrote:
> 
>> So to fix this we need to make acpi_video_get_backlight_type()
>> return native on the Acer Chromebook Spin 713.
> 
> Isn't the issue broader than that? Unless the platform is Windows 8 or 
> later, we'll *always* (outside of some corner cases) return 
> acpi_backlight_vendor if there's no ACPI video interface. This is broken 
> for any platform that implements ACPI but relies on native video 
> control, which is going to include a range of Coreboot platforms, not 
> just Chromebooks.

That is a valid point, but keep in mind that this is only used on ACPI
platforms and then only on devices with a builtin LCD panel and then
only by GPU drivers which actually call acpi_video_get_backlight_type(),
so e.g. not by all the ARM specific display drivers.

So I believe that Chromebooks quite likely are the only devices with
this issue.

We could do something like the patch which I have pasted at the end
of this email, but as its commit message notes there is a real
good chance this will cause regressions on some laptops.

So if we ever decide to go with something like the patch below,
I think we should at a minimum wait for the next cycle with that,
because 6.1 already significantly reworks the ACPI backlight
detect handling and I don't want to throw this into the mix
on top of those changes.

> I think for this to work correctly you need to have 
> the infrastructure be aware of whether or not a vendor interface exists, 
> which means having to handle cleanup if a vendor-specific module gets 
> loaded later.

Getting rid of the whole ping-ponging of which backlight drivers
get loaded during boot was actually one of the goals of the rework
which landed in 6.1 this actually allowed us to remove some quirks
because some hw/firmware did not like us changing our mind and
switching backlight interfaces after first poking another one.
So we definitely don't want to go back to the ping-pong thing.

Regards,

Hans



>From 67ee5d7163e33e65dca06887befd0639b0345883 Mon Sep 17 00:00:00 2001
From: Hans de Goede 
Date: Tue, 25 Oct 2022 20:38:56 +0200
Subject: [PATCH] ACPI: video: Simplify __acpi_video_get_backlight_type()

Simplify __acpi_video_get_backlight_type() removing a nested if which
makes the flow harder to follow.

Note this will cause a behavior change on devices which do not have
ACPI video support but do have both a vendor and native backlight
driver available. This change will cause these devices to switch
from vendor to native.

This may not be desirable in all cases, this is likely to happen
on significantly older laptops, where there very well might be
cases where the native driver does not work because the backlight is
controlled by the EC.

This removes the need for the special handling of Chromebooks,
these will now hit the if (native_available) return acpi_backlight_native;
path.

Signed-off-by: Hans de Goede 
---
 drivers/acpi/video_detect.c | 36 +++-
 1 file changed, 11 insertions(+), 25 deletions(-)

diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c
index 9cd8797d12bb..9bd85b159e02 100644
--- a/drivers/acpi/video_detect.c
+++ b/drivers/acpi/video_detect.c
@@ -668,11 +668,6 @@ static const struct dmi_system_id video_detect_dmi_table[] 
= {
{ },
 };
 
-static bool google_cros_ec_present(void)
-{
-   return acpi_dev_found("GOOG0004");
-}
-
 /*
  * Determine which type of backlight interface to use on this system,
  * First check cmdline, then dmi quirks, then do autodetect.
@@ -718,30 +713,21 @@ static enum acpi_backlight_type 
__acpi_video_get_backlight_type(bool native)
if (apple_gmux_present())
return acpi_backlight_apple_gmux;
 
-   /* On systems with ACPI video use either native or ACPI video. */
-   if (video_caps & ACPI_VIDEO_BACKLIGHT) {
-   /*
-* Windows 8 and newer no longer use the ACPI video interface,
-* so it often does not work. If the ACPI tables are written
-* for win8 and native brightness ctl is available, use that.
-*
-* The native check deliberately is inside the if acpi-video
-* block on older devices without acpi-video support native
-* is usually not the best choice.
-*/
-   if (acpi_osi_is_win8() && native_available)
-   return acpi_backlight_native;
-   else
-   return acpi_backlight_video;
-   }
-
/*
-* Chromebooks that don't have backlight handle in ACPI table
-* are supposed to use native backlight if it's available.
+* Pre Windows 8, Windows uses ACPI video, so prefer that over native
+* on pre-win8 systems (Windows 8+ no longer uses ACPI video).
 */
-   if (google_cros_ec_present() && native_available)
+   

[Intel-gfx] [PATCH 09/10] vfio: Make vfio_container optionally compiled

[Jason Gunthorpe]

Add a kconfig CONFIG_VFIO_CONTAINER that controls compiling the container
code. If 'n' then only iommufd will provide the container service. All the
support for vfio iommu drivers, including type1, will not be built.

This allows a compilation check that no inappropriate dependencies between
the device/group and container have been created.

Signed-off-by: Jason Gunthorpe 
---
 drivers/vfio/Kconfig  | 37 
 drivers/vfio/Makefile |  4 +--
 drivers/vfio/vfio.h   | 65 +++
 3 files changed, 92 insertions(+), 14 deletions(-)

diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig
index 1118d322eec97d..d384419d151dda 100644
--- a/drivers/vfio/Kconfig
+++ b/drivers/vfio/Kconfig
@@ -3,8 +3,8 @@ menuconfig VFIO
tristate "VFIO Non-Privileged userspace driver framework"
select IOMMU_API
depends on IOMMUFD || !IOMMUFD
-   select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64)
select INTERVAL_TREE
+   select VFIO_CONTAINER if IOMMUFD=n
help
  VFIO provides a framework for secure userspace device drivers.
  See Documentation/driver-api/vfio.rst for more details.
@@ -12,25 +12,27 @@ menuconfig VFIO
  If you don't know what to do here, say N.
 
 if VFIO
+config VFIO_CONTAINER
+   bool "Support for the VFIO container /dev/vfio/vfio"
+   select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64)
+   default y
+   help
+ The VFIO container is the classic interface to VFIO for establishing
+ mappings. If N is selected here then IOMMUFD must be used the manage
+ the mappings.
+
+ Unless testing IOMMUFD say Y here.
+
+if VFIO_CONTAINER
 config VFIO_IOMMU_TYPE1
tristate
-   default n
+   default MMU && (X86 || S390 || ARM || ARM64)
 
 config VFIO_IOMMU_SPAPR_TCE
tristate
depends on SPAPR_TCE_IOMMU
default VFIO
 
-config VFIO_SPAPR_EEH
-   tristate
-   depends on EEH && VFIO_IOMMU_SPAPR_TCE
-   default VFIO
-
-config VFIO_VIRQFD
-   tristate
-   select EVENTFD
-   default n
-
 config VFIO_NOIOMMU
bool "VFIO No-IOMMU support"
help
@@ -44,6 +46,17 @@ config VFIO_NOIOMMU
  this mode since there is no IOMMU to provide DMA translation.
 
  If you don't know what to do here, say N.
+endif
+
+config VFIO_SPAPR_EEH
+   tristate
+   depends on EEH && VFIO_IOMMU_SPAPR_TCE
+   default VFIO
+
+config VFIO_VIRQFD
+   tristate
+   select EVENTFD
+   default n
 
 source "drivers/vfio/pci/Kconfig"
 source "drivers/vfio/platform/Kconfig"
diff --git a/drivers/vfio/Makefile b/drivers/vfio/Makefile
index 3863922529ef20..b953517dc70f99 100644
--- a/drivers/vfio/Makefile
+++ b/drivers/vfio/Makefile
@@ -4,9 +4,9 @@ vfio_virqfd-y := virqfd.o
 obj-$(CONFIG_VFIO) += vfio.o
 
 vfio-y += vfio_main.o \
- iova_bitmap.o \
- container.o
+ iova_bitmap.o
 vfio-$(CONFIG_IOMMUFD) += iommufd.o
+vfio-$(CONFIG_VFIO_CONTAINER) += container.o
 
 obj-$(CONFIG_VFIO_VIRQFD) += vfio_virqfd.o
 obj-$(CONFIG_VFIO_IOMMU_TYPE1) += vfio_iommu_type1.o
diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
index d57a08afb5cf5c..3378714a746274 100644
--- a/drivers/vfio/vfio.h
+++ b/drivers/vfio/vfio.h
@@ -55,7 +55,9 @@ struct vfio_group {
struct list_headdevice_list;
struct mutexdevice_lock;
struct list_headvfio_next;
+#if IS_ENABLED(CONFIG_VFIO_CONTAINER)
struct list_headcontainer_next;
+#endif
enum vfio_group_typetype;
struct mutexgroup_lock;
struct kvm  *kvm;
@@ -64,6 +66,7 @@ struct vfio_group {
struct iommufd_ctx  *iommufd;
 };
 
+#if IS_ENABLED(CONFIG_VFIO_CONTAINER)
 /* events for the backend driver notify callback */
 enum vfio_iommu_notify_type {
VFIO_IOMMU_CONTAINER_CLOSE = 0,
@@ -129,6 +132,68 @@ int vfio_container_dma_rw(struct vfio_container 
*container, dma_addr_t iova,
 
 int __init vfio_container_init(void);
 void vfio_container_cleanup(void);
+#else
+static inline struct vfio_container *
+vfio_container_from_file(struct file *filep)
+{
+   return NULL;
+}
+
+static inline int vfio_group_use_container(struct vfio_group *group)
+{
+   return -EOPNOTSUPP;
+}
+
+static inline void vfio_group_unuse_container(struct vfio_group *group)
+{
+}
+
+static inline int vfio_container_attach_group(struct vfio_container *container,
+ struct vfio_group *group)
+{
+   return -EOPNOTSUPP;
+}
+
+static inline void vfio_group_detach_container(struct vfio_group *group)
+{
+}
+
+static inline void vfio_device_container_register(struct vfio_device *device)
+{
+}
+
+static inline void vfio_device_container_unregister(struct vfio_device *device)
+{
+}
+
+static inline int 

[Intel-gfx] [PATCH 06/10] vfio-iommufd: Allow iommufd to be used in place of a container fd

[Jason Gunthorpe]

This makes VFIO_GROUP_SET_CONTAINER accept both a vfio container FD and an
iommufd.

In iommufd mode an IOAS will exist after the SET_CONTAINER, but it will
not be attached to any groups.

>From a VFIO perspective this means that the VFIO_GROUP_GET_STATUS and
VFIO_GROUP_FLAGS_VIABLE works subtly differently. With the container FD
the iommu_group_claim_dma_owner() is done during SET_CONTAINER but for
IOMMFD this is done during VFIO_GROUP_GET_DEVICE_FD. Meaning that
VFIO_GROUP_FLAGS_VIABLE could be set but GET_DEVICE_FD will fail due to
viability.

As GET_DEVICE_FD can fail for many reasons already this is not expected to
be a meaningful difference.

Reorganize the tests for if the group has an assigned container or iommu
into a vfio_group_has_iommu() function and consolidate all the duplicated
WARN_ON's etc related to this.

Call container functions only if a container is actually present on the
group.

Signed-off-by: Jason Gunthorpe 
---
 drivers/vfio/Kconfig |  1 +
 drivers/vfio/container.c |  7 ++--
 drivers/vfio/vfio.h  |  2 ++
 drivers/vfio/vfio_main.c | 76 
 4 files changed, 69 insertions(+), 17 deletions(-)

diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig
index 86c381ceb9a1e9..1118d322eec97d 100644
--- a/drivers/vfio/Kconfig
+++ b/drivers/vfio/Kconfig
@@ -2,6 +2,7 @@
 menuconfig VFIO
tristate "VFIO Non-Privileged userspace driver framework"
select IOMMU_API
+   depends on IOMMUFD || !IOMMUFD
select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64)
select INTERVAL_TREE
help
diff --git a/drivers/vfio/container.c b/drivers/vfio/container.c
index d97747dfb05d02..8772dad6808539 100644
--- a/drivers/vfio/container.c
+++ b/drivers/vfio/container.c
@@ -516,8 +516,11 @@ int vfio_group_use_container(struct vfio_group *group)
 {
lockdep_assert_held(>group_lock);
 
-   if (!group->container || !group->container->iommu_driver ||
-   WARN_ON(!group->container_users))
+   /*
+* The container fd has been assigned with VFIO_GROUP_SET_CONTAINER but
+* VFIO_SET_IOMMU hasn't been done yet.
+*/
+   if (!group->container->iommu_driver)
return -EINVAL;
 
if (group->type == VFIO_NO_IOMMU && !capable(CAP_SYS_RAWIO))
diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
index 247590334e14b0..985e13d52989ca 100644
--- a/drivers/vfio/vfio.h
+++ b/drivers/vfio/vfio.h
@@ -10,6 +10,7 @@
 #include 
 #include 
 
+struct iommufd_ctx;
 struct iommu_group;
 struct vfio_device;
 struct vfio_container;
@@ -60,6 +61,7 @@ struct vfio_group {
struct kvm  *kvm;
struct file *opened_file;
struct blocking_notifier_head   notifier;
+   struct iommufd_ctx  *iommufd;
 };
 
 /* events for the backend driver notify callback */
diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index a8d1fbfcc3ddad..cf0ea744de931e 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -35,6 +35,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "vfio.h"
 
 #define DRIVER_VERSION "0.3"
@@ -665,6 +666,16 @@ EXPORT_SYMBOL_GPL(vfio_unregister_group_dev);
 /*
  * VFIO Group fd, /dev/vfio/$GROUP
  */
+static bool vfio_group_has_iommu(struct vfio_group *group)
+{
+   lockdep_assert_held(>group_lock);
+   if (!group->container)
+   WARN_ON(group->container_users);
+   else
+   WARN_ON(!group->container_users);
+   return group->container || group->iommufd;
+}
+
 /*
  * VFIO_GROUP_UNSET_CONTAINER should fail if there are other users or
  * if there was no container to unset.  Since the ioctl is called on
@@ -676,15 +687,21 @@ static int vfio_group_ioctl_unset_container(struct 
vfio_group *group)
int ret = 0;
 
mutex_lock(>group_lock);
-   if (!group->container) {
+   if (!vfio_group_has_iommu(group)) {
ret = -EINVAL;
goto out_unlock;
}
-   if (group->container_users != 1) {
-   ret = -EBUSY;
-   goto out_unlock;
+   if (group->container) {
+   if (group->container_users != 1) {
+   ret = -EBUSY;
+   goto out_unlock;
+   }
+   vfio_group_detach_container(group);
+   }
+   if (group->iommufd) {
+   iommufd_ctx_put(group->iommufd);
+   group->iommufd = NULL;
}
-   vfio_group_detach_container(group);
 
 out_unlock:
mutex_unlock(>group_lock);
@@ -695,6 +712,7 @@ static int vfio_group_ioctl_set_container(struct vfio_group 
*group,
  int __user *arg)
 {
struct vfio_container *container;
+   struct iommufd_ctx *iommufd;
struct fd f;
int ret;
int fd;
@@ -707,7 +725,7 @@ static int vfio_group_ioctl_set_container(struct vfio_group 
*group,
   

[Intel-gfx] [PATCH 07/10] vfio-iommufd: Support iommufd for physical VFIO devices

[Jason Gunthorpe]

This creates the iommufd_device for the physical VFIO drivers. These are
all the drivers that are calling vfio_register_group_dev() and expect the
type1 code to setup a real iommu_domain against their parent struct
device.

The design gives the driver a choice in how it gets connected to iommufd
by providing bind_iommufd/unbind_iommufd/attach_ioas callbacks to
implement as required. The core code provides three default callbacks for
physical mode using a real iommu_domain. This is suitable for drivers
using vfio_register_group_dev()

Signed-off-by: Jason Gunthorpe 
---
 drivers/vfio/Makefile |   1 +
 drivers/vfio/fsl-mc/vfio_fsl_mc.c |   3 +
 drivers/vfio/iommufd.c| 104 ++
 .../vfio/pci/hisilicon/hisi_acc_vfio_pci.c|   6 +
 drivers/vfio/pci/mlx5/main.c  |   3 +
 drivers/vfio/pci/vfio_pci.c   |   3 +
 drivers/vfio/platform/vfio_amba.c |   3 +
 drivers/vfio/platform/vfio_platform.c |   3 +
 drivers/vfio/vfio.h   |  15 +++
 drivers/vfio/vfio_main.c  |  13 ++-
 include/linux/vfio.h  |  25 +
 11 files changed, 177 insertions(+), 2 deletions(-)
 create mode 100644 drivers/vfio/iommufd.c

diff --git a/drivers/vfio/Makefile b/drivers/vfio/Makefile
index b693a1169286f8..3863922529ef20 100644
--- a/drivers/vfio/Makefile
+++ b/drivers/vfio/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_VFIO) += vfio.o
 vfio-y += vfio_main.o \
  iova_bitmap.o \
  container.o
+vfio-$(CONFIG_IOMMUFD) += iommufd.o
 
 obj-$(CONFIG_VFIO_VIRQFD) += vfio_virqfd.o
 obj-$(CONFIG_VFIO_IOMMU_TYPE1) += vfio_iommu_type1.o
diff --git a/drivers/vfio/fsl-mc/vfio_fsl_mc.c 
b/drivers/vfio/fsl-mc/vfio_fsl_mc.c
index b16874e913e4f5..5cd4bb47644039 100644
--- a/drivers/vfio/fsl-mc/vfio_fsl_mc.c
+++ b/drivers/vfio/fsl-mc/vfio_fsl_mc.c
@@ -592,6 +592,9 @@ static const struct vfio_device_ops vfio_fsl_mc_ops = {
.read   = vfio_fsl_mc_read,
.write  = vfio_fsl_mc_write,
.mmap   = vfio_fsl_mc_mmap,
+   .bind_iommufd   = vfio_iommufd_physical_bind,
+   .unbind_iommufd = vfio_iommufd_physical_unbind,
+   .attach_ioas= vfio_iommufd_physical_attach_ioas,
 };
 
 static struct fsl_mc_driver vfio_fsl_mc_driver = {
diff --git a/drivers/vfio/iommufd.c b/drivers/vfio/iommufd.c
new file mode 100644
index 00..8280bb32ee677c
--- /dev/null
+++ b/drivers/vfio/iommufd.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES
+ */
+#include 
+#include 
+
+#include "vfio.h"
+
+MODULE_IMPORT_NS(IOMMUFD);
+MODULE_IMPORT_NS(IOMMUFD_VFIO);
+
+int vfio_iommufd_bind(struct vfio_device *vdev, struct iommufd_ctx *ictx)
+{
+   u32 ioas_id;
+   u32 device_id;
+   int ret;
+
+   lockdep_assert_held(>dev_set->lock);
+
+   /*
+* If the driver doesn't provide this op then it means the device does
+* not do DMA at all. So nothing to do.
+*/
+   if (!vdev->ops->bind_iommufd)
+   return 0;
+
+   ret = vdev->ops->bind_iommufd(vdev, ictx, _id);
+   if (ret)
+   return ret;
+
+   if (vdev->ops->attach_ioas) {
+   ret = iommufd_vfio_compat_ioas_id(ictx, _id);
+   if (ret)
+   goto err_unbind;
+   ret = vdev->ops->attach_ioas(vdev, _id);
+   if (ret)
+   goto err_unbind;
+   vdev->iommufd_attached = true;
+   }
+
+   /*
+* The legacy path has no way to return the device id or the selected
+* pt_id
+*/
+   return 0;
+
+err_unbind:
+   if (vdev->ops->unbind_iommufd)
+   vdev->ops->unbind_iommufd(vdev);
+   return ret;
+}
+
+void vfio_iommufd_unbind(struct vfio_device *vdev)
+{
+   lockdep_assert_held(>dev_set->lock);
+
+   if (!vdev->iommufd_device)
+   return;
+
+   if (vdev->ops->unbind_iommufd)
+   vdev->ops->unbind_iommufd(vdev);
+}
+
+/*
+ * The physical standard ops mean that the iommufd_device is bound to the
+ * physical device vdev->dev that was provided to vfio_init_group_dev(). 
Drivers
+ * using this ops set should call vfio_register_group_dev()
+ */
+int vfio_iommufd_physical_bind(struct vfio_device *vdev,
+  struct iommufd_ctx *ictx, u32 *out_device_id)
+{
+   struct iommufd_device *idev;
+
+   idev = iommufd_device_bind(ictx, vdev->dev, out_device_id);
+   if (IS_ERR(idev))
+   return PTR_ERR(idev);
+   vdev->iommufd_device = idev;
+   return 0;
+}
+EXPORT_SYMBOL_GPL(vfio_iommufd_physical_bind);
+
+void vfio_iommufd_physical_unbind(struct vfio_device *vdev)
+{
+   lockdep_assert_held(>dev_set->lock);
+
+   if (vdev->iommufd_attached) {
+   iommufd_device_detach(vdev->iommufd_device);
+ 

[Intel-gfx] [PATCH 08/10] vfio-iommufd: Support iommufd for emulated VFIO devices

[Jason Gunthorpe]

Emulated VFIO devices are calling vfio_register_emulated_iommu_dev() and
consist of all the mdev drivers.

Like the physical drivers, support for iommufd is provided by the driver
supplying the correct correct standard ops. Provide ops from the core that
duplicate what vfio_register_emulated_iommu_dev() does.

Emulated drivers are where it is more likely to see variation in the
iommfd support ops. For instance IDXD will probably need to setup both a
iommfd_device context linked to a PASID and an iommufd_access context to
support all their mdev operations.

Signed-off-by: Jason Gunthorpe 
---
 drivers/gpu/drm/i915/gvt/kvmgt.c  |   3 +
 drivers/s390/cio/vfio_ccw_ops.c   |   3 +
 drivers/s390/crypto/vfio_ap_ops.c |   3 +
 drivers/vfio/container.c  | 108 ++---
 drivers/vfio/iommufd.c|  57 
 drivers/vfio/vfio.h   |  10 ++-
 drivers/vfio/vfio_main.c  | 110 +-
 include/linux/vfio.h  |  14 
 8 files changed, 217 insertions(+), 91 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 7a45e5360caf2d..579b230a0f58d9 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -1474,6 +1474,9 @@ static const struct vfio_device_ops intel_vgpu_dev_ops = {
.mmap   = intel_vgpu_mmap,
.ioctl  = intel_vgpu_ioctl,
.dma_unmap  = intel_vgpu_dma_unmap,
+   .bind_iommufd   = vfio_iommufd_emulated_bind,
+   .unbind_iommufd = vfio_iommufd_emulated_unbind,
+   .attach_ioas= vfio_iommufd_emulated_attach_ioas,
 };
 
 static int intel_vgpu_probe(struct mdev_device *mdev)
diff --git a/drivers/s390/cio/vfio_ccw_ops.c b/drivers/s390/cio/vfio_ccw_ops.c
index 6ae4d012d80084..560453d99c24fc 100644
--- a/drivers/s390/cio/vfio_ccw_ops.c
+++ b/drivers/s390/cio/vfio_ccw_ops.c
@@ -588,6 +588,9 @@ static const struct vfio_device_ops vfio_ccw_dev_ops = {
.ioctl = vfio_ccw_mdev_ioctl,
.request = vfio_ccw_mdev_request,
.dma_unmap = vfio_ccw_dma_unmap,
+   .bind_iommufd = vfio_iommufd_emulated_bind,
+   .unbind_iommufd = vfio_iommufd_emulated_unbind,
+   .attach_ioas = vfio_iommufd_emulated_attach_ioas,
 };
 
 struct mdev_driver vfio_ccw_mdev_driver = {
diff --git a/drivers/s390/crypto/vfio_ap_ops.c 
b/drivers/s390/crypto/vfio_ap_ops.c
index 0b4cc8c597ae67..bb7776d207924f 100644
--- a/drivers/s390/crypto/vfio_ap_ops.c
+++ b/drivers/s390/crypto/vfio_ap_ops.c
@@ -1789,6 +1789,9 @@ static const struct vfio_device_ops 
vfio_ap_matrix_dev_ops = {
.close_device = vfio_ap_mdev_close_device,
.ioctl = vfio_ap_mdev_ioctl,
.dma_unmap = vfio_ap_mdev_dma_unmap,
+   .bind_iommufd = vfio_iommufd_emulated_bind,
+   .unbind_iommufd = vfio_iommufd_emulated_unbind,
+   .attach_ioas = vfio_iommufd_emulated_attach_ioas,
 };
 
 static struct mdev_driver vfio_ap_matrix_driver = {
diff --git a/drivers/vfio/container.c b/drivers/vfio/container.c
index 8772dad6808539..0388f2e33447eb 100644
--- a/drivers/vfio/container.c
+++ b/drivers/vfio/container.c
@@ -540,113 +540,45 @@ void vfio_group_unuse_container(struct vfio_group *group)
fput(group->opened_file);
 }
 
-/*
- * Pin contiguous user pages and return their associated host pages for local
- * domain only.
- * @device [in]  : device
- * @iova [in]: starting IOVA of user pages to be pinned.
- * @npage [in]   : count of pages to be pinned.  This count should not
- *be greater than VFIO_PIN_PAGES_MAX_ENTRIES.
- * @prot [in]: protection flags
- * @pages[out]   : array of host pages
- * Return error or number of pages pinned.
- *
- * A driver may only call this function if the vfio_device was created
- * by vfio_register_emulated_iommu_dev().
- */
-int vfio_pin_pages(struct vfio_device *device, dma_addr_t iova,
-  int npage, int prot, struct page **pages)
+int vfio_container_pin_pages(struct vfio_container *container,
+struct iommu_group *iommu_group, dma_addr_t iova,
+int npage, int prot, struct page **pages)
 {
-   struct vfio_container *container;
-   struct vfio_group *group = device->group;
-   struct vfio_iommu_driver *driver;
-   int ret;
-
-   if (!pages || !npage || !vfio_assert_device_open(device))
-   return -EINVAL;
+   /* group->container cannot change while a vfio device is open */
+   struct vfio_iommu_driver *driver = container->iommu_driver;
 
if (npage > VFIO_PIN_PAGES_MAX_ENTRIES)
return -E2BIG;
 
/* group->container cannot change while a vfio device is open */
-   container = group->container;
driver = container->iommu_driver;
-   if (likely(driver && driver->ops->pin_pages))
-   ret = driver->ops->pin_pages(container->iommu_data,
-

[Intel-gfx] [PATCH 10/10] iommufd: Allow iommufd to supply /dev/vfio/vfio

[Jason Gunthorpe]

If the VFIO container is compiled out, give a kconfig option for iommufd
to provide the miscdev node with the same name and permissions as vfio
uses.

The compatibility node supports the same ioctls as VFIO and automatically
enables the VFIO compatible pinned page accounting mode.

Signed-off-by: Jason Gunthorpe 
---
 drivers/iommu/iommufd/Kconfig | 12 
 drivers/iommu/iommufd/main.c  | 35 ---
 2 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/drivers/iommu/iommufd/Kconfig b/drivers/iommu/iommufd/Kconfig
index f0a2012234fa09..afc83b7575cce6 100644
--- a/drivers/iommu/iommufd/Kconfig
+++ b/drivers/iommu/iommufd/Kconfig
@@ -14,6 +14,18 @@ config IOMMUFD
  If you don't know what to do here, say N.
 
 if IOMMUFD
+config IOMMUFD_VFIO_CONTAINER
+   bool "IOMMUFD provides the VFIO container /dev/vfio/vfio"
+   depends on VFIO && !VFIO_CONTAINER
+   default VFIO && !VFIO_CONTAINER
+   help
+ IOMMUFD will provide /dev/vfio/vfio instead of VFIO. This relies on
+ IOMMUFD providing compatibility emulation to give the same ioctls.
+ It provides an option to build a kernel with legacy VFIO components
+ removed.
+
+ Unless testing IOMMUFD say N here.
+
 config IOMMUFD_TEST
bool "IOMMU Userspace API Test support"
depends on RUNTIME_TESTING_MENU
diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c
index 8a31c1a14cdd53..19db81fbf7f08f 100644
--- a/drivers/iommu/iommufd/main.c
+++ b/drivers/iommu/iommufd/main.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 
+#include "io_pagetable.h"
 #include "iommufd_private.h"
 #include "iommufd_test.h"
 
@@ -31,6 +32,7 @@ struct iommufd_object_ops {
void (*destroy)(struct iommufd_object *obj);
 };
 static struct iommufd_object_ops iommufd_object_ops[];
+static struct miscdevice vfio_misc_dev;
 
 struct iommufd_object *_iommufd_object_alloc(struct iommufd_ctx *ictx,
 size_t size,
@@ -167,6 +169,13 @@ static int iommufd_fops_open(struct inode *inode, struct 
file *filp)
if (!ictx)
return -ENOMEM;
 
+   /*
+* For compatibility with VFIO when /dev/vfio/vfio is opened we default
+* to the same rlimit accounting as vfio uses.
+*/
+   if (filp->private_data == _misc_dev)
+   ictx->account_mode = IOPT_PAGES_ACCOUNT_MM;
+
xa_init_flags(>objects, XA_FLAGS_ALLOC1 | XA_FLAGS_ACCOUNT);
ictx->file = filp;
filp->private_data = ictx;
@@ -392,26 +401,46 @@ static struct miscdevice iommu_misc_dev = {
.mode = 0660,
 };
 
+
+static struct miscdevice vfio_misc_dev = {
+   .minor = VFIO_MINOR,
+   .name = "vfio",
+   .fops = _fops,
+   .nodename = "vfio/vfio",
+   .mode = 0666,
+};
+
 static int __init iommufd_init(void)
 {
int ret;
 
ret = misc_register(_misc_dev);
-   if (ret) {
-   pr_err("Failed to register misc device\n");
+   if (ret)
return ret;
-   }
 
+   if (IS_ENABLED(CONFIG_IOMMUFD_VFIO_CONTAINER)) {
+   ret = misc_register(_misc_dev);
+   if (ret)
+   goto err_misc;
+   }
return 0;
+err_misc:
+   misc_deregister(_misc_dev);
+   return ret;
 }
 
 static void __exit iommufd_exit(void)
 {
+   if (IS_ENABLED(CONFIG_IOMMUFD_VFIO_CONTAINER))
+   misc_deregister(_misc_dev);
misc_deregister(_misc_dev);
 }
 
 module_init(iommufd_init);
 module_exit(iommufd_exit);
 
+#if IS_ENABLED(CONFIG_IOMMUFD_VFIO_CONTAINER)
+MODULE_ALIAS_MISCDEV(VFIO_MINOR);
+#endif
 MODULE_DESCRIPTION("I/O Address Space Management for passthrough devices");
 MODULE_LICENSE("GPL");
-- 
2.38.0

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/dg2: Introduce Wa_18018764978

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/dg2: Introduce Wa_18018764978
URL   : https://patchwork.freedesktop.org/series/110131/
State : warning

== Summary ==

Error: dim checkpatch failed
c5d85fb8644b drm/i915/dg2: Introduce Wa_18018764978
-:37: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#37: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:748:
+   if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) ||
+   IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))

total: 0 errors, 0 warnings, 1 checks, 20 lines checked
99f313e60fa1 drm/i915/dg2: Introduce Wa_18019271663

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Fix a build error used with clang compiler

[Dixit, Ashutosh]

On Tue, 25 Oct 2022 07:30:49 -0700, Jani Nikula wrote:
>
> On Tue, 25 Oct 2022, Jani Nikula  wrote:
> > On Tue, 25 Oct 2022, Gwan-gyeong Mun  wrote:
> >> If a non-constant variable is used as the first argument of the FIELD_PREP
> >> macro, a build error occurs when using the clang compiler.
> >>
> >> Fix the following build error used with clang compiler:
> >>
> >> drivers/gpu/drm/i915/i915_hwmon.c:115:16: error: result of comparison of 
> >> constant 18446744073709551615 with expression of type 'typeof 
> >> (_Generic((field_msk), char: (unsigned char)0, unsigned char: (unsigned 
> >> char)0, signed char: (unsigned char)0, unsigned short: (unsigned short)0, 
> >> short: (unsigned short)0, unsigned int: (unsigned int)0, int: (unsigned 
> >> int)0, unsigned long: (unsigned long)0, long: (unsigned long)0, unsigned 
> >> long long: (unsigned long long)0, long long: (unsigned long long)0, 
> >> default: (field_msk)))' (aka 'unsigned int') is always false 
> >> [-Werror,-Wtautological-constant-out-of-range-compare]
> >> bits_to_set = FIELD_PREP(field_msk, nval);
> >>   ^~~
> >> ./include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP'
> >> __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: ");\
> >> ^~~
> >> ./include/linux/bitfield.h:71:53: note: expanded from macro 
> >> '__BF_FIELD_CHECK'
> >> BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
> >> ~~^~~
> >> ./include/linux/build_bug.h:39:58: note: expanded from macro 
> >> 'BUILD_BUG_ON_MSG'
> >> ~^~~
> >> ./include/linux/compiler_types.h:357:22: note: expanded from macro 
> >> 'compiletime_assert'
> >> _compiletime_assert(condition, msg, __compiletime_assert_, 
> >> __COUNTER__)
> >> 
> >> ^~~
> >> ./include/linux/compiler_types.h:345:23: note: expanded from macro 
> >> '_compiletime_assert'
> >> __compiletime_assert(condition, msg, prefix, suffix)
> >> ~^~~
> >> ./include/linux/compiler_types.h:337:9: note: expanded from macro 
> >> '__compiletime_assert'
> >> if (!(condition))   \
> >>
> >> Fixes: 99f55efb7911 ("drm/i915/hwmon: Power PL1 limit and TDP setting")
> >> Cc: Ashutosh Dixit 
> >> Cc: Anshuman Gupta 
> >> Cc: Andi Shyti 
> >> Signed-off-by: Gwan-gyeong Mun 
> >> ---
> >>  drivers/gpu/drm/i915/i915_hwmon.c | 12 +++-
> >>  1 file changed, 3 insertions(+), 9 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c 
> >> b/drivers/gpu/drm/i915/i915_hwmon.c
> >> index 9e9781493025..782a621b1928 100644
> >> --- a/drivers/gpu/drm/i915/i915_hwmon.c
> >> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> >> @@ -101,21 +101,16 @@ hwm_field_read_and_scale(struct hwm_drvdata *ddat, 
> >> i915_reg_t rgadr,
> >>
> >>  static void
> >>  hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
> >> -u32 field_msk, int nshift,
> >> -unsigned int scale_factor, long lval)
> >> +int nshift, unsigned int scale_factor, long lval)
> >>  {
> >>u32 nval;
> >> -  u32 bits_to_clear;
> >> -  u32 bits_to_set;
> >>
> >>/* Computation in 64-bits to avoid overflow. Round to nearest. */
> >>nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor);
> >>
> >> -  bits_to_clear = field_msk;
> >> -  bits_to_set = FIELD_PREP(field_msk, nval);
> >
> > Please just switch to REG_FIELD_PREP() and it should be fine.
>
> Actually, probably not, but please switch to it anyway. ;)

This is what happens with REG_FIELD_PREP(), that is why we went ahead with
FIELD_PREP(). So REG_FIELD_PREP is not an option.

  CC [M]  drivers/gpu/drm/i915/i915_hwmon.o
In file included from ./include/linux/bits.h:22,
 from ./include/linux/bitops.h:6,
 from ./include/linux/hwmon.h:15,
 from drivers/gpu/drm/i915/i915_hwmon.c:6:
drivers/gpu/drm/i915/i915_hwmon.c: In function ‘hwm_field_scale_and_write’:
./include/linux/build_bug.h:16:51: error: negative width in bit-field 
‘’
   16 | #define BUILD_BUG_ON_ZERO(e) ((int)(sizeof(struct { int:(-!!(e)); })))
  |   ^
./drivers/gpu/drm/i915/i915_reg_defs.h:72:16: note: in expansion of macro 
‘BUILD_BUG_ON_ZERO’
   72 |BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + 
\
  |^
drivers/gpu/drm/i915/i915_hwmon.c:115:23: note: in expansion of macro 
‘REG_FIELD_PREP’
  115 | bits_to_set = REG_FIELD_PREP(field_msk, nval);
  |   ^~
./include/linux/build_bug.h:16:51: error: 

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Fix a build error used with clang compiler

[Dixit, Ashutosh]

On Tue, 25 Oct 2022 02:25:06 -0700, Andi Shyti wrote:
>
> Hi Ashutosh,

Hi Andi :)

> > > If a non-constant variable is used as the first argument of the FIELD_PREP
> > > macro, a build error occurs when using the clang compiler.

A "non-constant variable" does not seem to be the cause of the compile
error with clang, see below.

>
> > > drivers/gpu/drm/i915/i915_hwmon.c:115:16: error: result of comparison of 
> > > constant 18446744073709551615 with expression of type 'typeof 
> > > (_Generic((field_msk), char: (unsigned char)0, unsigned char: (unsigned 
> > > char)0, signed char: (unsigned char)0, unsigned short: (unsigned short)0, 
> > > short: (unsigned short)0, unsigned int: (unsigned int)0, int: (unsigned 
> > > int)0, unsigned long: (unsigned long)0, long: (unsigned long)0, unsigned 
> > > long long: (unsigned long long)0, long long: (unsigned long long)0, 
> > > default: (field_msk)))' (aka 'unsigned int') is always false 
> > > [-Werror,-Wtautological-constant-out-of-range-compare]
> >
> > What is 18446744073709551615? You may want to limit the length of this line
> > or checkpatch doesn't complain?
>
> yeah! I am not a clang user, and this must be some ugly error
> output. I don't think it makes sense to break it, though.

18446744073709551615 == ~0ull (see use in __BF_FIELD_CHECK).

>
> > > bits_to_set = FIELD_PREP(field_msk, nval);
> > >   ^~~
> > > ./include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP'
> > > __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: ");\
> > > ^~~
> > > ./include/linux/bitfield.h:71:53: note: expanded from macro 
> > > '__BF_FIELD_CHECK'
> > > BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \

So clang seems to break here at this line in __BF_FIELD_CHECK (note ~0ull
also occurs here):

BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
 __bf_cast_unsigned(_reg, ~0ull),   \
 _pfx "type of reg too small for mask"); \

So it goes through previous checks including the "mask is not constant"
check. As Nick Desaulniers mentions "__builtin_constant_p is evaluated
after most optimizations have run" so by that time both compilers (gcc and
clang) have figured out that even though _mask is coming in as function
argument it is really the constant below:

#define   PKG_PWR_LIM_1 REG_GENMASK(14, 0)

But it is not clear why clang chokes on this "type of reg too small for
mask" check (and gcc doesn't) since everything is u32.

It is for this reason I want someone from llvm to chime in.

> > > ~~^~~
> > > ./include/linux/build_bug.h:39:58: note: expanded from macro 
> > > 'BUILD_BUG_ON_MSG'
> > > ~^~~
> > > ./include/linux/compiler_types.h:357:22: note: expanded from macro 
> > > 'compiletime_assert'
> > > _compiletime_assert(condition, msg, __compiletime_assert_, 
> > > __COUNTER__)
> > > 
> > > ^~~
> > > ./include/linux/compiler_types.h:345:23: note: expanded from macro 
> > > '_compiletime_assert'
> > > __compiletime_assert(condition, msg, prefix, suffix)
> > > ~^~~
> > > ./include/linux/compiler_types.h:337:9: note: expanded from macro 
> > > '__compiletime_assert'
> > > if (!(condition))   \
> > >
> > > Fixes: 99f55efb7911 ("drm/i915/hwmon: Power PL1 limit and TDP setting")
> > > Cc: Ashutosh Dixit 
> > > Cc: Anshuman Gupta 
> > > Cc: Andi Shyti 
> > > Signed-off-by: Gwan-gyeong Mun 
> > > ---
> > >  drivers/gpu/drm/i915/i915_hwmon.c | 12 +++-
> > >  1 file changed, 3 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c 
> > > b/drivers/gpu/drm/i915/i915_hwmon.c
> > > index 9e9781493025..782a621b1928 100644
> > > --- a/drivers/gpu/drm/i915/i915_hwmon.c
> > > +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> > > @@ -101,21 +101,16 @@ hwm_field_read_and_scale(struct hwm_drvdata *ddat, 
> > > i915_reg_t rgadr,
> > >
> > >  static void
> > >  hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
> > > -   u32 field_msk, int nshift,
> > > -   unsigned int scale_factor, long lval)
> > > +   int nshift, unsigned int scale_factor, long lval)
> > >  {
> > >   u32 nval;
> > > - u32 bits_to_clear;
> > > - u32 bits_to_set;
> > >
> > >   /* Computation in 64-bits to avoid overflow. Round to nearest. */
> > >   nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor);
> > >
> > > - bits_to_clear = field_msk;
> > > - bits_to_set = FIELD_PREP(field_msk, nval);
> > > -
> > >   

[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915/uapi: expose GTT alignment"

[Patchwork]

== Series Details ==

Series: Revert "drm/i915/uapi: expose GTT alignment"
URL   : https://patchwork.freedesktop.org/series/110041/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12284 -> Patchwork_110041v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html

Participating hosts (41 -> 42)
--

  Additional (4): fi-kbl-soraka fi-hsw-4770 fi-icl-u2 bat-atsm-1 
  Missing(3): fi-ctg-p8600 fi-bdw-samus fi-tgl-dsi 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110041v1:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_parallel@engines@contexts:
- {fi-ehl-2}: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-ehl-2/igt@gem_exec_parallel@engi...@contexts.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-ehl-2/igt@gem_exec_parallel@engi...@contexts.html

  
Known issues


  Here are the changes found in Patchwork_110041v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271]) +9 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_exec_gttf...@basic.html
- fi-pnv-d510:[PASS][4] -> [FAIL][5] ([i915#7229])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][6] ([i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [PASS][10] -> [INCOMPLETE][11] ([i915#7056])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271]) +9 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html

  * igt@i915_module_load@load:
- fi-kbl-soraka:  NOTRUN -> [DMESG-WARN][13] ([i915#1982])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_module_l...@load.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#3012])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][15] ([i915#1886])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][16] ([i915#4785])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@hugepages:
- fi-glk-j4005:   [PASS][17] -> [DMESG-FAIL][18] ([i915#7311])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-glk-j4005/igt@i915_selftest@l...@hugepages.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-glk-j4005/igt@i915_selftest@l...@hugepages.html
- fi-rkl-guc: [PASS][19] -> [DMESG-FAIL][20] ([i915#7311])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-rkl-guc/igt@i915_selftest@l...@hugepages.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-rkl-guc/igt@i915_selftest@l...@hugepages.html
- fi-icl-u2:  NOTRUN -> [DMESG-FAIL][21] ([i915#7311])
   

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode

[Patchwork]

== Series Details ==

Series: drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode
URL   : https://patchwork.freedesktop.org/series/110130/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12294 -> Patchwork_110130v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/index.html

Participating hosts (40 -> 37)
--

  Additional (1): fi-skl-guc 
  Missing(4): fi-ctg-p8600 fi-hsw-4770 fi-bdw-samus fi-pnv-d510 

Known issues


  Here are the changes found in Patchwork_110130v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-skl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/fi-skl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#111827])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/fi-skl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-skl-guc: NOTRUN -> [SKIP][4] ([fdo#109271]) +10 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/fi-skl-guc/igt@kms_setm...@basic-clone-single-crtc.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rpls-1}:   [DMESG-WARN][5] ([i915#6687]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [INCOMPLETE][7] ([i915#3303] / [i915#4785]) -> 
[PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@slpc:
- {bat-rpls-1}:   [DMESG-FAIL][9] ([i915#6367]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-1/igt@i915_selftest@l...@slpc.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [FAIL][11] ([i915#6298]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687


Build changes
-

  * Linux: CI_DRM_12294 -> Patchwork_110130v1

  CI-20190529: 20190529
  CI_DRM_12294: fca30d6149441ff19df784c0554b8c20a29c7f53 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7026: ce0f97e7e0aa54c40049a8365b3d61773c92e588 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_110130v1: 

[Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function

[Anusha Srivatsa]

No functional change. Introduce dg2_cdclk_squash_program and
move squash_ctl register programming bits to this.

v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)

Cc: Jani Nikula 
Cc: Balasubramani Vivekanandan 
Cc: Ville Syrjälä 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Balasubramani Vivekanandan 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +-
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3893779e0c23..e21cd0fbe29a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1705,6 +1705,18 @@ static void bxt_cdclk_pll_update(struct drm_i915_private 
*i915, int vco)
 
 }
 
+static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
+u16 waveform)
+{
+   u32 squash_ctl = 0;
+
+   if (waveform)
+   squash_ctl = CDCLK_SQUASH_ENABLE |
+CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
+
+   intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
+}
+
 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
  const struct intel_cdclk_config *cdclk_config,
  enum pipe pipe)
@@ -1752,15 +1764,8 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
else
clock = cdclk;
 
-   if (HAS_CDCLK_SQUASH(dev_priv)) {
-   u32 squash_ctl = 0;
-
-   if (waveform)
-   squash_ctl = CDCLK_SQUASH_ENABLE |
-   CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
-
-   intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
-   }
+   if (HAS_CDCLK_SQUASH(dev_priv))
+   dg2_cdclk_squash_program(dev_priv, waveform);
 
val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
-- 
2.25.1

[Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro

[Anusha Srivatsa]

Driver had discrepancy in how cdclk squash and crawl support
were checked. Like crawl, add squash as a 1 bit feature flag
to the display section of DG2.

Cc: Balasubramani Vivekanandan 
Cc: Ville Syrjälä 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Balasubramani Vivekanandan 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +--
 drivers/gpu/drm/i915/i915_drv.h|  1 +
 drivers/gpu/drm/i915/i915_pci.c|  1 +
 drivers/gpu/drm/i915/intel_device_info.h   |  1 +
 4 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0f5add2fc51b..45babbc6290f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1220,11 +1220,6 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private 
*dev_priv)
skl_set_cdclk(dev_priv, _config, INVALID_PIPE);
 }
 
-static bool has_cdclk_squash(struct drm_i915_private *i915)
-{
-   return IS_DG2(i915);
-}
-
 struct intel_cdclk_vals {
u32 cdclk;
u16 refclk;
@@ -1520,7 +1515,7 @@ static void bxt_get_cdclk(struct drm_i915_private 
*dev_priv,
return;
}
 
-   if (has_cdclk_squash(dev_priv))
+   if (HAS_CDCLK_SQUASH(dev_priv))
squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
 
if (squash_ctl & CDCLK_SQUASH_ENABLE) {
@@ -1747,7 +1742,7 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
else
clock = cdclk;
 
-   if (has_cdclk_squash(dev_priv)) {
+   if (HAS_CDCLK_SQUASH(dev_priv)) {
u32 squash_ctl = 0;
 
if (waveform)
@@ -1845,7 +1840,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private 
*dev_priv)
expected = skl_cdclk_decimal(cdclk);
 
/* Figure out what CD2X divider we should be using for this cdclk */
-   if (has_cdclk_squash(dev_priv))
+   if (HAS_CDCLK_SQUASH(dev_priv))
clock = dev_priv->display.cdclk.hw.vco / 2;
else
clock = dev_priv->display.cdclk.hw.cdclk;
@@ -1976,7 +1971,7 @@ static bool intel_cdclk_can_squash(struct 
drm_i915_private *dev_priv,
 * the moment all platforms with squasher use a fixed cd2x
 * divider.
 */
-   if (!has_cdclk_squash(dev_priv))
+   if (!HAS_CDCLK_SQUASH(dev_priv))
return false;
 
return a->cdclk != b->cdclk &&
@@ -2028,7 +2023,7 @@ static bool intel_cdclk_can_cd2x_update(struct 
drm_i915_private *dev_priv,
 * the moment all platforms with squasher use a fixed cd2x
 * divider.
 */
-   if (has_cdclk_squash(dev_priv))
+   if (HAS_CDCLK_SQUASH(dev_priv))
return false;
 
return a->cdclk != b->cdclk &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d7b8eb9d4117..db51050e3ba2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -869,6 +869,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)  (DISPLAY_VER(dev_priv) >= 9 || 
IS_BROADWELL(dev_priv))
 
 #define HAS_CDCLK_CRAWL(dev_priv)   
(INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
+#define HAS_CDCLK_SQUASH(dev_priv)  
(INTEL_INFO(dev_priv)->display.has_cdclk_squash)
 #define HAS_DDI(dev_priv)   (INTEL_INFO(dev_priv)->display.has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) 
(INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 #define HAS_PSR(dev_priv)   (INTEL_INFO(dev_priv)->display.has_psr)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 19bf5ef6a20d..a88e1439a426 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1064,6 +1064,7 @@ static const struct intel_device_info xehpsdv_info = {
.has_guc_deprivilege = 1, \
.has_heci_pxp = 1, \
.has_media_ratio_mode = 1, \
+   .display.has_cdclk_squash = 1, \
.__runtime.platform_engine_mask = \
BIT(RCS0) | BIT(BCS0) | \
BIT(VECS0) | BIT(VECS1) | \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index cdf78728dcad..67d8759c802c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -180,6 +180,7 @@ enum intel_ppgtt_type {
/* Keep in alphabetical order */ \
func(cursor_needs_physical); \
func(has_cdclk_crawl); \
+   func(has_cdclk_squash); \
func(has_ddi); \
func(has_dp_mst); \
func(has_dsb); \
-- 
2.25.1

[Intel-gfx] [PATCH 1/4] drm/i915/display: Change terminology for cdclk actions

[Anusha Srivatsa]

No functional changes. Changing terminology in some
print statements. s/has_cdclk_squasher/has_cdclk_squash,
s/crawler/crawl and s/squasher/squash.

Cc: Balasubramani Vivekanandan 
Cc: Ville Syrjälä 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Balasubramani Vivekanandan 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ad401357ab66..0f5add2fc51b 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1220,7 +1220,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private 
*dev_priv)
skl_set_cdclk(dev_priv, _config, INVALID_PIPE);
 }
 
-static bool has_cdclk_squasher(struct drm_i915_private *i915)
+static bool has_cdclk_squash(struct drm_i915_private *i915)
 {
return IS_DG2(i915);
 }
@@ -1520,7 +1520,7 @@ static void bxt_get_cdclk(struct drm_i915_private 
*dev_priv,
return;
}
 
-   if (has_cdclk_squasher(dev_priv))
+   if (has_cdclk_squash(dev_priv))
squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
 
if (squash_ctl & CDCLK_SQUASH_ENABLE) {
@@ -1747,7 +1747,7 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
else
clock = cdclk;
 
-   if (has_cdclk_squasher(dev_priv)) {
+   if (has_cdclk_squash(dev_priv)) {
u32 squash_ctl = 0;
 
if (waveform)
@@ -1845,7 +1845,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private 
*dev_priv)
expected = skl_cdclk_decimal(cdclk);
 
/* Figure out what CD2X divider we should be using for this cdclk */
-   if (has_cdclk_squasher(dev_priv))
+   if (has_cdclk_squash(dev_priv))
clock = dev_priv->display.cdclk.hw.vco / 2;
else
clock = dev_priv->display.cdclk.hw.cdclk;
@@ -1976,7 +1976,7 @@ static bool intel_cdclk_can_squash(struct 
drm_i915_private *dev_priv,
 * the moment all platforms with squasher use a fixed cd2x
 * divider.
 */
-   if (!has_cdclk_squasher(dev_priv))
+   if (!has_cdclk_squash(dev_priv))
return false;
 
return a->cdclk != b->cdclk &&
@@ -2028,7 +2028,7 @@ static bool intel_cdclk_can_cd2x_update(struct 
drm_i915_private *dev_priv,
 * the moment all platforms with squasher use a fixed cd2x
 * divider.
 */
-   if (has_cdclk_squasher(dev_priv))
+   if (has_cdclk_squash(dev_priv))
return false;
 
return a->cdclk != b->cdclk &&
@@ -2754,12 +2754,12 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state 
*state)
   _cdclk_state->actual,
   _cdclk_state->actual)) {
drm_dbg_kms(_priv->drm,
-   "Can change cdclk via squasher\n");
+   "Can change cdclk via squashing\n");
} else if (intel_cdclk_can_crawl(dev_priv,
 _cdclk_state->actual,
 _cdclk_state->actual)) {
drm_dbg_kms(_priv->drm,
-   "Can change cdclk via crawl\n");
+   "Can change cdclk via crawling\n");
} else if (pipe != INVALID_PIPE) {
new_cdclk_state->pipe = pipe;
 
-- 
2.25.1

[Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk()

[Anusha Srivatsa]

No functional change. Moving segments out to simplify
bxt_set_cdlck()

v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani)

Cc: Jani Nikula 
Cc: Balasubramani Vivekanandan 
Cc: Ville Syrjälä 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Balasubramani Vivekanandan 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++
 1 file changed, 25 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 45babbc6290f..3893779e0c23 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1684,6 +1684,27 @@ static u32 cdclk_squash_waveform(struct drm_i915_private 
*dev_priv,
return 0x;
 }
 
+static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco)
+{
+   if (i915->display.cdclk.hw.vco != 0 &&
+   i915->display.cdclk.hw.vco != vco)
+   icl_cdclk_pll_disable(i915);
+
+   if (i915->display.cdclk.hw.vco != vco)
+   icl_cdclk_pll_enable(i915, vco);
+}
+
+static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
+{
+   if (i915->display.cdclk.hw.vco != 0 &&
+   i915->display.cdclk.hw.vco != vco)
+   bxt_de_pll_disable(i915);
+
+   if (i915->display.cdclk.hw.vco != vco)
+   bxt_de_pll_enable(i915, vco);
+
+}
+
 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
  const struct intel_cdclk_config *cdclk_config,
  enum pipe pipe)
@@ -1719,21 +1740,10 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && 
vco > 0) {
if (dev_priv->display.cdclk.hw.vco != vco)
adlp_cdclk_pll_crawl(dev_priv, vco);
-   } else if (DISPLAY_VER(dev_priv) >= 11) {
-   if (dev_priv->display.cdclk.hw.vco != 0 &&
-   dev_priv->display.cdclk.hw.vco != vco)
-   icl_cdclk_pll_disable(dev_priv);
-
-   if (dev_priv->display.cdclk.hw.vco != vco)
-   icl_cdclk_pll_enable(dev_priv, vco);
-   } else {
-   if (dev_priv->display.cdclk.hw.vco != 0 &&
-   dev_priv->display.cdclk.hw.vco != vco)
-   bxt_de_pll_disable(dev_priv);
-
-   if (dev_priv->display.cdclk.hw.vco != vco)
-   bxt_de_pll_enable(dev_priv, vco);
-   }
+   } else if (DISPLAY_VER(dev_priv) >= 11)
+   icl_cdclk_pll_update(dev_priv, vco);
+   else
+   bxt_cdclk_pll_update(dev_priv, vco);
 
waveform = cdclk_squash_waveform(dev_priv, cdclk);
 
-- 
2.25.1

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/edid: EDID override refactoring and fixes (rev3)

[Patchwork]

== Series Details ==

Series: drm/edid: EDID override refactoring and fixes (rev3)
URL   : https://patchwork.freedesktop.org/series/109579/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109579v3_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109579v3_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_ctx_shared@q-smoketest@vcs0:
- {shard-rkl}:NOTRUN -> [DMESG-WARN][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-rkl-5/igt@gem_ctx_shared@q-smoket...@vcs0.html

  * igt@gem_exec_whisper@basic-contexts-priority:
- {shard-rkl}:NOTRUN -> [FAIL][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-rkl-5/igt@gem_exec_whis...@basic-contexts-priority.html

  * igt@sysfs_timeslice_duration@idempotent@vcs0:
- {shard-dg1}:NOTRUN -> [FAIL][3] +9 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-dg1-17/igt@sysfs_timeslice_duration@idempot...@vcs0.html

  
Known issues


  Here are the changes found in Patchwork_109579v3_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#6268])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb2/igt@gem_ctx_e...@basic-nohangcheck.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-tglb2/igt@gem_ctx_e...@basic-nohangcheck.html

  * igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][6] -> [SKIP][7] ([i915#4525]) +1 similar issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb1/igt@gem_exec_balan...@parallel-out-fence.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-iclb3/igt@gem_exec_balan...@parallel-out-fence.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-skl7/igt@gem_lmem_swapp...@parallel-random.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl:  NOTRUN -> [SKIP][10] ([fdo#109271]) +47 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-skl7/igt@kms_big...@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_color_chamelium@ctm-limited-range:
- shard-skl:  NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +2 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-skl7/igt@kms_color_chamel...@ctm-limited-range.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl:  [PASS][12] -> [FAIL][13] ([i915#79])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-skl7/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-apl:  [PASS][14] -> [DMESG-WARN][15] ([i915#180])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl3/igt@kms_flip@flip-vs-susp...@c-dp1.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-apl1/igt@kms_flip@flip-vs-susp...@c-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-skl:  [PASS][16] -> [FAIL][17] ([i915#2122])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@kms_flip@plain-flip-fb-recre...@c-edp1.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-skl7/igt@kms_flip@plain-flip-fb-recre...@c-edp1.html

  * 
igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#2587] / [i915#2672]) +3 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-iclb6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscal...@pipe-a-valid-mode.html

  * 
igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#2672]) +4 similar issues
   [19]: 

[Intel-gfx] [PATCH 01/10] vfio: Move vfio_device driver open/close code to a function

[Jason Gunthorpe]

This error unwind is getting complicated. Move all the code into two
pair'd function. The functions should be called when the open_count == 1
after incrementing/before decrementing.

Signed-off-by: Jason Gunthorpe 
---
 drivers/vfio/vfio_main.c | 95 ++--
 1 file changed, 53 insertions(+), 42 deletions(-)

diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index 2d168793d4e1ce..d043383fc3ba2b 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -734,6 +734,51 @@ bool vfio_assert_device_open(struct vfio_device *device)
return !WARN_ON_ONCE(!READ_ONCE(device->open_count));
 }
 
+static int vfio_device_first_open(struct vfio_device *device)
+{
+   int ret;
+
+   lockdep_assert_held(>dev_set->lock);
+
+   if (!try_module_get(device->dev->driver->owner))
+   return -ENODEV;
+
+   /*
+* Here we pass the KVM pointer with the group under the read lock.  If
+* the device driver will use it, it must obtain a reference and release
+* it during close_device.
+*/
+   mutex_lock(>group->group_lock);
+   device->kvm = device->group->kvm;
+   if (device->ops->open_device) {
+   ret = device->ops->open_device(device);
+   if (ret)
+   goto err_module_put;
+   }
+   vfio_device_container_register(device);
+   mutex_unlock(>group->group_lock);
+   return 0;
+
+err_module_put:
+   device->kvm = NULL;
+   mutex_unlock(>group->group_lock);
+   module_put(device->dev->driver->owner);
+   return ret;
+}
+
+static void vfio_device_last_close(struct vfio_device *device)
+{
+   lockdep_assert_held(>dev_set->lock);
+
+   mutex_lock(>group->group_lock);
+   vfio_device_container_unregister(device);
+   if (device->ops->close_device)
+   device->ops->close_device(device);
+   device->kvm = NULL;
+   mutex_unlock(>group->group_lock);
+   module_put(device->dev->driver->owner);
+}
+
 static struct file *vfio_device_open(struct vfio_device *device)
 {
struct file *filep;
@@ -745,29 +790,12 @@ static struct file *vfio_device_open(struct vfio_device 
*device)
if (ret)
return ERR_PTR(ret);
 
-   if (!try_module_get(device->dev->driver->owner)) {
-   ret = -ENODEV;
-   goto err_unassign_container;
-   }
-
mutex_lock(>dev_set->lock);
device->open_count++;
if (device->open_count == 1) {
-   /*
-* Here we pass the KVM pointer with the group under the read
-* lock.  If the device driver will use it, it must obtain a
-* reference and release it during close_device.
-*/
-   mutex_lock(>group->group_lock);
-   device->kvm = device->group->kvm;
-
-   if (device->ops->open_device) {
-   ret = device->ops->open_device(device);
-   if (ret)
-   goto err_undo_count;
-   }
-   vfio_device_container_register(device);
-   mutex_unlock(>group->group_lock);
+   ret = vfio_device_first_open(device);
+   if (ret)
+   goto err_unassign_container;
}
mutex_unlock(>dev_set->lock);
 
@@ -800,20 +828,11 @@ static struct file *vfio_device_open(struct vfio_device 
*device)
 
 err_close_device:
mutex_lock(>dev_set->lock);
-   mutex_lock(>group->group_lock);
-   if (device->open_count == 1 && device->ops->close_device) {
-   device->ops->close_device(device);
-
-   vfio_device_container_unregister(device);
-   }
-err_undo_count:
-   mutex_unlock(>group->group_lock);
+   if (device->open_count == 1)
+   vfio_device_last_close(device);
+err_unassign_container:
device->open_count--;
-   if (device->open_count == 0 && device->kvm)
-   device->kvm = NULL;
mutex_unlock(>dev_set->lock);
-   module_put(device->dev->driver->owner);
-err_unassign_container:
vfio_device_unassign_container(device);
return ERR_PTR(ret);
 }
@@ -1016,19 +1035,11 @@ static int vfio_device_fops_release(struct inode 
*inode, struct file *filep)
 
mutex_lock(>dev_set->lock);
vfio_assert_device_open(device);
-   mutex_lock(>group->group_lock);
-   if (device->open_count == 1 && device->ops->close_device)
-   device->ops->close_device(device);
-
-   vfio_device_container_unregister(device);
-   mutex_unlock(>group->group_lock);
+   if (device->open_count == 1)
+   vfio_device_last_close(device);
device->open_count--;
-   if (device->open_count == 0)
-   device->kvm = NULL;
mutex_unlock(>dev_set->lock);
 
-   module_put(device->dev->driver->owner);
-

[Intel-gfx] [PATCH 00/10] Connect VFIO to IOMMUFD

[Jason Gunthorpe]

This series provides an alternative container layer for VFIO implemented
using iommufd. This is optional, if CONFIG_IOMMUFD is not set then it will
not be compiled in.

At this point iommufd can be injected by passing in a iommfd FD to
VFIO_GROUP_SET_CONTAINER which will use the VFIO compat layer in iommufd
to obtain the compat IOAS and then connect up all the VFIO drivers as
appropriate.

This is temporary stopping point, a following series will provide a way to
directly open a VFIO device FD and directly connect it to IOMMUFD using
native ioctls that can expose the IOMMUFD features like hwpt, future
vPASID and dynamic attachment.

This series, in compat mode, has passed all the qemu tests we have
available, including the test suites for the Intel GVT mdev. Aside from
the temporary limitation with P2P memory this is belived to be fully
compatible with VFIO.

This is on github: https://github.com/jgunthorpe/linux/commits/vfio_iommufd

It requires the iommufd series:

https://lore.kernel.org/r/0-v3-402a7d6459de+24b-iommufd_...@nvidia.com

Jason Gunthorpe (10):
  vfio: Move vfio_device driver open/close code to a function
  vfio: Move vfio_device_assign_container() into
vfio_device_first_open()
  vfio: Rename vfio_device_assign/unassign_container()
  vfio: Move storage of allow_unsafe_interrupts to vfio_main.c
  vfio: Use IOMMU_CAP_ENFORCE_CACHE_COHERENCY for
vfio_file_enforced_coherent()
  vfio-iommufd: Allow iommufd to be used in place of a container fd
  vfio-iommufd: Support iommufd for physical VFIO devices
  vfio-iommufd: Support iommufd for emulated VFIO devices
  vfio: Make vfio_container optionally compiled
  iommufd: Allow iommufd to supply /dev/vfio/vfio

 drivers/gpu/drm/i915/gvt/kvmgt.c  |   3 +
 drivers/iommu/iommufd/Kconfig |  12 +
 drivers/iommu/iommufd/main.c  |  35 +-
 drivers/s390/cio/vfio_ccw_ops.c   |   3 +
 drivers/s390/crypto/vfio_ap_ops.c |   3 +
 drivers/vfio/Kconfig  |  38 ++-
 drivers/vfio/Makefile |   5 +-
 drivers/vfio/container.c  | 136 ++--
 drivers/vfio/fsl-mc/vfio_fsl_mc.c |   3 +
 drivers/vfio/iommufd.c| 161 +
 .../vfio/pci/hisilicon/hisi_acc_vfio_pci.c|   6 +
 drivers/vfio/pci/mlx5/main.c  |   3 +
 drivers/vfio/pci/vfio_pci.c   |   3 +
 drivers/vfio/platform/vfio_amba.c |   3 +
 drivers/vfio/platform/vfio_platform.c |   3 +
 drivers/vfio/vfio.h   | 100 +-
 drivers/vfio/vfio_iommu_type1.c   |   5 +-
 drivers/vfio/vfio_main.c  | 318 ++
 include/linux/vfio.h  |  39 +++
 19 files changed, 681 insertions(+), 198 deletions(-)
 create mode 100644 drivers/vfio/iommufd.c


base-commit: 3bec937e94942a6aee8854be1c1f5cc2b92d15e2
-- 
2.38.0

[Intel-gfx] [PATCH 04/10] vfio: Move storage of allow_unsafe_interrupts to vfio_main.c

[Jason Gunthorpe]

This legacy module knob has become uAPI, when set on the vfio_iommu_type1
it disables some security protections in the iommu drivers. Move the
storage for this knob to vfio_main.c so that iommufd can access it too.

Signed-off-by: Jason Gunthorpe 
---
 drivers/vfio/vfio.h | 2 ++
 drivers/vfio/vfio_iommu_type1.c | 5 ++---
 drivers/vfio/vfio_main.c| 3 +++
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
index f95f4925b83bbd..54e5a8e0834ccb 100644
--- a/drivers/vfio/vfio.h
+++ b/drivers/vfio/vfio.h
@@ -130,4 +130,6 @@ extern bool vfio_noiommu __read_mostly;
 enum { vfio_noiommu = false };
 #endif
 
+extern bool vfio_allow_unsafe_interrupts;
+
 #endif
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index 23c24fe98c00d4..186e33a006d314 100644
--- a/drivers/vfio/vfio_iommu_type1.c
+++ b/drivers/vfio/vfio_iommu_type1.c
@@ -44,9 +44,8 @@
 #define DRIVER_AUTHOR   "Alex Williamson "
 #define DRIVER_DESC "Type1 IOMMU driver for VFIO"
 
-static bool allow_unsafe_interrupts;
 module_param_named(allow_unsafe_interrupts,
-  allow_unsafe_interrupts, bool, S_IRUGO | S_IWUSR);
+  vfio_allow_unsafe_interrupts, bool, S_IRUGO | S_IWUSR);
 MODULE_PARM_DESC(allow_unsafe_interrupts,
 "Enable VFIO IOMMU support for on platforms without interrupt 
remapping support.");
 
@@ -2282,7 +2281,7 @@ static int vfio_iommu_type1_attach_group(void *iommu_data,
iommu_group_for_each_dev(iommu_group, (void 
*)IOMMU_CAP_INTR_REMAP,
 vfio_iommu_device_capable);
 
-   if (!allow_unsafe_interrupts && !msi_remap) {
+   if (!vfio_allow_unsafe_interrupts && !msi_remap) {
pr_warn("%s: No interrupt remapping support.  Use the module 
param \"allow_unsafe_interrupts\" to enable VFIO IOMMU support on this 
platform\n",
   __func__);
ret = -EPERM;
diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index 8d809ecd982b39..1e414b2c48a511 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -51,6 +51,9 @@ static struct vfio {
struct ida  device_ida;
 } vfio;
 
+bool vfio_allow_unsafe_interrupts;
+EXPORT_SYMBOL_GPL(vfio_allow_unsafe_interrupts);
+
 static DEFINE_XARRAY(vfio_device_set_xa);
 static const struct file_operations vfio_group_fops;
 
-- 
2.38.0

[Intel-gfx] [PATCH 02/10] vfio: Move vfio_device_assign_container() into vfio_device_first_open()

[Jason Gunthorpe]

The only thing this function does is assert the group has an assigned
container and incrs refcounts.

The overall model we have is that once a conatiner_users refcount is
incremented it cannot be de-assigned from the group -
vfio_group_ioctl_unset_container() will fail and the group FD cannot be
closed.

Thus we do not need to check this on evey device FD open, just the
first. Reorganize the code so that only the first open and last close
manages the container.

Signed-off-by: Jason Gunthorpe 
---
 drivers/vfio/container.c |  4 ++--
 drivers/vfio/vfio_main.c | 18 --
 2 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/drivers/vfio/container.c b/drivers/vfio/container.c
index d74164abbf401d..dd79a66ec62cad 100644
--- a/drivers/vfio/container.c
+++ b/drivers/vfio/container.c
@@ -531,11 +531,11 @@ int vfio_device_assign_container(struct vfio_device 
*device)
 
 void vfio_device_unassign_container(struct vfio_device *device)
 {
-   mutex_lock(>group->group_lock);
+   lockdep_assert_held_write(>group->group_lock);
+
WARN_ON(device->group->container_users <= 1);
device->group->container_users--;
fput(device->group->opened_file);
-   mutex_unlock(>group->group_lock);
 }
 
 /*
diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index d043383fc3ba2b..204443ba3b3cd9 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -749,16 +749,22 @@ static int vfio_device_first_open(struct vfio_device 
*device)
 * it during close_device.
 */
mutex_lock(>group->group_lock);
+   ret = vfio_device_assign_container(device);
+   if (ret)
+   goto err_module_put;
+
device->kvm = device->group->kvm;
if (device->ops->open_device) {
ret = device->ops->open_device(device);
if (ret)
-   goto err_module_put;
+   goto err_container;
}
vfio_device_container_register(device);
mutex_unlock(>group->group_lock);
return 0;
 
+err_container:
+   vfio_device_unassign_container(device);
 err_module_put:
device->kvm = NULL;
mutex_unlock(>group->group_lock);
@@ -775,6 +781,7 @@ static void vfio_device_last_close(struct vfio_device 
*device)
if (device->ops->close_device)
device->ops->close_device(device);
device->kvm = NULL;
+   vfio_device_unassign_container(device);
mutex_unlock(>group->group_lock);
module_put(device->dev->driver->owner);
 }
@@ -784,12 +791,6 @@ static struct file *vfio_device_open(struct vfio_device 
*device)
struct file *filep;
int ret;
 
-   mutex_lock(>group->group_lock);
-   ret = vfio_device_assign_container(device);
-   mutex_unlock(>group->group_lock);
-   if (ret)
-   return ERR_PTR(ret);
-
mutex_lock(>dev_set->lock);
device->open_count++;
if (device->open_count == 1) {
@@ -833,7 +834,6 @@ static struct file *vfio_device_open(struct vfio_device 
*device)
 err_unassign_container:
device->open_count--;
mutex_unlock(>dev_set->lock);
-   vfio_device_unassign_container(device);
return ERR_PTR(ret);
 }
 
@@ -1040,8 +1040,6 @@ static int vfio_device_fops_release(struct inode *inode, 
struct file *filep)
device->open_count--;
mutex_unlock(>dev_set->lock);
 
-   vfio_device_unassign_container(device);
-
vfio_device_put_registration(device);
 
return 0;
-- 
2.38.0

[Intel-gfx] [PATCH 03/10] vfio: Rename vfio_device_assign/unassign_container()

[Jason Gunthorpe]

These functions don't really assign anything anymore, they just increment
some refcounts and do a sanity check. Call them
vfio_group_[un]use_container()

Signed-off-by: Jason Gunthorpe 
---
 drivers/vfio/container.c | 14 ++
 drivers/vfio/vfio.h  |  4 ++--
 drivers/vfio/vfio_main.c |  6 +++---
 3 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/vfio/container.c b/drivers/vfio/container.c
index dd79a66ec62cad..499777930b08fa 100644
--- a/drivers/vfio/container.c
+++ b/drivers/vfio/container.c
@@ -511,10 +511,8 @@ void vfio_group_detach_container(struct vfio_group *group)
vfio_container_put(container);
 }
 
-int vfio_device_assign_container(struct vfio_device *device)
+int vfio_group_use_container(struct vfio_group *group)
 {
-   struct vfio_group *group = device->group;
-
lockdep_assert_held(>group_lock);
 
if (!group->container || !group->container->iommu_driver ||
@@ -529,13 +527,13 @@ int vfio_device_assign_container(struct vfio_device 
*device)
return 0;
 }
 
-void vfio_device_unassign_container(struct vfio_device *device)
+void vfio_group_unuse_container(struct vfio_group *group)
 {
-   lockdep_assert_held_write(>group->group_lock);
+   lockdep_assert_held(>group_lock);
 
-   WARN_ON(device->group->container_users <= 1);
-   device->group->container_users--;
-   fput(device->group->opened_file);
+   WARN_ON(group->container_users <= 1);
+   group->container_users--;
+   fput(group->opened_file);
 }
 
 /*
diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
index bcad54bbab08c4..f95f4925b83bbd 100644
--- a/drivers/vfio/vfio.h
+++ b/drivers/vfio/vfio.h
@@ -112,8 +112,8 @@ void vfio_unregister_iommu_driver(const struct 
vfio_iommu_driver_ops *ops);
 bool vfio_assert_device_open(struct vfio_device *device);
 
 struct vfio_container *vfio_container_from_file(struct file *filep);
-int vfio_device_assign_container(struct vfio_device *device);
-void vfio_device_unassign_container(struct vfio_device *device);
+int vfio_group_use_container(struct vfio_group *group);
+void vfio_group_unuse_container(struct vfio_group *group);
 int vfio_container_attach_group(struct vfio_container *container,
struct vfio_group *group);
 void vfio_group_detach_container(struct vfio_group *group);
diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index 204443ba3b3cd9..8d809ecd982b39 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -749,7 +749,7 @@ static int vfio_device_first_open(struct vfio_device 
*device)
 * it during close_device.
 */
mutex_lock(>group->group_lock);
-   ret = vfio_device_assign_container(device);
+   ret = vfio_group_use_container(device->group);
if (ret)
goto err_module_put;
 
@@ -764,7 +764,7 @@ static int vfio_device_first_open(struct vfio_device 
*device)
return 0;
 
 err_container:
-   vfio_device_unassign_container(device);
+   vfio_group_unuse_container(device->group);
 err_module_put:
device->kvm = NULL;
mutex_unlock(>group->group_lock);
@@ -781,7 +781,7 @@ static void vfio_device_last_close(struct vfio_device 
*device)
if (device->ops->close_device)
device->ops->close_device(device);
device->kvm = NULL;
-   vfio_device_unassign_container(device);
+   vfio_group_unuse_container(device->group);
mutex_unlock(>group->group_lock);
module_put(device->dev->driver->owner);
 }
-- 
2.38.0

[Intel-gfx] [PATCH 05/10] vfio: Use IOMMU_CAP_ENFORCE_CACHE_COHERENCY for vfio_file_enforced_coherent()

[Jason Gunthorpe]

iommufd doesn't establish the iommu_domains until after the device FD is
opened, even if the container has been set. This design is part of moving
away from the group centric iommu APIs.

This is fine, except that the normal sequence of establishing the kvm
wbindv won't work:

   group = open("/dev/vfio/XX")
   ioctl(group, VFIO_GROUP_SET_CONTAINER)
   ioctl(kvm, KVM_DEV_VFIO_GROUP_ADD)
   ioctl(group, VFIO_GROUP_GET_DEVICE_FD)

As the domains don't start existing until GET_DEVICE_FD. Further,
GET_DEVICE_FD requires that KVM_DEV_VFIO_GROUP_ADD already be done as that
is what sets the group->kvm and thus device->kvm for the driver to use
during open.

Now that we have device centric cap ops and the new
IOMMU_CAP_ENFORCE_CACHE_COHERENCY we know what the iommu_domain will be
capable of without having to create it. Use this to compute
vfio_file_enforced_coherent() and resolve the ordering problems.

Signed-off-by: Jason Gunthorpe 
---
 drivers/vfio/container.c |  5 +++--
 drivers/vfio/vfio.h  |  2 --
 drivers/vfio/vfio_main.c | 27 ++-
 3 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/vfio/container.c b/drivers/vfio/container.c
index 499777930b08fa..d97747dfb05d02 100644
--- a/drivers/vfio/container.c
+++ b/drivers/vfio/container.c
@@ -188,8 +188,9 @@ void vfio_device_container_unregister(struct vfio_device 
*device)
device->group->container->iommu_data, device);
 }
 
-long vfio_container_ioctl_check_extension(struct vfio_container *container,
- unsigned long arg)
+static long
+vfio_container_ioctl_check_extension(struct vfio_container *container,
+unsigned long arg)
 {
struct vfio_iommu_driver *driver;
long ret = 0;
diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
index 54e5a8e0834ccb..247590334e14b0 100644
--- a/drivers/vfio/vfio.h
+++ b/drivers/vfio/vfio.h
@@ -119,8 +119,6 @@ int vfio_container_attach_group(struct vfio_container 
*container,
 void vfio_group_detach_container(struct vfio_group *group);
 void vfio_device_container_register(struct vfio_device *device);
 void vfio_device_container_unregister(struct vfio_device *device);
-long vfio_container_ioctl_check_extension(struct vfio_container *container,
- unsigned long arg);
 int __init vfio_container_init(void);
 void vfio_container_cleanup(void);
 
diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index 1e414b2c48a511..a8d1fbfcc3ddad 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -1625,24 +1625,25 @@ EXPORT_SYMBOL_GPL(vfio_file_is_group);
 bool vfio_file_enforced_coherent(struct file *file)
 {
struct vfio_group *group = file->private_data;
-   bool ret;
+   struct vfio_device *device;
+   bool ret = true;
 
if (!vfio_file_is_group(file))
return true;
 
-   mutex_lock(>group_lock);
-   if (group->container) {
-   ret = vfio_container_ioctl_check_extension(group->container,
-  VFIO_DMA_CC_IOMMU);
-   } else {
-   /*
-* Since the coherency state is determined only once a container
-* is attached the user must do so before they can prove they
-* have permission.
-*/
-   ret = true;
+   /*
+* If the device does not have IOMMU_CAP_ENFORCE_CACHE_COHERENCY then
+* any domain later attached to it will also not support it.
+*/
+   mutex_lock(>device_lock);
+   list_for_each_entry(device, >device_list, group_next) {
+   if (!device_iommu_capable(device->dev,
+ IOMMU_CAP_ENFORCE_CACHE_COHERENCY)) {
+   ret = false;
+   break;
+   }
}
-   mutex_unlock(>group_lock);
+   mutex_unlock(>device_lock);
return ret;
 }
 EXPORT_SYMBOL_GPL(vfio_file_enforced_coherent);
-- 
2.38.0

[Intel-gfx] [PATCH 1/2] drm/i915/dg2: Introduce Wa_18018764978

[Matt Atwood]

Wa_18018764978 applies to specific steppings of DG2 (G11 C0+,
G11 and G12 A0+).

Bspec: 66622

Signed-off-by: Matt Atwood 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 36d95b79022c..e8372d4cd548 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -448,6 +448,9 @@
 #define GEN8_L3CNTLREG _MMIO(0x7034)
 #define   GEN8_ERRDETBCTRL (1 << 9)
 
+#define PSS_MODE2  _MMIO(0x703c)
+#define   SCOREBOARD_STALL_FLUSH_CONTROL   REG_BIT(5)
+
 #define GEN7_SC_INSTDONE   _MMIO(0x7100)
 #define GEN12_SC_INSTDONE_EXTRA_MMIO(0x7104)
 #define GEN12_SC_INSTDONE_EXTRA2   _MMIO(0x7108)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 63e1e6becf34..ced3a26cf7e7 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -743,6 +743,11 @@ static void dg2_ctx_workarounds_init(struct 
intel_engine_cs *engine,
IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
wa_masked_field_set(wal, VF_PREEMPTION, 
PREEMPTION_VERTEX_COUNT, 0x4000);
 
+   /* Wa_18018764978:dg2 */
+   if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) ||
+   IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
+   wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
+
/* Wa_15010599737:dg2 */
wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
 }
-- 
2.37.3

[Intel-gfx] [PATCH 2/2] drm/i915/dg2: Introduce Wa_18019271663

[Matt Atwood]

Wa_18019271663 applies to all DG2 steppings and skus.

Bspec:45809

Signed-off-by: Matt Atwood 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 ---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index e8372d4cd548..46035503068c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -421,9 +421,10 @@
 #define   RC_OP_FLUSH_ENABLE   (1 << 0)
 #define   HIZ_RAW_STALL_OPT_DISABLE(1 << 2)
 #define CACHE_MODE_1   _MMIO(0x7004) /* IVB+ */
-#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE(1 << 6)
-#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE(1 << 6)
-#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   (1 << 1)
+#define   MSAA_OPTIMIZATION_REDUC_DISABLE  REG_BIT(11)
+#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLEREG_BIT(6)
+#define   GEN8_4x4_STC_OPTIMIZATION_DISABLEREG_BIT(6)
+#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   REG_BIT(1)
 
 #define GEN7_GT_MODE   _MMIO(0x7008)
 #define   GEN9_IZ_HASHING_MASK(slice)  (0x3 << ((slice) * 2))
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ced3a26cf7e7..9f39b7758ff3 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -750,6 +750,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs 
*engine,
 
/* Wa_15010599737:dg2 */
wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
+
+   /* Wa_18019271663:dg2 */
+   wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
 }
 
 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
-- 
2.37.3

Re: [Intel-gfx] [PATCH] drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode

[Jani Nikula]

On Tue, 25 Oct 2022, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> If we can't dig out a fixed mode for LVDS from the VBT or EDID
> let's fall back to using the current output timings. This should
> work as long as the BIOS has (somehow) enabled the output.
>
> In this case we are dealing with the some kind of BLB based POS
> machine (Toshiba SurePOS 500) where neither the OpRegion mailbox
> nor the vbios ROM contain a valid VBT. And no EDID anywhere we
> could find either.
>
> Cc:  # v5.19+
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7301
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Jani Nikula 

But they're saying it's a regression between 4.19 and 5.10...


> ---
>  drivers/gpu/drm/i915/display/intel_panel.c |  6 ++--
>  drivers/gpu/drm/i915/display/intel_panel.h |  3 ++
>  drivers/gpu/drm/i915/display/intel_sdvo.c  | 40 ++
>  3 files changed, 46 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c 
> b/drivers/gpu/drm/i915/display/intel_panel.c
> index 69ce77711b7c..69082fbc7647 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -275,9 +275,9 @@ void intel_panel_add_edid_fixed_modes(struct 
> intel_connector *connector,
>   intel_panel_destroy_probed_modes(connector);
>  }
>  
> -static void intel_panel_add_fixed_mode(struct intel_connector *connector,
> -struct drm_display_mode *fixed_mode,
> -const char *type)
> +void intel_panel_add_fixed_mode(struct intel_connector *connector,
> + struct drm_display_mode *fixed_mode,
> + const char *type)
>  {
>   struct drm_i915_private *i915 = to_i915(connector->base.dev);
>   struct drm_display_info *info = >base.display_info;
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.h 
> b/drivers/gpu/drm/i915/display/intel_panel.h
> index 5c5b5b7f95b6..964efed8ef3c 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.h
> +++ b/drivers/gpu/drm/i915/display/intel_panel.h
> @@ -43,6 +43,9 @@ int intel_panel_fitting(struct intel_crtc_state *crtc_state,
>   const struct drm_connector_state *conn_state);
>  int intel_panel_compute_config(struct intel_connector *connector,
>  struct drm_display_mode *adjusted_mode);
> +void intel_panel_add_fixed_mode(struct intel_connector *connector,
> + struct drm_display_mode *fixed_mode,
> + const char *type);
>  void intel_panel_add_edid_fixed_modes(struct intel_connector *connector,
> bool use_alt_fixed_modes);
>  void intel_panel_add_vbt_lfp_fixed_mode(struct intel_connector *connector);
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c 
> b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index cf8e80936d8e..9ed54118b669 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -781,6 +781,13 @@ static bool intel_sdvo_get_input_timing(struct 
> intel_sdvo *intel_sdvo,
>SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
>  }
>  
> +static bool intel_sdvo_get_output_timing(struct intel_sdvo *intel_sdvo,
> +  struct intel_sdvo_dtd *dtd)
> +{
> + return intel_sdvo_get_timing(intel_sdvo,
> +  SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
> +}
> +
>  static bool
>  intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
>struct intel_sdvo_connector 
> *intel_sdvo_connector,
> @@ -2864,6 +2871,36 @@ intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, 
> int device)
>   return true;
>  }
>  
> +static void
> +intel_sdvo_add_current_fixed_mode(struct intel_sdvo *intel_sdvo,
> +   struct intel_sdvo_connector *connector)
> +{
> + struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
> + struct drm_display_mode *mode;
> + struct intel_sdvo_dtd dtd = {};
> +
> + if (!intel_sdvo_set_target_output(intel_sdvo,
> +   connector->output_flag)) {
> + drm_dbg_kms(>drm, "failed to set SDVO target output\n");
> + return;
> + }
> +
> + if (!intel_sdvo_get_output_timing(intel_sdvo, )) {
> + drm_dbg_kms(>drm, "failed to get SDVO output timings\n");
> + return;
> + }
> +
> + mode = drm_mode_create(>drm);
> + if (!mode)
> + return;
> +
> + intel_sdvo_get_mode_from_dtd(mode, );
> +
> + drm_mode_set_name(mode);
> +
> + intel_panel_add_fixed_mode(>base, mode, "current (SDVO)");
> +}
> +
>  static bool
>  intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
>  {
> @@ -2913,6 +2950,9 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int 
> 

Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function

[Balasubramani Vivekanandan]

On 21.10.2022 14:39, Anusha Srivatsa wrote:
> No functional change. Introduce dg2_cdclk_squash_program and
> move squash_ctl register programming bits to this.
> 
> v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)
> 
> Cc: Jani Nikula 
> Cc: Balasubramani Vivekanandan 
> Cc: Ville Syrjälä 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +-
>  1 file changed, 14 insertions(+), 9 deletions(-)

Reviewed-by: Balasubramani Vivekanandan 

> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 3893779e0c23..e21cd0fbe29a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1705,6 +1705,18 @@ static void bxt_cdclk_pll_update(struct 
> drm_i915_private *i915, int vco)
>  
>  }
>  
> +static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
> +  u16 waveform)
> +{
> + u32 squash_ctl = 0;
> +
> + if (waveform)
> + squash_ctl = CDCLK_SQUASH_ENABLE |
> +  CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> +
> + intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
> +}
> +
>  static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> @@ -1752,15 +1764,8 @@ static void bxt_set_cdclk(struct drm_i915_private 
> *dev_priv,
>   else
>   clock = cdclk;
>  
> - if (HAS_CDCLK_SQUASH(dev_priv)) {
> - u32 squash_ctl = 0;
> -
> - if (waveform)
> - squash_ctl = CDCLK_SQUASH_ENABLE |
> - CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> -
> - intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
> - }
> + if (HAS_CDCLK_SQUASH(dev_priv))
> + dg2_cdclk_squash_program(dev_priv, waveform);
>  
>   val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
>   bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
> -- 
> 2.25.1
> 

Re: [Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk()

[Balasubramani Vivekanandan]

On 21.10.2022 14:39, Anusha Srivatsa wrote:
> No functional change. Moving segments out to simplify
> bxt_set_cdlck()
> 
> v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani)
> 
> Cc: Jani Nikula 
> Cc: Balasubramani Vivekanandan 
> Cc: Ville Syrjälä 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++
>  1 file changed, 25 insertions(+), 15 deletions(-)

Reviewed-by: Balasubramani Vivekanandan 

> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 45babbc6290f..3893779e0c23 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1684,6 +1684,27 @@ static u32 cdclk_squash_waveform(struct 
> drm_i915_private *dev_priv,
>   return 0x;
>  }
>  
> +static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco)
> +{
> + if (i915->display.cdclk.hw.vco != 0 &&
> + i915->display.cdclk.hw.vco != vco)
> + icl_cdclk_pll_disable(i915);
> +
> + if (i915->display.cdclk.hw.vco != vco)
> + icl_cdclk_pll_enable(i915, vco);
> +}
> +
> +static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
> +{
> + if (i915->display.cdclk.hw.vco != 0 &&
> + i915->display.cdclk.hw.vco != vco)
> + bxt_de_pll_disable(i915);
> +
> + if (i915->display.cdclk.hw.vco != vco)
> + bxt_de_pll_enable(i915, vco);
> +
> +}
> +
>  static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> @@ -1719,21 +1740,10 @@ static void bxt_set_cdclk(struct drm_i915_private 
> *dev_priv,
>   if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && 
> vco > 0) {
>   if (dev_priv->display.cdclk.hw.vco != vco)
>   adlp_cdclk_pll_crawl(dev_priv, vco);
> - } else if (DISPLAY_VER(dev_priv) >= 11) {
> - if (dev_priv->display.cdclk.hw.vco != 0 &&
> - dev_priv->display.cdclk.hw.vco != vco)
> - icl_cdclk_pll_disable(dev_priv);
> -
> - if (dev_priv->display.cdclk.hw.vco != vco)
> - icl_cdclk_pll_enable(dev_priv, vco);
> - } else {
> - if (dev_priv->display.cdclk.hw.vco != 0 &&
> - dev_priv->display.cdclk.hw.vco != vco)
> - bxt_de_pll_disable(dev_priv);
> -
> - if (dev_priv->display.cdclk.hw.vco != vco)
> - bxt_de_pll_enable(dev_priv, vco);
> - }
> + } else if (DISPLAY_VER(dev_priv) >= 11)
> + icl_cdclk_pll_update(dev_priv, vco);
> + else
> + bxt_cdclk_pll_update(dev_priv, vco);
>  
>   waveform = cdclk_squash_waveform(dev_priv, cdclk);
>  
> -- 
> 2.25.1
> 

Re: [Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro

[Balasubramani Vivekanandan]

On 21.10.2022 14:39, Anusha Srivatsa wrote:
> Driver had discrepancy in how cdclk squash and crawl support
> were checked. Like crawl, add squash as a 1 bit feature flag
> to the display section of DG2.
> 
> Cc: Balasubramani Vivekanandan 
> Cc: Ville Syrjälä 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +--
>  drivers/gpu/drm/i915/i915_drv.h|  1 +
>  drivers/gpu/drm/i915/i915_pci.c|  1 +
>  drivers/gpu/drm/i915/intel_device_info.h   |  1 +
>  4 files changed, 8 insertions(+), 10 deletions(-)

Reviewed-by: Balasubramani Vivekanandan 

> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 0f5add2fc51b..45babbc6290f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1220,11 +1220,6 @@ static void skl_cdclk_uninit_hw(struct 
> drm_i915_private *dev_priv)
>   skl_set_cdclk(dev_priv, _config, INVALID_PIPE);
>  }
>  
> -static bool has_cdclk_squash(struct drm_i915_private *i915)
> -{
> - return IS_DG2(i915);
> -}
> -
>  struct intel_cdclk_vals {
>   u32 cdclk;
>   u16 refclk;
> @@ -1520,7 +1515,7 @@ static void bxt_get_cdclk(struct drm_i915_private 
> *dev_priv,
>   return;
>   }
>  
> - if (has_cdclk_squash(dev_priv))
> + if (HAS_CDCLK_SQUASH(dev_priv))
>   squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
>  
>   if (squash_ctl & CDCLK_SQUASH_ENABLE) {
> @@ -1747,7 +1742,7 @@ static void bxt_set_cdclk(struct drm_i915_private 
> *dev_priv,
>   else
>   clock = cdclk;
>  
> - if (has_cdclk_squash(dev_priv)) {
> + if (HAS_CDCLK_SQUASH(dev_priv)) {
>   u32 squash_ctl = 0;
>  
>   if (waveform)
> @@ -1845,7 +1840,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private 
> *dev_priv)
>   expected = skl_cdclk_decimal(cdclk);
>  
>   /* Figure out what CD2X divider we should be using for this cdclk */
> - if (has_cdclk_squash(dev_priv))
> + if (HAS_CDCLK_SQUASH(dev_priv))
>   clock = dev_priv->display.cdclk.hw.vco / 2;
>   else
>   clock = dev_priv->display.cdclk.hw.cdclk;
> @@ -1976,7 +1971,7 @@ static bool intel_cdclk_can_squash(struct 
> drm_i915_private *dev_priv,
>* the moment all platforms with squasher use a fixed cd2x
>* divider.
>*/
> - if (!has_cdclk_squash(dev_priv))
> + if (!HAS_CDCLK_SQUASH(dev_priv))
>   return false;
>  
>   return a->cdclk != b->cdclk &&
> @@ -2028,7 +2023,7 @@ static bool intel_cdclk_can_cd2x_update(struct 
> drm_i915_private *dev_priv,
>* the moment all platforms with squasher use a fixed cd2x
>* divider.
>*/
> - if (has_cdclk_squash(dev_priv))
> + if (HAS_CDCLK_SQUASH(dev_priv))
>   return false;
>  
>   return a->cdclk != b->cdclk &&
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d7b8eb9d4117..db51050e3ba2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -869,6 +869,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)(DISPLAY_VER(dev_priv) >= 9 || 
> IS_BROADWELL(dev_priv))
>  
>  #define HAS_CDCLK_CRAWL(dev_priv) 
> (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
> +#define HAS_CDCLK_SQUASH(dev_priv)
> (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
>  #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) 
> (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
>  #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 19bf5ef6a20d..a88e1439a426 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1064,6 +1064,7 @@ static const struct intel_device_info xehpsdv_info = {
>   .has_guc_deprivilege = 1, \
>   .has_heci_pxp = 1, \
>   .has_media_ratio_mode = 1, \
> + .display.has_cdclk_squash = 1, \
>   .__runtime.platform_engine_mask = \
>   BIT(RCS0) | BIT(BCS0) | \
>   BIT(VECS0) | BIT(VECS1) | \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index cdf78728dcad..67d8759c802c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -180,6 +180,7 @@ enum intel_ppgtt_type {
>   /* Keep in alphabetical order */ \
>   func(cursor_needs_physical); \
>   func(has_cdclk_crawl); \
> + func(has_cdclk_squash); \
>   func(has_ddi); \
>   func(has_dp_mst); \
>   func(has_dsb); \
> -- 
> 2.25.1
> 

Re: [Intel-gfx] [PATCH 1/4] drm/i915/display: Change terminology for cdclk actions

[Balasubramani Vivekanandan]

On 21.10.2022 14:39, Anusha Srivatsa wrote:
> No functional changes. Changing terminolgy in some
> print statements. s/has_cdclk_squasher/has_cdclk_squash,
> s/crawler/crawl and s/squasher/squash.
> 
> Cc: Balasubramani Vivekanandan 
> Cc: Ville Syrjälä 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 16 
>  1 file changed, 8 insertions(+), 8 deletions(-)

Reviewed-by: Balasubramani Vivekanandan 

> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index ad401357ab66..0f5add2fc51b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1220,7 +1220,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private 
> *dev_priv)
>   skl_set_cdclk(dev_priv, _config, INVALID_PIPE);
>  }
>  
> -static bool has_cdclk_squasher(struct drm_i915_private *i915)
> +static bool has_cdclk_squash(struct drm_i915_private *i915)
>  {
>   return IS_DG2(i915);
>  }
> @@ -1520,7 +1520,7 @@ static void bxt_get_cdclk(struct drm_i915_private 
> *dev_priv,
>   return;
>   }
>  
> - if (has_cdclk_squasher(dev_priv))
> + if (has_cdclk_squash(dev_priv))
>   squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
>  
>   if (squash_ctl & CDCLK_SQUASH_ENABLE) {
> @@ -1747,7 +1747,7 @@ static void bxt_set_cdclk(struct drm_i915_private 
> *dev_priv,
>   else
>   clock = cdclk;
>  
> - if (has_cdclk_squasher(dev_priv)) {
> + if (has_cdclk_squash(dev_priv)) {
>   u32 squash_ctl = 0;
>  
>   if (waveform)
> @@ -1845,7 +1845,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private 
> *dev_priv)
>   expected = skl_cdclk_decimal(cdclk);
>  
>   /* Figure out what CD2X divider we should be using for this cdclk */
> - if (has_cdclk_squasher(dev_priv))
> + if (has_cdclk_squash(dev_priv))
>   clock = dev_priv->display.cdclk.hw.vco / 2;
>   else
>   clock = dev_priv->display.cdclk.hw.cdclk;
> @@ -1976,7 +1976,7 @@ static bool intel_cdclk_can_squash(struct 
> drm_i915_private *dev_priv,
>* the moment all platforms with squasher use a fixed cd2x
>* divider.
>*/
> - if (!has_cdclk_squasher(dev_priv))
> + if (!has_cdclk_squash(dev_priv))
>   return false;
>  
>   return a->cdclk != b->cdclk &&
> @@ -2028,7 +2028,7 @@ static bool intel_cdclk_can_cd2x_update(struct 
> drm_i915_private *dev_priv,
>* the moment all platforms with squasher use a fixed cd2x
>* divider.
>*/
> - if (has_cdclk_squasher(dev_priv))
> + if (has_cdclk_squash(dev_priv))
>   return false;
>  
>   return a->cdclk != b->cdclk &&
> @@ -2754,12 +2754,12 @@ int intel_modeset_calc_cdclk(struct 
> intel_atomic_state *state)
>  _cdclk_state->actual,
>  _cdclk_state->actual)) {
>   drm_dbg_kms(_priv->drm,
> - "Can change cdclk via squasher\n");
> + "Can change cdclk via squashing\n");
>   } else if (intel_cdclk_can_crawl(dev_priv,
>_cdclk_state->actual,
>_cdclk_state->actual)) {
>   drm_dbg_kms(_priv->drm,
> - "Can change cdclk via crawl\n");
> + "Can change cdclk via crawling\n");
>   } else if (pipe != INVALID_PIPE) {
>   new_cdclk_state->pipe = pipe;
>  
> -- 
> 2.25.1
> 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/slpc: Use platform limits for min/max frequency (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/slpc: Use platform limits for min/max frequency (rev5)
URL   : https://patchwork.freedesktop.org/series/109632/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12293 -> Patchwork_109632v5


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/index.html

Participating hosts (42 -> 39)
--

  Missing(3): fi-ctg-p8600 fi-icl-u2 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_109632v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@gem_tiled_blits@basic:
- fi-pnv-d510:[PASS][2] -> [SKIP][3] ([fdo#109271])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-pnv-d510/igt@gem_tiled_bl...@basic.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- bat-adlp-4: NOTRUN -> [SKIP][5] ([fdo#111827])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/bat-adlp-4/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-apl-guc: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-apl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlp-4: NOTRUN -> [SKIP][7] ([i915#3546])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/bat-adlp-4/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-apl-guc: NOTRUN -> [SKIP][8] ([fdo#109271]) +11 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-apl-guc/igt@kms_psr@sprite_plane_onoff.html

  * igt@runner@aborted:
- fi-skl-guc: NOTRUN -> [FAIL][9] ([i915#4312])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-skl-guc/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][10] ([i915#2867]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_linear_blits@basic:
- fi-pnv-d510:[SKIP][12] ([fdo#109271]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-pnv-d510/igt@gem_linear_bl...@basic.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-pnv-d510/igt@gem_linear_bl...@basic.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [INCOMPLETE][14] ([i915#7056]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_selftest@live@guc:
- {bat-rpls-2}:   [DMESG-WARN][16] ([i915#6471]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rpls-2/igt@i915_selftest@l...@guc.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/bat-rpls-2/igt@i915_selftest@l...@guc.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][18] ([i915#4785]) -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@migrate:
- bat-adlp-4: [INCOMPLETE][20] ([i915#7308]) -> [PASS][21]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-adlp-4/igt@i915_selftest@l...@migrate.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/bat-adlp-4/igt@i915_selftest@l...@migrate.html

  * igt@i915_selftest@live@requests:
- {bat-rpls-1}:   [INCOMPLETE][22] ([i915#6257]) -> [PASS][23]
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rpls-1/igt@i915_selftest@l...@requests.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/bat-rpls-1/igt@i915_selftest@l...@requests.html

 

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: CAGF and RC6 changes for MTL (rev11)

[Dixit, Ashutosh]

On Mon, 24 Oct 2022 18:25:06 -0700, Patchwork wrote:
>

Hi Lakshmi,

The below failures are unrelated to this series.

Thanks.
--
Ashutosh

> Patch Details
>
> Series:  i915: CAGF and RC6 changes for MTL (rev11)
> URL: https://patchwork.freedesktop.org/series/108156/
> State:   failure
> Details: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.html
>
> CI Bug Log - changes from CI_DRM_12288 -> Patchwork_108156v11
>
> Summary
>
> FAILURE
>
> Serious unknown changes coming with Patchwork_108156v11 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_108156v11, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.html
>
> Participating hosts (41 -> 40)
>
> Additional (1): bat-atsm-1
> Missing (2): fi-ctg-p8600 fi-icl-u2
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in 
> Patchwork_108156v11:
>
> IGT changes
>
> Possible regressions
>
>   • igt@gem_exec_parallel@engines@contexts:
>
>   □ fi-bsw-nick: PASS -> INCOMPLETE
>   • igt@i915_selftest@live@hugepages:
>
>   □ fi-cfl-8109u: PASS -> DMESG-FAIL
>
>   □ fi-skl-guc: PASS -> DMESG-FAIL
>
>   • igt@i915_suspend@basic-s3-without-i915:
>
>   □ fi-rkl-11600: NOTRUN -> INCOMPLETE
>
> Suppressed

[Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

[Patchwork]

== Series Details ==

Series: Revert "drm/i915/uapi: expose GTT alignment"
URL   : https://patchwork.freedesktop.org/series/110041/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12284 -> Patchwork_110041v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110041v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110041v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html

Participating hosts (41 -> 42)
--

  Additional (4): fi-kbl-soraka fi-hsw-4770 fi-icl-u2 bat-atsm-1 
  Missing(3): fi-ctg-p8600 fi-bdw-samus fi-tgl-dsi 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110041v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@hugepages:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_selftest@l...@hugepages.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_parallel@engines@contexts:
- {fi-ehl-2}: [PASS][2] -> [INCOMPLETE][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-ehl-2/igt@gem_exec_parallel@engi...@contexts.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-ehl-2/igt@gem_exec_parallel@engi...@contexts.html

  
Known issues


  Here are the changes found in Patchwork_110041v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_exec_gttf...@basic.html
- fi-pnv-d510:[PASS][5] -> [FAIL][6] ([i915#7229])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][7] ([i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([i915#4613]) +3 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [PASS][11] -> [INCOMPLETE][12] ([i915#7056])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271]) +9 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html

  * igt@i915_module_load@load:
- fi-kbl-soraka:  NOTRUN -> [DMESG-WARN][14] ([i915#1982])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_module_l...@load.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3012])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][16] ([i915#1886])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][17] ([i915#4785])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@hugepages:
- fi-glk-j4005:   [PASS][18] -> [DMESG-FAIL][19] ([i915#7311])
   [18]: 

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

[Matthew Auld]

On 25/10/2022 17:37, Patchwork wrote:

*Patch Details*
*Series:*   Revert "drm/i915/uapi: expose GTT alignment"
*URL:*	https://patchwork.freedesktop.org/series/110041/ 


*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html 




  CI Bug Log - changes from CI_DRM_12284 -> Patchwork_110041v1


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_110041v1 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_110041v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html



Participating hosts (41 -> 42)

Additional (4): fi-kbl-soraka fi-hsw-4770 fi-icl-u2 bat-atsm-1
Missing (3): fi-ctg-p8600 fi-bdw-samus fi-tgl-dsi


Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_110041v1:



  IGT changes


Possible regressions

  * igt@i915_selftest@live@hugepages:
  o fi-kbl-soraka: NOTRUN -> INCOMPLETE




Also unrelated. Looks like some incomplete with no logs in the 
selftests. Patch is for sure not related, since it's just some uapi thing.





Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  * igt@gem_exec_parallel@engines@contexts:
  o {fi-ehl-2}: PASS


 -> INCOMPLETE 



Known issues

Here are the changes found in Patchwork_110041v1 that come from known 
issues:



  IGT changes


Issues hit

  *

igt@gem_exec_gttfill@basic:

  o

fi-kbl-soraka: NOTRUN -> SKIP


 (fdo#109271 ) +9 similar issues

  o

fi-pnv-d510: PASS


 -> FAIL 

 (i915#7229 )

  *

igt@gem_huc_copy@huc-copy:

  o

fi-icl-u2: NOTRUN -> SKIP


 (i915#2190 )

  o

fi-kbl-soraka: NOTRUN -> SKIP


 (fdo#109271  / i915#2190 
)

  *

igt@gem_lmem_swapping@basic:

  o fi-kbl-soraka: NOTRUN -> SKIP


 (fdo#109271  / i915#4613 
) +3 similar issues
  *

igt@gem_lmem_swapping@random-engines:

  o fi-icl-u2: NOTRUN -> SKIP


 (i915#4613 ) +3 similar issues
  *

igt@gem_render_tiled_blits@basic:

  o fi-apl-guc: PASS


 -> INCOMPLETE 

 (i915#7056 )
  *

igt@gem_softpin@allocator-basic-reserve:

  o fi-hsw-4770: NOTRUN -> SKIP


 (fdo#109271 ) +9 similar issues
  *

igt@i915_module_load@load:

  o fi-kbl-soraka: NOTRUN -> DMESG-WARN


 (i915#1982 )
  *

igt@i915_pm_backlight@basic-brightness:

  o fi-hsw-4770: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/slpc: Use platform limits for min/max frequency (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/slpc: Use platform limits for min/max frequency (rev5)
URL   : https://patchwork.freedesktop.org/series/109632/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] [PATCH] drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode

[Ville Syrjala]

From: Ville Syrjälä 

If we can't dig out a fixed mode for LVDS from the VBT or EDID
let's fall back to using the current output timings. This should
work as long as the BIOS has (somehow) enabled the output.

In this case we are dealing with the some kind of BLB based POS
machine (Toshiba SurePOS 500) where neither the OpRegion mailbox
nor the vbios ROM contain a valid VBT. And no EDID anywhere we
could find either.

Cc:  # v5.19+
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7301
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_panel.c |  6 ++--
 drivers/gpu/drm/i915/display/intel_panel.h |  3 ++
 drivers/gpu/drm/i915/display/intel_sdvo.c  | 40 ++
 3 files changed, 46 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_panel.c 
b/drivers/gpu/drm/i915/display/intel_panel.c
index 69ce77711b7c..69082fbc7647 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -275,9 +275,9 @@ void intel_panel_add_edid_fixed_modes(struct 
intel_connector *connector,
intel_panel_destroy_probed_modes(connector);
 }
 
-static void intel_panel_add_fixed_mode(struct intel_connector *connector,
-  struct drm_display_mode *fixed_mode,
-  const char *type)
+void intel_panel_add_fixed_mode(struct intel_connector *connector,
+   struct drm_display_mode *fixed_mode,
+   const char *type)
 {
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct drm_display_info *info = >base.display_info;
diff --git a/drivers/gpu/drm/i915/display/intel_panel.h 
b/drivers/gpu/drm/i915/display/intel_panel.h
index 5c5b5b7f95b6..964efed8ef3c 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.h
+++ b/drivers/gpu/drm/i915/display/intel_panel.h
@@ -43,6 +43,9 @@ int intel_panel_fitting(struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
 int intel_panel_compute_config(struct intel_connector *connector,
   struct drm_display_mode *adjusted_mode);
+void intel_panel_add_fixed_mode(struct intel_connector *connector,
+   struct drm_display_mode *fixed_mode,
+   const char *type);
 void intel_panel_add_edid_fixed_modes(struct intel_connector *connector,
  bool use_alt_fixed_modes);
 void intel_panel_add_vbt_lfp_fixed_mode(struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c 
b/drivers/gpu/drm/i915/display/intel_sdvo.c
index cf8e80936d8e..9ed54118b669 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -781,6 +781,13 @@ static bool intel_sdvo_get_input_timing(struct intel_sdvo 
*intel_sdvo,
 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
 }
 
+static bool intel_sdvo_get_output_timing(struct intel_sdvo *intel_sdvo,
+struct intel_sdvo_dtd *dtd)
+{
+   return intel_sdvo_get_timing(intel_sdvo,
+SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
+}
+
 static bool
 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
 struct intel_sdvo_connector 
*intel_sdvo_connector,
@@ -2864,6 +2871,36 @@ intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, 
int device)
return true;
 }
 
+static void
+intel_sdvo_add_current_fixed_mode(struct intel_sdvo *intel_sdvo,
+ struct intel_sdvo_connector *connector)
+{
+   struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
+   struct drm_display_mode *mode;
+   struct intel_sdvo_dtd dtd = {};
+
+   if (!intel_sdvo_set_target_output(intel_sdvo,
+ connector->output_flag)) {
+   drm_dbg_kms(>drm, "failed to set SDVO target output\n");
+   return;
+   }
+
+   if (!intel_sdvo_get_output_timing(intel_sdvo, )) {
+   drm_dbg_kms(>drm, "failed to get SDVO output timings\n");
+   return;
+   }
+
+   mode = drm_mode_create(>drm);
+   if (!mode)
+   return;
+
+   intel_sdvo_get_mode_from_dtd(mode, );
+
+   drm_mode_set_name(mode);
+
+   intel_panel_add_fixed_mode(>base, mode, "current (SDVO)");
+}
+
 static bool
 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
 {
@@ -2913,6 +2950,9 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int 
device)
intel_panel_add_edid_fixed_modes(intel_connector, false);
}
 
+   if (!intel_panel_preferred_fixed_mode(intel_connector))
+   intel_sdvo_add_current_fixed_mode(intel_sdvo, 
intel_sdvo_connector);
+

Re: [Intel-gfx] [PATCH v2] drm/ttm: rework on ttm_resource to use size_t type

[Matthew Auld]

On Tue, 25 Oct 2022 at 16:51, Somalapuram Amaranath
 wrote:
>
> Change ttm_resource structure from num_pages to size_t size in bytes.
> v1 -> v2: change PFN_UP(dst_mem->size) to ttm->num_pages
> v1 -> v2: change bo->resource->size to bo->base.size at some places
> v1 -> v2: remove the local variable
> v1 -> v2: cleanup cmp_size_smaller_first()
>
> Signed-off-by: Somalapuram Amaranath 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c|  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  3 ++-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h |  4 ++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h  |  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  6 +++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c   |  8 
>  drivers/gpu/drm/i915/gem/i915_gem_ttm.c|  2 +-
>  drivers/gpu/drm/i915/i915_scatterlist.c|  4 ++--
>  drivers/gpu/drm/i915/i915_ttm_buddy_manager.c  | 12 ++--
>  drivers/gpu/drm/i915/intel_region_ttm.c|  2 +-
>  drivers/gpu/drm/nouveau/nouveau_bo.c   |  4 ++--
>  drivers/gpu/drm/nouveau/nouveau_bo0039.c   |  4 ++--
>  drivers/gpu/drm/nouveau/nouveau_bo5039.c   |  2 +-
>  drivers/gpu/drm/nouveau/nouveau_bo74c1.c   |  2 +-
>  drivers/gpu/drm/nouveau/nouveau_bo85b5.c   |  4 ++--
>  drivers/gpu/drm/nouveau/nouveau_bo9039.c   |  4 ++--
>  drivers/gpu/drm/nouveau/nouveau_bo90b5.c   |  4 ++--
>  drivers/gpu/drm/nouveau/nouveau_boa0b5.c   |  2 +-
>  drivers/gpu/drm/nouveau/nouveau_gem.c  |  5 ++---
>  drivers/gpu/drm/nouveau/nouveau_mem.c  |  4 ++--
>  drivers/gpu/drm/nouveau/nouveau_ttm.c  |  2 +-
>  drivers/gpu/drm/radeon/radeon_cs.c |  7 +--
>  drivers/gpu/drm/radeon/radeon_object.c |  4 ++--
>  drivers/gpu/drm/radeon/radeon_trace.h  |  2 +-
>  drivers/gpu/drm/radeon/radeon_ttm.c|  4 ++--
>  drivers/gpu/drm/ttm/ttm_bo.c   |  3 ---
>  drivers/gpu/drm/ttm/ttm_bo_util.c  |  6 +++---
>  drivers/gpu/drm/ttm/ttm_bo_vm.c|  4 ++--
>  drivers/gpu/drm/ttm/ttm_range_manager.c|  2 +-
>  drivers/gpu/drm/ttm/ttm_resource.c | 14 ++
>  drivers/gpu/drm/vmwgfx/vmwgfx_blit.c   |  4 ++--
>  drivers/gpu/drm/vmwgfx/vmwgfx_bo.c |  6 +++---
>  drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c|  2 +-
>  drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c|  2 +-
>  drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c  |  6 +++---
>  drivers/gpu/drm/vmwgfx/vmwgfx_kms.c|  2 +-
>  drivers/gpu/drm/vmwgfx/vmwgfx_page_dirty.c |  6 +++---
>  include/drm/ttm/ttm_resource.h |  4 ++--
>  38 files changed, 79 insertions(+), 81 deletions(-)
>



> diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
> index 38119311284d..f86dc92965bb 100644
> --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c
> +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
> @@ -217,7 +217,7 @@ vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf,
> page_last = vma_pages(vma) + vma->vm_pgoff -
> drm_vma_node_start(>base.vma_node);
>
> -   if (unlikely(page_offset >= bo->resource->num_pages))
> +   if (unlikely(page_offset >= bo->base.size))

At a glance it looks like we are missing PFN_UP(bo->base.size) for this one?

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Fix a build error used with clang compiler

[Nick Desaulniers]

Start of lore thread for context:
https://lore.kernel.org/intel-gfx/20221024210953.1572998-1-gwan-gyeong@intel.com/

On Tue, Oct 25, 2022 at 2:25 AM Andi Shyti  wrote:
>
> Hi Ashutosh,
>
> > > drivers/gpu/drm/i915/i915_hwmon.c:115:16: error: result of comparison of 
> > > constant 18446744073709551615 with expression of type 'typeof 
> > > (_Generic((field_msk), char: (unsigned char)0, unsigned char: (unsigned 
> > > char)0, signed char: (unsigned char)0, unsigned short: (unsigned short)0, 
> > > short: (unsigned short)0, unsigned int: (unsigned int)0, int: (unsigned 
> > > int)0, unsigned long: (unsigned long)0, long: (unsigned long)0, unsigned 
> > > long long: (unsigned long long)0, long long: (unsigned long long)0, 
> > > default: (field_msk)))' (aka 'unsigned int') is always false 
> > > [-Werror,-Wtautological-constant-out-of-range-compare]
> >
> > What is 18446744073709551615? You may want to limit the length of this line
> > or checkpatch doesn't complain?
>
> yeah! I am not a clang user, and this must be some ugly error
> output. I don't think it makes sense to break it, though.
>
> > > bits_to_set = FIELD_PREP(field_msk, nval);
> > >   ^~~
> > > ./include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP'
> > > __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: ");\
> > > ^~~
> > > ./include/linux/bitfield.h:71:53: note: expanded from macro 
> > > '__BF_FIELD_CHECK'
> > > BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
> > > ~~^~~
> > > ./include/linux/build_bug.h:39:58: note: expanded from macro 
> > > 'BUILD_BUG_ON_MSG'
> > > ~^~~
> > > ./include/linux/compiler_types.h:357:22: note: expanded from macro 
> > > 'compiletime_assert'
> > > _compiletime_assert(condition, msg, __compiletime_assert_, 
> > > __COUNTER__)
> > > 
> > > ^~~
> > > ./include/linux/compiler_types.h:345:23: note: expanded from macro 
> > > '_compiletime_assert'
> > > __compiletime_assert(condition, msg, prefix, suffix)
> > > ~^~~
> > > ./include/linux/compiler_types.h:337:9: note: expanded from macro 
> > > '__compiletime_assert'
> > > if (!(condition))   \
> > >
> > > Fixes: 99f55efb7911 ("drm/i915/hwmon: Power PL1 limit and TDP setting")
> > > Cc: Ashutosh Dixit 
> > > Cc: Anshuman Gupta 
> > > Cc: Andi Shyti 
> > > Signed-off-by: Gwan-gyeong Mun 
> > > ---
> > >  drivers/gpu/drm/i915/i915_hwmon.c | 12 +++-
> > >  1 file changed, 3 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c 
> > > b/drivers/gpu/drm/i915/i915_hwmon.c
> > > index 9e9781493025..782a621b1928 100644
> > > --- a/drivers/gpu/drm/i915/i915_hwmon.c
> > > +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> > > @@ -101,21 +101,16 @@ hwm_field_read_and_scale(struct hwm_drvdata *ddat, 
> > > i915_reg_t rgadr,
> > >
> > >  static void
> > >  hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
> > > - u32 field_msk, int nshift,
> > > - unsigned int scale_factor, long lval)
> > > + int nshift, unsigned int scale_factor, long lval)
> > >  {
> > > u32 nval;
> > > -   u32 bits_to_clear;
> > > -   u32 bits_to_set;
> > >
> > > /* Computation in 64-bits to avoid overflow. Round to nearest. */
> > > nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor);
> > >
> > > -   bits_to_clear = field_msk;
> > > -   bits_to_set = FIELD_PREP(field_msk, nval);
> > > -
> > > hwm_locked_with_pm_intel_uncore_rmw(ddat, rgadr,
> > > -   bits_to_clear, bits_to_set);
> > > +   PKG_PWR_LIM_1,
> > > +   FIELD_PREP(PKG_PWR_LIM_1, nval));
> >
> > I don't want to give up so easily. We might have future uses for the
> > function where we want field_msk to be passed into the function (rather
> > than set inside the function as in this patch).
> >
> > Do we understand what clang is complaining about? And why this compiles
> > with gcc?
>
> Because we are not compiling the builtin functions with gcc but
> gcc has support for them. The FIELD_PREP checks if the first
> parameter is a constant:
>
> BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask),
>
> where _mask was our field_mask, but we ignore it. Apparently
> clang doesn't.

So we've been in this code before. I'm having vague memories of
commit 444da3f52407 ("bitfield.h: don't compile-time validate _val in
FIELD_FIT")

But looking at the first __builtin_constant_p check in
__BF_FIELD_CHECK, I'm curious 

[Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

[Patchwork]

== Series Details ==

Series: Revert "drm/i915/uapi: expose GTT alignment"
URL   : https://patchwork.freedesktop.org/series/110041/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12284 -> Patchwork_110041v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110041v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110041v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html

Participating hosts (41 -> 42)
--

  Additional (4): fi-kbl-soraka fi-hsw-4770 fi-icl-u2 bat-atsm-1 
  Missing(3): fi-ctg-p8600 fi-bdw-samus fi-tgl-dsi 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110041v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@hugepages:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_selftest@l...@hugepages.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_parallel@engines@contexts:
- {fi-ehl-2}: [PASS][2] -> [INCOMPLETE][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-ehl-2/igt@gem_exec_parallel@engi...@contexts.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-ehl-2/igt@gem_exec_parallel@engi...@contexts.html

  
Known issues


  Here are the changes found in Patchwork_110041v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_exec_gttf...@basic.html
- fi-pnv-d510:[PASS][5] -> [FAIL][6] ([i915#7229])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][7] ([i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([i915#4613]) +3 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [PASS][11] -> [INCOMPLETE][12] ([i915#7056])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271]) +9 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html

  * igt@i915_module_load@load:
- fi-kbl-soraka:  NOTRUN -> [DMESG-WARN][14] ([i915#1982])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_module_l...@load.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3012])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][16] ([i915#1886])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][17] ([i915#4785])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@hugepages:
- fi-glk-j4005:   [PASS][18] -> [DMESG-FAIL][19] ([i915#7311])
   [18]: 

Re: [Intel-gfx] [PATCH v2] drm/ttm: rework on ttm_resource to use size_t type

[Christian König]

Am 25.10.22 um 17:50 schrieb Somalapuram Amaranath:

Change ttm_resource structure from num_pages to size_t size in bytes.
v1 -> v2: change PFN_UP(dst_mem->size) to ttm->num_pages
v1 -> v2: change bo->resource->size to bo->base.size at some places
v1 -> v2: remove the local variable
v1 -> v2: cleanup cmp_size_smaller_first()


Of hand that looks good to me now.

It would be nice if we keep the separation of one patch for each driver. 
But that would mean we need something like adding the size field first, 
patch all drivers and then remove num_pages which isn't a good approach 
either.


But please make sure that the Intel CI systems are happy with that.


Signed-off-by: Somalapuram Amaranath 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c|  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  3 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h  |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  6 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c   |  8 
  drivers/gpu/drm/i915/gem/i915_gem_ttm.c|  2 +-
  drivers/gpu/drm/i915/i915_scatterlist.c|  4 ++--
  drivers/gpu/drm/i915/i915_ttm_buddy_manager.c  | 12 ++--
  drivers/gpu/drm/i915/intel_region_ttm.c|  2 +-
  drivers/gpu/drm/nouveau/nouveau_bo.c   |  4 ++--
  drivers/gpu/drm/nouveau/nouveau_bo0039.c   |  4 ++--
  drivers/gpu/drm/nouveau/nouveau_bo5039.c   |  2 +-
  drivers/gpu/drm/nouveau/nouveau_bo74c1.c   |  2 +-
  drivers/gpu/drm/nouveau/nouveau_bo85b5.c   |  4 ++--
  drivers/gpu/drm/nouveau/nouveau_bo9039.c   |  4 ++--
  drivers/gpu/drm/nouveau/nouveau_bo90b5.c   |  4 ++--
  drivers/gpu/drm/nouveau/nouveau_boa0b5.c   |  2 +-
  drivers/gpu/drm/nouveau/nouveau_gem.c  |  5 ++---
  drivers/gpu/drm/nouveau/nouveau_mem.c  |  4 ++--
  drivers/gpu/drm/nouveau/nouveau_ttm.c  |  2 +-
  drivers/gpu/drm/radeon/radeon_cs.c |  7 +--
  drivers/gpu/drm/radeon/radeon_object.c |  4 ++--
  drivers/gpu/drm/radeon/radeon_trace.h  |  2 +-
  drivers/gpu/drm/radeon/radeon_ttm.c|  4 ++--
  drivers/gpu/drm/ttm/ttm_bo.c   |  3 ---
  drivers/gpu/drm/ttm/ttm_bo_util.c  |  6 +++---
  drivers/gpu/drm/ttm/ttm_bo_vm.c|  4 ++--
  drivers/gpu/drm/ttm/ttm_range_manager.c|  2 +-
  drivers/gpu/drm/ttm/ttm_resource.c | 14 ++
  drivers/gpu/drm/vmwgfx/vmwgfx_blit.c   |  4 ++--
  drivers/gpu/drm/vmwgfx/vmwgfx_bo.c |  6 +++---
  drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c|  2 +-
  drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c|  2 +-
  drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c  |  6 +++---
  drivers/gpu/drm/vmwgfx/vmwgfx_kms.c|  2 +-
  drivers/gpu/drm/vmwgfx/vmwgfx_page_dirty.c |  6 +++---
  include/drm/ttm/ttm_resource.h |  4 ++--
  38 files changed, 79 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 1f3302aebeff..44367f03316f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -144,7 +144,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager 
*man,
node->base.start = node->mm_nodes[0].start;
} else {
node->mm_nodes[0].start = 0;
-   node->mm_nodes[0].size = node->base.num_pages;
+   node->mm_nodes[0].size = PFN_UP(node->base.size);
node->base.start = AMDGPU_BO_INVALID_OFFSET;
}
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

index 2e8f6cd7a729..974e85d8b6cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -542,6 +542,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
/* GWS and OA don't need any alignment. */
page_align = bp->byte_align;
size <<= PAGE_SHIFT;
+
} else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
/* Both size and alignment must be a multiple of 4. */
page_align = ALIGN(bp->byte_align, 4);
@@ -776,7 +777,7 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
return 0;
}
  
-	r = ttm_bo_kmap(>tbo, 0, bo->tbo.resource->num_pages, >kmap);

+   r = ttm_bo_kmap(>tbo, 0, PFN_UP(bo->tbo.base.size), >kmap);
if (r)
return r;
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h

index 6546552e596c..5c4f93ee0c57 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
@@ -62,7 +62,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res,
if (!res)

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/ttm: rework on ttm_resource to use size_t type

[Patchwork]

== Series Details ==

Series: drm/ttm: rework on ttm_resource to use size_t type
URL   : https://patchwork.freedesktop.org/series/110129/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12293 -> Patchwork_110129v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/index.html

Participating hosts (42 -> 38)
--

  Missing(4): fi-ctg-p8600 fi-hsw-4770 fi-bdw-samus bat-dg1-5 

Known issues


  Here are the changes found in Patchwork_110129v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- bat-adlp-4: NOTRUN -> [SKIP][2] ([fdo#111827])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/bat-adlp-4/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-apl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/fi-apl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor@atomic:
- fi-icl-u2:  [PASS][4] -> [DMESG-WARN][5] ([i915#4890])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cur...@atomic.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cur...@atomic.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlp-4: NOTRUN -> [SKIP][6] ([i915#3546])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/bat-adlp-4/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-apl-guc: NOTRUN -> [SKIP][7] ([fdo#109271]) +11 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/fi-apl-guc/igt@kms_psr@sprite_plane_onoff.html

  * igt@runner@aborted:
- fi-icl-u2:  NOTRUN -> [FAIL][8] ([i915#4312])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/fi-icl-u2/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][9] ([i915#2867]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_linear_blits@basic:
- fi-pnv-d510:[SKIP][11] ([fdo#109271]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-pnv-d510/igt@gem_linear_bl...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/fi-pnv-d510/igt@gem_linear_bl...@basic.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [INCOMPLETE][13] ([i915#7056]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_selftest@live@migrate:
- bat-adlp-4: [INCOMPLETE][15] ([i915#7308]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-adlp-4/igt@i915_selftest@l...@migrate.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/bat-adlp-4/igt@i915_selftest@l...@migrate.html

  * igt@i915_selftest@live@requests:
- {bat-rpls-1}:   [INCOMPLETE][17] ([i915#6257]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rpls-1/igt@i915_selftest@l...@requests.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/bat-rpls-1/igt@i915_selftest@l...@requests.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
  [i915#6687]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/ttm: rework on ttm_resource to use size_t type

[Patchwork]

== Series Details ==

Series: drm/ttm: rework on ttm_resource to use size_t type
URL   : https://patchwork.freedesktop.org/series/110129/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.