Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dgfx: Grab wakeref at i915_ttm_unmap_virtual (rev4)

[Gupta, Anshuman]

Hi Lakshmi ,
Below CI failure are not related to this series.
Could you please re-report the results.
Br,
Anshuman Gupta.

From: Patchwork 
Sent: Thursday, October 27, 2022 8:11 PM
To: Gupta, Anshuman 
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: failure for drm/i915/dgfx: Grab wakeref at 
i915_ttm_unmap_virtual (rev4)

Patch Details
Series:
drm/i915/dgfx: Grab wakeref at i915_ttm_unmap_virtual (rev4)
URL:
https://patchwork.freedesktop.org/series/108972/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108972v4/index.html
CI Bug Log - changes from CI_DRM_12310 -> Patchwork_108972v4
Summary

FAILURE

Serious unknown changes coming with Patchwork_108972v4 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108972v4, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108972v4/index.html

Participating hosts (42 -> 39)

Additional (1): fi-kbl-soraka
Missing (4): fi-ctg-p8600 fi-hsw-4770 fi-rkl-11600 fi-icl-u2

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_108972v4:

IGT changes
Possible regressions

  *   igt@i915_selftest@live@gem_migrate:

 *   fi-kbl-soraka: NOTRUN -> 
INCOMPLETE

Known issues

Here are the changes found in Patchwork_108972v4 that come from known issues:

IGT changes
Issues hit

  *   igt@gem_exec_gttfill@basic:

 *   fi-kbl-soraka: NOTRUN -> 
SKIP
 (fdo#109271) +9 similar 
issues

  *   igt@gem_huc_copy@huc-copy:

 *   fi-kbl-soraka: NOTRUN -> 
SKIP
 (fdo#109271 / 
i915#2190)

  *   igt@gem_lmem_swapping@basic:

 *   fi-kbl-soraka: NOTRUN -> 
SKIP
 (fdo#109271 / 
i915#4613) +3 similar 
issues

  *   igt@gem_tiled_blits@basic:

 *   fi-pnv-d510: 
PASS
 -> 
SKIP
 (fdo#109271) +2 similar 
issues

  *   igt@i915_module_load@reload:

 *   fi-skl-guc: 
PASS
 -> 
DMESG-WARN
 (i915#1982)

  *   igt@i915_selftest@live@gt_pm:

 *   fi-kbl-soraka: NOTRUN -> 
DMESG-FAIL
 (i915#1886)

  *   igt@i915_selftest@live@hangcheck:

 *   fi-rkl-guc: 
PASS
 -> 
INCOMPLETE
 (i915#4983)

  *   igt@kms_chamelium@hdmi-hpd-fast:

 *   fi-kbl-soraka: NOTRUN -> 
SKIP
 (fdo#109271 / 
fdo#111827) +7 similar 
issues

Possible fixes

  *   igt@gem_exec_suspend@basic-s3@smem:

 *   {bat-rplp-1}: 
DMESG-WARN
 (i915#2867) -> 
PASS
 *   {bat-adlm-1}: 
DMESG-WARN
 (i915#2867) -> 
PASS

  *   igt@gem_huc_copy@huc-copy:

   

Re: [Intel-gfx] [PATCH v5] overflow: Introduce overflows_type() and castable_to_type()

[Gwan-gyeong Mun]

Hi Kees,

I've updated to v5 with the last comment of Nathan.
Could you please kindly review what more is needed as we move forward 
with this patch?


Br,

G.G.

On 10/24/22 11:11 PM, Gwan-gyeong Mun wrote:

From: Kees Cook 

Implement a robust overflows_type() macro to test if a variable or
constant value would overflow another variable or type. This can be
used as a constant expression for static_assert() (which requires a
constant expression[1][2]) when used on constant values. This must be
constructed manually, since __builtin_add_overflow() does not produce
a constant expression[3].

Additionally adds castable_to_type(), similar to __same_type(), but for
checking if a constant value would overflow if cast to a given type.

Add unit tests for overflows_type(), __same_type(), and castable_to_type()
to the existing KUnit "overflow" test.

[1] https://en.cppreference.com/w/c/language/_Static_assert
[2] C11 standard (ISO/IEC 9899:2011): 6.7.10 Static assertions
[3] https://gcc.gnu.org/onlinedocs/gcc/Integer-Overflow-Builtins.html
 6.56 Built-in Functions to Perform Arithmetic with Overflow Checking
 Built-in Function: bool __builtin_add_overflow (type1 a, type2 b,

Cc: Luc Van Oostenryck 
Cc: Nathan Chancellor 
Cc: Nick Desaulniers 
Cc: Tom Rix 
Cc: Daniel Latypov 
Cc: Vitor Massaru Iha 
Cc: "Gustavo A. R. Silva" 
Cc: Jani Nikula 
Cc: Mauro Carvalho Chehab 
Cc: linux-harden...@vger.kernel.org
Cc: l...@lists.linux.dev
Co-developed-by: Gwan-gyeong Mun 
Signed-off-by: Gwan-gyeong Mun 
Signed-off-by: Kees Cook 
---
v5: drop the cc-disable-warning and just disable the warning directly (Nathan)
v4:
  - move version v2 changelog commit message to under the --- marker (Mauro)
  - remove the #pragma addition in the code and modify the Makefile to handle 
the
same feature (Jani)
v3:
  - chagne to use uintptr_t type when checking for overflow of pointer type
variable
v2:
  - fix comment typo
  - wrap clang pragma to avoid GCC warnings
  - style nit cleanups
  - rename __castable_to_type() to castable_to_type()
  - remove prior overflows_type() definition
v1: https://lore.kernel.org/lkml/20220926003743.409911-1-keesc...@chromium.org
---
  drivers/gpu/drm/i915/i915_user_extensions.c |   2 +-
  drivers/gpu/drm/i915/i915_utils.h   |   4 -
  include/linux/compiler.h|   1 +
  include/linux/overflow.h|  48 +++
  lib/Makefile|   4 +
  lib/overflow_kunit.c| 383 +++-
  6 files changed, 436 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_user_extensions.c 
b/drivers/gpu/drm/i915/i915_user_extensions.c
index c822d0aafd2d..e3f808372c47 100644
--- a/drivers/gpu/drm/i915/i915_user_extensions.c
+++ b/drivers/gpu/drm/i915/i915_user_extensions.c
@@ -51,7 +51,7 @@ int i915_user_extensions(struct i915_user_extension __user 
*ext,
return err;
  
  		if (get_user(next, >next_extension) ||

-   overflows_type(next, ext))
+   overflows_type(next, uintptr_t))
return -EFAULT;
  
  		ext = u64_to_user_ptr(next);

diff --git a/drivers/gpu/drm/i915/i915_utils.h 
b/drivers/gpu/drm/i915/i915_utils.h
index 6c14d13364bf..67a66d4d5c70 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -111,10 +111,6 @@ bool i915_error_injected(void);
  #define range_overflows_end_t(type, start, size, max) \
range_overflows_end((type)(start), (type)(size), (type)(max))
  
-/* Note we don't consider signbits :| */

-#define overflows_type(x, T) \
-   (sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T))
-
  #define ptr_mask_bits(ptr, n) ({  \
unsigned long __v = (unsigned long)(ptr);   \
(typeof(ptr))(__v & -BIT(n));   \
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index 973a1bfd7ef5..947a60b801db 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -236,6 +236,7 @@ static inline void *offset_to_ptr(const int *off)
   * bool and also pointer types.
   */
  #define is_signed_type(type) (((type)(-1)) < (__force type)1)
+#define is_unsigned_type(type) (!is_signed_type(type))
  
  /*

   * This is needed in functions which generate the stack canary, see
diff --git a/include/linux/overflow.h b/include/linux/overflow.h
index 19dfdd74835e..58eb34aa2af9 100644
--- a/include/linux/overflow.h
+++ b/include/linux/overflow.h
@@ -127,6 +127,54 @@ static inline bool __must_check __must_check_overflow(bool 
overflow)
(*_d >> _to_shift) != _a);\
  }))
  
+#define __overflows_type_constexpr(x, T) (			\

+   is_unsigned_type(typeof(x)) ?   \
+   (x) > type_max(typeof(T)) ? 1 : 0\
+   : is_unsigned_type(typeof(T)) ? \
+   

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/hwmon: Fix a build error used with clang compiler (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/hwmon: Fix a build error used with clang compiler (rev5)
URL   : https://patchwork.freedesktop.org/series/110094/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12318 -> Patchwork_110094v5


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110094v5/index.html

Participating hosts (39 -> 38)
--

  Additional (1): fi-snb-2520m 
  Missing(2): fi-ctg-p8600 fi-icl-u2 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110094v5:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@requests:
- {bat-dg2-11}:   [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12318/bat-dg2-11/igt@i915_selftest@l...@requests.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110094v5/bat-dg2-11/igt@i915_selftest@l...@requests.html

  
Known issues


  Here are the changes found in Patchwork_110094v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110094v5/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110094v5/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2520m:   NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110094v5/fi-snb-2520m/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@prime_vgem@basic-fence-flip:
- fi-snb-2520m:   NOTRUN -> [SKIP][6] ([fdo#109271]) +21 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110094v5/fi-snb-2520m/igt@prime_v...@basic-fence-flip.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- {bat-adlm-1}:   [DMESG-WARN][7] ([i915#2867]) -> [PASS][8] +1 similar 
issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12318/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110094v5/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@gt_pm:
- {bat-rpls-2}:   [DMESG-FAIL][9] ([i915#4258]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12318/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110094v5/bat-rpls-2/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][11] ([i915#4785]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12318/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110094v5/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-g3258:   [INCOMPLETE][13] ([i915#3303] / [i915#4785]) -> 
[PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12318/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110094v5/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@migrate:
- {bat-adlp-6}:   [INCOMPLETE][15] ([i915#7348]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12318/bat-adlp-6/igt@i915_selftest@l...@migrate.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110094v5/bat-adlp-6/igt@i915_selftest@l...@migrate.html

  * igt@i915_selftest@live@reset:
- {bat-rpls-1}:   [DMESG-FAIL][17] ([i915#4983]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12318/bat-rpls-1/igt@i915_selftest@l...@reset.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110094v5/bat-rpls-1/igt@i915_selftest@l...@reset.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4785]: 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/hwmon: Fix a build error used with clang compiler (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/hwmon: Fix a build error used with clang compiler (rev5)
URL   : https://patchwork.freedesktop.org/series/110094/
State : warning

== Summary ==

Error: dim checkpatch failed
1fa009971802 drm/i915/hwmon: Fix a build error used with clang compiler
-:33: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#33: 
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)

total: 0 errors, 1 warnings, 0 checks, 31 lines checked

[Intel-gfx] [PATCH v2] drm/i915/hwmon: Fix a build error used with clang compiler

[Gwan-gyeong Mun]

Use REG_FIELD_PREP() and a constant value for hwm_field_scale_and_write()

If the first argument of FIELD_PREP() is not a compile-time constant value
or unsigned long long type, this routine of the __BF_FIELD_CHECK() macro
used internally by the FIELD_PREP() macro always returns false.

 BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) >  \
  __bf_cast_unsigned(_reg, ~0ull),\
  _pfx "type of reg too small for mask"); \

And it returns a build error by the option among the clang
compilation options. [-Werror,-Wtautological-constant-out-of-range-compare]

Reported build error while using clang compiler:

drivers/gpu/drm/i915/i915_hwmon.c:115:16: error: result of comparison of 
constant 18446744073709551615 with expression of type 'typeof 
(_Generic((field_msk), char: (unsigned char)0, unsigned char: (unsigned char)0, 
signed char: (unsigned char)0, unsigned short: (unsigned short)0, short: 
(unsigned short)0, unsigned int: (unsigned int)0, int: (unsigned int)0, 
unsigned long: (unsigned long)0, long: (unsigned long)0, unsigned long long: 
(unsigned long long)0, long long: (unsigned long long)0, default: 
(field_msk)))' (aka 'unsigned int') is always false 
[-Werror,-Wtautological-constant-out-of-range-compare]
bits_to_set = FIELD_PREP(field_msk, nval);
  ^~~
./include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP'
__BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: ");\
^~~
./include/linux/bitfield.h:71:53: note: expanded from macro '__BF_FIELD_CHECK'
BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
~~^~~
./include/linux/build_bug.h:39:58: note: expanded from macro 'BUILD_BUG_ON_MSG'
~^~~
./include/linux/compiler_types.h:357:22: note: expanded from macro 
'compiletime_assert'
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~
./include/linux/compiler_types.h:345:23: note: expanded from macro 
'_compiletime_assert'
__compiletime_assert(condition, msg, prefix, suffix)
~^~~
./include/linux/compiler_types.h:337:9: note: expanded from macro 
'__compiletime_assert'
if (!(condition))   \

v2: Use REG_FIELD_PREP() macro instead of FIELD_PREP() (Jani)

Fixes: 99f55efb7911 ("drm/i915/hwmon: Power PL1 limit and TDP setting")
Cc: Ashutosh Dixit 
Cc: Anshuman Gupta 
Cc: Andi Shyti 
Cc: Jani Nikula 
Signed-off-by: Gwan-gyeong Mun 
---
 drivers/gpu/drm/i915/i915_hwmon.c | 12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_hwmon.c 
b/drivers/gpu/drm/i915/i915_hwmon.c
index 9e9781493025..c588a17f97e9 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -101,21 +101,16 @@ hwm_field_read_and_scale(struct hwm_drvdata *ddat, 
i915_reg_t rgadr,
 
 static void
 hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
- u32 field_msk, int nshift,
- unsigned int scale_factor, long lval)
+ int nshift, unsigned int scale_factor, long lval)
 {
u32 nval;
-   u32 bits_to_clear;
-   u32 bits_to_set;
 
/* Computation in 64-bits to avoid overflow. Round to nearest. */
nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor);
 
-   bits_to_clear = field_msk;
-   bits_to_set = FIELD_PREP(field_msk, nval);
-
hwm_locked_with_pm_intel_uncore_rmw(ddat, rgadr,
-   bits_to_clear, bits_to_set);
+   PKG_PWR_LIM_1,
+   REG_FIELD_PREP(PKG_PWR_LIM_1, 
nval));
 }
 
 /*
@@ -406,7 +401,6 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int 
chan, long val)
case hwmon_power_max:
hwm_field_scale_and_write(ddat,
  hwmon->rg.pkg_rapl_limit,
- PKG_PWR_LIM_1,
  hwmon->scl_shift_power,
  SF_POWER, val);
return 0;
-- 
2.37.1

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/userptr: restore probe_range behaviour (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/userptr: restore probe_range behaviour (rev3)
URL   : https://patchwork.freedesktop.org/series/110083/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12316_full -> Patchwork_110083v3_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110083v3_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110083v3_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110083v3_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_cursor_legacy@cursor-vs-flip@atomic:
- shard-skl:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/shard-skl9/igt@kms_cursor_legacy@cursor-vs-f...@atomic.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-rkl}:[PASS][2] -> [FAIL][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-rkl-1/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html

  
Known issues


  Here are the changes found in Patchwork_110083v3_full that come from known 
issues:

### CI changes ###

 Possible fixes 

  * boot:
- shard-apl:  ([PASS][4], [PASS][5], [FAIL][6], [PASS][7], 
[PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], 
[PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], 
[PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], 
[PASS][26], [PASS][27], [PASS][28]) ([i915#4386]) -> ([PASS][29], [PASS][30], 
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], 
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], 
[PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl1/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl1/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl1/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl1/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl1/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl2/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl2/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl2/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl2/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl3/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl3/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl3/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl3/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl6/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl6/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl6/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl6/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl7/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl7/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl7/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl7/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl8/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl8/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl8/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl8/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/shard-apl1/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/shard-apl1/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/shard-apl1/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/shard-apl1/boot.html
   [33]: 

[Intel-gfx] ✗ Fi.CI.IGT: failure for Enable YCbCr420 for VDSC

[Patchwork]

== Series Details ==

Series: Enable YCbCr420 for VDSC
URL   : https://patchwork.freedesktop.org/series/110253/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12316_full -> Patchwork_110253v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110253v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110253v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110253v1_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_suspend@fence-restore-tiled2untiled:
- shard-skl:  [PASS][1] -> [INCOMPLETE][2] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-skl6/igt@i915_susp...@fence-restore-tiled2untiled.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/shard-skl7/igt@i915_susp...@fence-restore-tiled2untiled.html

  * 
igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-tglb5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscal...@pipe-a-valid-mode.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/shard-tglb8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscal...@pipe-a-valid-mode.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_ctx_exec@basic-close-race:
- {shard-rkl}:[PASS][5] -> [INCOMPLETE][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-rkl-5/igt@gem_ctx_e...@basic-close-race.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/shard-rkl-4/igt@gem_ctx_e...@basic-close-race.html

  
Known issues


  Here are the changes found in Patchwork_110253v1_full that come from known 
issues:

### CI changes ###

 Possible fixes 

  * boot:
- shard-apl:  ([PASS][7], [PASS][8], [FAIL][9], [PASS][10], 
[PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], 
[PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], 
[PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], 
[PASS][29], [PASS][30], [PASS][31]) ([i915#4386]) -> ([PASS][32], [PASS][33], 
[PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], 
[PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], 
[PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], 
[PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl1/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl1/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl1/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl1/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl1/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl2/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl2/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl2/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl2/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl3/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl3/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl3/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl3/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl6/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl6/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl6/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl6/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl7/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl7/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl7/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl7/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/shard-apl8/boot.html
   [29]: 

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Add missing steering table terminators

[Matt Roper]

On Fri, Oct 28, 2022 at 04:04:18PM -0700, Lucas De Marchi wrote:
> On Fri, Oct 28, 2022 at 03:40:22PM -0700, Matt Roper wrote:
> > The termination entries were missing for a couple of the recently-added
> > MTL steering tables.
> > 
> > Fixes: f32898c94a10 ("drm/i915/xelpg: Add multicast steering")
> > Fixes: a7ec65fc7e83 ("drm/i915/xelpmp: Add multicast steering for media GT")
> 
> I was thinking if we would need separate commits so they can be
> backported independently, but no... those commits were very close.
> 
> > Signed-off-by: Matt Roper 
> 
> 
> Reviewed-by: Lucas De Marchi 

Thanks for the review.  Applied to drm-intel-gt-next.


Matt

> 
> Lucas De Marchi
> 
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 2 ++
> > 1 file changed, 2 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c 
> > b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > index 46cf2f3d1e8e..830edffe88cc 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > @@ -128,11 +128,13 @@ static const struct intel_mmio_range 
> > xelpg_dss_steering_table[] = {
> > { 0x00D800, 0x00D87F }, /* SLICE */
> > { 0x00DC00, 0x00DCFF }, /* SLICE */
> > { 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
> > +   {},
> > };
> > 
> > static const struct intel_mmio_range xelpmp_oaddrm_steering_table[] = {
> > { 0x393200, 0x39323F },
> > { 0x393400, 0x3934FF },
> > +   {},
> > };
> > 
> > void intel_gt_mcr_init(struct intel_gt *gt)
> > -- 
> > 2.37.3
> > 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Add missing steering table terminators

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: Add missing steering table terminators
URL   : https://patchwork.freedesktop.org/series/110279/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12317 -> Patchwork_110279v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110279v1/index.html

Participating hosts (40 -> 39)
--

  Additional (1): fi-pnv-d510 
  Missing(2): fi-ctg-p8600 fi-cfl-8700k 

Known issues


  Here are the changes found in Patchwork_110279v1 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot:
- fi-ilk-650: [FAIL][1] ([i915#7350]) -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-ilk-650/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110279v1/fi-ilk-650/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:NOTRUN -> [FAIL][3] ([i915#7229])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110279v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-ilk-650: NOTRUN -> [SKIP][4] ([fdo#109271]) +19 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110279v1/fi-ilk-650/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-bdw-5557u:   [PASS][5] -> [INCOMPLETE][6] ([i915#146])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110279v1/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2:  NOTRUN -> [SKIP][7] ([fdo#111827])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110279v1/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-ilk-650: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110279v1/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_psr@primary_page_flip:
- fi-pnv-d510:NOTRUN -> [SKIP][9] ([fdo#109271]) +45 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110279v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- {bat-rpls-2}:   [DMESG-WARN][10] ([i915#6434]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/bat-rpls-2/igt@gem_exec_suspend@basic...@smem.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110279v1/bat-rpls-2/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][12] ([i915#2867]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110279v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
- {bat-rpls-1}:   [DMESG-WARN][14] ([i915#6687]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110279v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@gt_pm:
- fi-icl-u2:  [DMESG-FAIL][16] ([i915#4890]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-icl-u2/igt@i915_selftest@live@gt_pm.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110279v1/fi-icl-u2/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@migrate:
- {bat-dg2-11}:   [DMESG-WARN][18] -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/bat-dg2-11/igt@i915_selftest@l...@migrate.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110279v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890
  [i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
  [i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
  

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Set PROBE_PREFER_ASYNCHRONOUS

[Patchwork]

== Series Details ==

Series: drm/i915: Set PROBE_PREFER_ASYNCHRONOUS
URL   : https://patchwork.freedesktop.org/series/110277/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12317 -> Patchwork_110277v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110277v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110277v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110277v1/index.html

Participating hosts (40 -> 41)
--

  Additional (3): fi-kbl-soraka fi-tgl-dsi fi-pnv-d510 
  Missing(2): fi-ctg-p8600 fi-cfl-8700k 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110277v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gt_engines:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-apl-guc/igt@i915_selftest@live@gt_engines.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110277v1/fi-apl-guc/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@gt_timelines:
- fi-bdw-gvtdvm:  [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-bdw-gvtdvm/igt@i915_selftest@live@gt_timelines.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110277v1/fi-bdw-gvtdvm/igt@i915_selftest@live@gt_timelines.html

  * igt@i915_selftest@live@sanitycheck:
- fi-bsw-nick:[PASS][5] -> [INCOMPLETE][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-bsw-nick/igt@i915_selftest@l...@sanitycheck.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110277v1/fi-bsw-nick/igt@i915_selftest@l...@sanitycheck.html
- fi-hsw-g3258:   [PASS][7] -> [INCOMPLETE][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-hsw-g3258/igt@i915_selftest@l...@sanitycheck.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110277v1/fi-hsw-g3258/igt@i915_selftest@l...@sanitycheck.html
- fi-bsw-kefka:   [PASS][9] -> [INCOMPLETE][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-bsw-kefka/igt@i915_selftest@l...@sanitycheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110277v1/fi-bsw-kefka/igt@i915_selftest@l...@sanitycheck.html
- fi-elk-e7500:   [PASS][11] -> [INCOMPLETE][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-elk-e7500/igt@i915_selftest@l...@sanitycheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110277v1/fi-elk-e7500/igt@i915_selftest@l...@sanitycheck.html
- fi-glk-j4005:   [PASS][13] -> [INCOMPLETE][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-glk-j4005/igt@i915_selftest@l...@sanitycheck.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110277v1/fi-glk-j4005/igt@i915_selftest@l...@sanitycheck.html

  * igt@i915_selftest@live@uncore:
- fi-rkl-guc: [PASS][15] -> [INCOMPLETE][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-rkl-guc/igt@i915_selftest@l...@uncore.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110277v1/fi-rkl-guc/igt@i915_selftest@l...@uncore.html
- fi-skl-guc: [PASS][17] -> [INCOMPLETE][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-skl-guc/igt@i915_selftest@l...@uncore.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110277v1/fi-skl-guc/igt@i915_selftest@l...@uncore.html
- fi-rkl-11600:   [PASS][19] -> [INCOMPLETE][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-rkl-11600/igt@i915_selftest@l...@uncore.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110277v1/fi-rkl-11600/igt@i915_selftest@l...@uncore.html
- fi-adl-ddr5:[PASS][21] -> [INCOMPLETE][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-adl-ddr5/igt@i915_selftest@l...@uncore.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110277v1/fi-adl-ddr5/igt@i915_selftest@l...@uncore.html
- fi-cfl-guc: [PASS][23] -> [INCOMPLETE][24]
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-cfl-guc/igt@i915_selftest@l...@uncore.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110277v1/fi-cfl-guc/igt@i915_selftest@l...@uncore.html
- fi-skl-6700k2:  [PASS][25] -> [INCOMPLETE][26]
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-skl-6700k2/igt@i915_selftest@l...@uncore.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110277v1/fi-skl-6700k2/igt@i915_selftest@l...@uncore.html
  

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/display: Do both crawl and squash 
when changing cdclk
URL   : https://patchwork.freedesktop.org/series/110275/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12317 -> Patchwork_110275v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110275v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110275v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110275v1/index.html

Participating hosts (40 -> 39)
--

  Additional (1): fi-pnv-d510 
  Missing(2): fi-ctg-p8600 fi-cfl-8700k 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110275v1:

### CI changes ###

 Possible regressions 

  * boot:
- fi-bxt-dsi: [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-bxt-dsi/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110275v1/fi-bxt-dsi/boot.html

  

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@gt_mocs:
- {bat-rpls-1}:   [PASS][3] -> [DMESG-FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/bat-rpls-1/igt@i915_selftest@live@gt_mocs.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110275v1/bat-rpls-1/igt@i915_selftest@live@gt_mocs.html

  
Known issues


  Here are the changes found in Patchwork_110275v1 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot:
- fi-ilk-650: [FAIL][5] ([i915#7350]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-ilk-650/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110275v1/fi-ilk-650/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_close_race@basic-process:
- fi-icl-u2:  [PASS][7] -> [DMESG-WARN][8] ([i915#4890])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-icl-u2/igt@gem_close_r...@basic-process.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110275v1/fi-icl-u2/igt@gem_close_r...@basic-process.html

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u:   [PASS][9] -> [INCOMPLETE][10] ([i915#146])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110275v1/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-ilk-650: NOTRUN -> [SKIP][11] ([fdo#109271]) +19 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110275v1/fi-ilk-650/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@kms_chamelium@hdmi-edid-read:
- fi-ilk-650: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110275v1/fi-ilk-650/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_psr@primary_page_flip:
- fi-pnv-d510:NOTRUN -> [SKIP][13] ([fdo#109271]) +43 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110275v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0@smem:
- {bat-adlm-1}:   [DMESG-WARN][14] ([i915#2867]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110275v1/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html
- {bat-rpls-2}:   [DMESG-WARN][16] ([i915#6434]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/bat-rpls-2/igt@gem_exec_suspend@basic...@smem.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110275v1/bat-rpls-2/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@migrate:
- {bat-dg2-11}:   [DMESG-WARN][18] -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/bat-dg2-11/igt@i915_selftest@l...@migrate.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110275v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#146]: 

[Intel-gfx] ✗ Fi.CI.BAT: failure for Fix for two GuC issues

[Patchwork]

== Series Details ==

Series: Fix for two GuC issues
URL   : https://patchwork.freedesktop.org/series/110269/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12317 -> Patchwork_110269v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110269v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110269v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110269v1/index.html

Participating hosts (40 -> 39)
--

  Additional (3): fi-kbl-soraka fi-tgl-dsi fi-pnv-d510 
  Missing(4): fi-ctg-p8600 fi-rkl-11600 fi-icl-u2 fi-cfl-8700k 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110269v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gem_contexts:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110269v1/fi-kbl-soraka/igt@i915_selftest@live@gem_contexts.html

  
Known issues


  Here are the changes found in Patchwork_110269v1 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot:
- fi-ilk-650: [FAIL][2] ([i915#7350]) -> [PASS][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-ilk-650/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110269v1/fi-ilk-650/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [PASS][4] -> [INCOMPLETE][5] ([i915#7073])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110269v1/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html

  * igt@gem_exec_gttfill@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][6] ([fdo#109271]) +9 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110269v1/fi-kbl-soraka/igt@gem_exec_gttf...@basic.html

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u:   [PASS][7] -> [INCOMPLETE][8] ([i915#146])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110269v1/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110269v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110269v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-ilk-650: NOTRUN -> [SKIP][11] ([fdo#109271]) +19 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110269v1/fi-ilk-650/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-glk-j4005:   [PASS][12] -> [DMESG-FAIL][13] ([i915#5334])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110269v1/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][14] ([i915#1886])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110269v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][15] -> [INCOMPLETE][16] ([i915#4785])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110269v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-ilk-650: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110269v1/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-soraka:  NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110269v1/fi-kbl-soraka/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_psr@primary_page_flip:
- fi-pnv-d510:NOTRUN -> [SKIP][19] ([fdo#109271]) +43 similar issues
   [19]: 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: Add MC6 Wa_14017210380 for SAMedia

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: Add MC6 Wa_14017210380 for SAMedia
URL   : https://patchwork.freedesktop.org/series/110268/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12317 -> Patchwork_110268v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110268v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110268v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110268v1/index.html

Participating hosts (40 -> 40)
--

  Additional (2): fi-kbl-soraka fi-pnv-d510 
  Missing(2): fi-ctg-p8600 fi-cfl-8700k 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110268v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@late_gt_pm:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110268v1/fi-kbl-soraka/igt@i915_selftest@live@late_gt_pm.html

  
Known issues


  Here are the changes found in Patchwork_110268v1 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot:
- fi-ilk-650: [FAIL][2] ([i915#7350]) -> [PASS][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-ilk-650/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110268v1/fi-ilk-650/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110268v1/fi-kbl-soraka/igt@gem_exec_gttf...@basic.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110268v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110268v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [PASS][7] -> [INCOMPLETE][8] ([i915#7056])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110268v1/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-ilk-650: NOTRUN -> [SKIP][9] ([fdo#109271]) +19 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110268v1/fi-ilk-650/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][10] ([i915#1886])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110268v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][11] -> [INCOMPLETE][12] ([i915#4785])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110268v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- fi-rkl-guc: [PASS][13] -> [INCOMPLETE][14] ([i915#4983])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-rkl-guc/igt@i915_selftest@l...@hangcheck.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110268v1/fi-rkl-guc/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_busy@basic@modeset:
- fi-icl-u2:  [PASS][15] -> [DMESG-WARN][16] ([i915#4890])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-icl-u2/igt@kms_busy@ba...@modeset.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110268v1/fi-icl-u2/igt@kms_busy@ba...@modeset.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-ilk-650: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110268v1/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-soraka:  NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110268v1/fi-kbl-soraka/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [PASS][19] -> [FAIL][20] ([i915#6298])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   

Re: [Intel-gfx] [PULL] drm-intel-next

[Ville Syrjälä]

On Fri, Oct 28, 2022 at 02:22:33PM -0400, Rodrigo Vivi wrote:
> Hi Dave and Daniel,
> 
> Here goes the first chunk of drm-intel-next targeting 6.2
> 
> The highlight goes to Ville with many display related clean-up
> and improvement, some other MTL enabling work and many other
> fixes and small clean-ups.
> 
> drm-intel-next-2022-10-28:
...
> - ELD precompute and readout (Ville)

A slight clarification seems to be in order. The ELD
precompute+readout is in fact not in yet. This was just a pile
of cleanups and minor fixes. The real ELD stuff will come later,
once we figure out how we actually want to do it.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Add missing steering table terminators

[Lucas De Marchi]

On Fri, Oct 28, 2022 at 03:40:22PM -0700, Matt Roper wrote:

The termination entries were missing for a couple of the recently-added
MTL steering tables.

Fixes: f32898c94a10 ("drm/i915/xelpg: Add multicast steering")
Fixes: a7ec65fc7e83 ("drm/i915/xelpmp: Add multicast steering for media GT")


I was thinking if we would need separate commits so they can be
backported independently, but no... those commits were very close.


Signed-off-by: Matt Roper 



Reviewed-by: Lucas De Marchi 

Lucas De Marchi


---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c 
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 46cf2f3d1e8e..830edffe88cc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -128,11 +128,13 @@ static const struct intel_mmio_range 
xelpg_dss_steering_table[] = {
{ 0x00D800, 0x00D87F }, /* SLICE */
{ 0x00DC00, 0x00DCFF }, /* SLICE */
{ 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
+   {},
};

static const struct intel_mmio_range xelpmp_oaddrm_steering_table[] = {
{ 0x393200, 0x39323F },
{ 0x393400, 0x3934FF },
+   {},
};

void intel_gt_mcr_init(struct intel_gt *gt)
--
2.37.3

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/mtl: Add missing steering table terminators

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: Add missing steering table terminators
URL   : https://patchwork.freedesktop.org/series/110279/
State : warning

== Summary ==

Error: make htmldocs had i915 warnings
./drivers/gpu/drm/i915/i915_perf_types.h:319: warning: Function parameter or 
member 'lock' not described in 'i915_perf_stream'

[Intel-gfx] ✗ Fi.CI.IGT: failure for Add selftest for slpc tile interaction (rev2)

[Patchwork]

== Series Details ==

Series: Add selftest for slpc tile interaction (rev2)
URL   : https://patchwork.freedesktop.org/series/110248/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12315_full -> Patchwork_110248v2_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110248v2_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110248v2_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 9)
--

  Missing(2): pig-skl-6260u pig-glk-j5005 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110248v2_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_cursor_legacy@cursor-vs-flip@atomic:
- shard-skl:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-skl4/igt@kms_cursor_legacy@cursor-vs-f...@atomic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110248v2/shard-skl10/igt@kms_cursor_legacy@cursor-vs-f...@atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-skl:  NOTRUN -> [INCOMPLETE][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110248v2/shard-skl7/igt@kms_cursor_legacy@flip-vs-cur...@atomic-transitions-varying-size.html

  
Known issues


  Here are the changes found in Patchwork_110248v2_full that come from known 
issues:

### CI changes ###

 Possible fixes 

  * boot:
- shard-glk:  ([PASS][4], [PASS][5], [PASS][6], [PASS][7], 
[PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], 
[PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], 
[PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], 
[FAIL][26], [PASS][27], [PASS][28]) ([i915#4392]) -> ([PASS][29], [PASS][30], 
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], 
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], 
[PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk1/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk1/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk2/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk2/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk2/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk2/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk3/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk3/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk3/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk5/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk5/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk5/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk5/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk6/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk6/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk6/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk7/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk7/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk7/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk8/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk8/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk8/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk9/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk9/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/shard-glk9/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110248v2/shard-glk2/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110248v2/shard-glk5/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110248v2/shard-glk5/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110248v2/shard-glk3/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110248v2/shard-glk3/boot.html
 

[Intel-gfx] [PATCH] drm/i915/mtl: Add missing steering table terminators

[Matt Roper]

The termination entries were missing for a couple of the recently-added
MTL steering tables.

Fixes: f32898c94a10 ("drm/i915/xelpg: Add multicast steering")
Fixes: a7ec65fc7e83 ("drm/i915/xelpmp: Add multicast steering for media GT")
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c 
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 46cf2f3d1e8e..830edffe88cc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -128,11 +128,13 @@ static const struct intel_mmio_range 
xelpg_dss_steering_table[] = {
{ 0x00D800, 0x00D87F }, /* SLICE */
{ 0x00DC00, 0x00DCFF }, /* SLICE */
{ 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
+   {},
 };
 
 static const struct intel_mmio_range xelpmp_oaddrm_steering_table[] = {
{ 0x393200, 0x39323F },
{ 0x393400, 0x3934FF },
+   {},
 };
 
 void intel_gt_mcr_init(struct intel_gt *gt)
-- 
2.37.3

Re: [Intel-gfx] [RFC] i915: make the probe asynchronous

[Brian Norris]

Hi,

On Thu, Aug 16, 2018 at 03:40:38PM +0800, Feng Tang wrote:
> On Tue, Aug 14, 2018 at 11:39:48AM +0200, Takashi Iwai wrote:
> > FYI, the upcoming 4.19 will have the completion in audio side binding,
> > so this problem should be solved there.
> 
> Really a great news! thanks for sharing

For the record: that was merged as:

  f9b54e1961c7 ("ALSA: hda/i915: Allow delayed i915 audio component binding")

I'm also poking here in case somebody still had reason we shouldn't do
this now. I wrote up my own patch, and the looked for past discussions
like this one. Feel free to comment here if there's still a problem:

  [PATCH] drm/i915: Set PROBE_PREFER_ASYNCHRONOUS
  
https://lore.kernel.org/lkml/20221028145319.1.I87b119c576d486ad139faf1b7278d97e158aabe4@changeid/

Thanks,
Brian

[Intel-gfx] [PATCH] drm/i915: Set PROBE_PREFER_ASYNCHRONOUS

[Brian Norris]

This driver often takes a good 100ms to start, but in some particularly
bad cases takes more than 1 second.

In surveying risk for this driver, I poked around for cross-device
shared state, which can be a source of race conditions. GVT support
(intel_gvt_devices) seems potentially suspect, but it has an appropriate
mutex, and doesn't seem to care about ordering -- if devices are present
when the kvmgt module loads, they'll get picked up; and if they probe
later than kvmgt, they'll attach then.

Additionally, I see past discussions about this patch [1], which
concluded that there were problems at the time due to the way
hdac_i915.c called request_module("i915") and expected it to complete
probing [2]. Work has since been merged [3] to fix that problem.

This driver was pinpointed as part of a survey of drivers that take more
than 100ms in their initcall (i.e., are built in, and probing
synchronously) on a lab of ChromeOS systems.

[1] [RFC] i915: make the probe asynchronous
https://lore.kernel.org/all/20180604053219.2040-1-feng.t...@intel.com/

[2] https://lore.kernel.org/all/s5hin4d1e3f.wl-ti...@suse.de/

[3] Commit f9b54e1961c7 ("ALSA: hda/i915: Allow delayed i915 audio
component binding")

Signed-off-by: Brian Norris 
---

 drivers/gpu/drm/i915/i915_pci.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 38460a0bd7cb..1cb1f87aea86 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1371,7 +1371,10 @@ static struct pci_driver i915_pci_driver = {
.probe = i915_pci_probe,
.remove = i915_pci_remove,
.shutdown = i915_pci_shutdown,
-   .driver.pm = _pm_ops,
+   .driver = {
+   .pm = _pm_ops,
+   .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+   },
 };
 
 int i915_pci_register_driver(void)
-- 
2.38.1.273.g43a17bfeac-goog

Re: [Intel-gfx] [PATCH 2/2] drm/i915/dg2: Introduce Wa_18019271663

[Matt Atwood]

On Thu, Oct 27, 2022 at 02:28:53PM -0300, Gustavo Sousa wrote:
> On Tue, Oct 25, 2022 at 11:03:35AM -0700, Matt Atwood wrote:
> > Wa_18019271663 applies to all DG2 steppings and skus.
> > 
> > Bspec:45809
> 
> Could we also add the reference to the BSpec containing the WA description?
Good catch bspec ref should be 66622
> 
> > 
> > Signed-off-by: Matt Atwood 
> > ---
> >  drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
> >  2 files changed, 7 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
> > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index e8372d4cd548..46035503068c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -421,9 +421,10 @@
> >  #define   RC_OP_FLUSH_ENABLE   (1 << 0)
> >  #define   HIZ_RAW_STALL_OPT_DISABLE(1 << 2)
> >  #define CACHE_MODE_1   _MMIO(0x7004) /* IVB+ */
> > -#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE(1 << 6)
> > -#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE(1 << 6)
> > -#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   (1 << 1)
> > +#define   MSAA_OPTIMIZATION_REDUC_DISABLE  REG_BIT(11)
> > +#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLEREG_BIT(6)
> > +#define   GEN8_4x4_STC_OPTIMIZATION_DISABLEREG_BIT(6)
> > +#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   REG_BIT(1)
> >  
> >  #define GEN7_GT_MODE   _MMIO(0x7008)
> >  #define   GEN9_IZ_HASHING_MASK(slice)  (0x3 << ((slice) * 2))
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index ced3a26cf7e7..9f39b7758ff3 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -750,6 +750,9 @@ static void dg2_ctx_workarounds_init(struct 
> > intel_engine_cs *engine,
> >  
> > /* Wa_15010599737:dg2 */
> > wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
> > +
> > +   /* Wa_18019271663:dg2 */
> > +   wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
> >  }
> >  
> >  static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
> > -- 
> > 2.37.3
> > 

[Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL

[Anusha Srivatsa]

As per bSpec MTL has 38.4 MHz Reference clock.
Addin gthe cdclk tables and cdclk_funcs that MTL
will use.

v2: Revert to using bxt_get_cdclk()

BSpec: 65243

Cc: Clint Taylor 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d79cf282faa8..54ac7f9a1253 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1345,6 +1345,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = 
{
{}
 };
 
+static const struct intel_cdclk_vals mtl_cdclk_table[] = {
+   { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, 
.waveform = 0xad5a },
+   { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, 
.waveform = 0xb6b6 },
+   { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, 
.waveform = 0x },
+   { .refclk = 38400, .cdclk = 48, .divider = 2, .ratio = 25, 
.waveform = 0x },
+   { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, 
.waveform = 0x },
+   { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, 
.waveform = 0x },
+   {}
+};
+
 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 {
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3159,6 +3169,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
 }
 
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+   .get_cdclk = bxt_get_cdclk,
+   .set_cdclk = bxt_set_cdclk,
+   .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+   .calc_voltage_level = tgl_calc_voltage_level,
+};
+
 static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
.get_cdclk = bxt_get_cdclk,
.set_cdclk = bxt_set_cdclk,
@@ -3294,7 +3311,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = 
{
  */
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
-   if (IS_DG2(dev_priv)) {
+   if (IS_METEORLAKE(dev_priv)) {
+   dev_priv->display.funcs.cdclk = _cdclk_funcs;
+   dev_priv->display.cdclk.table = mtl_cdclk_table;
+   } else if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
-- 
2.25.1

[Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk

[Anusha Srivatsa]

From: Ville Syrjälä 

For MTL, changing cdclk from between certain frequencies has
both squash and crawl. Use the current cdclk config and
the new(desired) cdclk config to construtc a mid cdclk config.
Set the cdclk twice:
- Current cdclk -> mid cdclk
- mid cdclk -> desired cdclk

v2: Add check in intel_modeset_calc_cdclk() to avoid cdclk
change via modeset for platforms that support squash_crawl sequences(Ville)

v3: Add checks for:
- scenario where only slow clock is used and
cdclk is actually 0 (bringing up display).
- PLLs are on before looking up the waveform.
- Squash and crawl capability checks.(Ville)

v4: Rebase
- Move checks to be more consistent (Ville)
- Add comments (Bala)
v5:
- Further small changes. Move checks around.
- Make if-else better looking (Ville)

Cc: Balasubramani Vivekanandan 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 156 +
 1 file changed, 128 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index eada931cb1c8..d79cf282faa8 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1716,37 +1716,74 @@ static void dg2_cdclk_squash_program(struct 
drm_i915_private *i915,
intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
 }
 
-static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *cdclk_config,
- enum pipe pipe)
+static int cdclk_squash_divider(u16 waveform)
+{
+   return hweight16(waveform ?: 0x);
+}
+
+static bool cdclk_crawl_and_squash(struct drm_i915_private *i915,
+  const struct intel_cdclk_config 
*old_cdclk_config,
+  const struct intel_cdclk_config 
*new_cdclk_config,
+  struct intel_cdclk_config *mid_cdclk_config)
+{
+   u16 old_waveform, new_waveform, mid_waveform;
+   int size = 16;
+   int div = 2;
+
+   /* Return if both Squash and Crawl are not present */
+   if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
+   return false;
+
+   old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
+   new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
+
+   /* Return if Squash only or Crawl only is the desired action */
+   if (old_cdclk_config->vco <= 0 || new_cdclk_config->vco <= 0 ||
+   old_cdclk_config->vco == new_cdclk_config->vco ||
+   old_waveform == new_waveform)
+   return false;
+
+   *mid_cdclk_config = *new_cdclk_config;
+
+   /* Populate the mid_cdclk_config accordingly.
+* - If moving to a higher cdclk, the desired action is squashing.
+* The mid cdclk config should have the new (squash) waveform.
+* - If moving to a lower cdclk, the desired action is crawling.
+* The mid cdclk config should have the new vco.
+*/
+
+   if (cdclk_squash_divider(new_waveform) > 
cdclk_squash_divider(old_waveform)) {
+   mid_cdclk_config->vco = old_cdclk_config->vco;
+   mid_waveform = new_waveform;
+   } else {
+   mid_cdclk_config->vco = new_cdclk_config->vco;
+   mid_waveform = old_waveform;
+   }
+
+   mid_cdclk_config->cdclk = 
DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
+   mid_cdclk_config->vco, size 
* div);
+
+   /* make sure the mid clock came out sane */
+
+   drm_WARN_ON(>drm, mid_cdclk_config->cdclk <
+   min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
+   drm_WARN_ON(>drm, mid_cdclk_config->cdclk >
+   i915->display.cdclk.max_cdclk_freq);
+   drm_WARN_ON(>drm, cdclk_squash_waveform(i915, 
mid_cdclk_config->cdclk) !=
+   mid_waveform);
+
+   return true;
+}
+
+static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
+  const struct intel_cdclk_config *cdclk_config,
+  enum pipe pipe)
 {
int cdclk = cdclk_config->cdclk;
int vco = cdclk_config->vco;
u32 val;
u16 waveform;
int clock;
-   int ret;
-
-   /* Inform power controller of upcoming frequency change. */
-   if (DISPLAY_VER(dev_priv) >= 11)
-   ret = skl_pcode_request(_priv->uncore, 
SKL_PCODE_CDCLK_CONTROL,
-   SKL_CDCLK_PREPARE_FOR_CHANGE,
-   SKL_CDCLK_READY_FOR_CHANGE,
-   SKL_CDCLK_READY_FOR_CHANGE, 3);
-   else
-   /*
-* BSpec requires us to wait up to 150usec, but that leads to
-* timeouts; the 2ms used here is based on experiment.
-*/
-   

Re: [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk

[Srivatsa, Anusha]

> -Original Message-
> From: Ville Syrjälä 
> Sent: Friday, October 28, 2022 2:05 AM
> To: Srivatsa, Anusha 
> Cc: intel-gfx@lists.freedesktop.org; Vivekanandan, Balasubramani
> 
> Subject: Re: [PATCH 1/2] drm/i915/display: Do both crawl and squash when
> changing cdclk
> 
> On Wed, Oct 26, 2022 at 04:22:56PM -0700, Anusha Srivatsa wrote:
> > From: Ville Syrjälä 
> >
> > For MTL, changing cdclk from between certain frequencies has both
> > squash and crawl. Use the current cdclk config and the new(desired)
> > cdclk config to construtc a mid cdclk config.
> > Set the cdclk twice:
> > - Current cdclk -> mid cdclk
> > - mid cdclk -> desired cdclk
> >
> > v2: Add check in intel_modeset_calc_cdclk() to avoid cdclk change via
> > modeset for platforms that support squash_crawl sequences(Ville)
> >
> > v3: Add checks for:
> > - scenario where only slow clock is used and cdclk is actually 0
> > (bringing up display).
> > - PLLs are on before looking up the waveform.
> > - Squash and crawl capability checks.(Ville)
> >
> > v4: Rebase
> > - Move checks to be more consistent (Ville)
> > - Add comments (Bala)
> >
> > Cc: Balasubramani Vivekanandan
> 
> > Signed-off-by: Anusha Srivatsa 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 157
> > +
> >  1 file changed, 129 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index eada931cb1c8..6a775367f02a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1716,37 +1716,74 @@ static void dg2_cdclk_squash_program(struct
> drm_i915_private *i915,
> > intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);  }
> >
> > -static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> > - const struct intel_cdclk_config *cdclk_config,
> > - enum pipe pipe)
> > +static int cdclk_squash_divider(u16 waveform) {
> > +   return hweight16(waveform ?: 0x); }
> > +
> > +static bool cdclk_crawl_and_squash(struct drm_i915_private *i915,
> > +  const struct intel_cdclk_config
> *old_cdclk_config,
> > +  const struct intel_cdclk_config
> *new_cdclk_config,
> > +  struct intel_cdclk_config *mid_cdclk_config)
> {
> > +   u16 old_waveform, new_waveform, mid_waveform;
> > +   int size = 16;
> > +   int div = 2;
> > +
> > +   /* Return if both Squash and Crawl are not present */
> > +   if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
> > +   return false;
> > +
> > +   /* Return if Squash only or Crawl only is the desired action */
> > +   if (old_cdclk_config->vco <= 0 || new_cdclk_config->vco <= 0 ||
> > +   old_cdclk_config->vco == new_cdclk_config->vco ||
> > +   old_waveform == new_waveform)
> 
> Those are not yet initialized.
*facepalm*

> > +   return false;
> > +
> > +   old_waveform = cdclk_squash_waveform(i915, old_cdclk_config-
> >cdclk);
> > +   new_waveform = cdclk_squash_waveform(i915, new_cdclk_config-
> >cdclk);
> > +
> > +   *mid_cdclk_config = *new_cdclk_config;
> > +
> > +   /* Populate the mid_cdclk_config accordingly.
> > +* - If moving to a higher cdclk, the desired action is squashing.
> > +* The mid cdclk config should have the new (squash) waveform.
> > +* - If moving to a lower cdclk, the desired action is crawling.
> > +* The mid cdclk config should have the new vco.
> > +*/
> > +
> > +   if (cdclk_squash_divider(new_waveform) >
> cdclk_squash_divider(old_waveform)) {
> > +   mid_cdclk_config->vco = old_cdclk_config->vco;
> > +   mid_waveform = new_waveform;
> > +   } else {
> > +   mid_cdclk_config->vco = new_cdclk_config->vco;
> > +   mid_waveform = old_waveform;
> > +   }
> > +
> > +   mid_cdclk_config->cdclk =
> DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
> > +   mid_cdclk_config->vco, size
> * div);
> > +
> > +   /* make sure the mid clock came out sane */
> > +
> > +   drm_WARN_ON(>drm, mid_cdclk_config->cdclk <
> > +   min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
> > +   drm_WARN_ON(>drm, mid_cdclk_config->cdclk >
> > +   i915->display.cdclk.max_cdclk_freq);
> > +   drm_WARN_ON(>drm, cdclk_squash_waveform(i915,
> mid_cdclk_config->cdclk) !=
> > +   mid_waveform);
> > +
> > +   return true;
> > +}
> > +
> > +static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> > +  const struct intel_cdclk_config *cdclk_config,
> > +  enum pipe pipe)
> >  {
> > int cdclk = cdclk_config->cdclk;
> > int vco = cdclk_config->vco;
> > u32 val;
> > u16 waveform;
> > int clock;
> > -   int ret;
> > -
> > -   /* Inform power controller of upcoming frequency change. */
> > -   

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Fix for two GuC issues

[Patchwork]

== Series Details ==

Series: Fix for two GuC issues
URL   : https://patchwork.freedesktop.org/series/110269/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add MC6 Wa_14017210380 for SAMedia

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: Add MC6 Wa_14017210380 for SAMedia
URL   : https://patchwork.freedesktop.org/series/110268/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add MC6 Wa_14017210380 for SAMedia

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: Add MC6 Wa_14017210380 for SAMedia
URL   : https://patchwork.freedesktop.org/series/110268/
State : warning

== Summary ==

Error: dim checkpatch failed
33ed282c8b12 drm/i915/mtl: Add MC6 Wa_14017210380 for SAMedia
-:118: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible 
side-effects?
#118: FILE: drivers/gpu/drm/i915/i915_drv.h:743:
+#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
+   (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) 
&& \
+IS_GRAPHICS_STEP(__i915, since, until))

total: 0 errors, 0 warnings, 1 checks, 101 lines checked

[Intel-gfx] [PATCH 1/2] drm/i915/guc: Properly initialise kernel contexts

[John . C . Harrison]

From: John Harrison 

If a context has already been registered prior to first submission
then context init code was not being called. The noticeable effect of
that was the scheduling priority was left at zero (meaning super high
priority) instead of being set to normal. This would occur with
kernel contexts at start of day as they are manually pinned up front
rather than on first submission. So add a call to initialise those
when they are pinned.

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 4ccb29f9ac55c..941613be3b9dd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4111,6 +4111,9 @@ static inline void guc_kernel_context_pin(struct 
intel_guc *guc,
if (context_guc_id_invalid(ce))
pin_guc_id(guc, ce);
 
+   if (!test_bit(CONTEXT_GUC_INIT, >flags))
+   guc_context_init(ce);
+
try_context_registration(ce, true);
 }
 
-- 
2.37.3

[Intel-gfx] [PATCH 2/2] drm/i915/guc: Don't deadlock busyness stats vs reset

[John . C . Harrison]

From: John Harrison 

The engine busyness stats has a worker function to do things like
64bit extend the 32bit hardware counters. The GuC's reset prepare
function flushes out this worker function to ensure no corruption
happens during the reset. Unforunately, the worker function has an
infinite wait for active resets to finish before doing its work. Thus
a deadlock would occur if the worker function had actually started
just as the reset starts.

Update the worker to abort if a reset is in progress rather than
waiting for it to complete. It will still acquire the reset lock in
the case where a reset was not already in progress. So the processing
is still safe from corruption, but the deadlock can no longer occur.

Signed-off-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/intel_reset.c | 15 ++-
 drivers/gpu/drm/i915/gt/intel_reset.h |  1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c |  6 --
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 3159df6cdd492..2f48c6e4420ea 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1407,7 +1407,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
intel_runtime_pm_put(gt->uncore->rpm, wakeref);
 }
 
-int intel_gt_reset_trylock(struct intel_gt *gt, int *srcu)
+static int _intel_gt_reset_trylock(struct intel_gt *gt, int *srcu, bool retry)
 {
might_lock(>reset.backoff_srcu);
might_sleep();
@@ -1416,6 +1416,9 @@ int intel_gt_reset_trylock(struct intel_gt *gt, int *srcu)
while (test_bit(I915_RESET_BACKOFF, >reset.flags)) {
rcu_read_unlock();
 
+   if (!retry)
+   return -EBUSY;
+
if (wait_event_interruptible(gt->reset.queue,
 !test_bit(I915_RESET_BACKOFF,
   >reset.flags)))
@@ -1429,6 +1432,16 @@ int intel_gt_reset_trylock(struct intel_gt *gt, int 
*srcu)
return 0;
 }
 
+int intel_gt_reset_trylock_noretry(struct intel_gt *gt, int *srcu)
+{
+   return _intel_gt_reset_trylock(gt, srcu, false);
+}
+
+int intel_gt_reset_trylock(struct intel_gt *gt, int *srcu)
+{
+   return _intel_gt_reset_trylock(gt, srcu, true);
+}
+
 void intel_gt_reset_unlock(struct intel_gt *gt, int tag)
 __releases(>reset.backoff_srcu)
 {
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h 
b/drivers/gpu/drm/i915/gt/intel_reset.h
index adc734e673870..7f863726eb6a2 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -38,6 +38,7 @@ int __intel_engine_reset_bh(struct intel_engine_cs *engine,
 
 void __i915_request_reset(struct i915_request *rq, bool guilty);
 
+int __must_check intel_gt_reset_trylock_noretry(struct intel_gt *gt, int 
*srcu);
 int __must_check intel_gt_reset_trylock(struct intel_gt *gt, int *srcu);
 void intel_gt_reset_unlock(struct intel_gt *gt, int tag);
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 941613be3b9dd..1fa1bc7dde3df 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1401,9 +1401,11 @@ static void guc_timestamp_ping(struct work_struct *wrk)
 
/*
 * Synchronize with gt reset to make sure the worker does not
-* corrupt the engine/guc stats.
+* corrupt the engine/guc stats. NB: can't actually block waiting
+* for a reset to complete as the reset requires flushing out
+* any running worker thread. So waiting would deadlock.
 */
-   ret = intel_gt_reset_trylock(gt, );
+   ret = intel_gt_reset_trylock_noretry(gt, );
if (ret)
return;
 
-- 
2.37.3

[Intel-gfx] [PATCH 0/2] Fix for two GuC issues

[John . C . Harrison]

From: John Harrison 

Fix for a deadlock issue between the GuC busyness stats worker and GT
resets. Also fix kernel contexts not getting the correct scheduling
priority at start of day.

Signed-off-by: John Harrison 


John Harrison (2):
  drm/i915/guc: Properly initialise kernel contexts
  drm/i915/guc: Don't deadlock busyness stats vs reset

 drivers/gpu/drm/i915/gt/intel_reset.c | 15 ++-
 drivers/gpu/drm/i915/gt/intel_reset.h |  1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c |  9 +++--
 3 files changed, 22 insertions(+), 3 deletions(-)

-- 
2.37.3

[Intel-gfx] ✗ Fi.CI.IGT: failure for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev5)

[Patchwork]

== Series Details ==

Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev5)
URL   : https://patchwork.freedesktop.org/series/107550/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12314_full -> Patchwork_107550v5_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_107550v5_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_107550v5_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_107550v5_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_schedule@wide@rcs0:
- shard-apl:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-apl6/igt@gem_exec_schedule@w...@rcs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v5/shard-apl8/igt@gem_exec_schedule@w...@rcs0.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-rkl}:[PASS][3] -> [WARN][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-rkl-4/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v5/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html

  
Known issues


  Here are the changes found in Patchwork_107550v5_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-glk:  ([PASS][5], [PASS][6], [PASS][7], [PASS][8], 
[PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], 
[PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], 
[PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], 
[PASS][27], [PASS][28], [PASS][29]) -> ([PASS][30], [PASS][31], [PASS][32], 
[PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], 
[PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], 
[PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], 
[PASS][51], [PASS][52], [FAIL][53], [PASS][54]) ([i915#4392])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk9/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk9/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk9/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk8/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk8/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk8/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk7/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk7/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk7/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk6/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk6/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk6/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk6/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk5/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk5/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk5/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk3/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk3/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk3/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk2/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk2/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk2/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk1/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk1/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk1/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v5/shard-glk1/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v5/shard-glk1/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v5/shard-glk1/boot.html
   [33]: 

[Intel-gfx] [PATCH] drm/i915/mtl: Add MC6 Wa_14017210380 for SAMedia

[Badal Nilawar]

This workaround is added for Media Tile of MTL A step. It is to help
pcode workaround which handles the hardware bug seen on CXL splitter
during package C2/C3 transitins due to MC6 entry/exit. As a part of
workaround pcode expect kmd to send mailbox message "media busy" when
components of Media tile is in use and "media not busy" when not in use.
As per workaround description gucrc need to be disabled so enabled
host based RC for Media tile.

HSD: 14017210380

Cc: Rodrigo Vivi 
Cc: Radhakrishna Sripada 
Cc: Vinay Belgaumkar 
Cc: Chris Wilson 
Signed-off-by: Badal Nilawar 
---
 drivers/gpu/drm/i915/gt/intel_gt_pm.c | 33 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 13 -
 drivers/gpu/drm/i915/i915_drv.h   |  4 +++
 drivers/gpu/drm/i915/i915_reg.h   |  9 +++
 4 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c 
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index f553e2173bda..398dbeb298ca 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -19,10 +19,37 @@
 #include "intel_rc6.h"
 #include "intel_rps.h"
 #include "intel_wakeref.h"
+#include "intel_pcode.h"
 #include "pxp/intel_pxp_pm.h"
 
 #define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2)
 
+/*
+ * Wa_14017210380: mtl
+ */
+
+static bool mtl_needs_media_mc6_wa(struct intel_gt *gt)
+{
+   return (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
+   gt->type == GT_MEDIA);
+}
+
+static void mtl_mc6_wa_media_busy(struct intel_gt *gt)
+{
+   if (mtl_needs_media_mc6_wa(gt))
+   snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE,
+ PCODE_MBOX_GT_STATE_MEDIA_BUSY,
+ PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0);
+}
+
+static void mtl_mc6_wa_media_not_busy(struct intel_gt *gt)
+{
+   if (mtl_needs_media_mc6_wa(gt))
+   snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE,
+ PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY,
+ PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0);
+}
+
 static void user_forcewake(struct intel_gt *gt, bool suspend)
 {
int count = atomic_read(>user_wakeref);
@@ -70,6 +97,9 @@ static int __gt_unpark(struct intel_wakeref *wf)
 
GT_TRACE(gt, "\n");
 
+   /* Wa_14017210380: mtl */
+   mtl_mc6_wa_media_busy(gt);
+
/*
 * It seems that the DMC likes to transition between the DC states a lot
 * when there are no connected displays (no active power domains) during
@@ -119,6 +149,9 @@ static int __gt_park(struct intel_wakeref *wf)
GEM_BUG_ON(!wakeref);
intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref);
 
+   /* Wa_14017210380: mtl */
+   mtl_mc6_wa_media_not_busy(gt);
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
index 8f8dd05835c5..cc6356ff84a5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
@@ -11,9 +11,20 @@
 
 static bool __guc_rc_supported(struct intel_guc *guc)
 {
+   struct intel_gt *gt = guc_to_gt(guc);
+
+   /*
+* Wa_14017210380: mtl
+* Do not enable gucrc to avoid additional interrupts which
+* may disrupt pcode wa.
+*/
+   if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
+   gt->type == GT_MEDIA)
+   return false;
+
/* GuC RC is unavailable for pre-Gen12 */
return guc->submission_supported &&
-   GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
+   GRAPHICS_VER(gt->i915) >= 12;
 }
 
 static bool __guc_rc_selected(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 05b3300cc4ed..659b92382ff2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -740,6 +740,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 
+#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
+   (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) 
&& \
+IS_GRAPHICS_STEP(__i915, since, until))
+
 /*
  * DG2 hardware steppings are a bit unusual.  The hardware design was forked to
  * create three variants (G10, G11, and G12) which each have distinct
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c0da50c0dc7..abe62cea083d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6678,6 +6678,15 @@
 /*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
 #define PCODE_MBOX_DOMAIN_NONE 0x0
 #define PCODE_MBOX_DOMAIN_MEDIAFF  0x3
+
+/* Wa_14017210380: mtl */
+#define   PCODE_MBOX_GT_STATE  0x50
+/* sub-commands (param1) 

Re: [Intel-gfx] [PATCH v1 3/7] vfio/ccw: move private initialization to callback

[Eric Farman]

On Fri, 2022-10-28 at 14:52 -0400, Matthew Rosato wrote:
> On 10/19/22 12:21 PM, Eric Farman wrote:
> > There's already a device initialization callback that is
> > used to initialize the release completion workaround.
> 
> As discussed off-list, maybe clarify what callback you're talking
> about here and/or reference the commit that added it.

Agreed. Will point out that it's private->release_comp, introduced with
commit ebb72b765fb49 ("vfio/ccw: Use the new device life cycle
helpers")

> 
> > 
> > Move the other elements of the vfio_ccw_private struct that
> > require distinct initialization over to that routine.
> > 
> > Signed-off-by: Eric Farman 
> > ---
> >  drivers/s390/cio/vfio_ccw_drv.c | 57 +++--
> > 
> >  drivers/s390/cio/vfio_ccw_ops.c | 43 ++
> >  drivers/s390/cio/vfio_ccw_private.h |  7 +++-
> >  3 files changed, 55 insertions(+), 52 deletions(-)
> > 
> > diff --git a/drivers/s390/cio/vfio_ccw_drv.c
> > b/drivers/s390/cio/vfio_ccw_drv.c
> > index 4ee953c8ae39..cc9ed2fd970f 100644
> > --- a/drivers/s390/cio/vfio_ccw_drv.c
> > +++ b/drivers/s390/cio/vfio_ccw_drv.c
> > @@ -24,10 +24,10 @@
> >  #include "vfio_ccw_private.h"
> >  
> >  struct workqueue_struct *vfio_ccw_work_q;
> > -static struct kmem_cache *vfio_ccw_io_region;
> > -static struct kmem_cache *vfio_ccw_cmd_region;
> > -static struct kmem_cache *vfio_ccw_schib_region;
> > -static struct kmem_cache *vfio_ccw_crw_region;
> > +struct kmem_cache *vfio_ccw_io_region;
> > +struct kmem_cache *vfio_ccw_cmd_region;
> > +struct kmem_cache *vfio_ccw_schib_region;
> > +struct kmem_cache *vfio_ccw_crw_region;
> >  
> >  debug_info_t *vfio_ccw_debug_msg_id;
> >  debug_info_t *vfio_ccw_debug_trace_id;
> > @@ -74,7 +74,7 @@ int vfio_ccw_sch_quiesce(struct subchannel *sch)
> > return ret;
> >  }
> >  
> > -static void vfio_ccw_sch_io_todo(struct work_struct *work)
> > +void vfio_ccw_sch_io_todo(struct work_struct *work)
> >  {
> > struct vfio_ccw_private *private;
> > struct irb *irb;
> > @@ -110,7 +110,7 @@ static void vfio_ccw_sch_io_todo(struct
> > work_struct *work)
> > eventfd_signal(private->io_trigger, 1);
> >  }
> >  
> > -static void vfio_ccw_crw_todo(struct work_struct *work)
> > +void vfio_ccw_crw_todo(struct work_struct *work)
> >  {
> > struct vfio_ccw_private *private;
> >  
> > @@ -154,52 +154,7 @@ static struct vfio_ccw_private
> > *vfio_ccw_alloc_private(struct subchannel *sch)
> > if (!private)
> > return ERR_PTR(-ENOMEM);
> 
> Not sure we really still need vfio_ccw_alloc_private() now or whether
> you can just kzalloc() inline right in vfio_ccw_sch_probe()

Fair. It ends up ends up getting scrapped in patch 6 anyway, but that
might clean things up just a smidge more. Will give it a whirl.

> Either way:
> 
> Reviewed-by: Matthew Rosato 

Thanks!

> 
> 
> >  
> > -   mutex_init(>io_mutex);
> > -   private->state = VFIO_CCW_STATE_STANDBY;
> > -   INIT_LIST_HEAD(>crw);
> > -   INIT_WORK(>io_work, vfio_ccw_sch_io_todo);
> > -   INIT_WORK(>crw_work, vfio_ccw_crw_todo);
> > -
> > -   private->cp.guest_cp = kcalloc(CCWCHAIN_LEN_MAX,
> > sizeof(struct ccw1),
> > -  GFP_KERNEL);
> > -   if (!private->cp.guest_cp)
> > -   goto out_free_private;
> > -
> > -   private->io_region = kmem_cache_zalloc(vfio_ccw_io_region,
> > -  GFP_KERNEL |
> > GFP_DMA);
> > -   if (!private->io_region)
> > -   goto out_free_cp;
> > -
> > -   private->cmd_region =
> > kmem_cache_zalloc(vfio_ccw_cmd_region,
> > -   GFP_KERNEL |
> > GFP_DMA);
> > -   if (!private->cmd_region)
> > -   goto out_free_io;
> > -
> > -   private->schib_region =
> > kmem_cache_zalloc(vfio_ccw_schib_region,
> > - GFP_KERNEL |
> > GFP_DMA);
> > -
> > -   if (!private->schib_region)
> > -   goto out_free_cmd;
> > -
> > -   private->crw_region =
> > kmem_cache_zalloc(vfio_ccw_crw_region,
> > -   GFP_KERNEL |
> > GFP_DMA);
> > -
> > -   if (!private->crw_region)
> > -   goto out_free_schib;
> > return private;
> > -
> > -out_free_schib:
> > -   kmem_cache_free(vfio_ccw_schib_region, private-
> > >schib_region);
> > -out_free_cmd:
> > -   kmem_cache_free(vfio_ccw_cmd_region, private->cmd_region);
> > -out_free_io:
> > -   kmem_cache_free(vfio_ccw_io_region, private->io_region);
> > -out_free_cp:
> > -   kfree(private->cp.guest_cp);
> > -out_free_private:
> > -   mutex_destroy(>io_mutex);
> > -   kfree(private);
> > -   return ERR_PTR(-ENOMEM);
> >  }
> >  
> >  static void vfio_ccw_free_private(struct vfio_ccw_private
> > *private)
> > diff --git a/drivers/s390/cio/vfio_ccw_ops.c
> > 

Re: [Intel-gfx] [PATCH 10/10] iommufd: Allow iommufd to supply /dev/vfio/vfio

[Jason Gunthorpe]

On Wed, Oct 26, 2022 at 03:31:33PM -0600, Alex Williamson wrote:
> On Tue, 25 Oct 2022 15:50:45 -0300
> Jason Gunthorpe  wrote:
> 
> > If the VFIO container is compiled out, give a kconfig option for iommufd
> > to provide the miscdev node with the same name and permissions as vfio
> > uses.
> > 
> > The compatibility node supports the same ioctls as VFIO and automatically
> > enables the VFIO compatible pinned page accounting mode.
> 
> I think I'd like to see some sort of breadcrumb when /dev/vfio/vfio is
> provided by something other than the vfio container code.  If we intend
> to include this before P2P is resolved, that breadcrumb 

I don't belive I can get P2P done soon enough. I plan to do it after
this is merged. Right now these two series are taking all my time.

> (dmesg I'm guessing) might also list any known limitations of the
> compatibility to save time with debugging.  Thanks,

Yes, that makes sense.

Do you want a dmesg at module load time, on every open, or a sysfs
something? What seems like it would make it into a bug report?

Thanks,
Jason

Re: [Intel-gfx] [PATCH 04/10] vfio: Move storage of allow_unsafe_interrupts to vfio_main.c

[Jason Gunthorpe]

On Wed, Oct 26, 2022 at 03:24:42PM -0600, Alex Williamson wrote:
> On Tue, 25 Oct 2022 15:17:10 -0300
> Jason Gunthorpe  wrote:
> 
> > This legacy module knob has become uAPI, when set on the vfio_iommu_type1
> > it disables some security protections in the iommu drivers. Move the
> > storage for this knob to vfio_main.c so that iommufd can access it too.
> 
> I don't really understand this, we're changing the behavior of the
> iommufd_device_attach() operation based on the modules options of
> vfio_iommu_type1, 

The specific reason it was done is that we had a misconfigured test VM
in the farm that needed it, and that VM has since been fixed. But it
did highlight we should try to preserve this in some way.

> which may not be loaded or even compiled into the
> kernel.  Our compatibility story falls apart when VFIO_CONTAINER is not
> set, iommufd sneaks in to usurp /dev/vfio/vfio, and the user's module
> options for type1 go unprocessed.

There are two aspects here, trying to preseve the
allow_unsafe_interrupts knob as it is already as some ABI in the best
way we can.

And the second is how do we make this work in the new world where
there may be no type 1 module at all. This patch is not trying to
address that topic. I am expecting a range of small adjustments before
VFIO_CONTAINER=n becomes really fully viable.

> I hate to suggest that type1 becomes a module that does nothing more
> than maintain consistency of this variable when the full type1 isn't
> available, but is that what we need to do?

It is one idea, it depends how literal you want to be on "module
parameters are ABI". IMHO it is a weak form of ABI and the need of
this paramter in particular is not that common in modern times, AFAIK.

So perhaps we just also expose it through vfio.ko and expect people to
migrate. That would give a window were both options are available.

Jason

[Intel-gfx] [PULL] drm-intel-next

[Rodrigo Vivi]

Hi Dave and Daniel,

Here goes the first chunk of drm-intel-next targeting 6.2

The highlight goes to Ville with many display related clean-up
and improvement, some other MTL enabling work and many other
fixes and small clean-ups.

drm-intel-next-2022-10-28:
- Hotplug code clean-up and organization (Jani, Gustavo)
- More VBT specific code clean-up, doc, organization,
  and improvements (Ville)
- More MTL enabling work (Matt, RK, Anusha, Jose)
- FBC related clean-ups and improvements (Ville)
- Removing unused sw_fence_await_reservation (Niranjana)
- Big chunch of display house clean-up (Ville)
- Many Watermark fixes and clean-ups (Ville)
- Fix device info for devices without display (Jani)
- Fix TC port PLLs after readout (Ville)
- DPLL ID clean-ups (Ville)
- Prep work for finishing (de)gamma readout (Ville)
- PSR fixes and improvements (Jouni, Jose)
- Reject excessive dotclocks early (Ville)
- DRRS related improvements (Ville)
- Simplify uncore register updates (Andrzej)
- Fix simulated GPU reset wrt. encoder HW readout (Imre)
- Add a ADL-P workaround (Jose)
- Fix clear mask in GEN7_MISCCPCTL update (Andrzej)
- Temporarily disable runtime_pm for discrete (Anshuman)
- Improve fbdev debugs (Nirmoy)
- Fix DP FRL link training status (Ankit)
- Other small display fixes (Ankit, Suraj)
- Allow panel fixed modes to have differing sync
  polarities (Ville)
- Clean up crtc state flag checks (Ville)
- Fix race conditions during DKL PHY accesses (Imre)
- Prep-work for cdclock squash and crawl modes (Anusha)
- ELD precompute and readout (Ville)

Thanks,
Rodrigo.

The following changes since commit 21f0b7dabf9c358e75a539b5554c0375bf1abe0a:

  drm/i915: Fix return type of mode_valid function hook (2022-09-15 10:28:55 
+0300)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2022-10-28

for you to fetch changes up to a6ebd538364b1e9e6048faaafbc0188172ed50c3:

  drm/i915/sdvo: Fix debug print (2022-10-28 14:46:21 +0300)


- Hotplug code clean-up and organization (Jani, Gustavo)
- More VBT specific code clean-up, doc, organization,
  and improvements (Ville)
- More MTL enabling work (Matt, RK, Anusha, Jose)
- FBC related clean-ups and improvements (Ville)
- Removing unused sw_fence_await_reservation (Niranjana)
- Big chunch of display house clean-up (Ville)
- Many Watermark fixes and clean-ups (Ville)
- Fix device info for devices without display (Jani)
- Fix TC port PLLs after readout (Ville)
- DPLL ID clean-ups (Ville)
- Prep work for finishing (de)gamma readout (Ville)
- PSR fixes and improvements (Jouni, Jose)
- Reject excessive dotclocks early (Ville)
- DRRS related improvements (Ville)
- Simplify uncore register updates (Andrzej)
- Fix simulated GPU reset wrt. encoder HW readout (Imre)
- Add a ADL-P workaround (Jose)
- Fix clear mask in GEN7_MISCCPCTL update (Andrzej)
- Temporarily disable runtime_pm for discrete (Anshuman)
- Improve fbdev debugs (Nirmoy)
- Fix DP FRL link training status (Ankit)
- Other small display fixes (Ankit, Suraj)
- Allow panel fixed modes to have differing sync
  polarities (Ville)
- Clean up crtc state flag checks (Ville)
- Fix race conditions during DKL PHY accesses (Imre)
- Prep-work for cdclock squash and crawl modes (Anusha)
- ELD precompute and readout (Ville)


Alan Previn (1):
  drm/i915/pxp: Add firmware status when ARB session fails

Andrzej Hajda (5):
  drm/i915/display: remove drm_device aliases
  drm/i915/display: Use intel_uncore alias if defined
  drm/i915: make intel_uncore_rmw() write unconditionally
  drm/i915: use proper helper for register updates
  drm/i915: fix clear mask in GEN7_MISCCPCTL update

Ankit Nautiyal (2):
  drm/i915/dp: Reset frl trained flag before restarting FRL training
  drm/i915/dp: Remove whitespace at the end of function.

Anshuman Gupta (1):
  drm/i915/dgfx: Keep PCI autosuspend control 'on' by default on all dGPU

Anusha Srivatsa (5):
  drm/i915/display: Add DC5 counter and DMC debugfs entries for MTL
  drm/i915/display: Change terminology for cdclk actions
  drm/i915/display: Introduce HAS_CDCLK_SQUASH macro
  drm/i915/display: Move chunks of code out of bxt_set_cdclk()
  drm/i915/display: Move squash_ctl register programming to its own function

Gustavo Sousa (1):
  drm/i915: Move hotplug inversion logic into separate helper

Imre Deak (6):
  drm/i915: Fix TypeC mode initialization during system resume
  drm/i915: Fix simulated GPU reset wrt. encoder HW readout
  drm/i915/tgl+: Add locking around DKL PHY register accesses
  drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.h
  drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.h
  drm/i915/tgl+: Sanitize DKL PHY register definitions

Jani Nikula (4):
  drm/i915/hotplug: move hotplug storm debugfs to 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: add CAT error handler (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: add CAT error handler (rev2)
URL   : https://patchwork.freedesktop.org/series/109865/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12314_full -> Patchwork_109865v2_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_109865v2_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_109865v2_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109865v2_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_softpin@noreloc-s3:
- shard-iclb: [PASS][1] -> [SKIP][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-iclb7/igt@gem_soft...@noreloc-s3.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/shard-iclb5/igt@gem_soft...@noreloc-s3.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
- shard-skl:  [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-skl4/igt@kms_flip@flip-vs-suspend-interrupti...@a-edp1.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/shard-skl7/igt@kms_flip@flip-vs-suspend-interrupti...@a-edp1.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_mmap_offset@clear@smem0:
- {shard-rkl}:[PASS][5] -> [INCOMPLETE][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-rkl-5/igt@gem_mmap_offset@cl...@smem0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/shard-rkl-5/igt@gem_mmap_offset@cl...@smem0.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-rkl}:[PASS][7] -> [WARN][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-rkl-4/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html

  
Known issues


  Here are the changes found in Patchwork_109865v2_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@psr2:
- shard-iclb: [PASS][9] -> [SKIP][10] ([i915#658])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-iclb2/igt@feature_discov...@psr2.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/shard-iclb8/igt@feature_discov...@psr2.html

  * igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][11] -> [SKIP][12] ([i915#4525]) +1 similar 
issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-iclb2/igt@gem_exec_balan...@parallel-out-fence.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/shard-iclb3/igt@gem_exec_balan...@parallel-out-fence.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk:  [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-glk5/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/shard-glk3/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-apl8/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#3989] / [i915#454])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-iclb5/igt@i915_pm...@dc6-psr.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/shard-iclb7/igt@i915_pm...@dc6-psr.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- shard-skl:  [PASS][19] -> [WARN][20] ([i915#1804])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/shard-skl4/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/shard-skl7/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#111644] / [i915#1397] / 
[i915#2411])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/shard-tglb1/igt@i915_pm_...@modeset-non-lpsp-stress-no-wait.html

  * igt@i915_pm_rps@engine-order:

Re: [Intel-gfx] [PATCH 5/5] drm/i915/mtl: don't expose GSC command streamer to the user

[Matt Roper]

On Fri, Oct 28, 2022 at 10:14:05AM -0700, Ceraolo Spurio, Daniele wrote:
> 
> 
> On 10/27/2022 8:40 PM, Matt Roper wrote:
> > On Thu, Oct 27, 2022 at 03:15:54PM -0700, Daniele Ceraolo Spurio wrote:
> > > There is no userspace user for this CS yet, we only need it for internal
> > > kernel ops (e.g. HuC, PXP), so don't expose it.
> > > 
> > > Signed-off-by: Daniele Ceraolo Spurio 
> > > Cc: Matt Roper 
> > Since we never expose it to userspace, we also never get to the point of
> > doing an engine rename and removing the apostrophe.  I assume we're okay
> > with this engine continuing to show up as "other'6" in debug logs?
> 
> I don't think it matters a lot in debug logs, but anyway it wouldn't be hard
> to rename it to something different. What do you suggest to rename it to?
> Since OTHER_CLASS doesn't have a uabi_class defined we can't use a count of
> engines of that type like we do for the other classes. Just rename it
> straight to hardcoded gsc0 ?

Yeah, a hardcoded "gsc0" seems fine to me.  I agree it doesn't matter
too much either way, so I'll leave it up to you whether you add that
rename or not.


Matt

> 
> Daniele
> 
> > 
> > Reviewed-by: Matt Roper 
> > 
> > > ---
> > >   drivers/gpu/drm/i915/gt/intel_engine_user.c | 4 
> > >   1 file changed, 4 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c 
> > > b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > index 79312b734690..ca795daca116 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > @@ -211,6 +211,10 @@ void intel_engines_driver_register(struct 
> > > drm_i915_private *i915)
> > >   if (intel_gt_has_unrecoverable_error(engine->gt))
> > >   continue; /* ignore incomplete engines */
> > > + /* don't expose GSC engine to user */
> > > + if (engine->class == OTHER_CLASS)
> > > + continue;
> > > +
> > >   GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
> > >   engine->uabi_class = uabi_classes[engine->class];
> > > -- 
> > > 2.37.3
> > > 
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH v1 1/7] vfio/ccw: create a parent struct

[Eric Farman]

On Fri, 2022-10-28 at 12:51 -0400, Matthew Rosato wrote:
> On 10/19/22 12:21 PM, Eric Farman wrote:
> > Move the stuff associated with the mdev parent (and thus the
> > subchannel struct) into its own struct, and leave the rest in
> > the existing private structure.
> > 
> > The subchannel will point to the parent, and the parent will point
> > to the private, for the areas where one or both are needed. Further
> > separation of these structs will follow.
> > 
> > Signed-off-by: Eric Farman 
> > ---
> >  drivers/s390/cio/vfio_ccw_drv.c | 104 
> > 
> >  drivers/s390/cio/vfio_ccw_ops.c |   9 ++-
> >  drivers/s390/cio/vfio_ccw_parent.h  |  28 
> >  drivers/s390/cio/vfio_ccw_private.h |   5 --
> >  4 files changed, 112 insertions(+), 34 deletions(-)
> >  create mode 100644 drivers/s390/cio/vfio_ccw_parent.h
> > 
> > diff --git a/drivers/s390/cio/vfio_ccw_drv.c
> > b/drivers/s390/cio/vfio_ccw_drv.c
> > index 7f5402fe857a..634760ca0dea 100644
> > --- a/drivers/s390/cio/vfio_ccw_drv.c
> > +++ b/drivers/s390/cio/vfio_ccw_drv.c
> > @@ -20,6 +20,7 @@
> >  #include "chp.h"
> >  #include "ioasm.h"
> >  #include "css.h"
> > +#include "vfio_ccw_parent.h"
> >  #include "vfio_ccw_private.h"
> >  
> >  struct workqueue_struct *vfio_ccw_work_q;
> > @@ -36,7 +37,8 @@ debug_info_t *vfio_ccw_debug_trace_id;
> >   */
> >  int vfio_ccw_sch_quiesce(struct subchannel *sch)
> >  {
> > -   struct vfio_ccw_private *private = dev_get_drvdata(
> > >dev);
> > +   struct vfio_ccw_parent *parent = dev_get_drvdata(
> > >dev);
> > +   struct vfio_ccw_private *private = dev_get_drvdata(
> > >dev);
> > DECLARE_COMPLETION_ONSTACK(completion);
> > int iretry, ret = 0;
> >  
> > @@ -51,19 +53,21 @@ int vfio_ccw_sch_quiesce(struct subchannel
> > *sch)
> > break;
> > }
> >  
> > -   /*
> > -    * Flush all I/O and wait for
> > -    * cancel/halt/clear completion.
> > -    */
> > -   private->completion = 
> > -   spin_unlock_irq(sch->lock);
> > +   if (private) {
> 
> Is it valid to ever reach this code with private == NULL?  If no,
> then this should probably be a WARN_ON upfront?

Hrm, the caller jumps from private -> subchannel, so it would be weird
if we couldn't then go back the other way. Probably impossible, I'll
unwind these whitespace changes and put the WARN_ON on top. Thanks for
the tip.

> 
> > +   /*
> > +    * Flush all I/O and wait for
> > +    * cancel/halt/clear completion.
> > +    */
> > +   private->completion = 
> > +   spin_unlock_irq(sch->lock);
> >  
> > -   if (ret == -EBUSY)
> > -   wait_for_completion_timeout(,
> > 3*HZ);
> > +   if (ret == -EBUSY)
> > +   wait_for_completion_timeout(
> > tion, 3*HZ);
> >  
> > -   private->completion = NULL;
> > -   flush_workqueue(vfio_ccw_work_q);
> > -   spin_lock_irq(sch->lock);
> > +   private->completion = NULL;
> > +   flush_workqueue(vfio_ccw_work_q);
> > +   spin_lock_irq(sch->lock);
> > +   }
> > ret = cio_disable_subchannel(sch);
> > } while (ret == -EBUSY);
> >  
> 
> .. snip ..
> 
> > diff --git a/drivers/s390/cio/vfio_ccw_parent.h
> > b/drivers/s390/cio/vfio_ccw_parent.h
> > new file mode 100644
> > index ..834c00077802
> > --- /dev/null
> > +++ b/drivers/s390/cio/vfio_ccw_parent.h
> > @@ -0,0 +1,28 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * MDEV Parent contents for vfio_ccw driver
> > + *
> > + * Copyright IBM Corp. 2022
> > + */
> > +
> > +#ifndef _VFIO_CCW_PARENT_H_
> > +#define _VFIO_CCW_PARENT_H_
> > +
> > +#include 
> > +
> > +/**
> > + * struct vfio_ccw_parent
> > + *
> > + * @dev: embedded device struct
> > + * @parent: parent data structures for mdevs created
> > + * @mdev_type(s): identifying information for mdevs created
> > + */
> > +struct vfio_ccw_parent {
> > +   struct device   dev;
> > +
> > +   struct mdev_parent  parent;
> > +   struct mdev_typemdev_type;
> > +   struct mdev_type*mdev_types[1];
> > +};
> 
> Structure itself seems fine, but any reason we need a new file for
> it?
> 

Not really. I could leave it in _private.h, but that file is just a
dumping ground for everything so I thought this would be a good
opportunity to start to cleaning that up. But it wouldn't bother me to
leave that whole process to another day too.

Re: [Intel-gfx] [PATCH 5/5] drm/i915/mtl: don't expose GSC command streamer to the user

[Ceraolo Spurio, Daniele]

On 10/27/2022 8:40 PM, Matt Roper wrote:

On Thu, Oct 27, 2022 at 03:15:54PM -0700, Daniele Ceraolo Spurio wrote:

There is no userspace user for this CS yet, we only need it for internal
kernel ops (e.g. HuC, PXP), so don't expose it.

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Matt Roper 

Since we never expose it to userspace, we also never get to the point of
doing an engine rename and removing the apostrophe.  I assume we're okay
with this engine continuing to show up as "other'6" in debug logs?


I don't think it matters a lot in debug logs, but anyway it wouldn't be 
hard to rename it to something different. What do you suggest to rename 
it to? Since OTHER_CLASS doesn't have a uabi_class defined we can't use 
a count of engines of that type like we do for the other classes. Just 
rename it straight to hardcoded gsc0 ?


Daniele



Reviewed-by: Matt Roper 


---
  drivers/gpu/drm/i915/gt/intel_engine_user.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c 
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 79312b734690..ca795daca116 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -211,6 +211,10 @@ void intel_engines_driver_register(struct drm_i915_private 
*i915)
if (intel_gt_has_unrecoverable_error(engine->gt))
continue; /* ignore incomplete engines */
  
+		/* don't expose GSC engine to user */

+   if (engine->class == OTHER_CLASS)
+   continue;
+
GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
engine->uabi_class = uabi_classes[engine->class];
  
--

2.37.3

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/4] drm/i915/dmabuf: fix sg_table handling in map_dma_buf

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/4] drm/i915/dmabuf: fix sg_table handling in 
map_dma_buf
URL   : https://patchwork.freedesktop.org/series/110261/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12317 -> Patchwork_110261v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/index.html

Participating hosts (40 -> 41)
--

  Additional (3): fi-kbl-soraka fi-kbl-x1275 fi-pnv-d510 
  Missing(2): fi-ctg-p8600 fi-icl-u2 

Known issues


  Here are the changes found in Patchwork_110261v1 that come from known issues:

### CI changes ###

 Possible fixes 

  * boot:
- fi-ilk-650: [FAIL][1] ([i915#7350]) -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-ilk-650/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/fi-ilk-650/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271]) +9 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/fi-kbl-soraka/igt@gem_exec_gttf...@basic.html
- fi-pnv-d510:NOTRUN -> [FAIL][4] ([i915#7229])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
- fi-kbl-x1275:   NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/fi-kbl-x1275/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@verify-random:
- fi-kbl-x1275:   NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/fi-kbl-x1275/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_module_load@load:
- fi-kbl-soraka:  NOTRUN -> [DMESG-WARN][9] ([i915#1982])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/fi-kbl-soraka/igt@i915_module_l...@load.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-ilk-650: NOTRUN -> [SKIP][10] ([fdo#109271]) +19 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/fi-ilk-650/igt@i915_pm_...@basic-pci-d3-state.html

  * igt@i915_selftest@live@client:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][11] ([i915#7100])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/fi-kbl-soraka/igt@i915_selftest@l...@client.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][12] -> [INCOMPLETE][13] ([i915#2940])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][14] -> [DMESG-FAIL][15] ([i915#5334])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
- fi-bxt-dsi: [PASS][16] -> [DMESG-FAIL][17] ([i915#5334])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12317/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][18] ([i915#1886])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-ilk-650: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html
- fi-kbl-x1275:   NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110261v1/fi-kbl-x1275/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-soraka:  NOTRUN -> [SKIP][21] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [21]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Send update also on invalidate (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/psr: Send update also on invalidate (rev2)
URL   : https://patchwork.freedesktop.org/series/110037/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12311 -> Patchwork_110037v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v2/index.html

Participating hosts (43 -> 41)
--

  Missing(2): fi-ctg-p8600 fi-hsw-4770 

Known issues


  Here are the changes found in Patchwork_110037v2 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-ilk-650: [PASS][1] -> [FAIL][2] ([i915#7350])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/fi-ilk-650/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v2/fi-ilk-650/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[PASS][3] -> [FAIL][4] ([i915#7229])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v2/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v2/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_tiled_blits@basic:
- fi-pnv-d510:[PASS][6] -> [SKIP][7] ([fdo#109271])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v2/fi-pnv-d510/igt@gem_tiled_bl...@basic.html

  * igt@i915_selftest@live@client:
- fi-kbl-soraka:  [PASS][8] -> [INCOMPLETE][9] ([i915#7100])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/fi-kbl-soraka/igt@i915_selftest@l...@client.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v2/fi-kbl-soraka/igt@i915_selftest@l...@client.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][10] -> [DMESG-FAIL][11] ([i915#5334])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@guc_multi_lrc:
- fi-cfl-8109u:   [PASS][12] -> [DMESG-WARN][13] ([i915#5904] / 
[i915#7174]) +2 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/fi-cfl-8109u/igt@i915_selftest@live@guc_multi_lrc.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v2/fi-cfl-8109u/igt@i915_selftest@live@guc_multi_lrc.html

  * igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u:   [PASS][14] -> [DMESG-WARN][15] ([i915#5904]) +32 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v2/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u:   [PASS][16] -> [DMESG-WARN][17] ([i915#5904] / 
[i915#62]) +3 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v2/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2:  NOTRUN -> [SKIP][18] ([fdo#111827])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v2/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][19] ([fdo#109285])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v2/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u:   [PASS][20] -> [DMESG-WARN][21] ([i915#165] / 
[i915#62]) +14 similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12311/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v2/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][22] ([i915#3555])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v2/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-icl-u2:  NOTRUN -> [SKIP][23] ([fdo#109295] / [i915#3301])
   [23]: 

Re: [Intel-gfx] [PATCH 3/5] drm/i915/mtl: add GSC CS interrupt support

[Ceraolo Spurio, Daniele]

On 10/28/2022 1:38 AM, Tvrtko Ursulin wrote:


On 27/10/2022 23:15, Daniele Ceraolo Spurio wrote:

The GSC CS re-uses the same interrupt bits that the GSC used in older
platforms. This means that we can now have an engine interrupt coming
out of OTHER_CLASS, so we need to handle that appropriately.

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Matt Roper 
---
  drivers/gpu/drm/i915/gt/intel_gt_irq.c | 78 ++
  1 file changed, 43 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c 
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c

index f26882fdc24c..34ff1ee7e931 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -81,35 +81,27 @@ gen11_other_irq_handler(struct intel_gt *gt, 
const u8 instance,

    instance, iir);
  }
  -static void
-gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
- const u8 instance, const u16 iir)
+static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 
instance)

  {
-    struct intel_engine_cs *engine;
-
-    /*
- * Platforms with standalone media have their media engines in 
another

- * GT.
- */
-    if (MEDIA_VER(gt->i915) >= 13 &&
-    (class == VIDEO_DECODE_CLASS || class == 
VIDEO_ENHANCEMENT_CLASS)) {

-    if (!gt->i915->media_gt)
-    goto err;
+    struct intel_gt *media_gt = gt->i915->media_gt;
  -    gt = gt->i915->media_gt;
+    /* we expect the non-media gt to be passed in */
+    GEM_BUG_ON(gt == media_gt);
+
+    if (!media_gt)
+    return gt;
+
+    switch (class) {
+    case VIDEO_DECODE_CLASS:
+    case VIDEO_ENHANCEMENT_CLASS:
+    return media_gt;
+    case OTHER_CLASS:
+    if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt, 
GSC0))

+    return media_gt;
+    fallthrough;
+    default:
+    return gt;
  }
-
-    if (instance <= MAX_ENGINE_INSTANCE)
-    engine = gt->engine_class[class][instance];
-    else
-    engine = NULL;
-
-    if (likely(engine))
-    return intel_engine_cs_irq(engine, iir);
-
-err:
-    WARN_ONCE(1, "unhandled engine interrupt class=0x%x, 
instance=0x%x\n",

-  class, instance);
  }
    static void
@@ -118,12 +110,24 @@ gen11_gt_identity_handler(struct intel_gt *gt, 
const u32 identity)

  const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
  const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
  const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
+    struct intel_engine_cs *engine;
    if (unlikely(!intr))
  return;
  -    if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS)
-    return gen11_engine_irq_handler(gt, class, instance, intr);
+    /*
+ * Platforms with standalone media have the media and GSC 
engines in

+ * another GT.
+ */
+    gt = pick_gt(gt, class, instance);
+
+    if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE)
+    engine = gt->engine_class[class][instance];
+    else
+    engine = NULL;
+
+    if (engine)
+    return intel_engine_cs_irq(engine, intr);


Drive by observation - you could fold the above two ifs into one since 
engine appears unused afterwards.


engine can be NULL in both branches of the if statement, so to get a 
unified if we'd have to do something like:


if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE) {
        struct intel_engine_cs *engine = gt->engine_class[class][instance];
        if (engine)
                return intel_engine_cs_irq(engine, intr);
}

Is this what you are suggesting?

Daniele



Regards,

Tvrtko


    if (class == OTHER_CLASS)
  return gen11_other_irq_handler(gt, instance, intr);
@@ -206,7 +210,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
  intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE,  0);
  if (CCS_MASK(gt))
  intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
-    if (HAS_HECI_GSC(gt->i915))
+    if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
  intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0);
    /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
@@ -233,7 +237,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
  intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
  if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
  intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
-    if (HAS_HECI_GSC(gt->i915))
+    if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0))
  intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0);
    intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
@@ -249,7 +253,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
  {
  struct intel_uncore *uncore = gt->uncore;
  u32 irqs = GT_RENDER_USER_INTERRUPT;
-    const u32 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
+    u32 gsc_mask = 0;
  u32 dmask;
  u32 smask;
  @@ -261,6 +265,11 @@ void 

Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/selftests: exercise GPU access from the importer

[Matthew Auld]

On 28/10/2022 17:10, Ruhl, Michael J wrote:

-Original Message-
From: Auld, Matthew 
Sent: Friday, October 28, 2022 11:50 AM
To: intel-gfx@lists.freedesktop.org
Cc: Landwerlin, Lionel G ; Tvrtko Ursulin
; Ville Syrjälä ;
Ruhl, Michael J 
Subject: [PATCH v2 2/4] drm/i915/selftests: exercise GPU access from the
importer

Using PAGE_SIZE here potentially hides issues so bump that to something
larger. This should also make it possible for iommu to coalesce entries
for us. With that in place verify we can write from the GPU using the
importers sg_table, followed by checking that our writes match when read
from the CPU side.

v2: Switch over to igt_gpu_fill_dw(), which looks to be more widely
supported than the migrate stuff (at least OOTB).

References: https://gitlab.freedesktop.org/drm/intel/-/issues/7306
Signed-off-by: Matthew Auld 
Cc: Lionel Landwerlin 
Cc: Tvrtko Ursulin 
Cc: Ville Syrjälä 
Cc: Michael J. Ruhl 
---
.../drm/i915/gem/selftests/i915_gem_dmabuf.c  | 79
++-
1 file changed, 78 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
index f2f3cfad807b..e57f9390076c 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
@@ -6,8 +6,12 @@

#include "i915_drv.h"
#include "i915_selftest.h"
+#include "gem/i915_gem_context.h"

+#include "mock_context.h"
#include "mock_dmabuf.h"
+#include "igt_gem_utils.h"
+#include "selftests/mock_drm.h"
#include "selftests/mock_gem_device.h"

static int igt_dmabuf_export(void *arg)
@@ -140,6 +144,75 @@ static int
igt_dmabuf_import_same_driver_lmem(void *arg)
return err;
}

+static int verify_access(struct drm_i915_private *i915,
+struct drm_i915_gem_object *native_obj,
+struct drm_i915_gem_object *import_obj)
+{
+   struct i915_gem_engines_iter it;
+   struct i915_gem_context *ctx;
+   struct intel_context *ce;
+   struct i915_vma *vma;
+   struct file *file;
+   u32 *vaddr;
+   int err = 0, i;
+
+   file = mock_file(i915);
+   if (IS_ERR(file))
+   return PTR_ERR(file);
+
+   ctx = live_context(i915, file);
+   if (IS_ERR(ctx)) {
+   err = PTR_ERR(ctx);
+   goto out_file;
+   }
+
+   for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+   if (intel_engine_can_store_dword(ce->engine))
+   break;
+   }
+   i915_gem_context_unlock_engines(ctx);
+   if (!ce)
+   goto out_file;
+
+   vma = i915_vma_instance(import_obj, ce->vm, NULL);
+   if (IS_ERR(vma)) {
+   err = PTR_ERR(vma);
+   goto out_file;
+   }
+
+   err = i915_vma_pin(vma, 0, 0, PIN_USER);
+   if (err)
+   goto out_file;
+
+   err = igt_gpu_fill_dw(ce, vma, 0,
+ vma->size >> PAGE_SHIFT, 0xdeadbeaf);
+   i915_vma_unpin(vma);
+   if (err)
+   goto out_file;
+
+   err = i915_gem_object_wait(import_obj, 0,
MAX_SCHEDULE_TIMEOUT);
+   if (err)
+   goto out_file;
+
+   vaddr = i915_gem_object_pin_map_unlocked(native_obj,
I915_MAP_WB);
+   if (IS_ERR(vaddr)) {
+   err = PTR_ERR(vaddr);
+   goto out_file;
+   }
+
+   for (i = 0; i < native_obj->base.size / sizeof(u32); i += PAGE_SIZE /
sizeof(u32)) {
+   if (vaddr[i] != 0xdeadbeaf) {
+   pr_err("Data mismatch [%d]=%u\n", i, vaddr[i]);
+   err = -EINVAL;
+   goto out_file;
+   }


Not sure what timing issues are related to this test, but this loop could have
some impact (takes a long time, assuming the object is LMEM).

Would checking the beginning, middle and end of each page be any less
beneficial than the current check?


We are currently just sampling the first dword of each page (that could 
perhaps be random instead). We could go further and sample a selection 
of random pages instead, if speed is a concern. Although here the pages 
must be in system memory. dma-buf in upstream will currently force 
migrate to system memory.




Not a suggested change, but just a thought to ponder if the timing becomes
an issue...

This test looks reasonable to me.

Reviewed-by: Michael J. Ruhl 

M


+   }
+
+out_file:
+   fput(file);
+   return err;
+}
+
static int igt_dmabuf_import_same_driver(struct drm_i915_private *i915,
 struct intel_memory_region
**regions,
 unsigned int num_regions)
@@ -154,7 +227,7 @@ static int igt_dmabuf_import_same_driver(struct
drm_i915_private *i915,

force_different_devices = true;

-   obj = __i915_gem_object_create_user(i915, PAGE_SIZE,
+   obj = __i915_gem_object_create_user(i915, SZ_8M,
  

Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/selftests: exercise GPU access from the importer

[Ruhl, Michael J]

>-Original Message-
>From: Auld, Matthew 
>Sent: Friday, October 28, 2022 11:50 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Landwerlin, Lionel G ; Tvrtko Ursulin
>; Ville Syrjälä 
>;
>Ruhl, Michael J 
>Subject: [PATCH v2 2/4] drm/i915/selftests: exercise GPU access from the
>importer
>
>Using PAGE_SIZE here potentially hides issues so bump that to something
>larger. This should also make it possible for iommu to coalesce entries
>for us. With that in place verify we can write from the GPU using the
>importers sg_table, followed by checking that our writes match when read
>from the CPU side.
>
>v2: Switch over to igt_gpu_fill_dw(), which looks to be more widely
>supported than the migrate stuff (at least OOTB).
>
>References: https://gitlab.freedesktop.org/drm/intel/-/issues/7306
>Signed-off-by: Matthew Auld 
>Cc: Lionel Landwerlin 
>Cc: Tvrtko Ursulin 
>Cc: Ville Syrjälä 
>Cc: Michael J. Ruhl 
>---
> .../drm/i915/gem/selftests/i915_gem_dmabuf.c  | 79
>++-
> 1 file changed, 78 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
>b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
>index f2f3cfad807b..e57f9390076c 100644
>--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
>+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
>@@ -6,8 +6,12 @@
>
> #include "i915_drv.h"
> #include "i915_selftest.h"
>+#include "gem/i915_gem_context.h"
>
>+#include "mock_context.h"
> #include "mock_dmabuf.h"
>+#include "igt_gem_utils.h"
>+#include "selftests/mock_drm.h"
> #include "selftests/mock_gem_device.h"
>
> static int igt_dmabuf_export(void *arg)
>@@ -140,6 +144,75 @@ static int
>igt_dmabuf_import_same_driver_lmem(void *arg)
>   return err;
> }
>
>+static int verify_access(struct drm_i915_private *i915,
>+   struct drm_i915_gem_object *native_obj,
>+   struct drm_i915_gem_object *import_obj)
>+{
>+  struct i915_gem_engines_iter it;
>+  struct i915_gem_context *ctx;
>+  struct intel_context *ce;
>+  struct i915_vma *vma;
>+  struct file *file;
>+  u32 *vaddr;
>+  int err = 0, i;
>+
>+  file = mock_file(i915);
>+  if (IS_ERR(file))
>+  return PTR_ERR(file);
>+
>+  ctx = live_context(i915, file);
>+  if (IS_ERR(ctx)) {
>+  err = PTR_ERR(ctx);
>+  goto out_file;
>+  }
>+
>+  for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
>+  if (intel_engine_can_store_dword(ce->engine))
>+  break;
>+  }
>+  i915_gem_context_unlock_engines(ctx);
>+  if (!ce)
>+  goto out_file;
>+
>+  vma = i915_vma_instance(import_obj, ce->vm, NULL);
>+  if (IS_ERR(vma)) {
>+  err = PTR_ERR(vma);
>+  goto out_file;
>+  }
>+
>+  err = i915_vma_pin(vma, 0, 0, PIN_USER);
>+  if (err)
>+  goto out_file;
>+
>+  err = igt_gpu_fill_dw(ce, vma, 0,
>+vma->size >> PAGE_SHIFT, 0xdeadbeaf);
>+  i915_vma_unpin(vma);
>+  if (err)
>+  goto out_file;
>+
>+  err = i915_gem_object_wait(import_obj, 0,
>MAX_SCHEDULE_TIMEOUT);
>+  if (err)
>+  goto out_file;
>+
>+  vaddr = i915_gem_object_pin_map_unlocked(native_obj,
>I915_MAP_WB);
>+  if (IS_ERR(vaddr)) {
>+  err = PTR_ERR(vaddr);
>+  goto out_file;
>+  }
>+
>+  for (i = 0; i < native_obj->base.size / sizeof(u32); i += PAGE_SIZE /
>sizeof(u32)) {
>+  if (vaddr[i] != 0xdeadbeaf) {
>+  pr_err("Data mismatch [%d]=%u\n", i, vaddr[i]);
>+  err = -EINVAL;
>+  goto out_file;
>+  }

Not sure what timing issues are related to this test, but this loop could have
some impact (takes a long time, assuming the object is LMEM).

Would checking the beginning, middle and end of each page be any less
beneficial than the current check?

Not a suggested change, but just a thought to ponder if the timing becomes
an issue...

This test looks reasonable to me.

Reviewed-by: Michael J. Ruhl 

M

>+  }
>+
>+out_file:
>+  fput(file);
>+  return err;
>+}
>+
> static int igt_dmabuf_import_same_driver(struct drm_i915_private *i915,
>struct intel_memory_region
>**regions,
>unsigned int num_regions)
>@@ -154,7 +227,7 @@ static int igt_dmabuf_import_same_driver(struct
>drm_i915_private *i915,
>
>   force_different_devices = true;
>
>-  obj = __i915_gem_object_create_user(i915, PAGE_SIZE,
>+  obj = __i915_gem_object_create_user(i915, SZ_8M,
>   regions, num_regions);
>   if (IS_ERR(obj)) {
>   pr_err("__i915_gem_object_create_user failed with
>err=%ld\n",
>@@ -206,6 +279,10 @@ static int igt_dmabuf_import_same_driver(struct
>drm_i915_private *i915,
>
>   

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Send update also on invalidate

[Patchwork]

== Series Details ==

Series: drm/i915/psr: Send update also on invalidate
URL   : https://patchwork.freedesktop.org/series/110037/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12280 -> Patchwork_110037v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110037v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110037v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v1/index.html

Participating hosts (42 -> 40)
--

  Additional (1): fi-kbl-soraka 
  Missing(3): fi-ctg-p8600 fi-bdw-gvtdvm fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110037v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@evict:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v1/fi-kbl-soraka/igt@i915_selftest@l...@evict.html

  
Known issues


  Here are the changes found in Patchwork_110037v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271]) +9 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v1/fi-kbl-soraka/igt@gem_exec_gttf...@basic.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-bsw-nick:NOTRUN -> [SKIP][5] ([fdo#109271]) +32 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v1/fi-bsw-nick/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@i915_selftest@live@execlists:
- fi-apl-guc: [PASS][6] -> [INCOMPLETE][7] ([i915#7156])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12280/fi-apl-guc/igt@i915_selftest@l...@execlists.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v1/fi-apl-guc/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][8] ([i915#1886])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hugepages:
- fi-skl-guc: [PASS][9] -> [DMESG-FAIL][10] ([i915#7311])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12280/fi-skl-guc/igt@i915_selftest@l...@hugepages.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v1/fi-skl-guc/igt@i915_selftest@l...@hugepages.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   NOTRUN -> [INCOMPLETE][11] ([i915#4817])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
- fi-kbl-x1275:   NOTRUN -> [SKIP][12] ([fdo#109271])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v1/fi-kbl-x1275/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-ivb-3770:NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v1/fi-ivb-3770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-kbl-x1275:   NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v1/fi-kbl-x1275/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-ilk-650: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v1/fi-ilk-650/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-bsw-nick:NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v1/fi-bsw-nick/igt@kms_chamel...@hdmi-hpd-fast.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110037v1/fi-kbl-soraka/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-2:
- fi-bdw-5557u:   [PASS][18] -> [INCOMPLETE][19] ([i915#146])
   [18]: 

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/dmabuf: fix sg_table handling in map_dma_buf

[Ruhl, Michael J]

>-Original Message-
>From: Auld, Matthew 
>Sent: Friday, October 28, 2022 11:50 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Landwerlin, Lionel G ; Tvrtko Ursulin
>; Ville Syrjälä 
>;
>Ruhl, Michael J 
>Subject: [PATCH v2 1/4] drm/i915/dmabuf: fix sg_table handling in
>map_dma_buf
>
>We need to iterate over the original entries here for the sg_table,
>pulling out the struct page for each one, to be remapped. However
>currently this incorrectly iterates over the final dma mapped entries,
>which is likely just one gigantic sg entry if the iommu is enabled,
>leading to us only mapping the first struct page (and any physically
>contiguous pages following it), even if there is potentially lots more
>data to follow.

I like this patch set a lot better. 

Reviewed-by: Michael J. Ruhl 

M

>Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7306
>Signed-off-by: Matthew Auld 
>Cc: Lionel Landwerlin 
>Cc: Tvrtko Ursulin 
>Cc: Ville Syrjälä 
>Cc: Michael J. Ruhl 
>---
> drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
>b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
>index 07eee1c09aaf..05ebbdfd3b3b 100644
>--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
>+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
>@@ -40,13 +40,13 @@ static struct sg_table *i915_gem_map_dma_buf(struct
>dma_buf_attachment *attachme
>   goto err;
>   }
>
>-  ret = sg_alloc_table(st, obj->mm.pages->nents, GFP_KERNEL);
>+  ret = sg_alloc_table(st, obj->mm.pages->orig_nents, GFP_KERNEL);
>   if (ret)
>   goto err_free;
>
>   src = obj->mm.pages->sgl;
>   dst = st->sgl;
>-  for (i = 0; i < obj->mm.pages->nents; i++) {
>+  for (i = 0; i < obj->mm.pages->orig_nents; i++) {
>   sg_set_page(dst, sg_page(src), src->length, 0);
>   dst = sg_next(dst);
>   src = sg_next(src);
>--
>2.37.3

Re: [Intel-gfx] Developing a new backlight driver for specific OLED screen

[Aurélien]

Hi, 

I come back on my problem regarding the development of a specific driver which 
controls the brightness of my OLED device.

> If it's eDP and uses some proprietary DPCD brightness control mechanism,
> I think in practice it usually is somewhat dependent on the GPU.
> 
> (OTOH I realize you don't mention eDP. If it's not eDP, DDC/CI is the
> more likely way to control brightness than DPCD.)

I succeed to control the brightness through the /dev/drm_dp_aux0 device.
Since I only need access to the DP AUX channel, I would like to develop an 
independant (from the GPU) driver. Unfortunately I don't know how to get access 
to the DP AUX channel from this independant driver.. Do you have some ideas?

I am totally agree with the fact that this display might only be used with an 
intel gfx card but I'm not sure that this code (which only use DP AUX 
read/write access) must be in the intel gfx driver code. 

>> Unfortunately I guess the mechanism is not shared with many OLED
>> displays...
> 
> Do you have a spec for it? How does it differ from the VESA eDP DPCD
> brightness control?

I don't have any specs but as far as I understood it configures some screen 
registers to scale the PWM of all OLED pixels depending on the display state. 
It uses its own vendor's ports and registers. And values sent on the display 
registers to set the desired brightness are computed with complex formulaes 
(and the calculation needs static tables of values and display information got 
from the display at startup).

Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/dmabuf: dmabuf cleanup

[Matthew Auld]

On Fri, 28 Oct 2022 at 16:51, Matthew Auld  wrote:
>
> From: "Michael J. Ruhl" 
>
> Some minor cleanup of some variables for consistency.
>
> Normalize struct sg_table to sgt.
> Normalize struct dma_buf_attachment to attach.
> checkpatch issues sizeof(), !NULL updates.
>
> Cc: Tvrtko Ursulin 
> Signed-off-by: Michael J. Ruhl 
Reviewed-by: Matthew Auld 

> Signed-off-by: Matthew Auld 
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 47 --
>  1 file changed, 25 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
> index 05ebbdfd3b3b..8342e01a0d27 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
> @@ -25,43 +25,46 @@ static struct drm_i915_gem_object *dma_buf_to_obj(struct 
> dma_buf *buf)
> return to_intel_bo(buf->priv);
>  }
>
> -static struct sg_table *i915_gem_map_dma_buf(struct dma_buf_attachment 
> *attachment,
> +static struct sg_table *i915_gem_map_dma_buf(struct dma_buf_attachment 
> *attach,
>  enum dma_data_direction dir)
>  {
> -   struct drm_i915_gem_object *obj = dma_buf_to_obj(attachment->dmabuf);
> -   struct sg_table *st;
> +   struct drm_i915_gem_object *obj = dma_buf_to_obj(attach->dmabuf);
> +   struct sg_table *sgt;
> struct scatterlist *src, *dst;
> int ret, i;
>
> -   /* Copy sg so that we make an independent mapping */
> -   st = kmalloc(sizeof(struct sg_table), GFP_KERNEL);
> -   if (st == NULL) {
> +   /*
> +* Make a copy of the object's sgt, so that we can make an independent
> +* mapping
> +*/
> +   sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
> +   if (!sgt) {
> ret = -ENOMEM;
> goto err;
> }
>
> -   ret = sg_alloc_table(st, obj->mm.pages->orig_nents, GFP_KERNEL);
> +   ret = sg_alloc_table(sgt, obj->mm.pages->orig_nents, GFP_KERNEL);
> if (ret)
> goto err_free;
>
> src = obj->mm.pages->sgl;
> -   dst = st->sgl;
> +   dst = sgt->sgl;
> for (i = 0; i < obj->mm.pages->orig_nents; i++) {
> sg_set_page(dst, sg_page(src), src->length, 0);
> dst = sg_next(dst);
> src = sg_next(src);
> }
>
> -   ret = dma_map_sgtable(attachment->dev, st, dir, 
> DMA_ATTR_SKIP_CPU_SYNC);
> +   ret = dma_map_sgtable(attach->dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC);
> if (ret)
> goto err_free_sg;
>
> -   return st;
> +   return sgt;
>
>  err_free_sg:
> -   sg_free_table(st);
> +   sg_free_table(sgt);
>  err_free:
> -   kfree(st);
> +   kfree(sgt);
>  err:
> return ERR_PTR(ret);
>  }
> @@ -236,15 +239,15 @@ struct dma_buf *i915_gem_prime_export(struct 
> drm_gem_object *gem_obj, int flags)
>  static int i915_gem_object_get_pages_dmabuf(struct drm_i915_gem_object *obj)
>  {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> -   struct sg_table *pages;
> +   struct sg_table *sgt;
> unsigned int sg_page_sizes;
>
> assert_object_held(obj);
>
> -   pages = dma_buf_map_attachment(obj->base.import_attach,
> -  DMA_BIDIRECTIONAL);
> -   if (IS_ERR(pages))
> -   return PTR_ERR(pages);
> +   sgt = dma_buf_map_attachment(obj->base.import_attach,
> +DMA_BIDIRECTIONAL);
> +   if (IS_ERR(sgt))
> +   return PTR_ERR(sgt);
>
> /*
>  * DG1 is special here since it still snoops transactions even with
> @@ -261,16 +264,16 @@ static int i915_gem_object_get_pages_dmabuf(struct 
> drm_i915_gem_object *obj)
> (!HAS_LLC(i915) && !IS_DG1(i915)))
> wbinvd_on_all_cpus();
>
> -   sg_page_sizes = i915_sg_dma_sizes(pages->sgl);
> -   __i915_gem_object_set_pages(obj, pages, sg_page_sizes);
> +   sg_page_sizes = i915_sg_dma_sizes(sgt->sgl);
> +   __i915_gem_object_set_pages(obj, sgt, sg_page_sizes);
>
> return 0;
>  }
>
>  static void i915_gem_object_put_pages_dmabuf(struct drm_i915_gem_object *obj,
> -struct sg_table *pages)
> +struct sg_table *sgt)
>  {
> -   dma_buf_unmap_attachment(obj->base.import_attach, pages,
> +   dma_buf_unmap_attachment(obj->base.import_attach, sgt,
>  DMA_BIDIRECTIONAL);
>  }
>
> @@ -313,7 +316,7 @@ struct drm_gem_object *i915_gem_prime_import(struct 
> drm_device *dev,
> get_dma_buf(dma_buf);
>
> obj = i915_gem_object_alloc();
> -   if (obj == NULL) {
> +   if (!obj) {
> ret = -ENOMEM;
> goto fail_detach;
> }
> --
> 2.37.3
>

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/dmabuf: Use scatterlist for_each_sg API

[Matthew Auld]

On Fri, 28 Oct 2022 at 16:51, Matthew Auld  wrote:
>
> From: "Michael J. Ruhl" 
>
> Update open coded for loop to use the standard scatterlist
> for_each_sg API.
>
> Cc: Tvrtko Ursulin 
> Signed-off-by: Michael J. Ruhl 
Reviewed-by: Matthew Auld 

> Signed-off-by: Matthew Auld 
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
> index 8342e01a0d27..ec6f7ae47783 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
> @@ -47,12 +47,10 @@ static struct sg_table *i915_gem_map_dma_buf(struct 
> dma_buf_attachment *attach,
> if (ret)
> goto err_free;
>
> -   src = obj->mm.pages->sgl;
> dst = sgt->sgl;
> -   for (i = 0; i < obj->mm.pages->orig_nents; i++) {
> +   for_each_sg(obj->mm.pages->sgl, src, obj->mm.pages->orig_nents, i) {
> sg_set_page(dst, sg_page(src), src->length, 0);
> dst = sg_next(dst);
> -   src = sg_next(src);
> }
>
> ret = dma_map_sgtable(attach->dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC);
> --
> 2.37.3
>

[Intel-gfx] [PATCH v2 4/4] drm/i915/dmabuf: Use scatterlist for_each_sg API

[Matthew Auld]

From: "Michael J. Ruhl" 

Update open coded for loop to use the standard scatterlist
for_each_sg API.

Cc: Tvrtko Ursulin 
Signed-off-by: Michael J. Ruhl 
Signed-off-by: Matthew Auld 
---
 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c 
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index 8342e01a0d27..ec6f7ae47783 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -47,12 +47,10 @@ static struct sg_table *i915_gem_map_dma_buf(struct 
dma_buf_attachment *attach,
if (ret)
goto err_free;
 
-   src = obj->mm.pages->sgl;
dst = sgt->sgl;
-   for (i = 0; i < obj->mm.pages->orig_nents; i++) {
+   for_each_sg(obj->mm.pages->sgl, src, obj->mm.pages->orig_nents, i) {
sg_set_page(dst, sg_page(src), src->length, 0);
dst = sg_next(dst);
-   src = sg_next(src);
}
 
ret = dma_map_sgtable(attach->dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC);
-- 
2.37.3

[Intel-gfx] [PATCH v2 3/4] drm/i915/dmabuf: dmabuf cleanup

[Matthew Auld]

From: "Michael J. Ruhl" 

Some minor cleanup of some variables for consistency.

Normalize struct sg_table to sgt.
Normalize struct dma_buf_attachment to attach.
checkpatch issues sizeof(), !NULL updates.

Cc: Tvrtko Ursulin 
Signed-off-by: Michael J. Ruhl 
Signed-off-by: Matthew Auld 
---
 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 47 --
 1 file changed, 25 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c 
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index 05ebbdfd3b3b..8342e01a0d27 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -25,43 +25,46 @@ static struct drm_i915_gem_object *dma_buf_to_obj(struct 
dma_buf *buf)
return to_intel_bo(buf->priv);
 }
 
-static struct sg_table *i915_gem_map_dma_buf(struct dma_buf_attachment 
*attachment,
+static struct sg_table *i915_gem_map_dma_buf(struct dma_buf_attachment *attach,
 enum dma_data_direction dir)
 {
-   struct drm_i915_gem_object *obj = dma_buf_to_obj(attachment->dmabuf);
-   struct sg_table *st;
+   struct drm_i915_gem_object *obj = dma_buf_to_obj(attach->dmabuf);
+   struct sg_table *sgt;
struct scatterlist *src, *dst;
int ret, i;
 
-   /* Copy sg so that we make an independent mapping */
-   st = kmalloc(sizeof(struct sg_table), GFP_KERNEL);
-   if (st == NULL) {
+   /*
+* Make a copy of the object's sgt, so that we can make an independent
+* mapping
+*/
+   sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
+   if (!sgt) {
ret = -ENOMEM;
goto err;
}
 
-   ret = sg_alloc_table(st, obj->mm.pages->orig_nents, GFP_KERNEL);
+   ret = sg_alloc_table(sgt, obj->mm.pages->orig_nents, GFP_KERNEL);
if (ret)
goto err_free;
 
src = obj->mm.pages->sgl;
-   dst = st->sgl;
+   dst = sgt->sgl;
for (i = 0; i < obj->mm.pages->orig_nents; i++) {
sg_set_page(dst, sg_page(src), src->length, 0);
dst = sg_next(dst);
src = sg_next(src);
}
 
-   ret = dma_map_sgtable(attachment->dev, st, dir, DMA_ATTR_SKIP_CPU_SYNC);
+   ret = dma_map_sgtable(attach->dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC);
if (ret)
goto err_free_sg;
 
-   return st;
+   return sgt;
 
 err_free_sg:
-   sg_free_table(st);
+   sg_free_table(sgt);
 err_free:
-   kfree(st);
+   kfree(sgt);
 err:
return ERR_PTR(ret);
 }
@@ -236,15 +239,15 @@ struct dma_buf *i915_gem_prime_export(struct 
drm_gem_object *gem_obj, int flags)
 static int i915_gem_object_get_pages_dmabuf(struct drm_i915_gem_object *obj)
 {
struct drm_i915_private *i915 = to_i915(obj->base.dev);
-   struct sg_table *pages;
+   struct sg_table *sgt;
unsigned int sg_page_sizes;
 
assert_object_held(obj);
 
-   pages = dma_buf_map_attachment(obj->base.import_attach,
-  DMA_BIDIRECTIONAL);
-   if (IS_ERR(pages))
-   return PTR_ERR(pages);
+   sgt = dma_buf_map_attachment(obj->base.import_attach,
+DMA_BIDIRECTIONAL);
+   if (IS_ERR(sgt))
+   return PTR_ERR(sgt);
 
/*
 * DG1 is special here since it still snoops transactions even with
@@ -261,16 +264,16 @@ static int i915_gem_object_get_pages_dmabuf(struct 
drm_i915_gem_object *obj)
(!HAS_LLC(i915) && !IS_DG1(i915)))
wbinvd_on_all_cpus();
 
-   sg_page_sizes = i915_sg_dma_sizes(pages->sgl);
-   __i915_gem_object_set_pages(obj, pages, sg_page_sizes);
+   sg_page_sizes = i915_sg_dma_sizes(sgt->sgl);
+   __i915_gem_object_set_pages(obj, sgt, sg_page_sizes);
 
return 0;
 }
 
 static void i915_gem_object_put_pages_dmabuf(struct drm_i915_gem_object *obj,
-struct sg_table *pages)
+struct sg_table *sgt)
 {
-   dma_buf_unmap_attachment(obj->base.import_attach, pages,
+   dma_buf_unmap_attachment(obj->base.import_attach, sgt,
 DMA_BIDIRECTIONAL);
 }
 
@@ -313,7 +316,7 @@ struct drm_gem_object *i915_gem_prime_import(struct 
drm_device *dev,
get_dma_buf(dma_buf);
 
obj = i915_gem_object_alloc();
-   if (obj == NULL) {
+   if (!obj) {
ret = -ENOMEM;
goto fail_detach;
}
-- 
2.37.3

[Intel-gfx] [PATCH v2 2/4] drm/i915/selftests: exercise GPU access from the importer

[Matthew Auld]

Using PAGE_SIZE here potentially hides issues so bump that to something
larger. This should also make it possible for iommu to coalesce entries
for us. With that in place verify we can write from the GPU using the
importers sg_table, followed by checking that our writes match when read
from the CPU side.

v2: Switch over to igt_gpu_fill_dw(), which looks to be more widely
supported than the migrate stuff (at least OOTB).

References: https://gitlab.freedesktop.org/drm/intel/-/issues/7306
Signed-off-by: Matthew Auld 
Cc: Lionel Landwerlin 
Cc: Tvrtko Ursulin 
Cc: Ville Syrjälä 
Cc: Michael J. Ruhl 
---
 .../drm/i915/gem/selftests/i915_gem_dmabuf.c  | 79 ++-
 1 file changed, 78 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
index f2f3cfad807b..e57f9390076c 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
@@ -6,8 +6,12 @@
 
 #include "i915_drv.h"
 #include "i915_selftest.h"
+#include "gem/i915_gem_context.h"
 
+#include "mock_context.h"
 #include "mock_dmabuf.h"
+#include "igt_gem_utils.h"
+#include "selftests/mock_drm.h"
 #include "selftests/mock_gem_device.h"
 
 static int igt_dmabuf_export(void *arg)
@@ -140,6 +144,75 @@ static int igt_dmabuf_import_same_driver_lmem(void *arg)
return err;
 }
 
+static int verify_access(struct drm_i915_private *i915,
+struct drm_i915_gem_object *native_obj,
+struct drm_i915_gem_object *import_obj)
+{
+   struct i915_gem_engines_iter it;
+   struct i915_gem_context *ctx;
+   struct intel_context *ce;
+   struct i915_vma *vma;
+   struct file *file;
+   u32 *vaddr;
+   int err = 0, i;
+
+   file = mock_file(i915);
+   if (IS_ERR(file))
+   return PTR_ERR(file);
+
+   ctx = live_context(i915, file);
+   if (IS_ERR(ctx)) {
+   err = PTR_ERR(ctx);
+   goto out_file;
+   }
+
+   for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+   if (intel_engine_can_store_dword(ce->engine))
+   break;
+   }
+   i915_gem_context_unlock_engines(ctx);
+   if (!ce)
+   goto out_file;
+
+   vma = i915_vma_instance(import_obj, ce->vm, NULL);
+   if (IS_ERR(vma)) {
+   err = PTR_ERR(vma);
+   goto out_file;
+   }
+
+   err = i915_vma_pin(vma, 0, 0, PIN_USER);
+   if (err)
+   goto out_file;
+
+   err = igt_gpu_fill_dw(ce, vma, 0,
+ vma->size >> PAGE_SHIFT, 0xdeadbeaf);
+   i915_vma_unpin(vma);
+   if (err)
+   goto out_file;
+
+   err = i915_gem_object_wait(import_obj, 0, MAX_SCHEDULE_TIMEOUT);
+   if (err)
+   goto out_file;
+
+   vaddr = i915_gem_object_pin_map_unlocked(native_obj, I915_MAP_WB);
+   if (IS_ERR(vaddr)) {
+   err = PTR_ERR(vaddr);
+   goto out_file;
+   }
+
+   for (i = 0; i < native_obj->base.size / sizeof(u32); i += PAGE_SIZE / 
sizeof(u32)) {
+   if (vaddr[i] != 0xdeadbeaf) {
+   pr_err("Data mismatch [%d]=%u\n", i, vaddr[i]);
+   err = -EINVAL;
+   goto out_file;
+   }
+   }
+
+out_file:
+   fput(file);
+   return err;
+}
+
 static int igt_dmabuf_import_same_driver(struct drm_i915_private *i915,
 struct intel_memory_region **regions,
 unsigned int num_regions)
@@ -154,7 +227,7 @@ static int igt_dmabuf_import_same_driver(struct 
drm_i915_private *i915,
 
force_different_devices = true;
 
-   obj = __i915_gem_object_create_user(i915, PAGE_SIZE,
+   obj = __i915_gem_object_create_user(i915, SZ_8M,
regions, num_regions);
if (IS_ERR(obj)) {
pr_err("__i915_gem_object_create_user failed with err=%ld\n",
@@ -206,6 +279,10 @@ static int igt_dmabuf_import_same_driver(struct 
drm_i915_private *i915,
 
i915_gem_object_unlock(import_obj);
 
+   err = verify_access(i915, obj, import_obj);
+   if (err)
+   goto out_import;
+
/* Now try a fake an importer */
import_attach = dma_buf_attach(dmabuf, obj->base.dev->dev);
if (IS_ERR(import_attach)) {
-- 
2.37.3

[Intel-gfx] [PATCH v2 1/4] drm/i915/dmabuf: fix sg_table handling in map_dma_buf

[Matthew Auld]

We need to iterate over the original entries here for the sg_table,
pulling out the struct page for each one, to be remapped. However
currently this incorrectly iterates over the final dma mapped entries,
which is likely just one gigantic sg entry if the iommu is enabled,
leading to us only mapping the first struct page (and any physically
contiguous pages following it), even if there is potentially lots more
data to follow.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7306
Signed-off-by: Matthew Auld 
Cc: Lionel Landwerlin 
Cc: Tvrtko Ursulin 
Cc: Ville Syrjälä 
Cc: Michael J. Ruhl 
---
 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c 
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index 07eee1c09aaf..05ebbdfd3b3b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -40,13 +40,13 @@ static struct sg_table *i915_gem_map_dma_buf(struct 
dma_buf_attachment *attachme
goto err;
}
 
-   ret = sg_alloc_table(st, obj->mm.pages->nents, GFP_KERNEL);
+   ret = sg_alloc_table(st, obj->mm.pages->orig_nents, GFP_KERNEL);
if (ret)
goto err_free;
 
src = obj->mm.pages->sgl;
dst = st->sgl;
-   for (i = 0; i < obj->mm.pages->nents; i++) {
+   for (i = 0; i < obj->mm.pages->orig_nents; i++) {
sg_set_page(dst, sg_page(src), src->length, 0);
dst = sg_next(dst);
src = sg_next(src);
-- 
2.37.3

Re: [Intel-gfx] [PATCH 1/2] drm/i915/dmabuf: fix sg_table handling in map_dma_buf

[Matthew Auld]

On 28/10/2022 14:55, Ruhl, Michael J wrote:

-Original Message-
From: Intel-gfx  On Behalf Of
Matthew Auld
Sent: Thursday, October 27, 2022 11:27 AM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 1/2] drm/i915/dmabuf: fix sg_table handling in
map_dma_buf

We need to iterate over the original entries here for the sg_table,
pulling out the struct page for each one, to be remapped. However
currently this incorrectly iterates over the final dma mapped entries,
which is likely just one gigantic sg entry if the iommu is enabled,
leading to us only mapping the first struct page (and any physically
contiguous pages following it), even if there is potentially lots more
data to follow.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7306
Signed-off-by: Matthew Auld 
Cc: Lionel Landwerlin 
Cc: Tvrtko Ursulin 
Cc: Ville Syrjälä 
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index 07eee1c09aaf..05ebbdfd3b3b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -40,13 +40,13 @@ static struct sg_table *i915_gem_map_dma_buf(struct
dma_buf_attachment *attachme
goto err;
}

-   ret = sg_alloc_table(st, obj->mm.pages->nents, GFP_KERNEL);
+   ret = sg_alloc_table(st, obj->mm.pages->orig_nents, GFP_KERNEL);
if (ret)
goto err_free;

src = obj->mm.pages->sgl;
dst = st->sgl;
-   for (i = 0; i < obj->mm.pages->nents; i++) {
+   for (i = 0; i < obj->mm.pages->orig_nents; i++) {


This really should use the for_each_sg() macro.

I proposed a clean up patch a while back that looked like this:

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c 
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index e2cdc2640c08..ccc5d46aa749 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -7,6 +7,7 @@
  #include 
  #include 
  #include 
+#include 
  
  #include "gem/i915_gem_dmabuf.h"

  #include "i915_drv.h"
@@ -41,12 +42,10 @@ static struct sg_table *i915_gem_map_dma_buf(struct 
dma_buf_attachment *attach,
 if (ret)
 goto err_free;
  
-   src = obj->mm.pages->sgl;

 dst = sgt->sgl;
-   for (i = 0; i < obj->mm.pages->nents; i++) {
+   for_each_sg(obj->mm.pages->sgl, src, obj->mm.pages->nents, i) {
 sg_set_page(dst, sg_page(src), src->length, 0);
 dst = sg_next(dst);
-   src = sg_next(src);
 }

If you are updating the for loop, this might be a reasonable update as well.


Ok, but such cleanups should normally be a separate patch. I'll grab 
your series and bolt that onto this one.




Mike


sg_set_page(dst, sg_page(src), src->length, 0);
dst = sg_next(dst);
src = sg_next(src);
--
2.37.3

[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/dmabuf: fix sg_table handling in map_dma_buf (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/dmabuf: fix sg_table handling in 
map_dma_buf (rev2)
URL   : https://patchwork.freedesktop.org/series/110229/
State : failure

== Summary ==

Error: patch 
https://patchwork.freedesktop.org/api/1.0/series/110229/revisions/2/mbox/ not 
applied
Applying: drm/i915/dmabuf: fix sg_table handling in map_dma_buf
error: corrupt patch at line 26
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915/dmabuf: fix sg_table handling in map_dma_buf
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/userptr: restore probe_range behaviour (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/userptr: restore probe_range behaviour (rev3)
URL   : https://patchwork.freedesktop.org/series/110083/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12316 -> Patchwork_110083v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/index.html

Participating hosts (42 -> 40)
--

  Missing(2): fi-ctg-p8600 fi-tgl-dsi 

Known issues


  Here are the changes found in Patchwork_110083v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@migrate:
- bat-adlp-4: [PASS][2] -> [INCOMPLETE][3] ([i915#7308] / 
[i915#7348])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/bat-adlp-4/igt@i915_selftest@l...@migrate.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/bat-adlp-4/igt@i915_selftest@l...@migrate.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2:  NOTRUN -> [SKIP][4] ([fdo#111827])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-apl-guc: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/fi-apl-guc/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][6] ([i915#4312])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/bat-adlp-4/igt@run...@aborted.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [INCOMPLETE][7] ([i915#7073]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html

  * igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}:   [DMESG-WARN][9] ([i915#5537]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/bat-rpls-2/igt@i915_pm_...@module-reload.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/bat-rpls-2/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-7567u:   [DMESG-FAIL][11] ([i915#5334]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@guc_multi_lrc:
- fi-icl-u2:  [DMESG-FAIL][13] ([i915#4890]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/fi-icl-u2/igt@i915_selftest@live@guc_multi_lrc.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/fi-icl-u2/igt@i915_selftest@live@guc_multi_lrc.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [FAIL][15] ([i915#6298]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110083v3/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5537]: 

Re: [Intel-gfx] [PATCH v2] drm/i915/userptr: restore probe_range behaviour

[Andrzej Hajda]

On 28.10.2022 15:06, Matthew Auld wrote:

The conversion looks harmless, however the addr value is updated inside
the loop with the previous vm_end, which then incorrectly leads to
for_each_vma_range() iterating over stuff outside the range we care
about. Fix this by storing the end value separately. Also fix the case
where the range doesn't intersect with any vma, or if the vma itself
doesn't extend the entire range, which must mean we have hole at the
end. Both should result in an error, as per the previous behaviour.

v2: Fix the cases where the range is empty, or if there's a hole at
the end of the range

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7247
Testcase: igt@gem_userptr_blits@probe
Fixes: f683b9d61319 ("i915: use the VMA iterator")
Reported-by: kernel test robot 
Signed-off-by: Matthew Auld 
Cc: Tvrtko Ursulin 
Cc: Matthew Wilcox (Oracle) 
Cc: Liam R. Howlett 
Cc: Vlastimil Babka 
Cc: Yu Zhao 


Reviewed-by: Andrzej Hajda 

Regards
Andrzej


---
  drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c 
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 1b1a22716722..ca7a388ba2bf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -427,9 +427,10 @@ probe_range(struct mm_struct *mm, unsigned long addr, 
unsigned long len)
  {
VMA_ITERATOR(vmi, mm, addr);
struct vm_area_struct *vma;
+   unsigned long end = addr + len;
  
  	mmap_read_lock(mm);

-   for_each_vma_range(vmi, vma, addr + len) {
+   for_each_vma_range(vmi, vma, end) {
/* Check for holes, note that we also update the addr below */
if (vma->vm_start > addr)
break;
@@ -441,7 +442,7 @@ probe_range(struct mm_struct *mm, unsigned long addr, 
unsigned long len)
}
mmap_read_unlock(mm);
  
-	if (vma)

+   if (vma || addr < end)
return -EFAULT;
return 0;
  }

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/userptr: restore probe_range behaviour (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/userptr: restore probe_range behaviour (rev3)
URL   : https://patchwork.freedesktop.org/series/110083/
State : warning

== Summary ==

Error: make htmldocs had i915 warnings
./drivers/gpu/drm/i915/i915_perf_types.h:319: warning: Function parameter or 
member 'lock' not described in 'i915_perf_stream'

[Intel-gfx] ✓ Fi.CI.BAT: success for Enable YCbCr420 for VDSC

[Patchwork]

== Series Details ==

Series: Enable YCbCr420 for VDSC
URL   : https://patchwork.freedesktop.org/series/110253/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12316 -> Patchwork_110253v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/index.html

Participating hosts (42 -> 39)
--

  Additional (1): bat-dg1-5 
  Missing(4): fi-adl-ddr5 fi-ctg-p8600 fi-tgl-dsi fi-apl-guc 

Known issues


  Here are the changes found in Patchwork_110253v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_mmap@basic:
- bat-dg1-5:  NOTRUN -> [SKIP][1] ([i915#4083])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/bat-dg1-5/igt@gem_m...@basic.html

  * igt@gem_tiled_blits@basic:
- bat-dg1-5:  NOTRUN -> [SKIP][2] ([i915#4077]) +2 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/bat-dg1-5/igt@gem_tiled_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg1-5:  NOTRUN -> [SKIP][3] ([i915#4079]) +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/bat-dg1-5/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-dg1-5:  NOTRUN -> [SKIP][4] ([i915#1155])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_pm_rps@basic-api:
- bat-dg1-5:  NOTRUN -> [SKIP][5] ([i915#6621])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/bat-dg1-5/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [PASS][6] -> [INCOMPLETE][7] ([i915#3303] / 
[i915#4785])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12316/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_addfb_basic@basic-x-tiled-legacy:
- bat-dg1-5:  NOTRUN -> [SKIP][8] ([i915#4212]) +7 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/bat-dg1-5/igt@kms_addfb_ba...@basic-x-tiled-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-5:  NOTRUN -> [SKIP][9] ([i915#4215])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/bat-dg1-5/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([fdo#111827])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- bat-dg1-5:  NOTRUN -> [SKIP][11] ([fdo#111827]) +8 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/bat-dg1-5/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-dg1-5:  NOTRUN -> [SKIP][12] ([i915#4103] / [i915#4213])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/bat-dg1-5/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-5:  NOTRUN -> [SKIP][13] ([fdo#109285])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/bat-dg1-5/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_psr@primary_page_flip:
- bat-dg1-5:  NOTRUN -> [SKIP][14] ([i915#1072] / [i915#4078]) +3 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/bat-dg1-5/igt@kms_psr@primary_page_flip.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-5:  NOTRUN -> [SKIP][15] ([i915#3555])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/bat-dg1-5/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-read:
- bat-dg1-5:  NOTRUN -> [SKIP][16] ([i915#3708]) +3 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/bat-dg1-5/igt@prime_v...@basic-fence-read.html

  * igt@prime_vgem@basic-gtt:
- bat-dg1-5:  NOTRUN -> [SKIP][17] ([i915#3708] / [i915#4077]) +1 
similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/bat-dg1-5/igt@prime_v...@basic-gtt.html

  * igt@prime_vgem@basic-userptr:
- bat-dg1-5:  NOTRUN -> [SKIP][18] ([i915#3708] / [i915#4873])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/bat-dg1-5/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- fi-hsw-g3258:   NOTRUN -> [FAIL][19] ([fdo#109271] / [i915#4312] / 
[i915#4991])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110253v1/fi-hsw-g3258/igt@run...@aborted.html

  

Re: [Intel-gfx] [PATCH 1/2] drm/i915/dmabuf: fix sg_table handling in map_dma_buf

[Ruhl, Michael J]

>-Original Message-
>From: Intel-gfx  On Behalf Of
>Matthew Auld
>Sent: Thursday, October 27, 2022 11:27 AM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 1/2] drm/i915/dmabuf: fix sg_table handling in
>map_dma_buf
>
>We need to iterate over the original entries here for the sg_table,
>pulling out the struct page for each one, to be remapped. However
>currently this incorrectly iterates over the final dma mapped entries,
>which is likely just one gigantic sg entry if the iommu is enabled,
>leading to us only mapping the first struct page (and any physically
>contiguous pages following it), even if there is potentially lots more
>data to follow.
>
>Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7306
>Signed-off-by: Matthew Auld 
>Cc: Lionel Landwerlin 
>Cc: Tvrtko Ursulin 
>Cc: Ville Syrjälä 
>---
> drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
>b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
>index 07eee1c09aaf..05ebbdfd3b3b 100644
>--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
>+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
>@@ -40,13 +40,13 @@ static struct sg_table *i915_gem_map_dma_buf(struct
>dma_buf_attachment *attachme
>   goto err;
>   }
>
>-  ret = sg_alloc_table(st, obj->mm.pages->nents, GFP_KERNEL);
>+  ret = sg_alloc_table(st, obj->mm.pages->orig_nents, GFP_KERNEL);
>   if (ret)
>   goto err_free;
>
>   src = obj->mm.pages->sgl;
>   dst = st->sgl;
>-  for (i = 0; i < obj->mm.pages->nents; i++) {
>+  for (i = 0; i < obj->mm.pages->orig_nents; i++) {

This really should use the for_each_sg() macro.

I proposed a clean up patch a while back that looked like this:

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c 
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index e2cdc2640c08..ccc5d46aa749 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "gem/i915_gem_dmabuf.h"
 #include "i915_drv.h"
@@ -41,12 +42,10 @@ static struct sg_table *i915_gem_map_dma_buf(struct 
dma_buf_attachment *attach,
if (ret)
goto err_free;
 
-   src = obj->mm.pages->sgl;
dst = sgt->sgl;
-   for (i = 0; i < obj->mm.pages->nents; i++) {
+   for_each_sg(obj->mm.pages->sgl, src, obj->mm.pages->nents, i) {
sg_set_page(dst, sg_page(src), src->length, 0);
dst = sg_next(dst);
-   src = sg_next(src);
}

If you are updating the for loop, this might be a reasonable update as well.

Mike

>   sg_set_page(dst, sg_page(src), src->length, 0);
>   dst = sg_next(dst);
>   src = sg_next(src);
>--
>2.37.3

Re: [Intel-gfx] [PATCH v2] drm/i915/userptr: restore probe_range behaviour

[Liam Howlett]

* Matthew Auld  [221028 09:07]:
> The conversion looks harmless, however the addr value is updated inside
> the loop with the previous vm_end, which then incorrectly leads to
> for_each_vma_range() iterating over stuff outside the range we care
> about. Fix this by storing the end value separately. Also fix the case
> where the range doesn't intersect with any vma, or if the vma itself
> doesn't extend the entire range, which must mean we have hole at the
> end. Both should result in an error, as per the previous behaviour.
> 
> v2: Fix the cases where the range is empty, or if there's a hole at
> the end of the range
> 

Reviewed-by: Liam R. Howlett 

> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7247
> Testcase: igt@gem_userptr_blits@probe
> Fixes: f683b9d61319 ("i915: use the VMA iterator")
> Reported-by: kernel test robot 
> Signed-off-by: Matthew Auld 
> Cc: Tvrtko Ursulin 
> Cc: Matthew Wilcox (Oracle) 
> Cc: Liam R. Howlett 
> Cc: Vlastimil Babka 
> Cc: Yu Zhao 
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> index 1b1a22716722..ca7a388ba2bf 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> @@ -427,9 +427,10 @@ probe_range(struct mm_struct *mm, unsigned long addr, 
> unsigned long len)
>  {
>   VMA_ITERATOR(vmi, mm, addr);
>   struct vm_area_struct *vma;
> + unsigned long end = addr + len;
>  
>   mmap_read_lock(mm);
> - for_each_vma_range(vmi, vma, addr + len) {
> + for_each_vma_range(vmi, vma, end) {
>   /* Check for holes, note that we also update the addr below */
>   if (vma->vm_start > addr)
>   break;
> @@ -441,7 +442,7 @@ probe_range(struct mm_struct *mm, unsigned long addr, 
> unsigned long len)
>   }
>   mmap_read_unlock(mm);
>  
> - if (vma)
> + if (vma || addr < end)
>   return -EFAULT;
>   return 0;
>  }
> -- 
> 2.37.3
> 

[Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce the GSC CS

[Patchwork]

== Series Details ==

Series: Introduce the GSC CS
URL   : https://patchwork.freedesktop.org/series/110237/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12313_full -> Patchwork_110237v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110237v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110237v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110237v1_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-iclb2/igt@i915_pm...@dc9-dpms.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-iclb7/igt@i915_pm...@dc9-dpms.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-c-edp-1:
- shard-skl:  [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-skl4/igt@kms_cursor_crc@cursor-susp...@pipe-c-edp-1.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl9/igt@kms_cursor_crc@cursor-susp...@pipe-c-edp-1.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_pread@exhaustion:
- {shard-rkl}:[SKIP][5] ([i915#3282]) -> [INCOMPLETE][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-rkl-1/igt@gem_pr...@exhaustion.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-rkl-5/igt@gem_pr...@exhaustion.html

  
Known issues


  Here are the changes found in Patchwork_110237v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@psr2:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#658])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-iclb2/igt@feature_discov...@psr2.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-iclb3/igt@feature_discov...@psr2.html

  * igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#6268])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-tglb2/igt@gem_ctx_e...@basic-nohangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-tglb1/igt@gem_ctx_e...@basic-nohangcheck.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][11] -> [SKIP][12] ([i915#4525])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-iclb1/igt@gem_exec_balan...@parallel-keep-in-fence.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-iclb6/igt@gem_exec_balan...@parallel-keep-in-fence.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-tglb6/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-tglb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-skl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl10/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1:
- shard-skl:  [PASS][16] -> [FAIL][17] ([i915#2521])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/shard-skl6/igt@kms_async_flips@alternate-sync-async-f...@pipe-c-edp-1.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl6/igt@kms_async_flips@alternate-sync-async-f...@pipe-c-edp-1.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-apl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3886]) +1 
similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-apl7/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-skl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3886]) +2 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110237v1/shard-skl10/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-edid-change-during-suspend:
- shard-apl:  NOTRUN -> [SKIP][20] 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable YCbCr420 for VDSC

[Patchwork]

== Series Details ==

Series: Enable YCbCr420 for VDSC
URL   : https://patchwork.freedesktop.org/series/110253/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC

[Patchwork]

== Series Details ==

Series: Enable YCbCr420 for VDSC
URL   : https://patchwork.freedesktop.org/series/110253/
State : warning

== Summary ==

Error: dim checkpatch failed
725469674e5e drm/dp_helper: Add helper to check if the sink supports given 
format with DSC
-:20: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#20: FILE: include/drm/display/drm_dp_helper.h:196:
 }
+/* Check if sink supports DSC with given output format */

total: 0 errors, 0 warnings, 1 checks, 12 lines checked
f2af65f313e1 drm/i915/dp: Check if DSC supports the given output_format
359916e75b3c drm/i915: Adding the new registers for DSC
ee9a17fe123d drm/i915: Enable YCbCr420 for VDSC
-:189: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_row' - possible 
side-effects?
#189: FILE: drivers/gpu/drm/i915/display/intel_qp_tables.c:447:
+#define PARAM_TABLE(_minmax, _bpc, _row, _col, _is_420)  do { \
+   if (bpc == (_bpc)) {\
+   if (_is_420)\
+   return 
rc_range_##_minmax##qp420_##_bpc##bpc[_row][_col]; \
+   else\
+   return 
rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+   }   \
 } while (0)

-:189: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_col' - possible 
side-effects?
#189: FILE: drivers/gpu/drm/i915/display/intel_qp_tables.c:447:
+#define PARAM_TABLE(_minmax, _bpc, _row, _col, _is_420)  do { \
+   if (bpc == (_bpc)) {\
+   if (_is_420)\
+   return 
rc_range_##_minmax##qp420_##_bpc##bpc[_row][_col]; \
+   else\
+   return 
rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+   }   \
 } while (0)

total: 0 errors, 0 warnings, 2 checks, 228 lines checked
03df68b9395c drm/i915: Fill in native_420 field
411bbe96f7f6 drm/i915/dsc: Add debugfs entry to validate DSC YCbCr420
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#10: 
both RGB and YCbCr420 output formats by the sink, our policy is to try RGB first

-:26: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#26: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:1774:
+  
str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, 
DP_DSC_YCbCr420_Native)));

total: 0 errors, 2 warnings, 0 checks, 109 lines checked
84bb46c116fe drm/i915/dsc: Allow DSC only with YCbCr420 format when forced from 
debugfs
-:20: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#20: FILE: drivers/gpu/drm/i915/display/intel_dp.c:1510:
+   if (intel_dp->force_dsc_ycbcr420_en && pipe_config->output_format != 
INTEL_OUTPUT_FORMAT_YCBCR420)

total: 0 errors, 1 warnings, 0 checks, 9 lines checked
6b5d2bc2cd05 drm/i915: Code styling fixes

Re: [Intel-gfx] [PATCH 2/2] drm/i915/selftests: add igt_vma_move_to_active_unlocked

[Andrzej Hajda]

On 24.10.2022 17:08, Andi Shyti wrote:

Hi Andrzej,

On Mon, Oct 24, 2022 at 04:05:57PM +0200, Andrzej Hajda wrote:

On 21.10.2022 17:39, Andi Shyti wrote:

Hi Andrzej,

[...]


+static inline int __must_check
+igt_vma_move_to_active_unlocked(struct i915_vma *vma, struct i915_request *rq,
+   unsigned int flags)
+{
+   int err;
+
+   i915_vma_lock(vma);
+   err = _i915_vma_move_to_active(vma, rq, >fence, flags);
+   i915_vma_unlock(vma);
+   return err;
+}
+


there are calls to i915_vma_move_to_active also outside
selftests, why not having a i915_move_to_active_unlocked() in
i915_vma.h?


As I said before, Chris suggested real users of this call should use locking
explicitly.


Yeah, sure... I was just thinking about it... no big opinion,
besides I don't hink my proposal in Patch 1 makes things easier.


Besides here you break also the bisect, because between patch 1
and 2 the i915_move_to_avtive would also call
i915_request_await_object(). Right or am I getting confused?


Hmm, looking at v2, I do not see breakage. Patch 1 moves all occurrences of
i915_request_await_object inside i915_vma_move_to_active.
Patch 2, just replaces sequence of calls with call to new helper.


Are you sure?

I might be getting confused, but in Patch 1
"i915_vma_move_to_active()" takes "i915_request_await_object()"
inside. This affects all the calls to "i915_vma_move_to_active()"
in the selftests that are not actually requesting
"i915_request_await_object()".


Apparently I've forgot to answer this comment. Let's do it now.
Currently every call to i915_vma_move_to_active is prepended with 
i915_request_await_object, the only exception is 
prepare_shadow_batch_buffer.
And selftests always calls i915_request_await_object before either 
directly, either via move_to_active helpers.

Patch 1 transforms all these calls, so maybe looking at patch2 confuses you?
I have double checked things, did not find any issue.
If I missed sth please let me know.



We need to wait for Patch 2 in order to have a local redefinition
of "i915_vma_move_to_active()" for those selftests.


And this does not seems to be true, patch 1 alone is independent.

Regards
Andrzej




Andi

[Intel-gfx] [PATCH v2] drm/i915/userptr: restore probe_range behaviour

[Matthew Auld]

The conversion looks harmless, however the addr value is updated inside
the loop with the previous vm_end, which then incorrectly leads to
for_each_vma_range() iterating over stuff outside the range we care
about. Fix this by storing the end value separately. Also fix the case
where the range doesn't intersect with any vma, or if the vma itself
doesn't extend the entire range, which must mean we have hole at the
end. Both should result in an error, as per the previous behaviour.

v2: Fix the cases where the range is empty, or if there's a hole at
the end of the range

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7247
Testcase: igt@gem_userptr_blits@probe
Fixes: f683b9d61319 ("i915: use the VMA iterator")
Reported-by: kernel test robot 
Signed-off-by: Matthew Auld 
Cc: Tvrtko Ursulin 
Cc: Matthew Wilcox (Oracle) 
Cc: Liam R. Howlett 
Cc: Vlastimil Babka 
Cc: Yu Zhao 
---
 drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c 
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 1b1a22716722..ca7a388ba2bf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -427,9 +427,10 @@ probe_range(struct mm_struct *mm, unsigned long addr, 
unsigned long len)
 {
VMA_ITERATOR(vmi, mm, addr);
struct vm_area_struct *vma;
+   unsigned long end = addr + len;
 
mmap_read_lock(mm);
-   for_each_vma_range(vmi, vma, addr + len) {
+   for_each_vma_range(vmi, vma, end) {
/* Check for holes, note that we also update the addr below */
if (vma->vm_start > addr)
break;
@@ -441,7 +442,7 @@ probe_range(struct mm_struct *mm, unsigned long addr, 
unsigned long len)
}
mmap_read_unlock(mm);
 
-   if (vma)
+   if (vma || addr < end)
return -EFAULT;
return 0;
 }
-- 
2.37.3

Re: [Intel-gfx] [PATCH v2] drm/i915/guc: add CAT error handler

[Andrzej Hajda]

On 28.10.2022 12:06, Tvrtko Ursulin wrote:


Hi,

I can't really provide feedback on the GuC interactions so only some 
superficial comments below.


On 28/10/2022 10:34, Andrzej Hajda wrote:

Bad GPU memory accesses can result in catastrophic error notifications
being send from the GPU to the KMD via the GuC. Add a handler to process
the notification by printing a kernel message and dumping the related
engine state (if appropriate).
Since the same CAT error can be reported twice, log only 1st one and
assume error for the same context reported in less than 100ms after the
1st one is duplicated.

Signed-off-by: Andrzej Hajda 
---
  .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  1 +
  drivers/gpu/drm/i915/gt/uc/intel_guc.h    |  2 +
  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |  3 ++
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 47 +++
  4 files changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h

index f359bef046e0b2..f9a1c5642855e3 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -138,6 +138,7 @@ enum intel_guc_action {
  INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
  INTEL_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
  INTEL_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
+    INTEL_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
  INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION = 0x8002,
  INTEL_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003,
  INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h

index 804133df1ac9b4..61b412732d095a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -445,6 +445,8 @@ int intel_guc_engine_failure_process_msg(struct 
intel_guc *guc,

   const u32 *msg, u32 len);
  int intel_guc_error_capture_process_msg(struct intel_guc *guc,
  const u32 *msg, u32 len);
+int intel_guc_cat_error_process_msg(struct intel_guc *guc,
+    const u32 *msg, u32 len);
  struct intel_engine_cs *
  intel_guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 
instance);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c

index 2b22065e87bf9a..f55f724e264407 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -1035,6 +1035,9 @@ static int ct_process_request(struct 
intel_guc_ct *ct, struct ct_incoming_msg *r

  CT_ERROR(ct, "Received GuC exception notification!\n");
  ret = 0;
  break;
+    case INTEL_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR:
+    ret = intel_guc_cat_error_process_msg(guc, payload, len);
+    break;
  default:
  ret = -EOPNOTSUPP;
  break;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

index 693b07a977893d..f68ae4a0ad864d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4659,6 +4659,53 @@ int intel_guc_engine_failure_process_msg(struct 
intel_guc *guc,

  return 0;
  }
+int intel_guc_cat_error_process_msg(struct intel_guc *guc,
+    const u32 *msg, u32 len)
+{
+    static struct {
+    u32 ctx_id;
+    unsigned long after;
+    } ratelimit;
+    struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
+    struct drm_printer p = drm_info_printer(i915->drm.dev);
+    struct intel_context *ce;
+    unsigned long flags;
+    u32 ctx_id;
+
+    if (unlikely(len != 1)) {
+    drm_dbg(>drm, "Invalid length %u\n", len);
+    return -EPROTO;
+    }
+    ctx_id = msg[0];
+
+    if (ctx_id == ratelimit.ctx_id && 
time_is_after_jiffies(ratelimit.after))

+    return 0;


This will be suboptimal with multi-gpu and multi-tile. Not sure if 
ratelimiting is needed,


In many cases they comes in pairs:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12313/bat-adln-1/igt@i915_selftest@l...@hugepages.html#dmesg-warnings510
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12304/bat-rpls-2/igt@i915_selftest@l...@hugepages.html#dmesg-warnings514
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12298/bat-rpls-1/igt@i915_selftest@l...@hugepages.html#dmesg-warnings553

And since CAT error usually (always???) means engine hang, they 
apparently both indicate the same error.



but if it is, then perhaps move the state into 
struct intel_guc?


Or intel_context or intel_engine_cs, then it logs will be avoided till 
reset of the engine?

It becomes complicated now, I just wanted only better log message :)



Would it be worth counting the rate limited ones and then log how many 
were not logged when the next one is logged?


I have no idea why there are two messages, for me it looks like 

[Intel-gfx] ✓ Fi.CI.BAT: success for Add selftest for slpc tile interaction (rev2)

[Patchwork]

== Series Details ==

Series: Add selftest for slpc tile interaction (rev2)
URL   : https://patchwork.freedesktop.org/series/110248/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12315 -> Patchwork_110248v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110248v2/index.html

Participating hosts (41 -> 39)
--

  Missing(2): fi-ctg-p8600 fi-icl-u2 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110248v2:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@workarounds:
- {bat-adlm-1}:   [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110248v2/bat-adlm-1/igt@i915_selftest@l...@workarounds.html

  
Known issues


  Here are the changes found in Patchwork_110248v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#7073])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110248v2/fi-apl-guc/igt@core_hotunp...@unbind-rebind.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-skl-6600u:   NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110248v2/fi-skl-6600u/igt@kms_chamel...@common-hpd-after-suspend.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rpls-1}:   [DMESG-WARN][6] ([i915#6687]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110248v2/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_tiled_blits@basic:
- fi-pnv-d510:[SKIP][8] ([fdo#109271]) -> [PASS][9] +1 similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110248v2/fi-pnv-d510/igt@gem_tiled_bl...@basic.html

  * igt@i915_selftest@live@mman:
- fi-rkl-guc: [INCOMPLETE][10] ([i915#6794]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/fi-rkl-guc/igt@i915_selftest@l...@mman.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110248v2/fi-rkl-guc/igt@i915_selftest@l...@mman.html

  * igt@i915_selftest@live@slpc:
- {bat-rpls-1}:   [DMESG-FAIL][12] ([i915#6367]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/bat-rpls-1/igt@i915_selftest@l...@slpc.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110248v2/bat-rpls-1/igt@i915_selftest@l...@slpc.html

  
 Warnings 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[SKIP][14] ([fdo#109271]) -> [FAIL][15] ([i915#7229])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12315/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110248v2/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7073]: https://gitlab.freedesktop.org/drm/intel/issues/7073
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229


Build changes
-

  * Linux: CI_DRM_12315 -> Patchwork_110248v2

  CI-20190529: 20190529
  CI_DRM_12315: 

[Intel-gfx] ✗ Fi.CI.DOCS: warning for Add selftest for slpc tile interaction (rev2)

[Patchwork]

== Series Details ==

Series: Add selftest for slpc tile interaction (rev2)
URL   : https://patchwork.freedesktop.org/series/110248/
State : warning

== Summary ==

Error: make htmldocs had i915 warnings
./drivers/gpu/drm/i915/i915_perf_types.h:319: warning: Function parameter or 
member 'lock' not described in 'i915_perf_stream'

[Intel-gfx] ✓ Fi.CI.BAT: success for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev5)

[Patchwork]

== Series Details ==

Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev5)
URL   : https://patchwork.freedesktop.org/series/107550/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12314 -> Patchwork_107550v5


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v5/index.html

Participating hosts (41 -> 40)
--

  Additional (1): fi-tgl-dsi 
  Missing(2): fi-ctg-p8600 fi-rkl-11600 

Known issues


  Here are the changes found in Patchwork_107550v5 that come from known issues:

### IGT changes ###

 Possible fixes 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[SKIP][1] ([fdo#109271]) -> [PASS][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v5/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_exec_suspend@basic-s0@smem:
- {bat-adlm-1}:   [DMESG-WARN][3] ([i915#2867]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v5/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@gt_pm:
- {fi-jsl-1}: [DMESG-FAIL][5] ([i915#1886]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v5/fi-jsl-1/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@requests:
- {bat-rpls-1}:   [INCOMPLETE][7] ([i915#4983] / [i915#6257]) -> 
[PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/bat-rpls-1/igt@i915_selftest@l...@requests.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v5/bat-rpls-1/igt@i915_selftest@l...@requests.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5828]: https://gitlab.freedesktop.org/drm/intel/issues/5828
  [i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
  [i915#6856]: https://gitlab.freedesktop.org/drm/intel/issues/6856
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7125]: https://gitlab.freedesktop.org/drm/intel/issues/7125


Build changes
-

  * Linux: CI_DRM_12314 -> Patchwork_107550v5

  CI-20190529: 20190529
  CI_DRM_12314: 6923e120f0a68b493aa2b06675a8f262a4007b90 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7028: 9e635a1c502970e7e6d64112d409392a2f01c688 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_107550v5: 6923e120f0a68b493aa2b06675a8f262a4007b90 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

0ddd21d9c81c drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints
789a4b174f13 drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP
7c4d61e9a7fb drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC
2383db7973f3 drm/i915/dp: Avoid DSC with output_format YCBC420
f51d6ee5f65d drm/i915/display: Add helper function to check if sink_format is 
420
59f37231b62a drm/i915/display: Use sink_format instead of ycbcr420_output flag
108c464ab5de drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state 
sink_format
cb822fc478a7 drm/i915/display: Add new member in intel_dp to store ycbcr420 
passthrough cap
85da0791c9c4 drm/i915/display: Add new member to configure PCON 

[Intel-gfx] [PATCH v4 4/8] drm/i915: Enable YCbCr420 for VDSC

[Swati Sharma]

From: Suraj Kandpal 

Implementation of VDSC for YCbCr420.

Signed-off-by: Suraj Kandpal 
---
 .../gpu/drm/i915/display/intel_qp_tables.c| 187 --
 .../gpu/drm/i915/display/intel_qp_tables.h|   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c |   4 +-
 3 files changed, 180 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c 
b/drivers/gpu/drm/i915/display/intel_qp_tables.c
index 6f8e4ec5c0fb..6e86c0971d24 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -17,6 +17,15 @@
 /* from BPP 6 to 36 in steps of 0.5 */
 #define RC_RANGE_QP444_12BPC_MAX_NUM_BPP   61
 
+/* from BPP 6 to 24 in steps of 0.5 */
+#define RC_RANGE_QP420_8BPC_MAX_NUM_BPP17
+
+/* from BPP 6 to 30 in steps of 0.5 */
+#define RC_RANGE_QP420_10BPC_MAX_NUM_BPP   23
+
+/* from BPP 6 to 36 in steps of 0.5 */
+#define RC_RANGE_QP420_12BPC_MAX_NUM_BPP   29
+
 /*
  * These qp tables are as per the C model
  * and it has the rows pointing to bpps which increment
@@ -283,26 +292,182 @@ static const u8 
rc_range_maxqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC
  11, 11, 10, 10, 10, 10, 10, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 
5, 4 }
 };
 
-#define PARAM_TABLE(_minmax, _bpc, _row, _col)  do { \
-   if (bpc == (_bpc)) \
-   return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+static const u8 
rc_range_minqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MAX_NUM_BPP] = {
+   { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+   { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+   { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+   { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+   { 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 },
+   { 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+   { 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
+   { 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 0 },
+   { 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 0 },
+   { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1 },
+   { 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 1, 1 },
+   { 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 2, 2, 1 },
+   { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 3, 3, 2, 1 },
+   { 9, 8, 8, 7, 7, 7, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 2 },
+   { 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3 }
+};
+
+static const u8 
rc_range_maxqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MAX_NUM_BPP] = {
+   { 4, 4, 3, 3, 2, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+   { 4, 4, 4, 4, 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+   { 5, 5, 5, 5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+   { 6, 6, 6, 6, 6, 5, 4, 3, 2, 2, 2, 1, 1, 1, 1, 0, 0 },
+   { 7, 7, 7, 7, 7, 5, 4, 3, 2, 2, 2, 2, 2, 1, 1, 1, 0 },
+   { 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 2, 2, 2, 1, 1, 0 },
+   { 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1 },
+   { 8, 8, 8, 8, 8, 7, 6, 5, 4, 4, 4, 3, 3, 2, 2, 2, 1 },
+   { 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 },
+   { 10, 10, 9, 9, 9, 8, 7, 6, 5, 5, 5, 4, 4, 3, 3, 2, 2 },
+   { 10, 10, 10, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 2, 2 },
+   { 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2 },
+   { 11, 11, 11, 10, 9, 9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3, 2 },
+   { 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4, 4, 4, 3 },
+   { 14, 13, 13, 12, 11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4 }
+};
+
+static const u8 
rc_range_minqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_MAX_NUM_BPP] = 
{
+   { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+   { 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+   { 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+   { 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0 },
+   { 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 0, 0, 0, 0 },
+   { 7, 7, 7, 7, 7, 6, 5, 5, 5, 5, 5, 4, 3, 3, 2, 2, 1, 1, 1, 1, 1, 0, 0 },
+   { 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 2, 2, 2, 2, 1, 1, 1, 0 },
+   { 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 4, 4, 4, 3, 2, 2, 2, 1, 1, 1, 0 },
+   { 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 2, 1, 1 },
+   { 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1, 1 },
+   { 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 },
+   { 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 7, 6, 6, 5, 4, 4, 3, 3, 2, 1 },
+   { 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 2, 1 },
+   { 13, 12, 12, 11, 11, 11, 11, 11, 11, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4, 3, 
3,
+ 2, 2 },
+   { 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 10, 9, 8, 8, 7, 6, 6, 
5,
+ 5, 4, 4 }
+};
+
+static const u8 

[Intel-gfx] [PATCH 8/8] drm/i915: Code styling fixes

[Swati Sharma]

Removed extra newlines and did few styling fixes.

Signed-off-by: Swati Sharma 
---
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 1f051f74a00a..2f19a84eebfe 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1438,7 +1438,6 @@ static ssize_t wm_latency_write(struct file *file, const 
char __user *ubuf,
return len;
 }
 
-
 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
size_t len, loff_t *offp)
 {
@@ -1787,13 +1786,13 @@ static ssize_t i915_dsc_fec_support_write(struct file 
*file,
  const char __user *ubuf,
  size_t len, loff_t *offp)
 {
-   bool dsc_enable = false;
-   int ret;
struct drm_connector *connector =
((struct seq_file *)file->private_data)->private;
struct intel_encoder *encoder = 
intel_attached_encoder(to_intel_connector(connector));
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+   bool dsc_enable = false;
+   int ret;
 
if (len == 0)
return 0;
@@ -1810,6 +1809,7 @@ static ssize_t i915_dsc_fec_support_write(struct file 
*file,
intel_dp->force_dsc_en = dsc_enable;
 
*offp += len;
+
return len;
 }
 
-- 
2.25.1

[Intel-gfx] [PATCH v4 5/8] drm/i915: Fill in native_420 field

[Swati Sharma]

From: Suraj Kandpal 

Now that we have laid the groundwork for YUV420 Enablement
we fill up native_420 field in vdsc_cfg and add appropriate
checks wherever required.

---v2
-adding native_422 field as 0 [Vandita]
-filling in second_line_bpg_offset, second_line_offset_adj
and nsl_bpg_offset in vds_cfg when native_420 is true

---v3
-adding display version check to solve igt issue

Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/i915/display/icl_dsi.c|  2 -
 drivers/gpu/drm/i915/display/intel_dp.c   |  3 -
 drivers/gpu/drm/i915/display/intel_vdsc.c | 74 ++-
 3 files changed, 71 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
b/drivers/gpu/drm/i915/display/icl_dsi.c
index e05e7cd6c412..f0c79247cc83 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1625,8 +1625,6 @@ static int gen11_dsi_dsc_compute_config(struct 
intel_encoder *encoder,
if (crtc_state->dsc.slice_count > 1)
crtc_state->dsc.dsc_split = true;
 
-   vdsc_cfg->convert_rgb = true;
-
/* FIXME: initialize from VBT */
vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index a5c31ac1ec73..b7b7b40ce7ff 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1440,9 +1440,6 @@ static int intel_dp_dsc_compute_params(struct 
intel_encoder *encoder,
min(intel_dp_source_dsc_version_minor(intel_dp),
intel_dp_sink_dsc_version_minor(intel_dp));
 
-   vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP 
- DP_DSC_SUPPORT] &
-   DP_DSC_RGB;
-
line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
if (!line_buf_depth) {
drm_dbg_kms(>drm,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c 
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index a642975a1b61..66a4f55c8955 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -462,14 +462,47 @@ int intel_dsc_compute_params(struct intel_crtc_state 
*pipe_config)
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 pipe_config->dsc.slice_count);
-
-   /* Gen 11 does not support YCbCr */
+   /*
+* According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb 
is 0
+* else 1
+*/
+   vdsc_cfg->convert_rgb = !(pipe_config->output_format == 
INTEL_OUTPUT_FORMAT_YCBCR420 ||
+ pipe_config->output_format == 
INTEL_OUTPUT_FORMAT_YCBCR444);
+
+   if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+   vdsc_cfg->native_420 = true;
+   /* We do not support YcBCr422 as of now */
+   vdsc_cfg->native_422 = false;
+   /* Gen 11 does not support YCbCr422 */
vdsc_cfg->simple_422 = false;
/* Gen 11 does not support VBR */
vdsc_cfg->vbr_enable = false;
 
/* Gen 11 only supports integral values of bpp */
vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+   /*
+* According to DSC 1.2 specs if native_420 is set:
+* -We need to double the current bpp.
+* -second_line_bpg_offset is 12 in general and equal to 
2*(slice_height-1) if slice
+* height < 8.
+* -second_line_offset_adj is 512 as shown by emperical values to yeild 
best chroma
+* preservation in second line.
+* -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 
then rounded
+* up to 16 fractional bits, we left shift second line offset by 11 to 
preserve 11
+* fractional bits.
+*/
+   if (vdsc_cfg->native_420) {
+   vdsc_cfg->bits_per_pixel <<= 1;
+   if (vdsc_cfg->slice_height >= 8)
+   vdsc_cfg->second_line_bpg_offset = 12;
+   else
+   vdsc_cfg->second_line_bpg_offset =
+   2 * (vdsc_cfg->slice_height - 1);
+   vdsc_cfg->second_line_offset_adj = 512;
+   vdsc_cfg->nsl_bpg_offset = 
DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,
+   vdsc_cfg->slice_height 
- 1);
+   }
+
vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
 
for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
@@ -596,8 +629,13 @@ static void intel_dsc_pps_configure(const struct 
intel_crtc_state *crtc_state)
DSC_VER_MIN_SHIFT |
vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
-   if (vdsc_cfg->dsc_version_minor == 2)
+   if (vdsc_cfg->dsc_version_minor == 2) {
  

[Intel-gfx] [PATCH v2 2/8] drm/i915/dp: Check if DSC supports the given output_format

[Swati Sharma]

From: Ankit Nautiyal 

Go with DSC only if the given output_format is supported.

v2: Use drm helper to get DSC format support for sink.

Signed-off-by: Ankit Nautiyal 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 28 +
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7400d6b4c587..a5c31ac1ec73 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1464,6 +1464,31 @@ static int intel_dp_dsc_compute_params(struct 
intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
 }
 
+static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
+enum intel_output_format output_format)
+{
+   u8 sink_dsc_format;
+
+   switch (output_format) {
+   case INTEL_OUTPUT_FORMAT_RGB:
+   sink_dsc_format = DP_DSC_RGB;
+   break;
+   case INTEL_OUTPUT_FORMAT_YCBCR444:
+   sink_dsc_format = DP_DSC_YCbCr444;
+   break;
+   case INTEL_OUTPUT_FORMAT_YCBCR420:
+   if (min(intel_dp_source_dsc_version_minor(intel_dp),
+   intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
+   return false;
+   sink_dsc_format = DP_DSC_YCbCr420_Native;
+   break;
+   default:
+   return false;
+   }
+
+   return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, 
sink_dsc_format);
+}
+
 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
   struct intel_crtc_state *pipe_config,
   struct drm_connector_state *conn_state,
@@ -1482,6 +1507,9 @@ static int intel_dp_dsc_compute_config(struct intel_dp 
*intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
 
+   if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
+   return -EINVAL;
+
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, 
conn_state->max_requested_bpc);
 
if (intel_dp->force_dsc_bpc) {
-- 
2.25.1

[Intel-gfx] [PATCH 7/8] drm/i915/dsc: Allow DSC only with YCbCr420 format when forced from debugfs

[Swati Sharma]

If force_dsc_ycbcr420_en is set through debugfs allow DSC iff
output_format is INTEL_OUTPUT_FORMAT_YCBCR420.

Signed-off-by: Swati Sharma 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index b7b7b40ce7ff..4e7f0fc4a3cf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1507,6 +1507,9 @@ static int intel_dp_dsc_compute_config(struct intel_dp 
*intel_dp,
if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
return -EINVAL;
 
+   if (intel_dp->force_dsc_ycbcr420_en && pipe_config->output_format != 
INTEL_OUTPUT_FORMAT_YCBCR420)
+   return -EINVAL;
+
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, 
conn_state->max_requested_bpc);
 
if (intel_dp->force_dsc_bpc) {
-- 
2.25.1

[Intel-gfx] [PATCH 6/8] drm/i915/dsc: Add debugfs entry to validate DSC YCbCr420

[Swati Sharma]

DSC_YCBCR420_Sink_Support entry is added to i915_dsc_fec_support_show
to depict if sink supports DSC YCbCr420.
Also, new debugfs entry is created to enforce YCbCr420 output format.
This is required because of our driver policy. If a mode is supported in
both RGB and YCbCr420 output formats by the sink, our policy is to try RGB first
and fall back to YCbCr420, if mode cannot be shown using RGB.
So, to test YCbCr420, we need a debugfs entry (force_dsc_ycbcr420) to force this
output format; so that YCbCr420 code gets executed.

Signed-off-by: Swati Sharma 
---
 .../drm/i915/display/intel_display_debugfs.c  | 84 +++
 .../drm/i915/display/intel_display_types.h|  1 +
 2 files changed, 85 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cfc056a05bbf..1f051f74a00a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1770,6 +1770,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, 
void *data)
   
str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
seq_printf(m, "Force_DSC_Enable: %s\n",
   str_yes_no(intel_dp->force_dsc_en));
+   seq_printf(m, "DSC_YCBCR420_Sink_Support: %s\n",
+  
str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, 
DP_DSC_YCbCr420_Native)));
if (!intel_dp_is_edp(intel_dp))
seq_printf(m, "FEC_Sink_Support: %s\n",
   
str_yes_no(drm_dp_sink_supports_fec(intel_dp->fec_capable)));
@@ -1893,6 +1895,85 @@ static const struct file_operations i915_dsc_bpc_fops = {
.write = i915_dsc_bpc_write
 };
 
+static int i915_dsc_ycbcr420_show(struct seq_file *m, void *data)
+{
+   struct drm_connector *connector = m->private;
+   struct drm_device *dev = connector->dev;
+   struct drm_crtc *crtc;
+   struct intel_dp *intel_dp;
+   struct intel_crtc_state *crtc_state;
+   struct intel_encoder *encoder = 
intel_attached_encoder(to_intel_connector(connector));
+   int ret;
+
+   if (!encoder)
+   return -ENODEV;
+
+   ret = 
drm_modeset_lock_single_interruptible(>mode_config.connection_mutex);
+   if (ret)
+   return ret;
+
+   crtc = connector->state->crtc;
+   if (connector->status != connector_status_connected || !crtc) {
+   ret = -ENODEV;
+   goto out;
+   }
+
+   intel_dp = intel_attached_dp(to_intel_connector(connector));
+   crtc_state = to_intel_crtc_state(crtc->state);
+   seq_printf(m, "Force_DSC_YCBCR420_Enable: %s\n",
+  str_yes_no(intel_dp->force_dsc_ycbcr420_en));
+
+out:   drm_modeset_unlock(>mode_config.connection_mutex);
+
+   return ret;
+}
+
+static ssize_t i915_dsc_ycbcr420_write(struct file *file,
+  const char __user *ubuf,
+  size_t len, loff_t *offp)
+{
+   struct drm_connector *connector =
+   ((struct seq_file *)file->private_data)->private;
+   struct intel_encoder *encoder = 
intel_attached_encoder(to_intel_connector(connector));
+   struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+   bool dsc_ycbcr420_enable = false;
+   int ret;
+
+   if (len == 0)
+   return 0;
+
+   drm_dbg(>drm,
+   "Copied %zu bytes from user to force YCBCR420 for DSC\n", len);
+
+   ret = kstrtobool_from_user(ubuf, len, _ycbcr420_enable);
+   if (ret < 0)
+   return ret;
+
+   drm_dbg(>drm, "Got %s for DSC YCBCR420 Enable\n",
+   (dsc_ycbcr420_enable) ? "true" : "false");
+   intel_dp->force_dsc_ycbcr420_en = dsc_ycbcr420_enable;
+
+   *offp += len;
+
+   return len;
+}
+
+static int i915_dsc_ycbcr420_open(struct inode *inode,
+ struct file *file)
+{
+   return single_open(file, i915_dsc_ycbcr420_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_ycbcr420_fops = {
+   .owner = THIS_MODULE,
+   .open = i915_dsc_ycbcr420_open,
+   .read = seq_read,
+   .llseek = seq_lseek,
+   .release = single_release,
+   .write = i915_dsc_ycbcr420_write
+};
+
 /*
  * Returns the Current CRTC's bpc.
  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1964,6 +2045,9 @@ void intel_connector_debugfs_add(struct intel_connector 
*intel_connector)
 
debugfs_create_file("i915_dsc_bpc", 0644, root,
connector, _dsc_bpc_fops);
+
+   debugfs_create_file("i915_dsc_ycbcr420", 0644, root,
+   connector, _dsc_ycbcr420_fops);
}
 
if 

[Intel-gfx] [PATCH v4 3/8] drm/i915: Adding the new registers for DSC

[Swati Sharma]

From: Suraj Kandpal 

Adding new DSC register which are introducted MTL onwards

Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/i915/i915_reg.h | 28 
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c0da50c0dc7..fc6d6651b775 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7841,6 +7841,8 @@ enum skl_power_gate {
 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
   
_ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
   
_ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
+#define  DSC_NATIVE_422_ENABLE (1 << 23)
+#define  DSC_NATIVE_420_ENABLE (1 << 22)
 #define  DSC_ALT_ICH_SEL   (1 << 20)
 #define  DSC_VBR_ENABLE(1 << 19)
 #define  DSC_422_ENABLE(1 << 18)
@@ -8085,6 +8087,32 @@ enum skl_power_gate {
 #define  DSC_SLICE_PER_LINE(slice_per_line)((slice_per_line) << 16)
 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)
((slice_chunk_size) << 0)
 
+/* MTL Display Stream Compression registers */
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB  0x782B4
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB  0x783B4
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC  0x784B4
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC  0x785B4
+#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe)_MMIO_PIPE((pipe) - 
PIPE_B, \
+  
_MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \
+  
_MTL_DSC0_PICTURE_PARAMETER_SET_17_PC)
+#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe)_MMIO_PIPE((pipe) - 
PIPE_B, \
+  
_MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
+  
_MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
+#define DSC_SL_BPG_OFFSET(offset)  ((offset) << 27)
+
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB  0x782B8
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB  0x783B8
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC  0x784B8
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC  0x785B8
+#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe)_MMIO_PIPE((pipe) - 
PIPE_B, \
+  
_MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \
+  
_MTL_DSC0_PICTURE_PARAMETER_SET_18_PC)
+#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe)_MMIO_PIPE((pipe) - 
PIPE_B, \
+  
_MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
+  
_MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
+#define DSC_NSL_BPG_OFFSET(offset) ((offset) << 16)
+#define DSC_SL_OFFSET_ADJ(offset)  ((offset) << 0)
+
 /* Icelake Rate Control Buffer Threshold Registers */
 #define DSCA_RC_BUF_THRESH_0   _MMIO(0x6B230)
 #define DSCA_RC_BUF_THRESH_0_UDW   _MMIO(0x6B230 + 4)
-- 
2.25.1

[Intel-gfx] [PATCH v5 0/8] Enable YCbCr420 for VDSC

[Swati Sharma]

This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.

---v2
-adding fields missed for vdsc_cfg [Vandita]
-adding corresponding registers and writing to the [Vandita]

---v3
-adding 11 bit left shift missed in nsl_bpg_offset calculation

---v4
-adding display version check before writing in new pps register

---v5
-added helper to check if sink supports given format with DSC
-added debugfs entry to enforce DSC with YCbCr420 format only

Ankit Nautiyal (2):
  drm/dp_helper: Add helper to check if the sink supports given format
with DSC
  drm/i915/dp: Check if DSC supports the given output_format

Suraj Kandpal (3):
  drm/i915: Adding the new registers for DSC
  drm/i915: Enable YCbCr420 for VDSC
  drm/i915: Fill in native_420 field

Swati Sharma (3):
  drm/i915/dsc: Add debugfs entry to validate DSC YCbCr420
  drm/i915/dsc: Allow DSC only with YCbCr420 format when forced from
debugfs
  drm/i915: Code styling fixes

 drivers/gpu/drm/i915/display/icl_dsi.c|   2 -
 .../drm/i915/display/intel_display_debugfs.c  |  90 -
 .../drm/i915/display/intel_display_types.h|   1 +
 drivers/gpu/drm/i915/display/intel_dp.c   |  34 +++-
 .../gpu/drm/i915/display/intel_qp_tables.c| 187 --
 .../gpu/drm/i915/display/intel_qp_tables.h|   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c |  78 +++-
 drivers/gpu/drm/i915/i915_reg.h   |  28 +++
 include/drm/display/drm_dp_helper.h   |   6 +
 9 files changed, 404 insertions(+), 26 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH 1/8] drm/dp_helper: Add helper to check if the sink supports given format with DSC

[Swati Sharma]

From: Ankit Nautiyal 

Add helper function to check if the DP sink supports DSC with the given
output format.

Signed-off-by: Ankit Nautiyal 
---
 include/drm/display/drm_dp_helper.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/include/drm/display/drm_dp_helper.h 
b/include/drm/display/drm_dp_helper.h
index ab55453f2d2c..6c1706280746 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -193,6 +193,12 @@ drm_dp_dsc_sink_max_slice_width(const u8 
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
DP_DSC_SLICE_WIDTH_MULTIPLIER;
 }
+/* Check if sink supports DSC with given output format */
+static inline bool
+drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 
u8 output_format)
+{
+   return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & 
output_format;
+}
 
 /* Forward Error Correction Support on DP 1.4 */
 static inline bool
-- 
2.25.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: add CAT error handler (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: add CAT error handler (rev2)
URL   : https://patchwork.freedesktop.org/series/109865/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12314 -> Patchwork_109865v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/index.html

Participating hosts (41 -> 41)
--

  Additional (1): fi-tgl-dsi 
  Missing(1): fi-ctg-p8600 

Known issues


  Here are the changes found in Patchwork_109865v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600:   NOTRUN -> [FAIL][1] ([fdo#103375])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@migrate:
- bat-adlp-4: [PASS][2] -> [INCOMPLETE][3] ([i915#7308])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/bat-adlp-4/igt@i915_selftest@l...@migrate.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/bat-adlp-4/igt@i915_selftest@l...@migrate.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-rkl-11600:   NOTRUN -> [SKIP][4] ([fdo#111827])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/fi-rkl-11600/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][5] ([i915#4312])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/bat-adlp-4/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[SKIP][6] ([fdo#109271]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_exec_suspend@basic-s0@smem:
- {bat-adlm-1}:   [DMESG-WARN][8] ([i915#2867]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/bat-adlm-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@gt_pm:
- {fi-jsl-1}: [DMESG-FAIL][10] ([i915#1886]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/fi-jsl-1/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@requests:
- {bat-rpls-1}:   [INCOMPLETE][12] ([i915#4983] / [i915#6257]) -> 
[PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/bat-rpls-1/igt@i915_selftest@l...@requests.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/bat-rpls-1/igt@i915_selftest@l...@requests.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [INCOMPLETE][14] ([i915#4817]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12314/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109865v2/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5354]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev5)

[Patchwork]

== Series Details ==

Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev5)
URL   : https://patchwork.freedesktop.org/series/107550/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/guc: add CAT error handler (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: add CAT error handler (rev2)
URL   : https://patchwork.freedesktop.org/series/109865/
State : warning

== Summary ==

Error: make htmldocs had i915 warnings
./drivers/gpu/drm/i915/i915_perf_types.h:319: warning: Function parameter or 
member 'lock' not described in 'i915_perf_stream'

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915/guc/slpc: Add selftest for slpc tile-tile interaction

[Tvrtko Ursulin]

Hi,

I peeked inside from curiosity and was pleasantly surprise to see 
kthread_work is used! Some comments below.


On 28/10/2022 10:50, Riana Tauro wrote:

Run a workload on tiles simultaneously by requesting for RP0 frequency.
Pcode can however limit the frequency being granted due to throttling
reasons. This test fails if there is any throttling

v2: Fix build error

Signed-off-by: Riana Tauro 
---
  drivers/gpu/drm/i915/gt/selftest_slpc.c | 63 +
  1 file changed, 63 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c 
b/drivers/gpu/drm/i915/gt/selftest_slpc.c
index 82ec95a299f6..d19486772f5a 100644
--- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
@@ -13,6 +13,14 @@ enum test_type {
VARY_MAX,
MAX_GRANTED,
SLPC_POWER,
+   TILE_INTERACTION,
+};
+
+struct slpc_thread {
+   struct kthread_worker *worker;
+   struct kthread_work work;
+   struct intel_gt *gt;
+   int result;
  };
  
  static int slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 freq)

@@ -310,6 +318,7 @@ static int run_test(struct intel_gt *gt, int test_type)
break;
  
  		case MAX_GRANTED:

+   case TILE_INTERACTION:
/* Media engines have a different RP0 */
if (engine->class == VIDEO_DECODE_CLASS ||
engine->class == VIDEO_ENHANCEMENT_CLASS) {
@@ -325,6 +334,7 @@ static int run_test(struct intel_gt *gt, int test_type)
case SLPC_POWER:
err = slpc_power(gt, engine);
break;
+


Noise.


}
  
  		if (test_type != SLPC_POWER) {

@@ -426,6 +436,58 @@ static int live_slpc_power(void *arg)
return ret;
  }
  
+static void slpc_spinner_thread(struct kthread_work *work)

+{
+   struct slpc_thread *thread = container_of(work, typeof(*thread), work);
+
+   thread->result = run_test(thread->gt, TILE_INTERACTION);
+}
+
+static int live_slpc_tile_interaction(void *arg)
+{
+   struct drm_i915_private *i915 = arg;
+   struct intel_gt *gt;
+   struct slpc_thread *threads;
+   int i = 0, ret = 0;
+
+   threads = kcalloc(I915_MAX_GT, sizeof(*threads), GFP_KERNEL);
+   if (!threads)
+   return -ENOMEM;
+
+   for_each_gt(gt, i915, i) {
+   pr_info("Running on GT: %d\n", gt->info.id);


Not sure logging these makes sense since test runs on all tiles in 
parallel anyway.



+   threads[i].worker = kthread_create_worker(0, 
"igt/slpc_parallel:%d", gt->info.id);
+
+   if (IS_ERR(threads[i].worker)) {
+   ret = PTR_ERR(threads[i].worker);
+   break;
+   }
+
+   threads[i].gt = gt;
+   threads[i].result = 0;


No need to zero result due kcalloc and runs do not repeat.


+   kthread_init_work([i].work, slpc_spinner_thread);
+   kthread_queue_work(threads[i].worker, [i].work);
+   }
+
+   for_each_gt(gt, i915, i) {
+   int status;
+
+   if (!threads[i].worker)
+   continue;


Could be ERR_PTR by the look of it so it would crash below. Either gate 
on threads[i].gt or use IS_ERR_OR_NULL.


Regards,

Tvrtko


+
+   kthread_flush_work([i].work);
+   status = READ_ONCE(threads[i].result);
+   if (status && !ret) {
+   pr_err("%s GT %d failed ", __func__, gt->info.id);
+   ret = status;
+   }
+   kthread_destroy_worker(threads[i].worker);
+   }
+
+   kfree(threads);
+   return ret;
+}
+
  int intel_slpc_live_selftests(struct drm_i915_private *i915)
  {
static const struct i915_subtest tests[] = {
@@ -433,6 +495,7 @@ int intel_slpc_live_selftests(struct drm_i915_private *i915)
SUBTEST(live_slpc_vary_min),
SUBTEST(live_slpc_max_granted),
SUBTEST(live_slpc_power),
+   SUBTEST(live_slpc_tile_interaction),
};
  
  	struct intel_gt *gt;

Re: [Intel-gfx] [PATCH v2] drm/i915/guc: add CAT error handler

[Tvrtko Ursulin]

Hi,

I can't really provide feedback on the GuC interactions so only some 
superficial comments below.


On 28/10/2022 10:34, Andrzej Hajda wrote:

Bad GPU memory accesses can result in catastrophic error notifications
being send from the GPU to the KMD via the GuC. Add a handler to process
the notification by printing a kernel message and dumping the related
engine state (if appropriate).
Since the same CAT error can be reported twice, log only 1st one and
assume error for the same context reported in less than 100ms after the
1st one is duplicated.

Signed-off-by: Andrzej Hajda 
---
  .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  1 +
  drivers/gpu/drm/i915/gt/uc/intel_guc.h|  2 +
  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |  3 ++
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 47 +++
  4 files changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index f359bef046e0b2..f9a1c5642855e3 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -138,6 +138,7 @@ enum intel_guc_action {
INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
INTEL_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
INTEL_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
+   INTEL_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION = 0x8002,
INTEL_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003,
INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 804133df1ac9b4..61b412732d095a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -445,6 +445,8 @@ int intel_guc_engine_failure_process_msg(struct intel_guc 
*guc,
 const u32 *msg, u32 len);
  int intel_guc_error_capture_process_msg(struct intel_guc *guc,
const u32 *msg, u32 len);
+int intel_guc_cat_error_process_msg(struct intel_guc *guc,
+   const u32 *msg, u32 len);
  
  struct intel_engine_cs *

  intel_guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 2b22065e87bf9a..f55f724e264407 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -1035,6 +1035,9 @@ static int ct_process_request(struct intel_guc_ct *ct, 
struct ct_incoming_msg *r
CT_ERROR(ct, "Received GuC exception notification!\n");
ret = 0;
break;
+   case INTEL_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR:
+   ret = intel_guc_cat_error_process_msg(guc, payload, len);
+   break;
default:
ret = -EOPNOTSUPP;
break;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 693b07a977893d..f68ae4a0ad864d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4659,6 +4659,53 @@ int intel_guc_engine_failure_process_msg(struct 
intel_guc *guc,
return 0;
  }
  
+int intel_guc_cat_error_process_msg(struct intel_guc *guc,

+   const u32 *msg, u32 len)
+{
+   static struct {
+   u32 ctx_id;
+   unsigned long after;
+   } ratelimit;
+   struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
+   struct drm_printer p = drm_info_printer(i915->drm.dev);
+   struct intel_context *ce;
+   unsigned long flags;
+   u32 ctx_id;
+
+   if (unlikely(len != 1)) {
+   drm_dbg(>drm, "Invalid length %u\n", len);
+   return -EPROTO;
+   }
+   ctx_id = msg[0];
+
+   if (ctx_id == ratelimit.ctx_id && 
time_is_after_jiffies(ratelimit.after))
+   return 0;


This will be suboptimal with multi-gpu and multi-tile. Not sure if 
ratelimiting is needed, but if it is, then perhaps move the state into 
struct intel_guc?


Would it be worth counting the rate limited ones and then log how many 
were not logged when the next one is logged?


Should the condition be inverted - !time_is_after?


+
+   ratelimit.ctx_id = ctx_id;
+   ratelimit.after = jiffies + msecs_to_jiffies(100);
+
+   if (unlikely(ctx_id == -1)) {
+   drm_err(>drm,
+   "GPU reported catastrophic error without providing valid 
context\n");
+   return 0;
+   }
+
+   xa_lock_irqsave(>context_lookup, flags);


The only caller seems to be a worker so just _irq I guess. 
ct_process_incoming_requests has the same issue but I haven't looked 
into other handlers called from ct_process_request.

[Intel-gfx] [PATCH v2 1/1] drm/i915/guc/slpc: Add selftest for slpc tile-tile interaction

[Riana Tauro]

Run a workload on tiles simultaneously by requesting for RP0 frequency.
Pcode can however limit the frequency being granted due to throttling
reasons. This test fails if there is any throttling

v2: Fix build error

Signed-off-by: Riana Tauro 
---
 drivers/gpu/drm/i915/gt/selftest_slpc.c | 63 +
 1 file changed, 63 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c 
b/drivers/gpu/drm/i915/gt/selftest_slpc.c
index 82ec95a299f6..d19486772f5a 100644
--- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
@@ -13,6 +13,14 @@ enum test_type {
VARY_MAX,
MAX_GRANTED,
SLPC_POWER,
+   TILE_INTERACTION,
+};
+
+struct slpc_thread {
+   struct kthread_worker *worker;
+   struct kthread_work work;
+   struct intel_gt *gt;
+   int result;
 };
 
 static int slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 freq)
@@ -310,6 +318,7 @@ static int run_test(struct intel_gt *gt, int test_type)
break;
 
case MAX_GRANTED:
+   case TILE_INTERACTION:
/* Media engines have a different RP0 */
if (engine->class == VIDEO_DECODE_CLASS ||
engine->class == VIDEO_ENHANCEMENT_CLASS) {
@@ -325,6 +334,7 @@ static int run_test(struct intel_gt *gt, int test_type)
case SLPC_POWER:
err = slpc_power(gt, engine);
break;
+
}
 
if (test_type != SLPC_POWER) {
@@ -426,6 +436,58 @@ static int live_slpc_power(void *arg)
return ret;
 }
 
+static void slpc_spinner_thread(struct kthread_work *work)
+{
+   struct slpc_thread *thread = container_of(work, typeof(*thread), work);
+
+   thread->result = run_test(thread->gt, TILE_INTERACTION);
+}
+
+static int live_slpc_tile_interaction(void *arg)
+{
+   struct drm_i915_private *i915 = arg;
+   struct intel_gt *gt;
+   struct slpc_thread *threads;
+   int i = 0, ret = 0;
+
+   threads = kcalloc(I915_MAX_GT, sizeof(*threads), GFP_KERNEL);
+   if (!threads)
+   return -ENOMEM;
+
+   for_each_gt(gt, i915, i) {
+   pr_info("Running on GT: %d\n", gt->info.id);
+   threads[i].worker = kthread_create_worker(0, 
"igt/slpc_parallel:%d", gt->info.id);
+
+   if (IS_ERR(threads[i].worker)) {
+   ret = PTR_ERR(threads[i].worker);
+   break;
+   }
+
+   threads[i].gt = gt;
+   threads[i].result = 0;
+   kthread_init_work([i].work, slpc_spinner_thread);
+   kthread_queue_work(threads[i].worker, [i].work);
+   }
+
+   for_each_gt(gt, i915, i) {
+   int status;
+
+   if (!threads[i].worker)
+   continue;
+
+   kthread_flush_work([i].work);
+   status = READ_ONCE(threads[i].result);
+   if (status && !ret) {
+   pr_err("%s GT %d failed ", __func__, gt->info.id);
+   ret = status;
+   }
+   kthread_destroy_worker(threads[i].worker);
+   }
+
+   kfree(threads);
+   return ret;
+}
+
 int intel_slpc_live_selftests(struct drm_i915_private *i915)
 {
static const struct i915_subtest tests[] = {
@@ -433,6 +495,7 @@ int intel_slpc_live_selftests(struct drm_i915_private *i915)
SUBTEST(live_slpc_vary_min),
SUBTEST(live_slpc_max_granted),
SUBTEST(live_slpc_power),
+   SUBTEST(live_slpc_tile_interaction),
};
 
struct intel_gt *gt;
-- 
2.25.1

[Intel-gfx] [PATCH v2 0/1] Add selftest for slpc tile interaction

[Riana Tauro]

This test runs a workload on tiles simultaneously by requesting for RP0 
frequency
and fails if there is a throttling error.

Rev2 : Fix build error

Riana Tauro (1):
  drm/i915/guc/slpc: Add selftest for slpc tile-tile interaction

 drivers/gpu/drm/i915/gt/selftest_slpc.c | 63 +
 1 file changed, 63 insertions(+)

-- 
2.25.1

[Intel-gfx] [PATCH v5 9/9] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints

[Ankit Nautiyal]

Add a wrapper function to check dp_downstream clock/bandwidth
constraints. Based on whether the sink supports FRL/TMDS the wrapper
calls the appropriate FRL/TMDS functions.

Signed-off-by: Ankit Nautiyal 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 51 +++--
 1 file changed, 23 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 03b42aecc4fb..8c267422cd8b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -933,6 +933,18 @@ intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int 
target_clock,
return MODE_OK;
 }
 
+static enum drm_mode_status
+intel_dp_hdmi_bw_check(struct intel_dp *intel_dp,
+  int target_clock, int bpc,
+  enum intel_output_format sink_format,
+  bool is_frl)
+{
+   if (is_frl)
+   return intel_dp_frl_bw_valid(intel_dp, target_clock, 8, 
sink_format);
+
+   return intel_dp_tmds_clock_valid(intel_dp, target_clock, 8, 
sink_format, true);
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid_downstream(struct intel_connector *connector,
   const struct drm_display_mode *mode,
@@ -942,48 +954,31 @@ intel_dp_mode_valid_downstream(struct intel_connector 
*connector,
const struct drm_display_info *info = >base.display_info;
enum drm_mode_status status;
bool ycbcr_420_only = drm_mode_is_420_only(info, mode);
+   bool is_frl;
enum intel_output_format sink_format;
+   int bpc = 8; /* Assume 8bpc for the DP++/HDMI/DVI TMDS/FRL bw heck */
 
-   ycbcr_420_only = drm_mode_is_420_only(info, mode);
+   if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
+   sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+   else
+   sink_format = INTEL_OUTPUT_FORMAT_RGB;
 
/* If PCON supports FRL MODE, check FRL bandwidth constraints */
-   if (intel_dp->dfp.pcon_max_frl_bw) {
+   is_frl = intel_dp->dfp.pcon_max_frl_bw ? true : false;
 
-   if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
-   sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
-   else
-   sink_format = INTEL_OUTPUT_FORMAT_RGB;
-
-   /* Assume 8bpc for the HDMI2.1 FRL BW check */
-   status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, 
sink_format);
-   if (status != MODE_OK) {
-   if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
-   !drm_mode_is_420_also(info, mode))
-   return status;
-   sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
-   status = intel_dp_frl_bw_valid(intel_dp, target_clock, 
8, sink_format);
-   if (status != MODE_OK)
-   return status;
-   }
-
-   return MODE_OK;
-   }
-
-   if (intel_dp->dfp.max_dotclock &&
+   if (!is_frl && intel_dp->dfp.max_dotclock &&
target_clock > intel_dp->dfp.max_dotclock)
return MODE_CLOCK_HIGH;
 
-   /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
-   status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
-  8, sink_format, true);
+   status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc, 
sink_format, is_frl);
 
if (status != MODE_OK) {
if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
!drm_mode_is_420_also(info, mode))
return status;
sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
-   status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
-  8, sink_format, true);
+   status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc, 
sink_format, is_frl);
+   } else {
if (status != MODE_OK)
return status;
}
-- 
2.25.1

[Intel-gfx] [PATCH v5 5/9] drm/i915/display: Add helper function to check if sink_format is 420

[Ankit Nautiyal]

Add an inline helper function to check if the sink_format is set to
YCBCR420 format.

Signed-off-by: Ankit Nautiyal 
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++
 drivers/gpu/drm/i915/display/intel_dp.c| 4 ++--
 drivers/gpu/drm/i915/display/intel_hdmi.c  | 6 +++---
 3 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index ae070420309d..33da22a9174c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2093,4 +2093,10 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
 }
 
+static inline bool
+intel_crtc_has_420_sink_format(const struct intel_crtc_state *crtc_state)
+{
+   return crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420;
+}
+
 #endif /*  __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index f40584130232..b9ef59882a90 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2008,7 +2008,7 @@ intel_dp_compute_output_format(struct intel_encoder 
*encoder,
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
   respect_downstream_limits);
if (ret) {
-   if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+   if (intel_crtc_has_420_sink_format(crtc_state) ||
!drm_mode_is_420_also(info, adjusted_mode))
return ret;
 
@@ -2688,7 +2688,7 @@ void intel_dp_configure_protocol_converter(struct 
intel_dp *intel_dp,
drm_dbg_kms(>drm, "Failed to %s protocol converter HDMI 
mode\n",
str_enable_disable(intel_dp->has_hdmi_sink));
 
-   if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+   if (intel_crtc_has_420_sink_format(crtc_state)) {
switch (crtc_state->output_format) {
case INTEL_OUTPUT_FORMAT_YCBCR420:
/*
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index cb7dd8ebb33f..c0e602ccb021 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2068,7 +2068,7 @@ static bool hdmi_bpc_possible(const struct 
intel_crtc_state *crtc_state, int bpc
return false;
 
/* Display Wa_1405510057:icl,ehl */
-   if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
+   if (intel_crtc_has_420_sink_format(crtc_state) &&
bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
(adjusted_mode->crtc_hblank_end -
 adjusted_mode->crtc_hblank_start) % 8 == 2)
@@ -2228,7 +2228,7 @@ static int intel_hdmi_compute_output_format(struct 
intel_encoder *encoder,
 
crtc_state->sink_format);
ret = intel_hdmi_compute_clock(encoder, crtc_state, 
respect_downstream_limits);
if (ret) {
-   if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+   if (intel_crtc_has_420_sink_format(crtc_state) ||
!drm_mode_is_420_also(info, adjusted_mode))
return ret;
 
@@ -2285,7 +2285,7 @@ int intel_hdmi_compute_config(struct intel_encoder 
*encoder,
return ret;
}
 
-   if (pipe_config->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+   if (intel_crtc_has_420_sink_format(pipe_config)) {
ret = intel_panel_fitting(pipe_config, conn_state);
if (ret)
return ret;
-- 
2.25.1

[Intel-gfx] [PATCH v5 7/9] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC

[Ankit Nautiyal]

Currently we use the highest input BPC supported by DP sink while using
DSC.In cases where PCON with HDMI2.1 as branch device, if PCON supports
DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same
input BPC that is used between Source and the PCON without DSC, which
might not work even with the maximum FRL rate supported by HDMI2.1
sink.

This patch calculates the max BPC that can be sufficient with either
RGB or YCBCR420 format for the maximum FRL rate supported.

v2: Rebase

v3: Use the sink_format in the functions instead of ycbcr420 flag.

Signed-off-by: Ankit Nautiyal 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 61 +++--
 1 file changed, 58 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4ffb470bcadc..ce59e99dcf84 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -117,6 +117,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
 
 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp);
 
 /* Is link rate UHBR and thus 128b/132b? */
 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -1473,12 +1474,47 @@ static int intel_dp_dsc_compute_params(struct 
intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
 }
 
+static int
+intel_dp_pcon_hdmi21_get_bpp_nodsc(struct intel_dp *intel_dp,
+  struct intel_crtc_state *pipe_config,
+  int max_bpc)
+{
+   struct intel_connector *intel_connector = intel_dp->attached_connector;
+   struct drm_connector *connector = _connector->base;
+   const struct drm_display_mode *adjusted_mode = 
_config->hw.adjusted_mode;
+   int i, num_bpc;
+   u8 dsc_bpc[3] = {0};
+   int req_rate_gbps;
+   int max_frl_rate = connector->display_info.hdmi.max_lanes *
+  connector->display_info.hdmi.max_frl_rate_per_lane;
+
+   num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
+  dsc_bpc);
+   for (i = 0; i < num_bpc; i++) {
+   if (dsc_bpc[i] > max_bpc)
+   continue;
+
+   req_rate_gbps = DIV_ROUND_UP(dsc_bpc[i] * 3 * 
adjusted_mode->clock, 100);
+
+   /* YCBCR420 reduces data rate by 2 */
+   if (intel_crtc_has_420_sink_format(pipe_config))
+   req_rate_gbps /= 2;
+
+   if (req_rate_gbps < max_frl_rate)
+   return dsc_bpc[i] * 3;
+   }
+
+   return 0;
+}
+
 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
   struct intel_crtc_state *pipe_config,
   struct drm_connector_state *conn_state,
   struct link_config_limits *limits)
 {
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+   struct intel_connector *intel_connector = intel_dp->attached_connector;
+   struct drm_connector *connector = _connector->base;
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
_config->hw.adjusted_mode;
@@ -1495,11 +1531,30 @@ static int intel_dp_dsc_compute_config(struct intel_dp 
*intel_dp,
if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
return -EINVAL;
 
-   pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, 
conn_state->max_requested_bpc);
-
-   if (intel_dp->force_dsc_bpc) {
+   /*
+* In cases where PCON with HDMI2.1 as branch device, if PCON supports
+* DSC but HDMI2.1 sink does not supports DSC, there can be issues due
+* to the bpc used.
+* With DSC, a source-PCON pair can support the mode with higher bpcs.
+* But PCON->Sink pair, cannot support the same bpc without sink having
+* DSC support.
+* So use the max BPC as input BPC that will be sufficient to show the
+* mode without DSC from PCON->HDMI2.1
+*/
+   if (intel_dp_is_hdmi_2_1_sink(intel_dp) &&
+   !connector->display_info.hdmi.dsc_cap.v_1p2) {
+   pipe_bpp = intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp, 
pipe_config,
+ 
conn_state->max_requested_bpc);
+   if (!pipe_bpp) {
+   drm_dbg_kms(_priv->drm,
+   "No BPC possible to support the mode 
without HDMI2.1 DSC\n");
+   return -EINVAL;
+   }
+   } else if (intel_dp->force_dsc_bpc) {
pipe_bpp = intel_dp->force_dsc_bpc * 3;

[Intel-gfx] [PATCH v5 8/9] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP

[Ankit Nautiyal]

During FRL bandwidth  check for downstream HDMI2.1 sink,
the min BPC supported is incorrectly taken for DP, and the check does
not consider ybcr420 only modes.
This patch fixes the bandwidth calculation similar to the TMDS case, by
taking min 8Bpc and considering Ycbcr420 only modes.

v2: Rebase

Signed-off-by: Ankit Nautiyal 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 66 +
 1 file changed, 46 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index ce59e99dcf84..03b42aecc4fb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -118,6 +118,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp);
+static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp);
 
 /* Is link rate UHBR and thus 128b/132b? */
 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -906,6 +907,32 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
return MODE_OK;
 }
 
+static enum drm_mode_status
+intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock,
+ int bpc, enum intel_output_format sink_format)
+{
+   int target_bw;
+   int max_frl_bw;
+   int bpp = bpc * 3;
+
+   if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+   target_clock /= 2;
+
+   target_bw = bpp * target_clock;
+
+   /* check for MAX FRL BW for both PCON and HDMI2.1 sink */
+   max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw,
+intel_dp_hdmi_sink_max_frl(intel_dp));
+
+   /* converting bw from Gbps to Kbps*/
+   max_frl_bw = max_frl_bw * 100;
+
+   if (target_bw > max_frl_bw)
+   return MODE_CLOCK_HIGH;
+
+   return MODE_OK;
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid_downstream(struct intel_connector *connector,
   const struct drm_display_mode *mode,
@@ -914,24 +941,30 @@ intel_dp_mode_valid_downstream(struct intel_connector 
*connector,
struct intel_dp *intel_dp = intel_attached_dp(connector);
const struct drm_display_info *info = >base.display_info;
enum drm_mode_status status;
-   bool ycbcr_420_only;
+   bool ycbcr_420_only = drm_mode_is_420_only(info, mode);
enum intel_output_format sink_format;
 
+   ycbcr_420_only = drm_mode_is_420_only(info, mode);
+
/* If PCON supports FRL MODE, check FRL bandwidth constraints */
if (intel_dp->dfp.pcon_max_frl_bw) {
-   int target_bw;
-   int max_frl_bw;
-   int bpp = intel_dp_mode_min_output_bpp(connector, mode);
-
-   target_bw = bpp * target_clock;
-
-   max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
 
-   /* converting bw from Gbps to Kbps*/
-   max_frl_bw = max_frl_bw * 100;
-
-   if (target_bw > max_frl_bw)
-   return MODE_CLOCK_HIGH;
+   if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
+   sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+   else
+   sink_format = INTEL_OUTPUT_FORMAT_RGB;
+
+   /* Assume 8bpc for the HDMI2.1 FRL BW check */
+   status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, 
sink_format);
+   if (status != MODE_OK) {
+   if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+   !drm_mode_is_420_also(info, mode))
+   return status;
+   sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+   status = intel_dp_frl_bw_valid(intel_dp, target_clock, 
8, sink_format);
+   if (status != MODE_OK)
+   return status;
+   }
 
return MODE_OK;
}
@@ -940,13 +973,6 @@ intel_dp_mode_valid_downstream(struct intel_connector 
*connector,
target_clock > intel_dp->dfp.max_dotclock)
return MODE_CLOCK_HIGH;
 
-   ycbcr_420_only = drm_mode_is_420_only(info, mode);
-
-   if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
-   sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
-   else
-   sink_format = INTEL_OUTPUT_FORMAT_RGB;
-
/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
   8, sink_format, true);
-- 
2.25.1

[Intel-gfx] [PATCH v5 1/9] drm/i915/display: Add new member to configure PCON color conversion

[Ankit Nautiyal]

The decision to use DFP output format conversion capabilities should be
during compute_config phase.

This patch adds new member to crtc_state to represent the final
output_format to the sink. In case of a DFP this can be different than
the output_format, as per the format conversion done via the PCON.

This will help to store only the format conversion capabilities of the
DP device in intel_dp->dfp, and use crtc_state to compute and store the
configuration for color/format conversion for a given mode.

v2: modified the new member to crtc_state to represent the final
output_format that eaches the sink, after possible conversion by
PCON kind of devices. (Ville)

v3: Addressed comments from Ville:
-Added comments to clarify difference between sink_format and
output_format.
-Corrected the order of setting sink_format and output_format.
-Added readout for sink_format in get_pipe_config hooks.

Signed-off-by: Ankit Nautiyal 
---
 drivers/gpu/drm/i915/display/icl_dsi.c|  1 +
 drivers/gpu/drm/i915/display/intel_crt.c  |  1 +
 .../drm/i915/display/intel_crtc_state_dump.c  |  5 +--
 drivers/gpu/drm/i915/display/intel_display.c  |  5 +++
 .../drm/i915/display/intel_display_types.h| 11 +-
 drivers/gpu/drm/i915/display/intel_dp.c   | 34 +--
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  1 +
 drivers/gpu/drm/i915/display/intel_dvo.c  |  1 +
 drivers/gpu/drm/i915/display/intel_hdmi.c | 24 -
 drivers/gpu/drm/i915/display/intel_lvds.c |  1 +
 drivers/gpu/drm/i915/display/intel_tv.c   |  1 +
 drivers/gpu/drm/i915/display/vlv_dsi.c|  1 +
 12 files changed, 63 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
b/drivers/gpu/drm/i915/display/icl_dsi.c
index e05e7cd6c412..533563e94f58 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1666,6 +1666,7 @@ static int gen11_dsi_compute_config(struct intel_encoder 
*encoder,
_config->hw.adjusted_mode;
int ret;
 
+   pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 
ret = intel_panel_compute_config(intel_connector, adjusted_mode);
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c 
b/drivers/gpu/drm/i915/display/intel_crt.c
index 94d0a5e1dd03..1b46d10fc6f4 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -391,6 +391,7 @@ static int intel_crt_compute_config(struct intel_encoder 
*encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
 
+   pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c 
b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index e9212f69c360..ed427b9cbf09 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -163,10 +163,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state 
*pipe_config,
 
snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
drm_dbg_kms(>drm,
-   "active: %s, output_types: %s (0x%x), output format: %s\n",
+   "active: %s, output_types: %s (0x%x), output format: %s, 
sink format: %s\n",
str_yes_no(pipe_config->hw.active),
buf, pipe_config->output_types,
-   output_formats(pipe_config->output_format));
+   output_formats(pipe_config->output_format),
+   output_formats(pipe_config->sink_format));
 
drm_dbg_kms(>drm,
"cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 9697179309c4..6edb3f2af376 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3240,6 +3240,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
return false;
 
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
+   pipe_config->sink_format = pipe_config->output_format;
pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
pipe_config->shared_dpll = NULL;
 
@@ -3699,6 +3700,8 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
break;
}
 
+   pipe_config->sink_format = pipe_config->output_format;
+
pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, 
tmp);
 
pipe_config->framestart_delay = 
REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
@@ -4094,6 +4097,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
bdw_get_pipemisc_output_format(crtc);
}
 
+   

[Intel-gfx] [PATCH v5 4/9] drm/i915/display: Use sink_format instead of ycbcr420_output flag

[Ankit Nautiyal]

Start passing the sink_format, to all functions that take a bool
ycbcr420_output as parameter. This will make the functions generic,
and will serve as a slight step towards 4:2:2 support later.

Suggested-by: Ville Syrj_l_ 
Signed-off-by: Ankit Nautiyal 
---
 drivers/gpu/drm/i915/display/intel_dp.c   | 33 +++
 drivers/gpu/drm/i915/display/intel_hdmi.c | 50 ---
 drivers/gpu/drm/i915/display/intel_hdmi.h |  5 ++-
 3 files changed, 44 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 95d0c653db7f..f40584130232 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -882,7 +882,8 @@ static int intel_dp_max_tmds_clock(struct intel_dp 
*intel_dp)
 
 static enum drm_mode_status
 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
- int clock, int bpc, bool ycbcr420_output,
+ int clock, int bpc,
+ enum intel_output_format sink_format,
  bool respect_downstream_limits)
 {
int tmds_clock, min_tmds_clock, max_tmds_clock;
@@ -890,7 +891,7 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
if (!respect_downstream_limits)
return MODE_OK;
 
-   tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
+   tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
 
min_tmds_clock = intel_dp->dfp.min_tmds_clock;
max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
@@ -913,6 +914,7 @@ intel_dp_mode_valid_downstream(struct intel_connector 
*connector,
const struct drm_display_info *info = >base.display_info;
enum drm_mode_status status;
bool ycbcr_420_only;
+   enum intel_output_format sink_format;
 
/* If PCON supports FRL MODE, check FRL bandwidth constraints */
if (intel_dp->dfp.pcon_max_frl_bw) {
@@ -939,18 +941,22 @@ intel_dp_mode_valid_downstream(struct intel_connector 
*connector,
 
ycbcr_420_only = drm_mode_is_420_only(info, mode);
 
+   if (ycbcr_420_only && connector->base.ycbcr_420_allowed)
+   sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+   else
+   sink_format = INTEL_OUTPUT_FORMAT_RGB;
+
/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
-  8, ycbcr_420_only, true);
+  8, sink_format, true);
 
if (status != MODE_OK) {
-   if (ycbcr_420_only ||
-   !connector->base.ycbcr_420_allowed ||
+   if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
!drm_mode_is_420_also(info, mode))
return status;
-
+   sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
-  8, true, true);
+  8, sink_format, true);
if (status != MODE_OK)
return status;
}
@@ -1189,19 +1195,10 @@ static bool intel_dp_supports_dsc(struct intel_dp 
*intel_dp,
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
 }
 
-static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
-const struct intel_crtc_state *crtc_state)
-{
-   return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
-   (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
-intel_dp->dfp.ycbcr_444_to_420);
-}
-
 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
 const struct intel_crtc_state *crtc_state,
 int bpc, bool respect_downstream_limits)
 {
-   bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
int clock = crtc_state->hw.adjusted_mode.crtc_clock;
 
/*
@@ -1221,8 +1218,8 @@ static int intel_dp_hdmi_compute_bpc(struct intel_dp 
*intel_dp,
 
for (; bpc >= 8; bpc -= 2) {
if (intel_hdmi_bpc_possible(crtc_state, bpc,
-   intel_dp->has_hdmi_sink, 
ycbcr420_output) &&
-   intel_dp_tmds_clock_valid(intel_dp, clock, bpc, 
ycbcr420_output,
+   intel_dp->has_hdmi_sink) &&
+   intel_dp_tmds_clock_valid(intel_dp, clock, bpc, 
crtc_state->sink_format,
  respect_downstream_limits) == 
MODE_OK)
return bpc;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index bd802ce69174..cb7dd8ebb33f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ 

[Intel-gfx] [PATCH v5 3/9] drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state sink_format

[Ankit Nautiyal]

The decision to use DFP output format conversion capabilities should be
during compute_config phase.

This patch uses the members of intel_dp->dfp to only store the
format conversion capabilities of the DP device and uses the crtc_state
sink_format member, to program the protocol-converter for
colorspace/format conversion.

v2: Use sink_format to determine the color conversion config for the
pcon (Ville).

v3: Fix typo: missing 'break' in switch case (lkp kernel test robot).

v4: Add helper to check if DP supports YCBCR420.

Signed-off-by: Ankit Nautiyal 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 122 
 1 file changed, 84 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0e4f7b467970..95d0c653db7f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -790,6 +790,7 @@ intel_dp_output_format(struct intel_connector *connector,
   enum intel_output_format sink_format)
 {
struct intel_dp *intel_dp = intel_attached_dp(connector);
+   struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 
if (!connector->base.ycbcr_420_allowed ||
sink_format != INTEL_OUTPUT_FORMAT_YCBCR420)
@@ -799,6 +800,10 @@ intel_dp_output_format(struct intel_connector *connector,
intel_dp->dfp.ycbcr_444_to_420)
return INTEL_OUTPUT_FORMAT_RGB;
 
+   /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
+   if (DISPLAY_VER(i915) >= 11 && intel_dp->dfp.ycbcr420_passthrough)
+   return INTEL_OUTPUT_FORMAT_YCBCR420;
+
if (intel_dp->dfp.ycbcr_444_to_420)
return INTEL_OUTPUT_FORMAT_YCBCR444;
else
@@ -2668,6 +2673,8 @@ void intel_dp_configure_protocol_converter(struct 
intel_dp *intel_dp,
   const struct intel_crtc_state 
*crtc_state)
 {
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+   bool ycbcr444_to_420 = false;
+   bool rgb_to_ycbcr = false;
u8 tmp;
 
if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
@@ -2684,8 +2691,35 @@ void intel_dp_configure_protocol_converter(struct 
intel_dp *intel_dp,
drm_dbg_kms(>drm, "Failed to %s protocol converter HDMI 
mode\n",
str_enable_disable(intel_dp->has_hdmi_sink));
 
-   tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
-   intel_dp->dfp.ycbcr_444_to_420 ? 
DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
+   if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+   switch (crtc_state->output_format) {
+   case INTEL_OUTPUT_FORMAT_YCBCR420:
+   /*
+* sink_format is YCBCR420, output_format is also 
YCBCR420:
+* Passthrough.
+*/
+   break;
+   case INTEL_OUTPUT_FORMAT_YCBCR444:
+   /*
+* sink_format is YCBCR420, output_format is YCBCR444:
+* Downsample.
+*/
+   ycbcr444_to_420 = true;
+   break;
+   case INTEL_OUTPUT_FORMAT_RGB:
+   /*
+* sink_format is YCBCR420, output_format is RGB:
+* Convert to YCBCR444 and Downsample.
+*/
+   rgb_to_ycbcr = true;
+   ycbcr444_to_420 = true;
+   break;
+   default:
+   break;
+   }
+   }
+
+   tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
 
if (drm_dp_dpcd_writeb(_dp->aux,
   DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
@@ -2693,13 +2727,12 @@ void intel_dp_configure_protocol_converter(struct 
intel_dp *intel_dp,
"Failed to %s protocol converter YCbCr 4:2:0 
conversion mode\n",
str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
 
-   tmp = intel_dp->dfp.rgb_to_ycbcr ?
-   DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
+   tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
 
if (drm_dp_pcon_convert_rgb_to_ycbcr(_dp->aux, tmp) < 0)
drm_dbg_kms(>drm,
-  "Failed to %s protocol converter RGB->YCbCr 
conversion mode\n",
-  str_enable_disable(tmp));
+   "Failed to %s protocol converter RGB->YCbCr 
conversion mode\n",
+   str_enable_disable(tmp));
 }
 
 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
@@ -4544,57 +4577,70 @@ intel_dp_update_dfp(struct intel_dp *intel_dp,
intel_dp_get_pcon_dsc_cap(intel_dp);
 }
 
-static void
-intel_dp_update_420(struct intel_dp *intel_dp)
+static 

[Intel-gfx] [PATCH v5 6/9] drm/i915/dp: Avoid DSC with output_format YCBC420

[Ankit Nautiyal]

Currently, DSC with YCBCR420 is not supported.
Return -EINVAL when trying with DSC with output_format as YCBCR420.

Signed-off-by: Ankit Nautiyal 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index b9ef59882a90..4ffb470bcadc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1491,6 +1491,10 @@ static int intel_dp_dsc_compute_config(struct intel_dp 
*intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
 
+   /* Currently DSC with YCBCR420 format is not supported */
+   if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+   return -EINVAL;
+
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, 
conn_state->max_requested_bpc);
 
if (intel_dp->force_dsc_bpc) {
-- 
2.25.1

[Intel-gfx] [PATCH v5 2/9] drm/i915/display: Add new member in intel_dp to store ycbcr420 passthrough cap

[Ankit Nautiyal]

New member to store the YCBCR20 Pass through capability of the DP sink.

Signed-off-by: Ankit Nautiyal 
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 924b7b656097..ae070420309d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1714,6 +1714,7 @@ struct intel_dp {
int pcon_max_frl_bw;
u8 max_bpc;
bool ycbcr_444_to_420;
+   bool ycbcr420_passthrough;
bool rgb_to_ycbcr;
} dfp;
 
-- 
2.25.1

[Intel-gfx] [PATCH v5 0/9] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes

[Ankit Nautiyal]

This series fixes issues faced when an HDMI2.1 sink that does not
support DSC is connected via HDMI2.1PCON. It also includes other minor
HDMI2.1 PCON fixes/refactoring.

Patch 1-2 Have minor fixes/cleanups.
Patch 3-6 Pull the decision making to use DFP conversion capabilities
for every mode during compute config, instead of having that decision
during DP initializing phase.
Patch 7-8 Calculate the max BPC that can be sufficient with either
RGB or YCbcr420 format for the maximum FRL rate supported.

Rev2: Split the refactoring of DFP RG->YCBCR conversion into smaller
patches, as suggested by Jani N.
Also dropped the unnecessary helper for DSC1.2 support for HDMI2.1 DFP.

Rev3: As suggested by Ville, added new member sink_format to store the
final format that the sink will be using, which might be different
than the output format, and thus might need color/format conversion
performed by the PCON.

Rev4: Fix typo in switch case as, reported by kernel test bot.

Rev5: Corrected order of setting sink_format and output_format. (Ville)
Avoided the flag ycbcr420_output and used the sink_format to facilitate
4:2:2 support at a later stage. (Ville)

Ankit Nautiyal (9):
  drm/i915/display: Add new member to configure PCON color conversion
  drm/i915/display: Add new member in intel_dp to store ycbcr420
passthrough cap
  drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state
sink_format
  drm/i915/display: Use sink_format instead of ycbcr420_output flag
  drm/i915/display: Add helper function to check if sink_format is 420
  drm/i915/dp: Avoid DSC with output_format YCBC420
  drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC
  drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP
  drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints

 drivers/gpu/drm/i915/display/icl_dsi.c|   1 +
 drivers/gpu/drm/i915/display/intel_crt.c  |   1 +
 .../drm/i915/display/intel_crtc_state_dump.c  |   5 +-
 drivers/gpu/drm/i915/display/intel_display.c  |   5 +
 .../drm/i915/display/intel_display_types.h|  18 +-
 drivers/gpu/drm/i915/display/intel_dp.c   | 321 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   1 +
 drivers/gpu/drm/i915/display/intel_dvo.c  |   1 +
 drivers/gpu/drm/i915/display/intel_hdmi.c |  74 ++--
 drivers/gpu/drm/i915/display/intel_hdmi.h |   5 +-
 drivers/gpu/drm/i915/display/intel_lvds.c |   1 +
 drivers/gpu/drm/i915/display/intel_tv.c   |   1 +
 drivers/gpu/drm/i915/display/vlv_dsi.c|   1 +
 13 files changed, 304 insertions(+), 131 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH v2] drm/i915/guc: add CAT error handler

[Andrzej Hajda]

Bad GPU memory accesses can result in catastrophic error notifications
being send from the GPU to the KMD via the GuC. Add a handler to process
the notification by printing a kernel message and dumping the related
engine state (if appropriate).
Since the same CAT error can be reported twice, log only 1st one and
assume error for the same context reported in less than 100ms after the
1st one is duplicated.

Signed-off-by: Andrzej Hajda 
---
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  2 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |  3 ++
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 47 +++
 4 files changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index f359bef046e0b2..f9a1c5642855e3 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -138,6 +138,7 @@ enum intel_guc_action {
INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
INTEL_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
INTEL_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
+   INTEL_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
INTEL_GUC_ACTION_STATE_CAPTURE_NOTIFICATION = 0x8002,
INTEL_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003,
INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 804133df1ac9b4..61b412732d095a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -445,6 +445,8 @@ int intel_guc_engine_failure_process_msg(struct intel_guc 
*guc,
 const u32 *msg, u32 len);
 int intel_guc_error_capture_process_msg(struct intel_guc *guc,
const u32 *msg, u32 len);
+int intel_guc_cat_error_process_msg(struct intel_guc *guc,
+   const u32 *msg, u32 len);
 
 struct intel_engine_cs *
 intel_guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 2b22065e87bf9a..f55f724e264407 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -1035,6 +1035,9 @@ static int ct_process_request(struct intel_guc_ct *ct, 
struct ct_incoming_msg *r
CT_ERROR(ct, "Received GuC exception notification!\n");
ret = 0;
break;
+   case INTEL_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR:
+   ret = intel_guc_cat_error_process_msg(guc, payload, len);
+   break;
default:
ret = -EOPNOTSUPP;
break;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 693b07a977893d..f68ae4a0ad864d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4659,6 +4659,53 @@ int intel_guc_engine_failure_process_msg(struct 
intel_guc *guc,
return 0;
 }
 
+int intel_guc_cat_error_process_msg(struct intel_guc *guc,
+   const u32 *msg, u32 len)
+{
+   static struct {
+   u32 ctx_id;
+   unsigned long after;
+   } ratelimit;
+   struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
+   struct drm_printer p = drm_info_printer(i915->drm.dev);
+   struct intel_context *ce;
+   unsigned long flags;
+   u32 ctx_id;
+
+   if (unlikely(len != 1)) {
+   drm_dbg(>drm, "Invalid length %u\n", len);
+   return -EPROTO;
+   }
+   ctx_id = msg[0];
+
+   if (ctx_id == ratelimit.ctx_id && 
time_is_after_jiffies(ratelimit.after))
+   return 0;
+
+   ratelimit.ctx_id = ctx_id;
+   ratelimit.after = jiffies + msecs_to_jiffies(100);
+
+   if (unlikely(ctx_id == -1)) {
+   drm_err(>drm,
+   "GPU reported catastrophic error without providing 
valid context\n");
+   return 0;
+   }
+
+   xa_lock_irqsave(>context_lookup, flags);
+   ce = g2h_context_lookup(guc, ctx_id);
+   if (ce)
+   intel_context_get(ce);
+   xa_unlock_irqrestore(>context_lookup, flags);
+   if (unlikely(!ce))
+   return -EPROTO;
+
+   drm_err(>drm, "GPU reported catastrophic error associated with 
context %u on %s\n",
+   ctx_id, ce->engine->name);
+   intel_engine_dump(ce->engine, , "%s\n", ce->engine->name);
+   intel_context_put(ce);
+
+   return 0;
+}
+
 void intel_guc_find_hung_context(struct intel_engine_cs *engine)
 {
struct intel_guc *guc = >gt->uc.guc;
-- 
2.34.1

Re: [Intel-gfx] [PATCH v5 18/19] drm/i915/vm_bind: Add uapi for user to enable vm_bind_mode

[Andi Shyti]

Hi Niranjana,

[...]

> +/*
> + * VM_BIND feature version supported.
> + *
> + * The following versions of VM_BIND have been defined:
> + *
> + * 0: No VM_BIND support.
> + *
> + * 1: In VM_UNBIND calls, the UMD must specify the exact mappings created
> + *previously with VM_BIND, the ioctl will not support unbinding multiple
> + *mappings or splitting them. Similarly, VM_BIND calls will not replace
> + *any existing mappings.
> + *
> + * See struct drm_i915_gem_vm_bind and struct drm_i915_gem_vm_unbind.
> + */
> +#define I915_PARAM_VM_BIND_VERSION   57

58... 57 has been taken right after you sent this patch

Andi

[...]

Re: [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk

[Ville Syrjälä]

On Wed, Oct 26, 2022 at 04:22:56PM -0700, Anusha Srivatsa wrote:
> From: Ville Syrjälä 
> 
> For MTL, changing cdclk from between certain frequencies has
> both squash and crawl. Use the current cdclk config and
> the new(desired) cdclk config to construtc a mid cdclk config.
> Set the cdclk twice:
> - Current cdclk -> mid cdclk
> - mid cdclk -> desired cdclk
> 
> v2: Add check in intel_modeset_calc_cdclk() to avoid cdclk
> change via modeset for platforms that support squash_crawl sequences(Ville)
> 
> v3: Add checks for:
> - scenario where only slow clock is used and
> cdclk is actually 0 (bringing up display).
> - PLLs are on before looking up the waveform.
> - Squash and crawl capability checks.(Ville)
> 
> v4: Rebase
> - Move checks to be more consistent (Ville)
> - Add comments (Bala)
> 
> Cc: Balasubramani Vivekanandan 
> Signed-off-by: Anusha Srivatsa 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 157 +
>  1 file changed, 129 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index eada931cb1c8..6a775367f02a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1716,37 +1716,74 @@ static void dg2_cdclk_squash_program(struct 
> drm_i915_private *i915,
>   intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
>  }
>  
> -static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> -   const struct intel_cdclk_config *cdclk_config,
> -   enum pipe pipe)
> +static int cdclk_squash_divider(u16 waveform)
> +{
> + return hweight16(waveform ?: 0x);
> +}
> +
> +static bool cdclk_crawl_and_squash(struct drm_i915_private *i915,
> +const struct intel_cdclk_config 
> *old_cdclk_config,
> +const struct intel_cdclk_config 
> *new_cdclk_config,
> +struct intel_cdclk_config *mid_cdclk_config)
> +{
> + u16 old_waveform, new_waveform, mid_waveform;
> + int size = 16;
> + int div = 2;
> +
> + /* Return if both Squash and Crawl are not present */
> + if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
> + return false;
> +
> + /* Return if Squash only or Crawl only is the desired action */
> + if (old_cdclk_config->vco <= 0 || new_cdclk_config->vco <= 0 ||
> + old_cdclk_config->vco == new_cdclk_config->vco ||
> + old_waveform == new_waveform)

Those are not yet initialized.

> + return false;
> +
> + old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
> + new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
> +
> + *mid_cdclk_config = *new_cdclk_config;
> +
> + /* Populate the mid_cdclk_config accordingly.
> +  * - If moving to a higher cdclk, the desired action is squashing.
> +  * The mid cdclk config should have the new (squash) waveform.
> +  * - If moving to a lower cdclk, the desired action is crawling.
> +  * The mid cdclk config should have the new vco.
> +  */
> +
> + if (cdclk_squash_divider(new_waveform) > 
> cdclk_squash_divider(old_waveform)) {
> + mid_cdclk_config->vco = old_cdclk_config->vco;
> + mid_waveform = new_waveform;
> + } else {
> + mid_cdclk_config->vco = new_cdclk_config->vco;
> + mid_waveform = old_waveform;
> + }
> +
> + mid_cdclk_config->cdclk = 
> DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
> + mid_cdclk_config->vco, size 
> * div);
> +
> + /* make sure the mid clock came out sane */
> +
> + drm_WARN_ON(>drm, mid_cdclk_config->cdclk <
> + min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
> + drm_WARN_ON(>drm, mid_cdclk_config->cdclk >
> + i915->display.cdclk.max_cdclk_freq);
> + drm_WARN_ON(>drm, cdclk_squash_waveform(i915, 
> mid_cdclk_config->cdclk) !=
> + mid_waveform);
> +
> + return true;
> +}
> +
> +static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> +const struct intel_cdclk_config *cdclk_config,
> +enum pipe pipe)
>  {
>   int cdclk = cdclk_config->cdclk;
>   int vco = cdclk_config->vco;
>   u32 val;
>   u16 waveform;
>   int clock;
> - int ret;
> -
> - /* Inform power controller of upcoming frequency change. */
> - if (DISPLAY_VER(dev_priv) >= 11)
> - ret = skl_pcode_request(_priv->uncore, 
> SKL_PCODE_CDCLK_CONTROL,
> - SKL_CDCLK_PREPARE_FOR_CHANGE,
> - SKL_CDCLK_READY_FOR_CHANGE,
> - SKL_CDCLK_READY_FOR_CHANGE, 3);
> - else
> - /*
> -  * BSpec requires us to