date:20221212

[Intel-gfx] ✗ Fi.CI.BAT: failure for Enable HDCP2.x via GSC CS (rev2)

2022-12-12 Thread Patchwork

== Series Details ==

Series: Enable HDCP2.x via GSC CS (rev2)
URL   : https://patchwork.freedesktop.org/series/111876/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12498 -> Patchwork_111876v2


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_111876v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111876v2, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v2/index.html

Participating hosts (39 -> 19)
--

  ERROR: It appears as if the changes made in Patchwork_111876v2 prevented too 
many machines from booting.

  Missing(20): fi-kbl-soraka bat-dg1-6 bat-dg1-5 bat-adlp-6 fi-skl-6600u 
fi-bsw-n3050 bat-dg2-8 bat-adlm-1 bat-dg2-9 fi-bwr-2160 bat-adln-1 bat-atsm-1 
bat-jsl-3 bat-rplp-1 bat-dg2-11 fi-bsw-nick bat-dg1-7 bat-kbl-2 bat-adlp-9 
bat-adlp-4 

Known issues


  Here are the changes found in Patchwork_111876v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600:   NOTRUN -> [INCOMPLETE][1] ([i915#6179])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v2/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#111827])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v2/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  
 Possible fixes 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[FAIL][3] ([i915#7229]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12498/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v2/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][5] ([i915#4785]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12498/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v2/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  
 Warnings 

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [INCOMPLETE][7] ([i915#4817]) -> [FAIL][8] 
([fdo#103375])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12498/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v2/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
  [i915#6179]: https://gitlab.freedesktop.org/drm/intel/issues/6179
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229


Build changes
-

  * Linux: CI_DRM_12498 -> Patchwork_111876v2

  CI-20190529: 20190529
  CI_DRM_12498: 76c062e92f2d28ab3d6a1b122cae8931e55b4fd9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7091: b8015f920c9f469d3733854263cb878373c1df51 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111876v2: 76c062e92f2d28ab3d6a1b122cae8931e55b4fd9 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

5af5aee5e720 drm/i915/mtl: Add HDCP GSC interface
9984069eb8cd drm/i915/mtl: Adding function to send command to GSC CS
ab28a96f815b drm/i915/hdcp: Fill wired_cmd_in structures at a single place
06dbf3976bd8 drm/i915/hdcp: Refactor HDCP API structures
93132565111b drm/i915/hdcp: HDCP2.x Refactoring to agnotic cp f/w
938e085f drm/i915/hdcp: Keep cp fw agonstic naming convention
6a20065a698a drm/i915/gsc: Create GSC request submission mechanism

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v2/index.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable HDCP2.x via GSC CS (rev2)

2022-12-12 Thread Patchwork

== Series Details ==

Series: Enable HDCP2.x via GSC CS (rev2)
URL   : https://patchwork.freedesktop.org/series/111876/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable HDCP2.x via GSC CS (rev2)

2022-12-12 Thread Patchwork

== Series Details ==

Series: Enable HDCP2.x via GSC CS (rev2)
URL   : https://patchwork.freedesktop.org/series/111876/
State : warning

== Summary ==

Error: dim checkpatch failed
d39a03598736 drm/i915/gsc: Create GSC request submission mechanism
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
-:140: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#140: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 147 lines checked
6482b09862f4 drm/i915/hdcp: Keep cp fw agonstic naming convention
-:45: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#45: 
rename from include/drm/i915_mei_hdcp_interface.h

total: 0 errors, 1 warnings, 0 checks, 31 lines checked
7256f15a75cb drm/i915/hdcp: HDCP2.x Refactoring to agnotic cp f/w
43b094c874c5 drm/i915/hdcp: Refactor HDCP API structures
217fef3c6b6a drm/i915/hdcp: Fill wired_cmd_in structures at a single place
fefe94c18264 drm/i915/mtl: Adding function to send command to GSC CS
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
-:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#35: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 249 lines checked
47a6013f0896 drm/i915/mtl: Add HDCP GSC interface
-:592: CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*data)...) over 
kzalloc(sizeof(struct i915_hdcp_fw_master)...)
#592: FILE: drivers/gpu/drm/i915/display/intel_hdcp_gsc.c:499:
+   data = kzalloc(sizeof(struct i915_hdcp_fw_master), GFP_KERNEL);

total: 0 errors, 0 warnings, 1 checks, 586 lines checked

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/hwconfig: Remove comment block

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915/hwconfig: Remove comment block
URL   : https://patchwork.freedesktop.org/series/111879/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12498 -> Patchwork_111879v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_111879v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111879v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111879v1/index.html

Participating hosts (39 -> 19)
--

  ERROR: It appears as if the changes made in Patchwork_111879v1 prevented too 
many machines from booting.

  Missing(20): fi-kbl-soraka bat-dg1-6 bat-dg1-5 bat-adlp-6 fi-skl-6600u 
fi-bsw-n3050 bat-dg2-8 bat-adlm-1 bat-dg2-9 fi-bwr-2160 bat-adln-1 bat-atsm-1 
bat-jsl-3 bat-rplp-1 bat-dg2-11 fi-bsw-nick bat-dg1-7 bat-kbl-2 bat-adlp-9 
bat-adlp-4 

Known issues


  Here are the changes found in Patchwork_111879v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#111827])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111879v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [PASS][2] -> [FAIL][3] ([i915#6298])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12498/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111879v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html

  
 Possible fixes 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[FAIL][4] ([i915#7229]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12498/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111879v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][6] ([i915#4785]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12498/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111879v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229


Build changes
-

  * Linux: CI_DRM_12498 -> Patchwork_111879v1

  CI-20190529: 20190529
  CI_DRM_12498: 76c062e92f2d28ab3d6a1b122cae8931e55b4fd9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7091: b8015f920c9f469d3733854263cb878373c1df51 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111879v1: 76c062e92f2d28ab3d6a1b122cae8931e55b4fd9 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

e269df174043 drm/i915/hwconfig: Remove comment block

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111879v1/index.html

[Intel-gfx] [PATCH v2 7/7] drm/i915/mtl: Add HDCP GSC interface

2022-12-12 Thread Suraj Kandpal

MTL uses GSC command streamer i.e gsc cs to send HDCP/PXP commands
to GSC f/w. It requires to keep hdcp display driver
agnostic to content protection f/w (ME/GSC fw) in the form of
i915_hdcp_fw_ops generic ops.

Adding HDCP GSC CS interface by leveraging the i915_hdcp_fw_ops generic
ops instead of I915_HDCP_COMPONENT as integral part of i915.

Adding checks to see if GSC is loaded and proxy is setup

Cc: Tomas Winkler 
Cc: Rodrigo Vivi 
Cc: Uma Shankar 
Cc: Ankit Nautiyal 
Signed-off-by: Anshuman Gupta 
Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/i915/display/intel_hdcp.c |  28 +-
 drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 503 +-
 2 files changed, 524 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c 
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index e856b10948ab..efdaa938df48 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -25,6 +25,8 @@
 #include "intel_hdcp.h"
 #include "intel_hdcp_regs.h"
 #include "intel_pcode.h"
+#include "intel_connector.h"
+#include "display/intel_hdcp_gsc.h"
 
 #define KEY_LOAD_TRIES 5
 #define HDCP2_LC_RETRY_CNT 3
@@ -203,13 +205,20 @@ bool intel_hdcp2_capable(struct intel_connector 
*connector)
struct intel_digital_port *dig_port = 
intel_attached_dig_port(connector);
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
+   struct intel_gt *gt = dev_priv->media_gt;
+   struct intel_gsc_uc *gsc = >->uc.gsc;
bool capable = false;
 
/* I915 support for HDCP2.2 */
if (!hdcp->hdcp2_supported)
return false;
 
-   /* MEI interface is solid */
+   /* If MTL+ make sure gsc is loaded and proxy is setup */
+   if (DISPLAY_VER(dev_priv) >= 14)
+   if (!intel_uc_fw_is_running(&gsc->fw))
+   return false;
+
+   /* MEI/GSC interface is solid depending on which is used */
mutex_lock(&dev_priv->display.hdcp.comp_mutex);
if (!dev_priv->display.hdcp.comp_added ||  
!dev_priv->display.hdcp.master) {
mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
@@ -2235,7 +2244,7 @@ static int initialize_hdcp_port_data(struct 
intel_connector *connector,
 
 static bool is_hdcp2_supported(struct drm_i915_private *dev_priv)
 {
-   if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP))
+   if (DISPLAY_VER(dev_priv) < 14 && !IS_ENABLED(CONFIG_INTEL_MEI_HDCP))
return false;
 
return (DISPLAY_VER(dev_priv) >= 10 ||
@@ -2256,10 +2265,14 @@ void intel_hdcp_component_init(struct drm_i915_private 
*dev_priv)
 
dev_priv->display.hdcp.comp_added = true;
mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
-   ret = component_add_typed(dev_priv->drm.dev, &i915_hdcp_component_ops,
- I915_COMPONENT_HDCP);
+
+   if (DISPLAY_VER(dev_priv) >= 14)
+   ret = intel_gsc_hdcp_init(dev_priv);
+   else
+   ret = component_add_typed(dev_priv->drm.dev, 
&i915_hdcp_component_ops,
+ I915_COMPONENT_HDCP);
if (ret < 0) {
-   drm_dbg_kms(&dev_priv->drm, "Failed at component add(%d)\n",
+   drm_dbg_kms(&dev_priv->drm, "Failed at fw component add(%d)\n",
ret);
mutex_lock(&dev_priv->display.hdcp.comp_mutex);
dev_priv->display.hdcp.comp_added = false;
@@ -2485,7 +2498,10 @@ void intel_hdcp_component_fini(struct drm_i915_private 
*dev_priv)
dev_priv->display.hdcp.comp_added = false;
mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
 
-   component_del(dev_priv->drm.dev, &i915_hdcp_component_ops);
+   if (DISPLAY_VER(dev_priv) >= 14)
+   intel_gsc_hdcp_fini(dev_priv);
+   else
+   component_del(dev_priv->drm.dev, &i915_hdcp_component_ops);
 }
 
 void intel_hdcp_cleanup(struct intel_connector *connector)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c 
b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
index aea3a1158c75..380ebbabb9ff 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
@@ -3,6 +3,7 @@
  * Copyright 2021, Intel Corporation.
  */
 
+#include 
 #include "i915_drv.h"
 #include "gt/uc/intel_gsc_fw.h"
 #include "gt/uc/intel_gsc_fwif.h"
@@ -16,6 +17,505 @@ struct intel_hdcp_gsc_message {
void *hdcp_cmd;
 };
 
+static int
+gsc_hdcp_initiate_session(struct device *dev, struct hdcp_port_data *data,
+ struct hdcp2_ake_init *ake_data)
+{
+   struct wired_cmd_initiate_hdcp2_session_in session_init_in = { { 0 } };
+   struct wired_cmd_initiate_hdcp2_session_out
+   session_init_out = { { 0 } };
+   struct drm_i915_private *i915;
+   ssize_t byte;
+
+   if (!dev

[Intel-gfx] [PATCH v2 6/7] drm/i915/mtl: Adding function to send command to GSC CS

2022-12-12 Thread Suraj Kandpal

Adding function that takes care of sending command to gsc cs. We start
of with allocation of memory for our command intel_hdcp_gsc_message that
contains gsc cs memory header as directed in specs followed by the
actual payload hdcp message that we want to send.
Spec states that we need to poll pending bit of response header around
20 times each try being 50ms apart hence adding that to current
gsc_msg_send function
Also we use the same function to take care of both sending and receiving
hence no separate function to get the response.

Cc: Ankit Nautiyal 
Cc: Daniele Ceraolo Spurio 
Cc: Uma Shankar 
Cc: Anshuman Gupta 
Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 207 ++
 drivers/gpu/drm/i915/display/intel_hdcp_gsc.h |  28 +++
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h   |   1 +
 4 files changed, 237 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdcp_gsc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index dfa211451a1d..42b8c3430365 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -250,6 +250,7 @@ i915-y += \
display/intel_frontbuffer.o \
display/intel_global_state.o \
display/intel_hdcp.o \
+   display/intel_hdcp_gsc.o \
display/intel_hotplug.o \
display/intel_hti.o \
display/intel_lpe_audio.o \
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c 
b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
new file mode 100644
index ..aea3a1158c75
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2021, Intel Corporation.
+ */
+
+#include "i915_drv.h"
+#include "gt/uc/intel_gsc_fw.h"
+#include "gt/uc/intel_gsc_fwif.h"
+#include "gem/i915_gem_region.h"
+#include "i915_utils.h"
+#include "display/intel_hdcp_gsc.h"
+
+struct intel_hdcp_gsc_message {
+   struct drm_i915_gem_object *obj;
+   struct i915_vma *vma;
+   void *hdcp_cmd;
+};
+
+/*This function helps allocate memory for the command that we will send to gsc 
cs */
+static int intel_initialize_hdcp_gsc_message(struct drm_i915_private *i915,
+struct intel_hdcp_gsc_message 
*hdcp_message)
+{
+   struct intel_gt *gt = i915->media_gt;
+   struct drm_i915_gem_object *obj = NULL;
+   struct i915_vma *vma = NULL;
+   void *cmd;
+   int err;
+
+   hdcp_message->obj = NULL;
+   hdcp_message->hdcp_cmd = NULL;
+   hdcp_message->vma = NULL;
+
+   /* allocate object of one page for HDCP command memory and store it */
+   obj = i915_gem_object_create_shmem(gt->i915, PAGE_SIZE);
+
+   if (IS_ERR(obj)) {
+   drm_err(>->i915->drm, "Failed to allocate HDCP streaming 
command!\n");
+   return PTR_ERR(obj);
+   }
+
+   cmd = i915_gem_object_pin_map_unlocked(obj, 
i915_coherent_map_type(gt->i915, obj, true));
+   if (IS_ERR(cmd)) {
+   drm_err(>->i915->drm, "Failed to map gsc message page!\n");
+   err = PTR_ERR(cmd);
+   goto out_unpin;
+   }
+
+   vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
+   if (IS_ERR(vma)) {
+   err = PTR_ERR(vma);
+   goto out_unmap;
+   }
+
+   err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+   if (err)
+   goto out_unmap;
+
+   memset(cmd, 0, obj->base.size);
+
+   hdcp_message->obj = obj;
+   hdcp_message->hdcp_cmd = cmd;
+   hdcp_message->vma = vma;
+
+   return 0;
+
+out_unmap:
+   i915_gem_object_unpin_map(obj);
+out_unpin:
+   i915_gem_object_put(obj);
+   return err;
+}
+
+static void intel_free_hdcp_gsc_message(struct intel_hdcp_gsc_message 
*hdcp_message)
+{
+   struct drm_i915_gem_object *obj = fetch_and_zero(&hdcp_message->obj);
+
+   if (!obj)
+   return;
+
+   if (hdcp_message->vma)
+   i915_vma_unpin(fetch_and_zero(&hdcp_message->vma));
+
+   i915_gem_object_unpin_map(obj);
+   i915_gem_object_put(obj);
+   kfree(hdcp_message);
+}
+
+static int intel_gsc_send_sync(struct drm_i915_private *i915,
+  struct intel_gsc_mtl_header *header, u64 addr,
+  size_t msg_out_len)
+{
+   struct intel_gt *gt = i915->media_gt;
+   int ret;
+
+   header->flags = 0;
+   ret = intel_gsc_fw_heci_send(>->uc.gsc, addr, header->message_size,
+addr, msg_out_len + sizeof(*header));
+   if (ret) {
+   drm_err(&i915->drm, "failed to send gsc HDCP msg (%d)\n", ret);
+   return ret;
+   }
+   /*
+* Checking validity marker for memory sanity
+*/
+   if (header->validity_marker != GSC_HECI_VALIDITY_M

[Intel-gfx] [PATCH v2 2/7] drm/i915/hdcp: Keep cp fw agonstic naming convention

2022-12-12 Thread Suraj Kandpal

From: Anshuman Gupta 

Change the include/drm/i915_mei_hdcp_interface.h to
include/drm/i915_cp_fw_hdcp_interface.h

Cc: Tomas Winkler 
Cc: Rodrigo Vivi 
Cc: Uma Shankar 
Cc: Ankit Nautiyal 
Signed-off-by: Anshuman Gupta 
Signed-off-by: Suraj Kandpal 
Acked-by: Tomas Winkler 
---
 drivers/gpu/drm/i915/display/intel_display_types.h  | 2 +-
 drivers/misc/mei/hdcp/mei_hdcp.c| 2 +-
 ...915_mei_hdcp_interface.h => i915_cp_fw_hdcp_interface.h} | 6 +++---
 3 files changed, 5 insertions(+), 5 deletions(-)
 rename include/drm/{i915_mei_hdcp_interface.h => i915_cp_fw_hdcp_interface.h} 
(97%)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 32e8b2fc3cc6..52d93e89b4c6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 
 #include "i915_vma.h"
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index e889a8bd7ac8..7e3cd3fd7f7b 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -23,7 +23,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 #include "mei_hdcp.h"
 
diff --git a/include/drm/i915_mei_hdcp_interface.h 
b/include/drm/i915_cp_fw_hdcp_interface.h
similarity index 97%
rename from include/drm/i915_mei_hdcp_interface.h
rename to include/drm/i915_cp_fw_hdcp_interface.h
index f441cbcd95a4..e5dc6b985b2f 100644
--- a/include/drm/i915_mei_hdcp_interface.h
+++ b/include/drm/i915_cp_fw_hdcp_interface.h
@@ -6,8 +6,8 @@
  * Ramalingam C 
  */
 
-#ifndef _I915_MEI_HDCP_INTERFACE_H_
-#define _I915_MEI_HDCP_INTERFACE_H_
+#ifndef _I915_CP_FW_HDCP_INTERFACE_H_
+#define _I915_CP_FW_HDCP_INTERFACE_H_
 
 #include 
 #include 
@@ -181,4 +181,4 @@ struct i915_hdcp_comp_master {
struct mutex mutex;
 };
 
-#endif /* _I915_MEI_HDCP_INTERFACE_H_ */
+#endif /* _I915_CP_FW_HDCP_INTERFACE_H_ */
-- 
2.25.1

[Intel-gfx] [PATCH v2 4/7] drm/i915/hdcp: Refactor HDCP API structures

2022-12-12 Thread Suraj Kandpal

From: Anshuman Gupta 

It requires to move intel specific HDCP API structures to
i915_cp_fw_hdcp_interface.h from driver/misc/mei/hdcp/mei_hdcp.h
so that any content protection fw interfaces can use these
structures.

Cc: Tomas Winkler 
Cc: Rodrigo Vivi 
Cc: Uma Shankar 
Cc: Ankit Nautiyal 
Signed-off-by: Anshuman Gupta 
Signed-off-by: Suraj Kandpal 
---
 .../gpu/drm/i915/display/intel_display_core.h |   2 +-
 drivers/misc/mei/hdcp/mei_hdcp.c  |  44 +--
 drivers/misc/mei/hdcp/mei_hdcp.h  | 355 +-
 include/drm/i915_cp_fw_hdcp_interface.h   | 354 +
 4 files changed, 378 insertions(+), 377 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h 
b/drivers/gpu/drm/i915/display/intel_display_core.h
index a769cc8e2745..0f6d14e55fbb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -15,8 +15,8 @@
 
 #include 
 #include 
+#include 
 
-#include "i915/i915_cp_fw_hdcp_interface.h"
 #include "intel_cdclk.h"
 #include "intel_display.h"
 #include "intel_display_power.h"
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 7ca8b739cd31..51e3edac565d 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -52,7 +52,7 @@ mei_hdcp_initiate_session(struct device *dev, struct 
hdcp_port_data *data,
 
session_init_in.header.api_version = HDCP_API_VERSION;
session_init_in.header.command_id = WIRED_INITIATE_HDCP2_SESSION;
-   session_init_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   session_init_in.header.status = FW_HDCP_STATUS_SUCCESS;
session_init_in.header.buffer_len =
WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN;
 
@@ -75,7 +75,7 @@ mei_hdcp_initiate_session(struct device *dev, struct 
hdcp_port_data *data,
return byte;
}
 
-   if (session_init_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   if (session_init_out.header.status != FW_HDCP_STATUS_SUCCESS) {
dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
WIRED_INITIATE_HDCP2_SESSION,
session_init_out.header.status);
@@ -122,7 +122,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device *dev,
 
verify_rxcert_in.header.api_version = HDCP_API_VERSION;
verify_rxcert_in.header.command_id = WIRED_VERIFY_RECEIVER_CERT;
-   verify_rxcert_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   verify_rxcert_in.header.status = FW_HDCP_STATUS_SUCCESS;
verify_rxcert_in.header.buffer_len =
WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN;
 
@@ -148,7 +148,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device *dev,
return byte;
}
 
-   if (verify_rxcert_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   if (verify_rxcert_out.header.status != FW_HDCP_STATUS_SUCCESS) {
dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
WIRED_VERIFY_RECEIVER_CERT,
verify_rxcert_out.header.status);
@@ -194,7 +194,7 @@ mei_hdcp_verify_hprime(struct device *dev, struct 
hdcp_port_data *data,
 
send_hprime_in.header.api_version = HDCP_API_VERSION;
send_hprime_in.header.command_id = WIRED_AKE_SEND_HPRIME;
-   send_hprime_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   send_hprime_in.header.status = FW_HDCP_STATUS_SUCCESS;
send_hprime_in.header.buffer_len = WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN;
 
send_hprime_in.port.integrated_port_type = data->port_type;
@@ -218,7 +218,7 @@ mei_hdcp_verify_hprime(struct device *dev, struct 
hdcp_port_data *data,
return byte;
}
 
-   if (send_hprime_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   if (send_hprime_out.header.status != FW_HDCP_STATUS_SUCCESS) {
dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
WIRED_AKE_SEND_HPRIME, send_hprime_out.header.status);
return -EIO;
@@ -251,7 +251,7 @@ mei_hdcp_store_pairing_info(struct device *dev, struct 
hdcp_port_data *data,
 
pairing_info_in.header.api_version = HDCP_API_VERSION;
pairing_info_in.header.command_id = WIRED_AKE_SEND_PAIRING_INFO;
-   pairing_info_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   pairing_info_in.header.status = FW_HDCP_STATUS_SUCCESS;
pairing_info_in.header.buffer_len =
WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN;
 
@@ -276,7 +276,7 @@ mei_hdcp_store_pairing_info(struct device *dev, struct 
hdcp_port_data *data,
return byte;
}
 
-   if (pairing_info_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   if (pairing_info_out.header.status != FW_HDCP_STATUS_SUCCESS) {
dev_dbg(dev, "ME cmd 0x%08X failed. Status: 0x%X\n",

[Intel-gfx] [PATCH v2 5/7] drm/i915/hdcp: Fill wired_cmd_in structures at a single place

2022-12-12 Thread Suraj Kandpal

Need to fill wired cmd in structures at a single place as they remain same
for both gsc and mei

Cc: Ankit Nautiyal 
Signed-off-by: Suraj Kandpal 
---
 drivers/misc/mei/hdcp/mei_hdcp.c| 154 ++
 include/drm/i915_cp_fw_hdcp_interface.h | 198 
 2 files changed, 212 insertions(+), 140 deletions(-)

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 51e3edac565d..a4c255be74df 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -50,17 +50,7 @@ mei_hdcp_initiate_session(struct device *dev, struct 
hdcp_port_data *data,
 
cldev = to_mei_cl_device(dev);
 
-   session_init_in.header.api_version = HDCP_API_VERSION;
-   session_init_in.header.command_id = WIRED_INITIATE_HDCP2_SESSION;
-   session_init_in.header.status = FW_HDCP_STATUS_SUCCESS;
-   session_init_in.header.buffer_len =
-   WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN;
-
-   session_init_in.port.integrated_port_type = data->port_type;
-   session_init_in.port.physical_port = (u8)data->fw_ddi;
-   session_init_in.port.attached_transcoder = (u8)data->fw_tc;
-   session_init_in.protocol = data->protocol;
-
+   i915_cp_fw_fill_session_in(&session_init_in, data);
byte = mei_cldev_send(cldev, (u8 *)&session_init_in,
  sizeof(session_init_in));
if (byte < 0) {
@@ -119,21 +109,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device 
*dev,
return -EINVAL;
 
cldev = to_mei_cl_device(dev);
-
-   verify_rxcert_in.header.api_version = HDCP_API_VERSION;
-   verify_rxcert_in.header.command_id = WIRED_VERIFY_RECEIVER_CERT;
-   verify_rxcert_in.header.status = FW_HDCP_STATUS_SUCCESS;
-   verify_rxcert_in.header.buffer_len =
-   WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN;
-
-   verify_rxcert_in.port.integrated_port_type = data->port_type;
-   verify_rxcert_in.port.physical_port = (u8)data->fw_ddi;
-   verify_rxcert_in.port.attached_transcoder = (u8)data->fw_tc;
-
-   verify_rxcert_in.cert_rx = rx_cert->cert_rx;
-   memcpy(verify_rxcert_in.r_rx, &rx_cert->r_rx, HDCP_2_2_RRX_LEN);
-   memcpy(verify_rxcert_in.rx_caps, rx_cert->rx_caps, HDCP_2_2_RXCAPS_LEN);
-
+   i915_cp_fw_fill_rxcert_in(&verify_rxcert_in, rx_cert, data);
byte = mei_cldev_send(cldev, (u8 *)&verify_rxcert_in,
  sizeof(verify_rxcert_in));
if (byte < 0) {
@@ -192,18 +168,7 @@ mei_hdcp_verify_hprime(struct device *dev, struct 
hdcp_port_data *data,
 
cldev = to_mei_cl_device(dev);
 
-   send_hprime_in.header.api_version = HDCP_API_VERSION;
-   send_hprime_in.header.command_id = WIRED_AKE_SEND_HPRIME;
-   send_hprime_in.header.status = FW_HDCP_STATUS_SUCCESS;
-   send_hprime_in.header.buffer_len = WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN;
-
-   send_hprime_in.port.integrated_port_type = data->port_type;
-   send_hprime_in.port.physical_port = (u8)data->fw_ddi;
-   send_hprime_in.port.attached_transcoder = (u8)data->fw_tc;
-
-   memcpy(send_hprime_in.h_prime, rx_hprime->h_prime,
-  HDCP_2_2_H_PRIME_LEN);
-
+   i915_cp_fw_fill_hprime_in(&send_hprime_in, rx_hprime, data);
byte = mei_cldev_send(cldev, (u8 *)&send_hprime_in,
  sizeof(send_hprime_in));
if (byte < 0) {
@@ -248,20 +213,8 @@ mei_hdcp_store_pairing_info(struct device *dev, struct 
hdcp_port_data *data,
return -EINVAL;
 
cldev = to_mei_cl_device(dev);
-
-   pairing_info_in.header.api_version = HDCP_API_VERSION;
-   pairing_info_in.header.command_id = WIRED_AKE_SEND_PAIRING_INFO;
-   pairing_info_in.header.status = FW_HDCP_STATUS_SUCCESS;
-   pairing_info_in.header.buffer_len =
-   WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN;
-
-   pairing_info_in.port.integrated_port_type = data->port_type;
-   pairing_info_in.port.physical_port = (u8)data->fw_ddi;
-   pairing_info_in.port.attached_transcoder = (u8)data->fw_tc;
-
-   memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km,
-  HDCP_2_2_E_KH_KM_LEN);
-
+   i915_cp_fw_fill_pairing_info_in(&pairing_info_in, pairing_info,
+   data);
byte = mei_cldev_send(cldev, (u8 *)&pairing_info_in,
  sizeof(pairing_info_in));
if (byte < 0) {
@@ -308,16 +261,7 @@ mei_hdcp_initiate_locality_check(struct device *dev,
return -EINVAL;
 
cldev = to_mei_cl_device(dev);
-
-   lc_init_in.header.api_version = HDCP_API_VERSION;
-   lc_init_in.header.command_id = WIRED_INIT_LOCALITY_CHECK;
-   lc_init_in.header.status = FW_HDCP_STATUS_SUCCESS;
-   lc_init_in.header.buffer_len = WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_IN;
-
-   lc_init_in.port.integrated_

[Intel-gfx] [PATCH v2 3/7] drm/i915/hdcp: HDCP2.x Refactoring to agnotic cp f/w

2022-12-12 Thread Suraj Kandpal

From: Anshuman Gupta 

As now we have more then one type of content protection
secrity firmware. Let change the i915_cp_fw_hdcp_interface.h
header naming convention to suit generic f/w type.
%s/MEI_/FW_
%s/mei_fw/cp_fw
%s/mei_dev/fw_dev

As interface to CP FW can be either a non i915 component or
i915 intergral component, change structure name Accordingly.
%s/i915_hdcp_comp_master/i915_hdcp_fw_master
%s/i915_hdcp_component_ops/i915_hdcp_fw_ops

Cc: Tomas Winkler 
Cc: Rodrigo Vivi 
Cc: Uma Shankar 
Cc: Ankit Nautiyal 
Signed-off-by: Anshuman Gupta 
Signed-off-by: Suraj Kandpal 
---
 .../gpu/drm/i915/display/intel_display_core.h |  3 +-
 drivers/gpu/drm/i915/display/intel_hdcp.c | 66 -
 drivers/misc/mei/hdcp/mei_hdcp.c  | 12 ++--
 include/drm/i915_cp_fw_hdcp_interface.h   | 70 +--
 4 files changed, 76 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h 
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 57ddce3ba02b..a769cc8e2745 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -16,6 +16,7 @@
 #include 
 #include 
 
+#include "i915/i915_cp_fw_hdcp_interface.h"
 #include "intel_cdclk.h"
 #include "intel_display.h"
 #include "intel_display_power.h"
@@ -368,7 +369,7 @@ struct intel_display {
} gmbus;
 
struct {
-   struct i915_hdcp_comp_master *master;
+   struct i915_hdcp_fw_master *master;
bool comp_added;
 
/* Mutex to protect the above hdcp component related values. */
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c 
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 6406fd487ee5..e856b10948ab 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1143,7 +1143,7 @@ hdcp2_prepare_ake_init(struct intel_connector *connector,
struct intel_digital_port *dig_port = 
intel_attached_dig_port(connector);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
-   struct i915_hdcp_comp_master *comp;
+   struct i915_hdcp_fw_master *comp;
int ret;
 
mutex_lock(&dev_priv->display.hdcp.comp_mutex);
@@ -1154,7 +1154,7 @@ hdcp2_prepare_ake_init(struct intel_connector *connector,
return -EINVAL;
}
 
-   ret = comp->ops->initiate_hdcp2_session(comp->mei_dev, data, ake_data);
+   ret = comp->ops->initiate_hdcp2_session(comp->fw_dev, data, ake_data);
if (ret)
drm_dbg_kms(&dev_priv->drm, "Prepare_ake_init failed. %d\n",
ret);
@@ -1173,7 +1173,7 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector 
*connector,
struct intel_digital_port *dig_port = 
intel_attached_dig_port(connector);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
-   struct i915_hdcp_comp_master *comp;
+   struct i915_hdcp_fw_master *comp;
int ret;
 
mutex_lock(&dev_priv->display.hdcp.comp_mutex);
@@ -1184,7 +1184,7 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector 
*connector,
return -EINVAL;
}
 
-   ret = comp->ops->verify_receiver_cert_prepare_km(comp->mei_dev, data,
+   ret = comp->ops->verify_receiver_cert_prepare_km(comp->fw_dev, data,
 rx_cert, paired,
 ek_pub_km, msg_sz);
if (ret < 0)
@@ -1201,7 +1201,7 @@ static int hdcp2_verify_hprime(struct intel_connector 
*connector,
struct intel_digital_port *dig_port = 
intel_attached_dig_port(connector);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
-   struct i915_hdcp_comp_master *comp;
+   struct i915_hdcp_fw_master *comp;
int ret;
 
mutex_lock(&dev_priv->display.hdcp.comp_mutex);
@@ -1212,7 +1212,7 @@ static int hdcp2_verify_hprime(struct intel_connector 
*connector,
return -EINVAL;
}
 
-   ret = comp->ops->verify_hprime(comp->mei_dev, data, rx_hprime);
+   ret = comp->ops->verify_hprime(comp->fw_dev, data, rx_hprime);
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Verify hprime failed. %d\n", ret);
mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
@@ -1227,7 +1227,7 @@ hdcp2_store_pairing_info(struct intel_connector 
*connector,
struct intel_digital_port *dig_port = 
intel_attached_dig_port(connector);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
-   struct i915_hdcp_comp_master *comp;
+   struct i915_hdcp_fw_master *comp;
int ret;

[Intel-gfx] [PATCH v2 1/7] drm/i915/gsc: Create GSC request submission mechanism

2022-12-12 Thread Suraj Kandpal

HDCP and PXP will require a common function to allow it to
submit commands to the gsc cs. Also adding the gsc mtl header
that needs to be added on to the existing payloads of HDCP
and PXP.

Cc: Daniele Ceraolo Spurio 
Cc: Alan Previn 
Signed-off-by: Suraj Kandpal
---
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h |  2 +
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c| 62 +++-
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h|  3 +
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h  | 41 +
 4 files changed, 105 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h

diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h 
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 2af1ae3831df..454179884801 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -439,6 +439,8 @@
 #define GSC_FW_LOAD GSC_INSTR(1, 0, 2)
 #define   HECI1_FW_LIMIT_VALID (1 << 31)
 
+#define GSC_HECI_CMD_PKT GSC_INSTR(0, 0, 6)
+
 /*
  * Used to convert any address to canonical form.
  * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
index e73d4440c5e8..f00e88fdb5d2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
@@ -30,6 +30,35 @@ bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc)
return fw_status & GSC_FW_INIT_COMPLETE_BIT;
 }
 
+struct gsc_heci_pkt {
+   u64 addr_in;
+   u32 size_in;
+   u64 addr_out;
+   u32 size_out;
+};
+
+static int emit_gsc_heci_pkt(struct i915_request *rq, struct gsc_heci_pkt *pkt)
+{
+   u32 *cs;
+
+   cs = intel_ring_begin(rq, 8);
+   if (IS_ERR(cs))
+   return PTR_ERR(cs);
+
+   *cs++ = GSC_HECI_CMD_PKT;
+   *cs++ = lower_32_bits(pkt->addr_in);
+   *cs++ = upper_32_bits(pkt->addr_in);
+   *cs++ = pkt->size_in;
+   *cs++ = lower_32_bits(pkt->addr_out);
+   *cs++ = upper_32_bits(pkt->addr_out);
+   *cs++ = pkt->size_out;
+   *cs++ = 0;
+
+   intel_ring_advance(rq, cs);
+
+   return 0;
+}
+
 static int emit_gsc_fw_load(struct i915_request *rq, struct intel_gsc_uc *gsc)
 {
u32 offset = i915_ggtt_offset(gsc->local);
@@ -49,7 +78,12 @@ static int emit_gsc_fw_load(struct i915_request *rq, struct 
intel_gsc_uc *gsc)
return 0;
 }
 
-static int gsc_fw_load(struct intel_gsc_uc *gsc)
+/*
+ * Our submissions to GSC are going to be either a FW load or an heci pkt, but
+ * all the request emission logic is the same so we can use a common func and
+ * just add the correct cmd
+ */
+static int submit_to_gsc_fw(struct intel_gsc_uc *gsc, struct gsc_heci_pkt *pkt)
 {
struct intel_context *ce = gsc->ce;
struct i915_request *rq;
@@ -68,7 +102,11 @@ static int gsc_fw_load(struct intel_gsc_uc *gsc)
goto out_rq;
}
 
-   err = emit_gsc_fw_load(rq, gsc);
+   if (pkt)
+   err = emit_gsc_heci_pkt(rq, pkt);
+   else
+   err = emit_gsc_fw_load(rq, gsc);
+
if (err)
goto out_rq;
 
@@ -89,12 +127,30 @@ static int gsc_fw_load(struct intel_gsc_uc *gsc)
 
if (err)
drm_err(&gsc_uc_to_gt(gsc)->i915->drm,
-   "Request submission for GSC load failed (%d)\n",
+   "Request submission for GSC failed (%d)\n",
err);
 
return err;
 }
 
+static int gsc_fw_load(struct intel_gsc_uc *gsc)
+{
+   return submit_to_gsc_fw(gsc, NULL);
+}
+
+int intel_gsc_fw_heci_send(struct intel_gsc_uc *gsc, u64 addr_in, u32 size_in,
+  u64 addr_out, u32 size_out)
+{
+   struct gsc_heci_pkt pkt = {
+   .addr_in = addr_in,
+   .size_in = size_in,
+   .addr_out = addr_out,
+   .size_out = size_out
+   };
+
+   return submit_to_gsc_fw(gsc, &pkt);
+}
+
 static int gsc_fw_load_prepare(struct intel_gsc_uc *gsc)
 {
struct intel_gt *gt = gsc_uc_to_gt(gsc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h 
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
index 4b5dbb44afb4..4a75c3dec669 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
@@ -12,4 +12,7 @@ struct intel_gsc_uc;
 
 int intel_gsc_uc_fw_upload(struct intel_gsc_uc *gsc);
 bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc);
+int intel_gsc_fw_heci_send(struct intel_gsc_uc *gsc, u64 addr_in, u32 size_in,
+  u64 addr_out, u32 size_out);
+
 #endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h
new file mode 100644
index ..1c2a04d092a8
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef _INTEL_GSC_FWIF_H_
+#define

[Intel-gfx] [PATCH v2 0/7] Enable HDCP2.x via GSC CS

2022-12-12 Thread Suraj Kandpal

These patches enable HDCP2.x on machines MTL and above.
>From MTL onwards CSME is spilt into GSC and CSC and now
we use GSC CS instead of MEI to talk to firmware to start
HDCP authentication

--v2
-Fixing some checkpatch changes which I forgot before sending
out the series

Anshuman Gupta (3):
  drm/i915/hdcp: Keep cp fw agonstic naming convention
  drm/i915/hdcp: HDCP2.x Refactoring to agnotic cp f/w
  drm/i915/hdcp: Refactor HDCP API structures

Suraj Kandpal (4):
  drm/i915/gsc: Create GSC request submission mechanism
  drm/i915/hdcp: Fill wired_cmd_in structures at a single place
  drm/i915/mtl: Adding function to send command to GSC CS
  drm/i915/mtl: Add HDCP GSC interface

 drivers/gpu/drm/i915/Makefile |   1 +
 .../gpu/drm/i915/display/intel_display_core.h |   3 +-
 .../drm/i915/display/intel_display_types.h|   2 +-
 drivers/gpu/drm/i915/display/intel_hdcp.c |  94 ++-
 drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 708 +
 drivers/gpu/drm/i915/display/intel_hdcp_gsc.h |  28 +
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h  |   2 +
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c |  62 +-
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h |   3 +
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h   |  42 +
 drivers/misc/mei/hdcp/mei_hdcp.c  | 190 +
 drivers/misc/mei/hdcp/mei_hdcp.h  | 355 +
 include/drm/i915_cp_fw_hdcp_interface.h   | 736 ++
 include/drm/i915_mei_hdcp_interface.h | 184 -
 14 files changed, 1670 insertions(+), 740 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdcp_gsc.h
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h
 create mode 100644 include/drm/i915_cp_fw_hdcp_interface.h
 delete mode 100644 include/drm/i915_mei_hdcp_interface.h

-- 
2.25.1

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/hdmi: Go for scrambling only if platform supports TMDS clock > 340MHz

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915/hdmi: Go for scrambling only if platform supports TMDS clock > 
340MHz
URL   : https://patchwork.freedesktop.org/series/111877/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12498 -> Patchwork_111877v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_111877v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111877v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111877v1/index.html

Participating hosts (39 -> 19)
--

  ERROR: It appears as if the changes made in Patchwork_111877v1 prevented too 
many machines from booting.

  Missing(20): fi-kbl-soraka bat-dg1-6 bat-dg1-5 bat-adlp-6 fi-skl-6600u 
fi-bsw-n3050 bat-dg2-8 bat-adlm-1 bat-dg2-9 fi-bwr-2160 bat-adln-1 bat-atsm-1 
bat-jsl-3 bat-rplp-1 bat-dg2-11 fi-bsw-nick bat-dg1-7 bat-kbl-2 bat-adlp-9 
bat-adlp-4 

Known issues


  Here are the changes found in Patchwork_111877v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#111827])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111877v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  
 Possible fixes 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[FAIL][2] ([i915#7229]) -> [PASS][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12498/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111877v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][4] ([i915#4785]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12498/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111877v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
  [i915#6106]: https://gitlab.freedesktop.org/drm/intel/issues/6106
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229


Build changes
-

  * Linux: CI_DRM_12498 -> Patchwork_111877v1

  CI-20190529: 20190529
  CI_DRM_12498: 76c062e92f2d28ab3d6a1b122cae8931e55b4fd9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7091: b8015f920c9f469d3733854263cb878373c1df51 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111877v1: 76c062e92f2d28ab3d6a1b122cae8931e55b4fd9 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

3c9f7099e0d8 drm/i915/hdmi: Go for scrambling only if platform supports TMDS 
clock > 340MHz

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111877v1/index.html

[Intel-gfx] ✗ Fi.CI.BAT: failure for Enable HDCP2.x via GSC CS

2022-12-12 Thread Patchwork

== Series Details ==

Series: Enable HDCP2.x via GSC CS
URL   : https://patchwork.freedesktop.org/series/111876/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12498 -> Patchwork_111876v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_111876v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111876v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v1/index.html

Participating hosts (39 -> 19)
--

  ERROR: It appears as if the changes made in Patchwork_111876v1 prevented too 
many machines from booting.

  Missing(20): fi-kbl-soraka bat-dg1-6 bat-dg1-5 bat-adlp-6 fi-skl-6600u 
fi-bsw-n3050 bat-dg2-8 bat-adlm-1 bat-dg2-9 fi-bwr-2160 bat-adln-1 bat-atsm-1 
bat-jsl-3 bat-rplp-1 bat-dg2-11 fi-bsw-nick bat-dg1-7 bat-kbl-2 bat-adlp-9 
bat-adlp-4 

Known issues


  Here are the changes found in Patchwork_111876v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#111827])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  
 Possible fixes 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[FAIL][2] ([i915#7229]) -> [PASS][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12498/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][4] ([i915#4785]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12498/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229


Build changes
-

  * Linux: CI_DRM_12498 -> Patchwork_111876v1

  CI-20190529: 20190529
  CI_DRM_12498: 76c062e92f2d28ab3d6a1b122cae8931e55b4fd9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7091: b8015f920c9f469d3733854263cb878373c1df51 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111876v1: 76c062e92f2d28ab3d6a1b122cae8931e55b4fd9 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

441033ee3375 drm/i915/mtl: Add HDCP GSC interface
539e0d8aa2cf drm/i915/mtl: Adding function to send command to GSC CS
61cb5c3d39d4 drm/i915/hdcp: Fill wired_cmd_in structures at a single place
4d5a5f2e41ff drm/i915/hdcp: Refactor HDCP API structures
a8775edff2c8 drm/i915/hdcp: HDCP2.x Refactoring to agnotic cp f/w
33123f6641be drm/i915/hdcp: Keep cp fw agonstic naming convention
de4a9ed2c011 drm/i915/gsc: Create GSC request submission mechanism

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v1/index.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable HDCP2.x via GSC CS

2022-12-12 Thread Patchwork

== Series Details ==

Series: Enable HDCP2.x via GSC CS
URL   : https://patchwork.freedesktop.org/series/111876/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable HDCP2.x via GSC CS

2022-12-12 Thread Patchwork

== Series Details ==

Series: Enable HDCP2.x via GSC CS
URL   : https://patchwork.freedesktop.org/series/111876/
State : warning

== Summary ==

Error: dim checkpatch failed
6de8612b95c0 drm/i915/gsc: Create GSC request submission mechanism
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
-:140: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#140: 
new file mode 100644

-:162: ERROR:TRAILING_WHITESPACE: trailing whitespace
#162: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h:18:
+ $

-:162: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#162: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h:18:
+ $

-:167: ERROR:TRAILING_WHITESPACE: trailing whitespace
#167: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h:23:
+ $

-:167: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#167: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h:23:
+ $

total: 2 errors, 3 warnings, 0 checks, 147 lines checked
1f1f20f4af0b drm/i915/hdcp: Keep cp fw agonstic naming convention
-:45: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#45: 
rename from include/drm/i915_mei_hdcp_interface.h

total: 0 errors, 1 warnings, 0 checks, 31 lines checked
efb9891043b1 drm/i915/hdcp: HDCP2.x Refactoring to agnotic cp f/w
27aea54bfe6a drm/i915/hdcp: Refactor HDCP API structures
b5222dbaf658 drm/i915/hdcp: Fill wired_cmd_in structures at a single place
-:97: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#97: FILE: drivers/misc/mei/hdcp/mei_hdcp.c:217:
+   i915_cp_fw_fill_pairing_info_in(&pairing_info_in, pairing_info,
+  data);

-:137: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#137: FILE: drivers/misc/mei/hdcp/mei_hdcp.c:312:
+   i915_cp_fw_fill_validate_locality_in(&verify_lprime_in, rx_lprime,
+   data);

-:207: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#207: FILE: drivers/misc/mei/hdcp/mei_hdcp.c:477:
+   i915_cp_fw_fill_auth_stream_req_in(verify_mprime_in, stream_ready,
+ cmd_size, data);

-:258: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#258: FILE: include/drm/i915_cp_fw_hdcp_interface.h:541:
+i915_cp_fw_fill_session_in(struct wired_cmd_initiate_hdcp2_session_in 
*session_init_in,
+ struct hdcp_port_data *data)

-:274: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#274: FILE: include/drm/i915_cp_fw_hdcp_interface.h:557:
+i915_cp_fw_fill_rxcert_in(struct wired_cmd_verify_receiver_cert_in 
*verify_rxcert_in,
+struct hdcp2_ake_send_cert *rx_cert,

-:292: CHECK:LINE_SPACING: Please don't use multiple blank lines
#292: FILE: include/drm/i915_cp_fw_hdcp_interface.h:575:
+
+

-:295: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#295: FILE: include/drm/i915_cp_fw_hdcp_interface.h:578:
+i915_cp_fw_fill_hprime_in(struct wired_cmd_ake_send_hprime_in *send_hprime_in,
+struct hdcp2_ake_send_hprime *rx_hprime,

-:313: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#313: FILE: include/drm/i915_cp_fw_hdcp_interface.h:596:
+i915_cp_fw_fill_pairing_info_in(struct wired_cmd_ake_send_pairing_info_in 
*pairing_info_in,
+  struct hdcp2_ake_send_pairing_info *pairing_info,

-:332: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#332: FILE: include/drm/i915_cp_fw_hdcp_interface.h:615:
+i915_cp_fw_fill_locality_check_in(struct wired_cmd_init_locality_check_in 
*lc_init_in,
+struct hdcp_port_data *data)

-:346: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#346: FILE: include/drm/i915_cp_fw_hdcp_interface.h:629:
+i915_cp_fw_fill_validate_locality_in(struct wired_cmd_validate_locality_in 
*verify_lprime_in,
+   struct hdcp2_lc_send_lprime *rx_lprime,

-:365: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#365: FILE: include/drm/i915_cp_fw_hdcp_interface.h:648:
+i915_cp_fw_fill_session_key_in(struct wired_cmd_get_session_key_in 
*get_skey_in,
+ struct hdcp_port_data *data)

-:379: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#379: FILE: include/drm/i915_cp_fw_hdcp_interface.h:662:
+i915_cp_fw_fill_repeater_in(struct wired_cmd_verify_repeater_in 
*verify_repeater_in,
+  struct hdcp2_rep_send_receiverid_list *rep_topology,

-:404: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#404: FILE: include/drm/i915_cp_fw_hdcp_interface.h:687:
+i915_cp_fw_fill_auth_stream_req_in(struct 
wired_cmd_repeater_auth_stream_req_in *verify_mprime_in,
+

[Intel-gfx] [PATCH v2] drm/i915/hwconfig: Remove comment block

2022-12-12 Thread Jiapeng Chong

No functional modification involved.

drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c:112: warning: expecting 
prototype for intel_guc_hwconfig_init(). Prototype was for guc_hwconfig_init() 
instead.

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=3414
Reported-by: Abaci Robot 
Signed-off-by: Jiapeng Chong 
---
Changes in v2:
  -Remove the comment block.

 drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
index 4781fccc2687..5559d39881ee 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
@@ -102,12 +102,6 @@ static bool has_table(struct drm_i915_private *i915)
return false;
 }
 
-/**
- * intel_guc_hwconfig_init - Initialize the HWConfig
- *
- * Retrieve the HWConfig table from the GuC and save it locally.
- * It can then be queried on demand by other users later on.
- */
 static int guc_hwconfig_init(struct intel_gt *gt)
 {
struct intel_hwconfig *hwconfig = >->info.hwconfig;
-- 
2.20.1.7.g153144c

[Intel-gfx] [PATCH] drm/i915/hdmi: Go for scrambling only if platform supports TMDS clock > 340MHz

2022-12-12 Thread Ankit Nautiyal

There are cases, where devices have an HDMI1.4 retimer, and TMDS clock rate
is capped to 340MHz via VBT. In such cases scrambling might be supported
by the platform and an HDMI2.0 sink for lower TMDS rates, but not
supported by the retimer, causing blankouts.

So avoid enabling scrambling, if the TMDS clock is capped to <= 340MHz.

Signed-off-by: Ankit Nautiyal 
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index efa2da080f62..c124fe667bc0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2244,6 +2244,11 @@ static bool intel_hdmi_is_cloned(const struct 
intel_crtc_state *crtc_state)
!is_power_of_2(crtc_state->uapi.encoder_mask);
 }
 
+static bool source_can_support_scrambling(struct intel_encoder *encoder)
+{
+   return intel_hdmi_source_max_tmds_clock(encoder) > 34;
+}
+
 int intel_hdmi_compute_config(struct intel_encoder *encoder,
  struct intel_crtc_state *pipe_config,
  struct drm_connector_state *conn_state)
@@ -2301,7 +2306,7 @@ int intel_hdmi_compute_config(struct intel_encoder 
*encoder,
 
pipe_config->lane_count = 4;
 
-   if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) {
+   if (scdc->scrambling.supported && 
source_can_support_scrambling(encoder)) {
if (scdc->scrambling.low_rates)
pipe_config->hdmi_scrambling = true;
 
-- 
2.25.1

Re: [Intel-gfx] [RESEND PATCHv3] drm/i915/dp: Change aux_ctl reg read to polling read

2022-12-12 Thread Murthy, Arun R

> -Original Message-
> From: Nikula, Jani 
> Sent: Friday, December 9, 2022 4:16 PM
> To: Murthy, Arun R ; intel-
> g...@lists.freedesktop.org; ville.syrj...@linux.intel.com; Deak, Imre
> 
> Cc: Murthy, Arun R 
> Subject: Re: [RESEND PATCHv3] drm/i915/dp: Change aux_ctl reg read to
> polling read
> 
> On Fri, 09 Dec 2022, Arun R Murthy  wrote:
> > The busy timeout logic checks for the AUX BUSY, then waits for the
> > timeout period and then after timeout reads the register for BUSY or
> > Success.
> > Instead replace interrupt with polling so as to read the AUX CTL
> > register often before the timeout period. Looks like there might be
> > some issue with interrupt-on-read. Hence changing the logic to polling
> read.
> >
> > v2: replace interrupt with polling read
> > v3: use usleep_rang instead of msleep, updated commit msg
> >
> > Signed-off-by: Arun R Murthy 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp_aux.c | 24
> > -
> >  1 file changed, 14 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > index 91c93c93e5fc..230f27d75846 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> > @@ -41,21 +41,25 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
> > i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
> > const unsigned int timeout_ms = 10;
> > u32 status;
> > -   bool done;
> > +   int try;
> >
> > -#define C (((status = intel_de_read_notrace(i915, ch_ctl)) &
> DP_AUX_CH_CTL_SEND_BUSY) == 0)
> > -   done = wait_event_timeout(i915->display.gmbus.wait_queue, C,
> > - msecs_to_jiffies_timeout(timeout_ms));
> > +   for (try = 0; try < 10; try++) {
> > +   status = intel_uncore_read_notrace(&i915->uncore, ch_ctl);
> > +   if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
> > +   break;
> > +   usleep_range(400, 500);
> > +   }
> > +   if (try == 3) {
> > +   status = intel_uncore_read_notrace(&i915->uncore, ch_ctl);
> > +   if ((status & DP_AUX_CH_CTL_SEND_BUSY) != 0)
> > +   drm_err(&i915->drm,
> > +   "%s: did not complete or timeout within
> %ums (status 0x%08x)\n",
> > +   intel_dp->aux.name, timeout_ms, status);
> > +   }
> >
> > /* just trace the final value */
> > trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
> 
> Okay, so there are still a bunch of issues above. For example, try < 10 vs. 
> try
> == 3, reverting back to intel_uncore_* functions after conflict resolution,
> having duplicated reads and conditions.
The logic tries to read in a loop for 10 times with a sleep of 500usec between 
each reads.
Finally after the 10th iteration for the last time the register is read again 
and the status is returned.

> 
> Now, I should've taken a step back earlier and realized you should use the
> helper we already have for this: intel_de_wait_for_register().

I checked this earlier. The reason for not opting this is this function is its
interrupt-on-read, but we need a polling read with timeout.

Thanks and Regards,
Arun R Murthy

> 
> All of the above shrinks to just a few lines:
> 
>   ret = intel_de_wait_for_register(i915, ch_ctl,
> DP_AUX_CH_CTL_SEND_BUSY, 0, timeout_ms);
>   if (ret)
>   drm_err(...);
> 
> Sorry for missing this earlier.
> 
> BR,
> Jani.
> 
> >
> > -   if (!done)
> > -   drm_err(&i915->drm,
> > -   "%s: did not complete or timeout within %ums
> (status 0x%08x)\n",
> > -   intel_dp->aux.name, timeout_ms, status);
> > -#undef C
> > -
> > return status;
> >  }
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 6/7] drm/i915/mtl: Adding function to send command to GSC CS

2022-12-12 Thread Suraj Kandpal

Adding function that takes care of sending command to gsc cs. We start
of with allocation of memory for our command intel_hdcp_gsc_message that
contains gsc cs memory header as directed in specs followed by the
actual payload hdcp message that we want to send.
Spec states that we need to poll pending bit of response header around
20 times each try being 50ms apart hence adding that to current
gsc_msg_send function
Also we use the same function to take care of both sending and receiving
hence no separate function to get the response.

Cc: Ankit Nautiyal 
Cc: Daniele Ceraolo Spurio 
Cc: Uma Shankar 
Cc: Anshuman Gupta 
Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 207 ++
 drivers/gpu/drm/i915/display/intel_hdcp_gsc.h |  28 +++
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h   |   1 +
 4 files changed, 237 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdcp_gsc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index dfa211451a1d..42b8c3430365 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -250,6 +250,7 @@ i915-y += \
display/intel_frontbuffer.o \
display/intel_global_state.o \
display/intel_hdcp.o \
+   display/intel_hdcp_gsc.o \
display/intel_hotplug.o \
display/intel_hti.o \
display/intel_lpe_audio.o \
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c 
b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
new file mode 100644
index ..aea3a1158c75
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2021, Intel Corporation.
+ */
+
+#include "i915_drv.h"
+#include "gt/uc/intel_gsc_fw.h"
+#include "gt/uc/intel_gsc_fwif.h"
+#include "gem/i915_gem_region.h"
+#include "i915_utils.h"
+#include "display/intel_hdcp_gsc.h"
+
+struct intel_hdcp_gsc_message {
+   struct drm_i915_gem_object *obj;
+   struct i915_vma *vma;
+   void *hdcp_cmd;
+};
+
+/*This function helps allocate memory for the command that we will send to gsc 
cs */
+static int intel_initialize_hdcp_gsc_message(struct drm_i915_private *i915,
+struct intel_hdcp_gsc_message 
*hdcp_message)
+{
+   struct intel_gt *gt = i915->media_gt;
+   struct drm_i915_gem_object *obj = NULL;
+   struct i915_vma *vma = NULL;
+   void *cmd;
+   int err;
+
+   hdcp_message->obj = NULL;
+   hdcp_message->hdcp_cmd = NULL;
+   hdcp_message->vma = NULL;
+
+   /* allocate object of one page for HDCP command memory and store it */
+   obj = i915_gem_object_create_shmem(gt->i915, PAGE_SIZE);
+
+   if (IS_ERR(obj)) {
+   drm_err(>->i915->drm, "Failed to allocate HDCP streaming 
command!\n");
+   return PTR_ERR(obj);
+   }
+
+   cmd = i915_gem_object_pin_map_unlocked(obj, 
i915_coherent_map_type(gt->i915, obj, true));
+   if (IS_ERR(cmd)) {
+   drm_err(>->i915->drm, "Failed to map gsc message page!\n");
+   err = PTR_ERR(cmd);
+   goto out_unpin;
+   }
+
+   vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
+   if (IS_ERR(vma)) {
+   err = PTR_ERR(vma);
+   goto out_unmap;
+   }
+
+   err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+   if (err)
+   goto out_unmap;
+
+   memset(cmd, 0, obj->base.size);
+
+   hdcp_message->obj = obj;
+   hdcp_message->hdcp_cmd = cmd;
+   hdcp_message->vma = vma;
+
+   return 0;
+
+out_unmap:
+   i915_gem_object_unpin_map(obj);
+out_unpin:
+   i915_gem_object_put(obj);
+   return err;
+}
+
+static void intel_free_hdcp_gsc_message(struct intel_hdcp_gsc_message 
*hdcp_message)
+{
+   struct drm_i915_gem_object *obj = fetch_and_zero(&hdcp_message->obj);
+
+   if (!obj)
+   return;
+
+   if (hdcp_message->vma)
+   i915_vma_unpin(fetch_and_zero(&hdcp_message->vma));
+
+   i915_gem_object_unpin_map(obj);
+   i915_gem_object_put(obj);
+   kfree(hdcp_message);
+}
+
+static int intel_gsc_send_sync(struct drm_i915_private *i915,
+  struct intel_gsc_mtl_header *header, u64 addr,
+  size_t msg_out_len)
+{
+   struct intel_gt *gt = i915->media_gt;
+   int ret;
+
+   header->flags = 0;
+   ret = intel_gsc_fw_heci_send(>->uc.gsc, addr, header->message_size,
+addr, msg_out_len + sizeof(*header));
+   if (ret) {
+   drm_err(&i915->drm, "failed to send gsc HDCP msg (%d)\n", ret);
+   return ret;
+   }
+   /*
+* Checking validity marker for memory sanity
+*/
+   if (header->validity_marker != GSC_HECI_VALIDITY_M

[Intel-gfx] [PATCH 5/7] drm/i915/hdcp: Fill wired_cmd_in structures at a single place

2022-12-12 Thread Suraj Kandpal

Need to fill wired cmd in structures at a single place as they remain same
for both gsc and mei

Cc: Ankit Nautiyal 
Signed-off-by: Suraj Kandpal 
---
 drivers/misc/mei/hdcp/mei_hdcp.c| 154 ++
 include/drm/i915_cp_fw_hdcp_interface.h | 200 
 2 files changed, 214 insertions(+), 140 deletions(-)

diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 51e3edac565d..34e041084170 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -50,17 +50,7 @@ mei_hdcp_initiate_session(struct device *dev, struct 
hdcp_port_data *data,
 
cldev = to_mei_cl_device(dev);
 
-   session_init_in.header.api_version = HDCP_API_VERSION;
-   session_init_in.header.command_id = WIRED_INITIATE_HDCP2_SESSION;
-   session_init_in.header.status = FW_HDCP_STATUS_SUCCESS;
-   session_init_in.header.buffer_len =
-   WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN;
-
-   session_init_in.port.integrated_port_type = data->port_type;
-   session_init_in.port.physical_port = (u8)data->fw_ddi;
-   session_init_in.port.attached_transcoder = (u8)data->fw_tc;
-   session_init_in.protocol = data->protocol;
-
+   i915_cp_fw_fill_session_in(&session_init_in, data);
byte = mei_cldev_send(cldev, (u8 *)&session_init_in,
  sizeof(session_init_in));
if (byte < 0) {
@@ -119,21 +109,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device 
*dev,
return -EINVAL;
 
cldev = to_mei_cl_device(dev);
-
-   verify_rxcert_in.header.api_version = HDCP_API_VERSION;
-   verify_rxcert_in.header.command_id = WIRED_VERIFY_RECEIVER_CERT;
-   verify_rxcert_in.header.status = FW_HDCP_STATUS_SUCCESS;
-   verify_rxcert_in.header.buffer_len =
-   WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN;
-
-   verify_rxcert_in.port.integrated_port_type = data->port_type;
-   verify_rxcert_in.port.physical_port = (u8)data->fw_ddi;
-   verify_rxcert_in.port.attached_transcoder = (u8)data->fw_tc;
-
-   verify_rxcert_in.cert_rx = rx_cert->cert_rx;
-   memcpy(verify_rxcert_in.r_rx, &rx_cert->r_rx, HDCP_2_2_RRX_LEN);
-   memcpy(verify_rxcert_in.rx_caps, rx_cert->rx_caps, HDCP_2_2_RXCAPS_LEN);
-
+   i915_cp_fw_fill_rxcert_in(&verify_rxcert_in, rx_cert, data);
byte = mei_cldev_send(cldev, (u8 *)&verify_rxcert_in,
  sizeof(verify_rxcert_in));
if (byte < 0) {
@@ -192,18 +168,7 @@ mei_hdcp_verify_hprime(struct device *dev, struct 
hdcp_port_data *data,
 
cldev = to_mei_cl_device(dev);
 
-   send_hprime_in.header.api_version = HDCP_API_VERSION;
-   send_hprime_in.header.command_id = WIRED_AKE_SEND_HPRIME;
-   send_hprime_in.header.status = FW_HDCP_STATUS_SUCCESS;
-   send_hprime_in.header.buffer_len = WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN;
-
-   send_hprime_in.port.integrated_port_type = data->port_type;
-   send_hprime_in.port.physical_port = (u8)data->fw_ddi;
-   send_hprime_in.port.attached_transcoder = (u8)data->fw_tc;
-
-   memcpy(send_hprime_in.h_prime, rx_hprime->h_prime,
-  HDCP_2_2_H_PRIME_LEN);
-
+   i915_cp_fw_fill_hprime_in(&send_hprime_in, rx_hprime, data);
byte = mei_cldev_send(cldev, (u8 *)&send_hprime_in,
  sizeof(send_hprime_in));
if (byte < 0) {
@@ -248,20 +213,8 @@ mei_hdcp_store_pairing_info(struct device *dev, struct 
hdcp_port_data *data,
return -EINVAL;
 
cldev = to_mei_cl_device(dev);
-
-   pairing_info_in.header.api_version = HDCP_API_VERSION;
-   pairing_info_in.header.command_id = WIRED_AKE_SEND_PAIRING_INFO;
-   pairing_info_in.header.status = FW_HDCP_STATUS_SUCCESS;
-   pairing_info_in.header.buffer_len =
-   WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN;
-
-   pairing_info_in.port.integrated_port_type = data->port_type;
-   pairing_info_in.port.physical_port = (u8)data->fw_ddi;
-   pairing_info_in.port.attached_transcoder = (u8)data->fw_tc;
-
-   memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km,
-  HDCP_2_2_E_KH_KM_LEN);
-
+   i915_cp_fw_fill_pairing_info_in(&pairing_info_in, pairing_info,
+  data);
byte = mei_cldev_send(cldev, (u8 *)&pairing_info_in,
  sizeof(pairing_info_in));
if (byte < 0) {
@@ -308,16 +261,7 @@ mei_hdcp_initiate_locality_check(struct device *dev,
return -EINVAL;
 
cldev = to_mei_cl_device(dev);
-
-   lc_init_in.header.api_version = HDCP_API_VERSION;
-   lc_init_in.header.command_id = WIRED_INIT_LOCALITY_CHECK;
-   lc_init_in.header.status = FW_HDCP_STATUS_SUCCESS;
-   lc_init_in.header.buffer_len = WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_IN;
-
-   lc_init_in.port.integrated_p

[Intel-gfx] [PATCH 3/7] drm/i915/hdcp: HDCP2.x Refactoring to agnotic cp f/w

2022-12-12 Thread Suraj Kandpal

From: Anshuman Gupta 

As now we have more then one type of content protection
secrity firmware. Let change the i915_cp_fw_hdcp_interface.h
header naming convention to suit generic f/w type.
%s/MEI_/FW_
%s/mei_fw/cp_fw
%s/mei_dev/fw_dev

As interface to CP FW can be either a non i915 component or
i915 intergral component, change structure name Accordingly.
%s/i915_hdcp_comp_master/i915_hdcp_fw_master
%s/i915_hdcp_component_ops/i915_hdcp_fw_ops

Cc: Tomas Winkler 
Cc: Rodrigo Vivi 
Cc: Uma Shankar 
Cc: Ankit Nautiyal 
Signed-off-by: Anshuman Gupta 
Signed-off-by: Suraj Kandpal 
---
 .../gpu/drm/i915/display/intel_display_core.h |  3 +-
 drivers/gpu/drm/i915/display/intel_hdcp.c | 66 -
 drivers/misc/mei/hdcp/mei_hdcp.c  | 12 ++--
 include/drm/i915_cp_fw_hdcp_interface.h   | 70 +--
 4 files changed, 76 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h 
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 57ddce3ba02b..a769cc8e2745 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -16,6 +16,7 @@
 #include 
 #include 
 
+#include "i915/i915_cp_fw_hdcp_interface.h"
 #include "intel_cdclk.h"
 #include "intel_display.h"
 #include "intel_display_power.h"
@@ -368,7 +369,7 @@ struct intel_display {
} gmbus;
 
struct {
-   struct i915_hdcp_comp_master *master;
+   struct i915_hdcp_fw_master *master;
bool comp_added;
 
/* Mutex to protect the above hdcp component related values. */
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c 
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 6406fd487ee5..e856b10948ab 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1143,7 +1143,7 @@ hdcp2_prepare_ake_init(struct intel_connector *connector,
struct intel_digital_port *dig_port = 
intel_attached_dig_port(connector);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
-   struct i915_hdcp_comp_master *comp;
+   struct i915_hdcp_fw_master *comp;
int ret;
 
mutex_lock(&dev_priv->display.hdcp.comp_mutex);
@@ -1154,7 +1154,7 @@ hdcp2_prepare_ake_init(struct intel_connector *connector,
return -EINVAL;
}
 
-   ret = comp->ops->initiate_hdcp2_session(comp->mei_dev, data, ake_data);
+   ret = comp->ops->initiate_hdcp2_session(comp->fw_dev, data, ake_data);
if (ret)
drm_dbg_kms(&dev_priv->drm, "Prepare_ake_init failed. %d\n",
ret);
@@ -1173,7 +1173,7 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector 
*connector,
struct intel_digital_port *dig_port = 
intel_attached_dig_port(connector);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
-   struct i915_hdcp_comp_master *comp;
+   struct i915_hdcp_fw_master *comp;
int ret;
 
mutex_lock(&dev_priv->display.hdcp.comp_mutex);
@@ -1184,7 +1184,7 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector 
*connector,
return -EINVAL;
}
 
-   ret = comp->ops->verify_receiver_cert_prepare_km(comp->mei_dev, data,
+   ret = comp->ops->verify_receiver_cert_prepare_km(comp->fw_dev, data,
 rx_cert, paired,
 ek_pub_km, msg_sz);
if (ret < 0)
@@ -1201,7 +1201,7 @@ static int hdcp2_verify_hprime(struct intel_connector 
*connector,
struct intel_digital_port *dig_port = 
intel_attached_dig_port(connector);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
-   struct i915_hdcp_comp_master *comp;
+   struct i915_hdcp_fw_master *comp;
int ret;
 
mutex_lock(&dev_priv->display.hdcp.comp_mutex);
@@ -1212,7 +1212,7 @@ static int hdcp2_verify_hprime(struct intel_connector 
*connector,
return -EINVAL;
}
 
-   ret = comp->ops->verify_hprime(comp->mei_dev, data, rx_hprime);
+   ret = comp->ops->verify_hprime(comp->fw_dev, data, rx_hprime);
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Verify hprime failed. %d\n", ret);
mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
@@ -1227,7 +1227,7 @@ hdcp2_store_pairing_info(struct intel_connector 
*connector,
struct intel_digital_port *dig_port = 
intel_attached_dig_port(connector);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
-   struct i915_hdcp_comp_master *comp;
+   struct i915_hdcp_fw_master *comp;
int ret;

[Intel-gfx] [PATCH 7/7] drm/i915/mtl: Add HDCP GSC interface

2022-12-12 Thread Suraj Kandpal

MTL uses GSC command streamer i.e gsc cs to send HDCP/PXP commands
to GSC f/w. It requires to keep hdcp display driver
agnostic to content protection f/w (ME/GSC fw) in the form of
i915_hdcp_fw_ops generic ops.

Adding HDCP GSC CS interface by leveraging the i915_hdcp_fw_ops generic
ops instead of I915_HDCP_COMPONENT as integral part of i915.

Adding checks to see if GSC is loaded and proxy is setup

Cc: Tomas Winkler 
Cc: Rodrigo Vivi 
Cc: Uma Shankar 
Cc: Ankit Nautiyal 
Signed-off-by: Anshuman Gupta 
Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/i915/display/intel_hdcp.c |  28 +-
 drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 503 +-
 2 files changed, 524 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c 
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index e856b10948ab..efdaa938df48 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -25,6 +25,8 @@
 #include "intel_hdcp.h"
 #include "intel_hdcp_regs.h"
 #include "intel_pcode.h"
+#include "intel_connector.h"
+#include "display/intel_hdcp_gsc.h"
 
 #define KEY_LOAD_TRIES 5
 #define HDCP2_LC_RETRY_CNT 3
@@ -203,13 +205,20 @@ bool intel_hdcp2_capable(struct intel_connector 
*connector)
struct intel_digital_port *dig_port = 
intel_attached_dig_port(connector);
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
+   struct intel_gt *gt = dev_priv->media_gt;
+   struct intel_gsc_uc *gsc = >->uc.gsc;
bool capable = false;
 
/* I915 support for HDCP2.2 */
if (!hdcp->hdcp2_supported)
return false;
 
-   /* MEI interface is solid */
+   /* If MTL+ make sure gsc is loaded and proxy is setup */
+   if (DISPLAY_VER(dev_priv) >= 14)
+   if (!intel_uc_fw_is_running(&gsc->fw))
+   return false;
+
+   /* MEI/GSC interface is solid depending on which is used */
mutex_lock(&dev_priv->display.hdcp.comp_mutex);
if (!dev_priv->display.hdcp.comp_added ||  
!dev_priv->display.hdcp.master) {
mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
@@ -2235,7 +2244,7 @@ static int initialize_hdcp_port_data(struct 
intel_connector *connector,
 
 static bool is_hdcp2_supported(struct drm_i915_private *dev_priv)
 {
-   if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP))
+   if (DISPLAY_VER(dev_priv) < 14 && !IS_ENABLED(CONFIG_INTEL_MEI_HDCP))
return false;
 
return (DISPLAY_VER(dev_priv) >= 10 ||
@@ -2256,10 +2265,14 @@ void intel_hdcp_component_init(struct drm_i915_private 
*dev_priv)
 
dev_priv->display.hdcp.comp_added = true;
mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
-   ret = component_add_typed(dev_priv->drm.dev, &i915_hdcp_component_ops,
- I915_COMPONENT_HDCP);
+
+   if (DISPLAY_VER(dev_priv) >= 14)
+   ret = intel_gsc_hdcp_init(dev_priv);
+   else
+   ret = component_add_typed(dev_priv->drm.dev, 
&i915_hdcp_component_ops,
+ I915_COMPONENT_HDCP);
if (ret < 0) {
-   drm_dbg_kms(&dev_priv->drm, "Failed at component add(%d)\n",
+   drm_dbg_kms(&dev_priv->drm, "Failed at fw component add(%d)\n",
ret);
mutex_lock(&dev_priv->display.hdcp.comp_mutex);
dev_priv->display.hdcp.comp_added = false;
@@ -2485,7 +2498,10 @@ void intel_hdcp_component_fini(struct drm_i915_private 
*dev_priv)
dev_priv->display.hdcp.comp_added = false;
mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
 
-   component_del(dev_priv->drm.dev, &i915_hdcp_component_ops);
+   if (DISPLAY_VER(dev_priv) >= 14)
+   intel_gsc_hdcp_fini(dev_priv);
+   else
+   component_del(dev_priv->drm.dev, &i915_hdcp_component_ops);
 }
 
 void intel_hdcp_cleanup(struct intel_connector *connector)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c 
b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
index aea3a1158c75..380ebbabb9ff 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
@@ -3,6 +3,7 @@
  * Copyright 2021, Intel Corporation.
  */
 
+#include 
 #include "i915_drv.h"
 #include "gt/uc/intel_gsc_fw.h"
 #include "gt/uc/intel_gsc_fwif.h"
@@ -16,6 +17,505 @@ struct intel_hdcp_gsc_message {
void *hdcp_cmd;
 };
 
+static int
+gsc_hdcp_initiate_session(struct device *dev, struct hdcp_port_data *data,
+ struct hdcp2_ake_init *ake_data)
+{
+   struct wired_cmd_initiate_hdcp2_session_in session_init_in = { { 0 } };
+   struct wired_cmd_initiate_hdcp2_session_out
+   session_init_out = { { 0 } };
+   struct drm_i915_private *i915;
+   ssize_t byte;
+
+   if (!dev

[Intel-gfx] [PATCH 4/7] drm/i915/hdcp: Refactor HDCP API structures

2022-12-12 Thread Suraj Kandpal

From: Anshuman Gupta 

It requires to move intel specific HDCP API structures to
i915_cp_fw_hdcp_interface.h from driver/misc/mei/hdcp/mei_hdcp.h
so that any content protection fw interfaces can use these
structures.

Cc: Tomas Winkler 
Cc: Rodrigo Vivi 
Cc: Uma Shankar 
Cc: Ankit Nautiyal 
Signed-off-by: Anshuman Gupta 
Signed-off-by: Suraj Kandpal 
---
 .../gpu/drm/i915/display/intel_display_core.h |   2 +-
 drivers/misc/mei/hdcp/mei_hdcp.c  |  44 +--
 drivers/misc/mei/hdcp/mei_hdcp.h  | 355 +-
 include/drm/i915_cp_fw_hdcp_interface.h   | 354 +
 4 files changed, 378 insertions(+), 377 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h 
b/drivers/gpu/drm/i915/display/intel_display_core.h
index a769cc8e2745..0f6d14e55fbb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -15,8 +15,8 @@
 
 #include 
 #include 
+#include 
 
-#include "i915/i915_cp_fw_hdcp_interface.h"
 #include "intel_cdclk.h"
 #include "intel_display.h"
 #include "intel_display_power.h"
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 7ca8b739cd31..51e3edac565d 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -52,7 +52,7 @@ mei_hdcp_initiate_session(struct device *dev, struct 
hdcp_port_data *data,
 
session_init_in.header.api_version = HDCP_API_VERSION;
session_init_in.header.command_id = WIRED_INITIATE_HDCP2_SESSION;
-   session_init_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   session_init_in.header.status = FW_HDCP_STATUS_SUCCESS;
session_init_in.header.buffer_len =
WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN;
 
@@ -75,7 +75,7 @@ mei_hdcp_initiate_session(struct device *dev, struct 
hdcp_port_data *data,
return byte;
}
 
-   if (session_init_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   if (session_init_out.header.status != FW_HDCP_STATUS_SUCCESS) {
dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
WIRED_INITIATE_HDCP2_SESSION,
session_init_out.header.status);
@@ -122,7 +122,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device *dev,
 
verify_rxcert_in.header.api_version = HDCP_API_VERSION;
verify_rxcert_in.header.command_id = WIRED_VERIFY_RECEIVER_CERT;
-   verify_rxcert_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   verify_rxcert_in.header.status = FW_HDCP_STATUS_SUCCESS;
verify_rxcert_in.header.buffer_len =
WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN;
 
@@ -148,7 +148,7 @@ mei_hdcp_verify_receiver_cert_prepare_km(struct device *dev,
return byte;
}
 
-   if (verify_rxcert_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   if (verify_rxcert_out.header.status != FW_HDCP_STATUS_SUCCESS) {
dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
WIRED_VERIFY_RECEIVER_CERT,
verify_rxcert_out.header.status);
@@ -194,7 +194,7 @@ mei_hdcp_verify_hprime(struct device *dev, struct 
hdcp_port_data *data,
 
send_hprime_in.header.api_version = HDCP_API_VERSION;
send_hprime_in.header.command_id = WIRED_AKE_SEND_HPRIME;
-   send_hprime_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   send_hprime_in.header.status = FW_HDCP_STATUS_SUCCESS;
send_hprime_in.header.buffer_len = WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN;
 
send_hprime_in.port.integrated_port_type = data->port_type;
@@ -218,7 +218,7 @@ mei_hdcp_verify_hprime(struct device *dev, struct 
hdcp_port_data *data,
return byte;
}
 
-   if (send_hprime_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   if (send_hprime_out.header.status != FW_HDCP_STATUS_SUCCESS) {
dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
WIRED_AKE_SEND_HPRIME, send_hprime_out.header.status);
return -EIO;
@@ -251,7 +251,7 @@ mei_hdcp_store_pairing_info(struct device *dev, struct 
hdcp_port_data *data,
 
pairing_info_in.header.api_version = HDCP_API_VERSION;
pairing_info_in.header.command_id = WIRED_AKE_SEND_PAIRING_INFO;
-   pairing_info_in.header.status = ME_HDCP_STATUS_SUCCESS;
+   pairing_info_in.header.status = FW_HDCP_STATUS_SUCCESS;
pairing_info_in.header.buffer_len =
WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN;
 
@@ -276,7 +276,7 @@ mei_hdcp_store_pairing_info(struct device *dev, struct 
hdcp_port_data *data,
return byte;
}
 
-   if (pairing_info_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+   if (pairing_info_out.header.status != FW_HDCP_STATUS_SUCCESS) {
dev_dbg(dev, "ME cmd 0x%08X failed. Status: 0x%X\n",

[Intel-gfx] [PATCH 2/7] drm/i915/hdcp: Keep cp fw agonstic naming convention

2022-12-12 Thread Suraj Kandpal

From: Anshuman Gupta 

Change the include/drm/i915_mei_hdcp_interface.h to
include/drm/i915_cp_fw_hdcp_interface.h

Cc: Tomas Winkler 
Cc: Rodrigo Vivi 
Cc: Uma Shankar 
Cc: Ankit Nautiyal 
Signed-off-by: Anshuman Gupta 
Signed-off-by: Suraj Kandpal 
Acked-by: Tomas Winkler 
---
 drivers/gpu/drm/i915/display/intel_display_types.h  | 2 +-
 drivers/misc/mei/hdcp/mei_hdcp.c| 2 +-
 ...915_mei_hdcp_interface.h => i915_cp_fw_hdcp_interface.h} | 6 +++---
 3 files changed, 5 insertions(+), 5 deletions(-)
 rename include/drm/{i915_mei_hdcp_interface.h => i915_cp_fw_hdcp_interface.h} 
(97%)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 32e8b2fc3cc6..52d93e89b4c6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 
 #include "i915_vma.h"
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index e889a8bd7ac8..7e3cd3fd7f7b 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -23,7 +23,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 #include "mei_hdcp.h"
 
diff --git a/include/drm/i915_mei_hdcp_interface.h 
b/include/drm/i915_cp_fw_hdcp_interface.h
similarity index 97%
rename from include/drm/i915_mei_hdcp_interface.h
rename to include/drm/i915_cp_fw_hdcp_interface.h
index f441cbcd95a4..e5dc6b985b2f 100644
--- a/include/drm/i915_mei_hdcp_interface.h
+++ b/include/drm/i915_cp_fw_hdcp_interface.h
@@ -6,8 +6,8 @@
  * Ramalingam C 
  */
 
-#ifndef _I915_MEI_HDCP_INTERFACE_H_
-#define _I915_MEI_HDCP_INTERFACE_H_
+#ifndef _I915_CP_FW_HDCP_INTERFACE_H_
+#define _I915_CP_FW_HDCP_INTERFACE_H_
 
 #include 
 #include 
@@ -181,4 +181,4 @@ struct i915_hdcp_comp_master {
struct mutex mutex;
 };
 
-#endif /* _I915_MEI_HDCP_INTERFACE_H_ */
+#endif /* _I915_CP_FW_HDCP_INTERFACE_H_ */
-- 
2.25.1

[Intel-gfx] [PATCH 0/7] Enable HDCP2.x via GSC CS

2022-12-12 Thread Suraj Kandpal

These patches enable HDCP2.x on machines MTL and above.
>From MTL onwards CSME is spilt into GSC and CSC and now
we use GSC CS instead of MEI to talk to firmware to start
HDCP authentication

Anshuman Gupta (3):
  drm/i915/hdcp: Keep cp fw agonstic naming convention
  drm/i915/hdcp: HDCP2.x Refactoring to agnotic cp f/w
  drm/i915/hdcp: Refactor HDCP API structures

Suraj Kandpal (4):
  drm/i915/gsc: Create GSC request submission mechanism
  drm/i915/hdcp: Fill wired_cmd_in structures at a single place
  drm/i915/mtl: Adding function to send command to GSC CS
  drm/i915/mtl: Add HDCP GSC interface

 drivers/gpu/drm/i915/Makefile |   1 +
 .../gpu/drm/i915/display/intel_display_core.h |   3 +-
 .../drm/i915/display/intel_display_types.h|   2 +-
 drivers/gpu/drm/i915/display/intel_hdcp.c |  94 ++-
 drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 708 +
 drivers/gpu/drm/i915/display/intel_hdcp_gsc.h |  28 +
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h  |   2 +
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c |  62 +-
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h |   3 +
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h   |  42 +
 drivers/misc/mei/hdcp/mei_hdcp.c  | 190 +
 drivers/misc/mei/hdcp/mei_hdcp.h  | 355 +
 include/drm/i915_cp_fw_hdcp_interface.h   | 738 ++
 include/drm/i915_mei_hdcp_interface.h | 184 -
 14 files changed, 1672 insertions(+), 740 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdcp_gsc.h
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h
 create mode 100644 include/drm/i915_cp_fw_hdcp_interface.h
 delete mode 100644 include/drm/i915_mei_hdcp_interface.h

-- 
2.25.1

[Intel-gfx] [PATCH 1/7] drm/i915/gsc: Create GSC request submission mechanism

2022-12-12 Thread Suraj Kandpal

HDCP and PXP will require a common function to allow it to
submit commands to the gsc cs. Also adding the gsc mtl header
that needs to be added on to the existing payloads of HDCP
and PXP.

Cc: Daniele Ceraolo Spurio 
Cc: Alan Previn 
Signed-off-by: Suraj Kandpal
---
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h |  2 +
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c| 62 +++-
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h|  3 +
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h  | 41 +
 4 files changed, 105 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h

diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h 
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 2af1ae3831df..454179884801 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -439,6 +439,8 @@
 #define GSC_FW_LOAD GSC_INSTR(1, 0, 2)
 #define   HECI1_FW_LIMIT_VALID (1 << 31)
 
+#define GSC_HECI_CMD_PKT GSC_INSTR(0, 0, 6)
+
 /*
  * Used to convert any address to canonical form.
  * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
index e73d4440c5e8..f00e88fdb5d2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
@@ -30,6 +30,35 @@ bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc)
return fw_status & GSC_FW_INIT_COMPLETE_BIT;
 }
 
+struct gsc_heci_pkt {
+   u64 addr_in;
+   u32 size_in;
+   u64 addr_out;
+   u32 size_out;
+};
+
+static int emit_gsc_heci_pkt(struct i915_request *rq, struct gsc_heci_pkt *pkt)
+{
+   u32 *cs;
+
+   cs = intel_ring_begin(rq, 8);
+   if (IS_ERR(cs))
+   return PTR_ERR(cs);
+
+   *cs++ = GSC_HECI_CMD_PKT;
+   *cs++ = lower_32_bits(pkt->addr_in);
+   *cs++ = upper_32_bits(pkt->addr_in);
+   *cs++ = pkt->size_in;
+   *cs++ = lower_32_bits(pkt->addr_out);
+   *cs++ = upper_32_bits(pkt->addr_out);
+   *cs++ = pkt->size_out;
+   *cs++ = 0;
+
+   intel_ring_advance(rq, cs);
+
+   return 0;
+}
+
 static int emit_gsc_fw_load(struct i915_request *rq, struct intel_gsc_uc *gsc)
 {
u32 offset = i915_ggtt_offset(gsc->local);
@@ -49,7 +78,12 @@ static int emit_gsc_fw_load(struct i915_request *rq, struct 
intel_gsc_uc *gsc)
return 0;
 }
 
-static int gsc_fw_load(struct intel_gsc_uc *gsc)
+/*
+ * Our submissions to GSC are going to be either a FW load or an heci pkt, but
+ * all the request emission logic is the same so we can use a common func and
+ * just add the correct cmd
+ */
+static int submit_to_gsc_fw(struct intel_gsc_uc *gsc, struct gsc_heci_pkt *pkt)
 {
struct intel_context *ce = gsc->ce;
struct i915_request *rq;
@@ -68,7 +102,11 @@ static int gsc_fw_load(struct intel_gsc_uc *gsc)
goto out_rq;
}
 
-   err = emit_gsc_fw_load(rq, gsc);
+   if (pkt)
+   err = emit_gsc_heci_pkt(rq, pkt);
+   else
+   err = emit_gsc_fw_load(rq, gsc);
+
if (err)
goto out_rq;
 
@@ -89,12 +127,30 @@ static int gsc_fw_load(struct intel_gsc_uc *gsc)
 
if (err)
drm_err(&gsc_uc_to_gt(gsc)->i915->drm,
-   "Request submission for GSC load failed (%d)\n",
+   "Request submission for GSC failed (%d)\n",
err);
 
return err;
 }
 
+static int gsc_fw_load(struct intel_gsc_uc *gsc)
+{
+   return submit_to_gsc_fw(gsc, NULL);
+}
+
+int intel_gsc_fw_heci_send(struct intel_gsc_uc *gsc, u64 addr_in, u32 size_in,
+  u64 addr_out, u32 size_out)
+{
+   struct gsc_heci_pkt pkt = {
+   .addr_in = addr_in,
+   .size_in = size_in,
+   .addr_out = addr_out,
+   .size_out = size_out
+   };
+
+   return submit_to_gsc_fw(gsc, &pkt);
+}
+
 static int gsc_fw_load_prepare(struct intel_gsc_uc *gsc)
 {
struct intel_gt *gt = gsc_uc_to_gt(gsc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h 
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
index 4b5dbb44afb4..4a75c3dec669 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
@@ -12,4 +12,7 @@ struct intel_gsc_uc;
 
 int intel_gsc_uc_fw_upload(struct intel_gsc_uc *gsc);
 bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc);
+int intel_gsc_fw_heci_send(struct intel_gsc_uc *gsc, u64 addr_in, u32 size_in,
+  u64 addr_out, u32 size_out);
+
 #endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h
new file mode 100644
index ..d0d298c47ad5
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fwif.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright ?? 2021 Intel Corporation
+ */
+
+#ifndef _INTEL_GSC_FWIF_H_
+#define

Re: [Intel-gfx] [PATCH v3] drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence

2022-12-12 Thread Ville Syrjälä

On Mon, Dec 12, 2022 at 04:37:53PM +0200, Jani Nikula wrote:
> Starting from ICL, the default for MIPI GPIO sequences seems to be using
> native GPIOs i.e. GPIOs available in the GPU. These native GPIOs reuse
> many pins that quite frankly seem scary to poke based on the VBT
> sequences. We pretty much have to trust that the board is configured
> such that the relevant HPD, PP_CONTROL and GPIO bits aren't used for
> anything else.
> 
> MIPI sequence v4 also adds a flag to fall back to non-native sequences.
> 
> v3:
> - Fix -Wbitwise-conditional-parentheses (kernel test robot )
> 
> v2:
> - Fix HPD pin output set (impacts GPIOs 0 and 5)
> - Fix GPIO data output direction set (impacts GPIOs 4 and 9)
> - Reduce register accesses to single intel_de_rwm()
> 
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6131
> Cc: Ville Syrjälä 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 84 +++-
>  drivers/gpu/drm/i915/i915_reg.h  |  1 +
>  2 files changed, 82 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
> b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> index fce69fa446d5..f19020074ee3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> @@ -41,9 +41,11 @@
>  
>  #include "i915_drv.h"
>  #include "i915_reg.h"
> +#include "intel_de.h"
>  #include "intel_display_types.h"
>  #include "intel_dsi.h"
>  #include "intel_dsi_vbt.h"
> +#include "intel_gmbus_regs.h"
>  #include "vlv_dsi.h"
>  #include "vlv_dsi_regs.h"
>  #include "vlv_sideband.h"
> @@ -377,6 +379,75 @@ static void icl_exec_gpio(struct intel_connector 
> *connector,
>   drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
>  }
>  
> +enum {
> + MIPI_RESET_1 = 0,
> + MIPI_AVDD_EN_1,
> + MIPI_BKLT_EN_1,
> + MIPI_AVEE_EN_1,
> + MIPI_VIO_EN_1,
> + MIPI_RESET_2,
> + MIPI_AVDD_EN_2,
> + MIPI_BKLT_EN_2,
> + MIPI_AVEE_EN_2,
> + MIPI_VIO_EN_2,
> +};
> +
> +static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
> +   int gpio, bool value)
> +{
> + int index;
> +
> + if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 11 && gpio >= 
> MIPI_RESET_2))
> + return;
> +
> + switch (gpio) {
> + case MIPI_RESET_1:
> + case MIPI_RESET_2:
> + index = gpio == MIPI_RESET_1 ? HPD_PORT_A : HPD_PORT_B;
> +
> + /* Disable HPD to set the pin to output, and set output value */
> + intel_de_rmw(dev_priv, SHOTPLUG_CTL_DDI,
> +  SHOTPLUG_CTL_DDI_HPD_ENABLE(index) |
> +  SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index),
> +  value ? SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index) : 
> 0);

This looks like it could race with hpd irq handling/setup. Assuming
one of the pins could be used for DSI and other for eg. HDMI.

> + break;
> + case MIPI_AVDD_EN_1:
> + case MIPI_AVDD_EN_2:
> + index = gpio == MIPI_AVDD_EN_1 ? 0 : 1;
> +
> + intel_de_rmw(dev_priv, PP_CONTROL(index), PANEL_POWER_ON,
> +  value ? PANEL_POWER_ON : 0);
> + break;
> + case MIPI_BKLT_EN_1:
> + case MIPI_BKLT_EN_2:
> + index = gpio == MIPI_AVDD_EN_1 ? 0 : 1;
> +
> + intel_de_rmw(dev_priv, PP_CONTROL(index), EDP_BLC_ENABLE,
> +  value ? EDP_BLC_ENABLE : 0);
> + break;
> + case MIPI_AVEE_EN_1:
> + case MIPI_AVEE_EN_2:
> + index = gpio == MIPI_AVEE_EN_1 ? 1 : 2;
> +
> + intel_de_rmw(dev_priv, GPIO(dev_priv, index),
> +  GPIO_CLOCK_VAL_OUT,
> +  GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT |
> +  GPIO_CLOCK_VAL_MASK | (value ? GPIO_CLOCK_VAL_OUT 
> : 0));
> + break;
> + case MIPI_VIO_EN_1:
> + case MIPI_VIO_EN_2:
> + index = gpio == MIPI_VIO_EN_1 ? 1 : 2;
> +
> + intel_de_rmw(dev_priv, GPIO(dev_priv, index),
> +  GPIO_DATA_VAL_OUT,
> +  GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT |
> +  GPIO_DATA_VAL_MASK | (value ? GPIO_DATA_VAL_OUT : 
> 0));
> + break;
> + default:
> + MISSING_CASE(gpio);
> + }
> +}
> +
>  static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>  {
>   struct drm_device *dev = intel_dsi->base.base.dev;
> @@ -384,8 +455,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
> *intel_dsi, const u8 *data)
>   struct intel_connector *connector = intel_dsi->attached_connector;
>   u8 gpio_source, gpio_index = 0, gpio_number;
>   bool value;
> -
> - drm_dbg_kms(&dev_priv->drm, "\n");
> + bool native = DISPLAY_VER(dev_priv) >= 11;
>  
>   if (connector->panel.vbt.dsi.seq_

Re: [Intel-gfx] [PATCH] drm/i915/display: Enable VDIP Enable VSC whenever GMP DIP enabled

2022-12-12 Thread Ville Syrjälä

On Mon, Dec 12, 2022 at 01:03:25PM +0530, Mitul Golani wrote:
> GMP VDIP gets dropped when enabled without VSC DIP being
> enabled. Enable VSC DIP whenever GMP DIP is enabled
> 
> WA:14015402699
> 
> Signed-off-by: Mitul Golani 
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 5 -
>  drivers/gpu/drm/i915/display/intel_lspcon.c | 2 ++
>  2 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 72cf83a27405..6c36ee26d399 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3275,10 +3275,13 @@ void intel_dp_set_infoframes(struct intel_encoder 
> *encoder,
>  {
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
> + u32 val;
>   u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
>VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
>VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
> - u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
> + if (IS_DISPLAY_VER(dev_priv, 13, 14))
> + dip_enable |= VIDEO_DIP_ENABLE_VSC_HSW;

What kind of garbage are we going to be sending to the sink here?

> + val = intel_de_read(dev_priv, reg) & ~dip_enable;
>  
>   /* TODO: Add DSC case (DIP_ENABLE_PPS) */
>   /* When PSR is enabled, this routine doesn't disable VSC DIP */
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c 
> b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index 9ff1c0b223ad..e7cdc521fbd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -630,6 +630,8 @@ u32 lspcon_infoframes_enabled(struct intel_encoder 
> *encoder,
>   tmp = intel_de_read(dev_priv,
>   
> HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
>   mask = VIDEO_DIP_ENABLE_GMP_HSW;
> + if (IS_DISPLAY_VER(dev_priv, 13, 14))
> + mask |= VIDEO_DIP_ENABLE_VSC_HSW;
>  
>   if (tmp & mask)
>   val |= 
> intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
> -- 
> 2.25.1

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 2/2] drm/i915/guc: Look for a guilty context when an engine reset fails

2022-12-12 Thread Umesh Nerlige Ramappa


On Tue, Nov 29, 2022 at 01:12:53PM -0800, john.c.harri...@intel.com wrote:

From: John Harrison 

Engine resets are supposed to never happen. But in the case when one
does (due to unknwon reasons that normally come down to a missing
w/a), it is useful to get as much information out of the system as
possible. Given that the GuC effectively dies on such a situation, it
is not possible to get a guilty context notification back. So do a
manual search instead. Given that GuC is dead, this is safe because
GuC won't be changing the engine state asynchronously.

Signed-off-by: John Harrison 
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0a42f1807f52c..c82730804a1c4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4751,11 +4751,24 @@ static void reset_fail_worker_func(struct work_struct 
*w)
guc->submission_state.reset_fail_mask = 0;
spin_unlock_irqrestore(&guc->submission_state.lock, flags);

-   if (likely(reset_fail_mask))
+   if (likely(reset_fail_mask)) {
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+
+   /*
+* GuC is toast at this point - it dead loops after sending the 
failed
+* reset notification. So need to manually determine the guilty 
context.
+* Note that it should be safe/reliable to do this here because 
the GuC
+* is toast and will not be scheduling behind the KMD's back.
+*/


Is that defined by the kmd-GuC interface that following a failed reset notification, GuC 
will always dead-loop OR not schedule anything (even on other engines) until KMD takes 
some action? What action should KMD take?


Regards,
Umesh


+   for_each_engine_masked(engine, gt, reset_fail_mask, id)
+   intel_guc_find_hung_context(engine);
+
intel_gt_handle_error(gt, reset_fail_mask,
  I915_ERROR_CAPTURE,
  "GuC failed to reset engine mask=0x%x\n",
  reset_fail_mask);
+   }
}

int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
--
2.37.3

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Allow error capture without a request

2022-12-12 Thread Umesh Nerlige Ramappa


On Tue, Nov 29, 2022 at 01:12:52PM -0800, john.c.harri...@intel.com wrote:

From: John Harrison 

There was a report of error captures occurring without any hung
context being indicated despite the capture being initiated by a 'hung
context notification' from GuC. The problem was not reproducible.
However, it is possible to happen if the context in question has no
active requests. For example, if the hang was in the context switch
itself then the breadcrumb write would have occurred and the KMD would
see an idle context.

In the interests of attempting to provide as much information as
possible about a hang, it seems wise to include the engine info
regardless of whether a request was found or not. As opposed to just
prentending there was no hang at all.

So update the error capture code to always record engine information
if an engine is given. Which means updating record_context() to take a
context instead of a request (which it only ever used to find the
context anyway). And split the request agnostic parts of
intel_engine_coredump_add_request() out into a seaprate function.

Signed-off-by: John Harrison 
---
drivers/gpu/drm/i915/i915_gpu_error.c | 55 +++
1 file changed, 40 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 9d5d5a397b64e..2ed1c84c9fab4 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1370,14 +1370,14 @@ static void engine_record_execlists(struct 
intel_engine_coredump *ee)
}

static bool record_context(struct i915_gem_context_coredump *e,
-  const struct i915_request *rq)
+  struct intel_context *ce)
{
struct i915_gem_context *ctx;
struct task_struct *task;
bool simulated;

rcu_read_lock();
-   ctx = rcu_dereference(rq->context->gem_context);
+   ctx = rcu_dereference(ce->gem_context);
if (ctx && !kref_get_unless_zero(&ctx->ref))
ctx = NULL;
rcu_read_unlock();
@@ -1396,8 +1396,8 @@ static bool record_context(struct 
i915_gem_context_coredump *e,
e->guilty = atomic_read(&ctx->guilty_count);
e->active = atomic_read(&ctx->active_count);

-   e->total_runtime = intel_context_get_total_runtime_ns(rq->context);
-   e->avg_runtime = intel_context_get_avg_runtime_ns(rq->context);
+   e->total_runtime = intel_context_get_total_runtime_ns(ce);
+   e->avg_runtime = intel_context_get_avg_runtime_ns(ce);

simulated = i915_gem_context_no_error_capture(ctx);

@@ -1532,15 +1532,37 @@ intel_engine_coredump_alloc(struct intel_engine_cs 
*engine, gfp_t gfp, u32 dump_
return ee;
}

+static struct intel_engine_capture_vma *
+engine_coredump_add_context(struct intel_engine_coredump *ee,
+   struct intel_context *ce,
+   gfp_t gfp)
+{
+   struct intel_engine_capture_vma *vma = NULL;
+
+   ee->simulated |= record_context(&ee->context, ce);
+   if (ee->simulated)
+   return NULL;
+
+   /*
+* We need to copy these to an anonymous buffer
+* as the simplest method to avoid being overwritten
+* by userspace.
+*/
+   vma = capture_vma(vma, ce->ring->vma, "ring", gfp);
+   vma = capture_vma(vma, ce->state, "HW context", gfp);
+
+   return vma;
+}
+
struct intel_engine_capture_vma *
intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
  struct i915_request *rq,
  gfp_t gfp)
{
-   struct intel_engine_capture_vma *vma = NULL;
+   struct intel_engine_capture_vma *vma;

-   ee->simulated |= record_context(&ee->context, rq);
-   if (ee->simulated)
+   vma = engine_coredump_add_context(ee, rq->context, gfp);
+   if (!vma)
return NULL;

/*
@@ -1550,8 +1572,6 @@ intel_engine_coredump_add_request(struct 
intel_engine_coredump *ee,
 */
vma = capture_vma_snapshot(vma, rq->batch_res, gfp, "batch");
vma = capture_user(vma, rq, gfp);
-   vma = capture_vma(vma, rq->ring->vma, "ring", gfp);
-   vma = capture_vma(vma, rq->context->state, "HW context", gfp);

ee->rq_head = rq->head;
ee->rq_post = rq->postfix;
@@ -1608,8 +1628,11 @@ capture_engine(struct intel_engine_cs *engine,
if (ce) {
intel_engine_clear_hung_context(engine);
rq = intel_context_find_active_request(ce);
-   if (!rq || !i915_request_started(rq))
-   goto no_request_capture;
+   if (rq && !i915_request_started(rq)) {
+   drm_info(&engine->gt->i915->drm, "Got hung context on %s 
with no active request!\n",
+engine->name);
+   rq = NULL;
+   }
} else {
/*
 * Getti

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/vm_bind: Add VM_BIND functionality (rev12)

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915/vm_bind: Add VM_BIND functionality (rev12)
URL   : https://patchwork.freedesktop.org/series/105879/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12497 -> Patchwork_105879v12


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/index.html

Participating hosts (18 -> 19)
--

  Additional (1): fi-pnv-d510 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105879v12:

### IGT changes ###

 Possible regressions 

  * {igt@i915_vm_bind_basic@basic-smem} (NEW):
- fi-rkl-11600:   NOTRUN -> [SKIP][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/fi-rkl-11600/igt@i915_vm_bind_ba...@basic-smem.html
- {fi-ehl-2}: NOTRUN -> [SKIP][2] +2 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/fi-ehl-2/igt@i915_vm_bind_ba...@basic-smem.html
- fi-icl-u2:  NOTRUN -> [SKIP][3] +2 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/fi-icl-u2/igt@i915_vm_bind_ba...@basic-smem.html
- fi-adl-ddr5:NOTRUN -> [SKIP][4]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/fi-adl-ddr5/igt@i915_vm_bind_ba...@basic-smem.html
- fi-rkl-guc: NOTRUN -> [SKIP][5]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/fi-rkl-guc/igt@i915_vm_bind_ba...@basic-smem.html

  * {igt@i915_vm_bind_sanity@basic} (NEW):
- {fi-jsl-1}: NOTRUN -> [SKIP][6] +1 similar issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/fi-jsl-1/igt@i915_vm_bind_san...@basic.html

  
New tests
-

  New tests have been introduced between CI_DRM_12497 and Patchwork_105879v12:

### New IGT tests (8) ###

  * igt@gem_exec3_basic@basic:
- Statuses : 16 skip(s)
- Exec time: [0.0] s

  * igt@gem_exec3_basic@basic@bcs0-smem:
- Statuses : 3 pass(s)
- Exec time: [0.0] s

  * igt@gem_exec3_basic@basic@rcs0-smem:
- Statuses : 3 pass(s)
- Exec time: [0.0] s

  * igt@gem_exec3_basic@basic@vcs0-smem:
- Statuses : 3 pass(s)
- Exec time: [0.0] s

  * igt@gem_exec3_basic@basic@vecs0-smem:
- Statuses : 3 pass(s)
- Exec time: [0.0] s

  * igt@i915_vm_bind_basic@basic-smem:
- Statuses : 19 skip(s)
- Exec time: [0.0] s

  * igt@i915_vm_bind_sanity@basic:
- Statuses : 16 skip(s)
- Exec time: [0.0] s

  * igt@i915_vm_bind_sanity@basic@smem0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_105879v12 that come from known issues:

### IGT changes ###

 Issues hit 

  * {igt@gem_exec3_basic@basic} (NEW):
- fi-bdw-gvtdvm:  NOTRUN -> [SKIP][7] ([fdo#109271]) +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/fi-bdw-gvtdvm/igt@gem_exec3_ba...@basic.html
- fi-pnv-d510:NOTRUN -> [SKIP][8] ([fdo#109271]) +47 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/fi-pnv-d510/igt@gem_exec3_ba...@basic.html

  * {igt@i915_vm_bind_basic@basic-smem} (NEW):
- fi-kbl-7567u:   NOTRUN -> [SKIP][9] ([fdo#109271]) +2 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/fi-kbl-7567u/igt@i915_vm_bind_ba...@basic-smem.html
- fi-snb-2600:NOTRUN -> [SKIP][10] ([fdo#109271]) +2 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/fi-snb-2600/igt@i915_vm_bind_ba...@basic-smem.html
- fi-kbl-8809g:   NOTRUN -> [SKIP][11] ([fdo#109271]) +2 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/fi-kbl-8809g/igt@i915_vm_bind_ba...@basic-smem.html
- fi-elk-e7500:   NOTRUN -> [SKIP][12] ([fdo#109271]) +2 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/fi-elk-e7500/igt@i915_vm_bind_ba...@basic-smem.html
- {fi-jsl-1}: NOTRUN -> [SKIP][13] ([fdo#112080])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/fi-jsl-1/igt@i915_vm_bind_ba...@basic-smem.html
- fi-bsw-kefka:   NOTRUN -> [SKIP][14] ([fdo#109271]) +2 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/fi-bsw-kefka/igt@i915_vm_bind_ba...@basic-smem.html
- fi-cfl-guc: NOTRUN -> [SKIP][15] ([fdo#109271]) +2 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/fi-cfl-guc/igt@i915_vm_bind_ba...@basic-smem.html

  * {igt@i915_vm_bind_sanity@basic} (NEW):
- fi-glk-j4005:   NOTRUN -> [SKIP][16] ([fdo#109271]) +2 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v12/fi-glk-j4005/igt@i915_vm_bind_san...@basic.html
- fi-hsw-4770:

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/vm_bind: Add VM_BIND functionality (rev12)

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915/vm_bind: Add VM_BIND functionality (rev12)
URL   : https://patchwork.freedesktop.org/series/105879/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/vm_bind: Add VM_BIND functionality (rev12)

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915/vm_bind: Add VM_BIND functionality (rev12)
URL   : https://patchwork.freedesktop.org/series/105879/
State : warning

== Summary ==

Error: dim checkpatch failed
c097e45018d9 drm/i915/vm_bind: Expose vm lookup function
b733052df604 drm/i915/vm_bind: Add __i915_sw_fence_await_reservation()
7f93bd081fd8 drm/i915/vm_bind: Expose i915_gem_object_max_page_size()
0914f8b4345a drm/i915/vm_bind: Support partially mapped vma resource
f1e828354170 drm/i915/vm_bind: Add support to create persistent vma
-:61: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#61: FILE: drivers/gpu/drm/i915/i915_vma.c:311:
+   GEM_BUG_ON(!IS_ERR(vma) && i915_vma_compare(vma, vm, view));

-:82: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#82: FILE: drivers/gpu/drm/i915/i915_vma.c:332:
+   GEM_BUG_ON(!kref_read(&vm->ref));

-:127: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#127: FILE: drivers/gpu/drm/i915/i915_vma.h:228:
+   GEM_BUG_ON(view && !(i915_is_ggtt_or_dpt(vm) ||

total: 0 errors, 3 warnings, 0 checks, 107 lines checked
22db08fd1eb2 drm/i915/vm_bind: Implement bind and unbind of object
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
-:83: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#83: 
new file mode 100644

-:466: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#466: FILE: drivers/gpu/drm/i915/gt/intel_gtt.c:182:
+   GEM_BUG_ON(!RB_EMPTY_ROOT(&vm->va.rb_root));

-:587: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#587: FILE: include/uapi/drm/i915_drm.h:539:
+#define DRM_IOCTL_I915_GEM_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + 
DRM_I915_GEM_VM_BIND, struct drm_i915_gem_vm_bind)

-:588: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#588: FILE: include/uapi/drm/i915_drm.h:540:
+#define DRM_IOCTL_I915_GEM_VM_UNBIND   DRM_IOWR(DRM_COMMAND_BASE + 
DRM_I915_GEM_VM_UNBIND, struct drm_i915_gem_vm_unbind)

total: 0 errors, 4 warnings, 0 checks, 609 lines checked
42e1e21f5d3e drm/i915/vm_bind: Support for VM private BOs
ab883e6d8e60 drm/i915/vm_bind: Add support to handle object evictions
788358767027 drm/i915/vm_bind: Support persistent vma activeness tracking
d5c48e91261f drm/i915/vm_bind: Add out fence support
77e59c80cfb5 drm/i915/vm_bind: Abstract out common execbuf functions
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
-:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#30: 
new file mode 100644

-:174: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#174: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c:140:
+   GEM_BUG_ON(err);/* perma-pinned should incr a counter */

-:249: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#249: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c:215:
+   GEM_BUG_ON("Context not found");

-:607: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#607: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c:573:
+   GEM_BUG_ON(!intel_context_is_parent(context));

total: 0 errors, 4 warnings, 0 checks, 754 lines checked
b3f05fab7477 drm/i915/vm_bind: Use common execbuf functions in execbuf path
7456fbb36b68 drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
-:39: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#39: 
new file mode 100644

-:266: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#266: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuf

[Intel-gfx] [PATCH v9 08/23] drm/i915/vm_bind: Add support to handle object evictions

2022-12-12 Thread Niranjana Vishwanathapura

Support eviction by maintaining a list of evicted persistent vmas
for rebinding during next submission. Ensure the list do not
include persistent vmas that are being purged.

v2: Remove unused I915_VMA_PURGED definition.
v3: Properly handle __i915_vma_unbind_async() case.

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 .../drm/i915/gem/i915_gem_vm_bind_object.c|  6 
 drivers/gpu/drm/i915/gt/intel_gtt.c   |  2 ++
 drivers/gpu/drm/i915/gt/intel_gtt.h   |  4 +++
 drivers/gpu/drm/i915/i915_vma.c   | 28 +++
 drivers/gpu/drm/i915/i915_vma.h   | 10 +++
 drivers/gpu/drm/i915/i915_vma_types.h |  8 ++
 6 files changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
index 4f9df4b756d2..dc738677466b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
@@ -86,6 +86,12 @@ static void i915_gem_vm_bind_remove(struct i915_vma *vma, 
bool release_obj)
 {
lockdep_assert_held(&vma->vm->vm_bind_lock);
 
+   spin_lock(&vma->vm->vm_rebind_lock);
+   if (!list_empty(&vma->vm_rebind_link))
+   list_del_init(&vma->vm_rebind_link);
+   i915_vma_set_purged(vma);
+   spin_unlock(&vma->vm->vm_rebind_lock);
+
list_del_init(&vma->vm_bind_link);
list_del_init(&vma->non_priv_vm_bind_link);
i915_vm_bind_it_remove(vma, &vma->vm->va);
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c 
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 7ce0237d664f..4f91857dca46 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -291,6 +291,8 @@ void i915_address_space_init(struct i915_address_space *vm, 
int subclass)
INIT_LIST_HEAD(&vm->vm_bound_list);
mutex_init(&vm->vm_bind_lock);
INIT_LIST_HEAD(&vm->non_priv_vm_bind_list);
+   INIT_LIST_HEAD(&vm->vm_rebind_list);
+   spin_lock_init(&vm->vm_rebind_lock);
 }
 
 void *__px_vaddr(struct drm_i915_gem_object *p)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h 
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index cb87d0e925c7..dbe6792df3e5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -266,6 +266,10 @@ struct i915_address_space {
struct list_head vm_bind_list;
/** @vm_bound_list: List of vm_binding completed */
struct list_head vm_bound_list;
+   /** @vm_rebind_list: list of vmas to be rebinded */
+   struct list_head vm_rebind_list;
+   /** @vm_rebind_lock: protects vm_rebound_list */
+   spinlock_t vm_rebind_lock;
/** @va: tree of persistent vmas */
struct rb_root_cached va;
/** @non_priv_vm_bind_list: list of non-private object mappings */
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 30f0c0aca007..353203bd5685 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -243,6 +243,7 @@ vma_create(struct drm_i915_gem_object *obj,
 
INIT_LIST_HEAD(&vma->vm_bind_link);
INIT_LIST_HEAD(&vma->non_priv_vm_bind_link);
+   INIT_LIST_HEAD(&vma->vm_rebind_link);
return vma;
 
 err_unlock:
@@ -1716,6 +1717,14 @@ static void force_unbind(struct i915_vma *vma)
if (!drm_mm_node_allocated(&vma->node))
return;
 
+   /*
+* Persistent vma should have been purged by now.
+* If not, issue a warning and purge it.
+*/
+   if (GEM_WARN_ON(i915_vma_is_persistent(vma) &&
+   !i915_vma_is_purged(vma)))
+   i915_vma_set_purged(vma);
+
atomic_and(~I915_VMA_PIN_MASK, &vma->flags);
WARN_ON(__i915_vma_unbind(vma));
GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
@@ -2082,6 +2091,16 @@ int __i915_vma_unbind(struct i915_vma *vma)
__i915_vma_evict(vma, false);
 
drm_mm_remove_node(&vma->node); /* pairs with i915_vma_release() */
+
+   if (i915_vma_is_persistent(vma)) {
+   spin_lock(&vma->vm->vm_rebind_lock);
+   if (list_empty(&vma->vm_rebind_link) &&
+   !i915_vma_is_purged(vma))
+   list_add_tail(&vma->vm_rebind_link,
+ &vma->vm->vm_rebind_list);
+   spin_unlock(&vma->vm->vm_rebind_lock);
+   }
+
return 0;
 }
 
@@ -2116,6 +2135,15 @@ static struct dma_fence *__i915_vma_unbind_async(struct 
i915_vma *vma)
 
drm_mm_remove_node(&vma->node); /* pairs with i915_vma_release() */
 
+   if (i915_vma_is_persistent(vma)) {
+   spin_lock(&vma->vm->vm_rebind_lock);
+   if (list_empty(&vma->vm_rebind_link) &&
+   !i915_vma_is_purged(vma))
+   list_add_tail(&vma->vm_rebind_link,
+ &vma->vm->vm_rebi

[Intel-gfx] [PATCH v9 15/23] drm/i915/vm_bind: Expose i915_request_await_bind()

2022-12-12 Thread Niranjana Vishwanathapura

Rename __i915_request_await_bind() as i915_request_await_bind()
and make it non-static as it will be used in execbuf3 ioctl path.

v2: add documentation

Reviewed-by: Matthew Auld 
Reviewed-by: Andi Shyti 
Signed-off-by: Niranjana Vishwanathapura 
---
 drivers/gpu/drm/i915/i915_vma.c |  8 +---
 drivers/gpu/drm/i915/i915_vma.h | 16 
 2 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 7013b2936565..af3eb6ce68b0 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1923,18 +1923,12 @@ void i915_vma_revoke_mmap(struct i915_vma *vma)
list_del(&vma->obj->userfault_link);
 }
 
-static int
-__i915_request_await_bind(struct i915_request *rq, struct i915_vma *vma)
-{
-   return __i915_request_await_exclusive(rq, &vma->active);
-}
-
 static int __i915_vma_move_to_active(struct i915_vma *vma, struct i915_request 
*rq)
 {
int err;
 
/* Wait for the vma to be bound before we start! */
-   err = __i915_request_await_bind(rq, vma);
+   err = i915_request_await_bind(rq, vma);
if (err)
return err;
 
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 1f25e45a6325..d6c05227fb04 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -55,6 +55,22 @@ void i915_vma_unpin_and_release(struct i915_vma **p_vma, 
unsigned int flags);
 #define __EXEC_OBJECT_NO_RESERVE BIT(31)
 #define __EXEC_OBJECT_NO_REQUEST_AWAIT BIT(30)
 
+/**
+ * i915_request_await_bind() - Setup request to wait for a vma bind completion
+ * @rq: the request which should wait
+ * @vma: vma whose binding @rq should wait to complete
+ *
+ * Setup the request @rq to asynchronously wait for @vma bind to complete
+ * before starting execution.
+ *
+ * Returns 0 on success, error code on failure.
+ */
+static inline int
+i915_request_await_bind(struct i915_request *rq, struct i915_vma *vma)
+{
+   return __i915_request_await_exclusive(rq, &vma->active);
+}
+
 int __must_check _i915_vma_move_to_active(struct i915_vma *vma,
  struct i915_request *rq,
  struct dma_fence *fence,
-- 
2.21.0.rc0.32.g243a4c7e27

[Intel-gfx] [PATCH v9 22/23] drm/i915/vm_bind: Properly build persistent map sg table

2022-12-12 Thread Niranjana Vishwanathapura

Properly build the sg table for persistent mapping which can
be partial map of the underlying object. Ensure the sg pages
are properly set for page backed regions. The dump capture
support requires this for page backed regions.

Signed-off-by: Niranjana Vishwanathapura 
---
 drivers/gpu/drm/i915/i915_vma.c | 120 +++-
 1 file changed, 119 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 7f23adcfb253..d092a86123ae 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1328,6 +1328,120 @@ intel_partial_pages(const struct i915_gtt_view *view,
return ERR_PTR(ret);
 }
 
+static unsigned int
+intel_copy_dma_sg(struct sg_table *src_st, struct sg_table *dst_st,
+ u64 offset, u64 length, bool dry_run)
+{
+   struct scatterlist *dst_sg, *src_sg;
+   unsigned int i, len, nents = 0;
+
+   dst_sg = dst_st->sgl;
+   for_each_sgtable_dma_sg(src_st, src_sg, i) {
+   if (sg_dma_len(src_sg) <= offset) {
+   offset -= sg_dma_len(src_sg);
+   continue;
+   }
+
+   nents++;
+   len = min(sg_dma_len(src_sg) - offset, length);
+   if (!dry_run) {
+   sg_dma_address(dst_sg) = sg_dma_address(src_sg) + 
offset;
+   sg_dma_len(dst_sg) = len;
+   dst_sg = sg_next(dst_sg);
+   }
+
+   length -= len;
+   offset = 0;
+   if (!length)
+   break;
+   }
+   WARN_ON_ONCE(length);
+
+   return nents;
+}
+
+static unsigned int
+intel_copy_sg(struct sg_table *src_st, struct sg_table *dst_st,
+ u64 offset, u64 length, bool dry_run)
+{
+   struct scatterlist *dst_sg, *src_sg;
+   unsigned int i, len, nents = 0;
+
+   dst_sg = dst_st->sgl;
+   for_each_sgtable_sg(src_st, src_sg, i) {
+   if (src_sg->length <= offset) {
+   offset -= src_sg->length;
+   continue;
+   }
+
+   nents++;
+   len = min(src_sg->length - offset, length);
+   if (!dry_run) {
+   unsigned long pfn;
+
+   pfn = page_to_pfn(sg_page(src_sg)) + offset / PAGE_SIZE;
+   sg_set_page(dst_sg, pfn_to_page(pfn), len, 0);
+   dst_sg = sg_next(dst_sg);
+   }
+
+   length -= len;
+   offset = 0;
+   if (!length)
+   break;
+   }
+   WARN_ON_ONCE(length);
+
+   return nents;
+}
+
+static noinline struct sg_table *
+intel_persistent_partial_pages(const struct i915_gtt_view *view,
+  struct drm_i915_gem_object *obj)
+{
+   u64 offset = view->partial.offset << PAGE_SHIFT;
+   struct sg_table *st, *obj_st = obj->mm.pages;
+   u64 length = view->partial.size << PAGE_SHIFT;
+   struct scatterlist *sg;
+   unsigned int nents;
+   int ret = -ENOMEM;
+
+   st = kmalloc(sizeof(*st), GFP_KERNEL);
+   if (!st)
+   goto err_st_alloc;
+
+   /* Get required sg_table size */
+   nents = intel_copy_dma_sg(obj_st, st, offset, length, true);
+   if (i915_gem_object_has_struct_page(obj)) {
+   unsigned int pg_nents;
+
+   pg_nents = intel_copy_sg(obj_st, st, offset, length, true);
+   if (nents < pg_nents)
+   nents = pg_nents;
+   }
+
+   ret = sg_alloc_table(st, nents, GFP_KERNEL);
+   if (ret)
+   goto err_sg_alloc;
+
+   /* Build sg_table for specified  section */
+   intel_copy_dma_sg(obj_st, st, offset, length, false);
+   if (i915_gem_object_has_struct_page(obj))
+   intel_copy_sg(obj_st, st, offset, length, false);
+
+   /* Mark last sg */
+   sg = st->sgl;
+   while (sg_next(sg))
+   sg = sg_next(sg);
+   sg_mark_end(sg);
+
+   return st;
+
+err_sg_alloc:
+   kfree(st);
+err_st_alloc:
+   return ERR_PTR(ret);
+}
+
 static int
 __i915_vma_get_pages(struct i915_vma *vma)
 {
@@ -1360,7 +1474,11 @@ __i915_vma_get_pages(struct i915_vma *vma)
break;
 
case I915_GTT_VIEW_PARTIAL:
-   pages = intel_partial_pages(&vma->gtt_view, vma->obj);
+   if (i915_vma_is_persistent(vma))
+   pages = intel_persistent_partial_pages(&vma->gtt_view,
+  vma->obj);
+   else
+   pages = intel_partial_pages(&vma->gtt_view, vma->obj);
break;
}
 
-- 
2.21.0.rc0.32.g243a4c7e27

[Intel-gfx] [PATCH v9 23/23] drm/i915/vm_bind: Support capture of persistent mappings

2022-12-12 Thread Niranjana Vishwanathapura

Support dump capture of persistent mappings upon user request.

Capture of a mapping is requested with the VM_BIND ioctl and
processed during the GPU error handling, thus not adding any
additional latency to the submission path.

A list of persistent vmas requiring capture is maintained
instead of a list of vma resources. This allows for no
additional handling around eviction.

v2: enable with CONFIG_DRM_I915_CAPTURE_ERROR, remove gfp
overwrite, add kernel-doc and expand commit message

Signed-off-by: Brian Welty 
Signed-off-by: Niranjana Vishwanathapura 
---
 .../gpu/drm/i915/gem/i915_gem_vm_bind_object.c | 13 +
 drivers/gpu/drm/i915/gt/intel_gtt.c|  5 +
 drivers/gpu/drm/i915/gt/intel_gtt.h|  7 +++
 drivers/gpu/drm/i915/i915_gpu_error.c  | 18 +-
 drivers/gpu/drm/i915/i915_vma.c|  4 
 drivers/gpu/drm/i915/i915_vma_types.h  |  4 
 include/uapi/drm/i915_drm.h|  9 +++--
 7 files changed, 57 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
index 78e7c0642c5f..562a67a988f2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
@@ -88,6 +88,12 @@ static void i915_gem_vm_bind_remove(struct i915_vma *vma, 
bool release_obj)
 {
lockdep_assert_held(&vma->vm->vm_bind_lock);
 
+#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
+   mutex_lock(&vma->vm->vm_capture_lock);
+   if (!list_empty(&vma->vm_capture_link))
+   list_del_init(&vma->vm_capture_link);
+   mutex_unlock(&vma->vm->vm_capture_lock);
+#endif
spin_lock(&vma->vm->vm_rebind_lock);
if (!list_empty(&vma->vm_rebind_link))
list_del_init(&vma->vm_rebind_link);
@@ -357,6 +363,13 @@ static int i915_gem_vm_bind_obj(struct i915_address_space 
*vm,
continue;
}
 
+#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
+   if (va->flags & I915_GEM_VM_BIND_CAPTURE) {
+   mutex_lock(&vm->vm_capture_lock);
+   list_add_tail(&vma->vm_capture_link, 
&vm->vm_capture_list);
+   mutex_unlock(&vm->vm_capture_lock);
+   }
+#endif
list_add_tail(&vma->vm_bind_link, &vm->vm_bound_list);
i915_vm_bind_it_insert(vma, &vm->va);
if (!obj->priv_root)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c 
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 2e4c9fabf3b8..103ca55222be 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -297,6 +297,11 @@ void i915_address_space_init(struct i915_address_space 
*vm, int subclass)
spin_lock_init(&vm->vm_rebind_lock);
spin_lock_init(&vm->userptr_invalidated_lock);
INIT_LIST_HEAD(&vm->userptr_invalidated_list);
+
+#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
+   INIT_LIST_HEAD(&vm->vm_capture_list);
+   mutex_init(&vm->vm_capture_lock);
+#endif
 }
 
 void *__px_vaddr(struct drm_i915_gem_object *p)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h 
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 620b4e020a9f..7f69e1d4fb5e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -281,6 +281,13 @@ struct i915_address_space {
/** @root_obj: root object for dma-resv sharing by private objects */
struct drm_i915_gem_object *root_obj;
 
+#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
+   /* @vm_capture_list: list of vm captures */
+   struct list_head vm_capture_list;
+   /* @vm_capture_lock: protects vm_capture_list */
+   struct mutex vm_capture_lock;
+#endif
+
/* Global GTT */
bool is_ggtt:1;
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 9d5d5a397b64..76b2834ce958 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1460,6 +1460,22 @@ capture_vma(struct intel_engine_capture_vma *next,
return next;
 }
 
+static struct intel_engine_capture_vma *
+capture_user_vm(struct intel_engine_capture_vma *capture,
+   struct i915_address_space *vm, gfp_t gfp)
+{
+   struct i915_vma *vma;
+
+   mutex_lock(&vm->vm_capture_lock);
+   /* vma->resource must be valid here as persistent vmas are bound */
+   list_for_each_entry(vma, &vm->vm_capture_list, vm_capture_link)
+   capture = capture_vma_snapshot(capture, vma->resource,
+  gfp, "user");
+   mutex_unlock(&vm->vm_capture_lock);
+
+   return capture;
+}
+
 static struct intel_engine_capture_vma *
 capture_user(struct intel_engine_capture_vma *capture,
 const struct i915_request *rq,
@@ -1471,7 +1487,7 @@ capture_user(struct intel_engine_capture_vma *cap

[Intel-gfx] [PATCH v9 18/23] drm/i915/vm_bind: Limit vm_bind mode to non-recoverable contexts

2022-12-12 Thread Niranjana Vishwanathapura

Only support vm_bind mode with non-recoverable contexts.
With new vm_bind mode with eb3 submission path, we need not
support older recoverable contexts.

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index fb4d2dab5053..9809c58316c2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1617,6 +1617,12 @@ i915_gem_create_context(struct drm_i915_private *i915,
INIT_LIST_HEAD(&ctx->stale.engines);
 
if (pc->vm) {
+   /* Only non-recoverable contexts are allowed in vm_bind mode */
+   if (i915_gem_vm_is_vm_bind_mode(pc->vm) &&
+   (pc->user_flags & BIT(UCONTEXT_RECOVERABLE))) {
+   err = -EINVAL;
+   goto err_ctx;
+   }
vm = i915_vm_get(pc->vm);
} else if (HAS_FULL_PPGTT(i915)) {
struct i915_ppgtt *ppgtt;
-- 
2.21.0.rc0.32.g243a4c7e27

[Intel-gfx] [PATCH v9 17/23] drm/i915/vm_bind: userptr dma-resv changes

2022-12-12 Thread Niranjana Vishwanathapura

For persistent (vm_bind) vmas of userptr BOs, handle the user
page pinning by using the i915_gem_object_userptr_submit_init()
/done() functions

v2: Do not double add vma to vm->userptr_invalidated_list
v3: Initialize vma->userptr_invalidated_link

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 .../gpu/drm/i915/gem/i915_gem_execbuffer3.c   | 84 ++-
 drivers/gpu/drm/i915/gem/i915_gem_userptr.c   | 19 +
 .../drm/i915/gem/i915_gem_vm_bind_object.c| 15 
 drivers/gpu/drm/i915/gt/intel_gtt.c   |  2 +
 drivers/gpu/drm/i915/gt/intel_gtt.h   |  4 +
 drivers/gpu/drm/i915/i915_vma.c   |  1 +
 drivers/gpu/drm/i915/i915_vma_types.h |  2 +
 7 files changed, 125 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
index 913b1f8bda9f..a1aee477e2df 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
@@ -20,6 +20,7 @@
 #include "i915_gem_vm_bind.h"
 #include "i915_trace.h"
 
+#define __EXEC3_USERPTR_USED   BIT_ULL(34)
 #define __EXEC3_HAS_PINBIT_ULL(33)
 #define __EXEC3_ENGINE_PINNED  BIT_ULL(32)
 #define __EXEC3_INTERNAL_FLAGS (~0ull << 32)
@@ -144,7 +145,22 @@ static void eb_scoop_unbound_vma_all(struct 
i915_address_space *vm)
 {
struct i915_vma *vma, *vn;
 
-   /**
+#ifdef CONFIG_MMU_NOTIFIER
+   /*
+* Move all invalidated userptr vmas back into vm_bind_list so that
+* they are looked up and revalidated.
+*/
+   spin_lock(&vm->userptr_invalidated_lock);
+   list_for_each_entry_safe(vma, vn, &vm->userptr_invalidated_list,
+userptr_invalidated_link) {
+   list_del_init(&vma->userptr_invalidated_link);
+   if (!list_empty(&vma->vm_bind_link))
+   list_move_tail(&vma->vm_bind_link, &vm->vm_bind_list);
+   }
+   spin_unlock(&vm->userptr_invalidated_lock);
+#endif
+
+   /*
 * Move all unbound vmas back into vm_bind_list so that they are
 * revalidated.
 */
@@ -157,10 +173,47 @@ static void eb_scoop_unbound_vma_all(struct 
i915_address_space *vm)
spin_unlock(&vm->vm_rebind_lock);
 }
 
+static int eb_lookup_persistent_userptr_vmas(struct i915_execbuffer *eb)
+{
+   struct i915_address_space *vm = eb->context->vm;
+   struct i915_vma *last_vma = NULL;
+   struct i915_vma *vma;
+   int err;
+
+   lockdep_assert_held(&vm->vm_bind_lock);
+
+   list_for_each_entry(vma, &vm->vm_bind_list, vm_bind_link) {
+   if (!i915_gem_object_is_userptr(vma->obj))
+   continue;
+
+   err = i915_gem_object_userptr_submit_init(vma->obj);
+   if (err)
+   return err;
+
+   /*
+* The above submit_init() call does the object unbind and
+* hence adds vma into vm_rebind_list. Remove it from that
+* list as it is already scooped for revalidation.
+*/
+   spin_lock(&vm->vm_rebind_lock);
+   if (!list_empty(&vma->vm_rebind_link))
+   list_del_init(&vma->vm_rebind_link);
+   spin_unlock(&vm->vm_rebind_lock);
+
+   last_vma = vma;
+   }
+
+   if (last_vma)
+   eb->args->flags |= __EXEC3_USERPTR_USED;
+
+   return 0;
+}
+
 static int eb_lookup_vma_all(struct i915_execbuffer *eb)
 {
struct i915_vma *vma;
unsigned int i;
+   int err = 0;
 
for (i = 0; i < eb->num_batches; i++) {
vma = eb_find_vma(eb->context->vm, eb->batch_addresses[i]);
@@ -172,6 +225,10 @@ static int eb_lookup_vma_all(struct i915_execbuffer *eb)
 
eb_scoop_unbound_vma_all(eb->context->vm);
 
+   err = eb_lookup_persistent_userptr_vmas(eb);
+   if (err)
+   return err;
+
return 0;
 }
 
@@ -344,6 +401,29 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
}
}
 
+#ifdef CONFIG_MMU_NOTIFIER
+   /* Check for further userptr invalidations */
+   spin_lock(&vm->userptr_invalidated_lock);
+   if (!list_empty(&vm->userptr_invalidated_list))
+   err = -EAGAIN;
+   spin_unlock(&vm->userptr_invalidated_lock);
+
+   if (!err && (eb->args->flags & __EXEC3_USERPTR_USED)) {
+   read_lock(&eb->i915->mm.notifier_lock);
+   list_for_each_entry(vma, &vm->vm_bind_list, vm_bind_link) {
+   if (!i915_gem_object_is_userptr(vma->obj))
+   continue;
+
+   err = i915_gem_object_userptr_submit_done(vma->obj);
+   if (err)
+   break;
+   }
+   read_unlock(&eb->i915->mm.notifier_lock

[Intel-gfx] [PATCH v9 19/23] drm/i915/vm_bind: Add uapi for user to enable vm_bind_mode

2022-12-12 Thread Niranjana Vishwanathapura

Add getparam support for VM_BIND capability version.
Add VM creation time flag to enable vm_bind_mode for the VM.

v2: update kernel-doc
v3: create vm->root_obj only upon I915_VM_CREATE_FLAGS_USE_VM_BIND
v4: replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode()

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 25 ++--
 drivers/gpu/drm/i915/gem/i915_gem_context.h |  3 +--
 drivers/gpu/drm/i915/gt/intel_gtt.c |  2 ++
 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/i915_getparam.c|  3 +++
 include/uapi/drm/i915_drm.h | 26 -
 6 files changed, 56 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 9809c58316c2..ba4aca5ff432 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1809,9 +1809,13 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, 
void *data,
if (!HAS_FULL_PPGTT(i915))
return -ENODEV;
 
-   if (args->flags)
+   if (args->flags & I915_VM_CREATE_FLAGS_UNKNOWN)
return -EINVAL;
 
+   if ((args->flags & I915_VM_CREATE_FLAGS_USE_VM_BIND) &&
+   !HAS_VM_BIND(i915))
+   return -EOPNOTSUPP;
+
ppgtt = i915_ppgtt_create(to_gt(i915), 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
@@ -1824,15 +1828,32 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, 
void *data,
goto err_put;
}
 
+   if (args->flags & I915_VM_CREATE_FLAGS_USE_VM_BIND) {
+   struct drm_i915_gem_object *obj;
+
+   obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+   if (IS_ERR(obj)) {
+   err = PTR_ERR(obj);
+   goto err_put;
+   }
+
+   ppgtt->vm.root_obj = obj;
+   }
+
err = xa_alloc(&file_priv->vm_xa, &id, &ppgtt->vm,
   xa_limit_32b, GFP_KERNEL);
if (err)
-   goto err_put;
+   goto err_root_obj_put;
 
GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */
args->vm_id = id;
return 0;
 
+err_root_obj_put:
+   if (ppgtt->vm.root_obj) {
+   i915_gem_object_put(ppgtt->vm.root_obj);
+   ppgtt->vm.root_obj = NULL;
+   }
 err_put:
i915_vm_put(&ppgtt->vm);
return err;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h 
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index e8b41aa8f8c4..b53aef2853cb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -150,8 +150,7 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device 
*dev, void *data,
  */
 static inline bool i915_gem_vm_is_vm_bind_mode(struct i915_address_space *vm)
 {
-   /* No support to enable vm_bind mode yet */
-   return false;
+   return !!vm->root_obj;
 }
 
 struct i915_address_space *
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c 
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 7045b2114df6..2e4c9fabf3b8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -179,6 +179,8 @@ int i915_vm_lock_objects(struct i915_address_space *vm,
 void i915_address_space_fini(struct i915_address_space *vm)
 {
drm_mm_takedown(&vm->mm);
+   if (vm->root_obj)
+   i915_gem_object_put(vm->root_obj);
GEM_BUG_ON(!RB_EMPTY_ROOT(&vm->va.rb_root));
mutex_destroy(&vm->vm_bind_lock);
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7a4e9dc15b69..dff6a76805cc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -967,6 +967,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
   GRAPHICS_VER_FULL(i915) >= IP_VER(12, 
70))
 
+#define HAS_VM_BIND(i915) (GRAPHICS_VER(i915) >= 12)
+
 /* intel_device_info.c */
 static inline struct intel_device_info *
 mkwrite_device_info(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c 
b/drivers/gpu/drm/i915/i915_getparam.c
index 61ef2d9cfa62..20c1bf904a65 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -178,6 +178,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_OA_TIMESTAMP_FREQUENCY:
value = i915_perf_oa_timestamp_frequency(i915);
break;
+   case I915_PARAM_VM_BIND_VERSION:
+   value = HAS_VM_BIND(i915);
+   break;
default:
drm_dbg(&i915->drm, "Unknown parameter %d\n", param->param);
return -EINVAL;
diff

[Intel-gfx] [PATCH v9 12/23] drm/i915/vm_bind: Use common execbuf functions in execbuf path

2022-12-12 Thread Niranjana Vishwanathapura

Update the execbuf path to use common execbuf functions to
reduce code duplication with the newer execbuf3 path.

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
---
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 513 ++
 1 file changed, 39 insertions(+), 474 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 6a7f0227f65f..8b49543f3265 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -28,6 +28,7 @@
 #include "i915_file_private.h"
 #include "i915_gem_clflush.h"
 #include "i915_gem_context.h"
+#include "i915_gem_execbuffer_common.h"
 #include "i915_gem_evict.h"
 #include "i915_gem_ioctls.h"
 #include "i915_reg.h"
@@ -236,13 +237,6 @@ enum {
  * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
  */
 
-struct eb_fence {
-   struct drm_syncobj *syncobj; /* Use with ptr_mask_bits() */
-   struct dma_fence *dma_fence;
-   u64 value;
-   struct dma_fence_chain *chain_fence;
-};
-
 struct i915_execbuffer {
struct drm_i915_private *i915; /** i915 backpointer */
struct drm_file *file; /** per-file lookup tables and limits */
@@ -2452,164 +2446,29 @@ static const enum intel_engine_id user_ring_map[] = {
[I915_EXEC_VEBOX]   = VECS0
 };
 
-static struct i915_request *eb_throttle(struct i915_execbuffer *eb, struct 
intel_context *ce)
-{
-   struct intel_ring *ring = ce->ring;
-   struct intel_timeline *tl = ce->timeline;
-   struct i915_request *rq;
-
-   /*
-* Completely unscientific finger-in-the-air estimates for suitable
-* maximum user request size (to avoid blocking) and then backoff.
-*/
-   if (intel_ring_update_space(ring) >= PAGE_SIZE)
-   return NULL;
-
-   /*
-* Find a request that after waiting upon, there will be at least half
-* the ring available. The hysteresis allows us to compete for the
-* shared ring and should mean that we sleep less often prior to
-* claiming our resources, but not so long that the ring completely
-* drains before we can submit our next request.
-*/
-   list_for_each_entry(rq, &tl->requests, link) {
-   if (rq->ring != ring)
-   continue;
-
-   if (__intel_ring_space(rq->postfix,
-  ring->emit, ring->size) > ring->size / 2)
-   break;
-   }
-   if (&rq->link == &tl->requests)
-   return NULL; /* weird, we will check again later for real */
-
-   return i915_request_get(rq);
-}
-
-static int eb_pin_timeline(struct i915_execbuffer *eb, struct intel_context 
*ce,
-  bool throttle)
-{
-   struct intel_timeline *tl;
-   struct i915_request *rq = NULL;
-
-   /*
-* Take a local wakeref for preparing to dispatch the execbuf as
-* we expect to access the hardware fairly frequently in the
-* process, and require the engine to be kept awake between accesses.
-* Upon dispatch, we acquire another prolonged wakeref that we hold
-* until the timeline is idle, which in turn releases the wakeref
-* taken on the engine, and the parent device.
-*/
-   tl = intel_context_timeline_lock(ce);
-   if (IS_ERR(tl))
-   return PTR_ERR(tl);
-
-   intel_context_enter(ce);
-   if (throttle)
-   rq = eb_throttle(eb, ce);
-   intel_context_timeline_unlock(tl);
-
-   if (rq) {
-   bool nonblock = eb->file->filp->f_flags & O_NONBLOCK;
-   long timeout = nonblock ? 0 : MAX_SCHEDULE_TIMEOUT;
-
-   if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
- timeout) < 0) {
-   i915_request_put(rq);
-
-   /*
-* Error path, cannot use intel_context_timeline_lock as
-* that is user interruptable and this clean up step
-* must be done.
-*/
-   mutex_lock(&ce->timeline->mutex);
-   intel_context_exit(ce);
-   mutex_unlock(&ce->timeline->mutex);
-
-   if (nonblock)
-   return -EWOULDBLOCK;
-   else
-   return -EINTR;
-   }
-   i915_request_put(rq);
-   }
-
-   return 0;
-}
-
 static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle)
 {
-   struct intel_context *ce = eb->context, *child;
int err;
-   int i = 0, j = 0;
 
GEM_BUG_ON(eb->args->flags & __EXEC_ENGINE_PINNED);
 
-   if (unlikely(intel_context_is_banned(ce)))
-   return -EIO;
-
-   /*
-* Pinning the contexts may g

[Intel-gfx] [PATCH v9 04/23] drm/i915/vm_bind: Support partially mapped vma resource

2022-12-12 Thread Niranjana Vishwanathapura

As persistent vmas can be partialled mapped to an object,
remove restriction which require vma resource sg table to
be just pointer to object's sg table.

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
---
 drivers/gpu/drm/i915/i915_vma.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 34f0e6c923c2..79b2e19a299f 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -2060,8 +2060,7 @@ static struct dma_fence *__i915_vma_unbind_async(struct 
i915_vma *vma)
if (!drm_mm_node_allocated(&vma->node))
return NULL;
 
-   if (i915_vma_is_pinned(vma) ||
-   &vma->obj->mm.rsgt->table != vma->resource->bi.pages)
+   if (i915_vma_is_pinned(vma))
return ERR_PTR(-EAGAIN);
 
/*
-- 
2.21.0.rc0.32.g243a4c7e27

[Intel-gfx] [PATCH v9 21/23] drm/i915/vm_bind: Async vm_unbind support

2022-12-12 Thread Niranjana Vishwanathapura

Asynchronously unbind the vma upon vm_unbind call.
Fall back to synchronous unbind if backend doesn't support
async unbind or if async unbind fails.

No need for vm_unbind out fence support as i915 will internally
handle all sequencing and user need not try to sequence any
operation with the unbind completion.

v2: use i915_vma_destroy_async in vm_unbind ioctl
v3: Add force_unbind function variants

Reviewed-by: Matthew Auld 
Reviewed-by: Andi Shyti 
Signed-off-by: Niranjana Vishwanathapura 
---
 .../drm/i915/gem/i915_gem_vm_bind_object.c|  2 +-
 drivers/gpu/drm/i915/i915_vma.c   | 49 ++-
 drivers/gpu/drm/i915/i915_vma.h   |  1 +
 include/uapi/drm/i915_drm.h   |  3 +-
 4 files changed, 51 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
index 1cc0b8a4e0e7..78e7c0642c5f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
@@ -210,7 +210,7 @@ static int i915_gem_vm_unbind_vma(struct i915_address_space 
*vm,
 */
obj = vma->obj;
i915_gem_object_lock(obj, NULL);
-   i915_vma_destroy(vma);
+   i915_vma_destroy_async(vma);
i915_gem_object_unlock(obj);
 
i915_gem_object_put(obj);
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index b27735eaaeb9..7f23adcfb253 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -42,6 +42,8 @@
 #include "i915_vma.h"
 #include "i915_vma_resource.h"
 
+static struct dma_fence *__i915_vma_unbind_async(struct i915_vma *vma);
+
 static inline void assert_vma_held_evict(const struct i915_vma *vma)
 {
/*
@@ -1746,7 +1748,7 @@ void i915_vma_reopen(struct i915_vma *vma)
spin_unlock_irq(>->closed_lock);
 }
 
-static void force_unbind(struct i915_vma *vma)
+static void __force_unbind(struct i915_vma *vma, bool async)
 {
if (!drm_mm_node_allocated(&vma->node))
return;
@@ -1760,10 +1762,26 @@ static void force_unbind(struct i915_vma *vma)
i915_vma_set_purged(vma);
 
atomic_and(~I915_VMA_PIN_MASK, &vma->flags);
-   WARN_ON(__i915_vma_unbind(vma));
+   if (async) {
+   struct dma_fence *fence;
+
+   fence = __i915_vma_unbind_async(vma);
+   if (IS_ERR_OR_NULL(fence)) {
+   async = false;
+   } else {
+   dma_resv_add_fence(vma->obj->base.resv, fence,
+  DMA_RESV_USAGE_READ);
+   dma_fence_put(fence);
+   }
+   }
+
+   if (!async)
+   WARN_ON(__i915_vma_unbind(vma));
GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
 }
 
+#define force_unbind(vma)  __force_unbind((vma), false)
+
 static void release_references(struct i915_vma *vma, struct intel_gt *gt,
   bool vm_ddestroy)
 {
@@ -1842,6 +1860,33 @@ void i915_vma_destroy(struct i915_vma *vma)
release_references(vma, gt, vm_ddestroy);
 }
 
+void i915_vma_destroy_async(struct i915_vma *vma)
+{
+   bool vm_ddestroy, async = vma->obj->mm.rsgt;
+   struct intel_gt *gt;
+
+   if (dma_resv_reserve_fences(vma->obj->base.resv, 1))
+   async = false;
+
+   mutex_lock(&vma->vm->mutex);
+   /*
+* Ensure any asynchronous binding is complete while using
+* async unbind as we will be releasing the vma here.
+*/
+   if (async && i915_active_wait(&vma->active))
+   async = false;
+
+   __force_unbind(vma, async);
+   list_del_init(&vma->vm_link);
+   vm_ddestroy = vma->vm_ddestroy;
+   vma->vm_ddestroy = false;
+
+   /* vma->vm may be freed when releasing vma->vm->mutex. */
+   gt = vma->vm->gt;
+   mutex_unlock(&vma->vm->mutex);
+   release_references(vma, gt, vm_ddestroy);
+}
+
 void i915_vma_parked(struct intel_gt *gt)
 {
struct i915_vma *vma, *next;
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index d6c05227fb04..8033f5c96efc 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -319,6 +319,7 @@ void i915_vma_reopen(struct i915_vma *vma);
 
 void i915_vma_destroy_locked(struct i915_vma *vma);
 void i915_vma_destroy(struct i915_vma *vma);
+void i915_vma_destroy_async(struct i915_vma *vma);
 
 #define assert_vma_held(vma) dma_resv_assert_held((vma)->obj->base.resv)
 
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 3f27001a2c8d..b9167f950327 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3970,7 +3970,8 @@ struct drm_i915_gem_vm_bind {
  * any error.
  *
  * VM_BIND/UNBIND ioctl calls executed on different CPU threads concurrently
- * are not ordered.
+ * are not ordered. Furthermore, parts of the VM_UNBIN

[Intel-gfx] [PATCH v9 20/23] drm/i915/vm_bind: Render VM_BIND documentation

2022-12-12 Thread Niranjana Vishwanathapura

Update i915 documentation to include VM_BIND changes
and render all VM_BIND related documentation.

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
---
 Documentation/gpu/i915.rst | 78 --
 1 file changed, 59 insertions(+), 19 deletions(-)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 60ea21734902..01429a8f0d6c 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -283,15 +283,18 @@ An Intel GPU has multiple engines. There are several 
engine types.
 
 The Intel GPU family is a family of integrated GPU's using Unified
 Memory Access. For having the GPU "do work", user space will feed the
-GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`
-or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will
-instruct the GPU to perform work (for example rendering) and that work
-needs memory from which to read and memory to which to write. All memory
-is encapsulated within GEM buffer objects (usually created with the ioctl
-`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU
-to create will also list all GEM buffer objects that the batchbuffer reads
-and/or writes. For implementation details of memory management see
-`GEM BO Management Implementation Details`_.
+GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`,
+`DRM_IOCTL_I915_GEM_EXECBUFFER2_WR` or `DRM_IOCTL_I915_GEM_EXECBUFFER3`.
+Most such batchbuffers will instruct the GPU to perform work (for example
+rendering) and that work needs memory from which to read and memory to
+which to write. All memory is encapsulated within GEM buffer objects
+(usually created with the ioctl `DRM_IOCTL_I915_GEM_CREATE`). In vm_bind mode
+(see `VM_BIND mode`_), the batch buffer and all the GEM buffer objects that
+it reads and/or writes should be bound with vm_bind ioctl before submitting
+the batch buffer to GPU. In legacy (non-VM_BIND) mode, an ioctl providing a
+batchbuffer for the GPU to create will also list all GEM buffer objects that
+the batchbuffer reads and/or writes. For implementation details of memory
+management see `GEM BO Management Implementation Details`_.
 
 The i915 driver allows user space to create a context via the ioctl
 `DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit
@@ -309,8 +312,9 @@ In addition to the ordering guarantees, the kernel will 
restore GPU
 state via HW context when commands are issued to a context, this saves
 user space the need to restore (most of atleast) the GPU state at the
 start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer
-work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1)
-to identify what context to use with the command.
+work can pass that ID (drm_i915_gem_execbuffer3::ctx_id, or in the lower
+bits of drm_i915_gem_execbuffer2::rsvd1) to identify what context to use
+with the command.
 
 The GPU has its own memory management and address space. The kernel
 driver maintains the memory translation table for the GPU. For older
@@ -318,14 +322,14 @@ GPUs (i.e. those before Gen8), there is a single global 
such translation
 table, a global Graphics Translation Table (GTT). For newer generation
 GPUs each context has its own translation table, called Per-Process
 Graphics Translation Table (PPGTT). Of important note, is that although
-PPGTT is named per-process it is actually per context. When user space
-submits a batchbuffer, the kernel walks the list of GEM buffer objects
-used by the batchbuffer and guarantees that not only is the memory of
-each such GEM buffer object resident but it is also present in the
-(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT,
-then it is given an address. Two consequences of this are: the kernel
-needs to edit the batchbuffer submitted to write the correct value of
-the GPU address when a GEM BO is assigned a GPU address and the kernel
+PPGTT is named per-process it is actually per context. In legacy
+(non-vm_bind) mode, when user space submits a batchbuffer, the kernel walks
+the list of GEM buffer objects used by the batchbuffer and guarantees that
+not only is the memory of each such GEM buffer object resident but it is
+also present in the (PP)GTT. If the GEM buffer object is not yet placed in
+the (PP)GTT, then it is given an address. Two consequences of this are: the
+kernel needs to edit the batchbuffer submitted to write the correct value
+of the GPU address when a GEM BO is assigned a GPU address and the kernel
 might evict a different GEM BO from the (PP)GTT to make address room
 for another GEM BO. Consequently, the ioctls submitting a batchbuffer
 for execution also include a list of all locations within buffers that
@@ -407,6 +411,15 @@ objects, which has the goal to make space in gpu virtual 
address spaces.
 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
:internal:
 
+VM_BIND mode
+
+
+.

[Intel-gfx] [PATCH v9 16/23] drm/i915/vm_bind: Handle persistent vmas in execbuf3

2022-12-12 Thread Niranjana Vishwanathapura

Handle persistent (VM_BIND) mappings during the request submission
in the execbuf3 path.

v2: Ensure requests wait for bindings to complete.
v3: Remove short term pinning with PIN_VALIDATE flag.
Individualize fences before adding to dma_resv obj.
v4: Fix bind completion check, use PIN_NOEVICT,
use proper lock while checking if vm_rebind_list is empty.

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 .../gpu/drm/i915/gem/i915_gem_execbuffer3.c   | 215 +-
 1 file changed, 214 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
index 49045858a3e9..913b1f8bda9f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
@@ -3,6 +3,7 @@
  * Copyright © 2022 Intel Corporation
  */
 
+#include 
 #include 
 #include 
 
@@ -19,6 +20,7 @@
 #include "i915_gem_vm_bind.h"
 #include "i915_trace.h"
 
+#define __EXEC3_HAS_PINBIT_ULL(33)
 #define __EXEC3_ENGINE_PINNED  BIT_ULL(32)
 #define __EXEC3_INTERNAL_FLAGS (~0ull << 32)
 
@@ -42,7 +44,9 @@
  * execlist. Hence, no support for implicit sync.
  *
  * The new execbuf3 ioctl only works in VM_BIND mode and the VM_BIND mode only
- * works with execbuf3 ioctl for submission.
+ * works with execbuf3 ioctl for submission. All BOs mapped on that VM (through
+ * VM_BIND call) at the time of execbuf3 call are deemed required for that
+ * submission.
  *
  * The execbuf3 ioctl directly specifies the batch addresses instead of as
  * object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not
@@ -58,6 +62,13 @@
  * So, a lot of code supporting execbuf2 ioctl, like relocations, VA evictions,
  * vma lookup table, implicit sync, vma active reference tracking etc., are not
  * applicable for execbuf3 ioctl.
+ *
+ * During each execbuf submission, request fence is added to all VM_BIND mapped
+ * objects with DMA_RESV_USAGE_BOOKKEEP. The DMA_RESV_USAGE_BOOKKEEP usage will
+ * prevent over sync (See enum dma_resv_usage). Note that DRM_I915_GEM_WAIT and
+ * DRM_I915_GEM_BUSY ioctls do not check for DMA_RESV_USAGE_BOOKKEEP usage and
+ * hence should not be used for end of batch check. Instead, the execbuf3
+ * timeline out fence should be used for end of batch check.
  */
 
 /**
@@ -129,6 +140,23 @@ eb_find_vma(struct i915_address_space *vm, u64 addr)
return i915_gem_vm_bind_lookup_vma(vm, va);
 }
 
+static void eb_scoop_unbound_vma_all(struct i915_address_space *vm)
+{
+   struct i915_vma *vma, *vn;
+
+   /**
+* Move all unbound vmas back into vm_bind_list so that they are
+* revalidated.
+*/
+   spin_lock(&vm->vm_rebind_lock);
+   list_for_each_entry_safe(vma, vn, &vm->vm_rebind_list, vm_rebind_link) {
+   list_del_init(&vma->vm_rebind_link);
+   if (!list_empty(&vma->vm_bind_link))
+   list_move_tail(&vma->vm_bind_link, &vm->vm_bind_list);
+   }
+   spin_unlock(&vm->vm_rebind_lock);
+}
+
 static int eb_lookup_vma_all(struct i915_execbuffer *eb)
 {
struct i915_vma *vma;
@@ -142,14 +170,108 @@ static int eb_lookup_vma_all(struct i915_execbuffer *eb)
eb->batches[i] = vma;
}
 
+   eb_scoop_unbound_vma_all(eb->context->vm);
+
+   return 0;
+}
+
+static int eb_lock_vma_all(struct i915_execbuffer *eb)
+{
+   struct i915_address_space *vm = eb->context->vm;
+   struct i915_vma *vma;
+   int err;
+
+   err = i915_gem_object_lock(eb->context->vm->root_obj, &eb->ww);
+   if (err)
+   return err;
+
+   list_for_each_entry(vma, &vm->non_priv_vm_bind_list,
+   non_priv_vm_bind_link) {
+   err = i915_gem_object_lock(vma->obj, &eb->ww);
+   if (err)
+   return err;
+   }
+
return 0;
 }
 
+static void eb_release_persistent_vma_all(struct i915_execbuffer *eb)
+{
+   struct i915_address_space *vm = eb->context->vm;
+   struct i915_vma *vma, *vn;
+
+   lockdep_assert_held(&vm->vm_bind_lock);
+
+   if (!(eb->args->flags & __EXEC3_HAS_PIN))
+   return;
+
+   assert_object_held(vm->root_obj);
+
+   list_for_each_entry_safe(vma, vn, &vm->vm_bind_list, vm_bind_link)
+   if (!i915_vma_verify_bind_complete(vma))
+   list_move_tail(&vma->vm_bind_link, &vm->vm_bound_list);
+
+   eb->args->flags &= ~__EXEC3_HAS_PIN;
+}
+
 static void eb_release_vma_all(struct i915_execbuffer *eb)
 {
+   eb_release_persistent_vma_all(eb);
eb_unpin_engine(eb);
 }
 
+static int eb_reserve_fence_for_persistent_vma_all(struct i915_execbuffer *eb)
+{
+   struct i915_address_space *vm = eb->context->vm;
+   u64 num_fences = 1;
+   struct i915_vma *vma;
+   int ret;
+
+   /* Reserve enough slots to accommodate composite

[Intel-gfx] [PATCH v9 07/23] drm/i915/vm_bind: Support for VM private BOs

2022-12-12 Thread Niranjana Vishwanathapura

Each VM creates a root_obj and shares it with all of its private objects
to use it as dma_resv object. This has a performance advantage as it
requires a single dma_resv object update for all private BOs vs list of
dma_resv objects update for shared BOs, in the execbuf path.

VM private BOs can be only mapped on specified VM and cannot be dmabuf
exported. Also, they are supported only in vm_bind mode.

v2: Pad struct drm_i915_gem_create_ext_vm_private for 64bit alignment,
add input validity checks.
v3: Create root_obj only for ppgtt.
v4: Fix releasing of obj->priv_root. Do not create vm->root_obj yet.
Allow vm private object creation only in vm_bind mode.
Replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode().

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |  1 +
 drivers/gpu/drm/i915/gem/i915_gem_create.c| 54 ++-
 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c|  6 +++
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c|  4 ++
 drivers/gpu/drm/i915/gem/i915_gem_object.c|  3 ++
 .../gpu/drm/i915/gem/i915_gem_object_types.h  |  6 +++
 .../drm/i915/gem/i915_gem_vm_bind_object.c|  9 
 drivers/gpu/drm/i915/gt/intel_gtt.c   |  1 +
 drivers/gpu/drm/i915/gt/intel_gtt.h   |  4 ++
 drivers/gpu/drm/i915/i915_vma.c   |  1 +
 drivers/gpu/drm/i915/i915_vma_types.h |  2 +
 include/uapi/drm/i915_drm.h   | 33 
 12 files changed, 122 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index b90901ad6866..fb4d2dab5053 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -83,6 +83,7 @@
 
 #include "i915_file_private.h"
 #include "i915_gem_context.h"
+#include "i915_gem_internal.h"
 #include "i915_trace.h"
 #include "i915_user_extensions.h"
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c 
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 86469710bd59..717403c79226 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -11,6 +11,7 @@
 #include "pxp/intel_pxp.h"
 
 #include "i915_drv.h"
+#include "i915_gem_context.h"
 #include "i915_gem_create.h"
 #include "i915_trace.h"
 #include "i915_user_extensions.h"
@@ -251,6 +252,7 @@ struct create_ext {
unsigned int n_placements;
unsigned int placement_mask;
unsigned long flags;
+   u32 vm_id;
 };
 
 static void repr_placements(char *buf, size_t size,
@@ -400,9 +402,32 @@ static int ext_set_protected(struct i915_user_extension 
__user *base, void *data
return 0;
 }
 
+static int ext_set_vm_private(struct i915_user_extension __user *base,
+ void *data)
+{
+   struct drm_i915_gem_create_ext_vm_private ext;
+   struct create_ext *ext_data = data;
+
+   if (copy_from_user(&ext, base, sizeof(ext)))
+   return -EFAULT;
+
+   /* Reserved fields must be 0 */
+   if (ext.rsvd)
+   return -EINVAL;
+
+   /* vm_id 0 is reserved */
+   if (!ext.vm_id)
+   return -ENOENT;
+
+   ext_data->vm_id = ext.vm_id;
+
+   return 0;
+}
+
 static const i915_user_extension_fn create_extensions[] = {
[I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements,
[I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected,
+   [I915_GEM_CREATE_EXT_VM_PRIVATE] = ext_set_vm_private,
 };
 
 /**
@@ -418,6 +443,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void 
*data,
struct drm_i915_private *i915 = to_i915(dev);
struct drm_i915_gem_create_ext *args = data;
struct create_ext ext_data = { .i915 = i915 };
+   struct i915_address_space *vm = NULL;
struct drm_i915_gem_object *obj;
int ret;
 
@@ -431,6 +457,17 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void 
*data,
if (ret)
return ret;
 
+   if (ext_data.vm_id) {
+   vm = i915_gem_vm_lookup(file->driver_priv, ext_data.vm_id);
+   if (unlikely(!vm))
+   return -ENOENT;
+
+   if (!i915_gem_vm_is_vm_bind_mode(vm)) {
+   ret = -EINVAL;
+   goto vm_put;
+   }
+   }
+
if (!ext_data.n_placements) {
ext_data.placements[0] =
intel_memory_region_by_type(i915, INTEL_MEMORY_SYSTEM);
@@ -457,8 +494,21 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void 
*data,
ext_data.placements,
ext_data.n_placements,
ext_data.flags);
-   if (IS_ERR(obj))
-   return PTR_ERR(obj);
+   if (IS_ERR(obj)) {
+   ret = PTR_E

[Intel-gfx] [PATCH v9 06/23] drm/i915/vm_bind: Implement bind and unbind of object

2022-12-12 Thread Niranjana Vishwanathapura

Add uapi and implement support for bind and unbind of an
object at the specified GPU virtual addresses.

The vm_bind mode is not supported in legacy execbuf2 ioctl.
It will be supported only in the newer execbuf3 ioctl.

v2: On older platforms ctx->vm is not set, check for it.
In vm_bind call, add vma to vm_bind_list.
Add more input validity checks.
Update some documentation.
v3: In vm_bind call, add vma to vm_bound_list as user can
request a fence and pass to execbuf3 as input fence.
Remove short term pinning with PIN_VALIDATE flag.
v4: Replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode().
v5: Ensure all reserved fields are 0, use PIN_NOEVICT.
v6: Add reserved fields to drm_i915_gem_vm_bind.

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Prathap Kumar Valsan 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/gem/i915_gem_context.h   |  15 +
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c|   5 +
 drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h   |  26 ++
 .../drm/i915/gem/i915_gem_vm_bind_object.c| 330 ++
 drivers/gpu/drm/i915/gt/intel_gtt.c   |  10 +
 drivers/gpu/drm/i915/gt/intel_gtt.h   |   9 +
 drivers/gpu/drm/i915/i915_driver.c|   3 +
 drivers/gpu/drm/i915/i915_vma.c   |   1 +
 drivers/gpu/drm/i915/i915_vma_types.h |  14 +
 include/uapi/drm/i915_drm.h   | 105 ++
 11 files changed, 519 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
 create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index dfa211451a1d..0bd7de1883fb 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -168,6 +168,7 @@ gem-y += \
gem/i915_gem_ttm_move.o \
gem/i915_gem_ttm_pm.o \
gem/i915_gem_userptr.o \
+   gem/i915_gem_vm_bind_object.o \
gem/i915_gem_wait.o \
gem/i915_gemfs.o
 i915-y += \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h 
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 899fa8f1e0fe..e8b41aa8f8c4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -139,6 +139,21 @@ int i915_gem_context_setparam_ioctl(struct drm_device 
*dev, void *data,
 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
   struct drm_file *file);
 
+/**
+ * i915_gem_vm_is_vm_bind_mode() - Check if address space is in vm_bind mode
+ * @vm: the address space
+ *
+ * Returns:
+ * true: @vm is in vm_bind mode; allows only vm_bind method of binding.
+ * false: @vm is not in vm_bind mode; allows only legacy execbuff method
+ *of binding.
+ */
+static inline bool i915_gem_vm_is_vm_bind_mode(struct i915_address_space *vm)
+{
+   /* No support to enable vm_bind mode yet */
+   return false;
+}
+
 struct i915_address_space *
 i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id);
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 192bb3f10733..6456f15448bd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -785,6 +785,11 @@ static int eb_select_context(struct i915_execbuffer *eb)
if (unlikely(IS_ERR(ctx)))
return PTR_ERR(ctx);
 
+   if (ctx->vm && i915_gem_vm_is_vm_bind_mode(ctx->vm)) {
+   i915_gem_context_put(ctx);
+   return -EOPNOTSUPP;
+   }
+
eb->gem_context = ctx;
if (i915_gem_context_has_full_ppgtt(ctx))
eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
new file mode 100644
index ..36262a6357b5
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __I915_GEM_VM_BIND_H
+#define __I915_GEM_VM_BIND_H
+
+#include 
+
+struct drm_device;
+struct drm_file;
+struct i915_address_space;
+struct i915_vma;
+
+struct i915_vma *
+i915_gem_vm_bind_lookup_vma(struct i915_address_space *vm, u64 va);
+
+int i915_gem_vm_bind_ioctl(struct drm_device *dev, void *data,
+  struct drm_file *file);
+int i915_gem_vm_unbind_ioctl(struct drm_device *dev, void *data,
+struct drm_file *file);
+
+void i915_gem_vm_unbind_all(struct i915_address_space *vm);
+
+#endif /* __I915_GEM_VM_BIND_H */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
new file mode 100644
index ..5064aba9ab87
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
@

[Intel-gfx] [PATCH v9 14/23] drm/i915/vm_bind: Update i915_vma_verify_bind_complete()

2022-12-12 Thread Niranjana Vishwanathapura

Ensure i915_vma_verify_bind_complete() handles case where bind
is not initiated. Also make it non static, add documentation
and move it out of CONFIG_DRM_I915_DEBUG_GEM.

v2: Fix fence leak

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/i915_vma.c | 22 --
 drivers/gpu/drm/i915/i915_vma.h |  1 +
 2 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 6970e1022fee..7013b2936565 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -441,12 +441,25 @@ int i915_vma_sync(struct i915_vma *vma)
return i915_vm_sync(vma->vm);
 }
 
-#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
-static int i915_vma_verify_bind_complete(struct i915_vma *vma)
+/**
+ * i915_vma_verify_bind_complete() - Check for the bind completion of the vma
+ * @vma: vma to check for bind completion
+ *
+ * As the fence reference is obtained under RCU, no locking is required by
+ * the caller.
+ *
+ * Returns: 0 if the vma bind is completed. Error code otherwise.
+ */
+int i915_vma_verify_bind_complete(struct i915_vma *vma)
 {
-   struct dma_fence *fence = i915_active_fence_get(&vma->active.excl);
+   struct dma_fence *fence;
int err;
 
+   /* Ensure vma bind is initiated */
+   if (!i915_vma_is_bound(vma, I915_VMA_BIND_MASK))
+   return -EINVAL;
+
+   fence = i915_active_fence_get(&vma->active.excl);
if (!fence)
return 0;
 
@@ -459,9 +472,6 @@ static int i915_vma_verify_bind_complete(struct i915_vma 
*vma)
 
return err;
 }
-#else
-#define i915_vma_verify_bind_complete(_vma) 0
-#endif
 
 I915_SELFTEST_EXPORT void
 i915_vma_resource_init_from_vma(struct i915_vma_resource *vma_res,
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index de1756e4f638..1f25e45a6325 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -487,6 +487,7 @@ void i915_vma_make_purgeable(struct i915_vma *vma);
 
 int i915_vma_wait_for_bind(struct i915_vma *vma);
 int i915_vma_sync(struct i915_vma *vma);
+int i915_vma_verify_bind_complete(struct i915_vma *vma);
 
 /**
  * i915_vma_get_current_resource - Get the current resource of the vma
-- 
2.21.0.rc0.32.g243a4c7e27

[Intel-gfx] [PATCH v9 11/23] drm/i915/vm_bind: Abstract out common execbuf functions

2022-12-12 Thread Niranjana Vishwanathapura

The new execbuf3 ioctl path and the legacy execbuf ioctl
paths have many common functionalities.
Abstract out the common execbuf functionalities into a
separate file where possible, thus allowing code sharing.

v2: Use drm_dbg instead of DRM_DEBUG

Reviewed-by: Andi Shyti 
Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
---
 drivers/gpu/drm/i915/Makefile |   1 +
 .../drm/i915/gem/i915_gem_execbuffer_common.c | 671 ++
 .../drm/i915/gem/i915_gem_execbuffer_common.h |  76 ++
 3 files changed, 748 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c
 create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0bd7de1883fb..bf3aa6e97ddd 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -150,6 +150,7 @@ gem-y += \
gem/i915_gem_create.o \
gem/i915_gem_dmabuf.o \
gem/i915_gem_domain.o \
+   gem/i915_gem_execbuffer_common.o \
gem/i915_gem_execbuffer.o \
gem/i915_gem_internal.o \
gem/i915_gem_object.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c
new file mode 100644
index ..fb1364f08a61
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c
@@ -0,0 +1,671 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include 
+
+#include 
+
+#include "gt/intel_context.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_gt_pm.h"
+#include "gt/intel_ring.h"
+
+#include "i915_drv.h"
+#include "i915_gem_execbuffer_common.h"
+
+#define __EXEC_COMMON_FENCE_WAIT   BIT(0)
+#define __EXEC_COMMON_FENCE_SIGNAL BIT(1)
+
+static struct i915_request *eb_throttle(struct intel_context *ce)
+{
+   struct intel_ring *ring = ce->ring;
+   struct intel_timeline *tl = ce->timeline;
+   struct i915_request *rq;
+
+   /*
+* Completely unscientific finger-in-the-air estimates for suitable
+* maximum user request size (to avoid blocking) and then backoff.
+*/
+   if (intel_ring_update_space(ring) >= PAGE_SIZE)
+   return NULL;
+
+   /*
+* Find a request that after waiting upon, there will be at least half
+* the ring available. The hysteresis allows us to compete for the
+* shared ring and should mean that we sleep less often prior to
+* claiming our resources, but not so long that the ring completely
+* drains before we can submit our next request.
+*/
+   list_for_each_entry(rq, &tl->requests, link) {
+   if (rq->ring != ring)
+   continue;
+
+   if (__intel_ring_space(rq->postfix,
+  ring->emit, ring->size) > ring->size / 2)
+   break;
+   }
+   if (&rq->link == &tl->requests)
+   return NULL; /* weird, we will check again later for real */
+
+   return i915_request_get(rq);
+}
+
+static int eb_pin_timeline(struct intel_context *ce, bool throttle,
+  bool nonblock)
+{
+   struct intel_timeline *tl;
+   struct i915_request *rq = NULL;
+
+   /*
+* Take a local wakeref for preparing to dispatch the execbuf as
+* we expect to access the hardware fairly frequently in the
+* process, and require the engine to be kept awake between accesses.
+* Upon dispatch, we acquire another prolonged wakeref that we hold
+* until the timeline is idle, which in turn releases the wakeref
+* taken on the engine, and the parent device.
+*/
+   tl = intel_context_timeline_lock(ce);
+   if (IS_ERR(tl))
+   return PTR_ERR(tl);
+
+   intel_context_enter(ce);
+   if (throttle)
+   rq = eb_throttle(ce);
+   intel_context_timeline_unlock(tl);
+
+   if (rq) {
+   long timeout = nonblock ? 0 : MAX_SCHEDULE_TIMEOUT;
+
+   if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
+ timeout) < 0) {
+   i915_request_put(rq);
+
+   /*
+* Error path, cannot use intel_context_timeline_lock as
+* that is user interruptable and this clean up step
+* must be done.
+*/
+   mutex_lock(&ce->timeline->mutex);
+   intel_context_exit(ce);
+   mutex_unlock(&ce->timeline->mutex);
+
+   if (nonblock)
+   return -EWOULDBLOCK;
+   else
+   return -EINTR;
+   }
+   i915_request_put(rq);
+   }
+
+   return 0;
+}
+
+/**
+ * i915_eb_pin_engine() - Pin the

[Intel-gfx] [PATCH v9 13/23] drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl

2022-12-12 Thread Niranjana Vishwanathapura

Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only
works in vm_bind mode. The vm_bind mode only works with
this new execbuf3 ioctl.

The new execbuf3 ioctl will not have any list of objects to validate
bind as all required objects binding would have been requested by the
userspace before submitting the execbuf3.

Legacy features like relocations etc are not supported by execbuf3.

v2: Add more input validity checks.
v3: batch_address is a VA (not an array) if num_batches=1,
minor cleanup
v4: replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode()
v5: Remove unwanted krealloc() and address other review comments.

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/Makefile |   1 +
 .../gpu/drm/i915/gem/i915_gem_execbuffer3.c   | 579 ++
 drivers/gpu/drm/i915/gem/i915_gem_ioctls.h|   2 +
 drivers/gpu/drm/i915/i915_driver.c|   1 +
 include/uapi/drm/i915_drm.h   |  61 ++
 5 files changed, 644 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index bf3aa6e97ddd..2aa63287f3a9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -152,6 +152,7 @@ gem-y += \
gem/i915_gem_domain.o \
gem/i915_gem_execbuffer_common.o \
gem/i915_gem_execbuffer.o \
+   gem/i915_gem_execbuffer3.o \
gem/i915_gem_internal.o \
gem/i915_gem_object.o \
gem/i915_gem_lmem.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
new file mode 100644
index ..49045858a3e9
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include 
+#include 
+
+#include 
+
+#include "gt/intel_context.h"
+#include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt.h"
+
+#include "i915_drv.h"
+#include "i915_gem_context.h"
+#include "i915_gem_execbuffer_common.h"
+#include "i915_gem_ioctls.h"
+#include "i915_gem_vm_bind.h"
+#include "i915_trace.h"
+
+#define __EXEC3_ENGINE_PINNED  BIT_ULL(32)
+#define __EXEC3_INTERNAL_FLAGS (~0ull << 32)
+
+/* Catch emission of unexpected errors for CI! */
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
+#undef EINVAL
+#define EINVAL ({ \
+   DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \
+   22; \
+})
+#endif
+
+/**
+ * DOC: User command execution in vm_bind mode
+ *
+ * A VM in VM_BIND mode will not support older execbuf mode of binding.
+ * The execbuf ioctl handling in VM_BIND mode differs significantly from the
+ * older execbuf2 ioctl (See struct drm_i915_gem_execbuffer2).
+ * Hence, a new execbuf3 ioctl has been added to support VM_BIND mode. (See
+ * struct drm_i915_gem_execbuffer3). The execbuf3 ioctl will not accept any
+ * execlist. Hence, no support for implicit sync.
+ *
+ * The new execbuf3 ioctl only works in VM_BIND mode and the VM_BIND mode only
+ * works with execbuf3 ioctl for submission.
+ *
+ * The execbuf3 ioctl directly specifies the batch addresses instead of as
+ * object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not
+ * support many of the older features like in/out/submit fences, fence array,
+ * default gem context etc. (See struct drm_i915_gem_execbuffer3).
+ *
+ * In VM_BIND mode, VA allocation is completely managed by the user instead of
+ * the i915 driver. Hence all VA assignment, eviction are not applicable in
+ * VM_BIND mode. Also, for determining object activeness, VM_BIND mode will not
+ * be using the i915_vma active reference tracking. It will instead check the
+ * dma-resv object's fence list for that.
+ *
+ * So, a lot of code supporting execbuf2 ioctl, like relocations, VA evictions,
+ * vma lookup table, implicit sync, vma active reference tracking etc., are not
+ * applicable for execbuf3 ioctl.
+ */
+
+/**
+ * struct i915_execbuffer - execbuf struct for execbuf3
+ * @i915: reference to the i915 instance we run on
+ * @file: drm file reference
+ * @args: execbuf3 ioctl structure
+ * @gt: reference to the gt instance ioctl submitted for
+ * @context: logical state for the request
+ * @gem_context: callers context
+ * @requests: requests to be build
+ * @composite_fence: used for excl fence in dma_resv objects when > 1 BB 
submitted
+ * @ww: i915_gem_ww_ctx instance
+ * @num_batches: number of batches submitted
+ * @batch_addresses: addresses corresponds to the submitted batches
+ * @batches: references to the i915_vmas corresponding to the batches
+ * @fences: array of execbuf fences (See struct eb_fence)
+ * @num_fences: number of fences in @fences array
+ */
+struct i915_execbuffer {
+   struct drm_i915_private *i915;
+   struct drm_file *file;
+   struct drm_i915_gem_execbuffer3 *args;
+
+   str

[Intel-gfx] [PATCH v9 05/23] drm/i915/vm_bind: Add support to create persistent vma

2022-12-12 Thread Niranjana Vishwanathapura

Add i915_vma_instance_persistent() to create persistent vmas.
Persistent vmas will use i915_gtt_view to support partial binding.

vma_lookup is tied to segment of the object instead of section
of VA space. Hence, it do not support aliasing. ie., multiple
mappings (at different VA) point to the same gtt_view of object.
Skip vma_lookup for persistent vmas to support aliasing.

v2: Remove unused I915_VMA_PERSISTENT definition,
update validity check in i915_vma_compare(),
remove unwanted is_persistent check in release_references().

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/i915_vma.c   | 36 +--
 drivers/gpu/drm/i915/i915_vma.h   | 17 -
 drivers/gpu/drm/i915/i915_vma_types.h |  6 +
 3 files changed, 56 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 79b2e19a299f..e43cbb5fa154 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -111,7 +111,8 @@ static void __i915_vma_retire(struct i915_active *ref)
 static struct i915_vma *
 vma_create(struct drm_i915_gem_object *obj,
   struct i915_address_space *vm,
-  const struct i915_gtt_view *view)
+  const struct i915_gtt_view *view,
+  bool skip_lookup_cache)
 {
struct i915_vma *pos = ERR_PTR(-E2BIG);
struct i915_vma *vma;
@@ -198,6 +199,9 @@ vma_create(struct drm_i915_gem_object *obj,
__set_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(vma));
}
 
+   if (skip_lookup_cache)
+   goto skip_rb_insert;
+
rb = NULL;
p = &obj->vma.tree.rb_node;
while (*p) {
@@ -222,6 +226,7 @@ vma_create(struct drm_i915_gem_object *obj,
rb_link_node(&vma->obj_node, rb, p);
rb_insert_color(&vma->obj_node, &obj->vma.tree);
 
+skip_rb_insert:
if (i915_vma_is_ggtt(vma))
/*
 * We put the GGTT vma at the start of the vma-list, followed
@@ -301,7 +306,34 @@ i915_vma_instance(struct drm_i915_gem_object *obj,
 
/* vma_create() will resolve the race if another creates the vma */
if (unlikely(!vma))
-   vma = vma_create(obj, vm, view);
+   vma = vma_create(obj, vm, view, false);
+
+   GEM_BUG_ON(!IS_ERR(vma) && i915_vma_compare(vma, vm, view));
+   return vma;
+}
+
+/**
+ * i915_vma_create_persistent - create a persistent VMA
+ * @obj: parent &struct drm_i915_gem_object to be mapped
+ * @vm: address space in which the mapping is located
+ * @view: additional mapping requirements
+ *
+ * Creates a persistent vma.
+ *
+ * Returns the vma, or an error pointer.
+ */
+struct i915_vma *
+i915_vma_create_persistent(struct drm_i915_gem_object *obj,
+  struct i915_address_space *vm,
+  const struct i915_gtt_view *view)
+{
+   struct i915_vma *vma;
+
+   GEM_BUG_ON(!kref_read(&vm->ref));
+
+   vma = vma_create(obj, vm, view, true);
+   if (!IS_ERR(vma))
+   i915_vma_set_persistent(vma);
 
GEM_BUG_ON(!IS_ERR(vma) && i915_vma_compare(vma, vm, view));
return vma;
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index ed5c9d682a1b..dd9951a41ff3 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -44,6 +44,10 @@ struct i915_vma *
 i915_vma_instance(struct drm_i915_gem_object *obj,
  struct i915_address_space *vm,
  const struct i915_gtt_view *view);
+struct i915_vma *
+i915_vma_create_persistent(struct drm_i915_gem_object *obj,
+  struct i915_address_space *vm,
+  const struct i915_gtt_view *view);
 
 void i915_vma_unpin_and_release(struct i915_vma **p_vma, unsigned int flags);
 #define I915_VMA_RELEASE_MAP BIT(0)
@@ -185,6 +189,16 @@ static inline u32 i915_ggtt_pin_bias(struct i915_vma *vma)
return i915_vm_to_ggtt(vma->vm)->pin_bias;
 }
 
+static inline bool i915_vma_is_persistent(const struct i915_vma *vma)
+{
+   return test_bit(I915_VMA_PERSISTENT_BIT, __i915_vma_flags(vma));
+}
+
+static inline void i915_vma_set_persistent(struct i915_vma *vma)
+{
+   set_bit(I915_VMA_PERSISTENT_BIT, __i915_vma_flags(vma));
+}
+
 static inline struct i915_vma *i915_vma_get(struct i915_vma *vma)
 {
i915_gem_object_get(vma->obj);
@@ -211,7 +225,8 @@ i915_vma_compare(struct i915_vma *vma,
 {
ptrdiff_t cmp;
 
-   GEM_BUG_ON(view && !i915_is_ggtt_or_dpt(vm));
+   GEM_BUG_ON(view && !(i915_is_ggtt_or_dpt(vm) ||
+i915_vma_is_persistent(vma)));
 
cmp = ptrdiff(vma->vm, vm);
if (cmp)
diff --git a/drivers/gpu/drm/i915/i915_vma_types.h 
b/drivers/gpu/drm/i915/i915_vma_types.h
index 77fda2244d16..be1cd76304cb 100644
--- a/drivers/gpu/drm/i915/i915_vma_types.h
+++ b/drivers/gpu/drm/i915/i9

[Intel-gfx] [PATCH v9 10/23] drm/i915/vm_bind: Add out fence support

2022-12-12 Thread Niranjana Vishwanathapura

Add support for handling out fence for vm_bind call.

v2: Reset vma->vm_bind_fence.syncobj to NULL at the end
of vm_bind call.
v3: Remove vm_unbind out fence uapi which is not supported yet.
v4: Return error if I915_TIMELINE_FENCE_WAIT fence flag is set.
Wait for bind to complete iff I915_TIMELINE_FENCE_SIGNAL is
not specified.
v5: Ensure __I915_TIMELINE_FENCE_UNKNOWN_FLAGS are not set.

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h   |  4 +
 .../drm/i915/gem/i915_gem_vm_bind_object.c| 98 ++-
 drivers/gpu/drm/i915/i915_vma.c   |  7 +-
 drivers/gpu/drm/i915/i915_vma_types.h |  7 ++
 include/uapi/drm/i915_drm.h   | 58 ++-
 5 files changed, 165 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
index 36262a6357b5..b70e900e35ab 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h
@@ -8,6 +8,7 @@
 
 #include 
 
+struct dma_fence;
 struct drm_device;
 struct drm_file;
 struct i915_address_space;
@@ -23,4 +24,7 @@ int i915_gem_vm_unbind_ioctl(struct drm_device *dev, void 
*data,
 
 void i915_gem_vm_unbind_all(struct i915_address_space *vm);
 
+void i915_vm_bind_signal_fence(struct i915_vma *vma,
+  struct dma_fence * const fence);
+
 #endif /* __I915_GEM_VM_BIND_H */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
index dc738677466b..fd1d82ce99e6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c
@@ -7,6 +7,8 @@
 
 #include 
 
+#include 
+
 #include "gem/i915_gem_context.h"
 #include "gem/i915_gem_vm_bind.h"
 
@@ -101,6 +103,77 @@ static void i915_gem_vm_bind_remove(struct i915_vma *vma, 
bool release_obj)
i915_gem_object_put(vma->obj);
 }
 
+static int i915_vm_bind_add_fence(struct drm_file *file, struct i915_vma *vma,
+ u32 handle, u64 point)
+{
+   struct drm_syncobj *syncobj;
+
+   syncobj = drm_syncobj_find(file, handle);
+   if (!syncobj) {
+   drm_dbg(&vma->vm->i915->drm,
+   "Invalid syncobj handle provided\n");
+   return -ENOENT;
+   }
+
+   /*
+* For timeline syncobjs we need to preallocate chains for
+* later signaling.
+*/
+   if (point) {
+   vma->vm_bind_fence.chain_fence = dma_fence_chain_alloc();
+   if (!vma->vm_bind_fence.chain_fence) {
+   drm_syncobj_put(syncobj);
+   return -ENOMEM;
+   }
+   } else {
+   vma->vm_bind_fence.chain_fence = NULL;
+   }
+   vma->vm_bind_fence.syncobj = syncobj;
+   vma->vm_bind_fence.value = point;
+
+   return 0;
+}
+
+static void i915_vm_bind_put_fence(struct i915_vma *vma)
+{
+   if (!vma->vm_bind_fence.syncobj)
+   return;
+
+   drm_syncobj_put(vma->vm_bind_fence.syncobj);
+   dma_fence_chain_free(vma->vm_bind_fence.chain_fence);
+   vma->vm_bind_fence.syncobj = NULL;
+}
+
+/**
+ * i915_vm_bind_signal_fence() - Add fence to vm_bind syncobj
+ * @vma: vma mapping requiring signaling
+ * @fence: fence to be added
+ *
+ * Associate specified @fence with the @vma's syncobj to be
+ * signaled after the @fence work completes.
+ */
+void i915_vm_bind_signal_fence(struct i915_vma *vma,
+  struct dma_fence * const fence)
+{
+   struct drm_syncobj *syncobj = vma->vm_bind_fence.syncobj;
+
+   if (!syncobj)
+   return;
+
+   if (vma->vm_bind_fence.chain_fence) {
+   drm_syncobj_add_point(syncobj,
+ vma->vm_bind_fence.chain_fence,
+ fence, vma->vm_bind_fence.value);
+   /*
+* The chain's ownership is transferred to the
+* timeline.
+*/
+   vma->vm_bind_fence.chain_fence = NULL;
+   } else {
+   drm_syncobj_replace_fence(syncobj, fence);
+   }
+}
+
 static int i915_gem_vm_unbind_vma(struct i915_address_space *vm,
  struct drm_i915_gem_vm_unbind *va)
 {
@@ -206,6 +279,11 @@ static int i915_gem_vm_bind_obj(struct i915_address_space 
*vm,
if (!va->length || !IS_ALIGNED(va->start, I915_GTT_PAGE_SIZE))
ret = -EINVAL;
 
+   /* In fences are not supported */
+   if ((va->fence.flags & I915_TIMELINE_FENCE_WAIT) ||
+   (va->fence.flags & __I915_TIMELINE_FENCE_UNKNOWN_FLAGS))
+   ret = -EINVAL;
+
obj = i915_gem_object_lookup(file, va->handle);
if (!obj)
return -ENOENT;
@@ -238,6 +316,13 @@ static int i9

[Intel-gfx] [PATCH v9 09/23] drm/i915/vm_bind: Support persistent vma activeness tracking

2022-12-12 Thread Niranjana Vishwanathapura

Do not use i915_vma activeness tracking for persistent vmas.

As persistent vmas are part of working set for each execbuf
submission on that address space (VM), a persistent vma is
active if the VM active. As vm->root_obj->base.resv will be
updated for each submission on that VM, it correctly
represent whether the VM is active or not.

Add i915_vm_is_active() and i915_vm_sync() functions based
on vm->root_obj->base.resv with DMA_RESV_USAGE_BOOKKEEP
usage. dma-resv fence list will be updated with this usage
during each submission with this VM in the new execbuf3
ioctl path.

Update i915_vma_is_active(), i915_vma_sync() and the
__i915_vma_unbind_async() functions to properly handle
persistent vmas.

v2: Ensure lvalue of dma_resv_wait_timeout() call is long.

Reviewed-by: Andi Shyti 
Signed-off-by: Niranjana Vishwanathapura 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 39 +
 drivers/gpu/drm/i915/i915_gem_gtt.h |  3 +++
 drivers/gpu/drm/i915/i915_vma.c | 28 +
 drivers/gpu/drm/i915/i915_vma.h | 25 +-
 4 files changed, 83 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7bd1861ddbdf..1d8506548d4a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -25,6 +25,45 @@
 #include "i915_trace.h"
 #include "i915_vgpu.h"
 
+/**
+ * i915_vm_sync() - Wait until address space is not in use
+ * @vm: address space
+ *
+ * Waits until all requests using the address space are complete.
+ *
+ * Returns: 0 if success, -ve err code upon failure
+ */
+int i915_vm_sync(struct i915_address_space *vm)
+{
+   long ret;
+
+   /* Wait for all requests under this vm to finish */
+   ret = dma_resv_wait_timeout(vm->root_obj->base.resv,
+   DMA_RESV_USAGE_BOOKKEEP, false,
+   MAX_SCHEDULE_TIMEOUT);
+   if (ret < 0)
+   return ret;
+   else if (ret > 0)
+   return 0;
+   else
+   return -ETIMEDOUT;
+}
+
+/**
+ * i915_vm_is_active() - Check if address space is being used
+ * @vm: address space
+ *
+ * Check if any request using the specified address space is
+ * active.
+ *
+ * Returns: true if address space is active, false otherwise.
+ */
+bool i915_vm_is_active(const struct i915_address_space *vm)
+{
+   return !dma_resv_test_signaled(vm->root_obj->base.resv,
+  DMA_RESV_USAGE_BOOKKEEP);
+}
+
 int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
   struct sg_table *pages)
 {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h 
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 243419783052..e62b52c74586 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -52,4 +52,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
 
 #define PIN_OFFSET_MASKI915_GTT_PAGE_MASK
 
+int i915_vm_sync(struct i915_address_space *vm);
+bool i915_vm_is_active(const struct i915_address_space *vm);
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 353203bd5685..c9527f1fdab9 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -422,6 +422,24 @@ int i915_vma_wait_for_bind(struct i915_vma *vma)
return err;
 }
 
+/**
+ * i915_vma_sync() - Wait for the vma to be idle
+ * @vma: vma to be tested
+ *
+ * Returns 0 on success and error code on failure
+ */
+int i915_vma_sync(struct i915_vma *vma)
+{
+   int ret;
+
+   /* Wait for the asynchronous bindings and pending GPU reads */
+   ret = i915_active_wait(&vma->active);
+   if (ret || !i915_vma_is_persistent(vma) || i915_vma_is_purged(vma))
+   return ret;
+
+   return i915_vm_sync(vma->vm);
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
 static int i915_vma_verify_bind_complete(struct i915_vma *vma)
 {
@@ -1917,6 +1935,8 @@ int _i915_vma_move_to_active(struct i915_vma *vma,
int err;
 
assert_object_held(obj);
+   if (i915_vma_is_persistent(vma))
+   return -EINVAL;
 
GEM_BUG_ON(!vma->pages);
 
@@ -2131,6 +2151,14 @@ static struct dma_fence *__i915_vma_unbind_async(struct 
i915_vma *vma)
return ERR_PTR(-EBUSY);
}
 
+   if (i915_vma_is_persistent(vma) &&
+   __i915_sw_fence_await_reservation(&vma->resource->chain,
+ vma->vm->root_obj->base.resv,
+ DMA_RESV_USAGE_BOOKKEEP,
+ i915_fence_timeout(vma->vm->i915),
+ GFP_NOWAIT | __GFP_NOWARN) < 0)
+   return ERR_PTR(-EBUSY);
+
fence = __i915_vma_evict(vma, true);
 
drm_mm_remove_node(&vma->node); /* pairs with i915_vma_release() */
diff --git a/drivers

[Intel-gfx] [PATCH v9 03/23] drm/i915/vm_bind: Expose i915_gem_object_max_page_size()

2022-12-12 Thread Niranjana Vishwanathapura

Expose i915_gem_object_max_page_size() function non-static
which will be used by the vm_bind feature.

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gem/i915_gem_create.c | 18 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.h |  2 ++
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c 
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 005a7f842784..86469710bd59 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -15,10 +15,18 @@
 #include "i915_trace.h"
 #include "i915_user_extensions.h"
 
-static u32 object_max_page_size(struct intel_memory_region **placements,
-   unsigned int n_placements)
+/**
+ * i915_gem_object_max_page_size() - max of min_page_size of the regions
+ * @placements:  list of regions
+ * @n_placements: number of the placements
+ *
+ * Returns the largest of min_page_size of the @placements,
+ * or I915_GTT_PAGE_SIZE_4K if @n_placements is 0.
+ */
+u32 i915_gem_object_max_page_size(struct intel_memory_region **placements,
+ unsigned int n_placements)
 {
-   u32 max_page_size = 0;
+   u32 max_page_size = I915_GTT_PAGE_SIZE_4K;
int i;
 
for (i = 0; i < n_placements; i++) {
@@ -28,7 +36,6 @@ static u32 object_max_page_size(struct intel_memory_region 
**placements,
max_page_size = max_t(u32, max_page_size, mr->min_page_size);
}
 
-   GEM_BUG_ON(!max_page_size);
return max_page_size;
 }
 
@@ -99,7 +106,8 @@ __i915_gem_object_create_user_ext(struct drm_i915_private 
*i915, u64 size,
 
i915_gem_flush_free_objects(i915);
 
-   size = round_up(size, object_max_page_size(placements, n_placements));
+   size = round_up(size, i915_gem_object_max_page_size(placements,
+   n_placements));
if (size == 0)
return ERR_PTR(-EINVAL);
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 3db53769864c..5455ca0eabe9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -47,6 +47,8 @@ static inline bool i915_gem_object_size_2big(u64 size)
 }
 
 void i915_gem_init__objects(struct drm_i915_private *i915);
+u32 i915_gem_object_max_page_size(struct intel_memory_region **placements,
+ unsigned int n_placements);
 
 void i915_objects_module_exit(void);
 int i915_objects_module_init(void);
-- 
2.21.0.rc0.32.g243a4c7e27

[Intel-gfx] [PATCH v9 02/23] drm/i915/vm_bind: Add __i915_sw_fence_await_reservation()

2022-12-12 Thread Niranjana Vishwanathapura

Add function __i915_sw_fence_await_reservation() for
asynchronous wait on a dma-resv object with specified
dma_resv_usage. This is required for async vma unbind
with vm_bind.

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
---
 drivers/gpu/drm/i915/i915_sw_fence.c | 28 +---
 drivers/gpu/drm/i915/i915_sw_fence.h | 23 +--
 2 files changed, 38 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c 
b/drivers/gpu/drm/i915/i915_sw_fence.c
index cc2a8821d22a..ae06d35db056 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -7,7 +7,6 @@
 #include 
 #include 
 #include 
-#include 
 
 #include "i915_sw_fence.h"
 #include "i915_selftest.h"
@@ -569,11 +568,26 @@ int __i915_sw_fence_await_dma_fence(struct i915_sw_fence 
*fence,
return ret;
 }
 
-int i915_sw_fence_await_reservation(struct i915_sw_fence *fence,
-   struct dma_resv *resv,
-   bool write,
-   unsigned long timeout,
-   gfp_t gfp)
+/**
+ * __i915_sw_fence_await_reservation() - Setup a fence to wait on a dma-resv
+ * object with specified usage.
+ * @fence: the fence that needs to wait
+ * @resv: dma-resv object
+ * @usage: dma_resv_usage (See enum dma_resv_usage)
+ * @timeout: how long to wait in jiffies
+ * @gfp: allocation mode
+ *
+ * Setup the @fence to asynchronously wait on dma-resv object @resv for
+ * @usage to complete before signaling.
+ *
+ * Returns 0 if there is nothing to wait on, -ve error code upon error
+ * and >0 upon successfully setting up the wait.
+ */
+int __i915_sw_fence_await_reservation(struct i915_sw_fence *fence,
+ struct dma_resv *resv,
+ enum dma_resv_usage usage,
+ unsigned long timeout,
+ gfp_t gfp)
 {
struct dma_resv_iter cursor;
struct dma_fence *f;
@@ -582,7 +596,7 @@ int i915_sw_fence_await_reservation(struct i915_sw_fence 
*fence,
debug_fence_assert(fence);
might_sleep_if(gfpflags_allow_blocking(gfp));
 
-   dma_resv_iter_begin(&cursor, resv, dma_resv_usage_rw(write));
+   dma_resv_iter_begin(&cursor, resv, usage);
dma_resv_for_each_fence_unlocked(&cursor, f) {
pending = i915_sw_fence_await_dma_fence(fence, f, timeout,
gfp);
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.h 
b/drivers/gpu/drm/i915/i915_sw_fence.h
index f752bfc7c6e1..9c4859dc4c0d 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.h
+++ b/drivers/gpu/drm/i915/i915_sw_fence.h
@@ -10,13 +10,13 @@
 #define _I915_SW_FENCE_H_
 
 #include 
+#include 
 #include 
 #include 
 #include  /* for NOTIFY_DONE */
 #include 
 
 struct completion;
-struct dma_resv;
 struct i915_sw_fence;
 
 enum i915_sw_fence_notify {
@@ -89,11 +89,22 @@ int i915_sw_fence_await_dma_fence(struct i915_sw_fence 
*fence,
  unsigned long timeout,
  gfp_t gfp);
 
-int i915_sw_fence_await_reservation(struct i915_sw_fence *fence,
-   struct dma_resv *resv,
-   bool write,
-   unsigned long timeout,
-   gfp_t gfp);
+int __i915_sw_fence_await_reservation(struct i915_sw_fence *fence,
+ struct dma_resv *resv,
+ enum dma_resv_usage usage,
+ unsigned long timeout,
+ gfp_t gfp);
+
+static inline int i915_sw_fence_await_reservation(struct i915_sw_fence *fence,
+ struct dma_resv *resv,
+ bool write,
+ unsigned long timeout,
+ gfp_t gfp)
+{
+   return __i915_sw_fence_await_reservation(fence, resv,
+dma_resv_usage_rw(write),
+timeout, gfp);
+}
 
 bool i915_sw_fence_await(struct i915_sw_fence *fence);
 void i915_sw_fence_complete(struct i915_sw_fence *fence);
-- 
2.21.0.rc0.32.g243a4c7e27

[Intel-gfx] [PATCH v9 00/23] drm/i915/vm_bind: Add VM_BIND functionality

2022-12-12 Thread Niranjana Vishwanathapura

DRM_I915_GEM_VM_BIND/UNBIND ioctls allows UMD to bind/unbind GEM
buffer objects (BOs) or sections of a BOs at specified GPU virtual
addresses on a specified address space (VM). Multiple mappings can map
to the same physical pages of an object (aliasing). These mappings (also
referred to as persistent mappings) will be persistent across multiple
GPU submissions (execbuf calls) issued by the UMD, without user having
to provide a list of all required mappings during each submission (as
required by older execbuf mode).

This patch series support VM_BIND version 1, as described by the param
I915_PARAM_VM_BIND_VERSION.

Add new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only works in
vm_bind mode. The vm_bind mode only works with this new execbuf3 ioctl.
The new execbuf3 ioctl will not have any execlist support and all the
legacy support like relocations etc., are removed.

NOTEs:
* It is based on below VM_BIND design+uapi rfc.
  Documentation/gpu/rfc/i915_vm_bind.rst

* The IGT RFC series is posted as,
  [PATCH i-g-t v9 0/19] vm_bind: Add VM_BIND validation support

v2: Address various review comments
v3: Address review comments and other fixes
v4: Remove vm_unbind out fence uapi which is not supported yet,
replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode()
v5: Render kernel-doc, use PIN_NOEVICT, limit vm_bind support to
non-recoverable faults
v6: Rebased, minor fixes, add reserved fields to drm_i915_gem_vm_bind,
add new patch for async vm_unbind support
v7: Rebased, minor cleanups as per review feedback
v8: Rebased, add capture support
v9: Address capture support feedback from v8

Test-with: 20221212231254.2303-1-niranjana.vishwanathap...@intel.com

Signed-off-by: Niranjana Vishwanathapura 

Niranjana Vishwanathapura (23):
  drm/i915/vm_bind: Expose vm lookup function
  drm/i915/vm_bind: Add __i915_sw_fence_await_reservation()
  drm/i915/vm_bind: Expose i915_gem_object_max_page_size()
  drm/i915/vm_bind: Support partially mapped vma resource
  drm/i915/vm_bind: Add support to create persistent vma
  drm/i915/vm_bind: Implement bind and unbind of object
  drm/i915/vm_bind: Support for VM private BOs
  drm/i915/vm_bind: Add support to handle object evictions
  drm/i915/vm_bind: Support persistent vma activeness tracking
  drm/i915/vm_bind: Add out fence support
  drm/i915/vm_bind: Abstract out common execbuf functions
  drm/i915/vm_bind: Use common execbuf functions in execbuf path
  drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl
  drm/i915/vm_bind: Update i915_vma_verify_bind_complete()
  drm/i915/vm_bind: Expose i915_request_await_bind()
  drm/i915/vm_bind: Handle persistent vmas in execbuf3
  drm/i915/vm_bind: userptr dma-resv changes
  drm/i915/vm_bind: Limit vm_bind mode to non-recoverable contexts
  drm/i915/vm_bind: Add uapi for user to enable vm_bind_mode
  drm/i915/vm_bind: Render VM_BIND documentation
  drm/i915/vm_bind: Async vm_unbind support
  drm/i915/vm_bind: Properly build persistent map sg table
  drm/i915/vm_bind: Support capture of persistent mappings

 Documentation/gpu/i915.rst|  78 +-
 drivers/gpu/drm/i915/Makefile |   3 +
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |  43 +-
 drivers/gpu/drm/i915/gem/i915_gem_context.h   |  17 +
 drivers/gpu/drm/i915/gem/i915_gem_create.c|  72 +-
 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c|   6 +
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 522 +--
 .../gpu/drm/i915/gem/i915_gem_execbuffer3.c   | 872 ++
 .../drm/i915/gem/i915_gem_execbuffer_common.c | 671 ++
 .../drm/i915/gem/i915_gem_execbuffer_common.h |  76 ++
 drivers/gpu/drm/i915/gem/i915_gem_ioctls.h|   2 +
 drivers/gpu/drm/i915/gem/i915_gem_object.c|   3 +
 drivers/gpu/drm/i915/gem/i915_gem_object.h|   2 +
 .../gpu/drm/i915/gem/i915_gem_object_types.h  |   6 +
 drivers/gpu/drm/i915/gem/i915_gem_userptr.c   |  19 +
 drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h   |  30 +
 .../drm/i915/gem/i915_gem_vm_bind_object.c| 463 ++
 drivers/gpu/drm/i915/gt/intel_gtt.c   |  22 +
 drivers/gpu/drm/i915/gt/intel_gtt.h   |  28 +
 drivers/gpu/drm/i915/i915_driver.c|   4 +
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/i915_gem_gtt.c   |  39 +
 drivers/gpu/drm/i915/i915_gem_gtt.h   |   3 +
 drivers/gpu/drm/i915/i915_getparam.c  |   3 +
 drivers/gpu/drm/i915/i915_gpu_error.c |  18 +-
 drivers/gpu/drm/i915/i915_sw_fence.c  |  28 +-
 drivers/gpu/drm/i915/i915_sw_fence.h  |  23 +-
 drivers/gpu/drm/i915/i915_vma.c   | 308 ++-
 drivers/gpu/drm/i915/i915_vma.h   |  70 +-
 drivers/gpu/drm/i915/i915_vma_types.h |  43 +
 include/uapi/drm/i915_drm.h   | 281 +-
 31 files changed, 3205 insertions(+), 552 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
 create mode 100644 drivers/gpu/drm/i915/gem/i

[Intel-gfx] [PATCH v9 01/23] drm/i915/vm_bind: Expose vm lookup function

2022-12-12 Thread Niranjana Vishwanathapura

Make i915_gem_vm_lookup() function non-static as it will be
used by the vm_bind feature.

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 11 ++-
 drivers/gpu/drm/i915/gem/i915_gem_context.h |  3 +++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 46e71f62fcec..b90901ad6866 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -346,7 +346,16 @@ static int proto_context_register(struct 
drm_i915_file_private *fpriv,
return ret;
 }
 
-static struct i915_address_space *
+/**
+ * i915_gem_vm_lookup() - looks up for the VM reference given the vm id
+ * @file_priv: the private data associated with the user's file
+ * @id: the VM id
+ *
+ * Finds the VM reference associated to a specific id.
+ *
+ * Returns the VM pointer on success, NULL in case of failure.
+ */
+struct i915_address_space *
 i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id)
 {
struct i915_address_space *vm;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h 
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index e5b0f66ea1fe..899fa8f1e0fe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -139,6 +139,9 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, 
void *data,
 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
   struct drm_file *file);
 
+struct i915_address_space *
+i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id);
+
 struct i915_gem_context *
 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id);
 
-- 
2.21.0.rc0.32.g243a4c7e27

Re: [Intel-gfx] [PATCH] drm/i915/gt: Reset twice

2022-12-12 Thread Andi Shyti

Hi Rodrigo,

On Mon, Dec 12, 2022 at 11:55:10AM -0500, Rodrigo Vivi wrote:
> On Mon, Dec 12, 2022 at 05:13:38PM +0100, Andi Shyti wrote:
> > From: Chris Wilson 
> > 
> > After applying an engine reset, on some platforms like Jasperlake, we
> > occasionally detect that the engine state is not cleared until shortly
> > after the resume. As we try to resume the engine with volatile internal
> > state, the first request fails with a spurious CS event (it looks like
> > it reports a lite-restore to the hung context, instead of the expected
> > idle->active context switch).
> > 
> > Signed-off-by: Chris Wilson 
> 
> There's a typo in the signature email I'm afraid...

oh yes, I forgot the 'C' :)

> Other than that, have we checked the possibility of using the 
> driver-initiated-flr bit
> instead of this second loop? That should be the right way to guarantee 
> everything is
> cleared on gen11+...

maybe I am misinterpreting it, but is FLR the same as resetting
hardware domains individually?

How am I supposed to use driver_initiated_flr() in this context?

Thanks,
Andi

> > Cc: sta...@vger.kernel.org
> > Cc: Mika Kuoppala 
> > Signed-off-by: Andi Shyti 
> > ---
> >  drivers/gpu/drm/i915/gt/intel_reset.c | 34 ++-
> >  1 file changed, 28 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
> > b/drivers/gpu/drm/i915/gt/intel_reset.c
> > index ffde89c5835a4..88dfc0c5316ff 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> > @@ -268,6 +268,7 @@ static int ilk_do_reset(struct intel_gt *gt, 
> > intel_engine_mask_t engine_mask,
> >  static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
> >  {
> > struct intel_uncore *uncore = gt->uncore;
> > +   int loops = 2;
> > int err;
> >  
> > /*
> > @@ -275,18 +276,39 @@ static int gen6_hw_domain_reset(struct intel_gt *gt, 
> > u32 hw_domain_mask)
> >  * for fifo space for the write or forcewake the chip for
> >  * the read
> >  */
> > -   intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
> > +   do {
> > +   intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
> >  
> > -   /* Wait for the device to ack the reset requests */
> > -   err = __intel_wait_for_register_fw(uncore,
> > -  GEN6_GDRST, hw_domain_mask, 0,
> > -  500, 0,
> > -  NULL);
> > +   /*
> > +* Wait for the device to ack the reset requests.
> > +*
> > +* On some platforms, e.g. Jasperlake, we see see that the
> > +* engine register state is not cleared until shortly after
> > +* GDRST reports completion, causing a failure as we try
> > +* to immediately resume while the internal state is still
> > +* in flux. If we immediately repeat the reset, the second
> > +* reset appears to serialise with the first, and since
> > +* it is a no-op, the registers should retain their reset
> > +* value. However, there is still a concern that upon
> > +* leaving the second reset, the internal engine state
> > +* is still in flux and not ready for resuming.
> > +*/
> > +   err = __intel_wait_for_register_fw(uncore, GEN6_GDRST,
> > +  hw_domain_mask, 0,
> > +  2000, 0,
> > +  NULL);
> > +   } while (err == 0 && --loops);
> > if (err)
> > GT_TRACE(gt,
> >  "Wait for 0x%08x engines reset failed\n",
> >  hw_domain_mask);
> >  
> > +   /*
> > +* As we have observed that the engine state is still volatile
> > +* after GDRST is acked, impose a small delay to let everything settle.
> > +*/
> > +   udelay(50);
> > +
> > return err;
> >  }
> >  
> > -- 
> > 2.38.1
> >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Add OAG 32 bit format support for MTL

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915/mtl: Add OAG 32 bit format support for MTL
URL   : https://patchwork.freedesktop.org/series/111868/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12497 -> Patchwork_111868v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111868v1/index.html

Participating hosts (18 -> 19)
--

  Additional (1): fi-pnv-d510 

Known issues


  Here are the changes found in Patchwork_111868v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:NOTRUN -> [FAIL][1] ([i915#7229])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111868v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@kms_psr@primary_page_flip:
- fi-pnv-d510:NOTRUN -> [SKIP][2] ([fdo#109271]) +44 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111868v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229


Build changes
-

  * Linux: CI_DRM_12497 -> Patchwork_111868v1

  CI-20190529: 20190529
  CI_DRM_12497: 6636ff92fd32bda3fed63832bc12bf2a9d7c1c33 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7091: b8015f920c9f469d3733854263cb878373c1df51 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111868v1: 6636ff92fd32bda3fed63832bc12bf2a9d7c1c33 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

bf4eec46f88a drm/i915/mtl: Add OA support by enabling 32 bit OAG formats for MTL
02d46558c571 drm/i915/mtl: Update OA mux whitelist for MTL
9f6e92daefe0 drm/i915/mtl: Add Wa_14015846243 to fix OA vs CS timestamp mismatch
4a63fce76c5d drm/i915/mtl: Resize noa_wait BO size to save restore GPR regs

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111868v1/index.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add OAG 32 bit format support for MTL

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915/mtl: Add OAG 32 bit format support for MTL
URL   : https://patchwork.freedesktop.org/series/111868/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] [PATCH v4 4/4] drm/i915/mtl: Add OA support by enabling 32 bit OAG formats for MTL

2022-12-12 Thread Umesh Nerlige Ramappa

Without an entry in oa_init_supported_formats, OA will not be functional
in MTL. Enable OA support by enabling 32 bit OAG formats for MTL.

Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20228

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_perf.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 41f6c0923ba5..824a34ec0b83 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4776,6 +4776,7 @@ static void oa_init_supported_formats(struct i915_perf 
*perf)
break;
 
case INTEL_DG2:
+   case INTEL_METEORLAKE:
oa_format_add(perf, I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
oa_format_add(perf, I915_OA_FORMAT_A24u40_A14u32_B8_C8);
break;
-- 
2.38.1

[Intel-gfx] [PATCH v4 0/4] drm/i915/mtl: Add OAG 32 bit format support for MTL

2022-12-12 Thread Umesh Nerlige Ramappa

Enable OA for MTL by adding 32-bit OA format support and relevant fixes.

v4: Rebase

Signed-off-by: Umesh Nerlige Ramappa 

Umesh Nerlige Ramappa (4):
  drm/i915/mtl: Resize noa_wait BO size to save restore GPR regs
  drm/i915/mtl: Add Wa_14015846243 to fix OA vs CS timestamp mismatch
  drm/i915/mtl: Update OA mux whitelist for MTL
  drm/i915/mtl: Add OA support by enabling 32 bit OAG formats for MTL

 drivers/gpu/drm/i915/gt/intel_gt_types.h |  6 ---
 drivers/gpu/drm/i915/i915_perf.c | 49 ++--
 2 files changed, 38 insertions(+), 17 deletions(-)

-- 
2.38.1

[Intel-gfx] [PATCH v4 3/4] drm/i915/mtl: Update OA mux whitelist for MTL

2022-12-12 Thread Umesh Nerlige Ramappa

0x20cc (WAIT_FOR_RC6_EXIT on other platforms) is repurposed on MTL. Use
a separate mux table to verify oa configs passed by user.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_perf.c | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 1a8618a787d6..41f6c0923ba5 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4322,6 +4322,17 @@ static const struct i915_range gen12_oa_mux_regs[] = {
{}
 };
 
+/*
+ * Ref: 14010536224:
+ * 0x20cc is repurposed on MTL, so use a separate array for MTL.
+ */
+static const struct i915_range mtl_oa_mux_regs[] = {
+   { .start = 0x0d00, .end = 0x0d04 }, /* RPM_CONFIG[0-1] */
+   { .start = 0x0d0c, .end = 0x0d2c }, /* NOA_CONFIG[0-8] */
+   { .start = 0x9840, .end = 0x9840 }, /* GDT_CHICKEN_BITS */
+   { .start = 0x9884, .end = 0x9888 }, /* NOA_WRITE */
+};
+
 static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
 {
return reg_in_range_table(addr, gen7_oa_b_counters);
@@ -4365,7 +4376,10 @@ static bool xehp_is_valid_b_counter_addr(struct 
i915_perf *perf, u32 addr)
 
 static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
 {
-   return reg_in_range_table(addr, gen12_oa_mux_regs);
+   if (IS_METEORLAKE(perf->i915))
+   return reg_in_range_table(addr, mtl_oa_mux_regs);
+   else
+   return reg_in_range_table(addr, gen12_oa_mux_regs);
 }
 
 static u32 mask_reg_value(u32 reg, u32 val)
-- 
2.38.1

[Intel-gfx] [PATCH v4 1/4] drm/i915/mtl: Resize noa_wait BO size to save restore GPR regs

2022-12-12 Thread Umesh Nerlige Ramappa

On MTL, gt->scratch was using stolen lmem. An MI_SRM to stolen lmem
caused a hang that was attributed to saving and restoring the GPR
registers used for noa_wait.

Add an additional page in noa_wait BO to save/restore GPR registers for
the noa_wait logic.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/gt/intel_gt_types.h |  6 --
 drivers/gpu/drm/i915/i915_perf.c | 25 
 2 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 0b6da2aa9718..f08c2556aa25 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -304,12 +304,6 @@ enum intel_gt_scratch_field {
 
/* 8 bytes */
INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
-
-   /* 6 * 8 bytes */
-   INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,
-
-   /* 4 bytes */
-   INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,
 };
 
 #endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index d22f30dd4fba..a8b34460d36f 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1846,8 +1846,7 @@ static u32 *save_restore_register(struct i915_perf_stream 
*stream, u32 *cs,
for (d = 0; d < dword_count; d++) {
*cs++ = cmd;
*cs++ = i915_mmio_reg_offset(reg) + 4 * d;
-   *cs++ = intel_gt_scratch_offset(stream->engine->gt,
-   offset) + 4 * d;
+   *cs++ = i915_ggtt_offset(stream->noa_wait) + offset + 4 * d;
*cs++ = 0;
}
 
@@ -1880,7 +1879,13 @@ static int alloc_noa_wait(struct i915_perf_stream 
*stream)
  MI_PREDICATE_RESULT_2_ENGINE(base) :
  
MI_PREDICATE_RESULT_1(RENDER_RING_BASE);
 
-   bo = i915_gem_object_create_internal(i915, 4096);
+   /*
+* gt->scratch was being used to save/restore the GPR registers, but on
+* MTL the scratch uses stolen lmem. An MI_SRM to this memory region
+* causes an engine hang. Instead allocate an additional page here to
+* save/restore GPR registers
+*/
+   bo = i915_gem_object_create_internal(i915, 8192);
if (IS_ERR(bo)) {
drm_err(&i915->drm,
"Failed to allocate NOA wait batchbuffer\n");
@@ -1914,14 +1919,19 @@ static int alloc_noa_wait(struct i915_perf_stream 
*stream)
goto err_unpin;
}
 
+   stream->noa_wait = vma;
+
+#define GPR_SAVE_OFFSET 4096
+#define PREDICATE_SAVE_OFFSET 4160
+
/* Save registers. */
for (i = 0; i < N_CS_GPR; i++)
cs = save_restore_register(
stream, cs, true /* save */, CS_GPR(i),
-   INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
+   GPR_SAVE_OFFSET + 8 * i, 2);
cs = save_restore_register(
stream, cs, true /* save */, mi_predicate_result,
-   INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
+   PREDICATE_SAVE_OFFSET, 1);
 
/* First timestamp snapshot location. */
ts0 = cs;
@@ -2037,10 +2047,10 @@ static int alloc_noa_wait(struct i915_perf_stream 
*stream)
for (i = 0; i < N_CS_GPR; i++)
cs = save_restore_register(
stream, cs, false /* restore */, CS_GPR(i),
-   INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
+   GPR_SAVE_OFFSET + 8 * i, 2);
cs = save_restore_register(
stream, cs, false /* restore */, mi_predicate_result,
-   INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
+   PREDICATE_SAVE_OFFSET, 1);
 
/* And return to the ring. */
*cs++ = MI_BATCH_BUFFER_END;
@@ -2050,7 +2060,6 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
i915_gem_object_flush_map(bo);
__i915_gem_object_release_map(bo);
 
-   stream->noa_wait = vma;
goto out_ww;
 
 err_unpin:
-- 
2.38.1

[Intel-gfx] [PATCH v4 2/4] drm/i915/mtl: Add Wa_14015846243 to fix OA vs CS timestamp mismatch

2022-12-12 Thread Umesh Nerlige Ramappa

Similar to ACM, OA timestamp that is part of the OA report is shifted
when compared to the CS timestamp. Add MTL to the WA.

Signed-off-by: Umesh Nerlige Ramappa 
Reviewed-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_perf.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index a8b34460d36f..1a8618a787d6 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3140,8 +3140,11 @@ get_sseu_config(struct intel_sseu *out_sseu,
  */
 u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
 {
-   /* Wa_18013179988:dg2 */
-   if (IS_DG2(i915)) {
+   /*
+* Wa_18013179988:dg2
+* Wa_14015846243:mtl
+*/
+   if (IS_DG2(i915) || IS_METEORLAKE(i915)) {
intel_wakeref_t wakeref;
u32 reg, shift;
 
-- 
2.38.1

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: Add OAG 32 bit format support for MTL (rev4)

2022-12-12 Thread Umesh Nerlige Ramappa


On Sat, Dec 10, 2022 at 05:09:40PM +, Patchwork wrote:

  Patch Details

Series:  drm/i915/mtl: Add OAG 32 bit format support for MTL (rev4)
URL: [1]https://patchwork.freedesktop.org/series/111512/
State:   failure
Details: 
[2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111512v4/index.html

 CI Bug Log - changes from CI_DRM_12491 -> Patchwork_111512v4

Summary

  FAILURE

  Serious unknown changes coming with Patchwork_111512v4 absolutely need to
  be
  verified manually.

  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111512v4, please notify your bug team to allow
  them
  to document this new failure mode, which will reduce false positives in
  CI.

  External URL:
  https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111512v4/index.html

Participating hosts (41 -> 5)

  ERROR: It appears as if the changes made in Patchwork_111512v4 prevented
  too many machines from booting.

  Missing (36): fi-kbl-soraka fi-rkl-11600 fi-rkl-guc bat-adls-5 bat-dg1-5
  fi-bdw-gvtdvm fi-icl-u2 bat-adlp-6 fi-pnv-d510 bat-rpls-2 fi-skl-6600u
  fi-snb-2600 fi-bsw-n3050 fi-adl-ddr5 bat-dg2-8 bat-adlm-1 bat-dg2-9
  fi-hsw-4770 bat-atsm-1 fi-ivb-3770 bat-jsl-3 fi-elk-e7500 bat-dg2-11
  fi-bsw-nick fi-skl-6700k2 fi-kbl-7567u bat-kbl-2 bat-adlp-9 fi-skl-guc
  fi-glk-j4005 fi-ehl-2 fi-jsl-1 fi-cfl-guc bat-adlp-4 fi-kbl-8809g
  fi-bsw-kefka


This looks like a false alarm. I loaded this on an ADLP and KBL and I 
don't see any issues.  This does not happen on rev2. Diff between rev2 
and rev3 is a change in commit message. rev4 is just a rerun.


I will post a rebased version to see if this resolves.

Regards,
Umesh



Known issues

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence
URL   : https://patchwork.freedesktop.org/series/111850/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12493_full -> Patchwork_111850v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_111850v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111850v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (14 -> 14)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_111850v1_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_backlight@fade-with-suspend:
- shard-tglb: NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/shard-tglb5/igt@i915_pm_backli...@fade-with-suspend.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_mmap_write_crc@main:
- {shard-tglu-9}: NOTRUN -> [SKIP][2] +2 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/shard-tglu-9/igt@kms_mmap_write_...@main.html

  
Known issues


  Here are the changes found in Patchwork_111850v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@psr2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#658])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/shard-iclb2/igt@feature_discov...@psr2.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/shard-iclb3/igt@feature_discov...@psr2.html

  * igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) +1 similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/shard-iclb2/igt@gem_exec_balan...@parallel-bb-first.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/shard-iclb3/igt@gem_exec_balan...@parallel-bb-first.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/shard-tglb1/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/shard-tglb1/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none@rcs0:
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/shard-glk5/igt@gem_exec_fair@basic-n...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/shard-glk4/igt@gem_exec_fair@basic-n...@rcs0.html

  * igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#3989] / [i915#454])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/shard-iclb2/igt@i915_pm...@dc6-dpms.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/shard-iclb3/igt@i915_pm...@dc6-dpms.html

  * igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [PASS][13] -> [SKIP][14] ([i915#4281])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/shard-iclb2/igt@i915_pm...@dc9-dpms.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/shard-iclb3/igt@i915_pm...@dc9-dpms.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- shard-skl:  [PASS][15] -> [WARN][16] ([i915#1804])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/shard-skl7/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/shard-skl7/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html

  * igt@kms_ccs@pipe-a-bad-rotation-90-4_tiled_dg2_rc_ccs:
- shard-tglb: NOTRUN -> [SKIP][17] ([i915#3689] / [i915#6095])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/shard-tglb1/igt@kms_ccs@pipe-a-bad-rotation-90-4_tiled_dg2_rc_ccs.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-skl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3886])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/shard-skl7/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-apl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3886]) +2 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/shard-apl6/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@vga-hpd-without-ddc:

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/migrate: fix corner case in CCS aux copying

2022-12-12 Thread Patchwork

== Series Details ==

Series: series starting with [1/2] drm/i915/migrate: fix corner case in CCS aux 
copying
URL   : https://patchwork.freedesktop.org/series/111863/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12497 -> Patchwork_111863v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111863v1/index.html

Participating hosts (18 -> 18)
--

  Additional (1): fi-pnv-d510 
  Missing(1): fi-rkl-11600 

Known issues


  Here are the changes found in Patchwork_111863v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][1] -> [INCOMPLETE][2] ([i915#4785])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12497/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111863v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_psr@primary_page_flip:
- fi-pnv-d510:NOTRUN -> [SKIP][3] ([fdo#109271]) +44 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111863v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][4] ([fdo#109271] / [i915#4312] / 
[i915#5594])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111863v1/fi-hsw-4770/igt@run...@aborted.html

  
 Possible fixes 

  * 
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka:   [FAIL][5] ([i915#6298]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12497/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111863v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298


Build changes
-

  * Linux: CI_DRM_12497 -> Patchwork_111863v1

  CI-20190529: 20190529
  CI_DRM_12497: 6636ff92fd32bda3fed63832bc12bf2a9d7c1c33 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7091: b8015f920c9f469d3733854263cb878373c1df51 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111863v1: 6636ff92fd32bda3fed63832bc12bf2a9d7c1c33 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

9e50a42eec84 drm/i915/ttm: consider CCS for backup objects
ae02d971ae1c drm/i915/migrate: fix corner case in CCS aux copying

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111863v1/index.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/migrate: fix corner case in CCS aux copying

2022-12-12 Thread Patchwork

== Series Details ==

Series: series starting with [1/2] drm/i915/migrate: fix corner case in CCS aux 
copying
URL   : https://patchwork.freedesktop.org/series/111863/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Reset twice

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915/gt: Reset twice
URL   : https://patchwork.freedesktop.org/series/111859/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12496 -> Patchwork_111859v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111859v1/index.html

Participating hosts (18 -> 19)
--

  Additional (1): fi-hsw-4770 

Known issues


  Here are the changes found in Patchwork_111859v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[PASS][1] -> [FAIL][2] ([i915#7229])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12496/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111859v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111859v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1072]) +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111859v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271]) +11 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111859v1/fi-hsw-4770/igt@kms_setm...@basic-clone-single-crtc.html
- fi-snb-2600:NOTRUN -> [SKIP][6] ([fdo#109271])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111859v1/fi-snb-2600/igt@kms_setm...@basic-clone-single-crtc.html

  
 Warnings 

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [FAIL][7] ([fdo#103375]) -> [INCOMPLETE][8] 
([i915#4817])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12496/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111859v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229


Build changes
-

  * Linux: CI_DRM_12496 -> Patchwork_111859v1

  CI-20190529: 20190529
  CI_DRM_12496: da695a0fe3c49c4c8709e1e6daabd07fc405cf81 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7091: b8015f920c9f469d3733854263cb878373c1df51 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111859v1: da695a0fe3c49c4c8709e1e6daabd07fc405cf81 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

94f3ea5ccb5c drm/i915/gt: Reset twice

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111859v1/index.html

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Reset twice

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915/gt: Reset twice
URL   : https://patchwork.freedesktop.org/series/111859/
State : warning

== Summary ==

Error: dim checkpatch failed
1fbbd5f0943a drm/i915/gt: Reset twice
-:46: WARNING:REPEATED_WORD: Possible repeated word: 'see'
#46: FILE: drivers/gpu/drm/i915/gt/intel_reset.c:285:
+* On some platforms, e.g. Jasperlake, we see see that the

-:71: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see 
Documentation/timers/timers-howto.rst
#71: FILE: drivers/gpu/drm/i915/gt/intel_reset.c:310:
+   udelay(50);

-:75: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address 
mismatch: 'From: Chris Wilson ' != 'Signed-off-by: 
Chris Wilson '

total: 0 errors, 2 warnings, 1 checks, 52 lines checked

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/mtl: Initial display workarounds (rev3)

2022-12-12 Thread Matt Roper

On Sat, Dec 10, 2022 at 03:06:42PM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/mtl: Initial display workarounds (rev3)
> URL   : https://patchwork.freedesktop.org/series/111592/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_12491_full -> Patchwork_111592v3_full
> 
> 
> Summary
> ---
> 
>   **SUCCESS**
> 
>   No regressions found.

Applied to drm-intel-next.  Thanks for the patch.


Matt

> 
>   
> 
> Participating hosts (14 -> 14)
> --
> 
>   No changes in participating hosts
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_111592v3_full:
> 
> ### IGT changes ###
> 
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * {igt@gem_softpin@evict-prime@vcs1}:
> - shard-iclb: NOTRUN -> [FAIL][1]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111592v3/shard-iclb1/igt@gem_softpin@evict-pr...@vcs1.html
> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_111592v3_full that come from known 
> issues:
> 
> ### CI changes ###
> 
>  Possible fixes 
> 
>   * boot:
> - shard-snb:  ([PASS][2], [PASS][3], [PASS][4], [PASS][5], 
> [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
> [PASS][12], [PASS][13], [PASS][14], [PASS][15], [FAIL][16], [PASS][17], 
> [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
> [PASS][24], [PASS][25], [PASS][26]) ([i915#4338]) -> ([PASS][27], [PASS][28], 
> [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], 
> [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], 
> [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], 
> [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51])
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb7/boot.html
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb7/boot.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb7/boot.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb7/boot.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb7/boot.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb7/boot.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb7/boot.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb7/boot.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
>[19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb4/boot.html
>[20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb4/boot.html
>[21]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb4/boot.html
>[22]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb4/boot.html
>[23]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb4/boot.html
>[24]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb4/boot.html
>[25]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb4/boot.html
>[26]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb4/boot.html
>[27]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111592v3/shard-snb7/boot.html
>[28]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111592v3/shard-snb7/boot.html
>[29]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111592v3/shard-snb7/boot.html
>[30]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111592v3/shard-snb7/boot.html
>[31]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111592v3/shard-snb7/boot.html
>[32]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111592v3/shard-snb7/boot.html
>[33]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111592v3/shard-snb7/boot.html
>[34]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111592v3/shard-snb7/boot.html
>[3

Re: [Intel-gfx] [PATCH v8 21/22] drm/i915/vm_bind: Properly build persistent map sg table

2022-12-12 Thread Matthew Auld


On 29/11/2022 07:26, Niranjana Vishwanathapura wrote:

Properly build the sg table for persistent mapping which can
be partial map of the underlying object. Ensure the sg pages
are properly set for page backed regions. The dump capture
support requires this for page backed regions.

Signed-off-by: Niranjana Vishwanathapura 
---
  drivers/gpu/drm/i915/i915_vma.c | 120 +++-
  1 file changed, 119 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 1b9033865768..68a9ac77b4f2 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1298,6 +1298,120 @@ intel_partial_pages(const struct i915_gtt_view *view,
return ERR_PTR(ret);
  }
  
+static unsigned int

+intel_copy_dma_sg(struct sg_table *src_st, struct sg_table *dst_st,
+ u64 offset, u64 length, bool dry_run)
+{
+   struct scatterlist *dst_sg, *src_sg;
+   unsigned int i, len, nents = 0;
+
+   dst_sg = dst_st->sgl;
+   for_each_sgtable_dma_sg(src_st, src_sg, i) {
+   if (sg_dma_len(src_sg) <= offset) {
+   offset -= sg_dma_len(src_sg);
+   continue;
+   }
+
+   nents++;
+   len = min(sg_dma_len(src_sg) - offset, length);
+   if (!dry_run) {
+   sg_dma_address(dst_sg) = sg_dma_address(src_sg) + 
offset;
+   sg_dma_len(dst_sg) = len;
+   dst_sg = sg_next(dst_sg);
+   }
+
+   length -= len;
+   offset = 0;
+   if (!length)
+   break;
+   }
+   WARN_ON_ONCE(length);
+
+   return nents;
+}
+
+static unsigned int
+intel_copy_sg(struct sg_table *src_st, struct sg_table *dst_st,
+ u64 offset, u64 length, bool dry_run)
+{
+   struct scatterlist *dst_sg, *src_sg;
+   unsigned int i, len, nents = 0;
+
+   dst_sg = dst_st->sgl;
+   for_each_sgtable_sg(src_st, src_sg, i) {
+   if (src_sg->length <= offset) {
+   offset -= src_sg->length;
+   continue;
+   }
+
+   nents++;
+   len = min(src_sg->length - offset, length);
+   if (!dry_run) {
+   unsigned long pfn;
+
+   pfn = page_to_pfn(sg_page(src_sg)) + offset / PAGE_SIZE;
+   sg_set_page(dst_sg, pfn_to_page(pfn), len, 0);
+   dst_sg = sg_next(dst_sg);
+   }
+
+   length -= len;
+   offset = 0;
+   if (!length)
+   break;
+   }
+   WARN_ON_ONCE(length);
+
+   return nents;
+}
+
+static noinline struct sg_table *
+intel_persistent_partial_pages(const struct i915_gtt_view *view,
+  struct drm_i915_gem_object *obj)
+{
+   u64 offset = view->partial.offset << PAGE_SHIFT;
+   struct sg_table *st, *obj_st = obj->mm.pages;
+   u64 length = view->partial.size << PAGE_SHIFT;
+   struct scatterlist *sg;
+   unsigned int nents;
+   int ret = -ENOMEM;
+
+   st = kmalloc(sizeof(*st), GFP_KERNEL);
+   if (!st)
+   goto err_st_alloc;
+
+   /* Get required sg_table size */
+   nents = intel_copy_dma_sg(obj_st, st, offset, length, true);
+   if (i915_gem_object_has_struct_page(obj)) {
+   unsigned int pg_nents;
+
+   pg_nents = intel_copy_sg(obj_st, st, offset, length, true);
+   if (nents < pg_nents)
+   nents = pg_nents;
+   }
+
+   ret = sg_alloc_table(st, nents, GFP_KERNEL);
+   if (ret)
+   goto err_sg_alloc;
+
+   /* Build sg_table for specified  section */
+   intel_copy_dma_sg(obj_st, st, offset, length, false);
+   if (i915_gem_object_has_struct_page(obj))
+   intel_copy_sg(obj_st, st, offset, length, false);
+
+   /* Mark last sg */
+   sg = st->sgl;
+   while (sg_next(sg))
+   sg = sg_next(sg);
+   sg_mark_end(sg);


Do we need this bit? The nents is exactly orig_nents, and sg_alloc_table 
will already mark the end for you.


Is it not possible to re-use remap_contiguous_pages() somehow? Also do 
we need the dry_run bit if we use sg_trim()? Maybe something like:


dst = sg_alloc_table(partial.size);

remap_contigious_pages_sg(dst, src);
i915_sg_trim(dst);

dst->nents = 0;
sg = remap_contigious_pages_dma_sg(dst, src);


+
+   return st;
+
+err_sg_alloc:
+   kfree(st);
+err_st_alloc:
+   return ERR_PTR(ret);
+}
+
  static int
  __i915_vma_get_pages(struct i915_vma *vma)
  {
@@ -1330,7 +1444,11 @@ __i915_vma_get_pages(struct i915_vma *vma)
break;
  
  	case I915_GTT_VIEW_PARTIAL:

-   pages = intel_partial_pages(&vma->gtt_view, vma->obj);
+   if (i915_vma_is_persistent(vma))
+

[Intel-gfx] [PATCH 2/2] drm/i915/ttm: consider CCS for backup objects

2022-12-12 Thread Matthew Auld

It seems we can have one or more framebuffers that are still pinned when
suspending lmem, in such a case we end up creating a shmem backup
object, instead of evicting the object directly, but this will skip
copying the CCS aux state, since we don't allocate the extra storage for
the CCS pages as part of the ttm_tt construction. Since we can already
deal with pinned objects just fine, it doesn't seem too nasty to just
extend to support dealing with the CCS aux state, if the object is a
pinned framebuffer. This fixes display corruption (like in gnome-shell)
seen on DG2 when returning from suspend.

Fixes: da0595ae91da ("drm/i915/migrate: Evict and restore the flatccs capable 
lmem obj")
Signed-off-by: Matthew Auld 
Cc: Ville Syrjälä 
Cc: Nirmoy Das 
Cc: Andrzej Hajda 
Cc: Shuicheng Lin 
Cc:  # v5.19+
---
 drivers/gpu/drm/i915/gem/i915_gem_object.c |  3 +++
 .../gpu/drm/i915/gem/i915_gem_object_types.h   | 10 ++
 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 18 +-
 3 files changed, 26 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 733696057761..1a0886b8aaa1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -785,6 +785,9 @@ bool i915_gem_object_needs_ccs_pages(struct 
drm_i915_gem_object *obj)
if (!HAS_FLAT_CCS(to_i915(obj->base.dev)))
return false;
 
+   if (obj->flags & I915_BO_ALLOC_CCS_AUX)
+   return true;
+
for (i = 0; i < obj->mm.n_placements; i++) {
/* Compression is not allowed for the objects with smem 
placement */
if (obj->mm.placements[i]->type == INTEL_MEMORY_SYSTEM)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index a7b70701617a..19c9bdd8f905 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -327,16 +327,18 @@ struct drm_i915_gem_object {
  * dealing with userspace objects the CPU fault handler is free to ignore this.
  */
 #define I915_BO_ALLOC_GPU_ONLY   BIT(6)
+#define I915_BO_ALLOC_CCS_AUXBIT(7)
 #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
 I915_BO_ALLOC_VOLATILE | \
 I915_BO_ALLOC_CPU_CLEAR | \
 I915_BO_ALLOC_USER | \
 I915_BO_ALLOC_PM_VOLATILE | \
 I915_BO_ALLOC_PM_EARLY | \
-I915_BO_ALLOC_GPU_ONLY)
-#define I915_BO_READONLY  BIT(7)
-#define I915_TILING_QUIRK_BIT 8 /* unknown swizzling; do not release! */
-#define I915_BO_PROTECTED BIT(9)
+I915_BO_ALLOC_GPU_ONLY | \
+I915_BO_ALLOC_CCS_AUX)
+#define I915_BO_READONLY  BIT(8)
+#define I915_TILING_QUIRK_BIT 9 /* unknown swizzling; do not release! */
+#define I915_BO_PROTECTED BIT(10)
/**
 * @mem_flags - Mutable placement-related flags
 *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
index 07e49f22f2de..7e67742bc65e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
@@ -50,6 +50,7 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region 
*apply,
container_of(bo->bdev, typeof(*i915), bdev);
struct drm_i915_gem_object *backup;
struct ttm_operation_ctx ctx = {};
+   unsigned int flags;
int err = 0;
 
if (bo->resource->mem_type == I915_PL_SYSTEM || obj->ttm.backup)
@@ -65,7 +66,22 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region 
*apply,
if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
return 0;
 
-   backup = i915_gem_object_create_shmem(i915, obj->base.size);
+   /*
+* It seems that we might have some framebuffers still pinned at this
+* stage, but for such objects we might also need to deal with the CCS
+* aux state. Make sure we force the save/restore of the CCS state,
+* otherwise we might observe display corruption, when returning from
+* suspend.
+*/
+   flags = 0;
+   if (i915_gem_object_needs_ccs_pages(obj)) {
+   WARN_ON_ONCE(!i915_gem_object_is_framebuffer(obj));
+   WARN_ON_ONCE(!pm_apply->allow_gpu);
+
+   flags = I915_BO_ALLOC_CCS_AUX;
+   }
+   backup = 
i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_SMEM],
+  obj->base.size, 0, flags);
if (IS_ERR(backup))
return PTR_ERR(backup);
 
-- 
2.38.1

[Intel-gfx] [PATCH 1/2] drm/i915/migrate: fix corner case in CCS aux copying

2022-12-12 Thread Matthew Auld

In the case of lmem -> lmem transfers, which is currently only possible
with small-bar systems, we need to ensure we copy the CCS aux state
as-is, rather than nuke it. This should fix some nasty display
corruption sometimes seen on DG2 small-bar systems, when also using
DG2_RC_CCS_CC for the surface.

Fixes: e3afc690188b ("drm/i915/display: consider DG2_RC_CCS_CC when migrating 
buffers")
Signed-off-by: Matthew Auld 
Cc: Ville Syrjälä 
Cc: Nirmoy Das 
Cc: Andrzej Hajda 
Cc: Shuicheng Lin 
---
 drivers/gpu/drm/i915/gt/intel_migrate.c | 37 +++--
 1 file changed, 29 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c 
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index e08a739b7091..3f638f198796 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -839,14 +839,35 @@ intel_context_migrate_copy(struct intel_context *ce,
if (err)
goto out_rq;
 
-   /*
-* While we can't always restore/manage the CCS state,
-* we still need to ensure we don't leak the CCS state
-* from the previous user, so make sure we overwrite it
-* with something.
-*/
-   err = emit_copy_ccs(rq, dst_offset, INDIRECT_ACCESS,
-   dst_offset, DIRECT_ACCESS, len);
+   if (src_is_lmem) {
+   /*
+* If the src is already in lmem, then we must
+* be doing an lmem -> lmem transfer, and so
+* should be safe to directly copy the CCS
+* state. In this case we have either
+* initialised the CCS aux state when first
+* clearing the pages (since it is already
+* allocated in lmem), or the user has
+* potentially populated it, in which case we
+* need to copy the CCS state as-is.
+*/
+   err = emit_copy_ccs(rq,
+   dst_offset, INDIRECT_ACCESS,
+   src_offset, INDIRECT_ACCESS,
+   len);
+   } else {
+   /*
+* While we can't always restore/manage the CCS
+* state, we still need to ensure we don't leak
+* the CCS state from the previous user, so make
+* sure we overwrite it with something.
+*/
+   err = emit_copy_ccs(rq,
+   dst_offset, INDIRECT_ACCESS,
+   dst_offset, DIRECT_ACCESS,
+   len);
+   }
+
if (err)
goto out_rq;
 
-- 
2.38.1

Re: [Intel-gfx] [PATCH] drm/i915/gt: Reset twice

2022-12-12 Thread Rodrigo Vivi

On Mon, Dec 12, 2022 at 05:13:38PM +0100, Andi Shyti wrote:
> From: Chris Wilson 
> 
> After applying an engine reset, on some platforms like Jasperlake, we
> occasionally detect that the engine state is not cleared until shortly
> after the resume. As we try to resume the engine with volatile internal
> state, the first request fails with a spurious CS event (it looks like
> it reports a lite-restore to the hung context, instead of the expected
> idle->active context switch).
> 
> Signed-off-by: Chris Wilson 

There's a typo in the signature email I'm afraid...

Other than that, have we checked the possibility of using the 
driver-initiated-flr bit
instead of this second loop? That should be the right way to guarantee 
everything is
cleared on gen11+...

> Cc: sta...@vger.kernel.org
> Cc: Mika Kuoppala 
> Signed-off-by: Andi Shyti 
> ---
>  drivers/gpu/drm/i915/gt/intel_reset.c | 34 ++-
>  1 file changed, 28 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index ffde89c5835a4..88dfc0c5316ff 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -268,6 +268,7 @@ static int ilk_do_reset(struct intel_gt *gt, 
> intel_engine_mask_t engine_mask,
>  static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
>  {
>   struct intel_uncore *uncore = gt->uncore;
> + int loops = 2;
>   int err;
>  
>   /*
> @@ -275,18 +276,39 @@ static int gen6_hw_domain_reset(struct intel_gt *gt, 
> u32 hw_domain_mask)
>* for fifo space for the write or forcewake the chip for
>* the read
>*/
> - intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
> + do {
> + intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
>  
> - /* Wait for the device to ack the reset requests */
> - err = __intel_wait_for_register_fw(uncore,
> -GEN6_GDRST, hw_domain_mask, 0,
> -500, 0,
> -NULL);
> + /*
> +  * Wait for the device to ack the reset requests.
> +  *
> +  * On some platforms, e.g. Jasperlake, we see see that the
> +  * engine register state is not cleared until shortly after
> +  * GDRST reports completion, causing a failure as we try
> +  * to immediately resume while the internal state is still
> +  * in flux. If we immediately repeat the reset, the second
> +  * reset appears to serialise with the first, and since
> +  * it is a no-op, the registers should retain their reset
> +  * value. However, there is still a concern that upon
> +  * leaving the second reset, the internal engine state
> +  * is still in flux and not ready for resuming.
> +  */
> + err = __intel_wait_for_register_fw(uncore, GEN6_GDRST,
> +hw_domain_mask, 0,
> +2000, 0,
> +NULL);
> + } while (err == 0 && --loops);
>   if (err)
>   GT_TRACE(gt,
>"Wait for 0x%08x engines reset failed\n",
>hw_domain_mask);
>  
> + /*
> +  * As we have observed that the engine state is still volatile
> +  * after GDRST is acked, impose a small delay to let everything settle.
> +  */
> + udelay(50);
> +
>   return err;
>  }
>  
> -- 
> 2.38.1
>

Re: [Intel-gfx] [PATCH] drm/i915/hwconfig: Modify mismatched function name

2022-12-12 Thread Rodrigo Vivi

On Mon, Dec 12, 2022 at 11:20:12AM +0800, Jiapeng Chong wrote:
> No functional modification involved.
> 
> drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c:112: warning: expecting 
> prototype for intel_guc_hwconfig_init(). Prototype was for 
> guc_hwconfig_init() instead.
> 
> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=3414
> Reported-by: Abaci Robot 
> Signed-off-by: Jiapeng Chong 
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c 
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
> index 4781fccc2687..bdb20beb3e70 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
> @@ -103,7 +103,7 @@ static bool has_table(struct drm_i915_private *i915)
>  }
>  
>  /**
> - * intel_guc_hwconfig_init - Initialize the HWConfig
> + * guc_hwconfig_init - Initialize the HWConfig
>   *
>   * Retrieve the HWConfig table from the GuC and save it locally.
>   * It can then be queried on demand by other users later on.
> -- 

The name chaged when the function become static. And we shouldn't be
documenting internal static functions. So, could you please entirely
remove this comment block instead of fixing the name?

Thanks,
Rodrigo. 

> 2.20.1.7.g153144c
>

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence (rev3)

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence (rev3)
URL   : https://patchwork.freedesktop.org/series/111850/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12493 -> Patchwork_111850v3


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_111850v3 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111850v3, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v3/index.html

Participating hosts (40 -> 18)
--

  ERROR: It appears as if the changes made in Patchwork_111850v3 prevented too 
many machines from booting.

  Missing(22): fi-kbl-soraka bat-adls-5 bat-dg1-6 bat-dg1-5 bat-adlp-6 
fi-pnv-d510 bat-rpls-2 fi-skl-6600u fi-bsw-n3050 bat-dg2-8 bat-adlm-1 bat-dg2-9 
bat-adln-1 bat-jsl-3 bat-rplp-1 bat-dg2-11 fi-bsw-nick bat-dg1-7 bat-kbl-2 
bat-adlp-9 bat-jsl-1 bat-adlp-4 

Known issues


  Here are the changes found in Patchwork_111850v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [PASS][1] -> [INCOMPLETE][2] ([i915#4817])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v3/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v3/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][4] ([i915#4785]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v3/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817


Build changes
-

  * Linux: CI_DRM_12493 -> Patchwork_111850v3

  CI-20190529: 20190529
  CI_DRM_12493: a6dc4d045339e2817103e99539e3efaa554c941f @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7090: 5aafcf060b6dfbb2fa7aace76c8074d98ac7da8f @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111850v3: a6dc4d045339e2817103e99539e3efaa554c941f @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

f65a9e3d37b0 drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v3/index.html

[Intel-gfx] [PATCH] drm/i915/gt: Reset twice

2022-12-12 Thread Andi Shyti

From: Chris Wilson 

After applying an engine reset, on some platforms like Jasperlake, we
occasionally detect that the engine state is not cleared until shortly
after the resume. As we try to resume the engine with volatile internal
state, the first request fails with a spurious CS event (it looks like
it reports a lite-restore to the hung context, instead of the expected
idle->active context switch).

Signed-off-by: Chris Wilson 
Cc: sta...@vger.kernel.org
Cc: Mika Kuoppala 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gt/intel_reset.c | 34 ++-
 1 file changed, 28 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
b/drivers/gpu/drm/i915/gt/intel_reset.c
index ffde89c5835a4..88dfc0c5316ff 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -268,6 +268,7 @@ static int ilk_do_reset(struct intel_gt *gt, 
intel_engine_mask_t engine_mask,
 static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
 {
struct intel_uncore *uncore = gt->uncore;
+   int loops = 2;
int err;
 
/*
@@ -275,18 +276,39 @@ static int gen6_hw_domain_reset(struct intel_gt *gt, u32 
hw_domain_mask)
 * for fifo space for the write or forcewake the chip for
 * the read
 */
-   intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
+   do {
+   intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
 
-   /* Wait for the device to ack the reset requests */
-   err = __intel_wait_for_register_fw(uncore,
-  GEN6_GDRST, hw_domain_mask, 0,
-  500, 0,
-  NULL);
+   /*
+* Wait for the device to ack the reset requests.
+*
+* On some platforms, e.g. Jasperlake, we see see that the
+* engine register state is not cleared until shortly after
+* GDRST reports completion, causing a failure as we try
+* to immediately resume while the internal state is still
+* in flux. If we immediately repeat the reset, the second
+* reset appears to serialise with the first, and since
+* it is a no-op, the registers should retain their reset
+* value. However, there is still a concern that upon
+* leaving the second reset, the internal engine state
+* is still in flux and not ready for resuming.
+*/
+   err = __intel_wait_for_register_fw(uncore, GEN6_GDRST,
+  hw_domain_mask, 0,
+  2000, 0,
+  NULL);
+   } while (err == 0 && --loops);
if (err)
GT_TRACE(gt,
 "Wait for 0x%08x engines reset failed\n",
 hw_domain_mask);
 
+   /*
+* As we have observed that the engine state is still volatile
+* after GDRST is acked, impose a small delay to let everything settle.
+*/
+   udelay(50);
+
return err;
 }
 
-- 
2.38.1

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence (rev2)

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence (rev2)
URL   : https://patchwork.freedesktop.org/series/111850/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12493 -> Patchwork_111850v2


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_111850v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111850v2, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v2/index.html

Participating hosts (40 -> 19)
--

  ERROR: It appears as if the changes made in Patchwork_111850v2 prevented too 
many machines from booting.

  Missing(21): fi-kbl-soraka bat-adls-5 bat-dg1-6 bat-dg1-5 bat-adlp-6 
bat-rpls-2 fi-skl-6600u fi-bsw-n3050 bat-dg2-8 bat-adlm-1 bat-dg2-9 bat-adln-1 
bat-jsl-3 bat-rplp-1 bat-dg2-11 fi-bsw-nick bat-dg1-7 bat-kbl-2 bat-adlp-9 
bat-jsl-1 bat-adlp-4 

Known issues


  Here are the changes found in Patchwork_111850v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [PASS][1] -> [INCOMPLETE][2] ([i915#4817])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v2/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v2/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  * 
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka:   [PASS][4] -> [FAIL][5] ([i915#6298])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v2/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][6] ([i915#4785]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v2/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298


Build changes
-

  * Linux: CI_DRM_12493 -> Patchwork_111850v2

  CI-20190529: 20190529
  CI_DRM_12493: a6dc4d045339e2817103e99539e3efaa554c941f @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7090: 5aafcf060b6dfbb2fa7aace76c8074d98ac7da8f @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111850v2: a6dc4d045339e2817103e99539e3efaa554c941f @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

2d17c209cee2 drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v2/index.html

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: extract vblank/scanline code to a separate file

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915: extract vblank/scanline code to a separate file
URL   : https://patchwork.freedesktop.org/series/111854/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12493 -> Patchwork_111854v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_111854v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111854v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111854v1/index.html

Participating hosts (40 -> 19)
--

  ERROR: It appears as if the changes made in Patchwork_111854v1 prevented too 
many machines from booting.

  Missing(21): fi-kbl-soraka bat-adls-5 bat-dg1-6 bat-dg1-5 bat-adlp-6 
bat-rpls-2 fi-skl-6600u fi-bsw-n3050 bat-dg2-8 bat-adlm-1 bat-dg2-9 bat-adln-1 
bat-jsl-3 bat-rplp-1 bat-dg2-11 fi-bsw-nick bat-dg1-7 bat-kbl-2 bat-adlp-9 
bat-jsl-1 bat-adlp-4 

Known issues


  Here are the changes found in Patchwork_111854v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#111827])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111854v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html

  
 Possible fixes 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[FAIL][2] ([i915#7229]) -> [PASS][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111854v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600:   [FAIL][4] ([fdo#103375]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111854v1/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][6] ([i915#4785]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111854v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229


Build changes
-

  * Linux: CI_DRM_12493 -> Patchwork_111854v1

  CI-20190529: 20190529
  CI_DRM_12493: a6dc4d045339e2817103e99539e3efaa554c941f @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7090: 5aafcf060b6dfbb2fa7aace76c8074d98ac7da8f @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111854v1: a6dc4d045339e2817103e99539e3efaa554c941f @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

85e6ae772631 drm/i915/reg: split out vblank/scanline regs
f51910697280 drm/i915/vblank: add and use intel_de_read64_2x32() to read vblank 
counter
dc0371955fd7 drm/i915/vblank: use intel_de_read()
9d717beba06e drm/i915/hdmi: abstract scanline range wait into intel_vblank.[ch]
d8e0ae4dbd16 drm/i915/display: use common function for checking scanline is 
moving
d3c5f97e4088 drm/i915/display: move more scanline functions to intel_vblank.[ch]
37bf1cfb7723 drm/i915/irq: split out vblank/scanline code to intel_vblank.[ch]

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111854v1/index.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: extract vblank/scanline code to a separate file

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915: extract vblank/scanline code to a separate file
URL   : https://patchwork.freedesktop.org/series/111854/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced s

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: extract vblank/scanline code to a separate file

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915: extract vblank/scanline code to a separate file
URL   : https://patchwork.freedesktop.org/series/111854/
State : warning

== Summary ==

Error: dim checkpatch failed
1ab2fa26774a drm/i915/irq: split out vblank/scanline code to intel_vblank.[ch]
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
-:53: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#53: 
new file mode 100644

-:95: WARNING:LONG_LINE_COMMENT: line length of 104 exceeds 100 columns
#95: FILE: drivers/gpu/drm/i915/display/intel_vblank.c:38:
+ * -vbs-> <---vbs+1---> <---vbs+2---> <-0-> <-1-> 
<-2--- (scanline counter gen2)

-:96: WARNING:LONG_LINE_COMMENT: line length of 105 exceeds 100 columns
#96: FILE: drivers/gpu/drm/i915/display/intel_vblank.c:39:
+ * -vbs-2---> <---vbs-1---> <---vbs-> <---vbs+1---> <---vbs+2---> 
<-0--- (scanline counter gen3+)

-:97: WARNING:LONG_LINE_COMMENT: line length of 109 exceeds 100 columns
#97: FILE: drivers/gpu/drm/i915/display/intel_vblank.c:40:
+ * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-> <---vbs+1---> 
<---vbs+2- (scanline counter hsw+ hdmi)

-:396: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#396: FILE: drivers/gpu/drm/i915/display/intel_vblank.c:339:
+   position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & 
PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;

-:460: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#460: FILE: drivers/gpu/drm/i915/display/intel_vblank.c:403:
+   return drm_crtc_vblank_helper_get_vblank_timestamp_internal(

total: 0 errors, 5 warnings, 1 checks, 893 lines checked
f01494675c93 drm/i915/display: move more scanline functions to intel_vblank.[ch]
-:86: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see 
Documentation/timers/timers-howto.rst
#86: FILE: drivers/gpu/drm/i915/display/intel_vblank.c:428:
+   msleep(5);

total: 0 errors, 1 warnings, 0 checks, 93 lines checked
95e14852bdca drm/i915/display: use common function for checking scanline is 
moving
52a99694085f drm/i915/hdmi: abstract scanline range wait into intel_vblank.[ch]
77b221471a62 drm/i915/vblank: use intel_de_read()
861132b4e91f drm/i915/vblank: add and use intel_de_read64_2x32() to read vblank 
counter
ad911901f7a8 drm/i915/reg: split out vblank/scanline regs
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in 
import git
ModuleNotFoundError: No module named 'git'
-:40: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#40: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 137 lines checked

[Intel-gfx] [PATCH v3] drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence

2022-12-12 Thread Jani Nikula

Starting from ICL, the default for MIPI GPIO sequences seems to be using
native GPIOs i.e. GPIOs available in the GPU. These native GPIOs reuse
many pins that quite frankly seem scary to poke based on the VBT
sequences. We pretty much have to trust that the board is configured
such that the relevant HPD, PP_CONTROL and GPIO bits aren't used for
anything else.

MIPI sequence v4 also adds a flag to fall back to non-native sequences.

v3:
- Fix -Wbitwise-conditional-parentheses (kernel test robot )

v2:
- Fix HPD pin output set (impacts GPIOs 0 and 5)
- Fix GPIO data output direction set (impacts GPIOs 4 and 9)
- Reduce register accesses to single intel_de_rwm()

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6131
Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 84 +++-
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 2 files changed, 82 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index fce69fa446d5..f19020074ee3 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -41,9 +41,11 @@
 
 #include "i915_drv.h"
 #include "i915_reg.h"
+#include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_dsi.h"
 #include "intel_dsi_vbt.h"
+#include "intel_gmbus_regs.h"
 #include "vlv_dsi.h"
 #include "vlv_dsi_regs.h"
 #include "vlv_sideband.h"
@@ -377,6 +379,75 @@ static void icl_exec_gpio(struct intel_connector 
*connector,
drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
 }
 
+enum {
+   MIPI_RESET_1 = 0,
+   MIPI_AVDD_EN_1,
+   MIPI_BKLT_EN_1,
+   MIPI_AVEE_EN_1,
+   MIPI_VIO_EN_1,
+   MIPI_RESET_2,
+   MIPI_AVDD_EN_2,
+   MIPI_BKLT_EN_2,
+   MIPI_AVEE_EN_2,
+   MIPI_VIO_EN_2,
+};
+
+static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
+ int gpio, bool value)
+{
+   int index;
+
+   if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 11 && gpio >= 
MIPI_RESET_2))
+   return;
+
+   switch (gpio) {
+   case MIPI_RESET_1:
+   case MIPI_RESET_2:
+   index = gpio == MIPI_RESET_1 ? HPD_PORT_A : HPD_PORT_B;
+
+   /* Disable HPD to set the pin to output, and set output value */
+   intel_de_rmw(dev_priv, SHOTPLUG_CTL_DDI,
+SHOTPLUG_CTL_DDI_HPD_ENABLE(index) |
+SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index),
+value ? SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index) : 
0);
+   break;
+   case MIPI_AVDD_EN_1:
+   case MIPI_AVDD_EN_2:
+   index = gpio == MIPI_AVDD_EN_1 ? 0 : 1;
+
+   intel_de_rmw(dev_priv, PP_CONTROL(index), PANEL_POWER_ON,
+value ? PANEL_POWER_ON : 0);
+   break;
+   case MIPI_BKLT_EN_1:
+   case MIPI_BKLT_EN_2:
+   index = gpio == MIPI_AVDD_EN_1 ? 0 : 1;
+
+   intel_de_rmw(dev_priv, PP_CONTROL(index), EDP_BLC_ENABLE,
+value ? EDP_BLC_ENABLE : 0);
+   break;
+   case MIPI_AVEE_EN_1:
+   case MIPI_AVEE_EN_2:
+   index = gpio == MIPI_AVEE_EN_1 ? 1 : 2;
+
+   intel_de_rmw(dev_priv, GPIO(dev_priv, index),
+GPIO_CLOCK_VAL_OUT,
+GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT |
+GPIO_CLOCK_VAL_MASK | (value ? GPIO_CLOCK_VAL_OUT 
: 0));
+   break;
+   case MIPI_VIO_EN_1:
+   case MIPI_VIO_EN_2:
+   index = gpio == MIPI_VIO_EN_1 ? 1 : 2;
+
+   intel_de_rmw(dev_priv, GPIO(dev_priv, index),
+GPIO_DATA_VAL_OUT,
+GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT |
+GPIO_DATA_VAL_MASK | (value ? GPIO_DATA_VAL_OUT : 
0));
+   break;
+   default:
+   MISSING_CASE(gpio);
+   }
+}
+
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 {
struct drm_device *dev = intel_dsi->base.base.dev;
@@ -384,8 +455,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
struct intel_connector *connector = intel_dsi->attached_connector;
u8 gpio_source, gpio_index = 0, gpio_number;
bool value;
-
-   drm_dbg_kms(&dev_priv->drm, "\n");
+   bool native = DISPLAY_VER(dev_priv) >= 11;
 
if (connector->panel.vbt.dsi.seq_version >= 3)
gpio_index = *data++;
@@ -398,10 +468,18 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
else
gpio_source = 0;
 
+   if (connector->panel.vbt.dsi.seq_version >= 4 && *data & BIT(1))
+   native = false;
+
/* pull up/down */

Re: [Intel-gfx] [PATCH 1/5] Renaming weak prng invocations - prandom_bytes_state, prandom_u32_state

2022-12-12 Thread Jason A. Donenfeld

Please CC me on future revisions.

As of 6.2, the prandom namespace is *only* for predictable randomness.
There's no need to rename anything. So nack on this patch 1/5.

With regards to the remaining patches in this series, if you want to
move prandom_u32_state callers over to get_random_bytes() and
get_random_u32(), that's fine from my perspective, but last I looked,
there was much usage in places where being repeatable was actually the
goal - test suites and such, where you want to be able to redo your
tests with the same seed. So you'll have to look at each instance case
by case and convince whoever maintains that code that they don't need
predictability. However, if you do that, the right functions to use are
get_random_bytes() and get_random_u32().

Jason

[Intel-gfx] [PATCH 5/7] drm/i915/vblank: use intel_de_read()

2022-12-12 Thread Jani Nikula

Use the intel_de_* functions for display registers.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_vblank.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c 
b/drivers/gpu/drm/i915/display/intel_vblank.c
index aec7758ef917..cf1215631b27 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -137,7 +137,7 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
if (!vblank->max_vblank_count)
return 0;
 
-   return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe));
+   return intel_de_read(dev_priv, PIPE_FRMCOUNT_G4X(pipe));
 }
 
 static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
-- 
2.34.1

[Intel-gfx] [PATCH 6/7] drm/i915/vblank: add and use intel_de_read64_2x32() to read vblank counter

2022-12-12 Thread Jani Nikula

Add intel_de_read64_2x32() wrapper for the uncore version of the same,
and use it to read the high and low frame registers. Avoid duplicating
code for existing helpers.

The slight functional difference is checking that the entire high
register remains the same across two reads, instead of just the part
we're interested in. This should be of no consequence. (Unless those
bits function as a PRNG.)

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_de.h |  7 ++
 drivers/gpu/drm/i915/display/intel_vblank.c | 25 +
 2 files changed, 13 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_de.h 
b/drivers/gpu/drm/i915/display/intel_de.h
index 3dbd76fdabd6..42552d8c151e 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -22,6 +22,13 @@ intel_de_read8(struct drm_i915_private *i915, i915_reg_t reg)
return intel_uncore_read8(&i915->uncore, reg);
 }
 
+static inline u64
+intel_de_read64_2x32(struct drm_i915_private *i915,
+i915_reg_t lower_reg, i915_reg_t upper_reg)
+{
+   return intel_uncore_read64_2x32(&i915->uncore, lower_reg, upper_reg);
+}
+
 static inline void
 intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c 
b/drivers/gpu/drm/i915/display/intel_vblank.c
index cf1215631b27..729c39180469 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -68,9 +68,8 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
struct drm_vblank_crtc *vblank = 
&dev_priv->drm.vblank[drm_crtc_index(crtc)];
const struct drm_display_mode *mode = &vblank->hwmode;
enum pipe pipe = to_intel_crtc(crtc)->pipe;
-   i915_reg_t high_frame, low_frame;
-   u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
-   unsigned long irqflags;
+   u32 pixel, vbl_start, hsync_start, htotal;
+   u64 frame;
 
/*
 * On i965gm TV output the frame counter only works up to
@@ -98,34 +97,22 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
/* Start of vblank event occurs at start of hsync */
vbl_start -= htotal - hsync_start;
 
-   high_frame = PIPEFRAME(pipe);
-   low_frame = PIPEFRAMEPIXEL(pipe);
-
-   spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
/*
 * High & low register fields aren't synchronized, so make sure
 * we get a low value that's stable across two reads of the high
 * register.
 */
-   do {
-   high1 = intel_de_read_fw(dev_priv, high_frame) & 
PIPE_FRAME_HIGH_MASK;
-   low   = intel_de_read_fw(dev_priv, low_frame);
-   high2 = intel_de_read_fw(dev_priv, high_frame) & 
PIPE_FRAME_HIGH_MASK;
-   } while (high1 != high2);
-
-   spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+   frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(pipe), 
PIPEFRAME(pipe));
 
-   high1 >>= PIPE_FRAME_HIGH_SHIFT;
-   pixel = low & PIPE_PIXEL_MASK;
-   low >>= PIPE_FRAME_LOW_SHIFT;
+   pixel = frame & PIPE_PIXEL_MASK;
+   frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xff;
 
/*
 * The frame counter increments at beginning of active.
 * Cook up a vblank counter by also checking the pixel
 * counter against vblank start.
 */
-   return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xff;
+   return (frame + (pixel >= vbl_start)) & 0xff;
 }
 
 u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
-- 
2.34.1

[Intel-gfx] [PATCH 7/7] drm/i915/reg: split out vblank/scanline regs

2022-12-12 Thread Jani Nikula

Reduce clutter in i915_reg.h by splitting out the vblank/scanline
registers.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_crt.c  |  1 +
 drivers/gpu/drm/i915/display/intel_vblank.c   |  1 +
 .../gpu/drm/i915/display/intel_vblank_regs.h  | 42 +++
 drivers/gpu/drm/i915/gvt/cmd_parser.c |  1 +
 drivers/gpu/drm/i915/gvt/display.c|  1 +
 drivers/gpu/drm/i915/gvt/handlers.c   |  1 +
 drivers/gpu/drm/i915/i915_reg.h   | 35 
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |  1 +
 8 files changed, 48 insertions(+), 35 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_vblank_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c 
b/drivers/gpu/drm/i915/display/intel_crt.c
index 7267ffc7f539..e7482fc9f726 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -49,6 +49,7 @@
 #include "intel_hotplug.h"
 #include "intel_pch_display.h"
 #include "intel_pch_refclk.h"
+#include "intel_vblank_regs.h"
 
 /* Here's the desired hotplug mode */
 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |   \
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c 
b/drivers/gpu/drm/i915/display/intel_vblank.c
index 729c39180469..b017c2d00a3b 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -8,6 +8,7 @@
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_vblank.h"
+#include "intel_vblank_regs.h"
 
 /*
  * This timing diagram depicts the video signal in and
diff --git a/drivers/gpu/drm/i915/display/intel_vblank_regs.h 
b/drivers/gpu/drm/i915/display/intel_vblank_regs.h
new file mode 100644
index ..a851255ac2f1
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_vblank_regs.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_VBLANK_REGS_H__
+#define __INTEL_VBLANK_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _PIPEADSL  0x7
+#define   PIPEDSL_CURR_FIELD   REG_BIT(31) /* ctg+ */
+#define   PIPEDSL_LINE_MASKREG_GENMASK(19, 0)
+#define PIPEDSL(pipe)  _MMIO_PIPE2(pipe, _PIPEADSL)
+
+/*
+ * The two pipe frame counter registers are not synchronized, so reading a
+ * stable value is somewhat tricky. Use:
+ *
+ * u64 frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(pipe), 
PIPEFRAME(pipe));
+ */
+
+#define _PIPEAFRAMEHIGH  0x70040
+#define PIPEFRAME(pipe)_MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
+#define   PIPE_FRAME_HIGH_MASK 0x
+#define   PIPE_FRAME_HIGH_SHIFT0
+
+#define _PIPEAFRAMEPIXEL   0x70044
+#define PIPEFRAMEPIXEL(pipe)   _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
+#define   PIPE_FRAME_LOW_MASK  0xff00
+#define   PIPE_FRAME_LOW_SHIFT 24
+#define   PIPE_PIXEL_MASK  0x00ff
+#define   PIPE_PIXEL_SHIFT 0
+
+/* GM45+ just has to be different */
+#define _PIPEA_FRMCOUNT_G4X0x70040
+#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
+
+#define _PIPEA_FLIPCOUNT_G4X   0x70044
+#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
+
+#endif /* __INTEL_VBLANK_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c 
b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 0ebf5fbf0e39..8a72c75943c6 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -38,6 +38,7 @@
 
 #include "i915_drv.h"
 #include "i915_reg.h"
+#include "display/intel_vblank_regs.h"
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gpu_commands.h"
 #include "gt/intel_gt_regs.h"
diff --git a/drivers/gpu/drm/i915/gvt/display.c 
b/drivers/gpu/drm/i915/gvt/display.c
index c033249e73f4..894c8497961f 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -37,6 +37,7 @@
 #include "gvt.h"
 
 #include "display/intel_dpio_phy.h"
+#include "display/intel_vblank_regs.h"
 
 static int get_edp_pipe(struct intel_vgpu *vgpu)
 {
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c 
b/drivers/gpu/drm/i915/gvt/handlers.c
index 735fc83e7026..efd613c2e068 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -45,6 +45,7 @@
 #include "display/intel_dmc_regs.h"
 #include "display/intel_dpio_phy.h"
 #include "display/intel_fbc.h"
+#include "display/intel_vblank_regs.h"
 #include "display/vlv_dsi_pll_regs.h"
 #include "gt/intel_gt_regs.h"
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2b7a63754e4d..f3d9797ceb52 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3489,9 +3489,6 @@
 /* Display & cursor control */
 
 /* Pipe A */
-#define _PIPEADSL  0x7
-#define   PIPEDSL_CURR_FIELD   REG_BIT(31) /* ctg+ */
-#define   PIPEDSL_LINE_MASKREG_GENMASK(19, 0)
 #define _PIPEACONF 0x70008

[Intel-gfx] [PATCH 4/7] drm/i915/hdmi: abstract scanline range wait into intel_vblank.[ch]

2022-12-12 Thread Jani Nikula

Let's not have scanline waits inline in hdmi code.

This kind of waits should really have timeouts; add a FIXME comment.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_hdmi.c   |  9 ++---
 drivers/gpu/drm/i915/display/intel_vblank.c | 14 ++
 drivers/gpu/drm/i915/display/intel_vblank.h |  1 +
 3 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c 
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index e82f8a07e2b0..af6ef665368e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -56,6 +56,7 @@
 #include "intel_lspcon.h"
 #include "intel_panel.h"
 #include "intel_snps_phy.h"
+#include "intel_vblank.h"
 
 static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi 
*intel_hdmi)
 {
@@ -1476,15 +1477,9 @@ static int kbl_repositioning_enc_en_signal(struct 
intel_connector *connector,
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_digital_port *dig_port = 
intel_attached_dig_port(connector);
struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
-   u32 scanline;
int ret;
 
-   for (;;) {
-   scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
-   if (scanline > 100 && scanline < 200)
-   break;
-   usleep_range(25, 50);
-   }
+   intel_wait_for_pipe_scanline_range(crtc, 100, 200);
 
ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
 false, TRANS_DDI_HDCP_SIGNALLING);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c 
b/drivers/gpu/drm/i915/display/intel_vblank.c
index f25ec643a0a3..aec7758ef917 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -452,3 +452,17 @@ void intel_wait_for_pipe_scanline_moving(struct intel_crtc 
*crtc)
 {
wait_for_pipe_scanline_moving(crtc, true);
 }
+
+void intel_wait_for_pipe_scanline_range(struct intel_crtc *crtc, u32 start, 
u32 end)
+{
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   u32 scanline;
+
+   /* FIXME: This needs to timeout and/or check that scanline is moving. */
+   for (;;) {
+   scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
+   if (scanline > start && scanline < end)
+   break;
+   usleep_range(25, 50);
+   }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h 
b/drivers/gpu/drm/i915/display/intel_vblank.h
index 54870cabd734..e88addfccea8 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.h
+++ b/drivers/gpu/drm/i915/display/intel_vblank.h
@@ -19,5 +19,6 @@ bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, 
int *max_error,
 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc);
 void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc);
+void intel_wait_for_pipe_scanline_range(struct intel_crtc *crtc, u32 start, 
u32 end);
 
 #endif /* __INTEL_VBLANK_H__ */
-- 
2.34.1

[Intel-gfx] [PATCH 3/7] drm/i915/display: use common function for checking scanline is moving

2022-12-12 Thread Jani Nikula

cpt_verify_modeset() is roughly the same as
intel_wait_for_pipe_scanline_moving(). Assume it's close enough.

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_display.c | 18 +-
 1 file changed, 1 insertion(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 0cdb514d7ee0..ef15cc2b1fa9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1062,22 +1062,6 @@ intel_get_crtc_new_encoder(const struct 
intel_atomic_state *state,
return encoder;
 }
 
-static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
-  enum pipe pipe)
-{
-   i915_reg_t dslreg = PIPEDSL(pipe);
-   u32 temp;
-
-   temp = intel_de_read(dev_priv, dslreg);
-   udelay(500);
-   if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
-   if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
-   drm_err(&dev_priv->drm,
-   "mode set failed: pipe %c stuck\n",
-   pipe_name(pipe));
-   }
-}
-
 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -1772,7 +1756,7 @@ static void ilk_crtc_enable(struct intel_atomic_state 
*state,
intel_encoders_enable(state, crtc);
 
if (HAS_PCH_CPT(dev_priv))
-   cpt_verify_modeset(dev_priv, pipe);
+   intel_wait_for_pipe_scanline_moving(crtc);
 
/*
 * Must wait for vblank to avoid spurious PCH FIFO underruns.
-- 
2.34.1

[Intel-gfx] [PATCH 2/7] drm/i915/display: move more scanline functions to intel_vblank.[ch]

2022-12-12 Thread Jani Nikula

Reduce clutter in intel_display.c by moving the scanline moving/stopped
wait functions to intel_vblank.[ch].

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_display.c | 36 +---
 drivers/gpu/drm/i915/display/intel_vblank.c  | 35 +++
 drivers/gpu/drm/i915/display/intel_vblank.h  |  2 ++
 3 files changed, 38 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 6cdfdae2c712..0cdb514d7ee0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -115,6 +115,7 @@
 #include "intel_quirks.h"
 #include "intel_sprite.h"
 #include "intel_tc.h"
+#include "intel_vblank.h"
 #include "intel_vga.h"
 #include "i9xx_plane.h"
 #include "skl_scaler.h"
@@ -386,41 +387,6 @@ struct intel_crtc *intel_master_crtc(const struct 
intel_crtc_state *crtc_state)
return to_intel_crtc(crtc_state->uapi.crtc);
 }
 
-static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
-   enum pipe pipe)
-{
-   i915_reg_t reg = PIPEDSL(pipe);
-   u32 line1, line2;
-
-   line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
-   msleep(5);
-   line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
-
-   return line1 != line2;
-}
-
-static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
-{
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   enum pipe pipe = crtc->pipe;
-
-   /* Wait for the display line to settle/start moving */
-   if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
-   drm_err(&dev_priv->drm,
-   "pipe %c scanline %s wait timed out\n",
-   pipe_name(pipe), str_on_off(state));
-}
-
-static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
-{
-   wait_for_pipe_scanline_moving(crtc, false);
-}
-
-static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
-{
-   wait_for_pipe_scanline_moving(crtc, true);
-}
-
 static void
 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c 
b/drivers/gpu/drm/i915/display/intel_vblank.c
index 78a579496ad1..f25ec643a0a3 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -417,3 +417,38 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc)
 
return position;
 }
+
+static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
+   enum pipe pipe)
+{
+   i915_reg_t reg = PIPEDSL(pipe);
+   u32 line1, line2;
+
+   line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
+   msleep(5);
+   line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
+
+   return line1 != line2;
+}
+
+static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
+{
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   enum pipe pipe = crtc->pipe;
+
+   /* Wait for the display line to settle/start moving */
+   if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
+   drm_err(&dev_priv->drm,
+   "pipe %c scanline %s wait timed out\n",
+   pipe_name(pipe), str_on_off(state));
+}
+
+void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
+{
+   wait_for_pipe_scanline_moving(crtc, false);
+}
+
+void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
+{
+   wait_for_pipe_scanline_moving(crtc, true);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h 
b/drivers/gpu/drm/i915/display/intel_vblank.h
index 9c0034d7454d..54870cabd734 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.h
+++ b/drivers/gpu/drm/i915/display/intel_vblank.h
@@ -17,5 +17,7 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc);
 bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
 ktime_t *vblank_time, bool in_vblank_irq);
 int intel_get_crtc_scanline(struct intel_crtc *crtc);
+void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc);
+void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc);
 
 #endif /* __INTEL_VBLANK_H__ */
-- 
2.34.1

[Intel-gfx] [PATCH 1/7] drm/i915/irq: split out vblank/scanline code to intel_vblank.[ch]

2022-12-12 Thread Jani Nikula

The vblank/scanline code is fairly isolated in i915_irq.c. Split it out
to new intel_vblank.[ch].

Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/display/intel_crtc.c |   1 +
 .../drm/i915/display/intel_display_trace.h|   1 +
 drivers/gpu/drm/i915/display/intel_vblank.c   | 419 ++
 drivers/gpu/drm/i915/display/intel_vblank.h   |  21 +
 drivers/gpu/drm/i915/i915_irq.c   | 408 -
 drivers/gpu/drm/i915/i915_irq.h   |   6 -
 7 files changed, 443 insertions(+), 414 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_vblank.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_vblank.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index dfa211451a1d..fc6d7885ad1d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -263,6 +263,7 @@ i915-y += \
display/intel_quirks.o \
display/intel_sprite.o \
display/intel_tc.o \
+   display/intel_vblank.o \
display/intel_vga.o \
display/i9xx_plane.o \
display/skl_scaler.o \
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c 
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 037fc140b585..82be0fbe9934 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -28,6 +28,7 @@
 #include "intel_pipe_crc.h"
 #include "intel_psr.h"
 #include "intel_sprite.h"
+#include "intel_vblank.h"
 #include "intel_vrr.h"
 #include "skl_universal_plane.h"
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_trace.h 
b/drivers/gpu/drm/i915/display/intel_display_trace.h
index 725aba3fa531..651ea8564e1b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_trace.h
+++ b/drivers/gpu/drm/i915/display/intel_display_trace.h
@@ -17,6 +17,7 @@
 #include "i915_irq.h"
 #include "intel_crtc.h"
 #include "intel_display_types.h"
+#include "intel_vblank.h"
 
 #define __dev_name_i915(i915) dev_name((i915)->drm.dev)
 #define __dev_name_kms(obj) dev_name((obj)->base.dev->dev)
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c 
b/drivers/gpu/drm/i915/display/intel_vblank.c
new file mode 100644
index ..78a579496ad1
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -0,0 +1,419 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "i915_reg.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+#include "intel_vblank.h"
+
+/*
+ * This timing diagram depicts the video signal in and
+ * around the vertical blanking period.
+ *
+ * Assumptions about the fictitious mode used in this example:
+ *  vblank_start >= 3
+ *  vsync_start = vblank_start + 1
+ *  vsync_end = vblank_start + 2
+ *  vtotal = vblank_start + 3
+ *
+ *   start of vblank:
+ *   latch double buffered registers
+ *   increment frame counter (ctg+)
+ *   generate start of vblank interrupt (gen4+)
+ *   |
+ *   |  frame start:
+ *   |  generate frame start interrupt (aka. vblank interrupt) 
(gmch)
+ *   |  may be shifted forward 1-3 extra lines via PIPECONF
+ *   |  |
+ *   |  |  start of vsync:
+ *   |  |  generate vsync interrupt
+ *   |  |  |
+ * ______________________________
___
+ *   .   \hs/   .  \hs/  \hs/  \hs/   .  \hs/
+ * va---> <-vb> 
 |
+ * -vbs-> <---vbs+1---> <---vbs+2---> <-0-> <-1-> 
<-2--- (scanline counter gen2)
+ * -vbs-2---> <---vbs-1---> <---vbs-> <---vbs+1---> <---vbs+2---> 
<-0--- (scanline counter gen3+)
+ * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-> <---vbs+1---> 
<---vbs+2- (scanline counter hsw+ hdmi)
+ *   |  | |
+ *   last visible pixel   first visible 
pixel
+ *  | increment frame 
counter (gen3/4)
+ *  pixel counter = vblank_start * htotal pixel counter = 
0 (gen3/4)
+ *
+ * x  = horizontal active
+ * _  = horizontal blanking
+ * hs = horizontal sync
+ * va = vertical active
+ * vb = vertical blanking
+ * vs = vertical sync
+ * vbs = vblank_start (number)
+ *
+ * Summary:
+ * - most events happen at the start of horizontal sync
+ * - frame start happens at the start of horizontal blank, 1-4 lines
+ *   (depending on PIPECONF settings) after the start of vblank
+ * - gen3/4 pixel and frame counter are synchronized with the start
+ *   of horizontal active on the first line of vertical active
+ */
+
+/*
+ * Called from drm generic code, passed a 'crtc',

[Intel-gfx] [PATCH 0/7] drm/i915: extract vblank/scanline code to a separate file

2022-12-12 Thread Jani Nikula

Add new intel_vblank.[ch] and dump a bunch of the vblank/scanline code
there.

Jani Nikula (7):
  drm/i915/irq: split out vblank/scanline code to intel_vblank.[ch]
  drm/i915/display: move more scanline functions to intel_vblank.[ch]
  drm/i915/display: use common function for checking scanline is moving
  drm/i915/hdmi: abstract scanline range wait into intel_vblank.[ch]
  drm/i915/vblank: use intel_de_read()
  drm/i915/vblank: add and use intel_de_read64_2x32() to read vblank
counter
  drm/i915/reg: split out vblank/scanline regs

 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/display/intel_crt.c  |   1 +
 drivers/gpu/drm/i915/display/intel_crtc.c |   1 +
 drivers/gpu/drm/i915/display/intel_de.h   |   7 +
 drivers/gpu/drm/i915/display/intel_display.c  |  54 +--
 .../drm/i915/display/intel_display_trace.h|   1 +
 drivers/gpu/drm/i915/display/intel_hdmi.c |   9 +-
 drivers/gpu/drm/i915/display/intel_vblank.c   | 456 ++
 drivers/gpu/drm/i915/display/intel_vblank.h   |  24 +
 .../gpu/drm/i915/display/intel_vblank_regs.h  |  42 ++
 drivers/gpu/drm/i915/gvt/cmd_parser.c |   1 +
 drivers/gpu/drm/i915/gvt/display.c|   1 +
 drivers/gpu/drm/i915/gvt/handlers.c   |   1 +
 drivers/gpu/drm/i915/i915_irq.c   | 408 
 drivers/gpu/drm/i915/i915_irq.h   |   6 -
 drivers/gpu/drm/i915/i915_reg.h   |  35 --
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |   1 +
 17 files changed, 541 insertions(+), 508 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_vblank.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_vblank.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_vblank_regs.h

-- 
2.34.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence
URL   : https://patchwork.freedesktop.org/series/111850/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12493 -> Patchwork_111850v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/index.html

Participating hosts (40 -> 24)
--

  Missing(16): fi-kbl-soraka bat-kbl-2 bat-adls-5 bat-adlp-9 bat-dg1-5 
fi-bsw-n3050 bat-dg2-8 bat-adlm-1 bat-dg2-9 bat-adlp-6 bat-adlp-4 fi-hsw-4770 
bat-jsl-3 bat-dg2-11 fi-bsw-nick fi-skl-6600u 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_111850v1:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@workarounds:
- {bat-rplp-1}:   [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/bat-rplp-1/igt@i915_selftest@l...@workarounds.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/bat-rplp-1/igt@i915_selftest@l...@workarounds.html

  
Known issues


  Here are the changes found in Patchwork_111850v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@mman:
- fi-rkl-guc: [PASS][3] -> [TIMEOUT][4] ([i915#6794])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/fi-rkl-guc/igt@i915_selftest@l...@mman.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/fi-rkl-guc/igt@i915_selftest@l...@mman.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600:   [PASS][5] -> [INCOMPLETE][6] ([i915#4817])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}:   [DMESG-WARN][7] ([i915#6434]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12493/bat-rpls-2/igt@i915_pm_...@module-reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/bat-rpls-2/igt@i915_pm_...@module-reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
  [i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
  [i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794


Build changes
-

  * Linux: CI_DRM_12493 -> Patchwork_111850v1

  CI-20190529: 20190529
  CI_DRM_12493: a6dc4d045339e2817103e99539e3efaa554c941f @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7090: 5aafcf060b6dfbb2fa7aace76c8074d98ac7da8f @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111850v1: a6dc4d045339e2817103e99539e3efaa554c941f @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

8d94e2693fce drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111850v1/index.html

[Intel-gfx] [PATCH] drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence

2022-12-12 Thread Jani Nikula

Starting from ICL, the default for MIPI GPIO sequences seems to be using
native GPIOs i.e. GPIOs available in the GPU. These native GPIOs reuse
many pins that quite frankly seem scary to poke based on the VBT
sequences. We pretty much have to trust that the board is configured
such that the relevant HPD, PP_CONTROL and GPIO bits aren't used for
anything else.

MIPI sequence v4 also adds a flag to fall back to non-native sequences.

v2:
- Fix HPD pin output set (impacts GPIOs 0 and 5)
- Fix GPIO data output direction set (impacts GPIOs 4 and 9)
- Reduce register accesses to single intel_de_rwm()

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6131
Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 84 +++-
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 2 files changed, 82 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c 
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index fce69fa446d5..18c6c2153076 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -41,9 +41,11 @@
 
 #include "i915_drv.h"
 #include "i915_reg.h"
+#include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_dsi.h"
 #include "intel_dsi_vbt.h"
+#include "intel_gmbus_regs.h"
 #include "vlv_dsi.h"
 #include "vlv_dsi_regs.h"
 #include "vlv_sideband.h"
@@ -377,6 +379,75 @@ static void icl_exec_gpio(struct intel_connector 
*connector,
drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
 }
 
+enum {
+   MIPI_RESET_1 = 0,
+   MIPI_AVDD_EN_1,
+   MIPI_BKLT_EN_1,
+   MIPI_AVEE_EN_1,
+   MIPI_VIO_EN_1,
+   MIPI_RESET_2,
+   MIPI_AVDD_EN_2,
+   MIPI_BKLT_EN_2,
+   MIPI_AVEE_EN_2,
+   MIPI_VIO_EN_2,
+};
+
+static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
+ int gpio, bool value)
+{
+   int index;
+
+   if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 11 && gpio >= 
MIPI_RESET_2))
+   return;
+
+   switch (gpio) {
+   case MIPI_RESET_1:
+   case MIPI_RESET_2:
+   index = gpio == MIPI_RESET_1 ? HPD_PORT_A : HPD_PORT_B;
+
+   /* Disable HPD to set the pin to output, and set output value */
+   intel_de_rmw(dev_priv, SHOTPLUG_CTL_DDI,
+SHOTPLUG_CTL_DDI_HPD_ENABLE(index) |
+SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index),
+value ? SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index) : 
0);
+   break;
+   case MIPI_AVDD_EN_1:
+   case MIPI_AVDD_EN_2:
+   index = gpio == MIPI_AVDD_EN_1 ? 0 : 1;
+
+   intel_de_rmw(dev_priv, PP_CONTROL(index), PANEL_POWER_ON,
+value ? PANEL_POWER_ON : 0);
+   break;
+   case MIPI_BKLT_EN_1:
+   case MIPI_BKLT_EN_2:
+   index = gpio == MIPI_AVDD_EN_1 ? 0 : 1;
+
+   intel_de_rmw(dev_priv, PP_CONTROL(index), EDP_BLC_ENABLE,
+value ? EDP_BLC_ENABLE : 0);
+   break;
+   case MIPI_AVEE_EN_1:
+   case MIPI_AVEE_EN_2:
+   index = gpio == MIPI_AVEE_EN_1 ? 1 : 2;
+
+   intel_de_rmw(dev_priv, GPIO(dev_priv, index),
+GPIO_CLOCK_VAL_OUT,
+GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT |
+GPIO_CLOCK_VAL_MASK | value ? GPIO_CLOCK_VAL_OUT : 
0);
+   break;
+   case MIPI_VIO_EN_1:
+   case MIPI_VIO_EN_2:
+   index = gpio == MIPI_VIO_EN_1 ? 1 : 2;
+
+   intel_de_rmw(dev_priv, GPIO(dev_priv, index),
+GPIO_DATA_VAL_OUT,
+GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT |
+GPIO_DATA_VAL_MASK | value ? GPIO_DATA_VAL_OUT : 
0);
+   break;
+   default:
+   MISSING_CASE(gpio);
+   }
+}
+
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 {
struct drm_device *dev = intel_dsi->base.base.dev;
@@ -384,8 +455,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
struct intel_connector *connector = intel_dsi->attached_connector;
u8 gpio_source, gpio_index = 0, gpio_number;
bool value;
-
-   drm_dbg_kms(&dev_priv->drm, "\n");
+   bool native = DISPLAY_VER(dev_priv) >= 11;
 
if (connector->panel.vbt.dsi.seq_version >= 3)
gpio_index = *data++;
@@ -398,10 +468,18 @@ static const u8 *mipi_exec_gpio(struct intel_dsi 
*intel_dsi, const u8 *data)
else
gpio_source = 0;
 
+   if (connector->panel.vbt.dsi.seq_version >= 4 && *data & BIT(1))
+   native = false;
+
/* pull up/down */
value = *data++ & 1;
 
-   if (DISPLAY_VER(dev_priv) >= 1

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/mtl: Add OA support by enabling 32 bit OAG formats for MTL

2022-12-12 Thread Joonas Lahtinen

(Switching to my @linux.intel.com address)

Quoting Umesh Nerlige Ramappa (2022-12-08 19:08:46)
> On Wed, Nov 30, 2022 at 05:05:35PM -0800, Umesh Nerlige Ramappa wrote:
> >Without an entry in oa_init_supported_formats, OA will not be functional
> >in MTL. Enable OA support by enabling 32 bit OAG formats for MTL.
> >
> Thanks Lionel for sharing the Mesa MR for MTL -
> https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20228

We should not merge the userspace changes ahead of the kernel changes.
They should be ready and reviewed, but not merged.

Umesh and Lionel, please re-read the requirements for merging new uAPI:

https://www.kernel.org/doc/html/latest/gpu/drm-uapi.html#open-source-userspace-requirements

The order is clearly documented there:

"The kernel patch can only be merged after all the above requirements are met, 
but it must be merged to either drm-next or drm-misc-next before the userspace 
patches land."

To follow that, please revert the Mesa changes for now and follow the right
ordering.

Regards, Joonas

> 
> Regards,
> Umesh
> 
> >Signed-off-by: Umesh Nerlige Ramappa 
> >---
> > drivers/gpu/drm/i915/i915_perf.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_perf.c 
> >b/drivers/gpu/drm/i915/i915_perf.c
> >index 8369ae4b850d..a735b9540113 100644
> >--- a/drivers/gpu/drm/i915/i915_perf.c
> >+++ b/drivers/gpu/drm/i915/i915_perf.c
> >@@ -4772,6 +4772,7 @@ static void oa_init_supported_formats(struct i915_perf 
> >*perf)
> >   break;
> >
> >   case INTEL_DG2:
> >+  case INTEL_METEORLAKE:
> >   oa_format_add(perf, I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
> >   oa_format_add(perf, I915_OA_FORMAT_A24u40_A14u32_B8_C8);
> >   break;
> >-- 
> >2.36.1
> >

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Enable VDIP Enable VSC whenever GMP DIP enabled (rev2)

2022-12-12 Thread Patchwork

== Series Details ==

Series: drm/i915/display: Enable VDIP Enable VSC whenever GMP DIP enabled (rev2)
URL   : https://patchwork.freedesktop.org/series/111835/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12491_full -> Patchwork_111835v2_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_111835v2_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111835v2_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (14 -> 14)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_111835v2_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_fence@syncobj-export:
- shard-skl:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-skl1/igt@gem_exec_fe...@syncobj-export.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111835v2/shard-skl1/igt@gem_exec_fe...@syncobj-export.html

  * igt@gem_exec_schedule@deep@vcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111835v2/shard-skl4/igt@gem_exec_schedule@d...@vcs0.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_invalid_mode@bad-vsync-start:
- {shard-tglu-9}: NOTRUN -> [SKIP][4] +4 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111835v2/shard-tglu-9/igt@kms_invalid_m...@bad-vsync-start.html

  
Known issues


  Here are the changes found in Patchwork_111835v2_full that come from known 
issues:

### CI changes ###

 Possible fixes 

  * boot:
- shard-snb:  ([PASS][5], [PASS][6], [PASS][7], [PASS][8], 
[PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], 
[PASS][15], [PASS][16], [PASS][17], [PASS][18], [FAIL][19], [PASS][20], 
[PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], 
[PASS][27], [PASS][28], [PASS][29]) ([i915#4338]) -> ([PASS][30], [PASS][31], 
[PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], 
[PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], 
[PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], 
[PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb7/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb7/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb7/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb7/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb7/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb7/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb7/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb5/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb4/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb4/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb4/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb4/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb4/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb4/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb4/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12491/shard-snb4/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111835v2/shard-snb4/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111835v2/shard-snb5/boot

Re: [Intel-gfx] [PATCH 1/5] linux/minmax.h: add non-atomic version of xchg

2022-12-12 Thread David Laight

From: Andrzej Hajda 
> Sent: 09 December 2022 15:49
> 
> The pattern of setting variable with new value and returning old
> one is very common in kernel. Usually atomicity of the operation
> is not required, so xchg seems to be suboptimal and confusing in
> such cases. Since name xchg is already in use and __xchg is used
> in architecture code, proposition is to name the macro exchange.

Dunno, if it is non-atomic then two separate assignment statements
is decidedly more obvious and needs less brain cells to process.
Otherwise someone will assume 'something clever' is going on
and the operation is atomic.

David

-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, 
UK
Registration No: 1397386 (Wales)

Re: [Intel-gfx] [PATCH 3/5] drm/i915/gt: kill fetch_and_zero usage

2022-12-12 Thread Andrzej Hajda





On 12.12.2022 10:14, Upadhyay, Tejas wrote:



-Original Message-
From: Intel-gfx  On Behalf Of
Andrzej Hajda
Sent: Friday, December 9, 2022 9:19 PM
To: linux-ker...@vger.kernel.org; intel-gfx@lists.freedesktop.org; dri-
de...@lists.freedesktop.org
Cc: Hajda, Andrzej ; Arnd Bergmann
; Vivi, Rodrigo ; Andrew Morton
; Andy Shevchenko

Subject: [Intel-gfx] [PATCH 3/5] drm/i915/gt: kill fetch_and_zero usage

Better use recently introduced kernel core helper.

Signed-off-by: Andrzej Hajda 
---
  drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 +-
  drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 4 ++--
  drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4 ++--
  drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 ++--
  drivers/gpu/drm/i915/gt/intel_gsc.c  | 2 +-
  drivers/gpu/drm/i915/gt/intel_gt.c   | 4 ++--
  drivers/gpu/drm/i915/gt/intel_gt_pm.c| 2 +-
  drivers/gpu/drm/i915/gt/intel_lrc.c  | 6 +++---
  drivers/gpu/drm/i915/gt/intel_migrate.c  | 2 +-
  drivers/gpu/drm/i915/gt/intel_rc6.c  | 2 +-
  drivers/gpu/drm/i915/gt/intel_rps.c  | 2 +-
  drivers/gpu/drm/i915/gt/selftest_context.c   | 2 +-
  drivers/gpu/drm/i915/gt/selftest_ring_submission.c   | 2 +-
  drivers/gpu/drm/i915/gt/selftest_timeline.c  | 2 +-
  drivers/gpu/drm/i915/gt/uc/intel_uc.c| 2 +-
  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
  16 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c33e0d72d6702b..de318d96d52abd 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1024,7 +1024,7 @@ static void cleanup_status_page(struct
intel_engine_cs *engine)
/* Prevent writes into HWSP after returning the page to the system */
intel_engine_set_hwsp_writemask(engine, ~0u);

-   vma = fetch_and_zero(&engine->status_page.vma);
+   vma = exchange(&engine->status_page.vma, NULL);
if (!vma)
return;

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index 9a527e1f5be655..6029fafaaa674f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -229,7 +229,7 @@ static void heartbeat(struct work_struct *wrk)
mutex_unlock(&ce->timeline->mutex);
  out:
if (!engine->i915->params.enable_hangcheck ||
!next_heartbeat(engine))
-   i915_request_put(fetch_and_zero(&engine-

heartbeat.systole));

+   i915_request_put(exchange(&engine->heartbeat.systole, 0));
intel_engine_pm_put(engine);
  }

@@ -244,7 +244,7 @@ void intel_engine_unpark_heartbeat(struct
intel_engine_cs *engine)  void intel_engine_park_heartbeat(struct
intel_engine_cs *engine)  {
if (cancel_delayed_work(&engine->heartbeat.work))
-   i915_request_put(fetch_and_zero(&engine-

heartbeat.systole));

+   i915_request_put(exchange(&engine->heartbeat.systole, 0));
  }

  void intel_gt_unpark_heartbeats(struct intel_gt *gt) diff --git
a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 49a8f10d76c77b..29e78078d55a8b 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3197,7 +3197,7 @@ static void execlists_reset_cancel(struct
intel_engine_cs *engine)
RB_CLEAR_NODE(rb);

spin_lock(&ve->base.sched_engine->lock);
-   rq = fetch_and_zero(&ve->request);
+   rq = exchange(&ve->request, NULL);
if (rq) {
if (i915_request_mark_eio(rq)) {
rq->engine = engine;
@@ -3602,7 +3602,7 @@ static void rcu_virtual_context_destroy(struct
work_struct *wrk)

spin_lock_irq(&ve->base.sched_engine->lock);

-   old = fetch_and_zero(&ve->request);
+   old = exchange(&ve->request, NULL);
if (old) {
GEM_BUG_ON(!__i915_request_is_complete(old));
__i915_request_submit(old);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 0c7fe360f87331..2eb0173c6e968c 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -684,7 +684,7 @@ static void fini_aliasing_ppgtt(struct i915_ggtt *ggtt)  {
struct i915_ppgtt *ppgtt;

-   ppgtt = fetch_and_zero(&ggtt->alias);
+   ppgtt = exchange(&ggtt->alias, NULL);
if (!ppgtt)
return;

@@ -1238,7 +1238,7 @@ bool i915_ggtt_resume_vm(struct
i915_address_space *vm)
   was_bound);

if (obj) { /*

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