Re: [Intel-gfx] [PATCH v8 20/24] vfio: Add cdev for vfio_device
> From: Alex Williamson
> Sent: Thursday, March 30, 2023 3:57 AM
>
> On Mon, 27 Mar 2023 02:40:43 -0700
> Yi Liu wrote:
>
[...]
> > +/*
> > + * device access via the fd opened by this function is blocked until
> > + * .open_device() is called successfully during BIND_IOMMUFD.
> > + */
> > +int vfio_device_fops_cdev_open(struct inode *inode, struct file *filep)
> > +{
> > + struct vfio_device *device = container_of(inode->i_cdev,
> > + struct vfio_device, cdev);
> > + struct vfio_device_file *df;
> > + int ret;
> > +
> > + if (!vfio_device_try_get_registration(device))
> > + return -ENODEV;
> > +
> > + df = vfio_allocate_device_file(device);
> > + if (IS_ERR(df)) {
> > + ret = PTR_ERR(df);
> > + goto err_put_registration;
> > + }
> > +
> > + filep->private_data = df;
> > +
> > + return 0;
> > +
> > +err_put_registration:
> > + vfio_device_put_registration(device);
> > + return ret;
> > +}
> > +
[...]
> > diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
> > index 8e96aab27029..58fc3bb768f2 100644
> > --- a/drivers/vfio/vfio_main.c
> > +++ b/drivers/vfio/vfio_main.c
> > @@ -242,6 +242,7 @@ static int vfio_init_device(struct vfio_device *device,
> > struct
> device *dev,
> > device->device.release = vfio_device_release;
> > device->device.class = vfio.device_class;
> > device->device.parent = device->dev;
> > + vfio_init_device_cdev(device);
> > return 0;
> >
> > out_uninit:
> > @@ -280,7 +281,7 @@ static int __vfio_register_dev(struct vfio_device
> > *device,
> > if (ret)
> > goto err_out;
> >
> > - ret = device_add(>device);
> > + ret = vfio_device_add(device);
> > if (ret)
> > goto err_out;
> >
> > @@ -320,6 +321,12 @@ void vfio_unregister_group_dev(struct vfio_device
> > *device)
> > bool interrupted = false;
> > long rc;
> >
> > + /* Prevent new device opened in the group path */
> > + vfio_device_group_unregister(device);
> > +
> > + /* Prevent new device opened in the cdev path */
> > + vfio_device_del(device);
> > +
> > vfio_device_put_registration(device);
> > rc = try_wait_for_completion(>comp);
> > while (rc <= 0) {
> > @@ -343,11 +350,6 @@ void vfio_unregister_group_dev(struct vfio_device
> > *device)
> > }
> > }
> >
> > - vfio_device_group_unregister(device);
> > -
> > - /* Balances device_add in register path */
> > - device_del(>device);
> > -
>
> Why were these relocated? And additionally why was the comment
> regarding the balance operations dropped? The move seems unrelated to
> the patch here, so if it's actually advisable for some reason, it
> should be a separate patch. Thanks,
The reason for the relocation is to prevent new device which would result
in the device->refcount increasing. If the user keeps open device then the
device->refcount may keep increasing. Then the vfio_unregister_group_dev()
may be stuck here. This is rare, but possible.
By doing vfio_device_group_unregister(), the device is removed from the
group->device_list. Then user cannot open the device by
VFIO_GROUP_GET_DEVICE_FD.
Hence it won't increase the device->refcount. I agree with you, this should
be done in a separate patch.
Same reason for relocating device_del(>device); User may keep
opening the cdev to increase the device->refcount. Then the
vfio_device_group_unregister() path would be stuck as well. But this
relocation needs to be done here since user cannot do it if without cdev.
Last, need to keep the balance comment as well even the sequence
it not strictly mirrored. will keep the comment.
> Alex
>
> > /* Balances vfio_device_set_group in register path */
> > vfio_device_remove_group(device);
> > }
> > @@ -555,7 +557,8 @@ static int vfio_device_fops_release(struct inode *inode,
> struct file *filep)
> > struct vfio_device_file *df = filep->private_data;
> > struct vfio_device *device = df->device;
> >
> > - vfio_device_group_close(df);
> > + if (df->group)
> > + vfio_device_group_close(df);
> >
> > vfio_device_put_registration(device);
> >
Thanks,
Yi Liu
[Intel-gfx] ✓ Fi.CI.BAT: success for Add MTL PMU support for multi-gt
== Series Details == Series: Add MTL PMU support for multi-gt URL : https://patchwork.freedesktop.org/series/115836/ State : success == Summary == CI Bug Log - changes from CI_DRM_12937 -> Patchwork_115836v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v1/index.html Participating hosts (36 -> 35) -- Additional (1): fi-pnv-d510 Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_115836v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - bat-rpls-1: [PASS][1] -> [ABORT][2] ([i915#6687] / [i915#7978]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@migrate: - bat-dg2-11: [PASS][3] -> [DMESG-WARN][4] ([i915#7699]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-dg2-11/igt@i915_selftest@l...@migrate.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@mman: - bat-rpls-1: [PASS][5] -> [TIMEOUT][6] ([i915#6794]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-rpls-1/igt@i915_selftest@l...@mman.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v1/bat-rpls-1/igt@i915_selftest@l...@mman.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#7828]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1: - bat-dg2-8: [PASS][8] -> [FAIL][9] ([i915#7932]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html * igt@kms_pipe_crc_basic@read-crc: - bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#5354]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v1/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc.html * igt@kms_psr@primary_page_flip: - fi-pnv-d510:NOTRUN -> [SKIP][11] ([fdo#109271]) +38 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html Possible fixes * igt@i915_selftest@live@gt_heartbeat: - fi-glk-j4005: [DMESG-FAIL][12] ([i915#5334]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v1/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@hangcheck: - bat-dg2-11: [ABORT][14] ([i915#7913]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v1/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687 [i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932 [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978 Build changes - * IGT: IGT_7226 -> IGTPW_8716 * Linux: CI_DRM_12937 -> Patchwork_115836v1 CI-20190529: 20190529 CI_DRM_12937: 6848d3613c0a63382d00ff550c41394902bda903 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_8716: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8716/index.html IGT_7226: 41be8b4ab86f9e11388c10366dfd71e5032589c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_115836v1: 6848d3613c0a63382d00ff550c41394902bda903 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 5d29036213d8 drm/i915/pmu: Enable legacy PMU events for MTL d60928cf3de7 drm/i915/pmu: Split reading engine and other events into helpers 57ff3141158f drm/i915/pmu: Use a helper to convert to MHz
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add MTL PMU support for multi-gt
== Series Details == Series: Add MTL PMU support for multi-gt URL : https://patchwork.freedesktop.org/series/115836/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add MTL PMU support for multi-gt
== Series Details == Series: Add MTL PMU support for multi-gt URL : https://patchwork.freedesktop.org/series/115836/ State : warning == Summary == Error: dim checkpatch failed 11153695e917 drm/i915/pmu: Support PMU for all engines e81f792130c7 drm/i915/pmu: Skip sampling engines with no enabled counters ecedc375d617 drm/i915/pmu: Transform PMU parking code to be GT based 12bdfd2a45f4 drm/i915/pmu: Add reference counting to the sampling timer 927155f231d6 drm/i915/pmu: Prepare for multi-tile non-engine counters -:54: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #54: FILE: drivers/gpu/drm/i915/i915_pmu.c:99: + GEM_BUG_ON(config_gt_id(config)); -:103: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #103: FILE: drivers/gpu/drm/i915/i915_pmu.c:197: + GEM_BUG_ON(idx >= ARRAY_SIZE(pmu->sample)); total: 0 errors, 2 warnings, 0 checks, 346 lines checked ab6717f2e5ca drm/i915/pmu: Export counters from all tiles 2a5e80bfe71e drm/i915/pmu: Use a helper to convert to MHz 3b4e837ed3d7 drm/i915/pmu: Split reading engine and other events into helpers 7d0b9b050afc drm/i915/pmu: Enable legacy PMU events for MTL -:241: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #241: FILE: drivers/gpu/drm/i915/i915_pmu.c:817: + GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count)); -:242: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #242: FILE: drivers/gpu/drm/i915/i915_pmu.c:818: + GEM_BUG_ON(pmu->enable_count[bit] == ~0); -:276: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #276: FILE: drivers/gpu/drm/i915/i915_pmu.c:909: + GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count)); -:277: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #277: FILE: drivers/gpu/drm/i915/i915_pmu.c:910: + GEM_BUG_ON(pmu->enable_count[bit] == 0); total: 0 errors, 4 warnings, 0 checks, 298 lines checked
Re: [Intel-gfx] [PATCH v2 10/10] vfio/pci: Add VFIO_DEVICE_GET_PCI_HOT_RESET_GROUP_INFO
> From: Tian, Kevin > Sent: Thursday, March 30, 2023 9:10 AM > > > From: Jason Gunthorpe > > Sent: Wednesday, March 29, 2023 11:50 PM > > > > On Wed, Mar 29, 2023 at 09:41:26AM +, Tian, Kevin wrote: > > > > > We could extend bind_iommufd to return the group id or introduce a > > > new ioctl to query it per dev_id. > > > > > Once that is in place looks we don't need a new _INFO ioctl? > > > > The iommu_group and the reset group are different things > > > > The issue is processing the BDF strings, not the group ID. > > > > Probably we should have some way for iommufd to report the group_id > > from the dev_id? > > > > Yes, that is my thought. Though iommu_group and reset group are > different things we could still leverage existing _INFO ioctl once there > is a way to associated dev_id to group_id. Please ignore this comment. Yes they are different things so even if a dev_id is in a group_id reported on a reset BDF string it doesn't mean this dev_id is in the reset group. Qemu can know that all affected devices are either owned by itself or not used by other processes if dev_id's opened by itself can be associated to all group_id's reported in the BDF strings. But it still lacks of information to tell the reset dependency within those opened devices within Qemu. So we do need a new _INFO ioctl for cdev. :/
Re: [Intel-gfx] [PATCH v2 10/10] vfio/pci: Add VFIO_DEVICE_GET_PCI_HOT_RESET_GROUP_INFO
> From: Jason Gunthorpe > Sent: Wednesday, March 29, 2023 11:58 PM > > On Wed, Mar 29, 2023 at 09:49:44AM -0600, Alex Williamson wrote: > > > > We could extend bind_iommufd to return the group id or introduce a > > > new ioctl to query it per dev_id. > > > > That would be ironic to go to all this trouble to remove groups from > > the API only to have them show up here. > > Groups always had to be part of the API for advanced cases like qemu - > the point was to make them a small side bit of information not front > and center in control of everything. Agree. > > > For example, devices within a group cannot be bound to separate > > iommufds due to lack of isolation, which is handled via DMA ownership, > > but barring DMA aliasing issues, due to conventional PCI buses or > > quirks, cdev could allow devices within the same group to be managed by > > separate IOAS's. > > Maybe some future kernel could do this, the API allows it at least.. > > > So the group information really isn't enough for > > userspace to infer address space restrictions with cdev anyway. > > > > Therefore aren't we expecting this to be denied at attach_ioas() and > > QEMU shouldn't be making these sorts of assumptions for cdev anyway? > > I guess we could make an API specifically to report same-iommu_domina > information? > > I was assuming qemu would use the group for now as I don't see a > likely future when we would relax that restriction.. So I was keeping > a "add it when we need it" attitude here. > IIRC we discussed this subgroup concept in the thread of reviewing my high level design proposal 2yrs ago. The consensus at the moment was that subgroup is architecturally allowed w/o DMA aliasing issues but we're yet to see a real demand of relaxing current group restriction to support it. Also with time moving newer platforms should have less multi-devices group so the need of subgroup is further decreased. So I'm also inclined to laying the existing group restriction with cdev for now. Then can we make a decision how this group_id might be reported? In nesting series we'll have a GET_INFO ioctl per dev_id. It could be extended to report group_id too. Or alternatively just return it in BIND_IOMMUFD together with dev_id.
Re: [Intel-gfx] [PATCH v2 10/10] vfio/pci: Add VFIO_DEVICE_GET_PCI_HOT_RESET_GROUP_INFO
> From: Jason Gunthorpe > Sent: Wednesday, March 29, 2023 11:50 PM > > On Wed, Mar 29, 2023 at 09:41:26AM +, Tian, Kevin wrote: > > > We could extend bind_iommufd to return the group id or introduce a > > new ioctl to query it per dev_id. > > > Once that is in place looks we don't need a new _INFO ioctl? > > The iommu_group and the reset group are different things > > The issue is processing the BDF strings, not the group ID. > > Probably we should have some way for iommufd to report the group_id > from the dev_id? > Yes, that is my thought. Though iommu_group and reset group are different things we could still leverage existing _INFO ioctl once there is a way to associated dev_id to group_id.
[Intel-gfx] [PATCH 7/9] drm/i915/pmu: Use a helper to convert to MHz
Use a helper to convert frequency values to MHz.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 2a5deabff088..40ce1dc00067 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -636,6 +636,11 @@ static int i915_pmu_event_init(struct perf_event *event)
return 0;
}
+static u64 read_sample_us(struct i915_pmu *pmu, unsigned int gt_id, int sample)
+{
+ return div_u64(read_sample(pmu, gt_id, sample), USEC_PER_SEC);
+}
+
static u64 __i915_pmu_event_read(struct perf_event *event)
{
struct drm_i915_private *i915 =
@@ -668,16 +673,10 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
switch (config) {
case I915_PMU_ACTUAL_FREQUENCY:
- val =
- div_u64(read_sample(pmu, gt_id,
- __I915_SAMPLE_FREQ_ACT),
- USEC_PER_SEC /* to MHz */);
+ val = read_sample_us(pmu, gt_id,
__I915_SAMPLE_FREQ_ACT);
break;
case I915_PMU_REQUESTED_FREQUENCY:
- val =
- div_u64(read_sample(pmu, gt_id,
- __I915_SAMPLE_FREQ_REQ),
- USEC_PER_SEC /* to MHz */);
+ val = read_sample_us(pmu, gt_id,
__I915_SAMPLE_FREQ_REQ);
break;
case I915_PMU_INTERRUPTS:
val = READ_ONCE(pmu->irq_count);
--
2.36.1
[Intel-gfx] [PATCH 5/9] drm/i915/pmu: Prepare for multi-tile non-engine counters
From: Tvrtko Ursulin
Reserve some bits in the counter config namespace which will carry the
tile id and prepare the code to handle this.
No per tile counters have been added yet.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_pmu.c | 153 +++-
drivers/gpu/drm/i915/i915_pmu.h | 9 +-
include/uapi/drm/i915_drm.h | 18 +++-
3 files changed, 132 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index c00b94c7f509..5d1de98d86b4 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -56,11 +56,21 @@ static bool is_engine_config(u64 config)
return config < __I915_PMU_OTHER(0);
}
+static unsigned int config_gt_id(const u64 config)
+{
+ return config >> __I915_PMU_GT_SHIFT;
+}
+
+static u64 config_counter(const u64 config)
+{
+ return config & ~(~0ULL << __I915_PMU_GT_SHIFT);
+}
+
static unsigned int other_bit(const u64 config)
{
unsigned int val;
- switch (config) {
+ switch (config_counter(config)) {
case I915_PMU_ACTUAL_FREQUENCY:
val = __I915_PMU_ACTUAL_FREQUENCY_ENABLED;
break;
@@ -78,15 +88,20 @@ static unsigned int other_bit(const u64 config)
return -1;
}
- return I915_ENGINE_SAMPLE_COUNT + val;
+ return I915_ENGINE_SAMPLE_COUNT +
+ config_gt_id(config) * __I915_PMU_TRACKED_EVENT_COUNT +
+ val;
}
static unsigned int config_bit(const u64 config)
{
- if (is_engine_config(config))
+ if (is_engine_config(config)) {
+ GEM_BUG_ON(config_gt_id(config));
+
return engine_config_sample(config);
- else
+ } else {
return other_bit(config);
+ }
}
static u64 config_mask(u64 config)
@@ -104,6 +119,18 @@ static unsigned int event_bit(struct perf_event *event)
return config_bit(event->attr.config);
}
+static u64 frequency_enabled_mask(void)
+{
+ unsigned int i;
+ u64 mask = 0;
+
+ for (i = 0; i < I915_PMU_MAX_GTS; i++)
+ mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) |
+ config_mask(__I915_PMU_REQUESTED_FREQUENCY(i));
+
+ return mask;
+}
+
static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
{
struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
@@ -120,9 +147,7 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool
gpu_active)
* Mask out all the ones which do not need the timer, or in
* other words keep all the ones that could need the timer.
*/
- enable &= config_mask(I915_PMU_ACTUAL_FREQUENCY) |
- config_mask(I915_PMU_REQUESTED_FREQUENCY) |
- ENGINE_SAMPLE_MASK;
+ enable &= frequency_enabled_mask() | ENGINE_SAMPLE_MASK;
/*
* When the GPU is idle per-engine counters do not need to be
@@ -164,9 +189,39 @@ static inline s64 ktime_since_raw(const ktime_t kt)
return ktime_to_ns(ktime_sub(ktime_get_raw(), kt));
}
+static unsigned int
+__sample_idx(struct i915_pmu *pmu, unsigned int gt_id, int sample)
+{
+ unsigned int idx = gt_id * __I915_NUM_PMU_SAMPLERS + sample;
+
+ GEM_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
+
+ return idx;
+}
+
+static u64 read_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample)
+{
+ return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur;
+}
+
+static void
+store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val)
+{
+ pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val;
+}
+
+static void
+add_sample_mult(struct i915_pmu *pmu, unsigned int gt_id, int sample, u32 val,
+ u32 mul)
+{
+ pmu->sample[__sample_idx(pmu, gt_id, sample)].cur +=
+ mul_u32_u32(val, mul);
+}
+
static u64 get_rc6(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
+ const unsigned int gt_id = gt->info.id;
struct i915_pmu *pmu = >pmu;
unsigned long flags;
bool awake = false;
@@ -181,7 +236,7 @@ static u64 get_rc6(struct intel_gt *gt)
spin_lock_irqsave(>lock, flags);
if (awake) {
- pmu->sample[__I915_SAMPLE_RC6].cur = val;
+ store_sample(pmu, gt_id, __I915_SAMPLE_RC6, val);
} else {
/*
* We think we are runtime suspended.
@@ -190,14 +245,14 @@ static u64 get_rc6(struct intel_gt *gt)
* on top of the last known real value, as the approximated RC6
* counter value.
*/
- val = ktime_since_raw(pmu->sleep_last);
- val += pmu->sample[__I915_SAMPLE_RC6].cur;
+ val = ktime_since_raw(pmu->sleep_last[gt_id]);
+ val += read_sample(pmu, gt_id, __I915_SAMPLE_RC6);
}
-
[Intel-gfx] [PATCH 0/7] Add MTL PMU support for multi-gt
With MTL, frequency and rc6 counters are specific to a gt. Export these counters via gt-specific events to the user space. Signed-off-by: Umesh Nerlige Ramappa Test-with: 20230330003656.1294873-1-umesh.nerlige.rama...@intel.com Tvrtko Ursulin (6): drm/i915/pmu: Support PMU for all engines drm/i915/pmu: Skip sampling engines with no enabled counters drm/i915/pmu: Transform PMU parking code to be GT based drm/i915/pmu: Add reference counting to the sampling timer drm/i915/pmu: Prepare for multi-tile non-engine counters drm/i915/pmu: Export counters from all tiles Umesh Nerlige Ramappa (3): drm/i915/pmu: Use a helper to convert to MHz drm/i915/pmu: Split reading engine and other events into helpers drm/i915/pmu: Enable legacy PMU events for MTL drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +- drivers/gpu/drm/i915/i915_pmu.c | 464 -- drivers/gpu/drm/i915/i915_pmu.h | 22 +- include/uapi/drm/i915_drm.h | 22 +- 4 files changed, 394 insertions(+), 118 deletions(-) -- 2.36.1
[Intel-gfx] [PATCH 4/9] drm/i915/pmu: Add reference counting to the sampling timer
From: Tvrtko Ursulin
We do not want to have timers per tile and waste CPU cycles and energy via
multiple wake-up sources, for a relatively un-important task of PMU
sampling, so keeping a single timer works well. But we also do not want
the first GT which goes idle to turn off the timer.
Add some reference counting, via a mask of unparked GTs, to solve this.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_pmu.c | 12 ++--
drivers/gpu/drm/i915/i915_pmu.h | 4
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 6f7f9b40860d..c00b94c7f509 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -251,7 +251,9 @@ void i915_pmu_gt_parked(struct intel_gt *gt)
* Signal sampling timer to stop if only engine events are enabled and
* GPU went idle.
*/
- pmu->timer_enabled = pmu_needs_timer(pmu, false);
+ pmu->unparked &= ~BIT(gt->info.id);
+ if (pmu->unparked == 0)
+ pmu->timer_enabled = pmu_needs_timer(pmu, false);
spin_unlock_irq(>lock);
}
@@ -268,7 +270,10 @@ void i915_pmu_gt_unparked(struct intel_gt *gt)
/*
* Re-enable sampling timer when GPU goes active.
*/
- __i915_pmu_maybe_start_timer(pmu);
+ if (pmu->unparked == 0)
+ __i915_pmu_maybe_start_timer(pmu);
+
+ pmu->unparked |= BIT(gt->info.id);
spin_unlock_irq(>lock);
}
@@ -438,6 +443,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
*/
for_each_gt(gt, i915, i) {
+ if (!(pmu->unparked & BIT(i)))
+ continue;
+
engines_sample(gt, period_ns);
/* Sample only gt0 until gt support is added for frequency */
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index d98fbc7a2f45..1b04c79907e8 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -76,6 +76,10 @@ struct i915_pmu {
* @lock: Lock protecting enable mask and ref count handling.
*/
spinlock_t lock;
+ /**
+* @unparked: GT unparked mask.
+*/
+ unsigned int unparked;
/**
* @timer: Timer for internal i915 PMU sampling.
*/
--
2.36.1
[Intel-gfx] [PATCH 1/9] drm/i915/pmu: Support PMU for all engines
From: Tvrtko Ursulin
Given how the metrics are already exported, we also need to run sampling
over engines from all GTs.
Problem of GT frequencies is left for later.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_pmu.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 7ece883a7d95..e274dba58629 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -10,6 +10,7 @@
#include "gt/intel_engine_pm.h"
#include "gt/intel_engine_regs.h"
#include "gt/intel_engine_user.h"
+#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_rc6.h"
@@ -414,8 +415,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
struct drm_i915_private *i915 =
container_of(hrtimer, struct drm_i915_private, pmu.timer);
struct i915_pmu *pmu = >pmu;
- struct intel_gt *gt = to_gt(i915);
unsigned int period_ns;
+ struct intel_gt *gt;
+ unsigned int i;
ktime_t now;
if (!READ_ONCE(pmu->timer_enabled))
@@ -431,8 +433,14 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
* grabbing the forcewake. However the potential error from timer call-
* back delay greatly dominates this so we keep it simple.
*/
- engines_sample(gt, period_ns);
- frequency_sample(gt, period_ns);
+
+ for_each_gt(gt, i915, i) {
+ engines_sample(gt, period_ns);
+
+ /* Sample only gt0 until gt support is added for frequency */
+ if (i == 0)
+ frequency_sample(gt, period_ns);
+ }
hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD));
--
2.36.1
[Intel-gfx] [PATCH 8/9] drm/i915/pmu: Split reading engine and other events into helpers
Split the event reading function into engine and other helpers.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 93 ++---
1 file changed, 52 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 40ce1dc00067..9bd9605d2662 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -641,58 +641,69 @@ static u64 read_sample_us(struct i915_pmu *pmu, unsigned
int gt_id, int sample)
return div_u64(read_sample(pmu, gt_id, sample), USEC_PER_SEC);
}
-static u64 __i915_pmu_event_read(struct perf_event *event)
+static u64 __i915_pmu_event_read_engine(struct perf_event *event)
{
- struct drm_i915_private *i915 =
- container_of(event->pmu, typeof(*i915), pmu.base);
- struct i915_pmu *pmu = >pmu;
+ struct drm_i915_private *i915 = container_of(event->pmu, typeof(*i915),
pmu.base);
+ u8 sample = engine_event_sample(event);
+ struct intel_engine_cs *engine;
u64 val = 0;
- if (is_engine_event(event)) {
- u8 sample = engine_event_sample(event);
- struct intel_engine_cs *engine;
-
- engine = intel_engine_lookup_user(i915,
- engine_event_class(event),
- engine_event_instance(event));
+ engine = intel_engine_lookup_user(i915,
+ engine_event_class(event),
+ engine_event_instance(event));
- if (drm_WARN_ON_ONCE(>drm, !engine)) {
- /* Do nothing */
- } else if (sample == I915_SAMPLE_BUSY &&
- intel_engine_supports_stats(engine)) {
- ktime_t unused;
+ if (drm_WARN_ON_ONCE(>drm, !engine)) {
+ /* Do nothing */
+ } else if (sample == I915_SAMPLE_BUSY &&
+ intel_engine_supports_stats(engine)) {
+ ktime_t unused;
- val = ktime_to_ns(intel_engine_get_busy_time(engine,
-));
- } else {
- val = engine->pmu.sample[sample].cur;
- }
+ val = ktime_to_ns(intel_engine_get_busy_time(engine,
+));
} else {
- const unsigned int gt_id = config_gt_id(event->attr.config);
- const u64 config = config_counter(event->attr.config);
-
- switch (config) {
- case I915_PMU_ACTUAL_FREQUENCY:
- val = read_sample_us(pmu, gt_id,
__I915_SAMPLE_FREQ_ACT);
- break;
- case I915_PMU_REQUESTED_FREQUENCY:
- val = read_sample_us(pmu, gt_id,
__I915_SAMPLE_FREQ_REQ);
- break;
- case I915_PMU_INTERRUPTS:
- val = READ_ONCE(pmu->irq_count);
- break;
- case I915_PMU_RC6_RESIDENCY:
- val = get_rc6(i915->gt[gt_id]);
- break;
- case I915_PMU_SOFTWARE_GT_AWAKE_TIME:
- val = ktime_to_ns(intel_gt_get_awake_time(to_gt(i915)));
- break;
- }
+ val = engine->pmu.sample[sample].cur;
}
return val;
}
+static u64 __i915_pmu_event_read_other(struct perf_event *event)
+{
+ struct drm_i915_private *i915 = container_of(event->pmu, typeof(*i915),
pmu.base);
+ const unsigned int gt_id = config_gt_id(event->attr.config);
+ const u64 config = config_counter(event->attr.config);
+ struct i915_pmu *pmu = >pmu;
+ u64 val = 0;
+
+ switch (config) {
+ case I915_PMU_ACTUAL_FREQUENCY:
+ val = read_sample_us(pmu, gt_id, __I915_SAMPLE_FREQ_ACT);
+ break;
+ case I915_PMU_REQUESTED_FREQUENCY:
+ val = read_sample_us(pmu, gt_id, __I915_SAMPLE_FREQ_REQ);
+ break;
+ case I915_PMU_INTERRUPTS:
+ val = READ_ONCE(pmu->irq_count);
+ break;
+ case I915_PMU_RC6_RESIDENCY:
+ val = get_rc6(i915->gt[gt_id]);
+ break;
+ case I915_PMU_SOFTWARE_GT_AWAKE_TIME:
+ val = ktime_to_ns(intel_gt_get_awake_time(to_gt(i915)));
+ break;
+ }
+
+ return val;
+}
+
+static u64 __i915_pmu_event_read(struct perf_event *event)
+{
+ if (is_engine_event(event))
+ return __i915_pmu_event_read_engine(event);
+ else
+ return __i915_pmu_event_read_other(event);
+}
+
static void i915_pmu_event_read(struct perf_event *event)
{
struct drm_i915_private *i915 =
--
2.36.1
[Intel-gfx] [PATCH 6/9] drm/i915/pmu: Export counters from all tiles
From: Tvrtko Ursulin
Start exporting frequency and RC6 counters from all tiles.
Existing counters keep their names and config values and new one use the
namespace added in the previous patch, with the "-gtN" added to their
names.
Interrupts counter is an odd one off. Because it is the global device
counters (not only GT) we choose not to add per tile versions for now.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Aravind Iddamsetty
---
drivers/gpu/drm/i915/i915_pmu.c | 96 ++---
1 file changed, 77 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 5d1de98d86b4..2a5deabff088 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -548,8 +548,9 @@ config_status(struct drm_i915_private *i915, u64 config)
struct intel_gt *gt = to_gt(i915);
unsigned int gt_id = config_gt_id(config);
+ unsigned int max_gt_id = HAS_EXTRA_GT_LIST(i915) ? 1 : 0;
- if (gt_id)
+ if (gt_id > max_gt_id)
return -ENOENT;
switch (config_counter(config)) {
@@ -563,6 +564,8 @@ config_status(struct drm_i915_private *i915, u64 config)
return -ENODEV;
break;
case I915_PMU_INTERRUPTS:
+ if (gt_id)
+ return -ENOENT;
break;
case I915_PMU_RC6_RESIDENCY:
if (!gt->rc6.supported)
@@ -932,9 +935,9 @@ static const struct attribute_group
i915_pmu_cpumask_attr_group = {
.attrs = i915_cpumask_attrs,
};
-#define __event(__config, __name, __unit) \
+#define __event(__counter, __name, __unit) \
{ \
- .config = (__config), \
+ .counter = (__counter), \
.name = (__name), \
.unit = (__unit), \
}
@@ -975,15 +978,21 @@ create_event_attributes(struct i915_pmu *pmu)
{
struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
static const struct {
- u64 config;
+ unsigned int counter;
const char *name;
const char *unit;
} events[] = {
- __event(I915_PMU_ACTUAL_FREQUENCY, "actual-frequency", "M"),
- __event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency",
"M"),
- __event(I915_PMU_INTERRUPTS, "interrupts", NULL),
- __event(I915_PMU_RC6_RESIDENCY, "rc6-residency", "ns"),
- __event(I915_PMU_SOFTWARE_GT_AWAKE_TIME,
"software-gt-awake-time", "ns"),
+ __event(0, "actual-frequency", "M"),
+ __event(1, "requested-frequency", "M"),
+ __event(3, "rc6-residency", "ns"),
+ __event(4, "software-gt-awake-time", "ns"),
+ };
+ static const struct {
+ unsigned int counter;
+ const char *name;
+ const char *unit;
+ } global_events[] = {
+ __event(2, "interrupts", NULL),
};
static const struct {
enum drm_i915_pmu_engine_sample sample;
@@ -998,14 +1007,29 @@ create_event_attributes(struct i915_pmu *pmu)
struct i915_ext_attribute *i915_attr = NULL, *i915_iter;
struct attribute **attr = NULL, **attr_iter;
struct intel_engine_cs *engine;
- unsigned int i;
+ struct intel_gt *gt;
+ unsigned int i, j;
/* Count how many counters we will be exposing. */
- for (i = 0; i < ARRAY_SIZE(events); i++) {
- if (!config_status(i915, events[i].config))
+ /* per gt counters */
+ for_each_gt(gt, i915, j) {
+ for (i = 0; i < ARRAY_SIZE(events); i++) {
+ u64 config = ___I915_PMU_OTHER(j, events[i].counter);
+
+ if (!config_status(i915, config))
+ count++;
+ }
+ }
+
+ /* global (per GPU) counters */
+ for (i = 0; i < ARRAY_SIZE(global_events); i++) {
+ u64 config = ___I915_PMU_OTHER(0, global_events[i].counter);
+
+ if (!config_status(i915, config))
count++;
}
+ /* per engine counters */
for_each_uabi_engine(engine, i915) {
for (i = 0; i < ARRAY_SIZE(engine_events); i++) {
if (!engine_event_status(engine,
@@ -1033,26 +1057,60 @@ create_event_attributes(struct i915_pmu *pmu)
attr_iter = attr;
/* Initialize supported non-engine counters. */
- for (i = 0; i < ARRAY_SIZE(events); i++) {
+ /* per gt counters */
+ for_each_gt(gt, i915, j) {
+ for (i = 0; i < ARRAY_SIZE(events); i++) {
+ u64 config = ___I915_PMU_OTHER(j, events[i].counter);
+ char *str;
+
+ if (config_status(i915, config))
+ continue;
+
+ str = kasprintf(GFP_KERNEL, "%s-gt%u",
+
[Intel-gfx] [PATCH 9/9] drm/i915/pmu: Enable legacy PMU events for MTL
MTL introduces separate GTs for render and media. This complicates the
definition of frequency and rc6 counters for the GPU as a whole since
each GT has an independent counter. The best way to support this change
is to deprecate the GPU-specific counters and create GT-specific
counters, however that just breaks ABI. Since perf tools and scripts may
be decentralized with probably many users, it's hard to deprecate the
legacy counters and have all the users on board with that.
Re-introduce the legacy counters and support them as min/max of
GT-specific counters as necessary to ensure backwards compatibility.
I915_PMU_ACTUAL_FREQUENCY - will show max of GT-specific counters
I915_PMU_REQUESTED_FREQUENCY - will show max of GT-specific counters
I915_PMU_INTERRUPTS - no changes since it is GPU specific on all platforms
I915_PMU_RC6_RESIDENCY - will show min of GT-specific counters
I915_PMU_SOFTWARE_GT_AWAKE_TIME - will show max of GT-specific counters
Note:
- For deeper debugging of performance issues, tools must be upgraded to
read the GT-specific counters.
- This patch deserves to be separate from the other PMU features so that
it can be easily dropped if legacy events are ever deprecated.
- Internal implementation relies on creating an extra entry in the
arrays used for GT specific counters. Index 0 is empty.
Index 1 through N are mapped to GTs 0 through N - 1.
- User interface will use GT numbers indexed from 0 to specify the GT of
interest.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 134 +++-
drivers/gpu/drm/i915/i915_pmu.h | 2 +-
include/uapi/drm/i915_drm.h | 14 ++--
3 files changed, 125 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 9bd9605d2662..0dc7711c3b4b 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -221,7 +221,7 @@ add_sample_mult(struct i915_pmu *pmu, unsigned int gt_id,
int sample, u32 val,
static u64 get_rc6(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
- const unsigned int gt_id = gt->info.id;
+ const unsigned int gt_id = gt->info.id + 1;
struct i915_pmu *pmu = >pmu;
unsigned long flags;
bool awake = false;
@@ -267,24 +267,26 @@ static void init_rc6(struct i915_pmu *pmu)
for_each_gt(gt, i915, i) {
intel_wakeref_t wakeref;
+ const unsigned int gt_id = i + 1;
with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
u64 val = __get_rc6(gt);
- store_sample(pmu, i, __I915_SAMPLE_RC6, val);
- store_sample(pmu, i, __I915_SAMPLE_RC6_LAST_REPORTED,
+ store_sample(pmu, gt_id, __I915_SAMPLE_RC6, val);
+ store_sample(pmu, gt_id,
__I915_SAMPLE_RC6_LAST_REPORTED,
val);
- pmu->sleep_last[i] = ktime_get_raw();
+ pmu->sleep_last[gt_id] = ktime_get_raw();
}
}
}
static void park_rc6(struct intel_gt *gt)
{
+ const unsigned int gt_id = gt->info.id + 1;
struct i915_pmu *pmu = >i915->pmu;
- store_sample(pmu, gt->info.id, __I915_SAMPLE_RC6, __get_rc6(gt));
- pmu->sleep_last[gt->info.id] = ktime_get_raw();
+ store_sample(pmu, gt_id, __I915_SAMPLE_RC6, __get_rc6(gt));
+ pmu->sleep_last[gt_id] = ktime_get_raw();
}
static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu)
@@ -436,18 +438,18 @@ static void
frequency_sample(struct intel_gt *gt, unsigned int period_ns)
{
struct drm_i915_private *i915 = gt->i915;
- const unsigned int gt_id = gt->info.id;
+ const unsigned int gt_id = gt->info.id + 1;
struct i915_pmu *pmu = >pmu;
struct intel_rps *rps = >rps;
- if (!frequency_sampling_enabled(pmu, gt_id))
+ if (!frequency_sampling_enabled(pmu, gt->info.id))
return;
/* Report 0/0 (actual/requested) frequency while parked. */
if (!intel_gt_pm_get_if_awake(gt))
return;
- if (pmu->enable & config_mask(__I915_PMU_ACTUAL_FREQUENCY(gt_id))) {
+ if (pmu->enable &
config_mask(__I915_PMU_ACTUAL_FREQUENCY(gt->info.id))) {
u32 val;
/*
@@ -467,7 +469,7 @@ frequency_sample(struct intel_gt *gt, unsigned int
period_ns)
val, period_ns / 1000);
}
- if (pmu->enable & config_mask(__I915_PMU_REQUESTED_FREQUENCY(gt_id))) {
+ if (pmu->enable &
config_mask(__I915_PMU_REQUESTED_FREQUENCY(gt->info.id))) {
add_sample_mult(pmu, gt_id, __I915_SAMPLE_FREQ_REQ,
intel_rps_get_requested_frequency(rps),
period_ns / 1000);
@@ -545,14 +547,15 @@ engine_event_status(struct intel_engine_cs *engine,
static int
[Intel-gfx] [PATCH 3/9] drm/i915/pmu: Transform PMU parking code to be GT based
From: Tvrtko Ursulin
Trivial prep work for full multi-tile enablement later.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++--
drivers/gpu/drm/i915/i915_pmu.c | 16
drivers/gpu/drm/i915/i915_pmu.h | 9 +
3 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index e02cb90723ae..c2e69bafd02b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -87,7 +87,7 @@ static int __gt_unpark(struct intel_wakeref *wf)
intel_rc6_unpark(>rc6);
intel_rps_unpark(>rps);
- i915_pmu_gt_unparked(i915);
+ i915_pmu_gt_unparked(gt);
intel_guc_busyness_unpark(gt);
intel_gt_unpark_requests(gt);
@@ -109,7 +109,7 @@ static int __gt_park(struct intel_wakeref *wf)
intel_guc_busyness_park(gt);
i915_vma_parked(gt);
- i915_pmu_gt_parked(i915);
+ i915_pmu_gt_parked(gt);
intel_rps_park(>rps);
intel_rc6_park(>rc6);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 6abd5042dea3..6f7f9b40860d 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -217,11 +217,11 @@ static void init_rc6(struct i915_pmu *pmu)
}
}
-static void park_rc6(struct drm_i915_private *i915)
+static void park_rc6(struct intel_gt *gt)
{
- struct i915_pmu *pmu = >pmu;
+ struct i915_pmu *pmu = >i915->pmu;
- pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(to_gt(i915));
+ pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(gt);
pmu->sleep_last = ktime_get_raw();
}
@@ -236,16 +236,16 @@ static void __i915_pmu_maybe_start_timer(struct i915_pmu
*pmu)
}
}
-void i915_pmu_gt_parked(struct drm_i915_private *i915)
+void i915_pmu_gt_parked(struct intel_gt *gt)
{
- struct i915_pmu *pmu = >pmu;
+ struct i915_pmu *pmu = >i915->pmu;
if (!pmu->base.event_init)
return;
spin_lock_irq(>lock);
- park_rc6(i915);
+ park_rc6(gt);
/*
* Signal sampling timer to stop if only engine events are enabled and
@@ -256,9 +256,9 @@ void i915_pmu_gt_parked(struct drm_i915_private *i915)
spin_unlock_irq(>lock);
}
-void i915_pmu_gt_unparked(struct drm_i915_private *i915)
+void i915_pmu_gt_unparked(struct intel_gt *gt)
{
- struct i915_pmu *pmu = >pmu;
+ struct i915_pmu *pmu = >i915->pmu;
if (!pmu->base.event_init)
return;
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index 449057648f39..d98fbc7a2f45 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -13,6 +13,7 @@
#include
struct drm_i915_private;
+struct intel_gt;
/**
* Non-engine events that we need to track enabled-disabled transition and
@@ -151,15 +152,15 @@ int i915_pmu_init(void);
void i915_pmu_exit(void);
void i915_pmu_register(struct drm_i915_private *i915);
void i915_pmu_unregister(struct drm_i915_private *i915);
-void i915_pmu_gt_parked(struct drm_i915_private *i915);
-void i915_pmu_gt_unparked(struct drm_i915_private *i915);
+void i915_pmu_gt_parked(struct intel_gt *gt);
+void i915_pmu_gt_unparked(struct intel_gt *gt);
#else
static inline int i915_pmu_init(void) { return 0; }
static inline void i915_pmu_exit(void) {}
static inline void i915_pmu_register(struct drm_i915_private *i915) {}
static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
-static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {}
-static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {}
+static inline void i915_pmu_gt_parked(struct intel_gt *gt) {}
+static inline void i915_pmu_gt_unparked(struct intel_gt *gt) {}
#endif
#endif
--
2.36.1
[Intel-gfx] [PATCH 2/9] drm/i915/pmu: Skip sampling engines with no enabled counters
From: Tvrtko Ursulin
As we have more and more engines do not waste time sampling the ones no-
one is monitoring.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_pmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index e274dba58629..6abd5042dea3 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -339,6 +339,9 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns)
return;
for_each_engine(engine, gt, id) {
+ if (!engine->pmu.enable)
+ continue;
+
if (!intel_engine_pm_get_if_awake(engine))
continue;
--
2.36.1
[Intel-gfx] ✓ Fi.CI.BAT: success for Add MTL Wa_14017066071, Wa_14017654203 and Wa_22015279794 (rev2)
== Series Details == Series: Add MTL Wa_14017066071, Wa_14017654203 and Wa_22015279794 (rev2) URL : https://patchwork.freedesktop.org/series/115821/ State : success == Summary == CI Bug Log - changes from CI_DRM_12937 -> Patchwork_115821v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115821v2/index.html Participating hosts (36 -> 35) -- Additional (1): fi-pnv-d510 Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_115821v2 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - bat-rpls-1: [PASS][1] -> [ABORT][2] ([i915#6687] / [i915#7978]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115821v2/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html * igt@i915_module_load@load: - fi-cfl-guc: [PASS][3] -> [ABORT][4] ([i915#8141]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/fi-cfl-guc/igt@i915_module_l...@load.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115821v2/fi-cfl-guc/igt@i915_module_l...@load.html * igt@i915_pm_rps@basic-api: - bat-dg2-11: [PASS][5] -> [FAIL][6] ([i915#8308]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-dg2-11/igt@i915_pm_...@basic-api.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115821v2/bat-dg2-11/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_lrc: - bat-adln-1: [PASS][7] -> [INCOMPLETE][8] ([i915#4983] / [i915#7609]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-adln-1/igt@i915_selftest@live@gt_lrc.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115821v2/bat-adln-1/igt@i915_selftest@live@gt_lrc.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#7828]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115821v2/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_psr@primary_page_flip: - fi-pnv-d510:NOTRUN -> [SKIP][10] ([fdo#109271]) +38 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115821v2/fi-pnv-d510/igt@kms_psr@primary_page_flip.html Possible fixes * igt@i915_selftest@live@gt_heartbeat: - fi-glk-j4005: [DMESG-FAIL][11] ([i915#5334]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115821v2/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@hangcheck: - bat-dg2-11: [ABORT][13] ([i915#7913]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115821v2/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html Warnings * igt@i915_selftest@live@slpc: - bat-rpls-1: [DMESG-FAIL][15] ([i915#6367]) -> [DMESG-FAIL][16] ([i915#6367] / [i915#6997]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-rpls-1/igt@i915_selftest@l...@slpc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115821v2/bat-rpls-1/igt@i915_selftest@l...@slpc.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687 [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997 [i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978 [i915#8141]: https://gitlab.freedesktop.org/drm/intel/issues/8141 [i915#8308]: https://gitlab.freedesktop.org/drm/intel/issues/8308 Build changes - * Linux: CI_DRM_12937 -> Patchwork_115821v2 CI-20190529: 20190529 CI_DRM_12937: 6848d3613c0a63382d00ff550c41394902bda903 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7226: 41be8b4ab86f9e11388c10366dfd71e5032589c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_115821v2: 6848d3613c0a63382d00ff550c41394902bda903 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits cc474cd41378 drm/i915/mtl: Add Wa_22015279794 58419d21c7de drm/i915/mtl: Add workarounds
Re: [Intel-gfx] [PATCH v6 5/8] drm/i915/pxp: Add ARB session creation and cleanup
On Wed, 2023-03-29 at 08:43 +0100, Tvrtko Ursulin wrote: > On 28/03/2023 18:52, Rodrigo Vivi wrote: > > On Tue, Mar 28, 2023 at 05:01:36PM +, Teres Alexis, Alan Previn wrote: > > > On Mon, 2023-03-27 at 17:15 +0100, Tvrtko Ursulin wrote: > > > alan:snip > How will the context create path look like on those platforms: > > 1. Block, then potentially error out if the full initialization failed. > 2. Error out "in progress" while initializing, error out "something > else" if initialization failed. > alan:i was thinking of taking a page from huc-authentication's get-param where we could return different values based on startup progress - in all cases we never block: 1. we dont support it in hw/kernel (i.e. not pxp in device-info or not enough CONFIG_foo - reusing intel_pxp_is_supported?) 2. we support it in kernel but internal dependencies are still in progress (i.e. we have not yet completed huc-loading/huc-authen/proxy-init - UAPI spec should include how many max seconds delay per platform) 3. we support it in kernel but internal dependencies failed (i.e. we know huc-load/authent. failed ... or we know proxy-init failed). 4. we support it in kernel but platform has no support (at this stage we actually attempt to create a PXP context or create the arb-session from inside i915-get-param but we ended up a PXP fw error indicating select list of failures such as fusing / BIOS-config / wrong-version. 0. we support it completely i.e. step 4's attempt to create active PXP session succeeded I want to differentiate 3 and 4 (as opposed to return x-means-ENODEV) because i have am sure it will save debug time when facing customer issues. Ofc we will have to optimize the checking sequences above but at #4, we would be creating a session which might take up to ~200 milisecs for the round trip response from fw. We could store a flag in i915-pxp-internal-struct to indicate if we ever did succeed a pxp creation after a fresh boot ... intel_pxp_is_ready_for_active()? ... true only if we ever did allocate a slot successfully at least once since boot. This also ensure mesa init will return almost immediately except at the first time when hitting #4.
Re: [Intel-gfx] [PATCH v8 21/24] vfio: Add VFIO_DEVICE_BIND_IOMMUFD
On Wed, Mar 29, 2023 at 03:00:55PM -0600, Alex Williamson wrote: > > + * The user should provide a device cookie when calling this ioctl. The > > + * cookie is carried only in event e.g. I/O fault reported to userspace > > + * via iommufd. The user should use devid returned by this ioctl to mark > > + * the target device in other ioctls (e.g. iommu hardware infomration query > > + * via iommufd, and etc.). > > AFAICT, the whole concept of this dev_cookie is a fantasy. It only > exists in this series in these comments and the structure below. It's > not even defined whether it needs to be unique within an iommufd > context, and clearly nothing here validates that. There's not enough > implementation for it to exist in this series. Maybe dev_cookie is > appended to the end of the structure and indicated with a flag when it > has some meaning. Yes, I've asked for this to be punted to the PRI series enough times already, why does it keep coming back ?? > > + * @argsz: user filled size of this data. > > + * @flags: reserved for future extension. > > + * @dev_cookie: a per device cookie provided by userspace. > > + * @iommufd:iommufd to bind. a negative value means noiommu. > > "Use a negative value for no-iommu, where supported", or better, should > we define this explicitly as -1, or why not use a flag bit to specify > no-iommu? Maybe minsz is only through flags for the noiommu use case. I was happy enough for this to be defined as -1. We could give it a formal sounding constant too Jason
Re: [Intel-gfx] [PATCH v8 24/24] docs: vfio: Add vfio device cdev description
On Wed, 29 Mar 2023 16:47:49 -0600 Alex Williamson wrote: > On Mon, 27 Mar 2023 02:40:47 -0700 > Yi Liu wrote: > > > This gives notes for userspace applications on device cdev usage. > > > > Reviewed-by: Kevin Tian > > Signed-off-by: Yi Liu > > --- > > Documentation/driver-api/vfio.rst | 127 ++ > > 1 file changed, 127 insertions(+) > > > > diff --git a/Documentation/driver-api/vfio.rst > > b/Documentation/driver-api/vfio.rst > > index 363e12c90b87..77408788b98d 100644 > > --- a/Documentation/driver-api/vfio.rst > > +++ b/Documentation/driver-api/vfio.rst > > @@ -239,6 +239,125 @@ group and can access them as follows:: > > /* Gratuitous device reset and go... */ > > ioctl(device, VFIO_DEVICE_RESET); > > > > +IOMMUFD and vfio_iommu_type1 > > + > > + > > +IOMMUFD is the new user API to manage I/O page tables from userspace. > > +It intends to be the portal of delivering advanced userspace DMA > > +features (nested translation [5], PASID [6], etc.) while being backward > > +compatible with the vfio_iommu_type1 driver. Eventually vfio_iommu_type1 > > +will be deprecated. > > "... while also providing a backwards compatibility interface for > existing VFIO_TYPE1v2_IOMMU use cases. Eventually the vfio_iommu_type1 > driver, as well as the legacy vfio container and group model is > intended to be deprecated." > > > + > > +With the backward compatibility, no change is required for legacy > > VFIO +drivers or applications to connect a VFIO device to IOMMUFD. > > + > > + When CONFIG_IOMMUFD_VFIO_CONTAINER=n, VFIO container still provides > > + /dev/vfio/vfio which connects to vfio_iommu_type1. To disable VFIO > > + container and vfio_iommu_type1, the administrator could symbol link > > + /dev/vfio/vfio to /dev/iommu to enable VFIO container emulation > > + in IOMMUFD. > > + > > + When CONFIG_IOMMUFD_VFIO_CONTAINER=y, IOMMUFD directly provides > > + /dev/vfio/vfio while the VFIO container and vfio_iommu_type1 are > > + explicitly disabled. > > + > > "The IOMMUFD backwards compatibility interface can be enabled two ways. > In the first method, the kernel can be configured with > CONFIG_IOMMUFD_VFIO_CONTAINER, in which case the IOMMUFD subsystem > transparently provides the entire infrastructure for the the VFIO > container and IOMMU backend interfaces. The compatibility mode can > also be accessed if the VFIO container interface, ie. /dev/vfio/vfio is > simply symlink'd to /dev/iommu. Note that at the time of writing, the > compatibility mode is not entirely feature complete relative to > VFIO_TYPE1v2_IOMMU (ex. DMA mapping MMIO) and does not attempt to > provide compatibility to the VFIO_SPAPR_TCE_IOMMU interface. Therefore > it is not generally advisable at this time to switch from native VFIO > implementations to the IOMMUFD compatibility interfaces. > > Long term, VFIO users should migrate to device access through the cdev > interface described below, and native access through the IOMMUFD > provided interfaces." > > Thanks, > Alex > > > +VFIO Device cdev > > + > > + > > +Traditionally user acquires a device fd via VFIO_GROUP_GET_DEVICE_FD > > +in a VFIO group. > > + > > +With CONFIG_VFIO_DEVICE_CDEV=y the user can now acquire a device fd > > +by directly opening a character device /dev/vfio/devices/vfioX where > > +"X" is the number allocated uniquely by VFIO for registered devices. > > +For noiommu devices, the character device would be named with > > "noiommu-" +prefix. e.g. /dev/vfio/devices/noiommu-vfioX. > > + > > +The cdev only works with IOMMUFD. Both VFIO drivers and applications > > +must adapt to the new cdev security model which requires using > > +VFIO_DEVICE_BIND_IOMMUFD to claim DMA ownership before starting to > > +actually use the device. Once BIND succeeds then a VFIO device can > > +be fully accessed by the user. > > + > > +VFIO device cdev doesn't rely on VFIO group/container/iommu drivers. > > +Hence those modules can be fully compiled out in an environment > > +where no legacy VFIO application exists. > > + > > +So far SPAPR does not support IOMMUFD yet. So it cannot support > > device +cdev neither. > > + > > +Device cdev Example > > +--- > > + > > +Assume user wants to access PCI device :6a:01.0:: > > + > > + $ ls /sys/bus/pci/devices/:6a:01.0/vfio-dev/ > > + vfio0 > > + > > +This device is therefore represented as vfio0. The user can verify > > +its existence:: > > + > > + $ ls -l /dev/vfio/devices/vfio0 > > + crw--- 1 root root 511, 0 Feb 16 01:22 > > /dev/vfio/devices/vfio0 > > + $ cat /sys/bus/pci/devices/:6a:01.0/vfio-dev/vfio0/dev > > + 511:0 > > + $ ls -l /dev/char/511\:0 > > + lrwxrwxrwx 1 root root 21 Feb 16 01:22 /dev/char/511:0 -> > > ../vfio/devices/vfio0 + > > +Then provide the user with access to the device if unprivileged > > +operation is desired:: > > + > > + $ chown user:user /dev/vfio/devices/vfio0
Re: [Intel-gfx] [PATCH v8 24/24] docs: vfio: Add vfio device cdev description
On Mon, 27 Mar 2023 02:40:47 -0700
Yi Liu wrote:
> This gives notes for userspace applications on device cdev usage.
>
> Reviewed-by: Kevin Tian
> Signed-off-by: Yi Liu
> ---
> Documentation/driver-api/vfio.rst | 127 ++
> 1 file changed, 127 insertions(+)
>
> diff --git a/Documentation/driver-api/vfio.rst
> b/Documentation/driver-api/vfio.rst
> index 363e12c90b87..77408788b98d 100644
> --- a/Documentation/driver-api/vfio.rst
> +++ b/Documentation/driver-api/vfio.rst
> @@ -239,6 +239,125 @@ group and can access them as follows::
> /* Gratuitous device reset and go... */
> ioctl(device, VFIO_DEVICE_RESET);
>
> +IOMMUFD and vfio_iommu_type1
> +
> +
> +IOMMUFD is the new user API to manage I/O page tables from userspace.
> +It intends to be the portal of delivering advanced userspace DMA
> +features (nested translation [5], PASID [6], etc.) while being backward
> +compatible with the vfio_iommu_type1 driver. Eventually vfio_iommu_type1
> +will be deprecated.
"... while also providing a backwards compatibility interface for
existing VFIO_TYPE1v2_IOMMU use cases. Eventually the vfio_iommu_type1
driver, as well as the legacy vfio container and group model is
intended to be deprecated."
> +
> +With the backward compatibility, no change is required for legacy
> VFIO +drivers or applications to connect a VFIO device to IOMMUFD.
> +
> + When CONFIG_IOMMUFD_VFIO_CONTAINER=n, VFIO container still provides
> + /dev/vfio/vfio which connects to vfio_iommu_type1. To disable VFIO
> + container and vfio_iommu_type1, the administrator could symbol link
> + /dev/vfio/vfio to /dev/iommu to enable VFIO container emulation
> + in IOMMUFD.
> +
> + When CONFIG_IOMMUFD_VFIO_CONTAINER=y, IOMMUFD directly provides
> + /dev/vfio/vfio while the VFIO container and vfio_iommu_type1 are
> + explicitly disabled.
> +
"The IOMMUFD backwards compatibility interface can be enabled two ways.
In the first method, the kernel can be configured with
CONFIG_IOMMUFD_VFIO_CONTAINER, in which case the IOMMUFD subsystem
transparently provides the entire infrastructure for the the VFIO
container and IOMMU backend interfaces. The compatibility mode can
also be accessed if the VFIO container interface, ie. /dev/vfio/vfio is
simply symlink'd to /dev/iommu. Note that at the time of writing, the
compatibility mode is not entirely feature complete relative to
VFIO_TYPE1v2_IOMMU (ex. DMA mapping MMIO) and does not attempt to
provide compatibility to the VFIO_SPAPR_TCE_IOMMU interface. Therefore
it is not generally advisable at this time to switch from native VFIO
implementations to the IOMMUFD compatibility interfaces.
Long term, VFIO users should migrate to device access through the cdev
interface described below, and native access through the IOMMUFD
provided interfaces."
Thanks,
Alex
> +VFIO Device cdev
> +
> +
> +Traditionally user acquires a device fd via VFIO_GROUP_GET_DEVICE_FD
> +in a VFIO group.
> +
> +With CONFIG_VFIO_DEVICE_CDEV=y the user can now acquire a device fd
> +by directly opening a character device /dev/vfio/devices/vfioX where
> +"X" is the number allocated uniquely by VFIO for registered devices.
> +For noiommu devices, the character device would be named with
> "noiommu-" +prefix. e.g. /dev/vfio/devices/noiommu-vfioX.
> +
> +The cdev only works with IOMMUFD. Both VFIO drivers and applications
> +must adapt to the new cdev security model which requires using
> +VFIO_DEVICE_BIND_IOMMUFD to claim DMA ownership before starting to
> +actually use the device. Once BIND succeeds then a VFIO device can
> +be fully accessed by the user.
> +
> +VFIO device cdev doesn't rely on VFIO group/container/iommu drivers.
> +Hence those modules can be fully compiled out in an environment
> +where no legacy VFIO application exists.
> +
> +So far SPAPR does not support IOMMUFD yet. So it cannot support
> device +cdev neither.
> +
> +Device cdev Example
> +---
> +
> +Assume user wants to access PCI device :6a:01.0::
> +
> + $ ls /sys/bus/pci/devices/:6a:01.0/vfio-dev/
> + vfio0
> +
> +This device is therefore represented as vfio0. The user can verify
> +its existence::
> +
> + $ ls -l /dev/vfio/devices/vfio0
> + crw--- 1 root root 511, 0 Feb 16 01:22
> /dev/vfio/devices/vfio0
> + $ cat /sys/bus/pci/devices/:6a:01.0/vfio-dev/vfio0/dev
> + 511:0
> + $ ls -l /dev/char/511\:0
> + lrwxrwxrwx 1 root root 21 Feb 16 01:22 /dev/char/511:0 ->
> ../vfio/devices/vfio0 +
> +Then provide the user with access to the device if unprivileged
> +operation is desired::
> +
> + $ chown user:user /dev/vfio/devices/vfio0
> +
> +Finally the user could get cdev fd by::
> +
> + cdev_fd = open("/dev/vfio/devices/vfio0", O_RDWR);
> +
> +An opened cdev_fd doesn't give the user any permission of accessing
> +the device except binding the cdev_fd to an iommufd. After that
>
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Skip cursor when writing PLANE_CHICKEN
== Series Details == Series: series starting with [1/3] drm/i915: Skip cursor when writing PLANE_CHICKEN URL : https://patchwork.freedesktop.org/series/115815/ State : success == Summary == CI Bug Log - changes from CI_DRM_12937 -> Patchwork_115815v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115815v1/index.html Participating hosts (36 -> 35) -- Additional (1): fi-pnv-d510 Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_115815v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - bat-rpls-1: [PASS][1] -> [ABORT][2] ([i915#6687] / [i915#7978]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115815v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html * igt@i915_pm_rps@basic-api: - bat-dg2-11: [PASS][3] -> [FAIL][4] ([i915#8308]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-dg2-11/igt@i915_pm_...@basic-api.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115815v1/bat-dg2-11/igt@i915_pm_...@basic-api.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#7828]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115815v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1: - bat-dg2-8: [PASS][6] -> [FAIL][7] ([i915#7932]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115815v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html * igt@kms_pipe_crc_basic@read-crc: - bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#5354]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115815v1/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc.html * igt@kms_psr@primary_page_flip: - fi-pnv-d510:NOTRUN -> [SKIP][9] ([fdo#109271]) +38 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115815v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html Possible fixes * igt@i915_selftest@live@gt_heartbeat: - fi-glk-j4005: [DMESG-FAIL][10] ([i915#5334]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115815v1/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@hangcheck: - bat-dg2-11: [ABORT][12] ([i915#7913]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115815v1/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@slpc: - bat-rpls-1: [DMESG-FAIL][14] ([i915#6367]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-rpls-1/igt@i915_selftest@l...@slpc.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115815v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932 [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978 [i915#8308]: https://gitlab.freedesktop.org/drm/intel/issues/8308 Build changes - * Linux: CI_DRM_12937 -> Patchwork_115815v1 CI-20190529: 20190529 CI_DRM_12937: 6848d3613c0a63382d00ff550c41394902bda903 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7226: 41be8b4ab86f9e11388c10366dfd71e5032589c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_115815v1: 6848d3613c0a63382d00ff550c41394902bda903 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 9aef6547c186 drm/i915: Define cursor chicken reg 138072267ebe drm/i915: Document that PLANE_CHICKEN are for tgl+ f3fdb02bfa34 drm/i915: Skip cursor when writing PLANE_CHICKEN == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115815v1/index.html
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: (mostly) PSR related register cleanups (rev2)
== Series Details == Series: drm/i915: (mostly) PSR related register cleanups (rev2) URL : https://patchwork.freedesktop.org/series/115708/ State : success == Summary == CI Bug Log - changes from CI_DRM_12937 -> Patchwork_115708v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115708v2/index.html Participating hosts (36 -> 35) -- Additional (1): fi-pnv-d510 Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_115708v2 that come from known issues: ### IGT changes ### Issues hit * igt@dmabuf@all-tests@dma_fence: - bat-adln-1: [PASS][1] -> [DMESG-FAIL][2] ([i915#8143]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-adln-1/igt@dmabuf@all-tests@dma_fence.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115708v2/bat-adln-1/igt@dmabuf@all-tests@dma_fence.html * igt@dmabuf@all-tests@sanitycheck: - bat-adln-1: [PASS][3] -> [ABORT][4] ([i915#8058] / [i915#8144]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-adln-1/igt@dmabuf@all-te...@sanitycheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115708v2/bat-adln-1/igt@dmabuf@all-te...@sanitycheck.html * igt@i915_selftest@live@reset: - bat-rpls-1: [PASS][5] -> [ABORT][6] ([i915#4983]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-rpls-1/igt@i915_selftest@l...@reset.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115708v2/bat-rpls-1/igt@i915_selftest@l...@reset.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#7828]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115708v2/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-3: - bat-dg2-9: [PASS][8] -> [FAIL][9] ([fdo#103375] / [i915#7932]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-dp-3.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115708v2/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-dp-3.html * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-dp-3: - bat-dg2-9: [PASS][10] -> [FAIL][11] ([fdo#103375]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-...@pipe-d-dp-3.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115708v2/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-...@pipe-d-dp-3.html * igt@kms_psr@primary_page_flip: - fi-pnv-d510:NOTRUN -> [SKIP][12] ([fdo#109271]) +38 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115708v2/fi-pnv-d510/igt@kms_psr@primary_page_flip.html Possible fixes * igt@i915_selftest@live@gt_heartbeat: - fi-glk-j4005: [DMESG-FAIL][13] ([i915#5334]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115708v2/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@hangcheck: - bat-dg2-11: [ABORT][15] ([i915#7913]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115708v2/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932 [i915#8058]: https://gitlab.freedesktop.org/drm/intel/issues/8058 [i915#8143]: https://gitlab.freedesktop.org/drm/intel/issues/8143 [i915#8144]: https://gitlab.freedesktop.org/drm/intel/issues/8144 Build changes - * Linux: CI_DRM_12937 -> Patchwork_115708v2 CI-20190529: 20190529 CI_DRM_12937: 6848d3613c0a63382d00ff550c41394902bda903 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7226: 41be8b4ab86f9e11388c10366dfd71e5032589c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_115708v2: 6848d3613c0a63382d00ff550c41394902bda903 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 956679d3b00a drm/i915/psr: Sprinkle cpu_transcoder variables around c3cc085585ed drm/i915/psr: Include PSR_PERF_CNT in debugfs output on all
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: (mostly) PSR related register cleanups (rev2)
== Series Details == Series: drm/i915: (mostly) PSR related register cleanups (rev2) URL : https://patchwork.freedesktop.org/series/115708/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: (mostly) PSR related register cleanups (rev2)
== Series Details == Series: drm/i915: (mostly) PSR related register cleanups (rev2) URL : https://patchwork.freedesktop.org/series/115708/ State : warning == Summary == Error: dim checkpatch failed c68fc57101a3 drm/i915: Fix up whitespace in some display chicken registers 07f7a824fe2d drm/i915: Clean up various display chicken registers -:182: WARNING:LONG_LINE: line length of 124 exceeds 100 columns #182: FILE: drivers/gpu/drm/i915/i915_reg.h:6142: +#define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */ total: 0 errors, 1 warnings, 0 checks, 165 lines checked cf970e6747ce drm/i915/psr: Clean up PSR register defininitions -:281: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #281: FILE: drivers/gpu/drm/i915/i915_reg.h:2240: + EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) -:288: WARNING:LONG_LINE: line length of 111 exceeds 100 columns #288: FILE: drivers/gpu/drm/i915/i915_reg.h:2244: + (lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) -:294: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #294: FILE: drivers/gpu/drm/i915/i915_reg.h:2248: + EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) -:311: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #311: FILE: drivers/gpu/drm/i915/i915_reg.h:2252: + (lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) total: 0 errors, 4 warnings, 0 checks, 329 lines checked d04c6674ff81 drm/i915/psr: Use intel_de_rmw() 2da5aba6acee drm/i915/psr: Define more PSR mask bits 05763f315bf6 drm/i915/psr: Add a FIXME for the PSR vs. AUX usage conflict 0a2da114d00c drm/i915/psr: Include PSR_PERF_CNT in debugfs output on all platforms fbe3b2c6eec9 drm/i915/psr: Sprinkle cpu_transcoder variables around -:150: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #150: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1186: + intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder)) & EDP_PSR2_ENABLE); total: 0 errors, 1 warnings, 0 checks, 387 lines checked
Re: [Intel-gfx] [PATCH v8 23/24] vfio: Compile group optionally
On Mon, 27 Mar 2023 02:40:46 -0700
Yi Liu wrote:
> group code is not needed for vfio device cdev, so with vfio device cdev
> introduced, the group infrastructures can be compiled out if only cdev
> is needed.
>
> Reviewed-by: Kevin Tian
> Tested-by: Terrence Xu
> Signed-off-by: Yi Liu
> ---
> drivers/iommu/iommufd/Kconfig | 4 +-
> drivers/vfio/Kconfig | 16 -
> drivers/vfio/Makefile | 2 +-
> drivers/vfio/vfio.h | 111 --
> include/linux/vfio.h | 13 +++-
> 5 files changed, 134 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/iommu/iommufd/Kconfig b/drivers/iommu/iommufd/Kconfig
> index ada693ea51a7..1946eed1826a 100644
> --- a/drivers/iommu/iommufd/Kconfig
> +++ b/drivers/iommu/iommufd/Kconfig
> @@ -14,8 +14,8 @@ config IOMMUFD
> if IOMMUFD
> config IOMMUFD_VFIO_CONTAINER
> bool "IOMMUFD provides the VFIO container /dev/vfio/vfio"
> - depends on VFIO && !VFIO_CONTAINER
> - default VFIO && !VFIO_CONTAINER
> + depends on VFIO && VFIO_GROUP && !VFIO_CONTAINER
> + default VFIO && VFIO_GROUP && !VFIO_CONTAINER
Shouldn't these simply replace VFIO with VFIO_GROUP since VFIO_GROUP
necessarily depends on VFIO?
> help
> IOMMUFD will provide /dev/vfio/vfio instead of VFIO. This relies on
> IOMMUFD providing compatibility emulation to give the same ioctls.
> diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig
> index e2105b4dac2d..0942a19601a2 100644
> --- a/drivers/vfio/Kconfig
> +++ b/drivers/vfio/Kconfig
> @@ -4,7 +4,9 @@ menuconfig VFIO
> select IOMMU_API
> depends on IOMMUFD || !IOMMUFD
> select INTERVAL_TREE
> - select VFIO_CONTAINER if IOMMUFD=n
> + select VFIO_GROUP if SPAPR_TCE_IOMMU || !IOMMUFD
This needs to be IOMMUFD=n or else VFIO_GROUP cannot be unset when
IOMMUFD=m
> + select VFIO_DEVICE_CDEV if !VFIO_GROUP
> + select VFIO_CONTAINER if IOMMUFD=n && VFIO_GROUP
The fact that CONTAINER depends on GROUP seems to be sufficient that we
don't need GROUP here. Thanks,
Alex
> help
> VFIO provides a framework for secure userspace device drivers.
> See Documentation/driver-api/vfio.rst for more details.
> @@ -15,6 +17,7 @@ if VFIO
> config VFIO_DEVICE_CDEV
> bool "Support for the VFIO cdev /dev/vfio/devices/vfioX"
> depends on IOMMUFD
> + default !VFIO_GROUP
> help
> The VFIO device cdev is another way for userspace to get device
> access. Userspace gets device fd by opening device cdev under
> @@ -23,9 +26,20 @@ config VFIO_DEVICE_CDEV
>
> If you don't know what to do here, say N.
>
> +config VFIO_GROUP
> + bool "Support for the VFIO group /dev/vfio/$group_id"
> + default y
> + help
> +VFIO group support provides the traditional model for accessing
> +devices through VFIO and is used by the majority of userspace
> +applications and drivers making use of VFIO.
> +
> +If you don't know what to do here, say Y.
> +
> config VFIO_CONTAINER
> bool "Support for the VFIO container /dev/vfio/vfio"
> select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64)
> + depends on VFIO_GROUP
> default y
> help
> The VFIO container is the classic interface to VFIO for establishing
> diff --git a/drivers/vfio/Makefile b/drivers/vfio/Makefile
> index 245394aeb94b..57c3515af606 100644
> --- a/drivers/vfio/Makefile
> +++ b/drivers/vfio/Makefile
> @@ -2,9 +2,9 @@
> obj-$(CONFIG_VFIO) += vfio.o
>
> vfio-y += vfio_main.o \
> - group.o \
> iova_bitmap.o
> vfio-$(CONFIG_VFIO_DEVICE_CDEV) += device_cdev.o
> +vfio-$(CONFIG_VFIO_GROUP) += group.o
> vfio-$(CONFIG_IOMMUFD) += iommufd.o
> vfio-$(CONFIG_VFIO_CONTAINER) += container.o
> vfio-$(CONFIG_VFIO_VIRQFD) += virqfd.o
> diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
> index c199e410db18..9c7a238ec8dd 100644
> --- a/drivers/vfio/vfio.h
> +++ b/drivers/vfio/vfio.h
> @@ -36,6 +36,12 @@ vfio_allocate_device_file(struct vfio_device *device);
>
> extern const struct file_operations vfio_device_fops;
>
> +#ifdef CONFIG_VFIO_NOIOMMU
> +extern bool vfio_noiommu __read_mostly;
> +#else
> +enum { vfio_noiommu = false };
> +#endif
> +
> enum vfio_group_type {
> /*
>* Physical device with IOMMU backing.
> @@ -60,6 +66,7 @@ enum vfio_group_type {
> VFIO_NO_IOMMU,
> };
>
> +#if IS_ENABLED(CONFIG_VFIO_GROUP)
> struct vfio_group {
> struct device dev;
> struct cdev cdev;
> @@ -113,6 +120,104 @@ static inline void vfio_device_set_noiommu(struct
> vfio_device *device)
> device->noiommu = IS_ENABLED(CONFIG_VFIO_NOIOMMU) &&
> device->group->type == VFIO_NO_IOMMU;
> }
> +#else
> +struct vfio_group;
> +
> +static inline int vfio_device_block_group(struct vfio_device *device)
> +{
> + return 0;
> +}
> +
> +static inline void
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix fast wake AUX sync len
== Series Details == Series: series starting with [1/2] drm/i915: Fix fast wake AUX sync len URL : https://patchwork.freedesktop.org/series/115810/ State : success == Summary == CI Bug Log - changes from CI_DRM_12937 -> Patchwork_115810v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115810v1/index.html Participating hosts (36 -> 34) -- Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_115810v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - bat-rpls-1: [PASS][1] -> [ABORT][2] ([i915#6687] / [i915#7978]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115810v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-dg2-11: NOTRUN -> [SKIP][3] ([i915#7828]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115810v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@read-crc: - bat-dg2-11: NOTRUN -> [SKIP][4] ([i915#5354]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115810v1/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc.html Possible fixes * igt@i915_selftest@live@gt_heartbeat: - fi-glk-j4005: [DMESG-FAIL][5] ([i915#5334]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115810v1/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@hangcheck: - bat-dg2-11: [ABORT][7] ([i915#7913]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115810v1/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html Warnings * igt@i915_selftest@live@slpc: - bat-rpls-1: [DMESG-FAIL][9] ([i915#6367]) -> [DMESG-FAIL][10] ([i915#6367] / [i915#7996]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-rpls-1/igt@i915_selftest@l...@slpc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115810v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978 [i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996 Build changes - * Linux: CI_DRM_12937 -> Patchwork_115810v1 CI-20190529: 20190529 CI_DRM_12937: 6848d3613c0a63382d00ff550c41394902bda903 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7226: 41be8b4ab86f9e11388c10366dfd71e5032589c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_115810v1: 6848d3613c0a63382d00ff550c41394902bda903 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits ca3d3eda792c drm/i915: Explain the magic numbers for AUX SYNC/precharge length 39b0f8225522 drm/i915: Fix fast wake AUX sync len == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115810v1/index.html
[Intel-gfx] [PATCH v2 2/2] drm/i915/mtl: Add Wa_22015279794
From: Radhakrishna Sripada Wa_22015279794 applies to MTL P from stepping A0 to B0 (exclusive). Signed-off-by: Radhakrishna Sripada Signed-off-by: Gustavo Sousa Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 ++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 1ec855813632..35a4cfac2d20 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1156,7 +1156,13 @@ #define ENABLE_EU_COUNT_FOR_TDL_FLUSHREG_BIT(10) #define DISABLE_ECC REG_BIT(5) #define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4) +/* + * We have both ENABLE and DISABLE defines below using the same bit because the + * meaning depends on the target platform. There are no platform prefix for them + * because different steppings of DG2 pick one or the other semantics. + */ #define ENABLE_PREFETCH_INTO_IC REG_BIT(3) +#define DISABLE_PREFETCH_INTO_IC REG_BIT(3) #define EU_PERF_CNTL0 PERF_REG(0xe458) #define EU_PERF_CNTL4 PERF_REG(0xe45c) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 6170535f94ef..1c8e0e91a2fe 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2980,6 +2980,11 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, MTL_DISABLE_SAMPLER_SC_OOO); + if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) + /* Wa_22015279794 */ + wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, +DISABLE_PREFETCH_INTO_IC); + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || -- 2.40.0
[Intel-gfx] [PATCH v2 1/2] drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203
From: Radhakrishna Sripada Both workarounds require the same implementation and apply to MTL P and M from stepping A0 to B0 (exclusive). v2: - Remove unrelated brace removal. (Matt) Signed-off-by: Radhakrishna Sripada Signed-off-by: Gustavo Sousa Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 + 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 4aecb5a7b631..1ec855813632 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1144,6 +1144,7 @@ #define ENABLE_SMALLPL REG_BIT(15) #define SC_DISABLE_POWER_OPTIMIZATION_EBBREG_BIT(9) #define GEN11_SAMPLER_ENABLE_HEADLESS_MSGREG_BIT(5) +#define MTL_DISABLE_SAMPLER_SC_OOO REG_BIT(3) #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194) #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index e7ee24bcad89..6170535f94ef 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2971,6 +2971,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li add_render_compute_tuning_settings(i915, wal); + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) + /* +* Wa_14017066071 +* Wa_14017654203 +*/ + wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, +MTL_DISABLE_SAMPLER_SC_OOO); + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || -- 2.40.0
[Intel-gfx] [PATCH v2 0/2] Add MTL Wa_14017066071, Wa_14017654203 and Wa_22015279794
Add some GT workarounds for MTL. Note that Wa_14017066071 and Wa_14017654203 require the same implementation and have the same platform and stepping bounds, so there is a single patch for them. v2: - Remove unrelated brace removal in first patch. (Matt) Radhakrishna Sripada (2): drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203 drm/i915/mtl: Add Wa_22015279794 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 ++ 2 files changed, 21 insertions(+) -- 2.40.0
Re: [Intel-gfx] [PATCH v8 22/24] vfio: Add VFIO_DEVICE_AT[DE]TACH_IOMMUFD_PT
Nit, ATDETACH? [AT|DE]TACH?
On Mon, 27 Mar 2023 02:40:45 -0700
Yi Liu wrote:
> This adds ioctl for userspace to attach device cdev fd to and detach
> from IOAS/hw_pagetable managed by iommufd.
>
> VFIO_DEVICE_ATTACH_IOMMUFD_PT: attach vfio device to IOAS, hw_pagetable
> managed by iommufd. Attach can be
> undo by VFIO_DEVICE_DETACH_IOMMUFD_PT
> or device fd close.
> VFIO_DEVICE_DETACH_IOMMUFD_PT: detach vfio device from the current
> attached
> IOAS or hw_pagetable managed by iommufd.
>
> Reviewed-by: Kevin Tian
> Tested-by: Terrence Xu
> Tested-by: Nicolin Chen
> Tested-by: Matthew Rosato
> Signed-off-by: Yi Liu
> ---
> drivers/vfio/device_cdev.c | 85 ++
> drivers/vfio/vfio.h| 16 +++
> drivers/vfio/vfio_main.c | 8
> include/uapi/linux/vfio.h | 52 +++
> 4 files changed, 161 insertions(+)
>
> diff --git a/drivers/vfio/device_cdev.c b/drivers/vfio/device_cdev.c
> index 2b563bac50b9..b5de997bff6d 100644
> --- a/drivers/vfio/device_cdev.c
> +++ b/drivers/vfio/device_cdev.c
> @@ -197,6 +197,91 @@ long vfio_device_ioctl_bind_iommufd(struct
> vfio_device_file *df,
> return ret;
> }
>
> +int vfio_ioctl_device_attach(struct vfio_device_file *df,
> + struct vfio_device_attach_iommufd_pt __user *arg)
> +{
> + struct vfio_device *device = df->device;
> + struct vfio_device_attach_iommufd_pt attach;
> + unsigned long minsz;
> + int ret;
> +
> + static_assert(__same_type(arg->pt_id, attach.pt_id));
Same comment as previous, given these are the same field of the same
structure, I don't understand how this could ever assert.
> +
> + minsz = offsetofend(struct vfio_device_attach_iommufd_pt, pt_id);
> +
> + if (copy_from_user(, arg, minsz))
> + return -EFAULT;
> +
> + if (attach.argsz < minsz || attach.flags)
> + return -EINVAL;
> +
> + if (!device->ops->bind_iommufd)
> + return -ENODEV;
Same as previous, we already require this to enable cdev support, so
this seems ultra paranoid.
> +
> + /* ATTACH only allowed for cdev fds */
> + if (df->group)
> + return -EINVAL;
> +
> + mutex_lock(>dev_set->lock);
> + /* noiommufd mode doesn't allow attach */
> + if (!df->iommufd) {
> + ret = -EOPNOTSUPP;
> + goto out_unlock;
> + }
> +
> + ret = device->ops->attach_ioas(device, _id);
> + if (ret)
> + goto out_unlock;
> +
> + ret = copy_to_user(>pt_id, _id,
> +sizeof(attach.pt_id)) ? -EFAULT : 0;
> + if (ret)
> + goto out_detach;
> + mutex_unlock(>dev_set->lock);
> +
> + return 0;
> +
> +out_detach:
> + device->ops->detach_ioas(device);
> +out_unlock:
> + mutex_unlock(>dev_set->lock);
> + return ret;
> +}
> +
> +int vfio_ioctl_device_detach(struct vfio_device_file *df,
> + struct vfio_device_detach_iommufd_pt __user *arg)
> +{
> + struct vfio_device *device = df->device;
> + struct vfio_device_detach_iommufd_pt detach;
> + unsigned long minsz;
> +
> + minsz = offsetofend(struct vfio_device_detach_iommufd_pt, flags);
> +
> + if (copy_from_user(, arg, minsz))
> + return -EFAULT;
> +
> + if (detach.argsz < minsz || detach.flags)
> + return -EINVAL;
> +
> + if (!device->ops->bind_iommufd)
> + return -ENODEV;
> +
> + /* DETACH only allowed for cdev fds */
> + if (df->group)
> + return -EINVAL;
> +
> + mutex_lock(>dev_set->lock);
> + /* noiommufd mode doesn't support detach */
> + if (!df->iommufd) {
> + mutex_unlock(>dev_set->lock);
> + return -EOPNOTSUPP;
> + }
> + device->ops->detach_ioas(device);
> + mutex_unlock(>dev_set->lock);
> +
> + return 0;
> +}
For both of these, can't a user trigger the
WARN_ON(!vdev->iommufd_device) if they call either of these before
VFIO_DEVICE_BIND_IOMMUFD? Thanks,
Alex
> +
> static char *vfio_device_devnode(const struct device *dev, umode_t *mode)
> {
> return kasprintf(GFP_KERNEL, "vfio/devices/%s", dev_name(dev));
> diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
> index ace3d52b0928..c199e410db18 100644
> --- a/drivers/vfio/vfio.h
> +++ b/drivers/vfio/vfio.h
> @@ -284,6 +284,10 @@ int vfio_device_fops_cdev_open(struct inode *inode,
> struct file *filep);
> void vfio_device_cdev_close(struct vfio_device_file *df);
> long vfio_device_ioctl_bind_iommufd(struct vfio_device_file *df,
> struct vfio_device_bind_iommufd __user
> *arg);
> +int vfio_ioctl_device_attach(struct vfio_device_file *df,
> + struct vfio_device_attach_iommufd_pt __user *arg);
> +int vfio_ioctl_device_detach(struct
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/scdc-helper: Pimp SCDC debugs
== Series Details == Series: drm/scdc-helper: Pimp SCDC debugs URL : https://patchwork.freedesktop.org/series/115807/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12937 -> Patchwork_115807v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_115807v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_115807v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115807v1/index.html Participating hosts (36 -> 35) -- Additional (1): fi-pnv-d510 Missing(2): fi-kbl-soraka fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_115807v1: ### IGT changes ### Possible regressions * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-a-vga-1: - fi-hsw-4770:[PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/fi-hsw-4770/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-a-vga-1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115807v1/fi-hsw-4770/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-a-vga-1.html * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-b-vga-1: - fi-hsw-4770:[PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/fi-hsw-4770/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-b-vga-1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115807v1/fi-hsw-4770/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-b-vga-1.html Known issues Here are the changes found in Patchwork_115807v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - bat-rpls-1: [PASS][5] -> [ABORT][6] ([i915#6687] / [i915#7978]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115807v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@migrate: - bat-adlp-9: [PASS][7] -> [DMESG-FAIL][8] ([i915#7699]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-adlp-9/igt@i915_selftest@l...@migrate.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115807v1/bat-adlp-9/igt@i915_selftest@l...@migrate.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#7828]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115807v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1: - bat-dg2-8: [PASS][10] -> [FAIL][11] ([i915#7932]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115807v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html * igt@kms_psr@primary_page_flip: - fi-pnv-d510:NOTRUN -> [SKIP][12] ([fdo#109271]) +38 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115807v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html Possible fixes * igt@i915_selftest@live@gt_heartbeat: - fi-glk-j4005: [DMESG-FAIL][13] ([i915#5334]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115807v1/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@hangcheck: - bat-dg2-11: [ABORT][15] ([i915#7913]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12937/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115807v1/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932 [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978 Build changes - * Linux: CI_DRM_12937 -> Patchwork_115807v1 CI-20190529: 20190529 CI_DRM_12937:
Re: [Intel-gfx] [PATCH 2/2] drm/i915/mtl: Add Wa_22015279794
On Wed, Mar 29, 2023 at 05:24:51PM -0300, Gustavo Sousa wrote: > From: Radhakrishna Sripada > > Wa_22015279794 applies to MTL P from stepping A0 to B0 (exclusive). > > Signed-off-by: Radhakrishna Sripada > Signed-off-by: Gustavo Sousa Reviewed-by: Matt Roper > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 ++ > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + > 2 files changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 1ec855813632..35a4cfac2d20 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1156,7 +1156,13 @@ > #define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10) > #define DISABLE_ECCREG_BIT(5) > #define FLOAT_BLEND_OPTIMIZATION_ENABLEREG_BIT(4) > +/* > + * We have both ENABLE and DISABLE defines below using the same bit because > the > + * meaning depends on the target platform. There are no platform prefix for > them > + * because different steppings of DG2 pick one or the other semantics. > + */ > #define ENABLE_PREFETCH_INTO_ICREG_BIT(3) > +#define DISABLE_PREFETCH_INTO_IC REG_BIT(3) > > #define EU_PERF_CNTL0PERF_REG(0xe458) > #define EU_PERF_CNTL4PERF_REG(0xe45c) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index cafdf66d9562..29d09ddfc8a9 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2979,6 +2979,11 @@ general_render_compute_wa_init(struct intel_engine_cs > *engine, struct i915_wa_li > wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, >MTL_DISABLE_SAMPLER_SC_OOO); > > + if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) > + /* Wa_22015279794 */ > + wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, > + DISABLE_PREFETCH_INTO_IC); > + > if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || > IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || > IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || > -- > 2.40.0 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
Re: [Intel-gfx] [PATCH 1/2] drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203
On Wed, Mar 29, 2023 at 05:24:50PM -0300, Gustavo Sousa wrote:
> From: Radhakrishna Sripada
>
> Both workarounds require the same implementation and apply to MTL P and
> M from stepping A0 to B0 (exclusive).
>
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++--
> 2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 4aecb5a7b631..1ec855813632 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1144,6 +1144,7 @@
> #define ENABLE_SMALLPL REG_BIT(15)
> #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
> #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
> +#define MTL_DISABLE_SAMPLER_SC_OOO REG_BIT(3)
>
> #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
> #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLAREG_BIT(15)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e7ee24bcad89..cafdf66d9562 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2388,11 +2388,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> struct drm_i915_private *i915 = engine->i915;
>
> if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> /* Wa_22014600077 */
> wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>ENABLE_EU_COUNT_FOR_TDL_FLUSH);
> - }
The brace removal here doesn't seem to be related to this patch.
Aside from that, the actual workaround addition below is
Reviewed-by: Matt Roper
>
> if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> @@ -2971,6 +2970,15 @@ general_render_compute_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_li
>
> add_render_compute_tuning_settings(i915, wal);
>
> + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> + /*
> + * Wa_14017066071
> + * Wa_14017654203
> + */
> + wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> + MTL_DISABLE_SAMPLER_SC_OOO);
> +
> if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> --
> 2.40.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [PATCH v8 21/24] vfio: Add VFIO_DEVICE_BIND_IOMMUFD
On Mon, 27 Mar 2023 02:40:44 -0700
Yi Liu wrote:
> This adds ioctl for userspace to bind device cdev fd to iommufd.
>
> VFIO_DEVICE_BIND_IOMMUFD: bind device to an iommufd, hence gain DMA
> control provided by the iommufd. open_device
> op is called after bind_iommufd op.
> VFIO no iommu mode is indicated by passing
> a negative iommufd value.
>
> Reviewed-by: Kevin Tian
> Tested-by: Terrence Xu
> Signed-off-by: Yi Liu
> ---
> drivers/vfio/device_cdev.c | 153 +
> drivers/vfio/vfio.h| 13
> drivers/vfio/vfio_main.c | 5 ++
> include/uapi/linux/vfio.h | 37 +
> 4 files changed, 208 insertions(+)
>
> diff --git a/drivers/vfio/device_cdev.c b/drivers/vfio/device_cdev.c
> index 1c640016a824..2b563bac50b9 100644
> --- a/drivers/vfio/device_cdev.c
> +++ b/drivers/vfio/device_cdev.c
> @@ -3,6 +3,7 @@
> * Copyright (c) 2023 Intel Corporation.
> */
> #include
> +#include
>
> #include "vfio.h"
>
> @@ -44,6 +45,158 @@ int vfio_device_fops_cdev_open(struct inode *inode,
> struct file *filep)
> return ret;
> }
>
> +static void vfio_device_get_kvm_safe(struct vfio_device_file *df)
> +{
> + spin_lock(>kvm_ref_lock);
> + if (df->kvm)
> + _vfio_device_get_kvm_safe(df->device, df->kvm);
> + spin_unlock(>kvm_ref_lock);
> +}
> +
> +void vfio_device_cdev_close(struct vfio_device_file *df)
> +{
> + struct vfio_device *device = df->device;
> +
> + /*
> + * As df->access_granted writer is under dev_set->lock as well,
> + * so this read no need to use smp_load_acquire() to pair with
Nit, "no need to use" -> "does not need to use"
> + * smp_store_release() in the caller of vfio_device_open().
> + */
> + if (!df->access_granted)
> + return;
> +
Isn't the lock we're acquiring below the one that we claim to have in
the comment above to make the non-smp_load_acquire() test safe?
> + mutex_lock(>dev_set->lock);
> + vfio_device_close(df);
> + vfio_device_put_kvm(device);
> + if (df->iommufd)
> + iommufd_ctx_put(df->iommufd);
> + mutex_unlock(>dev_set->lock);
> + vfio_device_unblock_group(device);
> +}
> +
> +static int vfio_device_cdev_enable_noiommu(struct vfio_device *device)
> +{
> + if (!capable(CAP_SYS_RAWIO))
> + return -EPERM;
> +
> + if (!device->noiommu)
> + return -EINVAL;
> +
> + return 0;
> +}
This is testing, not enabling. ie. naming nit.
> +
> +static struct iommufd_ctx *vfio_get_iommufd_from_fd(int fd)
> +{
> + struct fd f;
> + struct iommufd_ctx *iommufd;
> +
> + f = fdget(fd);
> + if (!f.file)
> + return ERR_PTR(-EBADF);
> +
> + iommufd = iommufd_ctx_from_file(f.file);
> +
> + fdput(f);
> + return iommufd;
> +}
> +
> +long vfio_device_ioctl_bind_iommufd(struct vfio_device_file *df,
> + struct vfio_device_bind_iommufd __user *arg)
> +{
> + struct vfio_device *device = df->device;
> + struct vfio_device_bind_iommufd bind;
> + struct iommufd_ctx *iommufd = NULL;
> + unsigned long minsz;
> + int ret;
> +
> + static_assert(__same_type(arg->out_devid, bind.out_devid));
They're the same field in the same structure, how could they be
otherwise?
> +
> + minsz = offsetofend(struct vfio_device_bind_iommufd, out_devid);
> +
> + if (copy_from_user(, arg, minsz))
> + return -EFAULT;
> +
> + if (bind.argsz < minsz || bind.flags)
> + return -EINVAL;
> +
> + if (!device->ops->bind_iommufd)
> + return -ENODEV;
This test seems beyond normal paranoia since we test in
__vfio_register_dev()
> +
> + /* BIND_IOMMUFD only allowed for cdev fds */
> + if (df->group)
> + return -EINVAL;
> +
> + ret = vfio_device_block_group(device);
> + if (ret)
> + return ret;
> +
> + mutex_lock(>dev_set->lock);
> + /* one device cannot be bound twice */
> + if (df->access_granted) {
> + ret = -EINVAL;
> + goto out_unlock;
> + }
> +
> + /* iommufd < 0 means noiommu mode */
> + if (bind.iommufd < 0) {
> + ret = vfio_device_cdev_enable_noiommu(device);
> + if (ret)
> + goto out_unlock;
> + } else {
> + iommufd = vfio_get_iommufd_from_fd(bind.iommufd);
> + if (IS_ERR(iommufd)) {
> + ret = PTR_ERR(iommufd);
> + goto out_unlock;
> + }
> + }
> +
> + /*
> + * Before the device open, get the KVM pointer currently
> + * associated with the device file (if there is) and obtain
> + * a reference. This reference is held until device closed.
> + * Save the pointer in the device for use by drivers.
> + */
> +
[Intel-gfx] [PATCH 1/2] drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203
From: Radhakrishna Sripada
Both workarounds require the same implementation and apply to MTL P and
M from stepping A0 to B0 (exclusive).
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 4aecb5a7b631..1ec855813632 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1144,6 +1144,7 @@
#define ENABLE_SMALLPL REG_BIT(15)
#define SC_DISABLE_POWER_OPTIMIZATION_EBBREG_BIT(9)
#define GEN11_SAMPLER_ENABLE_HEADLESS_MSGREG_BIT(5)
+#define MTL_DISABLE_SAMPLER_SC_OOO REG_BIT(3)
#define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e7ee24bcad89..cafdf66d9562 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2388,11 +2388,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
struct drm_i915_private *i915 = engine->i915;
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
/* Wa_22014600077 */
wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
ENABLE_EU_COUNT_FOR_TDL_FLUSH);
- }
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
@@ -2971,6 +2970,15 @@ general_render_compute_wa_init(struct intel_engine_cs
*engine, struct i915_wa_li
add_render_compute_tuning_settings(i915, wal);
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ /*
+* Wa_14017066071
+* Wa_14017654203
+*/
+ wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
+MTL_DISABLE_SAMPLER_SC_OOO);
+
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
--
2.40.0
[Intel-gfx] [PATCH 2/2] drm/i915/mtl: Add Wa_22015279794
From: Radhakrishna Sripada Wa_22015279794 applies to MTL P from stepping A0 to B0 (exclusive). Signed-off-by: Radhakrishna Sripada Signed-off-by: Gustavo Sousa --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 ++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 1ec855813632..35a4cfac2d20 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1156,7 +1156,13 @@ #define ENABLE_EU_COUNT_FOR_TDL_FLUSHREG_BIT(10) #define DISABLE_ECC REG_BIT(5) #define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4) +/* + * We have both ENABLE and DISABLE defines below using the same bit because the + * meaning depends on the target platform. There are no platform prefix for them + * because different steppings of DG2 pick one or the other semantics. + */ #define ENABLE_PREFETCH_INTO_IC REG_BIT(3) +#define DISABLE_PREFETCH_INTO_IC REG_BIT(3) #define EU_PERF_CNTL0 PERF_REG(0xe458) #define EU_PERF_CNTL4 PERF_REG(0xe45c) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index cafdf66d9562..29d09ddfc8a9 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2979,6 +2979,11 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, MTL_DISABLE_SAMPLER_SC_OOO); + if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) + /* Wa_22015279794 */ + wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, +DISABLE_PREFETCH_INTO_IC); + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || -- 2.40.0
[Intel-gfx] [PATCH 0/2] Add MTL Wa_14017066071, Wa_14017654203 and Wa_22015279794
Add some GT workarounds for MTL. Note that Wa_14017066071 and Wa_14017654203 require the same implementation and have the same platform and stepping bounds, so there is a single patch for them. Radhakrishna Sripada (2): drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203 drm/i915/mtl: Add Wa_22015279794 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 +++-- 2 files changed, 22 insertions(+), 2 deletions(-) -- 2.40.0
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add support for MTL GSC SW Proxy
== Series Details == Series: drm/i915: Add support for MTL GSC SW Proxy URL : https://patchwork.freedesktop.org/series/115806/ State : success == Summary == CI Bug Log - changes from CI_DRM_12936 -> Patchwork_115806v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v1/index.html Participating hosts (37 -> 35) -- Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_115806v1 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [PASS][1] -> [DMESG-FAIL][2] ([i915#5334]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@slpc: - bat-rpls-1: NOTRUN -> [DMESG-FAIL][3] ([i915#6367]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html - bat-adlp-9: [PASS][4] -> [DMESG-FAIL][5] ([i915#6367]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-adlp-9/igt@i915_selftest@l...@slpc.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v1/bat-adlp-9/igt@i915_selftest@l...@slpc.html * igt@i915_selftest@live@workarounds: - bat-dg2-11: [PASS][6] -> [INCOMPLETE][7] ([i915#7913]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-11/igt@i915_selftest@l...@workarounds.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v1/bat-dg2-11/igt@i915_selftest@l...@workarounds.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - fi-bsw-nick:NOTRUN -> [SKIP][8] ([fdo#109271]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v1/fi-bsw-nick/igt@kms_chamelium_...@common-hpd-after-suspend.html - bat-rpls-1: NOTRUN -> [SKIP][9] ([i915#7828]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v1/bat-rpls-1/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#5354]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@kms_pipe_crc_basic@read-crc: - bat-adlp-9: NOTRUN -> [SKIP][11] ([i915#3546]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v1/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html * igt@kms_pipe_crc_basic@suspend-read-crc: - bat-rpls-1: NOTRUN -> [SKIP][12] ([i915#1845]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v1/bat-rpls-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html Possible fixes * igt@gem_exec_suspend@basic-s3@smem: - bat-rpls-1: [ABORT][13] ([i915#6687] / [i915#7978]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@execlists: - fi-bsw-nick:[ABORT][15] ([i915#7911] / [i915#7913]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@mman: - bat-rpls-1: [TIMEOUT][17] ([i915#6794]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-rpls-1/igt@i915_selftest@l...@mman.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v1/bat-rpls-1/igt@i915_selftest@l...@mman.html * igt@i915_selftest@live@slpc: - bat-rplp-1: [DMESG-FAIL][19] ([i915#6367] / [i915#7913]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-rplp-1/igt@i915_selftest@l...@slpc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v1/bat-rplp-1/igt@i915_selftest@l...@slpc.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1: - bat-dg2-8: [FAIL][21] ([i915#7932]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115806v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1845]:
Re: [Intel-gfx] [PATCH v3 2/6] iommufd: Create access in vfio_iommufd_emulated_bind()
On Mon, Mar 27, 2023 at 02:33:47AM -0700, Yi Liu wrote:
> @@ -494,6 +479,30 @@ void iommufd_access_destroy(struct iommufd_access
> *access)
> }
> EXPORT_SYMBOL_NS_GPL(iommufd_access_destroy, IOMMUFD);
>
> +int iommufd_access_attach(struct iommufd_access *access, u32 ioas_id)
> +{
> + struct iommufd_ioas *new_ioas;
> + int rc = 0;
> +
> + if (access->ioas != NULL && access->ioas->obj.id != ioas_id)
> + return -EINVAL;
This should just be
if (access->ioas)
return -EINVAL;
> +
> + new_ioas = iommufd_get_ioas(access->ictx, ioas_id);
> + if (IS_ERR(new_ioas))
> + return PTR_ERR(new_ioas);
> +
> + rc = iopt_add_access(_ioas->iopt, access);
> + if (rc) {
> + iommufd_put_object(_ioas->obj);
> + return rc;
> + }
> + iommufd_ref_to_users(_ioas->obj);
> +
> + access->ioas = new_ioas;
Since if ioas is non-null here then we will lose the reference counts
already held.
I'll fix it
Jason
Re: [Intel-gfx] [PATCH v8 20/24] vfio: Add cdev for vfio_device
On Mon, 27 Mar 2023 02:40:43 -0700
Yi Liu wrote:
> This allows user to directly open a vfio device w/o using the legacy
> container/group interface, as a prerequisite for supporting new iommu
> features like nested translation.
>
> The device fd opened in this manner doesn't have the capability to access
> the device as the fops open() doesn't open the device until the successful
> BIND_IOMMUFD which be added in next patch.
>
> With this patch, devices registered to vfio core have both group and device
> interface created.
>
> - group interface : /dev/vfio/$groupID
> - device interface: /dev/vfio/devices/vfioX - normal device
> /dev/vfio/devices/noiommu-vfioX - noiommu device
> ("X" is the minor number and is unique across devices)
>
> Given a vfio device the user can identify the matching vfioX by checking
> the sysfs path of the device. Take PCI device (:6a:01.0) for example,
> /sys/bus/pci/devices/\:6a\:01.0/vfio-dev/vfio0/dev contains the
> major:minor of the matching vfioX.
>
> Userspace then opens the /dev/vfio/devices/vfioX and checks with fstat
> that the major:minor matches.
>
> The vfio_device cdev logic in this patch:
> *) __vfio_register_dev() path ends up doing cdev_device_add() for each
>vfio_device if VFIO_DEVICE_CDEV configured.
> *) vfio_unregister_group_dev() path does cdev_device_del();
>
> Reviewed-by: Kevin Tian
> Tested-by: Terrence Xu
> Tested-by: Nicolin Chen
> Tested-by: Matthew Rosato
> Signed-off-by: Yi Liu
> ---
> drivers/vfio/Kconfig | 11 +++
> drivers/vfio/Makefile | 1 +
> drivers/vfio/device_cdev.c | 62 ++
> drivers/vfio/vfio.h| 46
> drivers/vfio/vfio_main.c | 26 +++-
> include/linux/vfio.h | 4 +++
> 6 files changed, 143 insertions(+), 7 deletions(-)
> create mode 100644 drivers/vfio/device_cdev.c
>
> diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig
> index 89e06c981e43..e2105b4dac2d 100644
> --- a/drivers/vfio/Kconfig
> +++ b/drivers/vfio/Kconfig
> @@ -12,6 +12,17 @@ menuconfig VFIO
> If you don't know what to do here, say N.
>
> if VFIO
> +config VFIO_DEVICE_CDEV
> + bool "Support for the VFIO cdev /dev/vfio/devices/vfioX"
> + depends on IOMMUFD
> + help
> + The VFIO device cdev is another way for userspace to get device
> + access. Userspace gets device fd by opening device cdev under
> + /dev/vfio/devices/vfioX, and then bind the device fd with an iommufd
> + to set up secure DMA context for device access.
> +
> + If you don't know what to do here, say N.
> +
> config VFIO_CONTAINER
> bool "Support for the VFIO container /dev/vfio/vfio"
> select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64)
> diff --git a/drivers/vfio/Makefile b/drivers/vfio/Makefile
> index 70e7dcb302ef..245394aeb94b 100644
> --- a/drivers/vfio/Makefile
> +++ b/drivers/vfio/Makefile
> @@ -4,6 +4,7 @@ obj-$(CONFIG_VFIO) += vfio.o
> vfio-y += vfio_main.o \
> group.o \
> iova_bitmap.o
> +vfio-$(CONFIG_VFIO_DEVICE_CDEV) += device_cdev.o
> vfio-$(CONFIG_IOMMUFD) += iommufd.o
> vfio-$(CONFIG_VFIO_CONTAINER) += container.o
> vfio-$(CONFIG_VFIO_VIRQFD) += virqfd.o
> diff --git a/drivers/vfio/device_cdev.c b/drivers/vfio/device_cdev.c
> new file mode 100644
> index ..1c640016a824
> --- /dev/null
> +++ b/drivers/vfio/device_cdev.c
> @@ -0,0 +1,62 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2023 Intel Corporation.
> + */
> +#include
> +
> +#include "vfio.h"
> +
> +static dev_t device_devt;
> +
> +void vfio_init_device_cdev(struct vfio_device *device)
> +{
> + device->device.devt = MKDEV(MAJOR(device_devt), device->index);
> + cdev_init(>cdev, _device_fops);
> + device->cdev.owner = THIS_MODULE;
> +}
> +
> +/*
> + * device access via the fd opened by this function is blocked until
> + * .open_device() is called successfully during BIND_IOMMUFD.
> + */
> +int vfio_device_fops_cdev_open(struct inode *inode, struct file *filep)
> +{
> + struct vfio_device *device = container_of(inode->i_cdev,
> + struct vfio_device, cdev);
> + struct vfio_device_file *df;
> + int ret;
> +
> + if (!vfio_device_try_get_registration(device))
> + return -ENODEV;
> +
> + df = vfio_allocate_device_file(device);
> + if (IS_ERR(df)) {
> + ret = PTR_ERR(df);
> + goto err_put_registration;
> + }
> +
> + filep->private_data = df;
> +
> + return 0;
> +
> +err_put_registration:
> + vfio_device_put_registration(device);
> + return ret;
> +}
> +
> +static char *vfio_device_devnode(const struct device *dev, umode_t *mode)
> +{
> + return kasprintf(GFP_KERNEL, "vfio/devices/%s", dev_name(dev));
> +}
> +
> +int vfio_cdev_init(struct class *device_class)
> +{
> + device_class->devnode =
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Add support for MTL GSC SW Proxy
== Series Details == Series: drm/i915: Add support for MTL GSC SW Proxy URL : https://patchwork.freedesktop.org/series/115806/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add support for MTL GSC SW Proxy
== Series Details ==
Series: drm/i915: Add support for MTL GSC SW Proxy
URL : https://patchwork.freedesktop.org/series/115806/
State : warning
== Summary ==
Error: dim checkpatch failed
cd5858341f03 drm/i915/mtl: Define GSC Proxy component interface
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#30:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 45 lines checked
9b6e1a1d6cf0 mei: gsc_proxy: add gsc proxy driver
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#35:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 238 lines checked
2429872a6959 drm/i915/gsc: add initial support for GSC proxy
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:45: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#45:
new file mode 100644
-:50: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#50: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c:1:
+#include "intel_gsc_proxy.h"
-:52: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#52: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c:3:
+// SPDX-License-Identifier: MIT
-:99: ERROR:OPEN_BRACE: open brace '{' following struct go on the same line
#99: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c:50:
+struct intel_gsc_proxy_header
+{
-:129: ERROR:OPEN_BRACE: open brace '{' following struct go on the same line
#129: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c:80:
+struct gsc_proxy_msg
+{
-:189: WARNING:MEMORY_BARRIER: memory barrier without comment
#189: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c:140:
+ wmb();
-:232: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#232: FILE: drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c:183:
+
+}
total: 2 errors, 4 warnings, 1 checks, 525 lines checked
c90211076ba2 drm/i915/gsc: add support for GSC proxy interrupt
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Replace kmap_atomic() with kmap_local_page()
== Series Details ==
Series: drm/i915: Replace kmap_atomic() with kmap_local_page()
URL : https://patchwork.freedesktop.org/series/115769/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12931_full -> Patchwork_115769v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_115769v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- {shard-tglu}: [SKIP][1] ([fdo#111614]) -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-tglu-7/igt@kms_big...@x-tiled-8bpp-rotate-270.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115769v1/shard-tglu-3/igt@kms_big...@x-tiled-8bpp-rotate-270.html
Known issues
Here are the changes found in Patchwork_115769v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115769v1/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-apl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115769v1/shard-apl6/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115769v1/shard-glk8/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#3886])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115769v1/shard-glk8/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#79])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vbl...@bc-hdmi-a1-hdmi-a2.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115769v1/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vbl...@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [PASS][11] -> [ABORT][12] ([i915#180])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-apl3/igt@kms_flip@flip-vs-suspend-interrupti...@a-dp1.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115769v1/shard-apl6/igt@kms_flip@flip-vs-suspend-interrupti...@a-dp1.html
*
igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271]) +52 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115769v1/shard-glk8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscal...@pipe-a-valid-mode.html
* igt@kms_psr2_su@frontbuffer-xrgb:
- shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#658])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115769v1/shard-glk8/igt@kms_psr2...@frontbuffer-xrgb.html
Possible fixes
* igt@gem_exec_endless@dispatch@vcs1:
- {shard-tglu}: [TIMEOUT][15] ([i915#3778]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-tglu-9/igt@gem_exec_endless@dispa...@vcs1.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115769v1/shard-tglu-6/igt@gem_exec_endless@dispa...@vcs1.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- {shard-dg1}:[DMESG-WARN][17] ([i915#4936]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-dg1-16/igt@gem_lmem_swapping@smem-...@lmem0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115769v1/shard-dg1-15/igt@gem_lmem_swapping@smem-...@lmem0.html
* igt@kms_addfb_basic@size-max:
- {shard-dg1}:[DMESG-WARN][19] -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-dg1-17/igt@kms_addfb_ba...@size-max.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115769v1/shard-dg1-18/igt@kms_addfb_ba...@size-max.html
*
Re: [Intel-gfx] [PATCH v3 0/6] vfio: Make emulated devices prepared for vfio device cdev
On Mon, Mar 27, 2023 at 02:33:45AM -0700, Yi Liu wrote: > Nicolin Chen (1): > iommufd: Create access in vfio_iommufd_emulated_bind() > > Yi Liu (5): > iommu/iommufd: Pass iommufd_ctx pointer in iommufd_get_ioas() > vfio-iommufd: No need to record iommufd_ctx in vfio_device > vfio-iommufd: Make vfio_iommufd_emulated_bind() return iommufd_access > ID > vfio/mdev: Uses the vfio emulated iommufd ops set in the mdev sample > drivers > vfio: Check the presence for iommufd callbacks in > __vfio_register_dev() > > drivers/iommu/iommufd/device.c | 55 +++-- > drivers/iommu/iommufd/ioas.c| 14 +++ > drivers/iommu/iommufd/iommufd_private.h | 4 +- > drivers/iommu/iommufd/selftest.c| 14 --- > drivers/iommu/iommufd/vfio_compat.c | 2 +- > drivers/vfio/iommufd.c | 37 - > drivers/vfio/vfio_main.c| 5 ++- > include/linux/iommufd.h | 5 ++- > include/linux/vfio.h| 1 - > samples/vfio-mdev/mbochs.c | 3 ++ > samples/vfio-mdev/mdpy.c| 3 ++ > samples/vfio-mdev/mtty.c| 3 ++ > 12 files changed, 85 insertions(+), 61 deletions(-) It looks like most of this is iommufd so I will take it - Ok Alex? The following cdev patch needs it so I'll stick it on its own branch and we can sort it out after the reset series is done Thanls, Jason
Re: [Intel-gfx] [PATCH 1/2] drm/i915/display: Restore dsparb_lock.
On Tue, Mar 28, 2023 at 07:22:24PM +0300, Jani Nikula wrote:
> On Mon, 27 Mar 2023, Rodrigo Vivi wrote:
> > uncore->lock only protects the forcewake domain itself,
> > not the register accesses.
> >
> > uncore's _fw alternatives are for cases where the domains
> > are not needed because we are sure that they are already
> > awake.
> >
> > So the move towards the uncore's _fw alternatives seems
> > right, however using the uncore-lock to protect the dsparb
> > registers seems an abuse of the uncore-lock.
> >
> > Let's restore the previous individual lock and try to get
> > rid of the direct uncore accesses from the display code.
> >
> > Cc: Ville Syrjälä
> > Cc: Jani Nikula
> > Signed-off-by: Rodrigo Vivi
> > Reviewed-by: Ville Syrjälä
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20230308165859.235520-1-rodrigo.v...@intel.com
> > ---
> > drivers/gpu/drm/i915/display/i9xx_wm.c| 13 ++---
> > drivers/gpu/drm/i915/display/intel_display_core.h | 3 +++
> > drivers/gpu/drm/i915/i915_driver.c| 1 +
> > 3 files changed, 6 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
> > b/drivers/gpu/drm/i915/display/i9xx_wm.c
> > index caef72d38798..8fe0b5c63d3a 100644
> > --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> > +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> > @@ -1771,16 +1771,7 @@ static void vlv_atomic_update_fifo(struct
> > intel_atomic_state *state,
> >
> > trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
> >
> > - /*
> > -* uncore.lock serves a double purpose here. It allows us to
> > -* use the less expensive I915_{READ,WRITE}_FW() functions, and
> > -* it protects the DSPARB registers from getting clobbered by
> > -* parallel updates from multiple pipes.
> > -*
> > -* intel_pipe_update_start() has already disabled interrupts
> > -* for us, so a plain spin_lock() is sufficient here.
> > -*/
> > - spin_lock(>lock);
> > + spin_lock(_priv->display.wm.dsparb_lock);
> >
> > switch (crtc->pipe) {
> > case PIPE_A:
> > @@ -1840,7 +1831,7 @@ static void vlv_atomic_update_fifo(struct
> > intel_atomic_state *state,
> >
> > intel_uncore_posting_read_fw(uncore, DSPARB);
> >
> > - spin_unlock(>lock);
> > + spin_unlock(_priv->display.wm.dsparb_lock);
> > }
> >
> > #undef VLV_FIFO
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> > b/drivers/gpu/drm/i915/display/intel_display_core.h
> > index 0b5509f268a7..e4da8902c878 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > @@ -264,6 +264,9 @@ struct intel_wm {
> > */
> > struct mutex wm_mutex;
> >
> > + /* protects DSPARB registers on pre-g4x/vlv/chv */
> > + spinlock_t dsparb_lock;
> > +
> > bool ipc_enabled;
> > };
> >
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c
> > b/drivers/gpu/drm/i915/i915_driver.c
> > index 12b5296ee744..e90a0c0403a6 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -223,6 +223,7 @@ static int i915_driver_early_probe(struct
> > drm_i915_private *dev_priv)
> > mutex_init(_priv->display.pps.mutex);
> > mutex_init(_priv->display.hdcp.comp_mutex);
> > spin_lock_init(_priv->display.dkl.phy_lock);
> > + spin_lock_init(_priv->display.wm.dsparb_lock);
>
> Can we do this in i9xx_wm_init() instead?
I was going to modify it here right now, but then I noticed
the cases above and remembered why I have put it here.
All the display locks are getting set in here.
Probably better to move with this patch as is and then add
a new on top moving the various locks to its individual inits?
>
>
> >
> > i915_memcpy_init_early(dev_priv);
> > intel_runtime_pm_init_early(_priv->runtime_pm);
>
> --
> Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✓ Fi.CI.BAT: success for High refresh rate PSR fixes (rev7)
== Series Details == Series: High refresh rate PSR fixes (rev7) URL : https://patchwork.freedesktop.org/series/115109/ State : success == Summary == CI Bug Log - changes from CI_DRM_12936 -> Patchwork_115109v7 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v7/index.html Participating hosts (37 -> 35) -- Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_115109v7 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rps@basic-api: - bat-dg2-11: [PASS][1] -> [FAIL][2] ([i915#8308]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-11/igt@i915_pm_...@basic-api.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v7/bat-dg2-11/igt@i915_pm_...@basic-api.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - fi-bsw-nick:NOTRUN -> [SKIP][3] ([fdo#109271]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v7/fi-bsw-nick/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][4] ([i915#5354]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v7/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html Possible fixes * igt@i915_selftest@live@execlists: - fi-bsw-nick:[ABORT][5] ([i915#7911] / [i915#7913]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v7/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@migrate: - bat-dg2-11: [DMESG-WARN][7] ([i915#7699]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-11/igt@i915_selftest@l...@migrate.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v7/bat-dg2-11/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@mman: - bat-rpls-1: [TIMEOUT][9] ([i915#6794]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-rpls-1/igt@i915_selftest@l...@mman.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v7/bat-rpls-1/igt@i915_selftest@l...@mman.html * igt@i915_selftest@live@slpc: - bat-rplp-1: [DMESG-FAIL][11] ([i915#6367] / [i915#7913]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-rplp-1/igt@i915_selftest@l...@slpc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v7/bat-rplp-1/igt@i915_selftest@l...@slpc.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1: - bat-dg2-8: [FAIL][13] ([i915#7932]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v7/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932 [i915#8308]: https://gitlab.freedesktop.org/drm/intel/issues/8308 Build changes - * Linux: CI_DRM_12936 -> Patchwork_115109v7 CI-20190529: 20190529 CI_DRM_12936: 906438caae695f109636f82e2d1845a258f57d8b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7226: 41be8b4ab86f9e11388c10366dfd71e5032589c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_115109v7: 906438caae695f109636f82e2d1845a258f57d8b @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits b2d07f7e0984 drm/i915/psr: Implement Display WA #1136 efee1595a60b drm/i915/psr: Check that vblank is long enough for psr2 97f718ec83eb drm/i915/psr: Add helpers for block count number handling 6b9a40d2e87d drm/i915/psr: Implement Wa_14015648006 1fbc701faf1d drm/i915/psr: Modify/Fix Wa_16013835468 and prepare for Wa_14015648006 f8ac1c827400 drm/i915/psr: Unify pre/post hooks == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v7/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for High refresh rate PSR fixes (rev7)
== Series Details == Series: High refresh rate PSR fixes (rev7) URL : https://patchwork.freedesktop.org/series/115109/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
[Intel-gfx] [PATCH 3/3] drm/i915: Define cursor chicken reg
From: Ville Syrjälä Define CUR_CHICKEN so we don't have to remember the offset. Looks like it's getting introduced in mtl. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 275ec891468c..f6a6f3b6c603 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3989,6 +3989,7 @@ #define CUR_FBC_EN REG_BIT(31) #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) #define CUR_FBC_HEIGHT(h)REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) +#define _CUR_CHICKEN_A 0x700a4 /* mtl+ */ #define _CURASURFLIVE 0x700ac /* g4x+ */ #define _CURBCNTR 0x700c0 #define _CURBBASE 0x700c4 @@ -4003,6 +4004,7 @@ #define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS) #define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE) #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A) +#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(pipe, _CUR_CHICKEN_A) #define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE) #define CURSOR_A_OFFSET 0x70080 -- 2.39.2
[Intel-gfx] [PATCH 2/3] drm/i915: Document that PLANE_CHICKEN are for tgl+
From: Ville Syrjälä Add tgl+ comments to the PLANE_CHICKEN registers which I apparently forgot to add when defining the registers. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_reg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8e4aca888b7a..275ec891468c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4655,8 +4655,8 @@ #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) -#define _PLANE_CHICKEN_1_A 0x7026C -#define _PLANE_CHICKEN_2_A 0x7036C +#define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */ +#define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */ #define PLANE_CHICKEN_DISABLE_DPTREG_BIT(19) /* mtl+ */ #define _PLANE_BUF_CFG_1_A 0x7027c #define _PLANE_BUF_CFG_2_A 0x7037c -- 2.39.2
[Intel-gfx] [PATCH 1/3] drm/i915: Skip cursor when writing PLANE_CHICKEN
From: Ville Syrjälä
Cursor is not a universal plane and thus doesn't have the
PLANE_CHICKEN register. Skip it.
Fixes: c5de248484af ("drm/i915/dpt: Add a modparam to disable DPT via the
chicken bit")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpt.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/display/intel_dpt.c
index 2bf5cce232d5..b8027392144d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -324,10 +324,14 @@ void intel_dpt_configure(struct intel_crtc *crtc)
enum pipe pipe = crtc->pipe;
enum plane_id plane_id;
- for_each_plane_id_on_crtc(crtc, plane_id)
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ if (plane_id == PLANE_CURSOR)
+ continue;
+
intel_de_rmw(i915, PLANE_CHICKEN(pipe, plane_id),
PLANE_CHICKEN_DISABLE_DPT,
i915->params.enable_dpt ? 0 :
PLANE_CHICKEN_DISABLE_DPT);
+ }
} else if (DISPLAY_VER(i915) == 13) {
intel_de_rmw(i915, CHICKEN_MISC_2,
CHICKEN_MISC_DISABLE_DPT,
--
2.39.2
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add CSC state readout/check
== Series Details == Series: drm/i915: Add CSC state readout/check URL : https://patchwork.freedesktop.org/series/115794/ State : success == Summary == CI Bug Log - changes from CI_DRM_12936 -> Patchwork_115794v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115794v1/index.html Participating hosts (37 -> 35) -- Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_115794v1 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gt_lrc: - bat-dg2-11: [PASS][1] -> [INCOMPLETE][2] ([i915#7609] / [i915#7913]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115794v1/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html * igt@i915_selftest@live@slpc: - bat-rpls-1: NOTRUN -> [DMESG-FAIL][3] ([i915#6367] / [i915#7996]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115794v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - fi-bsw-nick:NOTRUN -> [SKIP][4] ([fdo#109271]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115794v1/fi-bsw-nick/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#5354]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115794v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1: - bat-dg2-8: [PASS][6] -> [FAIL][7] ([i915#7932]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115794v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html Possible fixes * igt@i915_selftest@live@execlists: - fi-bsw-nick:[ABORT][8] ([i915#7911] / [i915#7913]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115794v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@mman: - bat-rpls-1: [TIMEOUT][10] ([i915#6794]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-rpls-1/igt@i915_selftest@l...@mman.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115794v1/bat-rpls-1/igt@i915_selftest@l...@mman.html * igt@i915_selftest@live@slpc: - bat-rplp-1: [DMESG-FAIL][12] ([i915#6367] / [i915#7913]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-rplp-1/igt@i915_selftest@l...@slpc.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115794v1/bat-rplp-1/igt@i915_selftest@l...@slpc.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1: - bat-dg2-8: [FAIL][14] ([i915#7932]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115794v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794 [i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609 [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932 [i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996 Build changes - * Linux: CI_DRM_12936 -> Patchwork_115794v1 CI-20190529: 20190529 CI_DRM_12936: 906438caae695f109636f82e2d1845a258f57d8b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7226: 41be8b4ab86f9e11388c10366dfd71e5032589c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_115794v1: 906438caae695f109636f82e2d1845a258f57d8b @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits b3184fd06e30 drm/i915: Do state check for color management changes 670191884f23 drm/i915: Hook up csc into state checker 6bcfe201fd6c drm/i915: Include the csc matrices in the crtc state dump e93adc454104 drm/i915: Implement chv cgm csc readout 11bbed66d0e6 drm/i915: Add hardware csc
Re: [Intel-gfx] [PATCH 5/8] drm/i915/psr: Define more PSR mask bits
On Tue, Mar 28, 2023 at 12:30:39PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Define more of the PSR mask bits, and describe in detail > what some of them do. Even if we don't set them all from > the driver they can be very useful during PSR debugging. > Having to trawl through bspec every time to find them is > not fun, and re-reverse engineering the behaviour every > time is time consuming (even if a bit more fun than spec > trawling). > > v2: Moar bits > Put the description into a comment to be easily available > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_psr.c | 85 > drivers/gpu/drm/i915/i915_reg.h | 27 ++-- > drivers/gpu/drm/i915/intel_pm.c | 4 +- > 3 files changed, 109 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 9e5ffe4eac6f..142cd174475e 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -84,6 +84,91 @@ > * use page flips. > */ > > +/* > + * Description of PSR mask bits: > + * > + * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl): > + * > + * When unmasked (nearly) all display register writes (eg. even > + * SWF) trigger a PSR exit. Some registers are excluded from this > + * and they have a more specific mask (described below). On icl+ > + * this bit no longer exists and is effectively always set. > + * > + * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+): > + * > + * When unmasked (nearly) all pipe/plane register writes > + * trigger a PSR exit. Some plane registers are excluded from this > + * and they have a more specific mask (described below). > + * > + * CHICKEN_PIPESL_1[11]/SKL_PSR_MASK_PLANE_FLIP (skl+): > + * PIPE_MISC[23]/PIPE_MISC_PSR_MASK_PRIMARY_FLIP (bdw): > + * EDP_PSR_DEBUG[23]/EDP_PSR_DEBUG_MASK_PRIMARY_FLIP (hsw): > + * > + * When unmasked PRI_SURF/PLANE_SURF writes trigger a PSR exit. > + * SPR_SURF/CURBASE are not included in this and instead are > + * controlled by PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+) or > + * EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw/bdw). > + * > + * PIPE_MISC[22]/PIPE_MISC_PSR_MASK_SPRITE_ENABLE (bdw): > + * EDP_PSR_DEBUG[21]/EDP_PSR_DEBUG_MASK_SPRITE_ENABLE (hsw): > + * > + * When unmasked PSR is blocked as long as the sprite > + * plane is enabled. skl+ with their universal planes no > + * longer have a mask bit like this, and no plane being > + * enabledb blocks PSR. > + * > + * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_CURSOR_MOVE (bdw): > + * EDP_PSR_DEBUG[20]/EDP_PSR_DEBUG_MASK_CURSOR_MOVE (hsw): > + * > + * When umasked CURPOS writes trigger a PSR exit. On skl+ > + * this doesn't exit but CURPOS is included in the > + * PIPE_MISC_PSR_MASK_PIPE_REG_WRITE mask. > + * > + * PIPE_MISC[20]/PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT (bdw+): > + * EDP_PSR_DEBUG[19]/EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT (hsw): > + * > + * When unmasked PSR is blocked as long as vblank and/or vsync > + * interrupt is unmasked in IMR *and* enabled in IER. > + * > + * CHICKEN_TRANS[30]/SKL_UNMASK_VBL_TO_PIPE_IN_SRD (skl+): > + * CHICKEN_PAR1_1[15]/HSW_MASK_VBL_TO_PIPE_IN_SRD (hsw/bdw): > + * > + * Selectcs whether PSR exit generates an extra vblank before > + * the first frame is transmitted. Also note the opposite polarity > + * if the bit on hsw/bdw vs. skl+ (masked==generate the extra vblank, > + * unmasked==do not generate the extra vblank). > + * > + * With DC states enabled the extra vblank happens after link training, > + * with DC states disabled it happens immediately upuon PSR exit trigger. > + * No idea as of now why there is a difference. HSW/BDW (which don't > + * even have DMC) always generate it after link training. Go figure. > + * > + * Unfortunately CHICKEN_TRANS itself seems to be double buffered > + * and thus won't latch until the first vblank. So with DC states > + * enabled the register effctively uses the reset value during DC5 > + * exit+PSR exit sequence, and thus the bit does nothing until > + * latched by the vblank that it was trying to prevent from being > + * generated in the first place. So we should probably call this > + * one a chicken/egg bit instead on skl+. > + * > + * In standby mode (as opposed to link-off) this makes no difference > + * as the timing generator keeps running the whole time generating > + * normal periodic vblanks. > + * > + * WaPsrDPAMaskVBlankInSRD asks us to set the bit on hsw/bdw, > + * and doing so makes the behaviour match the skl+ reset value. > + * > + * CHICKEN_PIPESL_1[0]/BDW_UNMASK_VBL_TO_REGS_IN_SRD (bdw): > + * CHICKEN_PIPESL_1[15]/HSW_UNMASK_VBL_TO_REGS_IN_SRD (hsw): > + * > + * Effect unknown. WaPsrDPRSUnmaskVBlankInSRD says to set the > + * bit, but not apparent change in hardware behaviour either > + * way. Actually there is a very clear effect on BDW; no vblanks whatsoever after PSR exit if the
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Add CSC state readout/check
== Series Details == Series: drm/i915: Add CSC state readout/check URL : https://patchwork.freedesktop.org/series/115794/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add CSC state readout/check
== Series Details ==
Series: drm/i915: Add CSC state readout/check
URL : https://patchwork.freedesktop.org/series/115794/
State : warning
== Summary ==
Error: dim checkpatch failed
01fd9db0cec9 drm/i915: Fix limited range csc matrix
e8f2d513ac2d drm/i915: Introduce intel_csc_matrix struct
40e623a7d092 drm/i915: Split chv_load_cgm_csc() into pieces
9fa8701c694e drm/i915: Start using struct intel_csc_matrix for chv cgm csc
3beb6ee5ef65 drm/i915: Store ilk+ csc matrices in the crtc state
-:124: WARNING:BRACES: braces {} are not necessary for any arm of this statement
#124: FILE: drivers/gpu/drm/i915/display/intel_color.c:408:
+ if (crtc_state->hw.ctm) {
[...]
+ } else {
[...]
total: 0 errors, 1 warnings, 0 checks, 168 lines checked
e9a4acb23fe0 drm/i915: Utilize crtc_state->csc on chv
-:65: WARNING:BRACES: braces {} are not necessary for any arm of this statement
#65: FILE: drivers/gpu/drm/i915/display/intel_color.c:479:
+ if (crtc_state->hw.ctm) {
[...]
+ } else {
[...]
total: 0 errors, 1 warnings, 0 checks, 71 lines checked
2d2e4f955511 drm/i915: Sprinke a few sanity check WARNS during csc assignment
6628bd2a5ab0 drm/i915: Add hardware csc readout for ilk+
249694979e1c drm/i915: Implement chv cgm csc readout
eed40cdf82d8 drm/i915: Include the csc matrices in the crtc state dump
-:37: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#37: FILE: drivers/gpu/drm/i915/display/intel_crtc_state_dump.c:174:
+ csc->coeff[3*i+0], csc->coeff[3*i+1],
csc->coeff[3*i+2]);
^
-:37: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#37: FILE: drivers/gpu/drm/i915/display/intel_crtc_state_dump.c:174:
+ csc->coeff[3*i+0], csc->coeff[3*i+1],
csc->coeff[3*i+2]);
^
-:37: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#37: FILE: drivers/gpu/drm/i915/display/intel_crtc_state_dump.c:174:
+ csc->coeff[3*i+0], csc->coeff[3*i+1],
csc->coeff[3*i+2]);
^
-:37: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#37: FILE: drivers/gpu/drm/i915/display/intel_crtc_state_dump.c:174:
+ csc->coeff[3*i+0], csc->coeff[3*i+1],
csc->coeff[3*i+2]);
^
-:37: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#37: FILE: drivers/gpu/drm/i915/display/intel_crtc_state_dump.c:174:
+ csc->coeff[3*i+0], csc->coeff[3*i+1],
csc->coeff[3*i+2]);
^
-:37: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#37: FILE: drivers/gpu/drm/i915/display/intel_crtc_state_dump.c:174:
+ csc->coeff[3*i+0], csc->coeff[3*i+1],
csc->coeff[3*i+2]);
^
-:56: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#56: FILE: drivers/gpu/drm/i915/display/intel_crtc_state_dump.c:193:
+ csc->coeff[3*i+0], csc->coeff[3*i+1],
csc->coeff[3*i+2]);
^
-:56: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#56: FILE: drivers/gpu/drm/i915/display/intel_crtc_state_dump.c:193:
+ csc->coeff[3*i+0], csc->coeff[3*i+1],
csc->coeff[3*i+2]);
^
-:56: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#56: FILE: drivers/gpu/drm/i915/display/intel_crtc_state_dump.c:193:
+ csc->coeff[3*i+0], csc->coeff[3*i+1],
csc->coeff[3*i+2]);
^
-:56: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#56: FILE: drivers/gpu/drm/i915/display/intel_crtc_state_dump.c:193:
+ csc->coeff[3*i+0], csc->coeff[3*i+1],
csc->coeff[3*i+2]);
^
-:56: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#56: FILE: drivers/gpu/drm/i915/display/intel_crtc_state_dump.c:193:
+ csc->coeff[3*i+0], csc->coeff[3*i+1],
csc->coeff[3*i+2]);
^
-:56: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#56: FILE: drivers/gpu/drm/i915/display/intel_crtc_state_dump.c:193:
+ csc->coeff[3*i+0], csc->coeff[3*i+1],
csc->coeff[3*i+2]);
^
total: 0 errors, 0 warnings, 12 checks, 55 lines checked
5c95dfdce9d4 drm/i915: Hook up csc into state checker
-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible
side-effects?
#22: FILE: drivers/gpu/drm/i915/display/intel_display.c:5646:
+#define
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/debugfs: drop debugfs_init() for the render and accel node v2
== Series Details == Series: series starting with [1/5] drm/debugfs: drop debugfs_init() for the render and accel node v2 URL : https://patchwork.freedesktop.org/series/115793/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12936 -> Patchwork_115793v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_115793v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_115793v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115793v1/index.html Participating hosts (37 -> 35) -- Missing(2): fi-kbl-soraka fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_115793v1: ### IGT changes ### Possible regressions * igt@gem_exec_suspend@basic-s0: - fi-kbl-8809g: NOTRUN -> [FAIL][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115793v1/fi-kbl-8809g/igt@gem_exec_susp...@basic-s0.html * igt@i915_module_load@reload: - fi-kbl-8809g: [PASS][2] -> [FAIL][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/fi-kbl-8809g/igt@i915_module_l...@reload.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115793v1/fi-kbl-8809g/igt@i915_module_l...@reload.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-tgl-1115g4: [PASS][4] -> [SKIP][5] +4 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/fi-tgl-1115g4/igt@i915_pm_...@basic-pci-d3-state.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115793v1/fi-tgl-1115g4/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_pm_rpm@basic-rte: - bat-rplp-1: [PASS][6] -> [SKIP][7] +5 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-rplp-1/igt@i915_pm_...@basic-rte.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115793v1/bat-rplp-1/igt@i915_pm_...@basic-rte.html - fi-rkl-11600: [PASS][8] -> [SKIP][9] +5 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/fi-rkl-11600/igt@i915_pm_...@basic-rte.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115793v1/fi-rkl-11600/igt@i915_pm_...@basic-rte.html - bat-dg2-9: [PASS][10] -> [SKIP][11] +4 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-9/igt@i915_pm_...@basic-rte.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115793v1/bat-dg2-9/igt@i915_pm_...@basic-rte.html * igt@i915_pm_rpm@module-reload: - bat-adls-5: [PASS][12] -> [SKIP][13] +5 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-adls-5/igt@i915_pm_...@module-reload.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115793v1/bat-adls-5/igt@i915_pm_...@module-reload.html - bat-dg1-5: [PASS][14] -> [SKIP][15] +4 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg1-5/igt@i915_pm_...@module-reload.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115793v1/bat-dg1-5/igt@i915_pm_...@module-reload.html - bat-dg2-11: [PASS][16] -> [SKIP][17] +4 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-11/igt@i915_pm_...@module-reload.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115793v1/bat-dg2-11/igt@i915_pm_...@module-reload.html * igt@kms_force_connector_basic@force-edid: - bat-dg2-8: [PASS][18] -> [SKIP][19] +4 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-8/igt@kms_force_connector_ba...@force-edid.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115793v1/bat-dg2-8/igt@kms_force_connector_ba...@force-edid.html - bat-jsl-1: [PASS][20] -> [SKIP][21] +5 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-jsl-1/igt@kms_force_connector_ba...@force-edid.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115793v1/bat-jsl-1/igt@kms_force_connector_ba...@force-edid.html - bat-rpls-1: [PASS][22] -> [SKIP][23] +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-rpls-1/igt@kms_force_connector_ba...@force-edid.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115793v1/bat-rpls-1/igt@kms_force_connector_ba...@force-edid.html - bat-adlp-9: [PASS][24] -> [SKIP][25] +5 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-adlp-9/igt@kms_force_connector_ba...@force-edid.html [25]:
Re: [Intel-gfx] [PATCH 2/5] drm/debugfs: rework debugfs directory creation v2
Hi Christian, I love your patch! Yet something to improve: [auto build test ERROR on drm-tip/drm-tip] url: https://github.com/intel-lab-lkp/linux/commits/Christian-K-nig/drm-debugfs-rework-debugfs-directory-creation-v2/20230329-212234 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip patch link: https://lore.kernel.org/r/20230329132130.105355-2-christian.koenig%40amd.com patch subject: [Intel-gfx] [PATCH 2/5] drm/debugfs: rework debugfs directory creation v2 config: hexagon-randconfig-r045-20230329 (https://download.01.org/0day-ci/archive/20230330/202303300140.xl9bhf8b-...@intel.com/config) compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project 67409911353323ca5edf2049ef0df54132fa1ca7) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/intel-lab-lkp/linux/commit/5da92df45b1b50f794218f0f494af20ecaf94d19 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Christian-K-nig/drm-debugfs-rework-debugfs-directory-creation-v2/20230329-212234 git checkout 5da92df45b1b50f794218f0f494af20ecaf94d19 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=hexagon olddefconfig COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=hexagon SHELL=/bin/bash drivers/gpu/ If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot | Link: https://lore.kernel.org/oe-kbuild-all/202303300140.xl9bhf8b-...@intel.com/ All errors (new ones prefixed by >>): In file included from drivers/gpu/drm/drm_atomic.c:32: In file included from include/drm/drm_atomic.h:31: In file included from include/drm/drm_crtc.h:32: In file included from include/drm/drm_modes.h:33: In file included from include/drm/drm_connector.h:32: In file included from include/drm/drm_util.h:35: In file included from include/linux/interrupt.h:11: In file included from include/linux/hardirq.h:11: In file included from ./arch/hexagon/include/generated/asm/hardirq.h:1: In file included from include/asm-generic/hardirq.h:17: In file included from include/linux/irq.h:20: In file included from include/linux/io.h:13: In file included from arch/hexagon/include/asm/io.h:334: include/asm-generic/io.h:547:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] val = __raw_readb(PCI_IOBASE + addr); ~~ ^ include/asm-generic/io.h:560:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr)); ~~ ^ include/uapi/linux/byteorder/little_endian.h:37:51: note: expanded from macro '__le16_to_cpu' #define __le16_to_cpu(x) ((__force __u16)(__le16)(x)) ^ In file included from drivers/gpu/drm/drm_atomic.c:32: In file included from include/drm/drm_atomic.h:31: In file included from include/drm/drm_crtc.h:32: In file included from include/drm/drm_modes.h:33: In file included from include/drm/drm_connector.h:32: In file included from include/drm/drm_util.h:35: In file included from include/linux/interrupt.h:11: In file included from include/linux/hardirq.h:11: In file included from ./arch/hexagon/include/generated/asm/hardirq.h:1: In file included from include/asm-generic/hardirq.h:17: In file included from include/linux/irq.h:20: In file included from include/linux/io.h:13: In file included from arch/hexagon/include/asm/io.h:334: include/asm-generic/io.h:573:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr)); ~~ ^ include/uapi/linux/byteorder/little_endian.h:35:51: note: expanded from macro '__le32_to_cpu' #define __le32_to_cpu(x) ((__force __u32)(__le32)(x)) ^ In file included from drivers/gpu/drm/drm_atomic.c:32: In file included from include/drm/drm_atomic.h:31: In file included from include/drm/drm_crtc.h:32: In file included from include/drm/drm_modes.h:33: In file included from include/drm/drm_connector.h:32: In file included from include/drm/drm_util.h:35: In file included from include/linux/interrupt.h:11: In file included from include/linux/hardirq.h:11: In file included from ./arch/h
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/debugfs: drop debugfs_init() for the render and accel node v2
== Series Details == Series: series starting with [1/5] drm/debugfs: drop debugfs_init() for the render and accel node v2 URL : https://patchwork.freedesktop.org/series/115793/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/debugfs: drop debugfs_init() for the render and accel node v2
== Series Details ==
Series: series starting with [1/5] drm/debugfs: drop debugfs_init() for the
render and accel node v2
URL : https://patchwork.freedesktop.org/series/115793/
State : warning
== Summary ==
Error: dim checkpatch failed
ec995fc695c1 drm/debugfs: drop debugfs_init() for the render and accel node v2
-:43: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: "Christian König" ' !=
'Signed-off-by: Christian König '
total: 0 errors, 1 warnings, 0 checks, 17 lines checked
da39d5843431 drm/debugfs: rework debugfs directory creation v2
-:418: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: "Christian König" ' !=
'Signed-off-by: Christian König '
total: 0 errors, 1 warnings, 0 checks, 321 lines checked
81d2f35746aa drm/debugfs: remove dev->debugfs_list and debugfs_mutex v2
-:165: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: "Christian König" ' !=
'Signed-off-by: Christian König '
total: 0 errors, 1 warnings, 0 checks, 115 lines checked
63dfc9fe1265 drm/debugfs: rework drm_debugfs_create_files implementation
-:271: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: "Christian König" ' !=
'Signed-off-by: Christian König '
total: 0 errors, 1 warnings, 0 checks, 203 lines checked
77d71d41765c drm/debugfs: remove debugfs_root pointer from minor
-:153: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IWUSR' are not
preferred. Consider using octal permissions '0200'.
#153: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_rap.c:125:
+ debugfs_create_file("rap_test", S_IWUSR, root, adev,
-:198: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IWUSR' are not
preferred. Consider using octal permissions '0200'.
#198: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c:180:
+ debugfs_create_file("securedisplay_test", S_IWUSR,
adev_to_drm(adev)->debugfs_root,
-:199: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#199: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c:181:
+ debugfs_create_file("securedisplay_test", S_IWUSR,
adev_to_drm(adev)->debugfs_root,
adev, _securedisplay_debugfs_ops);
-:279: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IRUGO | S_IWUSR' are not
preferred. Consider using octal permissions '0644'.
#279: FILE: drivers/gpu/drm/arm/malidp_drv.c:555:
+ debugfs_create_file("debug", S_IRUGO | S_IWUSR,
minor->dev->debugfs_root,
-:521: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IRUSR' are not
preferred. Consider using octal permissions '0400'.
#521: FILE: drivers/gpu/drm/i915/i915_debugfs.c:814:
+ debugfs_create_file("i915_forcewake_user", S_IRUSR,
minor->dev->debugfs_root,
-:579: WARNING:EXPORTED_WORLD_WRITABLE: Exporting world writable files is
usually an error. Consider more restrictive permissions.
#579: FILE: drivers/gpu/drm/msm/adreno/a5xx_debugfs.c:157:
+ debugfs_create_file_unsafe("reset", S_IWUGO, minor->dev->debugfs_root,
dev,
-:579: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IWUGO' are not
preferred. Consider using octal permissions '0222'.
#579: FILE: drivers/gpu/drm/msm/adreno/a5xx_debugfs.c:157:
+ debugfs_create_file_unsafe("reset", S_IWUGO, minor->dev->debugfs_root,
dev,
-:580: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#580: FILE: drivers/gpu/drm/msm/adreno/a5xx_debugfs.c:158:
+ debugfs_create_file_unsafe("reset", S_IWUGO, minor->dev->debugfs_root,
dev,
_fops);
-:646: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IRUSR' are not
preferred. Consider using octal permissions '0400'.
#646: FILE: drivers/gpu/drm/msm/msm_debugfs.c:314:
+ debugfs_create_file("gpu", S_IRUSR, minor->dev->debugfs_root,
-:647: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#647: FILE: drivers/gpu/drm/msm/msm_debugfs.c:315:
+ debugfs_create_file("gpu", S_IRUSR, minor->dev->debugfs_root,
dev, _gpu_fops);
-:650: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IRUSR' are not
preferred. Consider using octal permissions '0400'.
#650: FILE: drivers/gpu/drm/msm/msm_debugfs.c:317:
+ debugfs_create_file("kms", S_IRUSR, minor->dev->debugfs_root,
-:651: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#651: FILE: drivers/gpu/drm/msm/msm_debugfs.c:318:
+ debugfs_create_file("kms", S_IRUSR, minor->dev->debugfs_root,
dev, _kms_fops);
-:655: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#655: FILE: drivers/gpu/drm/msm/msm_debugfs.c:321:
+ debugfs_create_u32("hangcheck_period_ms", 0600,
minor->dev->debugfs_root,
>hangcheck_period);
-:659: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#659: FILE: drivers/gpu/drm/msm/msm_debugfs.c:324:
+ debugfs_create_bool("disable_err_irq", 0600, minor->dev->debugfs_root,
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Make utility pin asserts more accurate (rev2)
== Series Details == Series: drm/i915: Make utility pin asserts more accurate (rev2) URL : https://patchwork.freedesktop.org/series/115741/ State : success == Summary == CI Bug Log - changes from CI_DRM_12936 -> Patchwork_115741v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115741v2/index.html Participating hosts (37 -> 35) -- Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_115741v2 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s0@lmem0: - bat-dg2-11: [PASS][1] -> [INCOMPLETE][2] ([i915#6311]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-11/igt@gem_exec_suspend@basic...@lmem0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115741v2/bat-dg2-11/igt@gem_exec_suspend@basic...@lmem0.html * igt@i915_pm_rps@basic-api: - bat-dg2-11: [PASS][3] -> [FAIL][4] ([i915#8308]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-11/igt@i915_pm_...@basic-api.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115741v2/bat-dg2-11/igt@i915_pm_...@basic-api.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - fi-bsw-nick:NOTRUN -> [SKIP][5] ([fdo#109271]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115741v2/fi-bsw-nick/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#5354]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115741v2/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1: - bat-dg2-8: [PASS][7] -> [FAIL][8] ([i915#7932]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115741v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html * igt@kms_pipe_crc_basic@read-crc: - bat-adlp-9: NOTRUN -> [SKIP][9] ([i915#3546]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115741v2/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html Possible fixes * igt@i915_selftest@live@execlists: - fi-bsw-nick:[ABORT][10] ([i915#7911] / [i915#7913]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115741v2/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@migrate: - bat-dg2-11: [DMESG-WARN][12] ([i915#7699]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-11/igt@i915_selftest@l...@migrate.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115741v2/bat-dg2-11/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@slpc: - bat-rplp-1: [DMESG-FAIL][14] ([i915#6367] / [i915#7913]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-rplp-1/igt@i915_selftest@l...@slpc.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115741v2/bat-rplp-1/igt@i915_selftest@l...@slpc.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1: - bat-dg2-8: [FAIL][16] ([i915#7932]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115741v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932 [i915#8308]: https://gitlab.freedesktop.org/drm/intel/issues/8308 Build changes - * Linux: CI_DRM_12936 -> Patchwork_115741v2 CI-20190529: 20190529 CI_DRM_12936: 906438caae695f109636f82e2d1845a258f57d8b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7226: 41be8b4ab86f9e11388c10366dfd71e5032589c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
[Intel-gfx] [PATCH 2/2] drm/i915: Explain the magic numbers for AUX SYNC/precharge length
From: Ville Syrjälä
Replace the hardcoded final numbers in the AUX SYNC/precharge
setup, and derive those from numbers from the (e)DP specs.
The new functions can serve as the single point of truth for
the number of SYNC pulses we use.
Cc: Jouni Högander
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 32 +++--
1 file changed, 29 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index ad0aac707219..374492293392 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -118,6 +118,32 @@ static u32 skl_get_aux_clock_divider(struct intel_dp
*intel_dp, int index)
return index ? 0 : 1;
}
+static int intel_dp_aux_sync_len(void)
+{
+ int precharge = 16; /* 10-16 */
+ int preamble = 16;
+
+ return precharge + preamble;
+}
+
+static int intel_dp_aux_fw_sync_len(void)
+{
+ int precharge = 16; /* 10-16 */
+ int preamble = 8;
+
+ return precharge + preamble;
+}
+
+static int g4x_dp_aux_precharge_len(void)
+{
+ int precharge_min = 10;
+ int preamble = 16;
+
+ /* HW wants the length of the extra precharge in 2us units */
+ return (intel_dp_aux_sync_len() -
+ precharge_min - preamble) / 2;
+}
+
static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
int send_bytes,
u32 aux_clock_divider)
@@ -140,7 +166,7 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
timeout |
DP_AUX_CH_CTL_RECEIVE_ERROR |
(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
- (3 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
+ (g4x_dp_aux_precharge_len() <<
DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
}
@@ -164,8 +190,8 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
DP_AUX_CH_CTL_TIME_OUT_MAX |
DP_AUX_CH_CTL_RECEIVE_ERROR |
(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
- DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(24) |
- DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
+ DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_len()) |
+ DP_AUX_CH_CTL_SYNC_PULSE_SKL(intel_dp_aux_sync_len());
if (intel_tc_port_in_tbt_alt_mode(dig_port))
ret |= DP_AUX_CH_CTL_TBT_IO;
--
2.39.2
[Intel-gfx] [PATCH 1/2] drm/i915: Fix fast wake AUX sync len
From: Ville Syrjälä Fast wake should use 8 SYNC pulses for the preamble and 10-16 SYNC pulses for the precharge. Recuce our fast wake SYNC count to match the maximum value. We also use the maximum precharge length for normal AUX transactions. Cc: Jouni Högander Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index eb07dc5d8709..ad0aac707219 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -164,7 +164,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, DP_AUX_CH_CTL_TIME_OUT_MAX | DP_AUX_CH_CTL_RECEIVE_ERROR | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | - DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | + DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(24) | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); if (intel_tc_port_in_tbt_alt_mode(dig_port)) -- 2.39.2
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make utility pin asserts more accurate (rev2)
== Series Details == Series: drm/i915: Make utility pin asserts more accurate (rev2) URL : https://patchwork.freedesktop.org/series/115741/ State : warning == Summary == Error: dim checkpatch failed 2cfb34bea1f1 drm/i915: Make utility pin asserts more accurate -:12: WARNING:COMMIT_LOG_USE_LINK: Unknown link reference 'References:', use 'Link:' instead #12: References: https://gitlab.freedesktop.org/drm/intel/-/issues/6609 total: 0 errors, 1 warnings, 0 checks, 24 lines checked
[Intel-gfx] [PATCH] drm/scdc-helper: Pimp SCDC debugs
From: Ville Syrjälä
Include the device and connector information in the SCDC
debugs. Makes it easier to figure out who did what.
Cc: Andrzej Hajda
Cc: Neil Armstrong
Cc: Robert Foss
Cc: Laurent Pinchart
Cc: Jonas Karlman
Cc: Jernej Skrabec
Cc: Thierry Reding
Cc: Emma Anholt
Cc: Maxime Ripard
Cc: intel-gfx@lists.freedesktop.org
Cc: linux-te...@vger.kernel.org
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 8 ++---
drivers/gpu/drm/display/drm_scdc_helper.c | 36 ++-
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +--
drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +--
drivers/gpu/drm/tegra/sor.c | 10 +++
drivers/gpu/drm/vc4/vc4_hdmi.c| 21 +++--
include/drm/display/drm_scdc_helper.h | 12 ++--
7 files changed, 62 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index aa51c61a78c7..7f57ca168ab6 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1426,9 +1426,9 @@ void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi
*hdmi,
/* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
if (dw_hdmi_support_scdc(hdmi, display)) {
if (mtmdsclock > HDMI14_MAX_TMDSCLK)
- drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
+ drm_scdc_set_high_tmds_clock_ratio(>connector,
hdmi->ddc, 1);
else
- drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
+ drm_scdc_set_high_tmds_clock_ratio(>connector,
hdmi->ddc, 0);
}
}
EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
@@ -2116,7 +2116,7 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
/* Enabled Scrambling in the Sink */
- drm_scdc_set_scrambling(hdmi->ddc, 1);
+ drm_scdc_set_scrambling(>connector, hdmi->ddc, 1);
/*
* To activate the scrambler feature, you must ensure
@@ -2132,7 +2132,7 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
HDMI_MC_SWRSTZ);
- drm_scdc_set_scrambling(hdmi->ddc, 0);
+ drm_scdc_set_scrambling(>connector, hdmi->ddc, 0);
}
}
diff --git a/drivers/gpu/drm/display/drm_scdc_helper.c
b/drivers/gpu/drm/display/drm_scdc_helper.c
index c3ad4ab2b456..2b124152384c 100644
--- a/drivers/gpu/drm/display/drm_scdc_helper.c
+++ b/drivers/gpu/drm/display/drm_scdc_helper.c
@@ -26,6 +26,8 @@
#include
#include
+#include
+#include
#include
/**
@@ -140,6 +142,7 @@ EXPORT_SYMBOL(drm_scdc_write);
/**
* drm_scdc_get_scrambling_status - what is status of scrambling?
+ * @connector: connector
* @adapter: I2C adapter for DDC channel
*
* Reads the scrambler status over SCDC, and checks the
@@ -148,14 +151,17 @@ EXPORT_SYMBOL(drm_scdc_write);
* Returns:
* True if the scrambling is enabled, false otherwise.
*/
-bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter)
+bool drm_scdc_get_scrambling_status(struct drm_connector *connector,
+ struct i2c_adapter *adapter)
{
u8 status;
int ret;
ret = drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, );
if (ret < 0) {
- DRM_DEBUG_KMS("Failed to read scrambling status: %d\n", ret);
+ drm_dbg_kms(connector->dev,
+ "[CONNECTOR:%d:%s] Failed to read scrambling
status: %d\n",
+ connector->base.id, connector->name, ret);
return false;
}
@@ -165,6 +171,7 @@ EXPORT_SYMBOL(drm_scdc_get_scrambling_status);
/**
* drm_scdc_set_scrambling - enable scrambling
+ * @connector: connector
* @adapter: I2C adapter for DDC channel
* @enable: bool to indicate if scrambling is to be enabled/disabled
*
@@ -175,14 +182,18 @@ EXPORT_SYMBOL(drm_scdc_get_scrambling_status);
* Returns:
* True if scrambling is set/reset successfully, false otherwise.
*/
-bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable)
+bool drm_scdc_set_scrambling(struct drm_connector *connector,
+struct i2c_adapter *adapter,
+bool enable)
{
u8 config;
int ret;
ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, );
if (ret < 0) {
- DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret);
+ drm_dbg_kms(connector->dev,
+ "[CONNECTOR:%d:%s] Failed to read TMDS config:
%d\n",
+
[Intel-gfx] [PATCH 4/4] drm/i915/gsc: add support for GSC proxy interrupt
The GSC notifies us of a proxy request via the HECI2 interrupt. The
interrupt must be enabled both in the HECI layer and in our usual gt irq
programming; for the latter, the interrupt is enabled via the same enable
register as the GSC CS, but it does have its own mask register. When the
interrupt is received, we also need to de-assert it in both layers.
The handling of the proxy request is deferred to the same worker that we
use for GSC load. New flags have been added to distinguish between the
init case and the proxy interrupt.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 22 --
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ++
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 44 +++-
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c| 44
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h| 3 ++
6 files changed, 103 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 1b25a6039152..c433ffdb3380 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -15,6 +15,7 @@
#include "intel_uncore.h"
#include "intel_rps.h"
#include "pxp/intel_pxp_irq.h"
+#include "uc/intel_gsc_proxy.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -81,6 +82,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
instance,
if (instance == OTHER_GSC_INSTANCE)
return intel_gsc_irq_handler(gt, iir);
+ if (instance == OTHER_GSC_HECI_2_INSTANCE)
+ return intel_gsc_proxy_irq_handler(>uc.gsc, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
@@ -100,6 +104,8 @@ static struct intel_gt *pick_gt(struct intel_gt *gt, u8
class, u8 instance)
case VIDEO_ENHANCEMENT_CLASS:
return media_gt;
case OTHER_CLASS:
+ if (instance == OTHER_GSC_HECI_2_INSTANCE)
+ return media_gt;
if (instance == OTHER_GSC_INSTANCE && HAS_ENGINE(media_gt,
GSC0))
return media_gt;
fallthrough;
@@ -256,6 +262,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
u32 irqs = GT_RENDER_USER_INTERRUPT;
u32 guc_mask = intel_uc_wants_guc(>uc) ? GUC_INTR_GUC2HOST : 0;
u32 gsc_mask = 0;
+ u32 heci_mask = 0;
u32 dmask;
u32 smask;
@@ -267,10 +274,16 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
dmask = irqs << 16 | irqs;
smask = irqs << 16;
- if (HAS_ENGINE(gt, GSC0))
+ if (HAS_ENGINE(gt, GSC0)) {
+ /*
+* the heci2 interrupt is enabled via the same register as the
+* GSC interrupt, but it has its own mask register.
+*/
gsc_mask = irqs;
- else if (HAS_HECI_GSC(gt->i915))
+ heci_mask = GSC_IRQ_INTF(1); /* HECI2 IRQ for SW Proxy*/
+ } else if (HAS_HECI_GSC(gt->i915)) {
gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
+ }
BUILD_BUG_ON(irqs & 0x);
@@ -280,7 +293,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
if (CCS_MASK(gt))
intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
if (gsc_mask)
- intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
gsc_mask);
+ intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
gsc_mask | heci_mask);
/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
@@ -308,6 +321,9 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
if (gsc_mask)
intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK,
~gsc_mask);
+ if (heci_mask)
+ intel_uncore_write(uncore, GEN11_HECI2_RSVD_INTR_MASK,
+ ~REG_FIELD_PREP(ENGINE1_MASK, heci_mask));
if (guc_mask) {
/* the enable bit is common for both GTs but the masks are
separate */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 4aecb5a7b631..da11ce5ca99e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1577,6 +1577,7 @@
#define GEN11_GT_INTR_DW(x)_MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
+#define GEN12_HECI_2 (30)
#define GEN11_GUNIT (28)
#define GEN11_GUC(25)
#define MTL_MGUC (24)
@@ -1618,6 +1619,7 @@
/* irq instances for OTHER_CLASS */
[Intel-gfx] [PATCH 3/4] drm/i915/gsc: add initial support for GSC proxy
The GSC uC needs to communicate with the CSME to perform certain
operations. Since the GSC can't perform this communication directly
on platforms where it is integrated in GT, i915 needs to transfer the
messages from GSC to CSME and back.
The proxy flow is as follow:
1 - i915 submits a request to GSC asking for the message to CSME
2 - GSC replies with the proxy header + payload for CSME
3 - i915 sends the reply from GSC as-is to CSME via the mei proxy
component
4 - CSME replies with the proxy header + payload for GSC
5 - i915 submits a request to GSC with the reply from CSME
6 - GSC replies either with a new header + payload (same as step 2,
so we restart from there) or with an end message.
After GSC load, i915 is expected to start the first proxy message chain,
while all subsequent ones will be triggered by the GSC via interrupt.
To communicate with the CSME, we use a dedicated mei component, which
means that we need to wait for it to bind before we can initialize the
proxies. This usually happens quite fast, but given that there is a
chance that we'll have to wait a few seconds the GSC work has been moved
to a dedicated WQ to not stall other processes.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 384 ++
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h | 17 +
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 40 +-
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h | 14 +-
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h | 1 +
6 files changed, 452 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 057ef22fa9c6..aae041137f93 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -194,6 +194,7 @@ i915-y += \
# general-purpose microcontroller (GuC) support
i915-y += \
gt/uc/intel_gsc_fw.o \
+ gt/uc/intel_gsc_proxy.o \
gt/uc/intel_gsc_uc.o \
gt/uc/intel_gsc_uc_heci_cmd_submit.o\
gt/uc/intel_guc.o \
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
new file mode 100644
index ..ed8f68e78c26
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
@@ -0,0 +1,384 @@
+#include "intel_gsc_proxy.h"
+
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include
+#include "drm/i915_gsc_proxy_mei_interface.h"
+#include "drm/i915_component.h"
+
+#include "gt/intel_gt.h"
+#include "gt/intel_gt_print.h"
+#include "intel_gsc_uc.h"
+#include "intel_gsc_uc_heci_cmd_submit.h"
+#include "i915_drv.h"
+
+/*
+ * GSC proxy:
+ * The GSC uC needs to communicate with the CSME to perform certain operations.
+ * Since the GSC can't perform this communication directly on platforms where
it
+ * is integrated in GT, i915 needs to transfer the messages from GSC to CSME
+ * and back. i915 must manually start the proxy flow after the GSC is loaded to
+ * signal to GSC that we're ready to handle its messages and allow it to query
+ * its init data from CSME; GSC will then trigger an HECI2 interrupt if it
needs
+ * to send messages to CSME again.
+ * The proxy flow is as follow:
+ * 1 - i915 submits a request to GSC asking for the message to CSME
+ * 2 - GSC replies with the proxy header + payload for CSME
+ * 3 - i915 sends the reply from GSC as-is to CSME via the mei proxy component
+ * 4 - CSME replies with the proxy header + payload for GSC
+ * 5 - i915 submits a request to GSC with the reply from CSME
+ * 6 - GSC replies either with a new header + payload (same as step 2, so we
+ * restart from there) or with an end message.
+ */
+
+/*
+ * The component should load quite quickly in most cases, but it could take
+ * a bit. Using a very big timeout just to cover the worst case scenario
+ */
+#define GSC_PROXY_INIT_TIMEOUT_MS 2
+
+/* the protocol supports up to 32K in each direction */
+#define GSC_PROXY_BUFFER_SIZE SZ_32K
+#define GSC_PROXY_CHANNEL_SIZE (GSC_PROXY_BUFFER_SIZE * 2)
+#define GSC_PROXY_MAX_MSG_SIZE (GSC_PROXY_BUFFER_SIZE - sizeof(struct
intel_gsc_mtl_header))
+
+/* FW-defined proxy header */
+struct intel_gsc_proxy_header
+{
+ /*
+* hdr:
+* Bits 0-7: type of the proxy message (see enum intel_gsc_proxy_type)
+* Bits 8-15: rsvd
+* Bits 16-31: length in bytes of the payload following the proxy header
+*/
+ u32 hdr;
+#define GSC_PROXY_TYPE GENMASK(7, 0)
+#define GSC_PROXY_PAYLOAD_LENGTH GENMASK(31, 16)
+
+ u32 source; /* Source of the Proxy message */
+ u32 destination;/* Destination of the Proxy message */
+#define GSC_PROXY_ADDRESSING_KMD 0x1
+#define GSC_PROXY_ADDRESSING_GSC 0x2
+#define
[Intel-gfx] [PATCH 1/4] drm/i915/mtl: Define GSC Proxy component interface
From: Alexander Usyskin
GSC Proxy component is used for communication between the
Intel graphics driver and MEI driver.
Cc: Daniele Ceraolo Spurio
Cc: Alan Previn
Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler
Acked-by: Greg Kroah-Hartman
---
include/drm/i915_component.h | 3 +-
include/drm/i915_gsc_proxy_mei_interface.h | 36 ++
2 files changed, 38 insertions(+), 1 deletion(-)
create mode 100644 include/drm/i915_gsc_proxy_mei_interface.h
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index c1e2a43d2d1e..56a84ee1c64c 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -29,7 +29,8 @@
enum i915_component_type {
I915_COMPONENT_AUDIO = 1,
I915_COMPONENT_HDCP,
- I915_COMPONENT_PXP
+ I915_COMPONENT_PXP,
+ I915_COMPONENT_GSC_PROXY,
};
/* MAX_PORT is the number of port
diff --git a/include/drm/i915_gsc_proxy_mei_interface.h
b/include/drm/i915_gsc_proxy_mei_interface.h
new file mode 100644
index ..e817bb316d5c
--- /dev/null
+++ b/include/drm/i915_gsc_proxy_mei_interface.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright (c) 2022-2023 Intel Corporation
+ */
+
+#ifndef _I915_GSC_PROXY_MEI_INTERFACE_H_
+#define _I915_GSC_PROXY_MEI_INTERFACE_H_
+
+#include
+#include
+
+/**
+ * struct i915_gsc_proxy_component_ops - ops for GSC Proxy services.
+ * @owner: Module providing the ops
+ * @send: sends data through GSC proxy
+ * @recv: receives data through GSC proxy
+ */
+struct i915_gsc_proxy_component_ops {
+ struct module *owner;
+
+ int (*send)(struct device *dev, const void *buf, size_t size);
+ int (*recv)(struct device *dev, void *buf, size_t size);
+};
+
+/**
+ * struct i915_gsc_proxy_component - Used for communication between i915 and
+ * MEI drivers for GSC proxy services
+ * @mei_dev: device that provide the GSC proxy service.
+ * @ops: Ops implemented by GSC proxy driver, used by i915 driver.
+ */
+struct i915_gsc_proxy_component {
+ struct device *mei_dev;
+ const struct i915_gsc_proxy_component_ops *ops;
+};
+
+#endif /* _I915_GSC_PROXY_MEI_INTERFACE_H_ */
--
2.37.3
[Intel-gfx] [PATCH 0/4] drm/i915: Add support for MTL GSC SW Proxy
On platforms where the GSC is part of GT, it needs to communicate with CSME for some of its operations. However, there is no direct HW communication channel, so the i915 and mei drivers must carry the messages back and forth between the 2 units. The protocol is fully described in the i915 patch that adds the initial support, but it basically amounts to SW blindly moving messages back and forth until the GSC tells us to stop. Implementing this features requires a new mei component to handle the mei side of things. The patches for this have already been reviewed on the char-misc ML and we already have an ack from Greg to merge them via the drm tree [1]. [1] https://lore.kernel.org/lkml/20230208142358.1401618-1-tomas.wink...@intel.com/t/ Cc: Alan Previn Cc: Suraj Kandpal Cc: Alexander Usyskin Cc: Greg Kroah-Hartman Alexander Usyskin (2): drm/i915/mtl: Define GSC Proxy component interface mei: gsc_proxy: add gsc proxy driver Daniele Ceraolo Spurio (2): drm/i915/gsc: add initial support for GSC proxy drm/i915/gsc: add support for GSC proxy interrupt drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_gt_irq.c| 22 +- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 + drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 424 ++ drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h | 18 + drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 66 ++- drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h | 17 +- .../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h | 1 + drivers/misc/mei/Kconfig | 2 +- drivers/misc/mei/Makefile | 1 + drivers/misc/mei/gsc_proxy/Kconfig| 14 + drivers/misc/mei/gsc_proxy/Makefile | 7 + drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c| 208 + include/drm/i915_component.h | 3 +- include/drm/i915_gsc_proxy_mei_interface.h| 36 ++ 15 files changed, 813 insertions(+), 10 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h create mode 100644 drivers/misc/mei/gsc_proxy/Kconfig create mode 100644 drivers/misc/mei/gsc_proxy/Makefile create mode 100644 drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c create mode 100644 include/drm/i915_gsc_proxy_mei_interface.h -- 2.37.3
[Intel-gfx] [PATCH 2/4] mei: gsc_proxy: add gsc proxy driver
From: Alexander Usyskin
Add GSC proxy driver. It to allows messaging between GSC component
on Intel on board graphics card and CSE device.
Cc: Daniele Ceraolo Spurio
Cc: Alan Previn
Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler
Acked-by: Greg Kroah-Hartman
---
drivers/misc/mei/Kconfig | 2 +-
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/gsc_proxy/Kconfig | 14 ++
drivers/misc/mei/gsc_proxy/Makefile| 7 +
drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c | 208 +
5 files changed, 231 insertions(+), 1 deletion(-)
create mode 100644 drivers/misc/mei/gsc_proxy/Kconfig
create mode 100644 drivers/misc/mei/gsc_proxy/Makefile
create mode 100644 drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index d21486d69df2..37db142de413 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -62,4 +62,4 @@ config INTEL_MEI_GSC
source "drivers/misc/mei/hdcp/Kconfig"
source "drivers/misc/mei/pxp/Kconfig"
-
+source "drivers/misc/mei/gsc_proxy/Kconfig"
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index fb740d754900..14aee253ae48 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -30,3 +30,4 @@ CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
+obj-$(CONFIG_INTEL_MEI_GSC_PROXY) += gsc_proxy/
diff --git a/drivers/misc/mei/gsc_proxy/Kconfig
b/drivers/misc/mei/gsc_proxy/Kconfig
new file mode 100644
index ..fd45ce8c1df4
--- /dev/null
+++ b/drivers/misc/mei/gsc_proxy/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_GSC_PROXY
+ tristate "Intel GSC Proxy services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for GSC Proxy Services on Intel platforms.
+
+ MEI GSC proxy enables messaging between GSC service on
+ Intel graphics on-board card and services on CSE (MEI)
+ firmware residing SoC or PCH.
+
diff --git a/drivers/misc/mei/gsc_proxy/Makefile
b/drivers/misc/mei/gsc_proxy/Makefile
new file mode 100644
index ..358847e9aaa9
--- /dev/null
+++ b/drivers/misc/mei/gsc_proxy/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
+#
+# Makefile - GSC Proxy client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_GSC_PROXY) += mei_gsc_proxy.o
diff --git a/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
b/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
new file mode 100644
index ..953eda1a16fb
--- /dev/null
+++ b/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022-2023 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_GSC_PROXY Client Driver
+ *
+ * The mei_gsc_proxy driver acts as a translation layer between
+ * proxy user (I915) and ME FW by proxying messages to ME FW
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * mei_gsc_proxy_send - Sends a proxy message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buf: a message buffer to send
+ * @size: size of the message
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int mei_gsc_proxy_send(struct device *dev, const void *buf, size_t size)
+{
+ ssize_t ret;
+
+ if (!dev || !buf)
+ return -EINVAL;
+
+ ret = mei_cldev_send(to_mei_cl_device(dev), buf, size);
+ if (ret < 0)
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", ret);
+
+ return ret;
+}
+
+/**
+ * mei_gsc_proxy_recv - Receives a proxy message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buf: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes received on Success, <0 on Failure
+ */
+static int mei_gsc_proxy_recv(struct device *dev, void *buf, size_t size)
+{
+ ssize_t ret;
+
+ if (!dev || !buf)
+ return -EINVAL;
+
+ ret = mei_cldev_recv(to_mei_cl_device(dev), buf, size);
+ if (ret < 0)
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", ret);
+
+ return ret;
+}
+
+static const struct i915_gsc_proxy_component_ops mei_gsc_proxy_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_gsc_proxy_send,
+ .recv = mei_gsc_proxy_recv,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_gsc_proxy_component *comp_master =
mei_cldev_get_drvdata(cldev);
+
+ comp_master->ops = _gsc_proxy_ops;
+ comp_master->mei_dev = dev;
+ return component_bind_all(dev, comp_master);
+}
+
+static void
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Add Support for C10 chips (rev2)
== Series Details == Series: drm/i915/mtl: Add Support for C10 chips (rev2) URL : https://patchwork.freedesktop.org/series/115664/ State : success == Summary == CI Bug Log - changes from CI_DRM_12936 -> Patchwork_115664v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/index.html Participating hosts (37 -> 34) -- Missing(3): fi-kbl-soraka fi-snb-2520m fi-pnv-d510 Known issues Here are the changes found in Patchwork_115664v2 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [PASS][1] -> [DMESG-FAIL][2] ([i915#5334]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@requests: - bat-rpls-1: [PASS][3] -> [ABORT][4] ([i915#4983] / [i915#7911]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-rpls-1/igt@i915_selftest@l...@requests.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/bat-rpls-1/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@workarounds: - bat-rplp-1: [PASS][5] -> [INCOMPLETE][6] ([i915#7913]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-rplp-1/igt@i915_selftest@l...@workarounds.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/bat-rplp-1/igt@i915_selftest@l...@workarounds.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - fi-bsw-nick:NOTRUN -> [SKIP][7] ([fdo#109271]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/fi-bsw-nick/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#5354]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@kms_pipe_crc_basic@read-crc: - bat-adlp-9: NOTRUN -> [SKIP][9] ([i915#3546]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html Possible fixes * igt@i915_selftest@live@execlists: - fi-bsw-nick:[ABORT][10] ([i915#7911] / [i915#7913]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@migrate: - bat-dg2-11: [DMESG-WARN][12] ([i915#7699]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-11/igt@i915_selftest@l...@migrate.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/bat-dg2-11/igt@i915_selftest@l...@migrate.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 Build changes - * Linux: CI_DRM_12936 -> Patchwork_115664v2 CI-20190529: 20190529 CI_DRM_12936: 906438caae695f109636f82e2d1845a258f57d8b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7226: 41be8b4ab86f9e11388c10366dfd71e5032589c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_115664v2: 906438caae695f109636f82e2d1845a258f57d8b @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 4cbd667a7a2b drm/i915/mtl: Add support for PM DEMAND c1d07d32f2b6 drm/i915/mtl: Add vswing programming for C10 phys c8d867cd648e drm/i915/mtl: Add C10 phy programming for HDMI e339d2062279 drm/i915/mtl: Add Support for C10 PHY message bus and pll programming b8a4482714af drm/i915/mtl: Create separate reg file for PICA registers fa6d4bc79a6c drm/i915/mtl: Add DP rates 0ad2cdd45c1d drm/i915/mtl: Initial DDI port setup == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/index.html
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Update DSC Bigjoiner BW check (rev2)
== Series Details == Series: Update DSC Bigjoiner BW check (rev2) URL : https://patchwork.freedesktop.org/series/115773/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/115773/revisions/2/mbox/ not applied Applying: drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp Applying: drm/i915/dp: Use current cdclk for DSC Bigjoiner BW check error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_dp.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0002 drm/i915/dp: Use current cdclk for DSC Bigjoiner BW check When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add Support for C10 chips (rev2)
== Series Details == Series: drm/i915/mtl: Add Support for C10 chips (rev2) URL : https://patchwork.freedesktop.org/series/115664/ State : warning == Summary == Error: dim checkpatch failed 9a839bd9b6b9 drm/i915/mtl: Initial DDI port setup febb42d9125a drm/i915/mtl: Add DP rates 7ad8892410b2 drm/i915/mtl: Create separate reg file for PICA registers Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:18: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #18: new file mode 100644 -:38: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #38: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:16: + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ -:39: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #39: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:17: + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ -:40: WARNING:LONG_LINE: line length of 121 exceeds 100 columns #40: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:18: + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ -:41: WARNING:LONG_LINE: line length of 133 exceeds 100 columns #41: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:19: + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4) -:44: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #44: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:22: +#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1) -:45: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #45: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:23: +#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2) -:46: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #46: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:24: +#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3) -:48: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #48: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:26: +#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val) -:51: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #51: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:29: +#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val) -:53: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #53: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:31: + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ -:54: WARNING:LONG_LINE: line length of 117 exceeds 100 columns #54: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:32: + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ -:55: WARNING:LONG_LINE: line length of 121 exceeds 100 columns #55: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:33: + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ -:56: WARNING:LONG_LINE: line length of 137 exceeds 100 columns #56: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:34: + _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8) -:62: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #62: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:40: +#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val) -:80: WARNING:LONG_LINE: line length of 111 exceeds 100 columns #80: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:58: + _XELPDP_PORT_BUF_CTL1_LN0_A, \ -:81: WARNING:LONG_LINE: line length of 111 exceeds 100 columns #81: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:59: + _XELPDP_PORT_BUF_CTL1_LN0_B, \ -:82: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #82: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:60: + _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \ -:83: WARNING:LONG_LINE: line length of 114 exceeds 100 columns #83: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:61: +
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add Support for C10 chips (rev2)
== Series Details == Series: drm/i915/mtl: Add Support for C10 chips (rev2) URL : https://patchwork.freedesktop.org/series/115664/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH v2 0/9] drm/i915: Replace kmap_atomic() with kmap_local_page()
On mercoledì 29 marzo 2023 09:32:11 CEST Zhao Liu wrote:
> From: Zhao Liu
>
> Hi list,
>
> Sorry for a long delay since v1 [1]. This patchset is based on 197b6b6
> (Linux 6.3-rc4).
>
> Welcome and thanks for your review and comments!
>
>
> # Purpose of this patchset
>
> The purpose of this pacthset is to replace all uses of kmap_atomic() in
> i915 with kmap_local_page() because the use of kmap_atomic() is being
> deprecated in favor of kmap_local_page()[1]. And 92b64bd (mm/highmem:
> add notes about conversions from kmap{,_atomic}()) has declared the
> deprecation of kmap_atomic().
>
>
> # Motivation for deprecating kmap_atomic() and using kmap_local_page()
>
> The main difference between atomic and local mappings is that local
> mappings doesn't disable page faults or preemption (the preemption is
> disabled for !PREEMPT_RT case, otherwise it only disables migration).
>
> With kmap_local_page(), we can avoid the often unwanted side effect of
> unnecessary page faults and preemption disables.
>
>
> # Patch summary
>
> Patch 1, 4-6 and 8-9 replace kamp_atomic()/kunmap_atomic() with
> kmap_local_page()/kunmap_local() directly. With thses local
> mappings, the page faults and preemption are allowed.
>
> Patch 2 and 7 use memcpy_from_page() and memcpy_to_page() to replace
> kamp_atomic()/kunmap_atomic(). These two variants of memcpy()
> are based on the local mapping, so page faults and preemption
> are also allowed in these two interfaces.
>
> Patch 3 replaces kamp_atomic()/kunmap_atomic() with kmap_local_page()/
> kunmap_local() and also diable page fault since the for special
> handling (pls see the commit message).
>
>
> # Changes since v1
>
> * Dropped hot plug related description in commit message since it has
> nothing to do with kmap_local_page().
> * Emphasized the motivation for using kmap_local_page() in commit
> message.
> * Rebased patch 1 on f47e630 (drm/i915/gem: Typecheck page lookups) to
> keep the "idx" variable of type pgoff_t here.
> * Used memcpy_from_page() and memcpy_to_page() to replace
> kmap_local_page() + memcpy() in patch 2.
>
>
> # Reference
>
> [1]:
> https://lore.kernel.org/lkml/20221017093726.2070674-1-zhao1.liu@linux.intel.c
> om/ [1]:
> https://lore.kernel.org/all/20220813220034.806698-1-ira.we...@intel.com ---
> Zhao Liu (9):
> drm/i915: Use kmap_local_page() in gem/i915_gem_object.c
> drm/i915: Use memcpy_[from/to]_page() in gem/i915_gem_pyhs.c
> drm/i915: Use kmap_local_page() in gem/i915_gem_shmem.c
> drm/i915: Use kmap_local_page() in gem/selftests/huge_pages.c
> drm/i915: Use kmap_local_page() in gem/selftests/i915_gem_coherency.c
> drm/i915: Use kmap_local_page() in gem/selftests/i915_gem_context.c
> drm/i915: Use memcpy_from_page() in gt/uc/intel_uc_fw.c
> drm/i915: Use kmap_local_page() in i915_cmd_parser.c
> drm/i915: Use kmap_local_page() in gem/i915_gem_execbuffer.c
>
I _think_ that the "long delay" you mentioned in the first sentence has paid
off in full.
I don't see things to improve (except all those "kamp_atomic()" typo in the
patches summary; however, typos are only in the cover so I'm sure they won't
hurt anybody).
Each of the nine patches listed above looks good to me, so they are all…
Reviewed-by: Fabio M. De Francesco
Thanks!
Fabio
PS: Obviously there was no need to reconfirm my tag for patch 3/9. A single
tag that catches all patches is easier for a lazy person like me :-)
>
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 10 +-
> drivers/gpu/drm/i915/gem/i915_gem_object.c | 8 +++-
> drivers/gpu/drm/i915/gem/i915_gem_phys.c | 10 ++
> drivers/gpu/drm/i915/gem/i915_gem_shmem.c| 6 --
> drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 6 +++---
> .../gpu/drm/i915/gem/selftests/i915_gem_coherency.c | 12
> .../gpu/drm/i915/gem/selftests/i915_gem_context.c| 8
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 5 +
> drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++--
> 9 files changed, 28 insertions(+), 41 deletions(-)
>
> --
> 2.34.1
Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
On Wed, Mar 29, 2023 at 06:40:39PM +0300, Imre Deak wrote:
> On Mon, Mar 27, 2023 at 03:34:30PM +0300, Mika Kahola wrote:
> [...]
> > +}
> > +
> > +static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port
> > port, int lane, u32 *val)
> > +{
> > + enum phy phy = intel_port_to_phy(i915, port);
> > +
> > + if (__intel_de_wait_for_register(i915,
> > +XELPDP_PORT_P2M_MSGBUS_STATUS(port,
> > lane - 1),
>
> As above this function should take the 0-based lane value.
Err, I meant here as earlier the function param should be
'u8 lane_mask' and use a helper to convert this mask to a lane.
--Imre
Re: [Intel-gfx] [PATCH v2 10/10] vfio/pci: Add VFIO_DEVICE_GET_PCI_HOT_RESET_GROUP_INFO
On Wed, Mar 29, 2023 at 09:49:44AM -0600, Alex Williamson wrote: > > We could extend bind_iommufd to return the group id or introduce a > > new ioctl to query it per dev_id. > > That would be ironic to go to all this trouble to remove groups from > the API only to have them show up here. Groups always had to be part of the API for advanced cases like qemu - the point was to make them a small side bit of information not front and center in control of everything. > For example, devices within a group cannot be bound to separate > iommufds due to lack of isolation, which is handled via DMA ownership, > but barring DMA aliasing issues, due to conventional PCI buses or > quirks, cdev could allow devices within the same group to be managed by > separate IOAS's. Maybe some future kernel could do this, the API allows it at least.. > So the group information really isn't enough for > userspace to infer address space restrictions with cdev anyway. > > Therefore aren't we expecting this to be denied at attach_ioas() and > QEMU shouldn't be making these sorts of assumptions for cdev anyway? I guess we could make an API specifically to report same-iommu_domina information? I was assuming qemu would use the group for now as I don't see a likely future when we would relax that restriction.. So I was keeping a "add it when we need it" attitude here. Jason
Re: [Intel-gfx] [PATCH v2 10/10] vfio/pci: Add VFIO_DEVICE_GET_PCI_HOT_RESET_GROUP_INFO
On Wed, Mar 29, 2023 at 09:41:26AM +, Tian, Kevin wrote: > We could extend bind_iommufd to return the group id or introduce a > new ioctl to query it per dev_id. > Once that is in place looks we don't need a new _INFO ioctl? The iommu_group and the reset group are different things The issue is processing the BDF strings, not the group ID. Probably we should have some way for iommufd to report the group_id from the dev_id? Jason
Re: [Intel-gfx] [PATCH v2 10/10] vfio/pci: Add VFIO_DEVICE_GET_PCI_HOT_RESET_GROUP_INFO
On Wed, 29 Mar 2023 09:41:26 + "Tian, Kevin" wrote: > > From: Liu, Yi L > > Sent: Wednesday, March 29, 2023 11:14 AM > > > > > From: Alex Williamson > > > Sent: Wednesday, March 29, 2023 12:00 AM > > > > > > > > > Personally I don't like the suggestion to fail with -EPERM if the user > > > doesn't own all the affected devices. This isn't a "probe if I can do > > > a reset" ioctl, it's a "provide information about the devices affected > > > by a reset to know how to call the hot-reset ioctl". We're returning > > > the bdf to the cdev version of this ioctl for exactly this debugging > > > purpose when the devices are not owned, that becomes useless if we give > > > up an return -EPERM if ownership doesn't align. > > > > Jason's suggestion makes sense for returning the case of returning dev_id > > as dev_id is local to iommufd. If there are devices in the same dev_set are > > opened by multiple users, multiple iommufd would be used. Then the > > dev_id would have overlap. e.g. a dev_set has three devices. Device A and > > B are opened by the current user as cdev, dev_id #1 and #2 are generated. > > While device C opened by another user as cdev, dev_id #n is generated for > > it. If dev_id #n happens to be #1, then user gets two info entries that have > > the same dev_id. > > > > In Alex's proposal you'll set a invalid dev_id for device C so the user can > still get the info for diagnostic purpose instead of seeing an -EPERM error. Yes, we shouldn't be reporting dev_ids outside of the user's iommufd context. > btw I found an open about fd pass scheme which may affect the choice here. > > In concept even with cdev we still expect the userspace to maintain the > group knowledge so it won't inadvertently attempt to assign devices in > the same group to different IOAS's. It also needs such knowledge when > constructing guest topology. > > with fd passed in Qemu has no way to associate the fd to a group. Hmm, QEMU tries to get the group for the device address space in the guest, so finding an existing group with a different address space indeed allows QEMU to know of this conflict since the group is the fundamental unit IOMMU context in the legacy vfio model. > We could extend bind_iommufd to return the group id or introduce a > new ioctl to query it per dev_id. That would be ironic to go to all this trouble to remove groups from the API only to have them show up here. But with a cdev interface, don't we break that model of conflating isolation and address-ability? For example, devices within a group cannot be bound to separate iommufds due to lack of isolation, which is handled via DMA ownership, but barring DMA aliasing issues, due to conventional PCI buses or quirks, cdev could allow devices within the same group to be managed by separate IOAS's. So the group information really isn't enough for userspace to infer address space restrictions with cdev anyway. Therefore aren't we expecting this to be denied at attach_ioas() and QEMU shouldn't be making these sorts of assumptions for cdev anyway? Thanks, Alex
Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
On Mon, Mar 27, 2023 at 03:34:30PM +0300, Mika Kahola wrote:
> From: Radhakrishna Sripada
>
> XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
> has a dedicated PIPE 5.2 Message bus for configuration. This message
> bus is used to configure the phy internal registers.
>
> XELPDP has C10 phys to drive output to the EDP and the native output
> from the display engine. Add structures, programming hardware state
> readout logic. Port clock calculations are similar to DG2. Use the DG2
> formulae to calculate the port clock but use the relevant pll signals.
> Note: PHY lane 0 is always used for PLL programming.
>
> Add sequences for C10 phy enable/disable phy lane reset,
> powerdown change sequence and phy lane programming.
>
> Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
>
> v2: Squash patches related to C10 phy message bus and pll
> programming support (Jani)
> Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
> Move macro definitions (Jani)
> DP rates as separate patch (Jani)
> Spin out xelpdp register definitions into a separate file (Jani)
> Replace macro to select registers based on phy lane with
> function calls (Jani)
> Fix styling issues (Jani)
> Call XELPDP_PORT_P2M_MSGBUS_STATUS() with port instead of phy (Lucas)
> v3: Move clear request flag into try-loop
> v4: On PHY idle change drm_err_once() as drm_dbg_kms() (Jani)
> use __intel_de_wait_for_register() instead of __intel_wait_for_register
> and uncomment intel_uncore.h (Jani)
> Add DP-alt support for PHY lane programming (Khaled)
>
> Cc: Mika Kahola
> Cc: Imre Deak
> Cc: Uma Shankar
> Cc: Gustavo Sousa
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/Makefile |1 +
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1120 +
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 43 +
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 32 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 22 +-
> .../drm/i915/display/intel_display_power.c|3 +-
> .../i915/display/intel_display_power_well.c |2 +-
> .../drm/i915/display/intel_display_types.h|6 +
> drivers/gpu/drm/i915/display/intel_dpll.c | 20 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c |2 +-
> .../drm/i915/display/intel_modeset_verify.c |2 +
> drivers/gpu/drm/i915/i915_reg.h |5 +
> drivers/gpu/drm/i915/i915_reg_defs.h | 57 +
> 13 files changed, 1309 insertions(+), 6 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 057ef22fa9c6..57b1417792b4 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -298,6 +298,7 @@ i915-y += \
> display/icl_dsi.o \
> display/intel_backlight.o \
> display/intel_crt.o \
> + display/intel_cx0_phy.o \
> display/intel_ddi.o \
> display/intel_ddi_buf_trans.o \
> display/intel_display_trace.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> new file mode 100644
> index ..ced8c8aa6c82
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -0,0 +1,1120 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include "i915_reg.h"
> +#include "intel_cx0_phy.h"
> +#include "intel_cx0_phy_regs.h"
> +#include "intel_de.h"
> +#include "intel_display_types.h"
> +#include "intel_dp.h"
> +#include "intel_panel.h"
> +#include "intel_tc.h"
> +
> +bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
> +{
> + if (IS_METEORLAKE(dev_priv) && (phy < PHY_C))
> + return true;
> +
> + return false;
> +}
> +
> +static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port
> port, int lane)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> +
> + /* Bring the phy to idle. */
> + intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
For the above and every other place taking a lane mask parameter or
converting the lane mask to a lane:
I think the function parameter should be an 'u8 lane_mask' for clarity
and instead of open-coding the conversion should be done by a
lane_mask_to_lane() helper which also sanity checks lane_mask (that it's
either INTEL_CX0_LANE0 or INTEL_CX0_LANE1, but not both).
> +XELPDP_PORT_M2P_TRANSACTION_RESET);
> +
> + /* Wait for Idle Clear. */
> + if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane
> - 1),
> + XELPDP_PORT_M2P_TRANSACTION_RESET,
> + XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> +
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Initialize fbdev DRM client with callback functions
Hi Thomas, On Tue, Mar 28, 2023 at 01:14:20PM +0200, Thomas Zimmermann wrote: > Initialize i915's fbdev client by giving an instance of struct > drm_client_funcsi to drm_client_init(). Also clean up with An extra i had sneaked in here Sam
[Intel-gfx] [PATCH v7 5/6] drm/i915/psr: Check that vblank is long enough for psr2
Ensure vblank >= psr2 vblank
where
Psr2 vblank = PSR2_CTL Block Count Number maximum line count.
Bspec: 71580, 49274
v2: Use calculated block count number maximum line count
Signed-off-by: Jouni Högander
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 07b0c016e78a..446c8acc265b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -968,6 +968,15 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
return false;
}
+ /* Vblank >= PSR2_CTL Block Count Number maximum line count */
+ if (crtc_state->hw.adjusted_mode.crtc_vblank_end -
+ crtc_state->hw.adjusted_mode.crtc_vblank_start <
+ psr2_block_count_lines(intel_dp)) {
+ drm_dbg_kms(_priv->drm,
+ "PSR2 not enabled, too short vblank time\n");
+ return false;
+ }
+
if (HAS_PSR2_SEL_FETCH(dev_priv)) {
if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
!HAS_PSR_HW_TRACKING(dev_priv)) {
--
2.34.1
[Intel-gfx] [PATCH v7 6/6] drm/i915/psr: Implement Display WA #1136
Implement Display WA #1136 for Pre-ICL.
Bspec: 21664
v2: Handle disable psr in pre/post plane hooks
Signed-off-by: Jouni Högander
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 7 +++
drivers/gpu/drm/i915/display/skl_watermark.c | 5 -
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 446c8acc265b..ecf1781c1556 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1968,11 +1968,14 @@ void intel_psr_pre_plane_update(struct
intel_atomic_state *state,
* - PSR disabled in new state
* - All planes will go inactive
* - Changing between PSR versions
+* - Display WA #1136: skl, bxt
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
needs_to_disable |= !new_crtc_state->active_planes;
needs_to_disable |= new_crtc_state->has_psr2 !=
psr->psr2_enabled;
+ needs_to_disable |= DISPLAY_VER(i915) < 11 &&
+ new_crtc_state->wm_level_disabled;
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
@@ -2006,6 +2009,10 @@ static void _intel_psr_post_plane_update(const struct
intel_atomic_state *state,
keep_disabled |= psr->sink_not_reliable;
keep_disabled |= !crtc_state->active_planes;
+ /* Display WA #1136: skl, bxt */
+ keep_disabled |= DISPLAY_VER(dev_priv) < 11 &&
+ crtc_state->wm_level_disabled;
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
else if (psr->enabled && !crtc_state->wm_level_disabled)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 7e2e76afbf2a..5296a20d62d3 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2281,11 +2281,6 @@ static int skl_wm_check_vblank(struct intel_crtc_state
*crtc_state)
*/
crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1;
- /*
-* FIXME also related to skl+ w/a 1136 (also unimplemented as of
-* now) perhaps?
-*/
-
for (level++; level < i915->display.wm.num_levels; level++) {
enum plane_id plane_id;
--
2.34.1
[Intel-gfx] [PATCH v7 3/6] drm/i915/psr: Implement Wa_14015648006
PSR WM optimization should be disabled based on any wm level being
disabled. Also same WA should be applied for ICL as well.
Bspec: 71580
v5:
- Set in pre plane hook and clear in post plane hook
v4:
- Handle mode change in psr enable/disable
- Handle wm_level_disable changes separately in pre plane hook
v3:
- Split patch
v2:
- set/clear chicken bit in post_plane_update
- apply for ICL as well
Signed-off-by: Jouni Högander
---
.../gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 16 +++-
drivers/gpu/drm/i915/display/skl_watermark.c | 7 +--
3 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index ab146b5b68bd..4236ad751c2c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1157,6 +1157,7 @@ struct intel_crtc_state {
bool has_psr2;
bool enable_psr2_sel_fetch;
bool req_psr2_sdp_prior_scanline;
+ bool wm_level_disabled;
u32 dc3co_exitline;
u16 su_y_granularity;
struct drm_dp_vsc_sdp psr_vsc;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 770f6fea5499..98f48eb10c44 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1136,6 +1136,7 @@ static u32 wa_16013835468_bit_get(struct intel_dp
*intel_dp)
/*
* Wa_16013835468
+ * Wa_14015648006
*/
static void wm_optimization_wa(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
@@ -1143,6 +1144,11 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
bool set_wa_bit = false;
+ /* Wa_14015648006 */
+ if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+ IS_DISPLAY_VER(dev_priv, 11, 13))
+ set_wa_bit |= crtc_state->wm_level_disabled;
+
/* Wa_16013835468 */
if (DISPLAY_VER(dev_priv) == 12)
set_wa_bit |= crtc_state->hw.adjusted_mode.crtc_vblank_start !=
@@ -1197,6 +1203,7 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
/*
* Wa_16013835468
+* Wa_14015648006
*/
wm_optimization_wa(intel_dp, crtc_state);
@@ -1374,8 +1381,9 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
/*
* Wa_16013835468
+* Wa_14015648006
*/
- if (DISPLAY_VER(dev_priv) == 12)
+ if (DISPLAY_VER(dev_priv) >= 11)
intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
wa_16013835468_bit_get(intel_dp), 0);
@@ -1949,6 +1957,9 @@ void intel_psr_pre_plane_update(struct intel_atomic_state
*state,
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
+ else if (psr->enabled && new_crtc_state->wm_level_disabled)
+ /* Wa_14015648006 */
+ wm_optimization_wa(intel_dp, new_crtc_state);
mutex_unlock(>lock);
}
@@ -1978,6 +1989,9 @@ static void _intel_psr_post_plane_update(const struct
intel_atomic_state *state,
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
+ else if (psr->enabled && !crtc_state->wm_level_disabled)
+ /* Wa_14015648006 */
+ wm_optimization_wa(intel_dp, crtc_state);
/* Force a PSR exit when enabling CRC to avoid CRC timeouts */
if (crtc_state->crc_enabled && psr->enabled)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index ff70225c0263..7e2e76afbf2a 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2276,9 +2276,12 @@ static int skl_wm_check_vblank(struct intel_crtc_state
*crtc_state)
return level;
/*
-* FIXME PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
+* PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
* based on whether we're limited by the vblank duration.
-*
+*/
+ crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1;
+
+ /*
* FIXME also related to skl+ w/a 1136 (also unimplemented as of
* now) perhaps?
*/
--
2.34.1
[Intel-gfx] [PATCH v7 4/6] drm/i915/psr: Add helpers for block count number handling
Add helpers to make it more clear how PSR2_CTL[Block Count Number]
is configured.
Signed-off-by: Jouni Högander
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_psr.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 98f48eb10c44..07b0c016e78a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -519,6 +519,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp
*intel_dp)
return val;
}
+static int psr2_block_count_lines(struct intel_dp *intel_dp)
+{
+ return intel_dp->psr.io_wake_lines < 9 &&
+ intel_dp->psr.fast_wake_lines < 9 ? 8 : 12;
+}
+
+static int psr2_block_count(struct intel_dp *intel_dp)
+{
+ return psr2_block_count_lines(intel_dp) / 4;
+}
+
static void hsw_activate_psr2(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -536,11 +547,10 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val |= intel_psr2_get_tp_time(intel_dp);
if (DISPLAY_VER(dev_priv) >= 12) {
- if (intel_dp->psr.io_wake_lines < 9 &&
- intel_dp->psr.fast_wake_lines < 9)
- val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
- else
+ if (psr2_block_count(intel_dp) > 2)
val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3;
+ else
+ val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
}
/* Wa_22012278275:adl-p */
--
2.34.1
[Intel-gfx] [PATCH v7 1/6] drm/i915/psr: Unify pre/post hooks
pre/post hooks are doing things differently. Unify them.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 31084d95711d..8dbf452d63c2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1954,23 +1954,22 @@ static void _intel_psr_post_plane_update(const struct
intel_atomic_state *state,
crtc_state->uapi.encoder_mask) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_psr *psr = _dp->psr;
+ bool keep_disabled = false;
mutex_lock(>lock);
- if (psr->sink_not_reliable)
- goto exit;
-
drm_WARN_ON(_priv->drm, psr->enabled &&
!crtc_state->active_planes);
- /* Only enable if there is active planes */
- if (!psr->enabled && crtc_state->active_planes)
+ keep_disabled |= psr->sink_not_reliable;
+ keep_disabled |= !crtc_state->active_planes;
+
+ if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
/* Force a PSR exit when enabling CRC to avoid CRC timeouts */
if (crtc_state->crc_enabled && psr->enabled)
psr_force_hw_tracking_exit(intel_dp);
-exit:
mutex_unlock(>lock);
}
}
--
2.34.1
[Intel-gfx] [PATCH v7 2/6] drm/i915/psr: Modify/Fix Wa_16013835468 and prepare for Wa_14015648006
Wa_16013835468 is a separate from Wa_14015648006 and needs to be
applied for display version 12. Fix this by removing all the
references to Wa_14015648006 and apply Wa_16013835468 according to
Bspec.
Also move workaround into separate function as a preparation for
Wa_14015648006 implementation.
Bspec: 55378
v3:
- apply for display version 12 only
v2:
- keep applying the wa in intel_psr_enable_source
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 35
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 8dbf452d63c2..770f6fea5499 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1134,6 +1134,28 @@ static u32 wa_16013835468_bit_get(struct intel_dp
*intel_dp)
}
}
+/*
+ * Wa_16013835468
+ */
+static void wm_optimization_wa(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ bool set_wa_bit = false;
+
+ /* Wa_16013835468 */
+ if (DISPLAY_VER(dev_priv) == 12)
+ set_wa_bit |= crtc_state->hw.adjusted_mode.crtc_vblank_start !=
+ crtc_state->hw.adjusted_mode.crtc_vdisplay;
+
+ if (set_wa_bit)
+ intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
+0, wa_16013835468_bit_get(intel_dp));
+ else
+ intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
+wa_16013835468_bit_get(intel_dp), 0);
+}
+
static void intel_psr_enable_source(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
@@ -1175,15 +1197,8 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
/*
* Wa_16013835468
-* Wa_14015648006
*/
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
- IS_DISPLAY_VER(dev_priv, 12, 13)) {
- if (crtc_state->hw.adjusted_mode.crtc_vblank_start !=
- crtc_state->hw.adjusted_mode.crtc_vdisplay)
- intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
-wa_16013835468_bit_get(intel_dp));
- }
+ wm_optimization_wa(intel_dp, crtc_state);
if (intel_dp->psr.psr2_enabled) {
if (DISPLAY_VER(dev_priv) == 9)
@@ -1359,10 +1374,8 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
/*
* Wa_16013835468
-* Wa_14015648006
*/
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
- IS_DISPLAY_VER(dev_priv, 12, 13))
+ if (DISPLAY_VER(dev_priv) == 12)
intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
wa_16013835468_bit_get(intel_dp), 0);
--
2.34.1
[Intel-gfx] [PATCH v7 0/6] High refresh rate PSR fixes
Fix/adjust Wa_16013835468 and implement Wa_14015648006. Implement Wa_1136 and check for vblank being long enough for psr2. v7: - Apply Wa_14015648006 for display version 12 only - Disable WM optimization in pre plane hook allow in post plane hook v6: - Handle mode change in psr enable/disable - Handle wm_level_disable changes separately in pre plane hook - Handle WA #1136 in pre/post plane hooks v5: - Add missing patch v4: - Keep/fix Wa_16013835468 - Use calculated block count number instead of fixed 12 v3: - apply Wa_16013835468 for icl as well - set/clear chicken bit in post plane update - Unify pre/post hooks v2: Implement Wa_1136 Cc: Ville Syrjälä Cc: Stanislav Lisovskiy Cc: Mika Kahola Jouni Högander (6): drm/i915/psr: Unify pre/post hooks drm/i915/psr: Modify/Fix Wa_16013835468 and prepare for Wa_14015648006 drm/i915/psr: Implement Wa_14015648006 drm/i915/psr: Add helpers for block count number handling drm/i915/psr: Check that vblank is long enough for psr2 drm/i915/psr: Implement Display WA #1136 .../drm/i915/display/intel_display_types.h| 1 + drivers/gpu/drm/i915/display/intel_psr.c | 90 +++ drivers/gpu/drm/i915/display/skl_watermark.c | 6 +- 3 files changed, 74 insertions(+), 23 deletions(-) -- 2.34.1
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: move DSC RC tables to drm_dsc_helper.c (rev4)
== Series Details ==
Series: drm/i915: move DSC RC tables to drm_dsc_helper.c (rev4)
URL : https://patchwork.freedesktop.org/series/114473/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12931_full -> Patchwork_114473v4_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_114473v4_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_draw_crc@draw-method-blt@xrgb2101010-ytiled}:
- shard-glk: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-glk4/igt@kms_draw_crc@draw-method-...@xrgb2101010-ytiled.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v4/shard-glk7/igt@kms_draw_crc@draw-method-...@xrgb2101010-ytiled.html
Known issues
Here are the changes found in Patchwork_114473v4_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2846])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-glk2/igt@gem_exec_f...@basic-deadline.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v4/shard-glk1/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v4/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-apl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v4/shard-apl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#118])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-glk4/igt@i915_pm_rc6_residency@rc6-i...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v4/shard-glk7/igt@i915_pm_rc6_residency@rc6-i...@rcs0.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][11] -> [INCOMPLETE][12] ([i915#7790])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-snb4/igt@i915_pm_...@reset.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v4/shard-snb4/igt@i915_pm_...@reset.html
Possible fixes
* igt@gem_exec_endless@dispatch@vcs1:
- {shard-tglu}: [TIMEOUT][13] ([i915#3778]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-tglu-9/igt@gem_exec_endless@dispa...@vcs1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v4/shard-tglu-8/igt@gem_exec_endless@dispa...@vcs1.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][15] ([i915#2346]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-glk2/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v4/shard-glk1/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
- shard-apl: [FAIL][17] ([i915#2346]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-apl3/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v4/shard-apl2/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][19] ([i915#2122]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12931/shard-glk3/igt@kms_flip@2x-plain-flip-fb-recreate-interrupti...@ac-hdmi-a1-hdmi-a2.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v4/shard-glk7/igt@kms_flip@2x-plain-flip-fb-recreate-interrupti...@ac-hdmi-a1-hdmi-a2.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109307]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: use ref_tracker library for tracking wakerefs (rev7)
== Series Details == Series: drm/i915: use ref_tracker library for tracking wakerefs (rev7) URL : https://patchwork.freedesktop.org/series/100327/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12934 -> Patchwork_100327v7 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_100327v7 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_100327v7, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v7/index.html Participating hosts (37 -> 35) -- Missing(2): fi-kbl-soraka fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_100327v7: ### IGT changes ### Possible regressions * igt@fbdev@read: - bat-rplp-1: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/bat-rplp-1/igt@fb...@read.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v7/bat-rplp-1/igt@fb...@read.html Known issues Here are the changes found in Patchwork_100327v7 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-bsw-nick:[PASS][3] -> [ABORT][4] ([i915#7911] / [i915#7913]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v7/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@hangcheck: - bat-dg2-11: [PASS][5] -> [ABORT][6] ([i915#7913]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v7/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html Possible fixes * igt@i915_pm_rps@basic-api: - bat-dg2-11: [FAIL][7] ([i915#8308]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/bat-dg2-11/igt@i915_pm_...@basic-api.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v7/bat-dg2-11/igt@i915_pm_...@basic-api.html * igt@i915_suspend@basic-s2idle-without-i915: - fi-kbl-7567u: [ABORT][9] ([i915#8299]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/fi-kbl-7567u/igt@i915_susp...@basic-s2idle-without-i915.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v7/fi-kbl-7567u/igt@i915_susp...@basic-s2idle-without-i915.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1: - bat-dg2-8: [FAIL][11] ([i915#7932]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v7/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-2: - fi-bsw-n3050: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/fi-bsw-n3050/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-hdmi-a-2.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v7/fi-bsw-n3050/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-hdmi-a-2.html * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-2: - bat-dg1-5: [FAIL][15] ([fdo#103375]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12934/bat-dg1-5/igt@kms_pipe_crc_basic@suspend-read-...@pipe-d-hdmi-a-2.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_100327v7/bat-dg1-5/igt@kms_pipe_crc_basic@suspend-read-...@pipe-d-hdmi-a-2.html [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932 [i915#8299]: https://gitlab.freedesktop.org/drm/intel/issues/8299 [i915#8308]: https://gitlab.freedesktop.org/drm/intel/issues/8308 Build changes - * Linux: CI_DRM_12934 -> Patchwork_100327v7 CI-20190529: 20190529 CI_DRM_12934: 0d5e1ccc82c11e9d26d31b55b885a8d3f6588a8d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7225: e2b54c935ac78a78a4243b22c53b1a61fd04ffdb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_100327v7: 0d5e1ccc82c11e9d26d31b55b885a8d3f6588a8d @
Re: [Intel-gfx] [PATCH 2/2] drm/i915/dp: Use current cdclk for DSC Bigjoiner BW check
On Wed, Mar 29, 2023 at 04:44:12PM +0300, Lisovskiy, Stanislav wrote: > On Wed, Mar 29, 2023 at 02:35:38PM +0300, Ville Syrjälä wrote: > > On Wed, Mar 29, 2023 at 05:00:55PM +0530, Nautiyal, Ankit K wrote: > > > > > > On 3/29/2023 4:23 PM, Ville Syrjälä wrote: > > > > On Wed, Mar 29, 2023 at 04:06:21PM +0530, Nautiyal, Ankit K wrote: > > > >> On 3/29/2023 3:27 PM, Ville Syrjälä wrote: > > > >>> On Wed, Mar 29, 2023 at 02:14:49PM +0530, Ankit Nautiyal wrote: > > > As per Bspec, Big Joiner BW check is: > > > Output bpp <= PPC * CDCLK frequency * Big joiner interface bits / > > > Pixel clock > > > > > > Currently we always use max_cdclk in the check for both modevalid > > > and compute config steps. > > > > > > During modevalid use max_cdclk_freq for the check. > > > During compute config step use current cdclk for the check. > > > >>> Nak. cdclk is computed much later based on what is actually needed. > > > >>> The cdclk freq you are using here is essentially a random number. > > > >> Oh I didn't realise that, perhaps I was lucky when I tested this. > > > >> > > > >> So this check where CDCLK is mentioned, actually expects > > > >> max_cdclk_freq? > > > >> > > We use max_cdclk_freq basically as a "hack" to estimate what could be the max > amount of the CDCLK, because for the reasons, Ville mentioned, we can't use > CDCLK directly here, because it hasn't been yet calculated. > > However we anyway know CDCLK will be aligned accordingly to pixel rate. > > > > >> If it doesnt then, we might have a compressed_bpp value, that might be > > > >> violating the big joiner bw check. > > > >> > > > >> Should this be handled while computing cdclk? > > > > Yes. I suggest adding something like intel_vdsc_min_cdclk() that > > > > handles all of it. > > > > > > > > > I can try that out. > > It is all again about that same chicken problem. > Our paradigm is that CDCLK is the last thing that we calculate, however that > check instructs us to choose the output bpp which obeys > > Output bpp <= PPC * CDCLK frequency * Big joiner interface bits / pixel clock > > rule. > > If we choose to adjust CDCLK accordingly, we loose an option to actually > change > the ourpur bpp to save the power, because theoretically we could avoid > increasing > CDCLK to match that rule, by decreasing the output bpp.. > > So this kinda leads us to possibly waste more power. The main questions in selecting the bpp are what kind of quality is achievable and/or acceptable. The rest (link rate/cdclk/etc.) are all derived based on that. Doing it the other way around would essentially result in non-deterministic behaviour. Currently the only way to affect the quality criteria is the max_bpc property which isn't really properly defined when it comes to compression. Also it just specifies the max, not the the min (or what the user would consider acceptable). Every now and then I muse about introducing some kind of abstract "power vs. quality/performance" knob that would give the driver better hints as to which the user values more. With something like that we could try to reduce the quality in places to achieve better power savings. -- Ville Syrjälä Intel
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: use ref_tracker library for tracking wakerefs (rev7)
== Series Details == Series: drm/i915: use ref_tracker library for tracking wakerefs (rev7) URL : https://patchwork.freedesktop.org/series/100327/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: use ref_tracker library for tracking wakerefs (rev7)
== Series Details ==
Series: drm/i915: use ref_tracker library for tracking wakerefs (rev7)
URL : https://patchwork.freedesktop.org/series/100327/
State : warning
== Summary ==
Error: dim checkpatch failed
a48ff8d4bbf3 lib/ref_tracker: add unlocked leak print helper
-:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#6:
To have reliable detection of leaks, caller must be able to check under the same
total: 0 errors, 1 warnings, 0 checks, 105 lines checked
996793d734ce lib/ref_tracker: improve printing stats
-:40: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#40: FILE: include/linux/ref_tracker.h:31:
+static inline void __ref_tracker_dir_init(struct ref_tracker_dir *dir,
+ unsigned int quarantine_count,
-:49: WARNING:STRLCPY: Prefer strscpy over strlcpy - see:
https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=v6a6g1ouzcprm...@mail.gmail.com/
#49: FILE: include/linux/ref_tracker.h:41:
+ strlcpy(dir->name, name, sizeof(dir->name));
total: 0 errors, 1 warnings, 1 checks, 151 lines checked
56912d5da2d2 lib/ref_tracker: add printing to memory buffer
-:54: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fmt' - possible side-effects?
#54: FILE: lib/ref_tracker.c:70:
+#define pr_ostream(stream, fmt, args...) \
+({ \
+ struct ostream *_s = (stream); \
+\
+ if (!_s->buf) { \
+ pr_err(fmt, ##args); \
+ } else { \
+ int ret, len = _s->size - _s->used; \
+ ret = snprintf(_s->buf + _s->used, len, pr_fmt(fmt), ##args); \
+ _s->used += min(ret, len); \
+ } \
+})
total: 0 errors, 0 warnings, 1 checks, 109 lines checked
8a5c4020d1b0 lib/ref_tracker: remove warnings in case of allocation failure
da506567d133 drm/i915: Correct type of wakeref variable
fe7edc6eb029 drm/i915: Replace custom intel runtime_pm tracker with ref_tracker
library
-:404: WARNING:NEW_TYPEDEFS: do not add new typedefs
#404: FILE: drivers/gpu/drm/i915/intel_wakeref.h:24:
+typedef unsigned long intel_wakeref_t;
total: 0 errors, 1 warnings, 0 checks, 426 lines checked
28b072da3355 drm/i915: track gt pm wakerefs
-:464: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'gt' - possible side-effects?
#464: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm.h:75:
+#define with_intel_gt_pm(gt, wf) \
+ for (wf = intel_gt_pm_get(gt); wf; intel_gt_pm_put(gt, wf), wf = 0)
-:464: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'wf' - possible side-effects?
#464: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm.h:75:
+#define with_intel_gt_pm(gt, wf) \
+ for (wf = intel_gt_pm_get(gt); wf; intel_gt_pm_put(gt, wf), wf = 0)
-:795: ERROR:ASSIGN_IN_IF: do not use assignment in if condition
#795: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1328:
+ if (!in_reset && (wakeref = intel_gt_pm_get_if_awake(gt))) {
total: 1 errors, 0 warnings, 2 checks, 789 lines checked
d3633524d9af drm/i915/gt: Hold a wakeref for the active VM
-:81: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of
BUG() or variants
#81: FILE: drivers/gpu/drm/i915/gt/intel_engine_pm.c:117:
+ GEM_BUG_ON(rq->context->active_count != 1);
total: 0 errors, 1 warnings, 0 checks, 57 lines checked
[Intel-gfx] [PATCH 12/12] drm/i915: Do state check for color management changes
From: Ville Syrjälä
In order to validate LUT programming more thoroughly let's
do a state check for all color management updates as well.
Not sure we really want this outside CI. It is rather heavy
and color management updates could become rather common
with all the HDR/etc. stuff happening. Maybe we should have
an extra knob for this that we could enable in CI?
v2: Skip for initial_commit to avoid FDI dotclock
sanity checks/etc. tripping up
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_modeset_verify.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 842d70f0dfd2..9e4767e1b900 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -228,6 +228,8 @@ void intel_modeset_verify_crtc(struct intel_crtc *crtc,
struct intel_crtc_state *new_crtc_state)
{
if (!intel_crtc_needs_modeset(new_crtc_state) &&
+ (!intel_crtc_needs_color_update(new_crtc_state) ||
+new_crtc_state->inherited) &&
!intel_crtc_needs_fastset(new_crtc_state))
return;
--
2.39.2
[Intel-gfx] [PATCH 10/12] drm/i915: Include the csc matrices in the crtc state dump
From: Ville Syrjälä
Include the csc matrices in the state dump. The format being
hardware specific we just dump as hex for now. Might have
to think of some way to get a bit more human readable
output...
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_crtc_state_dump.c | 43 +++
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 766633566fd6..2c410ad53ccd 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -158,6 +158,41 @@ static void intel_dump_plane_state(const struct
intel_plane_state *plane_state)
DRM_RECT_ARG(_state->uapi.dst));
}
+static void
+ilk_dump_csc(struct drm_i915_private *i915, const char *name,
+const struct intel_csc_matrix *csc)
+{
+ int i;
+
+ drm_dbg_kms(>drm,
+ "%s: pre offsets: 0x%04x 0x%04x 0x%04x\n", name,
+ csc->preoff[0], csc->preoff[1], csc->preoff[2]);
+
+ for (i = 0; i < 3; i++)
+ drm_dbg_kms(>drm,
+ "%s: coefficients: 0x%04x 0x%04x 0x%04x\n", name,
+ csc->coeff[3*i+0], csc->coeff[3*i+1],
csc->coeff[3*i+2]);
+
+ if (DISPLAY_VER(i915) < 7)
+ return;
+
+ drm_dbg_kms(>drm,
+ "%s: post offsets: 0x%04x 0x%04x 0x%04x\n", name,
+ csc->postoff[0], csc->postoff[1], csc->postoff[2]);
+}
+
+static void
+chv_dump_csc(struct drm_i915_private *i915, const char *name,
+const struct intel_csc_matrix *csc)
+{
+ int i;
+
+ for (i = 0; i < 3; i++)
+ drm_dbg_kms(>drm,
+ "%s: coefficients: 0x%04x 0x%04x 0x%04x\n", name,
+ csc->coeff[3*i+0], csc->coeff[3*i+1],
csc->coeff[3*i+2]);
+}
+
void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state,
const char *context)
@@ -325,6 +360,14 @@ void intel_crtc_state_dump(const struct intel_crtc_state
*pipe_config,
pipe_config->post_csc_lut ?
drm_color_lut_size(pipe_config->post_csc_lut) : 0);
+ if (DISPLAY_VER(i915) >= 11)
+ ilk_dump_csc(i915, "output csc", _config->output_csc);
+
+ if (!HAS_GMCH(i915))
+ ilk_dump_csc(i915, "pipe csc", _config->csc);
+ else if (IS_CHERRYVIEW(i915))
+ chv_dump_csc(i915, "cgm csc", _config->csc);
+
dump_planes:
if (!state)
return;
--
2.39.2
[Intel-gfx] [PATCH 09/12] drm/i915: Implement chv cgm csc readout
From: Ville Syrjälä
Read out the csc matrix on chv, and stash the result into the
correct spot in the crtc state.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 36 ++
1 file changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 86b0d8260574..baadf62aabb4 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -612,6 +612,41 @@ static void chv_load_cgm_csc(struct intel_crtc *crtc,
csc->coeff[8]);
}
+static void chv_read_cgm_csc(struct intel_crtc *crtc,
+struct intel_csc_matrix *csc)
+{
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 tmp;
+
+ tmp = intel_de_read_fw(i915, CGM_PIPE_CSC_COEFF01(pipe));
+ csc->coeff[0] = tmp & 0x;
+ csc->coeff[1] = tmp >> 16;
+
+ tmp = intel_de_read_fw(i915, CGM_PIPE_CSC_COEFF23(pipe));
+ csc->coeff[2] = tmp & 0x;
+ csc->coeff[3] = tmp >> 16;
+
+ tmp = intel_de_read_fw(i915, CGM_PIPE_CSC_COEFF45(pipe));
+ csc->coeff[4] = tmp & 0x;
+ csc->coeff[5] = tmp >> 16;
+
+ tmp = intel_de_read_fw(i915, CGM_PIPE_CSC_COEFF67(pipe));
+ csc->coeff[6] = tmp & 0x;
+ csc->coeff[7] = tmp >> 16;
+
+ tmp = intel_de_read_fw(i915, CGM_PIPE_CSC_COEFF8(pipe));
+ csc->coeff[8] = tmp & 0x;
+}
+
+static void chv_read_csc(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
+ chv_read_cgm_csc(crtc, _state->csc);
+}
+
static void chv_assign_csc(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
@@ -3329,6 +3364,7 @@ static const struct intel_color_funcs chv_color_funcs = {
.load_luts = chv_load_luts,
.read_luts = chv_read_luts,
.lut_equal = chv_lut_equal,
+ .read_csc = chv_read_csc,
};
static const struct intel_color_funcs i965_color_funcs = {
--
2.39.2
[Intel-gfx] [PATCH 11/12] drm/i915: Hook up csc into state checker
From: Ville Syrjälä
Have the state checker validate that the csc matrices
look correct when read back from the hardware.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 21
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index aa22241c971c..763f7fdfb27c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5643,6 +5643,24 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_CSC(name) do { \
+ PIPE_CONF_CHECK_X(name.preoff[0]); \
+ PIPE_CONF_CHECK_X(name.preoff[1]); \
+ PIPE_CONF_CHECK_X(name.preoff[2]); \
+ PIPE_CONF_CHECK_X(name.coeff[0]); \
+ PIPE_CONF_CHECK_X(name.coeff[1]); \
+ PIPE_CONF_CHECK_X(name.coeff[2]); \
+ PIPE_CONF_CHECK_X(name.coeff[3]); \
+ PIPE_CONF_CHECK_X(name.coeff[4]); \
+ PIPE_CONF_CHECK_X(name.coeff[5]); \
+ PIPE_CONF_CHECK_X(name.coeff[6]); \
+ PIPE_CONF_CHECK_X(name.coeff[7]); \
+ PIPE_CONF_CHECK_X(name.coeff[8]); \
+ PIPE_CONF_CHECK_X(name.postoff[0]); \
+ PIPE_CONF_CHECK_X(name.postoff[1]); \
+ PIPE_CONF_CHECK_X(name.postoff[2]); \
+} while (0)
+
#define PIPE_CONF_QUIRK(quirk) \
((current_config->quirks | pipe_config->quirks) & (quirk))
@@ -5740,6 +5758,9 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
+ PIPE_CONF_CHECK_CSC(csc);
+ PIPE_CONF_CHECK_CSC(output_csc);
+
if (current_config->active_planes) {
PIPE_CONF_CHECK_BOOL(has_psr);
PIPE_CONF_CHECK_BOOL(has_psr2);
--
2.39.2
[Intel-gfx] [PATCH 07/12] drm/i915: Sprinke a few sanity check WARNS during csc assignment
From: Ville Syrjälä
Make sure the csc enable bit(s) match the way we're about to
fill the csc matrices.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 7e8820583942..2988c91d8ff6 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -373,10 +373,16 @@ static void ilk_assign_csc(struct intel_crtc_state
*crtc_state)
bool limited_color_range = ilk_csc_limited_range(crtc_state);
if (crtc_state->hw.ctm) {
+ drm_WARN_ON(>drm, !crtc_state->csc_enable);
+
ilk_csc_convert_ctm(crtc_state, _state->csc,
limited_color_range);
} else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
+ drm_WARN_ON(>drm, !crtc_state->csc_enable);
+
ilk_csc_copy(i915, _state->csc,
_csc_matrix_rgb_to_ycbcr);
} else if (limited_color_range) {
+ drm_WARN_ON(>drm, !crtc_state->csc_enable);
+
ilk_csc_copy(i915, _state->csc,
_csc_matrix_limited_range);
} else if (crtc_state->csc_enable) {
/*
@@ -406,16 +412,26 @@ static void icl_assign_csc(struct intel_crtc_state
*crtc_state)
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
if (crtc_state->hw.ctm) {
+ drm_WARN_ON(>drm, (crtc_state->csc_mode & ICL_CSC_ENABLE)
== 0);
+
ilk_csc_convert_ctm(crtc_state, _state->csc, false);
} else {
+ drm_WARN_ON(>drm, (crtc_state->csc_mode & ICL_CSC_ENABLE)
!= 0);
+
intel_csc_clear(_state->csc);
}
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
+ drm_WARN_ON(>drm, (crtc_state->csc_mode &
ICL_OUTPUT_CSC_ENABLE) == 0);
+
ilk_csc_copy(i915, _state->output_csc,
_csc_matrix_rgb_to_ycbcr);
} else if (crtc_state->limited_color_range) {
+ drm_WARN_ON(>drm, (crtc_state->csc_mode &
ICL_OUTPUT_CSC_ENABLE) == 0);
+
ilk_csc_copy(i915, _state->output_csc,
_csc_matrix_limited_range);
} else {
+ drm_WARN_ON(>drm, (crtc_state->csc_mode &
ICL_OUTPUT_CSC_ENABLE) != 0);
+
intel_csc_clear(_state->output_csc);
}
}
@@ -476,9 +492,15 @@ static void chv_load_cgm_csc(struct intel_crtc *crtc,
static void chv_assign_csc(struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+
if (crtc_state->hw.ctm) {
+ drm_WARN_ON(>drm, (crtc_state->cgm_mode &
CGM_PIPE_MODE_CSC) == 0);
+
chv_cgm_csc_convert_ctm(crtc_state, _state->csc);
} else {
+ drm_WARN_ON(>drm, (crtc_state->cgm_mode &
CGM_PIPE_MODE_CSC) != 0);
+
intel_csc_clear(_state->csc);
}
}
--
2.39.2
[Intel-gfx] [PATCH 08/12] drm/i915: Add hardware csc readout for ilk+
From: Ville Syrjälä
Read out the pipe/output csc matrices on ilk+ and stash the results
(in the hardware specific format) into the appropriate place
in the crtc state.
Note that on skl/glk/icl the pipe csc unit suffers from an issue
where *reads* of the coefficient/offset registers also disarm
the double buffer update (if currently armed via CSC_MODE write).
So it's rather important that the readout only happens after the
csc registers have been latched. Fortunately the state checker
only runs after the start of vblank where the latching happens.
And on skl/glk the DMC + CSC register read has the potential to
corrupt the latched CSC register values, so let's add a comment
reminding us that the DC states should remain off until the
readout has been completed.
TODO: maybe we could somehow check to make sure PSR has in fact
latched the new register values already, and that DC states
have been off all along?
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 133 +++
drivers/gpu/drm/i915/display/intel_display.c | 6 +
2 files changed, 139 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 2988c91d8ff6..86b0d8260574 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -25,6 +25,7 @@
#include "i915_reg.h"
#include "intel_color.h"
#include "intel_de.h"
+#include "intel_display_power.h"
#include "intel_display_types.h"
#include "intel_dsb.h"
@@ -70,6 +71,11 @@ struct intel_color_funcs {
const struct drm_property_blob *blob1,
const struct drm_property_blob *blob2,
bool is_pre_csc_lut);
+ /*
+* Read out the CSCs (if any) from the hardware into the
+* software state. Used by eg. the hardware state checker.
+*/
+ void (*read_csc)(struct intel_crtc_state *crtc_state);
};
#define CTM_COEFF_SIGN (1ULL << 63)
@@ -227,6 +233,72 @@ static void ilk_update_pipe_csc(struct intel_crtc *crtc,
intel_de_write_fw(i915, PIPE_CSC_POSTOFF_LO(pipe), csc->postoff[2]);
}
+static void ilk_read_pipe_csc(struct intel_crtc *crtc,
+ struct intel_csc_matrix *csc)
+{
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 tmp;
+
+ csc->preoff[0] = intel_de_read_fw(i915, PIPE_CSC_PREOFF_HI(pipe));
+ csc->preoff[1] = intel_de_read_fw(i915, PIPE_CSC_PREOFF_ME(pipe));
+ csc->preoff[2] = intel_de_read_fw(i915, PIPE_CSC_PREOFF_LO(pipe));
+
+ tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_RY_GY(pipe));
+ csc->coeff[0] = tmp >> 16;
+ csc->coeff[1] = tmp & 0x;
+ tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_BY(pipe));
+ csc->coeff[2] = tmp >> 16;
+
+ tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_RU_GU(pipe));
+ csc->coeff[3] = tmp >> 16;
+ csc->coeff[4] = tmp & 0x;
+ tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_BU(pipe));
+ csc->coeff[5] = tmp >> 16;
+
+ tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_RV_GV(pipe));
+ csc->coeff[6] = tmp >> 16;
+ csc->coeff[7] = tmp & 0x;
+ tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_BV(pipe));
+ csc->coeff[8] = tmp >> 16;
+
+ if (DISPLAY_VER(i915) < 7)
+ return;
+
+ csc->postoff[0] = intel_de_read_fw(i915, PIPE_CSC_POSTOFF_HI(pipe));
+ csc->postoff[1] = intel_de_read_fw(i915, PIPE_CSC_POSTOFF_ME(pipe));
+ csc->postoff[2] = intel_de_read_fw(i915, PIPE_CSC_POSTOFF_LO(pipe));
+}
+
+static void ilk_read_csc(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if (crtc_state->csc_enable)
+ ilk_read_pipe_csc(crtc, _state->csc);
+}
+
+static void skl_read_csc(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ /*
+* Display WA #1184: skl,glk
+* Wa_1406463849: icl
+*
+* Danger! On SKL-ICL *reads* from the CSC coeff/offset registers
+* will disarm an already armed CSC double buffer update.
+* So this must not be called while armed. Fortunately the state checker
+* readout happens only after the update has been already been latched.
+*
+* On earlier and later platforms only writes to said registers will
+* disarm the update. This is considered normal behavior and also
+* happens with various other hardware units.
+*/
+ if (crtc_state->csc_enable)
+ ilk_read_pipe_csc(crtc, _state->csc);
+}
+
static void icl_update_output_csc(struct intel_crtc *crtc,
const struct intel_csc_matrix *csc)
{
@@ -257,6 +329,56 @@ static void icl_update_output_csc(struct intel_crtc *crtc,
[Intel-gfx] [PATCH 06/12] drm/i915: Utilize crtc_state->csc on chv
From: Ville Syrjälä
Store the chv cgm csc matrix in the crtc state as well. We
shall store it in the same place where we store the ilk+
pipe csc matrix (as opposed to the output csc matrix).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 35 +-
1 file changed, 21 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index a6f7eba59e12..7e8820583942 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -431,10 +431,10 @@ static void icl_load_csc_matrix(const struct
intel_crtc_state *crtc_state)
icl_update_output_csc(crtc, _state->output_csc);
}
-static void chv_cgm_csc_convert_ctm(struct intel_csc_matrix *csc,
- const struct drm_property_blob *blob)
+static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
+ struct intel_csc_matrix *csc)
{
- const struct drm_color_ctm *ctm = blob->data;
+ const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
int i;
for (i = 0; i < 9; i++) {
@@ -457,24 +457,30 @@ static void chv_cgm_csc_convert_ctm(struct
intel_csc_matrix *csc,
}
static void chv_load_cgm_csc(struct intel_crtc *crtc,
-const struct drm_property_blob *blob)
+const struct intel_csc_matrix *csc)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- struct intel_csc_matrix tmp;
-
- chv_cgm_csc_convert_ctm(, blob);
intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF01(pipe),
- tmp.coeff[1] << 16 | tmp.coeff[0]);
+ csc->coeff[1] << 16 | csc->coeff[0]);
intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF23(pipe),
- tmp.coeff[3] << 16 | tmp.coeff[2]);
+ csc->coeff[3] << 16 | csc->coeff[2]);
intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF45(pipe),
- tmp.coeff[5] << 16 | tmp.coeff[4]);
+ csc->coeff[5] << 16 | csc->coeff[4]);
intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF67(pipe),
- tmp.coeff[7] << 16 | tmp.coeff[6]);
+ csc->coeff[7] << 16 | csc->coeff[6]);
intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF8(pipe),
- tmp.coeff[8]);
+ csc->coeff[8]);
+}
+
+static void chv_assign_csc(struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->hw.ctm) {
+ chv_cgm_csc_convert_ctm(crtc_state, _state->csc);
+ } else {
+ intel_csc_clear(_state->csc);
+ }
}
/* convert hw value with given bit_precision to lut property val */
@@ -1442,10 +1448,9 @@ static void chv_load_luts(const struct intel_crtc_state
*crtc_state)
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
- const struct drm_property_blob *ctm = crtc_state->hw.ctm;
if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
- chv_load_cgm_csc(crtc, ctm);
+ chv_load_cgm_csc(crtc, _state->csc);
if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
chv_load_cgm_degamma(crtc, pre_csc_lut);
@@ -1872,6 +1877,8 @@ static int chv_color_check(struct intel_crtc_state
*crtc_state)
intel_assign_luts(crtc_state);
+ chv_assign_csc(crtc_state);
+
crtc_state->preload_luts = chv_can_preload_luts(crtc_state);
return 0;
--
2.39.2
