[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests

[Patchwork]

== Series Details ==

Series: drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests
URL   : https://patchwork.freedesktop.org/series/117713/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13143_full -> Patchwork_117713v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_117713v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_117713v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (7 -> 7)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_117713v1_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-apl:  [PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-apl7/igt@kms_plane@plane-panning-bottom-right-susp...@pipe-b-planes.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/shard-apl2/igt@kms_plane@plane-panning-bottom-right-susp...@pipe-b-planes.html

  
Known issues


  Here are the changes found in Patchwork_117713v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][3] -> [FAIL][4] ([i915#2842])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_lmem_swapping@massive-random:
- shard-glk:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/shard-glk2/igt@gem_lmem_swapp...@massive-random.html

  * igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-snb:  [PASS][6] -> [DMESG-FAIL][7] ([i915#8295])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-snb4/igt@gem_pp...@blt-vs-render-ctx0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/shard-snb6/igt@gem_pp...@blt-vs-render-ctx0.html

  * igt@gen9_exec_parse@allowed-single:
- shard-apl:  [PASS][8] -> [ABORT][9] ([i915#5566])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-apl2/igt@gen9_exec_pa...@allowed-single.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/shard-apl3/igt@gen9_exec_pa...@allowed-single.html

  * igt@kms_chamelium_color@ctm-max:
- shard-glk:  NOTRUN -> [SKIP][10] ([fdo#109271]) +24 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/shard-glk2/igt@kms_chamelium_co...@ctm-max.html

  * igt@kms_content_protection@atomic:
- shard-glk:  NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4579])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/shard-glk2/igt@kms_content_protect...@atomic.html

  
 Possible fixes 

  * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}:[FAIL][12] ([i915#7742]) -> [PASS][13] +1 similar 
issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/shard-rkl-3/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html

  * igt@gem_ctx_freq@sysfs:
- {shard-dg1}:[FAIL][14] ([i915#6786]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-dg1-15/igt@gem_ctx_f...@sysfs.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/shard-dg1-14/igt@gem_ctx_f...@sysfs.html

  * igt@gem_eio@hibernate:
- {shard-dg1}:[ABORT][16] ([i915#7975] / [i915#8213]) -> [PASS][17] 
+1 similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-dg1-14/igt@gem_...@hibernate.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/shard-dg1-17/igt@gem_...@hibernate.html

  * igt@gem_eio@in-flight-contexts-10ms:
- {shard-tglu}:   [TIMEOUT][18] ([i915#3063] / [i915#7941]) -> 
[PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-tglu-3/igt@gem_...@in-flight-contexts-10ms.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/shard-tglu-2/igt@gem_...@in-flight-contexts-10ms.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
- {shard-dg1}:[TIMEOUT][20] ([i915#5493]) -> [PASS][21]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-dg1-17/igt@gem_lmem_swapping@smem-...@lmem0.html
   [21]: 

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

[Dixit, Ashutosh]

On Fri, 12 May 2023 18:55:44 -0700, Umesh Nerlige Ramappa wrote:
>
> From: Tvrtko Ursulin 
>
> Reserve some bits in the counter config namespace which will carry the
> tile id and prepare the code to handle this.
>
> No per tile counters have been added yet.
>
> v2:
> - Fix checkpatch issues
> - Use 4 bits for gt id in non-engine counters. Drop FIXME.
> - Set MAX GTs to 4. Drop FIXME.
>
> v3: (Ashutosh, Tvrtko)
> - Drop BUG_ON that would never fire
> - Make enable u64
> - Pull in some code from next patch

Just a reminder in case you want to do something like:

#define I915_PMU_MAX_GTS I915_MAX_GT

Or replace I915_PMU_MAX_GTS by I915_MAX_GT.

But otherwise v3 LGTM:

Reviewed-by: Ashutosh Dixit 

> Signed-off-by: Tvrtko Ursulin 
> Signed-off-by: Umesh Nerlige Ramappa 
> ---
>  drivers/gpu/drm/i915/i915_pmu.c | 148 +++-
>  drivers/gpu/drm/i915/i915_pmu.h |  11 ++-
>  include/uapi/drm/i915_drm.h |  17 +++-
>  3 files changed, 129 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 725b01b00775..b3dd9e51c5cc 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -56,11 +56,21 @@ static bool is_engine_config(u64 config)
>   return config < __I915_PMU_OTHER(0);
>  }
>
> +static unsigned int config_gt_id(const u64 config)
> +{
> + return config >> __I915_PMU_GT_SHIFT;
> +}
> +
> +static u64 config_counter(const u64 config)
> +{
> + return config & ~(~0ULL << __I915_PMU_GT_SHIFT);
> +}
> +
>  static unsigned int other_bit(const u64 config)
>  {
>   unsigned int val;
>
> - switch (config) {
> + switch (config_counter(config)) {
>   case I915_PMU_ACTUAL_FREQUENCY:
>   val =  __I915_PMU_ACTUAL_FREQUENCY_ENABLED;
>   break;
> @@ -78,7 +88,9 @@ static unsigned int other_bit(const u64 config)
>   return -1;
>   }
>
> - return I915_ENGINE_SAMPLE_COUNT + val;
> + return I915_ENGINE_SAMPLE_COUNT +
> +config_gt_id(config) * __I915_PMU_TRACKED_EVENT_COUNT +
> +val;
>  }
>
>  static unsigned int config_bit(const u64 config)
> @@ -104,10 +116,22 @@ static unsigned int event_bit(struct perf_event *event)
>   return config_bit(event->attr.config);
>  }
>
> +static u64 frequency_enabled_mask(void)
> +{
> + unsigned int i;
> + u64 mask = 0;
> +
> + for (i = 0; i < I915_PMU_MAX_GTS; i++)
> + mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) |
> + config_mask(__I915_PMU_REQUESTED_FREQUENCY(i));
> +
> + return mask;
> +}
> +
>  static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
>  {
>   struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
> - u32 enable;
> + u64 enable;
>
>   /*
>* Only some counters need the sampling timer.
> @@ -120,9 +144,7 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool 
> gpu_active)
>* Mask out all the ones which do not need the timer, or in
>* other words keep all the ones that could need the timer.
>*/
> - enable &= config_mask(I915_PMU_ACTUAL_FREQUENCY) |
> -   config_mask(I915_PMU_REQUESTED_FREQUENCY) |
> -   ENGINE_SAMPLE_MASK;
> + enable &= frequency_enabled_mask() | ENGINE_SAMPLE_MASK;
>
>   /*
>* When the GPU is idle per-engine counters do not need to be
> @@ -164,9 +186,37 @@ static inline s64 ktime_since_raw(const ktime_t kt)
>   return ktime_to_ns(ktime_sub(ktime_get_raw(), kt));
>  }
>
> +static unsigned int
> +__sample_idx(struct i915_pmu *pmu, unsigned int gt_id, int sample)
> +{
> + unsigned int idx = gt_id * __I915_NUM_PMU_SAMPLERS + sample;
> +
> + GEM_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
> +
> + return idx;
> +}
> +
> +static u64 read_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample)
> +{
> + return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur;
> +}
> +
> +static void
> +store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val)
> +{
> + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val;
> +}
> +
> +static void
> +add_sample_mult(struct i915_pmu *pmu, unsigned int gt_id, int sample, u32 
> val, u32 mul)
> +{
> + pmu->sample[__sample_idx(pmu, gt_id, sample)].cur += mul_u32_u32(val, 
> mul);
> +}
> +
>  static u64 get_rc6(struct intel_gt *gt)
>  {
>   struct drm_i915_private *i915 = gt->i915;
> + const unsigned int gt_id = gt->info.id;
>   struct i915_pmu *pmu = >pmu;
>   unsigned long flags;
>   bool awake = false;
> @@ -181,7 +231,7 @@ static u64 get_rc6(struct intel_gt *gt)
>   spin_lock_irqsave(>lock, flags);
>
>   if (awake) {
> - pmu->sample[__I915_SAMPLE_RC6].cur = val;
> + store_sample(pmu, gt_id, __I915_SAMPLE_RC6, val);
>   } else {
>   /*
>* We think we are runtime suspended.
> @@ -190,14 +240,14 @@ static u64 

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915/mtl: Extend Wa_16014892111 to MTL A-step

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/mtl: Extend Wa_16014892111 to 
MTL A-step
URL   : https://patchwork.freedesktop.org/series/117717/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13143 -> Patchwork_117717v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_117717v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_117717v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117717v1/index.html

Participating hosts (38 -> 38)
--

  Additional (1): fi-kbl-soraka 
  Missing(1): fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_117717v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_module_load@load:
- bat-adls-5: [PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-adls-5/igt@i915_module_l...@load.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117717v1/bat-adls-5/igt@i915_module_l...@load.html

  
Known issues


  Here are the changes found in Patchwork_117717v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117717v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117717v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][5] ([i915#5334] / [i915#7872])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117717v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][6] ([i915#1886] / [i915#7913])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117717v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@mman:
- bat-rpls-2: [PASS][7] -> [TIMEOUT][8] ([i915#6794] / [i915#7392])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rpls-2/igt@i915_selftest@l...@mman.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117717v1/bat-rpls-2/igt@i915_selftest@l...@mman.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][9] ([i915#6687])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117717v1/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][10] ([i915#6687] / [i915#7953] / 
[i915#7978])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117717v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka:  NOTRUN -> [SKIP][11] ([fdo#109271]) +15 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117717v1/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html

  * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1:
- bat-dg2-8:  [PASS][12] -> [FAIL][13] ([i915#7932])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117717v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-soraka:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4579])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117717v1/fi-kbl-soraka/igt@kms_setm...@basic-clone-single-crtc.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][15] ([i915#5334]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117717v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@reset:
- bat-rpls-1: [ABORT][17] ([i915#4983] / [i915#7461] / [i915#7953] 
/ [i915#8347] / [i915#8384]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rpls-1/igt@i915_selftest@l...@reset.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117717v1/bat-rpls-1/igt@i915_selftest@l...@reset.html

  
 Warnings 

  * 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc/slpc: Disable rps_boost debugfs

[Patchwork]

== Series Details ==

Series: drm/i915/guc/slpc: Disable rps_boost debugfs
URL   : https://patchwork.freedesktop.org/series/117711/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13143_full -> Patchwork_117711v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_117711v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_117711v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (7 -> 8)
--

  Additional (1): shard-rkl0 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_117711v1_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-apl:  [PASS][1] -> [TIMEOUT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-apl3/igt@i915_pm_...@modeset-non-lpsp-stress-no-wait.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/shard-apl4/igt@i915_pm_...@modeset-non-lpsp-stress-no-wait.html

  
Known issues


  Here are the changes found in Patchwork_117711v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@massive-random:
- shard-glk:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/shard-glk8/igt@gem_lmem_swapp...@massive-random.html

  * igt@kms_chamelium_color@ctm-max:
- shard-glk:  NOTRUN -> [SKIP][4] ([fdo#109271]) +26 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/shard-glk8/igt@kms_chamelium_co...@ctm-max.html

  * igt@kms_content_protection@atomic:
- shard-glk:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4579])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/shard-glk8/igt@kms_content_protect...@atomic.html

  
 Possible fixes 

  * igt@gem_barrier_race@remote-request@rcs0:
- shard-glk:  [ABORT][6] ([i915#7461] / [i915#8211]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@gem_barrier_race@remote-requ...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/shard-glk4/igt@gem_barrier_race@remote-requ...@rcs0.html

  * igt@gem_ctx_freq@sysfs:
- {shard-dg1}:[FAIL][8] ([i915#6786]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-dg1-15/igt@gem_ctx_f...@sysfs.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/shard-dg1-17/igt@gem_ctx_f...@sysfs.html

  * igt@gem_eio@hibernate:
- {shard-dg1}:[ABORT][10] ([i915#7975] / [i915#8213]) -> [PASS][11] 
+1 similar issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-dg1-14/igt@gem_...@hibernate.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/shard-dg1-17/igt@gem_...@hibernate.html

  * igt@gem_eio@in-flight-contexts-10ms:
- {shard-tglu}:   [TIMEOUT][12] ([i915#3063] / [i915#7941]) -> 
[PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-tglu-3/igt@gem_...@in-flight-contexts-10ms.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/shard-tglu-2/igt@gem_...@in-flight-contexts-10ms.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl:  [FAIL][14] ([i915#2842]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-apl2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/shard-apl2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
- {shard-tglu}:   [FAIL][16] ([i915#2842]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-tglu-10/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/shard-tglu-7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- {shard-rkl}:[FAIL][18] ([i915#2842]) -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-rkl-1/igt@gem_exec_fair@basic-p...@rcs0.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/shard-rkl-2/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gen9_exec_parse@allowed-single:
- shard-glk:  [ABORT][20] ([i915#5566]) -> [PASS][21]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk1/igt@gen9_exec_pa...@allowed-single.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/shard-glk8/igt@gen9_exec_pa...@allowed-single.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/2] drm/i915/mtl: Extend Wa_16014892111 to MTL A-step

[Patchwork]

== Series Details ==

Series: series starting with [v2,1/2] drm/i915/mtl: Extend Wa_16014892111 to 
MTL A-step
URL   : https://patchwork.freedesktop.org/series/117717/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced 
symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced 
symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced 
symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced 
symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced 
symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced 
symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced 
symbol 'mask'

[Intel-gfx] ✗ Fi.CI.BAT: failure for Add MTL PMU support for multi-gt (rev3)

[Patchwork]

== Series Details ==

Series: Add MTL PMU support for multi-gt (rev3)
URL   : https://patchwork.freedesktop.org/series/115836/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13143 -> Patchwork_115836v3


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_115836v3 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_115836v3, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v3/index.html

Participating hosts (38 -> 38)
--

  Additional (1): fi-kbl-soraka 
  Missing(1): fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_115836v3:

### IGT changes ###

 Possible regressions 

  * igt@i915_module_load@load:
- bat-adls-5: [PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-adls-5/igt@i915_module_l...@load.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v3/bat-adls-5/igt@i915_module_l...@load.html

  
Known issues


  Here are the changes found in Patchwork_115836v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v3/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v3/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_pm_backlight@basic-brightness@edp-1:
- bat-rplp-1: NOTRUN -> [ABORT][5] ([i915#7077])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v3/bat-rplp-1/igt@i915_pm_backlight@basic-brightn...@edp-1.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][6] ([i915#1886] / [i915#7913])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v3/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][7] ([i915#6687])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v3/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271]) +15 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v3/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-1:
- fi-rkl-11600:   [PASS][9] -> [FAIL][10] ([fdo#103375])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/fi-rkl-11600/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-1.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v3/fi-rkl-11600/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-1.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-soraka:  NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4579])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v3/fi-kbl-soraka/igt@kms_setm...@basic-clone-single-crtc.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][12] ([i915#5334]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v3/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@requests:
- {bat-mtlp-8}:   [ABORT][14] ([i915#4983] / [i915#7920] / [i915#7953]) 
-> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-mtlp-8/igt@i915_selftest@l...@requests.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v3/bat-mtlp-8/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][16] ([i915#4983] / [i915#7461] / [i915#7913] 
/ [i915#8347]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rpls-2/igt@i915_selftest@l...@reset.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115836v3/bat-rpls-2/igt@i915_selftest@l...@reset.html

  
 Warnings 

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [ABORT][18] ([i915#4579] / [i915#8260]) -> [SKIP][19] 
([i915#3555] / [i915#4579])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
   [19]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add MTL PMU support for multi-gt (rev3)

[Patchwork]

== Series Details ==

Series: Add MTL PMU support for multi-gt (rev3)
URL   : https://patchwork.freedesktop.org/series/115836/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add MTL PMU support for multi-gt (rev3)

[Patchwork]

== Series Details ==

Series: Add MTL PMU support for multi-gt (rev3)
URL   : https://patchwork.freedesktop.org/series/115836/
State : warning

== Summary ==

Error: dim checkpatch failed
676522fb00c9 drm/i915/pmu: Support PMU for all engines
61ea4272bfb6 drm/i915/pmu: Skip sampling engines with no enabled counters
9fe606b911b9 drm/i915/pmu: Transform PMU parking code to be GT based
43f184cc4b6d drm/i915/pmu: Add reference counting to the sampling timer
073311739b04 drm/i915/pmu: Prepare for multi-tile non-engine counters
-:106: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#106: FILE: drivers/gpu/drm/i915/i915_pmu.c:194:
+   GEM_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));

total: 0 errors, 1 warnings, 0 checks, 351 lines checked
a68ee0bfca8f drm/i915/pmu: Export counters from all tiles

Re: [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer

[Dixit, Ashutosh]

On Fri, 12 May 2023 18:55:43 -0700, Umesh Nerlige Ramappa wrote:
>
> From: Tvrtko Ursulin 
>
> We do not want to have timers per tile and waste CPU cycles and energy via
> multiple wake-up sources, for a relatively un-important task of PMU
> sampling, so keeping a single timer works well. But we also do not want
> the first GT which goes idle to turn off the timer.
>
> Add some reference counting, via a mask of unparked GTs, to solve this.
>
> v2: Drop the check for unparked in i915_sample (Ashutosh)

Reviewed-by: Ashutosh Dixit 

>
> Signed-off-by: Tvrtko Ursulin 
> Reviewed-by: Umesh Nerlige Ramappa 
> Signed-off-by: Umesh Nerlige Ramappa 
> ---
>  drivers/gpu/drm/i915/i915_pmu.c | 9 +++--
>  drivers/gpu/drm/i915/i915_pmu.h | 4 
>  2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 2b63ee31e1b3..725b01b00775 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -251,7 +251,9 @@ void i915_pmu_gt_parked(struct intel_gt *gt)
>* Signal sampling timer to stop if only engine events are enabled and
>* GPU went idle.
>*/
> - pmu->timer_enabled = pmu_needs_timer(pmu, false);
> + pmu->unparked &= ~BIT(gt->info.id);
> + if (pmu->unparked == 0)
> + pmu->timer_enabled = pmu_needs_timer(pmu, false);
>
>   spin_unlock_irq(>lock);
>  }
> @@ -268,7 +270,10 @@ void i915_pmu_gt_unparked(struct intel_gt *gt)
>   /*
>* Re-enable sampling timer when GPU goes active.
>*/
> - __i915_pmu_maybe_start_timer(pmu);
> + if (pmu->unparked == 0)
> + __i915_pmu_maybe_start_timer(pmu);
> +
> + pmu->unparked |= BIT(gt->info.id);
>
>   spin_unlock_irq(>lock);
>  }
> diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
> index a686fd7ccedf..3a811266ac6a 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.h
> +++ b/drivers/gpu/drm/i915/i915_pmu.h
> @@ -76,6 +76,10 @@ struct i915_pmu {
>* @lock: Lock protecting enable mask and ref count handling.
>*/
>   spinlock_t lock;
> + /**
> +  * @unparked: GT unparked mask.
> +  */
> + unsigned int unparked;
>   /**
>* @timer: Timer for internal i915 PMU sampling.
>*/
> --
> 2.36.1
>

[Intel-gfx] [PATCH v2 1/2] drm/i915/mtl: Extend Wa_16014892111 to MTL A-step

[Radhakrishna Sripada]

The dg2 workaround which is used for performance tuning
is needed for Meteorlake A-step.

v2: Limit the WA for A-step

Bspec: 68331
Cc: Haridhar Kalvala 
Cc: Matt Roper 
Cc: Gustavo Sousa 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 81a96c52a92b..9c1007c44298 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1370,7 +1370,9 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context 
*ce, u32 *cs)
  cs, GEN12_GFX_CCS_AUX_NV);
 
/* Wa_16014892111 */
-   if (IS_DG2(ce->engine->i915))
+   if (IS_DG2(ce->engine->i915) ||
+   IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
+   IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0))
cs = dg2_emit_draw_watermark_setting(cs);
 
return cs;
-- 
2.34.1

[Intel-gfx] [PATCH v2 2/2] drm/i915/mtl: Add MTL performance tuning changes

[Radhakrishna Sripada]

MTL reuses the tuning parameters for DG2. Extend the dg2
performance tuning parameters to MTL.

v2: Add DRAW_WATERMARK tuning parameter.

Bspec: 68331
Cc: Haridhar Kalvala 
Cc: Matt Roper 
Cc: Gustavo Sousa 
Signed-off-by: Radhakrishna Sripada 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 786349e95487..72dab970de5b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -817,6 +817,10 @@ static void mtl_ctx_workarounds_init(struct 
intel_engine_cs *engine,
 {
struct drm_i915_private *i915 = engine->i915;
 
+   dg2_ctx_gt_tuning_init(engine, wal);
+
+   wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
+
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
/* Wa_14014947963 */
@@ -1754,7 +1758,7 @@ static void gt_tuning_settings(struct intel_gt *gt, 
struct i915_wa_list *wal)
wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
}
 
-   if (IS_DG2(gt->i915)) {
+   if (IS_DG2(gt->i915) || IS_METEORLAKE(gt->i915)) {
wa_mcr_write_or(wal, XEHP_L3SCQREG7, 
BLEND_FILL_CACHING_OPT_DIS);
wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
}
@@ -2944,7 +2948,7 @@ static void
 add_render_compute_tuning_settings(struct drm_i915_private *i915,
   struct i915_wa_list *wal)
 {
-   if (IS_DG2(i915))
+   if (IS_DG2(i915) || IS_METEORLAKE(i915))
wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, 
STACKID_CTRL_512);
 
/*
-- 
2.34.1

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hwmon: Silence UBSAN uninitialized bool variable warning (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/hwmon: Silence UBSAN uninitialized bool variable warning (rev2)
URL   : https://patchwork.freedesktop.org/series/117591/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13143_full -> Patchwork_117591v2_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (7 -> 8)
--

  Additional (1): shard-tglu0 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_117591v2_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_lease@lessee_list@pipe-b-hdmi-a-4:
- {shard-dg1}:[PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-dg1-16/igt@kms_lease@lessee_l...@pipe-b-hdmi-a-4.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/shard-dg1-16/igt@kms_lease@lessee_l...@pipe-b-hdmi-a-4.html

  * igt@kms_lease@lessee_list@pipe-d-hdmi-a-4:
- {shard-dg1}:[PASS][3] -> [DMESG-WARN][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-dg1-16/igt@kms_lease@lessee_l...@pipe-d-hdmi-a-4.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/shard-dg1-16/igt@kms_lease@lessee_l...@pipe-d-hdmi-a-4.html

  
Known issues


  Here are the changes found in Patchwork_117591v2_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_barrier_race@remote-request@rcs0:
- shard-apl:  [PASS][5] -> [ABORT][6] ([i915#7461] / [i915#8211] / 
[i915#8234])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-apl1/igt@gem_barrier_race@remote-requ...@rcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/shard-apl7/igt@gem_barrier_race@remote-requ...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_lmem_swapping@massive-random:
- shard-glk:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/shard-glk6/igt@gem_lmem_swapp...@massive-random.html

  * igt@gen9_exec_parse@allowed-all:
- shard-apl:  [PASS][10] -> [ABORT][11] ([i915#5566])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-apl2/igt@gen9_exec_pa...@allowed-all.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/shard-apl1/igt@gen9_exec_pa...@allowed-all.html

  * igt@kms_chamelium_color@ctm-max:
- shard-glk:  NOTRUN -> [SKIP][12] ([fdo#109271]) +26 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/shard-glk6/igt@kms_chamelium_co...@ctm-max.html

  * igt@kms_content_protection@atomic:
- shard-glk:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4579])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/shard-glk6/igt@kms_content_protect...@atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk:  [PASS][14] -> [FAIL][15] ([i915#2346])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/shard-glk4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk:  [PASS][16] -> [FAIL][17] ([i915#2122])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html

  
 Possible fixes 

  * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}:[FAIL][18] ([i915#7742]) -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/shard-rkl-6/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html

  * igt@gem_barrier_race@remote-request@rcs0:
- shard-glk:  [ABORT][20] ([i915#7461] / [i915#8211]) -> [PASS][21]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@gem_barrier_race@remote-requ...@rcs0.html
   [21]: 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gvt: KVM: KVMGT fixes and page-track cleanups (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915/gvt: KVM: KVMGT fixes and page-track cleanups (rev8)
URL   : https://patchwork.freedesktop.org/series/112196/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13143 -> Patchwork_112196v8


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_112196v8 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_112196v8, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112196v8/index.html

Participating hosts (38 -> 36)
--

  Missing(2): bat-rpls-2 fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_112196v8:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@dmabuf:
- bat-adls-5: [PASS][1] -> [DMESG-WARN][2] +19 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-adls-5/igt@i915_selftest@l...@dmabuf.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112196v8/bat-adls-5/igt@i915_selftest@l...@dmabuf.html

  
Known issues


  Here are the changes found in Patchwork_112196v8 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_backlight@basic-brightness@edp-1:
- bat-rplp-1: NOTRUN -> [ABORT][3] ([i915#7077])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112196v8/bat-rplp-1/igt@i915_pm_backlight@basic-brightn...@edp-1.html

  * igt@i915_selftest@live@migrate:
- bat-dg2-11: [PASS][4] -> [DMESG-WARN][5] ([i915#7699] / 
[i915#7953])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-dg2-11/igt@i915_selftest@l...@migrate.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112196v8/bat-dg2-11/igt@i915_selftest@l...@migrate.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][6] ([i915#6687] / [i915#7953] / 
[i915#7978])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112196v8/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#1845] / [i915#5354]) +2 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112196v8/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][8] ([i915#5334]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112196v8/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@requests:
- {bat-mtlp-8}:   [ABORT][10] ([i915#4983] / [i915#7920] / [i915#7953]) 
-> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-mtlp-8/igt@i915_selftest@l...@requests.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112196v8/bat-mtlp-8/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@reset:
- bat-rpls-1: [ABORT][12] ([i915#4983] / [i915#7461] / [i915#7953] 
/ [i915#8347] / [i915#8384]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rpls-1/igt@i915_selftest@l...@reset.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112196v8/bat-rpls-1/igt@i915_selftest@l...@reset.html

  
 Warnings 

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [ABORT][14] ([i915#4579] / [i915#8260]) -> [SKIP][15] 
([i915#3555] / [i915#4579])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112196v8/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#7077]: 

[Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

[Umesh Nerlige Ramappa]

From: Tvrtko Ursulin 

Reserve some bits in the counter config namespace which will carry the
tile id and prepare the code to handle this.

No per tile counters have been added yet.

v2:
- Fix checkpatch issues
- Use 4 bits for gt id in non-engine counters. Drop FIXME.
- Set MAX GTs to 4. Drop FIXME.

v3: (Ashutosh, Tvrtko)
- Drop BUG_ON that would never fire
- Make enable u64
- Pull in some code from next patch

Signed-off-by: Tvrtko Ursulin 
Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/i915_pmu.c | 148 +++-
 drivers/gpu/drm/i915/i915_pmu.h |  11 ++-
 include/uapi/drm/i915_drm.h |  17 +++-
 3 files changed, 129 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 725b01b00775..b3dd9e51c5cc 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -56,11 +56,21 @@ static bool is_engine_config(u64 config)
return config < __I915_PMU_OTHER(0);
 }
 
+static unsigned int config_gt_id(const u64 config)
+{
+   return config >> __I915_PMU_GT_SHIFT;
+}
+
+static u64 config_counter(const u64 config)
+{
+   return config & ~(~0ULL << __I915_PMU_GT_SHIFT);
+}
+
 static unsigned int other_bit(const u64 config)
 {
unsigned int val;
 
-   switch (config) {
+   switch (config_counter(config)) {
case I915_PMU_ACTUAL_FREQUENCY:
val =  __I915_PMU_ACTUAL_FREQUENCY_ENABLED;
break;
@@ -78,7 +88,9 @@ static unsigned int other_bit(const u64 config)
return -1;
}
 
-   return I915_ENGINE_SAMPLE_COUNT + val;
+   return I915_ENGINE_SAMPLE_COUNT +
+  config_gt_id(config) * __I915_PMU_TRACKED_EVENT_COUNT +
+  val;
 }
 
 static unsigned int config_bit(const u64 config)
@@ -104,10 +116,22 @@ static unsigned int event_bit(struct perf_event *event)
return config_bit(event->attr.config);
 }
 
+static u64 frequency_enabled_mask(void)
+{
+   unsigned int i;
+   u64 mask = 0;
+
+   for (i = 0; i < I915_PMU_MAX_GTS; i++)
+   mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) |
+   config_mask(__I915_PMU_REQUESTED_FREQUENCY(i));
+
+   return mask;
+}
+
 static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
 {
struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
-   u32 enable;
+   u64 enable;
 
/*
 * Only some counters need the sampling timer.
@@ -120,9 +144,7 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool 
gpu_active)
 * Mask out all the ones which do not need the timer, or in
 * other words keep all the ones that could need the timer.
 */
-   enable &= config_mask(I915_PMU_ACTUAL_FREQUENCY) |
- config_mask(I915_PMU_REQUESTED_FREQUENCY) |
- ENGINE_SAMPLE_MASK;
+   enable &= frequency_enabled_mask() | ENGINE_SAMPLE_MASK;
 
/*
 * When the GPU is idle per-engine counters do not need to be
@@ -164,9 +186,37 @@ static inline s64 ktime_since_raw(const ktime_t kt)
return ktime_to_ns(ktime_sub(ktime_get_raw(), kt));
 }
 
+static unsigned int
+__sample_idx(struct i915_pmu *pmu, unsigned int gt_id, int sample)
+{
+   unsigned int idx = gt_id * __I915_NUM_PMU_SAMPLERS + sample;
+
+   GEM_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
+
+   return idx;
+}
+
+static u64 read_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample)
+{
+   return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur;
+}
+
+static void
+store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val)
+{
+   pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val;
+}
+
+static void
+add_sample_mult(struct i915_pmu *pmu, unsigned int gt_id, int sample, u32 val, 
u32 mul)
+{
+   pmu->sample[__sample_idx(pmu, gt_id, sample)].cur += mul_u32_u32(val, 
mul);
+}
+
 static u64 get_rc6(struct intel_gt *gt)
 {
struct drm_i915_private *i915 = gt->i915;
+   const unsigned int gt_id = gt->info.id;
struct i915_pmu *pmu = >pmu;
unsigned long flags;
bool awake = false;
@@ -181,7 +231,7 @@ static u64 get_rc6(struct intel_gt *gt)
spin_lock_irqsave(>lock, flags);
 
if (awake) {
-   pmu->sample[__I915_SAMPLE_RC6].cur = val;
+   store_sample(pmu, gt_id, __I915_SAMPLE_RC6, val);
} else {
/*
 * We think we are runtime suspended.
@@ -190,14 +240,14 @@ static u64 get_rc6(struct intel_gt *gt)
 * on top of the last known real value, as the approximated RC6
 * counter value.
 */
-   val = ktime_since_raw(pmu->sleep_last);
-   val += pmu->sample[__I915_SAMPLE_RC6].cur;
+   val = ktime_since_raw(pmu->sleep_last[gt_id]);
+   val += read_sample(pmu, gt_id, __I915_SAMPLE_RC6);
}
 
-

[Intel-gfx] [PATCH 0/6] Add MTL PMU support for multi-gt

[Umesh Nerlige Ramappa]

With MTL, frequency and rc6 counters are specific to a gt. Export these
counters via gt-specific events to the user space.

v2: Review comments (Ashutosh, Tvrtko)

Signed-off-by: Umesh Nerlige Ramappa 

Tvrtko Ursulin (6):
  drm/i915/pmu: Support PMU for all engines
  drm/i915/pmu: Skip sampling engines with no enabled counters
  drm/i915/pmu: Transform PMU parking code to be GT based
  drm/i915/pmu: Add reference counting to the sampling timer
  drm/i915/pmu: Prepare for multi-tile non-engine counters
  drm/i915/pmu: Export counters from all tiles

 drivers/gpu/drm/i915/gt/intel_gt_pm.c |   4 +-
 drivers/gpu/drm/i915/i915_pmu.c   | 263 ++
 drivers/gpu/drm/i915/i915_pmu.h   |  24 ++-
 include/uapi/drm/i915_drm.h   |  17 +-
 4 files changed, 219 insertions(+), 89 deletions(-)

-- 
2.36.1

[Intel-gfx] [PATCH 3/6] drm/i915/pmu: Transform PMU parking code to be GT based

[Umesh Nerlige Ramappa]

From: Tvrtko Ursulin 

Trivial prep work for full multi-tile enablement later.

Signed-off-by: Tvrtko Ursulin 
Signed-off-by: Vinay Belgaumkar 
Reviewed-by: Umesh Nerlige Ramappa 
Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/gt/intel_gt_pm.c |  4 ++--
 drivers/gpu/drm/i915/i915_pmu.c   | 16 
 drivers/gpu/drm/i915/i915_pmu.h   |  9 +
 3 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c 
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index e02cb90723ae..c2e69bafd02b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -87,7 +87,7 @@ static int __gt_unpark(struct intel_wakeref *wf)
 
intel_rc6_unpark(>rc6);
intel_rps_unpark(>rps);
-   i915_pmu_gt_unparked(i915);
+   i915_pmu_gt_unparked(gt);
intel_guc_busyness_unpark(gt);
 
intel_gt_unpark_requests(gt);
@@ -109,7 +109,7 @@ static int __gt_park(struct intel_wakeref *wf)
 
intel_guc_busyness_park(gt);
i915_vma_parked(gt);
-   i915_pmu_gt_parked(i915);
+   i915_pmu_gt_parked(gt);
intel_rps_park(>rps);
intel_rc6_park(>rc6);
 
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index ba769f7fc385..2b63ee31e1b3 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -217,11 +217,11 @@ static void init_rc6(struct i915_pmu *pmu)
}
 }
 
-static void park_rc6(struct drm_i915_private *i915)
+static void park_rc6(struct intel_gt *gt)
 {
-   struct i915_pmu *pmu = >pmu;
+   struct i915_pmu *pmu = >i915->pmu;
 
-   pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(to_gt(i915));
+   pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(gt);
pmu->sleep_last = ktime_get_raw();
 }
 
@@ -236,16 +236,16 @@ static void __i915_pmu_maybe_start_timer(struct i915_pmu 
*pmu)
}
 }
 
-void i915_pmu_gt_parked(struct drm_i915_private *i915)
+void i915_pmu_gt_parked(struct intel_gt *gt)
 {
-   struct i915_pmu *pmu = >pmu;
+   struct i915_pmu *pmu = >i915->pmu;
 
if (!pmu->base.event_init)
return;
 
spin_lock_irq(>lock);
 
-   park_rc6(i915);
+   park_rc6(gt);
 
/*
 * Signal sampling timer to stop if only engine events are enabled and
@@ -256,9 +256,9 @@ void i915_pmu_gt_parked(struct drm_i915_private *i915)
spin_unlock_irq(>lock);
 }
 
-void i915_pmu_gt_unparked(struct drm_i915_private *i915)
+void i915_pmu_gt_unparked(struct intel_gt *gt)
 {
-   struct i915_pmu *pmu = >pmu;
+   struct i915_pmu *pmu = >i915->pmu;
 
if (!pmu->base.event_init)
return;
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index c30f43319a78..a686fd7ccedf 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -13,6 +13,7 @@
 #include 
 
 struct drm_i915_private;
+struct intel_gt;
 
 /*
  * Non-engine events that we need to track enabled-disabled transition and
@@ -151,15 +152,15 @@ int i915_pmu_init(void);
 void i915_pmu_exit(void);
 void i915_pmu_register(struct drm_i915_private *i915);
 void i915_pmu_unregister(struct drm_i915_private *i915);
-void i915_pmu_gt_parked(struct drm_i915_private *i915);
-void i915_pmu_gt_unparked(struct drm_i915_private *i915);
+void i915_pmu_gt_parked(struct intel_gt *gt);
+void i915_pmu_gt_unparked(struct intel_gt *gt);
 #else
 static inline int i915_pmu_init(void) { return 0; }
 static inline void i915_pmu_exit(void) {}
 static inline void i915_pmu_register(struct drm_i915_private *i915) {}
 static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
-static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {}
-static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {}
+static inline void i915_pmu_gt_parked(struct intel_gt *gt) {}
+static inline void i915_pmu_gt_unparked(struct intel_gt *gt) {}
 #endif
 
 #endif
-- 
2.36.1

[Intel-gfx] [PATCH 1/6] drm/i915/pmu: Support PMU for all engines

[Umesh Nerlige Ramappa]

From: Tvrtko Ursulin 

Given how the metrics are already exported, we also need to run sampling
over engines from all GTs.

Problem of GT frequencies is left for later.

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Umesh Nerlige Ramappa 
Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/i915_pmu.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 7ece883a7d95..67fa6cd77529 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -10,6 +10,7 @@
 #include "gt/intel_engine_pm.h"
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_engine_user.h"
+#include "gt/intel_gt.h"
 #include "gt/intel_gt_pm.h"
 #include "gt/intel_gt_regs.h"
 #include "gt/intel_rc6.h"
@@ -414,8 +415,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer 
*hrtimer)
struct drm_i915_private *i915 =
container_of(hrtimer, struct drm_i915_private, pmu.timer);
struct i915_pmu *pmu = >pmu;
-   struct intel_gt *gt = to_gt(i915);
unsigned int period_ns;
+   struct intel_gt *gt;
+   unsigned int i;
ktime_t now;
 
if (!READ_ONCE(pmu->timer_enabled))
@@ -431,8 +433,13 @@ static enum hrtimer_restart i915_sample(struct hrtimer 
*hrtimer)
 * grabbing the forcewake. However the potential error from timer call-
 * back delay greatly dominates this so we keep it simple.
 */
-   engines_sample(gt, period_ns);
-   frequency_sample(gt, period_ns);
+
+   for_each_gt(gt, i915, i) {
+   engines_sample(gt, period_ns);
+
+   if (i == 0) /* FIXME */
+   frequency_sample(gt, period_ns);
+   }
 
hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD));
 
-- 
2.36.1

[Intel-gfx] [PATCH 6/6] drm/i915/pmu: Export counters from all tiles

[Umesh Nerlige Ramappa]

From: Tvrtko Ursulin 

Start exporting frequency and RC6 counters from all tiles.

Existing counters keep their names and config values and new one use the
namespace added in the previous patch, with the "-gtN" added to their
names.

Interrupts counter is an odd one off. Because it is the global device
counters (not only GT) we choose not to add per tile versions for now.

Signed-off-by: Tvrtko Ursulin 
Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/i915_pmu.c | 82 ++---
 1 file changed, 55 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index b3dd9e51c5cc..12345fd0b2cd 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -927,11 +927,20 @@ static const struct attribute_group 
i915_pmu_cpumask_attr_group = {
.attrs = i915_cpumask_attrs,
 };
 
-#define __event(__config, __name, __unit) \
+#define __event(__counter, __name, __unit) \
 { \
-   .config = (__config), \
+   .counter = (__counter), \
.name = (__name), \
.unit = (__unit), \
+   .global = false, \
+}
+
+#define __global_event(__counter, __name, __unit) \
+{ \
+   .counter = (__counter), \
+   .name = (__name), \
+   .unit = (__unit), \
+   .global = true, \
 }
 
 #define __engine_event(__sample, __name) \
@@ -970,15 +979,16 @@ create_event_attributes(struct i915_pmu *pmu)
 {
struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
static const struct {
-   u64 config;
+   unsigned int counter;
const char *name;
const char *unit;
+   bool global;
} events[] = {
-   __event(I915_PMU_ACTUAL_FREQUENCY, "actual-frequency", "M"),
-   __event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency", 
"M"),
-   __event(I915_PMU_INTERRUPTS, "interrupts", NULL),
-   __event(I915_PMU_RC6_RESIDENCY, "rc6-residency", "ns"),
-   __event(I915_PMU_SOFTWARE_GT_AWAKE_TIME, 
"software-gt-awake-time", "ns"),
+   __event(0, "actual-frequency", "M"),
+   __event(1, "requested-frequency", "M"),
+   __global_event(2, "interrupts", NULL),
+   __event(3, "rc6-residency", "ns"),
+   __event(4, "software-gt-awake-time", "ns"),
};
static const struct {
enum drm_i915_pmu_engine_sample sample;
@@ -993,12 +1003,17 @@ create_event_attributes(struct i915_pmu *pmu)
struct i915_ext_attribute *i915_attr = NULL, *i915_iter;
struct attribute **attr = NULL, **attr_iter;
struct intel_engine_cs *engine;
-   unsigned int i;
+   struct intel_gt *gt;
+   unsigned int i, j;
 
/* Count how many counters we will be exposing. */
-   for (i = 0; i < ARRAY_SIZE(events); i++) {
-   if (!config_status(i915, events[i].config))
-   count++;
+   for_each_gt(gt, i915, j) {
+   for (i = 0; i < ARRAY_SIZE(events); i++) {
+   u64 config = ___I915_PMU_OTHER(j, events[i].counter);
+
+   if (!config_status(i915, config))
+   count++;
+   }
}
 
for_each_uabi_engine(engine, i915) {
@@ -1028,26 +1043,39 @@ create_event_attributes(struct i915_pmu *pmu)
attr_iter = attr;
 
/* Initialize supported non-engine counters. */
-   for (i = 0; i < ARRAY_SIZE(events); i++) {
-   char *str;
-
-   if (config_status(i915, events[i].config))
-   continue;
-
-   str = kstrdup(events[i].name, GFP_KERNEL);
-   if (!str)
-   goto err;
+   for_each_gt(gt, i915, j) {
+   for (i = 0; i < ARRAY_SIZE(events); i++) {
+   u64 config = ___I915_PMU_OTHER(j, events[i].counter);
+   char *str;
 
-   *attr_iter++ = _iter->attr.attr;
-   i915_iter = add_i915_attr(i915_iter, str, events[i].config);
+   if (config_status(i915, config))
+   continue;
 
-   if (events[i].unit) {
-   str = kasprintf(GFP_KERNEL, "%s.unit", events[i].name);
+   if (events[i].global || !HAS_EXTRA_GT_LIST(i915))
+   str = kstrdup(events[i].name, GFP_KERNEL);
+   else
+   str = kasprintf(GFP_KERNEL, "%s-gt%u",
+   events[i].name, j);
if (!str)
goto err;
 
-   *attr_iter++ = _iter->attr.attr;
-   pmu_iter = add_pmu_attr(pmu_iter, str, events[i].unit);
+   *attr_iter++ = _iter->attr.attr;
+ 

[Intel-gfx] [PATCH 2/6] drm/i915/pmu: Skip sampling engines with no enabled counters

[Umesh Nerlige Ramappa]

From: Tvrtko Ursulin 

As we have more and more engines do not waste time sampling the ones no-
one is monitoring.

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Umesh Nerlige Ramappa 
Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/i915_pmu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 67fa6cd77529..ba769f7fc385 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -339,6 +339,9 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns)
return;
 
for_each_engine(engine, gt, id) {
+   if (!engine->pmu.enable)
+   continue;
+
if (!intel_engine_pm_get_if_awake(engine))
continue;
 
-- 
2.36.1

[Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer

[Umesh Nerlige Ramappa]

From: Tvrtko Ursulin 

We do not want to have timers per tile and waste CPU cycles and energy via
multiple wake-up sources, for a relatively un-important task of PMU
sampling, so keeping a single timer works well. But we also do not want
the first GT which goes idle to turn off the timer.

Add some reference counting, via a mask of unparked GTs, to solve this.

v2: Drop the check for unparked in i915_sample (Ashutosh)

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Umesh Nerlige Ramappa 
Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/i915_pmu.c | 9 +++--
 drivers/gpu/drm/i915/i915_pmu.h | 4 
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 2b63ee31e1b3..725b01b00775 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -251,7 +251,9 @@ void i915_pmu_gt_parked(struct intel_gt *gt)
 * Signal sampling timer to stop if only engine events are enabled and
 * GPU went idle.
 */
-   pmu->timer_enabled = pmu_needs_timer(pmu, false);
+   pmu->unparked &= ~BIT(gt->info.id);
+   if (pmu->unparked == 0)
+   pmu->timer_enabled = pmu_needs_timer(pmu, false);
 
spin_unlock_irq(>lock);
 }
@@ -268,7 +270,10 @@ void i915_pmu_gt_unparked(struct intel_gt *gt)
/*
 * Re-enable sampling timer when GPU goes active.
 */
-   __i915_pmu_maybe_start_timer(pmu);
+   if (pmu->unparked == 0)
+   __i915_pmu_maybe_start_timer(pmu);
+
+   pmu->unparked |= BIT(gt->info.id);
 
spin_unlock_irq(>lock);
 }
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index a686fd7ccedf..3a811266ac6a 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -76,6 +76,10 @@ struct i915_pmu {
 * @lock: Lock protecting enable mask and ref count handling.
 */
spinlock_t lock;
+   /**
+* @unparked: GT unparked mask.
+*/
+   unsigned int unparked;
/**
 * @timer: Timer for internal i915 PMU sampling.
 */
-- 
2.36.1

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gvt: KVM: KVMGT fixes and page-track cleanups (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915/gvt: KVM: KVMGT fixes and page-track cleanups (rev8)
URL   : https://patchwork.freedesktop.org/series/112196/
State : warning

== Summary ==

Error: dim checkpatch failed
7ddfeb73c37a drm/i915/gvt: Verify pfn is "valid" before dereferencing "struct 
page"
6e46a75c5c15 drm/i915/gvt: remove interface intel_gvt_is_valid_gfn
60cd1c1b954f drm/i915/gvt: Verify hugepages are contiguous in physical address 
space
82759b84f7fc drm/i915/gvt: Put the page reference obtained by KVM's gfn_to_pfn()
a85e87c63800 drm/i915/gvt: Explicitly check that vGPU is attached before 
shadowing
2678442df896 drm/i915/gvt: Error out on an attempt to shadowing an unknown GTT 
entry type
425220f2cc46 drm/i915/gvt: Don't rely on KVM's gfn_to_pfn() to query possible 
2M GTT
66caadcfb561 drm/i915/gvt: Use an "unsigned long" to iterate over memslot gfns
cc12e36d8b5e drm/i915/gvt: Drop unused helper intel_vgpu_reset_gtt()
dfc1236b7e6e drm/i915/gvt: Protect gfn hash table with vgpu_lock
722d8f7ef123 KVM: x86/mmu: Move kvm_arch_flush_shadow_{all, memslot}() to mmu.c
b2fdeb2bb4b6 KVM: x86/mmu: Don't rely on page-track mechanism to flush on 
memslot change
58d52301be4c KVM: x86/mmu: Don't bounce through page-track mechanism for guest 
PTEs
84403a9c8920 KVM: drm/i915/gvt: Drop @vcpu from KVM's ->track_write() hook
c5834b025c35 KVM: x86: Reject memslot MOVE operations if KVMGT is attached
0e65c8e6f583 drm/i915/gvt: Don't bother removing write-protection on 
to-be-deleted slot
ad683a55df9c KVM: x86: Add a new page-track hook to handle memslot deletion
287f9c98484d drm/i915/gvt: switch from ->track_flush_slot() to 
->track_remove_region()
7630b3b1d29e KVM: x86: Remove the unused page-track hook track_flush_slot()
556343eb5969 KVM: x86/mmu: Move KVM-only page-track declarations to internal 
header
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:114: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#114: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 113 lines checked
5eeebf29aa14 KVM: x86/mmu: Use page-track notifiers iff there are external users
ec3a18744340 KVM: x86/mmu: Drop infrastructure for multiple page-track modes
1464bd80f0c0 KVM: x86/mmu: Rename page-track APIs to reflect the new reality
ccd34fefb1d2 KVM: x86/mmu: Assert that correct locks are held for page 
write-tracking
3601016aae9f KVM: x86/mmu: Bug the VM if write-tracking is used but not enabled
730b76683f02 KVM: x86/mmu: Drop @slot param from exported/external page-track 
APIs
7fcd298749ba KVM: x86/mmu: Handle KVM bookkeeping in page-track APIs, not 
callers
c1cebe248055 drm/i915/gvt: Drop final dependencies on KVM internal details

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests

[Patchwork]

== Series Details ==

Series: drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests
URL   : https://patchwork.freedesktop.org/series/117713/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13143 -> Patchwork_117713v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/index.html

Participating hosts (38 -> 37)
--

  Missing(1): fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_117713v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_backlight@basic-brightness@edp-1:
- bat-rplp-1: NOTRUN -> [ABORT][1] ([i915#7077])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/bat-rplp-1/igt@i915_pm_backlight@basic-brightn...@edp-1.html

  * igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][2] ([i915#6367])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html
- bat-rpls-1: NOTRUN -> [DMESG-WARN][3] ([i915#6367] / [i915#7953])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html

  * igt@i915_selftest@live@workarounds:
- bat-adlm-1: [PASS][4] -> [DMESG-FAIL][5] ([i915#7904])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/bat-adlm-1/igt@i915_selftest@l...@workarounds.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][6] ([i915#6687])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][7] ([i915#6687] / [i915#7953] / 
[i915#7978])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#1845] / [i915#5354]) +2 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][9] ([i915#5334]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][11] ([i915#4983] / [i915#7461] / [i915#7913] 
/ [i915#8347]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rpls-2/igt@i915_selftest@l...@reset.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/bat-rpls-2/igt@i915_selftest@l...@reset.html
- bat-rpls-1: [ABORT][13] ([i915#4983] / [i915#7461] / [i915#7953] 
/ [i915#8347] / [i915#8384]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rpls-1/igt@i915_selftest@l...@reset.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/bat-rpls-1/igt@i915_selftest@l...@reset.html

  * igt@i915_selftest@live@slpc:
- {bat-mtlp-6}:   [DMESG-WARN][15] ([i915#6367] / [i915#7953]) -> 
[PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-mtlp-6/igt@i915_selftest@l...@slpc.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/bat-mtlp-6/igt@i915_selftest@l...@slpc.html

  
 Warnings 

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [ABORT][17] ([i915#4579] / [i915#8260]) -> [SKIP][18] 
([i915#3555] / [i915#4579])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117713v1/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6687]: 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests

[Patchwork]

== Series Details ==

Series: drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests
URL   : https://patchwork.freedesktop.org/series/117713/
State : warning

== Summary ==

Error: dim checkpatch failed
b97349ae2b23 drm/i915/selftest/gsc: Ensure GSC Proxy init completes before 
selftests
-:62: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#62: FILE: drivers/gpu/drm/i915/selftests/i915_selftest.c:154:
+static struct __startup_waiter all_startup_waiters[] = { \

total: 0 errors, 1 warnings, 0 checks, 71 lines checked

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

[Dixit, Ashutosh]

On Fri, 12 May 2023 13:57:59 -0700, Umesh Nerlige Ramappa wrote:
>
> On Fri, May 12, 2023 at 11:56:18AM +0100, Tvrtko Ursulin wrote:
> >
> > On 12/05/2023 02:08, Dixit, Ashutosh wrote:
> >> On Fri, 05 May 2023 17:58:15 -0700, Umesh Nerlige Ramappa wrote:
> >>>
> >>> From: Tvrtko Ursulin 
> >>>
> >>> Reserve some bits in the counter config namespace which will carry the
> >>> tile id and prepare the code to handle this.
> >>>
> >>> No per tile counters have been added yet.
> >>>
> >>> v2:
> >>> - Fix checkpatch issues
> >>> - Use 4 bits for gt id in non-engine counters. Drop FIXME.
> >>> - Set MAX GTs to 4. Drop FIXME.
> >>>
> >>> Signed-off-by: Tvrtko Ursulin 
> >>> Signed-off-by: Umesh Nerlige Ramappa 
> >>> ---
> >>>  drivers/gpu/drm/i915/i915_pmu.c | 150 +++-
> >>>  drivers/gpu/drm/i915/i915_pmu.h |   9 +-
> >>>  include/uapi/drm/i915_drm.h |  17 +++-
> >>>  3 files changed, 129 insertions(+), 47 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_pmu.c 
> >>> b/drivers/gpu/drm/i915/i915_pmu.c
> >>> index 669a42e44082..12b2f3169abf 100644
> >>> --- a/drivers/gpu/drm/i915/i915_pmu.c
> >>> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> >>> @@ -56,11 +56,21 @@ static bool is_engine_config(u64 config)
> >>>   return config < __I915_PMU_OTHER(0);
> >>>  }
> >>>
> >>> +static unsigned int config_gt_id(const u64 config)
> >>> +{
> >>> + return config >> __I915_PMU_GT_SHIFT;
> >>> +}
> >>> +
> >>> +static u64 config_counter(const u64 config)
> >>> +{
> >>> + return config & ~(~0ULL << __I915_PMU_GT_SHIFT);
> >>
> >> ok, but another possibility:
> >>
> >>return config & ~REG_GENMASK64(63, __I915_PMU_GT_SHIFT);
> >
> > It's not a register so no. :) GENMASK_ULL maybe but meh.
>
> leaving as is.
>
> >
> >>> +}
> >>> +
> >>>  static unsigned int other_bit(const u64 config)
> >>>  {
> >>>   unsigned int val;
> >>>
> >>> - switch (config) {
> >>> + switch (config_counter(config)) {
> >>>   case I915_PMU_ACTUAL_FREQUENCY:
> >>>   val =  __I915_PMU_ACTUAL_FREQUENCY_ENABLED;
> >>>   break;
> >>> @@ -78,15 +88,20 @@ static unsigned int other_bit(const u64 config)
> >>>   return -1;
> >>>   }
> >>>
> >>> - return I915_ENGINE_SAMPLE_COUNT + val;
> >>> + return I915_ENGINE_SAMPLE_COUNT +
> >>> +config_gt_id(config) * __I915_PMU_TRACKED_EVENT_COUNT +
> >>> +val;
> >>>  }
> >>>
> >>>  static unsigned int config_bit(const u64 config)
> >>>  {
> >>> - if (is_engine_config(config))
> >>> + if (is_engine_config(config)) {
> >>> + GEM_BUG_ON(config_gt_id(config));
> >>
> >> This GEM_BUG_ON is not needed since:
> >>
> >>static bool is_engine_config(u64 config)
> >>{
> >>return config < __I915_PMU_OTHER(0);
> >>}
> >
> > True!
>
> dropping BUG_ON
>
> >
> >>> +
> >>>   return engine_config_sample(config);
> >>> - else
> >>> + } else {
> >>>   return other_bit(config);
> >>> + }
> >>>  }
> >>>
> >>>  static u64 config_mask(u64 config)
> >>> @@ -104,6 +119,18 @@ static unsigned int event_bit(struct perf_event 
> >>> *event)
> >>>   return config_bit(event->attr.config);
> >>>  }
> >>>
> >>> +static u64 frequency_enabled_mask(void)
> >>> +{
> >>> + unsigned int i;
> >>> + u64 mask = 0;
> >>> +
> >>> + for (i = 0; i < I915_PMU_MAX_GTS; i++)
> >>> + mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) |
> >>> + config_mask(__I915_PMU_REQUESTED_FREQUENCY(i));
> >>> +
> >>> + return mask;
> >>> +}
> >>> +
> >>>  static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
> >>>  {
> >>>   struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
> >>> @@ -120,9 +147,7 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, 
> >>> bool gpu_active)
> >>>* Mask out all the ones which do not need the timer, or in
> >>>* other words keep all the ones that could need the timer.
> >>>*/
> >>> - enable &= config_mask(I915_PMU_ACTUAL_FREQUENCY) |
> >>> -   config_mask(I915_PMU_REQUESTED_FREQUENCY) |
> >>> -   ENGINE_SAMPLE_MASK;
> >>> + enable &= frequency_enabled_mask() | ENGINE_SAMPLE_MASK;
> >>
> >> u32 enable & u64 frequency_enabled_mask
> >>
> >> ugly but ok I guess? Or change enable to u64?
>
> making pmu->enable u64 as well as other places where it is assigned to
> local variables.

Yes, that's the way to do it.

>
> >
> > Hmm.. yes very ugly. Could have been an accident which happened to work
> > because there is a single timer (not per tile).
>
> Happened to work because the frequency mask does not spill over to the
> upper 32 bits (even for multi tile).

Even with 4 tiles, I checked.

>
> - START_SECTION 
> >
> > Similar issue in frequency_sampling_enabled too. Gt_id argument to it
> > seems pointless.
>
> Not sure why it's pointless. We need the gt_id to determine the right mask
> for that specific gt. If it's not enabled, then we just return without
> pm_get and async put (like you mention later).
> And this 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tc: Add a workaround for an IOM/TCSS firmware hang issue (rev13)

[Patchwork]

== Series Details ==

Series: drm/i915/tc: Add a workaround for an IOM/TCSS firmware hang issue 
(rev13)
URL   : https://patchwork.freedesktop.org/series/117004/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13143_full -> Patchwork_117004v13_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (7 -> 7)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_117004v13_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][1] -> [FAIL][2] ([i915#2842])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_lmem_swapping@massive-random:
- shard-glk:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk8/igt@gem_lmem_swapp...@massive-random.html

  * igt@kms_chamelium_color@ctm-max:
- shard-glk:  NOTRUN -> [SKIP][4] ([fdo#109271]) +26 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk8/igt@kms_chamelium_co...@ctm-max.html

  * igt@kms_content_protection@atomic:
- shard-glk:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4579])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk8/igt@kms_content_protect...@atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk:  [PASS][6] -> [FAIL][7] ([i915#2346])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk3/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk:  [PASS][8] -> [FAIL][9] ([i915#79])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@ab-hdmi-a1-hdmi-a2.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk:  [PASS][10] -> [FAIL][11] ([i915#2122]) +1 similar 
issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html

  
 Possible fixes 

  * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}:[FAIL][12] ([i915#7742]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-rkl-7/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html

  * igt@gem_barrier_race@remote-request@rcs0:
- shard-glk:  [ABORT][14] ([i915#7461] / [i915#8211]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@gem_barrier_race@remote-requ...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk1/igt@gem_barrier_race@remote-requ...@rcs0.html

  * igt@gem_ctx_freq@sysfs:
- {shard-dg1}:[FAIL][16] ([i915#6786]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-dg1-15/igt@gem_ctx_f...@sysfs.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-dg1-17/igt@gem_ctx_f...@sysfs.html

  * igt@gem_eio@in-flight-contexts-10ms:
- {shard-tglu}:   [TIMEOUT][18] ([i915#3063] / [i915#7941]) -> 
[PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-tglu-3/igt@gem_...@in-flight-contexts-10ms.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-tglu-2/igt@gem_...@in-flight-contexts-10ms.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [FAIL][20] ([i915#2846]) -> [PASS][21]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@gem_exec_f...@basic-deadline.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/shard-glk3/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl:  [FAIL][22] ([i915#2842]) -> [PASS][23]
   [22]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc/slpc: Disable rps_boost debugfs

[Patchwork]

== Series Details ==

Series: drm/i915/guc/slpc: Disable rps_boost debugfs
URL   : https://patchwork.freedesktop.org/series/117711/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13143 -> Patchwork_117711v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/index.html

Participating hosts (38 -> 37)
--

  Missing(1): fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_117711v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_create@basic-files:
- fi-tgl-1115g4:  [PASS][1] -> [ABORT][2] ([i915#7953])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/fi-tgl-1115g4/igt@gem_ctx_cre...@basic-files.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/fi-tgl-1115g4/igt@gem_ctx_cre...@basic-files.html

  * igt@i915_selftest@live@slpc:
- bat-rpls-1: NOTRUN -> [DMESG-WARN][3] ([i915#6367] / [i915#7953])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][4] ([i915#6687] / [i915#7953] / 
[i915#7978])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][5] ([i915#5334]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@requests:
- {bat-mtlp-8}:   [ABORT][7] ([i915#4983] / [i915#7920] / [i915#7953]) 
-> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-mtlp-8/igt@i915_selftest@l...@requests.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@reset:
- bat-rpls-1: [ABORT][9] ([i915#4983] / [i915#7461] / [i915#7953] / 
[i915#8347] / [i915#8384]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rpls-1/igt@i915_selftest@l...@reset.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/bat-rpls-1/igt@i915_selftest@l...@reset.html

  * igt@i915_selftest@live@slpc:
- {bat-mtlp-6}:   [DMESG-WARN][11] ([i915#6367] / [i915#7953]) -> 
[PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-mtlp-6/igt@i915_selftest@l...@slpc.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/bat-mtlp-6/igt@i915_selftest@l...@slpc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
  [i915#7953]: https://gitlab.freedesktop.org/drm/intel/issues/7953
  [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
  [i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
  [i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384


Build changes
-

  * Linux: CI_DRM_13143 -> Patchwork_117711v1

  CI-20190529: 20190529
  CI_DRM_13143: 222ff19f23b0bd6aca0b52001d69699f78f5a206 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7286: a482779488f11c432d7ddcb1980691ab1603f356 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_117711v1: 222ff19f23b0bd6aca0b52001d69699f78f5a206 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

a8bc51407d9e drm/i915/guc/slpc: Disable rps_boost debugfs

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117711v1/index.html

Re: [Intel-gfx] [PATCH v2 5/8] drm/i915/huc: differentiate the 2 steps of the MTL HuC auth flow

[Teres Alexis, Alan Previn]

On Fri, 2023-04-28 at 11:58 -0700, Ceraolo Spurio, Daniele wrote:
> Before we add the second step of the MTL HuC auth (via GSC), we need to
> have the ability to differentiate between them. To do so, the huc
> authentication check is duplicated for GuC and GSC auth, with meu
> binaries being considered fully authenticated only after the GSC auth
> step.
> 
> To report the difference between the 2 auth steps, a new case is added
> to the HuC getparam. This way, the clear media driver can start
> submitting before full auth, as partial auth is enough for those
> workloads.
> 
> v2: fix authentication status check for DG2
> 
> Signed-off-by: Daniele Ceraolo Spurio 
> Cc: Alan Previn 
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_huc.c| 94 +--
>  drivers/gpu/drm/i915/gt/uc/intel_huc.h| 16 +++-
>  drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c |  4 +-
>  drivers/gpu/drm/i915/i915_reg.h   |  3 +
>  include/uapi/drm/i915_drm.h   |  3 +-
>  5 files changed, 91 insertions(+), 29 deletions(-)
> 
I believe you need a rebase with the PXP single session merged (the
readiness code in gsccs backend). Other than that, all looks good:

Reviewed-by: Alan Previn 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc/slpc: Disable rps_boost debugfs

[Patchwork]

== Series Details ==

Series: drm/i915/guc/slpc: Disable rps_boost debugfs
URL   : https://patchwork.freedesktop.org/series/117711/
State : warning

== Summary ==

Error: dim checkpatch failed
0cd47cc8985c drm/i915/guc/slpc: Disable rps_boost debugfs
-:11: WARNING:COMMIT_LOG_USE_LINK: Unknown link reference 'Bug:', use 'Link:' 
or 'Closes:' instead
#11: 
Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7632

total: 0 errors, 1 warnings, 0 checks, 19 lines checked

Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Disable rps_boost debugfs

[Dixit, Ashutosh]

On Fri, 12 May 2023 16:56:03 -0700, Vinay Belgaumkar wrote:
>

Hi Vinay,

> rps_boost debugfs shows host turbo related info. This is not valid
> when SLPC is enabled.

A couple of thoughts about this. It appears people are know only about
rps_boost_info and don't know about guc_slpc_info? So:

a. Instead of hiding the rps_boost_info file do we need to print there
   saying "SLPC is enabled, go look at guc_slpc_info"?

b. Or, even just call guc_slpc_info_show from rps_boost_show (so the two
   files will show the same SLPC information)?

Ashutosh


> guc_slpc_info already shows the number of boosts.  Add num_waiters there
> as well and disable rps_boost when SLPC is enabled.
>
> Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7632
> Signed-off-by: Vinay Belgaumkar 

Re: [Intel-gfx] [PATCH v2] drm/i915/huc: Parse the GSC-enabled HuC binary

[Teres Alexis, Alan Previn]

On Tue, 2023-05-02 at 08:27 -0700, Ceraolo Spurio, Daniele wrote:
> The new binaries that support the 2-step authentication have contain the
> legacy-style binary, which we can use for loading the HuC via DMA. To
> find out where this is located in the image, we need to parse the meu
> manifest of the GSC binary. The manifest consist of a partition header
> followed by entries, one of which contains the offset we're looking for.
> Note that the DG2 GSC binary contains entries with the same names, but
> it doesn't contain a full legacy binary, so we need to skip assigning
> the dma offset in that case (which we can do by checking the ccs).
> Also, since we're now parsing the entries, we can extract the HuC
> version that way instead of using hardcoded offsets.
> 
> Note that the meu structure will be re-used for parsing the GSC binary,
> so they've been added in their own header.
> 
> v2: fix structure names to match meu defines (s/CPT/CPD/), update commit
> message, check ccs validity, drop old version location defines.
> 
> Signed-off-by: Daniele Ceraolo Spurio 
> Cc: Alan Previn 
> ---
>  .../drm/i915/gt/uc/intel_gsc_meu_headers.h|  74 ++

Compared line by line as per internal reviews and the spec.
All looks good to me - nice to see that additional ccs validity.
LGTM, Reviewed-by: Alan Previn 

[Intel-gfx] [PATCH v3 27/28] KVM: x86/mmu: Handle KVM bookkeeping in page-track APIs, not callers

[Sean Christopherson]

Get/put references to KVM when a page-track notifier is (un)registered
instead of relying on the caller to do so.  Forcing the caller to do the
bookkeeping is unnecessary and adds one more thing for users to get
wrong, e.g. see commit 9ed1fdee9ee3 ("drm/i915/gvt: Get reference to KVM
iff attachment to VM is successful").

Reviewed-by: Yan Zhao 
Signed-off-by: Sean Christopherson 
---
 arch/x86/include/asm/kvm_page_track.h | 11 +--
 arch/x86/kvm/mmu/page_track.c | 18 --
 drivers/gpu/drm/i915/gvt/kvmgt.c  | 17 +++--
 3 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/arch/x86/include/asm/kvm_page_track.h 
b/arch/x86/include/asm/kvm_page_track.h
index 4afab697e21c..3d040741044b 100644
--- a/arch/x86/include/asm/kvm_page_track.h
+++ b/arch/x86/include/asm/kvm_page_track.h
@@ -44,12 +44,11 @@ struct kvm_page_track_notifier_node {
struct kvm_page_track_notifier_node *node);
 };
 
-void
-kvm_page_track_register_notifier(struct kvm *kvm,
-struct kvm_page_track_notifier_node *n);
-void
-kvm_page_track_unregister_notifier(struct kvm *kvm,
-  struct kvm_page_track_notifier_node *n);
+int kvm_page_track_register_notifier(struct kvm *kvm,
+struct kvm_page_track_notifier_node *n);
+void kvm_page_track_unregister_notifier(struct kvm *kvm,
+   struct kvm_page_track_notifier_node *n);
+
 int kvm_write_track_add_gfn(struct kvm *kvm, gfn_t gfn);
 int kvm_write_track_remove_gfn(struct kvm *kvm, gfn_t gfn);
 #else
diff --git a/arch/x86/kvm/mmu/page_track.c b/arch/x86/kvm/mmu/page_track.c
index 2a64df38ccab..fd04e618ad2d 100644
--- a/arch/x86/kvm/mmu/page_track.c
+++ b/arch/x86/kvm/mmu/page_track.c
@@ -157,17 +157,22 @@ int kvm_page_track_init(struct kvm *kvm)
  * register the notifier so that event interception for the tracked guest
  * pages can be received.
  */
-void
-kvm_page_track_register_notifier(struct kvm *kvm,
-struct kvm_page_track_notifier_node *n)
+int kvm_page_track_register_notifier(struct kvm *kvm,
+struct kvm_page_track_notifier_node *n)
 {
struct kvm_page_track_notifier_head *head;
 
+   if (!kvm || kvm->mm != current->mm)
+   return -ESRCH;
+
+   kvm_get_kvm(kvm);
+
head = >arch.track_notifier_head;
 
write_lock(>mmu_lock);
hlist_add_head_rcu(>node, >track_notifier_list);
write_unlock(>mmu_lock);
+   return 0;
 }
 EXPORT_SYMBOL_GPL(kvm_page_track_register_notifier);
 
@@ -175,9 +180,8 @@ EXPORT_SYMBOL_GPL(kvm_page_track_register_notifier);
  * stop receiving the event interception. It is the opposed operation of
  * kvm_page_track_register_notifier().
  */
-void
-kvm_page_track_unregister_notifier(struct kvm *kvm,
-  struct kvm_page_track_notifier_node *n)
+void kvm_page_track_unregister_notifier(struct kvm *kvm,
+   struct kvm_page_track_notifier_node *n)
 {
struct kvm_page_track_notifier_head *head;
 
@@ -187,6 +191,8 @@ kvm_page_track_unregister_notifier(struct kvm *kvm,
hlist_del_rcu(>node);
write_unlock(>mmu_lock);
synchronize_srcu(>track_srcu);
+
+   kvm_put_kvm(kvm);
 }
 EXPORT_SYMBOL_GPL(kvm_page_track_unregister_notifier);
 
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index b995d75a19c3..597ffc9d12fd 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -653,21 +653,19 @@ static bool __kvmgt_vgpu_exist(struct intel_vgpu *vgpu)
 static int intel_vgpu_open_device(struct vfio_device *vfio_dev)
 {
struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev);
-
-   if (!vgpu->vfio_device.kvm ||
-   vgpu->vfio_device.kvm->mm != current->mm) {
-   gvt_vgpu_err("KVM is required to use Intel vGPU\n");
-   return -ESRCH;
-   }
+   int ret;
 
if (__kvmgt_vgpu_exist(vgpu))
return -EEXIST;
 
vgpu->track_node.track_write = kvmgt_page_track_write;
vgpu->track_node.track_remove_region = kvmgt_page_track_remove_region;
-   kvm_get_kvm(vgpu->vfio_device.kvm);
-   kvm_page_track_register_notifier(vgpu->vfio_device.kvm,
->track_node);
+   ret = kvm_page_track_register_notifier(vgpu->vfio_device.kvm,
+  >track_node);
+   if (ret) {
+   gvt_vgpu_err("KVM is required to use Intel vGPU\n");
+   return ret;
+   }
 
set_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status);
 
@@ -702,7 +700,6 @@ static void intel_vgpu_close_device(struct vfio_device 
*vfio_dev)
 
kvm_page_track_unregister_notifier(vgpu->vfio_device.kvm,
   >track_node);
- 

[Intel-gfx] [PATCH v3 25/28] KVM: x86/mmu: Bug the VM if write-tracking is used but not enabled

[Sean Christopherson]

Bug the VM if something attempts to write-track a gfn, but write-tracking
isn't enabled.  The VM is doomed (and KVM has an egregious bug) if KVM or
KVMGT wants to shadow guest page tables but can't because write-tracking
isn't enabled.

Signed-off-by: Sean Christopherson 
---
 arch/x86/kvm/mmu/page_track.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kvm/mmu/page_track.c b/arch/x86/kvm/mmu/page_track.c
index 29ae61f1e303..eedb5889d73e 100644
--- a/arch/x86/kvm/mmu/page_track.c
+++ b/arch/x86/kvm/mmu/page_track.c
@@ -90,7 +90,7 @@ void kvm_write_track_add_gfn(struct kvm *kvm, struct 
kvm_memory_slot *slot,
lockdep_assert_once(lockdep_is_held(>slots_lock) ||
srcu_read_lock_held(>srcu));
 
-   if (WARN_ON(!kvm_page_track_write_tracking_enabled(kvm)))
+   if (KVM_BUG_ON(!kvm_page_track_write_tracking_enabled(kvm), kvm))
return;
 
update_gfn_write_track(slot, gfn, 1);
@@ -122,7 +122,7 @@ void kvm_write_track_remove_gfn(struct kvm *kvm,
lockdep_assert_once(lockdep_is_held(>slots_lock) ||
srcu_read_lock_held(>srcu));
 
-   if (WARN_ON(!kvm_page_track_write_tracking_enabled(kvm)))
+   if (KVM_BUG_ON(!kvm_page_track_write_tracking_enabled(kvm), kvm))
return;
 
update_gfn_write_track(slot, gfn, -1);
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 22/28] KVM: x86/mmu: Drop infrastructure for multiple page-track modes

[Sean Christopherson]

Drop "support" for multiple page-track modes, as there is no evidence
that array-based and refcounted metadata is the optimal solution for
other modes, nor is there any evidence that other use cases, e.g. for
access-tracking, will be a good fit for the page-track machinery in
general.

E.g. one potential use case of access-tracking would be to prevent guest
access to poisoned memory (from the guest's perspective).  In that case,
the number of poisoned pages is likely to be a very small percentage of
the guest memory, and there is no need to reference count the number of
access-tracking users, i.e. expanding gfn_track[] for a new mode would be
grossly inefficient.  And for poisoned memory, host userspace would also
likely want to trap accesses, e.g. to inject #MC into the guest, and that
isn't currently supported by the page-track framework.

A better alternative for that poisoned page use case is likely a
variation of the proposed per-gfn attributes overlay (linked), which
would allow efficiently tracking the sparse set of poisoned pages, and by
default would exit to userspace on access.

Link: https://lore.kernel.org/all/y2wb48kd0j4vg...@google.com
Cc: Ben Gardon 
Signed-off-by: Sean Christopherson 
---
 arch/x86/include/asm/kvm_host.h   |  12 +--
 arch/x86/include/asm/kvm_page_track.h |  11 +--
 arch/x86/kvm/mmu/mmu.c|  14 ++--
 arch/x86/kvm/mmu/page_track.c | 111 --
 arch/x86/kvm/mmu/page_track.h |   3 +-
 drivers/gpu/drm/i915/gvt/kvmgt.c  |   4 +-
 6 files changed, 51 insertions(+), 104 deletions(-)

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 5ce06a75d3de..3dde3a3a 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -288,13 +288,13 @@ struct kvm_kernel_irq_routing_entry;
  * kvm_mmu_page_role tracks the properties of a shadow page (where shadow page
  * also includes TDP pages) to determine whether or not a page can be used in
  * the given MMU context.  This is a subset of the overall kvm_cpu_role to
- * minimize the size of kvm_memory_slot.arch.gfn_track, i.e. allows allocating
- * 2 bytes per gfn instead of 4 bytes per gfn.
+ * minimize the size of kvm_memory_slot.arch.gfn_write_track, i.e. allows
+ * allocating 2 bytes per gfn instead of 4 bytes per gfn.
  *
  * Upper-level shadow pages having gptes are tracked for write-protection via
- * gfn_track.  As above, gfn_track is a 16 bit counter, so KVM must not create
- * more than 2^16-1 upper-level shadow pages at a single gfn, otherwise
- * gfn_track will overflow and explosions will ensure.
+ * gfn_write_track.  As above, gfn_write_track is a 16 bit counter, so KVM must
+ * not create more than 2^16-1 upper-level shadow pages at a single gfn,
+ * otherwise gfn_write_track will overflow and explosions will ensue.
  *
  * A unique shadow page (SP) for a gfn is created if and only if an existing SP
  * cannot be reused.  The ability to reuse a SP is tracked by its role, which
@@ -1005,7 +1005,7 @@ struct kvm_lpage_info {
 struct kvm_arch_memory_slot {
struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES];
struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1];
-   unsigned short *gfn_track[KVM_PAGE_TRACK_MAX];
+   unsigned short *gfn_write_track;
 };
 
 /*
diff --git a/arch/x86/include/asm/kvm_page_track.h 
b/arch/x86/include/asm/kvm_page_track.h
index 61adb07b5927..9e4ee26d1779 100644
--- a/arch/x86/include/asm/kvm_page_track.h
+++ b/arch/x86/include/asm/kvm_page_track.h
@@ -4,17 +4,10 @@
 
 #include 
 
-enum kvm_page_track_mode {
-   KVM_PAGE_TRACK_WRITE,
-   KVM_PAGE_TRACK_MAX,
-};
-
 void kvm_slot_page_track_add_page(struct kvm *kvm,
- struct kvm_memory_slot *slot, gfn_t gfn,
- enum kvm_page_track_mode mode);
+ struct kvm_memory_slot *slot, gfn_t gfn);
 void kvm_slot_page_track_remove_page(struct kvm *kvm,
-struct kvm_memory_slot *slot, gfn_t gfn,
-enum kvm_page_track_mode mode);
+struct kvm_memory_slot *slot, gfn_t gfn);
 
 #ifdef CONFIG_KVM_EXTERNAL_WRITE_TRACKING
 /*
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 0d9fe54ecb01..8041f5747704 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -837,8 +837,7 @@ static void account_shadowed(struct kvm *kvm, struct 
kvm_mmu_page *sp)
 
/* the non-leaf shadow pages are keeping readonly. */
if (sp->role.level > PG_LEVEL_4K)
-   return kvm_slot_page_track_add_page(kvm, slot, gfn,
-   KVM_PAGE_TRACK_WRITE);
+   return kvm_slot_page_track_add_page(kvm, slot, gfn);
 
kvm_mmu_gfn_disallow_lpage(slot, gfn);
 
@@ -884,8 +883,7 @@ static void unaccount_shadowed(struct kvm *kvm, struct 
kvm_mmu_page *sp)

[Intel-gfx] [PATCH v3 28/28] drm/i915/gvt: Drop final dependencies on KVM internal details

[Sean Christopherson]

Open code gpa_to_gfn() in kvmgt_page_track_write() and drop KVMGT's
dependency on kvm_host.h, i.e. include only kvm_page_track.h.  KVMGT
assumes "gfn == gpa >> PAGE_SHIFT" all over the place, including a few
lines below in the same function with the same gpa, i.e. there's no
reason to use KVM's helper for this one case.

No functional change intended.

Reviewed-by: Yan Zhao 
Signed-off-by: Sean Christopherson 
---
 drivers/gpu/drm/i915/gvt/gvt.h   | 3 ++-
 drivers/gpu/drm/i915/gvt/kvmgt.c | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 2d65800d8e93..53a0a42a50db 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -34,10 +34,11 @@
 #define _GVT_H_
 
 #include 
-#include 
 #include 
 #include 
 
+#include 
+
 #include "i915_drv.h"
 #include "intel_gvt.h"
 
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 597ffc9d12fd..191b4484cc7e 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -1584,7 +1584,7 @@ static void kvmgt_page_track_write(gpa_t gpa, const u8 
*val, int len,
 
mutex_lock(>vgpu_lock);
 
-   if (kvmgt_gfn_is_write_protected(info, gpa_to_gfn(gpa)))
+   if (kvmgt_gfn_is_write_protected(info, gpa >> PAGE_SHIFT))
intel_vgpu_page_track_handler(info, gpa,
 (void *)val, len);
 
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 26/28] KVM: x86/mmu: Drop @slot param from exported/external page-track APIs

[Sean Christopherson]

Refactor KVM's exported/external page-track, a.k.a. write-track, APIs
to take only the gfn and do the required memslot lookup in KVM proper.
Forcing users of the APIs to get the memslot unnecessarily bleeds
KVM internals into KVMGT and complicates usage of the APIs.

No functional change intended.

Reviewed-by: Yan Zhao 
Signed-off-by: Sean Christopherson 
---
 arch/x86/include/asm/kvm_page_track.h |  7 +--
 arch/x86/kvm/mmu/mmu.c|  4 +-
 arch/x86/kvm/mmu/page_track.c | 85 ---
 arch/x86/kvm/mmu/page_track.h |  5 ++
 drivers/gpu/drm/i915/gvt/kvmgt.c  | 37 +++-
 5 files changed, 80 insertions(+), 58 deletions(-)

diff --git a/arch/x86/include/asm/kvm_page_track.h 
b/arch/x86/include/asm/kvm_page_track.h
index f5c1db36cdb7..4afab697e21c 100644
--- a/arch/x86/include/asm/kvm_page_track.h
+++ b/arch/x86/include/asm/kvm_page_track.h
@@ -4,11 +4,6 @@
 
 #include 
 
-void kvm_write_track_add_gfn(struct kvm *kvm,
-struct kvm_memory_slot *slot, gfn_t gfn);
-void kvm_write_track_remove_gfn(struct kvm *kvm, struct kvm_memory_slot *slot,
-   gfn_t gfn);
-
 #ifdef CONFIG_KVM_EXTERNAL_WRITE_TRACKING
 /*
  * The notifier represented by @kvm_page_track_notifier_node is linked into
@@ -55,6 +50,8 @@ kvm_page_track_register_notifier(struct kvm *kvm,
 void
 kvm_page_track_unregister_notifier(struct kvm *kvm,
   struct kvm_page_track_notifier_node *n);
+int kvm_write_track_add_gfn(struct kvm *kvm, gfn_t gfn);
+int kvm_write_track_remove_gfn(struct kvm *kvm, gfn_t gfn);
 #else
 /*
  * Allow defining a node in a structure even if page tracking is disabled, e.g.
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 1818c047891f..22f13963c320 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -837,7 +837,7 @@ static void account_shadowed(struct kvm *kvm, struct 
kvm_mmu_page *sp)
 
/* the non-leaf shadow pages are keeping readonly. */
if (sp->role.level > PG_LEVEL_4K)
-   return kvm_write_track_add_gfn(kvm, slot, gfn);
+   return __kvm_write_track_add_gfn(kvm, slot, gfn);
 
kvm_mmu_gfn_disallow_lpage(slot, gfn);
 
@@ -883,7 +883,7 @@ static void unaccount_shadowed(struct kvm *kvm, struct 
kvm_mmu_page *sp)
slots = kvm_memslots_for_spte_role(kvm, sp->role);
slot = __gfn_to_memslot(slots, gfn);
if (sp->role.level > PG_LEVEL_4K)
-   return kvm_write_track_remove_gfn(kvm, slot, gfn);
+   return __kvm_write_track_remove_gfn(kvm, slot, gfn);
 
kvm_mmu_gfn_allow_lpage(slot, gfn);
 }
diff --git a/arch/x86/kvm/mmu/page_track.c b/arch/x86/kvm/mmu/page_track.c
index eedb5889d73e..2a64df38ccab 100644
--- a/arch/x86/kvm/mmu/page_track.c
+++ b/arch/x86/kvm/mmu/page_track.c
@@ -74,16 +74,8 @@ static void update_gfn_write_track(struct kvm_memory_slot 
*slot, gfn_t gfn,
slot->arch.gfn_write_track[index] += count;
 }
 
-/*
- * add guest page to the tracking pool so that corresponding access on that
- * page will be intercepted.
- *
- * @kvm: the guest instance we are interested in.
- * @slot: the @gfn belongs to.
- * @gfn: the guest page.
- */
-void kvm_write_track_add_gfn(struct kvm *kvm, struct kvm_memory_slot *slot,
-gfn_t gfn)
+void __kvm_write_track_add_gfn(struct kvm *kvm, struct kvm_memory_slot *slot,
+  gfn_t gfn)
 {
lockdep_assert_held_write(>mmu_lock);
 
@@ -104,18 +96,9 @@ void kvm_write_track_add_gfn(struct kvm *kvm, struct 
kvm_memory_slot *slot,
if (kvm_mmu_slot_gfn_write_protect(kvm, slot, gfn, PG_LEVEL_4K))
kvm_flush_remote_tlbs(kvm);
 }
-EXPORT_SYMBOL_GPL(kvm_write_track_add_gfn);
 
-/*
- * remove the guest page from the tracking pool which stops the interception
- * of corresponding access on that page.
- *
- * @kvm: the guest instance we are interested in.
- * @slot: the @gfn belongs to.
- * @gfn: the guest page.
- */
-void kvm_write_track_remove_gfn(struct kvm *kvm,
-   struct kvm_memory_slot *slot, gfn_t gfn)
+void __kvm_write_track_remove_gfn(struct kvm *kvm,
+ struct kvm_memory_slot *slot, gfn_t gfn)
 {
lockdep_assert_held_write(>mmu_lock);
 
@@ -133,7 +116,6 @@ void kvm_write_track_remove_gfn(struct kvm *kvm,
 */
kvm_mmu_gfn_allow_lpage(slot, gfn);
 }
-EXPORT_SYMBOL_GPL(kvm_write_track_remove_gfn);
 
 /*
  * check if the corresponding access on the specified guest page is tracked.
@@ -257,4 +239,63 @@ void kvm_page_track_delete_slot(struct kvm *kvm, struct 
kvm_memory_slot *slot)
srcu_read_unlock(>track_srcu, idx);
 }
 
+/*
+ * add guest page to the tracking pool so that corresponding access on that
+ * page will be intercepted.
+ *
+ * @kvm: the guest instance we are interested in.
+ * @gfn: the guest page.
+ */
+int kvm_write_track_add_gfn(struct kvm 

[Intel-gfx] [PATCH v3 21/28] KVM: x86/mmu: Use page-track notifiers iff there are external users

[Sean Christopherson]

Disable the page-track notifier code at compile time if there are no
external users, i.e. if CONFIG_KVM_EXTERNAL_WRITE_TRACKING=n.  KVM itself
now hooks emulated writes directly instead of relying on the page-track
mechanism.

Provide a stub for "struct kvm_page_track_notifier_node" so that including
headers directly from the command line, e.g. for testing include guards,
doesn't fail due to a struct having an incomplete type.

Signed-off-by: Sean Christopherson 
---
 arch/x86/include/asm/kvm_host.h   |  2 ++
 arch/x86/include/asm/kvm_page_track.h | 22 +---
 arch/x86/kvm/mmu/page_track.c | 10 -
 arch/x86/kvm/mmu/page_track.h | 29 +++
 4 files changed, 47 insertions(+), 16 deletions(-)

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 113598d3e886..5ce06a75d3de 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -1247,7 +1247,9 @@ struct kvm_arch {
 * create an NX huge page (without hanging the guest).
 */
struct list_head possible_nx_huge_pages;
+#ifdef CONFIG_KVM_EXTERNAL_WRITE_TRACKING
struct kvm_page_track_notifier_head track_notifier_head;
+#endif
/*
 * Protects marking pages unsync during page faults, as TDP MMU page
 * faults only take mmu_lock for read.  For simplicity, the unsync
diff --git a/arch/x86/include/asm/kvm_page_track.h 
b/arch/x86/include/asm/kvm_page_track.h
index 76c0070dfe2a..61adb07b5927 100644
--- a/arch/x86/include/asm/kvm_page_track.h
+++ b/arch/x86/include/asm/kvm_page_track.h
@@ -9,6 +9,14 @@ enum kvm_page_track_mode {
KVM_PAGE_TRACK_MAX,
 };
 
+void kvm_slot_page_track_add_page(struct kvm *kvm,
+ struct kvm_memory_slot *slot, gfn_t gfn,
+ enum kvm_page_track_mode mode);
+void kvm_slot_page_track_remove_page(struct kvm *kvm,
+struct kvm_memory_slot *slot, gfn_t gfn,
+enum kvm_page_track_mode mode);
+
+#ifdef CONFIG_KVM_EXTERNAL_WRITE_TRACKING
 /*
  * The notifier represented by @kvm_page_track_notifier_node is linked into
  * the head which will be notified when guest is triggering the track event.
@@ -48,18 +56,18 @@ struct kvm_page_track_notifier_node {
struct kvm_page_track_notifier_node *node);
 };
 
-void kvm_slot_page_track_add_page(struct kvm *kvm,
- struct kvm_memory_slot *slot, gfn_t gfn,
- enum kvm_page_track_mode mode);
-void kvm_slot_page_track_remove_page(struct kvm *kvm,
-struct kvm_memory_slot *slot, gfn_t gfn,
-enum kvm_page_track_mode mode);
-
 void
 kvm_page_track_register_notifier(struct kvm *kvm,
 struct kvm_page_track_notifier_node *n);
 void
 kvm_page_track_unregister_notifier(struct kvm *kvm,
   struct kvm_page_track_notifier_node *n);
+#else
+/*
+ * Allow defining a node in a structure even if page tracking is disabled, e.g.
+ * to play nice with testing headers via direct inclusion from the command 
line.
+ */
+struct kvm_page_track_notifier_node {};
+#endif /* CONFIG_KVM_EXTERNAL_WRITE_TRACKING */
 
 #endif
diff --git a/arch/x86/kvm/mmu/page_track.c b/arch/x86/kvm/mmu/page_track.c
index e15329d48f95..b20aad7ac3fe 100644
--- a/arch/x86/kvm/mmu/page_track.c
+++ b/arch/x86/kvm/mmu/page_track.c
@@ -194,6 +194,7 @@ bool kvm_slot_page_track_is_active(struct kvm *kvm,
return !!READ_ONCE(slot->arch.gfn_track[mode][index]);
 }
 
+#ifdef CONFIG_KVM_EXTERNAL_WRITE_TRACKING
 void kvm_page_track_cleanup(struct kvm *kvm)
 {
struct kvm_page_track_notifier_head *head;
@@ -255,14 +256,13 @@ EXPORT_SYMBOL_GPL(kvm_page_track_unregister_notifier);
  * The node should figure out if the written page is the one that node is
  * interested in by itself.
  */
-void kvm_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, const u8 *new,
- int bytes)
+void __kvm_page_track_write(struct kvm *kvm, gpa_t gpa, const u8 *new, int 
bytes)
 {
struct kvm_page_track_notifier_head *head;
struct kvm_page_track_notifier_node *n;
int idx;
 
-   head = >kvm->arch.track_notifier_head;
+   head = >arch.track_notifier_head;
 
if (hlist_empty(>track_notifier_list))
return;
@@ -273,8 +273,6 @@ void kvm_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, 
const u8 *new,
if (n->track_write)
n->track_write(gpa, new, bytes, n);
srcu_read_unlock(>track_srcu, idx);
-
-   kvm_mmu_track_write(vcpu, gpa, new, bytes);
 }
 
 /*
@@ -299,3 +297,5 @@ void kvm_page_track_delete_slot(struct kvm *kvm, struct 
kvm_memory_slot *slot)
n->track_remove_region(slot->base_gfn, slot->npages, 

[Intel-gfx] [PATCH v3 24/28] KVM: x86/mmu: Assert that correct locks are held for page write-tracking

[Sean Christopherson]

When adding/removing gfns to/from write-tracking, assert that mmu_lock
is held for write, and that either slots_lock or kvm->srcu is held.
mmu_lock must be held for write to protect gfn_write_track's refcount,
and SRCU or slots_lock must be held to protect the memslot itself.

Tested-by: Yan Zhao 
Signed-off-by: Sean Christopherson 
---
 arch/x86/kvm/mmu/page_track.c | 17 +++--
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kvm/mmu/page_track.c b/arch/x86/kvm/mmu/page_track.c
index b835ba7f325c..29ae61f1e303 100644
--- a/arch/x86/kvm/mmu/page_track.c
+++ b/arch/x86/kvm/mmu/page_track.c
@@ -12,6 +12,7 @@
  */
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
+#include 
 #include 
 #include 
 
@@ -77,9 +78,6 @@ static void update_gfn_write_track(struct kvm_memory_slot 
*slot, gfn_t gfn,
  * add guest page to the tracking pool so that corresponding access on that
  * page will be intercepted.
  *
- * It should be called under the protection both of mmu-lock and kvm->srcu
- * or kvm->slots_lock.
- *
  * @kvm: the guest instance we are interested in.
  * @slot: the @gfn belongs to.
  * @gfn: the guest page.
@@ -87,6 +85,11 @@ static void update_gfn_write_track(struct kvm_memory_slot 
*slot, gfn_t gfn,
 void kvm_write_track_add_gfn(struct kvm *kvm, struct kvm_memory_slot *slot,
 gfn_t gfn)
 {
+   lockdep_assert_held_write(>mmu_lock);
+
+   lockdep_assert_once(lockdep_is_held(>slots_lock) ||
+   srcu_read_lock_held(>srcu));
+
if (WARN_ON(!kvm_page_track_write_tracking_enabled(kvm)))
return;
 
@@ -107,9 +110,6 @@ EXPORT_SYMBOL_GPL(kvm_write_track_add_gfn);
  * remove the guest page from the tracking pool which stops the interception
  * of corresponding access on that page.
  *
- * It should be called under the protection both of mmu-lock and kvm->srcu
- * or kvm->slots_lock.
- *
  * @kvm: the guest instance we are interested in.
  * @slot: the @gfn belongs to.
  * @gfn: the guest page.
@@ -117,6 +117,11 @@ EXPORT_SYMBOL_GPL(kvm_write_track_add_gfn);
 void kvm_write_track_remove_gfn(struct kvm *kvm,
struct kvm_memory_slot *slot, gfn_t gfn)
 {
+   lockdep_assert_held_write(>mmu_lock);
+
+   lockdep_assert_once(lockdep_is_held(>slots_lock) ||
+   srcu_read_lock_held(>srcu));
+
if (WARN_ON(!kvm_page_track_write_tracking_enabled(kvm)))
return;
 
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 20/28] KVM: x86/mmu: Move KVM-only page-track declarations to internal header

[Sean Christopherson]

Bury the declaration of the page-track helpers that are intended only for
internal KVM use in a "private" header.  In addition to guarding against
unwanted usage of the internal-only helpers, dropping their definitions
avoids exposing other structures that should be KVM-internal, e.g. for
memslots.  This is a baby step toward making kvm_host.h a KVM-internal
header in the very distant future.

Signed-off-by: Sean Christopherson 
---
 arch/x86/include/asm/kvm_page_track.h | 21 ++---
 arch/x86/kvm/mmu/mmu.c|  3 ++-
 arch/x86/kvm/mmu/page_track.c |  8 +--
 arch/x86/kvm/mmu/page_track.h | 33 +++
 arch/x86/kvm/x86.c|  1 +
 5 files changed, 39 insertions(+), 27 deletions(-)
 create mode 100644 arch/x86/kvm/mmu/page_track.h

diff --git a/arch/x86/include/asm/kvm_page_track.h 
b/arch/x86/include/asm/kvm_page_track.h
index 5c348ffdc194..76c0070dfe2a 100644
--- a/arch/x86/include/asm/kvm_page_track.h
+++ b/arch/x86/include/asm/kvm_page_track.h
@@ -2,6 +2,8 @@
 #ifndef _ASM_X86_KVM_PAGE_TRACK_H
 #define _ASM_X86_KVM_PAGE_TRACK_H
 
+#include 
+
 enum kvm_page_track_mode {
KVM_PAGE_TRACK_WRITE,
KVM_PAGE_TRACK_MAX,
@@ -46,26 +48,12 @@ struct kvm_page_track_notifier_node {
struct kvm_page_track_notifier_node *node);
 };
 
-int kvm_page_track_init(struct kvm *kvm);
-void kvm_page_track_cleanup(struct kvm *kvm);
-
-bool kvm_page_track_write_tracking_enabled(struct kvm *kvm);
-int kvm_page_track_write_tracking_alloc(struct kvm_memory_slot *slot);
-
-void kvm_page_track_free_memslot(struct kvm_memory_slot *slot);
-int kvm_page_track_create_memslot(struct kvm *kvm,
- struct kvm_memory_slot *slot,
- unsigned long npages);
-
 void kvm_slot_page_track_add_page(struct kvm *kvm,
  struct kvm_memory_slot *slot, gfn_t gfn,
  enum kvm_page_track_mode mode);
 void kvm_slot_page_track_remove_page(struct kvm *kvm,
 struct kvm_memory_slot *slot, gfn_t gfn,
 enum kvm_page_track_mode mode);
-bool kvm_slot_page_track_is_active(struct kvm *kvm,
-  const struct kvm_memory_slot *slot,
-  gfn_t gfn, enum kvm_page_track_mode mode);
 
 void
 kvm_page_track_register_notifier(struct kvm *kvm,
@@ -73,10 +61,5 @@ kvm_page_track_register_notifier(struct kvm *kvm,
 void
 kvm_page_track_unregister_notifier(struct kvm *kvm,
   struct kvm_page_track_notifier_node *n);
-void kvm_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, const u8 *new,
- int bytes);
-void kvm_page_track_delete_slot(struct kvm *kvm, struct kvm_memory_slot *slot);
-
-bool kvm_page_track_has_external_user(struct kvm *kvm);
 
 #endif
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 3f9030650c3d..0d9fe54ecb01 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -25,6 +25,7 @@
 #include "kvm_cache_regs.h"
 #include "smm.h"
 #include "kvm_emulate.h"
+#include "page_track.h"
 #include "cpuid.h"
 #include "spte.h"
 
@@ -53,7 +54,7 @@
 #include 
 #include 
 #include 
-#include 
+
 #include "trace.h"
 
 extern bool itlb_multihit_kvm_mitigation;
diff --git a/arch/x86/kvm/mmu/page_track.c b/arch/x86/kvm/mmu/page_track.c
index 2a6ab7c455c0..e15329d48f95 100644
--- a/arch/x86/kvm/mmu/page_track.c
+++ b/arch/x86/kvm/mmu/page_track.c
@@ -15,10 +15,9 @@
 #include 
 #include 
 
-#include 
-
 #include "mmu.h"
 #include "mmu_internal.h"
+#include "page_track.h"
 
 bool kvm_page_track_write_tracking_enabled(struct kvm *kvm)
 {
@@ -300,8 +299,3 @@ void kvm_page_track_delete_slot(struct kvm *kvm, struct 
kvm_memory_slot *slot)
n->track_remove_region(slot->base_gfn, slot->npages, n);
srcu_read_unlock(>track_srcu, idx);
 }
-
-bool kvm_page_track_has_external_user(struct kvm *kvm)
-{
-   return hlist_empty(>arch.track_notifier_head.track_notifier_list);
-}
diff --git a/arch/x86/kvm/mmu/page_track.h b/arch/x86/kvm/mmu/page_track.h
new file mode 100644
index ..89712f123ad3
--- /dev/null
+++ b/arch/x86/kvm/mmu/page_track.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __KVM_X86_PAGE_TRACK_H
+#define __KVM_X86_PAGE_TRACK_H
+
+#include 
+
+#include 
+
+int kvm_page_track_init(struct kvm *kvm);
+void kvm_page_track_cleanup(struct kvm *kvm);
+
+bool kvm_page_track_write_tracking_enabled(struct kvm *kvm);
+int kvm_page_track_write_tracking_alloc(struct kvm_memory_slot *slot);
+
+void kvm_page_track_free_memslot(struct kvm_memory_slot *slot);
+int kvm_page_track_create_memslot(struct kvm *kvm,
+ struct kvm_memory_slot *slot,
+ unsigned long npages);
+
+bool kvm_slot_page_track_is_active(struct kvm 

[Intel-gfx] [PATCH v3 23/28] KVM: x86/mmu: Rename page-track APIs to reflect the new reality

[Sean Christopherson]

Rename the page-track APIs to capture that they're all about tracking
writes, now that the facade of supporting multiple modes is gone.

Opportunstically replace "slot" with "gfn" in anticipation of removing
the @slot param from the external APIs.

No functional change intended.

Signed-off-by: Sean Christopherson 
---
 arch/x86/include/asm/kvm_page_track.h |  8 
 arch/x86/kvm/mmu/mmu.c|  8 
 arch/x86/kvm/mmu/page_track.c | 21 +
 arch/x86/kvm/mmu/page_track.h |  4 ++--
 drivers/gpu/drm/i915/gvt/kvmgt.c  |  4 ++--
 5 files changed, 21 insertions(+), 24 deletions(-)

diff --git a/arch/x86/include/asm/kvm_page_track.h 
b/arch/x86/include/asm/kvm_page_track.h
index 9e4ee26d1779..f5c1db36cdb7 100644
--- a/arch/x86/include/asm/kvm_page_track.h
+++ b/arch/x86/include/asm/kvm_page_track.h
@@ -4,10 +4,10 @@
 
 #include 
 
-void kvm_slot_page_track_add_page(struct kvm *kvm,
- struct kvm_memory_slot *slot, gfn_t gfn);
-void kvm_slot_page_track_remove_page(struct kvm *kvm,
-struct kvm_memory_slot *slot, gfn_t gfn);
+void kvm_write_track_add_gfn(struct kvm *kvm,
+struct kvm_memory_slot *slot, gfn_t gfn);
+void kvm_write_track_remove_gfn(struct kvm *kvm, struct kvm_memory_slot *slot,
+   gfn_t gfn);
 
 #ifdef CONFIG_KVM_EXTERNAL_WRITE_TRACKING
 /*
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 8041f5747704..1818c047891f 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -837,7 +837,7 @@ static void account_shadowed(struct kvm *kvm, struct 
kvm_mmu_page *sp)
 
/* the non-leaf shadow pages are keeping readonly. */
if (sp->role.level > PG_LEVEL_4K)
-   return kvm_slot_page_track_add_page(kvm, slot, gfn);
+   return kvm_write_track_add_gfn(kvm, slot, gfn);
 
kvm_mmu_gfn_disallow_lpage(slot, gfn);
 
@@ -883,7 +883,7 @@ static void unaccount_shadowed(struct kvm *kvm, struct 
kvm_mmu_page *sp)
slots = kvm_memslots_for_spte_role(kvm, sp->role);
slot = __gfn_to_memslot(slots, gfn);
if (sp->role.level > PG_LEVEL_4K)
-   return kvm_slot_page_track_remove_page(kvm, slot, gfn);
+   return kvm_write_track_remove_gfn(kvm, slot, gfn);
 
kvm_mmu_gfn_allow_lpage(slot, gfn);
 }
@@ -2823,7 +2823,7 @@ int mmu_try_to_unsync_pages(struct kvm *kvm, const struct 
kvm_memory_slot *slot,
 * track machinery is used to write-protect upper-level shadow pages,
 * i.e. this guards the role.level == 4K assertion below!
 */
-   if (kvm_slot_page_track_is_active(kvm, slot, gfn))
+   if (kvm_gfn_is_write_tracked(kvm, slot, gfn))
return -EPERM;
 
/*
@@ -4224,7 +4224,7 @@ static bool page_fault_handle_page_track(struct kvm_vcpu 
*vcpu,
 * guest is writing the page which is write tracked which can
 * not be fixed by page fault handler.
 */
-   if (kvm_slot_page_track_is_active(vcpu->kvm, fault->slot, fault->gfn))
+   if (kvm_gfn_is_write_tracked(vcpu->kvm, fault->slot, fault->gfn))
return true;
 
return false;
diff --git a/arch/x86/kvm/mmu/page_track.c b/arch/x86/kvm/mmu/page_track.c
index cdc6069b8caf..b835ba7f325c 100644
--- a/arch/x86/kvm/mmu/page_track.c
+++ b/arch/x86/kvm/mmu/page_track.c
@@ -84,10 +84,9 @@ static void update_gfn_write_track(struct kvm_memory_slot 
*slot, gfn_t gfn,
  * @slot: the @gfn belongs to.
  * @gfn: the guest page.
  */
-void kvm_slot_page_track_add_page(struct kvm *kvm,
- struct kvm_memory_slot *slot, gfn_t gfn)
+void kvm_write_track_add_gfn(struct kvm *kvm, struct kvm_memory_slot *slot,
+gfn_t gfn)
 {
-
if (WARN_ON(!kvm_page_track_write_tracking_enabled(kvm)))
return;
 
@@ -102,12 +101,11 @@ void kvm_slot_page_track_add_page(struct kvm *kvm,
if (kvm_mmu_slot_gfn_write_protect(kvm, slot, gfn, PG_LEVEL_4K))
kvm_flush_remote_tlbs(kvm);
 }
-EXPORT_SYMBOL_GPL(kvm_slot_page_track_add_page);
+EXPORT_SYMBOL_GPL(kvm_write_track_add_gfn);
 
 /*
  * remove the guest page from the tracking pool which stops the interception
- * of corresponding access on that page. It is the opposed operation of
- * kvm_slot_page_track_add_page().
+ * of corresponding access on that page.
  *
  * It should be called under the protection both of mmu-lock and kvm->srcu
  * or kvm->slots_lock.
@@ -116,8 +114,8 @@ EXPORT_SYMBOL_GPL(kvm_slot_page_track_add_page);
  * @slot: the @gfn belongs to.
  * @gfn: the guest page.
  */
-void kvm_slot_page_track_remove_page(struct kvm *kvm,
-struct kvm_memory_slot *slot, gfn_t gfn)
+void kvm_write_track_remove_gfn(struct kvm *kvm,
+   struct kvm_memory_slot *slot, gfn_t gfn)
 {
if 

[Intel-gfx] [PATCH v3 17/28] KVM: x86: Add a new page-track hook to handle memslot deletion

[Sean Christopherson]

From: Yan Zhao 

Add a new page-track hook, track_remove_region(), that is called when a
memslot DELETE operation is about to be committed.  The "remove" hook
will be used by KVMGT and will effectively replace the existing
track_flush_slot() altogether now that KVM itself doesn't rely on the
"flush" hook either.

The "flush" hook is flawed as it's invoked before the memslot operation
is guaranteed to succeed, i.e. KVM might ultimately keep the existing
memslot without notifying external page track users, a.k.a. KVMGT.  In
practice, this can't currently happen on x86, but there are no guarantees
that won't change in the future, not to mention that "flush" does a very
poor job of describing what is happening.

Pass in the gfn+nr_pages instead of the slot itself so external users,
i.e. KVMGT, don't need to exposed to KVM internals (memslots).  This will
help set the stage for additional cleanups to the page-track APIs.

Opportunistically align the existing srcu_read_lock_held() usage so that
the new case doesn't stand out like a sore thumb (and not aligning the
new code makes bots unhappy).

Cc: Zhenyu Wang 
Signed-off-by: Yan Zhao 
Co-developed-by: Sean Christopherson 
Signed-off-by: Sean Christopherson 
---
 arch/x86/include/asm/kvm_page_track.h | 12 
 arch/x86/kvm/mmu/page_track.c | 27 +--
 arch/x86/kvm/x86.c|  3 +++
 3 files changed, 40 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/kvm_page_track.h 
b/arch/x86/include/asm/kvm_page_track.h
index f744682648e7..cfd36c22b467 100644
--- a/arch/x86/include/asm/kvm_page_track.h
+++ b/arch/x86/include/asm/kvm_page_track.h
@@ -43,6 +43,17 @@ struct kvm_page_track_notifier_node {
 */
void (*track_flush_slot)(struct kvm *kvm, struct kvm_memory_slot *slot,
struct kvm_page_track_notifier_node *node);
+
+   /*
+* Invoked when a memory region is removed from the guest.  Or in KVM
+* terms, when a memslot is deleted.
+*
+* @gfn:   base gfn of the region being removed
+* @nr_pages:  number of pages in the to-be-removed region
+* @node:  this node
+*/
+   void (*track_remove_region)(gfn_t gfn, unsigned long nr_pages,
+   struct kvm_page_track_notifier_node *node);
 };
 
 int kvm_page_track_init(struct kvm *kvm);
@@ -75,6 +86,7 @@ kvm_page_track_unregister_notifier(struct kvm *kvm,
 void kvm_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, const u8 *new,
  int bytes);
 void kvm_page_track_flush_slot(struct kvm *kvm, struct kvm_memory_slot *slot);
+void kvm_page_track_delete_slot(struct kvm *kvm, struct kvm_memory_slot *slot);
 
 bool kvm_page_track_has_external_user(struct kvm *kvm);
 
diff --git a/arch/x86/kvm/mmu/page_track.c b/arch/x86/kvm/mmu/page_track.c
index e6de9638e560..d971c28be99d 100644
--- a/arch/x86/kvm/mmu/page_track.c
+++ b/arch/x86/kvm/mmu/page_track.c
@@ -270,7 +270,7 @@ void kvm_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, 
const u8 *new,
 
idx = srcu_read_lock(>track_srcu);
hlist_for_each_entry_srcu(n, >track_notifier_list, node,
-   srcu_read_lock_held(>track_srcu))
+ srcu_read_lock_held(>track_srcu))
if (n->track_write)
n->track_write(gpa, new, bytes, n);
srcu_read_unlock(>track_srcu, idx);
@@ -298,12 +298,35 @@ void kvm_page_track_flush_slot(struct kvm *kvm, struct 
kvm_memory_slot *slot)
 
idx = srcu_read_lock(>track_srcu);
hlist_for_each_entry_srcu(n, >track_notifier_list, node,
-   srcu_read_lock_held(>track_srcu))
+ srcu_read_lock_held(>track_srcu))
if (n->track_flush_slot)
n->track_flush_slot(kvm, slot, n);
srcu_read_unlock(>track_srcu, idx);
 }
 
+/*
+ * Notify external page track nodes that a memory region is being removed from
+ * the VM, e.g. so that users can free any associated metadata.
+ */
+void kvm_page_track_delete_slot(struct kvm *kvm, struct kvm_memory_slot *slot)
+{
+   struct kvm_page_track_notifier_head *head;
+   struct kvm_page_track_notifier_node *n;
+   int idx;
+
+   head = >arch.track_notifier_head;
+
+   if (hlist_empty(>track_notifier_list))
+   return;
+
+   idx = srcu_read_lock(>track_srcu);
+   hlist_for_each_entry_srcu(n, >track_notifier_list, node,
+ srcu_read_lock_held(>track_srcu))
+   if (n->track_remove_region)
+   n->track_remove_region(slot->base_gfn, slot->npages, n);
+   srcu_read_unlock(>track_srcu, idx);
+}
+
 bool kvm_page_track_has_external_user(struct kvm *kvm)
 {
return hlist_empty(>arch.track_notifier_head.track_notifier_list);
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 

[Intel-gfx] [PATCH v3 15/28] KVM: x86: Reject memslot MOVE operations if KVMGT is attached

[Sean Christopherson]

Disallow moving memslots if the VM has external page-track users, i.e. if
KVMGT is being used to expose a virtual GPU to the guest, as KVMGT doesn't
correctly handle moving memory regions.

Note, this is potential ABI breakage!  E.g. userspace could move regions
that aren't shadowed by KVMGT without harming the guest.  However, the
only known user of KVMGT is QEMU, and QEMU doesn't move generic memory
regions.  KVM's own support for moving memory regions was also broken for
multiple years (albeit for an edge case, but arguably moving RAM is
itself an edge case), e.g. see commit edd4fa37baa6 ("KVM: x86: Allocate
new rmap and large page tracking when moving memslot").

Reviewed-by: Yan Zhao 
Signed-off-by: Sean Christopherson 
---
 arch/x86/include/asm/kvm_page_track.h | 3 +++
 arch/x86/kvm/mmu/page_track.c | 5 +
 arch/x86/kvm/x86.c| 7 +++
 3 files changed, 15 insertions(+)

diff --git a/arch/x86/include/asm/kvm_page_track.h 
b/arch/x86/include/asm/kvm_page_track.h
index 8c4d216e3b2b..f744682648e7 100644
--- a/arch/x86/include/asm/kvm_page_track.h
+++ b/arch/x86/include/asm/kvm_page_track.h
@@ -75,4 +75,7 @@ kvm_page_track_unregister_notifier(struct kvm *kvm,
 void kvm_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, const u8 *new,
  int bytes);
 void kvm_page_track_flush_slot(struct kvm *kvm, struct kvm_memory_slot *slot);
+
+bool kvm_page_track_has_external_user(struct kvm *kvm);
+
 #endif
diff --git a/arch/x86/kvm/mmu/page_track.c b/arch/x86/kvm/mmu/page_track.c
index 891e5cc52b45..e6de9638e560 100644
--- a/arch/x86/kvm/mmu/page_track.c
+++ b/arch/x86/kvm/mmu/page_track.c
@@ -303,3 +303,8 @@ void kvm_page_track_flush_slot(struct kvm *kvm, struct 
kvm_memory_slot *slot)
n->track_flush_slot(kvm, slot, n);
srcu_read_unlock(>track_srcu, idx);
 }
+
+bool kvm_page_track_has_external_user(struct kvm *kvm)
+{
+   return hlist_empty(>arch.track_notifier_head.track_notifier_list);
+}
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index b2d9c5979df7..c6bbd8ffd8c8 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -12588,6 +12588,13 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
   struct kvm_memory_slot *new,
   enum kvm_mr_change change)
 {
+   /*
+* KVM doesn't support moving memslots when there are external page
+* trackers attached to the VM, i.e. if KVMGT is in use.
+*/
+   if (change == KVM_MR_MOVE && kvm_page_track_has_external_user(kvm))
+   return -EINVAL;
+
if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) {
if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn())
return -EINVAL;
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 19/28] KVM: x86: Remove the unused page-track hook track_flush_slot()

[Sean Christopherson]

From: Yan Zhao 

Remove ->track_remove_slot(), there are no longer any users and it's
unlikely a "flush" hook will ever be the correct API to provide to an
external page-track user.

Cc: Zhenyu Wang 
Suggested-by: Sean Christopherson 
Signed-off-by: Yan Zhao 
Signed-off-by: Sean Christopherson 
---
 arch/x86/include/asm/kvm_page_track.h | 11 ---
 arch/x86/kvm/mmu/mmu.c|  2 --
 arch/x86/kvm/mmu/page_track.c | 26 --
 3 files changed, 39 deletions(-)

diff --git a/arch/x86/include/asm/kvm_page_track.h 
b/arch/x86/include/asm/kvm_page_track.h
index cfd36c22b467..5c348ffdc194 100644
--- a/arch/x86/include/asm/kvm_page_track.h
+++ b/arch/x86/include/asm/kvm_page_track.h
@@ -33,16 +33,6 @@ struct kvm_page_track_notifier_node {
 */
void (*track_write)(gpa_t gpa, const u8 *new, int bytes,
struct kvm_page_track_notifier_node *node);
-   /*
-* It is called when memory slot is being moved or removed
-* users can drop write-protection for the pages in that memory slot
-*
-* @kvm: the kvm where memory slot being moved or removed
-* @slot: the memory slot being moved or removed
-* @node: this node
-*/
-   void (*track_flush_slot)(struct kvm *kvm, struct kvm_memory_slot *slot,
-   struct kvm_page_track_notifier_node *node);
 
/*
 * Invoked when a memory region is removed from the guest.  Or in KVM
@@ -85,7 +75,6 @@ kvm_page_track_unregister_notifier(struct kvm *kvm,
   struct kvm_page_track_notifier_node *n);
 void kvm_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, const u8 *new,
  int bytes);
-void kvm_page_track_flush_slot(struct kvm *kvm, struct kvm_memory_slot *slot);
 void kvm_page_track_delete_slot(struct kvm *kvm, struct kvm_memory_slot *slot);
 
 bool kvm_page_track_has_external_user(struct kvm *kvm);
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index af3e562d3106..3f9030650c3d 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -6734,8 +6734,6 @@ void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
   struct kvm_memory_slot *slot)
 {
kvm_mmu_zap_all_fast(kvm);
-
-   kvm_page_track_flush_slot(kvm, slot);
 }
 
 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
diff --git a/arch/x86/kvm/mmu/page_track.c b/arch/x86/kvm/mmu/page_track.c
index d971c28be99d..2a6ab7c455c0 100644
--- a/arch/x86/kvm/mmu/page_track.c
+++ b/arch/x86/kvm/mmu/page_track.c
@@ -278,32 +278,6 @@ void kvm_page_track_write(struct kvm_vcpu *vcpu, gpa_t 
gpa, const u8 *new,
kvm_mmu_track_write(vcpu, gpa, new, bytes);
 }
 
-/*
- * Notify the node that memory slot is being removed or moved so that it can
- * drop write-protection for the pages in the memory slot.
- *
- * The node should figure out it has any write-protected pages in this slot
- * by itself.
- */
-void kvm_page_track_flush_slot(struct kvm *kvm, struct kvm_memory_slot *slot)
-{
-   struct kvm_page_track_notifier_head *head;
-   struct kvm_page_track_notifier_node *n;
-   int idx;
-
-   head = >arch.track_notifier_head;
-
-   if (hlist_empty(>track_notifier_list))
-   return;
-
-   idx = srcu_read_lock(>track_srcu);
-   hlist_for_each_entry_srcu(n, >track_notifier_list, node,
- srcu_read_lock_held(>track_srcu))
-   if (n->track_flush_slot)
-   n->track_flush_slot(kvm, slot, n);
-   srcu_read_unlock(>track_srcu, idx);
-}
-
 /*
  * Notify external page track nodes that a memory region is being removed from
  * the VM, e.g. so that users can free any associated metadata.
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 18/28] drm/i915/gvt: switch from ->track_flush_slot() to ->track_remove_region()

[Sean Christopherson]

From: Yan Zhao 

Switch from the poorly named and flawed ->track_flush_slot() to the newly
introduced ->track_remove_region().  From KVMGT's perspective, the two
hooks are functionally equivalent, the only difference being that
->track_remove_region() is called only when KVM is 100% certain the
memory region will be removed, i.e. is invoked slightly later in KVM's
memslot modification flow.

Cc: Zhenyu Wang 
Suggested-by: Sean Christopherson 
Signed-off-by: Yan Zhao 
[sean: handle name change, massage changelog, rebase]
Tested-by: Yan Zhao 
Signed-off-by: Sean Christopherson 
---
 drivers/gpu/drm/i915/gvt/kvmgt.c | 21 +
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index c309a77f495f..2e65901270ca 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -108,9 +108,8 @@ struct gvt_dma {
 
 static void kvmgt_page_track_write(gpa_t gpa, const u8 *val, int len,
   struct kvm_page_track_notifier_node *node);
-static void kvmgt_page_track_flush_slot(struct kvm *kvm,
-   struct kvm_memory_slot *slot,
-   struct kvm_page_track_notifier_node *node);
+static void kvmgt_page_track_remove_region(gfn_t gfn, unsigned long nr_pages,
+  struct kvm_page_track_notifier_node 
*node);
 
 static ssize_t intel_vgpu_show_description(struct mdev_type *mtype, char *buf)
 {
@@ -665,7 +664,7 @@ static int intel_vgpu_open_device(struct vfio_device 
*vfio_dev)
return -EEXIST;
 
vgpu->track_node.track_write = kvmgt_page_track_write;
-   vgpu->track_node.track_flush_slot = kvmgt_page_track_flush_slot;
+   vgpu->track_node.track_remove_region = kvmgt_page_track_remove_region;
kvm_get_kvm(vgpu->vfio_device.kvm);
kvm_page_track_register_notifier(vgpu->vfio_device.kvm,
 >track_node);
@@ -1616,22 +1615,20 @@ static void kvmgt_page_track_write(gpa_t gpa, const u8 
*val, int len,
mutex_unlock(>vgpu_lock);
 }
 
-static void kvmgt_page_track_flush_slot(struct kvm *kvm,
-   struct kvm_memory_slot *slot,
-   struct kvm_page_track_notifier_node *node)
+static void kvmgt_page_track_remove_region(gfn_t gfn, unsigned long nr_pages,
+  struct kvm_page_track_notifier_node 
*node)
 {
unsigned long i;
-   gfn_t gfn;
struct intel_vgpu *info =
container_of(node, struct intel_vgpu, track_node);
 
mutex_lock(>vgpu_lock);
 
-   for (i = 0; i < slot->npages; i++) {
-   gfn = slot->base_gfn + i;
-   if (kvmgt_gfn_is_write_protected(info, gfn))
-   kvmgt_protect_table_del(info, gfn);
+   for (i = 0; i < nr_pages; i++) {
+   if (kvmgt_gfn_is_write_protected(info, gfn + i))
+   kvmgt_protect_table_del(info, gfn + i);
}
+
mutex_unlock(>vgpu_lock);
 }
 
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 16/28] drm/i915/gvt: Don't bother removing write-protection on to-be-deleted slot

[Sean Christopherson]

When handling a slot "flush", don't call back into KVM to drop write
protection for gfns in the slot.  Now that KVM rejects attempts to move
memory slots while KVMGT is attached, the only time a slot is "flushed"
is when it's being removed, i.e. the memslot and all its write-tracking
metadata is about to be deleted.

Reviewed-by: Yan Zhao 
Signed-off-by: Sean Christopherson 
---
 drivers/gpu/drm/i915/gvt/kvmgt.c | 8 +---
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index aaebb44c139f..c309a77f495f 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -1629,14 +1629,8 @@ static void kvmgt_page_track_flush_slot(struct kvm *kvm,
 
for (i = 0; i < slot->npages; i++) {
gfn = slot->base_gfn + i;
-   if (kvmgt_gfn_is_write_protected(info, gfn)) {
-   write_lock(>mmu_lock);
-   kvm_slot_page_track_remove_page(kvm, slot, gfn,
-   KVM_PAGE_TRACK_WRITE);
-   write_unlock(>mmu_lock);
-
+   if (kvmgt_gfn_is_write_protected(info, gfn))
kvmgt_protect_table_del(info, gfn);
-   }
}
mutex_unlock(>vgpu_lock);
 }
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 13/28] KVM: x86/mmu: Don't bounce through page-track mechanism for guest PTEs

[Sean Christopherson]

Don't use the generic page-track mechanism to handle writes to guest PTEs
in KVM's MMU.  KVM's MMU needs access to information that should not be
exposed to external page-track users, e.g. KVM needs (for some definitions
of "need") the vCPU to query the current paging mode, whereas external
users, i.e. KVMGT, have no ties to the current vCPU and so should never
need the vCPU.

Moving away from the page-track mechanism will allow dropping use of the
page-track mechanism for KVM's own MMU, and will also allow simplifying
and cleaning up the page-track APIs.

Reviewed-by: Yan Zhao 
Signed-off-by: Sean Christopherson 
---
 arch/x86/include/asm/kvm_host.h |  1 -
 arch/x86/kvm/mmu.h  |  2 ++
 arch/x86/kvm/mmu/mmu.c  | 13 ++---
 arch/x86/kvm/mmu/page_track.c   |  2 ++
 4 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 564a29153cee..113598d3e886 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -1247,7 +1247,6 @@ struct kvm_arch {
 * create an NX huge page (without hanging the guest).
 */
struct list_head possible_nx_huge_pages;
-   struct kvm_page_track_notifier_node mmu_sp_tracker;
struct kvm_page_track_notifier_head track_notifier_head;
/*
 * Protects marking pages unsync during page faults, as TDP MMU page
diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h
index 92d5a1924fc1..253fb2093d5d 100644
--- a/arch/x86/kvm/mmu.h
+++ b/arch/x86/kvm/mmu.h
@@ -121,6 +121,8 @@ void kvm_mmu_unload(struct kvm_vcpu *vcpu);
 void kvm_mmu_free_obsolete_roots(struct kvm_vcpu *vcpu);
 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
 void kvm_mmu_sync_prev_roots(struct kvm_vcpu *vcpu);
+void kvm_mmu_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, const u8 *new,
+int bytes);
 
 static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
 {
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 23a79723031b..af3e562d3106 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -5677,9 +5677,8 @@ static u64 *get_written_sptes(struct kvm_mmu_page *sp, 
gpa_t gpa, int *nspte)
return spte;
 }
 
-static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
- const u8 *new, int bytes,
- struct kvm_page_track_notifier_node *node)
+void kvm_mmu_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, const u8 *new,
+int bytes)
 {
gfn_t gfn = gpa >> PAGE_SHIFT;
struct kvm_mmu_page *sp;
@@ -6186,7 +6185,6 @@ static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
 
 int kvm_mmu_init_vm(struct kvm *kvm)
 {
-   struct kvm_page_track_notifier_node *node = >arch.mmu_sp_tracker;
int r;
 
INIT_LIST_HEAD(>arch.active_mmu_pages);
@@ -6200,9 +6198,6 @@ int kvm_mmu_init_vm(struct kvm *kvm)
return r;
}
 
-   node->track_write = kvm_mmu_pte_write;
-   kvm_page_track_register_notifier(kvm, node);
-
kvm->arch.split_page_header_cache.kmem_cache = mmu_page_header_cache;
kvm->arch.split_page_header_cache.gfp_zero = __GFP_ZERO;
 
@@ -6223,10 +6218,6 @@ static void mmu_free_vm_memory_caches(struct kvm *kvm)
 
 void kvm_mmu_uninit_vm(struct kvm *kvm)
 {
-   struct kvm_page_track_notifier_node *node = >arch.mmu_sp_tracker;
-
-   kvm_page_track_unregister_notifier(kvm, node);
-
if (tdp_mmu_enabled)
kvm_mmu_uninit_tdp_mmu(kvm);
 
diff --git a/arch/x86/kvm/mmu/page_track.c b/arch/x86/kvm/mmu/page_track.c
index 0a2ac438d647..23088c90d2fd 100644
--- a/arch/x86/kvm/mmu/page_track.c
+++ b/arch/x86/kvm/mmu/page_track.c
@@ -274,6 +274,8 @@ void kvm_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, 
const u8 *new,
if (n->track_write)
n->track_write(vcpu, gpa, new, bytes, n);
srcu_read_unlock(>track_srcu, idx);
+
+   kvm_mmu_track_write(vcpu, gpa, new, bytes);
 }
 
 /*
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 14/28] KVM: drm/i915/gvt: Drop @vcpu from KVM's ->track_write() hook

[Sean Christopherson]

Drop @vcpu from KVM's ->track_write() hook provided for external users of
the page-track APIs now that KVM itself doesn't use the page-track
mechanism.

Reviewed-by: Yan Zhao 
Signed-off-by: Sean Christopherson 
---
 arch/x86/include/asm/kvm_page_track.h |  5 ++---
 arch/x86/kvm/mmu/page_track.c |  2 +-
 drivers/gpu/drm/i915/gvt/kvmgt.c  | 10 --
 3 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/arch/x86/include/asm/kvm_page_track.h 
b/arch/x86/include/asm/kvm_page_track.h
index eb186bc57f6a..8c4d216e3b2b 100644
--- a/arch/x86/include/asm/kvm_page_track.h
+++ b/arch/x86/include/asm/kvm_page_track.h
@@ -26,14 +26,13 @@ struct kvm_page_track_notifier_node {
 * It is called when guest is writing the write-tracked page
 * and write emulation is finished at that time.
 *
-* @vcpu: the vcpu where the write access happened.
 * @gpa: the physical address written by guest.
 * @new: the data was written to the address.
 * @bytes: the written length.
 * @node: this node
 */
-   void (*track_write)(struct kvm_vcpu *vcpu, gpa_t gpa, const u8 *new,
-   int bytes, struct kvm_page_track_notifier_node 
*node);
+   void (*track_write)(gpa_t gpa, const u8 *new, int bytes,
+   struct kvm_page_track_notifier_node *node);
/*
 * It is called when memory slot is being moved or removed
 * users can drop write-protection for the pages in that memory slot
diff --git a/arch/x86/kvm/mmu/page_track.c b/arch/x86/kvm/mmu/page_track.c
index 23088c90d2fd..891e5cc52b45 100644
--- a/arch/x86/kvm/mmu/page_track.c
+++ b/arch/x86/kvm/mmu/page_track.c
@@ -272,7 +272,7 @@ void kvm_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, 
const u8 *new,
hlist_for_each_entry_srcu(n, >track_notifier_list, node,
srcu_read_lock_held(>track_srcu))
if (n->track_write)
-   n->track_write(vcpu, gpa, new, bytes, n);
+   n->track_write(gpa, new, bytes, n);
srcu_read_unlock(>track_srcu, idx);
 
kvm_mmu_track_write(vcpu, gpa, new, bytes);
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 0785f9cb2c20..aaebb44c139f 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -106,9 +106,8 @@ struct gvt_dma {
 #define vfio_dev_to_vgpu(vfio_dev) \
container_of((vfio_dev), struct intel_vgpu, vfio_device)
 
-static void kvmgt_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa,
-   const u8 *val, int len,
-   struct kvm_page_track_notifier_node *node);
+static void kvmgt_page_track_write(gpa_t gpa, const u8 *val, int len,
+  struct kvm_page_track_notifier_node *node);
 static void kvmgt_page_track_flush_slot(struct kvm *kvm,
struct kvm_memory_slot *slot,
struct kvm_page_track_notifier_node *node);
@@ -1602,9 +1601,8 @@ int intel_gvt_page_track_remove(struct intel_vgpu *info, 
u64 gfn)
return 0;
 }
 
-static void kvmgt_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa,
-   const u8 *val, int len,
-   struct kvm_page_track_notifier_node *node)
+static void kvmgt_page_track_write(gpa_t gpa, const u8 *val, int len,
+  struct kvm_page_track_notifier_node *node)
 {
struct intel_vgpu *info =
container_of(node, struct intel_vgpu, track_node);
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 09/28] drm/i915/gvt: Drop unused helper intel_vgpu_reset_gtt()

[Sean Christopherson]

Drop intel_vgpu_reset_gtt() as it no longer has any callers.  In addition
to eliminating dead code, this eliminates the last possible scenario where
__kvmgt_protect_table_find() can be reached without holding vgpu_lock.
Requiring vgpu_lock to be held when calling __kvmgt_protect_table_find()
will allow a protecting the gfn hash with vgpu_lock without too much fuss.

No functional change intended.

Fixes: ba25d977571e ("drm/i915/gvt: Do not destroy ppgtt_mm during vGPU 
D3->D0.")
Reviewed-by: Yan Zhao 
Signed-off-by: Sean Christopherson 
---
 drivers/gpu/drm/i915/gvt/gtt.c | 18 --
 drivers/gpu/drm/i915/gvt/gtt.h |  1 -
 2 files changed, 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index f505be9e647a..c3c623b929ce 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -2817,24 +2817,6 @@ void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool 
invalidate_old)
ggtt_invalidate(gvt->gt);
 }
 
-/**
- * intel_vgpu_reset_gtt - reset the all GTT related status
- * @vgpu: a vGPU
- *
- * This function is called from vfio core to reset reset all
- * GTT related status, including GGTT, PPGTT, scratch page.
- *
- */
-void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu)
-{
-   /* Shadow pages are only created when there is no page
-* table tracking data, so remove page tracking data after
-* removing the shadow pages.
-*/
-   intel_vgpu_destroy_all_ppgtt_mm(vgpu);
-   intel_vgpu_reset_ggtt(vgpu, true);
-}
-
 /**
  * intel_gvt_restore_ggtt - restore all vGPU's ggtt entries
  * @gvt: intel gvt device
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index a3b0f59ec8bd..4cb183e06e95 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -224,7 +224,6 @@ void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool 
invalidate_old);
 void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu);
 
 int intel_gvt_init_gtt(struct intel_gvt *gvt);
-void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu);
 void intel_gvt_clean_gtt(struct intel_gvt *gvt);
 
 struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu,
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 12/28] KVM: x86/mmu: Don't rely on page-track mechanism to flush on memslot change

[Sean Christopherson]

Call kvm_mmu_zap_all_fast() directly when flushing a memslot instead of
bouncing through the page-track mechanism.  KVM (unfortunately) needs to
zap and flush all page tables on memslot DELETE/MOVE irrespective of
whether KVM is shadowing guest page tables.

This will allow changing KVM to register a page-track notifier on the
first shadow root allocation, and will also allow deleting the misguided
kvm_page_track_flush_slot() hook itself once KVM-GT also moves to a
different method for reacting to memslot changes.

No functional change intended.

Cc: Yan Zhao 
Link: https://lore.kernel.org/r/20221110014821.1548347-2-sea...@google.com
Signed-off-by: Sean Christopherson 
---
 arch/x86/kvm/mmu/mmu.c | 10 ++
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 2e4476d38377..23a79723031b 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -6184,13 +6184,6 @@ static bool kvm_has_zapped_obsolete_pages(struct kvm 
*kvm)
return unlikely(!list_empty_careful(>arch.zapped_obsolete_pages));
 }
 
-static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
-   struct kvm_memory_slot *slot,
-   struct kvm_page_track_notifier_node *node)
-{
-   kvm_mmu_zap_all_fast(kvm);
-}
-
 int kvm_mmu_init_vm(struct kvm *kvm)
 {
struct kvm_page_track_notifier_node *node = >arch.mmu_sp_tracker;
@@ -6208,7 +6201,6 @@ int kvm_mmu_init_vm(struct kvm *kvm)
}
 
node->track_write = kvm_mmu_pte_write;
-   node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
kvm_page_track_register_notifier(kvm, node);
 
kvm->arch.split_page_header_cache.kmem_cache = mmu_page_header_cache;
@@ -6750,6 +6742,8 @@ void kvm_arch_flush_shadow_all(struct kvm *kvm)
 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
   struct kvm_memory_slot *slot)
 {
+   kvm_mmu_zap_all_fast(kvm);
+
kvm_page_track_flush_slot(kvm, slot);
 }
 
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 10/28] drm/i915/gvt: Protect gfn hash table with vgpu_lock

[Sean Christopherson]

Use vgpu_lock instead of KVM's mmu_lock to protect accesses to the hash
table used to track which gfns are write-protected when shadowing the
guest's GTT, and hoist the acquisition of vgpu_lock from
intel_vgpu_page_track_handler() out to its sole caller,
kvmgt_page_track_write().

This fixes a bug where kvmgt_page_track_write(), which doesn't hold
kvm->mmu_lock, could race with intel_gvt_page_track_remove() and trigger
a use-after-free.

Fixing kvmgt_page_track_write() by taking kvm->mmu_lock is not an option
as mmu_lock is a r/w spinlock, and intel_vgpu_page_track_handler() might
sleep when acquiring vgpu->cache_lock deep down the callstack:

  intel_vgpu_page_track_handler()
  |
  |->  page_track->handler / ppgtt_write_protection_handler()
   |
   |-> ppgtt_handle_guest_write_page_table_bytes()
   |
   |->  ppgtt_handle_guest_write_page_table()
|
|-> ppgtt_handle_guest_entry_removal()
|
|-> ppgtt_invalidate_pte()
|
|-> intel_gvt_dma_unmap_guest_page()
|
|-> mutex_lock(>cache_lock);

Reviewed-by: Yan Zhao 
Signed-off-by: Sean Christopherson 
---
 drivers/gpu/drm/i915/gvt/kvmgt.c  | 55 +++
 drivers/gpu/drm/i915/gvt/page_track.c | 10 +
 2 files changed, 33 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 117bac85ac2c..0785f9cb2c20 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -351,6 +351,8 @@ __kvmgt_protect_table_find(struct intel_vgpu *info, gfn_t 
gfn)
 {
struct kvmgt_pgfn *p, *res = NULL;
 
+   lockdep_assert_held(>vgpu_lock);
+
hash_for_each_possible(info->ptable, p, hnode, gfn) {
if (gfn == p->gfn) {
res = p;
@@ -1552,6 +1554,9 @@ int intel_gvt_page_track_add(struct intel_vgpu *info, u64 
gfn)
if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, info->status))
return -ESRCH;
 
+   if (kvmgt_gfn_is_write_protected(info, gfn))
+   return 0;
+
idx = srcu_read_lock(>srcu);
slot = gfn_to_memslot(kvm, gfn);
if (!slot) {
@@ -1560,16 +1565,12 @@ int intel_gvt_page_track_add(struct intel_vgpu *info, 
u64 gfn)
}
 
write_lock(>mmu_lock);
-
-   if (kvmgt_gfn_is_write_protected(info, gfn))
-   goto out;
-
kvm_slot_page_track_add_page(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE);
+   write_unlock(>mmu_lock);
+
+   srcu_read_unlock(>srcu, idx);
+
kvmgt_protect_table_add(info, gfn);
-
-out:
-   write_unlock(>mmu_lock);
-   srcu_read_unlock(>srcu, idx);
return 0;
 }
 
@@ -1582,24 +1583,22 @@ int intel_gvt_page_track_remove(struct intel_vgpu 
*info, u64 gfn)
if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, info->status))
return -ESRCH;
 
-   idx = srcu_read_lock(>srcu);
-   slot = gfn_to_memslot(kvm, gfn);
-   if (!slot) {
-   srcu_read_unlock(>srcu, idx);
-   return -EINVAL;
-   }
-
-   write_lock(>mmu_lock);
-
if (!kvmgt_gfn_is_write_protected(info, gfn))
-   goto out;
+   return 0;
 
+   idx = srcu_read_lock(>srcu);
+   slot = gfn_to_memslot(kvm, gfn);
+   if (!slot) {
+   srcu_read_unlock(>srcu, idx);
+   return -EINVAL;
+   }
+
+   write_lock(>mmu_lock);
kvm_slot_page_track_remove_page(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE);
+   write_unlock(>mmu_lock);
+   srcu_read_unlock(>srcu, idx);
+
kvmgt_protect_table_del(info, gfn);
-
-out:
-   write_unlock(>mmu_lock);
-   srcu_read_unlock(>srcu, idx);
return 0;
 }
 
@@ -1610,9 +1609,13 @@ static void kvmgt_page_track_write(struct kvm_vcpu 
*vcpu, gpa_t gpa,
struct intel_vgpu *info =
container_of(node, struct intel_vgpu, track_node);
 
+   mutex_lock(>vgpu_lock);
+
if (kvmgt_gfn_is_write_protected(info, gpa_to_gfn(gpa)))
intel_vgpu_page_track_handler(info, gpa,
 (void *)val, len);
+
+   mutex_unlock(>vgpu_lock);
 }
 
 static void kvmgt_page_track_flush_slot(struct kvm *kvm,
@@ -1624,16 +1627,20 @@ static void kvmgt_page_track_flush_slot(struct kvm *kvm,
struct intel_vgpu *info =
container_of(node, struct intel_vgpu, track_node);
 
-   write_lock(>mmu_lock);
+   mutex_lock(>vgpu_lock);
+
for (i = 0; i < slot->npages; i++) {
gfn = slot->base_gfn + i;
if (kvmgt_gfn_is_write_protected(info, gfn)) {
+   write_lock(>mmu_lock);
kvm_slot_page_track_remove_page(kvm, slot, gfn,
KVM_PAGE_TRACK_WRITE);
+   

[Intel-gfx] [PATCH v3 11/28] KVM: x86/mmu: Move kvm_arch_flush_shadow_{all, memslot}() to mmu.c

[Sean Christopherson]

Move x86's implementation of kvm_arch_flush_shadow_{all,memslot}() into
mmu.c, and make kvm_mmu_zap_all() static as it was globally visible only
for kvm_arch_flush_shadow_all().  This will allow refactoring
kvm_arch_flush_shadow_memslot() to call kvm_mmu_zap_all() directly without
having to expose kvm_mmu_zap_all_fast() outside of mmu.c.  Keeping
everything in mmu.c will also likely simplify supporting TDX, which
intends to do zap only relevant SPTEs on memslot updates.

No functional change intended.

Suggested-by: Yan Zhao 
Signed-off-by: Sean Christopherson 
---
 arch/x86/include/asm/kvm_host.h |  1 -
 arch/x86/kvm/mmu/mmu.c  | 13 -
 arch/x86/kvm/x86.c  | 11 ---
 3 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index fb9d1f2d6136..564a29153cee 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -1832,7 +1832,6 @@ void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
   const struct kvm_memory_slot *memslot);
 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
   const struct kvm_memory_slot *memslot);
-void kvm_mmu_zap_all(struct kvm *kvm);
 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen);
 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages);
 
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index c8961f45e3b1..2e4476d38377 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -6717,7 +6717,7 @@ void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
 */
 }
 
-void kvm_mmu_zap_all(struct kvm *kvm)
+static void kvm_mmu_zap_all(struct kvm *kvm)
 {
struct kvm_mmu_page *sp, *node;
LIST_HEAD(invalid_list);
@@ -6742,6 +6742,17 @@ void kvm_mmu_zap_all(struct kvm *kvm)
write_unlock(>mmu_lock);
 }
 
+void kvm_arch_flush_shadow_all(struct kvm *kvm)
+{
+   kvm_mmu_zap_all(kvm);
+}
+
+void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
+  struct kvm_memory_slot *slot)
+{
+   kvm_page_track_flush_slot(kvm, slot);
+}
+
 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
 {
WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 523c39a03c00..b2d9c5979df7 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -12758,17 +12758,6 @@ void kvm_arch_commit_memory_region(struct kvm *kvm,
kvm_arch_free_memslot(kvm, old);
 }
 
-void kvm_arch_flush_shadow_all(struct kvm *kvm)
-{
-   kvm_mmu_zap_all(kvm);
-}
-
-void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
-  struct kvm_memory_slot *slot)
-{
-   kvm_page_track_flush_slot(kvm, slot);
-}
-
 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
 {
return (is_guest_mode(vcpu) &&
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 07/28] drm/i915/gvt: Don't rely on KVM's gfn_to_pfn() to query possible 2M GTT

[Sean Christopherson]

Now that gvt_pin_guest_page() explicitly verifies the pinned PFN is a
transparent hugepage page, don't use KVM's gfn_to_pfn() to pre-check if a
2MiB GTT entry is possible and instead just try to map the GFN with a 2MiB
entry.  Using KVM to query pfn that is ultimately managed through VFIO is
odd, and KVM's gfn_to_pfn() is not intended for non-KVM consumption; it's
exported only because of KVM vendor modules (x86 and PPC).

Open code the check on 2MiB support instead of keeping
is_2MB_gtt_possible() around for a single line of code.

Move the call to intel_gvt_dma_map_guest_page() for a 4KiB entry into its
case statement, i.e. fork the common path into the 4KiB and 2MiB "direct"
shadow paths.  Keeping the call in the "common" path is arguably more in
the spirit of "one change per patch", but retaining the local "page_size"
variable is silly, i.e. the call site will be changed either way, and
jumping around the no-longer-common code is more subtle and rather odd,
i.e. would just need to be immediately cleaned up.

Drop the error message from gvt_pin_guest_page() when KVMGT attempts to
shadow a 2MiB guest page that isn't backed by a compatible hugepage in the
host.  Dropping the pre-check on a THP makes it much more likely that the
"error" will be encountered in normal operation.

Signed-off-by: Sean Christopherson 
---
 drivers/gpu/drm/i915/gvt/gtt.c   | 49 ++--
 drivers/gpu/drm/i915/gvt/kvmgt.c |  1 -
 2 files changed, 8 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 61e38acee2d5..f505be9e647a 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1145,36 +1145,6 @@ static inline void ppgtt_generate_shadow_entry(struct 
intel_gvt_gtt_entry *se,
ops->set_pfn(se, s->shadow_page.mfn);
 }
 
-/*
- * Check if can do 2M page
- * @vgpu: target vgpu
- * @entry: target pfn's gtt entry
- *
- * Return 1 if 2MB huge gtt shadowing is possible, 0 if miscondition,
- * negative if found err.
- */
-static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
-   struct intel_gvt_gtt_entry *entry)
-{
-   const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
-   kvm_pfn_t pfn;
-   int ret;
-
-   if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M))
-   return 0;
-
-   pfn = gfn_to_pfn(vgpu->vfio_device.kvm, ops->get_pfn(entry));
-   if (is_error_noslot_pfn(pfn))
-   return -EINVAL;
-
-   if (!pfn_valid(pfn))
-   return -EINVAL;
-
-   ret = PageTransHuge(pfn_to_page(pfn));
-   kvm_release_pfn_clean(pfn);
-   return ret;
-}
-
 static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
struct intel_gvt_gtt_entry *se)
@@ -1268,7 +1238,7 @@ static int ppgtt_populate_shadow_entry(struct intel_vgpu 
*vgpu,
 {
const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
struct intel_gvt_gtt_entry se = *ge;
-   unsigned long gfn, page_size = PAGE_SIZE;
+   unsigned long gfn;
dma_addr_t dma_addr;
int ret;
 
@@ -1283,6 +1253,9 @@ static int ppgtt_populate_shadow_entry(struct intel_vgpu 
*vgpu,
switch (ge->type) {
case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
gvt_vdbg_mm("shadow 4K gtt entry\n");
+   ret = intel_gvt_dma_map_guest_page(vgpu, gfn, PAGE_SIZE, 
_addr);
+   if (ret)
+   return -ENXIO;
break;
case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
gvt_vdbg_mm("shadow 64K gtt entry\n");
@@ -1294,12 +1267,10 @@ static int ppgtt_populate_shadow_entry(struct 
intel_vgpu *vgpu,
return split_64KB_gtt_entry(vgpu, spt, index, );
case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
gvt_vdbg_mm("shadow 2M gtt entry\n");
-   ret = is_2MB_gtt_possible(vgpu, ge);
-   if (ret == 0)
+   if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M) 
||
+   intel_gvt_dma_map_guest_page(vgpu, gfn,
+I915_GTT_PAGE_SIZE_2M, 
_addr))
return split_2MB_gtt_entry(vgpu, spt, index, );
-   else if (ret < 0)
-   return ret;
-   page_size = I915_GTT_PAGE_SIZE_2M;
break;
case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
gvt_vgpu_err("GVT doesn't support 1GB entry\n");
@@ -1309,11 +1280,7 @@ static int ppgtt_populate_shadow_entry(struct intel_vgpu 
*vgpu,
return -EINVAL;
}
 
-   /* direct shadow */
-   ret = intel_gvt_dma_map_guest_page(vgpu, gfn, page_size, _addr);
-   if (ret)
-   return -ENXIO;
-
+   /* Successfully shadowed a 4K or 2M page (without splitting). */
pte_ops->set_pfn(, dma_addr >> PAGE_SHIFT);
ppgtt_set_shadow_entry(spt, , index);

[Intel-gfx] [PATCH v3 08/28] drm/i915/gvt: Use an "unsigned long" to iterate over memslot gfns

[Sean Christopherson]

Use an "unsigned long" instead of an "int" when iterating over the gfns
in a memslot.  The number of pages in the memslot is tracked as an
"unsigned long", e.g. KVMGT could theoretically break if a KVM memslot
larger than 16TiB were deleted (2^32 * 4KiB).

Reviewed-by: Yan Zhao 
Signed-off-by: Sean Christopherson 
---
 drivers/gpu/drm/i915/gvt/kvmgt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 92ceefe1e6fb..117bac85ac2c 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -1619,7 +1619,7 @@ static void kvmgt_page_track_flush_slot(struct kvm *kvm,
struct kvm_memory_slot *slot,
struct kvm_page_track_notifier_node *node)
 {
-   int i;
+   unsigned long i;
gfn_t gfn;
struct intel_vgpu *info =
container_of(node, struct intel_vgpu, track_node);
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 06/28] drm/i915/gvt: Error out on an attempt to shadowing an unknown GTT entry type

[Sean Christopherson]

Bail from ppgtt_populate_shadow_entry() if an unexpected GTT entry type
is encountered instead of subtly falling through to the common "direct
shadow" path.  Eliminating the default/error path's reliance on the common
handling will allow hoisting intel_gvt_dma_map_guest_page() into the case
statements so that the 2MiB case can try intel_gvt_dma_map_guest_page()
and fallback to splitting the entry on failure.

Signed-off-by: Sean Christopherson 
---
 drivers/gpu/drm/i915/gvt/gtt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 2aed31b497c9..61e38acee2d5 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1306,6 +1306,7 @@ static int ppgtt_populate_shadow_entry(struct intel_vgpu 
*vgpu,
return -EINVAL;
default:
GEM_BUG_ON(1);
+   return -EINVAL;
}
 
/* direct shadow */
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 05/28] drm/i915/gvt: Explicitly check that vGPU is attached before shadowing

[Sean Christopherson]

Move the check that a vGPU is attacked from is_2MB_gtt_possible() to its
sole caller, ppgtt_populate_shadow_entry().  All of the paths in
ppgtt_populate_shadow_entry() eventually check for attachment by way of
intel_gvt_dma_map_guest_page(), but explicitly checking can avoid
unnecessary work and will make it more obvious that a future cleanup of
is_2MB_gtt_possible() isn't introducing a bug.

Signed-off-by: Sean Christopherson 
---
 drivers/gpu/drm/i915/gvt/gtt.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 5426a27c1b71..2aed31b497c9 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1163,8 +1163,6 @@ static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M))
return 0;
 
-   if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
-   return -EINVAL;
pfn = gfn_to_pfn(vgpu->vfio_device.kvm, ops->get_pfn(entry));
if (is_error_noslot_pfn(pfn))
return -EINVAL;
@@ -1277,6 +1275,9 @@ static int ppgtt_populate_shadow_entry(struct intel_vgpu 
*vgpu,
if (!pte_ops->test_present(ge))
return 0;
 
+   if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
+   return -EINVAL;
+
gfn = pte_ops->get_pfn(ge);
 
switch (ge->type) {
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 04/28] drm/i915/gvt: Put the page reference obtained by KVM's gfn_to_pfn()

[Sean Christopherson]

Put the struct page reference acquired by gfn_to_pfn(), KVM's API is that
the caller is ultimately responsible for dropping any reference.

Note, kvm_release_pfn_clean() ensures the pfn is actually a refcounted
struct page before trying to put any references.

Fixes: b901b252b6cf ("drm/i915/gvt: Add 2M huge gtt support")
Reviewed-by: Yan Zhao 
Signed-off-by: Sean Christopherson 
---
 drivers/gpu/drm/i915/gvt/gtt.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index f30922c55a0c..5426a27c1b71 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1158,6 +1158,7 @@ static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
 {
const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
kvm_pfn_t pfn;
+   int ret;
 
if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M))
return 0;
@@ -1171,7 +1172,9 @@ static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
if (!pfn_valid(pfn))
return -EINVAL;
 
-   return PageTransHuge(pfn_to_page(pfn));
+   ret = PageTransHuge(pfn_to_page(pfn));
+   kvm_release_pfn_clean(pfn);
+   return ret;
 }
 
 static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 03/28] drm/i915/gvt: Verify hugepages are contiguous in physical address space

[Sean Christopherson]

When shadowing a GTT entry with a 2M page, verify that the pfns are
contiguous, not just that the struct page pointers are contiguous.  The
memory map is virtual contiguous if "CONFIG_FLATMEM=y ||
CONFIG_SPARSEMEM_VMEMMAP=y", but not for "CONFIG_SPARSEMEM=y &&
CONFIG_SPARSEMEM_VMEMMAP=n", so theoretically KVMGT could encounter struct
pages that are virtually contiguous, but not physically contiguous.

In practice, this flaw is likely a non-issue as it would cause functional
problems iff a section isn't 2M aligned _and_ is directly adjacent to
another section with discontiguous pfns.

Signed-off-by: Sean Christopherson 
---
 drivers/gpu/drm/i915/gvt/kvmgt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index de675d799c7d..429f0f993a13 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -161,7 +161,7 @@ static int gvt_pin_guest_page(struct intel_vgpu *vgpu, 
unsigned long gfn,
 
if (npage == 0)
base_page = cur_page;
-   else if (base_page + npage != cur_page) {
+   else if (page_to_pfn(base_page) + npage != 
page_to_pfn(cur_page)) {
gvt_vgpu_err("The pages are not continuous\n");
ret = -EINVAL;
npage++;
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 02/28] drm/i915/gvt: remove interface intel_gvt_is_valid_gfn

[Sean Christopherson]

From: Yan Zhao 

Currently intel_gvt_is_valid_gfn() is called in two places:
(1) shadowing guest GGTT entry
(2) shadowing guest PPGTT leaf entry,
which was introduced in commit cc753fbe1ac4
("drm/i915/gvt: validate gfn before set shadow page entry").

However, now it's not necessary to call this interface any more, because
a. GGTT partial write issue has been fixed by
   commit bc0686ff5fad
   ("drm/i915/gvt: support inconsecutive partial gtt entry write")
   commit 510fe10b6180
   ("drm/i915/gvt: fix a bug of partially write ggtt enties")
b. PPGTT resides in normal guest RAM and we only treat 8-byte writes
   as valid page table writes. Any invalid GPA found is regarded as
   an error, either due to guest misbehavior/attack or bug in host
   shadow code.
   So,rather than do GFN pre-checking and replace invalid GFNs with
   scratch GFN and continue silently, just remove the pre-checking and
   abort PPGTT shadowing on error detected.
c. GFN validity check is still performed in
   intel_gvt_dma_map_guest_page() --> gvt_pin_guest_page().
   It's more desirable to call VFIO interface to do both validity check
   and mapping.
   Calling intel_gvt_is_valid_gfn() to do GFN validity check from KVM side
   while later mapping the GFN through VFIO interface is unnecessarily
   fragile and confusing for unaware readers.

Signed-off-by: Yan Zhao 
[sean: remove now-unused local variables]
Signed-off-by: Sean Christopherson 
---
 drivers/gpu/drm/i915/gvt/gtt.c | 36 +-
 1 file changed, 1 insertion(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 58b9b316ae46..f30922c55a0c 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -49,22 +49,6 @@
 static bool enable_out_of_sync = false;
 static int preallocated_oos_pages = 8192;
 
-static bool intel_gvt_is_valid_gfn(struct intel_vgpu *vgpu, unsigned long gfn)
-{
-   struct kvm *kvm = vgpu->vfio_device.kvm;
-   int idx;
-   bool ret;
-
-   if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
-   return false;
-
-   idx = srcu_read_lock(>srcu);
-   ret = kvm_is_visible_gfn(kvm, gfn);
-   srcu_read_unlock(>srcu, idx);
-
-   return ret;
-}
-
 /*
  * validate a gm address and related range size,
  * translate it to host gm address
@@ -1333,11 +1317,9 @@ static int ppgtt_populate_shadow_entry(struct intel_vgpu 
*vgpu,
 static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt)
 {
struct intel_vgpu *vgpu = spt->vgpu;
-   struct intel_gvt *gvt = vgpu->gvt;
-   const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
struct intel_vgpu_ppgtt_spt *s;
struct intel_gvt_gtt_entry se, ge;
-   unsigned long gfn, i;
+   unsigned long i;
int ret;
 
trace_spt_change(spt->vgpu->id, "born", spt,
@@ -1354,13 +1336,6 @@ static int ppgtt_populate_spt(struct 
intel_vgpu_ppgtt_spt *spt)
ppgtt_generate_shadow_entry(, s, );
ppgtt_set_shadow_entry(spt, , i);
} else {
-   gfn = ops->get_pfn();
-   if (!intel_gvt_is_valid_gfn(vgpu, gfn)) {
-   ops->set_pfn(, gvt->gtt.scratch_mfn);
-   ppgtt_set_shadow_entry(spt, , i);
-   continue;
-   }
-
ret = ppgtt_populate_shadow_entry(vgpu, spt, i, );
if (ret)
goto fail;
@@ -2335,14 +2310,6 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu 
*vgpu, unsigned int off,
m.val64 = e.val64;
m.type = e.type;
 
-   /* one PTE update may be issued in multiple writes and the
-* first write may not construct a valid gfn
-*/
-   if (!intel_gvt_is_valid_gfn(vgpu, gfn)) {
-   ops->set_pfn(, gvt->gtt.scratch_mfn);
-   goto out;
-   }
-
ret = intel_gvt_dma_map_guest_page(vgpu, gfn, PAGE_SIZE,
   _addr);
if (ret) {
@@ -2359,7 +2326,6 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu 
*vgpu, unsigned int off,
ops->clear_present();
}
 
-out:
ggtt_set_guest_entry(ggtt_mm, , g_gtt_index);
 
ggtt_get_host_entry(ggtt_mm, , g_gtt_index);
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 01/28] drm/i915/gvt: Verify pfn is "valid" before dereferencing "struct page"

[Sean Christopherson]

Check that the pfn found by gfn_to_pfn() is actually backed by "struct
page" memory prior to retrieving and dereferencing the page.  KVM
supports backing guest memory with VM_PFNMAP, VM_IO, etc., and so
there is no guarantee the pfn returned by gfn_to_pfn() has an associated
"struct page".

Fixes: b901b252b6cf ("drm/i915/gvt: Add 2M huge gtt support")
Reviewed-by: Yan Zhao 
Signed-off-by: Sean Christopherson 
---
 drivers/gpu/drm/i915/gvt/gtt.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 4ec85308379a..58b9b316ae46 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1183,6 +1183,10 @@ static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
pfn = gfn_to_pfn(vgpu->vfio_device.kvm, ops->get_pfn(entry));
if (is_error_noslot_pfn(pfn))
return -EINVAL;
+
+   if (!pfn_valid(pfn))
+   return -EINVAL;
+
return PageTransHuge(pfn_to_page(pfn));
 }
 
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] [PATCH v3 00/28] drm/i915/gvt: KVM: KVMGT fixes and page-track cleanups

[Sean Christopherson]

Fix a variety of found-by-inspection bugs in KVMGT, and overhaul KVM's
page-track APIs to provide a leaner and cleaner interface.  The motivation
for this series is to (significantly) reduce the number of KVM APIs that
KVMGT uses, with a long-term goal of making all kvm_host.h headers
KVM-internal.

As always for this series, the KVMGT changes are compile tested only.

Based on "git://git.kernel.org/pub/scm/virt/kvm/kvm.git tags/kvm-6.4-1".

v3:
 - Collect reviewed/tested tags (I apologize if I missed any, I manually
   gathered them this time due to a goof in my workflow). [Yan]
 - Drop check on max KVM paging size from KVMGT. [Yan]
 - Drop the explicit change on THP pages, and instead validate that the
   pfns (not struct page pointers) are contiguous. [Yan]
 - Fix buggy intel_gvt_dma_map_guest_page() usage by eliminating a helper
   for shadowing 2MiB GTT entries. [Yan]
 - Move kvm_arch_flush_shadow_{all,memslot}() to mmu.c instead of exposing
   kvm_mmu_zap_all_fast() outside of mmu.c. [Yan]
 - Fix an alignment goof in hlist_for_each_entry_srcu() usage. [Yan]
 - Wrap full definition of external page track structures with
   CONFIG_KVM_EXTERNAL_WRITE_TRACKING. [Yan]

v2:
 - https://lore.kernel.org/all/20230311002258.852397-1-sea...@google.com
 - Reuse vgpu_lock to protect gfn hash instead of introducing a new (and
   buggy) mutext. [Yan]
 - Remove a spurious return from kvm_page_track_init(). [Yan]
 - Take @kvm directly in the inner __kvm_page_track_write(). [Yan]
 - Delete the gfn sanity check that relies on kvm_is_visible_gfn() instead
   of providing a dedicated interface. [Yan]

v1: https://lore.kernel.org/lkml/20221223005739.1295925-1-sea...@google.com

Sean Christopherson (24):
  drm/i915/gvt: Verify pfn is "valid" before dereferencing "struct page"
  drm/i915/gvt: Verify hugepages are contiguous in physical address
space
  drm/i915/gvt: Put the page reference obtained by KVM's gfn_to_pfn()
  drm/i915/gvt: Explicitly check that vGPU is attached before shadowing
  drm/i915/gvt: Error out on an attempt to shadowing an unknown GTT
entry type
  drm/i915/gvt: Don't rely on KVM's gfn_to_pfn() to query possible 2M
GTT
  drm/i915/gvt: Use an "unsigned long" to iterate over memslot gfns
  drm/i915/gvt: Drop unused helper intel_vgpu_reset_gtt()
  drm/i915/gvt: Protect gfn hash table with vgpu_lock
  KVM: x86/mmu: Move kvm_arch_flush_shadow_{all,memslot}() to mmu.c
  KVM: x86/mmu: Don't rely on page-track mechanism to flush on memslot
change
  KVM: x86/mmu: Don't bounce through page-track mechanism for guest PTEs
  KVM: drm/i915/gvt: Drop @vcpu from KVM's ->track_write() hook
  KVM: x86: Reject memslot MOVE operations if KVMGT is attached
  drm/i915/gvt: Don't bother removing write-protection on to-be-deleted
slot
  KVM: x86/mmu: Move KVM-only page-track declarations to internal header
  KVM: x86/mmu: Use page-track notifiers iff there are external users
  KVM: x86/mmu: Drop infrastructure for multiple page-track modes
  KVM: x86/mmu: Rename page-track APIs to reflect the new reality
  KVM: x86/mmu: Assert that correct locks are held for page
write-tracking
  KVM: x86/mmu: Bug the VM if write-tracking is used but not enabled
  KVM: x86/mmu: Drop @slot param from exported/external page-track APIs
  KVM: x86/mmu: Handle KVM bookkeeping in page-track APIs, not callers
  drm/i915/gvt: Drop final dependencies on KVM internal details

Yan Zhao (4):
  drm/i915/gvt: remove interface intel_gvt_is_valid_gfn
  KVM: x86: Add a new page-track hook to handle memslot deletion
  drm/i915/gvt: switch from ->track_flush_slot() to
->track_remove_region()
  KVM: x86: Remove the unused page-track hook track_flush_slot()

 arch/x86/include/asm/kvm_host.h   |  16 +-
 arch/x86/include/asm/kvm_page_track.h |  73 +++-
 arch/x86/kvm/mmu.h|   2 +
 arch/x86/kvm/mmu/mmu.c|  51 +++--
 arch/x86/kvm/mmu/page_track.c | 256 +-
 arch/x86/kvm/mmu/page_track.h |  58 ++
 arch/x86/kvm/x86.c|  22 +--
 drivers/gpu/drm/i915/gvt/gtt.c| 102 ++
 drivers/gpu/drm/i915/gvt/gtt.h|   1 -
 drivers/gpu/drm/i915/gvt/gvt.h|   3 +-
 drivers/gpu/drm/i915/gvt/kvmgt.c  | 117 +---
 drivers/gpu/drm/i915/gvt/page_track.c |  10 +-
 12 files changed, 320 insertions(+), 391 deletions(-)
 create mode 100644 arch/x86/kvm/mmu/page_track.h


base-commit: b3c98052d46948a8d65d2778c7f306ff38366aac
-- 
2.40.1.606.ga4b1b128d6-goog

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Allow user to set cache at BO creation (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915: Allow user to set cache at BO creation (rev8)
URL   : https://patchwork.freedesktop.org/series/116870/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13143 -> Patchwork_116870v8


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_116870v8 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_116870v8, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v8/index.html

Participating hosts (38 -> 38)
--

  Additional (1): fi-kbl-soraka 
  Missing(1): fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_116870v8:

### IGT changes ###

 Possible regressions 

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck@pipe-b-dp-1:
- bat-dg2-8:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-dg2-8/igt@kms_pipe_crc_basic@compare-crc-sanitych...@pipe-b-dp-1.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v8/bat-dg2-8/igt@kms_pipe_crc_basic@compare-crc-sanitych...@pipe-b-dp-1.html

  
Known issues


  Here are the changes found in Patchwork_116870v8 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v8/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v8/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#7913])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v8/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@migrate:
- bat-dg2-11: [PASS][6] -> [DMESG-FAIL][7] ([i915#7699] / 
[i915#7913])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-dg2-11/igt@i915_selftest@l...@migrate.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v8/bat-dg2-11/igt@i915_selftest@l...@migrate.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][8] ([i915#6687])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v8/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][9] ([i915#6687] / [i915#7953] / 
[i915#7978])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v8/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka:  NOTRUN -> [SKIP][10] ([fdo#109271]) +15 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v8/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#1845] / [i915#5354]) +2 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v8/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-soraka:  NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4579])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v8/fi-kbl-soraka/igt@kms_setm...@basic-clone-single-crtc.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][13] ([i915#5334]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v8/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][15] ([i915#4983] / [i915#7461] / [i915#7913] 
/ [i915#8347]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rpls-2/igt@i915_selftest@l...@reset.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v8/bat-rpls-2/igt@i915_selftest@l...@reset.html
- bat-rpls-1: [ABORT][17] ([i915#4983] / [i915#7461] / [i915#7953] 
/ [i915#8347] / [i915#8384]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rpls-1/igt@i915_selftest@l...@reset.html
   [18]: 

[Intel-gfx] [linux-next:master] BUILD SUCCESS WITH WARNING e922ba281a8d84f640d8c8e18a385d032c19e185

[kernel test robot]

tree/branch: 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: e922ba281a8d84f640d8c8e18a385d032c19e185  Add linux-next specific 
files for 20230512

Warning reports:

https://lore.kernel.org/oe-kbuild-all/202305130809.sjnm01fl-...@intel.com

Warning: (recently discovered and may have been fixed)

drivers/base/regmap/regcache-maple.c:113:23: warning: 'lower_index' is used 
uninitialized [-Wuninitialized]
drivers/base/regmap/regcache-maple.c:113:36: warning: 'lower_last' is used 
uninitialized [-Wuninitialized]
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:6396:21: warning: 
variable 'count' set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:499:13: warning: variable 'j' set but 
not used [-Wunused-but-set-variable]
lib/maple_tree.c:4707:7: warning: no previous prototype for 'mas_next_slot' 
[-Wmissing-prototypes]

Unverified Warning (likely false positive, please contact us if interested):

drivers/crypto/intel/qat/qat_common/adf_cfg.c:262 adf_cfg_add_key_value_param() 
warn: argument 4 to %lx specifier is cast from pointer
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:648:3-9: preceding lock on line 640
drivers/gpu/drm/i915/display/intel_psr.c:2999:0-23: WARNING: 
i915_edp_psr_debug_fops should be defined with DEFINE_DEBUGFS_ATTRIBUTE

Warning ids grouped by kconfigs:

gcc_recent_errors
|-- alpha-allyesconfig
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used
|   `-- 
drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used
|-- alpha-randconfig-r013-20230511
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used
|   `-- 
drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used
|-- alpha-randconfig-s043-20230510
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used
|   `-- 
drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used
|-- arc-allyesconfig
|   |-- 
drivers-base-regmap-regcache-maple.c:warning:lower_index-is-used-uninitialized
|   |-- 
drivers-base-regmap-regcache-maple.c:warning:lower_last-is-used-uninitialized
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used
|   `-- 
drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used
|-- arc-randconfig-r011-20230509
|   `-- 
drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used
|-- arc-randconfig-r011-20230511
|   |-- 
drivers-base-regmap-regcache-maple.c:warning:lower_index-is-used-uninitialized
|   `-- 
drivers-base-regmap-regcache-maple.c:warning:lower_last-is-used-uninitialized
|-- arc-randconfig-r043-20230511
|   |-- 
drivers-base-regmap-regcache-maple.c:warning:lower_index-is-used-uninitialized
|   |-- 
drivers-base-regmap-regcache-maple.c:warning:lower_last-is-used-uninitialized
|   `-- 
drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used
|-- arm-allmodconfig
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used
|   `-- 
drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used
|-- arm-allyesconfig
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used
|   `-- 
drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used
|-- arm64-allyesconfig
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used
|   `-- 
drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used
|-- arm64-randconfig-c004-20230509
|   |-- drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:preceding-lock-on-line
|   `-- 
drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used
|-- csky-randconfig-s041-20230510
|   `-- 
drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used
|-- i386-allyesconfig
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used
|   `-- 
drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used
|-- i386-randconfig-m021
|   `-- 
drivers-crypto-intel-qat-qat_common-adf_cfg.c-adf_cfg_add_key_value_param()-warn:argument-to-lx-specifier-is-cast-from-pointer
|-- ia64-allmodconfig
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used
|   `-- 
drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used
|-- ia64-randconfig-r006-20230511
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used
|   `-- 
drivers-gpu-drm-amd-amdgpu-amdgpu_gfx.c:warning:variable-j-set-but-not-used
|-- loongarch-allmodconfig
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-amdgpu_dm-amdgpu_dm.c:warning:variable-count-set-but-not-used

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Allow user to set cache at BO creation (rev8)

[Patchwork]

== Series Details ==

Series: drm/i915: Allow user to set cache at BO creation (rev8)
URL   : https://patchwork.freedesktop.org/series/116870/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915/dpll: drop a useless I915_STATE_WARN_ON() (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/dpll: drop a useless 
I915_STATE_WARN_ON() (rev2)
URL   : https://patchwork.freedesktop.org/series/117685/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13143_full -> Patchwork_117685v2_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (7 -> 7)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_117685v2_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][1] -> [FAIL][2] ([i915#2842])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-apl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][3] -> [FAIL][4] ([i915#2842])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_lmem_swapping@massive-random:
- shard-glk:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/shard-glk6/igt@gem_lmem_swapp...@massive-random.html

  * igt@kms_chamelium_color@ctm-max:
- shard-glk:  NOTRUN -> [SKIP][6] ([fdo#109271]) +26 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/shard-glk6/igt@kms_chamelium_co...@ctm-max.html

  * igt@kms_content_protection@atomic:
- shard-glk:  NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4579])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/shard-glk6/igt@kms_content_protect...@atomic.html

  
 Possible fixes 

  * igt@gem_barrier_race@remote-request@rcs0:
- shard-glk:  [ABORT][8] ([i915#7461] / [i915#8211]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@gem_barrier_race@remote-requ...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/shard-glk4/igt@gem_barrier_race@remote-requ...@rcs0.html

  * igt@gem_ctx_freq@sysfs:
- {shard-dg1}:[FAIL][10] ([i915#6786]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-dg1-15/igt@gem_ctx_f...@sysfs.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/shard-dg1-12/igt@gem_ctx_f...@sysfs.html

  * igt@gem_eio@hibernate:
- {shard-dg1}:[ABORT][12] ([i915#7975] / [i915#8213]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-dg1-14/igt@gem_...@hibernate.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/shard-dg1-15/igt@gem_...@hibernate.html

  * igt@gem_eio@in-flight-contexts-10ms:
- {shard-tglu}:   [TIMEOUT][14] ([i915#3063] / [i915#7941]) -> 
[PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-tglu-3/igt@gem_...@in-flight-contexts-10ms.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/shard-tglu-3/igt@gem_...@in-flight-contexts-10ms.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [FAIL][16] ([i915#2846]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk2/igt@gem_exec_f...@basic-deadline.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/shard-glk1/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- {shard-rkl}:[FAIL][18] ([i915#2842]) -> [PASS][19] +1 similar 
issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-rkl-1/igt@gem_exec_fair@basic-p...@rcs0.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/shard-rkl-6/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
- {shard-dg1}:[TIMEOUT][20] ([i915#5493]) -> [PASS][21]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-dg1-17/igt@gem_lmem_swapping@smem-...@lmem0.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/shard-dg1-12/igt@gem_lmem_swapping@smem-...@lmem0.html

  * igt@gen9_exec_parse@allowed-single:
- shard-glk:  [ABORT][22] ([i915#5566]) -> [PASS][23]
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/shard-glk1/igt@gen9_exec_pa...@allowed-single.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/shard-glk6/igt@gen9_exec_pa...@allowed-single.html

  * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-rkl}:[SKIP][24] ([i915#1397]) -> [PASS][25]
   [24]: 

[Intel-gfx] [PATCH] drm/i915/selftest/gsc: Ensure GSC Proxy init completes before selftests

[Alan Previn]

On MTL, if the GSC Proxy init flows haven't completed, submissions to the
GSC engine will fail. Those init flows are dependent on the mei's
gsc_proxy component that is loaded in parallel with i915 and a
worker that could potentially start after i915 driver init is done.

That said, all subsytems that access the GSC engine today does check
for such init flow completion before using the GSC engine. However,
selftests currently don't wait on anything before starting.

To fix this, add a waiter function at the start of __run_selftests
that waits for gsc-proxy init flows to complete. While implementing this,
use an table of function pointers so its scalable to add additional
waiter functions for future such "wait on dependency" cases that.

Signed-off-by: Alan Previn 
---
 .../gpu/drm/i915/selftests/i915_selftest.c| 53 +++
 1 file changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/i915/selftests/i915_selftest.c 
b/drivers/gpu/drm/i915/selftests/i915_selftest.c
index 39da0fb0d6d2..a05effdbce94 100644
--- a/drivers/gpu/drm/i915/selftests/i915_selftest.c
+++ b/drivers/gpu/drm/i915/selftests/i915_selftest.c
@@ -24,6 +24,8 @@
 #include 
 
 #include "gt/intel_gt_pm.h"
+#include "gt/uc/intel_gsc_fw.h"
+
 #include "i915_driver.h"
 #include "i915_drv.h"
 #include "i915_selftest.h"
@@ -127,6 +129,55 @@ static void set_default_test_all(struct selftest *st, 
unsigned int count)
st[i].enabled = true;
 }
 
+static int
+__wait_gsc_proxy_completed(struct drm_i915_private *i915,
+  unsigned long timeout_ms)
+{
+   bool need_to_wait = (IS_ENABLED(CONFIG_INTEL_MEI_GSC_PROXY) &&
+i915->media_gt &&
+HAS_ENGINE(i915->media_gt, GSC0) &&
+
intel_uc_fw_is_loadable(>media_gt->uc.gsc.fw));
+
+   if (need_to_wait &&
+   (wait_for(intel_gsc_uc_fw_proxy_init_done(>media_gt->uc.gsc),
+   timeout_ms)))
+   return -ETIME;
+
+   return 0;
+}
+
+struct __startup_waiter {
+   const char *name;
+   int (*wait_to_completed)(struct drm_i915_private *i915, unsigned long 
timeout_ms);
+};
+
+static struct __startup_waiter all_startup_waiters[] = { \
+   {"gsc_proxy", __wait_gsc_proxy_completed} \
+   };
+
+static int __wait_on_all_system_dependencies(struct drm_i915_private *i915)
+{
+   struct __startup_waiter *waiter = all_startup_waiters;
+   int count = ARRAY_SIZE(all_startup_waiters);
+   int ret;
+
+   if (!waiter || !count || !i915)
+   return 0;
+
+   for (; count--; waiter++) {
+   if (!waiter->wait_to_completed)
+   continue;
+   ret = waiter->wait_to_completed(i915, i915_selftest.timeout_ms);
+   if (ret) {
+   pr_info(DRIVER_NAME ": Pre-selftest waiter %s failed 
with %d\n",
+   waiter->name, ret);
+   return ret;
+   }
+   }
+
+   return 0;
+}
+
 static int __run_selftests(const char *name,
   struct selftest *st,
   unsigned int count,
@@ -134,6 +185,8 @@ static int __run_selftests(const char *name,
 {
int err = 0;
 
+   __wait_on_all_system_dependencies(data);
+
while (!i915_selftest.random_seed)
i915_selftest.random_seed = get_random_u32();
 

base-commit: 222ff19f23b0bd6aca0b52001d69699f78f5a206
-- 
2.39.0

[Intel-gfx] [PATCH] drm/i915/guc/slpc: Disable rps_boost debugfs

[Vinay Belgaumkar]

rps_boost debugfs shows host turbo related info. This is not valid
when SLPC is enabled. guc_slpc_info already shows the number of boosts.
Add num_waiters there as well and disable rps_boost when SLPC is
enabled.

Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7632
Signed-off-by: Vinay Belgaumkar 
---
 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 5 -
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   | 2 ++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c 
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 80dbbef86b1d..357e2f865727 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -539,7 +539,10 @@ static bool rps_eval(void *data)
 {
struct intel_gt *gt = data;
 
-   return HAS_RPS(gt->i915);
+   if (intel_guc_slpc_is_used(>uc.guc))
+   return false;
+   else
+   return HAS_RPS(gt->i915);
 }
 
 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 56dbba1ef668..01b75529311c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -837,6 +837,8 @@ int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, 
struct drm_printer *p
   slpc_decode_min_freq(slpc));
drm_printf(p, "\twaitboosts: %u\n",
   slpc->num_boosts);
+   drm_printf(p, "\tBoosts outstanding: %u\n",
+  atomic_read(>num_waiters));
}
}
 
-- 
2.38.1

Re: [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer

[Umesh Nerlige Ramappa]

On Fri, May 12, 2023 at 04:20:19PM -0700, Dixit, Ashutosh wrote:

On Fri, 12 May 2023 15:44:00 -0700, Umesh Nerlige Ramappa wrote:


On Fri, May 12, 2023 at 03:29:03PM -0700, Dixit, Ashutosh wrote:
> On Fri, 05 May 2023 17:58:14 -0700, Umesh Nerlige Ramappa wrote:
>>
>
> Hi Umesh/Tvrtko,
>
>> From: Tvrtko Ursulin 
>>
>> We do not want to have timers per tile and waste CPU cycles and energy via
>> multiple wake-up sources, for a relatively un-important task of PMU
>> sampling, so keeping a single timer works well. But we also do not want
>> the first GT which goes idle to turn off the timer.
>>
>> Add some reference counting, via a mask of unparked GTs, to solve this.
>>
>> Signed-off-by: Tvrtko Ursulin 
>> Signed-off-by: Umesh Nerlige Ramappa 
>> ---
>>  drivers/gpu/drm/i915/i915_pmu.c | 12 ++--
>>  drivers/gpu/drm/i915/i915_pmu.h |  4 
>>  2 files changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_pmu.c 
b/drivers/gpu/drm/i915/i915_pmu.c
>> index 2b63ee31e1b3..669a42e44082 100644
>> --- a/drivers/gpu/drm/i915/i915_pmu.c
>> +++ b/drivers/gpu/drm/i915/i915_pmu.c
>> @@ -251,7 +251,9 @@ void i915_pmu_gt_parked(struct intel_gt *gt)
>> * Signal sampling timer to stop if only engine events are enabled and
>> * GPU went idle.
>> */
>> -  pmu->timer_enabled = pmu_needs_timer(pmu, false);
>> +  pmu->unparked &= ~BIT(gt->info.id);
>> +  if (pmu->unparked == 0)
>> +  pmu->timer_enabled = pmu_needs_timer(pmu, false);
>>
>>spin_unlock_irq(>lock);
>>  }
>> @@ -268,7 +270,10 @@ void i915_pmu_gt_unparked(struct intel_gt *gt)
>>/*
>> * Re-enable sampling timer when GPU goes active.
>> */
>> -  __i915_pmu_maybe_start_timer(pmu);
>> +  if (pmu->unparked == 0)
>> +  __i915_pmu_maybe_start_timer(pmu);
>> +
>> +  pmu->unparked |= BIT(gt->info.id);
>>
>>spin_unlock_irq(>lock);
>>  }
>> @@ -438,6 +443,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer 
*hrtimer)
>> */
>>
>>for_each_gt(gt, i915, i) {
>> +  if (!(pmu->unparked & BIT(i)))
>> +  continue;
>> +
>
> This is not correct. In this series we are at least sampling frequencies
> (calling frequency_sample) even when GT is parked. So these 3 lines should be
> deleted. engines_sample will get called and will return without doing
> anything if engine events are disabled.

Not sure I understand. This is checking pmu->'un'parked bits.


Sorry, my bad. Not "engines_sample will get called and will return without
doing anything if engine events are disabled" but "engines_sample will get
called and will return without doing anything if GT is not awake". This is
the same as the previous behavior before this series.

Umesh and I discussed this but writing this out in case Tvrtko takes a
look.


Sounds good, Dropping the check here in the new revision.

Thanks,
Umesh


Thanks.
--
Ashutosh




>
>
>>engines_sample(gt, period_ns);
>>
>>if (i == 0) /* FIXME */
>> diff --git a/drivers/gpu/drm/i915/i915_pmu.h 
b/drivers/gpu/drm/i915/i915_pmu.h
>> index a686fd7ccedf..3a811266ac6a 100644
>> --- a/drivers/gpu/drm/i915/i915_pmu.h
>> +++ b/drivers/gpu/drm/i915/i915_pmu.h
>> @@ -76,6 +76,10 @@ struct i915_pmu {
>> * @lock: Lock protecting enable mask and ref count handling.
>> */
>>spinlock_t lock;
>> +  /**
>> +   * @unparked: GT unparked mask.
>> +   */
>> +  unsigned int unparked;
>>/**
>> * @timer: Timer for internal i915 PMU sampling.
>> */
>> --
>> 2.36.1
>>

Re: [Intel-gfx] [PATCH v7 4/4] drm/i915: Allow user to set cache at BO creation

[Yang, Fei]

> On 2023-05-10 15:14:16, Andi Shyti wrote:
>> Hi,
>>
>> On Tue, May 09, 2023 at 09:59:42AM -0700, fei.y...@intel.com wrote:
>>> From: Fei Yang 
>>>
>>> To comply with the design that buffer objects shall have immutable
>>> cache setting through out their life cycle, {set, get}_caching ioctl's
>>> are no longer supported from MTL onward. With that change caching
>>> policy can only be set at object creation time. The current code
>>> applies a default (platform dependent) cache setting for all objects.
>>> However this is not optimal for performance tuning. The patch extends
>>> the existing gem_create uAPI to let user set PAT index for the object
>>> at creation time.
>>> The new extension is platform independent, so UMD's can switch to using
>>> this extension for older platforms as well, while {set, get}_caching are
>>> still supported on these legacy paltforms for compatibility reason.
>>>
>>> Cc: Chris Wilson 
>>> Cc: Matt Roper 
>>> Cc: Andi Shyti 
>>> Signed-off-by: Fei Yang 
>>> Reviewed-by: Andi Shyti 
>>
>> just for a matter of completeness, this is new uapi is tested
>> through the "create-ext-set-pat" test case from the "gem_create"
>> igt test[1]. Can any of the igt maintainers give it a look,
>> comment and ack?
>>
>> The mesa merge request is here [2]. As there is a merge request
>> in progress, would anyone from mesa be so kind to give an ack to
>> this patch, as well?
>>
>> With the mesa ack in place this patch should be ready to go and
>> I'm looking forward to having it in.
>
> I tested my MR [2] in our CI. There was some bad news, but I don't
> think it needs to block these patches.
>
> The good news was that I found that OpenGL testing with our iris
> driver appeared to have ok results when using this interface.
>
> But, our Vulkan Anvil driver was not stable with the current patches
> in the Mesa MR. We will need to debug this further before using the
> interface on Vulkan.
>
> I don't suspect that this is an issue with the kernel interface, so
> you can add:
>
> Tested-by: Jordan Justen 

v8 sent with updates.

> -Jordan

Thanks Jordan.

>>
>> Thanks,
>> Andi
>>
>> [1] https://patchwork.freedesktop.org/patch/534955/?series=117185=1
>> [2] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
>>

[Intel-gfx] [PATCH v8 1/2] drm/i915/mtl: end support for set caching ioctl

[fei . yang]

From: Fei Yang 

The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
cache. For userspace components needing to fine tune the caching policy
for BO's, a follow up patch will extend the GEM_CREATE uAPI to allow
them specify caching mode at BO creation time.

Signed-off-by: Fei Yang 
Reviewed-by: Andi Shyti 
Reviewed-by: Andrzej Hajda 
---
 drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c  | 9 -
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c 
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 05107a6efe45..dfaaa8b66ac3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -350,6 +350,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void 
*data,
if (IS_DGFX(i915))
return -ENODEV;
 
+   if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+   return -EOPNOTSUPP;
+
switch (args->caching) {
case I915_CACHING_NONE:
level = I915_CACHE_NONE;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c 
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 37d1efcd3ca6..cad4a6017f4b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region 
*mem,
obj->write_domain = I915_GEM_DOMAIN_CPU;
obj->read_domains = I915_GEM_DOMAIN_CPU;
 
-   if (HAS_LLC(i915))
+   /*
+* MTL doesn't snoop CPU cache by default for GPU access (namely
+* 1-way coherency). However some UMD's are currently depending on
+* that. Make 1-way coherent the default setting for MTL. A follow
+* up patch will extend the GEM_CREATE uAPI to allow UMD's specify
+* caching mode at BO creation time
+*/
+   if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)))
/* On some devices, we can have the GPU use the LLC (the CPU
 * cache) for about a 10% performance improvement
 * compared to uncached.  Graphics requests other than
-- 
2.25.1

[Intel-gfx] [PATCH v8 2/2] drm/i915: Allow user to set cache at BO creation

[fei . yang]

From: Fei Yang 

To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a default (platform dependent) cache setting for all objects.
However this is not optimal for performance tuning. The patch extends
the existing gem_create uAPI to let user set PAT index for the object
at creation time.
The new extension is platform independent, so UMD's can switch to using
this extension for older platforms as well, while {set, get}_caching are
still supported on these legacy paltforms for compatibility reason.

IGT posted at https://patchwork.freedesktop.org/series/117695/

Tested with https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878

Tested-by: Jordan Justen 
Cc: Chris Wilson 
Cc: Matt Roper 
Cc: Andi Shyti 
Signed-off-by: Fei Yang 
Reviewed-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 ++
 drivers/gpu/drm/i915/gem/i915_gem_object.c |  6 
 include/uapi/drm/i915_drm.h| 36 ++
 tools/include/uapi/drm/i915_drm.h  | 36 ++
 4 files changed, 114 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c 
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index bfe1dbda4cb7..644a936248ad 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -245,6 +245,7 @@ struct create_ext {
unsigned int n_placements;
unsigned int placement_mask;
unsigned long flags;
+   unsigned int pat_index;
 };
 
 static void repr_placements(char *buf, size_t size,
@@ -394,11 +395,39 @@ static int ext_set_protected(struct i915_user_extension 
__user *base, void *data
return 0;
 }
 
+static int ext_set_pat(struct i915_user_extension __user *base, void *data)
+{
+   struct create_ext *ext_data = data;
+   struct drm_i915_private *i915 = ext_data->i915;
+   struct drm_i915_gem_create_ext_set_pat ext;
+   unsigned int max_pat_index;
+
+   BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
+offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
+
+   if (copy_from_user(, base, sizeof(ext)))
+   return -EFAULT;
+
+   max_pat_index = INTEL_INFO(i915)->max_pat_index;
+
+   if (ext.pat_index > max_pat_index) {
+   drm_dbg(>drm, "PAT index is invalid: %u\n",
+   ext.pat_index);
+   return -EINVAL;
+   }
+
+   ext_data->pat_index = ext.pat_index;
+
+   return 0;
+}
+
 static const i915_user_extension_fn create_extensions[] = {
[I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements,
[I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected,
+   [I915_GEM_CREATE_EXT_SET_PAT] = ext_set_pat,
 };
 
+#define PAT_INDEX_NOT_SET  0x
 /**
  * i915_gem_create_ext_ioctl - Creates a new mm object and returns a handle to 
it.
  * @dev: drm device pointer
@@ -418,6 +447,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void 
*data,
if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS)
return -EINVAL;
 
+   ext_data.pat_index = PAT_INDEX_NOT_SET;
ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
   create_extensions,
   ARRAY_SIZE(create_extensions),
@@ -454,5 +484,11 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void 
*data,
if (IS_ERR(obj))
return PTR_ERR(obj);
 
+   if (ext_data.pat_index != PAT_INDEX_NOT_SET) {
+   i915_gem_object_set_pat_index(obj, ext_data.pat_index);
+   /* Mark pat_index is set by UMD */
+   obj->pat_set_by_user = true;
+   }
+
return i915_gem_publish(obj, file, >size, >handle);
 }
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c 
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 46a19b099ec8..97ac6fb37958 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -208,6 +208,12 @@ bool i915_gem_object_can_bypass_llc(struct 
drm_i915_gem_object *obj)
if (!(obj->flags & I915_BO_ALLOC_USER))
return false;
 
+   /*
+* Always flush cache for UMD objects at creation time.
+*/
+   if (obj->pat_set_by_user)
+   return true;
+
/*
 * EHL and JSL add the 'Bypass LLC' MOCS entry, which should make it
 * possible for userspace to bypass the GTT caching bits set by the
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index ba40855dbc93..7f5597920257 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3664,9 +3664,13 @@ struct drm_i915_gem_create_ext {
 *
 * 

[Intel-gfx] [PATCH v8 0/2] drm/i915: Allow user to set cache at BO creation

[fei . yang]

From: Fei Yang 

The first three patches in this series are taken from
https://patchwork.freedesktop.org/series/116868/
These patches are included here because the last patch
has dependency on the pat_index refactor.

This series is focusing on uAPI changes,
1. end support for set caching ioctl [PATCH 4/5]
2. add set_pat extension for gem_create [PATCH 5/5]

v2: drop one patch that was merged separately
commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function")
v3: rebased on https://patchwork.freedesktop.org/series/117082/
v4: fix missing unlock introduced in v3, and
solve a rebase conflict
v5: replace obj->cache_level with pat_set_by_user,
fix i915_cache_level_str() for legacy platforms.
v6: rebased on https://patchwork.freedesktop.org/series/117480/
v7: rebased on https://patchwork.freedesktop.org/series/117528/
v8: dropped the two dependent patches that has been merged
separately. Add IGT link and Tested-by (MESA).

Fei Yang (2):
  drm/i915/mtl: end support for set caching ioctl
  drm/i915: Allow user to set cache at BO creation

 drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 ++
 drivers/gpu/drm/i915/gem/i915_gem_domain.c |  3 ++
 drivers/gpu/drm/i915/gem/i915_gem_object.c |  6 
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c  |  9 +-
 include/uapi/drm/i915_drm.h| 36 ++
 tools/include/uapi/drm/i915_drm.h  | 36 ++
 6 files changed, 125 insertions(+), 1 deletion(-)

-- 
2.25.1

Re: [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer

[Dixit, Ashutosh]

On Fri, 12 May 2023 15:44:00 -0700, Umesh Nerlige Ramappa wrote:
>
> On Fri, May 12, 2023 at 03:29:03PM -0700, Dixit, Ashutosh wrote:
> > On Fri, 05 May 2023 17:58:14 -0700, Umesh Nerlige Ramappa wrote:
> >>
> >
> > Hi Umesh/Tvrtko,
> >
> >> From: Tvrtko Ursulin 
> >>
> >> We do not want to have timers per tile and waste CPU cycles and energy via
> >> multiple wake-up sources, for a relatively un-important task of PMU
> >> sampling, so keeping a single timer works well. But we also do not want
> >> the first GT which goes idle to turn off the timer.
> >>
> >> Add some reference counting, via a mask of unparked GTs, to solve this.
> >>
> >> Signed-off-by: Tvrtko Ursulin 
> >> Signed-off-by: Umesh Nerlige Ramappa 
> >> ---
> >>  drivers/gpu/drm/i915/i915_pmu.c | 12 ++--
> >>  drivers/gpu/drm/i915/i915_pmu.h |  4 
> >>  2 files changed, 14 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_pmu.c 
> >> b/drivers/gpu/drm/i915/i915_pmu.c
> >> index 2b63ee31e1b3..669a42e44082 100644
> >> --- a/drivers/gpu/drm/i915/i915_pmu.c
> >> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> >> @@ -251,7 +251,9 @@ void i915_pmu_gt_parked(struct intel_gt *gt)
> >> * Signal sampling timer to stop if only engine events are enabled and
> >> * GPU went idle.
> >> */
> >> -  pmu->timer_enabled = pmu_needs_timer(pmu, false);
> >> +  pmu->unparked &= ~BIT(gt->info.id);
> >> +  if (pmu->unparked == 0)
> >> +  pmu->timer_enabled = pmu_needs_timer(pmu, false);
> >>
> >>spin_unlock_irq(>lock);
> >>  }
> >> @@ -268,7 +270,10 @@ void i915_pmu_gt_unparked(struct intel_gt *gt)
> >>/*
> >> * Re-enable sampling timer when GPU goes active.
> >> */
> >> -  __i915_pmu_maybe_start_timer(pmu);
> >> +  if (pmu->unparked == 0)
> >> +  __i915_pmu_maybe_start_timer(pmu);
> >> +
> >> +  pmu->unparked |= BIT(gt->info.id);
> >>
> >>spin_unlock_irq(>lock);
> >>  }
> >> @@ -438,6 +443,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer 
> >> *hrtimer)
> >> */
> >>
> >>for_each_gt(gt, i915, i) {
> >> +  if (!(pmu->unparked & BIT(i)))
> >> +  continue;
> >> +
> >
> > This is not correct. In this series we are at least sampling frequencies
> > (calling frequency_sample) even when GT is parked. So these 3 lines should 
> > be
> > deleted. engines_sample will get called and will return without doing
> > anything if engine events are disabled.
>
> Not sure I understand. This is checking pmu->'un'parked bits.

Sorry, my bad. Not "engines_sample will get called and will return without
doing anything if engine events are disabled" but "engines_sample will get
called and will return without doing anything if GT is not awake". This is
the same as the previous behavior before this series.

Umesh and I discussed this but writing this out in case Tvrtko takes a
look.

Thanks.
--
Ashutosh



> >
> >
> >>engines_sample(gt, period_ns);
> >>
> >>if (i == 0) /* FIXME */
> >> diff --git a/drivers/gpu/drm/i915/i915_pmu.h 
> >> b/drivers/gpu/drm/i915/i915_pmu.h
> >> index a686fd7ccedf..3a811266ac6a 100644
> >> --- a/drivers/gpu/drm/i915/i915_pmu.h
> >> +++ b/drivers/gpu/drm/i915/i915_pmu.h
> >> @@ -76,6 +76,10 @@ struct i915_pmu {
> >> * @lock: Lock protecting enable mask and ref count handling.
> >> */
> >>spinlock_t lock;
> >> +  /**
> >> +   * @unparked: GT unparked mask.
> >> +   */
> >> +  unsigned int unparked;
> >>/**
> >> * @timer: Timer for internal i915 PMU sampling.
> >> */
> >> --
> >> 2.36.1
> >>

Re: [Intel-gfx] [PATCH] drm/i915: RFC: Introduce Wa_14011282866

[Matt Roper]

On Wed, May 10, 2023 at 02:58:11PM -0700, Matt Atwood wrote:
> From: Tilak Tangudu 
> 
> Wa_14011282866 applies to RKL, ADL-S, ADL-P and TGL.

Wa_14011282866 isn't a valid workaround number.

> 
> Allocate buffer pinned to GGTT and add WA to restore sampler power
> context.
> 
> Bspec: 46247
> 
> Signed-off-by: Matt Atwood 
> Signed-off-by: Tilak Tangudu 

These lines are backward if Tilak is the original author as shown above.
>From Documentation/process/submitting-patches.rst:

"Any further SoBs (Signed-off-by:'s) following the author's SoB
are from people handling and transporting the patch, but were
not involved in its development. SoB chains should reflect the
**real** route a patch took as it was propagated to the
maintainers and ultimately to Linus, with the first SoB entry
signalling primary authorship of a single author."

> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h   |  5 ++
>  drivers/gpu/drm/i915/gt/intel_rc6.c   | 88 +++
>  drivers/gpu/drm/i915/gt/intel_rc6_types.h |  3 +
>  3 files changed, 96 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index b8a39c219b60..91cbdd24572f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -48,6 +48,11 @@
>  /* RCP unit config (Gen8+) */
>  #define RCP_CONFIG   _MMIO(0xd08)
>  
> +#define CTX_WA_PTR   _MMIO(0x2058)
> +#define CTX_WA_PTR_ADDR_MASK REG_GENMASK(31, 12)
> +#define CTX_WA_TYPE_MASK REG_GENMASK(4, 3)
> +#define CTX_WA_VALID REG_BIT(0)

This register isn't at the right place.  Also the bit definitions are
missing a couple spaces before the bitfield names.

> +
>  #define RC6_LOCATION _MMIO(0xd40)
>  #define   RC6_CTX_IN_DRAM(1 << 0)
>  #define RC6_CTX_BASE _MMIO(0xd48)
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c 
> b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 908a3d0f2343..9589af2e8ca3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -12,6 +12,7 @@
>  #include "i915_vgpu.h"
>  #include "intel_engine_regs.h"
>  #include "intel_gt.h"
> +#include "intel_gpu_commands.h"
>  #include "intel_gt_pm.h"
>  #include "intel_gt_regs.h"
>  #include "intel_pcode.h"
> @@ -38,6 +39,7 @@
>   * require higher latency to switch to and wake up.
>   */
>  
> +#define RC6_CTX_WA_BB_SIZE (PAGE_SIZE)

Do we really need this?  It's unlikely that we'll wind up needing more
than a page (and we're not even trying to check in the code below either).

>  static struct intel_gt *rc6_to_gt(struct intel_rc6 *rc6)
>  {
>   return container_of(rc6, struct intel_gt, rc6);
> @@ -53,8 +55,86 @@ static struct drm_i915_private *rc6_to_i915(struct 
> intel_rc6 *rc)
>   return rc6_to_gt(rc)->i915;
>  }
>  
> +static int rc6_wa_bb_ctx_init(struct intel_rc6 *rc6)
> +{
> + struct drm_i915_private *i915 = rc6_to_i915(rc6);
> + struct intel_gt *gt = rc6_to_gt(rc6);
> + struct drm_i915_gem_object *obj;
> + struct i915_vma *vma;
> + void *batch;
> + struct i915_gem_ww_ctx ww;
> + int err;
> +
> + obj = i915_gem_object_create_shmem(i915, RC6_CTX_WA_BB_SIZE);
> + if (IS_ERR(obj))
> + return PTR_ERR(obj);
> +
> + vma = i915_vma_instance(obj, >ggtt->vm, NULL);
> + if (IS_ERR(vma)) {
> + err = PTR_ERR(vma);
> + goto err;
> + }
> + rc6->vma = vma;
> + i915_gem_ww_ctx_init(, true);
> +retry:
> + err = i915_gem_object_lock(rc6->vma->obj, );

Nitpick:  Can't we just use the shorter local variable 'obj' here and in
the pin_map?

> + if (!err)
> + err = i915_ggtt_pin(rc6->vma, , 0, PIN_HIGH);
> + if (err)
> + goto err_ww_fini;
> +
> + batch = i915_gem_object_pin_map(rc6->vma->obj, I915_MAP_WB);
> + if (IS_ERR(batch)) {
> + err = PTR_ERR(batch);
> + goto err_unpin;
> + }
> + rc6->rc6_wa_bb = batch;
> + return 0;
> +err_unpin:
> + if (err)
> + i915_vma_unpin(rc6->vma);
> +err_ww_fini:
> + if (err == -EDEADLK) {
> + err = i915_gem_ww_ctx_backoff();
> + if (!err)
> + goto retry;
> + }
> + i915_gem_ww_ctx_fini();
> +
> + if (err)
> + i915_vma_put(rc6->vma);
> +err:
> + i915_gem_object_put(obj);
> + return err;
> +}

Where do we clean up all the stuff done in this function?

> +
> +static void rc6_wa_bb_restore_sampler_power_ctx(struct intel_rc6 *rc6)
> +{
> + struct intel_uncore *uncore = rc6_to_uncore(rc6);
> + u32 *rc6_wa_bb;
> +
> + if (!rc6->vma->obj)
> + return;
> +
> + rc6_wa_bb = rc6->rc6_wa_bb;
> + *rc6_wa_bb++ = MI_NOOP;
> + *rc6_wa_bb++ = MI_LOAD_REGISTER_IMM(1) | 

Re: [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer

[Umesh Nerlige Ramappa]

On Fri, May 12, 2023 at 03:29:03PM -0700, Dixit, Ashutosh wrote:

On Fri, 05 May 2023 17:58:14 -0700, Umesh Nerlige Ramappa wrote:




Hi Umesh/Tvrtko,


From: Tvrtko Ursulin 

We do not want to have timers per tile and waste CPU cycles and energy via
multiple wake-up sources, for a relatively un-important task of PMU
sampling, so keeping a single timer works well. But we also do not want
the first GT which goes idle to turn off the timer.

Add some reference counting, via a mask of unparked GTs, to solve this.

Signed-off-by: Tvrtko Ursulin 
Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/i915_pmu.c | 12 ++--
 drivers/gpu/drm/i915/i915_pmu.h |  4 
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 2b63ee31e1b3..669a42e44082 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -251,7 +251,9 @@ void i915_pmu_gt_parked(struct intel_gt *gt)
 * Signal sampling timer to stop if only engine events are enabled and
 * GPU went idle.
 */
-   pmu->timer_enabled = pmu_needs_timer(pmu, false);
+   pmu->unparked &= ~BIT(gt->info.id);
+   if (pmu->unparked == 0)
+   pmu->timer_enabled = pmu_needs_timer(pmu, false);

spin_unlock_irq(>lock);
 }
@@ -268,7 +270,10 @@ void i915_pmu_gt_unparked(struct intel_gt *gt)
/*
 * Re-enable sampling timer when GPU goes active.
 */
-   __i915_pmu_maybe_start_timer(pmu);
+   if (pmu->unparked == 0)
+   __i915_pmu_maybe_start_timer(pmu);
+
+   pmu->unparked |= BIT(gt->info.id);

spin_unlock_irq(>lock);
 }
@@ -438,6 +443,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer 
*hrtimer)
 */

for_each_gt(gt, i915, i) {
+   if (!(pmu->unparked & BIT(i)))
+   continue;
+


This is not correct. In this series we are at least sampling frequencies
(calling frequency_sample) even when GT is parked. So these 3 lines should be
deleted. engines_sample will get called and will return without doing
anything if engine events are disabled.


Not sure I understand. This is checking pmu->'un'parked bits.

Thanks,
Umesh


Thanks.
--
Ashutosh



engines_sample(gt, period_ns);

if (i == 0) /* FIXME */
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index a686fd7ccedf..3a811266ac6a 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -76,6 +76,10 @@ struct i915_pmu {
 * @lock: Lock protecting enable mask and ref count handling.
 */
spinlock_t lock;
+   /**
+* @unparked: GT unparked mask.
+*/
+   unsigned int unparked;
/**
 * @timer: Timer for internal i915 PMU sampling.
 */
--
2.36.1

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

[Umesh Nerlige Ramappa]

On Fri, May 12, 2023 at 01:57:59PM -0700, Umesh Nerlige Ramappa wrote:

On Fri, May 12, 2023 at 11:56:18AM +0100, Tvrtko Ursulin wrote:


On 12/05/2023 02:08, Dixit, Ashutosh wrote:

On Fri, 05 May 2023 17:58:15 -0700, Umesh Nerlige Ramappa wrote:


From: Tvrtko Ursulin 

Reserve some bits in the counter config namespace which will carry the
tile id and prepare the code to handle this.

No per tile counters have been added yet.

v2:
- Fix checkpatch issues
- Use 4 bits for gt id in non-engine counters. Drop FIXME.
- Set MAX GTs to 4. Drop FIXME.

Signed-off-by: Tvrtko Ursulin 
Signed-off-by: Umesh Nerlige Ramappa 
---
drivers/gpu/drm/i915/i915_pmu.c | 150 +++-
drivers/gpu/drm/i915/i915_pmu.h |   9 +-
include/uapi/drm/i915_drm.h |  17 +++-
3 files changed, 129 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 669a42e44082..12b2f3169abf 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -56,11 +56,21 @@ static bool is_engine_config(u64 config)
return config < __I915_PMU_OTHER(0);
}

+static unsigned int config_gt_id(const u64 config)
+{
+   return config >> __I915_PMU_GT_SHIFT;
+}
+
+static u64 config_counter(const u64 config)
+{
+   return config & ~(~0ULL << __I915_PMU_GT_SHIFT);


ok, but another possibility:

return config & ~REG_GENMASK64(63, __I915_PMU_GT_SHIFT);


It's not a register so no. :) GENMASK_ULL maybe but meh.


leaving as is.




+}
+
static unsigned int other_bit(const u64 config)
{
unsigned int val;

-   switch (config) {
+   switch (config_counter(config)) {
case I915_PMU_ACTUAL_FREQUENCY:
val =  __I915_PMU_ACTUAL_FREQUENCY_ENABLED;
break;
@@ -78,15 +88,20 @@ static unsigned int other_bit(const u64 config)
return -1;
}

-   return I915_ENGINE_SAMPLE_COUNT + val;
+   return I915_ENGINE_SAMPLE_COUNT +
+  config_gt_id(config) * __I915_PMU_TRACKED_EVENT_COUNT +
+  val;
}

static unsigned int config_bit(const u64 config)
{
-   if (is_engine_config(config))
+   if (is_engine_config(config)) {
+   GEM_BUG_ON(config_gt_id(config));


This GEM_BUG_ON is not needed since:

static bool is_engine_config(u64 config)
{
return config < __I915_PMU_OTHER(0);
}


True!


dropping BUG_ON




+
return engine_config_sample(config);
-   else
+   } else {
return other_bit(config);
+   }
}

static u64 config_mask(u64 config)
@@ -104,6 +119,18 @@ static unsigned int event_bit(struct perf_event *event)
return config_bit(event->attr.config);
}

+static u64 frequency_enabled_mask(void)
+{
+   unsigned int i;
+   u64 mask = 0;
+
+   for (i = 0; i < I915_PMU_MAX_GTS; i++)
+   mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) |
+   config_mask(__I915_PMU_REQUESTED_FREQUENCY(i));
+
+   return mask;
+}
+
static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
{
struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
@@ -120,9 +147,7 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool 
gpu_active)
 * Mask out all the ones which do not need the timer, or in
 * other words keep all the ones that could need the timer.
 */
-   enable &= config_mask(I915_PMU_ACTUAL_FREQUENCY) |
- config_mask(I915_PMU_REQUESTED_FREQUENCY) |
- ENGINE_SAMPLE_MASK;
+   enable &= frequency_enabled_mask() | ENGINE_SAMPLE_MASK;


u32 enable & u64 frequency_enabled_mask

ugly but ok I guess? Or change enable to u64?


making pmu->enable u64 as well as other places where it is assigned to 
local variables.




Hmm.. yes very ugly. Could have been an accident which happened to 
work because there is a single timer (not per tile).


Happened to work because the frequency mask does not spill over to the 
upper 32 bits (even for multi tile).


- START_SECTION 


Similar issue in frequency_sampling_enabled too. Gt_id argument to 
it seems pointless.


Not sure why it's pointless. We need the gt_id to determine the right 
mask for that specific gt. If it's not enabled, then we just return 
without pm_get and async put (like you mention later).


And this piece of code is called within for_each_gt.



So I now think whole frequency_enabled_mask() is just pointless and 
should be removed. And then pmu_needs_time code can stay as is. 
Possibly add a config_mask_32 helper which ensures no bits in upper 
32 bits are returned.


That is if we are happy for the frequency_sampling_enabled returning 
true for all gts, regardless of which ones actually have frequency 
sampling enabled.


Or if we want to implement it as I probably have intended, we will 
need to add some gt bits into pmu->enable. Maybe 

Re: [Intel-gfx] [PATCH 4/6] drm/i915/pmu: Add reference counting to the sampling timer

[Dixit, Ashutosh]

On Fri, 05 May 2023 17:58:14 -0700, Umesh Nerlige Ramappa wrote:
>

Hi Umesh/Tvrtko,

> From: Tvrtko Ursulin 
>
> We do not want to have timers per tile and waste CPU cycles and energy via
> multiple wake-up sources, for a relatively un-important task of PMU
> sampling, so keeping a single timer works well. But we also do not want
> the first GT which goes idle to turn off the timer.
>
> Add some reference counting, via a mask of unparked GTs, to solve this.
>
> Signed-off-by: Tvrtko Ursulin 
> Signed-off-by: Umesh Nerlige Ramappa 
> ---
>  drivers/gpu/drm/i915/i915_pmu.c | 12 ++--
>  drivers/gpu/drm/i915/i915_pmu.h |  4 
>  2 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 2b63ee31e1b3..669a42e44082 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -251,7 +251,9 @@ void i915_pmu_gt_parked(struct intel_gt *gt)
>* Signal sampling timer to stop if only engine events are enabled and
>* GPU went idle.
>*/
> - pmu->timer_enabled = pmu_needs_timer(pmu, false);
> + pmu->unparked &= ~BIT(gt->info.id);
> + if (pmu->unparked == 0)
> + pmu->timer_enabled = pmu_needs_timer(pmu, false);
>
>   spin_unlock_irq(>lock);
>  }
> @@ -268,7 +270,10 @@ void i915_pmu_gt_unparked(struct intel_gt *gt)
>   /*
>* Re-enable sampling timer when GPU goes active.
>*/
> - __i915_pmu_maybe_start_timer(pmu);
> + if (pmu->unparked == 0)
> + __i915_pmu_maybe_start_timer(pmu);
> +
> + pmu->unparked |= BIT(gt->info.id);
>
>   spin_unlock_irq(>lock);
>  }
> @@ -438,6 +443,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer 
> *hrtimer)
>*/
>
>   for_each_gt(gt, i915, i) {
> + if (!(pmu->unparked & BIT(i)))
> + continue;
> +

This is not correct. In this series we are at least sampling frequencies
(calling frequency_sample) even when GT is parked. So these 3 lines should be
deleted. engines_sample will get called and will return without doing
anything if engine events are disabled.

Thanks.
--
Ashutosh


>   engines_sample(gt, period_ns);
>
>   if (i == 0) /* FIXME */
> diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
> index a686fd7ccedf..3a811266ac6a 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.h
> +++ b/drivers/gpu/drm/i915/i915_pmu.h
> @@ -76,6 +76,10 @@ struct i915_pmu {
>* @lock: Lock protecting enable mask and ref count handling.
>*/
>   spinlock_t lock;
> + /**
> +  * @unparked: GT unparked mask.
> +  */
> + unsigned int unparked;
>   /**
>* @timer: Timer for internal i915 PMU sampling.
>*/
> --
> 2.36.1
>

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/hwmon: Silence UBSAN uninitialized bool variable warning (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/hwmon: Silence UBSAN uninitialized bool variable warning (rev2)
URL   : https://patchwork.freedesktop.org/series/117591/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13143 -> Patchwork_117591v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/index.html

Participating hosts (38 -> 38)
--

  Additional (1): fi-kbl-soraka 
  Missing(1): fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_117591v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_pm_backlight@basic-brightness@edp-1:
- bat-rplp-1: NOTRUN -> [ABORT][3] ([i915#7077])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/bat-rplp-1/igt@i915_pm_backlight@basic-brightn...@edp-1.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][4] ([i915#1886] / [i915#7913])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][5] -> [ABORT][6] ([i915#7911] / [i915#7920] / 
[i915#7953] / [i915#7982])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rpls-1/igt@i915_selftest@l...@requests.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/bat-rpls-1/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][7] ([i915#6367])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/bat-rpls-2/igt@i915_selftest@l...@slpc.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][8] ([i915#6687])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271]) +15 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-soraka:  NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4579])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/fi-kbl-soraka/igt@kms_setm...@basic-clone-single-crtc.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][11] ([i915#5334]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][13] ([i915#4983] / [i915#7461] / [i915#7913] 
/ [i915#8347]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rpls-2/igt@i915_selftest@l...@reset.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/bat-rpls-2/igt@i915_selftest@l...@reset.html

  
 Warnings 

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [ABORT][15] ([i915#4579] / [i915#8260]) -> [SKIP][16] 
([i915#3555] / [i915#4579])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117591v2/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6687]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tc: Add a workaround for an IOM/TCSS firmware hang issue (rev13)

[Patchwork]

== Series Details ==

Series: drm/i915/tc: Add a workaround for an IOM/TCSS firmware hang issue 
(rev13)
URL   : https://patchwork.freedesktop.org/series/117004/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13143 -> Patchwork_117004v13


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/index.html

Participating hosts (38 -> 37)
--

  Missing(1): fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_117004v13 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-x1275:   [PASS][1] -> [DMESG-FAIL][2] ([i915#5334] / 
[i915#7872])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/fi-kbl-x1275/igt@i915_selftest@live@gt_heartbeat.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/fi-kbl-x1275/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_lrc:
- bat-dg2-11: [PASS][3] -> [INCOMPLETE][4] ([i915#7609] / 
[i915#7913] / [i915#7953])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@slpc:
- bat-rpls-1: NOTRUN -> [DMESG-WARN][5] ([i915#6367] / [i915#7953])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/bat-rpls-1/igt@i915_selftest@l...@slpc.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][6] ([i915#6687])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][7] ([i915#6687] / [i915#7953] / 
[i915#7978])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#1845] / [i915#5354]) +2 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][9] ([i915#5334]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@requests:
- {bat-mtlp-8}:   [ABORT][11] ([i915#4983] / [i915#7920] / [i915#7953]) 
-> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-mtlp-8/igt@i915_selftest@l...@requests.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/bat-mtlp-8/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][13] ([i915#4983] / [i915#7461] / [i915#7913] 
/ [i915#8347]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rpls-2/igt@i915_selftest@l...@reset.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/bat-rpls-2/igt@i915_selftest@l...@reset.html
- bat-rpls-1: [ABORT][15] ([i915#4983] / [i915#7461] / [i915#7953] 
/ [i915#8347] / [i915#8384]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rpls-1/igt@i915_selftest@l...@reset.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117004v13/bat-rpls-1/igt@i915_selftest@l...@reset.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
  [i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
  [i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
  [i915#7953]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tc: Add a workaround for an IOM/TCSS firmware hang issue (rev13)

[Patchwork]

== Series Details ==

Series: drm/i915/tc: Add a workaround for an IOM/TCSS firmware hang issue 
(rev13)
URL   : https://patchwork.freedesktop.org/series/117004/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tc: Add a workaround for an IOM/TCSS firmware hang issue (rev13)

[Patchwork]

== Series Details ==

Series: drm/i915/tc: Add a workaround for an IOM/TCSS firmware hang issue 
(rev13)
URL   : https://patchwork.freedesktop.org/series/117004/
State : warning

== Summary ==

Error: dim checkpatch failed
60bf22a36d66 drm/i915: Fix PIPEDMC disabling for a bigjoiner configuration
27a983bdef3f drm/i915: Add helpers to reference/unreference a DPLL for a CRTC
67301cdfc6bc drm/i915: Make the CRTC state consistent during sanitize-disabling
623cdeeb6183 drm/i915: Update connector atomic state before crtc 
sanitize-disabling
d81c1ac81d72 drm/i915: Separate intel_crtc_disable_noatomic_begin/complete()
99046a224e99 drm/i915: Factor out set_encoder_for_connector()
7e41b9a1010b drm/i915: Add support for disabling any CRTCs during HW 
readout/sanitization
86bba6efdb76 drm/i915/dp: Add link training debug and error printing helpers
-:34: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#34: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:30:
+#define LT_MSG_ARGS(_intel_dp, _dp_phy)
(_intel_dp)->attached_connector->base.base.id, \
+   
(_intel_dp)->attached_connector->base.name, \
+   
dp_to_dig_port(_intel_dp)->base.base.base.id, \
+   
dp_to_dig_port(_intel_dp)->base.base.name, \
+   drm_dp_phy_name(_dp_phy)

-:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_intel_dp' - possible 
side-effects?
#34: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:30:
+#define LT_MSG_ARGS(_intel_dp, _dp_phy)
(_intel_dp)->attached_connector->base.base.id, \
+   
(_intel_dp)->attached_connector->base.name, \
+   
dp_to_dig_port(_intel_dp)->base.base.base.id, \
+   
dp_to_dig_port(_intel_dp)->base.base.name, \
+   drm_dp_phy_name(_dp_phy)

-:40: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_intel_dp' - possible 
side-effects?
#40: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:36:
+#define lt_dbg(_intel_dp, _dp_phy, _format, ...) \
+   drm_dbg_kms(_to_i915(_intel_dp)->drm, \
+   LT_MSG_PREFIX _format, \
+   LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__)

-:45: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_intel_dp' - possible 
side-effects?
#45: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:41:
+#define lt_err(_intel_dp, _dp_phy, _format, ...) \
+   drm_err(_to_i915(_intel_dp)->drm, \
+   LT_MSG_PREFIX _format, \
+   LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__)

total: 1 errors, 0 warnings, 3 checks, 758 lines checked
faf11aab775b drm/i915/dp: Convert link training error to debug message on 
disconnected sink
-:39: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_intel_dp' - possible 
side-effects?
#39: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:41:
+#define lt_err(_intel_dp, _dp_phy, _format, ...) do { \
+   if (intel_digital_port_connected(_to_dig_port(_intel_dp)->base)) \
+   drm_err(_to_i915(_intel_dp)->drm, \
+   LT_MSG_PREFIX _format, \
+   LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__); \
+   else \
+   lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## 
__VA_ARGS__); \
+} while (0)

-:39: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_dp_phy' - possible 
side-effects?
#39: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:41:
+#define lt_err(_intel_dp, _dp_phy, _format, ...) do { \
+   if (intel_digital_port_connected(_to_dig_port(_intel_dp)->base)) \
+   drm_err(_to_i915(_intel_dp)->drm, \
+   LT_MSG_PREFIX _format, \
+   LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__); \
+   else \
+   lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## 
__VA_ARGS__); \
+} while (0)

-:39: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_format' - possible 
side-effects?
#39: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:41:
+#define lt_err(_intel_dp, _dp_phy, _format, ...) do { \
+   if (intel_digital_port_connected(_to_dig_port(_intel_dp)->base)) \
+   drm_err(_to_i915(_intel_dp)->drm, \
+   LT_MSG_PREFIX _format, \
+   LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__); \
+   else \
+   lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## 
__VA_ARGS__); \
+} while (0)

total: 0 errors, 0 warnings, 3 checks, 18 lines checked
98e16a313580 drm/i915/dp: Prevent link training fallback on disconnected port
3af810d57bfe drm/i915/dp: Factor out intel_dp_get_active_pipes()
85ba493a190a drm/i915: Factor out a helper for handling atomic modeset 
locks/state
Traceback (most recent call last):
  File 

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

[Umesh Nerlige Ramappa]

On Fri, May 12, 2023 at 11:56:18AM +0100, Tvrtko Ursulin wrote:


On 12/05/2023 02:08, Dixit, Ashutosh wrote:

On Fri, 05 May 2023 17:58:15 -0700, Umesh Nerlige Ramappa wrote:


From: Tvrtko Ursulin 

Reserve some bits in the counter config namespace which will carry the
tile id and prepare the code to handle this.

No per tile counters have been added yet.

v2:
- Fix checkpatch issues
- Use 4 bits for gt id in non-engine counters. Drop FIXME.
- Set MAX GTs to 4. Drop FIXME.

Signed-off-by: Tvrtko Ursulin 
Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/i915_pmu.c | 150 +++-
 drivers/gpu/drm/i915/i915_pmu.h |   9 +-
 include/uapi/drm/i915_drm.h |  17 +++-
 3 files changed, 129 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 669a42e44082..12b2f3169abf 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -56,11 +56,21 @@ static bool is_engine_config(u64 config)
return config < __I915_PMU_OTHER(0);
 }

+static unsigned int config_gt_id(const u64 config)
+{
+   return config >> __I915_PMU_GT_SHIFT;
+}
+
+static u64 config_counter(const u64 config)
+{
+   return config & ~(~0ULL << __I915_PMU_GT_SHIFT);


ok, but another possibility:

return config & ~REG_GENMASK64(63, __I915_PMU_GT_SHIFT);


It's not a register so no. :) GENMASK_ULL maybe but meh.


leaving as is.




+}
+
 static unsigned int other_bit(const u64 config)
 {
unsigned int val;

-   switch (config) {
+   switch (config_counter(config)) {
case I915_PMU_ACTUAL_FREQUENCY:
val =  __I915_PMU_ACTUAL_FREQUENCY_ENABLED;
break;
@@ -78,15 +88,20 @@ static unsigned int other_bit(const u64 config)
return -1;
}

-   return I915_ENGINE_SAMPLE_COUNT + val;
+   return I915_ENGINE_SAMPLE_COUNT +
+  config_gt_id(config) * __I915_PMU_TRACKED_EVENT_COUNT +
+  val;
 }

 static unsigned int config_bit(const u64 config)
 {
-   if (is_engine_config(config))
+   if (is_engine_config(config)) {
+   GEM_BUG_ON(config_gt_id(config));


This GEM_BUG_ON is not needed since:

static bool is_engine_config(u64 config)
{
return config < __I915_PMU_OTHER(0);
}


True!


dropping BUG_ON




+
return engine_config_sample(config);
-   else
+   } else {
return other_bit(config);
+   }
 }

 static u64 config_mask(u64 config)
@@ -104,6 +119,18 @@ static unsigned int event_bit(struct perf_event *event)
return config_bit(event->attr.config);
 }

+static u64 frequency_enabled_mask(void)
+{
+   unsigned int i;
+   u64 mask = 0;
+
+   for (i = 0; i < I915_PMU_MAX_GTS; i++)
+   mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) |
+   config_mask(__I915_PMU_REQUESTED_FREQUENCY(i));
+
+   return mask;
+}
+
 static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
 {
struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
@@ -120,9 +147,7 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool 
gpu_active)
 * Mask out all the ones which do not need the timer, or in
 * other words keep all the ones that could need the timer.
 */
-   enable &= config_mask(I915_PMU_ACTUAL_FREQUENCY) |
- config_mask(I915_PMU_REQUESTED_FREQUENCY) |
- ENGINE_SAMPLE_MASK;
+   enable &= frequency_enabled_mask() | ENGINE_SAMPLE_MASK;


u32 enable & u64 frequency_enabled_mask

ugly but ok I guess? Or change enable to u64?


making pmu->enable u64 as well as other places where it is assigned to 
local variables.




Hmm.. yes very ugly. Could have been an accident which happened to 
work because there is a single timer (not per tile).


Happened to work because the frequency mask does not spill over to the 
upper 32 bits (even for multi tile).


- START_SECTION 


Similar issue in frequency_sampling_enabled too. Gt_id argument to it 
seems pointless.


Not sure why it's pointless. We need the gt_id to determine the right 
mask for that specific gt. If it's not enabled, then we just return 
without pm_get and async put (like you mention later). 


And this piece of code is called within for_each_gt.



So I now think whole frequency_enabled_mask() is just pointless and 
should be removed. And then pmu_needs_time code can stay as is. 
Possibly add a config_mask_32 helper which ensures no bits in upper 32 
bits are returned.


That is if we are happy for the frequency_sampling_enabled returning 
true for all gts, regardless of which ones actually have frequency 
sampling enabled.


Or if we want to implement it as I probably have intended, we will 
need to add some gt bits into pmu->enable. Maybe reserve top four same 
as with config counters.


Nope. 

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/dpll: drop a useless I915_STATE_WARN_ON() (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/dpll: drop a useless 
I915_STATE_WARN_ON() (rev2)
URL   : https://patchwork.freedesktop.org/series/117685/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13143 -> Patchwork_117685v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/index.html

Participating hosts (38 -> 36)
--

  Missing(2): fi-apl-guc fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_117685v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_backlight@basic-brightness@edp-1:
- bat-rplp-1: NOTRUN -> [ABORT][1] ([i915#7077])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/bat-rplp-1/igt@i915_pm_backlight@basic-brightn...@edp-1.html

  * igt@i915_selftest@live@gt_engines:
- bat-atsm-1: [PASS][2] -> [FAIL][3] ([i915#6268])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-atsm-1/igt@i915_selftest@live@gt_engines.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/bat-atsm-1/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@slpc:
- bat-rpls-1: NOTRUN -> [DMESG-WARN][4] ([i915#6367] / [i915#7953])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/bat-rpls-1/igt@i915_selftest@l...@slpc.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][5] ([i915#6687] / [i915#7953] / 
[i915#7978])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1:
- bat-dg2-8:  [PASS][6] -> [FAIL][7] ([i915#7932])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-1:
- fi-rkl-11600:   [PASS][8] -> [FAIL][9] ([fdo#103375])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/fi-rkl-11600/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-1.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/fi-rkl-11600/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-1.html

  
 Possible fixes 

  * igt@i915_selftest@live@reset:
- bat-rpls-1: [ABORT][10] ([i915#4983] / [i915#7461] / [i915#7953] 
/ [i915#8347] / [i915#8384]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rpls-1/igt@i915_selftest@l...@reset.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/bat-rpls-1/igt@i915_selftest@l...@reset.html

  * igt@i915_selftest@live@slpc:
- {bat-mtlp-6}:   [DMESG-WARN][12] ([i915#6367] / [i915#7953]) -> 
[PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-mtlp-6/igt@i915_selftest@l...@slpc.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/bat-mtlp-6/igt@i915_selftest@l...@slpc.html

  
 Warnings 

  * igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][14] ([i915#4983] / [i915#7461] / [i915#7913] 
/ [i915#8347]) -> [ABORT][15] ([i915#4983] / [i915#7461] / [i915#7913] / 
[i915#7981] / [i915#8347])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rpls-2/igt@i915_selftest@l...@reset.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/bat-rpls-2/igt@i915_selftest@l...@reset.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [ABORT][16] ([i915#4579] / [i915#8260]) -> [SKIP][17] 
([i915#3555] / [i915#4579])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13143/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117685v2/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
  [i915#7461]: 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/dpll: drop a useless I915_STATE_WARN_ON() (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/4] drm/i915/dpll: drop a useless 
I915_STATE_WARN_ON() (rev2)
URL   : https://patchwork.freedesktop.org/series/117685/
State : warning

== Summary ==

Error: dim checkpatch failed
c7e4ac68951f drm/i915/dpll: drop a useless I915_STATE_WARN_ON()
828667e88c08 drm/i915/crtc: replace I915_STATE_WARN_ON() with I915_STATE_WARN()
4f60e04a5946 drm/i915/display: remove I915_STATE_WARN_ON()
b8924587748c drm/i915/display: add i915 parameter to I915_STATE_WARN()
-:180: WARNING:LONG_LINE: line length of 146 exceeds 100 columns
#180: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:1197:
+   (intel_de_read(dev_priv, UTIL_PIN_CTL) & 
(UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | 
UTIL_PIN_MODE_PWM),

-:502: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#502: FILE: drivers/gpu/drm/i915/display/intel_pch_display.c:90:
+   intel_lvds_port_enabled(dev_priv, PCH_LVDS, _pipe) 
&& port_pipe == pipe,

total: 0 errors, 2 warnings, 0 checks, 467 lines checked

Re: [Intel-gfx] [PATCH v3 7/8] drm/i915/mtl: Add support for PM DEMAND

[Gustavo Sousa]

Quoting Govindapillai, Vinod (2023-05-11 20:24:55)
>Hello
>
>Thanks for the comments. Pls see some inline replies..
>
>On Thu, 2023-04-27 at 17:24 -0300, Gustavo Sousa wrote:
>> Quoting Vinod Govindapillai (2023-04-27 12:00:15)
>> > From: Mika Kahola 
>> > 
>> > Display14 introduces a new way to instruct the PUnit with
>> > power and bandwidth requirements of DE. Add the functionality
>> > to program the registers and handle waits using interrupts.
>> > The current wait time for timeouts is programmed for 10 msecs to
>> > factor in the worst case scenarios. Changes made to use REG_BIT
>> > for a register that we touched(GEN8_DE_MISC_IER _MMIO).
>> > 
>> > Wa_14016740474 is added which applies to Xe_LPD+ display
>> > 
>> > v2: checkpatch warning fixes, simplify program pmdemand part
>> > 
>> > v3: update to dbufs and pipes values to pmdemand register(stan)
>> >    Removed the macro usage in update_pmdemand_values()
>> > 
>> > Bspec: 66451, 64636, 64602, 64603
>> > Cc: Matt Atwood 
>> > Cc: Matt Roper 
>> > Cc: Lucas De Marchi 
>> > Cc: Gustavo Sousa 
>> > Signed-off-by: José Roberto de Souza 
>> > Signed-off-by: Radhakrishna Sripada 
>> > Signed-off-by: Gustavo Sousa 
>> > Signed-off-by: Mika Kahola 
>> > Signed-off-by: Vinod Govindapillai 
>> > ---
>> > drivers/gpu/drm/i915/Makefile |   3 +-
>> > drivers/gpu/drm/i915/display/intel_display.c  |   7 +
>> > .../gpu/drm/i915/display/intel_display_core.h |   6 +
>> > .../drm/i915/display/intel_display_driver.c   |   7 +
>> > .../drm/i915/display/intel_display_power.c    |   8 +
>> > drivers/gpu/drm/i915/display/intel_pmdemand.c | 455 ++
>> > drivers/gpu/drm/i915/display/intel_pmdemand.h |  24 +
>> > drivers/gpu/drm/i915/i915_irq.c   |  21 +-
>> > drivers/gpu/drm/i915/i915_reg.h   |  36 +-
>> > 9 files changed, 562 insertions(+), 5 deletions(-)
>> > create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
>> > create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
>> > 
>> > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>> > index 9af76e376ca9..eb899fa86e51 100644
>> > --- a/drivers/gpu/drm/i915/Makefile
>> > +++ b/drivers/gpu/drm/i915/Makefile
>> > @@ -281,7 +281,8 @@ i915-y += \
>> >    display/i9xx_wm.o \
>> >    display/skl_scaler.o \
>> >    display/skl_universal_plane.o \
>> > -  display/skl_watermark.o
>> > +  display/skl_watermark.o \
>> > +  display/intel_pmdemand.o
>> > i915-$(CONFIG_ACPI) += \
>> >    display/intel_acpi.o \
>> >    display/intel_opregion.o
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> > b/drivers/gpu/drm/i915/display/intel_display.c
>> > index bf391a6cd8d6..f98e235fadc6 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> > @@ -99,6 +99,7 @@
>> > #include "intel_pcode.h"
>> > #include "intel_pipe_crc.h"
>> > #include "intel_plane_initial.h"
>> > +#include "intel_pmdemand.h"
>> > #include "intel_pps.h"
>> > #include "intel_psr.h"
>> > #include "intel_sdvo.h"
>> > @@ -6306,6 +6307,10 @@ int intel_atomic_check(struct drm_device *dev,
>> >    return ret;
>> >    }
>> > 
>> > +  ret = intel_pmdemand_atomic_check(state);
>> > +  if (ret)
>> > +  goto fail;
>> > +
>> >    ret = intel_atomic_check_crtcs(state);
>> >    if (ret)
>> >    goto fail;
>> > @@ -6960,6 +6965,7 @@ static void intel_atomic_commit_tail(struct 
>> > intel_atomic_state *state)
>> >    }
>> > 
>> >    intel_sagv_pre_plane_update(state);
>> > +  intel_pmdemand_pre_plane_update(state);
>> > 
>> >    /* Complete the events for pipes that have now been disabled */
>> >    for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> > @@ -7070,6 +7076,7 @@ static void intel_atomic_commit_tail(struct 
>> > intel_atomic_state *state)
>> >    intel_verify_planes(state);
>> > 
>> >    intel_sagv_post_plane_update(state);
>> > +  intel_pmdemand_post_plane_update(state);
>> > 
>> >    drm_atomic_helper_commit_hw_done(>base);
>> > 
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> > b/drivers/gpu/drm/i915/display/intel_display_core.h
>> > index 9f66d734edf6..9471a052aa57 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> > @@ -345,6 +345,12 @@ struct intel_display {
>> >    struct intel_global_obj obj;
>> >    } dbuf;
>> > 
>> > +  struct {
>> > +  wait_queue_head_t waitqueue;
>> > +  struct mutex lock;
>> > +  struct intel_global_obj obj;
>> > +  } pmdemand;
>> > +
>> >    struct {
>> >    /*
>> >     * dkl.phy_lock protects against concurrent access of the
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
>> > b/drivers/gpu/drm/i915/display/intel_display_driver.c
>> > index 

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Silence UBSAN uninitialized bool variable warning

[Dixit, Ashutosh]

On Fri, 12 May 2023 02:33:33 -0700, Andi Shyti wrote:
>
Hi Andi,
>
> On Thu, May 11, 2023 at 10:43:30AM -0700, Dixit, Ashutosh wrote:
> > On Wed, 10 May 2023 11:36:06 -0700, Ashutosh Dixit wrote:
> > >
> > > Loading i915 on UBSAN enabled kernels (CONFIG_UBSAN/CONFIG_UBSAN_BOOL)
> > > causes the following warning:
> > >
> > >   UBSAN: invalid-load in drivers/gpu/drm/i915/gt/uc/intel_uc.c:558:2
> > >   load of value 255 is not a valid value for type '_Bool'
> > >   Call Trace:
> > >dump_stack_lvl+0x57/0x7d
> > >ubsan_epilogue+0x5/0x40
> > >__ubsan_handle_load_invalid_value.cold+0x43/0x48
> > >__uc_init_hw+0x76a/0x903 [i915]
> > >...
> > >i915_driver_probe+0xfb1/0x1eb0 [i915]
> > >i915_pci_probe+0xbe/0x2d0 [i915]
> > >
> > > The warning happens because during probe i915_hwmon is still not available
> > > which results in the output boolean variable *old remaining
> > > uninitialized.
> >
> > Note that the variable was uninitialized in this case but it was never used
> > uninitialized (the variable was not needed when it was uninitialized). So
> > there was no bug in the code. UBSAN warning is just complaining about the
> > uninitialized variable being passed into a function (where it is not used).
> >
> > Also the variable can be initialized in the caller (__uc_init_hw) too and
> > it will fix this issue. However in __uc_init_hw the assumption is that the
> > variable will be initialized in the callee (i915_hwmon_power_max_disable),
> > so that is how I have done it in this patch.
> >
> > I thought these clarifications will help with the review.
>
> I think we should not just consider what's now but also what can
> come later. The use of pl1en is not 100% future proof and
> therefore your patch, even though now is not fixing anything,
> might avoid wrong uses in the future.
>
> I'm just wondering, though, why not initializing the variable at
> it's declaration. As you wish.

OK, in v2 I went ahead and did just that (initializing the variable at the
declaration). I was splitting hair too much :/

> Reviewed-by: Andi Shyti 

Thanks.
--
Ashutosh


> >
> > > Silence the warning by initializing the variable to an arbitrary value.
> > >
> > > Signed-off-by: Ashutosh Dixit 
> > > ---
> > >  drivers/gpu/drm/i915/i915_hwmon.c | 5 -
> > >  1 file changed, 4 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c 
> > > b/drivers/gpu/drm/i915/i915_hwmon.c
> > > index a3bdd9f68a458..685663861bc0b 100644
> > > --- a/drivers/gpu/drm/i915/i915_hwmon.c
> > > +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> > > @@ -502,8 +502,11 @@ void i915_hwmon_power_max_disable(struct 
> > > drm_i915_private *i915, bool *old)
> > >   struct i915_hwmon *hwmon = i915->hwmon;
> > >   u32 r;
> > >
> > > - if (!hwmon || !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit))
> > > + if (!hwmon || !i915_mmio_reg_valid(hwmon->rg.pkg_rapl_limit)) {
> > > + /* Fix uninitialized bool variable warning */
> > > + *old = false;
> > >   return;
> > > + }
> > >
> > >   mutex_lock(>hwmon_lock);
> > >
> > > --
> > > 2.38.0
> > >

[Intel-gfx] [PATCH v2] drm/i915/hwmon: Silence UBSAN uninitialized bool variable warning

[Ashutosh Dixit]

Loading i915 on UBSAN enabled kernels (CONFIG_UBSAN/CONFIG_UBSAN_BOOL)
causes the following warning:

  UBSAN: invalid-load in drivers/gpu/drm/i915/gt/uc/intel_uc.c:558:2
  load of value 255 is not a valid value for type '_Bool'
  Call Trace:
   dump_stack_lvl+0x57/0x7d
   ubsan_epilogue+0x5/0x40
   __ubsan_handle_load_invalid_value.cold+0x43/0x48
   __uc_init_hw+0x76a/0x903 [i915]
   ...
   i915_driver_probe+0xfb1/0x1eb0 [i915]
   i915_pci_probe+0xbe/0x2d0 [i915]

The warning happens because during probe i915_hwmon is still not available
which results in the output boolean variable *old remaining
uninitialized. Silence the warning by initializing the variable to an
arbitrary value.

v2: Move variable initialization to the declaration (Andi)

Signed-off-by: Ashutosh Dixit 
Reviewed-by: Andi Shyti 
Reviewed-by: Andrzej Hajda 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 1381943b8973d..c8b9cbb7ba3a9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -465,7 +465,7 @@ static int __uc_init_hw(struct intel_uc *uc)
struct intel_guc *guc = >guc;
struct intel_huc *huc = >huc;
int ret, attempts;
-   bool pl1en;
+   bool pl1en = false;
 
GEM_BUG_ON(!intel_uc_supports_guc(uc));
GEM_BUG_ON(!intel_uc_wants_guc(uc));
-- 
2.38.0

Re: [Intel-gfx] [PATCH 6/6] drm/i915/pmu: Export counters from all tiles

[Dixit, Ashutosh]

On Fri, 12 May 2023 11:53:32 -0700, Umesh Nerlige Ramappa wrote:
>
> On Fri, May 12, 2023 at 10:08:58AM -0700, Dixit, Ashutosh wrote:
> > On Fri, 12 May 2023 03:57:35 -0700, Tvrtko Ursulin wrote:
> >>
> >>
> >> On 11/05/2023 19:57, Dixit, Ashutosh wrote:
> >> > On Fri, 05 May 2023 17:58:16 -0700, Umesh Nerlige Ramappa wrote:
> >> >>
> >> >
> >> > One drive-by comment:
> >> >
> >> >> diff --git a/drivers/gpu/drm/i915/i915_pmu.c 
> >> >> b/drivers/gpu/drm/i915/i915_pmu.c
> >> >> index 12b2f3169abf..284e5c5b97bb 100644
> >> >> --- a/drivers/gpu/drm/i915/i915_pmu.c
> >> >> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> >> >> @@ -546,8 +546,9 @@ config_status(struct drm_i915_private *i915, u64 
> >> >> config)
> >> >> struct intel_gt *gt = to_gt(i915);
> >> >>
> >> >> unsigned int gt_id = config_gt_id(config);
> >> >> +   unsigned int max_gt_id = HAS_EXTRA_GT_LIST(i915) ? 1 : 0;
> >> >
> >> > But in Patch 5 we have:
> >> >
> >> > #define I915_PMU_MAX_GTS (4)
> >>
> >> AFAIR that one is just to size the internal arrays, while max_gt_id is to
> >> report to userspace which events are present.
> >
> > Hmm, apart from the #defines's in i915_drm.h in Patch 5, not seeing
> > anything else reported to userspace about which events are present.
>
> Ex: We have only gt0 and gt1 on MTL. When user configures an event (sets
> event id, tile id etc on the config parameter) and calls the
> perf_event_open, it results in i915_pmu_event_init() -> config_status()
> which will return an ENOENT if the event was for say gt2 or gt3. This is
> for runtime check only.

Ah ok, sorry I missed that. In that case what we have above is fine. xe has
a tile_count field but in i915 there's no easy way to find number of gt's,
short of using for_each_gt() and incrementing a count. That seems like an
overkill. So maybe what we have above is fine.

Thanks.
--
Ashutosh


>
> >
> > Also, we already have I915_MAX_GT, we shouldn't need I915_PMU_MAX_GTS, or
> > at least:
> >
> > #define I915_PMU_MAX_GTS I915_MAX_GT
> >
> > Better to use things uniformly. If we want I915_PMU_MAX_GTS to be 2 instead
> > of I915_MAX_GT (but why?, below is just a check) let's do
> >
> > #define I915_PMU_MAX_GTS 2
> >
> > And use that in the code above. But I think we should just use I915_MAX_GT.
>
> Agree,
>
> Thanks,
> Umesh
> >
> > Thanks.
> > --
> > Ashutosh
> >
> >
> >> >
> >> >>
> >> >> -   if (gt_id)
> >> >> +   if (gt_id > max_gt_id)
> >> >> return -ENOENT;
> >> >>
> >> >> switch (config_counter(config)) {
> >> >> @@ -561,6 +562,8 @@ config_status(struct drm_i915_private *i915, u64 
> >> >> config)
> >> >> return -ENODEV;
> >> >> break;
> >> >> case I915_PMU_INTERRUPTS:
> >> >> +   if (gt_id)
> >> >> +   return -ENOENT;
> >> >> break;
> >> >> case I915_PMU_RC6_RESIDENCY:
> >> >> if (!gt->rc6.supported)

[Intel-gfx] [PATCH v5 14/14] drm/i915/tc: Reset TypeC PHYs left enabled in DP-alt mode after the sink disconnects

[Imre Deak]

If the output on a DP-alt link with its sink disconnected is kept
enabled for too long (about 20 sec), then some IOM/TCSS firmware timeout
will cause havoc on the PCI bus, at least for other GFX devices on it
which will stop powering up. Since user space is not guaranteed to do a
disabling modeset in time, switch such disconnected but active links to
TBT mode - which is without such shortcomings - with a 2 second delay.

If the above condition is detected already during the driver load/system
resume sanitization step disable the output instead, as at that point no
user space or kernel client depends on a consistent output state yet and
because subsequent atomic modeset on such connectors - without the
actual sink capabilities available - can fail.

An active/disconnected port as above will also block the HPD status of
other active/disconnected ports to get updated (stuck in the connected
state), until the former port is disabled, its PHY is disconnected and
a ~10 ms delay has elapsed. This means the link state for all TypeC
ports/CRTCs must be rechecked after a CRTC is disabled due to the above
reason. For this disconnect the PHY synchronously after the CRTC/port is
disabled and recheck all CRTCs for the above condition whenever such a
port is disabled.

To account for a race condition during driver loading where the sink is
disconnected after the above sanitization step and before the HPD
interrupts get enabled, do an explicit check/link reset if needed from
the encoder's late_register hook, which is called after the HPD
interrupts are enabled already.

v2:
- Handle an active/disconnected port blocking the HPD state update of
  another active/disconnected port.
- Cancel the delayed work resetting the link also from the encoder
  enable/suspend/shutdown hooks.
- Rebase on the earlier intel_modeset_lock_ctx_retry() addition,
  fixing here the missed atomic state reset in case of a retry.
- Fix handling of an error return from intel_atomic_get_crtc_state().
- Recheck if the port needs to be reset after all the atomic state
  is locked and async commits are waited on.

v3:
- Add intel_crtc_needs_link_reset(), instead of open-coding it,
  keep intel_crtc_has_encoders(). (Ville)
- Fix state dumping and use a bitmask to track disabled CRTCs in
  intel_sanitize_all_crtcs(). (Ville)
- Set internal in intel_atomic_state right after allocating it.
  (Ville)
- Recheck all CRTCs (not yet force-disabled) after a CRTC is
  force-disabled for any reason (not only due to a link state)
  in intel_sanitize_all_crtcs().
- Reduce delay after CRTC disabling to 20ms, and use the simpler
  msleep().
- Clarify code comment about HPD behaviour in
  intel_sanitize_all_crtcs().
- Move all the TC link reset logic to intel_tc.c .
- Cancel the link reset work synchronously during system suspend,
  driver unload and shutdown.

v4:
- Rebased on previous patch, which allows calling the TC port
  suspend/cleanup handlers without modeset locks held; remove the
  display driver suspended assert from the link reset work
  accordingly.

v5: (Ville)
- Remove reset work canceling from intel_ddi_pre_pll_enable().
- Track a crtc vs. pipe mask in intel_sanitize_all_crtcs().
- Add reset_link_commit() to clarify the
  intel_modeset_lock_ctx_retry loop.

Cc: Kai-Heng Feng 
Cc: Ville Syrjälä 
Tested-by: Kai-Heng Feng 
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5860
Reviewed-by: Ville Syrjälä 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_ddi.c  |  30 +++-
 drivers/gpu/drm/i915/display/intel_dp.c   |   6 +-
 drivers/gpu/drm/i915/display/intel_dp.h   |   3 +
 .../drm/i915/display/intel_modeset_setup.c|  87 --
 drivers/gpu/drm/i915/display/intel_tc.c   | 159 +-
 drivers/gpu/drm/i915/display/intel_tc.h   |   5 +-
 6 files changed, 265 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7d09bd2412352..3baf329343dab 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3313,6 +3313,8 @@ static void intel_disable_ddi(struct intel_atomic_state 
*state,
  const struct intel_crtc_state *old_crtc_state,
  const struct drm_connector_state *old_conn_state)
 {
+   intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder));
+
intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
 
if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
@@ -4232,9 +4234,19 @@ static void intel_ddi_encoder_reset(struct drm_encoder 
*encoder)
intel_tc_port_init_mode(dig_port);
 }
 
+static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder)
+{
+   struct intel_encoder *encoder = to_intel_encoder(_encoder);
+
+   intel_tc_port_link_reset(enc_to_dig_port(encoder));
+
+   return 0;
+}
+
 static const struct drm_encoder_funcs 

[Intel-gfx] [PATCH v5 13/14] drm/i915/tc: Call TypeC port flush_work/cleanup without modeset locks held

[Imre Deak]

Call the TypeC port flush_work and cleanup handlers without the modeset
locks held. These don't require the locks, as the work takes - as it
should be able to at any point in time - any locks it needs and by the
time cleanup is called and after cleanup returns the encoder is not in
use.

This is required by the next patch canceling a TypeC port work
synchronously during encoder suspend and shutdown, where the work can
take modeset locks as well, hence the canceling must be done without
holding the locks.

I also considered moving the modeset locking down to each encoder
suspend()/shutdown() hook instead, however locking the full modeset
state for each encoder separately would be odd, and the bigger change -
affecting all encoders - is beyond the scope of this patchset.

v2:
- Add a TODO: comment to remove modeset locks if no encoder depends
  on this. (Ville)

Cc: Ville Syrjälä 
Reviewed-by: Ville Syrjälä 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_ddi.c  | 27 +--
 .../drm/i915/display/intel_display_types.h| 12 +
 drivers/gpu/drm/i915/i915_driver.c| 16 +++
 3 files changed, 41 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 813be957ed11b..7d09bd2412352 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4617,31 +4617,27 @@ static bool intel_ddi_is_tc(struct drm_i915_private 
*i915, enum port port)
 
 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
 {
-   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-   struct drm_i915_private *i915 = dp_to_i915(intel_dp);
-   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-   enum phy phy = intel_port_to_phy(i915, encoder->port);
-
intel_dp_encoder_suspend(encoder);
+}
 
-   if (!intel_phy_is_tc(i915, phy))
-   return;
+static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder 
*encoder)
+{
+   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 
intel_tc_port_flush_work(dig_port);
 }
 
 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
 {
-   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-   struct drm_i915_private *i915 = dp_to_i915(intel_dp);
-   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-   enum phy phy = intel_port_to_phy(i915, encoder->port);
-
intel_dp_encoder_shutdown(encoder);
intel_hdmi_encoder_shutdown(encoder);
+}
 
-   if (!intel_phy_is_tc(i915, phy))
-   return;
+static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder 
*encoder)
+{
+   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 
intel_tc_port_cleanup(dig_port);
 }
@@ -4908,6 +4904,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, 
enum port port)
is_legacy ? "legacy" : "non-legacy");
}
 
+   encoder->suspend_complete = 
intel_ddi_tc_encoder_suspend_complete;
+   encoder->shutdown_complete = 
intel_ddi_tc_encoder_shutdown_complete;
+
if (intel_tc_port_init(dig_port, is_legacy) < 0)
goto err;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 270c4c84a2920..88b2a55d19f21 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -233,13 +233,25 @@ struct intel_encoder {
 * Called during system suspend after all pending requests for the
 * encoder are flushed (for example for DP AUX transactions) and
 * device interrupts are disabled.
+* All modeset locks are held while the hook is called.
 */
void (*suspend)(struct intel_encoder *);
+   /*
+* Called without the modeset locks held after the suspend() hook for
+* all encoders have been called.
+*/
+   void (*suspend_complete)(struct intel_encoder *encoder);
/*
 * Called during system reboot/shutdown after all the
 * encoders have been disabled and suspended.
+* All modeset locks are held while the hook is called.
 */
void (*shutdown)(struct intel_encoder *encoder);
+   /*
+* Called without the modeset locks held after the shutdown() hook for
+* all encoders have been called.
+*/
+   void (*shutdown_complete)(struct intel_encoder *encoder);
/*
 * Enable/disable the clock to the port.
 */
diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index fd198700272b1..522733a899463 100644

Re: [Intel-gfx] [PATCH v7 4/4] drm/i915: Allow user to set cache at BO creation

[Jordan Justen]

On 2023-05-10 15:14:16, Andi Shyti wrote:
> Hi,
> 
> On Tue, May 09, 2023 at 09:59:42AM -0700, fei.y...@intel.com wrote:
> > From: Fei Yang 
> > 
> > To comply with the design that buffer objects shall have immutable
> > cache setting through out their life cycle, {set, get}_caching ioctl's
> > are no longer supported from MTL onward. With that change caching
> > policy can only be set at object creation time. The current code
> > applies a default (platform dependent) cache setting for all objects.
> > However this is not optimal for performance tuning. The patch extends
> > the existing gem_create uAPI to let user set PAT index for the object
> > at creation time.
> > The new extension is platform independent, so UMD's can switch to using
> > this extension for older platforms as well, while {set, get}_caching are
> > still supported on these legacy paltforms for compatibility reason.
> > 
> > Cc: Chris Wilson 
> > Cc: Matt Roper 
> > Cc: Andi Shyti 
> > Signed-off-by: Fei Yang 
> > Reviewed-by: Andi Shyti 
> 
> just for a matter of completeness, this is new uapi is tested
> through the "create-ext-set-pat" test case from the "gem_create"
> igt test[1]. Can any of the igt maintainers give it a look,
> comment and ack?
> 
> The mesa merge request is here [2]. As there is a merge request
> in progress, would anyone from mesa be so kind to give an ack to
> this patch, as well?
> 
> With the mesa ack in place this patch should be ready to go and
> I'm looking forward to having it in.

I tested my MR [2] in our CI. There was some bad news, but I don't
think it needs to block these patches.

The good news was that I found that OpenGL testing with our iris
driver appeared to have ok results when using this interface.

But, our Vulkan Anvil driver was not stable with the current patches
in the Mesa MR. We will need to debug this further before using the
interface on Vulkan.

I don't suspect that this is an issue with the kernel interface, so
you can add:

Tested-by: Jordan Justen 

-Jordan

> 
> Thanks,
> Andi
> 
> [1] https://patchwork.freedesktop.org/patch/534955/?series=117185=1
> [2] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
>

Re: [Intel-gfx] [PATCH 6/6] drm/i915/pmu: Export counters from all tiles

[Umesh Nerlige Ramappa]

On Fri, May 12, 2023 at 10:08:58AM -0700, Dixit, Ashutosh wrote:

On Fri, 12 May 2023 03:57:35 -0700, Tvrtko Ursulin wrote:



On 11/05/2023 19:57, Dixit, Ashutosh wrote:
> On Fri, 05 May 2023 17:58:16 -0700, Umesh Nerlige Ramappa wrote:
>>
>
> One drive-by comment:
>
>> diff --git a/drivers/gpu/drm/i915/i915_pmu.c 
b/drivers/gpu/drm/i915/i915_pmu.c
>> index 12b2f3169abf..284e5c5b97bb 100644
>> --- a/drivers/gpu/drm/i915/i915_pmu.c
>> +++ b/drivers/gpu/drm/i915/i915_pmu.c
>> @@ -546,8 +546,9 @@ config_status(struct drm_i915_private *i915, u64 config)
>>struct intel_gt *gt = to_gt(i915);
>>
>>unsigned int gt_id = config_gt_id(config);
>> +  unsigned int max_gt_id = HAS_EXTRA_GT_LIST(i915) ? 1 : 0;
>
> But in Patch 5 we have:
>
> #define I915_PMU_MAX_GTS (4)

AFAIR that one is just to size the internal arrays, while max_gt_id is to
report to userspace which events are present.


Hmm, apart from the #defines's in i915_drm.h in Patch 5, not seeing
anything else reported to userspace about which events are present.


Ex: We have only gt0 and gt1 on MTL. When user configures an event (sets 
event id, tile id etc on the config parameter) and calls the 
perf_event_open, it results in i915_pmu_event_init() -> config_status() 
which will return an ENOENT if the event was for say gt2 or gt3. This is 
for runtime check only.




Also, we already have I915_MAX_GT, we shouldn't need I915_PMU_MAX_GTS, or
at least:

#define I915_PMU_MAX_GTS I915_MAX_GT

Better to use things uniformly. If we want I915_PMU_MAX_GTS to be 2 instead
of I915_MAX_GT (but why?, below is just a check) let's do

#define I915_PMU_MAX_GTS 2

And use that in the code above. But I think we should just use I915_MAX_GT.


Agree,

Thanks,
Umesh


Thanks.
--
Ashutosh



>
>>
>> -  if (gt_id)
>> +  if (gt_id > max_gt_id)
>>return -ENOENT;
>>
>>switch (config_counter(config)) {
>> @@ -561,6 +562,8 @@ config_status(struct drm_i915_private *i915, u64 config)
>>return -ENODEV;
>>break;
>>case I915_PMU_INTERRUPTS:
>> +  if (gt_id)
>> +  return -ENOENT;
>>break;
>>case I915_PMU_RC6_RESIDENCY:
>>if (!gt->rc6.supported)

Re: [Intel-gfx] [PATCH 3/3] drm/i915/irq: split out display irq handling

[Jani Nikula]

On Fri, 12 May 2023, Gustavo Sousa  wrote:
> Quoting Jani Nikula (2023-05-12 07:23:10)
>>Split (non-hotplug) display irq handling out of i915_irq.[ch] into
>>display/intel_display_irq.[ch].
>>
>>v2:
>>- Rebase
>>- Preserve [I915_MAX_PIPES] in functions (kernel test robot)
>>
>>Signed-off-by: Jani Nikula 


>>+void i9xx_pipestat_irq_ack(struct drm_i915_private *i915, u32 iir, u32 
>>*pipe_stats);
>
> I guess this one slipped out when fixing the error diagnosed by 
> "-Werror=array-parameter=".

Indeed, *facepalm*. I'm still rolling with gcc 10, and I believe that
was introduced in gcc 11.

> Used "git show --color-moved ..." to help me review this one and changes look
> sane to me. With the above fixed,
>
> Reviewed-by: Gustavo Sousa 

Thanks,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: add i915 parameter to I915_STATE_WARN()

[Jani Nikula]

On Fri, 12 May 2023, Rodrigo Vivi  wrote:
> On Fri, May 12, 2023 at 02:04:44PM +0300, Jani Nikula wrote:
>> Add i915 parameter to I915_STATE_WARN() and use device based logging.
>> 
>> Done using cocci + hand edited where there was no i915 local variable
>> ready.
>> 
>> Signed-off-by: Jani Nikula 
>
> with a bit of trust in coccinelle + compiler (for dev_priv vs i915 checks):

That was too much trust, as verify_connector_state() had crtc->base.dev
but it's possible the crtc is NULL. Caught by CI, hooray.

>> @@ -64,6 +65,7 @@ static void
>>  verify_connector_state(struct intel_atomic_state *state,
>> struct intel_crtc *crtc)
>>  {
>> +struct drm_i915_private *i915 = to_i915(crtc->base.dev);

crtc can be NULL here.

v2 in-reply to v1.

BR,
Jani.

>>  struct drm_connector *connector;
>>  struct drm_connector_state *new_conn_state;
>>  int i;
>> @@ -80,7 +82,7 @@ verify_connector_state(struct intel_atomic_state *state,
>>  
>>  intel_connector_verify_state(crtc_state, new_conn_state);
>>  
>> -I915_STATE_WARN(new_conn_state->best_encoder != encoder,
>> +I915_STATE_WARN(i915, new_conn_state->best_encoder != encoder,
>>  "connector's atomic encoder doesn't match 
>> legacy encoder\n");
>>  }
>>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH v2] drm/i915/display: add i915 parameter to I915_STATE_WARN()

[Jani Nikula]

Add i915 parameter to I915_STATE_WARN() and use device based logging.

Done using cocci + hand edited where there was no i915 local variable
ready.

v2: avoid null deref in verify_connector_state()

Reviewed-by: Rodrigo Vivi 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/g4x_dp.c |  4 +-
 drivers/gpu/drm/i915/display/intel_crtc.c |  4 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 10 ++---
 drivers/gpu/drm/i915/display/intel_display.c  |  9 +++--
 drivers/gpu/drm/i915/display/intel_display.h  |  7 ++--
 .../drm/i915/display/intel_display_power.c| 37 ---
 drivers/gpu/drm/i915/display/intel_dpll.c |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 ---
 drivers/gpu/drm/i915/display/intel_fdi.c  |  9 +++--
 .../drm/i915/display/intel_modeset_verify.c   | 34 +
 .../gpu/drm/i915/display/intel_pch_display.c  | 20 +-
 drivers/gpu/drm/i915/display/intel_pps.c  |  7 ++--
 drivers/gpu/drm/i915/display/intel_snps_phy.c |  2 +-
 drivers/gpu/drm/i915/display/vlv_dsi_pll.c|  2 +-
 14 files changed, 99 insertions(+), 78 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c 
b/drivers/gpu/drm/i915/display/g4x_dp.c
index 920d570f7594..112d91d81fdc 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -169,7 +169,7 @@ static void assert_dp_port(struct intel_dp *intel_dp, bool 
state)
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & 
DP_PORT_EN;
 
-   I915_STATE_WARN(cur_state != state,
+   I915_STATE_WARN(dev_priv, cur_state != state,
"[ENCODER:%d:%s] state assertion failure (expected %s, 
current %s)\n",
dig_port->base.base.base.id, dig_port->base.base.name,
str_on_off(state), str_on_off(cur_state));
@@ -180,7 +180,7 @@ static void assert_edp_pll(struct drm_i915_private 
*dev_priv, bool state)
 {
bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
 
-   I915_STATE_WARN(cur_state != state,
+   I915_STATE_WARN(dev_priv, cur_state != state,
"eDP PLL state assertion failure (expected %s, current 
%s)\n",
str_on_off(state), str_on_off(cur_state));
 }
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c 
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 1e3f88d00609..ecae9bf05269 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -35,7 +35,9 @@
 
 static void assert_vblank_disabled(struct drm_crtc *crtc)
 {
-   if (I915_STATE_WARN(drm_crtc_vblank_get(crtc) == 0,
+   struct drm_i915_private *i915 = to_i915(crtc->dev);
+
+   if (I915_STATE_WARN(i915, drm_crtc_vblank_get(crtc) == 0,
"[CRTC:%d:%s] vblank assertion failure (expected 
off, current on)\n",
crtc->base.id, crtc->name))
drm_crtc_vblank_put(crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index d94127e7448b..ef0615cdc8a0 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2945,18 +2945,18 @@ void intel_c10pll_state_verify(struct 
intel_atomic_state *state,
for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) {
u8 expected = mpllb_sw_state->pll[i];
 
-   I915_STATE_WARN(mpllb_hw_state.pll[i] != expected,
+   I915_STATE_WARN(i915, mpllb_hw_state.pll[i] != expected,
"[CRTC:%d:%s] mismatch in C10MPLLB: 
Register[%d] (expected 0x%02x, found 0x%02x)",
-   crtc->base.base.id, crtc->base.name,
-   i, expected, mpllb_hw_state.pll[i]);
+   crtc->base.base.id, crtc->base.name, i,
+   expected, mpllb_hw_state.pll[i]);
}
 
-   I915_STATE_WARN(mpllb_hw_state.tx != mpllb_sw_state->tx,
+   I915_STATE_WARN(i915, mpllb_hw_state.tx != mpllb_sw_state->tx,
"[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 
(expected 0x%02x, found 0x%02x)",
crtc->base.base.id, crtc->base.name,
mpllb_sw_state->tx, mpllb_hw_state.tx);
 
-   I915_STATE_WARN(mpllb_hw_state.cmn != mpllb_sw_state->cmn,
+   I915_STATE_WARN(i915, mpllb_hw_state.cmn != mpllb_sw_state->cmn,
"[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 
(expected 0x%02x, found 0x%02x)",
crtc->base.base.id, crtc->base.name,
mpllb_sw_state->cmn, mpllb_hw_state.cmn);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 1d5d42a40803..4b70b389e0cb 100644
--- 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i1915/guc: Fix probe injection CI failures after recent change

[John Harrison]

On 5/10/2023 21:39, Patchwork wrote:

Project List - Patchwork *Patch Details*
*Series:* 	drm/i1915/guc: Fix probe injection CI failures after recent 
change

*URL:*  https://patchwork.freedesktop.org/series/117600/
*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117600v1/index.html



  CI Bug Log - changes from CI_DRM_13131_full -> Patchwork_117600v1_full


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_117600v1_full absolutely 
need to be

verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_117600v1_full, please notify your bug team to 
allow them
to document this new failure mode, which will reduce false positives 
in CI.



Participating hosts (7 -> 7)

No changes in participating hosts


Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_117600v1_full:



  IGT changes


Possible regressions

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
  o shard-apl: PASS


-> ABORT




Log shows a display failure. Not related to injection probe testing at all.

John.


 *


Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
  o {shard-dg1}: PASS


-> DMESG-WARN


+1 similar issue


Known issues

Here are the changes found in Patchwork_117600v1_full that come from 
known issues:



  IGT changes


Issues hit

 *

igt@gem_exec_fair@basic-pace-solo@rcs0:

  o shard-glk: PASS


-> FAIL


(i915#2842 )
 *

igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:

 o

shard-glk: PASS


-> FAIL


(i915#2346 )

 o

shard-apl: PASS


-> FAIL


(i915#2346 )

 *

igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2:

  o shard-glk: PASS


-> FAIL


(i915#2122 )
 *

igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:

  o shard-apl: PASS


-> FAIL


(i915#1188 )
 *

igt@kms_plane@pixel-format-source-clamping@pipe-b-planes:

  o shard-glk: PASS


-> DMESG-FAIL


(i915#118 )


Possible fixes

 *

igt@gem_ctx_exec@basic-nohangcheck:

  o {shard-rkl}: FAIL

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/bios: add helper for reading SPI (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/bios: add helper for reading SPI (rev3)
URL   : https://patchwork.freedesktop.org/series/103480/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13142_full -> Patchwork_103480v3_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_103480v3_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_103480v3_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (8 -> 7)
--

  Missing(1): shard-rkl0 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103480v3_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-apl:  [PASS][1] -> [TIMEOUT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/shard-apl4/igt@i915_pm_...@modeset-non-lpsp-stress-no-wait.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/shard-apl3/igt@i915_pm_...@modeset-non-lpsp-stress-no-wait.html

  
Known issues


  Here are the changes found in Patchwork_103480v3_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_capture@capture-invisible@smem0:
- shard-apl:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4579] / 
[i915#6334])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/shard-apl1/igt@gem_exec_capture@capture-invisi...@smem0.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][4] -> [FAIL][5] ([i915#2846])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/shard-glk3/igt@gem_exec_f...@basic-deadline.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/shard-glk7/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl:  [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/shard-apl1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/shard-apl6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-apl:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/shard-apl1/igt@gem_lmem_swapp...@heavy-random.html

  * igt@i915_pm_dc@dc9-dpms:
- shard-apl:  [PASS][9] -> [FAIL][10] ([i915#4275])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/shard-apl2/igt@i915_pm...@dc9-dpms.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/shard-apl1/igt@i915_pm...@dc9-dpms.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-apl:  NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#3886]) +3 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/shard-apl1/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2:
- shard-glk:  [PASS][12] -> [FAIL][13] ([i915#2122])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/shard-glk1/igt@kms_flip@2x-plain-flip-fb-recre...@ab-hdmi-a1-hdmi-a2.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/shard-glk9/igt@kms_flip@2x-plain-flip-fb-recre...@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-c-dp-1:
- shard-apl:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4579]) +1 
similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/shard-apl1/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-...@pipe-c-dp-1.html

  * igt@v3d/v3d_submit_csd@bad-multisync-out-sync:
- shard-apl:  NOTRUN -> [SKIP][15] ([fdo#109271]) +30 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/shard-apl1/igt@v3d/v3d_submit_...@bad-multisync-out-sync.html

  
 Possible fixes 

  * igt@drm_fdinfo@most-busy-check-all@rcs0:
- {shard-rkl}:[FAIL][16] ([i915#7742]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/shard-rkl-7/igt@drm_fdinfo@most-busy-check-...@rcs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/shard-rkl-2/igt@drm_fdinfo@most-busy-check-...@rcs0.html

  * igt@gem_barrier_race@remote-request@rcs0:
- {shard-dg1}:[ABORT][18] ([i915#7461] / [i915#8234]) -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/shard-dg1-13/igt@gem_barrier_race@remote-requ...@rcs0.html
   [19]: 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: Fix expected reg value for Thunderbolt PLL disabling (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: Fix expected reg value for Thunderbolt PLL disabling 
(rev2)
URL   : https://patchwork.freedesktop.org/series/117690/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13142 -> Patchwork_117690v2


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_117690v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_117690v2, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v2/index.html

Participating hosts (40 -> 37)
--

  Missing(3): fi-ilk-650 fi-ivb-3770 fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_117690v2:

### IGT changes ###

 Possible regressions 

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-hsw-4770:[PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/fi-hsw-4770/igt@i915_susp...@basic-s2idle-without-i915.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v2/fi-hsw-4770/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence:
- bat-adls-5: NOTRUN -> [SKIP][3] +6 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v2/bat-adls-5/igt@kms_pipe_crc_ba...@read-crc-frame-sequence.html

  
Known issues


  Here are the changes found in Patchwork_117690v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@fbdev@eof:
- bat-adls-5: [PASS][4] -> [SKIP][5] ([i915#2582]) +4 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/bat-adls-5/igt@fb...@eof.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v2/bat-adls-5/igt@fb...@eof.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-adls-5: NOTRUN -> [SKIP][6] ([i915#7561])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v2/bat-adls-5/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@migrate:
- bat-dg2-11: [PASS][7] -> [DMESG-WARN][8] ([i915#7699] / 
[i915#7953])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/bat-dg2-11/igt@i915_selftest@l...@migrate.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v2/bat-dg2-11/igt@i915_selftest@l...@migrate.html

  * igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][9] -> [ABORT][10] ([i915#4983] / [i915#7911] / 
[i915#7920] / [i915#7953])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/bat-rpls-1/igt@i915_selftest@l...@requests.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v2/bat-rpls-1/igt@i915_selftest@l...@requests.html

  * igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][11] ([i915#6367])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v2/bat-rpls-2/igt@i915_selftest@l...@slpc.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-apl-guc: [PASS][12] -> [DMESG-WARN][13] ([i915#1982] / 
[i915#8189])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/fi-apl-guc/igt@i915_susp...@basic-s3-without-i915.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v2/fi-apl-guc/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_busy@basic:
- bat-adls-5: NOTRUN -> [SKIP][14] ([i915#1845])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v2/bat-adls-5/igt@kms_b...@basic.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- bat-adls-5: [PASS][15] -> [SKIP][16] ([i915#1845]) +5 similar 
issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/bat-adls-5/igt@kms_cursor_leg...@basic-flip-before-cursor-varying-size.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v2/bat-adls-5/igt@kms_cursor_leg...@basic-flip-before-cursor-varying-size.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
- bat-adls-5: NOTRUN -> [SKIP][17] ([i915#3637]) +3 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v2/bat-adls-5/igt@kms_flip@basic-flip-vs-wf_vblank.html

  * igt@kms_frontbuffer_tracking@basic:
- bat-adls-5: [PASS][18] -> [SKIP][19] ([i915#1849])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/bat-adls-5/igt@kms_frontbuffer_track...@basic.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117690v2/bat-adls-5/igt@kms_frontbuffer_track...@basic.html

  * igt@prime_vgem@basic-fence-flip:
- bat-adls-5: [PASS][20] -> [SKIP][21] ([fdo#109295])
   [20]: 

Re: [Intel-gfx] [PATCH 6/6] drm/i915/pmu: Export counters from all tiles

[Dixit, Ashutosh]

On Fri, 12 May 2023 03:57:35 -0700, Tvrtko Ursulin wrote:
>
>
> On 11/05/2023 19:57, Dixit, Ashutosh wrote:
> > On Fri, 05 May 2023 17:58:16 -0700, Umesh Nerlige Ramappa wrote:
> >>
> >
> > One drive-by comment:
> >
> >> diff --git a/drivers/gpu/drm/i915/i915_pmu.c 
> >> b/drivers/gpu/drm/i915/i915_pmu.c
> >> index 12b2f3169abf..284e5c5b97bb 100644
> >> --- a/drivers/gpu/drm/i915/i915_pmu.c
> >> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> >> @@ -546,8 +546,9 @@ config_status(struct drm_i915_private *i915, u64 
> >> config)
> >>struct intel_gt *gt = to_gt(i915);
> >>
> >>unsigned int gt_id = config_gt_id(config);
> >> +  unsigned int max_gt_id = HAS_EXTRA_GT_LIST(i915) ? 1 : 0;
> >
> > But in Patch 5 we have:
> >
> > #define I915_PMU_MAX_GTS (4)
>
> AFAIR that one is just to size the internal arrays, while max_gt_id is to
> report to userspace which events are present.

Hmm, apart from the #defines's in i915_drm.h in Patch 5, not seeing
anything else reported to userspace about which events are present.

Also, we already have I915_MAX_GT, we shouldn't need I915_PMU_MAX_GTS, or
at least:

#define I915_PMU_MAX_GTS I915_MAX_GT

Better to use things uniformly. If we want I915_PMU_MAX_GTS to be 2 instead
of I915_MAX_GT (but why?, below is just a check) let's do

#define I915_PMU_MAX_GTS 2

And use that in the code above. But I think we should just use I915_MAX_GT.

Thanks.
--
Ashutosh


> >
> >>
> >> -  if (gt_id)
> >> +  if (gt_id > max_gt_id)
> >>return -ENOENT;
> >>
> >>switch (config_counter(config)) {
> >> @@ -561,6 +562,8 @@ config_status(struct drm_i915_private *i915, u64 
> >> config)
> >>return -ENODEV;
> >>break;
> >>case I915_PMU_INTERRUPTS:
> >> +  if (gt_id)
> >> +  return -ENOENT;
> >>break;
> >>case I915_PMU_RC6_RESIDENCY:
> >>if (!gt->rc6.supported)

Re: [Intel-gfx] [PATCH 2/3] linux/bits.h: Add fixed-width GENMASK and BIT macros

[Lucas De Marchi]

On Fri, May 12, 2023 at 02:14:19PM +0300, Andy Shevchenko wrote:

On Mon, May 08, 2023 at 10:14:02PM -0700, Lucas De Marchi wrote:

Add GENMASK_U32(), GENMASK_U16() and GENMASK_U8()  macros to create
masks for fixed-width types and also the corresponding BIT_U32(),
BIT_U16() and BIT_U8().


Why?


to create the masks/values for device registers that are
of a certain width, preventing mistakes like:

#define REG10x10
#define REG1_ENABLE BIT(17)
#define REG1_FOOGENMASK(16, 15);

register_write(REG1_ENABLE, REG1);


... if REG1 is a 16bit register for example. There were mistakes in the
past in the i915 source leading to the creation of the REG_* variants on
top of normal GENMASK/BIT (see last patch and commit 09b434d4f6d2
("drm/i915: introduce REG_BIT() and REG_GENMASK() to define register
contents")

We are preparing another driver (xe), still to be merged but already
open (https://gitlab.freedesktop.org/drm/xe/kernel), that has
similar requirements.





All of those depend on a new "U" suffix added to the integer constant.
Due to naming clashes it's better to call the macro U32. Since C doesn't
have a proper suffix for short and char types, the U16 and U18 variants
just use U32 with one additional check in the BIT_* macros to make
sure the compiler gives an error when the those types overflow.
The BIT_U16() and BIT_U8() need the help of GENMASK_INPUT_CHECK(),
as otherwise they would allow an invalid bit to be passed. Hence
implement them in include/linux/bits.h rather than together with
the other BIT* variants.


So, we have _Generic() in case you still wish to implement this.


humn... how would a _Generic() help here? The input is 1 or 2 integer
literals (h and l) so the compiler can check it is correct at build
time.  See example above.

Lucas De Marchi

Re: [Intel-gfx] [PATCH 07/11] drm/omapdrm: Use regular fbdev I/O helpers

[kernel test robot]

Hi Thomas,

kernel test robot noticed the following build errors:

[auto build test ERROR on 451e49cfbaa90720149e63f4fa9c7824013c783d]

url:
https://github.com/intel-lab-lkp/linux/commits/Thomas-Zimmermann/drm-armada-Use-regular-fbdev-I-O-helpers/20230512-164432
base:   451e49cfbaa90720149e63f4fa9c7824013c783d
patch link:
https://lore.kernel.org/r/20230512084152.31233-8-tzimmermann%40suse.de
patch subject: [Intel-gfx] [PATCH 07/11] drm/omapdrm: Use regular fbdev I/O 
helpers
config: arm-allmodconfig 
(https://download.01.org/0day-ci/archive/20230513/202305130058.vuw3nbps-...@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# 
https://github.com/intel-lab-lkp/linux/commit/f9113ec6815b748d0b917f78527582b8b08deb40
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review 
Thomas-Zimmermann/drm-armada-Use-regular-fbdev-I-O-helpers/20230512-164432
git checkout f9113ec6815b748d0b917f78527582b8b08deb40
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 
O=build_dir ARCH=arm olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 
O=build_dir ARCH=arm SHELL=/bin/bash drivers/gpu/drm/omapdrm/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot 
| Link: 
https://lore.kernel.org/oe-kbuild-all/202305130058.vuw3nbps-...@intel.com/

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/omapdrm/omap_fbdev.c:306:6: error: redefinition of 
>> 'omap_fbdev_setup'
 306 | void omap_fbdev_setup(struct drm_device *dev)
 |  ^~~~
   In file included from drivers/gpu/drm/omapdrm/omap_fbdev.c:19:
   drivers/gpu/drm/omapdrm/omap_fbdev.h:17:20: note: previous definition of 
'omap_fbdev_setup' with type 'void(struct drm_device *)'
  17 | static inline void omap_fbdev_setup(struct drm_device *dev)
 |^~~~


vim +/omap_fbdev_setup +306 drivers/gpu/drm/omapdrm/omap_fbdev.c

9e69bcd88e4593 Thomas Zimmermann 2023-04-03  305  
9e69bcd88e4593 Thomas Zimmermann 2023-04-03 @306  void omap_fbdev_setup(struct 
drm_device *dev)

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/bios: add helper for reading SPI (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/bios: add helper for reading SPI (rev3)
URL   : https://patchwork.freedesktop.org/series/103480/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13142 -> Patchwork_103480v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/index.html

Participating hosts (40 -> 37)
--

  Additional (1): fi-kbl-soraka 
  Missing(4): fi-ilk-650 fi-ivb-3770 bat-adls-5 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_103480v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-3:  [PASS][1] -> [ABORT][2] ([i915#5122])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][5] ([i915#5334] / [i915#7872])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][6] ([i915#1886] / [i915#7913])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@reset:
- bat-rpls-1: [PASS][7] -> [ABORT][8] ([i915#4983] / [i915#7461] / 
[i915#7953] / [i915#8347] / [i915#8384])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/bat-rpls-1/igt@i915_selftest@l...@reset.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/bat-rpls-1/igt@i915_selftest@l...@reset.html

  * igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][9] ([i915#6367])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/bat-rpls-2/igt@i915_selftest@l...@slpc.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-jsl-3:  [PASS][10] -> [FAIL][11] ([fdo#103375])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka:  NOTRUN -> [SKIP][12] ([fdo#109271]) +15 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-soraka:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4579])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/fi-kbl-soraka/igt@kms_setm...@basic-clone-single-crtc.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-glk-j4005:   [DMESG-FAIL][14] ([i915#5334]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@mman:
- bat-rpls-2: [TIMEOUT][16] ([i915#6794] / [i915#7392]) -> 
[PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/bat-rpls-2/igt@i915_selftest@l...@mman.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/bat-rpls-2/igt@i915_selftest@l...@mman.html

  * igt@i915_selftest@live@requests:
- {bat-mtlp-6}:   [ABORT][18] ([i915#4983] / [i915#7920] / [i915#7953]) 
-> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/bat-mtlp-6/igt@i915_selftest@l...@requests.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/bat-mtlp-6/igt@i915_selftest@l...@requests.html

  * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1:
- bat-dg2-8:  [FAIL][20] ([i915#7932]) -> [PASS][21] +1 similar 
issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13142/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103480v3/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html

  
  {name}: This element is