[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Add workaround 14016712196 (rev2)
== Series Details ==
Series: drm/i915/gt: Add workaround 14016712196 (rev2)
URL : https://patchwork.freedesktop.org/series/117661/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13160_full -> Patchwork_117661v2_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_117661v2_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_fbcon_fbt@fbc-suspend:
- {shard-dg1}:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-dg1-16/igt@kms_fbcon_...@fbc-suspend.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-dg1-13/igt@kms_fbcon_...@fbc-suspend.html
Known issues
Here are the changes found in Patchwork_117661v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_barrier_race@remote-request@rcs0:
- shard-glk: [PASS][3] -> [ABORT][4] ([i915#7461] / [i915#8211])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-glk1/igt@gem_barrier_race@remote-requ...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-glk3/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][5] -> [ABORT][6] ([i915#5566])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-apl3/igt@gen9_exec_pa...@allowed-single.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-apl4/igt@gen9_exec_pa...@allowed-single.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#79])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-glk9/igt@kms_flip@flip-vs-expired-vbl...@b-hdmi-a1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-glk4/igt@kms_flip@flip-vs-expired-vbl...@b-hdmi-a1.html
Possible fixes
* igt@gem_barrier_race@remote-request@rcs0:
- {shard-dg1}:[ABORT][9] ([i915#7461] / [i915#8234]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-dg1-17/igt@gem_barrier_race@remote-requ...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-dg1-18/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][11] ([i915#2842]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
- {shard-tglu}: [FAIL][13] ([i915#2842]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-tglu-6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-tglu-4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@i915_module_load@reload-with-fault-injection:
- {shard-dg1}:[DMESG-WARN][15] ([i915#4391]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-dg1-17/igt@i915_module_l...@reload-with-fault-injection.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-dg1-16/igt@i915_module_l...@reload-with-fault-injection.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- {shard-rkl}:[SKIP][17] ([i915#1937] / [i915#4579]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-rkl-2/igt@i915_pm_lpsp@kms-l...@kms-lpsp-hdmi-a.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-rkl-7/igt@i915_pm_lpsp@kms-l...@kms-lpsp-hdmi-a.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-dg1}:[FAIL][19] ([i915#3591]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-i...@vcs0.html
* igt@i915_pm_rps@reset:
- {shard-tglu}: [INCOMPLETE][21] ([i915#8320]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/shard-tglu-5/igt@i915_pm_...@reset.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/shard-tglu-7/igt@i915_pm_...@reset.html
* igt@i915_suspend@basic-s3-without-i915:
- {shard-rkl}:[FAIL][23] ([fdo#103375]) -> [PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/s
Re: [Intel-gfx] [PATCH 2/5] drm/i915: Convert INTEL_INFO()->display to a pointer
On 18.05.2023 05:18, Matt Roper wrote:
Rather than embeddeding the display's device info within the main device
info structure, just provide a pointer to the display-specific
structure. This is in preparation for moving the display device info
definitions into the display code itself and for eventually allowing the
pointer to be assigned at runtime on platforms that use GMD_ID for
device identification.
In the future, this will also eventually allow the same display device
info structures to be used outside the current i915 code (e.g., from the
Xe driver).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_color.c| 30 +-
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
.../drm/i915/display/intel_display_power.c| 6 +-
.../drm/i915/display/intel_display_reg_defs.h | 14 +-
drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +-
drivers/gpu/drm/i915/display/intel_hti.c | 2 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 28 +-
drivers/gpu/drm/i915/i915_pci.c | 579 --
drivers/gpu/drm/i915/intel_device_info.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
12 files changed, 450 insertions(+), 231 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 07f1afe1d406..ba32808f434b 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1824,14 +1824,14 @@ static u32 intel_gamma_lut_tests(const struct
intel_crtc_state *crtc_state)
if (lut_is_legacy(gamma_lut))
return 0;
- return INTEL_INFO(i915)->display.color.gamma_lut_tests;
+ return INTEL_INFO(i915)->display->color.gamma_lut_tests;
Looking at the number of occurences of INTEL_INFO(i915)->display we
could define:
#define DISPLAY_INFO(i915) (INTEL_INFO(i915)->display)
but I do not know if it will be helpful in further steps in abstracting
out display from core.
Reviewed-by: Andrzej Hajda
Regards
Andrzej
}
static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- return INTEL_INFO(i915)->display.color.degamma_lut_tests;
+ return INTEL_INFO(i915)->display->color.degamma_lut_tests;
}
static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
@@ -1842,14 +1842,14 @@ static int intel_gamma_lut_size(const struct
intel_crtc_state *crtc_state)
if (lut_is_legacy(gamma_lut))
return LEGACY_LUT_LENGTH;
- return INTEL_INFO(i915)->display.color.gamma_lut_size;
+ return INTEL_INFO(i915)->display->color.gamma_lut_size;
}
static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- return INTEL_INFO(i915)->display.color.degamma_lut_size;
+ return INTEL_INFO(i915)->display->color.degamma_lut_size;
}
static int check_lut_size(const struct drm_property_blob *lut, int expected)
@@ -2321,7 +2321,7 @@ static int glk_assign_luts(struct intel_crtc_state
*crtc_state)
struct drm_property_blob *gamma_lut;
gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut,
-
INTEL_INFO(i915)->display.color.degamma_lut_size,
+
INTEL_INFO(i915)->display->color.degamma_lut_size,
false);
if (IS_ERR(gamma_lut))
return PTR_ERR(gamma_lut);
@@ -2855,7 +2855,7 @@ static struct drm_property_blob *i9xx_read_lut_8(struct
intel_crtc *crtc)
static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
+ u32 lut_size = INTEL_INFO(dev_priv)->display->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -2904,7 +2904,7 @@ static void i9xx_read_luts(struct intel_crtc_state
*crtc_state)
static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
+ int i, lut_size = INTEL_INFO(dev_priv)->display->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -2954,7 +2954,7 @@ static void i965_read_luts(struct intel_crtc_state
*crtc_state)
static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc)
{
[Intel-gfx] [PATCH 3/3] drm/i915/hdcp: Rename comp_mutex to hdcp_mutex
Rename comp_mutex to hdcp_mutex as after MTL we use gsc cs
to enable hdcp hence this mutex protects not only hdcp
component we add to mei.
Cc: Jani Nikula
Cc: Ankit Nautiyal
Signed-off-by: Suraj Kandpal
---
.../gpu/drm/i915/display/intel_display_core.h | 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 94 +--
drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 4 +-
drivers/gpu/drm/i915/i915_driver.c| 2 +-
4 files changed, 52 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 57f76321a393..e853ca3b72ed 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -404,8 +404,8 @@ struct intel_display {
* this is only populated post Meteorlake
*/
struct intel_hdcp_gsc_message *hdcp_message;
- /* Mutex to protect the above hdcp component related values. */
- struct mutex comp_mutex;
+ /* Mutex to protect the above hdcp related values. */
+ struct mutex hdcp_mutex;
} hdcp;
struct {
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 7d43845d5157..3413455df36e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -182,12 +182,12 @@ bool intel_hdcp2_capable(struct intel_connector
*connector)
}
/* MEI/GSC interface is solid depending on which is used */
- mutex_lock(&i915->display.hdcp.comp_mutex);
+ mutex_lock(&i915->display.hdcp.hdcp_mutex);
if (!i915->display.hdcp.comp_added || !i915->display.hdcp.arbiter) {
- mutex_unlock(&i915->display.hdcp.comp_mutex);
+ mutex_unlock(&i915->display.hdcp.hdcp_mutex);
return false;
}
- mutex_unlock(&i915->display.hdcp.comp_mutex);
+ mutex_unlock(&i915->display.hdcp.hdcp_mutex);
/* Sink's capability for HDCP2.2 */
hdcp->shim->hdcp_2_2_capable(dig_port, &capable);
@@ -1117,11 +1117,11 @@ hdcp2_prepare_ake_init(struct intel_connector
*connector,
struct i915_hdcp_arbiter *arbiter;
int ret;
- mutex_lock(&i915->display.hdcp.comp_mutex);
+ mutex_lock(&i915->display.hdcp.hdcp_mutex);
arbiter = i915->display.hdcp.arbiter;
if (!arbiter || !arbiter->ops) {
- mutex_unlock(&i915->display.hdcp.comp_mutex);
+ mutex_unlock(&i915->display.hdcp.hdcp_mutex);
return -EINVAL;
}
@@ -1129,7 +1129,7 @@ hdcp2_prepare_ake_init(struct intel_connector *connector,
if (ret)
drm_dbg_kms(&i915->drm, "Prepare_ake_init failed. %d\n",
ret);
- mutex_unlock(&i915->display.hdcp.comp_mutex);
+ mutex_unlock(&i915->display.hdcp.hdcp_mutex);
return ret;
}
@@ -1147,11 +1147,11 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
struct i915_hdcp_arbiter *arbiter;
int ret;
- mutex_lock(&i915->display.hdcp.comp_mutex);
+ mutex_lock(&i915->display.hdcp.hdcp_mutex);
arbiter = i915->display.hdcp.arbiter;
if (!arbiter || !arbiter->ops) {
- mutex_unlock(&i915->display.hdcp.comp_mutex);
+ mutex_unlock(&i915->display.hdcp.hdcp_mutex);
return -EINVAL;
}
@@ -1161,7 +1161,7 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
if (ret < 0)
drm_dbg_kms(&i915->drm, "Verify rx_cert failed. %d\n",
ret);
- mutex_unlock(&i915->display.hdcp.comp_mutex);
+ mutex_unlock(&i915->display.hdcp.hdcp_mutex);
return ret;
}
@@ -1175,18 +1175,18 @@ static int hdcp2_verify_hprime(struct intel_connector
*connector,
struct i915_hdcp_arbiter *arbiter;
int ret;
- mutex_lock(&i915->display.hdcp.comp_mutex);
+ mutex_lock(&i915->display.hdcp.hdcp_mutex);
arbiter = i915->display.hdcp.arbiter;
if (!arbiter || !arbiter->ops) {
- mutex_unlock(&i915->display.hdcp.comp_mutex);
+ mutex_unlock(&i915->display.hdcp.hdcp_mutex);
return -EINVAL;
}
ret = arbiter->ops->verify_hprime(arbiter->hdcp_dev, data, rx_hprime);
if (ret < 0)
drm_dbg_kms(&i915->drm, "Verify hprime failed. %d\n", ret);
- mutex_unlock(&i915->display.hdcp.comp_mutex);
+ mutex_unlock(&i915->display.hdcp.hdcp_mutex);
return ret;
}
@@ -1201,11 +1201,11 @@ hdcp2_store_pairing_info(struct intel_connector
*connector,
struct i915_hdcp_arbiter *arbiter;
int ret;
- mutex_lock(&i915->display.hdcp.comp_mutex);
+ mutex_lock(&i915->display.hdcp.hdcp_mutex);
arbiter = i915->display.hdcp.arbite
[Intel-gfx] [PATCH 2/3] drm/i915/hdcp: Move away from master naming to arbiter
Rename variables to move away from master convention to
arbiter
master->arbiter
i915_hdcp_master->i915_hdcp_arbiter
comp_master->comp_arbiter
Cc: Ankit Nautiyal
Cc: Jani Nikula
Signed-off-by: Suraj Kandpal
---
.../gpu/drm/i915/display/intel_display_core.h | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 52 +--
drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 12 ++---
drivers/misc/mei/hdcp/mei_hdcp.c | 26 +-
include/drm/i915_hdcp_interface.h | 4 +-
5 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index e36f88a39b86..57f76321a393 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -395,7 +395,7 @@ struct intel_display {
} gmbus;
struct {
- struct i915_hdcp_master *master;
+ struct i915_hdcp_arbiter *arbiter;
bool comp_added;
/*
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 19c0b779e435..7d43845d5157 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -183,7 +183,7 @@ bool intel_hdcp2_capable(struct intel_connector *connector)
/* MEI/GSC interface is solid depending on which is used */
mutex_lock(&i915->display.hdcp.comp_mutex);
- if (!i915->display.hdcp.comp_added || !i915->display.hdcp.master) {
+ if (!i915->display.hdcp.comp_added || !i915->display.hdcp.arbiter) {
mutex_unlock(&i915->display.hdcp.comp_mutex);
return false;
}
@@ -1114,11 +1114,11 @@ hdcp2_prepare_ake_init(struct intel_connector
*connector,
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct i915_hdcp_master *arbiter;
+ struct i915_hdcp_arbiter *arbiter;
int ret;
mutex_lock(&i915->display.hdcp.comp_mutex);
- arbiter = i915->display.hdcp.master;
+ arbiter = i915->display.hdcp.arbiter;
if (!arbiter || !arbiter->ops) {
mutex_unlock(&i915->display.hdcp.comp_mutex);
@@ -1144,11 +1144,11 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct i915_hdcp_master *arbiter;
+ struct i915_hdcp_arbiter *arbiter;
int ret;
mutex_lock(&i915->display.hdcp.comp_mutex);
- arbiter = i915->display.hdcp.master;
+ arbiter = i915->display.hdcp.arbiter;
if (!arbiter || !arbiter->ops) {
mutex_unlock(&i915->display.hdcp.comp_mutex);
@@ -1172,11 +1172,11 @@ static int hdcp2_verify_hprime(struct intel_connector
*connector,
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct i915_hdcp_master *arbiter;
+ struct i915_hdcp_arbiter *arbiter;
int ret;
mutex_lock(&i915->display.hdcp.comp_mutex);
- arbiter = i915->display.hdcp.master;
+ arbiter = i915->display.hdcp.arbiter;
if (!arbiter || !arbiter->ops) {
mutex_unlock(&i915->display.hdcp.comp_mutex);
@@ -1198,11 +1198,11 @@ hdcp2_store_pairing_info(struct intel_connector
*connector,
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct i915_hdcp_master *arbiter;
+ struct i915_hdcp_arbiter *arbiter;
int ret;
mutex_lock(&i915->display.hdcp.comp_mutex);
- arbiter = i915->display.hdcp.master;
+ arbiter = i915->display.hdcp.arbiter;
if (!arbiter || !arbiter->ops) {
mutex_unlock(&i915->display.hdcp.comp_mutex);
@@ -1225,11 +1225,11 @@ hdcp2_prepare_lc_init(struct intel_connector *connector,
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct i915_hdcp_master *arbiter;
+ struct i915_hdcp_arbiter *arbiter;
int ret;
mutex_lock(&i915->display.hdcp.comp_mutex);
- arbiter = i915->display.hdcp.master;
+ arbiter = i915->display.hdcp.arbiter;
if (!arbiter || !arbiter->ops) {
[Intel-gfx] [PATCH 1/3] drm/i915/hdcp: Rename dev_priv to i915
Rename dev_priv to i915 to keep up with latest code standards.
Cc: Ankit Nautiyal
Cc: Jani Nikula
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 630 +++---
drivers/gpu/drm/i915/display/intel_hdcp.h | 6 +-
2 files changed, 318 insertions(+), 318 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index dd539106ee5a..19c0b779e435 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -164,7 +164,7 @@ bool intel_hdcp_capable(struct intel_connector *connector)
bool intel_hdcp2_capable(struct intel_connector *connector)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
bool capable = false;
@@ -173,8 +173,8 @@ bool intel_hdcp2_capable(struct intel_connector *connector)
return false;
/* If MTL+ make sure gsc is loaded and proxy is setup */
- if (intel_hdcp_gsc_cs_required(dev_priv)) {
- struct intel_gt *gt = dev_priv->media_gt;
+ if (intel_hdcp_gsc_cs_required(i915)) {
+ struct intel_gt *gt = i915->media_gt;
struct intel_gsc_uc *gsc = gt ? >->uc.gsc : NULL;
if (!gsc || !intel_uc_fw_is_running(&gsc->fw))
@@ -182,12 +182,12 @@ bool intel_hdcp2_capable(struct intel_connector
*connector)
}
/* MEI/GSC interface is solid depending on which is used */
- mutex_lock(&dev_priv->display.hdcp.comp_mutex);
- if (!dev_priv->display.hdcp.comp_added ||
!dev_priv->display.hdcp.master) {
- mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
+ mutex_lock(&i915->display.hdcp.comp_mutex);
+ if (!i915->display.hdcp.comp_added || !i915->display.hdcp.master) {
+ mutex_unlock(&i915->display.hdcp.comp_mutex);
return false;
}
- mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
+ mutex_unlock(&i915->display.hdcp.comp_mutex);
/* Sink's capability for HDCP2.2 */
hdcp->shim->hdcp_2_2_capable(dig_port, &capable);
@@ -195,20 +195,20 @@ bool intel_hdcp2_capable(struct intel_connector
*connector)
return capable;
}
-static bool intel_hdcp_in_use(struct drm_i915_private *dev_priv,
+static bool intel_hdcp_in_use(struct drm_i915_private *i915,
enum transcoder cpu_transcoder, enum port port)
{
- return intel_de_read(dev_priv,
-HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
- HDCP_STATUS_ENC;
+ return intel_de_read(i915,
+HDCP_STATUS(i915, cpu_transcoder, port)) &
+ HDCP_STATUS_ENC;
}
-static bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv,
+static bool intel_hdcp2_in_use(struct drm_i915_private *i915,
enum transcoder cpu_transcoder, enum port port)
{
- return intel_de_read(dev_priv,
-HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
- LINK_ENCRYPTION_STATUS;
+ return intel_de_read(i915,
+HDCP2_STATUS(i915, cpu_transcoder, port)) &
+ LINK_ENCRYPTION_STATUS;
}
static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *dig_port,
@@ -232,7 +232,7 @@ static int intel_hdcp_poll_ksv_fifo(struct
intel_digital_port *dig_port,
return 0;
}
-static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
+static bool hdcp_key_loadable(struct drm_i915_private *i915)
{
enum i915_power_well_id id;
intel_wakeref_t wakeref;
@@ -242,14 +242,14 @@ static bool hdcp_key_loadable(struct drm_i915_private
*dev_priv)
* On HSW and BDW, Display HW loads the Key as soon as Display resumes.
* On all BXT+, SW can load the keys only when the PW#1 is turned on.
*/
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+ if (IS_HASWELL(i915) || IS_BROADWELL(i915))
id = HSW_DISP_PW_GLOBAL;
else
id = SKL_DISP_PW_1;
/* PG1 (power well #1) needs to be enabled */
- with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
- enabled = intel_display_power_well_is_enabled(dev_priv, id);
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref)
+ enabled = intel_display_power_well_is_enabled(i915, id);
/*
* Another req for hdcp key loadability is enabled state of pll for
@@ -260,19 +260,19 @@ static bool hdcp_key_loadable(struct drm_i915_private
*dev_priv)
return enabled;
}
-static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv)
+static void intel_hdcp_clear_keys(struct drm_i915_private *i915)
{
-
[Intel-gfx] [PATCH 0/3] HDCP Cleanup
Some basic cleanup of hdcp code. Consists of -rename dev_priv to i915. -move away from master naming rename it to arbiter. -rename comp_mutex to hdcp_mutex. Signed-off-by: Suraj Kandpal Suraj Kandpal (3): drm/i915/hdcp: Rename dev_priv to i915 drm/i915/hdcp: Move away from master naming to arbiter drm/i915/hdcp: Rename comp_mutex to hdcp_mutex .../gpu/drm/i915/display/intel_display_core.h | 6 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 652 +- drivers/gpu/drm/i915/display/intel_hdcp.h | 6 +- drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 16 +- drivers/gpu/drm/i915/i915_driver.c| 2 +- drivers/misc/mei/hdcp/mei_hdcp.c | 26 +- include/drm/i915_hdcp_interface.h | 4 +- 7 files changed, 356 insertions(+), 356 deletions(-) -- 2.25.1
Re: [Intel-gfx] [PATCH 1/5] drm/i915/display: Move display device info to header under display/
On 18.05.2023 05:18, Matt Roper wrote:
Moving display-specific substruture definitions will help keep display
more self-contained and make it easier to re-use in other drivers (i.e.,
Xe) in the future.
Signed-off-by: Matt Roper
s/substruture/substructure/
Reviewed-by: Andrzej Hajda
Regards
Andrzej
---
.../drm/i915/display/intel_display_device.h | 60 +++
drivers/gpu/drm/i915/intel_device_info.h | 49 +--
2 files changed, 62 insertions(+), 47 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.h
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/intel_display_device.h
new file mode 100644
index ..c689d582dbf1
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __INTEL_DISPLAY_DEVICE_H__
+#define __INTEL_DISPLAY_DEVICE_H__
+
+#include
+
+#include "display/intel_display_limits.h"
+
+#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
+ /* Keep in alphabetical order */ \
+ func(cursor_needs_physical); \
+ func(has_cdclk_crawl); \
+ func(has_cdclk_squash); \
+ func(has_ddi); \
+ func(has_dp_mst); \
+ func(has_dsb); \
+ func(has_fpga_dbg); \
+ func(has_gmch); \
+ func(has_hotplug); \
+ func(has_hti); \
+ func(has_ipc); \
+ func(has_overlay); \
+ func(has_psr); \
+ func(has_psr_hw_tracking); \
+ func(overlay_needs_physical); \
+ func(supports_tv);
+
+struct intel_display_device_info {
+ u8 abox_mask;
+
+ struct {
+ u16 size; /* in blocks */
+ u8 slice_mask;
+ } dbuf;
+
+#define DEFINE_FLAG(name) u8 name:1
+ DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
+#undef DEFINE_FLAG
+
+ /* Global register offset for the display engine */
+ u32 mmio_offset;
+
+ /* Register offsets for the various display pipes and transcoders */
+ u32 pipe_offsets[I915_MAX_TRANSCODERS];
+ u32 trans_offsets[I915_MAX_TRANSCODERS];
+ u32 cursor_offsets[I915_MAX_PIPES];
+
+ struct {
+ u32 degamma_lut_size;
+ u32 gamma_lut_size;
+ u32 degamma_lut_tests;
+ u32 gamma_lut_tests;
+ } color;
+};
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 959a4080840c..96f6bdb04b1b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -29,7 +29,7 @@
#include "intel_step.h"
-#include "display/intel_display_limits.h"
+#include "display/intel_display_device.h"
#include "gt/intel_engine_types.h"
#include "gt/intel_context_types.h"
@@ -182,25 +182,6 @@ enum intel_ppgtt_type {
func(unfenced_needs_alignment); \
func(hws_needs_physical);
-#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
- /* Keep in alphabetical order */ \
- func(cursor_needs_physical); \
- func(has_cdclk_crawl); \
- func(has_cdclk_squash); \
- func(has_ddi); \
- func(has_dp_mst); \
- func(has_dsb); \
- func(has_fpga_dbg); \
- func(has_gmch); \
- func(has_hotplug); \
- func(has_hti); \
- func(has_ipc); \
- func(has_overlay); \
- func(has_psr); \
- func(has_psr_hw_tracking); \
- func(overlay_needs_physical); \
- func(supports_tv);
-
struct intel_ip_version {
u8 ver;
u8 rel;
@@ -278,33 +259,7 @@ struct intel_device_info {
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
- struct {
- u8 abox_mask;
-
- struct {
- u16 size; /* in blocks */
- u8 slice_mask;
- } dbuf;
-
-#define DEFINE_FLAG(name) u8 name:1
- DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
-#undef DEFINE_FLAG
-
- /* Global register offset for the display engine */
- u32 mmio_offset;
-
- /* Register offsets for the various display pipes and
transcoders */
- u32 pipe_offsets[I915_MAX_TRANSCODERS];
- u32 trans_offsets[I915_MAX_TRANSCODERS];
- u32 cursor_offsets[I915_MAX_PIPES];
-
- struct {
- u32 degamma_lut_size;
- u32 gamma_lut_size;
- u32 degamma_lut_tests;
- u32 gamma_lut_tests;
- } color;
- } display;
+ struct intel_display_device_info display;
/*
* Initial runtime info. Do not access outside of i915_driver_create().
Re: [Intel-gfx] [PATCH v5 00/10] Enhance vfio PCI hot reset for vfio cdev device
> -Original Message- > From: Liu, Yi L > Subject: [PATCH v5 00/10] Enhance vfio PCI hot reset for vfio cdev device > > VFIO_DEVICE_PCI_HOT_RESET requires user to pass an array of group fds to > prove that it owns all devices affected by resetting the calling device. While > for cdev devices, user can use an iommufd-based ownership checking model > and invoke VFIO_DEVICE_PCI_HOT_RESET with a zero-length fd array. > > This series first creates iommufd_access for noiommu devices to fill the gap > for adding iommufd-based ownership checking model, then extends > VFIO_DEVICE_GET_PCI_HOT_RESET_INFO to check ownership and return > the check result and the devid of affected devices to user. In the end, > extends the VFIO_DEVICE_PCI_HOT_RESET to accept zero-length fd array for > hot-reset with cdev devices. > > The new hot reset method and updated _INFO ioctl are tested with the > below qemu: > > https://github.com/yiliu1765/qemu/tree/iommufd_rfcv4.mig.reset.v4_var3 > (requires to test with the cdev kernel) > > Change log: > > v5: > - Drop patch 01 of v4 (Alex) > - Create noiommu_access for noiommu devices (Jason) > - Reserve all negative iommufd IDs, hence VFIO can encode negative >values (Jason) > - Make vfio_iommufd_physical_devid() return -EINVAL if it's not called >with a physical device or a noiommu device. > - Add vfio_find_device_in_devset() in vfio_main.c (Alex) > - Add iommufd_ctx_has_group() to replace > vfio_devset_iommufd_has_group(). >Reason: vfio_devset_iommufd_has_group() only loops the devices within >the given devset to check the iommufd an iommu_group, but an > iommu_group >can span into multiple devsets. So if failed to find the group in a >devset doesn't mean the group is not owned by the iommufd. So here > either >needs to search all the devsets or add an iommufd API to check it. It >appears an iommufd API makes more sense. > - Adopt suggestions from Alex on patch 08 and 09 of v4, refine the hot-reset >uapi description and minor tweaks > - Use bitfields for bool members (Alex) > > v4: https://lore.kernel.org/kvm/20230426145419.450922-1-yi.l@intel.com/ > - Rename the patch series subject > - Patch 01 is moved from the cdev series > - Patch 02, 06 are new per review comments in v3 > - Patch 03/04/05/07/08/09 are from v3 with updates > > v3: https://lore.kernel.org/kvm/20230401144429.88673-1-yi.l@intel.com/ > - Remove the new _INFO ioctl of v2, extend the existing _INFO ioctl to >report devid (Alex) > - Add r-b from Jason > - Add t-b from Terrence Xu and Yanting Jiang (mainly regression test) > > v2: https://lore.kernel.org/kvm/20230327093458.44939-1-yi.l@intel.com/ > - Split the patch 03 of v1 to be 03, 04 and 05 of v2 (Jaon) > - Add r-b from Kevin and Jason > - Add patch 10 to introduce a new _INFO ioctl for the usage of device >fd passing usage in cdev path (Jason, Alex) > > v1: https://lore.kernel.org/kvm/20230316124156.12064-1-yi.l@intel.com/ > > Regards, > Yi Liu > > Yi Liu (10): > vfio-iommufd: Create iommufd_access for noiommu devices > vfio/pci: Update comment around group_fd get in > vfio_pci_ioctl_pci_hot_reset() > vfio/pci: Move the existing hot reset logic to be a helper > vfio: Mark cdev usage in vfio_device > iommufd: Reserve all negative IDs in the iommufd xarray > vfio-iommufd: Add helper to retrieve iommufd_ctx and devid for > vfio_device > vfio: Add helper to search vfio_device in a dev_set > iommufd: Add iommufd_ctx_has_group() > vfio/pci: Extend VFIO_DEVICE_GET_PCI_HOT_RESET_INFO for vfio device > cdev > vfio/pci: Allow passing zero-length fd array in > VFIO_DEVICE_PCI_HOT_RESET > > drivers/iommu/iommufd/device.c | 53 + > drivers/iommu/iommufd/main.c | 2 +- > drivers/vfio/iommufd.c | 63 ++- > drivers/vfio/pci/vfio_pci_core.c | 184 --- > drivers/vfio/vfio_main.c | 15 +++ > include/linux/iommufd.h | 14 +++ > include/linux/vfio.h | 23 > include/uapi/linux/vfio.h| 60 +- > 8 files changed, 368 insertions(+), 46 deletions(-) > > -- > 2.34.1 The new uapi works fine. Tested GVT-g / GVT-d VFIO legacy mode / compat mode / cdev mode, including negative tests. No regression be introduced. Tested-by: Terrence Xu
Re: [Intel-gfx] [PATCH v11 00/23] Add vfio_device cdev for iommufd support
> -Original Message- > From: Liu, Yi L > Subject: [PATCH v11 00/23] Add vfio_device cdev for iommufd support > > Existing VFIO provides group-centric user APIs for userspace. Userspace > opens the /dev/vfio/$group_id first before getting device fd and hence > getting access to device. This is not the desired model for iommufd. Per the > conclusion of community discussion[1], iommufd provides device-centric > kAPIs and requires its consumer (like VFIO) to be device-centric user APIs. > Such user APIs are used to associate device with iommufd and also the I/O > address spaces managed by the iommufd. > > This series first introduces a per device file structure to be prepared for > further enhancement and refactors the kvm-vfio code to be prepared for > accepting device file from userspace. After this, adds a mechanism for > blocking device access before iommufd bind. Then refactors the vfio to be > able to handle cdev path (e.g. iommufd binding, no-iommufd, [de]attach > ioas). > This refactor includes making the device_open exclusive between the group > and the cdev path, only allow single device open in cdev path; vfio-iommufd > code is also refactored to support cdev. e.g. split the vfio_iommufd_bind() > into two steps. Eventually, adds the cdev support for vfio device and the new > ioctls, then makes group infrastructure optional as it is not needed when vfio > device cdev is compiled. > > This series is based on some preparation works done to vfio emulated > devices[2] and vfio pci hot reset enhancements[3]. > > This series is a prerequisite for iommu nesting for vfio device[4] [5]. > > The complete code can be found in below branch, simple tests done to the > legacy group path and the cdev path. Draft QEMU branch can be found at[6] > However, the noiommu mode test is only done with some hacks in kernel > and qemu to check if qemu can boot with noiommu devices. > > https://github.com/yiliu1765/iommufd/tree/vfio_device_cdev_v11 > (config CONFIG_IOMMUFD=y CONFIG_VFIO_DEVICE_CDEV=y) > > base-commit: b8b967d5ec691bddb883ab2abbfb8d632c97052e > > [1] > https://lore.kernel.org/kvm/BN9PR11MB5433B1E4AE5B0480369F97178C189 > @BN9PR11MB5433.namprd11.prod.outlook.com/ > [2] https://lore.kernel.org/kvm/20230327093351.44505-1-yi.l@intel.com/ - > merged [3] https://lore.kernel.org/kvm/20230513132136.15021-1- > yi.l@intel.com/ > [4] https://lore.kernel.org/linux-iommu/20230511143844.22693-1- > yi.l@intel.com/ > [5] https://lore.kernel.org/linux-iommu/20230511145110.27707-1- > yi.l@intel.com/#t > [6] > https://github.com/yiliu1765/qemu/tree/iommufd_rfcv4.mig.reset.v4_var3 > > Change log: > > v11: > - Add back the noiommu determination at vfio device registration patch and >put it prior to compiling vfio_group code optionally as compiling > vfio_group >optionaly is the major reason for it. > - Fix a typo related to SPAPR (Cédric Le Goater) > - Add t-b from Shameerali Kolothum Thodi, tested on HiSilicon D06(ARM64) > platform >with a NIC pass-through > > v10: https://lore.kernel.org/kvm/20230426150321.454465-1- > yi.l@intel.com/ > - Drop patch 03 of v9 as vfio_file_is_group() is still needed by pci hot > reset > path > - Drop 11 of v9 per the change of noiommu support > - Move patch 18 of v9 to hot-reset series [3] > - vfio_file_has_device_access() is dropped as no usage now (hot-reset does > not accept >device fd, hence no need for this helper) > - Minor change to patch 02, mainly make it back to patch v2 of v6 which is > before >splitting hot-reset series > - Minor change in 10 and 11 due to rebase > - Functional changes in patch 19, 20 and 21 per the latest noiommu support >policy. noiommu device can be bound to valid iommufd now, this is > different >from the prior policy in which noiommu device is not allowed to be bound > to >valid iommufd. So may pay more attention on the three patches, previous > r-b >and t-b are dropped for these three patches. > > v9: https://lore.kernel.org/kvm/20230401151833.124749-1-yi.l@intel.com/ > - Use smp_load_acquire() in vfio_file_has_device_access() for df- > >access_granted (Alex) > - Fix lock init in patch 16 of v8 (Jon Pan-Doh) > - Split patch 20 of v8 (Alex) > - Refine noiommu logic in BIND_IOMMUFD (Alex) > - Remove dev_cookie in BIND_IOMMUFD ioctl (Alex, Jason) > - Remove static_assert in ATTACH/DETACH ioctl handling (Alex) > - Remove device->ops->bind_iommufd presence check in > BIND_IOMMUFD/ATTACH/DETACH handling (Alex) > - Remove VFIO dependecny for VFIO_CONTAINER as VFIO_GROUP should > imply it (Alex) > - Improve the documentation per suggestions from Alex on patch 24 of v8 > (Alex) > - Remove WARN_ON(df->group) in vfio_device_group_uses_container() of > patch 11 > - Add r-b from Kevin to patch 18/19 of v8 > - Add r-b from Jason to patch 03/10/11 of v8 > - Add t-b from Yanting Jiang and Nicolin Chen > > v8: https://lore.kernel.org/kvm/20230327094047.47215-1-yi.l@intel.co
Re: [Intel-gfx] [Intel-xe] [PATCH 2/5] drm/i915: Convert INTEL_INFO()->display to a pointer
On Wed, May 17, 2023 at 08:18:01PM -0700, Matt Roper wrote:
Rather than embeddeding the display's device info within the main device
info structure, just provide a pointer to the display-specific
structure. This is in preparation for moving the display device info
definitions into the display code itself and for eventually allowing the
pointer to be assigned at runtime on platforms that use GMD_ID for
device identification.
In the future, this will also eventually allow the same display device
info structures to be used outside the current i915 code (e.g., from the
Xe driver).
Signed-off-by: Matt Roper
and here you did what I was thinking after reading patch 1.
Acked-by: Lucas De Marchi
... since I couldn't go the entire patch right now to review, but I like
where this is leading
Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_color.c| 30 +-
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
.../drm/i915/display/intel_display_power.c| 6 +-
.../drm/i915/display/intel_display_reg_defs.h | 14 +-
drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +-
drivers/gpu/drm/i915/display/intel_hti.c | 2 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 28 +-
drivers/gpu/drm/i915/i915_pci.c | 579 --
drivers/gpu/drm/i915/intel_device_info.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
12 files changed, 450 insertions(+), 231 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 07f1afe1d406..ba32808f434b 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1824,14 +1824,14 @@ static u32 intel_gamma_lut_tests(const struct
intel_crtc_state *crtc_state)
if (lut_is_legacy(gamma_lut))
return 0;
- return INTEL_INFO(i915)->display.color.gamma_lut_tests;
+ return INTEL_INFO(i915)->display->color.gamma_lut_tests;
}
static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- return INTEL_INFO(i915)->display.color.degamma_lut_tests;
+ return INTEL_INFO(i915)->display->color.degamma_lut_tests;
}
static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
@@ -1842,14 +1842,14 @@ static int intel_gamma_lut_size(const struct
intel_crtc_state *crtc_state)
if (lut_is_legacy(gamma_lut))
return LEGACY_LUT_LENGTH;
- return INTEL_INFO(i915)->display.color.gamma_lut_size;
+ return INTEL_INFO(i915)->display->color.gamma_lut_size;
}
static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- return INTEL_INFO(i915)->display.color.degamma_lut_size;
+ return INTEL_INFO(i915)->display->color.degamma_lut_size;
}
static int check_lut_size(const struct drm_property_blob *lut, int expected)
@@ -2321,7 +2321,7 @@ static int glk_assign_luts(struct intel_crtc_state
*crtc_state)
struct drm_property_blob *gamma_lut;
gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut,
-
INTEL_INFO(i915)->display.color.degamma_lut_size,
+
INTEL_INFO(i915)->display->color.degamma_lut_size,
false);
if (IS_ERR(gamma_lut))
return PTR_ERR(gamma_lut);
@@ -2855,7 +2855,7 @@ static struct drm_property_blob *i9xx_read_lut_8(struct
intel_crtc *crtc)
static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
+ u32 lut_size = INTEL_INFO(dev_priv)->display->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -2904,7 +2904,7 @@ static void i9xx_read_luts(struct intel_crtc_state
*crtc_state)
static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
+ int i, lut_size = INTEL_INFO(dev_priv)->display->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -2954,7 +2954,7 @@ static void i965_read_luts(struct intel_crtc_state
*crtc_state)
static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int i, lut_size = INTEL_INFO(dev_priv
Re: [Intel-gfx] [Intel-xe] [PATCH 1/5] drm/i915/display: Move display device info to header under display/
On Wed, May 17, 2023 at 08:18:00PM -0700, Matt Roper wrote:
Moving display-specific substruture definitions will help keep display
more self-contained and make it easier to re-use in other drivers (i.e.,
Xe) in the future.
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_device.h | 60 +++
drivers/gpu/drm/i915/intel_device_info.h | 49 +--
2 files changed, 62 insertions(+), 47 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.h
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/intel_display_device.h
new file mode 100644
index ..c689d582dbf1
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __INTEL_DISPLAY_DEVICE_H__
+#define __INTEL_DISPLAY_DEVICE_H__
+
+#include
+
+#include "display/intel_display_limits.h"
+
+#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
+ /* Keep in alphabetical order */ \
+ func(cursor_needs_physical); \
+ func(has_cdclk_crawl); \
+ func(has_cdclk_squash); \
+ func(has_ddi); \
+ func(has_dp_mst); \
+ func(has_dsb); \
+ func(has_fpga_dbg); \
+ func(has_gmch); \
+ func(has_hotplug); \
+ func(has_hti); \
+ func(has_ipc); \
+ func(has_overlay); \
+ func(has_psr); \
+ func(has_psr_hw_tracking); \
+ func(overlay_needs_physical); \
+ func(supports_tv);
+
+struct intel_display_device_info {
+ u8 abox_mask;
+
+ struct {
+ u16 size; /* in blocks */
+ u8 slice_mask;
+ } dbuf;
+
+#define DEFINE_FLAG(name) u8 name:1
+ DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
+#undef DEFINE_FLAG
+
+ /* Global register offset for the display engine */
+ u32 mmio_offset;
+
+ /* Register offsets for the various display pipes and transcoders */
+ u32 pipe_offsets[I915_MAX_TRANSCODERS];
+ u32 trans_offsets[I915_MAX_TRANSCODERS];
+ u32 cursor_offsets[I915_MAX_PIPES];
+
+ struct {
+ u32 degamma_lut_size;
+ u32 gamma_lut_size;
+ u32 degamma_lut_tests;
+ u32 gamma_lut_tests;
+ } color;
+};
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 959a4080840c..96f6bdb04b1b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -29,7 +29,7 @@
#include "intel_step.h"
-#include "display/intel_display_limits.h"
+#include "display/intel_display_device.h"
#include "gt/intel_engine_types.h"
#include "gt/intel_context_types.h"
@@ -182,25 +182,6 @@ enum intel_ppgtt_type {
func(unfenced_needs_alignment); \
func(hws_needs_physical);
-#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
- /* Keep in alphabetical order */ \
- func(cursor_needs_physical); \
- func(has_cdclk_crawl); \
- func(has_cdclk_squash); \
- func(has_ddi); \
- func(has_dp_mst); \
- func(has_dsb); \
- func(has_fpga_dbg); \
- func(has_gmch); \
- func(has_hotplug); \
- func(has_hti); \
- func(has_ipc); \
- func(has_overlay); \
- func(has_psr); \
- func(has_psr_hw_tracking); \
- func(overlay_needs_physical); \
- func(supports_tv);
-
struct intel_ip_version {
u8 ver;
u8 rel;
@@ -278,33 +259,7 @@ struct intel_device_info {
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
- struct {
- u8 abox_mask;
-
- struct {
- u16 size; /* in blocks */
- u8 slice_mask;
- } dbuf;
-
-#define DEFINE_FLAG(name) u8 name:1
- DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
-#undef DEFINE_FLAG
-
- /* Global register offset for the display engine */
- u32 mmio_offset;
-
- /* Register offsets for the various display pipes and
transcoders */
- u32 pipe_offsets[I915_MAX_TRANSCODERS];
- u32 trans_offsets[I915_MAX_TRANSCODERS];
- u32 cursor_offsets[I915_MAX_PIPES];
-
- struct {
- u32 degamma_lut_size;
- u32 gamma_lut_size;
- u32 degamma_lut_tests;
- u32 gamma_lut_tests;
- } color;
- } display;
+ struct intel_display_device_info display;
nice!! this greatly reduces the header needs for xe so we can eventually
stop including the whole display world just to have the types needed
available. If we go one step further and make it an opaque pointer, then
it'd be even better, but we'd need a mass conversion everywhere using
display. It seems to be going the right directions
Reviewed-by: Lucas De Marchi
Lucas De
[Intel-gfx] ✓ Fi.CI.BAT: success for i915: Move display identification/probing under display/
== Series Details ==
Series: i915: Move display identification/probing under display/
URL : https://patchwork.freedesktop.org/series/117931/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13162 -> Patchwork_117931v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/index.html
Participating hosts (38 -> 36)
--
Missing(2): fi-kbl-soraka fi-snb-2520m
Known issues
Here are the changes found in Patchwork_117931v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- bat-adls-5: [PASS][1] -> [DMESG-WARN][2] ([i915#5591])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/bat-adls-5/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-adls-5/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: [PASS][3] -> [DMESG-WARN][4] ([i915#6367])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/bat-rpls-2/igt@i915_selftest@l...@slpc.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html
- bat-rpls-1: NOTRUN -> [DMESG-WARN][5] ([i915#6367])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][6] ([i915#6687] / [i915#7978])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#7828])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#1845] / [i915#5354]) +1
similar issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][9] ([i915#5334]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_lrc:
- bat-dg2-11: [INCOMPLETE][11] ([i915#7609] / [i915#7913]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: [ABORT][13] ([i915#4983] / [i915#7461] / [i915#8347]
/ [i915#8384]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/bat-rpls-1/igt@i915_selftest@l...@reset.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-rpls-1/igt@i915_selftest@l...@reset.html
Warnings
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [SKIP][15] ([i915#3555] / [i915#4579]) -> [ABORT][16]
([i915#4579] / [i915#8260])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13162/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117931v1/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#8260]: https://gitlab.free
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Move display identification/probing under display/
== Series Details == Series: i915: Move display identification/probing under display/ URL : https://patchwork.freedesktop.org/series/117931/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Move display identification/probing under display/
== Series Details == Series: i915: Move display identification/probing under display/ URL : https://patchwork.freedesktop.org/series/117931/ State : warning == Summary == Error: dim checkpatch failed 9c8f732467ae drm/i915/display: Move display device info to header under display/ Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:14: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #14: new file mode 100644 -:31: ERROR:MULTISTATEMENT_MACRO_USE_DO_WHILE: Macros with multiple statements should be enclosed in a do - while loop #31: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:13: +#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ + /* Keep in alphabetical order */ \ + func(cursor_needs_physical); \ + func(has_cdclk_crawl); \ + func(has_cdclk_squash); \ + func(has_ddi); \ + func(has_dp_mst); \ + func(has_dsb); \ + func(has_fpga_dbg); \ + func(has_gmch); \ + func(has_hotplug); \ + func(has_hti); \ + func(has_ipc); \ + func(has_overlay); \ + func(has_psr); \ + func(has_psr_hw_tracking); \ + func(overlay_needs_physical); \ + func(supports_tv); -:31: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'func' - possible side-effects? #31: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:13: +#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ + /* Keep in alphabetical order */ \ + func(cursor_needs_physical); \ + func(has_cdclk_crawl); \ + func(has_cdclk_squash); \ + func(has_ddi); \ + func(has_dp_mst); \ + func(has_dsb); \ + func(has_fpga_dbg); \ + func(has_gmch); \ + func(has_hotplug); \ + func(has_hti); \ + func(has_ipc); \ + func(has_overlay); \ + func(has_psr); \ + func(has_psr_hw_tracking); \ + func(overlay_needs_physical); \ + func(supports_tv); -:31: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon #31: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:13: +#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ + /* Keep in alphabetical order */ \ + func(cursor_needs_physical); \ + func(has_cdclk_crawl); \ + func(has_cdclk_squash); \ + func(has_ddi); \ + func(has_dp_mst); \ + func(has_dsb); \ + func(has_fpga_dbg); \ + func(has_gmch); \ + func(has_hotplug); \ + func(has_hti); \ + func(has_ipc); \ + func(has_overlay); \ + func(has_psr); \ + func(has_psr_hw_tracking); \ + func(overlay_needs_physical); \ + func(supports_tv); total: 1 errors, 2 warnings, 1 checks, 127 lines checked 133ee53cfbb9 drm/i915: Convert INTEL_INFO()->display to a pointer -:225: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #225: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:39: +#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display->pipe_offsets[(pipe)] - \ -:226: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #226: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:40: + INTEL_INFO(dev_priv)->display->pipe_offsets[PIPE_A] + \ -:230: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #230: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:42: +#define _MMIO_TRANS2(tran, reg) _MMIO(INTEL_INFO(dev_priv)->display->trans_offsets[(tran)] - \ -:231: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #231: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:43: + INTEL_INFO(dev_priv)->display->trans_offsets[TRANSCODER_A] + \ -:235: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #235: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:45: +#define _MMIO_CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display->cursor_offsets[(pipe)] - \ -:236: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #236: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:46: + INTEL_INFO(dev_priv)->display->cursor_offsets[PIPE_A] + \ -:1192: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations #1192: FILE: drivers/gpu/drm/i915/i915_pci.c:844: + .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ -:1724: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues #1724: FILE: drivers/gpu/drm/i915/intel_device_info.c:141: +#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display->name)) total: 0 errors, 7 warnings, 1 checks, 1602 lines checked 49bdae529172 drm/i915/display: Move display runtime info to display structure -:60: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-e
[Intel-gfx] [PATCH 4/5] drm/i915/display: Make display responsible for probing its own IP
Rather than selecting the display IP and feature flags at the same time
the general PCI probing happens, move this step into the display code
itself so that it can be more easily re-used outside of i915 (i.e., by
the Xe driver).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/Makefile | 2 +
.../drm/i915/display/intel_display_device.c | 692 ++
.../drm/i915/display/intel_display_device.h | 3 +
drivers/gpu/drm/i915/i915_pci.c | 650
drivers/gpu/drm/i915/i915_reg.h | 33 -
drivers/gpu/drm/i915/intel_device_info.c | 13 +-
6 files changed, 707 insertions(+), 686 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index dd9ca69f4998..06374fc072d3 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -25,6 +25,7 @@ subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
# Fine grained warnings disable
CFLAGS_i915_pci.o = $(call cc-disable-warning, override-init)
+CFLAGS_display/intel_display_device.o = $(call cc-disable-warning,
override-init)
CFLAGS_display/intel_fbdev.o = $(call cc-disable-warning, override-init)
subdir-ccflags-y += -I$(srctree)/$(src)
@@ -308,6 +309,7 @@ i915-y += \
display/intel_cx0_phy.o \
display/intel_ddi.o \
display/intel_ddi_buf_trans.o \
+ display/intel_display_device.o \
display/intel_display_trace.o \
display/intel_dkl_phy.o \
display/intel_dp.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
new file mode 100644
index ..78fa522aaf0b
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -0,0 +1,692 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include
+#include
+#include
+
+#include "intel_display_device.h"
+#include "intel_display_power.h"
+#include "intel_display_reg_defs.h"
+#include "intel_fbc.h"
+
+#define PIPE_A_OFFSET 0x7
+#define PIPE_B_OFFSET 0x71000
+#define PIPE_C_OFFSET 0x72000
+#define PIPE_D_OFFSET 0x73000
+#define CHV_PIPE_C_OFFSET 0x74000
+/*
+ * There's actually no pipe EDP. Some pipe registers have
+ * simply shifted from the pipe to the transcoder, while
+ * keeping their original offset. Thus we need PIPE_EDP_OFFSET
+ * to access such registers in transcoder EDP.
+ */
+#define PIPE_EDP_OFFSET0x7f000
+
+/* ICL DSI 0 and 1 */
+#define PIPE_DSI0_OFFSET 0x7b000
+#define PIPE_DSI1_OFFSET 0x7b800
+
+#define TRANSCODER_A_OFFSET 0x6
+#define TRANSCODER_B_OFFSET 0x61000
+#define TRANSCODER_C_OFFSET 0x62000
+#define CHV_TRANSCODER_C_OFFSET 0x63000
+#define TRANSCODER_D_OFFSET 0x63000
+#define TRANSCODER_EDP_OFFSET 0x6f000
+#define TRANSCODER_DSI0_OFFSET 0x6b000
+#define TRANSCODER_DSI1_OFFSET 0x6b800
+
+#define CURSOR_A_OFFSET 0x70080
+#define CURSOR_B_OFFSET 0x700c0
+#define CHV_CURSOR_C_OFFSET 0x700e0
+#define IVB_CURSOR_B_OFFSET 0x71080
+#define IVB_CURSOR_C_OFFSET 0x72080
+#define TGL_CURSOR_D_OFFSET 0x73080
+
+#define I845_PIPE_OFFSETS \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ }
+
+#define I9XX_PIPE_OFFSETS \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ }
+
+#define IVB_PIPE_OFFSETS \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ }
+
+#define HSW_PIPE_OFFSETS \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
+ }
+
+#define CHV_PIPE_OFFSETS \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCOD
[Intel-gfx] [PATCH 0/5] i915: Move display identification/probing under display/
Since i915's display code will soon be shared by two DRM drivers (i915 and Xe), it makes sense for the display code itself to be responsible for recognizing the platform it's running on rather than relying on the making the top-level DRM driver handle this. This also becomes more important for all platforms MTL and beyond where we're not really supposed to identify platform behavior by PCI device ID anymore, but rather by the hardware IP version reported by the device through the GMD_ID register. This series creates a more well-defined split between display and non-display deviceinfo/runtimeinfo and then moves the definition of the display-specific feature flags under the display/ code. Finally, it switches MTL (and all future platforms), to select the display feature flags based on the hardware's GMD_ID identification. Cc: Jani Nikula Cc: Lucas De Marchi Matt Roper (5): drm/i915/display: Move display device info to header under display/ drm/i915: Convert INTEL_INFO()->display to a pointer drm/i915/display: Move display runtime info to display structure drm/i915/display: Make display responsible for probing its own IP drm/i915/display: Handle GMD_ID identification in display code drivers/gpu/drm/i915/Makefile | 2 + drivers/gpu/drm/i915/display/intel_color.c| 30 +- drivers/gpu/drm/i915/display/intel_crtc.c | 2 +- drivers/gpu/drm/i915/display/intel_cursor.c | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_display.h | 10 +- .../drm/i915/display/intel_display_device.c | 746 ++ .../drm/i915/display/intel_display_device.h | 89 +++ .../drm/i915/display/intel_display_power.c| 6 +- .../drm/i915/display/intel_display_reg_defs.h | 14 +- drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 6 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +- drivers/gpu/drm/i915/display/intel_hti.c | 2 +- .../drm/i915/display/skl_universal_plane.c| 2 +- drivers/gpu/drm/i915/display/skl_watermark.c | 8 +- drivers/gpu/drm/i915/i915_driver.c| 10 +- drivers/gpu/drm/i915/i915_drv.h | 45 +- drivers/gpu/drm/i915/i915_pci.c | 382 + drivers/gpu/drm/i915/i915_reg.h | 33 - drivers/gpu/drm/i915/intel_device_info.c | 121 +-- drivers/gpu/drm/i915/intel_device_info.h | 67 +- drivers/gpu/drm/i915/intel_step.c | 8 +- 23 files changed, 995 insertions(+), 598 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.c create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.h -- 2.40.0
[Intel-gfx] [PATCH 1/5] drm/i915/display: Move display device info to header under display/
Moving display-specific substruture definitions will help keep display
more self-contained and make it easier to re-use in other drivers (i.e.,
Xe) in the future.
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_device.h | 60 +++
drivers/gpu/drm/i915/intel_device_info.h | 49 +--
2 files changed, 62 insertions(+), 47 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_display_device.h
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/intel_display_device.h
new file mode 100644
index ..c689d582dbf1
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __INTEL_DISPLAY_DEVICE_H__
+#define __INTEL_DISPLAY_DEVICE_H__
+
+#include
+
+#include "display/intel_display_limits.h"
+
+#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
+ /* Keep in alphabetical order */ \
+ func(cursor_needs_physical); \
+ func(has_cdclk_crawl); \
+ func(has_cdclk_squash); \
+ func(has_ddi); \
+ func(has_dp_mst); \
+ func(has_dsb); \
+ func(has_fpga_dbg); \
+ func(has_gmch); \
+ func(has_hotplug); \
+ func(has_hti); \
+ func(has_ipc); \
+ func(has_overlay); \
+ func(has_psr); \
+ func(has_psr_hw_tracking); \
+ func(overlay_needs_physical); \
+ func(supports_tv);
+
+struct intel_display_device_info {
+ u8 abox_mask;
+
+ struct {
+ u16 size; /* in blocks */
+ u8 slice_mask;
+ } dbuf;
+
+#define DEFINE_FLAG(name) u8 name:1
+ DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
+#undef DEFINE_FLAG
+
+ /* Global register offset for the display engine */
+ u32 mmio_offset;
+
+ /* Register offsets for the various display pipes and transcoders */
+ u32 pipe_offsets[I915_MAX_TRANSCODERS];
+ u32 trans_offsets[I915_MAX_TRANSCODERS];
+ u32 cursor_offsets[I915_MAX_PIPES];
+
+ struct {
+ u32 degamma_lut_size;
+ u32 gamma_lut_size;
+ u32 degamma_lut_tests;
+ u32 gamma_lut_tests;
+ } color;
+};
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 959a4080840c..96f6bdb04b1b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -29,7 +29,7 @@
#include "intel_step.h"
-#include "display/intel_display_limits.h"
+#include "display/intel_display_device.h"
#include "gt/intel_engine_types.h"
#include "gt/intel_context_types.h"
@@ -182,25 +182,6 @@ enum intel_ppgtt_type {
func(unfenced_needs_alignment); \
func(hws_needs_physical);
-#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
- /* Keep in alphabetical order */ \
- func(cursor_needs_physical); \
- func(has_cdclk_crawl); \
- func(has_cdclk_squash); \
- func(has_ddi); \
- func(has_dp_mst); \
- func(has_dsb); \
- func(has_fpga_dbg); \
- func(has_gmch); \
- func(has_hotplug); \
- func(has_hti); \
- func(has_ipc); \
- func(has_overlay); \
- func(has_psr); \
- func(has_psr_hw_tracking); \
- func(overlay_needs_physical); \
- func(supports_tv);
-
struct intel_ip_version {
u8 ver;
u8 rel;
@@ -278,33 +259,7 @@ struct intel_device_info {
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
- struct {
- u8 abox_mask;
-
- struct {
- u16 size; /* in blocks */
- u8 slice_mask;
- } dbuf;
-
-#define DEFINE_FLAG(name) u8 name:1
- DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
-#undef DEFINE_FLAG
-
- /* Global register offset for the display engine */
- u32 mmio_offset;
-
- /* Register offsets for the various display pipes and
transcoders */
- u32 pipe_offsets[I915_MAX_TRANSCODERS];
- u32 trans_offsets[I915_MAX_TRANSCODERS];
- u32 cursor_offsets[I915_MAX_PIPES];
-
- struct {
- u32 degamma_lut_size;
- u32 gamma_lut_size;
- u32 degamma_lut_tests;
- u32 gamma_lut_tests;
- } color;
- } display;
+ struct intel_display_device_info display;
/*
* Initial runtime info. Do not access outside of i915_driver_create().
--
2.40.0
[Intel-gfx] [PATCH 3/5] drm/i915/display: Move display runtime info to display structure
Move the runtime info specific to display into display-specific
structures as has already been done with the constant display info.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 8 +-
.../drm/i915/display/intel_display_device.h | 23 ++
drivers/gpu/drm/i915/display/intel_fbc.c | 6 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
.../drm/i915/display/skl_universal_plane.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h | 17 +-
drivers/gpu/drm/i915/i915_pci.c | 221 +++---
drivers/gpu/drm/i915/intel_device_info.c | 101
drivers/gpu/drm/i915/intel_device_info.h | 18 --
drivers/gpu/drm/i915/intel_step.c | 8 +-
13 files changed, 245 insertions(+), 167 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 93c3226b98c9..182c6dd64f47 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -306,7 +306,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum
pipe pipe)
return PTR_ERR(crtc);
crtc->pipe = pipe;
- crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
+ crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe];
if (DISPLAY_VER(dev_priv) >= 9)
primary = skl_universal_plane_create(dev_priv, pipe,
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index dd2def27add9..093fc881ddc1 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -814,7 +814,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
DRM_MODE_ROTATE_0 |
DRM_MODE_ROTATE_180);
- zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
+ zpos = DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
if (DISPLAY_VER(dev_priv) >= 12)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 09320e14d75c..f1130e2c3542 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3366,7 +3366,7 @@ static u8 bigjoiner_pipes(struct drm_i915_private *i915)
else
pipes = 0;
- return pipes & RUNTIME_INFO(i915)->pipe_mask;
+ return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
}
static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index aa3a21ccd7fe..c744c021af23 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -105,7 +105,7 @@ enum i9xx_plane_id {
};
#define plane_name(p) ((p) + 'A')
-#define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] +
(s) + 'A')
+#define sprite_name(p, s) ((p) *
DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
#define for_each_plane_id_on_crtc(__crtc, __p) \
for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
@@ -221,7 +221,7 @@ enum phy_fia {
#define for_each_pipe(__dev_priv, __p) \
for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
- for_each_if(RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
+ for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask &
BIT(__p))
#define for_each_pipe_masked(__dev_priv, __p, __mask) \
for_each_pipe(__dev_priv, __p) \
@@ -229,7 +229,7 @@ enum phy_fia {
#define for_each_cpu_transcoder(__dev_priv, __t) \
for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
- for_each_if (RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask &
BIT(__t))
+ for_each_if
(DISPLAY_RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
for_each_cpu_transcoder(__dev_priv, __t) \
@@ -237,7 +237,7 @@ enum phy_fia {
#define for_each_sprite(__dev_priv, __p, __s) \
for ((__s) = 0; \
-(__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
+(__s) < DISPLAY_RUNTIME_INFO(__dev_priv)->num_sprites[(__p)];
\
(__s)++)
#define for_each_port(__port) \
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/intel_display_device.h
index c689d582dbf1..241f39b13f2f 100644
--- a/drivers/gpu/drm/i915/dis
[Intel-gfx] [PATCH 5/5] drm/i915/display: Handle GMD_ID identification in display code
For platforms with GMD_ID support (i.e., everything MTL and beyond),
identification of the display IP present should be based on the contents
of the GMD_ID register rather than a PCI devid match.
Note that since GMD_ID readout requires access to the PCI BAR, a slight
change to the driver init sequence is needed --- pci_enable_device() is
now called before i915_driver_create().
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_device.c | 64 +--
.../drm/i915/display/intel_display_device.h | 5 +-
drivers/gpu/drm/i915/i915_driver.c| 10 +--
drivers/gpu/drm/i915/intel_device_info.c | 13 ++--
4 files changed, 78 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 78fa522aaf0b..813a2a494082 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -6,7 +6,10 @@
#include
#include
#include
+#include
+#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display_device.h"
#include "intel_display_power.h"
#include "intel_display_reg_defs.h"
@@ -674,18 +677,69 @@ static const struct pci_device_id intel_display_ids[] = {
INTEL_RPLP_IDS(&xe_lpd_display),
INTEL_DG2_IDS(&xe_hpd_display),
- /* FIXME: Replace this with a GMD_ID lookup */
- INTEL_MTL_IDS(&xe_lpdp_display),
+ /*
+* Do not add any GMD_ID-based platforms to this list. They will
+* be probed automatically based on the IP version reported by
+* the hardware.
+*/
};
+struct {
+ u16 ver;
+ u16 rel;
+ const struct intel_display_device_info *display;
+} gmdid_display_map[] = {
+ { 14, 0, &xe_lpdp_display },
+};
+
+static const struct intel_display_device_info *
+probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16
*step)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ void __iomem *addr;
+ u32 val;
+ int i;
+
+ addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY),
sizeof(u32));
+ if (!addr) {
+ drm_err(&i915->drm, "Cannot map MMIO BAR to read display
GMD_ID\n");
+ return NULL;
+ }
+
+ val = ioread32(addr);
+ pci_iounmap(pdev, addr);
+
+ if (val == 0)
+ /* Platform doesn't have display */
+ return NULL;
+
+ *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
+ *rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
+ *step = REG_FIELD_GET(GMD_ID_STEP, val);
+
+ for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++)
+ if (*ver == gmdid_display_map[i].ver &&
+ *rel == gmdid_display_map[i].rel)
+ return gmdid_display_map[i].display;
+
+ drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling
display.\n",
+ *ver, *rel);
+ return NULL;
+}
+
const struct intel_display_device_info *
-intel_display_device_probe(u16 pci_devid)
+intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid,
+ u16 *gmdid_ver, u16 *gmdid_rel, u16 *gmdid_step)
{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
int i;
+ if (has_gmdid)
+ return probe_gmdid_display(i915, gmdid_ver, gmdid_rel,
gmdid_step);
+
for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
- if (intel_display_ids[i].device == pci_devid)
- return (struct intel_display_device_info
*)intel_display_ids[i].driver_data;
+ if (intel_display_ids[i].device == pdev->device)
+ return (const struct intel_display_device_info
*)intel_display_ids[i].driver_data;
}
return NULL;
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/intel_display_device.h
index 0a60ebfaff80..9a344ee36d8c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -80,7 +80,10 @@ struct intel_display_device_info {
} color;
};
+struct drm_i915_private;
+
const struct intel_display_device_info *
-intel_display_device_probe(u16 pci_devid);
+intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid,
+ u16 *ver, u16 *rel, u16 *step);
#endif
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index 522733a89946..d02c602e9a0b 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -754,14 +754,16 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
struct drm_i915_private *i915;
int ret;
- i915 = i915_driver_create(pdev, ent);
- if (IS_ERR(i915))
- return PTR_ERR(i915);
-
ret = pci_
[Intel-gfx] [PATCH 2/5] drm/i915: Convert INTEL_INFO()->display to a pointer
Rather than embeddeding the display's device info within the main device
info structure, just provide a pointer to the display-specific
structure. This is in preparation for moving the display device info
definitions into the display code itself and for eventually allowing the
pointer to be assigned at runtime on platforms that use GMD_ID for
device identification.
In the future, this will also eventually allow the same display device
info structures to be used outside the current i915 code (e.g., from the
Xe driver).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_color.c| 30 +-
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
.../drm/i915/display/intel_display_power.c| 6 +-
.../drm/i915/display/intel_display_reg_defs.h | 14 +-
drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +-
drivers/gpu/drm/i915/display/intel_hti.c | 2 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 28 +-
drivers/gpu/drm/i915/i915_pci.c | 579 --
drivers/gpu/drm/i915/intel_device_info.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
12 files changed, 450 insertions(+), 231 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 07f1afe1d406..ba32808f434b 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1824,14 +1824,14 @@ static u32 intel_gamma_lut_tests(const struct
intel_crtc_state *crtc_state)
if (lut_is_legacy(gamma_lut))
return 0;
- return INTEL_INFO(i915)->display.color.gamma_lut_tests;
+ return INTEL_INFO(i915)->display->color.gamma_lut_tests;
}
static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- return INTEL_INFO(i915)->display.color.degamma_lut_tests;
+ return INTEL_INFO(i915)->display->color.degamma_lut_tests;
}
static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
@@ -1842,14 +1842,14 @@ static int intel_gamma_lut_size(const struct
intel_crtc_state *crtc_state)
if (lut_is_legacy(gamma_lut))
return LEGACY_LUT_LENGTH;
- return INTEL_INFO(i915)->display.color.gamma_lut_size;
+ return INTEL_INFO(i915)->display->color.gamma_lut_size;
}
static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- return INTEL_INFO(i915)->display.color.degamma_lut_size;
+ return INTEL_INFO(i915)->display->color.degamma_lut_size;
}
static int check_lut_size(const struct drm_property_blob *lut, int expected)
@@ -2321,7 +2321,7 @@ static int glk_assign_luts(struct intel_crtc_state
*crtc_state)
struct drm_property_blob *gamma_lut;
gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut,
-
INTEL_INFO(i915)->display.color.degamma_lut_size,
+
INTEL_INFO(i915)->display->color.degamma_lut_size,
false);
if (IS_ERR(gamma_lut))
return PTR_ERR(gamma_lut);
@@ -2855,7 +2855,7 @@ static struct drm_property_blob *i9xx_read_lut_8(struct
intel_crtc *crtc)
static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
+ u32 lut_size = INTEL_INFO(dev_priv)->display->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -2904,7 +2904,7 @@ static void i9xx_read_luts(struct intel_crtc_state
*crtc_state)
static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
+ int i, lut_size = INTEL_INFO(dev_priv)->display->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -2954,7 +2954,7 @@ static void i965_read_luts(struct intel_crtc_state
*crtc_state)
static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
+ int i, lut_size = INTEL_INFO(dev_priv)->display->color.degamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -
Re: [Intel-gfx] [PATCH v6 6/7] drm/i915/pmu: Prepare for multi-tile non-engine counters
On Wed, 17 May 2023 13:55:41 -0700, Umesh Nerlige Ramappa wrote: > > From: Tvrtko Ursulin > > Reserve some bits in the counter config namespace which will carry the > tile id and prepare the code to handle this. > > No per tile counters have been added yet. > > v2: > - Fix checkpatch issues > - Use 4 bits for gt id in non-engine counters. Drop FIXME. > - Set MAX GTs to 4. Drop FIXME. > > v3: (Ashutosh, Tvrtko) > - Drop BUG_ON that would never fire > - Make enable u64 > - Pull in some code from next patch > > v4: Set I915_PMU_MAX_GTS to 2 (Tvrtko) > > v5: s/u64/u32 where needed (Ashutosh) Reviewed-by: Ashutosh Dixit
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v5,1/2] drm/i915/mtl: Add MTL performance tuning changes
== Series Details ==
Series: series starting with [v5,1/2] drm/i915/mtl: Add MTL performance tuning
changes
URL : https://patchwork.freedesktop.org/series/117923/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13161 -> Patchwork_117923v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117923v1/index.html
Participating hosts (37 -> 35)
--
Missing(2): fi-snb-2520m bat-mtlp-6
Known issues
Here are the changes found in Patchwork_117923v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gt_lrc:
- bat-rpls-1: [PASS][1] -> [INCOMPLETE][2] ([i915#4983])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13161/bat-rpls-1/igt@i915_selftest@live@gt_lrc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117923v1/bat-rpls-1/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@guc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][3] ([i915#7852])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117923v1/bat-rpls-2/igt@i915_selftest@l...@guc.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][4] ([i915#6367])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117923v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- fi-bsw-nick:NOTRUN -> [SKIP][5] ([fdo#109271]) +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117923v1/fi-bsw-nick/igt@kms_chamelium_...@common-hpd-after-suspend.html
- bat-jsl-1: NOTRUN -> [SKIP][6] ([i915#7828])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117923v1/bat-jsl-1/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [PASS][7] -> [FAIL][8] ([i915#7932]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13161/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117923v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
Possible fixes
* igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-1: [ABORT][9] ([i915#5122]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13161/bat-jsl-1/igt@gem_exec_suspend@basic...@smem.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117923v1/bat-jsl-1/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@hugepages:
- fi-bsw-nick:[ABORT][11] ([i915#6217]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13161/fi-bsw-nick/igt@i915_selftest@l...@hugepages.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117923v1/fi-bsw-nick/igt@i915_selftest@l...@hugepages.html
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [DMESG-WARN][13] ([i915#7699]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13161/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117923v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html
* igt@i915_selftest@live@mman:
- bat-rpls-2: [TIMEOUT][15] ([i915#6794] / [i915#7392]) ->
[PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13161/bat-rpls-2/igt@i915_selftest@l...@mman.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117923v1/bat-rpls-2/igt@i915_selftest@l...@mman.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-jsl-1: [FAIL][17] ([fdo#103375]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13161/bat-jsl-1/igt@i915_susp...@basic-s3-without-i915.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117923v1/bat-jsl-1/igt@i915_susp...@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#6217]: https://gitlab.freedesktop.org/drm/intel/issues/6217
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7852]: https://gitlab.freedesktop.org/drm/intel/iss
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v5,1/2] drm/i915/mtl: Add MTL performance tuning changes
== Series Details == Series: series starting with [v5,1/2] drm/i915/mtl: Add MTL performance tuning changes URL : https://patchwork.freedesktop.org/series/117923/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./drivers/gpu/drm/i915/intel_uncore.h:346:1: warning: trying to copy expression type 31 +./drivers/gpu/drm/i915/intel_uncore.h:351:1: warning: trying to copy expression type 31 +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask' +./include/asm-generi
[Intel-gfx] [PATCH v5 1/2] drm/i915/mtl: Add MTL performance tuning changes
MTL reuses the tuning parameters for DG2. Extend the dg2
performance tuning parameters to MTL.
v2: Add DRAW_WATERMARK tuning parameter.
v3: Limit DRAW_WATERMARK tuning to non A0 step.
v4: Reorder platform checks.
Restrict Blend fill caching optimization to Render GT.
v5: Move mtl tuning params to its own function
Bspec: 68331
Cc: Haridhar Kalvala
Cc: Matt Roper
Reviewed-by: Gustavo Sousa
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 23 -
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 786349e95487..4d2dece96011 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -812,11 +812,25 @@ static void dg2_ctx_workarounds_init(struct
intel_engine_cs *engine,
wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
}
+static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
+{
+ struct drm_i915_private *i915 = engine->i915;
+
+ dg2_ctx_gt_tuning_init(engine, wal);
+
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+ wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
+}
+
static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
+ mtl_ctx_gt_tuning_init(engine, wal);
+
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
/* Wa_14014947963 */
@@ -1748,6 +1762,13 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct
i915_wa_list *wal)
*/
static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
{
+ if (IS_METEORLAKE(gt->i915)) {
+ if (gt->type != GT_MEDIA)
+ wa_mcr_write_or(wal, XEHP_L3SCQREG7,
BLEND_FILL_CACHING_OPT_DIS);
+
+ wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
+ }
+
if (IS_PONTEVECCHIO(gt->i915)) {
wa_mcr_write(wal, XEHPC_L3SCRUB,
SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
@@ -2944,7 +2965,7 @@ static void
add_render_compute_tuning_settings(struct drm_i915_private *i915,
struct i915_wa_list *wal)
{
- if (IS_DG2(i915))
+ if (IS_METEORLAKE(i915) || IS_DG2(i915))
wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL,
STACKID_CTRL_512);
/*
--
2.34.1
[Intel-gfx] [PATCH v5 2/2] drm/i915/mtl: Extend Wa_16014892111 to MTL A-step
Like DG2, MTL a-step hardware is subject to Wa_16014892111 which requires that any changes made to the DRAW_WATERMARK register be done via an INDIRECT_CTX batch buffer rather than through a regular context workaround. The bspec gives the same non-default recommended tuning value for DRAW_WATERMARK as DG2, so we can re-use the INDIRECT_CTX code to apply that tuning setting on A-step hardware. Application of the tuning setting on B-step and later does not need INDIRECT_CTX handling and is already done in mtl_ctx_workarounds_init() as usual. v2: Limit the WA for A-step v3: Update the commit message. v4: Reorder platform checks and update commit message. Bspec: 68331 Cc: Haridhar Kalvala Cc: Gustavo Sousa Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 81a96c52a92b..a4ec20aaafe2 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1370,7 +1370,9 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) cs, GEN12_GFX_CCS_AUX_NV); /* Wa_16014892111 */ - if (IS_DG2(ce->engine->i915)) + if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) || + IS_DG2(ce->engine->i915)) cs = dg2_emit_draw_watermark_setting(cs); return cs; -- 2.34.1
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: move DSC RC tables to drm_dsc_helper.c (rev8)
== Series Details ==
Series: drm/i915: move DSC RC tables to drm_dsc_helper.c (rev8)
URL : https://patchwork.freedesktop.org/series/114473/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13158_full -> Patchwork_114473v8_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_114473v8_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_114473v8_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_114473v8_full:
### IGT changes ###
Possible regressions
* igt@i915_module_load@reload-with-fault-injection:
- shard-apl: [PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/shard-apl4/igt@i915_module_l...@reload-with-fault-injection.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/shard-apl2/igt@i915_module_l...@reload-with-fault-injection.html
Known issues
Here are the changes found in Patchwork_114473v8_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/shard-glk3/igt@gem_exec_fair@basic-p...@vcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/shard-glk7/igt@gem_exec_fair@basic-p...@vcs0.html
* igt@i915_pm_rpm@system-suspend:
- shard-apl: [PASS][5] -> [ABORT][6] ([i915#8213])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/shard-apl2/igt@i915_pm_...@system-suspend.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/shard-apl1/igt@i915_pm_...@system-suspend.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][7] -> [INCOMPLETE][8] ([i915#7790])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/shard-snb6/igt@i915_pm_...@reset.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/shard-snb7/igt@i915_pm_...@reset.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#72])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/shard-glk3/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/shard-glk8/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2346])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/shard-glk6/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/shard-glk6/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1:
- shard-apl: [PASS][13] -> [FAIL][14] ([i915#79])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/shard-apl2/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-dp1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/shard-apl4/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-dp1.html
* igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:
- shard-apl: [PASS][15] -> [FAIL][16] ([i915#1188])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/shard-apl6/igt@kms_hdr@bpc-switch-d...@pipe-a-dp-1.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/shard-apl7/igt@kms_hdr@bpc-switch-d...@pipe-a-dp-1.html
Possible fixes
* igt@gem_eio@hibernate:
- {shard-dg1}:[ABORT][17] ([i915#4391] / [i915#7975] / [i915#8213])
-> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/shard-dg1-14/igt@gem_...@hibernate.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/shard-dg1-13/igt@gem_...@hibernate.html
* igt@gem_eio@kms:
- {shard-dg1}:[FAIL][19] ([i915#5784]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/shard-dg1-12/igt@gem_...@kms.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/shard-dg1-15/igt@gem_...@kms.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: [FAIL][21] ([i915#2846]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/shard-apl2/igt@gem_exec_f...@basic-deadline.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/shard-ap
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Enhance vfio PCI hot reset for vfio cdev device (rev3)
== Series Details == Series: Enhance vfio PCI hot reset for vfio cdev device (rev3) URL : https://patchwork.freedesktop.org/series/116991/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/116991/revisions/3/mbox/ not applied Applying: vfio-iommufd: Create iommufd_access for noiommu devices Applying: vfio/pci: Update comment around group_fd get in vfio_pci_ioctl_pci_hot_reset() Applying: vfio/pci: Move the existing hot reset logic to be a helper Applying: vfio: Mark cdev usage in vfio_device Applying: iommufd: Reserve all negative IDs in the iommufd xarray Applying: vfio-iommufd: Add helper to retrieve iommufd_ctx and devid for vfio_device Applying: vfio: Add helper to search vfio_device in a dev_set Applying: iommufd: Add iommufd_ctx_has_group() Applying: vfio/pci: Extend VFIO_DEVICE_GET_PCI_HOT_RESET_INFO for vfio device cdev error: sha1 information is lacking or useless (drivers/vfio/pci/vfio_pci_core.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0009 vfio/pci: Extend VFIO_DEVICE_GET_PCI_HOT_RESET_INFO for vfio device cdev When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
Re: [Intel-gfx] [PATCH v5 09/10] vfio/pci: Extend VFIO_DEVICE_GET_PCI_HOT_RESET_INFO for vfio device cdev
On Sat, 13 May 2023 06:21:35 -0700
Yi Liu wrote:
> This makes VFIO_DEVICE_GET_PCI_HOT_RESET_INFO ioctl to use the iommufd_ctx
s/makes/allows/?
s/to//
> of the cdev device to check the ownership of the other affected devices.
>
> This returns devid for each of the affected devices. If it is bound to the
> iommufd_ctx of the cdev device, _INFO reports a valid devid > 0; If it is
> not opened by the calling user, but it belongs to the same iommu_group of
> a device that is bound to the iommufd_ctx of the cdev device, reports devid
> value of 0; If the device is un-owned device, configured within a different
> iommufd, or opened outside of the vfio device cdev API, the _INFO ioctl shall
> report devid value of -1.
>
> devid >=0 doesn't block hot-reset as the affected devices are considered to
> be owned, while devid == -1 will block the use of VFIO_DEVICE_PCI_HOT_RESET
> outside of proof-of-ownership calling conventions (ie. via legacy group
> accessed devices).
>
> This adds flag VFIO_PCI_HOT_RESET_FLAG_DEV_ID to tell the user devid is
> returned in case of calling user get device fd from other software stack
"other software stack"? I think this is trying to say something like:
When VFIO_DEVICE_GET_PCI_HOT_RESET_INFO is called on an IOMMUFD
managed device, the new flag VFIO_PCI_HOT_RESET_FLAG_DEV_ID is
reported to indicate the values returned are IOMMUFD devids rather
than group IDs as used when accessing vfio devices through the
conventional vfio group interface. Additionally the flag
VFIO_PCI_HOT_RESET_FLAG_DEV_ID_OWNED will be reported in this mode if
all of the devices affected by the hot-reset are owned by either
virtue of being directly bound to the same iommufd context as the
calling device, or implicitly owned via a shared IOMMU group.
> and adds flag VFIO_PCI_HOT_RESET_FLAG_DEV_ID_OWNED to tell user if all
> the affected devices are owned, so user can know it without looping all
> the returned devids.
>
> Suggested-by: Jason Gunthorpe
> Suggested-by: Alex Williamson
> Signed-off-by: Yi Liu
> ---
> drivers/vfio/pci/vfio_pci_core.c | 52 ++--
> include/uapi/linux/vfio.h| 46 +++-
> 2 files changed, 95 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/vfio/pci/vfio_pci_core.c
> b/drivers/vfio/pci/vfio_pci_core.c
> index 4df2def35bdd..57586be770af 100644
> --- a/drivers/vfio/pci/vfio_pci_core.c
> +++ b/drivers/vfio/pci/vfio_pci_core.c
> @@ -27,6 +27,7 @@
> #include
> #include
> #include
> +#include
> #if IS_ENABLED(CONFIG_EEH)
> #include
> #endif
> @@ -36,6 +37,10 @@
> #define DRIVER_AUTHOR "Alex Williamson "
> #define DRIVER_DESC "core driver for VFIO based PCI devices"
>
> +#ifdef CONFIG_IOMMUFD
> +MODULE_IMPORT_NS(IOMMUFD);
> +#endif
> +
> static bool nointxmask;
> static bool disable_vga;
> static bool disable_idle_d3;
> @@ -776,6 +781,9 @@ struct vfio_pci_fill_info {
> int max;
> int cur;
> struct vfio_pci_dependent_device *devices;
> + struct vfio_device *vdev;
> + bool devid:1;
> + bool dev_owned:1;
> };
>
> static int vfio_pci_fill_devs(struct pci_dev *pdev, void *data)
> @@ -790,7 +798,37 @@ static int vfio_pci_fill_devs(struct pci_dev *pdev, void
> *data)
> if (!iommu_group)
> return -EPERM; /* Cannot reset non-isolated devices */
>
> - fill->devices[fill->cur].group_id = iommu_group_id(iommu_group);
> + if (fill->devid) {
> + struct iommufd_ctx *iommufd =
> vfio_iommufd_physical_ictx(fill->vdev);
> + struct vfio_device_set *dev_set = fill->vdev->dev_set;
> + struct vfio_device *vdev;
> +
> + /*
> + * Report devid for the affected devices:
> + * - valid devid > 0 for the devices that are bound with
> + * the iommufd of the calling device.
> + * - devid == 0 for the devices that have not been opened
> + * but have same group with one of the devices bound to
> + * the iommufd of the calling device.
> + * - devid == -1 for others, and clear dev_owned flag.
> + */
> + vdev = vfio_find_device_in_devset(dev_set, &pdev->dev);
> + if (vdev && iommufd == vfio_iommufd_physical_ictx(vdev)) {
> + int ret;
> +
> + ret = vfio_iommufd_physical_devid(vdev);
> + if (WARN_ON(ret < 0))
> + return ret;
> + fill->devices[fill->cur].devid = ret;
Nit, @devid seems like a better variable name here rather than @ret.
> + } else if (vdev && iommufd_ctx_has_group(iommufd, iommu_group))
> {
> + fill->devices[fill->cur].devid = VFIO_PCI_DEVID_OWNED;
> + } else {
> + fill->devices[fill->cur].devid =
> VFIO_PCI_DEVID_NOT_OWNED;
> + fill->dev_owned = false;
> +
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add MTL PMU support for multi-gt
== Series Details == Series: Add MTL PMU support for multi-gt URL : https://patchwork.freedesktop.org/series/117913/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add MTL PMU support for multi-gt
== Series Details == Series: Add MTL PMU support for multi-gt URL : https://patchwork.freedesktop.org/series/117913/ State : warning == Summary == Error: dim checkpatch failed 210d9b13e02b drm/i915/pmu: Change bitmask of enabled events to u32 1c19f595d54a drm/i915/pmu: Support PMU for all engines b3f0a6813864 drm/i915/pmu: Skip sampling engines with no enabled counters b566ba4d283f drm/i915/pmu: Transform PMU parking code to be GT based 866e5d18d35a drm/i915/pmu: Add reference counting to the sampling timer 42554172eb8c drm/i915/pmu: Prepare for multi-tile non-engine counters -:105: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #105: FILE: drivers/gpu/drm/i915/i915_pmu.c:205: + GEM_BUG_ON(idx >= ARRAY_SIZE(pmu->sample)); total: 0 errors, 1 warnings, 0 checks, 338 lines checked d4a8070fba6c drm/i915/pmu: Export counters from all tiles
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: do not enable render power-gating on MTL (rev2)
== Series Details ==
Series: drm/i915/mtl: do not enable render power-gating on MTL (rev2)
URL : https://patchwork.freedesktop.org/series/117883/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13160 -> Patchwork_117883v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v2/index.html
Participating hosts (36 -> 37)
--
Additional (2): fi-kbl-soraka bat-mtlp-6
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_117883v2:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_mocs:
- {bat-mtlp-8}: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v2/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
Known issues
Here are the changes found in Patchwork_117883v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v2/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v2/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#7913])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@guc:
- bat-rpls-1: NOTRUN -> [DMESG-WARN][6] ([i915#7852])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v2/bat-rpls-1/igt@i915_selftest@l...@guc.html
* igt@i915_selftest@live@requests:
- bat-rpls-2: [PASS][7] -> [ABORT][8] ([i915#7913] / [i915#7982])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-rpls-2/igt@i915_selftest@l...@requests.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v2/bat-rpls-2/igt@i915_selftest@l...@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][9] ([i915#6687] / [i915#7978])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v2/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271]) +14 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v2/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#1845] / [i915#5354]) +2
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v2/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4579])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v2/fi-kbl-soraka/igt@kms_setm...@basic-clone-single-crtc.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- bat-rpls-1: [INCOMPLETE][13] ([i915#4983] / [i915#7677]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-rpls-1/igt@i915_selftest@l...@hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v2/bat-rpls-1/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [ABORT][15] ([i915#4983] / [i915#7920]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v2/bat-mtlp-8/igt@i915_selftest@l...@requests.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [FAIL][17] ([i915#7932]) -> [PASS][18] +1 similar
issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
Warnings
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [SKIP][19] ([i915#3555] / [i915#4579]) -> [ABORT][20]
([i915#4579] / [i915#8260])
Re: [Intel-gfx] [PATCH v2 2/8] drm/i915/uc: perma-pin firmwares
On 5/17/2023 1:59 PM, John Harrison wrote:
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
Now that each FW has its own reserved area, we can keep them always
pinned and skip the pin/unpin dance on reset. This will make things
easier for the 2-step HuC authentication, which requires the FW to be
pinned in GGTT after the xfer is completed.
Given that we use dummy vmas for the pinning, we do need to explicitly
re-pin on resume because the automated helper won't cover us.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 ++
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 7 -
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 8 +
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 2 ++
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 36 ++-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 5 +++-
8 files changed, 53 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 20915edc8bd9..ab71ed11de79 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -1322,6 +1322,9 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt)
ggtt->vm.scratch_range(&ggtt->vm, ggtt->error_capture.start,
ggtt->error_capture.size);
+ list_for_each_entry(gt, &ggtt->gt_list, ggtt_link)
+ intel_uc_resume_mappings(>->uc);
+
ggtt->invalidate(ggtt);
if (flush)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
index 64bff01026e8..af542e3cb3e9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
@@ -80,7 +80,12 @@ void intel_gsc_uc_init_early(struct intel_gsc_uc
*gsc)
{
struct intel_gt *gt = gsc_uc_to_gt(gsc);
- intel_uc_fw_init_early(&gsc->fw, INTEL_UC_FW_TYPE_GSC);
+ /*
+ * GSC FW needs to be copied to a dedicated memory allocations for
+ * loading (see gsc->local), so we don't need to GGTT map the FW
image
+ * itself into GGTT.
+ */
+ intel_uc_fw_init_early(&gsc->fw, INTEL_UC_FW_TYPE_GSC, false);
INIT_WORK(&gsc->work, gsc_work);
/* we can arrive here from i915_driver_early_probe for primary
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index c9f20385f6a0..2eb891b270ae 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -164,7 +164,7 @@ void intel_guc_init_early(struct intel_guc *guc)
struct intel_gt *gt = guc_to_gt(guc);
struct drm_i915_private *i915 = gt->i915;
- intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC);
+ intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC, true);
intel_guc_ct_init_early(&guc->ct);
intel_guc_log_init_early(&guc->log);
intel_guc_submission_init_early(guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index aefdaa62da99..9721761373fb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -276,7 +276,7 @@ void intel_huc_init_early(struct intel_huc *huc)
struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
struct intel_gt *gt = huc_to_gt(huc);
- intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC);
+ intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC, true);
/*
* we always init the fence as already completed, even if HuC
is not
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 996168312340..b6adfda3761e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -697,6 +697,12 @@ void intel_uc_suspend(struct intel_uc *uc)
}
}
+static void __uc_resume_mappings(struct intel_uc *uc)
+{
+ intel_uc_fw_resume_mapping(&uc->guc.fw);
+ intel_uc_fw_resume_mapping(&uc->huc.fw);
+}
+
static int __uc_resume(struct intel_uc *uc, bool enable_communication)
{
struct intel_guc *guc = &uc->guc;
@@ -764,4 +770,6 @@ static const struct intel_uc_ops uc_ops_on = {
.init_hw = __uc_init_hw,
.fini_hw = __uc_fini_hw,
+
+ .resume_mappings = __uc_resume_mappings,
};
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
index 5d0f1bcc381e..c2783e6e752b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
@@ -24,6 +24,7 @@ struct intel_uc_ops {
void (*fini)(struct intel_uc *uc);
int (*init_hw)(struct intel_uc *uc);
void (*fini_hw)(struct intel_uc *uc);
+ void (*resume_mappings)(struct intel_uc *uc);
};
struct intel_uc {
@@ -113,6 +114,7 @@ intel_uc_ops_function(init, init, int, 0);
intel_uc_ops_function(fini, fini, void, );
intel_uc_op
Re: [Intel-gfx] [PATCH v2] drm/i915/huc: Parse the GSC-enabled HuC binary
On 5/2/2023 08:27, Daniele Ceraolo Spurio wrote:
The new binaries that support the 2-step authentication have contain the
have contain?
legacy-style binary, which we can use for loading the HuC via DMA. To
find out where this is located in the image, we need to parse the meu
'meu manifest' needs some kind of explanation. 'meu' is mentioned many
times but nothing ever seems to explain what it is or where it comes
from. Also, sometimes it is capitalised and sometimes not.
manifest of the GSC binary. The manifest consist of a partition header
followed by entries, one of which contains the offset we're looking for.
Note that the DG2 GSC binary contains entries with the same names, but
it doesn't contain a full legacy binary, so we need to skip assigning
the dma offset in that case (which we can do by checking the ccs).
Also, since we're now parsing the entries, we can extract the HuC
version that way instead of using hardcoded offsets.
Note that the meu structure will be re-used for parsing the GSC binary,
so they've been added in their own header.
v2: fix structure names to match meu defines (s/CPT/CPD/), update commit
message, check ccs validity, drop old version location defines.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
.../drm/i915/gt/uc/intel_gsc_meu_headers.h| 74 ++
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 11 +-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 135 ++
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h | 5 +-
drivers/gpu/drm/i915/gt/uc/intel_huc_print.h | 21 +++
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 71 +
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 +
drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 6 -
8 files changed, 272 insertions(+), 53 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_huc_print.h
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
new file mode 100644
index ..d55a66202576
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_meu_headers.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _INTEL_GSC_MEU_H_
+#define _INTEL_GSC_MEU_H_
+
+#include
+
+/* Code partition directory (CPD) structures */
+struct intel_gsc_cpd_header_v2 {
+ u32 header_marker;
+#define INTEL_GSC_CPD_HEADER_MARKER 0x44504324
+
+ u32 num_of_entries;
+ u8 header_version;
+ u8 entry_version;
+ u8 header_length; /* in bytes */
+ u8 flags;
+ u32 partition_name;
+ u32 crc32;
+} __packed;
+
+struct intel_gsc_cpd_entry {
+ u8 name[12];
+
+ /*
+* Bits 0-24: offset from the beginning of the code partition
+* Bit 25: huffman compressed
+* Bits 26-31: reserved
+*/
+ u32 offset;
+#define INTEL_GSC_CPD_ENTRY_OFFSET_MASK GENMASK(24, 0)
+#define INTEL_GSC_CPD_ENTRY_HUFFMAN_COMP BIT(25)
+
+ /*
+* Module/Item length, in bytes. For Huffman-compressed modules, this
+* refers to the uncompressed size. For software-compressed modules,
+* this refers to the compressed size.
+*/
+ u32 length;
+
+ u8 reserved[4];
+} __packed;
+
+struct intel_gsc_meu_version {
+ u16 major;
+ u16 minor;
+ u16 hotfix;
+ u16 build;
+} __packed;
+
+struct intel_gsc_manifest_header {
+ u32 header_type; /* 0x4 for manifest type */
+ u32 header_length; /* in dwords */
+ u32 header_version;
+ u32 flags;
+ u32 vendor;
+ u32 date;
+ u32 size; /* In dwords, size of entire manifest (header + extensions) */
+ u32 header_id;
+ u32 internal_data;
+ struct intel_gsc_meu_version fw_version;
+ u32 security_version;
+ struct intel_gsc_meu_version meu_kit_version;
+ u32 meu_manifest_version;
+ u8 general_data[4];
+ u8 reserved3[56];
+ u32 modulus_size; /* in dwords */
+ u32 exponent_size; /* in dwords */
+} __packed;
+
+#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 9721761373fb..062ff914b274 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -6,23 +6,14 @@
#include
#include "gt/intel_gt.h"
-#include "gt/intel_gt_print.h"
#include "intel_guc_reg.h"
#include "intel_huc.h"
+#include "intel_huc_print.h"
#include "i915_drv.h"
#include
#include
-#define huc_printk(_huc, _level, _fmt, ...) \
- gt_##_level(huc_to_gt(_huc), "HuC: " _fmt, ##__VA_ARGS__)
-#define huc_err(_huc, _fmt, ...) huc_printk((_huc), err, _fmt,
##__VA_ARGS__)
-#define huc_warn(_huc, _fmt, ...) huc_printk((_huc), warn, _fmt,
##__VA_ARGS__)
-#define huc_notice(_huc, _fmt, ...)huc_printk((_huc), notice, _fmt,
##__VA_ARGS__)
-#de
Re: [Intel-gfx] [PATCH v2 2/8] drm/i915/uc: perma-pin firmwares
On 4/28/2023 11:58, Daniele Ceraolo Spurio wrote:
Now that each FW has its own reserved area, we can keep them always
pinned and skip the pin/unpin dance on reset. This will make things
easier for the 2-step HuC authentication, which requires the FW to be
pinned in GGTT after the xfer is completed.
Given that we use dummy vmas for the pinning, we do need to explicitly
re-pin on resume because the automated helper won't cover us.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 ++
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 7 -
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 8 +
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 2 ++
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 36 ++-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 5 +++-
8 files changed, 53 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 20915edc8bd9..ab71ed11de79 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -1322,6 +1322,9 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt)
ggtt->vm.scratch_range(&ggtt->vm, ggtt->error_capture.start,
ggtt->error_capture.size);
+ list_for_each_entry(gt, &ggtt->gt_list, ggtt_link)
+ intel_uc_resume_mappings(>->uc);
+
ggtt->invalidate(ggtt);
if (flush)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
index 64bff01026e8..af542e3cb3e9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
@@ -80,7 +80,12 @@ void intel_gsc_uc_init_early(struct intel_gsc_uc *gsc)
{
struct intel_gt *gt = gsc_uc_to_gt(gsc);
- intel_uc_fw_init_early(&gsc->fw, INTEL_UC_FW_TYPE_GSC);
+ /*
+* GSC FW needs to be copied to a dedicated memory allocations for
+* loading (see gsc->local), so we don't need to GGTT map the FW image
+* itself into GGTT.
+*/
+ intel_uc_fw_init_early(&gsc->fw, INTEL_UC_FW_TYPE_GSC, false);
INIT_WORK(&gsc->work, gsc_work);
/* we can arrive here from i915_driver_early_probe for primary
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index c9f20385f6a0..2eb891b270ae 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -164,7 +164,7 @@ void intel_guc_init_early(struct intel_guc *guc)
struct intel_gt *gt = guc_to_gt(guc);
struct drm_i915_private *i915 = gt->i915;
- intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC);
+ intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC, true);
intel_guc_ct_init_early(&guc->ct);
intel_guc_log_init_early(&guc->log);
intel_guc_submission_init_early(guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index aefdaa62da99..9721761373fb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -276,7 +276,7 @@ void intel_huc_init_early(struct intel_huc *huc)
struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
struct intel_gt *gt = huc_to_gt(huc);
- intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC);
+ intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC, true);
/*
* we always init the fence as already completed, even if HuC is not
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 996168312340..b6adfda3761e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -697,6 +697,12 @@ void intel_uc_suspend(struct intel_uc *uc)
}
}
+static void __uc_resume_mappings(struct intel_uc *uc)
+{
+ intel_uc_fw_resume_mapping(&uc->guc.fw);
+ intel_uc_fw_resume_mapping(&uc->huc.fw);
+}
+
static int __uc_resume(struct intel_uc *uc, bool enable_communication)
{
struct intel_guc *guc = &uc->guc;
@@ -764,4 +770,6 @@ static const struct intel_uc_ops uc_ops_on = {
.init_hw = __uc_init_hw,
.fini_hw = __uc_fini_hw,
+
+ .resume_mappings = __uc_resume_mappings,
};
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
index 5d0f1bcc381e..c2783e6e752b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
@@ -24,6 +24,7 @@ struct intel_uc_ops {
void (*fini)(struct intel_uc *uc);
int (*init_hw)(struct intel_uc *uc);
void (*fini_hw)(struct intel_uc *uc);
+ void (*resume_mappings)(struct intel_uc *uc);
};
struct intel_uc {
@@ -113,6 +114,7 @@ intel_uc_ops_function(init, init, int, 0);
intel_uc_ops_function
[Intel-gfx] [PATCH v6 5/7] drm/i915/pmu: Add reference counting to the sampling timer
From: Tvrtko Ursulin
We do not want to have timers per tile and waste CPU cycles and energy via
multiple wake-up sources, for a relatively un-important task of PMU
sampling, so keeping a single timer works well. But we also do not want
the first GT which goes idle to turn off the timer.
Add some reference counting, via a mask of unparked GTs, to solve this.
v2: Drop the check for unparked in i915_sample (Ashutosh)
v3: Revert v2 (Tvrtko)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_pmu.c | 12 ++--
drivers/gpu/drm/i915/i915_pmu.h | 4
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 890693fdaf9e..ecb57a94143e 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -262,7 +262,9 @@ void i915_pmu_gt_parked(struct intel_gt *gt)
* Signal sampling timer to stop if only engine events are enabled and
* GPU went idle.
*/
- pmu->timer_enabled = pmu_needs_timer(pmu, false);
+ pmu->unparked &= ~BIT(gt->info.id);
+ if (pmu->unparked == 0)
+ pmu->timer_enabled = pmu_needs_timer(pmu, false);
spin_unlock_irq(&pmu->lock);
}
@@ -279,7 +281,10 @@ void i915_pmu_gt_unparked(struct intel_gt *gt)
/*
* Re-enable sampling timer when GPU goes active.
*/
- __i915_pmu_maybe_start_timer(pmu);
+ if (pmu->unparked == 0)
+ __i915_pmu_maybe_start_timer(pmu);
+
+ pmu->unparked |= BIT(gt->info.id);
spin_unlock_irq(&pmu->lock);
}
@@ -449,6 +454,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
*/
for_each_gt(gt, i915, i) {
+ if (!(pmu->unparked & BIT(i)))
+ continue;
+
engines_sample(gt, period_ns);
if (i == 0) /* FIXME */
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index a686fd7ccedf..3a811266ac6a 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -76,6 +76,10 @@ struct i915_pmu {
* @lock: Lock protecting enable mask and ref count handling.
*/
spinlock_t lock;
+ /**
+* @unparked: GT unparked mask.
+*/
+ unsigned int unparked;
/**
* @timer: Timer for internal i915 PMU sampling.
*/
--
2.36.1
[Intel-gfx] [PATCH v6 4/7] drm/i915/pmu: Transform PMU parking code to be GT based
From: Tvrtko Ursulin
Trivial prep work for full multi-tile enablement later.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Vinay Belgaumkar
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++--
drivers/gpu/drm/i915/i915_pmu.c | 16
drivers/gpu/drm/i915/i915_pmu.h | 9 +
3 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index e02cb90723ae..c2e69bafd02b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -87,7 +87,7 @@ static int __gt_unpark(struct intel_wakeref *wf)
intel_rc6_unpark(>->rc6);
intel_rps_unpark(>->rps);
- i915_pmu_gt_unparked(i915);
+ i915_pmu_gt_unparked(gt);
intel_guc_busyness_unpark(gt);
intel_gt_unpark_requests(gt);
@@ -109,7 +109,7 @@ static int __gt_park(struct intel_wakeref *wf)
intel_guc_busyness_park(gt);
i915_vma_parked(gt);
- i915_pmu_gt_parked(i915);
+ i915_pmu_gt_parked(gt);
intel_rps_park(>->rps);
intel_rc6_park(>->rc6);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 6d594f67f365..890693fdaf9e 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -228,11 +228,11 @@ static void init_rc6(struct i915_pmu *pmu)
}
}
-static void park_rc6(struct drm_i915_private *i915)
+static void park_rc6(struct intel_gt *gt)
{
- struct i915_pmu *pmu = &i915->pmu;
+ struct i915_pmu *pmu = >->i915->pmu;
- pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(to_gt(i915));
+ pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(gt);
pmu->sleep_last = ktime_get_raw();
}
@@ -247,16 +247,16 @@ static void __i915_pmu_maybe_start_timer(struct i915_pmu
*pmu)
}
}
-void i915_pmu_gt_parked(struct drm_i915_private *i915)
+void i915_pmu_gt_parked(struct intel_gt *gt)
{
- struct i915_pmu *pmu = &i915->pmu;
+ struct i915_pmu *pmu = >->i915->pmu;
if (!pmu->base.event_init)
return;
spin_lock_irq(&pmu->lock);
- park_rc6(i915);
+ park_rc6(gt);
/*
* Signal sampling timer to stop if only engine events are enabled and
@@ -267,9 +267,9 @@ void i915_pmu_gt_parked(struct drm_i915_private *i915)
spin_unlock_irq(&pmu->lock);
}
-void i915_pmu_gt_unparked(struct drm_i915_private *i915)
+void i915_pmu_gt_unparked(struct intel_gt *gt)
{
- struct i915_pmu *pmu = &i915->pmu;
+ struct i915_pmu *pmu = >->i915->pmu;
if (!pmu->base.event_init)
return;
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index c30f43319a78..a686fd7ccedf 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -13,6 +13,7 @@
#include
struct drm_i915_private;
+struct intel_gt;
/*
* Non-engine events that we need to track enabled-disabled transition and
@@ -151,15 +152,15 @@ int i915_pmu_init(void);
void i915_pmu_exit(void);
void i915_pmu_register(struct drm_i915_private *i915);
void i915_pmu_unregister(struct drm_i915_private *i915);
-void i915_pmu_gt_parked(struct drm_i915_private *i915);
-void i915_pmu_gt_unparked(struct drm_i915_private *i915);
+void i915_pmu_gt_parked(struct intel_gt *gt);
+void i915_pmu_gt_unparked(struct intel_gt *gt);
#else
static inline int i915_pmu_init(void) { return 0; }
static inline void i915_pmu_exit(void) {}
static inline void i915_pmu_register(struct drm_i915_private *i915) {}
static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
-static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {}
-static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {}
+static inline void i915_pmu_gt_parked(struct intel_gt *gt) {}
+static inline void i915_pmu_gt_unparked(struct intel_gt *gt) {}
#endif
#endif
--
2.36.1
[Intel-gfx] [PATCH v6 6/7] drm/i915/pmu: Prepare for multi-tile non-engine counters
From: Tvrtko Ursulin
Reserve some bits in the counter config namespace which will carry the
tile id and prepare the code to handle this.
No per tile counters have been added yet.
v2:
- Fix checkpatch issues
- Use 4 bits for gt id in non-engine counters. Drop FIXME.
- Set MAX GTs to 4. Drop FIXME.
v3: (Ashutosh, Tvrtko)
- Drop BUG_ON that would never fire
- Make enable u64
- Pull in some code from next patch
v4: Set I915_PMU_MAX_GTS to 2 (Tvrtko)
v5: s/u64/u32 where needed (Ashutosh)
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 146 +++-
drivers/gpu/drm/i915/i915_pmu.h | 9 +-
include/uapi/drm/i915_drm.h | 17 +++-
3 files changed, 127 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index ecb57a94143e..5cfc322e69b4 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -56,11 +56,21 @@ static bool is_engine_config(const u64 config)
return config < __I915_PMU_OTHER(0);
}
+static unsigned int config_gt_id(const u64 config)
+{
+ return config >> __I915_PMU_GT_SHIFT;
+}
+
+static u64 config_counter(const u64 config)
+{
+ return config & ~(~0ULL << __I915_PMU_GT_SHIFT);
+}
+
static unsigned int other_bit(const u64 config)
{
unsigned int val;
- switch (config) {
+ switch (config_counter(config)) {
case I915_PMU_ACTUAL_FREQUENCY:
val = __I915_PMU_ACTUAL_FREQUENCY_ENABLED;
break;
@@ -78,7 +88,9 @@ static unsigned int other_bit(const u64 config)
return -1;
}
- return I915_ENGINE_SAMPLE_COUNT + val;
+ return I915_ENGINE_SAMPLE_COUNT +
+ config_gt_id(config) * __I915_PMU_TRACKED_EVENT_COUNT +
+ val;
}
static unsigned int config_bit(const u64 config)
@@ -115,6 +127,18 @@ static unsigned int event_bit(struct perf_event *event)
return config_bit(event->attr.config);
}
+static u32 frequency_enabled_mask(void)
+{
+ unsigned int i;
+ u32 mask = 0;
+
+ for (i = 0; i < I915_PMU_MAX_GTS; i++)
+ mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) |
+ config_mask(__I915_PMU_REQUESTED_FREQUENCY(i));
+
+ return mask;
+}
+
static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
{
struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
@@ -131,9 +155,7 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool
gpu_active)
* Mask out all the ones which do not need the timer, or in
* other words keep all the ones that could need the timer.
*/
- enable &= config_mask(I915_PMU_ACTUAL_FREQUENCY) |
- config_mask(I915_PMU_REQUESTED_FREQUENCY) |
- ENGINE_SAMPLE_MASK;
+ enable &= frequency_enabled_mask() | ENGINE_SAMPLE_MASK;
/*
* When the GPU is idle per-engine counters do not need to be
@@ -175,9 +197,37 @@ static inline s64 ktime_since_raw(const ktime_t kt)
return ktime_to_ns(ktime_sub(ktime_get_raw(), kt));
}
+static unsigned int
+__sample_idx(struct i915_pmu *pmu, unsigned int gt_id, int sample)
+{
+ unsigned int idx = gt_id * __I915_NUM_PMU_SAMPLERS + sample;
+
+ GEM_BUG_ON(idx >= ARRAY_SIZE(pmu->sample));
+
+ return idx;
+}
+
+static u64 read_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample)
+{
+ return pmu->sample[__sample_idx(pmu, gt_id, sample)].cur;
+}
+
+static void
+store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val)
+{
+ pmu->sample[__sample_idx(pmu, gt_id, sample)].cur = val;
+}
+
+static void
+add_sample_mult(struct i915_pmu *pmu, unsigned int gt_id, int sample, u32 val,
u32 mul)
+{
+ pmu->sample[__sample_idx(pmu, gt_id, sample)].cur += mul_u32_u32(val,
mul);
+}
+
static u64 get_rc6(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
+ const unsigned int gt_id = gt->info.id;
struct i915_pmu *pmu = &i915->pmu;
unsigned long flags;
bool awake = false;
@@ -192,7 +242,7 @@ static u64 get_rc6(struct intel_gt *gt)
spin_lock_irqsave(&pmu->lock, flags);
if (awake) {
- pmu->sample[__I915_SAMPLE_RC6].cur = val;
+ store_sample(pmu, gt_id, __I915_SAMPLE_RC6, val);
} else {
/*
* We think we are runtime suspended.
@@ -201,14 +251,14 @@ static u64 get_rc6(struct intel_gt *gt)
* on top of the last known real value, as the approximated RC6
* counter value.
*/
- val = ktime_since_raw(pmu->sleep_last);
- val += pmu->sample[__I915_SAMPLE_RC6].cur;
+ val = ktime_since_raw(pmu->sleep_last[gt_id]);
+ val += read_sample(pmu, gt_id, __I915_SAMPLE_RC6);
}
- if (val < p
[Intel-gfx] [PATCH v6 3/7] drm/i915/pmu: Skip sampling engines with no enabled counters
From: Tvrtko Ursulin
As we have more and more engines do not waste time sampling the ones no-
one is monitoring.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 9edf87ee5d10..6d594f67f365 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -350,6 +350,9 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns)
return;
for_each_engine(engine, gt, id) {
+ if (!engine->pmu.enable)
+ continue;
+
if (!intel_engine_pm_get_if_awake(engine))
continue;
--
2.36.1
[Intel-gfx] [PATCH v6 0/7] Add MTL PMU support for multi-gt
With MTL, frequency and rc6 counters are specific to a gt. Export these counters via gt-specific events to the user space. v2: Remove aggregation support from kernel v3: Review comments (Ashutosh, Tvrtko) v4: - Include R-b for 6/6 - Add Test-with - Fix versioning info in cover letter v5: - Include "drm/i915/pmu: Change bitmask of enabled events to u32" Signed-off-by: Umesh Nerlige Ramappa Test-with: 20230513022234.2832233-1-umesh.nerlige.rama...@intel.com Tvrtko Ursulin (7): drm/i915/pmu: Change bitmask of enabled events to u32 drm/i915/pmu: Support PMU for all engines drm/i915/pmu: Skip sampling engines with no enabled counters drm/i915/pmu: Transform PMU parking code to be GT based drm/i915/pmu: Add reference counting to the sampling timer drm/i915/pmu: Prepare for multi-tile non-engine counters drm/i915/pmu: Export counters from all tiles drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +- drivers/gpu/drm/i915/i915_pmu.c | 290 ++ drivers/gpu/drm/i915/i915_pmu.h | 22 +- include/uapi/drm/i915_drm.h | 17 +- 4 files changed, 238 insertions(+), 95 deletions(-) -- 2.36.1
[Intel-gfx] [PATCH v6 1/7] drm/i915/pmu: Change bitmask of enabled events to u32
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless) mistake.
Also add some asserts to make sure the internal field does not overflow
in the future.
v2: Fix WARN_ON firing for INTERRUPT event (Umesh)
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_pmu.c | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 7ece883a7d95..96543dce2db1 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -50,7 +50,7 @@ static u8 engine_event_instance(struct perf_event *event)
return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
}
-static bool is_engine_config(u64 config)
+static bool is_engine_config(const u64 config)
{
return config < __I915_PMU_OTHER(0);
}
@@ -88,9 +88,20 @@ static unsigned int config_bit(const u64 config)
return other_bit(config);
}
-static u64 config_mask(u64 config)
+static u32 config_mask(const u64 config)
{
- return BIT_ULL(config_bit(config));
+ unsigned int bit = config_bit(config);
+
+ if (__builtin_constant_p(config))
+ BUILD_BUG_ON(bit >
+BITS_PER_TYPE(typeof_member(struct i915_pmu,
+enable)) - 1);
+ else
+ WARN_ON_ONCE(bit >
+BITS_PER_TYPE(typeof_member(struct i915_pmu,
+enable)) - 1);
+
+ return BIT(config_bit(config));
}
static bool is_engine_event(struct perf_event *event)
@@ -633,11 +644,10 @@ static void i915_pmu_enable(struct perf_event *event)
{
struct drm_i915_private *i915 =
container_of(event->pmu, typeof(*i915), pmu.base);
+ const unsigned int bit = event_bit(event);
struct i915_pmu *pmu = &i915->pmu;
unsigned long flags;
- unsigned int bit;
- bit = event_bit(event);
if (bit == -1)
goto update;
@@ -651,7 +661,7 @@ static void i915_pmu_enable(struct perf_event *event)
GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
GEM_BUG_ON(pmu->enable_count[bit] == ~0);
- pmu->enable |= BIT_ULL(bit);
+ pmu->enable |= BIT(bit);
pmu->enable_count[bit]++;
/*
@@ -698,7 +708,7 @@ static void i915_pmu_disable(struct perf_event *event)
{
struct drm_i915_private *i915 =
container_of(event->pmu, typeof(*i915), pmu.base);
- unsigned int bit = event_bit(event);
+ const unsigned int bit = event_bit(event);
struct i915_pmu *pmu = &i915->pmu;
unsigned long flags;
@@ -734,7 +744,7 @@ static void i915_pmu_disable(struct perf_event *event)
* bitmask when the last listener on an event goes away.
*/
if (--pmu->enable_count[bit] == 0) {
- pmu->enable &= ~BIT_ULL(bit);
+ pmu->enable &= ~BIT(bit);
pmu->timer_enabled &= pmu_needs_timer(pmu, true);
}
--
2.36.1
[Intel-gfx] [PATCH v6 2/7] drm/i915/pmu: Support PMU for all engines
From: Tvrtko Ursulin
Given how the metrics are already exported, we also need to run sampling
over engines from all GTs.
Problem of GT frequencies is left for later.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 96543dce2db1..9edf87ee5d10 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -10,6 +10,7 @@
#include "gt/intel_engine_pm.h"
#include "gt/intel_engine_regs.h"
#include "gt/intel_engine_user.h"
+#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_gt_regs.h"
#include "gt/intel_rc6.h"
@@ -425,8 +426,9 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
struct drm_i915_private *i915 =
container_of(hrtimer, struct drm_i915_private, pmu.timer);
struct i915_pmu *pmu = &i915->pmu;
- struct intel_gt *gt = to_gt(i915);
unsigned int period_ns;
+ struct intel_gt *gt;
+ unsigned int i;
ktime_t now;
if (!READ_ONCE(pmu->timer_enabled))
@@ -442,8 +444,13 @@ static enum hrtimer_restart i915_sample(struct hrtimer
*hrtimer)
* grabbing the forcewake. However the potential error from timer call-
* back delay greatly dominates this so we keep it simple.
*/
- engines_sample(gt, period_ns);
- frequency_sample(gt, period_ns);
+
+ for_each_gt(gt, i915, i) {
+ engines_sample(gt, period_ns);
+
+ if (i == 0) /* FIXME */
+ frequency_sample(gt, period_ns);
+ }
hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD));
--
2.36.1
[Intel-gfx] [PATCH v6 7/7] drm/i915/pmu: Export counters from all tiles
From: Tvrtko Ursulin
Start exporting frequency and RC6 counters from all tiles.
Existing counters keep their names and config values and new one use the
namespace added in the previous patch, with the "-gtN" added to their
names.
Interrupts counter is an odd one off. Because it is the global device
counters (not only GT) we choose not to add per tile versions for now.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Aravind Iddamsetty
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_pmu.c | 82 ++---
1 file changed, 55 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 5cfc322e69b4..a814583e19fd 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -940,11 +940,20 @@ static const struct attribute_group
i915_pmu_cpumask_attr_group = {
.attrs = i915_cpumask_attrs,
};
-#define __event(__config, __name, __unit) \
+#define __event(__counter, __name, __unit) \
{ \
- .config = (__config), \
+ .counter = (__counter), \
.name = (__name), \
.unit = (__unit), \
+ .global = false, \
+}
+
+#define __global_event(__counter, __name, __unit) \
+{ \
+ .counter = (__counter), \
+ .name = (__name), \
+ .unit = (__unit), \
+ .global = true, \
}
#define __engine_event(__sample, __name) \
@@ -983,15 +992,16 @@ create_event_attributes(struct i915_pmu *pmu)
{
struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
static const struct {
- u64 config;
+ unsigned int counter;
const char *name;
const char *unit;
+ bool global;
} events[] = {
- __event(I915_PMU_ACTUAL_FREQUENCY, "actual-frequency", "M"),
- __event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency",
"M"),
- __event(I915_PMU_INTERRUPTS, "interrupts", NULL),
- __event(I915_PMU_RC6_RESIDENCY, "rc6-residency", "ns"),
- __event(I915_PMU_SOFTWARE_GT_AWAKE_TIME,
"software-gt-awake-time", "ns"),
+ __event(0, "actual-frequency", "M"),
+ __event(1, "requested-frequency", "M"),
+ __global_event(2, "interrupts", NULL),
+ __event(3, "rc6-residency", "ns"),
+ __event(4, "software-gt-awake-time", "ns"),
};
static const struct {
enum drm_i915_pmu_engine_sample sample;
@@ -1006,12 +1016,17 @@ create_event_attributes(struct i915_pmu *pmu)
struct i915_ext_attribute *i915_attr = NULL, *i915_iter;
struct attribute **attr = NULL, **attr_iter;
struct intel_engine_cs *engine;
- unsigned int i;
+ struct intel_gt *gt;
+ unsigned int i, j;
/* Count how many counters we will be exposing. */
- for (i = 0; i < ARRAY_SIZE(events); i++) {
- if (!config_status(i915, events[i].config))
- count++;
+ for_each_gt(gt, i915, j) {
+ for (i = 0; i < ARRAY_SIZE(events); i++) {
+ u64 config = ___I915_PMU_OTHER(j, events[i].counter);
+
+ if (!config_status(i915, config))
+ count++;
+ }
}
for_each_uabi_engine(engine, i915) {
@@ -1041,26 +1056,39 @@ create_event_attributes(struct i915_pmu *pmu)
attr_iter = attr;
/* Initialize supported non-engine counters. */
- for (i = 0; i < ARRAY_SIZE(events); i++) {
- char *str;
-
- if (config_status(i915, events[i].config))
- continue;
-
- str = kstrdup(events[i].name, GFP_KERNEL);
- if (!str)
- goto err;
+ for_each_gt(gt, i915, j) {
+ for (i = 0; i < ARRAY_SIZE(events); i++) {
+ u64 config = ___I915_PMU_OTHER(j, events[i].counter);
+ char *str;
- *attr_iter++ = &i915_iter->attr.attr;
- i915_iter = add_i915_attr(i915_iter, str, events[i].config);
+ if (config_status(i915, config))
+ continue;
- if (events[i].unit) {
- str = kasprintf(GFP_KERNEL, "%s.unit", events[i].name);
+ if (events[i].global || !HAS_EXTRA_GT_LIST(i915))
+ str = kstrdup(events[i].name, GFP_KERNEL);
+ else
+ str = kasprintf(GFP_KERNEL, "%s-gt%u",
+ events[i].name, j);
if (!str)
goto err;
- *attr_iter++ = &pmu_iter->attr.attr;
- pmu_iter = add_pmu_attr(pmu_iter, str, events[i].unit);
+
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable render power-gating on MTL
== Series Details ==
Series: series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable
render power-gating on MTL
URL : https://patchwork.freedesktop.org/series/117912/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13160 -> Patchwork_117912v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_117912v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_117912v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117912v1/index.html
Participating hosts (36 -> 36)
--
Additional (1): bat-mtlp-6
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_117912v1:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@uncore:
- bat-rpls-2: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-rpls-2/igt@i915_selftest@l...@uncore.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117912v1/bat-rpls-2/igt@i915_selftest@l...@uncore.html
- bat-rpls-1: [PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-rpls-1/igt@i915_selftest@l...@uncore.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117912v1/bat-rpls-1/igt@i915_selftest@l...@uncore.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_mocs:
- {bat-mtlp-8}: [PASS][5] -> [DMESG-FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117912v1/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [ABORT][7] ([i915#4983] / [i915#7920]) ->
[DMESG-FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117912v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html
Known issues
Here are the changes found in Patchwork_117912v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-7567u: [PASS][9] -> [DMESG-FAIL][10] ([i915#5334] /
[i915#7872])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117912v1/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][11] ([i915#6367])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117912v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html
- bat-rpls-1: NOTRUN -> [DMESG-WARN][12] ([i915#6367])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117912v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html
* igt@i915_selftest@live@uncore:
- bat-dg2-11: [PASS][13] -> [ABORT][14] ([i915#7913])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-dg2-11/igt@i915_selftest@l...@uncore.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117912v1/bat-dg2-11/igt@i915_selftest@l...@uncore.html
- bat-dg2-9: [PASS][15] -> [ABORT][16] ([i915#7913] / [i915#8405])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-dg2-9/igt@i915_selftest@l...@uncore.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117912v1/bat-dg2-9/igt@i915_selftest@l...@uncore.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][17] ([i915#6687])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117912v1/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][18] ([i915#6687] / [i915#7978])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117912v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][19] ([i915#1845] / [i915#5354])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117912v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- bat-rpls-1: [INCOMPLETE][20] ([i915#4983] / [i915#7677]) ->
[PASS][21]
[20]:
https://intel-gfx-ci.01.org/t
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable render power-gating on MTL
== Series Details == Series: series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable render power-gating on MTL URL : https://patchwork.freedesktop.org/series/117912/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./drivers/gpu/drm/i915/intel_uncore.h:346:1: warning: trying to copy expression type 31 +./drivers/gpu/drm/i915/intel_uncore.h:351:1: warning: trying to copy expression type 31 +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable render power-gating on MTL
== Series Details == Series: series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable render power-gating on MTL URL : https://patchwork.freedesktop.org/series/117912/ State : warning == Summary == Error: dim checkpatch failed 51fd4c7e1efa drm/i915/mtl: do not enable render power-gating on MTL e61f2c27f201 drm/i915/gt: do not enable render and media power-gating on ADL -:10: WARNING:COMMIT_LOG_USE_LINK: Unknown link reference 'References:', use 'Link:' or 'Closes:' instead #10: References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 total: 0 errors, 1 warnings, 0 checks, 9 lines checked 38b99bb9bc5d drm/i915/selftests: add forcewake_with_spinners tests -:78: CHECK:SPACING: No space is necessary after a cast #78: FILE: drivers/gpu/drm/i915/selftests/intel_uncore.c:397: + intel_klog_error_capture(gt, (intel_engine_mask_t) ~0U); -:84: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst #84: FILE: drivers/gpu/drm/i915/selftests/intel_uncore.c:403: + msleep(3); total: 0 errors, 1 warnings, 1 checks, 104 lines checked
Re: [Intel-gfx] [PATCH v5 1/7] drm/i915/pmu: Change bitmask of enabled events to u32
On Wed, 17 May 2023 13:15:14 -0700, Umesh Nerlige Ramappa wrote: > > Leaving it as is. @Ashutosh, okay to use your R-b without any changes to > this patch? Yes. Reviewed-by: Ashutosh Dixit
Re: [Intel-gfx] [PATCH v5 1/7] drm/i915/pmu: Change bitmask of enabled events to u32
On Wed, May 17, 2023 at 09:25:03AM -0700, Dixit, Ashutosh wrote:
On Wed, 17 May 2023 01:26:15 -0700, Tvrtko Ursulin wrote:
On 17/05/2023 07:55, Umesh Nerlige Ramappa wrote:
> On Tue, May 16, 2023 at 05:25:50PM -0700, Dixit, Ashutosh wrote:
>> On Tue, 16 May 2023 16:35:28 -0700, Umesh Nerlige Ramappa wrote:
>>>
>>
>> Hi Umesh/Tvrtko,
>>
>> Mostly repeating comments/questions made on the previous patch below.
First of all thanks for improving this, my v1 obviously wasn't good enough.
>>
>>> From: Tvrtko Ursulin
>>>
>>> Having it as u64 was a confusing (but harmless) mistake.
>>>
>>> Also add some asserts to make sure the internal field does not overflow
>>> in the future.
>>>
>>> v2: Fix WARN_ON firing for INTERRUPT event (Umesh)
>>>
>>> Signed-off-by: Tvrtko Ursulin
>>> Signed-off-by: Umesh Nerlige Ramappa
>>> Cc: Ashutosh Dixit
>>> ---
>>> drivers/gpu/drm/i915/i915_pmu.c | 26 ++
>>> 1 file changed, 18 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_pmu.c
>>> b/drivers/gpu/drm/i915/i915_pmu.c
>>> index 7ece883a7d95..96543dce2db1 100644
>>> --- a/drivers/gpu/drm/i915/i915_pmu.c
>>> +++ b/drivers/gpu/drm/i915/i915_pmu.c
>>> @@ -50,7 +50,7 @@ static u8 engine_event_instance(struct perf_event
>>> *event)
>>> return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
>>> }
>>>
>>> -static bool is_engine_config(u64 config)
>>> +static bool is_engine_config(const u64 config)
>>> {
>>> return config < __I915_PMU_OTHER(0);
>>> }
>>> @@ -88,9 +88,20 @@ static unsigned int config_bit(const u64 config)
>>> return other_bit(config);
>>> }
>>>
>>> -static u64 config_mask(u64 config)
>>> +static u32 config_mask(const u64 config)
>>> {
>>> - return BIT_ULL(config_bit(config));
>>> + unsigned int bit = config_bit(config);
>>
>> Give that config_bit() can return -1 (I understand it is avoided in
>> moving
>> the code to config_mask from config_bit), maybe the code below should
>> also
>> have that check?
>
> config_mask is only called to check frequency related events in the code,
> so I don't see it returing -1 here.
Yeah that should be fine since -1 would make the below asserts fire
anyway. (If it would get called from a different path in the future.)
>>
>> int bit = config_bit(config);
>>
>> if (bit != -1)
>> {
>> ...
>> }
>>
>> Though as mentioned below the 'if (__builtin_constant_p())' would have to
>> go. Maybe the code could even have stayed in config_bit with the check.
>>
>>> +
>>> + if (__builtin_constant_p(config))
>>> + BUILD_BUG_ON(bit >
>>> + BITS_PER_TYPE(typeof_member(struct i915_pmu,
>>> + enable)) - 1);
>>
>> Given that config comes from the event (it is event->attr.config), can
>> this
>> ever be a builtin constant?
>
> Not sure about earlier code where these checks were inside config_bit(),
> but with changes I made, I don't see this being a builtin
> constant. However, nothing prevents a caller from just passing a
> builtin_constant to this in future.
Are you sure? I would have thought it would always be a compile time
constant now that the check is in config_mask. Aahhh.. with the multi-tile
changes maybe it can't unroll the loops and calculate the masks at compile
time. Maybe it is a bit too much and we should drop the
__builtin_constant_p branch? Probably..
Ah yes, with the code move to config_mask, they really all are compile time
constants (provided compiler can unroll the loops) so at least that is the
justfication for leaving the __builtin_constant_p in. So I'd probably just
leave it as is (though it is a bit too much).
But I guess it is safe to use GEM_WARN_ON_ONCE instead of WARN_ON_ONCE
since there are no external callers (nothing coming from event) now. That
way at least production builds don't have to have the check.
Hmm, there's a GEM_WARN_ON but no GEM_WARN_ON_ONCE. So leave that as is too
I guess.
So I'm ok with the code staying as is. Enough bike-shed on this already.
Leaving it as is. @Ashutosh, okay to use your R-b without any changes to
this patch?
Thanks,
Umesh
Thanks.
--
Ashutosh
Regards,
Tvrtko
>
> Thanks,
> Umesh
>
>>
>>> + else
>>> + WARN_ON_ONCE(bit >
>>> + BITS_PER_TYPE(typeof_member(struct i915_pmu,
>>> + enable)) - 1);
>>
>> There is really an even stricter limit on what the bit can be, which is
>> the
>> total number of possible events but anyway this is good enough.
>>
>> After addressing the above, this patch is:
>>
>> Reviewed-by: Ashutosh Dixit
>>
>>> +
>>> + return BIT(config_bit(config));
>>> }
>>>
>>> static bool is_engine_event(struct perf_event *event)
>>> @@ -633,11 +644,10 @@ static void i915_pmu_enable(struct perf_event
>>> *event)
>>> {
>>> struct drm_i915_private *i915 =
>>> container_of(event->pmu, typeof(*i915), pmu.base);
>>> + const unsigned int bit = event_bit(event);
>>> struct i915_pm
Re: [Intel-gfx] [PATCH] drm/i915/mtl: do not enable render power-gating on MTL
On Wed, May 17, 2023 at 05:36:33PM +0200, Das, Nirmoy wrote: > > On 5/17/2023 5:25 PM, Vivi, Rodrigo wrote: > > On Wed, 2023-05-17 at 17:12 +0200, Das, Nirmoy wrote: > > > On 5/17/2023 3:59 PM, Andrzej Hajda wrote: > > > > Multiple CI tests fails with forcewake ack timeouts > > > > if render power gating is enabled. > > > > BSpec 52698 clearly states it should be 0 for MTL. > > > > > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 > > > > Signed-off-by: Andrzej Hajda > > > > --- > > > > drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +++-- > > > > 1 file changed, 3 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c > > > > b/drivers/gpu/drm/i915/gt/intel_rc6.c > > > > index 908a3d0f2343f4..ebb2373dd73640 100644 > > > > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c > > > > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c > > > > @@ -117,8 +117,9 @@ static void gen11_rc6_enable(struct intel_rc6 > > > > *rc6) > > > > GEN6_RC_CTL_RC6_ENABLE | > > > > GEN6_RC_CTL_EI_MODE(1); > > > > - /* Wa_16011777198 - Render powergating must remain disabled > > > > */ > > > > - if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) > > > > || > > > > + /* Wa_16011777198 and BSpec 52698 - Render powergating must > > > > be off */ > > > Nice catch! > > Indeed! What a mess in the workaround database. > > It is telling us that no_impact on MTL SKUs while we clearly needs > > that. I tried to reopen that and get that fixed in the hsds. > > > > > > > instead of bspec you could add Wa_1401266. > > not actually. > > 16011777198 is the right lineage number for 1401266. > > Besides, 1401266 is for DG2 anyway. > > > > Let's keep the way Adrzej put with the BSPec reference besides the > > lineage. > > Makes sense, didn't realize 1401266 is much older. > > Thanks! > > > > > > > > > > + if (IS_METEORLAKE(gt->i915) || > > > > + IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) > > > > || > > > > IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) > > > > pg_enable = > > > > GEN9_MEDIA_PG_ENABLE | > > > > > > > > --- > > > > base-commit: 01d3dd92d1b71421f6ee85e1bea829e0a917d979 > > > > change-id: 20230517-mtl_disable_render_pg-b9f9f1567f9e > > > ^ unwanted artifacts ? Otherwise this looks good to me. > > > > > > Reviewed-by: Nirmoy Das > > with the artifacts removed: > > Reviewed-by: Rodrigo Vivi Folks, please do not merge this patch. At least not as it is right now... We need to root cause this. The hw bug related to this workaround was really fixed and this workaround should not be needed in MTL. We need to find the root cause instead of masking it here. Or at least merge as temporary FIXME/XXX and then work to get the root cause... The BSPec will get updated to remove the MTL mention there. Sorry about that. > > > > > > > > Best regards,
[Intel-gfx] [CI DO_NOT_MERGE 1/3] drm/i915/mtl: do not enable render power-gating on MTL
Multiple CI tests fails with forcewake ack timeouts if render power gating is enabled. BSpec 52698 clearly states it should be 0 for MTL. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 908a3d0f2343f4..ebb2373dd73640 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -117,8 +117,9 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) GEN6_RC_CTL_RC6_ENABLE | GEN6_RC_CTL_EI_MODE(1); - /* Wa_16011777198 - Render powergating must remain disabled */ - if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || + /* Wa_16011777198 and BSpec 52698 - Render powergating must be off */ + if (IS_METEORLAKE(gt->i915) || + IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) pg_enable = GEN9_MEDIA_PG_ENABLE | -- 2.34.1
[Intel-gfx] [CI DO_NOT_MERGE 3/3] drm/i915/selftests: add forcewake_with_spinners tests
The test examines if running spinners do not interfere with forcewake.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/i915/selftests/intel_uncore.c | 85 +++
1 file changed, 85 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c
b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index e4281508d5808b..0ce8a5c5ee0064 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -22,7 +22,10 @@
*
*/
+#include
+#include
#include "../i915_selftest.h"
+#include
static int intel_fw_table_check(const struct intel_forcewake_range *ranges,
unsigned int num_ranges,
@@ -342,12 +345,94 @@ static int live_fw_table(void *arg)
GRAPHICS_VER(gt->i915) >= 9);
}
+static int live_forcewake_with_spinners(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_uncore_forcewake_domain *domain;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ intel_wakeref_t wakeref;
+ struct igt_spinner spin;
+ unsigned int tmp;
+ int err;
+
+ wakeref = intel_runtime_pm_get(gt->uncore->rpm);
+
+ err = igt_spinner_init(&spin, gt);
+ if (err)
+ goto err_rpm;
+
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce;
+ struct i915_request *rq;
+
+ if (!intel_engine_can_store_dword(engine))
+ continue;
+
+ pr_info("%s: Spinning %s\n", __func__, engine->name);
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce)) {
+ err = PTR_ERR(ce);
+ goto err_spin;
+ }
+ rq = igt_spinner_create_request(&spin, ce, MI_ARB_CHECK);
+ intel_context_put(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_spin;
+ }
+ i915_request_add(rq);
+ }
+
+ intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
+ for_each_fw_domain(domain, gt->uncore, tmp) {
+ if (readl(domain->reg_ack) & FORCEWAKE_KERNEL)
+ continue;
+ pr_err("%s: not acked\n",
intel_uncore_forcewake_domain_to_str(domain->id));
+ err = -EINVAL;
+ }
+ if (err) {
+#if defined(CONFIG_DRM_I915_DEBUG_WAKEREF) // Ugly test of presence of
intel_klog_error_capture
+ intel_klog_error_capture(gt, (intel_engine_mask_t) ~0U);
+#else
+ pr_err("Time to catch GuC logs.\n");
+ msleep(4000);
+#endif
+ }
+ msleep(3);
+ intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
+
+err_spin:
+ igt_spinner_fini(&spin);
+err_rpm:
+ intel_runtime_pm_put(gt->uncore->rpm, wakeref);
+
+ return err;
+}
+
+static int live_forcewake_with_spinners_25s(void *arg)
+{
+ ktime_t t = ktime_get();
+ int err = 0;
+
+ while (ktime_ms_delta(ktime_get(), t) < 25000) {
+ err = live_forcewake_with_spinners(arg);
+ if (err)
+ break;
+ }
+
+ return err;
+}
+
int intel_uncore_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_fw_table),
SUBTEST(live_forcewake_ops),
SUBTEST(live_forcewake_domains),
+ SUBTEST(live_forcewake_with_spinners),
+ SUBTEST(live_forcewake_with_spinners_25s),
};
return intel_gt_live_subtests(tests, to_gt(i915));
--
2.34.1
[Intel-gfx] [CI DO_NOT_MERGE 2/3] drm/i915/gt: do not enable render and media power-gating on ADL
Multiple CI tests fails with forcewake timeouts. Disabling power gating for render and media solves the issue. References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index ebb2373dd73640..e80685ac92dbef 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -124,6 +124,9 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) pg_enable = GEN9_MEDIA_PG_ENABLE | GEN11_MEDIA_SAMPLER_PG_ENABLE; + /* Testing */ + else if (IS_ALDERLAKE_S(gt->i915) || IS_ALDERLAKE_P(gt->i915)) + pg_enable = 0; else pg_enable = GEN9_RENDER_PG_ENABLE | -- 2.34.1
Re: [Intel-gfx] [PATCH v5 08/10] iommufd: Add iommufd_ctx_has_group()
On Sat, 13 May 2023 06:21:34 -0700
Yi Liu wrote:
> to check if any device within the given iommu_group has been bound with
Nit, I find these commit logs where the subject line is intended to
flow into the commit log to form a complete sentence difficult to read.
I expect complete thoughts within the commit log itself and the subject
should be a separate summary of the log. Repeating the subject within
the commit log is ok.
> the iommufd_ctx. This helpful for the checking on device ownership for
s/This/This is/
> the devices which have been bound but cannot be bound to any other iommufd
s/have been/have not been/?
> as the iommu_group has been bound.
>
> Signed-off-by: Yi Liu
> ---
> drivers/iommu/iommufd/device.c | 29 +
> include/linux/iommufd.h| 8
> 2 files changed, 37 insertions(+)
>
> diff --git a/drivers/iommu/iommufd/device.c b/drivers/iommu/iommufd/device.c
> index 81466b97023f..5e5f7912807b 100644
> --- a/drivers/iommu/iommufd/device.c
> +++ b/drivers/iommu/iommufd/device.c
> @@ -98,6 +98,35 @@ struct iommufd_device *iommufd_device_bind(struct
> iommufd_ctx *ictx,
> }
> EXPORT_SYMBOL_NS_GPL(iommufd_device_bind, IOMMUFD);
>
> +/**
> + * iommufd_ctx_has_group - True if the struct device is bound to this ictx
What struct device? Isn't this "True if any device within the group is
bound to the ictx"?
> + * @ictx: iommufd file descriptor
> + * @group: Pointer to a physical iommu_group struct
> + *
> + * True if a iommufd_device_bind() is present for any device within the
> + * group.
How can a function be present for a device? Maybe "True if any device
within the group has been bound to this ictx, ex. via
iommufd_device_bind(), therefore implying ictx ownership of the group." Thanks,
Alex
> + */
> +bool iommufd_ctx_has_group(struct iommufd_ctx *ictx, struct iommu_group
> *group)
> +{
> + struct iommufd_object *obj;
> + unsigned long index;
> +
> + if (!ictx || !group)
> + return false;
> +
> + xa_lock(&ictx->objects);
> + xa_for_each(&ictx->objects, index, obj) {
> + if (obj->type == IOMMUFD_OBJ_DEVICE &&
> + container_of(obj, struct iommufd_device, obj)->group ==
> group) {
> + xa_unlock(&ictx->objects);
> + return true;
> + }
> + }
> + xa_unlock(&ictx->objects);
> + return false;
> +}
> +EXPORT_SYMBOL_NS_GPL(iommufd_ctx_has_group, IOMMUFD);
> +
> /**
> * iommufd_device_unbind - Undo iommufd_device_bind()
> * @idev: Device returned by iommufd_device_bind()
> diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h
> index 68cd65274e28..e49c16cd6831 100644
> --- a/include/linux/iommufd.h
> +++ b/include/linux/iommufd.h
> @@ -16,6 +16,7 @@ struct page;
> struct iommufd_ctx;
> struct iommufd_access;
> struct file;
> +struct iommu_group;
>
> struct iommufd_device *iommufd_device_bind(struct iommufd_ctx *ictx,
> struct device *dev, u32 *id);
> @@ -56,6 +57,7 @@ void iommufd_ctx_get(struct iommufd_ctx *ictx);
> #if IS_ENABLED(CONFIG_IOMMUFD)
> struct iommufd_ctx *iommufd_ctx_from_file(struct file *file);
> void iommufd_ctx_put(struct iommufd_ctx *ictx);
> +bool iommufd_ctx_has_group(struct iommufd_ctx *ictx, struct iommu_group
> *group);
>
> int iommufd_access_pin_pages(struct iommufd_access *access, unsigned long
> iova,
>unsigned long length, struct page **out_pages,
> @@ -77,6 +79,12 @@ static inline void iommufd_ctx_put(struct iommufd_ctx
> *ictx)
> {
> }
>
> +static inline bool iommufd_ctx_has_group(struct iommufd_ctx *ictx,
> + struct iommu_group *group)
> +{
> + return false;
> +}
> +
> static inline int iommufd_access_pin_pages(struct iommufd_access *access,
> unsigned long iova,
> unsigned long length,
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: do not enable render power-gating on MTL
== Series Details ==
Series: drm/i915/mtl: do not enable render power-gating on MTL
URL : https://patchwork.freedesktop.org/series/117883/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13160 -> Patchwork_117883v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_117883v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_117883v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v1/index.html
Participating hosts (36 -> 37)
--
Additional (2): fi-kbl-soraka bat-mtlp-6
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_117883v1:
### IGT changes ###
Possible regressions
* igt@i915_suspend@basic-s3-without-i915:
- fi-kbl-7567u: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/fi-kbl-7567u/igt@i915_susp...@basic-s3-without-i915.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v1/fi-kbl-7567u/igt@i915_susp...@basic-s3-without-i915.html
Known issues
Here are the changes found in Patchwork_117883v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#7913])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@requests:
- bat-rpls-2: [PASS][6] -> [ABORT][7] ([i915#4983] / [i915#7913])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-rpls-2/igt@i915_selftest@l...@requests.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v1/bat-rpls-2/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@slpc:
- bat-rpls-1: NOTRUN -> [DMESG-WARN][8] ([i915#6367])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][9] ([i915#6687] / [i915#7978])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271]) +14 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v1/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#1845] / [i915#5354]) +2
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][12] ([i915#3546]) +1 similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v1/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4579])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v1/fi-kbl-soraka/igt@kms_setm...@basic-clone-single-crtc.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- bat-rpls-1: [INCOMPLETE][14] ([i915#4983] / [i915#7677]) ->
[PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-rpls-1/igt@i915_selftest@l...@hangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v1/bat-rpls-1/igt@i915_selftest@l...@hangcheck.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [FAIL][16] ([i915#7932]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117883v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
{name}: This element is suppressed. This means it is ignored when computing
Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/mtl: Add MTL performance tuning changes
Quoting Radhakrishna Sripada (2023-05-16 21:40:45-03:00)
>MTL reuses the tuning parameters for DG2. Extend the dg2
>performance tuning parameters to MTL.
>
>v2: Add DRAW_WATERMARK tuning parameter.
>v3: Limit DRAW_WATERMARK tuning to non A0 step.
>v4: Reorder platform checks.
>Restrict Blend fill caching optimization to Render GT.
>
>Bspec: 68331
>Cc: Haridhar Kalvala
>Cc: Matt Roper
>Cc: Gustavo Sousa
>Signed-off-by: Radhakrishna Sripada
>---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 15 ++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>index 786349e95487..b6d3185cf868 100644
>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>@@ -817,6 +817,12 @@ static void mtl_ctx_workarounds_init(struct
>intel_engine_cs *engine,
> {
> struct drm_i915_private *i915 = engine->i915;
>
>+dg2_ctx_gt_tuning_init(engine, wal);
>+
>+if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>+IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>+wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
>+
I would put those (dg2_ctx_gt_tuning_init() call and DRAW_WATERMARK
programming) in a separate mtl_ctx_gt_tuning_init() function. That would
be more consistent with having tuning for context save/restore registers
in separate functions and makes it easy to see this particular programming of
DRAW_WATERMARK is a recommended tuning instead of a workaround.
With that,
Reviewed-by: Gustavo Sousa
--
Gustavo Sousa
> if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> /* Wa_14014947963 */
>@@ -1748,6 +1754,13 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct
>i915_wa_list *wal)
> */
> static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
> {
>+if (IS_METEORLAKE(gt->i915)) {
>+if (gt->type != GT_MEDIA)
>+wa_mcr_write_or(wal, XEHP_L3SCQREG7,
>BLEND_FILL_CACHING_OPT_DIS);
>+
>+wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
>+}
>+
> if (IS_PONTEVECCHIO(gt->i915)) {
> wa_mcr_write(wal, XEHPC_L3SCRUB,
> SCRUB_CL_DWNGRADE_SHARED |
> SCRUB_RATE_4B_PER_CLK);
>@@ -2944,7 +2957,7 @@ static void
> add_render_compute_tuning_settings(struct drm_i915_private *i915,
>struct i915_wa_list *wal)
> {
>-if (IS_DG2(i915))
>+if (IS_METEORLAKE(i915) || IS_DG2(i915))
> wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL,
> STACKID_CTRL_512);
>
> /*
>--
>2.34.1
>
Re: [Intel-gfx] [PATCH v5 07/10] vfio: Add helper to search vfio_device in a dev_set
On Sat, 13 May 2023 06:21:33 -0700
Yi Liu wrote:
> There are drivers that need to search vfio_device within a given dev_set.
> e.g. vfio-pci. So add a helper.
>
> Signed-off-by: Yi Liu
> ---
> drivers/vfio/pci/vfio_pci_core.c | 8 +++-
> drivers/vfio/vfio_main.c | 15 +++
> include/linux/vfio.h | 3 +++
> 3 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/vfio/pci/vfio_pci_core.c
> b/drivers/vfio/pci/vfio_pci_core.c
> index 39e7823088e7..4df2def35bdd 100644
> --- a/drivers/vfio/pci/vfio_pci_core.c
> +++ b/drivers/vfio/pci/vfio_pci_core.c
> @@ -2335,12 +2335,10 @@ static bool vfio_dev_in_groups(struct
> vfio_pci_core_device *vdev,
> static int vfio_pci_is_device_in_set(struct pci_dev *pdev, void *data)
> {
> struct vfio_device_set *dev_set = data;
> - struct vfio_device *cur;
>
> - list_for_each_entry(cur, &dev_set->device_list, dev_set_list)
> - if (cur->dev == &pdev->dev)
> - return 0;
> - return -EBUSY;
> + lockdep_assert_held(&dev_set->lock);
> +
> + return vfio_find_device_in_devset(dev_set, &pdev->dev) ? 0 : -EBUSY;
Maybe an opportunity to revisit why this returns -EBUSY rather than
something reasonable like -ENODEV. It looks like we picked up the
-EBUSY in a882c16a2b7e where I think it was trying to preserve the
return of vfio_pci_try_zap_and_vma_lock_cb() but the return value here
is not even propagated so this looks like an chance to have it make
sense again. Thanks,
Alex
> }
>
> /*
> diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
> index f0ca33b2e1df..ab4f3a794f78 100644
> --- a/drivers/vfio/vfio_main.c
> +++ b/drivers/vfio/vfio_main.c
> @@ -141,6 +141,21 @@ unsigned int vfio_device_set_open_count(struct
> vfio_device_set *dev_set)
> }
> EXPORT_SYMBOL_GPL(vfio_device_set_open_count);
>
> +struct vfio_device *
> +vfio_find_device_in_devset(struct vfio_device_set *dev_set,
> +struct device *dev)
> +{
> + struct vfio_device *cur;
> +
> + lockdep_assert_held(&dev_set->lock);
> +
> + list_for_each_entry(cur, &dev_set->device_list, dev_set_list)
> + if (cur->dev == dev)
> + return cur;
> + return NULL;
> +}
> +EXPORT_SYMBOL_GPL(vfio_find_device_in_devset);
> +
> /*
> * Device objects - create, release, get, put, search
> */
> diff --git a/include/linux/vfio.h b/include/linux/vfio.h
> index fcbe084b18c8..4c17395ed4d2 100644
> --- a/include/linux/vfio.h
> +++ b/include/linux/vfio.h
> @@ -259,6 +259,9 @@ void vfio_unregister_group_dev(struct vfio_device
> *device);
>
> int vfio_assign_device_set(struct vfio_device *device, void *set_id);
> unsigned int vfio_device_set_open_count(struct vfio_device_set *dev_set);
> +struct vfio_device *
> +vfio_find_device_in_devset(struct vfio_device_set *dev_set,
> +struct device *dev);
>
> int vfio_mig_get_next_state(struct vfio_device *device,
> enum vfio_device_mig_state cur_fsm,
Re: [Intel-gfx] [PATCH v9 2/2] drm/i915: Allow user to set cache at BO creation
> On 16/05/2023 19:11, fei.y...@intel.com wrote:
>> From: Fei Yang
>>
>> To comply with the design that buffer objects shall have immutable
>> cache setting through out their life cycle, {set, get}_caching ioctl's
>> are no longer supported from MTL onward. With that change caching
>> policy can only be set at object creation time. The current code
>> applies a default (platform dependent) cache setting for all objects.
>> However this is not optimal for performance tuning. The patch extends
>> the existing gem_create uAPI to let user set PAT index for the object
>> at creation time.
>> The new extension is platform independent, so UMD's can switch to using
>> this extension for older platforms as well, while {set, get}_caching are
>> still supported on these legacy paltforms for compatibility reason.
>>
>> Test igt@gem_create@create_ext_set_pat posted at
>> https://patchwork.freedesktop.org/series/117695/
>>
>> Tested with https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
>>
>> Signed-off-by: Fei Yang
>> Cc: Chris Wilson
>> Cc: Matt Roper
>> Cc: Andi Shyti
>> Reviewed-by: Andi Shyti
>> Tested-by: Jordan Justen
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++
>> drivers/gpu/drm/i915/gem/i915_gem_object.c | 6
>> include/uapi/drm/i915_drm.h| 42 ++
>> tools/include/uapi/drm/i915_drm.h | 42 ++
>> 4 files changed, 126 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_create.c
>> index bfe1dbda4cb7..644a936248ad 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
>> @@ -245,6 +245,7 @@ struct create_ext {
>>unsigned int n_placements;
>>unsigned int placement_mask;
>>unsigned long flags;
>> + unsigned int pat_index;
>> };
>>
>> static void repr_placements(char *buf, size_t size,
>> @@ -394,11 +395,39 @@ static int ext_set_protected(struct
>> i915_user_extension __user *base, void *data
>>return 0;
>> }
>>
>> +static int ext_set_pat(struct i915_user_extension __user *base, void *data)
>> +{
>> + struct create_ext *ext_data = data;
>> + struct drm_i915_private *i915 = ext_data->i915;
>> + struct drm_i915_gem_create_ext_set_pat ext;
>> + unsigned int max_pat_index;
>> +
>> + BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
>> + offsetofend(struct drm_i915_gem_create_ext_set_pat,
>> rsvd));
>> +
>> + if (copy_from_user(&ext, base, sizeof(ext)))
>> + return -EFAULT;
>> +
>> + max_pat_index = INTEL_INFO(i915)->max_pat_index;
>> +
>> + if (ext.pat_index > max_pat_index) {
>> + drm_dbg(&i915->drm, "PAT index is invalid: %u\n",
>> + ext.pat_index);
>> + return -EINVAL;
>> + }
>> +
>> + ext_data->pat_index = ext.pat_index;
>> +
>> + return 0;
>> +}
>> +
>> static const i915_user_extension_fn create_extensions[] = {
>>[I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements,
>>[I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected,
>> + [I915_GEM_CREATE_EXT_SET_PAT] = ext_set_pat,
>> };
>>
>> +#define PAT_INDEX_NOT_SET0x
>> /**
>>* i915_gem_create_ext_ioctl - Creates a new mm object and returns a
>> handle to it.
>>* @dev: drm device pointer
>> @@ -418,6 +447,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void
>> *data,
>>if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS)
>>return -EINVAL;
>>
>> + ext_data.pat_index = PAT_INDEX_NOT_SET;
>>ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
>> create_extensions,
>> ARRAY_SIZE(create_extensions),
>> @@ -454,5 +484,11 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void
>> *data,
>>if (IS_ERR(obj))
>>return PTR_ERR(obj);
>>
>> + if (ext_data.pat_index != PAT_INDEX_NOT_SET) {
>> + i915_gem_object_set_pat_index(obj, ext_data.pat_index);
>> + /* Mark pat_index is set by UMD */
>> + obj->pat_set_by_user = true;
>> + }
>> +
>>return i915_gem_publish(obj, file, &args->size, &args->handle);
>> }
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_object.c
>> index 46a19b099ec8..97ac6fb37958 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
>> @@ -208,6 +208,12 @@ bool i915_gem_object_can_bypass_llc(struct
>> drm_i915_gem_object *obj)
>>if (!(obj->flags & I915_BO_ALLOC_USER))
>>return false;
>>
>> + /*
>> + * Always flush cache for UMD objects at creation time.
>> + */
>> + if (obj->pat_set_by_user)
>> + return true;
>> +
>>/*
>>
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave & Daniel, Here goes drm-intel-fixes for v6.4-rc3. Just one missing null check addition for HDCP code. Regards, Joonas *** drm-intel-fixes-2023-05-17: Add missing null check for HDCP code. The following changes since commit f1fcbaa18b28dec10281551dfe6ed3a3ed80e3d6: Linux 6.4-rc2 (2023-05-14 12:51:40 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2023-05-17 for you to fetch changes up to 5896f2d363d5cfb7510856c90d5e0ed934a1d340: drm/i915/hdcp: Check if media_gt exists (2023-05-15 10:42:35 +0300) Add missing null check for HDCP code. Suraj Kandpal (1): drm/i915/hdcp: Check if media_gt exists drivers/gpu/drm/i915/display/intel_hdcp.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-)
Re: [Intel-gfx] [PATCH v5 06/10] vfio-iommufd: Add helper to retrieve iommufd_ctx and devid for vfio_device
On Wed, May 17, 2023 at 12:40:32PM -0600, Alex Williamson wrote:
> On Wed, 17 May 2023 15:22:27 -0300
> Jason Gunthorpe wrote:
>
> > On Wed, May 17, 2023 at 12:15:17PM -0600, Alex Williamson wrote:
> >
> > > > +int vfio_iommufd_physical_devid(struct vfio_device *vdev)
> > > > +{
> > > > + if (vdev->iommufd_device)
> > > > + return iommufd_device_to_id(vdev->iommufd_device);
> > > > + if (vdev->noiommu_access)
> > > > + return iommufd_access_to_id(vdev->noiommu_access);
> > > > + return -EINVAL;
> > > > +}
> > > > +EXPORT_SYMBOL_GPL(vfio_iommufd_physical_devid);
> > >
> > > I think these exemplify that it would be better if both emulated and
> > > noiommu use the same iommufd_access pointer. Thanks,
> >
> > Oh, I mis understood your other remark.. Yeah good question I have to
> > study this also
>
> I guess I also missed that this wasn't iommufd_access vs
> noiommu_access, it's device vs access, but shouldn't any iommufd_access
> pointer provide the devid? I need to go look why we need two different
> methods to get a devid...
At least this hunk above makes sense, access and device are two
different objects with different types, so having different ID
accessors is reasonably logical.
But it is a good point that this should return the dev id of the
normal access for a normal mdev too
Ideally I'd like to see that we always return a dev id to userspace
for all vfio device types. Then we can rely on it
Jason
Re: [Intel-gfx] [PATCH v5 06/10] vfio-iommufd: Add helper to retrieve iommufd_ctx and devid for vfio_device
On Wed, 17 May 2023 15:22:27 -0300
Jason Gunthorpe wrote:
> On Wed, May 17, 2023 at 12:15:17PM -0600, Alex Williamson wrote:
>
> > > +int vfio_iommufd_physical_devid(struct vfio_device *vdev)
> > > +{
> > > + if (vdev->iommufd_device)
> > > + return iommufd_device_to_id(vdev->iommufd_device);
> > > + if (vdev->noiommu_access)
> > > + return iommufd_access_to_id(vdev->noiommu_access);
> > > + return -EINVAL;
> > > +}
> > > +EXPORT_SYMBOL_GPL(vfio_iommufd_physical_devid);
> >
> > I think these exemplify that it would be better if both emulated and
> > noiommu use the same iommufd_access pointer. Thanks,
>
> Oh, I mis understood your other remark.. Yeah good question I have to
> study this also
I guess I also missed that this wasn't iommufd_access vs
noiommu_access, it's device vs access, but shouldn't any iommufd_access
pointer provide the devid? I need to go look why we need two different
methods to get a devid... Thanks,
Alex
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Use large rings for compute contexts (rev2)
== Series Details ==
Series: drm/i915/gem: Use large rings for compute contexts (rev2)
URL : https://patchwork.freedesktop.org/series/117814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13160 -> Patchwork_117814v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v2/index.html
Participating hosts (36 -> 36)
--
Additional (1): fi-kbl-soraka
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_117814v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v2/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3
similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v2/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][3] ([i915#1886] / [i915#7913])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@guc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][4] ([i915#7852])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v2/bat-rpls-2/igt@i915_selftest@l...@guc.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][5] ([i915#6367])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v2/bat-rpls-2/igt@i915_selftest@l...@slpc.html
- bat-rpls-1: NOTRUN -> [DMESG-WARN][6] ([i915#6367])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v2/bat-rpls-1/igt@i915_selftest@l...@slpc.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][7] ([i915#6687])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v2/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][8] ([i915#6687] / [i915#7978])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v2/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271]) +14 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v2/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#1845] / [i915#5354]) +2
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v2/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][11] ([i915#3546]) +1 similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v2/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4579])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v2/fi-kbl-soraka/igt@kms_setm...@basic-clone-single-crtc.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- bat-rpls-1: [INCOMPLETE][13] ([i915#4983] / [i915#7677]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-rpls-1/igt@i915_selftest@l...@hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v2/bat-rpls-1/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][15] ([i915#4983] / [i915#7461] / [i915#7913]
/ [i915#8347]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-rpls-2/igt@i915_selftest@l...@reset.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v2/bat-rpls-2/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [FAIL][17] ([i915#7932]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117814v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issu
Re: [Intel-gfx] [PATCH v5 06/10] vfio-iommufd: Add helper to retrieve iommufd_ctx and devid for vfio_device
On Wed, May 17, 2023 at 12:15:17PM -0600, Alex Williamson wrote:
> > +int vfio_iommufd_physical_devid(struct vfio_device *vdev)
> > +{
> > + if (vdev->iommufd_device)
> > + return iommufd_device_to_id(vdev->iommufd_device);
> > + if (vdev->noiommu_access)
> > + return iommufd_access_to_id(vdev->noiommu_access);
> > + return -EINVAL;
> > +}
> > +EXPORT_SYMBOL_GPL(vfio_iommufd_physical_devid);
>
> I think these exemplify that it would be better if both emulated and
> noiommu use the same iommufd_access pointer. Thanks,
Oh, I mis understood your other remark.. Yeah good question I have to
study this also
Jason
Re: [Intel-gfx] [PATCH v5 01/10] vfio-iommufd: Create iommufd_access for noiommu devices
On Wed, May 17, 2023 at 11:26:09AM -0600, Alex Williamson wrote: > It's not clear to me why we need a separate iommufd_access for > noiommu. The point was to allocate an ID for the device so we can use that ID with the other interfaces in all cases. Otherwise it is a too weird special case that is probably going to keep causing trouble down the road... Jason
Re: [Intel-gfx] [PATCH 3/3] media: v4l2-core: Describe privacy_led field of v4l2_subdev
Hi Bagas,
On Fri, Feb 03, 2023 at 05:02:15PM +0700, Bagas Sanjaya wrote:
> Stephen Rothwell reported htmldocs warning:
>
> include/media/v4l2-subdev.h:1088: warning: Function parameter or member
> 'privacy_led' not described in 'v4l2_subdev'
>
> Describe privacy_led field to fix the warning.
>
> Link:
> https://lore.kernel.org/linux-next/20230203135303.32da1...@canb.auug.org.au/
> Fixes: 10d96e289fbd77 ("media: v4l2-core: Make the v4l2-core code
> enable/disable the privacy LED if present")
> Reported-by: Stephen Rothwell
> Signed-off-by: Bagas Sanjaya
> ---
> include/media/v4l2-subdev.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/media/v4l2-subdev.h b/include/media/v4l2-subdev.h
> index 1ef5bbbf9d38c8..3e7a97c0657e1c 100644
> --- a/include/media/v4l2-subdev.h
> +++ b/include/media/v4l2-subdev.h
> @@ -1033,6 +1033,7 @@ struct v4l2_subdev_platform_data {
> * @active_state: Active state for the subdev (NULL for subdevs tracking the
> * state internally). Initialized by calling
> * v4l2_subdev_init_finalize().
> + * @privacy_led: Privacy LED associated with the sub-device.
> * @enabled_streams: Bitmask of enabled streams used by
> *v4l2_subdev_enable_streams() and
> *v4l2_subdev_disable_streams() helper functions for fallback
I'm not sure how this ever was an issue --- privacy_led field was
documented in the same patch that added it.
--
Kind regards,
Sakari Ailus
Re: [Intel-gfx] [PATCH v5 06/10] vfio-iommufd: Add helper to retrieve iommufd_ctx and devid for vfio_device
On Sat, 13 May 2023 06:21:32 -0700
Yi Liu wrote:
> This is needed by the vfio-pci driver to report affected devices in the
> hot reset for a given device.
>
> Signed-off-by: Yi Liu
> ---
> drivers/iommu/iommufd/device.c | 24
> drivers/vfio/iommufd.c | 20
> include/linux/iommufd.h| 6 ++
> include/linux/vfio.h | 14 ++
> 4 files changed, 64 insertions(+)
>
> diff --git a/drivers/iommu/iommufd/device.c b/drivers/iommu/iommufd/device.c
> index 4f9b2142274c..81466b97023f 100644
> --- a/drivers/iommu/iommufd/device.c
> +++ b/drivers/iommu/iommufd/device.c
> @@ -116,6 +116,18 @@ void iommufd_device_unbind(struct iommufd_device *idev)
> }
> EXPORT_SYMBOL_NS_GPL(iommufd_device_unbind, IOMMUFD);
>
> +struct iommufd_ctx *iommufd_device_to_ictx(struct iommufd_device *idev)
> +{
> + return idev->ictx;
> +}
> +EXPORT_SYMBOL_NS_GPL(iommufd_device_to_ictx, IOMMUFD);
> +
> +u32 iommufd_device_to_id(struct iommufd_device *idev)
> +{
> + return idev->obj.id;
> +}
> +EXPORT_SYMBOL_NS_GPL(iommufd_device_to_id, IOMMUFD);
> +
> static int iommufd_device_setup_msi(struct iommufd_device *idev,
> struct iommufd_hw_pagetable *hwpt,
> phys_addr_t sw_msi_start)
> @@ -463,6 +475,18 @@ void iommufd_access_destroy(struct iommufd_access
> *access)
> }
> EXPORT_SYMBOL_NS_GPL(iommufd_access_destroy, IOMMUFD);
>
> +struct iommufd_ctx *iommufd_access_to_ictx(struct iommufd_access *access)
> +{
> + return access->ictx;
> +}
> +EXPORT_SYMBOL_NS_GPL(iommufd_access_to_ictx, IOMMUFD);
> +
> +u32 iommufd_access_to_id(struct iommufd_access *access)
> +{
> + return access->obj.id;
> +}
> +EXPORT_SYMBOL_NS_GPL(iommufd_access_to_id, IOMMUFD);
> +
> int iommufd_access_attach(struct iommufd_access *access, u32 ioas_id)
> {
> struct iommufd_ioas *new_ioas;
> diff --git a/drivers/vfio/iommufd.c b/drivers/vfio/iommufd.c
> index c1379e826052..a18e920be164 100644
> --- a/drivers/vfio/iommufd.c
> +++ b/drivers/vfio/iommufd.c
> @@ -105,6 +105,26 @@ void vfio_iommufd_unbind(struct vfio_device *vdev)
> vdev->ops->unbind_iommufd(vdev);
> }
>
> +struct iommufd_ctx *vfio_iommufd_physical_ictx(struct vfio_device *vdev)
> +{
> + if (vdev->iommufd_device)
> + return iommufd_device_to_ictx(vdev->iommufd_device);
> + if (vdev->noiommu_access)
> + return iommufd_access_to_ictx(vdev->noiommu_access);
> + return NULL;
> +}
> +EXPORT_SYMBOL_GPL(vfio_iommufd_physical_ictx);
> +
> +int vfio_iommufd_physical_devid(struct vfio_device *vdev)
> +{
> + if (vdev->iommufd_device)
> + return iommufd_device_to_id(vdev->iommufd_device);
> + if (vdev->noiommu_access)
> + return iommufd_access_to_id(vdev->noiommu_access);
> + return -EINVAL;
> +}
> +EXPORT_SYMBOL_GPL(vfio_iommufd_physical_devid);
I think these exemplify that it would be better if both emulated and
noiommu use the same iommufd_access pointer. Thanks,
Alex
> +
> /*
> * The physical standard ops mean that the iommufd_device is bound to the
> * physical device vdev->dev that was provided to vfio_init_group_dev().
> Drivers
> diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h
> index 1129a36a74c4..68cd65274e28 100644
> --- a/include/linux/iommufd.h
> +++ b/include/linux/iommufd.h
> @@ -24,6 +24,9 @@ void iommufd_device_unbind(struct iommufd_device *idev);
> int iommufd_device_attach(struct iommufd_device *idev, u32 *pt_id);
> void iommufd_device_detach(struct iommufd_device *idev);
>
> +struct iommufd_ctx *iommufd_device_to_ictx(struct iommufd_device *idev);
> +u32 iommufd_device_to_id(struct iommufd_device *idev);
> +
> struct iommufd_access_ops {
> u8 needs_pin_pages : 1;
> void (*unmap)(void *data, unsigned long iova, unsigned long length);
> @@ -45,6 +48,9 @@ iommufd_access_create(struct iommufd_ctx *ictx,
> void iommufd_access_destroy(struct iommufd_access *access);
> int iommufd_access_attach(struct iommufd_access *access, u32 ioas_id);
>
> +struct iommufd_ctx *iommufd_access_to_ictx(struct iommufd_access *access);
> +u32 iommufd_access_to_id(struct iommufd_access *access);
> +
> void iommufd_ctx_get(struct iommufd_ctx *ictx);
>
> #if IS_ENABLED(CONFIG_IOMMUFD)
> diff --git a/include/linux/vfio.h b/include/linux/vfio.h
> index a61130bc06a2..fcbe084b18c8 100644
> --- a/include/linux/vfio.h
> +++ b/include/linux/vfio.h
> @@ -115,6 +115,8 @@ struct vfio_device_ops {
> };
>
> #if IS_ENABLED(CONFIG_IOMMUFD)
> +struct iommufd_ctx *vfio_iommufd_physical_ictx(struct vfio_device *vdev);
> +int vfio_iommufd_physical_devid(struct vfio_device *vdev);
> int vfio_iommufd_physical_bind(struct vfio_device *vdev,
> struct iommufd_ctx *ictx, u32 *out_device_id);
> void vfio_iommufd_physical_unbind(struct vfio_device *vdev);
> @@ -124,6 +126,18 @@ int vfio_iommufd_emulated_bi
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Add workaround 14016712196 (rev2)
== Series Details ==
Series: drm/i915/gt: Add workaround 14016712196 (rev2)
URL : https://patchwork.freedesktop.org/series/117661/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13160 -> Patchwork_117661v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/index.html
Participating hosts (36 -> 37)
--
Additional (2): fi-kbl-soraka bat-mtlp-6
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_117661v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3
similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][3] ([i915#1886] / [i915#7913])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][4] ([i915#6367])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/bat-rpls-2/igt@i915_selftest@l...@slpc.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][5] ([i915#6687])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][6] ([i915#6687] / [i915#7978])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271]) +14 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#1845] / [i915#5354])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4579])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/fi-kbl-soraka/igt@kms_setm...@basic-clone-single-crtc.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- bat-rpls-1: [INCOMPLETE][10] ([i915#4983] / [i915#7677]) ->
[PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-rpls-1/igt@i915_selftest@l...@hangcheck.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/bat-rpls-1/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][12] ([i915#4983] / [i915#7461] / [i915#7913]
/ [i915#8347]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13160/bat-rpls-2/igt@i915_selftest@l...@reset.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117661v2/bat-rpls-2/igt@i915_selftest@l...@reset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
[i915#4579]: https://gitlab.freedesktop.org/drm/in
Re: [Intel-gfx] [PATCH v5 01/10] vfio-iommufd: Create iommufd_access for noiommu devices
On Sat, 13 May 2023 06:21:27 -0700
Yi Liu wrote:
> This binds noiommu device to iommufd and creates iommufd_access for this
> bond. This is useful for adding an iommufd-based device ownership check
> for VFIO_DEVICE_PCI_HOT_RESET since this model requires all the other
> affected devices bound to the same iommufd as the device to be reset.
> For noiommu devices, there is no backend iommu, so create iommufd_access
> instead of iommufd_device.
>
> Suggested-by: Jason Gunthorpe
> Signed-off-by: Yi Liu
> ---
> drivers/vfio/iommufd.c | 43 --
> include/linux/vfio.h | 1 +
> 2 files changed, 42 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/vfio/iommufd.c b/drivers/vfio/iommufd.c
> index 88b00c501015..c1379e826052 100644
> --- a/drivers/vfio/iommufd.c
> +++ b/drivers/vfio/iommufd.c
> @@ -10,6 +10,42 @@
> MODULE_IMPORT_NS(IOMMUFD);
> MODULE_IMPORT_NS(IOMMUFD_VFIO);
>
> +static void vfio_noiommu_access_unmap(void *data, unsigned long iova,
> + unsigned long length)
> +{
Should this WARN_ON if called?
> +}
> +
> +static const struct iommufd_access_ops vfio_user_noiommu_ops = {
> + .needs_pin_pages = 1,
But it doesn't.
> + .unmap = vfio_noiommu_access_unmap,
> +};
> +
> +static int vfio_iommufd_noiommu_bind(struct vfio_device *vdev,
> + struct iommufd_ctx *ictx,
> + u32 *out_device_id)
> +{
> + struct iommufd_access *user;
> +
> + lockdep_assert_held(&vdev->dev_set->lock);
> +
> + user = iommufd_access_create(ictx, &vfio_user_noiommu_ops,
> + vdev, out_device_id);
> + if (IS_ERR(user))
> + return PTR_ERR(user);
> + vdev->noiommu_access = user;
> + return 0;
> +}
> +
> +static void vfio_iommufd_noiommu_unbind(struct vfio_device *vdev)
> +{
> + lockdep_assert_held(&vdev->dev_set->lock);
> +
> + if (vdev->noiommu_access) {
> + iommufd_access_destroy(vdev->noiommu_access);
> + vdev->noiommu_access = NULL;
> + }
> +}
> +
> int vfio_iommufd_bind(struct vfio_device *vdev, struct iommufd_ctx *ictx)
> {
> u32 ioas_id;
> @@ -29,7 +65,8 @@ int vfio_iommufd_bind(struct vfio_device *vdev, struct
> iommufd_ctx *ictx)
>*/
> if (!iommufd_vfio_compat_ioas_get_id(ictx, &ioas_id))
> return -EPERM;
> - return 0;
> +
> + return vfio_iommufd_noiommu_bind(vdev, ictx, &device_id);
> }
>
> ret = vdev->ops->bind_iommufd(vdev, ictx, &device_id);
> @@ -59,8 +96,10 @@ void vfio_iommufd_unbind(struct vfio_device *vdev)
> {
> lockdep_assert_held(&vdev->dev_set->lock);
>
> - if (vfio_device_is_noiommu(vdev))
> + if (vfio_device_is_noiommu(vdev)) {
> + vfio_iommufd_noiommu_unbind(vdev);
> return;
> + }
>
> if (vdev->ops->unbind_iommufd)
> vdev->ops->unbind_iommufd(vdev);
> diff --git a/include/linux/vfio.h b/include/linux/vfio.h
> index 2c137ea94a3e..16fd04490550 100644
> --- a/include/linux/vfio.h
> +++ b/include/linux/vfio.h
> @@ -57,6 +57,7 @@ struct vfio_device {
> struct list_head group_next;
> struct list_head iommu_entry;
> struct iommufd_access *iommufd_access;
> + struct iommufd_access *noiommu_access;
It's not clear to me why we need a separate iommufd_access for noiommu.
Can't we add a vfio_device_is_noiommu() check to the
vfio_{un}pin_pages() and vfio_dma_rw() interfaces and reuse the
existing pointer for both emulated and noiommu cases? Maybe even the
iommufd_access* functions should test needs_pin_pages and generate an
error/warning if an access that was registered without reporting that
it needs page pinning makes use of such an interface. Thanks,
Alex
> void (*put_kvm)(struct kvm *kvm);
> #if IS_ENABLED(CONFIG_IOMMUFD)
> struct iommufd_device *iommufd_device;
Re: [Intel-gfx] [PULL] drm-misc-next
Ping! This appears to be unmerged. Let me know if there's anything wrong with the PR. Am 11.05.23 um 09:28 schrieb Maxime Ripard: Hi, Here's the first drm-misc-next PR for 6.5 Please note that I'll be off for about a month starting next week, and Thomas has kindly agreed to fill in. Thanks! Maxime drm-misc-next-2023-05-11: drm-misc-next for 6.5: UAPI Changes: Cross-subsystem Changes: - arch: Consolidate Core Changes: - aperture: Ignore firmware framebuffers with non-primary devices - fbdev: Use fbdev's I/O helpers - sysfs: Expose DRM connector ID - tests: More tests for drm_rect Driver Changes: - armada: Implement fbdev emulation as a client - bridge: - fsl-ldb: Support i.MX6SX - lt9211: Remove blanking packets - lt9611: Remove blanking packets - tc358768: Implement input bus formats reporting, fix various timings and clocks settings - ti-sn65dsi86: Implement wait_hpd_asserted - nouveau: Improve NULL pointer checks before dereference - panel: - nt36523: Support Lenovo J606F - st7703: Support Anbernic RG353V-V2 - new panels: InnoLux G070ACE-L01 - sun4i: Fix MIPI-DSI dotclock - vc4: RGB Range toggle property, BT601 and BT2020 support for HDMI - vkms: Convert to drmm helpers, Add reflection and rotation support The following changes since commit ac9a78681b921877518763ba0e89202254349d1b: Linux 6.4-rc1 (2023-05-07 13:34:35 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2023-05-11 for you to fetch changes up to 4795c78768bcbd58d4ffab650674d314dc6dd772: drm: sun4i: calculate proper DCLK rate for DSI (2023-05-10 16:03:19 +0200) drm-misc-next for 6.5: UAPI Changes: Cross-subsystem Changes: - arch: Consolidate Core Changes: - aperture: Ignore firmware framebuffers with non-primary devices - fbdev: Use fbdev's I/O helpers - sysfs: Expose DRM connector ID - tests: More tests for drm_rect Driver Changes: - armada: Implement fbdev emulation as a client - bridge: - fsl-ldb: Support i.MX6SX - lt9211: Remove blanking packets - lt9611: Remove blanking packets - tc358768: Implement input bus formats reporting, fix various timings and clocks settings - ti-sn65dsi86: Implement wait_hpd_asserted - nouveau: Improve NULL pointer checks before dereference - panel: - nt36523: Support Lenovo J606F - st7703: Support Anbernic RG353V-V2 - new panels: InnoLux G070ACE-L01 - sun4i: Fix MIPI-DSI dotclock - vc4: RGB Range toggle property, BT601 and BT2020 support for HDMI - vkms: Convert to drmm helpers, Add reflection and rotation support Alexander Stein (1): drm/bridge: ti-sn65dsi83: Fix enable error path Arthur Grillo (5): drm/tests: Add test cases for drm_rect_intersect() drm/tests: Add test cases for drm_rect_calc_hscale() drm/tests: Add test cases for drm_rect_calc_vscale() drm/tests: Add test cases for drm_rect_rotate() drm/test: Add test cases for drm_rect_rotate_inv() Brandon Pollack (1): Documentation: vkms: clarify devres managed reference cleanup Brian Norris (2): drm/atomic: Allow vblank-enabled + self-refresh "disable" drm/rockchip: vop: Leave vblank enabled in self-refresh Chris Morgan (3): dt-bindings: panel: Add Anbernic RG353V-V2 panel compatible drm/panel: st7703: Rename CMD_UNKNOWN_C6 to CMD_SETECO drm/panel: st7703: Add Anbernic RG353V-V2 Panel Support Christian König (3): drm/scheduler: properly forward fence errors drm/scheduler: add drm_sched_entity_error and use rcu for last_scheduled drm/scheduler: mark jobs without fence as canceled Dan Carpenter (2): drm/imx/lcdc: fix a NULL vs IS_ERR() bug in probe drm/udl: delete dead code Daniel Vetter (9): MAINTAINERS: add drm_bridge for drm bridge maintainers drm/gma500: Use drm_aperture_remove_conflicting_pci_framebuffers video/aperture: use generic code to figure out the vga default device drm/aperture: Remove primary argument video/aperture: Only kick vgacon when the pdev is decoding vga video/aperture: Move vga handling to pci function video/aperture: Drop primary argument video/aperture: Only remove sysfb on the default vga pci device fbdev: Simplify fb_is_primary_device for x86 Danilo Krummrich (1): drm/scheduler: set entity to NULL in drm_sched_entity_pop_job() Dave Stevenson (7): drm/vc4: hdmi: Add Broadcast RGB property to allow override of RGB range drm/vc4: hdmi: Rename full range helper drm/vc4: hdmi: Swap CSC matrix channels for YUV444 drm/vc4: hdmi: Rework the CSC matrices organization drm/vc4: hdmi: Add a function to retrieve the CSC matrix drm/vc4: hdmi: Add BT.601 Support
Re: [Intel-gfx] [PATCH v5 1/7] drm/i915/pmu: Change bitmask of enabled events to u32
On Wed, 17 May 2023 01:26:15 -0700, Tvrtko Ursulin wrote:
>
>
> On 17/05/2023 07:55, Umesh Nerlige Ramappa wrote:
> > On Tue, May 16, 2023 at 05:25:50PM -0700, Dixit, Ashutosh wrote:
> >> On Tue, 16 May 2023 16:35:28 -0700, Umesh Nerlige Ramappa wrote:
> >>>
> >>
> >> Hi Umesh/Tvrtko,
> >>
> >> Mostly repeating comments/questions made on the previous patch below.
>
> First of all thanks for improving this, my v1 obviously wasn't good enough.
>
> >>
> >>> From: Tvrtko Ursulin
> >>>
> >>> Having it as u64 was a confusing (but harmless) mistake.
> >>>
> >>> Also add some asserts to make sure the internal field does not overflow
> >>> in the future.
> >>>
> >>> v2: Fix WARN_ON firing for INTERRUPT event (Umesh)
> >>>
> >>> Signed-off-by: Tvrtko Ursulin
> >>> Signed-off-by: Umesh Nerlige Ramappa
> >>> Cc: Ashutosh Dixit
> >>> ---
> >>> drivers/gpu/drm/i915/i915_pmu.c | 26 ++
> >>> 1 file changed, 18 insertions(+), 8 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_pmu.c
> >>> b/drivers/gpu/drm/i915/i915_pmu.c
> >>> index 7ece883a7d95..96543dce2db1 100644
> >>> --- a/drivers/gpu/drm/i915/i915_pmu.c
> >>> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> >>> @@ -50,7 +50,7 @@ static u8 engine_event_instance(struct perf_event
> >>> *event)
> >>> return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
> >>> }
> >>>
> >>> -static bool is_engine_config(u64 config)
> >>> +static bool is_engine_config(const u64 config)
> >>> {
> >>> return config < __I915_PMU_OTHER(0);
> >>> }
> >>> @@ -88,9 +88,20 @@ static unsigned int config_bit(const u64 config)
> >>> return other_bit(config);
> >>> }
> >>>
> >>> -static u64 config_mask(u64 config)
> >>> +static u32 config_mask(const u64 config)
> >>> {
> >>> - return BIT_ULL(config_bit(config));
> >>> + unsigned int bit = config_bit(config);
> >>
> >> Give that config_bit() can return -1 (I understand it is avoided in
> >> moving
> >> the code to config_mask from config_bit), maybe the code below should
> >> also
> >> have that check?
> >
> > config_mask is only called to check frequency related events in the code,
> > so I don't see it returing -1 here.
>
> Yeah that should be fine since -1 would make the below asserts fire
> anyway. (If it would get called from a different path in the future.)
>
> >>
> >> int bit = config_bit(config);
> >>
> >> if (bit != -1)
> >> {
> >> ...
> >> }
> >>
> >> Though as mentioned below the 'if (__builtin_constant_p())' would have to
> >> go. Maybe the code could even have stayed in config_bit with the check.
> >>
> >>> +
> >>> + if (__builtin_constant_p(config))
> >>> + BUILD_BUG_ON(bit >
> >>> + BITS_PER_TYPE(typeof_member(struct i915_pmu,
> >>> + enable)) - 1);
> >>
> >> Given that config comes from the event (it is event->attr.config), can
> >> this
> >> ever be a builtin constant?
> >
> > Not sure about earlier code where these checks were inside config_bit(),
> > but with changes I made, I don't see this being a builtin
> > constant. However, nothing prevents a caller from just passing a
> > builtin_constant to this in future.
>
> Are you sure? I would have thought it would always be a compile time
> constant now that the check is in config_mask. Aahhh.. with the multi-tile
> changes maybe it can't unroll the loops and calculate the masks at compile
> time. Maybe it is a bit too much and we should drop the
> __builtin_constant_p branch? Probably..
Ah yes, with the code move to config_mask, they really all are compile time
constants (provided compiler can unroll the loops) so at least that is the
justfication for leaving the __builtin_constant_p in. So I'd probably just
leave it as is (though it is a bit too much).
> But I guess it is safe to use GEM_WARN_ON_ONCE instead of WARN_ON_ONCE
> since there are no external callers (nothing coming from event) now. That
> way at least production builds don't have to have the check.
Hmm, there's a GEM_WARN_ON but no GEM_WARN_ON_ONCE. So leave that as is too
I guess.
So I'm ok with the code staying as is. Enough bike-shed on this already.
Thanks.
--
Ashutosh
>
> Regards,
>
> Tvrtko
>
> >
> > Thanks,
> > Umesh
> >
> >>
> >>> + else
> >>> + WARN_ON_ONCE(bit >
> >>> + BITS_PER_TYPE(typeof_member(struct i915_pmu,
> >>> + enable)) - 1);
> >>
> >> There is really an even stricter limit on what the bit can be, which is
> >> the
> >> total number of possible events but anyway this is good enough.
> >>
> >> After addressing the above, this patch is:
> >>
> >> Reviewed-by: Ashutosh Dixit
> >>
> >>> +
> >>> + return BIT(config_bit(config));
> >>> }
> >>>
> >>> static bool is_engine_event(struct perf_event *event)
> >>> @@ -633,11 +644,10 @@ static void i915_pmu_enable(struct perf_event
> >>> *event)
> >>> {
> >>> struct drm_i915_private *i915 =
> >>> container_of(event->pmu, typeof(*i915), pmu.b
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,DO_NOT_MERGE,1/2] drm/i915/mtl: do not enable render power-gating on MTL (rev2)
== Series Details ==
Series: series starting with [CI,DO_NOT_MERGE,1/2] drm/i915/mtl: do not enable
render power-gating on MTL (rev2)
URL : https://patchwork.freedesktop.org/series/117839/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13154_full -> Patchwork_117839v2_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_117839v2_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_117839v2_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_117839v2_full:
### IGT changes ###
Possible regressions
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-apl7/igt@kms_fbcon_...@fbc-suspend.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v2/shard-apl6/igt@kms_fbcon_...@fbc-suspend.html
Known issues
Here are the changes found in Patchwork_117839v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-glk9/igt@gem_exec_fair@basic-p...@vecs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v2/shard-glk1/igt@gem_exec_fair@basic-p...@vecs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v2/shard-apl4/igt@gem_huc_c...@huc-copy.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3886]) +1
similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v2/shard-apl4/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium_color@ctm-0-75:
- shard-apl: NOTRUN -> [SKIP][7] ([fdo#109271]) +36 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v2/shard-apl4/igt@kms_chamelium_co...@ctm-0-75.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][8] -> [FAIL][9] ([i915#2346])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-glk5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v2/shard-glk8/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
- shard-apl: NOTRUN -> [FAIL][10] ([i915#2346])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v2/shard-apl4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
* igt@kms_panel_fitting@legacy:
- shard-apl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4579]) +3
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v2/shard-apl4/igt@kms_panel_fitt...@legacy.html
* igt@kms_psr2_su@frontbuffer-xrgb:
- shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#658])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v2/shard-apl4/igt@kms_psr2...@frontbuffer-xrgb.html
Possible fixes
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- {shard-rkl}:[FAIL][13] ([i915#7742]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-rkl-1/igt@drm_fdinfo@most-busy-check-...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v2/shard-rkl-4/igt@drm_fdinfo@most-busy-check-...@rcs0.html
* igt@gem_barrier_race@remote-request@rcs0:
- {shard-dg1}:[ABORT][15] ([i915#7461] / [i915#8234]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-dg1-14/igt@gem_barrier_race@remote-requ...@rcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v2/shard-dg1-12/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][17] ([i915#2842]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117839v2/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- {shard-rkl}:[FAIL][19] ([i915#2842]) -> [PASS][20] +2 similar
issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-rkl-4/igt@gem
Re: [Intel-gfx] [PATCH] drm/i915/mtl: do not enable render power-gating on MTL
On 5/17/2023 5:25 PM, Vivi, Rodrigo wrote: On Wed, 2023-05-17 at 17:12 +0200, Das, Nirmoy wrote: On 5/17/2023 3:59 PM, Andrzej Hajda wrote: Multiple CI tests fails with forcewake ack timeouts if render power gating is enabled. BSpec 52698 clearly states it should be 0 for MTL. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 908a3d0f2343f4..ebb2373dd73640 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -117,8 +117,9 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) GEN6_RC_CTL_RC6_ENABLE | GEN6_RC_CTL_EI_MODE(1); - /* Wa_16011777198 - Render powergating must remain disabled */ - if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || + /* Wa_16011777198 and BSpec 52698 - Render powergating must be off */ Nice catch! Indeed! What a mess in the workaround database. It is telling us that no_impact on MTL SKUs while we clearly needs that. I tried to reopen that and get that fixed in the hsds. instead of bspec you could add Wa_1401266. not actually. 16011777198 is the right lineage number for 1401266. Besides, 1401266 is for DG2 anyway. Let's keep the way Adrzej put with the BSPec reference besides the lineage. Makes sense, didn't realize 1401266 is much older. Thanks! + if (IS_METEORLAKE(gt->i915) || + IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) pg_enable = GEN9_MEDIA_PG_ENABLE | --- base-commit: 01d3dd92d1b71421f6ee85e1bea829e0a917d979 change-id: 20230517-mtl_disable_render_pg-b9f9f1567f9e ^ unwanted artifacts ? Otherwise this looks good to me. Reviewed-by: Nirmoy Das with the artifacts removed: Reviewed-by: Rodrigo Vivi Best regards,
Re: [Intel-gfx] [PATCH] drm/i915/mtl: do not enable render power-gating on MTL
On 17.05.2023 17:12, Das, Nirmoy wrote: On 5/17/2023 3:59 PM, Andrzej Hajda wrote: Multiple CI tests fails with forcewake ack timeouts if render power gating is enabled. BSpec 52698 clearly states it should be 0 for MTL. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 908a3d0f2343f4..ebb2373dd73640 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -117,8 +117,9 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) GEN6_RC_CTL_RC6_ENABLE | GEN6_RC_CTL_EI_MODE(1); - /* Wa_16011777198 - Render powergating must remain disabled */ - if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || + /* Wa_16011777198 and BSpec 52698 - Render powergating must be off */ Nice catch! instead of bspec you could add Wa_1401266. I put bspec because it is quite clear on the subject in contrast to WA :) but I can change it if this way is preferred. + if (IS_METEORLAKE(gt->i915) || + IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) pg_enable = GEN9_MEDIA_PG_ENABLE | --- base-commit: 01d3dd92d1b71421f6ee85e1bea829e0a917d979 change-id: 20230517-mtl_disable_render_pg-b9f9f1567f9e ^ unwanted artifacts ? Otherwise this looks good to me. It is added by b4 tool, git deals with it correctly. Reviewed-by: Nirmoy Das Thx Regards Andrzej Best regards,
Re: [Intel-gfx] [PATCH] drm/i915/mtl: do not enable render power-gating on MTL
On Wed, 2023-05-17 at 17:12 +0200, Das, Nirmoy wrote: > > On 5/17/2023 3:59 PM, Andrzej Hajda wrote: > > Multiple CI tests fails with forcewake ack timeouts > > if render power gating is enabled. > > BSpec 52698 clearly states it should be 0 for MTL. > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 > > Signed-off-by: Andrzej Hajda > > --- > > drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +++-- > > 1 file changed, 3 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c > > b/drivers/gpu/drm/i915/gt/intel_rc6.c > > index 908a3d0f2343f4..ebb2373dd73640 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c > > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c > > @@ -117,8 +117,9 @@ static void gen11_rc6_enable(struct intel_rc6 > > *rc6) > > GEN6_RC_CTL_RC6_ENABLE | > > GEN6_RC_CTL_EI_MODE(1); > > > > - /* Wa_16011777198 - Render powergating must remain disabled > > */ > > - if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) > > || > > + /* Wa_16011777198 and BSpec 52698 - Render powergating must > > be off */ > > Nice catch! Indeed! What a mess in the workaround database. It is telling us that no_impact on MTL SKUs while we clearly needs that. I tried to reopen that and get that fixed in the hsds. > instead of bspec you could add Wa_1401266. not actually. 16011777198 is the right lineage number for 1401266. Besides, 1401266 is for DG2 anyway. Let's keep the way Adrzej put with the BSPec reference besides the lineage. > > > > + if (IS_METEORLAKE(gt->i915) || > > + IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) > > || > > IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) > > pg_enable = > > GEN9_MEDIA_PG_ENABLE | > > > > --- > > base-commit: 01d3dd92d1b71421f6ee85e1bea829e0a917d979 > > change-id: 20230517-mtl_disable_render_pg-b9f9f1567f9e > > ^ unwanted artifacts ? Otherwise this looks good to me. > > Reviewed-by: Nirmoy Das with the artifacts removed: Reviewed-by: Rodrigo Vivi > > > > > Best regards,
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/color: register & get config abstractions
== Series Details == Series: drm/i915/color: register & get config abstractions URL : https://patchwork.freedesktop.org/series/117875/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13159 -> Patchwork_117875v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_117875v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_117875v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117875v1/index.html Participating hosts (37 -> 37) -- Additional (1): fi-kbl-soraka Missing(1): fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_117875v1: ### IGT changes ### Possible regressions * igt@dmabuf@all-tests@dma_fence: - bat-dg1-7: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13159/bat-dg1-7/igt@dmabuf@all-tests@dma_fence.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117875v1/bat-dg1-7/igt@dmabuf@all-tests@dma_fence.html * igt@dmabuf@all-tests@sanitycheck: - bat-dg1-7: [PASS][3] -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13159/bat-dg1-7/igt@dmabuf@all-te...@sanitycheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117875v1/bat-dg1-7/igt@dmabuf@all-te...@sanitycheck.html Known issues Here are the changes found in Patchwork_117875v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s0@smem: - bat-jsl-1: [PASS][5] -> [ABORT][6] ([i915#5122]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13159/bat-jsl-1/igt@gem_exec_suspend@basic...@smem.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117875v1/bat-jsl-1/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117875v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117875v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#5334] / [i915#7872]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117875v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][10] ([i915#1886] / [i915#7913]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117875v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@mman: - bat-rpls-2: [PASS][11] -> [TIMEOUT][12] ([i915#6794] / [i915#7392]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13159/bat-rpls-2/igt@i915_selftest@l...@mman.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117875v1/bat-rpls-2/igt@i915_selftest@l...@mman.html * igt@i915_selftest@live@reset: - bat-rpls-1: [PASS][13] -> [ABORT][14] ([i915#4983] / [i915#7461] / [i915#8347] / [i915#8384]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13159/bat-rpls-1/igt@i915_selftest@l...@reset.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117875v1/bat-rpls-1/igt@i915_selftest@l...@reset.html * igt@i915_suspend@basic-s3-without-i915: - bat-jsl-1: [PASS][15] -> [FAIL][16] ([fdo#103375]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13159/bat-jsl-1/igt@i915_susp...@basic-s3-without-i915.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117875v1/bat-jsl-1/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_chamelium_frames@hdmi-crc-fast: - fi-kbl-soraka: NOTRUN -> [SKIP][17] ([fdo#109271]) +14 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117875v1/fi-kbl-soraka/igt@kms_chamelium_fra...@hdmi-crc-fast.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#7828]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117875v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@read-crc: - bat-adlp-9: NOTRUN -> [SKIP][19] ([i915#3546]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117875v1/bat-adlp-9/igt@kms_pipe_crc_ba...@read-crc.html * igt@kms_setmode@basic-clone-single-crtc: - fi-kbl-soraka: NOTRUN -> [SKIP][
Re: [Intel-gfx] [PATCH] drm/i915/mtl: do not enable render power-gating on MTL
On 5/17/2023 3:59 PM, Andrzej Hajda wrote: Multiple CI tests fails with forcewake ack timeouts if render power gating is enabled. BSpec 52698 clearly states it should be 0 for MTL. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 908a3d0f2343f4..ebb2373dd73640 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -117,8 +117,9 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) GEN6_RC_CTL_RC6_ENABLE | GEN6_RC_CTL_EI_MODE(1); - /* Wa_16011777198 - Render powergating must remain disabled */ - if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || + /* Wa_16011777198 and BSpec 52698 - Render powergating must be off */ Nice catch! instead of bspec you could add Wa_1401266. + if (IS_METEORLAKE(gt->i915) || + IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) pg_enable = GEN9_MEDIA_PG_ENABLE | --- base-commit: 01d3dd92d1b71421f6ee85e1bea829e0a917d979 change-id: 20230517-mtl_disable_render_pg-b9f9f1567f9e ^ unwanted artifacts ? Otherwise this looks good to me. Reviewed-by: Nirmoy Das Best regards,
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/color: register & get config abstractions
== Series Details == Series: drm/i915/color: register & get config abstractions URL : https://patchwork.freedesktop.org/series/117875/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/color: register & get config abstractions
== Series Details == Series: drm/i915/color: register & get config abstractions URL : https://patchwork.freedesktop.org/series/117875/ State : warning == Summary == Error: dim checkpatch failed 88392f9a0c53 drm/i915/regs: split out intel_color_regs.h Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #35: new file mode 100644 -:75: WARNING:LONG_LINE_COMMENT: line length of 105 exceeds 100 columns #75: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:36: +#define PREC_PIPEGCMAX(pipe, i)_MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1.16 */ -:87: WARNING:LONG_LINE_COMMENT: line length of 101 exceeds 100 columns #87: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:48: +#define GAMMA_MODE_MODE_SPLIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* ivb-bdw */ -:88: WARNING:LONG_LINE_COMMENT: line length of 101 exceeds 100 columns #88: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:49: +#define GAMMA_MODE_MODE_12BIT_MULTI_SEG REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* icl-tgl */ -:126: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #126: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:87: +#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) -:128: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #128: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:89: +#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) -:130: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #130: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:91: +#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) -:133: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #133: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:94: +#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) -:134: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #134: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:95: +#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) -:135: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #135: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:96: +#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) -:136: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #136: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:97: +#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) -:137: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #137: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:98: +#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) -:138: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #138: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:99: +#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) -:228: WARNING:LONG_LINE: line length of 120 exceeds 100 columns #228: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:189: +#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) /* u1.16 */ -:229: WARNING:LONG_LINE: line length of 128 exceeds 100 columns #229: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:190: +#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) /* u3.16 */ -:230: WARNING:LONG_LINE: line length of 136 exceeds 100 columns #230: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:191: +#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) /* glk+, u3.16 */ -:242: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #242: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:203: +#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) -:250: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #250: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:211: +#define PAL_PREC_MULTI_SEG_INDEX_VALUE(x) REG_FIELD_PREP(PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK, (x)) -:295: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #295: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:256: +#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) -:296: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #296: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:
Re: [Intel-gfx] [PATCH v3 03/28] drm/i915/gvt: Verify hugepages are contiguous in physical address space
On Tue, May 16, 2023, Yan Zhao wrote: > hi Sean > > Do you think it's necessary to double check that struct page pointers > are also contiguous? No, the virtual address space should be irrelevant. The only way it would be problematic is if something in dma_map_page() expected to be able to access the entire chunk of memory by getting the virtual address of only the first page, but I can't imagine that code is reading or writing memory, let alone doing so across a huge range of memory. > And do you like to also include a fix as below, which is to remove the > warning in vfio_device_container_unpin_pages() when npage is 0? > > @ -169,7 +173,8 @@ static int gvt_pin_guest_page(struct intel_vgpu *vgpu, > unsigned long gfn, > *page = base_page; > return 0; > err: > - gvt_unpin_guest_page(vgpu, gfn, npage * PAGE_SIZE); > + if (npage) > + gvt_unpin_guest_page(vgpu, gfn, npage * PAGE_SIZE); > return ret; > } Sure. Want to give your SoB? I'll write a changelog. Thanks again!
[Intel-gfx] [PATCH] drm/i915/mtl: do not enable render power-gating on MTL
Multiple CI tests fails with forcewake ack timeouts if render power gating is enabled. BSpec 52698 clearly states it should be 0 for MTL. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4983 Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 908a3d0f2343f4..ebb2373dd73640 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -117,8 +117,9 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) GEN6_RC_CTL_RC6_ENABLE | GEN6_RC_CTL_EI_MODE(1); - /* Wa_16011777198 - Render powergating must remain disabled */ - if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || + /* Wa_16011777198 and BSpec 52698 - Render powergating must be off */ + if (IS_METEORLAKE(gt->i915) || + IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) pg_enable = GEN9_MEDIA_PG_ENABLE | --- base-commit: 01d3dd92d1b71421f6ee85e1bea829e0a917d979 change-id: 20230517-mtl_disable_render_pg-b9f9f1567f9e Best regards, -- Andrzej Hajda
[Intel-gfx] [PATCH V2] drm/i915/gem: Use large rings for compute contexts
From: Chris Wilson Allow compute contexts to submit the maximal amount of work without blocking userspace. The original size for user LRC ring's (SZ_16K) was chosen to minimise memory consumption, without being so small as to frequently stall in the middle of workloads. With the main consumers being GL / media pipelines of 2 or 3 batches per frame, we want to support ~10 requests in flight to allow for the application to control throttling without stalling within a frame. v2: - cover with else part Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 5402a7bbcb1d..9a9ff84c90d7 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -964,7 +964,11 @@ static int intel_context_set_gem(struct intel_context *ce, RCU_INIT_POINTER(ce->gem_context, ctx); GEM_BUG_ON(intel_context_is_pinned(ce)); - ce->ring_size = SZ_16K; + + if (ce->engine->class == COMPUTE_CLASS) + ce->ring_size = SZ_512K; + else + ce->ring_size = SZ_16K; i915_vm_put(ce->vm); ce->vm = i915_gem_context_get_eb_vm(ctx); -- 2.25.1
[Intel-gfx] [PATCH V2] drm/i915/gt: Add workaround 14016712196
Wa_14016712196 implementation for mtl
Bspec: 72197
V2:
- Fix kernel test robot warnings
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202305121525.3ewdgoby-...@intel.com/
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 41
1 file changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e1c76e5bfa82..737eb515544b 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -177,14 +177,38 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32
*cs, const i915_reg_t inv
return cs;
}
+static int mtl_dummy_pipe_control(struct i915_request *rq, u32 *cs)
+{
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+ cs = gen12_emit_pipe_control(cs,
+0,
+PIPE_CONTROL_DEPTH_CACHE_FLUSH,
+LRC_PPHWSP_SCRATCH_ADDR);
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
{
struct intel_engine_cs *engine = rq->engine;
+ int err;
if (mode & EMIT_FLUSH) {
u32 flags = 0;
u32 *cs;
+ /* Wa_14016712196 */
+ if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(engine->i915, P, STEP_A0, STEP_B0)) {
+ /* dummy PIPE_CONTROL + depth flush */
+ cs = intel_ring_begin(rq, 6);
+ err = mtl_dummy_pipe_control(rq, cs);
+ if (err)
+ return err;
+ }
+
flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
flags |= PIPE_CONTROL_FLUSH_L3;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
@@ -218,6 +242,16 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
u32 flags = 0;
u32 *cs, count;
+ /* Wa_14016712196 */
+ if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(engine->i915, P, STEP_A0, STEP_B0)) {
+ /* dummy PIPE_CONTROL + depth flush */
+ cs = intel_ring_begin(rq, 6);
+ err = mtl_dummy_pipe_control(rq, cs);
+ if (err)
+ return err;
+ }
+
flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
flags |= PIPE_CONTROL_TLB_INVALIDATE;
flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
@@ -733,6 +767,13 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request
*rq, u32 *cs)
PIPE_CONTROL_DC_FLUSH_ENABLE |
PIPE_CONTROL_FLUSH_ENABLE);
+ /* Wa_14016712196 */
+ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ /* dummy PIPE_CONTROL + depth flush */
+ cs = gen12_emit_pipe_control(cs, 0,
+PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
+
if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12,
50))
/* Wa_1409600907 */
flags |= PIPE_CONTROL_DEPTH_STALL;
--
2.25.1
Re: [Intel-gfx] [PATCH v3 7/8] drm/i915/mtl: Add support for PM DEMAND
On Thu, 27 Apr 2023, Vinod Govindapillai wrote:
> From: Mika Kahola
>
> Display14 introduces a new way to instruct the PUnit with
> power and bandwidth requirements of DE. Add the functionality
> to program the registers and handle waits using interrupts.
> The current wait time for timeouts is programmed for 10 msecs to
> factor in the worst case scenarios. Changes made to use REG_BIT
> for a register that we touched(GEN8_DE_MISC_IER _MMIO).
>
> Wa_14016740474 is added which applies to Xe_LPD+ display
>
> v2: checkpatch warning fixes, simplify program pmdemand part
>
> v3: update to dbufs and pipes values to pmdemand register(stan)
> Removed the macro usage in update_pmdemand_values()
>
> Bspec: 66451, 64636, 64602, 64603
> Cc: Matt Atwood
> Cc: Matt Roper
> Cc: Lucas De Marchi
> Cc: Gustavo Sousa
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Gustavo Sousa
> Signed-off-by: Mika Kahola
> Signed-off-by: Vinod Govindapillai
> ---
> drivers/gpu/drm/i915/Makefile | 3 +-
> drivers/gpu/drm/i915/display/intel_display.c | 7 +
> .../gpu/drm/i915/display/intel_display_core.h | 6 +
> .../drm/i915/display/intel_display_driver.c | 7 +
> .../drm/i915/display/intel_display_power.c| 8 +
> drivers/gpu/drm/i915/display/intel_pmdemand.c | 455 ++
> drivers/gpu/drm/i915/display/intel_pmdemand.h | 24 +
> drivers/gpu/drm/i915/i915_irq.c | 21 +-
> drivers/gpu/drm/i915/i915_reg.h | 36 +-
> 9 files changed, 562 insertions(+), 5 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 9af76e376ca9..eb899fa86e51 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -281,7 +281,8 @@ i915-y += \
> display/i9xx_wm.o \
> display/skl_scaler.o \
> display/skl_universal_plane.o \
> - display/skl_watermark.o
> + display/skl_watermark.o \
> + display/intel_pmdemand.o
> i915-$(CONFIG_ACPI) += \
> display/intel_acpi.o \
> display/intel_opregion.o
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index bf391a6cd8d6..f98e235fadc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -99,6 +99,7 @@
> #include "intel_pcode.h"
> #include "intel_pipe_crc.h"
> #include "intel_plane_initial.h"
> +#include "intel_pmdemand.h"
> #include "intel_pps.h"
> #include "intel_psr.h"
> #include "intel_sdvo.h"
> @@ -6306,6 +6307,10 @@ int intel_atomic_check(struct drm_device *dev,
> return ret;
> }
>
> + ret = intel_pmdemand_atomic_check(state);
> + if (ret)
> + goto fail;
> +
> ret = intel_atomic_check_crtcs(state);
> if (ret)
> goto fail;
> @@ -6960,6 +6965,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> }
>
> intel_sagv_pre_plane_update(state);
> + intel_pmdemand_pre_plane_update(state);
>
> /* Complete the events for pipes that have now been disabled */
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> @@ -7070,6 +7076,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> intel_verify_planes(state);
>
> intel_sagv_post_plane_update(state);
> + intel_pmdemand_post_plane_update(state);
>
> drm_atomic_helper_commit_hw_done(&state->base);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 9f66d734edf6..9471a052aa57 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -345,6 +345,12 @@ struct intel_display {
> struct intel_global_obj obj;
> } dbuf;
>
> + struct {
> + wait_queue_head_t waitqueue;
> + struct mutex lock;
> + struct intel_global_obj obj;
> + } pmdemand;
> +
See the comment a little higher up:
/* Grouping using anonymous structs. Keep sorted. */
> struct {
> /*
>* dkl.phy_lock protects against concurrent access of the
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 60ce10fc7205..79853d8c3240 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -47,6 +47,7 @@
> #include "intel_opregion.h"
> #include "intel_overlay.h"
> #include "intel_plane_initial.h"
> +#include "intel_pmdemand.h"
> #include "intel_pps.h"
> #include "intel_quirks.h"
> #include "intel_vga.h"
> @@ -211,6 +212
Re: [Intel-gfx] [PATCH] drm/i915: tweak language in fastset pipe config compare logging
On Tue, 16 May 2023, "Kandpal, Suraj" wrote:
>>
>> The "fastset mismatch" debug logging has been slightly confusing, leading
>> people to believe some error happened. Change it to the more informative
>> "fastset requirement not met", and add a final message about this leading to
>> full modeset.
>>
>
> LGTM.
>
> Reviewed-by: Suraj Kandpal
Thanks, pushed to din.
BR,
Jani.
>
>> Cc: Ville Syrjälä
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 15 ++-
>> 1 file changed, 10 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index 4b70b389e0cb..8afbaf8d1196 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -4857,7 +4857,7 @@ pipe_config_infoframe_mismatch(struct
>> drm_i915_private *dev_priv,
>> return;
>>
>> drm_dbg_kms(&dev_priv->drm,
>> - "fastset mismatch in %s infoframe\n", name);
>> + "fastset requirement not met in %s infoframe\n",
>> name);
>> drm_dbg_kms(&dev_priv->drm, "expected:\n");
>> hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
>> drm_dbg_kms(&dev_priv->drm, "found:\n"); @@ -4882,7
>> +4882,7 @@ pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private
>> *dev_priv,
>> return;
>>
>> drm_dbg_kms(&dev_priv->drm,
>> - "fastset mismatch in %s dp sdp\n", name);
>> + "fastset requirement not met in %s dp sdp\n",
>> name);
>> drm_dbg_kms(&dev_priv->drm, "expected:\n");
>> drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
>> drm_dbg_kms(&dev_priv->drm, "found:\n"); @@ -4923,7
>> +4923,7 @@ pipe_config_buffer_mismatch(struct drm_i915_private
>> *dev_priv,
>> len = memcmp_diff_len(a, b, len);
>>
>> drm_dbg_kms(&dev_priv->drm,
>> - "fastset mismatch in %s buffer\n", name);
>> + "fastset requirement not met in %s buffer\n",
>> name);
>> print_hex_dump(KERN_DEBUG, "expected: ",
>> DUMP_PREFIX_NONE,
>> 16, 0, a, len, false);
>> print_hex_dump(KERN_DEBUG, "found: ",
>> DUMP_PREFIX_NONE, @@ -4954,7 +4954,7 @@ pipe_config_mismatch(bool
>> fastset, const struct intel_crtc *crtc,
>>
>> if (fastset)
>> drm_dbg_kms(&i915->drm,
>> - "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
>> + "[CRTC:%d:%s] fastset requirement not met in %s
>> %pV\n",
>> crtc->base.base.id, crtc->base.name, name, &vaf);
>> else
>> drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s
>> %pV\n", @@ -5542,8 +5542,13 @@ static int intel_modeset_checks(struct
>> intel_atomic_state *state) static void intel_crtc_check_fastset(const struct
>> intel_crtc_state *old_crtc_state,
>>struct intel_crtc_state *new_crtc_state)
>> {
>> - if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
>> + struct drm_i915_private *i915 =
>> +to_i915(old_crtc_state->uapi.crtc->dev);
>> +
>> + if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
>> {
>> + drm_dbg_kms(&i915->drm, "fastset requirement not met,
>> forcing full
>> +modeset\n");
>> +
>> return;
>> + }
>>
>> new_crtc_state->uapi.mode_changed = false;
>> if (!intel_crtc_needs_modeset(new_crtc_state))
>> --
>> 2.39.2
>
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH 6/6] drm/i915/color: move pre-SKL gamma and CSC enable read to intel_color
Abstract the register access better. The DSPCNTR read could be moved to
either i9xx_plane.c or intel_color.c. The latter feels better, even if
the register is written in the former.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_color.c | 25
drivers/gpu/drm/i915/display/intel_display.c | 23 --
2 files changed, 25 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 882536b372e0..6c9086dfce8f 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -916,12 +916,31 @@ static u32 ilk_read_csc_mode(struct intel_crtc *crtc)
return intel_de_read(i915, PIPE_CSC_MODE(crtc->pipe));
}
+static void i9xx_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
+ u32 tmp;
+
+ tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
+
+ if (tmp & DISP_PIPE_GAMMA_ENABLE)
+ crtc_state->gamma_enable = true;
+
+ if (!HAS_GMCH(dev_priv) && tmp & DISP_PIPE_CSC_ENABLE)
+ crtc_state->csc_enable = true;
+}
+
static void hsw_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);
crtc_state->csc_mode = ilk_read_csc_mode(crtc);
+
+ i9xx_get_config(crtc_state);
}
static void skl_get_config(struct intel_crtc_state *crtc_state)
@@ -3057,6 +3076,8 @@ static void chv_get_config(struct intel_crtc_state
*crtc_state)
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
crtc_state->cgm_mode = intel_de_read(i915, CGM_PIPE_MODE(crtc->pipe));
+
+ i9xx_get_config(crtc_state);
}
static void chv_read_luts(struct intel_crtc_state *crtc_state)
@@ -3127,6 +3148,8 @@ static void ilk_get_config(struct intel_crtc_state
*crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
crtc_state->csc_mode = ilk_read_csc_mode(crtc);
+
+ i9xx_get_config(crtc_state);
}
static void ilk_read_luts(struct intel_crtc_state *crtc_state)
@@ -3436,6 +3459,7 @@ static const struct intel_color_funcs i965_color_funcs = {
.load_luts = i965_load_luts,
.read_luts = i965_read_luts,
.lut_equal = i965_lut_equal,
+ .get_config = i9xx_get_config,
};
static const struct intel_color_funcs i9xx_color_funcs = {
@@ -3444,6 +3468,7 @@ static const struct intel_color_funcs i9xx_color_funcs = {
.load_luts = i9xx_load_luts,
.read_luts = i9xx_read_luts,
.lut_equal = i9xx_lut_equal,
+ .get_config = i9xx_get_config,
};
static const struct intel_color_funcs tgl_color_funcs = {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index b17279ddc409..568cf74fb07a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2865,24 +2865,6 @@ bdw_get_pipe_misc_output_format(struct intel_crtc *crtc)
}
}
-static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct intel_plane *plane = to_intel_plane(crtc->base.primary);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
- u32 tmp;
-
- tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
-
- if (tmp & DISP_PIPE_GAMMA_ENABLE)
- crtc_state->gamma_enable = true;
-
- if (!HAS_GMCH(dev_priv) &&
- tmp & DISP_PIPE_CSC_ENABLE)
- crtc_state->csc_enable = true;
-}
-
static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
@@ -2934,7 +2916,6 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
pipe_config->framestart_delay =
REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
- i9xx_get_pipe_color_config(pipe_config);
intel_color_get_config(pipe_config);
if (DISPLAY_VER(dev_priv) < 4)
@@ -3328,7 +3309,6 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
pipe_config->msa_timing_delay =
REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
- i9xx_get_pipe_color_config(pipe_config);
intel_color_get_config(pipe_config);
pipe_config->pixel_multiplier = 1;
@@ -3719,9 +3699,6 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
pipe_config->sink_format = pipe_config->output_format;
- if (DISPLAY_VER(dev_priv) < 9)
-
[Intel-gfx] [PATCH 5/6] drm/i915/color: move SKL+ gamma and CSC enable read to intel_color
Abstract the platform specific register access better.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_color.c | 26 +---
drivers/gpu/drm/i915/display/intel_display.c | 12 +
2 files changed, 23 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index c99941472cb2..882536b372e0 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -924,6 +924,24 @@ static void hsw_get_config(struct intel_crtc_state
*crtc_state)
crtc_state->csc_mode = ilk_read_csc_mode(crtc);
}
+static void skl_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ u32 tmp;
+
+ crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);
+ crtc_state->csc_mode = ilk_read_csc_mode(crtc);
+
+ tmp = intel_de_read(i915, SKL_BOTTOM_COLOR(crtc->pipe));
+
+ if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
+ crtc_state->gamma_enable = true;
+
+ if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
+ crtc_state->csc_enable = true;
+}
+
static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -3436,7 +3454,7 @@ static const struct intel_color_funcs tgl_color_funcs = {
.read_luts = icl_read_luts,
.lut_equal = icl_lut_equal,
.read_csc = icl_read_csc,
- .get_config = hsw_get_config,
+ .get_config = skl_get_config,
};
static const struct intel_color_funcs icl_color_funcs = {
@@ -3448,7 +3466,7 @@ static const struct intel_color_funcs icl_color_funcs = {
.read_luts = icl_read_luts,
.lut_equal = icl_lut_equal,
.read_csc = icl_read_csc,
- .get_config = hsw_get_config,
+ .get_config = skl_get_config,
};
static const struct intel_color_funcs glk_color_funcs = {
@@ -3459,7 +3477,7 @@ static const struct intel_color_funcs glk_color_funcs = {
.read_luts = glk_read_luts,
.lut_equal = glk_lut_equal,
.read_csc = skl_read_csc,
- .get_config = hsw_get_config,
+ .get_config = skl_get_config,
};
static const struct intel_color_funcs skl_color_funcs = {
@@ -3470,7 +3488,7 @@ static const struct intel_color_funcs skl_color_funcs = {
.read_luts = bdw_read_luts,
.lut_equal = ivb_lut_equal,
.read_csc = skl_read_csc,
- .get_config = hsw_get_config,
+ .get_config = skl_get_config,
};
static const struct intel_color_funcs bdw_color_funcs = {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a24466efe0ae..b17279ddc409 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -61,7 +61,6 @@
#include "intel_cdclk.h"
#include "intel_clock_gating.h"
#include "intel_color.h"
-#include "intel_color_regs.h"
#include "intel_crt.h"
#include "intel_crtc.h"
#include "intel_crtc_state_dump.h"
@@ -3720,17 +3719,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
pipe_config->sink_format = pipe_config->output_format;
- if (DISPLAY_VER(dev_priv) >= 9) {
- tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
-
- if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
- pipe_config->gamma_enable = true;
-
- if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
- pipe_config->csc_enable = true;
- } else {
+ if (DISPLAY_VER(dev_priv) < 9)
i9xx_get_pipe_color_config(pipe_config);
- }
intel_color_get_config(pipe_config);
--
2.39.2
[Intel-gfx] [PATCH 4/6] drm/i915: move ILK+ CSC mode read to intel_color
Abstract the platform specific register access better.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_color.c | 17 +
drivers/gpu/drm/i915/display/intel_display.c | 6 --
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 25730697fa8a..c99941472cb2 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -909,11 +909,19 @@ static u32 hsw_read_gamma_mode(struct intel_crtc *crtc)
return intel_de_read(i915, GAMMA_MODE(crtc->pipe));
}
+static u32 ilk_read_csc_mode(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+ return intel_de_read(i915, PIPE_CSC_MODE(crtc->pipe));
+}
+
static void hsw_get_config(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);
+ crtc_state->csc_mode = ilk_read_csc_mode(crtc);
}
static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
@@ -3096,6 +3104,13 @@ static struct drm_property_blob *ilk_read_lut_10(struct
intel_crtc *crtc)
return blob;
}
+static void ilk_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ crtc_state->csc_mode = ilk_read_csc_mode(crtc);
+}
+
static void ilk_read_luts(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -3488,6 +3503,7 @@ static const struct intel_color_funcs ivb_color_funcs = {
.read_luts = ivb_read_luts,
.lut_equal = ivb_lut_equal,
.read_csc = ilk_read_csc,
+ .get_config = ilk_get_config,
};
static const struct intel_color_funcs ilk_color_funcs = {
@@ -3498,6 +3514,7 @@ static const struct intel_color_funcs ilk_color_funcs = {
.read_luts = ilk_read_luts,
.lut_equal = ilk_lut_equal,
.read_csc = ilk_read_csc,
+ .get_config = ilk_get_config,
};
void intel_color_crtc_init(struct intel_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 3c93f1676e14..a24466efe0ae 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3329,9 +3329,6 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
pipe_config->msa_timing_delay =
REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
- pipe_config->csc_mode = intel_de_read(dev_priv,
- PIPE_CSC_MODE(crtc->pipe));
-
i9xx_get_pipe_color_config(pipe_config);
intel_color_get_config(pipe_config);
@@ -3723,9 +3720,6 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
pipe_config->sink_format = pipe_config->output_format;
- pipe_config->csc_mode = intel_de_read(dev_priv,
- PIPE_CSC_MODE(crtc->pipe));
-
if (DISPLAY_VER(dev_priv) >= 9) {
tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
--
2.39.2
[Intel-gfx] [PATCH 3/6] drm/i915: move HSW+ gamma mode read to intel_color
Abstract the platform specific register access better. The separate
hsw_read_gamma_mode() will make more sense with the following changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_color.c | 20
drivers/gpu/drm/i915/display/intel_display.c | 3 ---
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 0a6d5ff494eb..25730697fa8a 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -902,6 +902,20 @@ static void hsw_color_commit_arm(const struct
intel_crtc_state *crtc_state)
crtc_state->csc_mode);
}
+static u32 hsw_read_gamma_mode(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+ return intel_de_read(i915, GAMMA_MODE(crtc->pipe));
+}
+
+static void hsw_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);
+}
+
static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -3407,6 +3421,7 @@ static const struct intel_color_funcs tgl_color_funcs = {
.read_luts = icl_read_luts,
.lut_equal = icl_lut_equal,
.read_csc = icl_read_csc,
+ .get_config = hsw_get_config,
};
static const struct intel_color_funcs icl_color_funcs = {
@@ -3418,6 +3433,7 @@ static const struct intel_color_funcs icl_color_funcs = {
.read_luts = icl_read_luts,
.lut_equal = icl_lut_equal,
.read_csc = icl_read_csc,
+ .get_config = hsw_get_config,
};
static const struct intel_color_funcs glk_color_funcs = {
@@ -3428,6 +3444,7 @@ static const struct intel_color_funcs glk_color_funcs = {
.read_luts = glk_read_luts,
.lut_equal = glk_lut_equal,
.read_csc = skl_read_csc,
+ .get_config = hsw_get_config,
};
static const struct intel_color_funcs skl_color_funcs = {
@@ -3438,6 +3455,7 @@ static const struct intel_color_funcs skl_color_funcs = {
.read_luts = bdw_read_luts,
.lut_equal = ivb_lut_equal,
.read_csc = skl_read_csc,
+ .get_config = hsw_get_config,
};
static const struct intel_color_funcs bdw_color_funcs = {
@@ -3448,6 +3466,7 @@ static const struct intel_color_funcs bdw_color_funcs = {
.read_luts = bdw_read_luts,
.lut_equal = ivb_lut_equal,
.read_csc = ilk_read_csc,
+ .get_config = hsw_get_config,
};
static const struct intel_color_funcs hsw_color_funcs = {
@@ -3458,6 +3477,7 @@ static const struct intel_color_funcs hsw_color_funcs = {
.read_luts = ivb_read_luts,
.lut_equal = ivb_lut_equal,
.read_csc = ilk_read_csc,
+ .get_config = hsw_get_config,
};
static const struct intel_color_funcs ivb_color_funcs = {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9b9b885db8d4..3c93f1676e14 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3723,9 +3723,6 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
pipe_config->sink_format = pipe_config->output_format;
- pipe_config->gamma_mode = intel_de_read(dev_priv,
- GAMMA_MODE(crtc->pipe));
-
pipe_config->csc_mode = intel_de_read(dev_priv,
PIPE_CSC_MODE(crtc->pipe));
--
2.39.2
[Intel-gfx] [PATCH 2/6] drm/i915/color: move CHV CGM pipe mode read to intel_color
Add color .get_config hook to read config other than LUTs and CSCs, and
start off with CHV CGM pipe mode to abstract the platform specific
register access better.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_color.c | 16
drivers/gpu/drm/i915/display/intel_display.c | 4
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index f458b136e6a8..0a6d5ff494eb 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -76,6 +76,10 @@ struct intel_color_funcs {
* software state. Used by eg. the hardware state checker.
*/
void (*read_csc)(struct intel_crtc_state *crtc_state);
+ /*
+* Read config other than LUTs and CSCs, before them. Optional.
+*/
+ void (*get_config)(struct intel_crtc_state *crtc_state);
};
#define CTM_COEFF_SIGN (1ULL << 63)
@@ -1737,6 +1741,9 @@ void intel_color_get_config(struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ if (i915->display.funcs.color->get_config)
+ i915->display.funcs.color->get_config(crtc_state);
+
i915->display.funcs.color->read_luts(crtc_state);
if (i915->display.funcs.color->read_csc)
@@ -3004,6 +3011,14 @@ static struct drm_property_blob
*chv_read_cgm_gamma(struct intel_crtc *crtc)
return blob;
}
+static void chv_get_config(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+ crtc_state->cgm_mode = intel_de_read(i915, CGM_PIPE_MODE(crtc->pipe));
+}
+
static void chv_read_luts(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -3365,6 +3380,7 @@ static const struct intel_color_funcs chv_color_funcs = {
.read_luts = chv_read_luts,
.lut_equal = chv_lut_equal,
.read_csc = chv_read_csc,
+ .get_config = chv_get_config,
};
static const struct intel_color_funcs i965_color_funcs = {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index bca7664d1ffc..9b9b885db8d4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2935,10 +2935,6 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
pipe_config->framestart_delay =
REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
- if (IS_CHERRYVIEW(dev_priv))
- pipe_config->cgm_mode = intel_de_read(dev_priv,
-
CGM_PIPE_MODE(crtc->pipe));
-
i9xx_get_pipe_color_config(pipe_config);
intel_color_get_config(pipe_config);
--
2.39.2
[Intel-gfx] [PATCH 1/6] drm/i915/regs: split out intel_color_regs.h
Declutter i915_regs.h. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/hsw_ips.c| 1 + drivers/gpu/drm/i915/display/intel_color.c| 1 + .../gpu/drm/i915/display/intel_color_regs.h | 272 ++ drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_overlay.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 260 - drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + 7 files changed, 277 insertions(+), 260 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_color_regs.h diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c index 8eca0de065b6..7dc38ac02092 100644 --- a/drivers/gpu/drm/i915/display/hsw_ips.c +++ b/drivers/gpu/drm/i915/display/hsw_ips.c @@ -6,6 +6,7 @@ #include "hsw_ips.h" #include "i915_drv.h" #include "i915_reg.h" +#include "intel_color_regs.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_pcode.h" diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 07f1afe1d406..f458b136e6a8 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -24,6 +24,7 @@ #include "i915_reg.h" #include "intel_color.h" +#include "intel_color_regs.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_dsb.h" diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h new file mode 100644 index ..30e6f66a724d --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h @@ -0,0 +1,272 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2023 Intel Corporation + */ + +#ifndef __INTEL_COLOR_REGS_H__ +#define __INTEL_COLOR_REGS_H__ + +#include "intel_display_reg_defs.h" + +/* legacy palette */ +#define _LGC_PALETTE_A 0x4a000 +#define _LGC_PALETTE_B 0x4a800 +/* see PALETTE_* for the bits */ +#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) + +/* ilk/snb precision palette */ +#define _PREC_PALETTE_A 0x4b000 +#define _PREC_PALETTE_B 0x4c000 +/* 10bit mode */ +#define PREC_PALETTE_10_RED_MASK REG_GENMASK(29, 20) +#define PREC_PALETTE_10_GREEN_MASK REG_GENMASK(19, 10) +#define PREC_PALETTE_10_BLUE_MASKREG_GENMASK(9, 0) +/* 12.4 interpolated mode ldw */ +#define PREC_PALETTE_12P4_RED_LDW_MASK REG_GENMASK(29, 24) +#define PREC_PALETTE_12P4_GREEN_LDW_MASK REG_GENMASK(19, 14) +#define PREC_PALETTE_12P4_BLUE_LDW_MASK REG_GENMASK(9, 4) +/* 12.4 interpolated mode udw */ +#define PREC_PALETTE_12P4_RED_UDW_MASK REG_GENMASK(29, 20) +#define PREC_PALETTE_12P4_GREEN_UDW_MASK REG_GENMASK(19, 10) +#define PREC_PALETTE_12P4_BLUE_UDW_MASK REG_GENMASK(9, 0) +#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) + +#define _PREC_PIPEAGCMAX 0x4d000 +#define _PREC_PIPEBGCMAX 0x4d010 +#define PREC_PIPEGCMAX(pipe, i)_MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1.16 */ + +#define _GAMMA_MODE_A 0x4a480 +#define _GAMMA_MODE_B 0x4ac80 +#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) +#define PRE_CSC_GAMMA_ENABLE REG_BIT(31) /* icl+ */ +#define POST_CSC_GAMMA_ENABLE REG_BIT(30) /* icl+ */ +#define PALETTE_ANTICOL_DISABLE REG_BIT(15) /* skl+ */ +#define GAMMA_MODE_MODE_MASK REG_GENMASK(1, 0) +#define GAMMA_MODE_MODE_8BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 0) +#define GAMMA_MODE_MODE_10BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 1) +#define GAMMA_MODE_MODE_12BIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 2) +#define GAMMA_MODE_MODE_SPLIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* ivb-bdw */ +#define GAMMA_MODE_MODE_12BIT_MULTI_SEG REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* icl-tgl */ + +/* pipe CSC */ +#define _PIPE_A_CSC_COEFF_RY_GY0x49010 +#define _PIPE_A_CSC_COEFF_BY 0x49014 +#define _PIPE_A_CSC_COEFF_RU_GU0x49018 +#define _PIPE_A_CSC_COEFF_BU 0x4901c +#define _PIPE_A_CSC_COEFF_RV_GV0x49020 +#define _PIPE_A_CSC_COEFF_BV 0x49024 + +#define _PIPE_A_CSC_MODE 0x49028 +#define ICL_CSC_ENABLE(1 << 31) /* icl+ */ +#define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */ +#define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */ +#define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */ +#define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */ + +#define _PIPE_A_CSC_PREOFF_HI 0x49030 +#define _PIPE_A_CSC_PREOFF_ME 0x49034 +#define _PIPE_A_CSC_PREOFF_LO 0x49038 +#define _PIPE_A_CSC_POSTOFF_HI 0x49040 +#define _PIPE_A_CSC_POSTOFF_ME 0x49044 +#define _PIPE_A_C
[Intel-gfx] [PATCH 0/6] drm/i915/color: register & get config abstractions
Move the color related registers to intel_color_regs.h and move the color config reads to intel_color_get_config() to declutter i915_reg.h and intel_display.c, respectively. BR, Jani. Jani Nikula (6): drm/i915/regs: split out intel_color_regs.h drm/i915/color: move CHV CGM pipe mode read to intel_color drm/i915: move HSW+ gamma mode read to intel_color drm/i915: move ILK+ CSC mode read to intel_color drm/i915/color: move SKL+ gamma and CSC enable read to intel_color drm/i915/color: move pre-SKL gamma and CSC enable read to intel_color drivers/gpu/drm/i915/display/hsw_ips.c| 1 + drivers/gpu/drm/i915/display/intel_color.c| 97 +++ .../gpu/drm/i915/display/intel_color_regs.h | 272 ++ drivers/gpu/drm/i915/display/intel_display.c | 45 --- drivers/gpu/drm/i915/display/intel_overlay.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 260 - drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + 7 files changed, 372 insertions(+), 305 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_color_regs.h -- 2.39.2
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v4,1/2] drm/i915/mtl: Add MTL performance tuning changes
== Series Details ==
Series: series starting with [v4,1/2] drm/i915/mtl: Add MTL performance tuning
changes
URL : https://patchwork.freedesktop.org/series/117847/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13154_full -> Patchwork_117847v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_117847v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2842]) +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-glk9/igt@gem_exec_fair@basic-p...@vcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/shard-glk5/igt@gem_exec_fair@basic-p...@vcs0.html
* igt@gem_mmap_gtt@fault-concurrent-y:
- shard-snb: [PASS][3] -> [ABORT][4] ([i915#5161])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-snb6/igt@gem_mmap_...@fault-concurrent-y.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/shard-snb2/igt@gem_mmap_...@fault-concurrent-y.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][5] -> [ABORT][6] ([i915#5566])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-apl3/igt@gen9_exec_pa...@allowed-all.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/shard-apl3/igt@gen9_exec_pa...@allowed-all.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2346])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-glk5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/shard-glk8/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
Possible fixes
* igt@gem_barrier_race@remote-request@rcs0:
- {shard-dg1}:[ABORT][9] ([i915#7461] / [i915#8234]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-dg1-14/igt@gem_barrier_race@remote-requ...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/shard-dg1-17/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][11] ([i915#2842]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- {shard-rkl}:[FAIL][13] ([i915#2842]) -> [PASS][14] +3 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-rkl-4/igt@gem_exec_fair@basic-n...@vcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/shard-rkl-3/igt@gem_exec_fair@basic-n...@vcs0.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-rkl}:[SKIP][15] ([i915#1397]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-rkl-3/igt@i915_pm_...@modeset-lpsp-stress-no-wait.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/shard-rkl-7/igt@i915_pm_...@modeset-lpsp-stress-no-wait.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][17] ([i915#2346]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-apl6/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117847v1/shard-apl2/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2527]: https://gitlab.
Re: [Intel-gfx] [PATCH v7 6/8] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
On 17/05/2023 13:42, Kandpal, Suraj wrote: The array of rc_parameters contains a mixture of parameters from DSC 1.1 and DSC 1.2 standards. Split these tow configuration arrays in preparation to adding more configuration data. Signed-off-by: Dmitry Baryshkov LGTM. Reviewed-by: Suraj Kandpal Just to note, this is not a proper R-B tag, it doesn't contain your email: 313685b15740 drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters -:12: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Suraj Kandpal' #12: Reviewed-by: Suraj Kandpal total: 1 errors, 0 warnings, 0 checks, 239 lines checked --- drivers/gpu/drm/display/drm_dsc_helper.c | 139 ++ drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +- include/drm/display/drm_dsc_helper.h | 7 +- 3 files changed, 129 insertions(+), 27 deletions(-) [skipped the patch] -- With best wishes Dmitry
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: move DSC RC tables to drm_dsc_helper.c (rev8)
== Series Details ==
Series: drm/i915: move DSC RC tables to drm_dsc_helper.c (rev8)
URL : https://patchwork.freedesktop.org/series/114473/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13158 -> Patchwork_114473v8
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/index.html
Participating hosts (36 -> 34)
--
Additional (1): bat-mtlp-6
Missing(3): fi-kbl-soraka bat-rpls-2 fi-snb-2520m
Known issues
Here are the changes found in Patchwork_114473v8 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gt_heartbeat:
- fi-bsw-nick:[PASS][1] -> [DMESG-FAIL][2] ([i915#5334])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/fi-bsw-nick/igt@i915_selftest@live@gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/fi-bsw-nick/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- bat-adlp-9: [PASS][3] -> [INCOMPLETE][4] ([i915#7677] /
[i915#7913])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/bat-adlp-9/igt@i915_selftest@l...@hangcheck.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/bat-adlp-9/igt@i915_selftest@l...@hangcheck.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1:
- bat-dg2-8: [PASS][5] -> [FAIL][6] ([i915#7932])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-3:
- bat-dg2-11: [PASS][7] -> [INCOMPLETE][8] ([i915#7908])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-3.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-...@pipe-b-hdmi-a-3.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-skl-guc: [DMESG-WARN][9] ([i915#8073]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [FAIL][11] ([i915#7932]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
Warnings
* igt@kms_psr@sprite_plane_onoff:
- bat-adln-1: [ABORT][13] ([i915#8442]) -> [ABORT][14] ([i915#8434]
/ [i915#8442])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13158/bat-adln-1/igt@kms_psr@sprite_plane_onoff.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v8/bat-adln-1/igt@kms_psr@sprite_plane_onoff.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6621]: https://g
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: move DSC RC tables to drm_dsc_helper.c (rev8)
== Series Details == Series: drm/i915: move DSC RC tables to drm_dsc_helper.c (rev8) URL : https://patchwork.freedesktop.org/series/114473/ State : warning == Summary == Error: dim checkpatch failed eb2b41f3d443 drm/i915/dsc: change DSC param tables to follow the DSC model 8da238066157 drm/i915/dsc: move rc_buf_thresh values to common helper eb367fd34b35 drm/i915/dsc: move DSC tables to DRM DSC helper 5e7eff11296f drm/i915/dsc: stop using interim structure for calculated params 3868256f67f5 drm/display/dsc: use flat array for rc_parameters lookup 313685b15740 drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters -:12: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Suraj Kandpal' #12: Reviewed-by: Suraj Kandpal total: 1 errors, 0 warnings, 0 checks, 239 lines checked a55bad9d938e drm/display/dsc: include the rest of pre-SCR parameters 62ba19a47aec drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
[Intel-gfx] ✓ Fi.CI.IGT: success for Add MTL PMU support for multi-gt
== Series Details ==
Series: Add MTL PMU support for multi-gt
URL : https://patchwork.freedesktop.org/series/117843/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13154_full -> Patchwork_117843v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_117843v1_full:
### IGT changes ###
Possible regressions
* {igt@perf_pmu@rc6-all-gts} (NEW):
- {shard-dg1}:NOTRUN -> [SKIP][1] +2 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/shard-dg1-16/igt@perf_...@rc6-all-gts.html
* {igt@perf_pmu@rc6@other-idle-gt0} (NEW):
- {shard-rkl}:NOTRUN -> [SKIP][2] +1 similar issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/shard-rkl-1/igt@perf_pmu@r...@other-idle-gt0.html
- {shard-tglu}: NOTRUN -> [SKIP][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/shard-tglu-5/igt@perf_pmu@r...@other-idle-gt0.html
New tests
-
New tests have been introduced between CI_DRM_13154_full and
Patchwork_117843v1_full:
### New IGT tests (7) ###
* igt@perf_pmu@frequency@gt0:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@perf_pmu@frequency@idle-gt0:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@perf_pmu@rc6-all-gts:
- Statuses : 4 skip(s)
- Exec time: [0.0] s
* igt@perf_pmu@rc6@gt0:
- Statuses : 6 pass(s)
- Exec time: [0.0] s
* igt@perf_pmu@rc6@other-idle-gt0:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@perf_pmu@rc6@runtime-pm-gt0:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@perf_pmu@rc6@runtime-pm-long-gt0:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_117843v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2842]) +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-apl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/shard-apl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/shard-apl3/igt@gem_huc_c...@huc-copy.html
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-snb: [PASS][9] -> [DMESG-FAIL][10] ([i915#8295])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-snb4/igt@gem_pp...@blt-vs-render-ctx0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/shard-snb6/igt@gem_pp...@blt-vs-render-ctx0.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][11] -> [DMESG-FAIL][12] ([i915#8319])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-snb4/igt@i915_pm_...@reset.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/shard-snb2/igt@i915_pm_...@reset.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#3886]) +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/shard-apl6/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium_color@ctm-0-75:
- shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271]) +43 similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/shard-apl1/igt@kms_chamelium_co...@ctm-0-75.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#2346])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-glk5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/shard-glk8/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [PASS][17] -> [ABORT][18] ([i915#180])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-apl1/igt@kms_flip@flip-vs-susp...@a-dp1.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117843v1/shard-
Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: create workqueue dedicated to wake references
On Fri, 2023-05-12 at 13:16 +0100, Tvrtko Ursulin wrote:
> On 12/05/2023 10:54, Coelho, Luciano wrote:
> > On Fri, 2023-05-12 at 10:32 +0100, Tvrtko Ursulin wrote:
> > > On 12/05/2023 10:10, Coelho, Luciano wrote:
> > > > On Fri, 2023-05-12 at 10:04 +0100, Tvrtko Ursulin wrote:
> > > > > On 11/05/2023 09:20, Luca Coelho wrote:
> > > > > > Add a work queue in the intel_wakeref structure to be used
> > > > > > exclusively
> > > > > > by the wake reference mechanism. This is needed in order to avoid
> > > > > > using the system workqueue and relying on flush_scheduled_work().
> > > > > >
> > > > > > Cc: Tetsuo Handa
> > > > > > Cc: Tvrtko Ursulin
> > > > > > Cc: Jani Nikula
> > > > > > Cc: Ville Syrjälä
> > > > > > Signed-off-by: Luca Coelho
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++-
> > > > > > drivers/gpu/drm/i915/gt/intel_engine_pm.c | 15 --
> > > > > > drivers/gpu/drm/i915/gt/intel_engine_pm.h | 3 ++-
> > > > > > drivers/gpu/drm/i915/gt/mock_engine.c | 8 +++-
> > > > > > drivers/gpu/drm/i915/intel_wakeref.c | 21
> > > > > > ++-
> > > > > > drivers/gpu/drm/i915/intel_wakeref.h | 25
> > > > > > +++
> > > > > > 6 files changed, 60 insertions(+), 19 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > > > > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > > > > index 0aff5bb13c53..6505bfa70cd0 100644
> > > > > > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > > > > @@ -1290,7 +1290,11 @@ static int engine_setup_common(struct
> > > > > > intel_engine_cs *engine)
> > > > > > goto err_cmd_parser;
> > > > > >
> > > > > > intel_engine_init_execlists(engine);
> > > > > > - intel_engine_init__pm(engine);
> > > > > > +
> > > > > > + err = intel_engine_init__pm(engine);
> > > > > > + if (err)
> > > > > > + goto err_cmd_parser;
> > > > > > +
> > > > > > intel_engine_init_retire(engine);
> > > > > >
> > > > > > /* Use the whole device by default */
> > > > > > @@ -1525,6 +1529,7 @@ void intel_engine_cleanup_common(struct
> > > > > > intel_engine_cs *engine)
> > > > > > {
> > > > > >
> > > > > > GEM_BUG_ON(!list_empty(&engine->sched_engine->requests));
> > > > > >
> > > > > > + intel_engine_destroy__pm(engine);
> > > > > > i915_sched_engine_put(engine->sched_engine);
> > > > > > intel_breadcrumbs_put(engine->breadcrumbs);
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > > > > > b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > > > > > index ee531a5c142c..859b62cf660f 100644
> > > > > > --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > > > > > @@ -294,14 +294,25 @@ static const struct intel_wakeref_ops wf_ops
> > > > > > = {
> > > > > > .put = __engine_park,
> > > > > > };
> > > > > >
> > > > > > -void intel_engine_init__pm(struct intel_engine_cs *engine)
> > > > > > +int intel_engine_init__pm(struct intel_engine_cs *engine)
> > > > > > {
> > > > > > struct intel_runtime_pm *rpm = engine->uncore->rpm;
> > > > > > + int err;
> > > > > > +
> > > > > > + err = intel_wakeref_init(&engine->wakeref, rpm, &wf_ops);
> > > > > > + if (err)
> > > > > > + return err;
> > > > > >
> > > > > > - intel_wakeref_init(&engine->wakeref, rpm, &wf_ops);
> > > > > > intel_engine_init_heartbeat(engine);
> > > > > >
> > > > > > intel_gsc_idle_msg_enable(engine);
> > > > > > +
> > > > > > + return 0;
> > > > > > +}
> > > > > > +
> > > > > > +void intel_engine_destroy__pm(struct intel_engine_cs *engine)
> > > > > > +{
> > > > > > + intel_wakeref_destroy(&engine->wakeref);
> > > > > > }
> > > > > >
> > > > > > /**
> > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.h
> > > > > > b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
> > > > > > index d68675925b79..e8568f7d10c6 100644
> > > > > > --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.h
> > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
> > > > > > @@ -104,7 +104,8 @@ intel_engine_create_kernel_request(struct
> > > > > > intel_engine_cs *engine)
> > > > > > return rq;
> > > > > > }
> > > > > >
> > > > > > -void intel_engine_init__pm(struct intel_engine_cs *engine);
> > > > > > +int intel_engine_init__pm(struct intel_engine_cs *engine);
> > > > > > +void intel_engine_destroy__pm(struct intel_engine_cs *engine);
> > > > > >
> > > > > > void intel_engine_reset_pinned_contexts(struct intel_engine_cs
> > > > > > *engine);
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c
> > > > > > b/drivers/gpu/drm/i915/gt/mock_engine.c
> > > > > > in
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Allow user to set cache at BO creation (rev9)
== Series Details ==
Series: drm/i915: Allow user to set cache at BO creation (rev9)
URL : https://patchwork.freedesktop.org/series/116870/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13154_full -> Patchwork_116870v9_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_116870v9_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_eio@in-flight-10ms:
- {shard-dg1}:[PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-dg1-18/igt@gem_...@in-flight-10ms.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/shard-dg1-15/igt@gem_...@in-flight-10ms.html
New tests
-
New tests have been introduced between CI_DRM_13154_full and
Patchwork_116870v9_full:
### New IGT tests (1) ###
* igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_116870v9_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/shard-apl2/igt@gem_huc_c...@huc-copy.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3886]) +1
similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/shard-apl2/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium_color@ctm-0-75:
- shard-apl: NOTRUN -> [SKIP][7] ([fdo#109271]) +36 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/shard-apl2/igt@kms_chamelium_co...@ctm-0-75.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][8] -> [FAIL][9] ([i915#2346])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-glk5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/shard-glk1/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
* igt@kms_panel_fitting@legacy:
- shard-apl: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4579]) +3
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/shard-apl2/igt@kms_panel_fitt...@legacy.html
* igt@kms_psr2_su@frontbuffer-xrgb:
- shard-apl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#658])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/shard-apl2/igt@kms_psr2...@frontbuffer-xrgb.html
Possible fixes
* igt@gem_barrier_race@remote-request@rcs0:
- {shard-dg1}:[ABORT][12] ([i915#7461] / [i915#8234]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-dg1-14/igt@gem_barrier_race@remote-requ...@rcs0.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/shard-dg1-17/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][14] ([i915#2842]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- {shard-rkl}:[FAIL][16] ([i915#2842]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-rkl-4/igt@gem_exec_fair@basic-n...@vcs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/shard-rkl-2/igt@gem_exec_fair@basic-n...@vcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [ABORT][18] ([i915#5566]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13154/shard-apl3/igt@gen9_exec_pa...@allowed-single.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v9/shard-apl2/igt@gen9_exec_pa...@allowed-single.html
* igt@i915_pm_dc@dc9-dpms:
- {shard-tglu}: [SKIP][20] ([i915#4281]) -> [P
Re: [Intel-gfx] [PATCH v7 6/8] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
>
> The array of rc_parameters contains a mixture of parameters from DSC 1.1
> and DSC 1.2 standards. Split these tow configuration arrays in preparation to
> adding more configuration data.
>
> Signed-off-by: Dmitry Baryshkov
LGTM.
Reviewed-by: Suraj Kandpal
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 139 ++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> include/drm/display/drm_dsc_helper.h | 7 +-
> 3 files changed, 129 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
> b/drivers/gpu/drm/display/drm_dsc_helper.c
> index acb93d4116e0..f1ba39df5708 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -325,10 +325,88 @@ struct rc_parameters_data {
> #define DSC_BPP(bpp) ((bpp) << 4)
>
> /*
> - * Selected Rate Control Related Parameter Recommended Values
> - * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> + * Rate Control Related Parameter Recommended Values from DSC_v1.1
> spec
> + prior
> + * to DSC 1.1 fractional bpp underflow SCR (DSC_v1.1_E1.pdf)
> + *
> + * Cross-checked against C Model releases: DSC_model_20161212 and
> + 20210623
> */
> -static const struct rc_parameters_data rc_parameters[] = {
> +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> + {
> + .bpp = DSC_BPP(8), .bpc = 8,
> + { 512, 12, 6144, 3, 12, 11, 11, {
> + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12,
> -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(8), .bpc = 10,
> + { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for
> range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12,
> -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16,
> -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(8), .bpc = 12,
> + { 512, 12, 6144, 11, 20, 19, 19, {
> + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11,
> 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 8,
> + { 341, 15, 2048, 3, 12, 11, 11, {
> + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13,
> 15, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 10,
> + { 341, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8
> },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16,
> -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 12,
> + { 341, 15, 2048, 11, 20, 19, 19, {
> + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11,
> 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> + },
> + { /* sentinel */ }
> +};
> +
> +/*
> + * Selected Rate Control Related Parameter Recommended Values from DSC
> +v1.2, v1.2a, v1.2b and
> + * DSC_v1.1_E1 specs.
> + *
> + * Cross-checked against C Model releases: DSC_model_20161212 and
> +20210623 */ static const struct rc_parameters_data
> +rc_parameters_1_2_444[] = {
> {
> .bpp = DSC_BPP(6), .bpc = 8,
> { 768, 15, 6144, 3, 13, 11, 11, {
> @@ -388,22 +466,18 @@
[Intel-gfx] [PATCH v7 8/8] drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
Include RC parameters for YCbCr 4:2:2 and 4:2:0 configurations.
Reviewed-by: Suraj Kandpal
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dsc_helper.c | 450 +++
include/drm/display/drm_dsc_helper.h | 2 +
2 files changed, 452 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
b/drivers/gpu/drm/display/drm_dsc_helper.c
index f6d8a7be5967..fc187a8d8873 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -748,6 +748,450 @@ static const struct rc_parameters_data
rc_parameters_1_2_444[] = {
{ /* sentinel */ }
};
+/*
+ * Selected Rate Control Related Parameter Recommended Values for 4:2:2 from
+ * DSC v1.2, v1.2a, v1.2b
+ *
+ * Cross-checked against C Model releases: DSC_model_20161212 and 20210623
+ */
+static const struct rc_parameters_data rc_parameters_1_2_422[] = {
+ {
+ .bpp = DSC_BPP(6), .bpc = 8,
+ { 512, 15, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11,
-12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 10,
+ { 512, 15, 6144, 7, 16, 15, 15, {
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12,
-8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15,
-12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 12,
+ { 512, 15, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11,
16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 14,
+ { 512, 15, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2
},
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15,
20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 16,
+ { 512, 15, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2
},
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19,
24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 8,
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10,
-10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 10,
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12,
-8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14,
-10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 12,
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2
},
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11,
16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 14,
+ { 410, 1
[Intel-gfx] [PATCH v7 3/8] drm/i915/dsc: move DSC tables to DRM DSC helper
Move DSC RC tables to DRM DSC helper. No additional code changes
and/or cleanups are a part of this commit, it will be cleaned up in the
followup commits.
Reviewed-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dsc_helper.c | 372 ++
drivers/gpu/drm/i915/display/intel_vdsc.c | 319 +--
include/drm/display/drm_dsc_helper.h | 1 +
3 files changed, 380 insertions(+), 312 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
b/drivers/gpu/drm/display/drm_dsc_helper.c
index be91abe2cfb2..122a292bbc8f 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -305,6 +305,378 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config
*vdsc_cfg)
}
EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
+enum ROW_INDEX_BPP {
+ ROW_INDEX_6BPP = 0,
+ ROW_INDEX_8BPP,
+ ROW_INDEX_10BPP,
+ ROW_INDEX_12BPP,
+ ROW_INDEX_15BPP,
+ MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+ COLUMN_INDEX_8BPC = 0,
+ COLUMN_INDEX_10BPC,
+ COLUMN_INDEX_12BPC,
+ COLUMN_INDEX_14BPC,
+ COLUMN_INDEX_16BPC,
+ MAX_COLUMN_INDEX
+};
+
+struct rc_parameters {
+ u16 initial_xmit_delay;
+ u8 first_line_bpg_offset;
+ u16 initial_offset;
+ u8 flatness_min_qp;
+ u8 flatness_max_qp;
+ u8 rc_quant_incr_limit0;
+ u8 rc_quant_incr_limit1;
+ struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+};
+
+/*
+ * Selected Rate Control Related Parameter Recommended Values
+ * from DSC_v1.11 spec & C Model release: DSC_model_20161212
+ */
+static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
+ {
+ /* 6BPP/8BPC */
+ { 768, 15, 6144, 3, 13, 11, 11, {
+ { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
+ { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
+ { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10,
12, -12 },
+ { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
+ }
+ },
+ /* 6BPP/10BPC */
+ { 768, 15, 6144, 7, 17, 15, 15, {
+ { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4
},
+ { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14,
-8 },
+ { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
+ { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
+ { 17, 18, -12 }
+ }
+ },
+ /* 6BPP/12BPC */
+ { 768, 15, 6144, 11, 21, 19, 19, {
+ { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16,
-4 },
+ { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14,
18, -8 },
+ { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
+ { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
+ { 21, 22, -12 }
+ }
+ },
+ /* 6BPP/14BPC */
+ { 768, 15, 6144, 15, 25, 23, 23, {
+ { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20,
-4 },
+ { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18,
22, -8 },
+ { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
+ { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
+ { 25, 26, -12 }
+ }
+ },
+ /* 6BPP/16BPC */
+ { 768, 15, 6144, 19, 29, 27, 27, {
+ { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24,
-4 },
+ { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22,
26, -8 },
+ { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
+ { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
+ { 29, 30, -12 }
+ }
+ },
+ },
+ {
+ /* 8BPP/8BPC */
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12,
-12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ },
+ /* 8BPP/10BPC */
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+* DSC model/pre-SCR-cfg has 8 for range_max_qp[0],
however
+* VESA DSC 1.1 Table E-5 sets it to 4.
+*/
+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+
[Intel-gfx] [PATCH v7 6/8] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
The array of rc_parameters contains a mixture of parameters from DSC 1.1
and DSC 1.2 standards. Split these tow configuration arrays in
preparation to adding more configuration data.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dsc_helper.c | 139 ++
drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
include/drm/display/drm_dsc_helper.h | 7 +-
3 files changed, 129 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
b/drivers/gpu/drm/display/drm_dsc_helper.c
index acb93d4116e0..f1ba39df5708 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -325,10 +325,88 @@ struct rc_parameters_data {
#define DSC_BPP(bpp) ((bpp) << 4)
/*
- * Selected Rate Control Related Parameter Recommended Values
- * from DSC_v1.11 spec & C Model release: DSC_model_20161212
+ * Rate Control Related Parameter Recommended Values from DSC_v1.1 spec prior
+ * to DSC 1.1 fractional bpp underflow SCR (DSC_v1.1_E1.pdf)
+ *
+ * Cross-checked against C Model releases: DSC_model_20161212 and 20210623
*/
-static const struct rc_parameters_data rc_parameters[] = {
+static const struct rc_parameters_data rc_parameters_pre_scr[] = {
+ {
+ .bpp = DSC_BPP(8), .bpc = 8,
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12,
-12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 10,
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+* DSC model/pre-SCR-cfg has 8 for range_max_qp[0],
however
+* VESA DSC 1.1 Table E-5 sets it to 4.
+*/
+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12,
-8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16,
-12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 12,
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11,
16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 8,
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13,
15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 10,
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8
},
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16,
-12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 12,
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11,
16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
+ { /* sentinel */ }
+};
+
+/*
+ * Selected Rate Control Related Parameter Recommended Values from DSC v1.2,
v1.2a, v1.2b and
+ * DSC_v1.1_E1 specs.
+ *
+ * Cross-checked against C Model releases: DSC_model_20161212 and 20210623
+ */
+static const struct rc_parameters_data rc_parameters_1_2_444[] = {
{
.bpp = DSC_BPP(6), .bpc = 8,
{ 768, 15, 6144, 3, 13, 11, 11, {
@@ -388,22 +466,18 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 512, 12, 6144, 3, 12, 11, 11, {
{ 0, 4,
