[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/huc: silence injected failure in the load via GSC path (rev6)
== Series Details ==
Series: drm/i915/huc: silence injected failure in the load via GSC path (rev6)
URL : https://patchwork.freedesktop.org/series/121080/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13627_full -> Patchwork_121080v6_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_121080v6_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_121080v6_full, please notify your bug team
(lgci.bug.fil...@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_121080v6_full:
### IGT changes ###
Possible regressions
* igt@perf_pmu@rc6-all-gts:
- shard-mtlp: NOTRUN -> [ABORT][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/shard-mtlp-5/igt@perf_...@rc6-all-gts.html
* igt@perf_pmu@render-node-busy-idle@rcs0:
- shard-rkl: [PASS][2] -> [INCOMPLETE][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/shard-rkl-7/igt@perf_pmu@render-node-busy-i...@rcs0.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/shard-rkl-6/igt@perf_pmu@render-node-busy-i...@rcs0.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_feature_discovery@display-4x}:
- shard-mtlp: NOTRUN -> [SKIP][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/shard-mtlp-5/igt@kms_feature_discov...@display-4x.html
* {igt@kms_feature_discovery@dp-mst}:
- shard-dg2: NOTRUN -> [SKIP][5] +1 other test skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/shard-dg2-11/igt@kms_feature_discov...@dp-mst.html
New tests
-
New tests have been introduced between CI_DRM_13627_full and
Patchwork_121080v6_full:
### New IGT tests (4) ###
* igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-a-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-b-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-128x128@pipe-a-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-128x128@pipe-d-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_121080v6_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@core_getversion:
- shard-mtlp: [PASS][6] -> [DMESG-WARN][7] ([i915#1982])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/shard-mtlp-3/igt@core_getversion.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/shard-mtlp-1/igt@core_getversion.html
* igt@device_reset@unbind-cold-reset-rebind:
- shard-dg2: NOTRUN -> [SKIP][8] ([i915#7701])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/shard-dg2-11/igt@device_re...@unbind-cold-reset-rebind.html
* igt@drm_fdinfo@busy@vcs0:
- shard-mtlp: NOTRUN -> [SKIP][9] ([i915#8414]) +6 other tests skip
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/shard-mtlp-2/igt@drm_fdinfo@b...@vcs0.html
* igt@drm_fdinfo@most-busy-check-all@bcs0:
- shard-dg2: NOTRUN -> [SKIP][10] ([i915#8414]) +10 other tests
skip
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/shard-dg2-6/igt@drm_fdinfo@most-busy-check-...@bcs0.html
* igt@drm_mm@drm_mm_test:
- shard-snb: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#8661]) +1
other test skip
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/shard-snb5/igt@drm_mm@drm_mm_test.html
* igt@gem_basic@multigpu-create-close:
- shard-mtlp: NOTRUN -> [SKIP][12] ([i915#7697])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/shard-mtlp-2/igt@gem_ba...@multigpu-create-close.html
* igt@gem_close_race@multigpu-basic-process:
- shard-dg2: NOTRUN -> [SKIP][13] ([i915#7697])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/shard-dg2-7/igt@gem_close_r...@multigpu-basic-process.html
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-snb: NOTRUN -> [DMESG-WARN][14] ([i915#8841]) +3 other
tests dmesg-warn
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/shard-snb5/igt@gem_ctx_isolation@preservation...@rcs0.html
* igt@gem_ctx_persistence@engines-persistence:
- shard-snb: NOTRUN
[Intel-gfx] ✗ Fi.CI.IGT: failure for i915/pmu: Move execlist stats initialization to execlist specific setup (rev2)
== Series Details ==
Series: i915/pmu: Move execlist stats initialization to execlist specific setup
(rev2)
URL : https://patchwork.freedesktop.org/series/123616/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13627_full -> Patchwork_123616v2_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_123616v2_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_123616v2_full, please notify your bug team
(lgci.bug.fil...@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 10)
--
Additional (1): shard-tglu0
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_123616v2_full:
### IGT changes ###
Possible regressions
* igt@perf_pmu@rc6-all-gts:
- shard-mtlp: NOTRUN -> [ABORT][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/shard-mtlp-6/igt@perf_...@rc6-all-gts.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_feature_discovery@display-4x}:
- shard-mtlp: NOTRUN -> [SKIP][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/shard-mtlp-6/igt@kms_feature_discov...@display-4x.html
New tests
-
New tests have been introduced between CI_DRM_13627_full and
Patchwork_123616v2_full:
### New IGT tests (4) ###
* igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-a-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_atomic_transition@plane-all-transition-nonblocking@pipe-b-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-128x128@pipe-a-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-128x128@pipe-d-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_123616v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [PASS][3] -> [FAIL][4] ([i915#7742])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/shard-rkl-2/igt@drm_fdinfo@most-busy-check-...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/shard-rkl-1/igt@drm_fdinfo@most-busy-check-...@rcs0.html
* igt@drm_fdinfo@virtual-busy:
- shard-dg2: NOTRUN -> [SKIP][5] ([i915#8414]) +1 other test skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/shard-dg2-1/igt@drm_fdi...@virtual-busy.html
* igt@drm_fdinfo@virtual-busy-hang:
- shard-mtlp: NOTRUN -> [SKIP][6] ([i915#8414]) +1 other test skip
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/shard-mtlp-4/igt@drm_fdi...@virtual-busy-hang.html
* igt@drm_mm@drm_mm_test:
- shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#8661]) +1
other test skip
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/shard-snb2/igt@drm_mm@drm_mm_test.html
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-snb: NOTRUN -> [DMESG-WARN][8] ([i915#8841]) +3 other
tests dmesg-warn
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/shard-snb2/igt@gem_ctx_isolation@preservation...@rcs0.html
* igt@gem_ctx_persistence@engines-persistence:
- shard-snb: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/shard-snb5/igt@gem_ctx_persiste...@engines-persistence.html
* igt@gem_ctx_persistence@heartbeat-many:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#8555])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/shard-mtlp-6/igt@gem_ctx_persiste...@heartbeat-many.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0:
- shard-dg2: NOTRUN -> [SKIP][11] ([i915#5882]) +9 other tests skip
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/shard-dg2-2/igt@gem_ctx_persistence@saturated-hostile-nopree...@ccs0.html
* igt@gem_ctx_sseu@engines:
- shard-dg2: NOTRUN -> [SKIP][12] ([i915#280])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/shard-dg2-2/igt@gem_ctx_s...@engines.html
* igt@gem_eio@hibernate:
- shard-dg1: [PASS][13] -> [ABORT][14] ([i915#7975] / [i915#8213])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/shard-dg1-18/igt@gem_...@hibernate.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/shard-dg1-14/igt@gem_...@hibernate.html
*
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Check lane count when determining FEC support
== Series Details ==
Series: series starting with [1/2] drm/i915: Check lane count when determining
FEC support
URL : https://patchwork.freedesktop.org/series/123643/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13627_full -> Patchwork_123643v1_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_123643v1_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_123643v1_full, please notify your bug team
(lgci.bug.fil...@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 10)
--
Additional (1): shard-tglu0
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_123643v1_full:
### IGT changes ###
Possible regressions
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-mtlp: [PASS][1] -> [ABORT][2] +1 other test abort
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/shard-mtlp-2/igt@gem_pp...@blt-vs-render-ctx0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/shard-mtlp-5/igt@gem_pp...@blt-vs-render-ctx0.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_feature_discovery@dp-mst}:
- shard-dg2: NOTRUN -> [SKIP][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/shard-dg2-7/igt@kms_feature_discov...@dp-mst.html
New tests
-
New tests have been introduced between CI_DRM_13627_full and
Patchwork_123643v1_full:
### New IGT tests (2) ###
* igt@kms_cursor_crc@cursor-onscreen-128x128@pipe-a-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-128x128@pipe-d-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_123643v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@drm_fdinfo@busy@vcs0:
- shard-mtlp: NOTRUN -> [SKIP][4] ([i915#8414]) +6 other tests skip
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/shard-mtlp-4/igt@drm_fdinfo@b...@vcs0.html
* igt@drm_fdinfo@most-busy-check-all@bcs0:
- shard-dg2: NOTRUN -> [SKIP][5] ([i915#8414]) +21 other tests skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/shard-dg2-2/igt@drm_fdinfo@most-busy-check-...@bcs0.html
* igt@drm_mm@drm_mm_test:
- shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#8661]) +1
other test skip
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/shard-snb1/igt@drm_mm@drm_mm_test.html
* igt@gem_basic@multigpu-create-close:
- shard-mtlp: NOTRUN -> [SKIP][7] ([i915#7697])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/shard-mtlp-4/igt@gem_ba...@multigpu-create-close.html
* igt@gem_busy@semaphore:
- shard-dg2: NOTRUN -> [SKIP][8] ([i915#3936])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/shard-dg2-2/igt@gem_b...@semaphore.html
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-snb: NOTRUN -> [DMESG-WARN][9] ([i915#8841]) +3 other
tests dmesg-warn
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/shard-snb1/igt@gem_ctx_isolation@preservation...@rcs0.html
* igt@gem_ctx_persistence@heartbeat-stop:
- shard-dg2: NOTRUN -> [SKIP][10] ([i915#8555])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/shard-dg2-2/igt@gem_ctx_persiste...@heartbeat-stop.html
* igt@gem_ctx_persistence@legacy-engines-hang@blt:
- shard-mtlp: [PASS][11] -> [ABORT][12] ([i915#9262])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/shard-mtlp-4/igt@gem_ctx_persistence@legacy-engines-h...@blt.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/shard-mtlp-6/igt@gem_ctx_persistence@legacy-engines-h...@blt.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0:
- shard-dg2: NOTRUN -> [SKIP][13] ([i915#5882]) +9 other tests skip
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/shard-dg2-11/igt@gem_ctx_persistence@saturated-hostile-nopree...@ccs0.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-dg2: NOTRUN -> [SKIP][14] ([i915#280]) +1 other test skip
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/shard-dg2-2/igt@gem_ctx_s...@invalid-sseu.html
* igt@gem_eio@kms:
- shard-dg2: [PASS][15] -> [FAIL][16] ([i915#5784])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/shard-dg2-11/igt@gem_...@kms.html
[16]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/1] drm/i915/pxp: Add drm_dbgs for critical PXP events.
== Series Details == Series: series starting with [v2,1/1] drm/i915/pxp: Add drm_dbgs for critical PXP events. URL : https://patchwork.freedesktop.org/series/123656/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13627 -> Patchwork_123656v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_123656v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_123656v1, please notify your bug team (lgci.bug.fil...@intel.com) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v1/index.html Participating hosts (42 -> 41) -- Missing(1): fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_123656v1: ### IGT changes ### Possible regressions * igt@i915_selftest@live@guc_multi_lrc: - fi-kbl-soraka: NOTRUN -> [ABORT][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v1/fi-kbl-soraka/igt@i915_selftest@live@guc_multi_lrc.html Known issues Here are the changes found in Patchwork_123656v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][2] ([i915#4613]) +3 other tests skip [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v1/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#4083]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v1/bat-mtlp-6/igt@gem_m...@basic.html * igt@gem_tiled_blits@basic: - bat-mtlp-6: NOTRUN -> [SKIP][4] ([i915#4077]) +2 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v1/bat-mtlp-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-mtlp-6: NOTRUN -> [SKIP][5] ([i915#4079]) +1 other test skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v1/bat-mtlp-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-6: NOTRUN -> [SKIP][6] ([i915#6621]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v1/bat-mtlp-6/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_engines: - bat-mtlp-6: NOTRUN -> [FAIL][7] ([i915#9278] / [i915#9290]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v1/bat-mtlp-6/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@gt_pm: - bat-mtlp-6: NOTRUN -> [DMESG-FAIL][8] ([i915#9270]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v1/bat-mtlp-6/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - bat-dg2-11: NOTRUN -> [ABORT][9] ([i915#7913]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v1/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@mman: - bat-rpls-1: [PASS][10] -> [TIMEOUT][11] ([i915#6794] / [i915#7392]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/bat-rpls-1/igt@i915_selftest@l...@mman.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v1/bat-rpls-1/igt@i915_selftest@l...@mman.html * igt@i915_selftest@live@requests: - bat-mtlp-8: [PASS][12] -> [ABORT][13] ([i915#9262]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/bat-mtlp-8/igt@i915_selftest@l...@requests.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html - bat-mtlp-6: NOTRUN -> [ABORT][14] ([i915#9262]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v1/bat-mtlp-6/igt@i915_selftest@l...@requests.html * igt@i915_suspend@basic-s2idle-without-i915: - bat-rpls-1: [PASS][15] -> [WARN][16] ([i915#8747]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/bat-rpls-1/igt@i915_susp...@basic-s2idle-without-i915.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v1/bat-rpls-1/igt@i915_susp...@basic-s2idle-without-i915.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][17] ([i915#4212]) +8 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v1/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#5190]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123656v1/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - bat-mtlp-6:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/1] drm/i915/pxp: Add drm_dbgs for critical PXP events.
== Series Details == Series: series starting with [v2,1/1] drm/i915/pxp: Add drm_dbgs for critical PXP events. URL : https://patchwork.freedesktop.org/series/123656/ State : warning == Summary == Error: dim checkpatch failed a1eb86307547 drm/i915/pxp: Add drm_dbgs for critical PXP events. -:93: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #93: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_irq.c:43: + pxp->session_events |= PXP_TERMINATION_REQUEST | PXP_INVAL_REQUIRED | PXP_EVENT_TYPE_IRQ; total: 0 errors, 1 warnings, 0 checks, 95 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/dp_mst: Fix NULL dereference during payload addition
== Series Details == Series: series starting with [1/4] drm/dp_mst: Fix NULL dereference during payload addition URL : https://patchwork.freedesktop.org/series/123652/ State : success == Summary == CI Bug Log - changes from CI_DRM_13627 -> Patchwork_123652v1 Summary --- **WARNING** Minor unknown changes coming with Patchwork_123652v1 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_123652v1, please notify your bug team (lgci.bug.fil...@intel.com) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123652v1/index.html Participating hosts (42 -> 41) -- Missing(1): fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_123652v1: ### IGT changes ### Warnings * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [DMESG-FAIL][1] ([i915#5334] / [i915#7872]) -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123652v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html Known issues Here are the changes found in Patchwork_123652v1 that come from known issues: ### CI changes ### Issues hit * boot: - fi-hsw-4770:[PASS][3] -> [FAIL][4] ([i915#8293]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/fi-hsw-4770/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123652v1/fi-hsw-4770/boot.html ### IGT changes ### Issues hit * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123652v1/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-6: NOTRUN -> [SKIP][6] ([i915#4083]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123652v1/bat-mtlp-6/igt@gem_m...@basic.html * igt@gem_tiled_blits@basic: - bat-mtlp-6: NOTRUN -> [SKIP][7] ([i915#4077]) +2 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123652v1/bat-mtlp-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-mtlp-6: NOTRUN -> [SKIP][8] ([i915#4079]) +1 other test skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123652v1/bat-mtlp-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-6: NOTRUN -> [SKIP][9] ([i915#6621]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123652v1/bat-mtlp-6/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_engines: - bat-mtlp-6: NOTRUN -> [FAIL][10] ([i915#9278] / [i915#9290]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123652v1/bat-mtlp-6/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@gt_pm: - bat-mtlp-6: NOTRUN -> [DMESG-FAIL][11] ([i915#9270]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123652v1/bat-mtlp-6/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@requests: - bat-mtlp-8: [PASS][12] -> [ABORT][13] ([i915#9262]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/bat-mtlp-8/igt@i915_selftest@l...@requests.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123652v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html - bat-mtlp-6: NOTRUN -> [ABORT][14] ([i915#9262]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123652v1/bat-mtlp-6/igt@i915_selftest@l...@requests.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][15] ([i915#4212]) +8 other tests skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123652v1/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][16] ([i915#5190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123652v1/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][17] ([i915#1845]) +12 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123652v1/bat-mtlp-6/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html * igt@kms_flip@basic-flip-vs-dpms: - bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#3637]) +3 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123652v1/bat-mtlp-6/igt@kms_f...@basic-flip-vs-dpms.html *
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: prepare for xe driver display integration (rev2)
== Series Details ==
Series: drm/i915: prepare for xe driver display integration (rev2)
URL : https://patchwork.freedesktop.org/series/123595/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13626_full -> Patchwork_123595v2_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_123595v2_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_123595v2_full, please notify your bug team
(lgci.bug.fil...@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_123595v2_full:
### IGT changes ###
Possible regressions
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-mtlp: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/shard-mtlp-5/igt@gem_...@ctrl-surf-copy-new-ctx.html
* igt@gem_mmap_offset@clear@smem0:
- shard-mtlp: [PASS][2] -> [ABORT][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/shard-mtlp-6/igt@gem_mmap_offset@cl...@smem0.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/shard-mtlp-5/igt@gem_mmap_offset@cl...@smem0.html
* igt@kms_flip@plain-flip-fb-recreate@a-vga1:
- shard-snb: [PASS][4] -> [ABORT][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/shard-snb6/igt@kms_flip@plain-flip-fb-recre...@a-vga1.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/shard-snb5/igt@kms_flip@plain-flip-fb-recre...@a-vga1.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_feature_discovery@dp-mst}:
- shard-dg2: NOTRUN -> [SKIP][6]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/shard-dg2-6/igt@kms_feature_discov...@dp-mst.html
Known issues
Here are the changes found in Patchwork_123595v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@api_intel_bb@object-reloc-purge-cache:
- shard-dg2: NOTRUN -> [SKIP][7] ([i915#8411])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/shard-dg2-7/igt@api_intel...@object-reloc-purge-cache.html
* igt@drm_fdinfo@all-busy-idle-check-all:
- shard-dg1: NOTRUN -> [SKIP][8] ([i915#8414])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/shard-dg1-12/igt@drm_fdi...@all-busy-idle-check-all.html
* igt@drm_fdinfo@busy-hang@bcs0:
- shard-dg2: NOTRUN -> [SKIP][9] ([i915#8414]) +9 other tests skip
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/shard-dg2-7/igt@drm_fdinfo@busy-h...@bcs0.html
* igt@drm_fdinfo@most-busy-check-all@vcs0:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#8414]) +5 other tests skip
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/shard-mtlp-2/igt@drm_fdinfo@most-busy-check-...@vcs0.html
* igt@gem_barrier_race@remote-request@rcs0:
- shard-glk: [PASS][11] -> [ABORT][12] ([i915#7461] / [i915#8190])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/shard-glk7/igt@gem_barrier_race@remote-requ...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/shard-glk5/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@gem_close_race@multigpu-basic-process:
- shard-mtlp: NOTRUN -> [SKIP][13] ([i915#7697])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/shard-mtlp-1/igt@gem_close_r...@multigpu-basic-process.html
* igt@gem_ctx_isolation@preservation@rcs0:
- shard-mtlp: NOTRUN -> [FAIL][14] ([i915#9327])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/shard-mtlp-5/igt@gem_ctx_isolation@preservat...@rcs0.html
* igt@gem_ctx_persistence@engines-persistence:
- shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#1099])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/shard-snb2/igt@gem_ctx_persiste...@engines-persistence.html
* igt@gem_ctx_persistence@heartbeat-stop:
- shard-mtlp: NOTRUN -> [SKIP][16] ([i915#8555])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/shard-mtlp-2/igt@gem_ctx_persiste...@heartbeat-stop.html
* igt@gem_ctx_persistence@legacy-engines-hang@bsd1:
- shard-mtlp: NOTRUN -> [FAIL][17] ([i915#2410])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/shard-mtlp-1/igt@gem_ctx_persistence@legacy-engines-h...@bsd1.html
* igt@gem_ctx_sseu@invalid-args:
- shard-dg1: NOTRUN ->
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/4] drm/dp_mst: Fix NULL dereference during payload addition
== Series Details == Series: series starting with [1/4] drm/dp_mst: Fix NULL dereference during payload addition URL : https://patchwork.freedesktop.org/series/123652/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/huc: silence injected failure in the load via GSC path (rev6)
== Series Details == Series: drm/i915/huc: silence injected failure in the load via GSC path (rev6) URL : https://patchwork.freedesktop.org/series/121080/ State : success == Summary == CI Bug Log - changes from CI_DRM_13627 -> Patchwork_121080v6 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/index.html Participating hosts (42 -> 40) -- Missing(2): fi-snb-2520m fi-pnv-d510 Known issues Here are the changes found in Patchwork_121080v6 that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][1] ([i915#4613]) +3 other tests skip [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-6: NOTRUN -> [SKIP][2] ([i915#4083]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@gem_m...@basic.html * igt@gem_tiled_blits@basic: - bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#4077]) +2 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-mtlp-6: NOTRUN -> [SKIP][4] ([i915#4079]) +1 other test skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-6: NOTRUN -> [SKIP][5] ([i915#6621]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_engines: - bat-mtlp-6: NOTRUN -> [FAIL][6] ([i915#9278] / [i915#9290]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@gt_pm: - bat-mtlp-6: NOTRUN -> [DMESG-FAIL][7] ([i915#9270]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@requests: - bat-mtlp-8: [PASS][8] -> [ABORT][9] ([i915#9262]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/bat-mtlp-8/igt@i915_selftest@l...@requests.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-8/igt@i915_selftest@l...@requests.html - bat-mtlp-6: NOTRUN -> [ABORT][10] ([i915#9262]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@i915_selftest@l...@requests.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][11] ([i915#4212]) +8 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][12] ([i915#5190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][13] ([i915#1845]) +12 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html * igt@kms_flip@basic-flip-vs-dpms: - bat-mtlp-6: NOTRUN -> [SKIP][14] ([i915#3637]) +3 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@kms_f...@basic-flip-vs-dpms.html * igt@kms_force_connector_basic@force-load-detect: - bat-mtlp-6: NOTRUN -> [SKIP][15] ([fdo#109285]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-mtlp-6: NOTRUN -> [SKIP][16] ([i915#5274]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_frontbuffer_tracking@basic: - bat-mtlp-6: NOTRUN -> [SKIP][17] ([i915#4342]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@nonblocking-crc: - bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#1845] / [i915#4078]) +3 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@kms_pipe_crc_ba...@nonblocking-crc.html * igt@kms_psr@cursor_plane_move: - bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#1072]) +3 other tests skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121080v6/bat-mtlp-6/igt@kms_psr@cursor_plane_move.html
[Intel-gfx] ✓ Fi.CI.BAT: success for i915/pmu: Move execlist stats initialization to execlist specific setup (rev2)
== Series Details == Series: i915/pmu: Move execlist stats initialization to execlist specific setup (rev2) URL : https://patchwork.freedesktop.org/series/123616/ State : success == Summary == CI Bug Log - changes from CI_DRM_13627 -> Patchwork_123616v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/index.html Participating hosts (42 -> 41) -- Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_123616v2 that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][1] ([i915#4613]) +3 other tests skip [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-6: NOTRUN -> [SKIP][2] ([i915#4083]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/bat-mtlp-6/igt@gem_m...@basic.html * igt@gem_tiled_blits@basic: - bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#4077]) +2 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/bat-mtlp-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-mtlp-6: NOTRUN -> [SKIP][4] ([i915#4079]) +1 other test skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/bat-mtlp-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-6: NOTRUN -> [SKIP][5] ([i915#6621]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/bat-mtlp-6/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_engines: - bat-mtlp-6: NOTRUN -> [FAIL][6] ([i915#9278] / [i915#9290]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/bat-mtlp-6/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@gt_pm: - bat-mtlp-6: NOTRUN -> [DMESG-FAIL][7] ([i915#9270]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/bat-mtlp-6/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@requests: - bat-mtlp-8: [PASS][8] -> [ABORT][9] ([i915#9262]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/bat-mtlp-8/igt@i915_selftest@l...@requests.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/bat-mtlp-8/igt@i915_selftest@l...@requests.html - bat-mtlp-6: NOTRUN -> [ABORT][10] ([i915#9262]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/bat-mtlp-6/igt@i915_selftest@l...@requests.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][11] ([i915#4212]) +8 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][12] ([i915#5190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][13] ([i915#1845]) +12 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/bat-mtlp-6/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html * igt@kms_flip@basic-flip-vs-dpms: - bat-mtlp-6: NOTRUN -> [SKIP][14] ([i915#3637]) +3 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/bat-mtlp-6/igt@kms_f...@basic-flip-vs-dpms.html * igt@kms_force_connector_basic@force-load-detect: - bat-mtlp-6: NOTRUN -> [SKIP][15] ([fdo#109285]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/bat-mtlp-6/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-mtlp-6: NOTRUN -> [SKIP][16] ([i915#5274]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/bat-mtlp-6/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_frontbuffer_tracking@basic: - bat-mtlp-6: NOTRUN -> [SKIP][17] ([i915#4342]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/bat-mtlp-6/igt@kms_frontbuffer_track...@basic.html * igt@kms_hdmi_inject@inject-audio: - fi-kbl-guc: [PASS][18] -> [FAIL][19] ([IGT#3] / [i915#6121]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123616v2/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html * igt@kms_pipe_crc_basic@nonblocking-crc: - bat-mtlp-6: NOTRUN -> [SKIP][20] ([i915#1845] / [i915#4078]) +3 other tests skip [20]:
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Check lane count when determining FEC support
== Series Details == Series: series starting with [1/2] drm/i915: Check lane count when determining FEC support URL : https://patchwork.freedesktop.org/series/123643/ State : success == Summary == CI Bug Log - changes from CI_DRM_13627 -> Patchwork_123643v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/index.html Participating hosts (42 -> 40) -- Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_123643v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][1] ([i915#4613]) +3 other tests skip [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-6: NOTRUN -> [SKIP][2] ([i915#4083]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-6/igt@gem_m...@basic.html * igt@gem_tiled_blits@basic: - bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#4077]) +2 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-mtlp-6: NOTRUN -> [SKIP][4] ([i915#4079]) +1 other test skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-6: NOTRUN -> [SKIP][5] ([i915#6621]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-6/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_engines: - bat-mtlp-6: NOTRUN -> [FAIL][6] ([i915#9278] / [i915#9290]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-6/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@gt_pm: - bat-mtlp-6: NOTRUN -> [DMESG-FAIL][7] ([i915#9270]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-6/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@requests: - bat-mtlp-8: [PASS][8] -> [ABORT][9] ([i915#9262]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/bat-mtlp-8/igt@i915_selftest@l...@requests.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html - bat-mtlp-6: NOTRUN -> [ABORT][10] ([i915#9262]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-6/igt@i915_selftest@l...@requests.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][11] ([i915#4212]) +8 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][12] ([i915#5190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][13] ([i915#1845]) +12 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-6/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html * igt@kms_flip@basic-flip-vs-dpms: - bat-mtlp-6: NOTRUN -> [SKIP][14] ([i915#3637]) +3 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-6/igt@kms_f...@basic-flip-vs-dpms.html * igt@kms_force_connector_basic@force-load-detect: - bat-mtlp-6: NOTRUN -> [SKIP][15] ([fdo#109285]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-6/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-mtlp-6: NOTRUN -> [SKIP][16] ([i915#5274]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-6/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_frontbuffer_tracking@basic: - bat-mtlp-6: NOTRUN -> [SKIP][17] ([i915#4342]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-6/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@nonblocking-crc: - bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#1845] / [i915#4078]) +3 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123643v1/bat-mtlp-6/igt@kms_pipe_crc_ba...@nonblocking-crc.html * igt@kms_psr@cursor_plane_move: - bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#1072]) +3 other tests skip [19]:
[Intel-gfx] [PATCH v2 1/1] drm/i915/pxp: Add drm_dbgs for critical PXP events.
Debugging PXP issues can't even begin without understanding precedding
sequence of events. Add drm_dbg into the most important PXP events.
v2 : - remove __func__ since drm_dbg covers that (Jani).
- add timeout of the restart from front-end (Alan).
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 2 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 15 ---
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 4 ++--
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 6 +-
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 1 +
5 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
index 5f138de3c14f..61216c4abaec 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
@@ -321,6 +321,7 @@ static int i915_gsc_proxy_component_bind(struct device
*i915_kdev,
mutex_lock(>proxy.mutex);
gsc->proxy.component = data;
gsc->proxy.component->mei_dev = mei_kdev;
+ gt_dbg(gt, "GSC proxy mei component bound\n");
mutex_unlock(>proxy.mutex);
return 0;
@@ -342,6 +343,7 @@ static void i915_gsc_proxy_component_unbind(struct device
*i915_kdev,
with_intel_runtime_pm(>runtime_pm, wakeref)
intel_uncore_rmw(gt->uncore, HECI_H_CSR(MTL_GSC_HECI2_BASE),
HECI_H_CSR_IE | HECI_H_CSR_RST, 0);
+ gt_dbg(gt, "GSC proxy mei component unbound\n");
}
static const struct component_ops i915_gsc_proxy_component_ops = {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index dc327cf40b5a..e11f562b1876 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -303,6 +303,8 @@ static int __pxp_global_teardown_final(struct intel_pxp
*pxp)
if (!pxp->arb_is_valid)
return 0;
+
+ drm_dbg(>ctrl_gt->i915->drm, "PXP: teardown for suspend/fini");
/*
* To ensure synchronous and coherent session teardown completion
* in response to suspend or shutdown triggers, don't use a worker.
@@ -324,6 +326,8 @@ static int __pxp_global_teardown_restart(struct intel_pxp
*pxp)
if (pxp->arb_is_valid)
return 0;
+
+ drm_dbg(>ctrl_gt->i915->drm, "PXP: teardown for restart");
/*
* The arb-session is currently inactive and we are doing a reset and
restart
* due to a runtime event. Use the worker that was designed for this.
@@ -332,8 +336,11 @@ static int __pxp_global_teardown_restart(struct intel_pxp
*pxp)
timeout = intel_pxp_get_backend_timeout_ms(pxp);
- if (!wait_for_completion_timeout(>termination,
msecs_to_jiffies(timeout)))
+ if (!wait_for_completion_timeout(>termination,
msecs_to_jiffies(timeout))) {
+ drm_dbg(>ctrl_gt->i915->drm, "PXP: restart backend timed
out (%d ms)",
+ timeout);
return -ETIMEDOUT;
+ }
return 0;
}
@@ -414,10 +421,12 @@ int intel_pxp_start(struct intel_pxp *pxp)
int ret = 0;
ret = intel_pxp_get_readiness_status(pxp, PXP_READINESS_TIMEOUT);
- if (ret < 0)
+ if (ret < 0) {
+ drm_dbg(>ctrl_gt->i915->drm, "PXP: tried but not-avail
(%d)", ret);
return ret;
- else if (ret > 1)
+ } else if (ret > 1) {
return -EIO; /* per UAPI spec, user may retry later */
+ }
mutex_lock(>arb_mutex);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
index 91e9622c07d0..0637b1d36356 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
@@ -40,11 +40,11 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT)) {
/* immediately mark PXP as inactive on termination */
intel_pxp_mark_termination_in_progress(pxp);
- pxp->session_events |= PXP_TERMINATION_REQUEST |
PXP_INVAL_REQUIRED;
+ pxp->session_events |= PXP_TERMINATION_REQUEST |
PXP_INVAL_REQUIRED | PXP_EVENT_TYPE_IRQ;
}
if (iir & GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT)
- pxp->session_events |= PXP_TERMINATION_COMPLETE;
+ pxp->session_events |= PXP_TERMINATION_COMPLETE |
PXP_EVENT_TYPE_IRQ;
if (pxp->session_events)
queue_work(system_unbound_wq, >session_work);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
index 0a3e66b0265e..091c86e03d1a 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -137,8 +137,10 @@ void intel_pxp_terminate(struct intel_pxp *pxp, bool
post_invalidation_needs_res
static void
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Convert fbdev to DRM client (rev2)
== Series Details == Series: drm/i915: Convert fbdev to DRM client (rev2) URL : https://patchwork.freedesktop.org/series/115714/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13627 -> Patchwork_115714v2 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_115714v2 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_115714v2, please notify your bug team (lgci.bug.fil...@intel.com) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115714v2/index.html Participating hosts (42 -> 40) -- Missing(2): fi-kbl-soraka fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_115714v2: ### IGT changes ### Possible regressions * igt@gem_lmem_swapping@basic: - bat-dg1-5: NOTRUN -> [FAIL][1] +3 other tests fail [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115714v2/bat-dg1-5/igt@gem_lmem_swapp...@basic.html - bat-dg2-11: NOTRUN -> [FAIL][2] +5 other tests fail [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115714v2/bat-dg2-11/igt@gem_lmem_swapp...@basic.html * igt@i915_module_load@load: - bat-atsm-1: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/bat-atsm-1/igt@i915_module_l...@load.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115714v2/bat-atsm-1/igt@i915_module_l...@load.html * igt@i915_module_load@reload: - bat-mtlp-6: NOTRUN -> [WARN][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115714v2/bat-mtlp-6/igt@i915_module_l...@reload.html - fi-skl-6600u: [PASS][6] -> [WARN][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/fi-skl-6600u/igt@i915_module_l...@reload.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115714v2/fi-skl-6600u/igt@i915_module_l...@reload.html - fi-apl-guc: [PASS][8] -> [WARN][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/fi-apl-guc/igt@i915_module_l...@reload.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115714v2/fi-apl-guc/igt@i915_module_l...@reload.html - bat-dg1-5: [PASS][10] -> [WARN][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/bat-dg1-5/igt@i915_module_l...@reload.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115714v2/bat-dg1-5/igt@i915_module_l...@reload.html - fi-pnv-d510:[PASS][12] -> [WARN][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/fi-pnv-d510/igt@i915_module_l...@reload.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115714v2/fi-pnv-d510/igt@i915_module_l...@reload.html - fi-glk-j4005: [PASS][14] -> [WARN][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/fi-glk-j4005/igt@i915_module_l...@reload.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115714v2/fi-glk-j4005/igt@i915_module_l...@reload.html - bat-adlp-9: [PASS][16] -> [WARN][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/bat-adlp-9/igt@i915_module_l...@reload.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115714v2/bat-adlp-9/igt@i915_module_l...@reload.html - fi-skl-guc: [PASS][18] -> [WARN][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/fi-skl-guc/igt@i915_module_l...@reload.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115714v2/fi-skl-guc/igt@i915_module_l...@reload.html - bat-dg2-11: [PASS][20] -> [WARN][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/bat-dg2-11/igt@i915_module_l...@reload.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115714v2/bat-dg2-11/igt@i915_module_l...@reload.html - fi-cfl-8700k: [PASS][22] -> [WARN][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/fi-cfl-8700k/igt@i915_module_l...@reload.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115714v2/fi-cfl-8700k/igt@i915_module_l...@reload.html - fi-bsw-nick:[PASS][24] -> [WARN][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/fi-bsw-nick/igt@i915_module_l...@reload.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115714v2/fi-bsw-nick/igt@i915_module_l...@reload.html - bat-kbl-2: [PASS][26] -> [WARN][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13627/bat-kbl-2/igt@i915_module_l...@reload.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115714v2/bat-kbl-2/igt@i915_module_l...@reload.html - fi-rkl-11600: [PASS][28] -> [WARN][29]
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Convert fbdev to DRM client (rev2)
== Series Details == Series: drm/i915: Convert fbdev to DRM client (rev2) URL : https://patchwork.freedesktop.org/series/115714/ State : warning == Summary == Error: dim checkpatch failed e92810deb3f2 drm/i915: Move fbdev functions -:119: CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*ifbdev)...) over kzalloc(sizeof(struct intel_fbdev)...) #119: FILE: drivers/gpu/drm/i915/display/intel_fbdev.c:683: + ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL); -:120: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!ifbdev" #120: FILE: drivers/gpu/drm/i915/display/intel_fbdev.c:684: + if (ifbdev == NULL) total: 0 errors, 0 warnings, 2 checks, 172 lines checked ee453b41ffc0 drm/i915: Initialize fbdev DRM client with callback functions 6c308c8ce62b drm/i915: Implement fbdev client callbacks e8823e5a5cd3 drm/i915: Implement fbdev emulation as in-kernel client
[Intel-gfx] [PATCH 4/4] drm/i915/dp_mst: Tune down error message during payload addition
If a sink is removed in the middle of payload addition drm_dp_add_payload_part1() will fail as expected, either not finding the payload's MST port or failing the payload-add AUX transaction. Based on the above tune the error message down to a debug messge. Cc: Lyude Paul Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 1c7f0b6afe475..ff3accebf0a89 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -726,8 +726,8 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, ret = drm_dp_add_payload_part1(_dp->mst_mgr, mst_state, drm_atomic_get_mst_payload_state(mst_state, connector->port)); if (ret < 0) - drm_err(_priv->drm, "Failed to create MST payload for %s: %d\n", - connector->base.name, ret); + drm_dbg_kms(_priv->drm, "Failed to create MST payload for %s: %d\n", + connector->base.name, ret); /* * Before Gen 12 this is not done as part of -- 2.37.2
[Intel-gfx] [PATCH 3/4] drm/dp_mst: Tune down error message during payload addition
If a sink is removed in the middle of payload addition the corresponding
AUX transfer will fail as expected, so tune the error message down to a
debug messge.
Cc: Wayne Lin
Cc: Lyude Paul
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index dbec9cf004594..c490e8befc2fa 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -3332,8 +3332,8 @@ int drm_dp_add_payload_part1(struct
drm_dp_mst_topology_mgr *mgr,
ret = drm_dp_create_payload_at_dfp(mgr, payload);
if (ret < 0) {
- drm_warn(mgr->dev, "Failed to create MST payload for port %p:
%d\n",
-payload->port, ret);
+ drm_dbg_kms(mgr->dev, "Failed to create MST payload for port
%p: %d\n",
+ payload->port, ret);
goto put_port;
}
--
2.37.2
[Intel-gfx] [PATCH 2/4] drm/dp_mst: Sanitize error return during payload addition
Return an error during payload addition if the payload port isn't
found. This shouldn't change the behavior since only the i915 driver
checks the return value, printing an error message in case of a failure.
While at it simplify the control flow.
Cc: Wayne Lin
Cc: Lyude Paul
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 26 +--
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 5f90860d49c34..dbec9cf004594 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -3308,8 +3308,7 @@ int drm_dp_add_payload_part1(struct
drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_atomic_payload *payload)
{
struct drm_dp_mst_port *port;
- int ret = 0;
- bool allocate = true;
+ int ret;
/* Update mst mgr info */
if (mgr->payload_count == 0)
@@ -3320,29 +3319,28 @@ int drm_dp_add_payload_part1(struct
drm_dp_mst_topology_mgr *mgr,
mgr->payload_count++;
mgr->next_start_slot += payload->time_slots;
+ payload->payload_allocation_status =
DRM_DP_MST_PAYLOAD_ALLOCATION_LOCAL;
+
/* Allocate payload to immediate downstream facing port */
port = drm_dp_mst_topology_get_port_validated(mgr, payload->port);
if (!port) {
drm_dbg_kms(mgr->dev,
"VCPI %d for port %p not in topology, not creating
a payload to remote\n",
payload->vcpi, payload->port);
- allocate = false;
+ return -EIO;
}
- if (allocate) {
- ret = drm_dp_create_payload_at_dfp(mgr, payload);
- if (ret < 0)
- drm_warn(mgr->dev, "Failed to create MST payload for
port %p: %d\n",
-payload->port, ret);
-
+ ret = drm_dp_create_payload_at_dfp(mgr, payload);
+ if (ret < 0) {
+ drm_warn(mgr->dev, "Failed to create MST payload for port %p:
%d\n",
+payload->port, ret);
+ goto put_port;
}
- payload->payload_allocation_status =
- (!allocate || ret < 0) ? DRM_DP_MST_PAYLOAD_ALLOCATION_LOCAL :
-
DRM_DP_MST_PAYLOAD_ALLOCATION_DFP;
+ payload->payload_allocation_status = DRM_DP_MST_PAYLOAD_ALLOCATION_DFP;
- if (port)
- drm_dp_mst_topology_put_port(port);
+put_port:
+ drm_dp_mst_topology_put_port(port);
return ret;
}
--
2.37.2
[Intel-gfx] [PATCH 1/4] drm/dp_mst: Fix NULL dereference during payload addition
Fix the NULL dereference leading to the following stack trace:
[ 129.687181] i915 :00:02.0: [drm:drm_dp_add_payload_part1
[drm_display_helper]] VCPI 1 for port 5be4423e not in topology, not
creating a payload to remote
[ 129.687257] BUG: kernel NULL pointer dereference, address: 0560
[ 129.694276] #PF: supervisor read access in kernel mode
[ 129.699459] #PF: error_code(0x) - not-present page
[ 129.704612] PGD 0 P4D 0
[ 129.707178] Oops: [#1] PREEMPT SMP NOPTI
[ 129.711556] CPU: 2 PID: 1623 Comm: Xorg Tainted: G U
6.6.0-rc1-imre+ #985
[ 129.719744] Hardware name: Intel Corporation Alder Lake Client
Platform/AlderLake-P DDR5 RVP, BIOS RPLPFWI1.R00.4035.A00.2301200723 01/20/2023
[ 129.732509] RIP: 0010:drm_dp_mst_topology_put_port+0x19/0x170
[drm_display_helper]
[ 129.740111] Code: 00 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 0f 1f
44 00 00 55 48 89 e5 41 57 41 56 41 55 41 54 53 48 89 fb 48 83 ec 08 <48> 8b 87
60 05 00 00 44 8b 0f 48 8b 70 58 41 83 e9 01 48 85 f6 74
[ 129.758842] RSP: 0018:c90001daf900 EFLAGS: 00010286
[ 129.764104] RAX: 0001 RBX: RCX:
[ 129.771246] RDX: RSI: 9e73d613 RDI:
[ 129.778394] RBP: c90001daf930 R08: R09: 0020
[ 129.785533] R10: 0010 R11: 000f R12: 888116c65e40
[ 129.792680] R13: R14: R15:
[ 129.799822] FS: 7f39f74b1a80() GS:88840f68()
knlGS:
[ 129.807913] CS: 0010 DS: ES: CR0: 80050033
[ 129.813670] CR2: 0560 CR3: 000138b88000 CR4: 00750ee0
[ 129.820815] PKRU: 5554
[ 129.823551] Call Trace:
[ 129.826022]
[ 129.828154] ? show_regs+0x65/0x70
[ 129.831599] ? __die+0x24/0x70
[ 129.834683] ? page_fault_oops+0x160/0x480
[ 129.838824] ? dev_printk_emit+0x83/0xb0
[ 129.842797] ? do_user_addr_fault+0x2e2/0x680
[ 129.847175] ? exc_page_fault+0x78/0x180
[ 129.851143] ? asm_exc_page_fault+0x27/0x30
[ 129.855353] ? drm_dp_mst_topology_put_port+0x19/0x170 [drm_display_helper]
[ 129.862354] drm_dp_add_payload_part1+0x85/0x100 [drm_display_helper]
[ 129.868832] intel_mst_pre_enable_dp+0x1ef/0x240 [i915]
[ 129.874170] intel_encoders_pre_enable+0x83/0xa0 [i915]
[ 129.879524] hsw_crtc_enable+0xbe/0x750 [i915]
[ 129.884095] intel_enable_crtc+0x68/0xa0 [i915]
[ 129.888752] skl_commit_modeset_enables+0x2c4/0x5d0 [i915]
[ 129.894365] intel_atomic_commit_tail+0x765/0x1070 [i915]
[ 129.899885] intel_atomic_commit+0x3ba/0x400 [i915]
[ 129.904892] drm_atomic_commit+0x96/0xd0 [drm]
[ 129.909405] ? __pfx___drm_printfn_info+0x10/0x10 [drm]
[ 129.914698] drm_atomic_helper_set_config+0x7e/0xc0 [drm_kms_helper]
[ 129.921102] drm_mode_setcrtc+0x5af/0x8d0 [drm]
[ 129.925695] ? __pfx_drm_mode_setcrtc+0x10/0x10 [drm]
[ 129.930810] drm_ioctl_kernel+0xc4/0x170 [drm]
[ 129.935317] drm_ioctl+0x2a4/0x520 [drm]
[ 129.939305] ? __pfx_drm_mode_setcrtc+0x10/0x10 [drm]
[ 129.944415] ? __fget_light+0xa5/0x110
[ 129.948212] __x64_sys_ioctl+0x98/0xd0
[ 129.951985] do_syscall_64+0x37/0x90
[ 129.955581] entry_SYSCALL_64_after_hwframe+0x6e/0xd8
Fixes: 5aa1dfcdf0a4 ("drm/mst: Refactor the flow for payload
allocation/removement")
Cc: Wayne Lin
Cc: Lyude Paul
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index e04f87ff755ac..5f90860d49c34 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -3341,7 +3341,8 @@ int drm_dp_add_payload_part1(struct
drm_dp_mst_topology_mgr *mgr,
(!allocate || ret < 0) ? DRM_DP_MST_PAYLOAD_ALLOCATION_LOCAL :
DRM_DP_MST_PAYLOAD_ALLOCATION_DFP;
- drm_dp_mst_topology_put_port(port);
+ if (port)
+ drm_dp_mst_topology_put_port(port);
return ret;
}
--
2.37.2
Re: [Intel-gfx] [PATCH v1 1/1] drm/i915/pxp: Add drm_dbgs for critical PXP events.
On Mon, 2023-09-11 at 12:26 +0300, Jani Nikula wrote: > On Wed, 06 Sep 2023, Alan Previn wrote: > > Debugging PXP issues can't even begin without understanding precedding > > sequence of events. Add drm_dbg into the most important PXP events. > > > > Signed-off-by: Alan Previn alan:snip > > > + > > + drm_dbg(>ctrl_gt->i915->drm, "PXP: %s invoked", __func__); > > drm_dbg already covers __func__ (via __builtin_return_address(0) in > __drm_dev_dbg), it's redundant. > > Ditto for all added debugs below. My bad - yup - will fix them. Thanks for taking time to review this patch. ...alan >
[Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123 (rev2)
== Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 (rev2) URL : https://patchwork.freedesktop.org/series/123605/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13626 -> Patchwork_123605v2 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_123605v2 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_123605v2, please notify your bug team (lgci.bug.fil...@intel.com) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123605v2/index.html Participating hosts (40 -> 39) -- Additional (2): fi-kbl-soraka fi-pnv-d510 Missing(3): bat-dg2-8 fi-snb-2520m fi-hsw-4770 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_123605v2: ### IGT changes ### Possible regressions * igt@gem_render_linear_blits@basic: - fi-rkl-11600: [PASS][1] -> [FAIL][2] +3 other tests fail [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/fi-rkl-11600/igt@gem_render_linear_bl...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123605v2/fi-rkl-11600/igt@gem_render_linear_bl...@basic.html - bat-adls-5: [PASS][3] -> [FAIL][4] +2 other tests fail [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/bat-adls-5/igt@gem_render_linear_bl...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123605v2/bat-adls-5/igt@gem_render_linear_bl...@basic.html - bat-dg1-5: [PASS][5] -> [FAIL][6] +1 other test fail [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/bat-dg1-5/igt@gem_render_linear_bl...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123605v2/bat-dg1-5/igt@gem_render_linear_bl...@basic.html - bat-mtlp-6: [PASS][7] -> [FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/bat-mtlp-6/igt@gem_render_linear_bl...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123605v2/bat-mtlp-6/igt@gem_render_linear_bl...@basic.html * igt@gem_render_tiled_blits@basic: - bat-adlp-9: [PASS][9] -> [FAIL][10] +3 other tests fail [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/bat-adlp-9/igt@gem_render_tiled_bl...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123605v2/bat-adlp-9/igt@gem_render_tiled_bl...@basic.html - bat-rplp-1: [PASS][11] -> [FAIL][12] +3 other tests fail [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/bat-rplp-1/igt@gem_render_tiled_bl...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123605v2/bat-rplp-1/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-adlm-1: [PASS][13] -> [FAIL][14] +2 other tests fail [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/bat-adlm-1/igt@gem_tiled_bl...@basic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123605v2/bat-adlm-1/igt@gem_tiled_bl...@basic.html - fi-tgl-1115g4: [PASS][15] -> [FAIL][16] +3 other tests fail [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/fi-tgl-1115g4/igt@gem_tiled_bl...@basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123605v2/fi-tgl-1115g4/igt@gem_tiled_bl...@basic.html - bat-rpls-1: [PASS][17] -> [FAIL][18] +2 other tests fail [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/bat-rpls-1/igt@gem_tiled_bl...@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123605v2/bat-rpls-1/igt@gem_tiled_bl...@basic.html * igt@kms_frontbuffer_tracking@basic: - bat-adlp-11:[PASS][19] -> [FAIL][20] +3 other tests fail [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/bat-adlp-11/igt@kms_frontbuffer_track...@basic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123605v2/bat-adlp-11/igt@kms_frontbuffer_track...@basic.html - bat-adln-1: [PASS][21] -> [FAIL][22] +3 other tests fail [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/bat-adln-1/igt@kms_frontbuffer_track...@basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123605v2/bat-adln-1/igt@kms_frontbuffer_track...@basic.html - bat-mtlp-8: [PASS][23] -> [FAIL][24] +1 other test fail [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/bat-mtlp-8/igt@kms_frontbuffer_track...@basic.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123605v2/bat-mtlp-8/igt@kms_frontbuffer_track...@basic.html - bat-adlp-6: [PASS][25] -> [FAIL][26] +3 other tests fail [25]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Apply Wa_16018031267 / Wa_16018063123 (rev2)
== Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 (rev2) URL : https://patchwork.freedesktop.org/series/123605/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply Wa_16018031267 / Wa_16018063123 (rev2)
== Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 (rev2) URL : https://patchwork.freedesktop.org/series/123605/ State : warning == Summary == Error: dim checkpatch failed 9dc317b700fb drm/i915: Reserve some kernel space per vm -:31: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #31: FILE: drivers/gpu/drm/i915/gt/gen8_ppgtt.c:1018: + GEM_BUG_ON(drm_mm_reserve_node(>vm.mm, >vm.rsvd)); total: 0 errors, 1 warnings, 0 checks, 26 lines checked 6f8cd00f23a5 drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 -:10: WARNING:BAD_SIGN_OFF: Co-developed-by and Signed-off-by: name/email do not match #10: Co-developed-by: Nirmoy Das Signed-off-by: Jonathan Cavitt -:35: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine' - possible side-effects? #35: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:86: +#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \ + IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 55), IP_VER(12, 71)) && \ + engine->class == COPY_ENGINE_CLASS) -:35: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'engine' may be better as '(engine)' to avoid precedence issues #35: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:86: +#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \ + IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 55), IP_VER(12, 71)) && \ + engine->class == COPY_ENGINE_CLASS) -:68: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #68: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:836: + GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1); -:184: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #184: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:1462: + GEM_BUG_ON(cs - start > I915_GTT_PAGE_SIZE / sizeof(*cs)); total: 0 errors, 3 warnings, 2 checks, 317 lines checked da5b30cc5620 drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123
[Intel-gfx] ✓ Fi.CI.BAT: success for Update GGTT with MI_UPDATE_GTT on MTL (rev4)
== Series Details == Series: Update GGTT with MI_UPDATE_GTT on MTL (rev4) URL : https://patchwork.freedesktop.org/series/123329/ State : success == Summary == CI Bug Log - changes from CI_DRM_13626 -> Patchwork_123329v4 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/index.html Participating hosts (40 -> 39) -- Additional (1): fi-pnv-d510 Missing(2): bat-dg2-8 fi-snb-2520m Known issues Here are the changes found in Patchwork_123329v4 that come from known issues: ### IGT changes ### Issues hit * igt@core_auth@basic-auth: - fi-apl-guc: NOTRUN -> [DMESG-WARN][1] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/fi-apl-guc/igt@core_a...@basic-auth.html * igt@gem_exec_suspend@basic-s0@lmem0: - bat-dg2-9: NOTRUN -> [INCOMPLETE][2] ([i915#8797] / [i915#9275]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html * igt@gem_lmem_swapping@basic: - fi-apl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/fi-apl-guc/igt@gem_lmem_swapp...@basic.html * igt@i915_pm_rps@basic-api: - bat-dg2-9: NOTRUN -> [SKIP][4] ([i915#6621]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/bat-dg2-9/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271]) +11 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-9: NOTRUN -> [SKIP][6] ([fdo#109285]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/bat-dg2-9/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-9: NOTRUN -> [SKIP][7] ([i915#5274]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/bat-dg2-9/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_frontbuffer_tracking@basic: - fi-bsw-nick:[PASS][8] -> [FAIL][9] ([i915#9276]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/fi-bsw-nick/igt@kms_frontbuffer_track...@basic.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/fi-bsw-nick/igt@kms_frontbuffer_track...@basic.html * igt@kms_hdmi_inject@inject-audio: - fi-apl-guc: NOTRUN -> [SKIP][10] ([fdo#109271]) +15 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/fi-apl-guc/igt@kms_hdmi_inj...@inject-audio.html * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1: - fi-hsw-4770:NOTRUN -> [DMESG-WARN][11] ([i915#8841]) +6 other tests dmesg-warn [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-vga-1.html * igt@kms_psr@primary_page_flip: - fi-pnv-d510:NOTRUN -> [SKIP][12] ([fdo#109271]) +30 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/fi-pnv-d510/igt@kms_psr@primary_page_flip.html * igt@kms_psr@sprite_plane_onoff: - bat-dg2-9: NOTRUN -> [SKIP][13] ([i915#1072]) +3 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/bat-dg2-9/igt@kms_psr@sprite_plane_onoff.html - fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1072]) +3 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg2-9: NOTRUN -> [SKIP][15] ([i915#3555]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/bat-dg2-9/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - bat-dg2-9: NOTRUN -> [SKIP][16] ([i915#3708]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/bat-dg2-9/igt@prime_v...@basic-fence-flip.html * igt@prime_vgem@basic-fence-mmap: - bat-dg2-9: NOTRUN -> [SKIP][17] ([i915#3708] / [i915#4077]) +1 other test skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/bat-dg2-9/igt@prime_v...@basic-fence-mmap.html * igt@prime_vgem@basic-write: - bat-dg2-9: NOTRUN -> [SKIP][18] ([i915#3291] / [i915#3708]) +2 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123329v4/bat-dg2-9/igt@prime_v...@basic-write.html Possible fixes * igt@kms_hdmi_inject@inject-audio: - fi-kbl-guc: [FAIL][19] ([IGT#3] /
Re: [Intel-gfx] [PATCH] i915/pmu: Move execlist stats initialization to execlist specific setup
I went up the call stack to ensure the differences between the
old and new location isnt skipping over other functions that may reference
something engine related (that may also end up triggering stats variabls).
Without digging further, i see the old postion here:
i915_driver_probe -> i915_driver_mmio_probe -> intel_gt_init_mmio ->
intel_engines_init_mmio -> intel_engine_setup
new postion here:
i915_driver_probe -> i915_gem_init -> (for_each_gt) intel_gt_init ->
intel_engines_init -> setup (intel_execlists_submission_setup)
And between i915_driver_mmio_probe and i915_gem_init are only mem/ggtt, display
and irq related init functions.
That said, LGTM (although you do need to address the BAT failure before
merging):
Reviewed-by: Alan Previn
On Tue, 2023-09-12 at 14:22 -0700, Umesh Nerlige Ramappa wrote:
> engine->stats is a union of execlist and guc stat objects. When execlist
> specific fields are initialized, the initial state of guc stats is
> affected. This results in bad busyness values when using GuC mode. Move
> the execlist initialization from common code to execlist specific code.
>
> Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
> pmu")
> Signed-off-by: Umesh Nerlige Ramappa
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c| 1 -
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 ++
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index dfb69fc977a0..84a75c95f3f7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -558,7 +558,6 @@ static int intel_engine_setup(struct intel_gt *gt, enum
> intel_engine_id id,
> DRIVER_CAPS(i915)->has_logical_contexts = true;
>
> ewma__engine_latency_init(>latency);
> - seqcount_init(>stats.execlists.lock);
>
> ATOMIC_INIT_NOTIFIER_HEAD(>context_status_notifier);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 4d05321dc5b5..e8f42ec6b1b4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -3548,6 +3548,8 @@ int intel_execlists_submission_setup(struct
> intel_engine_cs *engine)
> logical_ring_default_vfuncs(engine);
> logical_ring_default_irqs(engine);
>
> + seqcount_init(>stats.execlists.lock);
> +
> if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
> rcs_submission_override(engine);
>
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Update GGTT with MI_UPDATE_GTT on MTL (rev4)
== Series Details == Series: Update GGTT with MI_UPDATE_GTT on MTL (rev4) URL : https://patchwork.freedesktop.org/series/123329/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Update GGTT with MI_UPDATE_GTT on MTL (rev4)
== Series Details == Series: Update GGTT with MI_UPDATE_GTT on MTL (rev4) URL : https://patchwork.freedesktop.org/series/123329/ State : warning == Summary == Error: dim checkpatch failed 83371cb18c6e drm/i915: Lift runtime-pm acquire callbacks out of intel_wakeref.mutex -:57: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #57: FILE: drivers/gpu/drm/i915/intel_wakeref.c:27: + INTEL_WAKEREF_BUG_ON(wf->wakeref); -:73: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #73: FILE: drivers/gpu/drm/i915/intel_wakeref.c:40: + INTEL_WAKEREF_BUG_ON(atomic_read(>count) <= 0); -:96: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #96: FILE: drivers/gpu/drm/i915/intel_wakeref.c:60: + INTEL_WAKEREF_BUG_ON(!wf->wakeref); total: 0 errors, 3 warnings, 0 checks, 83 lines checked e909fdff0fa3 drm/i915: Create a kernel context for GGTT updates 4289fdd7ebb7 drm/i915: Implement for_each_sgt_daddr_next -:39: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__iter' - possible side-effects? #39: FILE: drivers/gpu/drm/i915/i915_scatterlist.h:100: +#define __for_each_daddr_next(__dp, __iter, __step) \ + for (; ((__dp) = (__iter).dma + (__iter).curr), (__iter).sgp; \ +(((__iter).curr += (__step)) >= (__iter).max) ?\ +(__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0) total: 0 errors, 0 warnings, 1 checks, 25 lines checked e2daed682032 drm/i915: Parameterize binder context creation 69c6942db204 drm/i915: Implement GGTT update method with MI_UPDATE_GTT -:68: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #68: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:276: + GEM_BUG_ON(!ce); -:238: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #238: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:491: + if (!gen8_ggtt_bind_ptes(ggtt, start, vma_res->bi.pages, + vma_res->node_size / I915_GTT_PAGE_SIZE, pte_encode)) -:286: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #286: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:553: + if (should_update_ggtt_with_bind(ggtt) && gen8_ggtt_bind_ptes(ggtt, first_entry, +NULL, num_entries, scratch_pte)) total: 0 errors, 1 warnings, 2 checks, 283 lines checked 60cb703f3d93 drm/i915: Toggle binder context ready status 255c6efee818 drm/i915: Enable GGTT updates with binder in MTL
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: prepare for xe driver display integration (rev2)
== Series Details ==
Series: drm/i915: prepare for xe driver display integration (rev2)
URL : https://patchwork.freedesktop.org/series/123595/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13626 -> Patchwork_123595v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/index.html
Participating hosts (40 -> 39)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_123595v2 that come from known issues:
### CI changes ###
Issues hit
* boot:
- fi-hsw-4770:[PASS][1] -> [FAIL][2] ([i915#8293])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/fi-hsw-4770/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/fi-hsw-4770/boot.html
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3
other tests skip
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/fi-apl-guc/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@reset:
- fi-apl-guc: NOTRUN -> [DMESG-WARN][4] ([i915#7634]) +32 other
tests dmesg-warn
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/fi-apl-guc/igt@i915_selftest@l...@reset.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-apl-guc: NOTRUN -> [DMESG-WARN][5] ([i915#180] / [i915#7634])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/fi-apl-guc/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_frontbuffer_tracking@basic:
- fi-bsw-nick:[PASS][6] -> [FAIL][7] ([i915#9276])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/fi-bsw-nick/igt@kms_frontbuffer_track...@basic.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/fi-bsw-nick/igt@kms_frontbuffer_track...@basic.html
* igt@kms_hdmi_inject@inject-audio:
- fi-apl-guc: NOTRUN -> [SKIP][8] ([fdo#109271]) +16 other tests
skip
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/fi-apl-guc/igt@kms_hdmi_inj...@inject-audio.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [PASS][9] -> [ABORT][10] ([i915#8668])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html
Possible fixes
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [FAIL][11] ([IGT#3] / [i915#6121]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123595v2/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#7634]: https://gitlab.freedesktop.org/drm/intel/issues/7634
[i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#9273]: https://gitlab.freedesktop.org/drm/intel/issues/9273
[i915#9276]: https://gitlab.freedesktop.org/drm/intel/issues/9276
[i915#9279]: https://gitlab.freedesktop.org/drm/intel/issues/9279
Build changes
-
* Linux: CI_DRM_13626 -> Patchwork_123595v2
CI-20190529: 20190529
CI_DRM_13626: d5838c603de7b95ea299cbf7ff87228496bc86b2 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7486: afd9a940c8247291baadd1977fe881d4f2edf0c7 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_123595v2: d5838c603de7b95ea299cbf7ff87228496bc86b2 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
eefa4a38c197 drm/i915/display: add I915 conditional build to vlv_dsi_pll.h
ba340b8b1992 drm/i915/display: add I915 conditional build to intel_tv.h
6a853e356ceb drm/i915/display: add I915 conditional build to intel_sdvo.h
ada956088dae drm/i915/display: add I915 conditional build to intel_dvo.h
5792becebf7a drm/i915/display: add I915 conditional build to g4x_hdmi.h
41d922d0d6d0 drm/i915/display: add I915 conditional build to i9xx_wm.h
3e8f337e1a9c drm/i915/display: add I915 conditional
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: prepare for xe driver display integration (rev2)
== Series Details == Series: drm/i915: prepare for xe driver display integration (rev2) URL : https://patchwork.freedesktop.org/series/123595/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: prepare for xe driver display integration (rev2)
== Series Details == Series: drm/i915: prepare for xe driver display integration (rev2) URL : https://patchwork.freedesktop.org/series/123595/ State : warning == Summary == Error: dim checkpatch failed 1b12af564c06 drm/i915: define I915 during i915 driver build 6acbd52df16f drm/i915/display: add I915 conditional build to intel_lvds.h -:30: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #30: FILE: drivers/gpu/drm/i915/display/intel_lvds.h:28: +} +static inline void intel_lvds_init(struct drm_i915_private *dev_priv) -:33: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #33: FILE: drivers/gpu/drm/i915/display/intel_lvds.h:31: +} +static inline struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv) -:37: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #37: FILE: drivers/gpu/drm/i915/display/intel_lvds.h:35: +} +static inline bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv) total: 0 errors, 0 warnings, 3 checks, 29 lines checked ecf3ba1f7f3c drm/i915/display: add I915 conditional build to hsw_ips.h -:31: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #31: FILE: drivers/gpu/drm/i915/display/hsw_ips.h:32: +} +static inline bool hsw_ips_pre_update(struct intel_atomic_state *state, -:36: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #36: FILE: drivers/gpu/drm/i915/display/hsw_ips.h:37: +} +static inline void hsw_ips_post_update(struct intel_atomic_state *state, -:40: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #40: FILE: drivers/gpu/drm/i915/display/hsw_ips.h:41: +} +static inline bool hsw_crtc_supports_ips(struct intel_crtc *crtc) -:44: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #44: FILE: drivers/gpu/drm/i915/display/hsw_ips.h:45: +} +static inline bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) -:48: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #48: FILE: drivers/gpu/drm/i915/display/hsw_ips.h:49: +} +static inline int hsw_ips_compute_config(struct intel_atomic_state *state, -:53: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #53: FILE: drivers/gpu/drm/i915/display/hsw_ips.h:54: +} +static inline void hsw_ips_get_config(struct intel_crtc_state *crtc_state) -:56: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #56: FILE: drivers/gpu/drm/i915/display/hsw_ips.h:57: +} +static inline void hsw_ips_crtc_debugfs_add(struct intel_crtc *crtc) total: 0 errors, 0 warnings, 7 checks, 46 lines checked a389119da8a1 drm/i915/display: add I915 conditional build to i9xx_plane.h -:33: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #33: FILE: drivers/gpu/drm/i915/display/i9xx_plane.h:36: +} +static inline int i9xx_check_plane_surface(struct intel_plane_state *plane_state) -:37: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #37: FILE: drivers/gpu/drm/i915/display/i9xx_plane.h:40: +} +static inline struct intel_plane * -:42: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #42: FILE: drivers/gpu/drm/i915/display/i9xx_plane.h:45: +} +static inline void i9xx_get_initial_plane_config(struct intel_crtc *crtc, total: 0 errors, 0 warnings, 3 checks, 33 lines checked 40c419b0967e drm/i915/display: add I915 conditional build to intel_lpe_audio.h -:31: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #31: FILE: drivers/gpu/drm/i915/display/intel_lpe_audio.h:27: +} +static inline void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv) -:34: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #34: FILE: drivers/gpu/drm/i915/display/intel_lpe_audio.h:30: +} +static inline void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv) -:37: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #37: FILE: drivers/gpu/drm/i915/display/intel_lpe_audio.h:33: +} +static inline void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, total: 0 errors, 0 warnings, 3 checks, 29 lines checked 67d8d4926626 drm/i915/display: add I915 conditional build to intel_pch_refclk.h -:31: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #31: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.h:26: +} +static inline void lpt_disable_iclkip(struct drm_i915_private *dev_priv) -:34: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #34: FILE: drivers/gpu/drm/i915/display/intel_pch_refclk.h:29:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Prevent error pointer dereference (rev2)
== Series Details ==
Series: drm/i915/gt: Prevent error pointer dereference (rev2)
URL : https://patchwork.freedesktop.org/series/123628/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13626 -> Patchwork_123628v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v2/index.html
Participating hosts (40 -> 40)
--
Additional (1): fi-pnv-d510
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_123628v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3
other tests skip
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v2/fi-apl-guc/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: NOTRUN -> [DMESG-FAIL][2] ([i915#5334])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271]) +12 other tests
skip
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v2/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_frontbuffer_tracking@basic:
- fi-bsw-nick:[PASS][4] -> [FAIL][5] ([i915#9276])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13626/fi-bsw-nick/igt@kms_frontbuffer_track...@basic.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v2/fi-bsw-nick/igt@kms_frontbuffer_track...@basic.html
* igt@kms_hdmi_inject@inject-audio:
- fi-apl-guc: NOTRUN -> [SKIP][6] ([fdo#109271]) +16 other tests
skip
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v2/fi-apl-guc/igt@kms_hdmi_inj...@inject-audio.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-adlp-9: NOTRUN -> [SKIP][7] ([i915#3546]) +2 other tests skip
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v2/bat-adlp-9/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1:
- fi-hsw-4770:NOTRUN -> [DMESG-WARN][8] ([i915#8841]) +6 other
tests dmesg-warn
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v2/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-vga-1.html
* igt@kms_psr@primary_page_flip:
- fi-pnv-d510:NOTRUN -> [SKIP][9] ([fdo#109271]) +31 other tests
skip
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v2/fi-pnv-d510/igt@kms_psr@primary_page_flip.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1072]) +3
other tests skip
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v2/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#9273]: https://gitlab.freedesktop.org/drm/intel/issues/9273
[i915#9276]: https://gitlab.freedesktop.org/drm/intel/issues/9276
[i915#9279]: https://gitlab.freedesktop.org/drm/intel/issues/9279
Build changes
-
* Linux: CI_DRM_13626 -> Patchwork_123628v2
CI-20190529: 20190529
CI_DRM_13626: d5838c603de7b95ea299cbf7ff87228496bc86b2 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7486: afd9a940c8247291baadd1977fe881d4f2edf0c7 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_123628v2: d5838c603de7b95ea299cbf7ff87228496bc86b2 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
ec409b4962bb drm/i915/gt: Prevent error pointer dereference
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v2/index.html
Re: [Intel-gfx] [PATCH v2 18/19] drm/i915/dsb: Re-instate DSB for LUT updates
> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, June 7, 2023 12:45 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v2 18/19] drm/i915/dsb: Re-instate DSB for LUT > updates > > From: Ville Syrjälä > > With all the known issues sorted out we can start to use DSB to load the LUTs. Reviewed-by: Uma Shankar > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_color.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c > b/drivers/gpu/drm/i915/display/intel_color.c > index c5a9ea53a718..213063872f26 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -1814,9 +1814,6 @@ void intel_color_prepare_commit(struct > intel_crtc_state *crtc_state) > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > struct drm_i915_private *i915 = to_i915(crtc->base.dev); > > - /* FIXME DSB has issues loading LUTs, disable it for now */ > - return; > - > if (!crtc_state->hw.active || > intel_crtc_needs_modeset(crtc_state)) > return; > -- > 2.39.3
Re: [Intel-gfx] [PATCH v2 17/19] drm/i915/dsb: Use DEwake to combat PkgC latency
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, June 7, 2023 12:45 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 17/19] drm/i915/dsb: Use DEwake to combat PkgC
> latency
>
> From: Ville Syrjälä
>
> Normally we could be in a deep PkgC state all the way up to the point when DSB
> starts its execution at the transcoders undelayed vblank. The DSB will then
> have
> to wait for the hardware to wake up before it can execute anything. This will
> waste a huge chunk of the vblank time just waiting, and risks the DSB
> execution
> spilling into the vertical active period. That will be very bad, especially
> when
> programming the LUTs as the anti-collision logic will cause DSB to corrupt LUT
> writes during vertical active.
>
> To avoid these problems we can instruct the DSB to pre-wake the display
> engined
> on a specific scanline so that everything will be 100% ready to go when we
> hit the
> transcoder's undelayed vblank.
>
> One annoyance is that the scanline is specified as just that, a single
> scanline. So if
> we happen to start the DSB execution after passing said scanline no DEwake
> will
> happen and we may drop back into some PkgC state before reaching the
> transcoder's undelayed vblank. To prevent that we'll use the "force DEwake"
> bit
> to manually force the display engined to stay awake. We'll then have to clear
> the
Nit: Typo in engine
> force bit again after the DSB is done (the force bit remains effective even
> when
> the DSB is otherwise disabled).
Approach looks good, this will help hardware be ready and maximize the chance of
update within the vblank.
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dsb.c | 91 +++---
> drivers/gpu/drm/i915/display/intel_dsb.h | 3 +-
> 3 files changed, 82 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index b3dd4013d058..c5a9ea53a718 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1824,7 +1824,7 @@ void intel_color_prepare_commit(struct
> intel_crtc_state *crtc_state)
> if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
> return;
>
> - crtc_state->dsb = intel_dsb_prepare(crtc, 1024);
> + crtc_state->dsb = intel_dsb_prepare(crtc_state, 1024);
> if (!crtc_state->dsb)
> return;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 73d609507f24..3e32aa49b8eb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -7,11 +7,16 @@
> #include "gem/i915_gem_internal.h"
>
> #include "i915_drv.h"
> +#include "i915_irq.h"
> #include "i915_reg.h"
> +#include "intel_crtc.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_dsb.h"
> #include "intel_dsb_regs.h"
> +#include "intel_vblank.h"
> +#include "intel_vrr.h"
> +#include "skl_watermark.h"
>
> struct i915_vma;
>
> @@ -47,6 +52,8 @@ struct intel_dsb {
>* register.
>*/
> unsigned int ins_start_offset;
> +
> + int dewake_scanline;
> };
>
> /**
> @@ -297,17 +304,40 @@ static void intel_dsb_align_tail(struct intel_dsb *dsb)
>
> void intel_dsb_finish(struct intel_dsb *dsb) {
> + struct intel_crtc *crtc = dsb->crtc;
> +
> + /*
> + * DSB_FORCE_DEWAKE remains active even after DSB is
> + * disabled, so make sure to clear it (if set during
> + * intel_dsb_commit()).
> + */
> + intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(crtc->pipe, dsb->id),
> +DSB_FORCE_DEWAKE, 0);
We should also keep DSB_BLOCK_DEWAKE_EXTENSION set to 1, the default .
With this fixed or clarified, this is:
Reviewed-by: Uma Shankar
> intel_dsb_align_tail(dsb);
> }
>
> -/**
> - * intel_dsb_commit() - Trigger workload execution of DSB.
> - * @dsb: DSB context
> - * @wait_for_vblank: wait for vblank before executing
> - *
> - * This function is used to do actual write to hardware using DSB.
> - */
> -void intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank)
> +static int intel_dsb_dewake_scanline(const struct intel_crtc_state
> +*crtc_state) {
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + const struct drm_display_mode *adjusted_mode = _state-
> >hw.adjusted_mode;
> + unsigned int latency = skl_watermark_max_latency(i915);
> + int vblank_start;
> +
> + if (crtc_state->vrr.enable) {
> + vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> + } else {
> + vblank_start = adjusted_mode->crtc_vblank_start;
> +
> + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> + vblank_start
Re: [Intel-gfx] [PATCH v2 16/19] drm/i915: Introudce intel_crtc_scanline_to_hw()
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, June 7, 2023 12:45 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 16/19] drm/i915: Introudce
> intel_crtc_scanline_to_hw()
Typo in introduce
With this fixed, this is:
Reviewed-by: Uma Shankar
> From: Ville Syrjälä
>
> Add a helper to convert our idea of a scanline to the hw's idea of the same
> scanline (ie. apply crtc->scanline_offset in reverse).
> We'll need this to tell the DSB do stuff on a specific scanline.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_vblank.c | 14 ++
> drivers/gpu/drm/i915/display/intel_vblank.h | 1 +
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c
> b/drivers/gpu/drm/i915/display/intel_vblank.c
> index f5659ebd08eb..2cec2abf9746 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -251,6 +251,20 @@ static int __intel_get_crtc_scanline(struct intel_crtc
> *crtc)
> return (position + crtc->scanline_offset) % vtotal; }
>
> +int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline) {
> + const struct drm_vblank_crtc *vblank =
> + >base.dev->vblank[drm_crtc_index(>base)];
> + const struct drm_display_mode *mode = >hwmode;
> + int vtotal;
> +
> + vtotal = mode->crtc_vtotal;
> + if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> + vtotal /= 2;
> +
> + return (scanline + vtotal - crtc->scanline_offset) % vtotal; }
> +
> static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
>bool in_vblank_irq,
>int *vpos, int *hpos,
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h
> b/drivers/gpu/drm/i915/display/intel_vblank.h
> index 08e706b29149..17636f140c71 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.h
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.h
> @@ -22,5 +22,6 @@ void intel_wait_for_pipe_scanline_stopped(struct intel_crtc
> *crtc); void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc);
> void
> intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
> bool vrr_enable);
> +int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline);
>
> #endif /* __INTEL_VBLANK_H__ */
> --
> 2.39.3
Re: [Intel-gfx] [PATCH v2 15/19] drm/i915: Introduce skl_watermark_max_latency()
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, June 7, 2023 12:45 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 15/19] drm/i915: Introduce
> skl_watermark_max_latency()
>
> From: Ville Syrjälä
>
> The DSB code will want to know the maximum PkgC latency it has to contend
> with. Add a helper to expose that information.
Looks Good to me.
Reviewed-by: Uma Shankar
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 14 ++
> drivers/gpu/drm/i915/display/skl_watermark.h | 2 ++
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index d1245c847f1c..a31adbca9dbc 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3719,3 +3719,17 @@ void skl_watermark_debugfs_register(struct
> drm_i915_private *i915)
> debugfs_create_file("i915_sagv_status", 0444, minor-
> >debugfs_root, i915,
> _sagv_status_fops);
> }
> +
> +unsigned int skl_watermark_max_latency(struct drm_i915_private *i915) {
> + int level;
> +
> + for (level = i915->display.wm.num_levels - 1; level >= 0; level--) {
> + unsigned int latency = skl_wm_latency(i915, level, NULL);
> +
> + if (latency)
> + return latency;
> + }
> +
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h
> b/drivers/gpu/drm/i915/display/skl_watermark.h
> index f91a3d4ddc07..edb61e33df83 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.h
> @@ -46,6 +46,8 @@ void skl_watermark_ipc_update(struct drm_i915_private
> *i915); bool skl_watermark_ipc_enabled(struct drm_i915_private *i915); void
> skl_watermark_debugfs_register(struct drm_i915_private *i915);
>
> +unsigned int skl_watermark_max_latency(struct drm_i915_private *i915);
> +
> void skl_wm_init(struct drm_i915_private *i915);
>
> struct intel_dbuf_state {
> --
> 2.39.3
Re: [Intel-gfx] [PATCH v2 14/19] drm/i915/dsb: Evade transcoder undelayed vblank when using DSB
> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, June 7, 2023 12:45 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v2 14/19] drm/i915/dsb: Evade transcoder undelayed > vblank when using DSB > > From: Ville Syrjälä > > We want to start the DSB execution from the transcoder's undelayed vblank, so > in > order to guarantee atomicity with the all the other mmio register writes we > need > to evade both vblanks. > > Note that currently we don't add any vblank delay, so this is effectively a > nop. But > in the future when we start to program double buffered registers from the DSB > we'll need to delay the pipe's vblank to provide the register programming > "window2" > for the DSB. Agree with this, looks good. Reviewed-by: Uma Shankar > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_crtc.c | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c > b/drivers/gpu/drm/i915/display/intel_crtc.c > index 36c9b590a058..ff0ebdf7cde3 100644 > --- a/drivers/gpu/drm/i915/display/intel_crtc.c > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c > @@ -519,8 +519,12 @@ void intel_pipe_update_start(struct intel_crtc_state > *new_crtc_state) > /* >* M/N is double buffered on the transcoder's undelayed vblank, >* so with seamless M/N we must evade both vblanks. > + * > + * DSB execution waits for the transcoder's undelayed vblank, > + * hence we must kick off the commit before that. >*/ > - if (new_crtc_state->seamless_m_n && > intel_crtc_needs_fastset(new_crtc_state)) > + if (new_crtc_state->dsb || > + (new_crtc_state->seamless_m_n && > +intel_crtc_needs_fastset(new_crtc_state))) > min -= adjusted_mode->crtc_vblank_start - adjusted_mode- > >crtc_vdisplay; > > if (min <= 0 || max <= 0) > -- > 2.39.3
Re: [Intel-gfx] [PATCH] drm/i915: Do not disable preemption for resets
On Wed, 13 Sept 2023 at 18:48, Sebastian Andrzej Siewior
wrote:
>
> On 2023-07-05 10:30:25 [+0100], Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > Commit ade8a0f59844 ("drm/i915: Make all GPU resets atomic") added a
> > preempt disable section over the hardware reset callback to prepare the
> > driver for being able to reset from atomic contexts.
> …
>
> This missed the v6.6 merge window. Has this been dropped for some reason
> or just missed by chance? Can this be still applied, please?
>
Just an FYI, but I happened to be looking at an internal bug report
for exactly this
error site, so +1 here :)
>
> Sebastian
>
Re: [Intel-gfx] [PATCH v2 13/19] drm/i915/dsb: Use non-posted register writes for legacy LUT
> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: Wednesday, June 7, 2023 12:45 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v2 13/19] drm/i915/dsb: Use non-posted register > writes for legacy LUT > > From: Ville Syrjälä > > The DSB has problems writing the legacy LUT. The two workarounds I've > discoverted are: > - write each entry twice back to back > - use non-posted writes > > Let's use non-posted writes as that seems a bit more standard. Change looks good but I feel it will be good to get this documented in spec. Not able to locate any reference. Anyways, with empirical data based on your findings no concern as such. Reviewed-by: Uma Shankar > TODO: measure which is faster > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_color.c | 11 +++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c > b/drivers/gpu/drm/i915/display/intel_color.c > index 077e45372dab..b3dd4013d058 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -1265,9 +1265,20 @@ static void ilk_load_lut_8(const struct > intel_crtc_state > *crtc_state, > > lut = blob->data; > > + /* > + * DSB fails to correctly load the legacy LUT > + * unless we either write each entry twice, > + * or use non-posted writes > + */ > + if (crtc_state->dsb) > + intel_dsb_nonpost_start(crtc_state->dsb); > + > for (i = 0; i < 256; i++) > ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i), > i9xx_lut_8([i])); > + > + if (crtc_state->dsb) > + intel_dsb_nonpost_end(crtc_state->dsb); > } > > static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state, > -- > 2.39.3
Re: [Intel-gfx] [PATCH 3/3] drm/i915/perf: Initialize gen12 OA buffer unconditionally
On Tue, 12 Sep 2023 18:46:12 -0700, Umesh Nerlige Ramappa wrote: > Hi Umesh, > On Fri, Sep 08, 2023 at 06:24:16PM -0700, Dixit, Ashutosh wrote: > > On Fri, 08 Sep 2023 18:16:26 -0700, Ashutosh Dixit wrote: > >> > > > >> From: Umesh Nerlige Ramappa > >> > >> Correct values for OAR counters are still dependent on enabling the > >> GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE in OAG_OACONTROL. Enabling this > >> bit means OAG unit will write reports to the OAG buffer, so > >> initialize the OAG buffer unconditionally for all use cases. > >> > >> BSpec: 46822 > >> > >> Signed-off-by: Umesh Nerlige Ramappa > >> Signed-off-by: Ashutosh Dixit > >> --- > >> drivers/gpu/drm/i915/i915_perf.c | 10 +- > >> 1 file changed, 5 insertions(+), 5 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_perf.c > >> b/drivers/gpu/drm/i915/i915_perf.c > >> index 1347e4ec9dd5a..30cf37d6e79be 100644 > >> --- a/drivers/gpu/drm/i915/i915_perf.c > >> +++ b/drivers/gpu/drm/i915/i915_perf.c > >> @@ -3032,12 +3032,12 @@ static void gen12_oa_enable(struct > >> i915_perf_stream *stream) > >>u32 val; > >> > >>/* > >> - * If we don't want OA reports from the OA buffer, then we don't even > >> - * need to program the OAG unit. > >> + * BSpec: 46822 > >> + * Correct values for OAR counters are still dependent on enabling the > >> + * GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE in OAG_OACONTROL. Enabling this > >> + * bit means OAG unit will write reports to the OAG buffer, so > >> + * initialize the OAG buffer correctly. > >> */ > >> - if (!(stream->sample_flags & SAMPLE_OA_REPORT)) > >> - return; > >> - > >>gen12_init_oa_buffer(stream); > >> > >>regs = __oa_regs(stream); > > > > Looks like this should be needed, I can R-b it. > > > > However, gen12_test_mi_rpc IGT says: > > > > /* OA unit configuration: > > * DRM_I915_PERF_PROP_SAMPLE_OA is no longer required for Gen12 > > * because the OAR unit increments counters only for the > > * relevant context. No other parameters are needed since we do > > * not rely on the OA buffer anymore to normalize the counter > > * values. > > */ > > That's wrong. When TGL support was added, this was misunderstood and I > removed the OAR-OAG dependency. Ideally we should enforce user to pass > SAMPLE_OA always, but now that will break uabi. SAMPLE_OA has other effects like enabling the timer etc. Also, if we enforce user to always pass it, we can do it in the kernel itself and ignore the uapi parameter. > > For for the OAR case, let's just enable OAG unconditionally so that the OAR > counters tick correctly. While we do that, we should disable all events > that trigger a report into the OA buffer. In addition, I would also > allocate the smallest OA buffer size for this case, so that memory impact > is low. > > Needs a Fixes tag with the commit that enabled OA for TGL. If you think this patch is needed, I think it's better you do this so that you can stay the patch author and I can be the reviewer, otherwise we'll need to go hunt for another reviewer. Thanks. -- Ashutosh > > > > So gen12_test_mi_rpc doesn't set DRM_I915_PERF_PROP_SAMPLE_OA and also > > seems to be passing in CI (don't see it but there seem to be no open > > bugs). Thoughts? > > > > Thanks. > > -- > > Ashutosh
Re: [Intel-gfx] [PATCH 7/7] drm/i915: Enable GGTT updates with binder in MTL
Reviewed-by: Oak Zeng
Thanks,
Oak
> -Original Message-
> From: Das, Nirmoy
> Sent: Wednesday, September 13, 2023 9:10 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Zeng, Oak ; chris.p.wil...@linux.intel.com;
> Piorkowski,
> Piotr ; Shyti, Andi ; Mun,
> Gwan-gyeong ; Roper, Matthew D
> ; Das, Nirmoy
> Subject: [PATCH 7/7] drm/i915: Enable GGTT updates with binder in MTL
>
> MTL can hang because of a HW bug while parallel reading/writing
> from/to LMEM/GTTMMADR BAR so try to reduce GGTT update
> related pci transactions with blitter command as recommended
> for Wa_13010847436 and Wa_14019519902.
>
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
> b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 4c89eb8d9af7..4fbed27ef0ec 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -23,7 +23,8 @@
>
> bool i915_ggtt_require_binder(struct drm_i915_private *i915)
> {
> - return false;
> + /* Wa_13010847436 & Wa_14019519902 */
> + return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
> }
>
> static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)
> --
> 2.41.0
Re: [Intel-gfx] [PATCH 4/7] drm/i915: Parameterize binder context creation
Reviewed-by: Oak Zeng
Thanks,
Oak
> -Original Message-
> From: Das, Nirmoy
> Sent: Wednesday, September 13, 2023 9:10 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Zeng, Oak ; chris.p.wil...@linux.intel.com;
> Piorkowski,
> Piotr ; Shyti, Andi ; Mun,
> Gwan-gyeong ; Roper, Matthew D
> ; Das, Nirmoy
> Subject: [PATCH 4/7] drm/i915: Parameterize binder context creation
>
> Add i915_ggtt_require_binder() to indicate that i915
> needs to create binder context which will be used
> by subsequent patch to enable i915_address_space vfuncs
> that will use GPU commands to update GGTT.
>
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gtt.c | 4
> drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++
> 3 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 52a24f55cb57..12af594e9164 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1478,7 +1478,7 @@ static int engine_init_common(struct intel_engine_cs
> *engine)
>* engines as well but BCS should be less busy engine so pick that for
>* GGTT updates.
>*/
> - if (engine->id == BCS0) {
> + if (i915_ggtt_require_binder(engine->i915) && engine->id == BCS0) {
> bce = create_ggtt_bind_context(engine);
> if (IS_ERR(bce))
> return PTR_ERR(bce);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
> b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 13944a14ea2d..4c89eb8d9af7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -21,6 +21,10 @@
> #include "intel_gt_regs.h"
> #include "intel_gtt.h"
>
> +bool i915_ggtt_require_binder(struct drm_i915_private *i915)
> +{
> + return false;
> +}
>
> static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)
> {
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
> b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index 41e530d0a4e9..b471edac2699 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -691,4 +691,6 @@ static inline struct sgt_dma {
> return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) };
> }
>
> +bool i915_ggtt_require_binder(struct drm_i915_private *i915);
> +
> #endif
> --
> 2.41.0
Re: [Intel-gfx] [PATCH 3/7] drm/i915: Implement for_each_sgt_daddr_next
Thanks,
Oak
> -Original Message-
> From: Das, Nirmoy
> Sent: Wednesday, September 13, 2023 9:10 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Zeng, Oak ; chris.p.wil...@linux.intel.com;
> Piorkowski,
> Piotr ; Shyti, Andi ; Mun,
> Gwan-gyeong ; Roper, Matthew D
> ; Das, Nirmoy
> Subject: [PATCH 3/7] drm/i915: Implement for_each_sgt_daddr_next
>
> Implement a way to iterate over sgt with pre-initialized
> sgt_iter state.
>
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++
> drivers/gpu/drm/i915/i915_scatterlist.h | 10 ++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
> b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index 346ec8ec2edd..41e530d0a4e9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -171,6 +171,9 @@ struct intel_gt;
> #define for_each_sgt_daddr(__dp, __iter, __sgt) \
> __for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE)
>
> +#define for_each_sgt_daddr_next(__dp, __iter) \
The naming of this macro... I feel _next is not a good name, but I couldn't
find a better name either...
The codes look good to me, so it is Reviewed-by: Oak Zeng
Oak
> + __for_each_daddr_next(__dp, __iter, I915_GTT_PAGE_SIZE)
> +
> struct i915_page_table {
> struct drm_i915_gem_object *base;
> union {
> diff --git a/drivers/gpu/drm/i915/i915_scatterlist.h
> b/drivers/gpu/drm/i915/i915_scatterlist.h
> index 5a10c1a31183..6cf8a298849f 100644
> --- a/drivers/gpu/drm/i915/i915_scatterlist.h
> +++ b/drivers/gpu/drm/i915/i915_scatterlist.h
> @@ -91,6 +91,16 @@ static inline struct scatterlist *__sg_next(struct
> scatterlist
> *sg)
>((__dp) = (__iter).dma + (__iter).curr), (__iter).sgp; \
>(((__iter).curr += (__step)) >= (__iter).max) ?\
>(__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
> +/**
> + * __for_each_daddr_next - iterates over the device addresses with pre-
> initialized iterator.
> + * @__dp:Device address (output)
> + * @__iter: 'struct sgt_iter' (iterator state, external)
> + * @__step: step size
> + */
> +#define __for_each_daddr_next(__dp, __iter, __step) \
> + for (; ((__dp) = (__iter).dma + (__iter).curr), (__iter).sgp; \
> + (((__iter).curr += (__step)) >= (__iter).max) ?\
> + (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
>
> /**
> * for_each_sgt_page - iterate over the pages of the given sg_table
> --
> 2.41.0
Re: [Intel-gfx] [PATCH 2/7] drm/i915: Create a kernel context for GGTT updates
Thanks,
Oak
> -Original Message-
> From: Das, Nirmoy
> Sent: Wednesday, September 13, 2023 9:10 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Zeng, Oak ; chris.p.wil...@linux.intel.com;
> Piorkowski,
> Piotr ; Shyti, Andi ; Mun,
> Gwan-gyeong ; Roper, Matthew D
> ; Das, Nirmoy
> Subject: [PATCH 2/7] drm/i915: Create a kernel context for GGTT updates
>
> Create a separate kernel context if a platform requires
> GGTT updates using MI_UPDATE_GTT blitter command.
>
> Subsequent patch will introduce methods to update
> GGTT using this bind context and MI_UPDATE_GTT blitter
> command.
>
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 2 ++
> drivers/gpu/drm/i915/gt/intel_engine_cs.c| 33 +++-
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 ++
> drivers/gpu/drm/i915/gt/intel_gt.c | 18 +++
> drivers/gpu/drm/i915/gt/intel_gt.h | 2 ++
> 5 files changed, 57 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> b/drivers/gpu/drm/i915/gt/intel_engine.h
> index b58c30ac8ef0..40269e4c1e31 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -170,6 +170,8 @@ intel_write_status_page(struct intel_engine_cs *engine,
> int reg, u32 value)
> #define I915_GEM_HWS_SEQNO 0x40
> #define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO
> * sizeof(u32))
> #define I915_GEM_HWS_MIGRATE (0x42 * sizeof(u32))
> +#define I915_GEM_HWS_GGTT_BIND 0x46
> +#define I915_GEM_HWS_GGTT_BIND_ADDR (I915_GEM_HWS_GGTT_BIND *
> sizeof(u32))
> #define I915_GEM_HWS_PXP 0x60
> #define I915_GEM_HWS_PXP_ADDR(I915_GEM_HWS_PXP *
> sizeof(u32))
> #define I915_GEM_HWS_GSC 0x62
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index dfb69fc977a0..52a24f55cb57 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1419,6 +1419,20 @@ void intel_engine_destroy_pinned_context(struct
> intel_context *ce)
> intel_context_put(ce);
> }
>
> +static struct intel_context *
> +create_ggtt_bind_context(struct intel_engine_cs *engine)
> +{
> + static struct lock_class_key kernel;
> +
> + /*
> + * MI_UPDATE_GTT can insert up to 512 PTE entries and there could be
> multiple
> + * bind requets at a time so get a bigger ring.
> + */
> + return intel_engine_create_pinned_context(engine, engine->gt->vm,
> SZ_512K,
> +
> I915_GEM_HWS_GGTT_BIND_ADDR,
> + , "ggtt_bind_context");
> +}
> +
> static struct intel_context *
> create_kernel_context(struct intel_engine_cs *engine)
> {
> @@ -1442,7 +1456,7 @@ create_kernel_context(struct intel_engine_cs *engine)
> */
> static int engine_init_common(struct intel_engine_cs *engine)
> {
> - struct intel_context *ce;
> + struct intel_context *ce, *bce = NULL;
> int ret;
>
> engine->set_default_submission(engine);
> @@ -1458,6 +1472,17 @@ static int engine_init_common(struct intel_engine_cs
> *engine)
> ce = create_kernel_context(engine);
> if (IS_ERR(ce))
> return PTR_ERR(ce);
> + /*
> + * Create a separate pinned context for GGTT update with blitter engine
> + * if a platform require such service. MI_UPDATE_GTT works on other
> + * engines as well but BCS should be less busy engine so pick that for
> + * GGTT updates.
> + */
> + if (engine->id == BCS0) {
> + bce = create_ggtt_bind_context(engine);
> + if (IS_ERR(bce))
> + return PTR_ERR(bce);
Do you need to destroy ce before return?
Oak
> + }
>
> ret = measure_breadcrumb_dw(ce);
> if (ret < 0)
> @@ -1465,11 +1490,14 @@ static int engine_init_common(struct intel_engine_cs
> *engine)
>
> engine->emit_fini_breadcrumb_dw = ret;
> engine->kernel_context = ce;
> + engine->bind_context = bce;
>
> return 0;
>
> err_context:
> intel_engine_destroy_pinned_context(ce);
> + if (bce)
> + intel_engine_destroy_pinned_context(ce);
> return ret;
> }
>
> @@ -1537,6 +1565,9 @@ void intel_engine_cleanup_common(struct
> intel_engine_cs *engine)
>
> if (engine->kernel_context)
> intel_engine_destroy_pinned_context(engine->kernel_context);
> + if (engine->bind_context)
> + intel_engine_destroy_pinned_context(engine->bind_context);
> +
>
> GEM_BUG_ON(!llist_empty(>barrier_tasks));
> cleanup_status_page(engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index a7e677598004..a8f527fab0f0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -416,6 +416,9 @@ struct
Re: [Intel-gfx] [PATCH v2 12/19] drm/i915/dsb: Load LUTs using the DSB during vblank
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, June 7, 2023 12:45 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 12/19] drm/i915/dsb: Load LUTs using the DSB
> during vblank
>
> From: Ville Syrjälä
>
> Loading LUTs with the DSB outside of vblank doesn't really work due to the
> palette anti-collision logic. Apparently the DSB register writes don't get
> stalled
> like CPU mmio writes do and instead we end up corrupting the LUT entries.
> Disabling the anti-collision logic would allow us to successfully load the LUT
> outside of vblank, but presumably that risks the LUT reads from the scanout
> (temportarily) getting corrupted data from the LUT instead.
Nit: Typo in temporarily.
>
> The anti-collision logic isn't active during vblank so that is when we can
> successfully load the LUT with the DSB. That is what we want to do anyway to
> avoid tearing.
Doing in vblank should be good, only case I see where we have to be watchful is
the
HRR (high refresh rate) cases. We need to be sure, through DSB we will be able
to get
this in time, it needs to be fast enough to fit the programming window, else we
may
have to have some fallback to MMIO and do in active. Ideally it should work out
with
DSB execution, just something to be mindful of.
Change looks good to me.
Reviewed-by: Uma Shankar
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 30
> drivers/gpu/drm/i915/display/intel_color.h | 2 ++
> drivers/gpu/drm/i915/display/intel_crtc.c| 4 ++-
> drivers/gpu/drm/i915/display/intel_display.c | 3 ++
> 4 files changed, 32 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 2db9d1d6dadd..077e45372dab 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1660,12 +1660,6 @@ static void icl_load_luts(const struct intel_crtc_state
> *crtc_state)
> MISSING_CASE(crtc_state->gamma_mode);
> break;
> }
> -
> - if (crtc_state->dsb) {
> - intel_dsb_finish(crtc_state->dsb);
> - intel_dsb_commit(crtc_state->dsb, false);
> - intel_dsb_wait(crtc_state->dsb);
> - }
> }
>
> static void vlv_load_luts(const struct intel_crtc_state *crtc_state) @@
> -1772,6
> +1766,9 @@ void intel_color_load_luts(const struct intel_crtc_state
> *crtc_state)
> {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>
> + if (crtc_state->dsb)
> + return;
> +
> i915->display.funcs.color->load_luts(crtc_state);
> }
>
> @@ -1788,6 +1785,9 @@ void intel_color_commit_arm(const struct
> intel_crtc_state *crtc_state)
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>
> i915->display.funcs.color->color_commit_arm(crtc_state);
> +
> + if (crtc_state->dsb)
> + intel_dsb_commit(crtc_state->dsb, true);
> }
>
> void intel_color_post_update(const struct intel_crtc_state *crtc_state) @@ -
> 1801,6 +1801,7 @@ void intel_color_post_update(const struct intel_crtc_state
> *crtc_state) void intel_color_prepare_commit(struct intel_crtc_state
> *crtc_state) {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>
> /* FIXME DSB has issues loading LUTs, disable it for now */
> return;
> @@ -1813,6 +1814,12 @@ void intel_color_prepare_commit(struct
> intel_crtc_state *crtc_state)
> return;
>
> crtc_state->dsb = intel_dsb_prepare(crtc, 1024);
> + if (!crtc_state->dsb)
> + return;
> +
> + i915->display.funcs.color->load_luts(crtc_state);
> +
> + intel_dsb_finish(crtc_state->dsb);
> }
>
> void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state) @@ -
> 1824,6 +1831,17 @@ void intel_color_cleanup_commit(struct intel_crtc_state
> *crtc_state)
> crtc_state->dsb = NULL;
> }
>
> +void intel_color_wait_commit(const struct intel_crtc_state *crtc_state)
> +{
> + if (crtc_state->dsb)
> + intel_dsb_wait(crtc_state->dsb);
> +}
> +
> +bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state) {
> + return crtc_state->dsb;
> +}
> +
> static bool intel_can_preload_luts(const struct intel_crtc_state
> *new_crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_color.h
> b/drivers/gpu/drm/i915/display/intel_color.h
> index 8002492be709..8ecd36149def 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.h
> +++ b/drivers/gpu/drm/i915/display/intel_color.h
> @@ -19,6 +19,8 @@ void intel_color_crtc_init(struct intel_crtc *crtc); int
> intel_color_check(struct intel_crtc_state *crtc_state); void
>
[Intel-gfx] [PATCH 1/2] drm/i915: Check lane count when determining FEC support
From: Ville Syrjälä
ICL doesn't support FEC with a x1 DP link. Make sure
we don't try to enable FEC in such cases.
Requires a bit of reordering to make sure we've computed lane_count
before checking it.
Cc: Luca Coelho
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 55ba6eeaa810..2cde8ac513bb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1363,7 +1363,8 @@ static bool intel_dp_source_supports_fec(struct intel_dp
*intel_dp,
if (DISPLAY_VER(dev_priv) >= 12)
return true;
- if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
+ if (DISPLAY_VER(dev_priv) == 11 &&
+ encoder->port != PORT_A && pipe_config->lane_count != 1)
return true;
return false;
@@ -2105,15 +2106,6 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
_config->hw.adjusted_mode;
int ret;
- pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
- intel_dp_supports_fec(intel_dp, pipe_config);
-
- if (!intel_dp_supports_dsc(intel_dp, pipe_config))
- return -EINVAL;
-
- if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
- return -EINVAL;
-
/*
* compute pipe bpp is set to false for DP MST DSC case
* and compressed_bpp is calculated same time once
@@ -2134,6 +2126,15 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
}
}
+ pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
+ intel_dp_supports_fec(intel_dp, pipe_config);
+
+ if (!intel_dp_supports_dsc(intel_dp, pipe_config))
+ return -EINVAL;
+
+ if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
+ return -EINVAL;
+
/* Calculate Slice count */
if (intel_dp_is_edp(intel_dp)) {
pipe_config->dsc.slice_count =
--
2.41.0
[Intel-gfx] [PATCH 2/2] drm/i915: Require FEC for DSC on DP-MST
From: Ville Syrjälä
The current check just asserts that we need FEC to use DSC
with (non-eDP) DP-SST. But MST also needs FEC for DSC. Just
check for !eDP instead to cover all the cases correctly.
Cc: Luca Coelho
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2cde8ac513bb..41f180f2879e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1380,7 +1380,7 @@ static bool intel_dp_supports_fec(struct intel_dp
*intel_dp,
static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
- if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) &&
!crtc_state->fec_enable)
+ if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
return false;
return intel_dsc_source_support(crtc_state) &&
--
2.41.0
[Intel-gfx] [PATCH v2 1/4] drm/i915: Move fbdev functions
Move functions within intel_fbdev.c to simplify later updates. No
functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 154 ++---
1 file changed, 77 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 31d0d695d5671..8d51550e18fd5 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -545,58 +545,6 @@ static void intel_fbdev_suspend_worker(struct work_struct
*work)
true);
}
-int intel_fbdev_init(struct drm_device *dev)
-{
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_fbdev *ifbdev;
- int ret;
-
- if (drm_WARN_ON(dev, !HAS_DISPLAY(dev_priv)))
- return -ENODEV;
-
- ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
- if (ifbdev == NULL)
- return -ENOMEM;
-
- mutex_init(>hpd_lock);
- drm_fb_helper_prepare(dev, >helper, 32, _fb_helper_funcs);
-
- if (intel_fbdev_init_bios(dev, ifbdev))
- ifbdev->helper.preferred_bpp = ifbdev->preferred_bpp;
- else
- ifbdev->preferred_bpp = ifbdev->helper.preferred_bpp;
-
- ret = drm_fb_helper_init(dev, >helper);
- if (ret) {
- kfree(ifbdev);
- return ret;
- }
-
- dev_priv->display.fbdev.fbdev = ifbdev;
- INIT_WORK(_priv->display.fbdev.suspend_work,
intel_fbdev_suspend_worker);
-
- return 0;
-}
-
-static void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
-{
- struct intel_fbdev *ifbdev = data;
-
- /* Due to peculiar init order wrt to hpd handling this is separate. */
- if (drm_fb_helper_initial_config(>helper))
- intel_fbdev_unregister(to_i915(ifbdev->helper.dev));
-}
-
-void intel_fbdev_initial_config_async(struct drm_i915_private *dev_priv)
-{
- struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev;
-
- if (!ifbdev)
- return;
-
- ifbdev->cookie = async_schedule(intel_fbdev_initial_config, ifbdev);
-}
-
static void intel_fbdev_sync(struct intel_fbdev *ifbdev)
{
if (!ifbdev->cookie)
@@ -607,31 +555,6 @@ static void intel_fbdev_sync(struct intel_fbdev *ifbdev)
ifbdev->cookie = 0;
}
-void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
-{
- struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev;
-
- if (!ifbdev)
- return;
-
- intel_fbdev_set_suspend(_priv->drm, FBINFO_STATE_SUSPENDED, true);
-
- if (!current_is_async())
- intel_fbdev_sync(ifbdev);
-
- drm_fb_helper_unregister_info(>helper);
-}
-
-void intel_fbdev_fini(struct drm_i915_private *dev_priv)
-{
- struct intel_fbdev *ifbdev =
fetch_and_zero(_priv->display.fbdev.fbdev);
-
- if (!ifbdev)
- return;
-
- intel_fbdev_destroy(ifbdev);
-}
-
/* Suspends/resumes fbdev processing of incoming HPD events. When resuming HPD
* processing, fbdev will perform a full connector reprobe if a hotplug event
* was received while HPD was suspended.
@@ -748,6 +671,83 @@ void intel_fbdev_restore_mode(struct drm_i915_private
*dev_priv)
intel_fbdev_invalidate(ifbdev);
}
+int intel_fbdev_init(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_fbdev *ifbdev;
+ int ret;
+
+ if (drm_WARN_ON(dev, !HAS_DISPLAY(dev_priv)))
+ return -ENODEV;
+
+ ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
+ if (ifbdev == NULL)
+ return -ENOMEM;
+
+ mutex_init(>hpd_lock);
+ drm_fb_helper_prepare(dev, >helper, 32, _fb_helper_funcs);
+
+ if (intel_fbdev_init_bios(dev, ifbdev))
+ ifbdev->helper.preferred_bpp = ifbdev->preferred_bpp;
+ else
+ ifbdev->preferred_bpp = ifbdev->helper.preferred_bpp;
+
+ ret = drm_fb_helper_init(dev, >helper);
+ if (ret) {
+ kfree(ifbdev);
+ return ret;
+ }
+
+ dev_priv->display.fbdev.fbdev = ifbdev;
+ INIT_WORK(_priv->display.fbdev.suspend_work,
intel_fbdev_suspend_worker);
+
+ return 0;
+}
+
+static void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
+{
+ struct intel_fbdev *ifbdev = data;
+
+ /* Due to peculiar init order wrt to hpd handling this is separate. */
+ if (drm_fb_helper_initial_config(>helper))
+ intel_fbdev_unregister(to_i915(ifbdev->helper.dev));
+}
+
+void intel_fbdev_initial_config_async(struct drm_i915_private *dev_priv)
+{
+ struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev;
+
+ if (!ifbdev)
+ return;
+
+ ifbdev->cookie = async_schedule(intel_fbdev_initial_config, ifbdev);
+}
+
+void intel_fbdev_unregister(struct drm_i915_private
[Intel-gfx] [PATCH v2 3/4] drm/i915: Implement fbdev client callbacks
Move code from ad-hoc fbdev callbacks into DRM client functions
and remove the old callbacks. The functions instruct the client
to poll for changed output or restore the display.
The DRM core calls both, the old callbacks and the new client
helpers, from the same places. The new functions perform the same
operation as before, so there's no change in functionality.
Signed-off-by: Thomas Zimmermann
---
.../drm/i915/display/intel_display_driver.c | 1 -
drivers/gpu/drm/i915/display/intel_fbdev.c| 11 --
drivers/gpu/drm/i915/display/intel_fbdev.h| 9
drivers/gpu/drm/i915/i915_driver.c| 22 ---
4 files changed, 9 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 9d9b034b9bdc7..0650c0ed30a0c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -96,7 +96,6 @@ void intel_display_driver_init_hw(struct drm_i915_private
*i915)
static const struct drm_mode_config_funcs intel_mode_funcs = {
.fb_create = intel_user_framebuffer_create,
.get_format_info = intel_fb_get_format_info,
- .output_poll_changed = intel_fbdev_output_poll_changed,
.mode_valid = intel_mode_valid,
.atomic_check = intel_atomic_check,
.atomic_commit = intel_atomic_commit,
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index d8a165582fd59..31e8275a70fea 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -638,7 +638,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int
state, bool synchronous
intel_fbdev_hpd_set_suspend(dev_priv, state);
}
-void intel_fbdev_output_poll_changed(struct drm_device *dev)
+static void intel_fbdev_output_poll_changed(struct drm_device *dev)
{
struct intel_fbdev *ifbdev = to_i915(dev)->display.fbdev.fbdev;
bool send_hpd;
@@ -657,7 +657,7 @@ void intel_fbdev_output_poll_changed(struct drm_device *dev)
drm_fb_helper_hotplug_event(>helper);
}
-void intel_fbdev_restore_mode(struct drm_i915_private *dev_priv)
+static void intel_fbdev_restore_mode(struct drm_i915_private *dev_priv)
{
struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev;
@@ -681,11 +681,18 @@ static void intel_fbdev_client_unregister(struct
drm_client_dev *client)
static int intel_fbdev_client_restore(struct drm_client_dev *client)
{
+ struct drm_i915_private *dev_priv = to_i915(client->dev);
+
+ intel_fbdev_restore_mode(dev_priv);
+ vga_switcheroo_process_delayed_switch();
+
return 0;
}
static int intel_fbdev_client_hotplug(struct drm_client_dev *client)
{
+ intel_fbdev_output_poll_changed(client->dev);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.h
b/drivers/gpu/drm/i915/display/intel_fbdev.h
index 04fd523a50232..8c953f102ba22 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.h
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.h
@@ -19,8 +19,6 @@ void intel_fbdev_initial_config_async(struct drm_i915_private
*dev_priv);
void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
void intel_fbdev_fini(struct drm_i915_private *dev_priv);
void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool
synchronous);
-void intel_fbdev_output_poll_changed(struct drm_device *dev);
-void intel_fbdev_restore_mode(struct drm_i915_private *dev_priv);
struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbdev);
#else
static inline int intel_fbdev_init(struct drm_device *dev)
@@ -44,13 +42,6 @@ static inline void intel_fbdev_set_suspend(struct drm_device
*dev, int state, bo
{
}
-static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
-{
-}
-
-static inline void intel_fbdev_restore_mode(struct drm_i915_private *i915)
-{
-}
static inline struct intel_framebuffer *intel_fbdev_framebuffer(struct
intel_fbdev *fbdev)
{
return NULL;
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index f8dbee7a5af7f..14aa863dca60c 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -921,27 +921,6 @@ static int i915_driver_open(struct drm_device *dev, struct
drm_file *file)
return 0;
}
-/**
- * i915_driver_lastclose - clean up after all DRM clients have exited
- * @dev: DRM device
- *
- * Take care of cleaning up after all DRM clients have exited. In the
- * mode setting case, we want to restore the kernel's initial mode (just
- * in case the last client left us in a bad state).
- *
- * Additionally, in the non-mode setting case, we'll tear down the GTT
- * and DMA structures, since the kernel won't be using them, and clea
- * up any GEM state.
- */
-static void i915_driver_lastclose(struct drm_device
[Intel-gfx] [PATCH v2 4/4] drm/i915: Implement fbdev emulation as in-kernel client
Replace all code that initializes or releases fbdev emulation
throughout the driver. Instead initialize the fbdev client by a
single call to i915_fbdev_setup() after i915 has registered its
DRM device. Just like similar code in other drivers, i915 fbdev
emulation now acts as a regular DRM client.
The fbdev client setup consists of the initial preparation and the
hot-plugging of the display. The latter creates the fbdev device
and sets up the fbdev framebuffer. The setup performs display
hot-plugging once. If no display can be detected, DRM probe helpers
re-run the detection on each hotplug event.
A call to drm_dev_unregister() releases the client automatically.
No further action is required within i915. If the fbdev framebuffer
has been fully set up, struct fb_ops.fb_destroy implements the
release. For partially initialized emulation, the fbdev client
reverts the initial setup.
v2:
* let drm_client_register() handle initial hotplug
* fix driver name in error message (Jani)
* fix non-fbdev build (kernel test robot)
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/i915/display/intel_display.c | 1 -
.../drm/i915/display/intel_display_driver.c | 18 --
drivers/gpu/drm/i915/display/intel_fbdev.c| 182 --
drivers/gpu/drm/i915/display/intel_fbdev.h| 20 +-
drivers/gpu/drm/i915/i915_driver.c| 2 +
5 files changed, 84 insertions(+), 139 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 83e1bc858b9fb..64578f991f41d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -81,7 +81,6 @@
#include "intel_dvo.h"
#include "intel_fb.h"
#include "intel_fbc.h"
-#include "intel_fbdev.h"
#include "intel_fdi.h"
#include "intel_fifo_underrun.h"
#include "intel_frontbuffer.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 0650c0ed30a0c..7f0d6dbc47cae 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -364,10 +364,6 @@ int intel_display_driver_probe(struct drm_i915_private
*i915)
intel_overlay_setup(i915);
- ret = intel_fbdev_init(>drm);
- if (ret)
- return ret;
-
/* Only enable hotplug handling once the fbdev is fully set up. */
intel_hpd_init(i915);
intel_hpd_poll_disable(i915);
@@ -390,16 +386,6 @@ void intel_display_driver_register(struct drm_i915_private
*i915)
intel_display_debugfs_register(i915);
- /*
-* Some ports require correctly set-up hpd registers for
-* detection to work properly (leading to ghost connected
-* connector status), e.g. VGA on gm45. Hence we can only set
-* up the initial fbdev config after hpd irqs are fully
-* enabled. We do it last so that the async config cannot run
-* before the connectors are registered.
-*/
- intel_fbdev_initial_config_async(i915);
-
/*
* We need to coordinate the hotplugs with the asynchronous
* fbdev configuration, for which we use the
@@ -440,9 +426,6 @@ void intel_display_driver_remove_noirq(struct
drm_i915_private *i915)
*/
intel_hpd_poll_fini(i915);
- /* poll work can call into fbdev, hence clean that up afterwards */
- intel_fbdev_fini(i915);
-
intel_unregister_dsm_handler();
/* flush any delayed tasks or pending work */
@@ -479,7 +462,6 @@ void intel_display_driver_unregister(struct
drm_i915_private *i915)
if (!HAS_DISPLAY(i915))
return;
- intel_fbdev_unregister(i915);
intel_audio_deinit(i915);
/*
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 31e8275a70fea..8a13909d3f0b2 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -24,7 +24,6 @@
* David Airlie
*/
-#include
#include
#include
#include
@@ -39,6 +38,7 @@
#include
#include
+#include
#include
#include
#include
@@ -58,7 +58,6 @@ struct intel_fbdev {
struct intel_framebuffer *fb;
struct i915_vma *vma;
unsigned long vma_flags;
- async_cookie_t cookie;
int preferred_bpp;
/* Whether or not fbdev hpd processing is temporarily suspended */
@@ -135,6 +134,26 @@ static int intel_fbdev_mmap(struct fb_info *info, struct
vm_area_struct *vma)
return i915_gem_fb_mmap(obj, vma);
}
+static void intel_fbdev_fb_destroy(struct fb_info *info)
+{
+ struct drm_fb_helper *fb_helper = info->par;
+ struct intel_fbdev *ifbdev = container_of(fb_helper, struct
intel_fbdev, helper);
+
+ drm_fb_helper_fini(>helper);
+
+ /*
+* We rely on the object-free to release the VMA pinning
[Intel-gfx] [PATCH v2 2/4] drm/i915: Initialize fbdev DRM client with callback functions
Initialize i915's fbdev client by giving an instance of struct
drm_client_funcs to drm_client_init(). Also clean up with
drm_client_release().
Doing this in i915 prevents fbdev helpers from initializing and
releasing the client internally (see drm_fb_helper_init()). No
functional change yet; the client callbacks will be filled later.
v2:
* call drm_fb_helper_unprepare() in error hndling (Jani)
* fix typo in commit message (Sam)
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 43 --
1 file changed, 39 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 8d51550e18fd5..d8a165582fd59 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -378,6 +378,7 @@ static void intel_fbdev_destroy(struct intel_fbdev *ifbdev)
if (ifbdev->fb)
drm_framebuffer_remove(>fb->base);
+ drm_client_release(>helper.client);
drm_fb_helper_unprepare(>helper);
kfree(ifbdev);
}
@@ -671,6 +672,30 @@ void intel_fbdev_restore_mode(struct drm_i915_private
*dev_priv)
intel_fbdev_invalidate(ifbdev);
}
+/*
+ * Fbdev client and struct drm_client_funcs
+ */
+
+static void intel_fbdev_client_unregister(struct drm_client_dev *client)
+{ }
+
+static int intel_fbdev_client_restore(struct drm_client_dev *client)
+{
+ return 0;
+}
+
+static int intel_fbdev_client_hotplug(struct drm_client_dev *client)
+{
+ return 0;
+}
+
+static const struct drm_client_funcs intel_fbdev_client_funcs = {
+ .owner = THIS_MODULE,
+ .unregister = intel_fbdev_client_unregister,
+ .restore= intel_fbdev_client_restore,
+ .hotplug= intel_fbdev_client_hotplug,
+};
+
int intel_fbdev_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -692,16 +717,26 @@ int intel_fbdev_init(struct drm_device *dev)
else
ifbdev->preferred_bpp = ifbdev->helper.preferred_bpp;
+ ret = drm_client_init(dev, >helper.client, "i915-fbdev",
+ _fbdev_client_funcs);
+ if (ret)
+ goto err_drm_fb_helper_unprepare;
+
ret = drm_fb_helper_init(dev, >helper);
- if (ret) {
- kfree(ifbdev);
- return ret;
- }
+ if (ret)
+ goto err_drm_client_release;
dev_priv->display.fbdev.fbdev = ifbdev;
INIT_WORK(_priv->display.fbdev.suspend_work,
intel_fbdev_suspend_worker);
return 0;
+
+err_drm_client_release:
+ drm_client_release(>helper.client);
+err_drm_fb_helper_unprepare:
+ drm_fb_helper_unprepare(>helper);
+ kfree(ifbdev);
+ return ret;
}
static void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
--
2.42.0
[Intel-gfx] [PATCH v2 0/4] drm/i915: Convert fbdev to DRM client
Convert i915's fbdev code to struct drm_client. Replaces the current ad-hoc integration. The conversion includes a number of cleanups. As with most other driver's fbdev emulation, fbdev in i915 is now just another DRM client that runs after the DRM device has been registered. This allows to remove the asynchronous initialization. I've long wanted to send out an update for this patchset. i915 is the last driver with an fbdev emulation that is not build upon struct drm_client. Once reviewed, the patches would ideally go into drm-misc-next, so that the old fbdev helper code can be removed. We can also attempt to add additional in-kernel clients. A DRM-based dmesg log or a bootsplash are commonly mentioned. DRM can then switch easily among the existing clients if/when required. v2: * fix error handling (Jani) * fix non-fbdev builds * various minor fixes and cleanups Thomas Zimmermann (4): drm/i915: Move fbdev functions drm/i915: Initialize fbdev DRM client with callback functions drm/i915: Implement fbdev client callbacks drm/i915: Implement fbdev emulation as in-kernel client drivers/gpu/drm/i915/display/intel_display.c | 1 - .../drm/i915/display/intel_display_driver.c | 19 -- drivers/gpu/drm/i915/display/intel_fbdev.c| 250 ++ drivers/gpu/drm/i915/display/intel_fbdev.h| 29 +- drivers/gpu/drm/i915/i915_driver.c| 24 +- 5 files changed, 139 insertions(+), 184 deletions(-) base-commit: f8d21cb17a99b75862196036bb4bb93ee9637b74 -- 2.42.0
Re: [Intel-gfx] [PATCH] drm/i915: Remove runtime suspended boolean from intel_runtime_pm struct
On Wed, Sep 13, 2023 at 03:02:58PM +0300, Jani Nikula wrote:
> On Wed, 13 Sep 2023, Jouni Högander wrote:
> > It's not necessary to carry separate suspended status information in
> > intel_runtime_pm struct as this information is already in underlying device
> > structure. Remove it and use pm_runtime_suspended() to obtain suspended
> > status information when needed.
>
> I started wondering if this is racy, and my conclusion is that it's
> "less" racy than the original. rpm->suspended gets toggled in the middle
> of the suspend/resume sequences. So it could be halfway. Dunno if
> anything *after* those toggles depends on the state having been changed
> already; didn't find any. Maybe Imre has a better idea.
>
> Also, pm_runtime_suspended() seems more reliable when suspend/resume
> fails.
The flag was added in the initial runtime PM enabling patch to detect
MMIO accesses while runtime suspended, looks like pm_runtime_suspended()
would've worked ok already at that point.
I wondered how the above detection would change in the system suspend /
resume handlers but that looks ok as well with the disable_depth check
in pm_runtime_suspended():
Reviewed-by: Imre Deak
> Acked-by: Jani Nikula
>
>
> >
> > Cc: Jani Nikula
> > Cc: Imre Deak
> >
> > Signed-off-by: Jouni Högander
> > ---
> > drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
> > drivers/gpu/drm/i915/i915_driver.c | 3 ---
> > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> > drivers/gpu/drm/i915/intel_runtime_pm.c| 1 -
> > drivers/gpu/drm/i915/intel_runtime_pm.h| 4 ++--
> > 5 files changed, 4 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 68cf5e6b0b46..889bb26009a2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -216,7 +216,7 @@ bool __intel_display_power_is_enabled(struct
> > drm_i915_private *dev_priv,
> > struct i915_power_well *power_well;
> > bool is_enabled;
> >
> > - if (dev_priv->runtime_pm.suspended)
> > + if (pm_runtime_suspended(dev_priv->drm.dev))
> > return false;
> >
> > is_enabled = true;
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c
> > b/drivers/gpu/drm/i915/i915_driver.c
> > index f8dbee7a5af7..cd98ee740976 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -1569,8 +1569,6 @@ static int intel_runtime_suspend(struct device *kdev)
> > if (root_pdev)
> > pci_d3cold_disable(root_pdev);
> >
> > - rpm->suspended = true;
> > -
> > /*
> > * FIXME: We really should find a document that references the arguments
> > * used below!
> > @@ -1621,7 +1619,6 @@ static int intel_runtime_resume(struct device *kdev)
> > disable_rpm_wakeref_asserts(rpm);
> >
> > intel_opregion_notify_adapter(dev_priv, PCI_D0);
> > - rpm->suspended = false;
> >
> > root_pdev = pcie_find_root_port(pdev);
> > if (root_pdev)
> > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> > b/drivers/gpu/drm/i915/i915_gpu_error.c
> > index 4008bb09fdb5..a60bab177c55 100644
> > --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > @@ -1972,7 +1972,7 @@ static void capture_gen(struct i915_gpu_coredump
> > *error)
> > struct drm_i915_private *i915 = error->i915;
> >
> > error->wakelock = atomic_read(>runtime_pm.wakeref_count);
> > - error->suspended = i915->runtime_pm.suspended;
> > + error->suspended = pm_runtime_suspended(i915->drm.dev);
> >
> > error->iommu = i915_vtd_active(i915);
> > error->reset_count = i915_reset_count(>gpu_error);
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 6d8e5e5c0cba..8743153fad87 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -652,7 +652,6 @@ void intel_runtime_pm_init_early(struct
> > intel_runtime_pm *rpm)
> >
> > rpm->kdev = kdev;
> > rpm->available = HAS_RUNTIME_PM(i915);
> > - rpm->suspended = false;
> > atomic_set(>wakeref_count, 0);
> >
> > init_intel_runtime_pm_wakeref(rpm);
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h
> > b/drivers/gpu/drm/i915/intel_runtime_pm.h
> > index 764b183ae452..f79cda7a2503 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.h
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.h
> > @@ -6,6 +6,7 @@
> > #ifndef __INTEL_RUNTIME_PM_H__
> > #define __INTEL_RUNTIME_PM_H__
> >
> > +#include
> > #include
> >
> > #include "intel_wakeref.h"
> > @@ -43,7 +44,6 @@ struct intel_runtime_pm {
> > atomic_t wakeref_count;
> > struct device *kdev; /* points to i915->drm.dev */
> > bool available;
> > - bool suspended;
> > bool irqs_enabled;
> >
Re: [Intel-gfx] [PATCH v2 1/3] drm/buddy: Improve contiguous memory allocation
On 11/09/23 03:46, Matthew Auld wrote:
On 09/09/2023 17:09, Arunpravin Paneer Selvam wrote:
Problem statement: The current method roundup_power_of_two()
to allocate contiguous address triggers -ENOSPC in some cases
even though we have enough free spaces and so to help with
that we introduce a try harder mechanism.
In case of -ENOSPC, the new try harder mechanism rounddown the
original size to power of 2 and iterating over the round down
sized freelist blocks to allocate the required size traversing
RHS and LHS.
As part of the above new method implementation we moved
contiguous/alignment size computation part and trim function
to the drm buddy file.
v2: Modify the alloc_range() function to return total allocated size
on -ENOSPC err and traverse RHS/LHS to allocate the required
size (Matthew).
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/drm_buddy.c | 138
include/drm/drm_buddy.h | 6 +-
2 files changed, 127 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index 7098f125b54a..e909eed9cf60 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -480,10 +480,12 @@ alloc_from_freelist(struct drm_buddy *mm,
static int __alloc_range(struct drm_buddy *mm,
struct list_head *dfs,
u64 start, u64 size,
- struct list_head *blocks)
+ struct list_head *blocks,
+ u64 *total_allocated_on_err)
{
struct drm_buddy_block *block;
struct drm_buddy_block *buddy;
+ u64 total_allocated = 0;
LIST_HEAD(allocated);
u64 end;
int err;
@@ -520,6 +522,7 @@ static int __alloc_range(struct drm_buddy *mm,
}
mark_allocated(block);
+ total_allocated += drm_buddy_block_size(mm, block);
mm->avail -= drm_buddy_block_size(mm, block);
list_add_tail(>link, );
continue;
@@ -551,13 +554,20 @@ static int __alloc_range(struct drm_buddy *mm,
__drm_buddy_free(mm, block);
err_free:
- drm_buddy_free_list(mm, );
+ if (err == -ENOSPC && total_allocated_on_err) {
+ list_splice_tail(, blocks);
+ *total_allocated_on_err = total_allocated;
+ } else {
+ drm_buddy_free_list(mm, );
+ }
+
return err;
}
static int __drm_buddy_alloc_range(struct drm_buddy *mm,
u64 start,
u64 size,
+ u64 *total_allocated_on_err,
struct list_head *blocks)
{
LIST_HEAD(dfs);
@@ -566,7 +576,62 @@ static int __drm_buddy_alloc_range(struct
drm_buddy *mm,
for (i = 0; i < mm->n_roots; ++i)
list_add_tail(>roots[i]->tmp_link, );
- return __alloc_range(mm, , start, size, blocks);
+ return __alloc_range(mm, , start, size,
+ blocks, total_allocated_on_err);
+}
+
+static int __alloc_contig_try_harder(struct drm_buddy *mm,
+ u64 size,
+ u64 min_block_size,
+ struct list_head *blocks)
+{
+ u64 rhs_offset, lhs_offset, lhs_size, filled;
+ struct drm_buddy_block *block;
+ struct list_head *list;
+ LIST_HEAD(blocks_lhs);
+ unsigned long pages;
+ unsigned int order;
+ u64 modify_size;
+ int err;
+
+ modify_size = rounddown_pow_of_two(size);
+ pages = modify_size >> ilog2(mm->chunk_size);
+ order = fls(pages) - 1;
+ if (order == 0)
+ return -ENOSPC;
+
+ list = >free_list[order];
+ if (list_empty(list))
+ return -ENOSPC;
+
+ list_for_each_entry_reverse(block, list, link) {
+ /* Allocate blocks traversing RHS */
+ rhs_offset = drm_buddy_block_offset(block);
+ err = __drm_buddy_alloc_range(mm, rhs_offset, size,
+ , blocks);
+ if (!err || err != -ENOSPC)
+ return err;
+
+ lhs_size = max((size - filled), min_block_size);
+ if (!IS_ALIGNED(lhs_size, min_block_size))
+ lhs_size = round_up(lhs_size, min_block_size);
+
+ /* Allocate blocks traversing LHS */
+ lhs_offset = drm_buddy_block_offset(block) - lhs_size;
+ err = __drm_buddy_alloc_range(mm, lhs_offset, lhs_size,
+ NULL, _lhs);
+ if (!err) {
+ list_splice(_lhs, blocks);
+ return 0;
I guess we could attempt to trim this also (could tweak the trim to
work on multiple nodes)? But I guess in practice should be pretty meh,
given that the extra rhs is hopefully not too big in the corner case
where the alignment doesn't fit the min_block_size?
Thanks for the review. good point. I will take a look into it.
Regards,
Arun.
Anyway, for patches 1-3,
Reviewed-by: Matthew Auld
+ } else if (err != -ENOSPC) {
+ drm_buddy_free_list(mm, blocks);
+ return err;
+ }
+ /* Free blocks for the next iteration */
+
Re: [Intel-gfx] [PATCH 05/11] drm/i915: Check lane count when determining FEC support
On Thu, May 25, 2023 at 11:09:30AM +0300, Luca Coelho wrote:
> On Tue, 2023-05-02 at 17:39 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > ICL doesn't support FEC with a x1 DP link. Make sure
> > we don't try to enable FEC in such cases.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 23 ---
> > 1 file changed, 12 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index b27b4fb71ed7..9ac199444155 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1218,7 +1218,8 @@ static bool intel_dp_source_supports_fec(struct
> > intel_dp *intel_dp,
> > if (DISPLAY_VER(dev_priv) >= 12)
> > return true;
> >
> > - if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
> > + if (DISPLAY_VER(dev_priv) == 11 &&
> > + encoder->port != PORT_A && pipe_config->lane_count != 1)
> > return true;
> >
> > return false;
> > @@ -1234,7 +1235,7 @@ static bool intel_dp_supports_fec(struct intel_dp
> > *intel_dp,
> > static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> > const struct intel_crtc_state *crtc_state)
> > {
> > - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) &&
> > !crtc_state->fec_enable)
> > + if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
>
> I'm probably missing something, but this change...
This should have been a separate change I suppose. What this is
currently asserting is DP-SST needs FEC to use DSC, but so does DP-MST
which this is totally forgetting to check. eDP is only case where we
can skip FEC.
>
>
> > return false;
> >
> > return intel_dsc_source_support(crtc_state) &&
> > @@ -1580,15 +1581,6 @@ int intel_dp_dsc_compute_config(struct intel_dp
> > *intel_dp,
> > int pipe_bpp;
> > int ret;
> >
> > - pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> > - intel_dp_supports_fec(intel_dp, pipe_config);
> > -
> > - if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > - return -EINVAL;
> > -
> > - if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> > - return -EINVAL;
> > -
> > if (compute_pipe_bpp)
> > pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
> > conn_state->max_requested_bpc);
> > else
> > @@ -1615,6 +1607,15 @@ int intel_dp_dsc_compute_config(struct intel_dp
> > *intel_dp,
> > pipe_config->port_clock = limits->max_rate;
> > pipe_config->lane_count = limits->max_lane_count;
> >
> > + pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> > + intel_dp_supports_fec(intel_dp, pipe_config);
> > +
> > + if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > + return -EINVAL;
> > +
> > + if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> > + return -EINVAL;
> > +
> > if (intel_dp_is_edp(intel_dp)) {
> > pipe_config->dsc.compressed_bpp =
> > min_t(u16,
> > drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
>
> ...and this code move are not explained in the commit message? How are
> they related?
This is moved becaue we need to compute lanel_count before we can
actually check it.
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v2 08/11] drm/i915: Introduce crtc_state->enhanced_framing
On Thu, May 25, 2023 at 12:51:28PM +0300, Luca Coelho wrote:
> On Wed, 2023-05-03 at 14:36 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Track DP enhanced framing properly in the crtc state instead
> > of relying just on the cached DPCD everywhere, and hook it
> > up into the state check and dump.
> >
> > v2: Actually set enhanced_framing in .compute_config()
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/g4x_dp.c | 10 --
> > drivers/gpu/drm/i915/display/intel_crt.c | 2 ++
> > drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 5 +++--
> > drivers/gpu/drm/i915/display/intel_ddi.c | 11 +--
> > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > drivers/gpu/drm/i915/display/intel_display_types.h| 2 ++
> > drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
> > drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
> > 8 files changed, 29 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> > b/drivers/gpu/drm/i915/display/g4x_dp.c
> > index 920d570f7594..534546ea7d0b 100644
> > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> > @@ -141,7 +141,7 @@ static void intel_dp_prepare(struct intel_encoder
> > *encoder,
> >
> > intel_de_rmw(dev_priv, TRANS_DP_CTL(crtc->pipe),
> > TRANS_DP_ENH_FRAMING,
> > -drm_dp_enhanced_frame_cap(intel_dp->dpcd) ?
> > +pipe_config->enhanced_framing ?
> > TRANS_DP_ENH_FRAMING : 0);
> > } else {
> > if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
> > @@ -153,7 +153,7 @@ static void intel_dp_prepare(struct intel_encoder
> > *encoder,
> > intel_dp->DP |= DP_SYNC_VS_HIGH;
> > intel_dp->DP |= DP_LINK_TRAIN_OFF;
> >
> > - if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> > + if (pipe_config->enhanced_framing)
> > intel_dp->DP |= DP_ENHANCED_FRAMING;
> >
> > if (IS_CHERRYVIEW(dev_priv))
> > @@ -351,6 +351,9 @@ static void intel_dp_get_config(struct intel_encoder
> > *encoder,
> > u32 trans_dp = intel_de_read(dev_priv,
> > TRANS_DP_CTL(crtc->pipe));
> >
> > + if (trans_dp & TRANS_DP_ENH_FRAMING)
> > + pipe_config->enhanced_framing = true;
> > +
> > if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
> > flags |= DRM_MODE_FLAG_PHSYNC;
> > else
> > @@ -361,6 +364,9 @@ static void intel_dp_get_config(struct intel_encoder
> > *encoder,
> > else
> > flags |= DRM_MODE_FLAG_NVSYNC;
> > } else {
> > + if (tmp & DP_ENHANCED_FRAMING)
> > + pipe_config->enhanced_framing = true;
> > +
> > if (tmp & DP_SYNC_HS_HIGH)
> > flags |= DRM_MODE_FLAG_PHSYNC;
> > else
> > diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> > b/drivers/gpu/drm/i915/display/intel_crt.c
> > index 13519f78cf9f..52af64aa9953 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> > @@ -449,6 +449,8 @@ static int hsw_crt_compute_config(struct intel_encoder
> > *encoder,
> > /* FDI must always be 2.7 GHz */
> > pipe_config->port_clock = 135000 * 2;
> >
> > + pipe_config->enhanced_framing = true;
> > +
>
> Just curious, why are you setting it to true by default here?
We always want to use enhanced framing with FDI. Setting it here
and doing the readout allows us to also state check it also for FDI.
>
> Otherwise, the changes look reasonable:
>
> Reviewed-by: Luca Coelho
>
> --
> Cheers,
> Luca.
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH i-g-t v2 07/17] lib/ktap: Don't ignore interrupt signals
On Monday, 11 September 2023 11:01:42 CEST Mauro Carvalho Chehab wrote: > On Fri, 8 Sep 2023 14:32:41 +0200 > Janusz Krzysztofik wrote: > > > While reading KTAP data from /dev/kmsg we now ignore interrupt signals > > that may occur during read() and we continue reading the data. No > > explanation has been provided on what that could be needed for. > > The reason is that kunit module load takes seconds, as it only finishes > loading after all tests are executed. > > So, interrupting IGT won't interrupt the tests, and kmsg will still > be filled by test results. > > IMO, the right thing to do here is to ignore interrupts, as otherwise > the logs for the next test will be polluted by the KTAP messages and > the Kernel will be kept on an unstable state, as running tests while > kUnit tests are running is not supported. Well, not really. Please have a look at the following two log excerpts. The first one is from a complete, not interrupted execution of drm_mm test: Sep 13 15:14:39 jkrzyszt-mobl2.ger.corp.intel.com sudo[15594]: jkrzyszt : TTY=pts/14 ; PWD=/home/jkrzyszt/build/igt ; USER=root ; COMMAND=./tests/drm_mm Sep 13 15:14:39 jkrzyszt-mobl2.ger.corp.intel.com sudo[15594]: pam_unix(sudo:session): session opened for user root(uid=0) by jkrzyszt(uid=1000) Sep 13 15:14:39 jkrzyszt-mobl2.ger.corp.intel.com kernel: Console: switching to colour dummy device 80x25 Sep 13 15:14:39 jkrzyszt-mobl2.ger.corp.intel.com unknown: [IGT] drm_mm: executing Sep 13 15:14:39 jkrzyszt-mobl2.ger.corp.intel.com unknown: [IGT] drm_mm: starting subtest drm_mm_test Sep 13 15:14:39 jkrzyszt-mobl2.ger.corp.intel.com kernel: # drm_mm: Testing DRM range manager, with random_seed=0x5b01fc53 max_iterations=8192 max_prime=128 Sep 13 15:14:39 jkrzyszt-mobl2.ger.corp.intel.com kernel: KTAP version 1 Sep 13 15:14:39 jkrzyszt-mobl2.ger.corp.intel.com kernel: # Subtest: drm_mm Sep 13 15:14:39 jkrzyszt-mobl2.ger.corp.intel.com kernel: 1..19 Sep 13 15:14:39 jkrzyszt-mobl2.ger.corp.intel.com kernel: ok 1 drm_test_mm_init Sep 13 15:14:39 jkrzyszt-mobl2.ger.corp.intel.com kernel: ok 2 drm_test_mm_debug Sep 13 15:14:39 jkrzyszt-mobl2.ger.corp.intel.com unknown: [IGT] drm_mm: starting dynamic subtest drm_mm-drm_test_mm_init Sep 13 15:14:39 jkrzyszt-mobl2.ger.corp.intel.com unknown: [IGT] drm_mm: finished subtest drm_mm-drm_test_mm_init, SUCCESS Sep 13 15:14:39 jkrzyszt-mobl2.ger.corp.intel.com unknown: [IGT] drm_mm: starting dynamic subtest drm_mm-drm_test_mm_debug Sep 13 15:14:39 jkrzyszt-mobl2.ger.corp.intel.com unknown: [IGT] drm_mm: finished subtest drm_mm-drm_test_mm_debug, SUCCESS Sep 13 15:14:46 jkrzyszt-mobl2.ger.corp.intel.com kernel: ok 3 drm_test_mm_reserve Sep 13 15:14:46 jkrzyszt-mobl2.ger.corp.intel.com kernel: ok 4 drm_test_mm_insert Sep 13 15:14:46 jkrzyszt-mobl2.ger.corp.intel.com unknown: [IGT] drm_mm: starting dynamic subtest drm_mm-drm_test_mm_reserve Sep 13 15:14:46 jkrzyszt-mobl2.ger.corp.intel.com unknown: [IGT] drm_mm: finished subtest drm_mm-drm_test_mm_reserve, SUCCESS Sep 13 15:14:46 jkrzyszt-mobl2.ger.corp.intel.com unknown: [IGT] drm_mm: starting dynamic subtest drm_mm-drm_test_mm_insert Sep 13 15:14:46 jkrzyszt-mobl2.ger.corp.intel.com unknown: [IGT] drm_mm: finished subtest drm_mm-drm_test_mm_insert, SUCCESS Sep 13 15:14:55 jkrzyszt-mobl2.ger.corp.intel.com kernel: ok 5 drm_test_mm_replace Sep 13 15:14:55 jkrzyszt-mobl2.ger.corp.intel.com kernel: ok 6 drm_test_mm_insert_range Sep 13 15:14:55 jkrzyszt-mobl2.ger.corp.intel.com unknown: [IGT] drm_mm: starting dynamic subtest drm_mm-drm_test_mm_replace Sep 13 15:14:55 jkrzyszt-mobl2.ger.corp.intel.com unknown: [IGT] drm_mm: finished subtest drm_mm-drm_test_mm_replace, SUCCESS Sep 13 15:14:55 jkrzyszt-mobl2.ger.corp.intel.com unknown: [IGT] drm_mm: starting dynamic subtest drm_mm-drm_test_mm_insert_range Sep 13 15:14:55 jkrzyszt-mobl2.ger.corp.intel.com unknown: [IGT] drm_mm: finished subtest drm_mm-drm_test_mm_insert_range, SUCCESS Sep 13 15:14:55 jkrzyszt-mobl2.ger.corp.intel.com kernel: # drm_test_mm_frag: bottom-up fragmented insert of 1 and 2 insertions took 6009658 and 13648333 nsecs Sep 13 15:14:55 jkrzyszt-mobl2.ger.corp.intel.com kernel: # drm_test_mm_frag: top-down fragmented insert of 1 and 2 insertions took 6518544 and 13824246 nsecs Sep 13 15:14:55 jkrzyszt-mobl2.ger.corp.intel.com kernel: ok 7 drm_test_mm_frag Sep 13 15:14:55 jkrzyszt-mobl2.ger.corp.intel.com kernel: ok 8 drm_test_mm_align Sep 13 15:14:55 jkrzyszt-mobl2.ger.corp.intel.com kernel: ok 9 drm_test_mm_align32 Sep 13 15:14:55 jkrzyszt-mobl2.ger.corp.intel.com kernel: ok 10 drm_test_mm_align64 Sep 13 15:14:55 jkrzyszt-mobl2.ger.corp.intel.com unknown: [IGT] drm_mm: starting dynamic subtest drm_mm-drm_test_mm_frag Sep 13 15:14:55 jkrzyszt-mobl2.ger.corp.intel.com unknown: [IGT] drm_mm: finished subtest drm_mm-drm_test_mm_frag, SUCCESS Sep 13 15:14:55
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Remove runtime suspended boolean from intel_runtime_pm struct
== Series Details == Series: drm/i915: Remove runtime suspended boolean from intel_runtime_pm struct URL : https://patchwork.freedesktop.org/series/123637/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13624 -> Patchwork_123637v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_123637v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_123637v1, please notify your bug team (lgci.bug.fil...@intel.com) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/index.html Participating hosts (17 -> 38) -- Additional (21): fi-kbl-soraka fi-rkl-11600 bat-dg1-5 fi-pnv-d510 bat-rpls-1 fi-skl-6600u fi-bsw-n3050 bat-adlm-1 bat-adln-1 fi-ivb-3770 fi-bsw-nick fi-kbl-7567u bat-adlp-9 fi-skl-guc fi-glk-j4005 bat-mtlp-8 bat-jsl-1 bat-mtlp-6 fi-kbl-guc fi-kbl-x1275 fi-cfl-8109u Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_123637v1: ### IGT changes ### Possible regressions * igt@i915_suspend@basic-s3-without-i915: - bat-rpls-1: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html Known issues Here are the changes found in Patchwork_123637v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-mtlp-8: NOTRUN -> [SKIP][2] ([i915#9318]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html - bat-adlp-9: NOTRUN -> [SKIP][3] ([i915#9318]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/bat-adlp-9/igt@debugfs_t...@basic-hwmon.html - fi-rkl-11600: NOTRUN -> [SKIP][4] ([i915#9318]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/fi-rkl-11600/igt@debugfs_t...@basic-hwmon.html - bat-adln-1: NOTRUN -> [SKIP][5] ([i915#9318]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/bat-adln-1/igt@debugfs_t...@basic-hwmon.html - bat-adlm-1: NOTRUN -> [SKIP][6] ([i915#3826]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/bat-adlm-1/igt@debugfs_t...@basic-hwmon.html - bat-jsl-1: NOTRUN -> [SKIP][7] ([i915#9318]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html - bat-rpls-1: NOTRUN -> [SKIP][8] ([i915#9318]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/bat-rpls-1/igt@debugfs_t...@basic-hwmon.html - bat-mtlp-6: NOTRUN -> [SKIP][9] ([i915#9318]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/bat-mtlp-6/igt@debugfs_t...@basic-hwmon.html * igt@debugfs_test@read_all_entries: - fi-kbl-7567u: NOTRUN -> [ABORT][10] ([i915#8913]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/fi-kbl-7567u/igt@debugfs_test@read_all_entries.html * igt@fbdev@eof: - bat-adlm-1: NOTRUN -> [SKIP][11] ([i915#2582]) +3 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/bat-adlm-1/igt@fb...@eof.html * igt@fbdev@info: - fi-kbl-x1275: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1849]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/fi-kbl-x1275/igt@fb...@info.html - fi-kbl-guc: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1849]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/fi-kbl-guc/igt@fb...@info.html - bat-rpls-1: NOTRUN -> [SKIP][14] ([i915#1849] / [i915#2582]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/bat-rpls-1/igt@fb...@info.html - bat-adlm-1: NOTRUN -> [SKIP][15] ([i915#1849] / [i915#2582]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/bat-adlm-1/igt@fb...@info.html - bat-mtlp-6: NOTRUN -> [SKIP][16] ([i915#1849] / [i915#2582]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/bat-mtlp-6/igt@fb...@info.html * igt@fbdev@write: - bat-rpls-1: NOTRUN -> [SKIP][17] ([i915#2582]) +3 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/bat-rpls-1/igt@fb...@write.html - bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#2582]) +3 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123637v1/bat-mtlp-6/igt@fb...@write.html * igt@gem_huc_copy@huc-copy: - fi-cfl-8109u: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2190]) [19]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Remove runtime suspended boolean from intel_runtime_pm struct
== Series Details == Series: drm/i915: Remove runtime suspended boolean from intel_runtime_pm struct URL : https://patchwork.freedesktop.org/series/123637/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] [PATCH 2/7] drm/i915: Create a kernel context for GGTT updates
Create a separate kernel context if a platform requires
GGTT updates using MI_UPDATE_GTT blitter command.
Subsequent patch will introduce methods to update
GGTT using this bind context and MI_UPDATE_GTT blitter
command.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_engine.h | 2 ++
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 33 +++-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 ++
drivers/gpu/drm/i915/gt/intel_gt.c | 18 +++
drivers/gpu/drm/i915/gt/intel_gt.h | 2 ++
5 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index b58c30ac8ef0..40269e4c1e31 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -170,6 +170,8 @@ intel_write_status_page(struct intel_engine_cs *engine, int
reg, u32 value)
#define I915_GEM_HWS_SEQNO 0x40
#define I915_GEM_HWS_SEQNO_ADDR(I915_GEM_HWS_SEQNO *
sizeof(u32))
#define I915_GEM_HWS_MIGRATE (0x42 * sizeof(u32))
+#define I915_GEM_HWS_GGTT_BIND 0x46
+#define I915_GEM_HWS_GGTT_BIND_ADDR(I915_GEM_HWS_GGTT_BIND * sizeof(u32))
#define I915_GEM_HWS_PXP 0x60
#define I915_GEM_HWS_PXP_ADDR (I915_GEM_HWS_PXP * sizeof(u32))
#define I915_GEM_HWS_GSC 0x62
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index dfb69fc977a0..52a24f55cb57 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1419,6 +1419,20 @@ void intel_engine_destroy_pinned_context(struct
intel_context *ce)
intel_context_put(ce);
}
+static struct intel_context *
+create_ggtt_bind_context(struct intel_engine_cs *engine)
+{
+ static struct lock_class_key kernel;
+
+ /*
+* MI_UPDATE_GTT can insert up to 512 PTE entries and there could be
multiple
+* bind requets at a time so get a bigger ring.
+*/
+ return intel_engine_create_pinned_context(engine, engine->gt->vm,
SZ_512K,
+ I915_GEM_HWS_GGTT_BIND_ADDR,
+ , "ggtt_bind_context");
+}
+
static struct intel_context *
create_kernel_context(struct intel_engine_cs *engine)
{
@@ -1442,7 +1456,7 @@ create_kernel_context(struct intel_engine_cs *engine)
*/
static int engine_init_common(struct intel_engine_cs *engine)
{
- struct intel_context *ce;
+ struct intel_context *ce, *bce = NULL;
int ret;
engine->set_default_submission(engine);
@@ -1458,6 +1472,17 @@ static int engine_init_common(struct intel_engine_cs
*engine)
ce = create_kernel_context(engine);
if (IS_ERR(ce))
return PTR_ERR(ce);
+ /*
+* Create a separate pinned context for GGTT update with blitter engine
+* if a platform require such service. MI_UPDATE_GTT works on other
+* engines as well but BCS should be less busy engine so pick that for
+* GGTT updates.
+*/
+ if (engine->id == BCS0) {
+ bce = create_ggtt_bind_context(engine);
+ if (IS_ERR(bce))
+ return PTR_ERR(bce);
+ }
ret = measure_breadcrumb_dw(ce);
if (ret < 0)
@@ -1465,11 +1490,14 @@ static int engine_init_common(struct intel_engine_cs
*engine)
engine->emit_fini_breadcrumb_dw = ret;
engine->kernel_context = ce;
+ engine->bind_context = bce;
return 0;
err_context:
intel_engine_destroy_pinned_context(ce);
+ if (bce)
+ intel_engine_destroy_pinned_context(ce);
return ret;
}
@@ -1537,6 +1565,9 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
if (engine->kernel_context)
intel_engine_destroy_pinned_context(engine->kernel_context);
+ if (engine->bind_context)
+ intel_engine_destroy_pinned_context(engine->bind_context);
+
GEM_BUG_ON(!llist_empty(>barrier_tasks));
cleanup_status_page(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index a7e677598004..a8f527fab0f0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -416,6 +416,9 @@ struct intel_engine_cs {
struct llist_head barrier_tasks;
struct intel_context *kernel_context; /* pinned */
+ struct intel_context *bind_context; /* pinned, only for BCS0 */
+ /* mark the bind context's availability status */
+ bool bind_context_ready;
/**
* pinned_contexts_list: List of pinned contexts. This list is only
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 449f0b7fc843..cd0ff1597db9 100644
---
[Intel-gfx] [PATCH 7/7] drm/i915: Enable GGTT updates with binder in MTL
MTL can hang because of a HW bug while parallel reading/writing
from/to LMEM/GTTMMADR BAR so try to reduce GGTT update
related pci transactions with blitter command as recommended
for Wa_13010847436 and Wa_14019519902.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 4c89eb8d9af7..4fbed27ef0ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -23,7 +23,8 @@
bool i915_ggtt_require_binder(struct drm_i915_private *i915)
{
- return false;
+ /* Wa_13010847436 & Wa_14019519902 */
+ return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
}
static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)
--
2.41.0
[Intel-gfx] [PATCH 5/7] drm/i915: Implement GGTT update method with MI_UPDATE_GTT
Implement GGTT update method with blitter command, MI_UPDATE_GTT
and install those handlers if a platform requires that.
v2: Make sure we hold the GT wakeref and Blitter engine wakeref before
we call mutex_lock/intel_context_enter below. When GT/engine are not
awake, the intel_context_enter calls into some runtime pm function which
can end up with kmalloc/fs_reclaim. But trigger fs_reclaim holding a
mutex lock is not allowed because shrinker can also try to hold the same
mutex lock. It is a circular lock. So hold the GT/blitter engine wakeref
before calling mutex_lock, to fix the circular lock.
Signed-off-by: Nirmoy Das
Signed-off-by: Oak Zeng
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 235 +++
1 file changed, 235 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index dd0ed941441a..b94de7cebfce 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -15,18 +15,23 @@
#include "display/intel_display.h"
#include "gem/i915_gem_lmem.h"
+#include "intel_context.h"
#include "intel_ggtt_gmch.h"
+#include "intel_gpu_commands.h"
#include "intel_gt.h"
#include "intel_gt_regs.h"
#include "intel_pci_config.h"
+#include "intel_ring.h"
#include "i915_drv.h"
#include "i915_pci.h"
+#include "i915_request.h"
#include "i915_scatterlist.h"
#include "i915_utils.h"
#include "i915_vgpu.h"
#include "intel_gtt.h"
#include "gen8_ppgtt.h"
+#include "intel_engine_pm.h"
static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
unsigned long color,
@@ -252,6 +257,145 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
return pte;
}
+static bool should_update_ggtt_with_bind(struct i915_ggtt *ggtt)
+{
+ struct intel_gt *gt = ggtt->vm.gt;
+
+ return intel_gt_is_bind_context_ready(gt);
+}
+
+static struct intel_context *gen8_ggtt_bind_get_ce(struct i915_ggtt *ggtt)
+{
+ struct intel_context *ce;
+ struct intel_gt *gt = ggtt->vm.gt;
+
+ if (intel_gt_is_wedged(gt))
+ return NULL;
+
+ ce = gt->engine[BCS0]->bind_context;
+ GEM_BUG_ON(!ce);
+
+ /*
+* If the GT is not awake already at this stage then fallback
+* to pci based GGTT update otherwise __intel_wakeref_get_first()
+* would conflict with fs_reclaim trying to allocate memory while
+* doing rpm_resume().
+*/
+ if (!intel_gt_pm_get_if_awake(gt))
+ return NULL;
+
+ intel_engine_pm_get(ce->engine);
+
+ return ce;
+}
+
+static void gen8_ggtt_bind_put_ce(struct intel_context *ce)
+{
+ intel_engine_pm_put(ce->engine);
+ intel_gt_pm_put(ce->engine->gt);
+}
+
+static bool gen8_ggtt_bind_ptes(struct i915_ggtt *ggtt, u32 offset,
+ struct sg_table *pages, u32 num_entries,
+ const gen8_pte_t pte)
+{
+ struct i915_sched_attr attr = {};
+ struct intel_gt *gt = ggtt->vm.gt;
+ const gen8_pte_t scratch_pte = ggtt->vm.scratch[0]->encode;
+ struct sgt_iter iter;
+ struct i915_request *rq;
+ struct intel_context *ce;
+ u32 *cs;
+
+ if (!num_entries)
+ return true;
+
+ ce = gen8_ggtt_bind_get_ce(ggtt);
+ if (!ce)
+ return false;
+
+ if (pages)
+ iter = __sgt_iter(pages->sgl, true);
+
+ while (num_entries) {
+ int count = 0;
+ dma_addr_t addr;
+ /*
+* MI_UPDATE_GTT can update 512 entries in a single command but
+* that end up with engine reset, 511 works.
+*/
+ u32 n_ptes = min_t(u32, 511, num_entries);
+
+ if (mutex_lock_interruptible(>timeline->mutex))
+ goto put_ce;
+
+ intel_context_enter(ce);
+ rq = __i915_request_create(ce, GFP_NOWAIT | GFP_ATOMIC);
+ intel_context_exit(ce);
+ if (IS_ERR(rq)) {
+ GT_TRACE(gt, "Failed to get bind request\n");
+ mutex_unlock(>timeline->mutex);
+ goto put_ce;
+ }
+
+ cs = intel_ring_begin(rq, 2 * n_ptes + 2);
+ if (IS_ERR(cs)) {
+ GT_TRACE(gt, "Failed to ring space for GGTT bind\n");
+ i915_request_set_error_once(rq, PTR_ERR(cs));
+ /* once a request is created, it must be queued */
+ goto queue_err_rq;
+ }
+
+ *cs++ = MI_UPDATE_GTT | (2 * n_ptes);
+ *cs++ = offset << 12;
+
+ if (pages) {
+ for_each_sgt_daddr_next(addr, iter) {
+ if (count == n_ptes)
+ break;
+ *cs++ = lower_32_bits(pte | addr);
+
[Intel-gfx] [PATCH 6/7] drm/i915: Toggle binder context ready status
Toggle binder context ready status when needed.
To issue gpu commands, the driver must be primed to receive
requests. Maintain binder-based GGTT update disablement until driver
probing completes. Moreover, implement a temporary disablement
of blitter prior to entering suspend, followed by re-enablement
post-resume. This is acceptable as those transition periods are
mostly single threaded.
Signed-off-by: Nirmoy Das
Signed-off-by: Oak Zeng
---
drivers/gpu/drm/i915/i915_driver.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index f8dbee7a5af7..8cc289acdb39 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -815,6 +815,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
i915_welcome_messages(i915);
i915->do_release = true;
+ intel_gt_bind_context_set_ready(to_gt(i915), true);
return 0;
@@ -855,6 +856,7 @@ void i915_driver_remove(struct drm_i915_private *i915)
{
intel_wakeref_t wakeref;
+ intel_gt_bind_context_set_ready(to_gt(i915), false);
wakeref = intel_runtime_pm_get(>runtime_pm);
i915_driver_unregister(i915);
@@ -1077,6 +1079,8 @@ static int i915_drm_suspend(struct drm_device *dev)
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
pci_power_t opregion_target_state;
+ intel_gt_bind_context_set_ready(to_gt(dev_priv), false);
+
disable_rpm_wakeref_asserts(_priv->runtime_pm);
/* We do a lot of poking in a lot of registers, make sure they work
@@ -1264,6 +1268,7 @@ static int i915_drm_resume(struct drm_device *dev)
intel_gvt_resume(dev_priv);
enable_rpm_wakeref_asserts(_priv->runtime_pm);
+ intel_gt_bind_context_set_ready(to_gt(dev_priv), true);
return 0;
}
--
2.41.0
[Intel-gfx] [PATCH 4/7] drm/i915: Parameterize binder context creation
Add i915_ggtt_require_binder() to indicate that i915
needs to create binder context which will be used
by subsequent patch to enable i915_address_space vfuncs
that will use GPU commands to update GGTT.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 4
drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 52a24f55cb57..12af594e9164 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1478,7 +1478,7 @@ static int engine_init_common(struct intel_engine_cs
*engine)
* engines as well but BCS should be less busy engine so pick that for
* GGTT updates.
*/
- if (engine->id == BCS0) {
+ if (i915_ggtt_require_binder(engine->i915) && engine->id == BCS0) {
bce = create_ggtt_bind_context(engine);
if (IS_ERR(bce))
return PTR_ERR(bce);
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 13944a14ea2d..4c89eb8d9af7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -21,6 +21,10 @@
#include "intel_gt_regs.h"
#include "intel_gtt.h"
+bool i915_ggtt_require_binder(struct drm_i915_private *i915)
+{
+ return false;
+}
static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 41e530d0a4e9..b471edac2699 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -691,4 +691,6 @@ static inline struct sgt_dma {
return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) };
}
+bool i915_ggtt_require_binder(struct drm_i915_private *i915);
+
#endif
--
2.41.0
[Intel-gfx] [PATCH 3/7] drm/i915: Implement for_each_sgt_daddr_next
Implement a way to iterate over sgt with pre-initialized
sgt_iter state.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++
drivers/gpu/drm/i915/i915_scatterlist.h | 10 ++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 346ec8ec2edd..41e530d0a4e9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -171,6 +171,9 @@ struct intel_gt;
#define for_each_sgt_daddr(__dp, __iter, __sgt) \
__for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE)
+#define for_each_sgt_daddr_next(__dp, __iter) \
+ __for_each_daddr_next(__dp, __iter, I915_GTT_PAGE_SIZE)
+
struct i915_page_table {
struct drm_i915_gem_object *base;
union {
diff --git a/drivers/gpu/drm/i915/i915_scatterlist.h
b/drivers/gpu/drm/i915/i915_scatterlist.h
index 5a10c1a31183..6cf8a298849f 100644
--- a/drivers/gpu/drm/i915/i915_scatterlist.h
+++ b/drivers/gpu/drm/i915/i915_scatterlist.h
@@ -91,6 +91,16 @@ static inline struct scatterlist *__sg_next(struct
scatterlist *sg)
((__dp) = (__iter).dma + (__iter).curr), (__iter).sgp; \
(((__iter).curr += (__step)) >= (__iter).max) ?\
(__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
+/**
+ * __for_each_daddr_next - iterates over the device addresses with
pre-initialized iterator.
+ * @__dp: Device address (output)
+ * @__iter:'struct sgt_iter' (iterator state, external)
+ * @__step:step size
+ */
+#define __for_each_daddr_next(__dp, __iter, __step) \
+ for (; ((__dp) = (__iter).dma + (__iter).curr), (__iter).sgp; \
+(((__iter).curr += (__step)) >= (__iter).max) ?\
+(__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
/**
* for_each_sgt_page - iterate over the pages of the given sg_table
--
2.41.0
[Intel-gfx] [PATCH 1/7] drm/i915: Lift runtime-pm acquire callbacks out of intel_wakeref.mutex
From: Chris Wilson
When runtime pm is first woken, it will synchronously call the
registered callbacks for the device. These callbacks
may pull in their own forest of locks, which we do not want to
conflate with the intel_wakeref.mutex. A second minor benefit to
reducing the coverage of the mutex, is that it will reduce
contention for frequent sleeps and wakes (such as when being used
for soft-rc6).
Signed-off-by: Chris Wilson
Signed-off-by: Nirmoy Das
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/intel_wakeref.c | 43 ++--
1 file changed, 21 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_wakeref.c
b/drivers/gpu/drm/i915/intel_wakeref.c
index 718f2f1b6174..af7b4cb5b4d7 100644
--- a/drivers/gpu/drm/i915/intel_wakeref.c
+++ b/drivers/gpu/drm/i915/intel_wakeref.c
@@ -10,21 +10,11 @@
#include "intel_wakeref.h"
#include "i915_drv.h"
-static void rpm_get(struct intel_wakeref *wf)
-{
- wf->wakeref = intel_runtime_pm_get(>i915->runtime_pm);
-}
-
-static void rpm_put(struct intel_wakeref *wf)
-{
- intel_wakeref_t wakeref = fetch_and_zero(>wakeref);
-
- intel_runtime_pm_put(>i915->runtime_pm, wakeref);
- INTEL_WAKEREF_BUG_ON(!wakeref);
-}
-
int __intel_wakeref_get_first(struct intel_wakeref *wf)
{
+ intel_wakeref_t wakeref = intel_runtime_pm_get(>i915->runtime_pm);
+ int err = 0;
+
/*
* Treat get/put as different subclasses, as we may need to run
* the put callback from under the shrinker and do not want to
@@ -32,41 +22,50 @@ int __intel_wakeref_get_first(struct intel_wakeref *wf)
* upon acquiring the wakeref.
*/
mutex_lock_nested(>mutex, SINGLE_DEPTH_NESTING);
- if (!atomic_read(>count)) {
- int err;
- rpm_get(wf);
+ if (likely(!atomic_read(>count))) {
+ INTEL_WAKEREF_BUG_ON(wf->wakeref);
+ wf->wakeref = fetch_and_zero();
err = wf->ops->get(wf);
if (unlikely(err)) {
- rpm_put(wf);
- mutex_unlock(>mutex);
- return err;
+ wakeref = xchg(>wakeref, 0);
+ wake_up_var(>wakeref);
+ goto unlock;
}
smp_mb__before_atomic(); /* release wf->count */
}
atomic_inc(>count);
+ INTEL_WAKEREF_BUG_ON(atomic_read(>count) <= 0);
+
+unlock:
mutex_unlock(>mutex);
+ if (unlikely(wakeref))
+ intel_runtime_pm_put(>i915->runtime_pm, wakeref);
- INTEL_WAKEREF_BUG_ON(atomic_read(>count) <= 0);
- return 0;
+ return err;
}
static void intel_wakeref_put_last(struct intel_wakeref *wf)
{
+ intel_wakeref_t wakeref = 0;
+
INTEL_WAKEREF_BUG_ON(atomic_read(>count) <= 0);
if (unlikely(!atomic_dec_and_test(>count)))
goto unlock;
/* ops->put() must reschedule its own release on error/deferral */
if (likely(!wf->ops->put(wf))) {
- rpm_put(wf);
+ INTEL_WAKEREF_BUG_ON(!wf->wakeref);
+ wakeref = xchg(>wakeref, 0);
wake_up_var(>wakeref);
}
unlock:
mutex_unlock(>mutex);
+ if (wakeref)
+ intel_runtime_pm_put(>i915->runtime_pm, wakeref);
}
void __intel_wakeref_put_last(struct intel_wakeref *wf, unsigned long flags)
--
2.41.0
[Intel-gfx] [PATCH 0/7] Update GGTT with MI_UPDATE_GTT on MTL
Implement a way to update GGTT using MI_UPDATE_GTT command when possible for MTL as a suggested work around for HW bugs, Wa_13010847436 and Wa_14019519902. v2: Fix lockdep warning related to GT wakeref vs blitter engine wakeref. v3: Rearrange patches/diffs to fix code mixups(Andi) Test-with: 20230913094252.6246-1-nirmoy@intel.com Chris Wilson (1): drm/i915: Lift runtime-pm acquire callbacks out of intel_wakeref.mutex Nirmoy Das (6): drm/i915: Create a kernel context for GGTT updates drm/i915: Implement for_each_sgt_daddr_next drm/i915: Parameterize binder context creation drm/i915: Implement GGTT update method with MI_UPDATE_GTT drm/i915: Toggle binder context ready status drm/i915: Enable GGTT updates with binder in MTL drivers/gpu/drm/i915/gt/intel_engine.h | 2 + drivers/gpu/drm/i915/gt/intel_engine_cs.c| 33 ++- drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 + drivers/gpu/drm/i915/gt/intel_ggtt.c | 235 +++ drivers/gpu/drm/i915/gt/intel_gt.c | 18 ++ drivers/gpu/drm/i915/gt/intel_gt.h | 2 + drivers/gpu/drm/i915/gt/intel_gtt.c | 5 + drivers/gpu/drm/i915/gt/intel_gtt.h | 5 + drivers/gpu/drm/i915/i915_driver.c | 5 + drivers/gpu/drm/i915/i915_scatterlist.h | 10 + drivers/gpu/drm/i915/intel_wakeref.c | 43 ++-- 11 files changed, 338 insertions(+), 23 deletions(-) -- 2.41.0
[Intel-gfx] [PATCH 0/7] Update GGTT with MI_UPDATE_GTT on MTL
Implement a way to update GGTT using MI_UPDATE_GTT command when possible for MTL as a suggested work around for HW bugs, Wa_13010847436 and Wa_14019519902. v2: Fix lockdep warning related to GT wakeref vs blitter engine wakeref. v3: Rearrange patches/diffs to fix code mixups(Andi) Test-with: 20230913094252.6246-1-nirmoy@intel.com Chris Wilson (1): drm/i915: Lift runtime-pm acquire callbacks out of intel_wakeref.mutex Nirmoy Das (6): drm/i915: Create a kernel context for GGTT updates drm/i915: Implement for_each_sgt_daddr_next drm/i915: Parameterize binder context creation drm/i915: Implement GGTT update method with MI_UPDATE_GTT drm/i915: Toggle binder context ready status drm/i915: Enable GGTT updates with binder in MTL drivers/gpu/drm/i915/gt/intel_engine.h | 2 + drivers/gpu/drm/i915/gt/intel_engine_cs.c| 33 ++- drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 + drivers/gpu/drm/i915/gt/intel_ggtt.c | 235 +++ drivers/gpu/drm/i915/gt/intel_gt.c | 18 ++ drivers/gpu/drm/i915/gt/intel_gt.h | 2 + drivers/gpu/drm/i915/gt/intel_gtt.c | 5 + drivers/gpu/drm/i915/gt/intel_gtt.h | 5 + drivers/gpu/drm/i915/i915_driver.c | 5 + drivers/gpu/drm/i915/i915_scatterlist.h | 10 + drivers/gpu/drm/i915/intel_wakeref.c | 43 ++-- 11 files changed, 338 insertions(+), 23 deletions(-) -- 2.41.0
Re: [Intel-gfx] [PATCH i-g-t v2 05/17] lib/kunit: Fix illegal igt_fail() calls inside subtest body
On Monday, 11 September 2023 13:57:29 CEST Mauro Carvalho Chehab wrote:
> On Mon, 11 Sep 2023 11:28:32 +0200
> Janusz Krzysztofik wrote:
>
> > Hi Mauro,
> >
> > Thanks for review.
> >
> > On Monday, 11 September 2023 10:52:51 CEST Mauro Carvalho Chehab wrote:
> > > On Fri, 8 Sep 2023 14:32:39 +0200
> > > Janusz Krzysztofik wrote:
> > >
> > > > In a body of a subtest with dynamic sub-subtests, it is illegal to
call
> > > > igt_fail() and its variants from outside of a dynamic sub-subtest
body.
> > > > On the other hand, it is perfectly legal to call either igt_skip() and
> > > > friends or __igt_abort() or its variant from there.
> > > >
> > > > In the current implementation of igt_kunit(), there are several places
> > > > where igt_fail() is called despite being illegal. Moreover, it is
called
> > > > with IGT_EXIT_ABORT as an argument with no good reason for using such
> > > > aggressive method that forces CI to trigger system reboot (in most
cases
> > > > igt_runner can decide if abort is required).
> > > >
> > > > Follow igt_kselftests() pattern more closely, where similar setup and
> > > > cleanup operations are performed but their potential errors are
processed
> > > > in a more friendly way. Move common cleanup and their corresponding
setup
> > > > steps out of the subtest body. Place the latter as requirements in a
> > > > preceding igt_fixture section. Replace remaining illegal igt_fail()
calls
> > > > with more friendly skips. Let igt_runner decide if abort is needed.
> > > >
> > > > Signed-off-by: Janusz Krzysztofik
> > > > ---
> > > > lib/igt_kmod.c | 75 ++
+---
> > > > 1 file changed, 22 insertions(+), 53 deletions(-)
> > > >
> > > > diff --git a/lib/igt_kmod.c b/lib/igt_kmod.c
> > > > index 1d1cd51170..78b8eb8f53 100644
> > > > --- a/lib/igt_kmod.c
> > > > +++ b/lib/igt_kmod.c
> > ...
> > > > @@ -825,24 +793,21 @@ static void __igt_kunit(const char *module_name,
const char *opts)
> > > > }
> > > > }
> > > >
> > > > -unload:
> > > > - igt_ktest_end();
> > > > -
> > > > - igt_ktest_fini();
> > > > -
> > > > - igt_skip_on_f(skip, "Skipping test, as probing KUnit module
failed\n");
> > > > -
> > > > - if (fail)
> > > > - igt_fail(IGT_EXIT_ABORT);
> > > > -
> > > > ret = ktap_parser_stop();
> > > >
> > > > - if (ret != 0)
> > > > - igt_fail(IGT_EXIT_ABORT);
> > > > + igt_skip_on_f(ret, "KTAP parser failed\n");
> > > > }
> > > >
> > > > void igt_kunit(const char *module_name, const char *name, const char
*opts)
> > > > {
> > > > + struct igt_ktest tst;
> > > > +
> > > > + if (igt_ktest_init(, module_name) != 0)
> > > > + return;
> > >
> > > Shouldn't it be calling igt_skip() here too?
> >
> > Maybe yes. I've chosen to follow the algorithm used in igt_kselftest.
There
> > was an igt_skip() variant there initially but in 2017 that was converted
to
> > the current return only by Peter with IGT commit 9f92893b11e8 ("lib/
igt_kmod:
> > Don't call igt_assert or igt_require without a fixture"). However,
> > justification for dropping igt_require() instead of calling it from an
> > igt_fixture section may not apply to kunit modules:
> >
> > "If kmod_module_new_from_name fails, ... return normally from
igt_kselftest,
> > matching behaviour when the module loading is successful but it doesn't
> > contain selftests."
> >
> > While i915 could be built with no selftests included, a kunit module
without
> > any tests doesn't make sense, then silent return may be not what we need.
>
> Yeah, selftests are handled on a different way with regards to module
> probe, so I guess we need the igt_skip there if modprobe fails.
After having a closer look at it, I think that igt_ktest_init() has nothing to
do with actual modprobe, and it can fail only on either no memory or if
module_name == NULL. Anyway, I'll make the subtest skip if it fails.
> Well, you can probably simulate it by renaming a Kunit module
> and see how IGT will handle that with the current code and with
> igt_skip().
Yes, I've tired, and my results have confirmed my conclusions from code
review. But more important, I've found an issue in patch 15/17, "Parse KTAP
report from the main process thread", that can cause first read() to wait
infinitely, unless interrupted, if modprobe fails. I've already developed a
working fix that interrupts that read() on modprobe failure, and I'll include
it in next version of the series.
Thanks,
Janusz
>
> (Btw, I intend to review the other patches on this series, but need
> some time to do tests, as some changes here are not trivial)
>
> Regards,
> Mauro
>
Re: [Intel-gfx] [PATCH v7 0/3] drm/bridge_connector: implement OOB HPD handling
On 25/08/2023 02:56, Dmitry Baryshkov wrote: Note, numbering for this series starts from v5, since there were several revisions for this patchset under a different series title ([1]). USB altmodes code would send OOB notifications to the drm_connector specified in the device tree. However as the MSM DP driver uses drm_bridge_connector, there is no way to receive these event directly. Implement a bridge between oob_hotplug_event and drm_bridge's hpd_notify. Merge strategy: since this series touches i915 code, it might make sense to merge all three patches through drm-intel. Dear drm-misc and drm-intel maintainers. Since the merge window has ended and the trees are fully open for the patches, I'd like to massage this patch series. We have R-B on all three patches. Heikki has acked the first patch, so it seems to be fine from the i915 point of view. Is it fine to be merged via drm-misc? Would you like to pick it up into drm-intel? [1] https://patchwork.freedesktop.org/series/103449/ Changes since v6: - Rebased on top of linux-next. Fixed the freshly added new drm_connector_oob_hotplug_event() call. Changes since v5: - Fixed checkpatch warning in the first patch (noted by intel-gfx CI). Changes since v4: - Picked up the patchset - Dropped msm-specific patches - Changed drm_bridge_connector_oob_hotplug_event to call connector's HPD callback directly, rather than going through the last bridge's hpd_notify - Added proper fwnode for the drm_bridge_connector Bjorn Andersson (1): drm: Add HPD state to drm_connector_oob_hotplug_event() Dmitry Baryshkov (2): drm/bridge_connector: stop filtering events in drm_bridge_connector_hpd_cb() drm/bridge_connector: implement oob_hotplug_event drivers/gpu/drm/drm_bridge_connector.c| 34 ++- drivers/gpu/drm/drm_connector.c | 6 ++-- .../gpu/drm/i915/display/intel_display_core.h | 3 ++ drivers/gpu/drm/i915/display/intel_dp.c | 17 -- drivers/usb/typec/altmodes/displayport.c | 17 +- include/drm/drm_connector.h | 6 ++-- 6 files changed, 60 insertions(+), 23 deletions(-) -- With best wishes Dmitry
Re: [Intel-gfx] [PATCH 00/12] drm/i915: Populate connector->ddc always
On Tue, Aug 29, 2023 at 02:39:08PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Populate connector->ddc for all output types that don't already > do so, and clean up a bunch of code as a result of having the > ddc i2c adapter in easy reach. And this also provides the sysfs > "ddc" symlink. > > There are potentially a few oddball (mostly DVI-I) cases where > the connector detection/EDID read uses an alternate DDC bus > internally, and so for those the symlink might not point at the > correct i2c adapter. I'm not interested in spending extra brain > cells on those, so we'll leave them as is for now. > > Ville Syrjälä (12): > drm: Reorder drm_sysfs_connector_remove() vs. > drm_debugfs_connector_remove() > drm/sysfs: Register "ddc" symlink later Maarten/Maxime/Thomas can I get an ack for merging these two via drm-intel-next? Would avoid having to wait for a backmerge... > drm/i915: Call the DDC bus i2c adapter "ddc" > drm/i915/lvds: Populate connector->ddc > drm/i915/crt: Populate connector->ddc > drm/i915/dvo: Populate connector->ddc > drm/i915/dp: Populate connector->ddc > drm/i915/mst: Populate connector->ddc > drm/i915/hdmi: Use connector->ddc everwhere > drm/i915/hdmi: Nuke hdmi->ddc_bus > drm/i915/hdmi: Remove old i2c symlink > drm/i915/sdvo: Constify mapping structs > > drivers/gpu/drm/drm_connector.c | 11 ++- > drivers/gpu/drm/drm_internal.h| 2 + > drivers/gpu/drm/drm_sysfs.c | 22 +++-- > .../gpu/drm/i915/display/intel_connector.c| 6 +- > .../gpu/drm/i915/display/intel_connector.h| 2 +- > drivers/gpu/drm/i915/display/intel_crt.c | 38 +++ > drivers/gpu/drm/i915/display/intel_ddi.c | 5 +- > .../drm/i915/display/intel_display_types.h| 1 - > drivers/gpu/drm/i915/display/intel_dp.c | 9 +- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +- > drivers/gpu/drm/i915/display/intel_dvo.c | 11 +-- > drivers/gpu/drm/i915/display/intel_hdmi.c | 98 ++- > drivers/gpu/drm/i915/display/intel_lspcon.c | 14 +-- > drivers/gpu/drm/i915/display/intel_lvds.c | 23 +++-- > drivers/gpu/drm/i915/display/intel_sdvo.c | 6 +- > 15 files changed, 119 insertions(+), 135 deletions(-) > > -- > 2.41.0 -- Ville Syrjälä Intel
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Implement GGTT update method with MI_UPDATE_GTT
On 9/7/2023 3:48 PM, Andi Shyti wrote: Hi Nirmoy, On Wed, Sep 06, 2023 at 01:31:20PM +0200, Nirmoy Das wrote: Implement GGTT update method with blitter command, MI_UPDATE_GTT and install those handlers if a platform requires that. v2: Make sure we hold the GT wakeref and Blitter engine wakeref before we call mutex_lock/intel_context_enter below. When GT/engine are not awake, the intel_context_enter calls into some runtime pm function which can end up with kmalloc/fs_reclaim. But trigger fs_reclaim holding a mutex lock is not allowed because shrinker can also try to hold the same mutex lock. It is a circular lock. So hold the GT/blitter engine wakeref before calling mutex_lock, to fix the circular lock. Thanks for the explanation here. Signed-off-by: Nirmoy Das Signed-off-by: Oak Zeng [...] all looks good [...] +#define for_each_sgt_daddr_next(__dp, __iter) \ + __for_each_daddr_next(__dp, __iter, I915_GTT_PAGE_SIZE) + should this go in the previous patch? Yes, I think so too. Will move it to the previous one. Andi
Re: [Intel-gfx] [PATCH 2/5] drm/i915: Create a kernel context for GGTT updates
On 9/7/2023 3:41 PM, Andi Shyti wrote:
Hi Nirmoy,
[...]
+ /* mark the bind context's availability status */
+ bool bind_context_ready;
Do we need some locking here?
bind_context_ready is changed in suspend/resume or after mod probe so no need to
worry about locking here.
/**
* pinned_contexts_list: List of pinned contexts. This list is only
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 449f0b7fc843..cd0ff1597db9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1019,3 +1019,21 @@ enum i915_map_type intel_gt_coherent_map_type(struct
intel_gt *gt,
else
return I915_MAP_WC;
}
+
+void intel_gt_bind_context_set_ready(struct intel_gt *gt, bool ready)
+{
+ struct intel_engine_cs *engine = gt->engine[BCS0];
+
+ if (engine && engine->bind_context)
+ engine->bind_context_ready = ready;
+}
+
+bool intel_gt_is_bind_context_ready(struct intel_gt *gt)
+{
+ struct intel_engine_cs *engine = gt->engine[BCS0];
+
+ if (engine)
+ return engine->bind_context_ready;
+
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 239848bcb2a4..9e70e625cebc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -180,4 +180,6 @@ enum i915_map_type intel_gt_coherent_map_type(struct
intel_gt *gt,
struct drm_i915_gem_object *obj,
bool always_coherent);
+void intel_gt_bind_context_set_ready(struct intel_gt *gt, bool ready);
+bool intel_gt_is_bind_context_ready(struct intel_gt *gt);
Can you put all this part in patch 4 or make it a separate patch?
This patch contains the new member intel_engine_cs->bind_context_ready
which is why I added these two function in this.
Probably it makes sense to move only i915_ggtt_require_binder() out of
this patch ?
Regards,
Nirmoy
Andi
Re: [Intel-gfx] [PATCH] drm/i915: Remove runtime suspended boolean from intel_runtime_pm struct
On Wed, 13 Sep 2023, Jouni Högander wrote:
> It's not necessary to carry separate suspended status information in
> intel_runtime_pm struct as this information is already in underlying device
> structure. Remove it and use pm_runtime_suspended() to obtain suspended
> status information when needed.
I started wondering if this is racy, and my conclusion is that it's
"less" racy than the original. rpm->suspended gets toggled in the middle
of the suspend/resume sequences. So it could be halfway. Dunno if
anything *after* those toggles depends on the state having been changed
already; didn't find any. Maybe Imre has a better idea.
Also, pm_runtime_suspended() seems more reliable when suspend/resume
fails.
Acked-by: Jani Nikula
>
> Cc: Jani Nikula
> Cc: Imre Deak
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
> drivers/gpu/drm/i915/i915_driver.c | 3 ---
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c| 1 -
> drivers/gpu/drm/i915/intel_runtime_pm.h| 4 ++--
> 5 files changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 68cf5e6b0b46..889bb26009a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -216,7 +216,7 @@ bool __intel_display_power_is_enabled(struct
> drm_i915_private *dev_priv,
> struct i915_power_well *power_well;
> bool is_enabled;
>
> - if (dev_priv->runtime_pm.suspended)
> + if (pm_runtime_suspended(dev_priv->drm.dev))
> return false;
>
> is_enabled = true;
> diff --git a/drivers/gpu/drm/i915/i915_driver.c
> b/drivers/gpu/drm/i915/i915_driver.c
> index f8dbee7a5af7..cd98ee740976 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -1569,8 +1569,6 @@ static int intel_runtime_suspend(struct device *kdev)
> if (root_pdev)
> pci_d3cold_disable(root_pdev);
>
> - rpm->suspended = true;
> -
> /*
>* FIXME: We really should find a document that references the arguments
>* used below!
> @@ -1621,7 +1619,6 @@ static int intel_runtime_resume(struct device *kdev)
> disable_rpm_wakeref_asserts(rpm);
>
> intel_opregion_notify_adapter(dev_priv, PCI_D0);
> - rpm->suspended = false;
>
> root_pdev = pcie_find_root_port(pdev);
> if (root_pdev)
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 4008bb09fdb5..a60bab177c55 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1972,7 +1972,7 @@ static void capture_gen(struct i915_gpu_coredump *error)
> struct drm_i915_private *i915 = error->i915;
>
> error->wakelock = atomic_read(>runtime_pm.wakeref_count);
> - error->suspended = i915->runtime_pm.suspended;
> + error->suspended = pm_runtime_suspended(i915->drm.dev);
>
> error->iommu = i915_vtd_active(i915);
> error->reset_count = i915_reset_count(>gpu_error);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 6d8e5e5c0cba..8743153fad87 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -652,7 +652,6 @@ void intel_runtime_pm_init_early(struct intel_runtime_pm
> *rpm)
>
> rpm->kdev = kdev;
> rpm->available = HAS_RUNTIME_PM(i915);
> - rpm->suspended = false;
> atomic_set(>wakeref_count, 0);
>
> init_intel_runtime_pm_wakeref(rpm);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h
> b/drivers/gpu/drm/i915/intel_runtime_pm.h
> index 764b183ae452..f79cda7a2503 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.h
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.h
> @@ -6,6 +6,7 @@
> #ifndef __INTEL_RUNTIME_PM_H__
> #define __INTEL_RUNTIME_PM_H__
>
> +#include
> #include
>
> #include "intel_wakeref.h"
> @@ -43,7 +44,6 @@ struct intel_runtime_pm {
> atomic_t wakeref_count;
> struct device *kdev; /* points to i915->drm.dev */
> bool available;
> - bool suspended;
> bool irqs_enabled;
> bool no_wakeref_tracking;
>
> @@ -110,7 +110,7 @@ intel_rpm_wakelock_count(int wakeref_count)
> static inline void
> assert_rpm_device_not_suspended(struct intel_runtime_pm *rpm)
> {
> - WARN_ONCE(rpm->suspended,
> + WARN_ONCE(pm_runtime_suspended(rpm->kdev),
> "Device suspended during HW access\n");
> }
--
Jani Nikula, Intel
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/cx0: Add step for programming msgbus timer (rev2)
Quoting Patchwork (2023-09-12 19:24:10-03:00) >== Series Details == > >Series: drm/i915/cx0: Add step for programming msgbus timer (rev2) >URL : https://patchwork.freedesktop.org/series/123551/ >State : failure > >== Summary == > >CI Bug Log - changes from CI_DRM_13623_full -> Patchwork_123551v2_full > > >Summary >--- > > **FAILURE** > > Serious unknown changes coming with Patchwork_123551v2_full absolutely need > to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_123551v2_full, please notify your bug team > (lgci.bug.fil...@intel.com) to allow them > to document this new failure mode, which will reduce false positives in CI. > > > >Participating hosts (9 -> 9) >-- > > No changes in participating hosts > >Possible new issues >--- > > Here are the unknown changes that may have been introduced in > Patchwork_123551v2_full: > >### IGT changes ### > > Possible regressions > > * igt@gem_eio@in-flight-contexts-10ms: >- shard-snb: [PASS][1] -> [FAIL][2] > [1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-snb6/igt@gem_...@in-flight-contexts-10ms.html > [2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123551v2/shard-snb4/igt@gem_...@in-flight-contexts-10ms.html > > * igt@gen9_exec_parse@allowed-single: >- shard-apl: [PASS][3] -> [INCOMPLETE][4] > [3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-apl4/igt@gen9_exec_pa...@allowed-single.html > [4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123551v2/shard-apl6/igt@gen9_exec_pa...@allowed-single.html > > * igt@kms_rotation_crc@primary-rotation-270: >- shard-rkl: [PASS][5] -> [INCOMPLETE][6] +1 other test incomplete > [5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-rkl-2/igt@kms_rotation_...@primary-rotation-270.html > [6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123551v2/shard-rkl-1/igt@kms_rotation_...@primary-rotation-270.html > > * igt@kms_universal_plane@cursor-fb-leak-pipe-a: >- shard-glk: [PASS][7] -> [FAIL][8] > [7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-glk1/igt@kms_universal_pl...@cursor-fb-leak-pipe-a.html > [8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123551v2/shard-glk3/igt@kms_universal_pl...@cursor-fb-leak-pipe-a.html > > * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend: >- shard-dg2: [PASS][9] -> [INCOMPLETE][10] > [9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-dg2-1/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html > [10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123551v2/shard-dg2-5/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html > None of those should be related to this patch since those machines do not use the C10 or C20 PHYs. Gustavo Sousa > >Known issues > > > Here are the changes found in Patchwork_123551v2_full that come from known > issues: > >### IGT changes ### > > Issues hit > > * igt@api_intel_bb@object-reloc-keep-cache: >- shard-dg2: NOTRUN -> [SKIP][11] ([i915#8411]) > [11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123551v2/shard-dg2-7/igt@api_intel...@object-reloc-keep-cache.html > > * igt@api_intel_bb@object-reloc-purge-cache: >- shard-mtlp: NOTRUN -> [SKIP][12] ([i915#8411]) > [12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123551v2/shard-mtlp-4/igt@api_intel...@object-reloc-purge-cache.html > > * igt@device_reset@cold-reset-bound: >- shard-dg2: NOTRUN -> [SKIP][13] ([i915#7701]) > [13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123551v2/shard-dg2-7/igt@device_re...@cold-reset-bound.html > > * igt@drm_fdinfo@most-busy-idle-check-all@vecs1: >- shard-dg2: NOTRUN -> [SKIP][14] ([i915#8414]) +9 other tests > skip > [14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123551v2/shard-dg2-7/igt@drm_fdinfo@most-busy-idle-check-...@vecs1.html > > * igt@feature_discovery@psr1: >- shard-dg2: NOTRUN -> [SKIP][15] ([i915#658]) > [15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123551v2/shard-dg2-10/igt@feature_discov...@psr1.html > > * igt@gem_close_race@multigpu-basic-process: >- shard-mtlp: NOTRUN -> [SKIP][16] ([i915#7697]) > [16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123551v2/shard-mtlp-4/igt@gem_close_r...@multigpu-basic-process.html > > * igt@gem_close_race@multigpu-basic-threads: >- shard-dg2: NOTRUN -> [SKIP][17] ([i915#7697]) > [17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123551v2/shard-dg2-6/igt@gem_close_r...@multigpu-basic-threads.html > > * igt@gem_create@create-ext-cpu-access-big: >- shard-dg2: NOTRUN -> [ABORT][18] ([i915#7461]) >
Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/lnl: FBC is supported with per pixel alpha
Hi Ville,
It was confirmed by Jani Nikula that it is 20. Here is his comments.
" display ver 20 is what the hardware reports to us. the current info is at
bspecb70821 if you scroll down to "LNL GMD Architecture IDs"
"
Br
Vinod
From: Ville Syrjälä
Sent: Wednesday, September 13, 2023 1:38:23 PM
To: Govindapillai, Vinod
Cc: intel...@lists.freedesktop.org ; Roper,
Matthew D ; intel-gfx@lists.freedesktop.org
; Syrjala, Ville
Subject: Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/lnl: FBC is supported with per
pixel alpha
On Mon, Sep 04, 2023 at 02:55:17PM +0300, Vinod Govindapillai wrote:
> For LNL onwards, FBC can be supported on planes with per
> pixel alpha
>
> Bspec: 69560
> Signed-off-by: Vinod Govindapillai
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index a3999ad95a19..c0e4caec03ea 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1209,7 +1209,8 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
>return 0;
>}
>
> - if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
> + if (DISPLAY_VER(i915) < 20 &&
Bspec still says 15. Someone needs to figure this mess out for
all LNL patches.
> + plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
>fb->format->has_alpha) {
We would have already rejected the pixel format earlier, so atm this
check is redundant.
>plane_state->no_fbc_reason = "per-pixel alpha not supported";
>return 0;
> --
> 2.34.1
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v4 2/2] drm/i915/lnl: FBC is supported with per pixel alpha
On Mon, Sep 04, 2023 at 02:55:17PM +0300, Vinod Govindapillai wrote:
> For LNL onwards, FBC can be supported on planes with per
> pixel alpha
>
> Bspec: 69560
> Signed-off-by: Vinod Govindapillai
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index a3999ad95a19..c0e4caec03ea 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1209,7 +1209,8 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
> return 0;
> }
>
> - if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
> + if (DISPLAY_VER(i915) < 20 &&
Bspec still says 15. Someone needs to figure this mess out for
all LNL patches.
> + plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
> fb->format->has_alpha) {
We would have already rejected the pixel format earlier, so atm this
check is redundant.
> plane_state->no_fbc_reason = "per-pixel alpha not supported";
> return 0;
> --
> 2.34.1
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH] drm/i915/gt: skip WA verfication for GEN7_MISCCPCTL on DG2
On 12.09.2023 23:05, Matt Roper wrote: On Tue, Sep 12, 2023 at 09:35:21AM +0200, Andrzej Hajda wrote: Some DG2 firmware locks this register for modification. Using wa_add with read_mask 0 allows to skip checks of such registers. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 70071ead0659cc..1d1474ad945e0c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1597,8 +1597,11 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) /* Wa_14014830051:dg2 */ wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); - /* Wa_14015795083 */ - wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); + /* Wa_14015795083 Minor nitpick: kernel coding style says that "/*" should be on a line by itself for multi-line comments. Aside from that, Reviewed-by: Matt Roper Thanks for both r-b. Pushed with adjusted comment. Regards Andrzej Matt +* Skip verification for possibly locked register. +*/ + wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, + 0, 0, false); /* Wa_18018781329 */ wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); -- 2.34.1
[Intel-gfx] [PATCH] drm/i915: Remove runtime suspended boolean from intel_runtime_pm struct
It's not necessary to carry separate suspended status information in
intel_runtime_pm struct as this information is already in underlying device
structure. Remove it and use pm_runtime_suspended() to obtain suspended
status information when needed.
Cc: Jani Nikula
Cc: Imre Deak
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/i915_driver.c | 3 ---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/intel_runtime_pm.c| 1 -
drivers/gpu/drm/i915/intel_runtime_pm.h| 4 ++--
5 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 68cf5e6b0b46..889bb26009a2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -216,7 +216,7 @@ bool __intel_display_power_is_enabled(struct
drm_i915_private *dev_priv,
struct i915_power_well *power_well;
bool is_enabled;
- if (dev_priv->runtime_pm.suspended)
+ if (pm_runtime_suspended(dev_priv->drm.dev))
return false;
is_enabled = true;
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index f8dbee7a5af7..cd98ee740976 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1569,8 +1569,6 @@ static int intel_runtime_suspend(struct device *kdev)
if (root_pdev)
pci_d3cold_disable(root_pdev);
- rpm->suspended = true;
-
/*
* FIXME: We really should find a document that references the arguments
* used below!
@@ -1621,7 +1619,6 @@ static int intel_runtime_resume(struct device *kdev)
disable_rpm_wakeref_asserts(rpm);
intel_opregion_notify_adapter(dev_priv, PCI_D0);
- rpm->suspended = false;
root_pdev = pcie_find_root_port(pdev);
if (root_pdev)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 4008bb09fdb5..a60bab177c55 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1972,7 +1972,7 @@ static void capture_gen(struct i915_gpu_coredump *error)
struct drm_i915_private *i915 = error->i915;
error->wakelock = atomic_read(>runtime_pm.wakeref_count);
- error->suspended = i915->runtime_pm.suspended;
+ error->suspended = pm_runtime_suspended(i915->drm.dev);
error->iommu = i915_vtd_active(i915);
error->reset_count = i915_reset_count(>gpu_error);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6d8e5e5c0cba..8743153fad87 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -652,7 +652,6 @@ void intel_runtime_pm_init_early(struct intel_runtime_pm
*rpm)
rpm->kdev = kdev;
rpm->available = HAS_RUNTIME_PM(i915);
- rpm->suspended = false;
atomic_set(>wakeref_count, 0);
init_intel_runtime_pm_wakeref(rpm);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h
b/drivers/gpu/drm/i915/intel_runtime_pm.h
index 764b183ae452..f79cda7a2503 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.h
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.h
@@ -6,6 +6,7 @@
#ifndef __INTEL_RUNTIME_PM_H__
#define __INTEL_RUNTIME_PM_H__
+#include
#include
#include "intel_wakeref.h"
@@ -43,7 +44,6 @@ struct intel_runtime_pm {
atomic_t wakeref_count;
struct device *kdev; /* points to i915->drm.dev */
bool available;
- bool suspended;
bool irqs_enabled;
bool no_wakeref_tracking;
@@ -110,7 +110,7 @@ intel_rpm_wakelock_count(int wakeref_count)
static inline void
assert_rpm_device_not_suspended(struct intel_runtime_pm *rpm)
{
- WARN_ONCE(rpm->suspended,
+ WARN_ONCE(pm_runtime_suspended(rpm->kdev),
"Device suspended during HW access\n");
}
--
2.34.1
[Intel-gfx] ✗ Fi.CI.BUILD: failure for linux-next: manual merge of the drm-misc tree with Linus' tree (rev3)
== Series Details == Series: linux-next: manual merge of the drm-misc tree with Linus' tree (rev3) URL : https://patchwork.freedesktop.org/series/60886/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/60886/revisions/3/mbox/ not applied Applying: linux-next: manual merge of the drm-misc tree with Linus' tree error: corrupt patch at line 11 error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 linux-next: manual merge of the drm-misc tree with Linus' tree When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
Re: [Intel-gfx] linux-next: manual merge of the drm-misc tree with Linus' tree
On Wed, Sep 13, 2023 at 11:09:39AM +1000, Stephen Rothwell wrote:
> Today's linux-next merge of the drm-misc tree got a conflict in:
>
> drivers/gpu/drm/mediatek/mtk_dpi.c
>
> between commits:
>
> 47d4bb6bbcdb ("drm/mediatek: mtk_dpi: Simplify with devm_drm_bridge_add()")
> 90c95c3892dd ("drm/mediatek: mtk_dpi: Switch to .remove_new() void
> callback")
>
> from Linus' tree and commit:
>
> c04ca6bbb7ea ("drm/mediatek: Convert to platform remove callback returning
> void")
>
> from the drm-misc tree.
>
> I fixed it up (the latter is the same as 90c95c3892dd)
That's not entirely true:
uwe@taurus:~/gsrc/linux$ git show --oneline --stat 90c95c3892dd
90c95c3892dd drm/mediatek: mtk_dpi: Switch to .remove_new() void callback
drivers/gpu/drm/mediatek/mtk_dpi.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
uwe@taurus:~/gsrc/linux$ git show --oneline --stat c04ca6bbb7ea
c04ca6bbb7ea drm/mediatek: Convert to platform remove callback returning void
drivers/gpu/drm/mediatek/mtk_disp_aal.c | 6 ++
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++
drivers/gpu/drm/mediatek/mtk_disp_color.c | 6 ++
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 6 ++
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 6 ++
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++
drivers/gpu/drm/mediatek/mtk_dp.c | 6 ++
drivers/gpu/drm/mediatek/mtk_dpi.c| 6 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.c| 6 ++
drivers/gpu/drm/mediatek/mtk_dsi.c| 6 ++
drivers/gpu/drm/mediatek/mtk_hdmi.c | 5 ++---
drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c | 6 ++
drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 5 ++---
14 files changed, 28 insertions(+), 54 deletions(-)
But yes, restricted to drivers/gpu/drm/mediatek/mtk_dpi.c the patches do
the same (but have a different base, so there is some fuzz):
$ diff -u <(git show c04ca6bbb7ea drivers/gpu/drm/mediatek/mtk_dpi.c ) <(git
show 90c95c3892dd)
--- /dev/fd/63 2023-09-13 10:22:37.368055450 +0200
+++ /dev/fd/62 2023-09-13 10:22:37.372055516 +0200
@@ -1,46 +1,36 @@
-commit c04ca6bbb7ea6ea7cba9ba8d3d4d4c767008d189
-Author: Uwe Kleine-König
-Date: Sun May 7 18:25:52 2023 +0200
+commit 90c95c3892dde019182ceac984d4ca1f3c85844b
+Author: AngeloGioacchino Del Regno
+Date: Wed Jul 26 10:22:43 2023 +0200
[...]
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
-index 28bdb1f427ff..0ef722c24150 100644
+index e9c5a0f44537..3a140498c98a 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
-@@ -1101,14 +1101,12 @@ static int mtk_dpi_probe(struct platform_device *pdev)
+@@ -1087,11 +1087,9 @@ static int mtk_dpi_probe(struct platform_device *pdev)
return 0;
}
-static int mtk_dpi_remove(struct platform_device *pdev)
+static void mtk_dpi_remove(struct platform_device *pdev)
{
- struct mtk_dpi *dpi = platform_get_drvdata(pdev);
-
component_del(>dev, _dpi_component_ops);
- drm_bridge_remove(>bridge);
-
- return 0;
}
static const struct of_device_id mtk_dpi_of_ids[] = {
-@@ -1139,7 +1137,7 @@ MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
+@@ -1122,7 +1120,7 @@ MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
struct platform_driver mtk_dpi_driver = {
.probe = mtk_dpi_probe,
e44dd16393896b2545a6d57b2c11381fe7628aa0 looks right.
Best regards and thanks,
Uwe
--
Pengutronix e.K. | Uwe Kleine-König|
Industrial Linux Solutions | https://www.pengutronix.de/ |
signature.asc
Description: PGP signature
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Prevent error pointer dereference
== Series Details == Series: drm/i915/gt: Prevent error pointer dereference URL : https://patchwork.freedesktop.org/series/123628/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13623 -> Patchwork_123628v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_123628v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_123628v1, please notify your bug team (lgci.bug.fil...@intel.com) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v1/index.html Participating hosts (39 -> 24) -- Additional (1): bat-adlm-1 Missing(16): fi-kbl-soraka fi-kbl-7567u fi-rkl-11600 bat-kbl-2 bat-dg1-5 fi-skl-guc bat-dg2-13 fi-cfl-guc fi-snb-2520m fi-ilk-650 fi-hsw-4770 fi-kbl-x1275 fi-cfl-8109u fi-elk-e7500 bat-rpls-1 fi-blb-e6850 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_123628v1: ### IGT changes ### Possible regressions * igt@gem_exec_fence@basic-await@vcs0: - bat-atsm-1: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/bat-atsm-1/igt@gem_exec_fence@basic-aw...@vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v1/bat-atsm-1/igt@gem_exec_fence@basic-aw...@vcs0.html Known issues Here are the changes found in Patchwork_123628v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-adlm-1: NOTRUN -> [SKIP][3] ([i915#3826]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v1/bat-adlm-1/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@eof: - bat-adlm-1: NOTRUN -> [SKIP][4] ([i915#2582]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v1/bat-adlm-1/igt@fb...@eof.html * igt@fbdev@info: - bat-adlm-1: NOTRUN -> [SKIP][5] ([i915#1849] / [i915#2582]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v1/bat-adlm-1/igt@fb...@info.html * igt@gem_exec_suspend@basic-s0@lmem0: - bat-dg2-9: [PASS][6] -> [INCOMPLETE][7] ([i915#8797] / [i915#9275]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v1/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-adlm-1: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v1/bat-adlm-1/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_tiled_pread_basic: - bat-adlm-1: NOTRUN -> [SKIP][9] ([i915#3282]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v1/bat-adlm-1/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-adlm-1: NOTRUN -> [SKIP][10] ([i915#6621]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v1/bat-adlm-1/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@hangcheck: - bat-dg2-11: [PASS][11] -> [ABORT][12] ([i915#7913]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v1/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size: - bat-adlm-1: NOTRUN -> [SKIP][13] ([i915#1845]) +16 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v1/bat-adlm-1/igt@kms_cursor_leg...@basic-flip-after-cursor-varying-size.html * igt@kms_flip@basic-plain-flip: - bat-adlm-1: NOTRUN -> [SKIP][14] ([i915#3637]) +3 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v1/bat-adlm-1/igt@kms_f...@basic-plain-flip.html * igt@kms_force_connector_basic@force-load-detect: - bat-adlm-1: NOTRUN -> [SKIP][15] ([fdo#109285]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v1/bat-adlm-1/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_frontbuffer_tracking@basic: - bat-adlm-1: NOTRUN -> [SKIP][16] ([i915#1849]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v1/bat-adlm-1/igt@kms_frontbuffer_track...@basic.html * igt@kms_psr@cursor_plane_move: - bat-adlm-1: NOTRUN -> [SKIP][17] ([i915#1072]) +3 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123628v1/bat-adlm-1/igt@kms_psr@cursor_plane_move.html * igt@kms_setmode@basic-clone-single-crtc: -
Re: [Intel-gfx] [PATCH] drm/i915/gt: Prevent error pointer dereference
Hi Dan,
On Wed, Sep 13, 2023 at 11:17:41AM +0300, Dan Carpenter wrote:
> Move the check for "if (IS_ERR(obj))" in front of the call to
> i915_gem_object_set_cache_coherency() which dereferences "obj".
> Otherwise it will lead to a crash.
>
> Fixes: 43aa755eae2c ("drm/i915/mtl: Update cache coherency setting for
> context structure")
> Signed-off-by: Dan Carpenter
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 957d0aeb0c02..c378cc7c953c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1094,6 +1094,9 @@ __lrc_alloc_state(struct intel_context *ce, struct
> intel_engine_cs *engine)
> I915_BO_ALLOC_PM_VOLATILE);
> if (IS_ERR(obj)) {
> obj = i915_gem_object_create_shmem(engine->i915, context_size);
> + if (IS_ERR(obj))
> + return ERR_CAST(obj);
> +
that's correct! When the workaround was added later it wasn't
checking whether obj had a valid value or not, leading to a
potential segfault.
Thanks for fixing it!
Reviewed-by: Andi Shyti
Andi
> /*
>* Wa_22016122933: For Media version 13.0, all Media GT shared
>* memory needs to be mapped as WC on CPU side and UC (PAT
> @@ -1102,8 +1105,6 @@ __lrc_alloc_state(struct intel_context *ce, struct
> intel_engine_cs *engine)
> if (intel_gt_needs_wa_22016122933(engine->gt))
> i915_gem_object_set_cache_coherency(obj,
> I915_CACHE_NONE);
> }
> - if (IS_ERR(obj))
> - return ERR_CAST(obj);
>
> vma = i915_vma_instance(obj, >gt->ggtt->vm, NULL);
> if (IS_ERR(vma)) {
[Intel-gfx] ✗ Fi.CI.IGT: failure for Add DSC fractional bpp support (rev7)
== Series Details == Series: Add DSC fractional bpp support (rev7) URL : https://patchwork.freedesktop.org/series/111391/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13623_full -> Patchwork_111391v7_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_111391v7_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_111391v7_full, please notify your bug team (lgci.bug.fil...@intel.com) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_111391v7_full: ### IGT changes ### Possible regressions * igt@kms_flip@flip-vs-suspend@b-hdmi-a1: - shard-tglu: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-tglu-4/igt@kms_flip@flip-vs-susp...@b-hdmi-a1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-4/igt@kms_flip@flip-vs-susp...@b-hdmi-a1.html * igt@kms_universal_plane@cursor-fb-leak-pipe-b: - shard-apl: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-apl2/igt@kms_universal_pl...@cursor-fb-leak-pipe-b.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-apl1/igt@kms_universal_pl...@cursor-fb-leak-pipe-b.html New tests - New tests have been introduced between CI_DRM_13623_full and Patchwork_111391v7_full: ### New IGT tests (4) ### * igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait@pipe-a-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_atomic_transition@plane-primary-toggle-with-vblank-wait@pipe-b-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_cursor_crc@cursor-offscreen-64x64@pipe-a-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_cursor_crc@cursor-offscreen-64x64@pipe-d-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_111391v7_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@object-reloc-keep-cache: - shard-dg2: NOTRUN -> [SKIP][5] ([i915#8411]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@api_intel...@object-reloc-keep-cache.html * igt@device_reset@cold-reset-bound: - shard-dg2: NOTRUN -> [SKIP][6] ([i915#7701]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@device_re...@cold-reset-bound.html * igt@drm_fdinfo@most-busy-idle-check-all@vecs1: - shard-dg2: NOTRUN -> [SKIP][7] ([i915#8414]) +9 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-1/igt@drm_fdinfo@most-busy-idle-check-...@vecs1.html * igt@drm_fdinfo@virtual-busy-idle-all: - shard-mtlp: NOTRUN -> [SKIP][8] ([i915#8414]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@drm_fdi...@virtual-busy-idle-all.html * igt@feature_discovery@psr1: - shard-dg2: NOTRUN -> [SKIP][9] ([i915#658]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@feature_discov...@psr1.html * igt@gem_basic@multigpu-create-close: - shard-mtlp: NOTRUN -> [SKIP][10] ([i915#7697]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-mtlp-1/igt@gem_ba...@multigpu-create-close.html * igt@gem_close_race@multigpu-basic-threads: - shard-dg2: NOTRUN -> [SKIP][11] ([i915#7697]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_close_r...@multigpu-basic-threads.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglu: [PASS][12] -> [FAIL][13] ([i915#6268]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/shard-tglu-9/igt@gem_ctx_e...@basic-nohangcheck.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-tglu-2/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_ctx_param@set-priority-not-supported: - shard-dg2: NOTRUN -> [SKIP][14] ([fdo#109314]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-6/igt@gem_ctx_pa...@set-priority-not-supported.html * igt@gem_ctx_persistence@heartbeat-hang: - shard-dg2: NOTRUN -> [SKIP][15] ([i915#8555]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/shard-dg2-2/igt@gem_ctx_persiste...@heartbeat-hang.html * igt@gem_ctx_persistence@processes: - shard-snb: NOTRUN
[Intel-gfx] [PATCH] drm/i915/gt: Prevent error pointer dereference
Move the check for "if (IS_ERR(obj))" in front of the call to
i915_gem_object_set_cache_coherency() which dereferences "obj".
Otherwise it will lead to a crash.
Fixes: 43aa755eae2c ("drm/i915/mtl: Update cache coherency setting for context
structure")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 957d0aeb0c02..c378cc7c953c 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1094,6 +1094,9 @@ __lrc_alloc_state(struct intel_context *ce, struct
intel_engine_cs *engine)
I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj)) {
obj = i915_gem_object_create_shmem(engine->i915, context_size);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
/*
* Wa_22016122933: For Media version 13.0, all Media GT shared
* memory needs to be mapped as WC on CPU side and UC (PAT
@@ -1102,8 +1105,6 @@ __lrc_alloc_state(struct intel_context *ce, struct
intel_engine_cs *engine)
if (intel_gt_needs_wa_22016122933(engine->gt))
i915_gem_object_set_cache_coherency(obj,
I915_CACHE_NONE);
}
- if (IS_ERR(obj))
- return ERR_CAST(obj);
vma = i915_vma_instance(obj, >gt->ggtt->vm, NULL);
if (IS_ERR(vma)) {
Re: [Intel-gfx] [PATCH] drm/i915: Do not disable preemption for resets
On 2023-07-05 10:30:25 [+0100], Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Commit ade8a0f59844 ("drm/i915: Make all GPU resets atomic") added a
> preempt disable section over the hardware reset callback to prepare the
> driver for being able to reset from atomic contexts.
…
This missed the v6.6 merge window. Has this been dropped for some reason
or just missed by chance? Can this be still applied, please?
Sebastian
[Intel-gfx] ✓ Fi.CI.BAT: success for Add DSC fractional bpp support (rev7)
== Series Details == Series: Add DSC fractional bpp support (rev7) URL : https://patchwork.freedesktop.org/series/111391/ State : success == Summary == CI Bug Log - changes from CI_DRM_13623 -> Patchwork_111391v7 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/index.html Participating hosts (39 -> 39) -- Additional (1): bat-adlm-1 Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_111391v7 that come from known issues: ### CI changes ### Issues hit * boot: - fi-hsw-4770:[PASS][1] -> [FAIL][2] ([i915#8293]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/fi-hsw-4770/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/fi-hsw-4770/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-adlm-1: NOTRUN -> [SKIP][3] ([i915#3826]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@eof: - bat-adlm-1: NOTRUN -> [SKIP][4] ([i915#2582]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@fb...@eof.html * igt@fbdev@info: - bat-adlm-1: NOTRUN -> [SKIP][5] ([i915#1849] / [i915#2582]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@fb...@info.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-adlm-1: NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_tiled_pread_basic: - bat-adlm-1: NOTRUN -> [SKIP][7] ([i915#3282]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-adlm-1: NOTRUN -> [SKIP][8] ([i915#6621]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@i915_pm_...@basic-api.html * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size: - bat-adlm-1: NOTRUN -> [SKIP][9] ([i915#1845]) +16 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@kms_cursor_leg...@basic-flip-after-cursor-varying-size.html * igt@kms_flip@basic-plain-flip: - bat-adlm-1: NOTRUN -> [SKIP][10] ([i915#3637]) +3 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@kms_f...@basic-plain-flip.html * igt@kms_force_connector_basic@force-load-detect: - bat-adlm-1: NOTRUN -> [SKIP][11] ([fdo#109285]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_frontbuffer_tracking@basic: - bat-adlm-1: NOTRUN -> [SKIP][12] ([i915#1849]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-adlp-9: NOTRUN -> [SKIP][13] ([i915#3546]) +2 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlp-9/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@kms_psr@cursor_plane_move: - bat-adlm-1: NOTRUN -> [SKIP][14] ([i915#1072]) +3 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@kms_psr@cursor_plane_move.html * igt@kms_setmode@basic-clone-single-crtc: - bat-adlm-1: NOTRUN -> [SKIP][15] ([i915#3555]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - bat-adlm-1: NOTRUN -> [SKIP][16] ([i915#1845] / [i915#3708]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@prime_v...@basic-fence-flip.html * igt@prime_vgem@basic-write: - bat-adlm-1: NOTRUN -> [SKIP][17] ([i915#3708]) +2 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/bat-adlm-1/igt@prime_v...@basic-write.html Possible fixes * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [DMESG-FAIL][18] ([i915#5334]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13623/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v7/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@hugepages: - bat-mtlp-8: [DMESG-WARN][20] ([i915#9121]) -> [PASS][21] [20]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/tests: Fix incorrect argument in drm_test_mm_insert_range
== Series Details == Series: drm/tests: Fix incorrect argument in drm_test_mm_insert_range URL : https://patchwork.freedesktop.org/series/123541/ State : success == Summary == CI Bug Log - changes from CI_DRM_13622_full -> Patchwork_123541v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 10) -- Additional (1): shard-rkl0 New tests - New tests have been introduced between CI_DRM_13622_full and Patchwork_123541v1_full: ### New IGT tests (18) ### * igt@kms_atomic_transition@plane-all-transition-nonblocking-fencing@pipe-a-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_atomic_transition@plane-all-transition-nonblocking-fencing@pipe-b-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@pipe-a-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@pipe-b-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_atomic_transition@plane-use-after-nonblocking-unbind@pipe-a-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_atomic_transition@plane-use-after-nonblocking-unbind@pipe-b-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_cursor_crc@cursor-offscreen-64x64@pipe-a-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_cursor_crc@cursor-offscreen-64x64@pipe-d-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_cursor_crc@cursor-random-64x21@pipe-a-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_cursor_crc@cursor-random-64x21@pipe-d-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_cursor_crc@cursor-rapid-movement-64x21@pipe-a-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_cursor_crc@cursor-rapid-movement-64x21@pipe-d-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_cursor_crc@cursor-sliding-64x64@pipe-a-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_cursor_crc@cursor-sliding-64x64@pipe-d-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_plane_multiple@tiling-y@pipe-a-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_plane_multiple@tiling-y@pipe-b-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_plane_multiple@tiling-y@pipe-c-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s * igt@kms_plane_multiple@tiling-y@pipe-d-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_123541v1_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@object-reloc-purge-cache: - shard-mtlp: NOTRUN -> [SKIP][1] ([i915#8411]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123541v1/shard-mtlp-4/igt@api_intel...@object-reloc-purge-cache.html - shard-rkl: NOTRUN -> [SKIP][2] ([i915#8411]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123541v1/shard-rkl-6/igt@api_intel...@object-reloc-purge-cache.html * igt@drm_fdinfo@all-busy-check-all: - shard-mtlp: NOTRUN -> [SKIP][3] ([i915#8414]) +6 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123541v1/shard-mtlp-3/igt@drm_fdi...@all-busy-check-all.html * igt@drm_fdinfo@busy-hang@bcs0: - shard-dg2: NOTRUN -> [SKIP][4] ([i915#8414]) +9 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123541v1/shard-dg2-10/igt@drm_fdinfo@busy-h...@bcs0.html * igt@drm_fdinfo@most-busy-check-all@rcs0: - shard-rkl: [PASS][5] -> [FAIL][6] ([i915#7742]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13622/shard-rkl-2/igt@drm_fdinfo@most-busy-check-...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123541v1/shard-rkl-2/igt@drm_fdinfo@most-busy-check-...@rcs0.html * igt@drm_fdinfo@virtual-idle: - shard-rkl: NOTRUN -> [FAIL][7] ([i915#7742]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123541v1/shard-rkl-6/igt@drm_fdi...@virtual-idle.html * igt@feature_discovery@display-2x: - shard-rkl: NOTRUN -> [SKIP][8] ([i915#1839]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123541v1/shard-rkl-6/igt@feature_discov...@display-2x.html * igt@feature_discovery@display-3x: - shard-mtlp: NOTRUN -> [SKIP][9] ([i915#1839]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123541v1/shard-mtlp-3/igt@feature_discov...@display-3x.html * igt@gem_bad_reloc@negative-reloc-lut: - shard-dg2: NOTRUN -> [SKIP][10] ([i915#3281]) [10]:
Re: [Intel-gfx] [PATCH v2] drm/i915/cx0: Add step for programming msgbus timer
> -Original Message-
> From: Sousa, Gustavo
> Sent: Tuesday, September 12, 2023 6:59 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika ; Taylor, Clinton A
>
> Subject: [PATCH v2] drm/i915/cx0: Add step for programming msgbus timer
>
> There was a recent update in the BSpec adding an extra step to the PLL enable
> sequence, which is for programming the msgbus
> timer. Since we also touch PHY registers during hw readout, let's do the
> programming when starting a transaction rather than only
> when doing the PLL enable sequence.
>
> This might be the missing step that was causing the timeouts that we have
> recently seen during C20 SRAM register programming
> sequences. With this in place, we shouldn't need the logic to bump the timer
> thresholds, since now we have a documented value
> that should be set peform programming the registers. As such, let's also
> remove intel_cx0_bus_check_and_bump_timer(), but
> keep the part that checks if hardware really detected a timeout, which might
> be useful debugging information.
>
> v2:
> - Use debug level instead of warning for the message notifying that
> the hardware did not detect the timeout. (Mika)
> - Got a new BSpec update clarifying that we need to program the msgbus
> timer of both PHY lanes. Update the changes to reflect that.
> (Gustavo)
>
> BSpec: 64568
> Cc: Mika Kahola
Reviewed-by: Mika Kahola
> Signed-off-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 87 +--
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 +-
> 2 files changed, 41 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index e6d3027c821d..abd607b564f1 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -29,8 +29,6 @@
> #define INTEL_CX0_LANE1 BIT(1)
> #define INTEL_CX0_BOTH_LANES (INTEL_CX0_LANE1 | INTEL_CX0_LANE0)
>
> -#define INTEL_CX0_MSGBUS_TIMER_BUMPED_VAL0x200
> -
> bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy) {
> if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0) && phy < PHY_C) @@ -73,19
> +71,38 @@ assert_dc_off(struct
> drm_i915_private *i915)
> drm_WARN_ON(>drm, !enabled);
> }
>
> +static void intel_cx0_program_msgbus_timer(struct intel_encoder
> +*encoder) {
> + int lane;
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +
> + for_each_cx0_lane_in_mask(INTEL_CX0_BOTH_LANES, lane)
> + intel_de_rmw(i915,
> + XELPDP_PORT_MSGBUS_TIMER(encoder->port, lane),
> + XELPDP_PORT_MSGBUS_TIMER_VAL_MASK,
> + XELPDP_PORT_MSGBUS_TIMER_VAL);
> +}
> +
> /*
> * Prepare HW for CX0 phy transactions.
> *
> * It is required that PSR and DC5/6 are disabled before any CX0 message
> * bus transaction is executed.
> + *
> + * We also do the msgbus timer programming here to ensure that the
> + timer
> + * is already programmed before any access to the msgbus.
> */
> static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder
> *encoder) {
> + intel_wakeref_t wakeref;
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> intel_psr_pause(intel_dp);
> - return intel_display_power_get(i915, POWER_DOMAIN_DC_OFF);
> + wakeref = intel_display_power_get(i915, POWER_DOMAIN_DC_OFF);
> + intel_cx0_program_msgbus_timer(encoder);
> +
> + return wakeref;
> }
>
> static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder,
> intel_wakeref_t wakeref) @@ -121,42 +138,6 @@
> static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port
> port, i
> intel_clear_response_ready_flag(i915, port, lane); }
>
> -/*
> - * Check if there was a timeout detected by the hardware in the message bus
> - * and bump the threshold if so.
> - */
> -static void intel_cx0_bus_check_and_bump_timer(struct drm_i915_private *i915,
> -enum port port, int lane)
> -{
> - enum phy phy = intel_port_to_phy(i915, port);
> - i915_reg_t reg;
> - u32 val;
> - u32 timer_val;
> -
> - reg = XELPDP_PORT_MSGBUS_TIMER(port, lane);
> - val = intel_de_read(i915, reg);
> -
> - if (!(val & XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT)) {
> - drm_warn(>drm,
> - "PHY %c lane %d: hardware did not detect a timeout\n",
> - phy_name(phy), lane);
> - return;
> - }
> -
> - timer_val = REG_FIELD_GET(XELPDP_PORT_MSGBUS_TIMER_VAL_MASK, val);
> -
> - if (timer_val == INTEL_CX0_MSGBUS_TIMER_BUMPED_VAL)
> - return;
> -
> - val &= ~XELPDP_PORT_MSGBUS_TIMER_VAL_MASK;
> - val |=
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC fractional bpp support (rev7)
== Series Details == Series: Add DSC fractional bpp support (rev7) URL : https://patchwork.freedesktop.org/series/111391/ State : warning == Summary == Error: dim checkpatch failed 335c97448415 drm/display/dp: Add helper function to get DSC bpp prescision 1e1010fd7a35 drm/i915/display: Store compressed bpp in U6.4 format Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:339: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #339: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 311 lines checked 346395c16c9e drm/i915/display: Consider fractional vdsc bpp while computing m_n values 931e5062e6b6 drm/i915/audio : Consider fractional vdsc bpp while computing tu_data df96870bfa53 drm/i915/dsc/mtl: Add support for fractional bpp dcce55cc2a23 drm/i915/dp: Iterate over output bpp with fractional step size 3ae03ebc7a51 drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp 5e2c4525feef drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add DSC fractional bpp support (rev7)
== Series Details == Series: Add DSC fractional bpp support (rev7) URL : https://patchwork.freedesktop.org/series/111391/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision
> Subject: [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp
> prescision
>
> From: Ankit Nautiyal
>
> Add helper to get the DSC bits_per_pixel precision for the DP sink.
>
I think you forgot to add my reviewed by that I gave in the last revision
Anyways,
LGTM.
Reviewed-by: Suraj Kandpal
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 27 +
> include/drm/display/drm_dp_helper.h | 1 +
> 2 files changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
> b/drivers/gpu/drm/display/drm_dp_helper.c
> index 8a1b64c57dfd..5c23d5b8fc50 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux,
> struct drm_dp_desc *desc, } EXPORT_SYMBOL(drm_dp_read_desc);
>
> +/**
> + * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
> + * @dsc_dpcd: DSC capabilities from DPCD
> + *
> + * Returns the bpp precision supported by the DP sink.
> + */
> +u8 drm_dp_dsc_sink_bpp_incr(const u8
> +dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> +{
> + u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC -
> +DP_DSC_SUPPORT];
> +
> + switch (bpp_increment_dpcd) {
> + case DP_DSC_BITS_PER_PIXEL_1_16:
> + return 16;
> + case DP_DSC_BITS_PER_PIXEL_1_8:
> + return 8;
> + case DP_DSC_BITS_PER_PIXEL_1_4:
> + return 4;
> + case DP_DSC_BITS_PER_PIXEL_1_2:
> + return 2;
> + case DP_DSC_BITS_PER_PIXEL_1_1:
> + return 1;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
> +
> /**
> * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
> * supported by the DSC sink.
> diff --git a/include/drm/display/drm_dp_helper.h
> b/include/drm/display/drm_dp_helper.h
> index 3369104e2d25..6968d4d87931 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -164,6 +164,7 @@ drm_dp_is_branch(const u8
> dpcd[DP_RECEIVER_CAP_SIZE]) }
>
> /* DP/eDP DSC support */
> +u8 drm_dp_dsc_sink_bpp_incr(const u8
> +dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
> u8 drm_dp_dsc_sink_max_slice_count(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
> bool is_edp);
> u8 drm_dp_dsc_sink_line_buf_depth(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
> --
> 2.25.1
[Intel-gfx] [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size
From: Ankit Nautiyal
This patch adds support to iterate over compressed output bpp as per the
fractional step, supported by DP sink.
v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp.c | 38 +++--
1 file changed, 23 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6e09e21909a1..d6c29006b816 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1716,15 +1716,15 @@ static bool intel_dp_dsc_supports_format(struct
intel_dp *intel_dp,
return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
sink_dsc_format);
}
-static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
+static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32
link_clock,
u32 lane_count, u32 mode_clock,
enum intel_output_format
output_format,
int timeslots)
{
u32 available_bw, required_bw;
- available_bw = (link_clock * lane_count * timeslots) / 8;
- required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock));
+ available_bw = (link_clock * lane_count * timeslots * 16) / 8;
+ required_bw = compressed_bppx16 *
(intel_dp_mode_to_fec_clock(mode_clock));
return available_bw > required_bw;
}
@@ -1732,7 +1732,7 @@ static bool is_bw_sufficient_for_dsc_config(u16
compressed_bpp, u32 link_clock,
static int dsc_compute_link_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct link_config_limits *limits,
- u16 compressed_bpp,
+ u16 compressed_bppx16,
int timeslots)
{
const struct drm_display_mode *adjusted_mode =
_config->hw.adjusted_mode;
@@ -1747,8 +1747,8 @@ static int dsc_compute_link_config(struct intel_dp
*intel_dp,
for (lane_count = limits->min_lane_count;
lane_count <= limits->max_lane_count;
lane_count <<= 1) {
- if (!is_bw_sufficient_for_dsc_config(compressed_bpp,
link_rate, lane_count,
-
adjusted_mode->clock,
+ if (!is_bw_sufficient_for_dsc_config(compressed_bppx16,
link_rate,
+lane_count,
adjusted_mode->clock,
pipe_config->output_format,
timeslots))
continue;
@@ -1861,7 +1861,7 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
ret = dsc_compute_link_config(intel_dp,
pipe_config,
limits,
- valid_dsc_bpp[i],
+ valid_dsc_bpp[i] << 4,
timeslots);
if (ret == 0) {
pipe_config->dsc.compressed_bpp_x16 =
@@ -1888,23 +1888,31 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
int pipe_bpp,
int timeslots)
{
- u16 compressed_bpp;
+ u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u16 compressed_bppx16;
+ u8 bppx16_step;
int ret;
+ if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
+ bppx16_step = 16;
+ else
+ bppx16_step = 16 / bppx16_incr;
+
/* Compressed BPP should be less than the Input DSC bpp */
- dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+ dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);
+ dsc_min_bpp = dsc_min_bpp << 4;
- for (compressed_bpp = dsc_max_bpp;
-compressed_bpp >= dsc_min_bpp;
-compressed_bpp--) {
+ for (compressed_bppx16 = dsc_max_bpp;
+compressed_bppx16 >= dsc_min_bpp;
+compressed_bppx16 -= bppx16_step) {
ret = dsc_compute_link_config(intel_dp,
pipe_config,
limits,
- compressed_bpp,
+ compressed_bppx16,
timeslots);
if (ret == 0) {
-
[Intel-gfx] [PATCH 8/8] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
From: Swati Sharma
If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
compressed bpp is fractional. Continue if the computed compressed bpp
turns out to be a integer.
v2:
-Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
-Fix comment (Suraj)
Signed-off-by: Swati Sharma
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index d6c29006b816..354d78593a5f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1906,6 +1906,9 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
for (compressed_bppx16 = dsc_max_bpp;
compressed_bppx16 >= dsc_min_bpp;
compressed_bppx16 -= bppx16_step) {
+ if (intel_dp->force_dsc_fractional_bpp_en &&
+ !intel_fractional_bpp_decimal(compressed_bppx16))
+ continue;
ret = dsc_compute_link_config(intel_dp,
pipe_config,
limits,
@@ -1913,6 +1916,10 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
timeslots);
if (ret == 0) {
pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
+ if (intel_dp->force_dsc_fractional_bpp_en &&
+ intel_fractional_bpp_decimal(compressed_bppx16))
+ drm_dbg_kms(>drm, "Forcing DSC fractional
bpp\n");
+
return 0;
}
}
--
2.25.1
[Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
From: Swati Sharma
DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if output_bpp is
computed as integer. With this approach, we will be able to validate
DSC with fractional bpp.
v2:
Add drm_modeset_unlock to new line(Suraj)
Signed-off-by: Swati Sharma
Signed-off-by: Ankit Nautiyal
Signed-off-by: Mitul Golani
Reviewed-by: Suraj Kandpal
---
.../drm/i915/display/intel_display_debugfs.c | 83 +++
.../drm/i915/display/intel_display_types.h| 1 +
2 files changed, 84 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f05b52381a83..776ab96def1f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m,
void *data)
DP_DSC_YCbCr420_Native)),
str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
DP_DSC_YCbCr444)));
+ seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
+ drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
seq_printf(m, "Force_DSC_Enable: %s\n",
str_yes_no(intel_dp->force_dsc_en));
if (!intel_dp_is_edp(intel_dp))
@@ -1436,6 +1438,84 @@ static const struct file_operations
i915_dsc_output_format_fops = {
.write = i915_dsc_output_format_write
};
+static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct drm_device *dev = connector->dev;
+ struct drm_crtc *crtc;
+ struct intel_dp *intel_dp;
+ struct intel_encoder *encoder =
intel_attached_encoder(to_intel_connector(connector));
+ int ret;
+
+ if (!encoder)
+ return -ENODEV;
+
+ ret =
drm_modeset_lock_single_interruptible(>mode_config.connection_mutex);
+ if (ret)
+ return ret;
+
+ crtc = connector->state->crtc;
+ if (connector->status != connector_status_connected || !crtc) {
+ ret = -ENODEV;
+ goto out;
+ }
+
+ intel_dp = intel_attached_dp(to_intel_connector(connector));
+ seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
+ str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
+
+out:
+ drm_modeset_unlock(>mode_config.connection_mutex);
+
+ return ret;
+}
+
+static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
+const char __user *ubuf,
+size_t len, loff_t *offp)
+{
+ struct drm_connector *connector =
+ ((struct seq_file *)file->private_data)->private;
+ struct intel_encoder *encoder =
intel_attached_encoder(to_intel_connector(connector));
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ bool dsc_fractional_bpp_enable = false;
+ int ret;
+
+ if (len == 0)
+ return 0;
+
+ drm_dbg(>drm,
+ "Copied %zu bytes from user to force fractional bpp for DSC\n",
len);
+
+ ret = kstrtobool_from_user(ubuf, len, _fractional_bpp_enable);
+ if (ret < 0)
+ return ret;
+
+ drm_dbg(>drm, "Got %s for DSC Fractional BPP Enable\n",
+ (dsc_fractional_bpp_enable) ? "true" : "false");
+ intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
+
+ *offp += len;
+
+ return len;
+}
+
+static int i915_dsc_fractional_bpp_open(struct inode *inode,
+ struct file *file)
+{
+ return single_open(file, i915_dsc_fractional_bpp_show,
inode->i_private);
+}
+
+static const struct file_operations i915_dsc_fractional_bpp_fops = {
+ .owner = THIS_MODULE,
+ .open = i915_dsc_fractional_bpp_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .write = i915_dsc_fractional_bpp_write
+};
+
/*
* Returns the Current CRTC's bpc.
* Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1513,6 +1593,9 @@ void intel_connector_debugfs_add(struct intel_connector
*intel_connector)
debugfs_create_file("i915_dsc_output_format", 0644, root,
connector, _dsc_output_format_fops);
+
+ debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
+ connector,
[Intel-gfx] [PATCH 4/8] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
From: Ankit Nautiyal MTL+ supports fractional compressed bits_per_pixel, with precision of 1/16. This compressed bpp is stored in U6.4 format. Accommodate the precision during calculation of transfer unit data for hblank_early calculation. v2: -Fixed tu_data calculation while dealing with U6.4 format. (Stan) Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_audio.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index 4f1db1581316..3b08be54ce4f 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -522,25 +522,25 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, unsigned int link_clks_available, link_clks_required; unsigned int tu_data, tu_line, link_clks_active; unsigned int h_active, h_total, hblank_delta, pixel_clk; - unsigned int fec_coeff, cdclk, vdsc_bpp; + unsigned int fec_coeff, cdclk, vdsc_bppx16; unsigned int link_clk, lanes; unsigned int hblank_rise; h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; h_total = crtc_state->hw.adjusted_mode.crtc_htotal; pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; - vdsc_bpp = intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16); + vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16; cdclk = i915->display.cdclk.hw.cdclk; /* fec= 0.972261, using rounding multiplier of 100 */ fec_coeff = 972261; link_clk = crtc_state->port_clock; lanes = crtc_state->lane_count; - drm_dbg_kms(>drm, "h_active = %u link_clk = %u :" - "lanes = %u vdsc_bpp = %u cdclk = %u\n", - h_active, link_clk, lanes, vdsc_bpp, cdclk); + drm_dbg_kms(>drm, + "h_active = %u link_clk = %u : lanes = %u vdsc_bppx16 = %u cdclk = %u\n", + h_active, link_clk, lanes, vdsc_bppx16, cdclk); - if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) + if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) return 0; link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; @@ -552,8 +552,8 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), mul_u32_u32(link_clk, cdclk)); - tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 100), - mul_u32_u32(link_clk * lanes, fec_coeff)); + tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 100), + mul_u32_u32(link_clk * lanes * 16, fec_coeff)); tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), mul_u32_u32(64 * pixel_clk, 100)); link_clks_active = (tu_line - 1) * 64 + tu_data; -- 2.25.1
[Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision
From: Ankit Nautiyal
Add helper to get the DSC bits_per_pixel precision for the DP sink.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/display/drm_dp_helper.c | 27 +
include/drm/display/drm_dp_helper.h | 1 +
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
b/drivers/gpu/drm/display/drm_dp_helper.c
index 8a1b64c57dfd..5c23d5b8fc50 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct
drm_dp_desc *desc,
}
EXPORT_SYMBOL(drm_dp_read_desc);
+/**
+ * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
+ * @dsc_dpcd: DSC capabilities from DPCD
+ *
+ * Returns the bpp precision supported by the DP sink.
+ */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC -
DP_DSC_SUPPORT];
+
+ switch (bpp_increment_dpcd) {
+ case DP_DSC_BITS_PER_PIXEL_1_16:
+ return 16;
+ case DP_DSC_BITS_PER_PIXEL_1_8:
+ return 8;
+ case DP_DSC_BITS_PER_PIXEL_1_4:
+ return 4;
+ case DP_DSC_BITS_PER_PIXEL_1_2:
+ return 2;
+ case DP_DSC_BITS_PER_PIXEL_1_1:
+ return 1;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
+
/**
* drm_dp_dsc_sink_max_slice_count() - Get the max slice count
* supported by the DSC sink.
diff --git a/include/drm/display/drm_dp_helper.h
b/include/drm/display/drm_dp_helper.h
index 3369104e2d25..6968d4d87931 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -164,6 +164,7 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
}
/* DP/eDP DSC support */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
bool is_edp);
u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
--
2.25.1
[Intel-gfx] [PATCH 5/8] drm/i915/dsc/mtl: Add support for fractional bpp
From: Vandita Kulkarni
Consider the fractional bpp while reading the qp values.
v2: Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
Signed-off-by: Vandita Kulkarni
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
.../gpu/drm/i915/display/intel_qp_tables.c| 3 ---
drivers/gpu/drm/i915/display/intel_vdsc.c | 25 +++
2 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c
b/drivers/gpu/drm/i915/display/intel_qp_tables.c
index 543cdc46aa1d..600c815e37e4 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -34,9 +34,6 @@
* These qp tables are as per the C model
* and it has the rows pointing to bpps which increment
* in steps of 0.5
- * We do not support fractional bpps as of today,
- * hence we would skip the fractional bpps during
- * our references for qp calclulations.
*/
static const u8
rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 1bd9391a6f5a..2c19078fbce8 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -78,8 +78,8 @@ intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg,
int buf,
static void
calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
{
+ int bpp = intel_fractional_bpp_from_x16(vdsc_cfg->bits_per_pixel);
int bpc = vdsc_cfg->bits_per_component;
- int bpp = vdsc_cfg->bits_per_pixel >> 4;
int qp_bpc_modifier = (bpc - 8) * 2;
int uncompressed_bpg_rate;
int first_line_bpg_offset;
@@ -149,7 +149,13 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
static const s8 ofs_und8[] = {
10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12,
-12
};
-
+ /*
+* For 420 format since bits_per_pixel (bpp) is set to target
bpp * 2,
+* QP table values for target bpp 4.0 to 4.4375 (rounded to
4.0) are
+* actually for bpp 8 to 8.875 (rounded to 4.0 * 2 i.e 8).
+* Similarly values for target bpp 4.5 to 4.8375 (rounded to
4.5)
+* are for bpp 9 to 9.875 (rounded to 4.5 * 2 i.e 9), and so on.
+*/
bpp_i = bpp - 8;
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
u8 range_bpg_offset;
@@ -179,6 +185,9 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
}
} else {
+ /* fractional bpp part * 1 (for precision up to 4 decimal
places) */
+ int fractional_bits =
intel_fractional_bpp_decimal(vdsc_cfg->bits_per_pixel);
+
static const s8 ofs_und6[] = {
0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12,
-12, -12
};
@@ -192,7 +201,14 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12,
-12
};
- bpp_i = (2 * (bpp - 6));
+ /*
+* QP table rows have values in increment of 0.5.
+* So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will
have index 1,
+* and so on.
+* 0.5 fractional part with 4 decimal precision becomes 5000
+*/
+ bpp_i = ((bpp - 6) + (fractional_bits < 5000 ? 0 : 1));
+
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
u8 range_bpg_offset;
@@ -280,8 +296,7 @@ int intel_dsc_compute_params(struct intel_crtc_state
*pipe_config)
/* Gen 11 does not support VBR */
vdsc_cfg->vbr_enable = false;
- /* Gen 11 only supports integral values of bpp */
- vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+ vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16;
/*
* According to DSC 1.2 specs in Section 4.1 if native_420 is set
--
2.25.1
[Intel-gfx] [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values
From: Ankit Nautiyal
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 --
drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
5 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index afcbdd4f105a..b37aeac961f4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2380,10 +2380,14 @@ void
intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
- bool fec_enable)
+ bool fec_enable,
+ bool is_dsc_fractional_bpp)
{
u32 data_clock = bits_per_pixel * pixel_clock;
+ if (is_dsc_fractional_bpp)
+ data_clock = DIV_ROUND_UP(bits_per_pixel * pixel_clock, 16);
+
if (fec_enable)
data_clock = intel_dp_mode_to_fec_clock(data_clock);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 49ac8473b988..a4c4ca3cad65 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -398,7 +398,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state,
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
- bool fec_enable);
+ bool fec_enable, bool is_dsc_fractional_bpp);
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier);
enum drm_mode_status
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index cb647bb38b12..6e09e21909a1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2562,7 +2562,7 @@ intel_dp_drrs_compute_config(struct intel_connector
*connector,
intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
pipe_config->port_clock, _config->dp_m2_n2,
- pipe_config->fec_enable);
+ pipe_config->fec_enable, false);
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
@@ -2741,7 +2741,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
adjusted_mode->crtc_clock,
pipe_config->port_clock,
_config->dp_m_n,
- pipe_config->fec_enable);
+ pipe_config->fec_enable,
+ pipe_config->dsc.compression_enable);
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 7bf0b6e4ac0b..8f6bd54532cb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -172,7 +172,8 @@ static int intel_dp_mst_compute_link_config(struct
intel_encoder *encoder,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
_state->dp_m_n,
- crtc_state->fec_enable);
+ crtc_state->fec_enable,
+ false);
crtc_state->dp_m_n.tu = slots;
return 0;
@@ -269,7 +270,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct
intel_encoder *encoder,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
_state->dp_m_n,
- crtc_state->fec_enable);
+ crtc_state->fec_enable,
+ crtc_state->dsc.compression_enable);
crtc_state->dp_m_n.tu = slots;
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index e12b46a84fa1..15fddabf7c2e 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -259,7 +259,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
pipe_config->fdi_lanes = lane;
intel_link_compute_m_n(pipe_config->pipe_bpp, lane,
[Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support
his patch series adds support for DSC fractional compressed bpp for MTL+. The series starts with some fixes, followed by patches that lay groundwork to iterate over valid compressed bpps to select the 'best' compressed bpp with optimal link configuration (taken from upstream series: https://patchwork.freedesktop.org/series/105200/). The later patches, add changes to accommodate compressed bpp with fractional part, including changes to QP calculations. To get the 'best' compressed bpp, we iterate over the valid compressed bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per sink support. The last 2 patches add support to depict DSC sink's fractional support, and debugfs to enforce use of fractional bpp, while choosing an appropriate compressed bpp. Ankit Nautiyal (5): drm/display/dp: Add helper function to get DSC bpp prescision drm/i915/display: Store compressed bpp in U6.4 format drm/i915/display: Consider fractional vdsc bpp while computing m_n values drm/i915/audio : Consider fractional vdsc bpp while computing tu_data drm/i915/dp: Iterate over output bpp with fractional step size Swati Sharma (2): drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs Vandita Kulkarni (1): drm/i915/dsc/mtl: Add support for fractional bpp drivers/gpu/drm/display/drm_dp_helper.c | 27 ++ drivers/gpu/drm/i915/display/icl_dsi.c| 11 +-- drivers/gpu/drm/i915/display/intel_audio.c| 17 ++-- drivers/gpu/drm/i915/display/intel_bios.c | 6 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 6 +- drivers/gpu/drm/i915/display/intel_display.c | 8 +- drivers/gpu/drm/i915/display/intel_display.h | 2 +- .../drm/i915/display/intel_display_debugfs.c | 83 +++ .../drm/i915/display/intel_display_types.h| 4 +- drivers/gpu/drm/i915/display/intel_dp.c | 81 +++--- drivers/gpu/drm/i915/display/intel_dp_mst.c | 32 --- drivers/gpu/drm/i915/display/intel_fdi.c | 2 +- .../i915/display/intel_fractional_helper.h| 36 .../gpu/drm/i915/display/intel_qp_tables.c| 3 - drivers/gpu/drm/i915/display/intel_vdsc.c | 30 +-- include/drm/display/drm_dp_helper.h | 1 + 16 files changed, 275 insertions(+), 74 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_fractional_helper.h -- 2.25.1
[Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format
From: Ankit Nautiyal
DSC parameter bits_per_pixel is stored in U6.4 format.
The 4 bits represent the fractional part of the bpp.
Currently we use compressed_bpp member of dsc structure to store
only the integral part of the bits_per_pixel.
To store the full bits_per_pixel along with the fractional part,
compressed_bpp is changed to store bpp in U6.4 formats. Intergral
part is retrieved by simply right shifting the member compressed_bpp by 4.
v2:
-Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing
with compressed bpp. (Suraj)
-Fix comment styling. (Suraj)
v3:
-Add separate file for 6.4 fixed point helper(Jani, Nikula)
-Add comment for magic values(Suraj)
v4:
-Fix checkpatch caused due to renaming(Suraj)
Signed-off-by: Ankit Nautiyal
Signed-off-by: Mitul Golani
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/icl_dsi.c| 11 +++---
drivers/gpu/drm/i915/display/intel_audio.c| 3 +-
drivers/gpu/drm/i915/display/intel_bios.c | 6 ++--
drivers/gpu/drm/i915/display/intel_cdclk.c| 6 ++--
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
.../drm/i915/display/intel_display_types.h| 3 +-
drivers/gpu/drm/i915/display/intel_dp.c | 33 ++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 26 --
.../i915/display/intel_fractional_helper.h| 36 +++
drivers/gpu/drm/i915/display/intel_vdsc.c | 5 +--
10 files changed, 93 insertions(+), 38 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_fractional_helper.h
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index ad6488e9c2b2..0f7594b6aa1f 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -43,6 +43,7 @@
#include "intel_de.h"
#include "intel_dsi.h"
#include "intel_dsi_vbt.h"
+#include "intel_fractional_helper.h"
#include "intel_panel.h"
#include "intel_vdsc.h"
#include "intel_vdsc_regs.h"
@@ -330,7 +331,7 @@ static int afe_clk(struct intel_encoder *encoder,
int bpp;
if (crtc_state->dsc.compression_enable)
- bpp = crtc_state->dsc.compressed_bpp;
+ bpp =
intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
else
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@@ -860,7 +861,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder,
* compressed and non-compressed bpp.
*/
if (crtc_state->dsc.compression_enable) {
- mul = crtc_state->dsc.compressed_bpp;
+ mul =
intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
}
@@ -884,7 +885,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder,
int bpp, line_time_us, byte_clk_period_ns;
if (crtc_state->dsc.compression_enable)
- bpp = crtc_state->dsc.compressed_bpp;
+ bpp =
intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
else
bpp =
mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@@ -1451,8 +1452,8 @@ static void gen11_dsi_get_timings(struct intel_encoder
*encoder,
struct drm_display_mode *adjusted_mode =
_config->hw.adjusted_mode;
- if (pipe_config->dsc.compressed_bpp) {
- int div = pipe_config->dsc.compressed_bpp;
+ if (pipe_config->dsc.compressed_bpp_x16) {
+ int div =
intel_fractional_bpp_from_x16(pipe_config->dsc.compressed_bpp_x16);
int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
adjusted_mode->crtc_htotal =
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 19605264a35c..4f1db1581316 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -35,6 +35,7 @@
#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_fractional_helper.h"
#include "intel_lpe_audio.h"
/**
@@ -528,7 +529,7 @@ static unsigned int calc_hblank_early_prog(struct
intel_encoder *encoder,
h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
- vdsc_bpp = crtc_state->dsc.compressed_bpp;
+ vdsc_bpp =
intel_fractional_bpp_from_x16(crtc_state->dsc.compressed_bpp_x16);
cdclk = i915->display.cdclk.hw.cdclk;
/* fec= 0.972261, using rounding multiplier of 100 */
fec_coeff = 972261;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index f735b035436c..3e4a3c62fc8a 100644
---
