[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Added Wa_18022495364 (rev5)
== Series Details == Series: drm/i915: Added Wa_18022495364 (rev5) URL : https://patchwork.freedesktop.org/series/123377/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13633_full -> Patchwork_123377v5_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_123377v5_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_123377v5_full, please notify your bug team (lgci.bug.fil...@intel.com) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_123377v5_full: ### IGT changes ### Possible regressions * igt@gem_exec_schedule@wide@ccs0: - shard-mtlp: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-mtlp-5/igt@gem_exec_schedule@w...@ccs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/shard-mtlp-5/igt@gem_exec_schedule@w...@ccs0.html * igt@i915_pm_rps@engine-order: - shard-mtlp: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-mtlp-2/igt@i915_pm_...@engine-order.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/shard-mtlp-5/igt@i915_pm_...@engine-order.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb@pipe-a-edp-1: - shard-mtlp: [PASS][5] -> [ABORT][6] +1 other test abort [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-mtlp-2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big...@pipe-a-edp-1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/shard-mtlp-5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big...@pipe-a-edp-1.html Warnings * igt@i915_suspend@forcewake: - shard-mtlp: [ABORT][7] ([i915#9262]) -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-mtlp-6/igt@i915_susp...@forcewake.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/shard-mtlp-4/igt@i915_susp...@forcewake.html Known issues Here are the changes found in Patchwork_123377v5_full that come from known issues: ### IGT changes ### Issues hit * igt@device_reset@unbind-cold-reset-rebind: - shard-mtlp: NOTRUN -> [SKIP][9] ([i915#7701]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/shard-mtlp-3/igt@device_re...@unbind-cold-reset-rebind.html * igt@drm_fdinfo@busy-hang@bcs0: - shard-dg2: NOTRUN -> [SKIP][10] ([i915#8414]) +10 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/shard-dg2-3/igt@drm_fdinfo@busy-h...@bcs0.html * igt@drm_fdinfo@virtual-busy-all: - shard-mtlp: NOTRUN -> [SKIP][11] ([i915#8414]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/shard-mtlp-3/igt@drm_fdi...@virtual-busy-all.html * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0: - shard-dg2: [PASS][12] -> [INCOMPLETE][13] ([i915#7297]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-dg2-2/igt@gem_ccs@suspend-res...@linear-compressed-compfmt0-smem-lmem0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/shard-dg2-7/igt@gem_ccs@suspend-res...@linear-compressed-compfmt0-smem-lmem0.html * igt@gem_close_race@multigpu-basic-threads: - shard-dg2: NOTRUN -> [SKIP][14] ([i915#7697]) +1 other test skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/shard-dg2-1/igt@gem_close_r...@multigpu-basic-threads.html * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-dg2: [PASS][15] -> [FAIL][16] ([fdo#103375]) +2 other tests fail [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-dg2-3/igt@gem_ctx_isolation@preservation...@bcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/shard-dg2-5/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_ctx_param@set-priority-not-supported: - shard-dg2: NOTRUN -> [SKIP][17] ([fdo#109314]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/shard-dg2-3/igt@gem_ctx_pa...@set-priority-not-supported.html * igt@gem_ctx_persistence@engines-hostile-preempt: - shard-snb: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#1099]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/shard-snb7/igt@gem_ctx_persiste...@engines-hostile-preempt.html * igt@gem_eio@in-flight-suspend: - shard-mtlp: NOTRUN -> [ABORT][19] ([i915#7892] / [i915#9262]) [19]:
Re: [Intel-gfx] [PATCH 08/12] drm/i915: Validate that the timings are within the VRR range
> -Original Message- > From: Intel-gfx On Behalf Of Ville > Syrjala > Sent: 01 September 2023 18:35 > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 08/12] drm/i915: Validate that the timings are > within the VRR range > > From: Ville Syrjälä > > Let's assume there are some crazy displays where the high end of the VRR > range ends up being lower than the refresh rate as determined by the actual > timings. In that case when we toggle VRR on/off we would step outside the > VRR range when toggling VRR on/off. Let's just make sure that never happens > by not using VRR in such cases. If the user really wants VRR they should then > select the timings to land within the VRR range. > > Cc: Manasi Navare > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c > b/drivers/gpu/drm/i915/display/intel_vrr.c > index 6ef782538337..12731ad725a8 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -117,10 +117,10 @@ intel_vrr_compute_config(struct intel_crtc_state > *crtc_state, > const struct drm_display_info *info = > >base.display_info; > int vmin, vmax; > > - if (!intel_vrr_is_capable(connector)) > + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) > return; > > - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) > + if (!intel_vrr_is_in_range(connector, > +drm_mode_vrefresh(adjusted_mode))) Changes LGTM Reviewed-by: Mitul Golani Regards, Mitul > return; > > vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, > -- > 2.41.0
Re: [Intel-gfx] [PATCH 07/12] drm/i915: Relocate is_in_vrr_range()
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: 01 September 2023 18:35
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 07/12] drm/i915: Relocate is_in_vrr_range()
>
> From: Ville Syrjälä
>
> Move is_in_vrr_range() into intel_vrr.c in anticipation of more users, and
> rename it accordingly.
>
> Cc: Manasi Navare
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_panel.c | 17 -
> drivers/gpu/drm/i915/display/intel_vrr.c | 9 +
> drivers/gpu/drm/i915/display/intel_vrr.h | 1 +
> 3 files changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
> b/drivers/gpu/drm/i915/display/intel_panel.c
> index 9232a305b1e6..086cb8dbe22c 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -59,15 +59,6 @@ intel_panel_preferred_fixed_mode(struct
> intel_connector *connector)
> struct drm_display_mode, head);
> }
>
> -static bool is_in_vrr_range(struct intel_connector *connector, int vrefresh)
> -{
> - const struct drm_display_info *info =
> >base.display_info;
> -
> - return intel_vrr_is_capable(connector) &&
> - vrefresh >= info->monitor_range.min_vfreq &&
> - vrefresh <= info->monitor_range.max_vfreq;
> -}
> -
> static bool is_best_fixed_mode(struct intel_connector *connector,
> int vrefresh, int fixed_mode_vrefresh,
> const struct drm_display_mode *best_mode)
> @@ -81,8 +72,8 @@ static bool is_best_fixed_mode(struct intel_connector
> *connector,
>* vrefresh, which we can then reduce to match the requested
>* vrefresh by extending the vblank length.
>*/
> - if (is_in_vrr_range(connector, vrefresh) &&
> - is_in_vrr_range(connector, fixed_mode_vrefresh) &&
> + if (intel_vrr_is_in_range(connector, vrefresh) &&
> + intel_vrr_is_in_range(connector, fixed_mode_vrefresh) &&
> fixed_mode_vrefresh < vrefresh)
> return false;
>
> @@ -224,8 +215,8 @@ int intel_panel_compute_config(struct
> intel_connector *connector,
>* Assume that we shouldn't muck about with the
>* timings if they don't land in the VRR range.
>*/
> - is_vrr = is_in_vrr_range(connector, vrefresh) &&
> - is_in_vrr_range(connector, fixed_mode_vrefresh);
> + is_vrr = intel_vrr_is_in_range(connector, vrefresh) &&
> + intel_vrr_is_in_range(connector, fixed_mode_vrefresh);
>
> if (!is_vrr) {
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 88e4759b538b..6ef782538337 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -42,6 +42,15 @@ bool intel_vrr_is_capable(struct intel_connector
> *connector)
> info->monitor_range.max_vfreq - info-
> >monitor_range.min_vfreq > 10; }
>
> +bool intel_vrr_is_in_range(struct intel_connector *connector, int
> +vrefresh) {
> + const struct drm_display_info *info =
> >base.display_info;
> +
> + return intel_vrr_is_capable(connector) &&
> + vrefresh >= info->monitor_range.min_vfreq &&
> + vrefresh <= info->monitor_range.max_vfreq; }
> +
Changes LGTM
Reviewed-by: Mitul Golani
Regards,
Mitul
> void
> intel_vrr_check_modeset(struct intel_atomic_state *state) { diff --git
> a/drivers/gpu/drm/i915/display/intel_vrr.h
> b/drivers/gpu/drm/i915/display/intel_vrr.h
> index de16960c4929..89937858200d 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -14,6 +14,7 @@ struct intel_connector; struct intel_crtc_state;
>
> bool intel_vrr_is_capable(struct intel_connector *connector);
> +bool intel_vrr_is_in_range(struct intel_connector *connector, int
> +vrefresh);
> void intel_vrr_check_modeset(struct intel_atomic_state *state); void
> intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state);
> --
> 2.41.0
[Intel-gfx] ✗ Fi.CI.BAT: failure for i915/guc: Get runtime pm in busyness worker only if already active
== Series Details ==
Series: i915/guc: Get runtime pm in busyness worker only if already active
URL : https://patchwork.freedesktop.org/series/123744/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13635 -> Patchwork_123744v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_123744v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_123744v1, please notify your bug team
(lgci.bug.fil...@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123744v1/index.html
Participating hosts (40 -> 40)
--
Additional (1): fi-kbl-soraka
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_123744v1:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@hangcheck:
- fi-skl-guc: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13635/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123744v1/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@perf:
- fi-kbl-soraka: NOTRUN -> [ABORT][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123744v1/fi-kbl-soraka/igt@i915_selftest@l...@perf.html
Known issues
Here are the changes found in Patchwork_123744v1 that come from known issues:
### CI changes ###
Possible fixes
* boot:
- fi-hsw-4770:[FAIL][4] ([i915#8293]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13635/fi-hsw-4770/boot.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123744v1/fi-hsw-4770/boot.html
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s0@smem:
- bat-dg2-9: [PASS][6] -> [INCOMPLETE][7] ([i915#9275])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13635/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123744v1/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123744v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3
other tests skip
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123744v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][10] ([i915#1886] / [i915#7913])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123744v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271]) +13 other tests
skip
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123744v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_dsc@dsc-basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271]) +9 other tests
skip
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123744v1/fi-kbl-soraka/igt@kms_...@dsc-basic.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1:
- fi-hsw-4770:NOTRUN -> [DMESG-WARN][13] ([i915#8841]) +6 other
tests dmesg-warn
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123744v1/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-vga-1.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1072]) +3
other tests skip
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123744v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275
Build
Re: [Intel-gfx] [PATCH 1/5] drm/i915/fbc: Remove ancient 16k plane stride limit
Thanks Ville for the fix! LGTM Reviewed-by: Swati Sharma On 14-Sep-23 5:08 PM, Ville Syrjala wrote: From: Ville Syrjälä The 16k max plane stride limit seems to be originally from i965gm, and no limit explicit limit has been specified since (g4x+). nitpick: "limit" seems to be extra here So let's assume the max plane stride itself is a suitable limit also for the more recent FBC hardware. In fact even for i965gm the max X-tiled stride is also 16k so technically we don't need the check there either, but let's keep it there anyway since it's explicitly mentioned in the spec. Gen2/3 have more strict limits checked separately. Cc: Swati Sharma Signed-off-by: Ville Syrjälä > --- drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 817e5784660b..1b3358a0fbfb 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -866,7 +866,8 @@ static bool stride_is_valid(const struct intel_plane_state *plane_state) if (DISPLAY_VER(i915) == 2 || DISPLAY_VER(i915) == 3) return stride == 4096 || stride == 8192; - if (DISPLAY_VER(i915) == 4 && !IS_G4X(i915) && stride < 2048) + if (DISPLAY_VER(i915) == 4 && !IS_G4X(i915) && + (stride < 2048 || stride > 16384)) return false; /* Display WA #1105: skl,bxt,kbl,cfl,glk */ @@ -874,9 +875,6 @@ static bool stride_is_valid(const struct intel_plane_state *plane_state) fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511) return false; - if (stride > 16384) - return false; - return true; }
Re: [Intel-gfx] [PATCH] drm/i915: refactor deprecated strncpy
On Thu, Sep 14, 2023 at 09:14:07PM +, Justin Stitt wrote:
> `strncpy` is deprecated for use on NUL-terminated destination strings [1].
>
> We should prefer more robust and less ambiguous string interfaces.
>
> A suitable replacement is `strscpy` [2] due to the fact that it guarantees
> NUL-termination on the destination buffer without unnecessarily NUL-padding.
>
> `ctx` is zero allocated and as such strncpy's NUL-padding behavior was
> strictly a performance hit which should now be resolved. It should be
> noted, however, that performance is not critical in these selftests,
> especially by these margins.
>
> Link:
> https://www.kernel.org/doc/html/latest/process/deprecated.html#strncpy-on-nul-terminated-strings
> [1]
> Link: https://manpages.debian.org/testing/linux-manual-4.8/strscpy.9.en.html
> [2]
> Link: https://github.com/KSPP/linux/issues/90
> Cc: linux-harden...@vger.kernel.org
> Signed-off-by: Justin Stitt
> ---
> drivers/gpu/drm/i915/gem/selftests/mock_context.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_context.c
> b/drivers/gpu/drm/i915/gem/selftests/mock_context.c
> index 8ac6726ec16b..025b9c773b93 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/mock_context.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/mock_context.c
> @@ -36,7 +36,7 @@ mock_context(struct drm_i915_private *i915,
> if (name) {
> struct i915_ppgtt *ppgtt;
>
> - strncpy(ctx->name, name, sizeof(ctx->name) - 1);
> + strscpy(ctx->name, name, sizeof(ctx->name) - 1);
I'd expect the "- 1" to go away...
-Kees
>
> ppgtt = mock_ppgtt(i915, name);
> if (!ppgtt)
>
> ---
> base-commit: 3669558bdf354cd352be955ef2764cde6a9bf5ec
> change-id:
> 20230914-strncpy-drivers-gpu-drm-i915-gem-selftests-mock_context-c-980c8ecc9142
>
> Best regards,
> --
> Justin Stitt
>
--
Kees Cook
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Improve BW management on shared display links (rev5)
== Series Details ==
Series: drm/i915: Improve BW management on shared display links (rev5)
URL : https://patchwork.freedesktop.org/series/122589/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13635 -> Patchwork_122589v5
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v5/index.html
Participating hosts (40 -> 40)
--
Additional (1): fi-kbl-soraka
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_122589v5 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_parallel@engines@fds:
- bat-mtlp-6: [PASS][1] -> [ABORT][2] ([i915#9262])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13635/bat-mtlp-6/igt@gem_exec_parallel@engi...@fds.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v5/bat-mtlp-6/igt@gem_exec_parallel@engi...@fds.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v5/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3
other tests skip
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v5/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@gem_contexts:
- bat-atsm-1: [PASS][5] -> [INCOMPLETE][6] ([i915#7913])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13635/bat-atsm-1/igt@i915_selftest@live@gem_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v5/bat-atsm-1/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][7] ([i915#1886] / [i915#7913])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v5/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-bsw-nick:[PASS][8] -> [INCOMPLETE][9] ([i915#4817])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13635/fi-bsw-nick/igt@i915_susp...@basic-s3-without-i915.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v5/fi-bsw-nick/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_dsc@dsc-basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271]) +9 other tests
skip
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v5/fi-kbl-soraka/igt@kms_...@dsc-basic.html
Possible fixes
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [FAIL][11] ([IGT#3] / [i915#6121]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13635/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v5/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952
[i915#9262]: https://gitlab.freedesktop.org/drm/intel/issues/9262
Build changes
-
* Linux: CI_DRM_13635 -> Patchwork_122589v5
CI-20190529: 20190529
CI_DRM_13635: c6b7f865a77a75af03c3b68baa4cf7eb66c1c6d5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7488: 099e058c5dfb7a49942edf03cae88a52a77077a3 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_122589v5: c6b7f865a77a75af03c3b68baa4cf7eb66c1c6d5 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
b0a3d0b34309 drm/i915/dp_mst: Check BW limitations only after all streams are
computed
6f8f53129a5a drm/i915/dp_mst: Improve BW sharing between MST streams
b5a5a7f88084 drm/i915/dp_mst: Allow DSC only for sink ports of the first branch
device
6cd5e811c7a4 drm/i915/dp_mst: Add missing DSC compression disabling
ee9689328b06 drm/i915/dp_mst: Enable DSC decompression if any stream needs this
c64811bf340a drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is
disabled
4f9f7b30b991 drm/i915/dp_mst: Program the DSC PPS SDP for each stream
e5c67f3706d4 drm/i915/dp_mst: Add atomic state for all streams on pre-tgl
platforms
65967e8437cc
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Improve BW management on shared display links (rev5)
== Series Details == Series: drm/i915: Improve BW management on shared display links (rev5) URL : https://patchwork.freedesktop.org/series/122589/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on shared display links (rev5)
== Series Details == Series: drm/i915: Improve BW management on shared display links (rev5) URL : https://patchwork.freedesktop.org/series/122589/ State : warning == Summary == Error: dim checkpatch failed 1c45ddaa2306 drm/i915/dp: Factor out helpers to compute the link limits -:122: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #122: FILE: drivers/gpu/drm/i915/display/intel_dp_mst.c:305: + limits->min_rate = limits->max_rate = -:125: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #125: FILE: drivers/gpu/drm/i915/display/intel_dp_mst.c:308: + limits->min_lane_count = limits->max_lane_count = total: 0 errors, 0 warnings, 2 checks, 147 lines checked 5cbf75c5fb66 drm/i915/dp: Track the pipe and link bpp limits separately -:49: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #49: FILE: drivers/gpu/drm/i915/display/intel_dp.c:1473: + limits->pipe.min_bpp = limits->pipe.max_bpp = bpp; -:106: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #106: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2211: + limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state, +respect_downstream_limits); total: 0 errors, 0 warnings, 2 checks, 146 lines checked 2e87799dc7ea drm/i915/dp: Skip computing a non-DSC link config if DSC is needed 667d1ee529b5 drm/i915/dp: Update the link bpp limits for DSC mode -:42: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #42: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:2124: +#define BPP_X16_ARGS(bpp_x16) to_bpp_int(bpp_x16), (to_bpp_frac(bpp_x16) * 625) -:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'bpp_x16' - possible side-effects? #42: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:2124: +#define BPP_X16_ARGS(bpp_x16) to_bpp_int(bpp_x16), (to_bpp_frac(bpp_x16) * 625) -:102: WARNING:LONG_LINE: line length of 164 exceeds 100 columns #102: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2239: + "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT "\n", total: 1 errors, 1 warnings, 1 checks, 201 lines checked 34432c0c443b drm/i915/dp: Limit the output link bpp in DSC mode e8ed36a51e75 drm/i915: Add helper to modeset a set of pipes cb5bc3bee5cb drm/i915: During modeset forcing handle inactive but enabled pipes a17735557882 drm/i915: Factor out a helper to check/compute all the CRTC states 5d31d9dbb9ed drm/i915: Add helpers for BW management on shared display links Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:202: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #202: new file mode 100644 -:345: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #345: FILE: drivers/gpu/drm/i915/display/intel_link_bw.c:139: +intel_link_bw_reset_pipe_limit_to_min(struct intel_atomic_state *state, + const struct intel_link_bw_limits *old_limits, total: 0 errors, 1 warnings, 1 checks, 399 lines checked ed7982fe9d39 drm/i915/fdi: Improve FDI BW sharing between pipe B and C b38be1ad15df drm/i915/fdi: Recompute state for affected CRTCs on FDI links 99d9a52aa5ea drm/dp_mst: Fix fractional DSC bpp handling 41e7f4331308 drm/dp_mst: Add a way to calculate PBN values with FEC overhead 25a200eb8743 drm/dp_mst: Add helper to determine if an MST port is downstream of another port 24bf5adfae59 drm/dp_mst: Factor out a helper to check the atomic state of a topology manager f3ffe6554889 drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations 21f5901a18f8 drm/i915/dp_mst: Fix PBN calculation with FEC overhead 9a1abab8aa76 drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms 60fff6a4ea44 drm/i915/dp_mst: Program the DSC PPS SDP for each stream 4890fc83d5c6 drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled 32535a81601d drm/i915/dp_mst: Enable DSC decompression if any stream needs this 4867d9c884e6 drm/i915/dp_mst: Add missing DSC compression disabling b57b36c685a6 drm/i915/dp_mst: Allow DSC only for sink ports of the first branch device d09682322e32 drm/i915/dp_mst: Improve BW sharing between MST streams 54f569c34398 drm/i915/dp_mst: Check BW limitations only after all streams are computed
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/edid: Fixup h/vsync_end instead of h/vtotal
== Series Details == Series: drm/edid: Fixup h/vsync_end instead of h/vtotal URL : https://patchwork.freedesktop.org/series/123685/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13633_full -> Patchwork_123685v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_123685v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_123685v1_full, please notify your bug team (lgci.bug.fil...@intel.com) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 10) -- Additional (1): shard-rkl0 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_123685v1_full: ### IGT changes ### Possible regressions * igt@gem_exec_suspend@basic-s0@smem: - shard-dg2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-dg2-11/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/shard-dg2-2/igt@gem_exec_suspend@basic...@smem.html * igt@perf_pmu@busy-idle@rcs0: - shard-rkl: [PASS][3] -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-rkl-6/igt@perf_pmu@busy-i...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/shard-rkl-6/igt@perf_pmu@busy-i...@rcs0.html Known issues Here are the changes found in Patchwork_123685v1_full that come from known issues: ### IGT changes ### Issues hit * igt@device_reset@unbind-cold-reset-rebind: - shard-mtlp: NOTRUN -> [SKIP][5] ([i915#7701]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/shard-mtlp-1/igt@device_re...@unbind-cold-reset-rebind.html * igt@drm_fdinfo@busy-hang@bcs0: - shard-dg2: NOTRUN -> [SKIP][6] ([i915#8414]) +10 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/shard-dg2-2/igt@drm_fdinfo@busy-h...@bcs0.html * igt@drm_fdinfo@virtual-busy: - shard-mtlp: NOTRUN -> [SKIP][7] ([i915#8414]) +1 other test skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/shard-mtlp-6/igt@drm_fdi...@virtual-busy.html * igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-smem-lmem0: - shard-dg2: [PASS][8] -> [INCOMPLETE][9] ([i915#7297]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-dg2-2/igt@gem_ccs@suspend-res...@xmajor-compressed-compfmt0-smem-lmem0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/shard-dg2-3/igt@gem_ccs@suspend-res...@xmajor-compressed-compfmt0-smem-lmem0.html * igt@gem_close_race@multigpu-basic-threads: - shard-dg2: NOTRUN -> [SKIP][10] ([i915#7697]) +1 other test skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/shard-dg2-11/igt@gem_close_r...@multigpu-basic-threads.html * igt@gem_create@create-ext-cpu-access-sanity-check: - shard-mtlp: NOTRUN -> [SKIP][11] ([i915#6335]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/shard-mtlp-3/igt@gem_cre...@create-ext-cpu-access-sanity-check.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-rkl: [PASS][12] -> [FAIL][13] ([i915#6268]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-rkl-4/igt@gem_ctx_e...@basic-nohangcheck.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/shard-rkl-1/igt@gem_ctx_e...@basic-nohangcheck.html - shard-tglu: [PASS][14] -> [FAIL][15] ([i915#6268]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-tglu-2/igt@gem_ctx_e...@basic-nohangcheck.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/shard-tglu-6/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-dg2: [PASS][16] -> [INCOMPLETE][17] ([i915#9162]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-dg2-3/igt@gem_ctx_isolation@preservation...@bcs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/shard-dg2-5/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-dg2: [PASS][18] -> [FAIL][19] ([fdo#103375]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-dg2-3/igt@gem_ctx_isolation@preservation...@rcs0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/shard-dg2-5/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_param@set-priority-not-supported: - shard-dg2: NOTRUN -> [SKIP][20] ([fdo#109314]) [20]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST (rev2)
== Series Details == Series: drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST (rev2) URL : https://patchwork.freedesktop.org/series/123157/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13633_full -> Patchwork_123157v2_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_123157v2_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_123157v2_full, please notify your bug team (lgci.bug.fil...@intel.com) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_123157v2_full: ### IGT changes ### Possible regressions * igt@gem_exec_suspend@basic-s0@smem: - shard-dg2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-dg2-11/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/shard-dg2-2/igt@gem_exec_suspend@basic...@smem.html * igt@kms_plane@plane-panning-top-left@pipe-a-planes: - shard-mtlp: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-mtlp-8/igt@kms_plane@plane-panning-top-l...@pipe-a-planes.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/shard-mtlp-5/igt@kms_plane@plane-panning-top-l...@pipe-a-planes.html Known issues Here are the changes found in Patchwork_123157v2_full that come from known issues: ### IGT changes ### Issues hit * igt@device_reset@unbind-cold-reset-rebind: - shard-mtlp: NOTRUN -> [SKIP][5] ([i915#7701]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/shard-mtlp-1/igt@device_re...@unbind-cold-reset-rebind.html * igt@drm_fdinfo@busy-hang@bcs0: - shard-dg2: NOTRUN -> [SKIP][6] ([i915#8414]) +10 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/shard-dg2-1/igt@drm_fdinfo@busy-h...@bcs0.html * igt@drm_fdinfo@virtual-busy-all: - shard-mtlp: NOTRUN -> [SKIP][7] ([i915#8414]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/shard-mtlp-1/igt@drm_fdi...@virtual-busy-all.html * igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-smem-lmem0: - shard-dg2: [PASS][8] -> [INCOMPLETE][9] ([i915#7297]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-dg2-2/igt@gem_ccs@suspend-res...@xmajor-compressed-compfmt0-smem-lmem0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/shard-dg2-1/igt@gem_ccs@suspend-res...@xmajor-compressed-compfmt0-smem-lmem0.html * igt@gem_close_race@multigpu-basic-threads: - shard-dg2: NOTRUN -> [SKIP][10] ([i915#7697]) +1 other test skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/shard-dg2-3/igt@gem_close_r...@multigpu-basic-threads.html * igt@gem_ctx_freq@sysfs@gt0: - shard-dg2: [PASS][11] -> [FAIL][12] ([i915#6786]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/shard-dg2-6/igt@gem_ctx_freq@sy...@gt0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/shard-dg2-6/igt@gem_ctx_freq@sy...@gt0.html * igt@gem_ctx_param@set-priority-not-supported: - shard-dg2: NOTRUN -> [SKIP][13] ([fdo#109314]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/shard-dg2-1/igt@gem_ctx_pa...@set-priority-not-supported.html * igt@gem_ctx_persistence@engines-hostile-preempt: - shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1099]) +1 other test skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/shard-snb5/igt@gem_ctx_persiste...@engines-hostile-preempt.html * igt@gem_eio@in-flight-suspend: - shard-mtlp: NOTRUN -> [ABORT][15] ([i915#7892] / [i915#9262]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/shard-mtlp-1/igt@gem_...@in-flight-suspend.html * igt@gem_exec_balancer@bonded-false-hang: - shard-dg2: NOTRUN -> [SKIP][16] ([i915#4812]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/shard-dg2-3/igt@gem_exec_balan...@bonded-false-hang.html * igt@gem_exec_fair@basic-none-rrul: - shard-dg2: NOTRUN -> [SKIP][17] ([i915#3539] / [i915#4852]) +1 other test skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/shard-dg2-1/igt@gem_exec_f...@basic-none-rrul.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [PASS][18] -> [FAIL][19] ([i915#2842]) [18]:
[Intel-gfx] [PATCH] i915/guc: Get runtime pm in busyness worker only if already active
Ideally the busyness worker should take a gt pm wakeref because the
worker only needs to be active while gt is awake. However, the gt_park
path cancels the worker synchronously and this complicates the flow if
the worker is also running at the same time. The cancel waits for the
worker and when the worker releases the wakeref, that would call gt_park
and would lead to a deadlock.
The resolution is to take the global pm wakeref if runtime pm is already
active. If not, we don't need to update the busyness stats as the stats
would already be updated when the gt was parked.
Note:
- We do not requeue the worker if we cannot take a reference to runtime
pm since intel_guc_busyness_unpark would requeue the worker in the
resume path.
- If the gt was parked longer than time taken for GT timestamp to roll
over, we ignore those rollovers since we don't care about tracking the
exact GT time. We only care about roll overs when the gt is active and
running workloads.
- There is a window of time between gt_park and runtime suspend, where
the worker may run. This is acceptable since the worker will not find
any new data to update busyness.
v2: (Daniele)
- Edit commit message and code comment
- Use runtime pm in the worker
- Put runtime pm after enabling the worker
- Use Link tag and add Fixes tag
v3: (Daniele)
- Reword commit and comments and add details
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7077
Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
pmu")
Signed-off-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 38 +--
1 file changed, 35 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index cabdc645fcdd..ae3495a9c814 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1432,6 +1432,36 @@ static void guc_timestamp_ping(struct work_struct *wrk)
unsigned long index;
int srcu, ret;
+ /*
+* Ideally the busyness worker should take a gt pm wakeref because the
+* worker only needs to be active while gt is awake. However, the
+* gt_park path cancels the worker synchronously and this complicates
+* the flow if the worker is also running at the same time. The cancel
+* waits for the worker and when the worker releases the wakeref, that
+* would call gt_park and would lead to a deadlock.
+*
+* The resolution is to take the global pm wakeref if runtime pm is
+* already active. If not, we don't need to update the busyness stats as
+* the stats would already be updated when the gt was parked.
+*
+* Note:
+* - We do not requeue the worker if we cannot take a reference to
runtime
+* pm since intel_guc_busyness_unpark would requeue the worker in the
+* resume path.
+*
+* - If the gt was parked longer than time taken for GT timestamp to
roll
+* over, we ignore those rollovers since we don't care about tracking
+* the exact GT time. We only care about roll overs when the gt is
+* active and running workloads.
+*
+* - There is a window of time between gt_park and runtime suspend,
+* where the worker may run. This is acceptable since the worker will
+* not find any new data to update busyness.
+*/
+ wakeref = intel_runtime_pm_get_if_active(>i915->runtime_pm);
+ if (!wakeref)
+ return;
+
/*
* Synchronize with gt reset to make sure the worker does not
* corrupt the engine/guc stats. NB: can't actually block waiting
@@ -1440,10 +1470,9 @@ static void guc_timestamp_ping(struct work_struct *wrk)
*/
ret = intel_gt_reset_trylock(gt, );
if (ret)
- return;
+ goto err_trylock;
- with_intel_runtime_pm(>i915->runtime_pm, wakeref)
- __update_guc_busyness_stats(guc);
+ __update_guc_busyness_stats(guc);
/* adjust context stats for overflow */
xa_for_each(>context_lookup, index, ce)
@@ -1452,6 +1481,9 @@ static void guc_timestamp_ping(struct work_struct *wrk)
intel_gt_reset_unlock(gt, srcu);
guc_enable_busyness_worker(guc);
+
+err_trylock:
+ intel_runtime_pm_put(>i915->runtime_pm, wakeref);
}
static int guc_action_enable_usage_stats(struct intel_guc *guc)
--
2.38.1
[Intel-gfx] ✓ Fi.CI.BAT: success for Enable Wa_14018913170 on DG2/MTL/PVD
== Series Details ==
Series: Enable Wa_14018913170 on DG2/MTL/PVD
URL : https://patchwork.freedesktop.org/series/123736/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13633 -> Patchwork_123736v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123736v1/index.html
Participating hosts (40 -> 38)
--
Missing(2): fi-hsw-4770 fi-snb-2520m
Known issues
Here are the changes found in Patchwork_123736v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_busy@busy@all-engines:
- bat-mtlp-8: [PASS][1] -> [DMESG-FAIL][2] ([i915#8962] /
[i915#9121])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-mtlp-8/igt@gem_busy@b...@all-engines.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123736v1/bat-mtlp-8/igt@gem_busy@b...@all-engines.html
* igt@gem_exec_suspend@basic-s0@lmem0:
- bat-dg2-9: [PASS][3] -> [INCOMPLETE][4] ([i915#9275])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123736v1/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-x1275: [PASS][5] -> [DMESG-FAIL][6] ([i915#5334] /
[i915#7872])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-kbl-x1275/igt@i915_selftest@live@gt_heartbeat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123736v1/fi-kbl-x1275/igt@i915_selftest@live@gt_heartbeat.html
- fi-apl-guc: [PASS][7] -> [DMESG-FAIL][8] ([i915#5334])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123736v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [PASS][9] -> [FAIL][10] ([fdo#103375])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123736v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-adlp-9: NOTRUN -> [SKIP][11] ([i915#3546]) +2 other tests skip
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123736v1/bat-adlp-9/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [ABORT][12] ([i915#7911] / [i915#7913]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123736v1/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-dg2-9: [WARN][14] -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-9/igt@i915_susp...@basic-s2idle-without-i915.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123736v1/bat-dg2-9/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_chamelium_edid@hdmi-edid-read:
- {bat-dg2-13}: [DMESG-WARN][16] ([i915#7952]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-13/igt@kms_chamelium_e...@hdmi-edid-read.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123736v1/bat-dg2-13/igt@kms_chamelium_e...@hdmi-edid-read.html
* igt@kms_chamelium_frames@dp-crc-fast:
- {bat-dg2-13}: [DMESG-WARN][18] ([Intel XE#485]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-13/igt@kms_chamelium_fra...@dp-crc-fast.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123736v1/bat-dg2-13/igt@kms_chamelium_fra...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#485]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/485
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952
[i915#8962]: https://gitlab.freedesktop.org/drm/intel/issues/8962
[i915#9121]: https://gitlab.freedesktop.org/drm/intel/issues/9121
[i915#9275]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable Wa_14018913170 on DG2/MTL/PVD
== Series Details == Series: Enable Wa_14018913170 on DG2/MTL/PVD URL : https://patchwork.freedesktop.org/series/123736/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add Wa_18022495364 (rev2)
== Series Details ==
Series: drm/i915: Add Wa_18022495364 (rev2)
URL : https://patchwork.freedesktop.org/series/123721/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13633 -> Patchwork_123721v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123721v2/index.html
Participating hosts (40 -> 38)
--
Missing(2): fi-snb-2520m fi-pnv-d510
Known issues
Here are the changes found in Patchwork_123721v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][1] -> [DMESG-FAIL][2] ([i915#5334])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123721v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [ABORT][3] ([i915#7911] / [i915#7913]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123721v2/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-dg2-9: [WARN][5] -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-9/igt@i915_susp...@basic-s2idle-without-i915.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123721v2/bat-dg2-9/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_chamelium_frames@dp-crc-fast:
- {bat-dg2-13}: [DMESG-WARN][7] ([Intel XE#485]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-13/igt@kms_chamelium_fra...@dp-crc-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123721v2/bat-dg2-13/igt@kms_chamelium_fra...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#485]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/485
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
Build changes
-
* Linux: CI_DRM_13633 -> Patchwork_123721v2
CI-20190529: 20190529
CI_DRM_13633: 5cf0e59ecc1424e51a5f5cf2f26682b5dcea5a25 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7488: 099e058c5dfb7a49942edf03cae88a52a77077a3 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_123721v2: 5cf0e59ecc1424e51a5f5cf2f26682b5dcea5a25 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
79a2bf6dc691 drm/i915: Add Wa_18022495364
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123721v2/index.html
[Intel-gfx] [PATCH v4 09/25] drm/i915: Add helpers for BW management on shared display links
At the moment a modeset fails if the config computation of a pipe can't
fit its required BW to the available link BW even though the limitation
may be resolved by reducing the BW requirement of other pipes.
To improve the above this patch adds helper functions checking the
overall BW limits after all CRTC states have been computed. If the check
fails the maximum link bpp for a selected pipe will be reduced and all
the CRTC states will be recomputed until either the overall BW limit
check passes, or further bpp reduction is not possible (because all
pipes/encoders sharing the link BW reached their minimum link bpp).
This change prepares for upcoming patches enabling the above BW
management on FDI and MST links.
v2:
- Rename intel_crtc_state::max_link_bpp to max_link_bpp_x16 and
intel_link_bw_limits::max_bpp to max_bpp_x16. (Jani)
v3:
- Add the helper functions in a separate patch. (Ville)
- Add the functions to intel_link_bw.c instead of intel_atomic.c (Ville)
- Return -ENOSPC instead of -EINVAL to userspace in case of a link BW
limit failure.
v4:
- Make intel_atomic_check_config() static.
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_crtc.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 61 -
.../drm/i915/display/intel_display_types.h| 3 +-
drivers/gpu/drm/i915/display/intel_link_bw.c | 226 ++
drivers/gpu/drm/i915/display/intel_link_bw.h | 38 +++
6 files changed, 325 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_link_bw.c
create mode 100644 drivers/gpu/drm/i915/display/intel_link_bw.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1b2e02e9d92cb..de4967c141f00 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -268,6 +268,7 @@ i915-y += \
display/intel_hotplug.o \
display/intel_hotplug_irq.o \
display/intel_hti.o \
+ display/intel_link_bw.o \
display/intel_load_detect.o \
display/intel_lpe_audio.o \
display/intel_modeset_lock.o \
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 182c6dd64f47c..1eda6a9f19aa8 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -175,6 +175,7 @@ void intel_crtc_state_reset(struct intel_crtc_state
*crtc_state,
crtc_state->hsw_workaround_pipe = INVALID_PIPE;
crtc_state->scaler_state.scaler_id = -1;
crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
+ crtc_state->max_link_bpp_x16 = INT_MAX;
}
static struct intel_crtc *intel_crtc_alloc(void)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index fe3b6844e063d..0f30723a68cc0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -87,6 +87,7 @@
#include "intel_frontbuffer.h"
#include "intel_hdmi.h"
#include "intel_hotplug.h"
+#include "intel_link_bw.h"
#include "intel_lvds.h"
#include "intel_lvds_regs.h"
#include "intel_modeset_setup.h"
@@ -4596,7 +4597,8 @@ intel_crtc_prepare_cleared_state(struct
intel_atomic_state *state,
static int
intel_modeset_pipe_config(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+ struct intel_crtc *crtc,
+ const struct intel_link_bw_limits *limits)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
@@ -4628,6 +4630,15 @@ intel_modeset_pipe_config(struct intel_atomic_state
*state,
if (ret)
return ret;
+ crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
+
+ if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {
+ drm_dbg_kms(>drm,
+ "[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT
"\n",
+ crtc->base.base.id, crtc->base.name,
+ BPP_X16_ARGS(crtc_state->max_link_bpp_x16));
+ }
+
base_bpp = crtc_state->pipe_bpp;
/*
@@ -6195,7 +6206,9 @@ static int intel_bigjoiner_add_affected_crtcs(struct
intel_atomic_state *state)
return 0;
}
-static int intel_atomic_check_config(struct intel_atomic_state *state)
+static int intel_atomic_check_config(struct intel_atomic_state *state,
+struct intel_link_bw_limits *limits,
+enum pipe *failed_pipe)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state;
@@ -6203,6 +6216,8 @@ static int intel_atomic_check_config(struct
intel_atomic_state *state)
int ret;
int i;
+ *failed_pipe = INVALID_PIPE;
+
[Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123
== Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 URL : https://patchwork.freedesktop.org/series/123723/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13633 -> Patchwork_123723v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_123723v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_123723v1, please notify your bug team (lgci.bug.fil...@intel.com) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123723v1/index.html Participating hosts (40 -> 40) -- Additional (1): fi-kbl-soraka Missing(1): fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_123723v1: ### IGT changes ### Possible regressions * igt@gem_render_linear_blits@basic: - fi-rkl-11600: [PASS][1] -> [FAIL][2] +3 other tests fail [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-rkl-11600/igt@gem_render_linear_bl...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123723v1/fi-rkl-11600/igt@gem_render_linear_bl...@basic.html - bat-adls-5: [PASS][3] -> [FAIL][4] +2 other tests fail [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-adls-5/igt@gem_render_linear_bl...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123723v1/bat-adls-5/igt@gem_render_linear_bl...@basic.html - bat-dg1-5: [PASS][5] -> [FAIL][6] +1 other test fail [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg1-5/igt@gem_render_linear_bl...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123723v1/bat-dg1-5/igt@gem_render_linear_bl...@basic.html - bat-mtlp-6: [PASS][7] -> [FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-mtlp-6/igt@gem_render_linear_bl...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123723v1/bat-mtlp-6/igt@gem_render_linear_bl...@basic.html * igt@gem_render_tiled_blits@basic: - bat-adlp-9: [PASS][9] -> [FAIL][10] +3 other tests fail [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-adlp-9/igt@gem_render_tiled_bl...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123723v1/bat-adlp-9/igt@gem_render_tiled_bl...@basic.html - bat-rplp-1: [PASS][11] -> [FAIL][12] +3 other tests fail [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-rplp-1/igt@gem_render_tiled_bl...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123723v1/bat-rplp-1/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-adlm-1: [PASS][13] -> [FAIL][14] +2 other tests fail [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-adlm-1/igt@gem_tiled_bl...@basic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123723v1/bat-adlm-1/igt@gem_tiled_bl...@basic.html - fi-tgl-1115g4: [PASS][15] -> [FAIL][16] +3 other tests fail [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-tgl-1115g4/igt@gem_tiled_bl...@basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123723v1/fi-tgl-1115g4/igt@gem_tiled_bl...@basic.html - bat-rpls-1: [PASS][17] -> [FAIL][18] +2 other tests fail [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-rpls-1/igt@gem_tiled_bl...@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123723v1/bat-rpls-1/igt@gem_tiled_bl...@basic.html * igt@kms_frontbuffer_tracking@basic: - bat-adlp-11:[PASS][19] -> [FAIL][20] +3 other tests fail [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-adlp-11/igt@kms_frontbuffer_track...@basic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123723v1/bat-adlp-11/igt@kms_frontbuffer_track...@basic.html - bat-adln-1: [PASS][21] -> [FAIL][22] +3 other tests fail [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-adln-1/igt@kms_frontbuffer_track...@basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123723v1/bat-adln-1/igt@kms_frontbuffer_track...@basic.html - bat-mtlp-8: [PASS][23] -> [FAIL][24] +1 other test fail [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-mtlp-8/igt@kms_frontbuffer_track...@basic.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123723v1/bat-mtlp-8/igt@kms_frontbuffer_track...@basic.html - bat-adlp-6: [PASS][25] -> [FAIL][26] +3 other tests fail [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-adlp-6/igt@kms_frontbuffer_track...@basic.html [26]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Apply Wa_16018031267 / Wa_16018063123
== Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 URL : https://patchwork.freedesktop.org/series/123723/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply Wa_16018031267 / Wa_16018063123
== Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 URL : https://patchwork.freedesktop.org/series/123723/ State : warning == Summary == Error: dim checkpatch failed f7190f348d57 drm/i915: Reserve some kernel space per vm -:31: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #31: FILE: drivers/gpu/drm/i915/gt/gen8_ppgtt.c:1018: + GEM_BUG_ON(drm_mm_reserve_node(>vm.mm, >vm.rsvd)); total: 0 errors, 1 warnings, 0 checks, 26 lines checked 860ac811e86d drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 -:10: WARNING:BAD_SIGN_OFF: Co-developed-by and Signed-off-by: name/email do not match #10: Co-developed-by: Nirmoy Das Signed-off-by: Jonathan Cavitt -:35: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine' - possible side-effects? #35: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:86: +#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \ + IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 55), IP_VER(12, 71)) && \ + engine->class == COPY_ENGINE_CLASS) -:35: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'engine' may be better as '(engine)' to avoid precedence issues #35: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:86: +#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \ + IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 55), IP_VER(12, 71)) && \ + engine->class == COPY_ENGINE_CLASS) -:68: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #68: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:836: + GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1); -:183: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #183: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:1462: + GEM_BUG_ON(cs - start > I915_GTT_PAGE_SIZE / sizeof(*cs)); total: 0 errors, 3 warnings, 2 checks, 316 lines checked 9681c5015749 drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/uapi: Enable L3 Bank Count Querying
== Series Details ==
Series: drm/i915/uapi: Enable L3 Bank Count Querying
URL : https://patchwork.freedesktop.org/series/123718/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13633 -> Patchwork_123718v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_123718v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_123718v1, please notify your bug team
(lgci.bug.fil...@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123718v1/index.html
Participating hosts (40 -> 39)
--
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_123718v1:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@hangcheck:
- bat-rpls-1: [PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-rpls-1/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123718v1/bat-rpls-1/igt@i915_selftest@l...@hangcheck.html
Known issues
Here are the changes found in Patchwork_123718v1 that come from known issues:
### CI changes ###
Possible fixes
* boot:
- fi-hsw-4770:[FAIL][3] ([i915#8293]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-hsw-4770/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123718v1/fi-hsw-4770/boot.html
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s0@smem:
- bat-dg2-9: [PASS][5] -> [INCOMPLETE][6] ([i915#9275])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123718v1/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271]) +13 other tests
skip
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123718v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [PASS][8] -> [FAIL][9] ([IGT#3] / [i915#6121])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123718v1/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1:
- fi-hsw-4770:NOTRUN -> [DMESG-WARN][10] ([i915#8841]) +6 other
tests dmesg-warn
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123718v1/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-vga-1.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#1072]) +3
other tests skip
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123718v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [ABORT][12] ([i915#7911] / [i915#7913]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123718v1/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-dg2-9: [WARN][14] -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-9/igt@i915_susp...@basic-s2idle-without-i915.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123718v1/bat-dg2-9/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_chamelium_frames@dp-crc-fast:
- {bat-dg2-13}: [DMESG-WARN][16] ([Intel XE#485]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-13/igt@kms_chamelium_fra...@dp-crc-fast.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123718v1/bat-dg2-13/igt@kms_chamelium_fra...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[Intel XE#485]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/485
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]:
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve BW management on shared display links (rev4)
== Series Details == Series: drm/i915: Improve BW management on shared display links (rev4) URL : https://patchwork.freedesktop.org/series/122589/ State : failure == Summary == Error: make failed CALLscripts/checksyscalls.sh DESCEND objtool INSTALL libsubcmd_headers CC [M] drivers/gpu/drm/i915/display/intel_display.o drivers/gpu/drm/i915/display/intel_display.c:6198:5: error: no previous prototype for ‘intel_atomic_check_config’ [-Werror=missing-prototypes] 6198 | int intel_atomic_check_config(struct intel_atomic_state *state, | ^ cc1: all warnings being treated as errors make[6]: *** [scripts/Makefile.build:243: drivers/gpu/drm/i915/display/intel_display.o] Error 1 make[5]: *** [scripts/Makefile.build:480: drivers/gpu/drm/i915] Error 2 make[4]: *** [scripts/Makefile.build:480: drivers/gpu/drm] Error 2 make[3]: *** [scripts/Makefile.build:480: drivers/gpu] Error 2 make[2]: *** [scripts/Makefile.build:480: drivers] Error 2 make[1]: *** [/home/kbuild2/kernel/Makefile:1913: .] Error 2 make: *** [Makefile:234: __sub-make] Error 2 Build failed, no error log produced
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/uapi: Enable L3 Bank Count Querying
== Series Details == Series: drm/i915/uapi: Enable L3 Bank Count Querying URL : https://patchwork.freedesktop.org/series/123718/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH 12/12] drm/i915: Implement transcoder LRR for TGL+
On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> Implement low refresh rate (LRR) where we change the vblank
> length by hand as requested, but otherwise keep the timing
> generator running in non-VRR mode (ie. fixed refresh rate).
>
> The panel itself must support VRR for this to work, and
> only TGL+ has the double buffred TRANS_VTOTAL.VTOTAL that
> we need to make the switch properly. The double buffer
> latching happens at the start of transcoders undelayed
> vblank. The other thing that we change is
> TRANS_VBLANK.VBLANK_END but the hardware entirely ignores
> that in DP mode. But I decided to keep writing it anyway
> just to avoid more special cases in readout/state check.
>
> v2: Document that TRANS_VBLANK.VBLANK_END is ignored by
> the hardware
> v3: Reconcile with VRR fastset
> Adjust update_lrr flag behaviour
> Make sure timings stay within VRR range
>
> TODO: Hook LRR into the automatic DRRS downclocking stuff?
>
> Cc: Manasi Navare
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
> drivers/gpu/drm/i915/display/intel_crtc.c | 9 +--
> drivers/gpu/drm/i915/display/intel_display.c | 60 +--
> .../drm/i915/display/intel_display_device.h | 1 +
> .../drm/i915/display/intel_display_types.h| 3 +-
> drivers/gpu/drm/i915/display/intel_vrr.c | 7 ++-
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 7 files changed, 71 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index aaddd8c0cfa0..5d18145da279 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -260,6 +260,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>
> crtc_state->update_pipe = false;
> crtc_state->update_m_n = false;
> + crtc_state->update_lrr = false;
> crtc_state->disable_lp_wm = false;
> crtc_state->disable_cxsr = false;
> crtc_state->update_wm_pre = false;
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index a39e31c1ca85..22e85fe7e8aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -495,7 +495,7 @@ static void intel_crtc_vblank_evade_scanlines(struct
> intel_atomic_state *state,
> if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> /* timing changes should happen with VRR disabled */
> drm_WARN_ON(state->base.dev,
> intel_crtc_needs_modeset(new_crtc_state) ||
> - new_crtc_state->update_m_n);
> + new_crtc_state->update_m_n ||
> new_crtc_state->update_lrr);
>
> if (intel_vrr_is_push_sent(crtc_state))
> *vblank_start =
> intel_vrr_vmin_vblank_start(crtc_state);
> @@ -511,10 +511,11 @@ static void intel_crtc_vblank_evade_scanlines(struct
> intel_atomic_state *state,
> *max = *vblank_start - 1;
>
> /*
> -* M/N is double buffered on the transcoder's undelayed vblank,
> -* so with seamless M/N we must evade both vblanks.
> +* M/N and TRANS_VTOTAL are double buffered on the transcoder's
> +* undelayed vblank, so with seamless M/N and LRR we must evade
> +* both vblanks.
> */
> - if (new_crtc_state->update_m_n)
> + if (new_crtc_state->update_m_n || new_crtc_state->update_lrr)
> *min -= adjusted_mode->crtc_vblank_start -
> adjusted_mode->crtc_vdisplay;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f0bb5c70ebfc..74cca5af8b4e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -928,7 +928,7 @@ static bool vrr_enabling(const struct intel_crtc_state
> *old_crtc_state,
> {
> return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> (new_crtc_state->vrr.enable &&
> -(new_crtc_state->update_m_n ||
> +(new_crtc_state->update_m_n || new_crtc_state->update_m_n ||
Did you mean to add new_crtc_state->update_lrr in the condition for
vrr_enabling ?
> vrr_params_changed(old_crtc_state, new_crtc_state)));
> }
>
> @@ -937,7 +937,7 @@ static bool vrr_disabling(const struct intel_crtc_state
> *old_crtc_state,
> {
> return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> (old_crtc_state->vrr.enable &&
> -(new_crtc_state->update_m_n ||
> +(new_crtc_state->update_m_n || new_crtc_state->update_m_n ||
> vrr_params_changed(old_crtc_state, new_crtc_state)));
> }
>
> @@ -2586,6 +2586,37 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: move more of the display probe to display code (rev3)
== Series Details ==
Series: series starting with [1/3] drm/i915: move more of the display probe to
display code (rev3)
URL : https://patchwork.freedesktop.org/series/123600/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13633 -> Patchwork_123600v3
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123600v3/index.html
Participating hosts (40 -> 40)
--
Additional (1): fi-kbl-soraka
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_123600v3 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s0@lmem0:
- bat-dg2-9: [PASS][1] -> [INCOMPLETE][2] ([i915#9275])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123600v3/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123600v3/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3
other tests skip
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123600v3/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_module_load@reload:
- fi-apl-guc: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-apl-guc/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123600v3/fi-apl-guc/igt@i915_module_l...@reload.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][7] -> [DMESG-FAIL][8] ([i915#5334])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123600v3/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#7913])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123600v3/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@guc:
- fi-kbl-soraka: NOTRUN -> [ABORT][10] ([i915#7913])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123600v3/fi-kbl-soraka/igt@i915_selftest@l...@guc.html
* igt@kms_dsc@dsc-basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][11] ([fdo#109271]) +9 other tests
skip
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123600v3/fi-kbl-soraka/igt@kms_...@dsc-basic.html
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [PASS][12] -> [FAIL][13] ([IGT#3] / [i915#6121])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123600v3/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#1845]) +3 other tests skip
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123600v3/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [ABORT][15] ([i915#7911] / [i915#7913]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123600v3/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-dg2-9: [WARN][17] -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-9/igt@i915_susp...@basic-s2idle-without-i915.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123600v3/bat-dg2-9/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_chamelium_edid@hdmi-edid-read:
- {bat-dg2-13}: [DMESG-WARN][19] ([i915#7952]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-13/igt@kms_chamelium_e...@hdmi-edid-read.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123600v3/bat-dg2-13/igt@kms_chamelium_e...@hdmi-edid-read.html
* igt@kms_chamelium_frames@dp-crc-fast:
- {bat-dg2-13}: [DMESG-WARN][21] ([Intel XE#485]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-13/igt@kms_chamelium_fra...@dp-crc-fast.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123600v3/bat-dg2-13/igt@kms_chamelium_fra...@dp-crc-fast.html
{name}: This
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915: move more of the display probe to display code (rev3)
== Series Details == Series: series starting with [1/3] drm/i915: move more of the display probe to display code (rev3) URL : https://patchwork.freedesktop.org/series/123600/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] [PATCH 0/2] Enable Wa_14018913170 on DG2/MTL/PVD
From: John Harrison Enable a WA on the latest platforms. Also update the recommended GuC version for those platforms to the latest available. Further patches will follow to make use of other features in the latest GuC firmware, but the w/a at least requires something newer than what was previously in use. Signed-off-by: John Harrison Daniele Ceraolo Spurio (1): drm/i915/guc: Enable WA 14018913170 John Harrison (1): drm/i915/guc: Update 'recommended' version to 70.11.0 for DG2/ADL-P/MTL drivers/gpu/drm/i915/gt/uc/intel_guc.c | 6 ++ drivers/gpu/drm/i915/gt/uc/intel_guc.h | 1 + drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 + drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c| 6 +++--- 4 files changed, 11 insertions(+), 3 deletions(-) -- 2.41.0
[Intel-gfx] [PATCH 2/2] drm/i915/guc: Enable WA 14018913170
From: Daniele Ceraolo Spurio
The GuC handles the WA, the KMD just needs to set the flag to enable
it on the appropriate platforms.
Signed-off-by: John Harrison
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 6 ++
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 +
3 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 27df41c53b890..3f3df1166b860 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -319,6 +319,12 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
if (!RCS_MASK(gt))
flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
+ /* Wa_14018913170 */
+ if (GUC_FIRMWARE_VER(guc) >= MAKE_GUC_VER(70, 7, 0)) {
+ if (IS_DG2(gt->i915) || IS_METEORLAKE(gt->i915) ||
IS_PONTEVECCHIO(gt->i915))
+ flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6;
+ }
+
return flags;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 6c392bad29c19..818c8c146fd47 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -295,6 +295,7 @@ struct intel_guc {
#define MAKE_GUC_VER(maj, min, pat)(((maj) << 16) | ((min) << 8) | (pat))
#define MAKE_GUC_VER_STRUCT(ver) MAKE_GUC_VER((ver).major, (ver).minor,
(ver).patch)
#define GUC_SUBMIT_VER(guc)
MAKE_GUC_VER_STRUCT((guc)->submission_version)
+#define GUC_FIRMWARE_VER(guc)
MAKE_GUC_VER_STRUCT((guc)->fw.file_selected.ver)
static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)
{
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index b4d56eccfb1f0..123ad75d2eb28 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -100,6 +100,7 @@
#define GUC_WA_HOLD_CCS_SWITCHOUTBIT(17)
#define GUC_WA_POLLCSBIT(18)
#define GUC_WA_RCS_REGS_IN_CCS_REGS_LIST BIT(21)
+#define GUC_WA_ENABLE_TSC_CHECK_ON_RC6 BIT(22)
#define GUC_CTL_FEATURE2
#define GUC_CTL_ENABLE_SLPC BIT(2)
--
2.41.0
[Intel-gfx] [PATCH 1/2] drm/i915/guc: Update 'recommended' version to 70.11.0 for DG2/ADL-P/MTL
From: John Harrison The latest GuC has new features and new workarounds that we wish to enable. So let the universe know that it is useful to update their firmware. Signed-off-by: John Harrison --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 32e27e9a2490f..a40f96c98308b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -88,9 +88,9 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, * security fixes, etc. to be enabled. */ #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_maj, guc_mmp) \ - fw_def(METEORLAKE, 0, guc_maj(mtl, 70, 6, 6)) \ - fw_def(DG2, 0, guc_maj(dg2, 70, 5, 1)) \ - fw_def(ALDERLAKE_P, 0, guc_maj(adlp, 70, 5, 1)) \ + fw_def(METEORLAKE, 0, guc_maj(mtl, 70, 11, 0)) \ + fw_def(DG2, 0, guc_maj(dg2, 70, 11, 0)) \ + fw_def(ALDERLAKE_P, 0, guc_maj(adlp, 70, 11, 0)) \ fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 70, 1, 1)) \ fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 69, 0, 3)) \ fw_def(ALDERLAKE_S, 0, guc_maj(tgl, 70, 5, 1)) \ -- 2.41.0
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Added Wa_18022495364 (rev5)
== Series Details == Series: drm/i915: Added Wa_18022495364 (rev5) URL : https://patchwork.freedesktop.org/series/123377/ State : success == Summary == CI Bug Log - changes from CI_DRM_13633 -> Patchwork_123377v5 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/index.html Participating hosts (40 -> 41) -- Additional (2): fi-kbl-soraka bat-dg2-8 Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_123377v5 that come from known issues: ### CI changes ### Possible fixes * boot: - fi-hsw-4770:[FAIL][1] ([i915#8293]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-hsw-4770/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/fi-hsw-4770/boot.html ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s0@lmem0: - bat-dg2-8: NOTRUN -> [INCOMPLETE][3] ([i915#9275]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/bat-dg2-8/igt@gem_exec_suspend@basic...@lmem0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_mmap@basic: - bat-dg2-8: NOTRUN -> [SKIP][6] ([i915#4083]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/bat-dg2-8/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-dg2-8: NOTRUN -> [SKIP][7] ([i915#4077]) +2 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/bat-dg2-8/igt@gem_mmap_...@basic.html * igt@gem_tiled_pread_basic: - bat-dg2-8: NOTRUN -> [SKIP][8] ([i915#4079]) +1 other test skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/bat-dg2-8/igt@gem_tiled_pread_basic.html * igt@i915_module_load@reload: - fi-kbl-soraka: NOTRUN -> [DMESG-WARN][9] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/fi-kbl-soraka/igt@i915_module_l...@reload.html * igt@i915_pm_rps@basic-api: - bat-dg2-8: NOTRUN -> [SKIP][10] ([i915#6621]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/bat-dg2-8/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][11] ([i915#1886] / [i915#7913]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_suspend@basic-s3-without-i915: - bat-dg2-8: NOTRUN -> [SKIP][12] ([i915#6645]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/bat-dg2-8/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271]) +13 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html - bat-dg2-8: NOTRUN -> [SKIP][14] ([i915#5190]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/bat-dg2-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-8: NOTRUN -> [SKIP][15] ([i915#4215] / [i915#5190]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/bat-dg2-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_addfb_basic@framebuffer-vs-set-tiling: - bat-dg2-8: NOTRUN -> [SKIP][16] ([i915#4212]) +7 other tests skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/bat-dg2-8/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-dg2-8: NOTRUN -> [SKIP][17] ([i915#4103] / [i915#4213]) +1 other test skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/bat-dg2-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - fi-kbl-soraka: NOTRUN -> [SKIP][18] ([fdo#109271]) +9 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/fi-kbl-soraka/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-8: NOTRUN -> [SKIP][19] ([fdo#109285]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123377v5/bat-dg2-8/igt@kms_force_connector_ba...@force-load-detect.html *
[Intel-gfx] [CI] PR for new GuC v70.11.0
The following changes since commit dfa11466cf000120d1551146fd5bf78c44941eda: Merge branch 'main' into 'main' (2023-09-07 11:36:57 +) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware guc_70.11.0 for you to fetch changes up to af0fdbdde5b3e2318aefa4db00115c808a9cfe2d: i915: Add GuC v70.11.0 for DG2, ADL-P and MTL (2023-09-14 14:25:18 -0700) John Harrison (1): i915: Add GuC v70.11.0 for DG2, ADL-P and MTL WHENCE | 6 +++--- i915/adlp_guc_70.bin | Bin 297984 -> 341696 bytes i915/dg2_guc_70.bin | Bin 385856 -> 443200 bytes i915/mtl_guc_70.bin | Bin 308032 -> 365376 bytes 4 files changed, 3 insertions(+), 3 deletions(-)
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/fbc: Remove ancient 16k plane stride limit
== Series Details ==
Series: series starting with [1/5] drm/i915/fbc: Remove ancient 16k plane
stride limit
URL : https://patchwork.freedesktop.org/series/123687/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13633 -> Patchwork_123687v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123687v1/index.html
Participating hosts (40 -> 40)
--
Additional (1): fi-kbl-soraka
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_123687v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123687v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3
other tests skip
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123687v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][3] ([i915#1886] / [i915#7913])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123687v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_dsc@dsc-basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271]) +9 other tests skip
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123687v1/fi-kbl-soraka/igt@kms_...@dsc-basic.html
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [PASS][5] -> [FAIL][6] ([IGT#3] / [i915#6121])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123687v1/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#1845]) +3 other tests skip
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123687v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [ABORT][8] ([i915#7911] / [i915#7913]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123687v1/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-dg2-9: [WARN][10] -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-9/igt@i915_susp...@basic-s2idle-without-i915.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123687v1/bat-dg2-9/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_chamelium_frames@dp-crc-fast:
- {bat-dg2-13}: [DMESG-WARN][12] ([Intel XE#485]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-13/igt@kms_chamelium_fra...@dp-crc-fast.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123687v1/bat-dg2-13/igt@kms_chamelium_fra...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[Intel XE#485]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/485
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
Build changes
-
* Linux: CI_DRM_13633 -> Patchwork_123687v1
CI-20190529: 20190529
CI_DRM_13633: 5cf0e59ecc1424e51a5f5cf2f26682b5dcea5a25 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7488: 099e058c5dfb7a49942edf03cae88a52a77077a3 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_123687v1: 5cf0e59ecc1424e51a5f5cf2f26682b5dcea5a25 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
1622a2dd32c6 drm/i915/fbc: Split plane pixel format checks per-platform
41ce6dbbbe51 drm/i915/fbc: Split plane rotation checks per-platform
899e9d6cc831 drm/i915/fbc: Split plane tiling checks per-platform
8899b49bda6b drm/i915/fbc: Split plane stride checks per-platform
7085df43df5d drm/i915/fbc: Remove ancient 16k plane stride limit
== Logs ==
[Intel-gfx] [PATCH v7] drm/i915: Add Wa_18022495364
Invalidate instruction and State cache bit using INDIRECT_CTX on
every gpu context switch for gen12.
The goal of this workaround is to actually perform an explicit
invalidation of that cache (by re-writing the register) during every GPU
context switch, which is accomplished via a "workaround batchbuffer"
that's attached to the context via INDIRECT_CTX. (Matt Roper)
BSpec: 11354
Please refer [1] for more reviews and comment on the same patch
[1] https://patchwork.freedesktop.org/series/123377/
v2:
- Remove extra parentheses from the condition (Lucas)
- Align spacing and new line (Lucas)
v3:
- Fix commit message.
v4:
- Only Gen12 changes are kept and Remove DG2+ condition (Matt Roper)
- Fix the commit message for r-b (Matt Roper)
- Rename the register bit in define
v5:
- Move out this workaround from golden context init (Matt Roper)
- Use INDIRECT_CTX to set bit on each GPU context switch (Matt Roper)
v6:
- Change IP Version base condition for Gen12 (Matt Roper)
- Made imperative form of commit version messages (Suraj)
- s/Added/Add in patch header (Suraj)
v7:
- In version descriptions s/Ropper/Roper (Matt Atwood)
Cc: Lucas De Marchi
Cc: Matt Roper
Cc: Suraj Kandpal
Cc: Matt Atwood
Signed-off-by: Dnyaneshwar Bhadane
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 13 +
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index a00ff51c681d..0d5260d126d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -164,6 +164,8 @@
#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20d4)
#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
+#define GEN12_CS_DEBUG_MODE2 _MMIO(0x20d8)
+#define INSTRUCTION_STATE_CACHE_INVALIDATE REG_BIT(6)
#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
#define GEN9_FFSC_PERCTX_PREEMPT_CTRL(1 << 14)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b99efa348ad1..56c916730e9b 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1333,6 +1333,15 @@ dg2_emit_draw_watermark_setting(u32 *cs)
return cs;
}
+static u32 *
+gen12_invalidate_state_cache(u32 *cs)
+{
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = i915_mmio_reg_offset(GEN12_CS_DEBUG_MODE2);
+ *cs++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);
+ return cs;
+}
+
static u32 *
gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
{
@@ -1346,6 +1355,10 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context
*ce, u32 *cs)
cs = gen12_emit_aux_table_inv(ce->engine, cs);
+ /* Wa_18022495364 */
+ if (IS_GFX_GT_IP_RANGE(ce->engine->gt, IP_VER(12, 0), IP_VER(12, 10)))
+ cs = gen12_invalidate_state_cache(cs);
+
/* Wa_16014892111 */
if (IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0)
||
IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)
||
--
2.34.1
Re: [Intel-gfx] [PATCH v6] drm/i915: Add Wa_18022495364
On Fri, Sep 15, 2023 at 01:10:32AM +0530, Dnyaneshwar Bhadane wrote:
> Invalidate instruction and State cache bit using INDIRECT_CTX on
> every gpu context switch for gen12.
> The goal of this workaround is to actually perform an explicit
> invalidation of that cache (by re-writing the register) during every GPU
> context switch, which is accomplished via a "workaround batchbuffer"
> that's attached to the context via INDIRECT_CTX. (Matt Ropper)
> BSpec: 11354
>
> Please refer [1] for more reviews and comment on the same patch
>
> [1] https://patchwork.freedesktop.org/patch/556154/
>
> v2:
> - Remove extra parentheses from the condition (Lucas)
> - Align spacing and new line (Lucas)
>
> v3:
> - Fix commit message.
>
> v4:
> - Only GEN12 changes are kept (Matt Ropper)
> - Fix the commit message for r-b (Matt Ropper)
> - Rename the register bit in define
>
> v5:
> - Move out this workaround from golden context init (Matt Roper)
> - Use INDIRECT_CTX to set bit on each GPU context switch (Matt Roper)
>
> v6:
> - Change IP Version base condition for Gen12 (Matt Ropper)
> - Made imperative form of commit version messages (Suraj)
> - s/Added/Add in patch header (Suraj)
>
> Cc: Lucas De Marchi
> Cc: Matt Roper
> Cc: Suraj Kandpal
> Signed-off-by: Dnyaneshwar Bhadane
Reviewed-by: Matt Roper
>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
> drivers/gpu/drm/i915/gt/intel_lrc.c | 13 +
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index a00ff51c681d..0d5260d126d8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -164,6 +164,8 @@
> #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20d4)
> #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
> #define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
> +#define GEN12_CS_DEBUG_MODE2 _MMIO(0x20d8)
> +#define INSTRUCTION_STATE_CACHE_INVALIDATE REG_BIT(6)
>
> #define GEN7_FF_SLICE_CS_CHICKEN1_MMIO(0x20e0)
> #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index b99efa348ad1..56c916730e9b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1333,6 +1333,15 @@ dg2_emit_draw_watermark_setting(u32 *cs)
> return cs;
> }
>
> +static u32 *
> +gen12_invalidate_state_cache(u32 *cs)
> +{
> + *cs++ = MI_LOAD_REGISTER_IMM(1);
> + *cs++ = i915_mmio_reg_offset(GEN12_CS_DEBUG_MODE2);
> + *cs++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);
> + return cs;
> +}
> +
> static u32 *
> gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
> {
> @@ -1346,6 +1355,10 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context
> *ce, u32 *cs)
>
> cs = gen12_emit_aux_table_inv(ce->engine, cs);
>
> + /* Wa_18022495364 */
> + if (IS_GFX_GT_IP_RANGE(ce->engine->gt, IP_VER(12, 0), IP_VER(12, 10)))
> + cs = gen12_invalidate_state_cache(cs);
> +
> /* Wa_16014892111 */
> if (IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0)
> ||
> IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)
> ||
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
[Intel-gfx] [PATCH v10 3/3] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123
Set copy engine arbitration into round robin mode for part of Wa_16018031267 / Wa_16018063123 mitigation. Signed-off-by: Nirmoy Das Signed-off-by: Jonathan Cavitt --- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h index 2e06bea73297a..823c6c40213f5 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h @@ -124,6 +124,9 @@ #define RING_INDIRECT_CTX(base)_MMIO((base) + 0x1c4) /* gen8+ */ #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ #define ECOSKPD(base) _MMIO((base) + 0x1d0) +#define XEHP_BLITTER_SCHEDULING_MODE_MASKREG_GENMASK(12, 11) +#define XEHP_BLITTER_ROUND_ROBIN_MODE\ + REG_FIELD_PREP(XEHP_BLITTER_SCHEDULING_MODE_MASK, 1) #define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4) #define ECO_GATING_CX_ONLY REG_BIT(3) #define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 660d4f358eab7..b8f3b991e4202 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2781,6 +2781,11 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) RING_SEMA_WAIT_POLL(engine->mmio_base), 1); } + /* Wa_16018031267, Wa_16018063123 */ + if (NEEDS_FASTCOLOR_BLT_WABB(engine)) + wa_masked_field_set(wal, ECOSKPD(engine->mmio_base), + XEHP_BLITTER_SCHEDULING_MODE_MASK, + XEHP_BLITTER_ROUND_ROBIN_MODE); } static void -- 2.25.1
[Intel-gfx] [PATCH v10 0/3] Apply Wa_16018031267 / Wa_16018063123
Apply Wa_16018031267 / Wa_16018063123. This necessitates submitting a fastcolor blit as WABB and setting the copy engine arbitration to round-robin mode. v2: - Rename old platform check in second patch to match declaration in first patch. - Refactor second patch name to match first patch. v3: - Move NEEDS_FASTCOLOR_BLT_WABB to intel_gt.h. - Refactor NEEDS_FASTCOLOR_BLT_WABB to make it more streamlined to use. - Stop dividing PAGE_SIZE by sizeof(u32) when computing ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx. - Reduce comment complexity. - Fix several checkpatch warnings. v4: - Actually stop dividing PAGE_SIZE by sizeof(u32) when computing ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx. v5: - Stop dividing PAGE_SIZE by sizeof(u32) in check_ring_start during lrc live selftest. v6: - Append MI_BATCH_BUFFER_END to end of all PER_CTX_BB command streams. - No longer skip on empty, as command stream will never be empty (always contains at least MI_BATCH_BUFFER_END). - No longer append MI_NOOP until cachline aligned (was a fragment from INDIRECT_CTX setup). v7: - Use 0x6b instead of 0 for color to maintain functionality. v8: - Revert v7. - Add some reserved kernel space per vm to run the workaround on. v9: - Hide reserved kernel space per vm from userspace. v10: - Revert v7 properly. - Test on updated IGT. Test-with: 20230914172332.2322524-2-jonathan.cav...@intel.com Signed-off-by: Nirmoy Das Signed-off-by: Jonathan Cavitt CC: Joonas Lahtinen CC: Rodrigo Vivi CC: Tomasz Mistat CC: Gregory F Germano CC: Matt Roper CC: James Ausmus CC: Chris Wilson CC: Andi Shyti Jonathan Cavitt (3): drm/i915: Reserve some kernel space per vm drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123 drivers/gpu/drm/i915/gt/gen8_ppgtt.c| 7 ++ drivers/gpu/drm/i915/gt/intel_engine_regs.h | 6 ++ drivers/gpu/drm/i915/gt/intel_gt.h | 4 + drivers/gpu/drm/i915/gt/intel_gt_types.h| 2 + drivers/gpu/drm/i915/gt/intel_gtt.h | 1 + drivers/gpu/drm/i915/gt/intel_lrc.c | 100 +++- drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + drivers/gpu/drm/i915/gt/selftest_lrc.c | 65 + 8 files changed, 169 insertions(+), 21 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH v10 1/3] drm/i915: Reserve some kernel space per vm
Reserve a page in each vm for kernel space to use for things
such as workarounds.
Signed-off-by: Jonathan Cavitt
Suggested-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 7 +++
drivers/gpu/drm/i915/gt/intel_gtt.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 9895e18df0435..1a85858c55639 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -230,6 +230,7 @@ static void gen8_ppgtt_cleanup(struct i915_address_space
*vm)
gen8_pd_top_count(vm), vm->top);
free_scratch(vm);
+ drm_mm_remove_node(>rsvd);
}
static u64 __gen8_ppgtt_clear(struct i915_address_space * const vm,
@@ -1011,6 +1012,12 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
ppgtt->vm.foreach = gen8_ppgtt_foreach;
ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
+ ppgtt->vm.rsvd.start = ppgtt->vm.total - SZ_4K;
+ ppgtt->vm.rsvd.size = SZ_4K;
+ ppgtt->vm.rsvd.color = I915_COLOR_UNEVICTABLE;
+ GEM_BUG_ON(drm_mm_reserve_node(>vm.mm, >vm.rsvd));
+ ppgtt->vm.total -= SZ_4K;
+
err = gen8_init_scratch(>vm);
if (err)
goto err_put;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 346ec8ec2edda..ab38a158fc715 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -246,6 +246,7 @@ struct i915_address_space {
struct work_struct release_work;
struct drm_mm mm;
+ struct drm_mm_node rsvd;
struct intel_gt *gt;
struct drm_i915_private *i915;
struct device *dma;
--
2.25.1
[Intel-gfx] [PATCH v10 2/3] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
Apply WABB blit for Wa_16018031267 / Wa_16018063123.
Additionally, update the lrc selftest to exercise the new
WABB changes.
Co-developed-by: Nirmoy Das
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +
drivers/gpu/drm/i915/gt/intel_gt.h | 4 +
drivers/gpu/drm/i915/gt/intel_gt_types.h| 2 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 100 +++-
drivers/gpu/drm/i915/gt/selftest_lrc.c | 65 +
5 files changed, 153 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index 6b9d9f8376692..2e06bea73297a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -118,6 +118,9 @@
#define CCID_EXTENDED_STATE_RESTORE BIT(2)
#define CCID_EXTENDED_STATE_SAVE BIT(3)
#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+
*/
+#define PER_CTX_BB_FORCE BIT(2)
+#define PER_CTX_BB_VALID BIT(0)
+
#define RING_INDIRECT_CTX(base)_MMIO((base) + 0x1c4)
/* gen8+ */
#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+
*/
#define ECOSKPD(base) _MMIO((base) + 0x1d0)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 239848bcb2a42..40cc0005dd735 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -83,6 +83,10 @@ struct drm_printer;
##__VA_ARGS__); \
} while (0)
+#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \
+ IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 55), IP_VER(12, 71)) && \
+ engine->class == COPY_ENGINE_CLASS)
+
static inline bool gt_is_root(struct intel_gt *gt)
{
return !gt->info.id;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index def7dd0eb6f19..4917633f299dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -307,6 +307,8 @@ enum intel_gt_scratch_field {
/* 8 bytes */
INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
+
+ INTEL_GT_SCRATCH_FIELD_DUMMY_BLIT = 384,
};
#define intel_gt_support_legacy_fencing(gt) ((gt)->ggtt->num_fences > 0)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b99efa348ad1e..ffe46c0ff1ff3 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -828,6 +828,18 @@ lrc_ring_indirect_offset_default(const struct
intel_engine_cs *engine)
return 0;
}
+static void
+lrc_setup_bb_per_ctx(u32 *regs,
+const struct intel_engine_cs *engine,
+u32 ctx_bb_ggtt_addr)
+{
+ GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1);
+ regs[lrc_ring_wa_bb_per_ctx(engine) + 1] =
+ ctx_bb_ggtt_addr |
+ PER_CTX_BB_FORCE |
+ PER_CTX_BB_VALID;
+}
+
static void
lrc_setup_indirect_ctx(u32 *regs,
const struct intel_engine_cs *engine,
@@ -997,7 +1009,13 @@ static u32 context_wa_bb_offset(const struct
intel_context *ce)
return PAGE_SIZE * ce->wa_bb_page;
}
-static u32 *context_indirect_bb(const struct intel_context *ce)
+/*
+ * per_ctx below determines which WABB section is used.
+ * When true, the function returns the location of the
+ * PER_CTX_BB. When false, the function returns the
+ * location of the INDIRECT_CTX.
+ */
+static u32 *context_wabb(const struct intel_context *ce, bool per_ctx)
{
void *ptr;
@@ -1006,6 +1024,7 @@ static u32 *context_indirect_bb(const struct
intel_context *ce)
ptr = ce->lrc_reg_state;
ptr -= LRC_STATE_OFFSET; /* back to start of context image */
ptr += context_wa_bb_offset(ce);
+ ptr += per_ctx ? PAGE_SIZE : 0;
return ptr;
}
@@ -1082,7 +1101,8 @@ __lrc_alloc_state(struct intel_context *ce, struct
intel_engine_cs *engine)
if (GRAPHICS_VER(engine->i915) >= 12) {
ce->wa_bb_page = context_size / PAGE_SIZE;
- context_size += PAGE_SIZE;
+ /* INDIRECT_CTX and PER_CTX_BB need separate pages. */
+ context_size += PAGE_SIZE * 2;
}
if (intel_context_is_parent(ce) && intel_engine_uses_guc(engine)) {
@@ -1371,12 +1391,85 @@ gen12_emit_indirect_ctx_xcs(const struct intel_context
*ce, u32 *cs)
return gen12_emit_aux_table_inv(ce->engine, cs);
}
+static u32 *xehp_emit_fastcolor_blt_wabb(const struct intel_context *ce, u32
*cs)
+{
+ struct intel_gt *gt = ce->engine->gt;
+ int mocs = gt->mocs.uc_index << 1;
+
+ /**
+* Wa_16018031267 / Wa_16018063123 requires that SW forces the
+* main copy engine arbitration into round robin mode. We
+*
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: Fixup h/vsync_end instead of h/vtotal
== Series Details ==
Series: drm/edid: Fixup h/vsync_end instead of h/vtotal
URL : https://patchwork.freedesktop.org/series/123685/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13633 -> Patchwork_123685v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/index.html
Participating hosts (40 -> 37)
--
Missing(3): bat-dg2-9 bat-atsm-1 fi-snb-2520m
Known issues
Here are the changes found in Patchwork_123685v1 that come from known issues:
### CI changes ###
Possible fixes
* boot:
- fi-hsw-4770:[FAIL][1] ([i915#8293]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-hsw-4770/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/fi-hsw-4770/boot.html
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gt_mocs:
- bat-rpls-1: [PASS][3] -> [INCOMPLETE][4] ([i915#9253])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-rpls-1/igt@i915_selftest@live@gt_mocs.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/bat-rpls-1/igt@i915_selftest@live@gt_mocs.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271]) +13 other tests
skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#1845]) +3 other tests skip
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [PASS][7] -> [ABORT][8] ([i915#8668])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-vga-1:
- fi-hsw-4770:NOTRUN -> [DMESG-WARN][9] ([i915#8841]) +6 other
tests dmesg-warn
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-...@pipe-c-vga-1.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1072]) +3
other tests skip
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [ABORT][11] ([i915#7911] / [i915#7913]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@kms_chamelium_edid@hdmi-edid-read:
- {bat-dg2-13}: [DMESG-WARN][13] ([i915#7952]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-13/igt@kms_chamelium_e...@hdmi-edid-read.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/bat-dg2-13/igt@kms_chamelium_e...@hdmi-edid-read.html
* igt@kms_chamelium_frames@dp-crc-fast:
- {bat-dg2-13}: [DMESG-WARN][15] ([Intel XE#485]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/bat-dg2-13/igt@kms_chamelium_fra...@dp-crc-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123685v1/bat-dg2-13/igt@kms_chamelium_fra...@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#485]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/485
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7952]: https://gitlab.freedesktop.org/drm/intel/issues/7952
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#9253]: https://gitlab.freedesktop.org/drm/intel/issues/9253
Build changes
-
* Linux: CI_DRM_13633 -> Patchwork_123685v1
CI-20190529: 20190529
CI_DRM_13633:
Re: [Intel-gfx] [PATCH v6] drm/i915: Add Wa_18022495364
> -Original Message-
> From: Atwood, Matthew S
> Sent: Friday, September 15, 2023 1:15 AM
> To: Bhadane, Dnyaneshwar
> Cc: intel-gfx@lists.freedesktop.org; De Marchi, Lucas
> ; Garg, Nemesa ; Roper,
> Matthew D ; Kandpal, Suraj
>
> Subject: Re: [PATCH v6] drm/i915: Add Wa_18022495364
>
> On Fri, Sep 15, 2023 at 01:10:32AM +0530, Dnyaneshwar Bhadane wrote:
> > Invalidate instruction and State cache bit using INDIRECT_CTX on every
> > gpu context switch for gen12.
> > The goal of this workaround is to actually perform an explicit
> > invalidation of that cache (by re-writing the register) during every
> > GPU context switch, which is accomplished via a "workaround batchbuffer"
> > that's attached to the context via INDIRECT_CTX. (Matt Ropper)
> > BSpec: 11354
> >
> > Please refer [1] for more reviews and comment on the same patch
> >
> > [1] https://patchwork.freedesktop.org/patch/556154/
> >
> > v2:
> > - Remove extra parentheses from the condition (Lucas)
> > - Align spacing and new line (Lucas)
> >
> > v3:
> > - Fix commit message.
> >
> > v4:
> > - Only GEN12 changes are kept (Matt Ropper)
> Not clear to me what this means,
Matt has corrected me by saying that this workaround should only be applied to
Gen12 platforms.
Initially, the patch was combined for the Gen12 and DG+ conditions, which was
an incorrect understanding.
Dnyaneshwar
> > also its Matt Roper
> > - Fix the commit message for r-b (Matt Ropper)
> > - Rename the register bit in define
> >
> > v5:
> > - Move out this workaround from golden context init (Matt Roper)
> > - Use INDIRECT_CTX to set bit on each GPU context switch (Matt Roper)
> >
> > v6:
> > - Change IP Version base condition for Gen12 (Matt Ropper)
> Matt Roper
> > - Made imperative form of commit version messages (Suraj)
> > - s/Added/Add in patch header (Suraj)
> >
> > Cc: Lucas De Marchi
> > Cc: Matt Roper
> > Cc: Suraj Kandpal
> > Signed-off-by: Dnyaneshwar Bhadane
> >
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 13 +
> > 2 files changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index a00ff51c681d..0d5260d126d8 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -164,6 +164,8 @@
> > #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20d4)
> > #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
> > #define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
> > +#define GEN12_CS_DEBUG_MODE2 _MMIO(0x20d8)
> > +#define INSTRUCTION_STATE_CACHE_INVALIDATE REG_BIT(6)
> >
> > #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
> > #define GEN9_FFSC_PERCTX_PREEMPT_CTRL(1 << 14)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index b99efa348ad1..56c916730e9b 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -1333,6 +1333,15 @@ dg2_emit_draw_watermark_setting(u32 *cs)
> > return cs;
> > }
> >
> > +static u32 *
> > +gen12_invalidate_state_cache(u32 *cs) {
> > + *cs++ = MI_LOAD_REGISTER_IMM(1);
> > + *cs++ = i915_mmio_reg_offset(GEN12_CS_DEBUG_MODE2);
> > + *cs++ =
> _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);
> > + return cs;
> > +}
> > +
> > static u32 *
> > gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
> > { @@ -1346,6 +1355,10 @@ gen12_emit_indirect_ctx_rcs(const struct
> > intel_context *ce, u32 *cs)
> >
> > cs = gen12_emit_aux_table_inv(ce->engine, cs);
> >
> > + /* Wa_18022495364 */
> > + if (IS_GFX_GT_IP_RANGE(ce->engine->gt, IP_VER(12, 0), IP_VER(12, 10)))
> > + cs = gen12_invalidate_state_cache(cs);
> > +
> > /* Wa_16014892111 */
> > if (IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0,
> STEP_B0) ||
> > IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0,
> > STEP_B0) ||
> > --
> > 2.34.1
> >
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/edid: Fixup h/vsync_end instead of h/vtotal
== Series Details == Series: drm/edid: Fixup h/vsync_end instead of h/vtotal URL : https://patchwork.freedesktop.org/series/123685/ State : warning == Summary == Error: dim checkpatch failed 473edd7231fd drm/edid: Fixup h/vsync_end instead of h/vtotal -:20: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?) #20: https://bugs.launchpad.net/ubuntu/hardy/+source/xserver-xorg-video-intel/+bug/297245 total: 0 errors, 1 warnings, 0 checks, 14 lines checked
Re: [Intel-gfx] [PATCH v6] drm/i915: Add Wa_18022495364
On Fri, Sep 15, 2023 at 01:10:32AM +0530, Dnyaneshwar Bhadane wrote:
> Invalidate instruction and State cache bit using INDIRECT_CTX on
> every gpu context switch for gen12.
> The goal of this workaround is to actually perform an explicit
> invalidation of that cache (by re-writing the register) during every GPU
> context switch, which is accomplished via a "workaround batchbuffer"
> that's attached to the context via INDIRECT_CTX. (Matt Ropper)
> BSpec: 11354
>
> Please refer [1] for more reviews and comment on the same patch
>
> [1] https://patchwork.freedesktop.org/patch/556154/
>
> v2:
> - Remove extra parentheses from the condition (Lucas)
> - Align spacing and new line (Lucas)
>
> v3:
> - Fix commit message.
>
> v4:
> - Only GEN12 changes are kept (Matt Ropper)
Not clear to me what this means, also its Matt Roper
> - Fix the commit message for r-b (Matt Ropper)
> - Rename the register bit in define
>
> v5:
> - Move out this workaround from golden context init (Matt Roper)
> - Use INDIRECT_CTX to set bit on each GPU context switch (Matt Roper)
>
> v6:
> - Change IP Version base condition for Gen12 (Matt Ropper)
Matt Roper
> - Made imperative form of commit version messages (Suraj)
> - s/Added/Add in patch header (Suraj)
>
> Cc: Lucas De Marchi
> Cc: Matt Roper
> Cc: Suraj Kandpal
> Signed-off-by: Dnyaneshwar Bhadane
>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
> drivers/gpu/drm/i915/gt/intel_lrc.c | 13 +
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index a00ff51c681d..0d5260d126d8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -164,6 +164,8 @@
> #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20d4)
> #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
> #define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
> +#define GEN12_CS_DEBUG_MODE2 _MMIO(0x20d8)
> +#define INSTRUCTION_STATE_CACHE_INVALIDATE REG_BIT(6)
>
> #define GEN7_FF_SLICE_CS_CHICKEN1_MMIO(0x20e0)
> #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index b99efa348ad1..56c916730e9b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1333,6 +1333,15 @@ dg2_emit_draw_watermark_setting(u32 *cs)
> return cs;
> }
>
> +static u32 *
> +gen12_invalidate_state_cache(u32 *cs)
> +{
> + *cs++ = MI_LOAD_REGISTER_IMM(1);
> + *cs++ = i915_mmio_reg_offset(GEN12_CS_DEBUG_MODE2);
> + *cs++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);
> + return cs;
> +}
> +
> static u32 *
> gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
> {
> @@ -1346,6 +1355,10 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context
> *ce, u32 *cs)
>
> cs = gen12_emit_aux_table_inv(ce->engine, cs);
>
> + /* Wa_18022495364 */
> + if (IS_GFX_GT_IP_RANGE(ce->engine->gt, IP_VER(12, 0), IP_VER(12, 10)))
> + cs = gen12_invalidate_state_cache(cs);
> +
> /* Wa_16014892111 */
> if (IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0)
> ||
> IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)
> ||
> --
> 2.34.1
>
[Intel-gfx] [PATCH v6] drm/i915: Add Wa_18022495364
Invalidate instruction and State cache bit using INDIRECT_CTX on
every gpu context switch for gen12.
The goal of this workaround is to actually perform an explicit
invalidation of that cache (by re-writing the register) during every GPU
context switch, which is accomplished via a "workaround batchbuffer"
that's attached to the context via INDIRECT_CTX. (Matt Ropper)
BSpec: 11354
Please refer [1] for more reviews and comment on the same patch
[1] https://patchwork.freedesktop.org/patch/556154/
v2:
- Remove extra parentheses from the condition (Lucas)
- Align spacing and new line (Lucas)
v3:
- Fix commit message.
v4:
- Only GEN12 changes are kept (Matt Ropper)
- Fix the commit message for r-b (Matt Ropper)
- Rename the register bit in define
v5:
- Move out this workaround from golden context init (Matt Roper)
- Use INDIRECT_CTX to set bit on each GPU context switch (Matt Roper)
v6:
- Change IP Version base condition for Gen12 (Matt Ropper)
- Made imperative form of commit version messages (Suraj)
- s/Added/Add in patch header (Suraj)
Cc: Lucas De Marchi
Cc: Matt Roper
Cc: Suraj Kandpal
Signed-off-by: Dnyaneshwar Bhadane
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 13 +
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index a00ff51c681d..0d5260d126d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -164,6 +164,8 @@
#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20d4)
#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
+#define GEN12_CS_DEBUG_MODE2 _MMIO(0x20d8)
+#define INSTRUCTION_STATE_CACHE_INVALIDATE REG_BIT(6)
#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
#define GEN9_FFSC_PERCTX_PREEMPT_CTRL(1 << 14)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b99efa348ad1..56c916730e9b 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1333,6 +1333,15 @@ dg2_emit_draw_watermark_setting(u32 *cs)
return cs;
}
+static u32 *
+gen12_invalidate_state_cache(u32 *cs)
+{
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = i915_mmio_reg_offset(GEN12_CS_DEBUG_MODE2);
+ *cs++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);
+ return cs;
+}
+
static u32 *
gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
{
@@ -1346,6 +1355,10 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context
*ce, u32 *cs)
cs = gen12_emit_aux_table_inv(ce->engine, cs);
+ /* Wa_18022495364 */
+ if (IS_GFX_GT_IP_RANGE(ce->engine->gt, IP_VER(12, 0), IP_VER(12, 10)))
+ cs = gen12_invalidate_state_cache(cs);
+
/* Wa_16014892111 */
if (IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0)
||
IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)
||
--
2.34.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST (rev2)
== Series Details == Series: drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST (rev2) URL : https://patchwork.freedesktop.org/series/123157/ State : success == Summary == CI Bug Log - changes from CI_DRM_13633 -> Patchwork_123157v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/index.html Participating hosts (40 -> 39) -- Additional (1): bat-dg2-8 Missing(2): bat-atsm-1 fi-snb-2520m Known issues Here are the changes found in Patchwork_123157v2 that come from known issues: ### CI changes ### Possible fixes * boot: - fi-hsw-4770:[FAIL][1] ([i915#8293]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-hsw-4770/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/fi-hsw-4770/boot.html ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/fi-hsw-4770/igt@debugfs_t...@basic-hwmon.html * igt@gem_exec_suspend@basic-s3@smem: - bat-dg2-8: NOTRUN -> [INCOMPLETE][4] ([i915#9275]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/bat-dg2-8/igt@gem_exec_suspend@basic...@smem.html * igt@gem_mmap@basic: - bat-dg2-8: NOTRUN -> [SKIP][5] ([i915#4083]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/bat-dg2-8/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-dg2-8: NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/bat-dg2-8/igt@gem_mmap_...@basic.html * igt@gem_tiled_pread_basic: - bat-dg2-8: NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/bat-dg2-8/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg2-8: NOTRUN -> [SKIP][8] ([i915#6621]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/bat-dg2-8/igt@i915_pm_...@basic-api.html * igt@i915_suspend@basic-s3-without-i915: - bat-dg2-8: NOTRUN -> [SKIP][9] ([i915#6645]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/bat-dg2-8/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-dg2-8: NOTRUN -> [SKIP][10] ([i915#5190]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/bat-dg2-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-8: NOTRUN -> [SKIP][11] ([i915#4215] / [i915#5190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/bat-dg2-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_addfb_basic@framebuffer-vs-set-tiling: - bat-dg2-8: NOTRUN -> [SKIP][12] ([i915#4212]) +7 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/bat-dg2-8/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-dg2-8: NOTRUN -> [SKIP][13] ([i915#4103] / [i915#4213]) +1 other test skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/bat-dg2-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-8: NOTRUN -> [SKIP][14] ([fdo#109285]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/bat-dg2-8/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-8: NOTRUN -> [SKIP][15] ([i915#5274]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/bat-dg2-8/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_hdmi_inject@inject-audio: - fi-kbl-guc: [PASS][16] -> [FAIL][17] ([IGT#3] / [i915#6121]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13633/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html * igt@kms_psr@cursor_plane_move: - bat-dg2-8: NOTRUN -> [SKIP][18] ([i915#1072]) +3 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/bat-dg2-8/igt@kms_psr@cursor_plane_move.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg2-8: NOTRUN -> [SKIP][19] ([i915#3555]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123157v2/bat-dg2-8/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - bat-dg2-8: NOTRUN -> [SKIP][20] ([i915#3708]) [20]:
[Intel-gfx] [PATCH v3 25/25] drm/i915/dp_mst: Check BW limitations only after all streams are computed
After the previous patch the BW limits on the whole MST topology will be
checked after computing the state for all the streams in the topology.
Accordingly remove the check during the stream's encoder compute config
step, to prevent failing an atomic commit due to a BW limit, if this can
be resolved only by reducing the BW of other streams on the same MST
link.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index bcfd5f19d994f..64867289174d9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -121,15 +121,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct
intel_encoder *encoder,
if (slots == -EDEADLK)
return slots;
- if (slots >= 0) {
- ret = drm_dp_mst_atomic_check(state);
- /*
-* If we got slots >= 0 and we can fit those based on
check
-* then we can exit the loop. Otherwise keep trying.
-*/
- if (!ret)
- break;
- }
+ if (slots >= 0)
+ break;
}
/* We failed to find a proper bpp/timeslots, return error */
--
2.37.2
[Intel-gfx] [PATCH v3 24/25] drm/i915/dp_mst: Improve BW sharing between MST streams
At the moment modesetting a stream CRTC will fail if the stream's BW
along with the current BW of all the other streams on the same MST link
is above the total BW of the MST link. Make the BW sharing more dynamic
by trying to reduce the link bpp of one or more streams on the MST link
in this case.
When selecting a stream to reduce the BW for, take into account which
link segment in the MST topology ran out of BW and which streams go
through this link segment. For instance with A,B,C streams in the same
MST topology A and B may share the BW of a link segment downstream of a
branch device, stream C not downstream of the branch device, hence not
affecting this BW. If this link segment's BW runs out one or both of
stream A/B's BW will be reduced until their total BW is within limits.
While reducing the link bpp for a given stream DSC may need to be
enabled for it, which requires FEC on the whole MST link. Check for this
condition and recompute the state for all streams taking the FEC
overhead into account (on 8b/10b links).
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
drivers/gpu/drm/i915/display/intel_dp.c | 13 +-
drivers/gpu/drm/i915/display/intel_dp.h | 2 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 129 +++
drivers/gpu/drm/i915/display/intel_dp_mst.h | 3 +
drivers/gpu/drm/i915/display/intel_link_bw.c | 15 ++-
drivers/gpu/drm/i915/display/intel_link_bw.h | 1 +
7 files changed, 159 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 31297a333f50e..e2f5f66c132b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4629,6 +4629,7 @@ intel_modeset_pipe_config(struct intel_atomic_state
*state,
if (ret)
return ret;
+ crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);
crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {
@@ -6408,10 +6409,6 @@ int intel_atomic_check(struct drm_device *dev,
goto fail;
}
- ret = drm_dp_mst_atomic_check(>base);
- if (ret)
- goto fail;
-
ret = intel_atomic_check_planes(state);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index ce8eafa4ece06..f18cde380e0cb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1369,8 +1369,8 @@ static bool intel_dp_source_supports_fec(struct intel_dp
*intel_dp,
return false;
}
-static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
- const struct intel_crtc_state *pipe_config)
+bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config)
{
return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
drm_dp_sink_supports_fec(intel_dp->fec_capable);
@@ -2111,8 +2111,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
_config->hw.adjusted_mode;
int ret;
- pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
- intel_dp_supports_fec(intel_dp, pipe_config);
+ pipe_config->fec_enable = pipe_config->fec_enable ||
+ (!intel_dp_is_edp(intel_dp) &&
+intel_dp_supports_fec(intel_dp, pipe_config));
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
@@ -2308,6 +2309,10 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
bool dsc_needed;
int ret = 0;
+ if (pipe_config->fec_enable &&
+ !intel_dp_supports_fec(intel_dp, pipe_config))
+ return -EINVAL;
+
if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
adjusted_mode->crtc_clock))
pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1,
crtc->pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 2cf3681bac64a..612105a303419 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -135,6 +135,8 @@ static inline unsigned int intel_dp_unused_lane_mask(int
lane_count)
return ~((1 << lane_count) - 1) & 0xf;
}
+bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config);
u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32
pipe_bpp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index f24f656d6d02a..bcfd5f19d994f 100644
---
[Intel-gfx] [PATCH v3 21/25] drm/i915/dp_mst: Enable DSC decompression if any stream needs this
Atm DSC decompression is enabled in the sink only if the first stream is compressed. This left compressed streams blank if the first stream was uncompressed. Enable decompression whenever FEC is enabled, which will be true for all streams if any stream is compressed. Enabling FEC correctly in all streams will be only fixed by an upcoming patch. Reviewed-by: Stanislav Lisovskiy Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index e942eb95d688f..ce8eafa4ece06 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2917,7 +2917,13 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, struct drm_i915_private *i915 = dp_to_i915(intel_dp); int ret; - if (!crtc_state->dsc.compression_enable) + /* +* In case of MST any stream can be compressed not just the first. If +* any stream is compressed FEC will be enabled in all streams, so toggle +* decompression whenever FEC is enabled. +*/ + if (!crtc_state->dsc.compression_enable && + !crtc_state->fec_enable) return; ret = drm_dp_dpcd_writeb(_dp->aux, DP_DSC_ENABLE, -- 2.37.2
[Intel-gfx] [PATCH v3 22/25] drm/i915/dp_mst: Add missing DSC compression disabling
Add the missing DSC compression disabling step for MST streams, similarly to how this is done for SST outputs. Reviewed-by: Stanislav Lisovskiy Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index a38a0e6da01bf..b2ac29a157fbd 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -646,6 +646,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, intel_ddi_disable_transcoder_func(old_crtc_state); + intel_dsc_disable(old_crtc_state); + if (DISPLAY_VER(dev_priv) >= 9) skl_scaler_disable(old_crtc_state); else -- 2.37.2
[Intel-gfx] [PATCH v3 23/25] drm/i915/dp_mst: Allow DSC only for sink ports of the first branch device
Atm the driver supports DSC on MST links only by enabling it globally in
the first branch device UFP's physical DPCD (vs. enabling it per-stream
in the virtual DPCD right upstream the DPRX). This means the branch
device will decompress any compressed stream (which it recognizes via
MSA / SDP compression info), but it does this only for streams going to
an SST output port. Accordingly allow DSC only for streams going to an
SST output port of the first branch device.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 26 +
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index b2ac29a157fbd..f24f656d6d02a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -335,6 +335,27 @@ intel_dp_mst_compute_config_limits(struct intel_dp
*intel_dp,
limits);
}
+static bool intel_dp_mst_port_supports_dsc(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ struct drm_connector_state
*conn_state)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_connector *connector =
+ to_intel_connector(conn_state->connector);
+ struct intel_crtc *crtc =
+ to_intel_crtc(crtc_state->uapi.crtc);
+
+ if (connector->port->parent != intel_dp->mst_mgr.mst_primary) {
+ drm_dbg_kms(>drm,
+ "[CRTC:%d:%s] DSC only allowed on sink ports of the
first branch device\n",
+ crtc->base.base.id, crtc->base.name);
+
+ return false;
+ }
+
+ return true;
+}
+
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
@@ -378,6 +399,11 @@ static int intel_dp_mst_compute_config(struct
intel_encoder *encoder,
str_yes_no(ret),
str_yes_no(intel_dp->force_dsc_en));
+ if (!intel_dp_mst_port_supports_dsc(intel_dp,
+ pipe_config,
+ conn_state))
+ return -EINVAL;
+
if (!intel_dp_mst_compute_config_limits(intel_dp,
pipe_config,
true,
--
2.37.2
[Intel-gfx] [PATCH v3 18/25] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms
If an MST stream is modeset, its state must be checked along all the other streams on the same MST link, for instance to resolve a BW overallocation of a non-sink MST port or to make sure that the FEC is enabled/disabled the same way for all these streams. To prepare for that this patch adds all the stream CRTCs to the atomic state and marks them for modeset similarly to tgl+ platforms. (If the state computation doesn't change the state the CRTC is switched back to fastset mode.) Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index c1fea894d3774..832e8b0e87e84 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -491,9 +491,6 @@ intel_dp_mst_atomic_master_trans_check(struct intel_connector *connector, struct intel_connector *connector_iter; int ret = 0; - if (DISPLAY_VER(dev_priv) < 12) - return 0; - if (!intel_connector_needs_modeset(state, >base)) return 0; -- 2.37.2
[Intel-gfx] [PATCH v3 16/25] drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations
drm_dp_mst_atomic_check_mgr() should check for BW limitation starting from sink ports continuing towards the root port, so that drivers can use the @failing_port returned to resolve a BW overallocation in an ideal way. For instance from streams A,B,C in a topology A,B going through @failing_port and C not going through it, a BW overallocation of A,B due to a limit of the port must be resolved first before considering the limits of other ports closer to the root port. This way can avoid reducing the BW of stream C unnecessarily due to a BW limit closer to the root port. Based on the above swap the order of the BW check for the root port and the check for all the ports downstream of it (the latter going through the topology already in the sink->root port direction). Cc: Lyude Paul Cc: dri-de...@lists.freedesktop.org Reviewed-by: Lyude Paul Signed-off-by: Imre Deak --- drivers/gpu/drm/display/drm_dp_mst_topology.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index 3d93bc093c46c..f4b70ee3d715c 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -5479,9 +5479,13 @@ EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc); * - %-ENOSPC, if the new state is invalid, because of BW limitation * @failing_port is set to: * - The non-root port where a BW limit check failed + * with all the ports downstream of @failing_port passing + * the BW limit check. * The returned port pointer is valid until at least * one payload downstream of it exists. * - %NULL if the BW limit check failed at the root port + * with all the ports downstream of the root port passing + * the BW limit check. * - %-EINVAL, if the new state is invalid, because the root port has * too many payloads. */ @@ -5497,17 +5501,16 @@ int drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state, if (!mgr->mst_state) return 0; - ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state); - if (ret) - return ret; - mutex_lock(>lock); ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary, mst_state, failing_port); mutex_unlock(>lock); - return ret < 0 ? ret : 0; + if (ret < 0) + return ret; + + return drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state); } EXPORT_SYMBOL(drm_dp_mst_atomic_check_mgr); -- 2.37.2
[Intel-gfx] [PATCH v3 14/25] drm/dp_mst: Add helper to determine if an MST port is downstream of another port
Add drm_dp_mst_port_downstream_of_parent() required by the i915
driver in a follow-up patch to resolve a BW overallocation of MST
streams going through a given MST port.
Cc: Lyude Paul
Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Lyude Paul
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 52 +++
include/drm/display/drm_dp_mst_helper.h | 3 ++
2 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index db97aa76575c1..22a901493d24c 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5136,6 +5136,58 @@ static bool drm_dp_mst_port_downstream_of_branch(struct
drm_dp_mst_port *port,
return false;
}
+static bool
+drm_dp_mst_port_downstream_of_parent_locked(struct drm_dp_mst_topology_mgr
*mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent)
+{
+ if (!mgr->mst_primary)
+ return false;
+
+ port = drm_dp_mst_topology_get_port_validated_locked(mgr->mst_primary,
+port);
+ if (!port)
+ return false;
+
+ if (!parent)
+ return true;
+
+ parent = drm_dp_mst_topology_get_port_validated_locked(mgr->mst_primary,
+ parent);
+ if (!parent)
+ return false;
+
+ if (!parent->mstb)
+ return false;
+
+ return drm_dp_mst_port_downstream_of_branch(port, parent->mstb);
+}
+
+/**
+ * drm_dp_mst_port_downstream_of_parent - check if a port is downstream of a
parent port
+ * @mgr: MST topology manager
+ * @port: the port being looked up
+ * @parent: the parent port
+ *
+ * The function returns %true if @port is downstream of @parent. If @parent is
+ * %NULL - denoting the root port - the function returns %true if @port is in
+ * @mgr's topology.
+ */
+bool
+drm_dp_mst_port_downstream_of_parent(struct drm_dp_mst_topology_mgr *mgr,
+struct drm_dp_mst_port *port,
+struct drm_dp_mst_port *parent)
+{
+ bool ret;
+
+ mutex_lock(>lock);
+ ret = drm_dp_mst_port_downstream_of_parent_locked(mgr, port, parent);
+ mutex_unlock(>lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(drm_dp_mst_port_downstream_of_parent);
+
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
struct drm_dp_mst_topology_state *state);
diff --git a/include/drm/display/drm_dp_mst_helper.h
b/include/drm/display/drm_dp_mst_helper.h
index 5de0c3d28794b..aecce52cae167 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -892,6 +892,9 @@ drm_atomic_get_new_mst_topology_state(struct
drm_atomic_state *state,
struct drm_dp_mst_atomic_payload *
drm_atomic_get_mst_payload_state(struct drm_dp_mst_topology_state *state,
struct drm_dp_mst_port *port);
+bool drm_dp_mst_port_downstream_of_parent(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent);
int __must_check
drm_dp_atomic_find_time_slots(struct drm_atomic_state *state,
struct drm_dp_mst_topology_mgr *mgr,
--
2.37.2
[Intel-gfx] [PATCH v3 19/25] drm/i915/dp_mst: Program the DSC PPS SDP for each stream
Atm the DSC PPS SDP is programmed only if the first stream is compressed
and then it's programmed only for the first stream. This left all other
compressed streams blank. Program the SDP for all streams.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c| 12 +++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 45db6349af94f..962c9c7c211ce 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2505,7 +2505,8 @@ static void mtl_ddi_pre_enable_dp(struct
intel_atomic_state *state,
/* 6.o Configure and enable FEC if needed */
intel_ddi_enable_fec(encoder, crtc_state);
- intel_dsc_dp_pps_write(encoder, crtc_state);
+ if (!is_mst)
+ intel_dsc_dp_pps_write(encoder, crtc_state);
}
static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -2643,7 +2644,8 @@ static void tgl_ddi_pre_enable_dp(struct
intel_atomic_state *state,
/* 7.l Configure and enable FEC if needed */
intel_ddi_enable_fec(encoder, crtc_state);
- intel_dsc_dp_pps_write(encoder, crtc_state);
+ if (!is_mst)
+ intel_dsc_dp_pps_write(encoder, crtc_state);
}
static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -2705,10 +2707,10 @@ static void hsw_ddi_pre_enable_dp(struct
intel_atomic_state *state,
intel_ddi_enable_fec(encoder, crtc_state);
- if (!is_mst)
+ if (!is_mst) {
intel_ddi_enable_transcoder_clock(encoder, crtc_state);
-
- intel_dsc_dp_pps_write(encoder, crtc_state);
+ intel_dsc_dp_pps_write(encoder, crtc_state);
+ }
}
static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 832e8b0e87e84..19548242fa0f2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -43,6 +43,7 @@
#include "intel_dpio_phy.h"
#include "intel_hdcp.h"
#include "intel_hotplug.h"
+#include "intel_vdsc.h"
#include "skl_scaler.h"
static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int
bpp,
@@ -775,6 +776,7 @@ static void intel_mst_pre_enable_dp(struct
intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
intel_ddi_enable_transcoder_clock(encoder, pipe_config);
+ intel_dsc_dp_pps_write(_port->base, pipe_config);
intel_ddi_set_dp_msa(pipe_config, conn_state);
}
--
2.37.2
[Intel-gfx] [PATCH v3 17/25] drm/i915/dp_mst: Fix PBN calculation with FEC overhead
On 8b/10b MST links the PBN value for DSC streams must be calculated accounting for the FEC overhead. The same applies to 8b/10b non-DSC streams if there is another DSC stream on the same link. Fix up the PBN calculation accordingly. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 01291bbb44693..c1fea894d3774 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -110,7 +110,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp << 4, - false); + (dsc || crtc_state->fec_enable) && + !intel_dp_is_uhbr(crtc_state)); slots = drm_dp_atomic_find_time_slots(state, _dp->mst_mgr, connector->port, -- 2.37.2
[Intel-gfx] [PATCH v3 20/25] drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled
Atm the DSC PPS SDP will stay enabled after enabling and disabling DSC. This leaves an output blank after switching off DSC on it. Make sure the SDP is disabled for an uncompressed output. v2: - Disable the SDP already during output disabling. (Ville) Cc: Ville Syrjälä Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 5 - drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 03010accc1c7f..e942eb95d688f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4027,7 +4027,10 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; u32 val = intel_de_read(dev_priv, reg) & ~dip_enable; - /* TODO: Add DSC case (DIP_ENABLE_PPS) */ + /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */ + if (!enable && HAS_DSC(dev_priv)) + val &= ~VDIP_ENABLE_PPS; + /* When PSR is enabled, this routine doesn't disable VSC DIP */ if (!crtc_state->has_psr) val &= ~VIDEO_DIP_ENABLE_VSC_HSW; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 19548242fa0f2..a38a0e6da01bf 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -662,9 +662,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, * BSpec 4287: disable DIP after the transcoder is disabled and before * the transcoder clock select is set to none. */ - if (last_mst_stream) - intel_dp_set_infoframes(_port->base, false, - old_crtc_state, NULL); + intel_dp_set_infoframes(_port->base, false, + old_crtc_state, NULL); /* * From TGL spec: "If multi-stream slave transcoder: Configure * Transcoder Clock Select to direct no clock to the transcoder" -- 2.37.2
[Intel-gfx] [PATCH v3 15/25] drm/dp_mst: Factor out a helper to check the atomic state of a topology manager
Factor out a helper to check the atomic state for one MST topology
manager, returning the MST port where the BW limit check has failed.
This will be used in a follow-up patch by the i915 driver to improve the
BW sharing between MST streams.
Cc: Lyude Paul
Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Lyude Paul
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 93 +++
include/drm/display/drm_dp_mst_helper.h | 4 +
2 files changed, 78 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 22a901493d24c..3d93bc093c46c 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5190,11 +5190,13 @@ EXPORT_SYMBOL(drm_dp_mst_port_downstream_of_parent);
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
- struct drm_dp_mst_topology_state *state);
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port);
static int
drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
- struct drm_dp_mst_topology_state *state)
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port)
{
struct drm_dp_mst_atomic_payload *payload;
struct drm_dp_mst_port *port;
@@ -5223,7 +5225,7 @@ drm_dp_mst_atomic_check_mstb_bw_limit(struct
drm_dp_mst_branch *mstb,
drm_dbg_atomic(mstb->mgr->dev, "[MSTB:%p] Checking bandwidth
limits\n", mstb);
list_for_each_entry(port, >ports, next) {
- ret = drm_dp_mst_atomic_check_port_bw_limit(port, state);
+ ret = drm_dp_mst_atomic_check_port_bw_limit(port, state,
failing_port);
if (ret < 0)
return ret;
@@ -5235,7 +5237,8 @@ drm_dp_mst_atomic_check_mstb_bw_limit(struct
drm_dp_mst_branch *mstb,
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
- struct drm_dp_mst_topology_state *state)
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port)
{
struct drm_dp_mst_atomic_payload *payload;
int pbn_used = 0;
@@ -5256,13 +5259,15 @@ drm_dp_mst_atomic_check_port_bw_limit(struct
drm_dp_mst_port *port,
drm_dbg_atomic(port->mgr->dev,
"[MSTB:%p] [MST PORT:%p] no BW available
for the port\n",
port->parent, port);
+ *failing_port = port;
return -EINVAL;
}
pbn_used = payload->pbn;
} else {
pbn_used = drm_dp_mst_atomic_check_mstb_bw_limit(port->mstb,
-state);
+state,
+failing_port);
if (pbn_used <= 0)
return pbn_used;
}
@@ -5271,6 +5276,7 @@ drm_dp_mst_atomic_check_port_bw_limit(struct
drm_dp_mst_port *port,
drm_dbg_atomic(port->mgr->dev,
"[MSTB:%p] [MST PORT:%p] required PBN of %d
exceeds port limit of %d\n",
port->parent, port, pbn_used, port->full_pbn);
+ *failing_port = port;
return -ENOSPC;
}
@@ -5448,20 +5454,79 @@ int drm_dp_mst_atomic_enable_dsc(struct
drm_atomic_state *state,
}
EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc);
+/**
+ * drm_dp_mst_atomic_check_mgr - Check the atomic state of an MST topology
manager
+ * @state: The global atomic state
+ * @mgr: Manager to check
+ * @mst_state: The MST atomic state for @mgr
+ * @failing_port: Returns the port with a BW limitation
+ *
+ * Checks the given MST manager's topology state for an atomic update to ensure
+ * that it's valid. This includes checking whether there's enough bandwidth to
+ * support the new timeslot allocations in the atomic update.
+ *
+ * Any atomic drivers supporting DP MST must make sure to call this or
+ * the drm_dp_mst_atomic_check() function after checking the rest of their
state
+ * in their _mode_config_funcs.atomic_check() callback.
+ *
+ * See also:
+ * drm_dp_mst_atomic_check()
+ * drm_dp_atomic_find_time_slots()
+ * drm_dp_atomic_release_time_slots()
+ *
+ * Returns:
+ * - 0 if the new state is valid
+ * - %-ENOSPC, if the new state is invalid, because of BW limitation
+ * @failing_port is set to:
+ * - The non-root port where a BW limit check
[Intel-gfx] [PATCH v3 12/25] drm/dp_mst: Fix fractional DSC bpp handling
From: Ville Syrjälä
The current code does '(bpp << 4) / 16' in the MST PBN
calculation, but that is just the same as 'bpp' so the
DSC codepath achieves absolutely nothing. Fix it up so that
the fractional part of the bpp value is actually used instead
of truncated away. 64*1006 has enough zero lsbs that we can
just shift that down in the dividend and thus still manage
to stick to a 32bit divisor.
And while touching this, let's just make the whole thing more
straightforward by making the passed in bpp value .4 binary
fixed point always, instead of having to pass in different
things based on whether DSC is enabled or not.
v2:
- Fix DSC kunit test cases.
Cc: Manasi Navare
Cc: Lyude Paul
Cc: Harry Wentland
Cc: David Francis
Cc: Mikita Lipski
Cc: Alex Deucher
Fixes: dc48529fb14e ("drm/dp_mst: Add PBN calculation for DSC modes")
Reviewed-by: Lyude Paul (v1)
Signed-off-by: Ville Syrjälä
[Imre: Fix kunit test cases]
Signed-off-by: Imre Deak
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
drivers/gpu/drm/display/drm_dp_mst_topology.c | 20 +--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 +--
.../gpu/drm/tests/drm_dp_mst_helper_test.c| 6 +++---
include/drm/display/drm_dp_mst_helper.h | 2 +-
7 files changed, 14 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 88ba8b66de1f7..1df65e3e674f6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6804,7 +6804,7 @@ static int dm_encoder_helper_atomic_check(struct
drm_encoder *encoder,
max_bpc);
bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
clock = adjusted_mode->clock;
- dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp,
false);
+ dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp
<< 4);
}
dm_new_connector_state->vcpi_slots =
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 57230661132bd..2afd1bc74978d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1636,7 +1636,7 @@ enum dc_status dm_dp_mst_is_port_support_mode(
} else {
/* check if mode could be supported within full_pbn */
bpp =
convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
- pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10,
bpp, false);
+ pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10,
bpp << 4);
if (pbn > aconnector->mst_output_port->full_pbn)
return DC_FAIL_BANDWIDTH_VALIDATE;
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index e04f87ff755ac..0264f673295a8 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -4719,13 +4719,12 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
/**
* drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
- * @clock: dot clock for the mode
- * @bpp: bpp for the mode.
- * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
+ * @clock: dot clock
+ * @bpp: bpp as .4 binary fixed point
*
* This uses the formula in the spec to calculate the PBN value for a mode.
*/
-int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
+int drm_dp_calc_pbn_mode(int clock, int bpp)
{
/*
* margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
@@ -4736,18 +4735,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
* peak_kbps *= (1006/1000)
* peak_kbps *= (64/54)
* peak_kbps *= 8convert to bytes
-*
-* If the bpp is in units of 1/16, further divide by 16. Put this
-* factor in the numerator rather than the denominator to avoid
-* integer overflow
*/
-
- if (dsc)
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 *
1006),
- 8 * 54 * 1000 * 1000);
-
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
- 8 * 54 * 1000 * 1000);
+ return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
+ 1000 * 8 * 54 * 1000);
}
EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index d38d0dd23fc39..dd04306ba9b32 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++
[Intel-gfx] [PATCH v3 13/25] drm/dp_mst: Add a way to calculate PBN values with FEC overhead
Add a way for drivers to calculate the MST PBN values with FEC overhead.
This is required by 8b/10b links both for DSC and non-DSC (the latter
needed if there are both DSC and non-DSC streams on the same MST link).
Also add a kunit test case for PBN values calculated with FEC overhead.
v2:
- Rebase on fractional bpp fix in the previous patch.
Cc: Lyude Paul
Cc: Harry Wentland
Cc: Wayne Lin
Cc: Alex Deucher
Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Lyude Paul (v1)
Signed-off-by: Imre Deak
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
drivers/gpu/drm/display/drm_dp_mst_topology.c | 19 ++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++--
drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
.../gpu/drm/tests/drm_dp_mst_helper_test.c| 15 ++-
include/drm/display/drm_dp_mst_helper.h | 2 +-
7 files changed, 35 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1df65e3e674f6..fb175ac279318 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6804,7 +6804,7 @@ static int dm_encoder_helper_atomic_check(struct
drm_encoder *encoder,
max_bpc);
bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
clock = adjusted_mode->clock;
- dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp
<< 4);
+ dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp
<< 4, false);
}
dm_new_connector_state->vcpi_slots =
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 2afd1bc74978d..46829361175dc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1636,7 +1636,7 @@ enum dc_status dm_dp_mst_is_port_support_mode(
} else {
/* check if mode could be supported within full_pbn */
bpp =
convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
- pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10,
bpp << 4);
+ pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10,
bpp << 4, false);
if (pbn > aconnector->mst_output_port->full_pbn)
return DC_FAIL_BANDWIDTH_VALIDATE;
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 0264f673295a8..db97aa76575c1 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -4721,22 +4721,31 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
* drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
* @clock: dot clock
* @bpp: bpp as .4 binary fixed point
+ * @fec: calculate PBN with FEC overhead
*
* This uses the formula in the spec to calculate the PBN value for a mode.
*/
-int drm_dp_calc_pbn_mode(int clock, int bpp)
+int drm_dp_calc_pbn_mode(int clock, int bpp, bool fec)
{
/*
-* margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
+* Overheads:
+* - SSC downspread and ref clock variation margin:
+* 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
+* - FEC symbol insertions:
+* 2.4% as per spec, factor is 1.024
+*
* The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
* common multiplier to render an integer PBN for all link rate/lane
* counts combinations
* calculate
-* peak_kbps *= (1006/1000)
+* peak_kbps *= (1006/1000) without FEC, or
+* peak_kbps *= (1030/1000) with FEC
* peak_kbps *= (64/54)
-* peak_kbps *= 8convert to bytes
+* peak_kbps /= 8convert to bytes
*/
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
+ u32 overhead = fec ? 1030 : 1006;
+
+ return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * overhead >> 4),
1000 * 8 * 54 * 1000);
}
EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index dd04306ba9b32..01291bbb44693 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -109,7 +109,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct
intel_encoder *encoder,
continue;
crtc_state->pbn =
drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
- bpp << 4);
+
[Intel-gfx] [PATCH v3 10/25] drm/i915/fdi: Improve FDI BW sharing between pipe B and C
At the moment modesetting pipe C on IVB will fail if pipe B uses 4 FDI
lanes. Make the BW sharing more dynamic by trying to reduce pipe B's
link bpp in this case, until pipe B uses only up to 2 FDI lanes.
For this instead of the encoder compute config retry loop - which
reduced link bpp only for the encoder's pipe - reduce the maximum link
bpp for pipe B/C as required after all CRTC states are computed and
recompute the CRTC states with the new bpp limit.
v2:
- Don't assume that a CRTC is already in the atomic state, while
reducing its link bpp.
- Add DocBook description to intel_fdi_atomic_check_link().
v3:
- Enable BW management for FDI links in a separate patch. (Ville)
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/g4x_hdmi.c | 6 +-
drivers/gpu/drm/i915/display/intel_crt.c | 7 ++
drivers/gpu/drm/i915/display/intel_display.c | 14 +---
drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 87 +++-
drivers/gpu/drm/i915/display/intel_fdi.h | 4 +
drivers/gpu/drm/i915/display/intel_link_bw.c | 7 +-
drivers/gpu/drm/i915/display/intel_lvds.c| 10 ++-
drivers/gpu/drm/i915/display/intel_sdvo.c| 10 ++-
9 files changed, 107 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c
b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 634b14116d9dd..8b5d26cd3b85e 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -19,6 +19,7 @@
#include "intel_fifo_underrun.h"
#include "intel_hdmi.h"
#include "intel_hotplug.h"
+#include "intel_link_bw.h"
#include "intel_sdvo.h"
#include "vlv_sideband.h"
@@ -133,8 +134,11 @@ static int g4x_hdmi_compute_config(struct intel_encoder
*encoder,
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- if (HAS_PCH_SPLIT(i915))
+ if (HAS_PCH_SPLIT(i915)) {
crtc_state->has_pch_encoder = true;
+ if (!intel_link_bw_compute_pipe_bpp(crtc_state))
+ return -EINVAL;
+ }
if (IS_G4X(i915))
crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state,
crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index f6df6c4fa72ef..7aa89d0fa3d6c 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -49,6 +49,7 @@
#include "intel_gmbus.h"
#include "intel_hotplug.h"
#include "intel_hotplug_irq.h"
+#include "intel_link_bw.h"
#include "intel_load_detect.h"
#include "intel_pch_display.h"
#include "intel_pch_refclk.h"
@@ -413,6 +414,9 @@ static int pch_crt_compute_config(struct intel_encoder
*encoder,
return -EINVAL;
pipe_config->has_pch_encoder = true;
+ if (!intel_link_bw_compute_pipe_bpp(pipe_config))
+ return -EINVAL;
+
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
return 0;
@@ -435,6 +439,9 @@ static int hsw_crt_compute_config(struct intel_encoder
*encoder,
return -EINVAL;
pipe_config->has_pch_encoder = true;
+ if (!intel_link_bw_compute_pipe_bpp(pipe_config))
+ return -EINVAL;
+
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
/* LPT FDI RX only supports 8bpc. */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 29816153fdd59..aad16dcceb788 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4607,7 +4607,6 @@ intel_modeset_pipe_config(struct intel_atomic_state
*state,
struct drm_connector_state *connector_state;
int pipe_src_w, pipe_src_h;
int base_bpp, ret, i;
- bool retry = true;
crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
@@ -4637,6 +4636,7 @@ intel_modeset_pipe_config(struct intel_atomic_state
*state,
"[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT
"\n",
crtc->base.base.id, crtc->base.name,
BPP_X16_ARGS(crtc_state->max_link_bpp_x16));
+ crtc_state->bw_constrained = true;
}
base_bpp = crtc_state->pipe_bpp;
@@ -4680,7 +4680,6 @@ intel_modeset_pipe_config(struct intel_atomic_state
*state,
crtc_state->output_types |= BIT(encoder->type);
}
-encoder_retry:
/* Ensure the port clock defaults are reset when retrying. */
crtc_state->port_clock = 0;
crtc_state->pixel_multiplier = 1;
@@ -4720,17 +4719,6 @@ intel_modeset_pipe_config(struct intel_atomic_state
*state,
ret = intel_crtc_compute_config(state, crtc);
if (ret == -EDEADLK)
return ret;
- if (ret == -EAGAIN) {
- if
[Intel-gfx] [PATCH v3 08/25] drm/i915: Factor out a helper to check/compute all the CRTC states
Factor out intel_atomic_check_config() to check and compute all the CRTC
states. This will be used by a follow up patch to recompute/check the
state until required by BW limitations between CRTCs.
Reviewed-by: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 78
1 file changed, 46 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 44abe583a672d..fe3b6844e063d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6195,6 +6195,51 @@ static int intel_bigjoiner_add_affected_crtcs(struct
intel_atomic_state *state)
return 0;
}
+static int intel_atomic_check_config(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc *crtc;
+ int ret;
+ int i;
+
+ ret = intel_bigjoiner_add_affected_crtcs(state);
+ if (ret)
+ return ret;
+
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ if (!intel_crtc_needs_modeset(new_crtc_state)) {
+ if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
+ copy_bigjoiner_crtc_state_nomodeset(state,
crtc);
+ else
+
intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
+ continue;
+ }
+
+ if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
+ drm_WARN_ON(>drm, new_crtc_state->uapi.enable);
+ continue;
+ }
+
+ ret = intel_crtc_prepare_cleared_state(state, crtc);
+ if (ret)
+ break;
+
+ if (!new_crtc_state->hw.enable)
+ continue;
+
+ ret = intel_modeset_pipe_config(state, crtc);
+ if (ret)
+ break;
+
+ ret = intel_atomic_check_bigjoiner(state, crtc);
+ if (ret)
+ break;
+ }
+
+ return ret;
+}
+
/**
* intel_atomic_check - validate state object
* @dev: drm device
@@ -6239,41 +6284,10 @@ int intel_atomic_check(struct drm_device *dev,
return ret;
}
- ret = intel_bigjoiner_add_affected_crtcs(state);
+ ret = intel_atomic_check_config(state);
if (ret)
goto fail;
- for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
- new_crtc_state, i) {
- if (!intel_crtc_needs_modeset(new_crtc_state)) {
- if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
- copy_bigjoiner_crtc_state_nomodeset(state,
crtc);
- else
-
intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
- continue;
- }
-
- if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
- drm_WARN_ON(_priv->drm,
new_crtc_state->uapi.enable);
- continue;
- }
-
- ret = intel_crtc_prepare_cleared_state(state, crtc);
- if (ret)
- goto fail;
-
- if (!new_crtc_state->hw.enable)
- continue;
-
- ret = intel_modeset_pipe_config(state, crtc);
- if (ret)
- goto fail;
-
- ret = intel_atomic_check_bigjoiner(state, crtc);
- if (ret)
- goto fail;
- }
-
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
if (!intel_crtc_needs_modeset(new_crtc_state))
--
2.37.2
[Intel-gfx] [PATCH v3 09/25] drm/i915: Add helpers for BW management on shared display links
At the moment a modeset fails if the config computation of a pipe can't
fit its required BW to the available link BW even though the limitation
may be resolved by reducing the BW requirement of other pipes.
To improve the above this patch adds helper functions checking the
overall BW limits after all CRTC states have been computed. If the check
fails the maximum link bpp for a selected pipe will be reduced and all
the CRTC states will be recomputed until either the overall BW limit
check passes, or further bpp reduction is not possible (because all
pipes/encoders sharing the link BW reached their minimum link bpp).
This change prepares for upcoming patches enabling the above BW
management on FDI and MST links.
v2:
- Rename intel_crtc_state::max_link_bpp to max_link_bpp_x16 and
intel_link_bw_limits::max_bpp to max_bpp_x16. (Jani)
v3:
- Add the helper functions in a separate patch. (Ville)
- Add the functions to intel_link_bw.c instead of intel_atomic.c (Ville)
- Return -ENOSPC instead of -EINVAL to userspace in case of a link BW
limit failure.
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_crtc.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 61 -
.../drm/i915/display/intel_display_types.h| 3 +-
drivers/gpu/drm/i915/display/intel_link_bw.c | 226 ++
drivers/gpu/drm/i915/display/intel_link_bw.h | 38 +++
6 files changed, 325 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_link_bw.c
create mode 100644 drivers/gpu/drm/i915/display/intel_link_bw.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1b2e02e9d92cb..de4967c141f00 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -268,6 +268,7 @@ i915-y += \
display/intel_hotplug.o \
display/intel_hotplug_irq.o \
display/intel_hti.o \
+ display/intel_link_bw.o \
display/intel_load_detect.o \
display/intel_lpe_audio.o \
display/intel_modeset_lock.o \
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 182c6dd64f47c..1eda6a9f19aa8 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -175,6 +175,7 @@ void intel_crtc_state_reset(struct intel_crtc_state
*crtc_state,
crtc_state->hsw_workaround_pipe = INVALID_PIPE;
crtc_state->scaler_state.scaler_id = -1;
crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
+ crtc_state->max_link_bpp_x16 = INT_MAX;
}
static struct intel_crtc *intel_crtc_alloc(void)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index fe3b6844e063d..29816153fdd59 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -87,6 +87,7 @@
#include "intel_frontbuffer.h"
#include "intel_hdmi.h"
#include "intel_hotplug.h"
+#include "intel_link_bw.h"
#include "intel_lvds.h"
#include "intel_lvds_regs.h"
#include "intel_modeset_setup.h"
@@ -4596,7 +4597,8 @@ intel_crtc_prepare_cleared_state(struct
intel_atomic_state *state,
static int
intel_modeset_pipe_config(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+ struct intel_crtc *crtc,
+ const struct intel_link_bw_limits *limits)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
@@ -4628,6 +4630,15 @@ intel_modeset_pipe_config(struct intel_atomic_state
*state,
if (ret)
return ret;
+ crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
+
+ if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {
+ drm_dbg_kms(>drm,
+ "[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT
"\n",
+ crtc->base.base.id, crtc->base.name,
+ BPP_X16_ARGS(crtc_state->max_link_bpp_x16));
+ }
+
base_bpp = crtc_state->pipe_bpp;
/*
@@ -6195,7 +6206,9 @@ static int intel_bigjoiner_add_affected_crtcs(struct
intel_atomic_state *state)
return 0;
}
-static int intel_atomic_check_config(struct intel_atomic_state *state)
+int intel_atomic_check_config(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits,
+ enum pipe *failed_pipe)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state;
@@ -6203,6 +6216,8 @@ static int intel_atomic_check_config(struct
intel_atomic_state *state)
int ret;
int i;
+ *failed_pipe = INVALID_PIPE;
+
ret = intel_bigjoiner_add_affected_crtcs(state);
if
[Intel-gfx] [PATCH v3 07/25] drm/i915: During modeset forcing handle inactive but enabled pipes
When forcing a modeset after a BW limit check to recompute the state of all CRTCs on a link shared by the CRTCs, inactive but otherwise enabled (aka DPMS off) CRTCs must be also modeset as their BW requirement may need to be decreased. Based on the above force-modeset inactive but enabled CRTCs as well as required. For the current force modeset scenarios (for instance CDCLK change) this won't make a difference, as during HW programming the inactive CRTCs are skipped even though they are marked for a modeset. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 27e6ea21e0a91..44abe583a672d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5426,7 +5426,7 @@ static int intel_modeset_pipes_in_mask(struct intel_atomic_state *state, if (IS_ERR(crtc_state)) return PTR_ERR(crtc_state); - if (!crtc_state->hw.active || + if (!crtc_state->hw.enable || intel_crtc_needs_modeset(crtc_state)) continue; -- 2.37.2
[Intel-gfx] [PATCH v3 11/25] drm/i915/fdi: Recompute state for affected CRTCs on FDI links
Recompute the state of all CRTCs on an FDI link during a modeset that
may be affected by the modeset of other CRTCs on the same link. This
ensures that each CRTC on the link maximizes its BW use (after another
CRTC is disabled).
In practice this means recomputing pipe B's config on IVB if pipe C gets
disabled.
v2:
- Add the change recomputing affected CRTC states in a separate patch.
(Ville)
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++
drivers/gpu/drm/i915/display/intel_fdi.c | 53
drivers/gpu/drm/i915/display/intel_fdi.h | 1 +
3 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index aad16dcceb788..31297a333f50e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6210,6 +6210,10 @@ int intel_atomic_check_config(struct intel_atomic_state
*state,
if (ret)
return ret;
+ ret = intel_fdi_add_affected_crtcs(state);
+ if (ret)
+ return ret;
+
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (!intel_crtc_needs_modeset(new_crtc_state)) {
if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index ad01915a4a39b..d723ae7e10d71 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -120,6 +120,59 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state);
}
+/**
+ * intel_fdi_add_affected_crtcs - add CRTCs on FDI affected by other modeset
CRTCs
+ * @state: intel atomic state
+ *
+ * Add a CRTC using FDI to @state if changing another CRTC's FDI BW usage is
+ * known to affect the available FDI BW for the former CRTC. In practice this
+ * means adding CRTC B on IVYBRIDGE if its use of FDI lanes is limited (by
+ * CRTC C) and CRTC C is getting disabled.
+ *
+ * Returns 0 in case of success, or a negative error code otherwise.
+ */
+int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_crtc_state *old_crtc_state;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc *crtc;
+
+ if (!IS_IVYBRIDGE(i915))
+ return 0;
+
+ crtc = intel_crtc_for_pipe(i915, PIPE_C);
+ new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (!new_crtc_state)
+ return 0;
+
+ old_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (!old_crtc_state->fdi_lanes)
+ return 0;
+
+ if (!intel_crtc_needs_modeset(new_crtc_state))
+ return 0;
+
+ if (new_crtc_state->uapi.enable)
+ return 0;
+
+ crtc = intel_crtc_for_pipe(i915, PIPE_B);
+ new_crtc_state = intel_atomic_get_crtc_state(>base, crtc);
+
+ if (IS_ERR(new_crtc_state))
+ return PTR_ERR(old_crtc_state);
+
+ old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
+ if (!old_crtc_state->fdi_lanes)
+ return 0;
+
+ return intel_modeset_pipes_in_mask_early(state,
+"FDI link BW decrease on pipe
C",
+BIT(PIPE_B));
+}
+
/* units of 100MHz */
static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
{
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h
b/drivers/gpu/drm/i915/display/intel_fdi.h
index 129444c580f27..eb02b967bb440 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.h
+++ b/drivers/gpu/drm/i915/display/intel_fdi.h
@@ -14,6 +14,7 @@ struct intel_crtc_state;
struct intel_encoder;
struct intel_link_bw_limits;
+int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state);
int intel_fdi_link_freq(struct drm_i915_private *i915,
const struct intel_crtc_state *pipe_config);
int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
--
2.37.2
[Intel-gfx] [PATCH v3 04/25] drm/i915/dp: Update the link bpp limits for DSC mode
In non-DSC mode the link bpp can be set in 2*3 bpp steps in the pipe bpp
range, while in DSC mode it can be set in 1/16 bpp steps to any value
up to the maximum pipe bpp. Update the limits accordingly in both modes
to prepare for a follow-up patch which may need to reduce the max link
bpp value and starts to check the link bpp limits in DSC mode as well.
While at it add more detail to the link limit debug print and print it
also for DSC mode.
v2:
- Add to_bpp_frac_dec() instead of open coding it. (Jani)
v3: (Ville)
- Add BPP_X16_FMT / BPP_X16_ARG.
- Add TODO: comment about initializing the DSC link bpp limits earlier.
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_types.h| 8 ++
drivers/gpu/drm/i915/display/intel_dp.c | 93 +++
drivers/gpu/drm/i915/display/intel_dp.h | 6 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 23 +++--
4 files changed, 108 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index bdad675e03fb8..50fe8ff354137 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2115,6 +2115,14 @@ static inline int to_bpp_int(int bpp_x16)
return bpp_x16 >> 4;
}
+static inline int to_bpp_frac(int bpp_x16)
+{
+ return bpp_x16 & 0xf;
+}
+
+#define BPP_X16_FMT"%d.%04d"
+#define BPP_X16_ARGS(bpp_x16) to_bpp_int(bpp_x16), (to_bpp_frac(bpp_x16) *
625)
+
static inline int to_bpp_x16(int bpp)
{
return bpp << 4;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index bdaaad34463fb..2a45eefc83ebf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2190,16 +2190,72 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
return 0;
}
-static void
+/**
+ * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
+ * @intel_dp: intel DP
+ * @crtc_state: crtc state
+ * @dsc: DSC compression mode
+ * @limits: link configuration limits
+ *
+ * Calculates the output link min, max bpp values in @limits based on the
+ * pipe bpp range, @crtc_state and @dsc mode.
+ *
+ * Returns %true in case of success.
+ */
+bool
+intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state,
+ bool dsc,
+ struct link_config_limits *limits)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ const struct drm_display_mode *adjusted_mode =
+ _state->hw.adjusted_mode;
+ const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
+ int max_link_bpp_x16;
+
+ max_link_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
+
+ if (!dsc) {
+ max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 *
3));
+
+ if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
+ return false;
+
+ limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
+ } else {
+ /*
+* TODO: set the DSC link limits already here, atm these are
+* initialized only later in intel_edp_dsc_compute_pipe_bpp() /
+* intel_dp_dsc_compute_pipe_bpp()
+*/
+ limits->link.min_bpp_x16 = 0;
+ }
+
+ limits->link.max_bpp_x16 = max_link_bpp_x16;
+
+ drm_dbg_kms(>drm,
+ "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d
kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT
"\n",
+ encoder->base.base.id, encoder->base.name,
+ crtc->base.base.id, crtc->base.name,
+ adjusted_mode->crtc_clock,
+ dsc ? "on" : "off",
+ limits->max_lane_count,
+ limits->max_rate,
+ limits->pipe.max_bpp,
+ BPP_X16_ARGS(limits->link.max_bpp_x16));
+
+ return true;
+}
+
+static bool
intel_dp_compute_config_limits(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
bool respect_downstream_limits,
+ bool dsc,
struct link_config_limits *limits)
{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- const struct drm_display_mode *adjusted_mode =
- _state->hw.adjusted_mode;
-
limits->min_rate = intel_dp_common_rate(intel_dp, 0);
limits->max_rate = intel_dp_max_link_rate(intel_dp);
@@ -2225,13 +2281,10 @@
[Intel-gfx] [PATCH v3 06/25] drm/i915: Add helper to modeset a set of pipes
Add intel_modeset_pipes_in_mask_early() to modeset a provided set of
pipes, used in a follow-up patch.
While at it add _late suffix to intel_modeset_all_pipes() for clarity
and add DocBook descriptions for the two exported functions.
v2:
- Add a flag controlling if active planes are force updated as well.
- Add DockBook descriptions.
v3:
- For clarity use _early/_late suffixes for the exported functions
instead of the update_active_planes parameter. (Ville)
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 45 ++--
drivers/gpu/drm/i915/display/intel_display.h | 6 ++-
drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
4 files changed, 47 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ad5251ba6fe13..a2e20b25d6361 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3139,7 +3139,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
} else if (intel_cdclk_needs_modeset(_cdclk_state->actual,
_cdclk_state->actual)) {
/* All pipes must be switched off while we change the cdclk. */
- ret = intel_modeset_all_pipes(state, "CDCLK change");
+ ret = intel_modeset_all_pipes_late(state, "CDCLK change");
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 6bbc9069754c4..27e6ea21e0a91 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5407,8 +5407,9 @@ intel_verify_planes(struct intel_atomic_state *state)
plane_state->uapi.visible);
}
-int intel_modeset_all_pipes(struct intel_atomic_state *state,
- const char *reason)
+static int intel_modeset_pipes_in_mask(struct intel_atomic_state *state,
+ const char *reason, u8 mask,
+ bool update_active_planes)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc *crtc;
@@ -5417,7 +5418,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state
*state,
* Add all pipes to the state, and force
* a modeset on all the active ones.
*/
- for_each_intel_crtc(_priv->drm, crtc) {
+ for_each_intel_crtc_in_pipe_mask(_priv->drm, crtc, mask) {
struct intel_crtc_state *crtc_state;
int ret;
@@ -5448,7 +5449,9 @@ int intel_modeset_all_pipes(struct intel_atomic_state
*state,
if (ret)
return ret;
- crtc_state->update_planes |= crtc_state->active_planes;
+ if (update_active_planes)
+ crtc_state->update_planes |= crtc_state->active_planes;
+
crtc_state->async_flip_planes = 0;
crtc_state->do_async_flip = false;
}
@@ -5456,6 +5459,40 @@ int intel_modeset_all_pipes(struct intel_atomic_state
*state,
return 0;
}
+/**
+ * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
+ * @state: intel atomic state
+ * @reason: the reason for the full modeset
+ * @mask: mask of pipes to modeset
+ *
+ * Force a full modeset on pipes in @mask due to the description in @reason.
+ * This function can be called only before new plane states are computed.
+ *
+ * Returns 0 in case of success, negative error code otherwise.
+ */
+int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
+ const char *reason, u8 mask)
+{
+ return intel_modeset_pipes_in_mask(state, reason, mask, false);
+}
+
+/**
+ * intel_modeset_all_pipes_late - force a full modeset on all pipes
+ * @state: intel atomic state
+ * @reason: the reason for the full modeset
+ *
+ * Force a full modeset on all pipes due to the description in @reason.
+ * This function can be called only after new plane states are computed
+ * already.
+ *
+ * Returns 0 in case of success, negative error code otherwise.
+ */
+int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
+const char *reason)
+{
+ return intel_modeset_pipes_in_mask(state, reason, -1, true);
+}
+
/*
* This implements the workaround described in the "notes" section of the mode
* set sequence documentation. When going from no pipes or single pipe to
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 49ac8473b988b..64a5be7859331 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -513,8 +513,10 @@ void
[Intel-gfx] [PATCH v3 05/25] drm/i915/dp: Limit the output link bpp in DSC mode
Limit the output link bpp in DSC mode to the link_config_limits
link.min_bpp_x16 .. max_bpp_x16 range the same way it's done in non-DSC
mode. Atm this doesn't make a difference, the link bpp range being
0 .. max pipe bpp, but a follow-up patch will need a way to reduce max
link bpp below its current value.
v2:
- Add to_bpp_int_roundup() instead of open coding it. (Jani)
Cc: Jani Nikula
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display_types.h | 5 +
drivers/gpu/drm/i915/display/intel_dp.c| 4
drivers/gpu/drm/i915/display/intel_dp_mst.c| 3 +++
3 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 50fe8ff354137..966163ccbd7a3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2123,6 +2123,11 @@ static inline int to_bpp_frac(int bpp_x16)
#define BPP_X16_FMT"%d.%04d"
#define BPP_X16_ARGS(bpp_x16) to_bpp_int(bpp_x16), (to_bpp_frac(bpp_x16) *
625)
+static inline int to_bpp_int_roundup(int bpp_x16)
+{
+ return (bpp_x16 + 0xf) >> 4;
+}
+
static inline int to_bpp_x16(int bpp)
{
return bpp << 4;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2a45eefc83ebf..d5e6813d36c8f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1925,6 +1925,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp
*intel_dp,
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
+ dsc_min_bpp = max(dsc_min_bpp,
to_bpp_int_roundup(limits->link.min_bpp_x16));
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config,
pipe_bpp / 3);
@@ -1934,6 +1935,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp
*intel_dp,
adjusted_mode->hdisplay,
pipe_config->bigjoiner_pipes);
dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
+ dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
if (DISPLAY_VER(i915) >= 13)
return xelpd_dsc_compute_link_config(intel_dp, pipe_config,
limits,
@@ -2079,10 +2081,12 @@ static int intel_edp_dsc_compute_pipe_bpp(struct
intel_dp *intel_dp,
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
+ dsc_min_bpp = max(dsc_min_bpp,
to_bpp_int_roundup(limits->link.min_bpp_x16));
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config,
pipe_bpp / 3);
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp)
: dsc_src_max_bpp;
+ dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
/* Compressed BPP should be less than the Input DSC bpp */
dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 7d84689d69fad..d38d0dd23fc39 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -233,6 +233,9 @@ static int intel_dp_dsc_mst_compute_link_config(struct
intel_encoder *encoder,
if (max_bpp > sink_max_bpp)
max_bpp = sink_max_bpp;
+ min_bpp = max(min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
+ max_bpp = min(max_bpp, to_bpp_int(limits->link.max_bpp_x16));
+
slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
max_bpp,
min_bpp, limits,
conn_state, 2 * 3, true);
--
2.37.2
[Intel-gfx] [PATCH v3 01/25] drm/i915/dp: Factor out helpers to compute the link limits
Factor out helpers that DP / DP_MST encoders can use to compute the link
rate/lane count and bpp limits. A follow-up patch will call these to
recalculate the limits if DSC compression is required.
Reviewed-by: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 61 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 52 ++
2 files changed, 68 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 55ba6eeaa810d..78984d5126bbe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2188,29 +2188,25 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
return 0;
}
-static int
-intel_dp_compute_link_config(struct intel_encoder *encoder,
-struct intel_crtc_state *pipe_config,
-struct drm_connector_state *conn_state,
-bool respect_downstream_limits)
+static void
+intel_dp_compute_config_limits(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ bool respect_downstream_limits,
+ struct link_config_limits *limits)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
const struct drm_display_mode *adjusted_mode =
- _config->hw.adjusted_mode;
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- struct link_config_limits limits;
- bool joiner_needs_dsc = false;
- int ret;
+ _state->hw.adjusted_mode;
- limits.min_rate = intel_dp_common_rate(intel_dp, 0);
- limits.max_rate = intel_dp_max_link_rate(intel_dp);
+ limits->min_rate = intel_dp_common_rate(intel_dp, 0);
+ limits->max_rate = intel_dp_max_link_rate(intel_dp);
- limits.min_lane_count = 1;
- limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
+ limits->min_lane_count = 1;
+ limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
- limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
- limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config,
respect_downstream_limits);
+ limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
+ limits->max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
+ respect_downstream_limits);
if (intel_dp->use_max_params) {
/*
@@ -2221,16 +2217,35 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
* configuration, and typically on older panels these
* values correspond to the native resolution of the panel.
*/
- limits.min_lane_count = limits.max_lane_count;
- limits.min_rate = limits.max_rate;
+ limits->min_lane_count = limits->max_lane_count;
+ limits->min_rate = limits->max_rate;
}
- intel_dp_adjust_compliance_config(intel_dp, pipe_config, );
+ intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
drm_dbg_kms(>drm, "DP link computation with max lane count %i "
"max rate %d max bpp %d pixel clock %iKHz\n",
- limits.max_lane_count, limits.max_rate,
- limits.max_bpp, adjusted_mode->crtc_clock);
+ limits->max_lane_count, limits->max_rate,
+ limits->max_bpp, adjusted_mode->crtc_clock);
+}
+
+static int
+intel_dp_compute_link_config(struct intel_encoder *encoder,
+struct intel_crtc_state *pipe_config,
+struct drm_connector_state *conn_state,
+bool respect_downstream_limits)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ const struct drm_display_mode *adjusted_mode =
+ _config->hw.adjusted_mode;
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct link_config_limits limits;
+ bool joiner_needs_dsc = false;
+ int ret;
+
+ intel_dp_compute_config_limits(intel_dp, pipe_config,
+ respect_downstream_limits, );
if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
adjusted_mode->crtc_clock))
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 1c7f0b6afe475..f4fcfc6926881 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -293,6 +293,35 @@ static int
[Intel-gfx] [PATCH v3 03/25] drm/i915/dp: Skip computing a non-DSC link config if DSC is needed
Computing the non-DSC mode link config is redundant once it's determined
that DSC will be needed, so skip computing it. In a follow-up patch this
simplifies setting the link limits which are dependent on the DSC vs.
non-DSC mode.
While at it sanitize the debug print about the MST DSC fallback path,
making it similar to the SST DSC one.
Reviewed-by: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp.c | 22 --
drivers/gpu/drm/i915/display/intel_dp_mst.c | 25 +++--
2 files changed, 33 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 5fd32280eab2f..bdaaad34463fb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2247,7 +2247,8 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct link_config_limits limits;
bool joiner_needs_dsc = false;
- int ret;
+ bool dsc_needed;
+ int ret = 0;
intel_dp_compute_config_limits(intel_dp, pipe_config,
respect_downstream_limits, );
@@ -2263,13 +2264,20 @@ intel_dp_compute_link_config(struct intel_encoder
*encoder,
*/
joiner_needs_dsc = DISPLAY_VER(i915) < 13 &&
pipe_config->bigjoiner_pipes;
- /*
-* Optimize for slow and wide for everything, because there are some
-* eDP 1.3 and 1.4 panels don't work well with fast and narrow.
-*/
- ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
conn_state, );
+ dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en;
- if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
+ if (!dsc_needed) {
+ /*
+* Optimize for slow and wide for everything, because there are
some
+* eDP 1.3 and 1.4 panels don't work well with fast and narrow.
+*/
+ ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
+ conn_state, );
+ if (ret)
+ dsc_needed = true;
+ }
+
+ if (dsc_needed) {
drm_dbg_kms(>drm, "Try DSC (fallback=%s, joiner=%s,
force=%s)\n",
str_yes_no(ret), str_yes_no(joiner_needs_dsc),
str_yes_no(intel_dp->force_dsc_en));
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 69342bce6953d..2a0f2caf5b8d7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -337,7 +337,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder
*encoder,
const struct drm_display_mode *adjusted_mode =
_config->hw.adjusted_mode;
struct link_config_limits limits;
- int ret;
+ bool dsc_needed;
+ int ret = 0;
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
@@ -348,15 +349,25 @@ static int intel_dp_mst_compute_config(struct
intel_encoder *encoder,
intel_dp_mst_compute_config_limits(intel_dp, pipe_config, );
- ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
- conn_state, );
+ dsc_needed = intel_dp->force_dsc_en;
- if (ret == -EDEADLK)
- return ret;
+ if (!dsc_needed) {
+ ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
+ conn_state, );
+
+ if (ret == -EDEADLK)
+ return ret;
+
+ if (ret)
+ dsc_needed = true;
+ }
/* enable compression if the mode doesn't fit available BW */
- drm_dbg_kms(_priv->drm, "Force DSC en = %d\n",
intel_dp->force_dsc_en);
- if (ret || intel_dp->force_dsc_en) {
+ if (dsc_needed) {
+ drm_dbg_kms(_priv->drm, "Try DSC (fallback=%s, force=%s)\n",
+ str_yes_no(ret),
+ str_yes_no(intel_dp->force_dsc_en));
+
/*
* FIXME: As bpc is hardcoded to 8, as mentioned above,
* WARN and ignore the debug flag force_dsc_bpc for now.
--
2.37.2
[Intel-gfx] [PATCH v3 02/25] drm/i915/dp: Track the pipe and link bpp limits separately
A follow-up patch will need to limit the output link bpp both in the
non-DSC and DSC configuration, so track the pipe and link bpp limits
separately in the link_config_limits struct.
Use .4 fixed point format for link bpp matching the 1/16 bpp granularity
in DSC mode and for now keep this limit matching the pipe bpp limit.
v2: (Jani)
- Add to_bpp_int(), to_bpp_x16() helpers instead of opencoding them.
- Rename link_config_limits::link.min/max_bpp to min/max_bpp_x16.
Cc: Jani Nikula
Reviewed-by: Luca Coelho
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_display_types.h| 10 +++
drivers/gpu/drm/i915/display/intel_dp.c | 27 +++
drivers/gpu/drm/i915/display/intel_dp.h | 9 ++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 +++-
4 files changed, 45 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 4b807c377166e..bdad675e03fb8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2110,4 +2110,14 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
+static inline int to_bpp_int(int bpp_x16)
+{
+ return bpp_x16 >> 4;
+}
+
+static inline int to_bpp_x16(int bpp)
+{
+ return bpp << 4;
+}
+
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 78984d5126bbe..5fd32280eab2f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1470,7 +1470,7 @@ intel_dp_adjust_compliance_config(struct intel_dp
*intel_dp,
if (intel_dp->compliance.test_data.bpc != 0) {
int bpp = 3 * intel_dp->compliance.test_data.bpc;
- limits->min_bpp = limits->max_bpp = bpp;
+ limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;
pipe_config->dither_force_disable = bpp == 6 * 3;
drm_dbg_kms(>drm, "Setting pipe_bpp to %d\n", bpp);
@@ -1532,7 +1532,9 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config,
conn_state);
int mode_rate, link_rate, link_avail;
- for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
+ for (bpp = to_bpp_int(limits->link.max_bpp_x16);
+bpp >= to_bpp_int(limits->link.min_bpp_x16);
+bpp -= 2 * 3) {
int link_bpp = intel_dp_output_bpp(pipe_config->output_format,
bpp);
mode_rate = intel_dp_link_required(clock, link_bpp);
@@ -1958,8 +1960,8 @@ bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private
*i915,
dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915),
conn_state->max_requested_bpc);
dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
- dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->max_bpp);
- dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->min_bpp);
+ dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
+ dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
return pipe_bpp >= dsc_min_pipe_bpp &&
pipe_bpp <= dsc_max_pipe_bpp;
@@ -2019,10 +2021,10 @@ static int intel_dp_dsc_compute_pipe_bpp(struct
intel_dp *intel_dp,
return -EINVAL;
dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
- dsc_max_bpp = min(dsc_max_bpc * 3, limits->max_bpp);
+ dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
- dsc_min_bpp = max(dsc_min_bpc * 3, limits->min_bpp);
+ dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
/*
* Get the maximum DSC bpc that will be supported by any valid
@@ -2061,7 +2063,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp
*intel_dp,
if (forced_bpp) {
pipe_bpp = forced_bpp;
} else {
- int max_bpc = min(limits->max_bpp / 3,
(int)conn_state->max_requested_bpc);
+ int max_bpc = min(limits->pipe.max_bpp / 3,
(int)conn_state->max_requested_bpc);
/* For eDP use max bpp that can be supported with DSC. */
pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, max_bpc);
@@ -2204,9 +2206,9 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
limits->min_lane_count = 1;
limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
- limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
- limits->max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
- respect_downstream_limits);
+ limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
+ limits->pipe.max_bpp =
[Intel-gfx] [PATCH v3 00/25] drm/i915: Improve BW management on shared display links
This is v3 of [1] addressing the review comments, adding R-bs and the following changes based on further testing / offline discussions: - Return -ENOSPC to userspace in case of a link BW limit failure. (Patch 9, thanks to Karthik B S for the related IGT testing) - Replace fractional bpp fix with a patch from Ville. (Patch 12) - Disable DSC PPS SDP during output disabling. (Patch 20, Ville) [1] https://lore.kernel.org/intel-gfx/20230824080517.693621-1-imre.d...@intel.com Cc: Jani Nikula Cc: Stanislav Lisovskiy Cc: Lyude Paul Cc: Ville Syrjälä Cc: Luca Coelho Imre Deak (24): drm/i915/dp: Factor out helpers to compute the link limits drm/i915/dp: Track the pipe and link bpp limits separately drm/i915/dp: Skip computing a non-DSC link config if DSC is needed drm/i915/dp: Update the link bpp limits for DSC mode drm/i915/dp: Limit the output link bpp in DSC mode drm/i915: Add helper to modeset a set of pipes drm/i915: During modeset forcing handle inactive but enabled pipes drm/i915: Factor out a helper to check/compute all the CRTC states drm/i915: Add helpers for BW management on shared display links drm/i915/fdi: Improve FDI BW sharing between pipe B and C drm/i915/fdi: Recompute state for affected CRTCs on FDI links drm/dp_mst: Add a way to calculate PBN values with FEC overhead drm/dp_mst: Add helper to determine if an MST port is downstream of another port drm/dp_mst: Factor out a helper to check the atomic state of a topology manager drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations drm/i915/dp_mst: Fix PBN calculation with FEC overhead drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms drm/i915/dp_mst: Program the DSC PPS SDP for each stream drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled drm/i915/dp_mst: Enable DSC decompression if any stream needs this drm/i915/dp_mst: Add missing DSC compression disabling drm/i915/dp_mst: Allow DSC only for sink ports of the first branch device drm/i915/dp_mst: Improve BW sharing between MST streams drm/i915/dp_mst: Check BW limitations only after all streams are computed Ville Syrjälä (1): drm/dp_mst: Fix fractional DSC bpp handling .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +- drivers/gpu/drm/display/drm_dp_mst_topology.c | 181 --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/g4x_hdmi.c | 6 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 2 +- drivers/gpu/drm/i915/display/intel_crt.c | 7 + drivers/gpu/drm/i915/display/intel_crtc.c | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 12 +- drivers/gpu/drm/i915/display/intel_display.c | 203 + drivers/gpu/drm/i915/display/intel_display.h | 6 +- .../drm/i915/display/intel_display_types.h| 26 +- drivers/gpu/drm/i915/display/intel_dp.c | 196 +--- drivers/gpu/drm/i915/display/intel_dp.h | 17 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 287 +++--- drivers/gpu/drm/i915/display/intel_dp_mst.h | 3 + drivers/gpu/drm/i915/display/intel_fdi.c | 140 +++-- drivers/gpu/drm/i915/display/intel_fdi.h | 5 + drivers/gpu/drm/i915/display/intel_link_bw.c | 244 +++ drivers/gpu/drm/i915/display/intel_link_bw.h | 39 +++ drivers/gpu/drm/i915/display/intel_lvds.c | 10 +- drivers/gpu/drm/i915/display/intel_sdvo.c | 10 +- drivers/gpu/drm/i915/display/skl_watermark.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 +- .../gpu/drm/tests/drm_dp_mst_helper_test.c| 19 +- include/drm/display/drm_dp_mst_helper.h | 9 +- 26 files changed, 1203 insertions(+), 230 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_link_bw.c create mode 100644 drivers/gpu/drm/i915/display/intel_link_bw.h -- 2.37.2
Re: [Intel-gfx] [PATCH 2/7] drm/i915: Create a kernel context for GGTT updates
Hi Oak,
On 9/13/2023 6:30 PM, Zeng, Oak wrote:
Thanks,
Oak
-Original Message-
From: Das, Nirmoy
Sent: Wednesday, September 13, 2023 9:10 AM
To: intel-gfx@lists.freedesktop.org
Cc: Zeng, Oak ; chris.p.wil...@linux.intel.com; Piorkowski,
Piotr ; Shyti, Andi ; Mun,
Gwan-gyeong ; Roper, Matthew D
; Das, Nirmoy
Subject: [PATCH 2/7] drm/i915: Create a kernel context for GGTT updates
Create a separate kernel context if a platform requires
GGTT updates using MI_UPDATE_GTT blitter command.
Subsequent patch will introduce methods to update
GGTT using this bind context and MI_UPDATE_GTT blitter
command.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_engine.h | 2 ++
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 33 +++-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 ++
drivers/gpu/drm/i915/gt/intel_gt.c | 18 +++
drivers/gpu/drm/i915/gt/intel_gt.h | 2 ++
5 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index b58c30ac8ef0..40269e4c1e31 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -170,6 +170,8 @@ intel_write_status_page(struct intel_engine_cs *engine,
int reg, u32 value)
#define I915_GEM_HWS_SEQNO0x40
#define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO
* sizeof(u32))
#define I915_GEM_HWS_MIGRATE (0x42 * sizeof(u32))
+#define I915_GEM_HWS_GGTT_BIND 0x46
+#define I915_GEM_HWS_GGTT_BIND_ADDR(I915_GEM_HWS_GGTT_BIND *
sizeof(u32))
#define I915_GEM_HWS_PXP 0x60
#define I915_GEM_HWS_PXP_ADDR (I915_GEM_HWS_PXP *
sizeof(u32))
#define I915_GEM_HWS_GSC 0x62
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index dfb69fc977a0..52a24f55cb57 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1419,6 +1419,20 @@ void intel_engine_destroy_pinned_context(struct
intel_context *ce)
intel_context_put(ce);
}
+static struct intel_context *
+create_ggtt_bind_context(struct intel_engine_cs *engine)
+{
+ static struct lock_class_key kernel;
+
+ /*
+* MI_UPDATE_GTT can insert up to 512 PTE entries and there could be
multiple
+* bind requets at a time so get a bigger ring.
+*/
+ return intel_engine_create_pinned_context(engine, engine->gt->vm,
SZ_512K,
+
I915_GEM_HWS_GGTT_BIND_ADDR,
+ , "ggtt_bind_context");
+}
+
static struct intel_context *
create_kernel_context(struct intel_engine_cs *engine)
{
@@ -1442,7 +1456,7 @@ create_kernel_context(struct intel_engine_cs *engine)
*/
static int engine_init_common(struct intel_engine_cs *engine)
{
- struct intel_context *ce;
+ struct intel_context *ce, *bce = NULL;
int ret;
engine->set_default_submission(engine);
@@ -1458,6 +1472,17 @@ static int engine_init_common(struct intel_engine_cs
*engine)
ce = create_kernel_context(engine);
if (IS_ERR(ce))
return PTR_ERR(ce);
+ /*
+* Create a separate pinned context for GGTT update with blitter engine
+* if a platform require such service. MI_UPDATE_GTT works on other
+* engines as well but BCS should be less busy engine so pick that for
+* GGTT updates.
+*/
+ if (engine->id == BCS0) {
+ bce = create_ggtt_bind_context(engine);
+ if (IS_ERR(bce))
+ return PTR_ERR(bce);
Do you need to destroy ce before return?
Yes , I will fix it in next rev.
Thanks,
Nirmoy
Oak
+ }
ret = measure_breadcrumb_dw(ce);
if (ret < 0)
@@ -1465,11 +1490,14 @@ static int engine_init_common(struct intel_engine_cs
*engine)
engine->emit_fini_breadcrumb_dw = ret;
engine->kernel_context = ce;
+ engine->bind_context = bce;
return 0;
err_context:
intel_engine_destroy_pinned_context(ce);
+ if (bce)
+ intel_engine_destroy_pinned_context(ce);
return ret;
}
@@ -1537,6 +1565,9 @@ void intel_engine_cleanup_common(struct
intel_engine_cs *engine)
if (engine->kernel_context)
intel_engine_destroy_pinned_context(engine->kernel_context);
+ if (engine->bind_context)
+ intel_engine_destroy_pinned_context(engine->bind_context);
+
GEM_BUG_ON(!llist_empty(>barrier_tasks));
cleanup_status_page(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index a7e677598004..a8f527fab0f0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -416,6 +416,9 @@ struct intel_engine_cs {
struct llist_head barrier_tasks;
[Intel-gfx] [PATCH 1/1] drm/i915/uapi: Enable L3 Bank Count Querying
Extend the query ioctl to allow querying the count of the available L3
Banks on a given engine.
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/i915/gt/intel_gt.c | 26 +++
drivers/gpu/drm/i915/gt/intel_gt.h | 3 +++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/i915_query.c | 34 +
include/uapi/drm/i915_drm.h | 15 ++-
5 files changed, 78 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 449f0b7fc8434..865854c76c375 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -884,6 +884,32 @@ static int intel_gt_tile_setup(struct intel_gt *gt,
phys_addr_t phys_addr)
return 0;
}
+int intel_count_l3_banks(struct drm_i915_private *i915,
+struct intel_engine_cs *engine)
+{
+ struct intel_gt *gt = engine->gt;
+ struct intel_uncore *uncore = gt->uncore;
+ intel_wakeref_t wakeref;
+ u32 count, store;
+
+ /* L3 Banks not supported prior to version 12 */
+ if (GRAPHICS_VER(i915) < 12)
+ return -ENODEV;
+
+ if (IS_PONTEVECCHIO(i915)) {
+ with_intel_runtime_pm(uncore->rpm, wakeref)
+ store = intel_uncore_read(uncore, GEN10_MIRROR_FUSE3);
+ count = hweight32(REG_FIELD_GET(GEN12_MEML3_EN_MASK, store)) *
4 *
+ hweight32(REG_FIELD_GET(XEHPC_GT_L3_MODE_MASK, store));
+ } else if (GRAPHICS_VER_FULL(i915) > IP_VER(12, 50)) {
+ count = hweight32(gt->info.mslice_mask) * 8;
+ } else {
+ count = hweight32(gt->info.l3bank_mask);
+ }
+
+ return count;
+}
+
int intel_gt_probe_all(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 239848bcb2a42..4a05443418efd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -161,6 +161,9 @@ static inline bool intel_gt_is_wedged(const struct intel_gt
*gt)
return unlikely(test_bit(I915_WEDGED, >reset.flags));
}
+int intel_count_l3_banks(struct drm_i915_private *i915,
+struct intel_engine_cs *engine);
+
int intel_gt_probe_all(struct drm_i915_private *i915);
int intel_gt_tiles_init(struct drm_i915_private *i915);
void intel_gt_release_all(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index a00ff51c681d5..f148bf3dfd4b3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -569,6 +569,7 @@
#defineGEN10_MIRROR_FUSE3 _MMIO(0x9118)
#define GEN10_L3BANK_PAIR_COUNT 4
#define GEN10_L3BANK_MASK0x0F
+#define XEHPC_GT_L3_MODE_MASKREG_GENMASK(7, 4)
/* on Xe_HP the same fuses indicates mslices instead of L3 banks */
#define GEN12_MAX_MSLICES4
#define GEN12_MEML3_EN_MASK 0x0F
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index 00871ef997920..bd3e68cf1bd10 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -10,6 +10,7 @@
#include "i915_perf.h"
#include "i915_query.h"
#include "gt/intel_engine_user.h"
+#include "gt/intel_gt.h"
#include
static int copy_query_item(void *query_hdr, size_t query_sz,
@@ -551,6 +552,38 @@ static int query_hwconfig_blob(struct drm_i915_private
*i915,
return hwconfig->size;
}
+static int
+query_l3bank_count(struct drm_i915_private *i915,
+ struct drm_i915_query_item *query_item)
+{
+ struct drm_i915_query_memory_regions __user *query_ptr =
+ u64_to_user_ptr(query_item->data_ptr);
+ struct i915_engine_class_instance classinstance;
+ struct intel_engine_cs *engine;
+ int count;
+
+ if (query_item->length == 0)
+ return sizeof(count);
+
+ classinstance = *((struct i915_engine_class_instance
*)_item->flags);
+
+ engine = intel_engine_lookup_user(i915, (u8)classinstance.engine_class,
+ (u8)classinstance.engine_instance);
+
+ if (!engine)
+ return -EINVAL;
+
+ count = intel_count_l3_banks(i915, engine);
+
+ if (count < 0)
+ return count;
+
+ if (copy_to_user(query_ptr, , sizeof(count)))
+ return -EFAULT;
+
+ return sizeof(count);
+}
+
static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
struct drm_i915_query_item *query_item)
= {
query_topology_info,
@@ -559,6 +592,7 @@ static int (* const i915_query_funcs[])(struct
drm_i915_private
[Intel-gfx] [PATCH 0/1] drm/i915/uapi: Enable L3 Bank Count Querying
Extend the query ioctl to allow querying the count of the available L3 Banks on a given engine. Signed-off-by: Jonathan Cavitt CC: Ashutosh Dixit CC: Matt Roper CC: John Harrison CC: Joonas Lahtinen CC: James Ausmus CC: James C Wright CC: Slawomir Milczarek CC: Michal Mrozek CC: Adam Cetnerowski CC: Bartosz Dunajski Jonathan Cavitt (1): drm/i915/uapi: Enable L3 Bank Count Querying drivers/gpu/drm/i915/gt/intel_gt.c | 26 +++ drivers/gpu/drm/i915/gt/intel_gt.h | 3 +++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/i915_query.c | 34 + include/uapi/drm/i915_drm.h | 15 ++- 5 files changed, 78 insertions(+), 1 deletion(-) -- 2.25.1
Re: [Intel-gfx] [PATCH] i915/guc: Run busyness worker only if gt is awake
On 9/11/2023 5:52 PM, Umesh Nerlige Ramappa wrote:
The worker is canceled in the __gt_park path, but we still see it
running sometimes during suspend.
Only update stats if gt is awake. If not, intel_guc_busyness_park would
have already updated the stats. Note that we do not requeue the worker
if gt is not awake since intel_guc_busyness_unpark would do that at some
point.
If the gt was parked longer than time taken for GT timestamp to roll
over, we ignore those rollovers since we don't care about tracking the
exact GT time. We only care about roll overs when the gt is active and
running workloads.
v2 (Daniele)
- Edit commit message and code comment
- Use runtime pm in the worker
- Put runtime pm after enabling the worker
- Use Link tag and add Fixes tag
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/7077
Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
pmu")
Signed-off-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 26 ---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e250bedf90fb..d37b29a0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1461,6 +1461,24 @@ static void guc_timestamp_ping(struct work_struct *wrk)
unsigned long index;
int srcu, ret;
+ /*
+* The worker is canceled in the __gt_park path, but we still see it
+* running sometimes during suspend.
This sounds very vague and more like there is a bug in __gt_park. We
actually do know that the issue on the park side is that the worker
re-queues itself if it's running while we cancel it; that's not really a
problem as long as we don't wake the device after it's gone to sleep
(which is what your change below does), so this sentence should be
reworded or dropped.
+*
+* Only update stats if gt is awake. If not, intel_guc_busyness_park
+* would have already updated the stats. Note that we do not requeue the
+* worker in this case since intel_guc_busyness_unpark would do that at
+* some point.
+*
+* If the gt was parked longer than time taken for GT timestamp to roll
+* over, we ignore those rollovers since we don't care about tracking
+* the exact GT time. We only care about roll overs when the gt is
+* active and running workloads.
+*/
+ wakeref = intel_runtime_pm_get_if_active(>i915->runtime_pm);
The patch title and the comment refer to GT being awake, but here you're
taking a global rpm ref and not a gt_pm ref. I understand that taking a
gt_pm ref in here can be complicated because of the canceling of the
worker in the gt_park flow and that taking an rpm ref does work for what
we need, but the title/comments need to reflect and explain that.
Daniele
+ if (!wakeref)
+ return;
+
/*
* Synchronize with gt reset to make sure the worker does not
* corrupt the engine/guc stats. NB: can't actually block waiting
@@ -1469,10 +1487,9 @@ static void guc_timestamp_ping(struct work_struct *wrk)
*/
ret = intel_gt_reset_trylock(gt, );
if (ret)
- return;
+ goto err_trylock;
- with_intel_runtime_pm(>i915->runtime_pm, wakeref)
- __update_guc_busyness_stats(guc);
+ __update_guc_busyness_stats(guc);
/* adjust context stats for overflow */
xa_for_each(>context_lookup, index, ce)
@@ -1481,6 +1498,9 @@ static void guc_timestamp_ping(struct work_struct *wrk)
intel_gt_reset_unlock(gt, srcu);
guc_enable_busyness_worker(guc);
+
+err_trylock:
+ intel_runtime_pm_put(>i915->runtime_pm, wakeref);
}
static int guc_action_enable_usage_stats(struct intel_guc *guc)
Re: [Intel-gfx] [PATCH 10/12] drm/i915: Update VRR parameters in fastset
On Fri, Sep 1, 2023 at 9:05 AM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> We should be able to change any of the VRR parameters
> during fastsets as long as we toggle VRR off at the start
> and then back on at the end. The transcoder will be running
> in non-VRR mode during the transition.
>
> Co-developed-by: Manasi Navare
Reviewed-by: Sean Paul
> Signed-off-by: Manasi Navare
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 34 +++-
> 1 file changed, 26 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index cbbee303cd00..f0bb5c70ebfc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -913,18 +913,32 @@ static bool planes_disabling(const struct
> intel_crtc_state *old_crtc_state,
> return is_disabling(active_planes, old_crtc_state, new_crtc_state);
> }
>
> +static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
> + const struct intel_crtc_state *new_crtc_state)
> +{
> + return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||
> + old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
> + old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
> + old_crtc_state->vrr.guardband !=
> new_crtc_state->vrr.guardband ||
> + old_crtc_state->vrr.pipeline_full !=
> new_crtc_state->vrr.pipeline_full;
> +}
> +
> static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> - (new_crtc_state->vrr.enable && new_crtc_state->update_m_n);
> + (new_crtc_state->vrr.enable &&
> +(new_crtc_state->update_m_n ||
> + vrr_params_changed(old_crtc_state, new_crtc_state)));
> }
>
> static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
> - (old_crtc_state->vrr.enable && new_crtc_state->update_m_n);
> + (old_crtc_state->vrr.enable &&
> +(new_crtc_state->update_m_n ||
> + vrr_params_changed(old_crtc_state, new_crtc_state)));
> }
>
> #undef is_disabling
> @@ -5342,13 +5356,14 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> PIPE_CONF_CHECK_I(splitter.link_count);
> PIPE_CONF_CHECK_I(splitter.pixel_overlap);
>
> - if (!fastset)
> + if (!fastset) {
> PIPE_CONF_CHECK_BOOL(vrr.enable);
> - PIPE_CONF_CHECK_I(vrr.vmin);
> - PIPE_CONF_CHECK_I(vrr.vmax);
> - PIPE_CONF_CHECK_I(vrr.flipline);
> - PIPE_CONF_CHECK_I(vrr.pipeline_full);
> - PIPE_CONF_CHECK_I(vrr.guardband);
> + PIPE_CONF_CHECK_I(vrr.vmin);
> + PIPE_CONF_CHECK_I(vrr.vmax);
> + PIPE_CONF_CHECK_I(vrr.flipline);
> + PIPE_CONF_CHECK_I(vrr.pipeline_full);
> + PIPE_CONF_CHECK_I(vrr.guardband);
> + }
>
> #undef PIPE_CONF_CHECK_X
> #undef PIPE_CONF_CHECK_I
> @@ -6554,6 +6569,9 @@ static void intel_update_crtc(struct intel_atomic_state
> *state,
> if (DISPLAY_VER(i915) >= 11 &&
> intel_crtc_needs_fastset(new_crtc_state))
> icl_set_pipe_chicken(new_crtc_state);
> +
> + if (vrr_params_changed(old_crtc_state, new_crtc_state))
> + intel_vrr_set_transcoder_timings(new_crtc_state);
> }
>
> intel_fbc_update(state, crtc);
> --
> 2.41.0
>
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: remove last uses of GEM_BUG_ON/GEM_WARN_ON
== Series Details == Series: drm/i915/display: remove last uses of GEM_BUG_ON/GEM_WARN_ON URL : https://patchwork.freedesktop.org/series/123679/ State : success == Summary == CI Bug Log - changes from CI_DRM_13632 -> Patchwork_123679v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/index.html Participating hosts (39 -> 38) -- Additional (2): fi-hsw-4770 bat-mtlp-8 Missing(3): fi-kbl-soraka fi-snb-2520m fi-pnv-d510 Known issues Here are the changes found in Patchwork_123679v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-mtlp-8: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-8: NOTRUN -> [SKIP][2] ([i915#4613]) +3 other tests skip [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-8: NOTRUN -> [SKIP][3] ([i915#4083]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/bat-mtlp-8/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-mtlp-8: NOTRUN -> [SKIP][4] ([i915#4077]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/bat-mtlp-8/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#4079]) +1 other test skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#6621]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/bat-mtlp-8/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_engines: - bat-mtlp-8: NOTRUN -> [FAIL][7] ([i915#9278] / [i915#9290]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/bat-mtlp-8/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@gt_pm: - bat-mtlp-8: NOTRUN -> [DMESG-FAIL][8] ([i915#9270]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/bat-mtlp-8/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - bat-dg2-11: [PASS][9] -> [ABORT][10] ([i915#7913]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13632/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@mman: - bat-rpls-1: [PASS][11] -> [TIMEOUT][12] ([i915#6794] / [i915#7392]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13632/bat-rpls-1/igt@i915_selftest@l...@mman.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/bat-rpls-1/igt@i915_selftest@l...@mman.html * igt@i915_selftest@live@requests: - bat-mtlp-8: NOTRUN -> [ABORT][13] ([i915#9262]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html * igt@i915_suspend@basic-s2idle-without-i915: - bat-rpls-1: [PASS][14] -> [WARN][15] ([i915#8747]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13632/bat-rpls-1/igt@i915_susp...@basic-s2idle-without-i915.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/bat-rpls-1/igt@i915_susp...@basic-s2idle-without-i915.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - fi-hsw-4770:NOTRUN -> [SKIP][16] ([fdo#109271]) +13 other tests skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html - bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#5190]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][18] ([i915#4212]) +8 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][19] ([i915#4213]) +1 other test skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123679v1/bat-mtlp-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-mtlp-8: NOTRUN -> [SKIP][20] ([i915#3555] / [i915#3840] / [i915#9159]) [20]:
Re: [Intel-gfx] [PATCH v5] drm/i915: Added Wa_18022495364
On Thu, Sep 14, 2023 at 07:17:24PM +0530, Dnyaneshwar Bhadane wrote:
> Set the instruction and state cache invalidate bit using INDIRECT_CTX on
> every gpu context switch.
> The goal of this workaround is to actually perform an explicit
> invalidation of that cache (by re-writing the register) during every GPU
> context switch, which is accomplished via a "workaround batchbuffer"
> that's attached to the context via INDIRECT_CTX. (Matt)
> BSpec: 11354
>
> v2:
> - Removed extra parentheses from the condition (Lucas)
> - Fixed spacing and new line (Lucas)
>
> v3:
> - Fixed commit message.
>
> v4:
> - Only GEN12 changes are kept (Matt Ropper)
> - Fixed the commit message for r-b (Matt Ropper)
> - Renamed the register bit in define
>
> v5:
> - Moved out the from golden context init (Matt Roper)
> - Use INDIRECT_CTX to set bit on each GPU context switch (Matt Roper)
>
> Cc: Lucas De Marchi
> Cc: Matt Roper
> Signed-off-by: Dnyaneshwar Bhadane
>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
> drivers/gpu/drm/i915/gt/intel_lrc.c | 15 +++
> 2 files changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 0e4c638fcbbf..38f02ef8ed01 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -164,6 +164,8 @@
> #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20d4)
> #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
> #define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
> +#define GEN12_CS_DEBUG_MODE2 _MMIO(0x20d8)
> +#define INSTRUCTION_STATE_CACHE_INVALIDATE REG_BIT(6)
>
> #define GEN7_FF_SLICE_CS_CHICKEN1_MMIO(0x20e0)
> #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 967fe4d77a87..fe98039499c5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1332,6 +1332,15 @@ dg2_emit_draw_watermark_setting(u32 *cs)
> return cs;
> }
>
> +static u32 *
> +gen12_set_instruction_state_cache_invalid(u32 *cs)
Minor nitpick: I'd name this "gen12_invalidate_state_cache." The
general terminology with caches is that we "invalidate" them rather than
"set invalid," and that also matches the terminology used by the
register bit itself.
> +{
> + *cs++ = MI_LOAD_REGISTER_IMM(1);
> + *cs++ = i915_mmio_reg_offset(GEN12_CS_DEBUG_MODE2);
> + *cs++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);
> + return cs;
> +}
> +
> static u32 *
> gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
> {
> @@ -1345,6 +1354,12 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context
> *ce, u32 *cs)
>
> cs = gen12_emit_aux_table_inv(ce->engine, cs);
>
> + /* Wa_18022495364 */
> + if (IS_ALDERLAKE_P(ce->engine->i915) ||
> IS_ALDERLAKE_P_N(ce->engine->i915) ||
ADL-N is defined as a subplatform of ADL-P in the driver, so ADL-N
platforms will automatically be matched by the IS_ALDERLAKE_P; you don't
need the IS_ALDERLAKE_P_N condition here (that's only for the rare
places where we want to match ADL-N specifically _without_ matching
other ADL-P platforms as well).
> + IS_ALDERLAKE_S(ce->engine->i915) || IS_TIGERLAKE(ce->engine->i915)
> ||
> + IS_ROCKETLAKE(ce->engine->i915) || IS_DG1(ce->engine->i915))
Since this workaround winds up applying to every single gen12lp platform, it's
probably simpler to just write the condition as
if (IS_GFX_GT_IP_RANGE(cs->engine->i915), IP_VER(12, 0), IP_VER(12, 10))
Matt
> + cs = gen12_set_instruction_state_cache_invalid(cs);
> +
> /* Wa_16014892111 */
> if (IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0)
> ||
> IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)
> ||
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: remove last uses of GEM_BUG_ON/GEM_WARN_ON
== Series Details == Series: drm/i915/display: remove last uses of GEM_BUG_ON/GEM_WARN_ON URL : https://patchwork.freedesktop.org/series/123679/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./drivers/gpu/drm/i915/intel_uncore.h:346:1: warning: trying to copy expression type 31 +./drivers/gpu/drm/i915/intel_uncore.h:351:1: warning: trying to copy expression type 31 +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
Re: [Intel-gfx] [PATCH v3 16/29] drm/i915/xe2lpd: Add display power well
On Tue, Sep 12, 2023 at 11:30:50AM -0500, Lucas De Marchi wrote:
> On Tue, Sep 12, 2023 at 09:04:17AM -0700, Matt Roper wrote:
> > On Mon, Sep 11, 2023 at 09:48:24PM -0700, Lucas De Marchi wrote:
> > > From: Ravi Kumar Vodapalli
> > >
> > > Add Display Power Well for LNL platform. It's mostly the same as MTL
> >
> > It might be better to say "Xe2_LPD" and "Xe_LPD+" instead of LNL/MTL?
>
> ok
>
> >
> > > platform so reuse the code. PGPICA1 contains type-C capable port slices
> > > which requires the well to power powered up, so add new power well
> > > definition for it.
> >
> > Maybe add a sentence noting that the dc_off fake powerwell will be added
> > in a follow-up patch so that people don't think it was overlooked here?
>
> ok
>
> >
> > >
> > > BSpec: 68886
> > > Signed-off-by: Ravi Kumar Vodapalli
> > > Signed-off-by: Gustavo Sousa
> > > Signed-off-by: Lucas De Marchi
> > > ---
> > > .../i915/display/intel_display_power_map.c| 36 ++-
> > > .../i915/display/intel_display_power_well.c | 44 +++
> > > .../i915/display/intel_display_power_well.h | 1 +
> > > .../gpu/drm/i915/display/intel_dp_aux_regs.h | 5 +++
> > > 4 files changed, 85 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > > b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > > index 0f1b93d139ca..31c11586ede5 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > > @@ -1536,6 +1536,38 @@ static const struct i915_power_well_desc_list
> > > xelpdp_power_wells[] = {
> > > I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> > > };
> > >
> > > +I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
> > > + POWER_DOMAIN_PORT_DDI_LANES_TC1,
> > > + POWER_DOMAIN_PORT_DDI_LANES_TC2,
> > > + POWER_DOMAIN_PORT_DDI_LANES_TC3,
> > > + POWER_DOMAIN_PORT_DDI_LANES_TC4,
> > > + POWER_DOMAIN_AUX_USBC1,
> > > + POWER_DOMAIN_AUX_USBC2,
> > > + POWER_DOMAIN_AUX_USBC3,
> > > + POWER_DOMAIN_AUX_USBC4,
> > > + POWER_DOMAIN_AUX_TBT1,
> > > + POWER_DOMAIN_AUX_TBT2,
> > > + POWER_DOMAIN_AUX_TBT3,
> > > + POWER_DOMAIN_AUX_TBT4,
> > > + POWER_DOMAIN_INIT);
> > > +
> > > +static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
> > > + {
> > > + .instances = _PW_INSTANCES(I915_PW("PICA_TC",
> > > + _pwdoms_pica_tc,
> > > + .id = DISP_PW_ID_NONE),
> > > +),
> > > + .ops = _pica_power_well_ops,
> > > + },
> > > +};
> > > +
> > > +static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
> > > + I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
> > > + I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> > > + I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> > > + I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
> > > +};
> > > +
> > > static void init_power_well_domains(const struct
> > > i915_power_well_instance *inst,
> > > struct i915_power_well *power_well)
> > > {
> > > @@ -1643,7 +1675,9 @@ int intel_display_power_map_init(struct
> > > i915_power_domains *power_domains)
> > > return 0;
> > > }
> > >
> > > - if (DISPLAY_VER(i915) >= 14)
> > > + if (DISPLAY_VER(i915) >= 20)
> > > + return set_power_wells(power_domains, xe2lpd_power_wells);
> > > + else if (DISPLAY_VER(i915) >= 14)
> > > return set_power_wells(power_domains, xelpdp_power_wells);
> > > else if (IS_DG2(i915))
> > > return set_power_wells(power_domains, xehpd_power_wells);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > index ca0714eba17a..adfe9901bde4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > @@ -1833,6 +1833,43 @@ static bool xelpdp_aux_power_well_enabled(struct
> > > drm_i915_private *dev_priv,
> > > XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
> > > }
> > >
> > > +static void xe2lpd_pica_power_well_enable(struct drm_i915_private
> > > *dev_priv,
> > > + struct i915_power_well *power_well)
> > > +{
> > > + intel_de_rmw(dev_priv, XE2LPD_PICA_PW_CTL,
> > > + XE2LPD_PICA_CTL_POWER_REQUEST,
> > > + XE2LPD_PICA_CTL_POWER_REQUEST);
> >
> > Do we need rmw here? Bit 31 is the only writable bit in the register
> > (bit 30 is RO and can't be clobbered), so a simple write should suffice?
> > Ditto on the disable below.
> >
> > > +
> > > + if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
> > > +
Re: [Intel-gfx] [PATCH v5] drm/i915: Added Wa_18022495364
> Subject: [Intel-gfx] [PATCH v5] drm/i915: Added Wa_18022495364
>
Commit message style should be imperative so the header becomes something
Around the lines of
"Add Wa_18022495364"
> Set the instruction and state cache invalidate bit using INDIRECT_CTX on every
> gpu context switch.
> The goal of this workaround is to actually perform an explicit invalidation of
> that cache (by re-writing the register) during every GPU context switch,
> which is
> accomplished via a "workaround batchbuffer"
> that's attached to the context via INDIRECT_CTX. (Matt)
> BSpec: 11354
>
> v2:
> - Removed extra parentheses from the condition (Lucas)
> - Fixed spacing and new line (Lucas)
>
> v3:
> - Fixed commit message.
>
> v4:
> - Only GEN12 changes are kept (Matt Ropper)
> - Fixed the commit message for r-b (Matt Ropper)
> - Renamed the register bit in define
>
> v5:
> - Moved out the from golden context init (Matt Roper)
> - Use INDIRECT_CTX to set bit on each GPU context switch (Matt Roper)
>
Same thing applies to the above version fix description
Remove, Fix, Rename, Move
Regards,
Suraj Kandpal
> Cc: Lucas De Marchi
> Cc: Matt Roper
> Signed-off-by: Dnyaneshwar Bhadane
>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
> drivers/gpu/drm/i915/gt/intel_lrc.c | 15 +++
> 2 files changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 0e4c638fcbbf..38f02ef8ed01 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -164,6 +164,8 @@
> #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20d4)
> #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
> #define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
> +#define GEN12_CS_DEBUG_MODE2 _MMIO(0x20d8)
> +#define INSTRUCTION_STATE_CACHE_INVALIDATE REG_BIT(6)
>
> #define GEN7_FF_SLICE_CS_CHICKEN1_MMIO(0x20e0)
> #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14)
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 967fe4d77a87..fe98039499c5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1332,6 +1332,15 @@ dg2_emit_draw_watermark_setting(u32 *cs)
> return cs;
> }
>
> +static u32 *
> +gen12_set_instruction_state_cache_invalid(u32 *cs) {
> + *cs++ = MI_LOAD_REGISTER_IMM(1);
> + *cs++ = i915_mmio_reg_offset(GEN12_CS_DEBUG_MODE2);
> + *cs++ =
> _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);
> + return cs;
> +}
> +
> static u32 *
> gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) { @@ -
> 1345,6 +1354,12 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context
> *ce, u32 *cs)
>
> cs = gen12_emit_aux_table_inv(ce->engine, cs);
>
> + /* Wa_18022495364 */
> + if (IS_ALDERLAKE_P(ce->engine->i915) || IS_ALDERLAKE_P_N(ce-
> >engine->i915) ||
> + IS_ALDERLAKE_S(ce->engine->i915) || IS_TIGERLAKE(ce->engine-
> >i915) ||
> + IS_ROCKETLAKE(ce->engine->i915) || IS_DG1(ce->engine-
> >i915))
> + cs = gen12_set_instruction_state_cache_invalid(cs);
> +
> /* Wa_16014892111 */
> if (IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0,
> STEP_B0) ||
> IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0,
> STEP_B0) ||
> --
> 2.34.1
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Remove runtime suspended boolean from intel_runtime_pm struct (rev3)
== Series Details == Series: drm/i915: Remove runtime suspended boolean from intel_runtime_pm struct (rev3) URL : https://patchwork.freedesktop.org/series/123637/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] PR for HuC v8.5.4 for MTL
The following changes since commit dfa11466cf000120d1551146fd5bf78c44941eda: Merge branch 'main' into 'main' (2023-09-07 11:36:57 +) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware mtl_huc_8.5.4 for you to fetch changes up to a5dbe400f776b0dc2d0a402ba76b4c16c231b38e: i915: update MTL HuC to version 8.5.4 (2023-09-14 08:34:08 -0700) Daniele Ceraolo Spurio (1): i915: update MTL HuC to version 8.5.4 WHENCE | 2 +- i915/mtl_huc_gsc.bin | Bin 569344 -> 561152 bytes 2 files changed, 1 insertion(+), 1 deletion(-)
Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/guc: Flush context destruction worker at suspend
On Sat, Sep 09, 2023 at 08:58:44PM -0700, Alan Previn wrote:
> When suspending, flush the context-guc-id
> deregistration worker at the final stages of
> intel_gt_suspend_late when we finally call gt_sanitize
> that eventually leads down to __uc_sanitize so that
> the deregistration worker doesn't fire off later as
> we reset the GuC microcontroller.
>
> Signed-off-by: Alan Previn
> Tested-by: Mousumi Jana
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 5 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h | 2 ++
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 ++
> 3 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index cabdc645fcdd..0ed44637bca0 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1578,6 +1578,11 @@ static void guc_flush_submissions(struct intel_guc
> *guc)
> spin_unlock_irqrestore(_engine->lock, flags);
> }
>
> +void intel_guc_submission_flush_work(struct intel_guc *guc)
> +{
> + flush_work(>submission_state.destroyed_worker);
> +}
> +
> static void guc_flush_destroyed_contexts(struct intel_guc *guc);
>
> void intel_guc_submission_reset_prepare(struct intel_guc *guc)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
> index c57b29cdb1a6..b6df75622d3b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
> @@ -38,6 +38,8 @@ int intel_guc_wait_for_pending_msg(struct intel_guc *guc,
> bool interruptible,
> long timeout);
>
> +void intel_guc_submission_flush_work(struct intel_guc *guc);
> +
> static inline bool intel_guc_submission_is_supported(struct intel_guc *guc)
> {
> return guc->submission_supported;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 98b103375b7a..eb3554cb5ea4 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -693,6 +693,8 @@ void intel_uc_suspend(struct intel_uc *uc)
> return;
> }
>
> + intel_guc_submission_flush_work(guc);
> +
> with_intel_runtime_pm(_to_gt(uc)->i915->runtime_pm, wakeref) {
> err = intel_guc_suspend(guc);
> if (err)
> --
> 2.39.0
>
Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/guc: Close deregister-context race against CT-loss
On Sat, Sep 09, 2023 at 08:58:45PM -0700, Alan Previn wrote:
> If we are at the end of suspend or very early in resume
> its possible an async fence signal could lead us to the
> execution of the context destruction worker (after the
> prior worker flush).
>
> Even if checking that the CT is enabled before calling
> destroyed_worker_func, guc_lrc_desc_unpin may still fail
> because in corner cases, as we traverse the GuC's
> context-destroy list, the CT could get disabled in the mid
> of it right before calling the GuC's CT send function.
>
> We've witnessed this race condition once every ~6000-8000
> suspend-resume cycles while ensuring workloads that render
> something onscreen is continuously started just before
> we suspend (and the workload is small enough to complete
> and trigger the queued engine/context free-up either very
> late in suspend or very early in resume).
>
> In such a case, we need to unroll the unpin process because
> guc-lrc-unpin takes a gt wakeref which only gets released in
> the G2H IRQ reply that never comes through in this corner
> case. That will cascade into a kernel hang later at the tail
> end of suspend in this function:
>
>intel_wakeref_wait_for_idle(>wakeref)
>(called by) - intel_gt_pm_wait_for_idle
>(called by) - wait_for_suspend
>
> Doing this unroll and keeping the context in the GuC's
> destroy-list will allow the context to get picked up on
> the next destroy worker invocation or purged as part of a
> major GuC sanitization or reset flow.
>
> Signed-off-by: Alan Previn
> Tested-by: Mousumi Jana
> ---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 76 ---
> 1 file changed, 65 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 0ed44637bca0..db7df1217350 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -235,6 +235,13 @@ set_context_destroyed(struct intel_context *ce)
> ce->guc_state.sched_state |= SCHED_STATE_DESTROYED;
> }
>
> +static inline void
> +clr_context_destroyed(struct intel_context *ce)
> +{
> + lockdep_assert_held(>guc_state.lock);
> + ce->guc_state.sched_state &= ~SCHED_STATE_DESTROYED;
> +}
> +
> static inline bool context_pending_disable(struct intel_context *ce)
> {
> return ce->guc_state.sched_state & SCHED_STATE_PENDING_DISABLE;
> @@ -612,6 +619,8 @@ static int guc_submission_send_busy_loop(struct intel_guc
> *guc,
>u32 g2h_len_dw,
>bool loop)
> {
> + int ret;
> +
> /*
>* We always loop when a send requires a reply (i.e. g2h_len_dw > 0),
>* so we don't handle the case where we don't get a reply because we
> @@ -622,7 +631,11 @@ static int guc_submission_send_busy_loop(struct
> intel_guc *guc,
> if (g2h_len_dw)
> atomic_inc(>outstanding_submission_g2h);
>
> - return intel_guc_send_busy_loop(guc, action, len, g2h_len_dw, loop);
> + ret = intel_guc_send_busy_loop(guc, action, len, g2h_len_dw, loop);
> + if (ret)
> + atomic_dec(>outstanding_submission_g2h);
> +
> + return ret;
> }
>
> int intel_guc_wait_for_pending_msg(struct intel_guc *guc,
> @@ -3173,12 +3186,13 @@ static void guc_context_close(struct intel_context
> *ce)
> spin_unlock_irqrestore(>guc_state.lock, flags);
> }
>
> -static inline void guc_lrc_desc_unpin(struct intel_context *ce)
> +static inline int guc_lrc_desc_unpin(struct intel_context *ce)
> {
> struct intel_guc *guc = ce_to_guc(ce);
> struct intel_gt *gt = guc_to_gt(guc);
> unsigned long flags;
> bool disabled;
> + int ret;
>
> GEM_BUG_ON(!intel_gt_pm_is_awake(gt));
> GEM_BUG_ON(!ctx_id_mapped(guc, ce->guc_id.id));
> @@ -3188,19 +3202,33 @@ static inline void guc_lrc_desc_unpin(struct
> intel_context *ce)
> /* Seal race with Reset */
> spin_lock_irqsave(>guc_state.lock, flags);
> disabled = submission_disabled(guc);
> - if (likely(!disabled)) {
> - __intel_gt_pm_get(gt);
> - set_context_destroyed(ce);
> - clr_context_registered(ce);
> - }
> - spin_unlock_irqrestore(>guc_state.lock, flags);
> if (unlikely(disabled)) {
> + spin_unlock_irqrestore(>guc_state.lock, flags);
> release_guc_id(guc, ce);
> __guc_context_destroy(ce);
> - return;
> + return 0;
> }
>
> - deregister_context(ce, ce->guc_id.id);
> + /* GuC is active, lets destroy this context,
> + * but at this point we can still be racing with
> + * suspend, so we undo everything if the H2G fails
> + */
> +
> + /* Change context state to destroyed and get gt-pm */
> + __intel_gt_pm_get(gt);
> + set_context_destroyed(ce);
> +
Re: [Intel-gfx] [PATCH 00/19] drm/i915: prepare for xe driver display integration
On Tue, Sep 12, 2023 at 02:06:27PM +0300, Jani Nikula wrote: > The upcoming drm/xe driver [1][2] will reuse the drm/i915 display code, > initially by compiling the relevant compilation units separately as part > of the xe driver. This series prepares for that in i915 side. > > The first patch defines I915 during the i915 driver build, to allow > conditional compilation based on the driver the code is being built for. > > The rest of the patches add stubs for functions in files that aren't > used in xe. The idea is that this is the least intrusive way of skipping > that code in xe, and is quite similar to the common kconfig stubs. > > While this is arguably unused code for the time being, or only used in > an out-of-tree driver yet to be upstreamed, the upstreaming has to start > somewhere. I see other benefits on adding this right now through drm-intel-next: 1. Separate the good patches from the other patches that are in drm-xe-next, that would require more work. 2. Minimize the non-xe patches in the xe pull-request. Cleaner and with reduced risk of conflicts. > > > BR, > Jani. > > > [1] https://gitlab.freedesktop.org/drm/xe/kernel/-/tree/drm-xe-next > [2] https://patchwork.freedesktop.org/series/112188/ > > Cc: David Airlie > Cc: Daniel Vetter > Cc: Joonas Lahtinen > Cc: Rodrigo Vivi > Cc: Tvrtko Ursulin > Cc: Lucas De Marchi Yeap, let's for sure get input from other maintainers, but meanwhile I'd like to state that I have once more reviewed these patches and that you can put my rv-b tag in all of them when we get the proper acks. > > Jani Nikula (19): > drm/i915: define I915 during i915 driver build > drm/i915/display: add I915 conditional build to intel_lvds.h > drm/i915/display: add I915 conditional build to hsw_ips.h > drm/i915/display: add I915 conditional build to i9xx_plane.h > drm/i915/display: add I915 conditional build to intel_lpe_audio.h > drm/i915/display: add I915 conditional build to intel_pch_refclk.h > drm/i915/display: add I915 conditional build to intel_pch_display.h > drm/i915/display: add I915 conditional build to intel_sprite.h > drm/i915/display: add I915 conditional build to intel_overlay.h > drm/i915/display: add I915 conditional build to g4x_dp.h > drm/i915/display: add I915 conditional build to intel_dpio_phy.h > drm/i915/display: add I915 conditional build to intel_crt.h > drm/i915/display: add I915 conditional build to vlv_dsi.h > drm/i915/display: add I915 conditional build to i9xx_wm.h > drm/i915/display: add I915 conditional build to g4x_hdmi.h > drm/i915/display: add I915 conditional build to intel_dvo.h > drm/i915/display: add I915 conditional build to intel_sdvo.h > drm/i915/display: add I915 conditional build to intel_tv.h > drm/i915/display: add I915 conditional build to vlv_dsi_pll.h > > drivers/gpu/drm/i915/Makefile | 4 + > drivers/gpu/drm/i915/display/g4x_dp.h | 26 + > drivers/gpu/drm/i915/display/g4x_hdmi.h | 12 +++ > drivers/gpu/drm/i915/display/hsw_ips.h| 35 +++ > drivers/gpu/drm/i915/display/i9xx_plane.h | 23 + > drivers/gpu/drm/i915/display/i9xx_wm.h| 17 > drivers/gpu/drm/i915/display/intel_crt.h | 14 +++ > drivers/gpu/drm/i915/display/intel_dpio_phy.h | 96 +++ > drivers/gpu/drm/i915/display/intel_dvo.h | 6 ++ > .../gpu/drm/i915/display/intel_lpe_audio.h| 18 > drivers/gpu/drm/i915/display/intel_lvds.h | 19 > drivers/gpu/drm/i915/display/intel_overlay.h | 35 +++ > .../gpu/drm/i915/display/intel_pch_display.h | 53 ++ > .../gpu/drm/i915/display/intel_pch_refclk.h | 23 + > drivers/gpu/drm/i915/display/intel_sdvo.h | 13 +++ > drivers/gpu/drm/i915/display/intel_sprite.h | 8 ++ > drivers/gpu/drm/i915/display/intel_tv.h | 6 ++ > drivers/gpu/drm/i915/display/vlv_dsi.h| 13 +++ > drivers/gpu/drm/i915/display/vlv_dsi_pll.h| 9 ++ > 19 files changed, 430 insertions(+) > > -- > 2.39.2 >
[Intel-gfx] [PATCH v5] drm/i915: Added Wa_18022495364
Set the instruction and state cache invalidate bit using INDIRECT_CTX on
every gpu context switch.
The goal of this workaround is to actually perform an explicit
invalidation of that cache (by re-writing the register) during every GPU
context switch, which is accomplished via a "workaround batchbuffer"
that's attached to the context via INDIRECT_CTX. (Matt)
BSpec: 11354
v2:
- Removed extra parentheses from the condition (Lucas)
- Fixed spacing and new line (Lucas)
v3:
- Fixed commit message.
v4:
- Only GEN12 changes are kept (Matt Ropper)
- Fixed the commit message for r-b (Matt Ropper)
- Renamed the register bit in define
v5:
- Moved out the from golden context init (Matt Roper)
- Use INDIRECT_CTX to set bit on each GPU context switch (Matt Roper)
Cc: Lucas De Marchi
Cc: Matt Roper
Signed-off-by: Dnyaneshwar Bhadane
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 0e4c638fcbbf..38f02ef8ed01 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -164,6 +164,8 @@
#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20d4)
#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
+#define GEN12_CS_DEBUG_MODE2 _MMIO(0x20d8)
+#define INSTRUCTION_STATE_CACHE_INVALIDATE REG_BIT(6)
#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
#define GEN9_FFSC_PERCTX_PREEMPT_CTRL(1 << 14)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 967fe4d77a87..fe98039499c5 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1332,6 +1332,15 @@ dg2_emit_draw_watermark_setting(u32 *cs)
return cs;
}
+static u32 *
+gen12_set_instruction_state_cache_invalid(u32 *cs)
+{
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = i915_mmio_reg_offset(GEN12_CS_DEBUG_MODE2);
+ *cs++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);
+ return cs;
+}
+
static u32 *
gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
{
@@ -1345,6 +1354,12 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context
*ce, u32 *cs)
cs = gen12_emit_aux_table_inv(ce->engine, cs);
+ /* Wa_18022495364 */
+ if (IS_ALDERLAKE_P(ce->engine->i915) ||
IS_ALDERLAKE_P_N(ce->engine->i915) ||
+ IS_ALDERLAKE_S(ce->engine->i915) || IS_TIGERLAKE(ce->engine->i915)
||
+ IS_ROCKETLAKE(ce->engine->i915) || IS_DG1(ce->engine->i915))
+ cs = gen12_set_instruction_state_cache_invalid(cs);
+
/* Wa_16014892111 */
if (IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0)
||
IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)
||
--
2.34.1
Re: [Intel-gfx] [PATCH 3/3] drm/i915/dpt: replace GEM_BUG_ON() with drm_WARN_ON()
On Thu, Sep 14, 2023 at 12:34:59PM +0300, Jani Nikula wrote:
> Avoid using GEM_BUG_ON() in display code.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_dpt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
> b/drivers/gpu/drm/i915/display/intel_dpt.c
> index fbfd8f959f17..48582b31b7f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpt.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpt.c
> @@ -29,7 +29,7 @@ static inline struct i915_dpt *
> i915_vm_to_dpt(struct i915_address_space *vm)
> {
> BUILD_BUG_ON(offsetof(struct i915_dpt, vm));
> - GEM_BUG_ON(!i915_is_dpt(vm));
> + drm_WARN_ON(>i915->drm, !i915_is_dpt(vm));
> return container_of(vm, struct i915_dpt, vm);
> }
>
> --
> 2.39.2
>
Re: [Intel-gfx] [PATCH 2/3] drm/i915/fb: replace GEM_WARN_ON() with drm_WARN_ON()
On Thu, Sep 14, 2023 at 12:34:58PM +0300, Jani Nikula wrote: > Avoid using GEM_WARN_ON() in display code. > > Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/display/intel_fb_pin.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c > b/drivers/gpu/drm/i915/display/intel_fb_pin.c > index fffd568070d4..7b42aef37d2f 100644 > --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c > +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c > @@ -35,7 +35,8 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb, >* We are not syncing against the binding (and potential migrations) >* below, so this vm must never be async. >*/ > - GEM_WARN_ON(vm->bind_async_flags); > + if (drm_WARN_ON(_priv->drm, vm->bind_async_flags)) > + return ERR_PTR(-EINVAL); > > if (WARN_ON(!i915_gem_object_is_framebuffer(obj))) > return ERR_PTR(-EINVAL); > -- > 2.39.2 >
Re: [Intel-gfx] [PATCH 1/3] drm/i915/fbc: replace GEM_BUG_ON() to drm_WARN_ON()
On Thu, Sep 14, 2023 at 12:34:57PM +0300, Jani Nikula wrote:
> Avoid using GEM_BUG_ON() in display code.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 14 --
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 817e5784660b..1cb9eec29640 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -333,12 +333,14 @@ static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
> {
> struct drm_i915_private *i915 = fbc->i915;
>
> - GEM_BUG_ON(range_overflows_end_t(u64,
> i915_gem_stolen_area_address(i915),
> -
> i915_gem_stolen_node_offset(>compressed_fb),
> - U32_MAX));
> - GEM_BUG_ON(range_overflows_end_t(u64,
> i915_gem_stolen_area_address(i915),
> -
> i915_gem_stolen_node_offset(>compressed_llb),
> - U32_MAX));
> + drm_WARN_ON(>drm,
> + range_overflows_end_t(u64,
> i915_gem_stolen_area_address(i915),
> +
> i915_gem_stolen_node_offset(>compressed_fb),
> + U32_MAX));
> + drm_WARN_ON(>drm,
> + range_overflows_end_t(u64,
> i915_gem_stolen_area_address(i915),
> +
> i915_gem_stolen_node_offset(>compressed_llb),
> + U32_MAX));
> intel_de_write(i915, FBC_CFB_BASE,
> i915_gem_stolen_node_address(i915, >compressed_fb));
> intel_de_write(i915, FBC_LL_BASE,
> --
> 2.39.2
>
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave and Daniel, Only a fix for blank-screen regression on Chromebooks, targeting stable 6.5. Here goes drm-intel-fixes-2023-09-14: - Only check eDP HPD when AUX CH is shared. (Ville) Thanks, Rodrigo. The following changes since commit 0bb80ecc33a8fb5a682236443c1e740d5c917d1d: Linux 6.6-rc1 (2023-09-10 16:28:41 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2023-09-14 for you to fetch changes up to 7c95ec3b59479bb24093918bbfc801c9f31826f2: drm/i915: Only check eDP HPD when AUX CH is shared (2023-09-12 08:35:32 -0400) - Only check eDP HPD when AUX CH is shared. Ville Syrjälä (1): drm/i915: Only check eDP HPD when AUX CH is shared drivers/gpu/drm/i915/display/intel_bios.c | 21 + drivers/gpu/drm/i915/display/intel_bios.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 7 ++- 3 files changed, 28 insertions(+), 1 deletion(-)
[Intel-gfx] [PULL] drm-misc-fixes
Hi Dave and Daniel, this is the weekly PR for drm-misc-fixes. Best regards Thomas drm-misc-fixes-2023-09-14: Short summary of fixes pull: * radeon: Uninterruptible fence waiting * tests: Fix use-after-free bug * vkms: Revert hrtimer fix The following changes since commit afaf2b38025ab327c85e218f36d1819e777d4d45: Merge tag 'drm-misc-next-fixes-2023-09-11' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes (2023-09-11 16:23:42 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2023-09-14 for you to fetch changes up to 139a27854bf5ce93ff9805f9f7683b88c13074dc: drm/tests: helpers: Avoid a driver uaf (2023-09-14 13:57:58 +0200) Short summary of fixes pull: * radeon: Uninterruptible fence waiting * tests: Fix use-after-free bug * vkms: Revert hrtimer fix Alex Deucher (1): drm/radeon: make fence wait in suballocator uninterrruptable Maíra Canal (1): Revert "drm/vkms: Fix race-condition between the hrtimer and the atomic commit" Thomas Hellström (1): drm/tests: helpers: Avoid a driver uaf Thomas Zimmermann (1): Merge drm/drm-fixes into drm-misc-fixes drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c | 2 +- drivers/gpu/drm/drm_connector.c| 2 ++ drivers/gpu/drm/radeon/radeon_sa.c | 2 +- drivers/gpu/drm/tiny/gm12u320.c| 10 +- drivers/gpu/drm/vkms/vkms_composer.c | 9 ++--- drivers/gpu/drm/vkms/vkms_crtc.c | 9 - drivers/gpu/drm/vkms/vkms_drv.h| 4 +--- include/drm/drm_kunit_helpers.h| 4 +++- 8 files changed, 19 insertions(+), 23 deletions(-) -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Frankenstrasse 146, 90461 Nuernberg, Germany GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman HRB 36809 (AG Nuernberg)
Re: [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately
On Thu, 2023-09-14 at 14:08 +0300, Imre Deak wrote:
> On Thu, Sep 14, 2023 at 01:51:16PM +0300, Luca Coelho wrote:
> > On Thu, 2023-09-14 at 12:55 +0300, Imre Deak wrote:
> > > On Thu, Sep 14, 2023 at 12:33:59PM +0300, Luca Coelho wrote:
> > > > On Thu, 2023-08-24 at 11:04 +0300, Imre Deak wrote:
> > > > > A follow-up patch will need to limit the output link bpp both in the
> > > > > non-DSC and DSC configuration, so track the pipe and link bpp limits
> > > > > separately in the link_config_limits struct.
> > > > >
> > > > > Use .4 fixed point format for link bpp matching the 1/16 bpp
> > > > > granularity
> > > > > in DSC mode and for now keep this limit matching the pipe bpp limit.
> > > > >
> > > > > v2: (Jani)
> > > > > - Add to_bpp_int(), to_bpp_x16() helpers instead of opencoding them.
> > > > > - Rename link_config_limits::link.min/max_bpp to min/max_bpp_x16.
> > > > >
> > > > > Cc: Jani Nikula
> > > > > Signed-off-by: Imre Deak
> > > > > ---
> > > > > .../drm/i915/display/intel_display_types.h| 10
> > > > > drivers/gpu/drm/i915/display/intel_dp.c | 25
> > > > > +++
> > > > > drivers/gpu/drm/i915/display/intel_dp.h | 9 ++-
> > > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 -
> > > > > 4 files changed, 44 insertions(+), 17 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > index 731f2ec04d5cd..5875eff5012ce 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > >
> > > > [...]
> > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> > > > > b/drivers/gpu/drm/i915/display/intel_dp.h
> > > > > index 788a577ebe16e..ebc7f4e60c777 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > > > > @@ -26,7 +26,14 @@ struct intel_encoder;
> > > > > struct link_config_limits {
> > > > > int min_rate, max_rate;
> > > > > int min_lane_count, max_lane_count;
> > > > > - int min_bpp, max_bpp;
> > > > > + struct {
> > > > > + /* Uncompressed DSC input or link output bpp in 1 bpp
> > > > > units */
> > > > > + int min_bpp, max_bpp;
> > > > > + } pipe;
> > > > > + struct {
> > > > > + /* Compressed or uncompressed link output bpp in 1/16
> > > > > bpp units */
> > > > > + int min_bpp_x16, max_bpp_x16;
> > > > > + } link;
> > > > > };
> > > >
> > > > It's not clear to me from the commit message (nor from the code, for
> > > > that matter) why you need to store the values in both formats. Can you
> > > > clarify?
> > >
> > > For DSC configuration two separate limits need to be considered:
> > >
> > > One is the bpp value which is a property of the pixel format input to
> > > the DSC engine, for this the DSC state computation should use the
> > > pipe.min/max_bpp limits and this functionality of the DSC HW block can
> > > be configured in 1 bits per pixel granularity.
> > >
> > > The other one is the bpp value which is the format of pixels output from
> > > the DSC engine (and is the actual pixel format on the link), for which
> > > the DSC state computation should use link.min/max_bpp_x16. The DSC HW
> > > block can be configure this pixel format in 1/16 bits per granularity.
> > >
> > > For instance pipe.min/max_bpp will be 16 .. 30 bpp range (in 1 bpp
> > > units), link.min/max_bpp_x16 in the 8 .. 27 bpp range (in 1/16 bpp
> > > units).
> >
> > Okay, but you're storing these two limits in the link structure. So
> > the important difference between them is not x16 vs non-x16. If it
> > were, you wouldn't have to store both, because you can easily convert
> > them with your new to_*() functions.
> >
> > So, isn't there a better name for these? Maybe input_max/min_bpp and
> > output_max/min_bpp? You could keep the _x16 in the relevant one, but I
> > think the main difference between the two should be reflected in the
> > symbol names.
>
> They are part of a pipe/link sub-structure, so the names are in effect
> pipe.min/max_bpp and link.min/max_bpp_x16. pipe and link in turn are the
> terms used for these same types of bpps elsewhere in DSC and non-DSC
> code, hence I used them here as well for clarity. Maybe the comments
> in the struct could be improved how the limits are used?
Oh, of course. Sorry, I missed that.
Reviewed-by: Luca Coelho
--
Cheers,
Luca.
[Intel-gfx] [PATCH 1/5] drm/i915/fbc: Remove ancient 16k plane stride limit
From: Ville Syrjälä The 16k max plane stride limit seems to be originally from i965gm, and no limit explicit limit has been specified since (g4x+). So let's assume the max plane stride itself is a suitable limit also for the more recent FBC hardware. In fact even for i965gm the max X-tiled stride is also 16k so technically we don't need the check there either, but let's keep it there anyway since it's explicitly mentioned in the spec. Gen2/3 have more strict limits checked separately. Cc: Swati Sharma Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 817e5784660b..1b3358a0fbfb 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -866,7 +866,8 @@ static bool stride_is_valid(const struct intel_plane_state *plane_state) if (DISPLAY_VER(i915) == 2 || DISPLAY_VER(i915) == 3) return stride == 4096 || stride == 8192; - if (DISPLAY_VER(i915) == 4 && !IS_G4X(i915) && stride < 2048) + if (DISPLAY_VER(i915) == 4 && !IS_G4X(i915) && + (stride < 2048 || stride > 16384)) return false; /* Display WA #1105: skl,bxt,kbl,cfl,glk */ @@ -874,9 +875,6 @@ static bool stride_is_valid(const struct intel_plane_state *plane_state) fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511) return false; - if (stride > 16384) - return false; - return true; } -- 2.41.0
[Intel-gfx] [PATCH 4/5] drm/i915/fbc: Split plane rotation checks per-platform
From: Ville Syrjälä
Carve up rotation_is_valid() into per-platform variants to
make it easier to see what limits are actually being imposed.
TODO: maybe go for vfuncs later
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 30 +++-
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 052f9d8b53d4..1a6931e66d5d 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -935,22 +935,40 @@ static bool pixel_format_is_valid(const struct
intel_plane_state *plane_state)
}
}
-static bool rotation_is_valid(const struct intel_plane_state *plane_state)
+static bool i8xx_fbc_rotation_is_valid(const struct intel_plane_state
*plane_state)
+{
+ return plane_state->hw.rotation == DRM_MODE_ROTATE_0;
+}
+
+static bool g4x_fbc_rotation_is_valid(const struct intel_plane_state
*plane_state)
+{
+ return true;
+}
+
+static bool skl_fbc_rotation_is_valid(const struct intel_plane_state
*plane_state)
{
- struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
unsigned int rotation = plane_state->hw.rotation;
- if (DISPLAY_VER(i915) >= 9 && fb->format->format == DRM_FORMAT_RGB565 &&
+ if (fb->format->format == DRM_FORMAT_RGB565 &&
drm_rotation_90_or_270(rotation))
return false;
- else if (DISPLAY_VER(i915) <= 4 && !IS_G4X(i915) &&
-rotation != DRM_MODE_ROTATE_0)
- return false;
return true;
}
+static bool rotation_is_valid(const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+
+ if (DISPLAY_VER(i915) >= 9)
+ return skl_fbc_rotation_is_valid(plane_state);
+ else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
+ return g4x_fbc_rotation_is_valid(plane_state);
+ else
+ return i8xx_fbc_rotation_is_valid(plane_state);
+}
+
/*
* For some reason, the hardware tracking starts looking at whatever we
* programmed as the display plane base address register. It does not look at
--
2.41.0
[Intel-gfx] [PATCH 2/5] drm/i915/fbc: Split plane stride checks per-platform
From: Ville Syrjälä
Carve up stride_is_valid() into per-platform variants to
make it easier to see what limits are actually being imposed.
TODO: maybe go for vfuncs later
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 68 ++--
1 file changed, 51 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 1b3358a0fbfb..4c4626c84666 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -848,6 +848,47 @@ void intel_fbc_cleanup(struct drm_i915_private *i915)
}
}
+static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state
*plane_state)
+{
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int stride = intel_fbc_plane_stride(plane_state) *
+ fb->format->cpp[0];
+
+ return stride == 4096 || stride == 8192;
+}
+
+static bool i965_fbc_stride_is_valid(const struct intel_plane_state
*plane_state)
+{
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int stride = intel_fbc_plane_stride(plane_state) *
+ fb->format->cpp[0];
+
+ return stride >= 2048 && stride <= 16384;
+}
+
+static bool g4x_fbc_stride_is_valid(const struct intel_plane_state
*plane_state)
+{
+ return true;
+}
+
+static bool skl_fbc_stride_is_valid(const struct intel_plane_state
*plane_state)
+{
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int stride = intel_fbc_plane_stride(plane_state) *
+ fb->format->cpp[0];
+
+ /* Display WA #1105: skl,bxt,kbl,cfl,glk */
+ if (fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
+ return false;
+
+ return true;
+}
+
+static bool icl_fbc_stride_is_valid(const struct intel_plane_state
*plane_state)
+{
+ return true;
+}
+
static bool stride_is_valid(const struct intel_plane_state *plane_state)
{
struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
@@ -859,23 +900,16 @@ static bool stride_is_valid(const struct
intel_plane_state *plane_state)
if (drm_WARN_ON_ONCE(>drm, (stride & (64 - 1)) != 0))
return false;
- /* Below are the additional FBC restrictions. */
- if (stride < 512)
- return false;
-
- if (DISPLAY_VER(i915) == 2 || DISPLAY_VER(i915) == 3)
- return stride == 4096 || stride == 8192;
-
- if (DISPLAY_VER(i915) == 4 && !IS_G4X(i915) &&
- (stride < 2048 || stride > 16384))
- return false;
-
- /* Display WA #1105: skl,bxt,kbl,cfl,glk */
- if ((DISPLAY_VER(i915) == 9 || IS_GEMINILAKE(i915)) &&
- fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
- return false;
-
- return true;
+ if (DISPLAY_VER(i915) >= 11)
+ return icl_fbc_stride_is_valid(plane_state);
+ else if (DISPLAY_VER(i915) >= 9)
+ return skl_fbc_stride_is_valid(plane_state);
+ else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
+ return g4x_fbc_stride_is_valid(plane_state);
+ else if (DISPLAY_VER(i915) == 4)
+ return i965_fbc_stride_is_valid(plane_state);
+ else
+ return i8xx_fbc_stride_is_valid(plane_state);
}
static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
--
2.41.0
[Intel-gfx] [PATCH 5/5] drm/i915/fbc: Split plane pixel format checks per-platform
From: Ville Syrjälä
Carve up pixel_format_is_valid() into per-platform variants to
make it easier to see what limits are actually being imposed.
Note that the XRGB1555 can be dropped from the g4x+ variant
since the plane no longer supports that format anyway.
TODO: maybe go for vfuncs later
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 1a6931e66d5d..51998b1ec941 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -912,7 +912,7 @@ static bool stride_is_valid(const struct intel_plane_state
*plane_state)
return i8xx_fbc_stride_is_valid(plane_state);
}
-static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
+static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state
*plane_state)
{
struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
@@ -926,6 +926,22 @@ static bool pixel_format_is_valid(const struct
intel_plane_state *plane_state)
/* 16bpp not supported on gen2 */
if (DISPLAY_VER(i915) == 2)
return false;
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state
*plane_state)
+{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+
+ switch (fb->format->format) {
+ case DRM_FORMAT_XRGB:
+ case DRM_FORMAT_XBGR:
+ return true;
+ case DRM_FORMAT_RGB565:
/* WaFbcOnly1to1Ratio:ctg */
if (IS_G4X(i915))
return false;
@@ -935,6 +951,16 @@ static bool pixel_format_is_valid(const struct
intel_plane_state *plane_state)
}
}
+static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+
+ if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
+ return g4x_fbc_pixel_format_is_valid(plane_state);
+ else
+ return i8xx_fbc_pixel_format_is_valid(plane_state);
+}
+
static bool i8xx_fbc_rotation_is_valid(const struct intel_plane_state
*plane_state)
{
return plane_state->hw.rotation == DRM_MODE_ROTATE_0;
--
2.41.0
[Intel-gfx] [PATCH 3/5] drm/i915/fbc: Split plane tiling checks per-platform
From: Ville Syrjälä
Carve up tiling_is_valid() into per-platform variants to
make it easier to see what limits are actually being imposed.
TODO: maybe go for vfuncs later
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 4c4626c84666..052f9d8b53d4 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -984,16 +984,21 @@ static bool intel_fbc_hw_tracking_covers_screen(const
struct intel_plane_state *
return effective_w <= max_w && effective_h <= max_h;
}
-static bool tiling_is_valid(const struct intel_plane_state *plane_state)
+static bool i8xx_fbc_tiling_valid(const struct intel_plane_state *plane_state)
+{
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+
+ return fb->modifier == I915_FORMAT_MOD_X_TILED;
+}
+
+static bool skl_fbc_tiling_valid(const struct intel_plane_state *plane_state)
{
- struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
switch (fb->modifier) {
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
- return DISPLAY_VER(i915) >= 9;
case I915_FORMAT_MOD_4_TILED:
case I915_FORMAT_MOD_X_TILED:
return true;
@@ -1002,6 +1007,16 @@ static bool tiling_is_valid(const struct
intel_plane_state *plane_state)
}
}
+static bool tiling_is_valid(const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+
+ if (DISPLAY_VER(i915) >= 9)
+ return skl_fbc_tiling_valid(plane_state);
+ else
+ return i8xx_fbc_tiling_valid(plane_state);
+}
+
static void intel_fbc_update_state(struct intel_atomic_state *state,
struct intel_crtc *crtc,
struct intel_plane *plane)
--
2.41.0
[Intel-gfx] [PATCH] drm/edid: Fixup h/vsync_end instead of h/vtotal
From: Ville Syrjälä
There are some weird EDIDs floating around that have the sync
pulse extending beyond the end of the blanking period.
On the currently problemtic machine (HP Omni 120) EDID reports
the following mode:
"1600x900": 60 108000 1600 1780 1860 1800 900 910 913 1000 0x40 0x5
which is then "corrected" to have htotal=1861 by the current drm_edid.c
code.
The fixup code was originally added in commit 7064fef56369 ("drm: work
around EDIDs with bad htotal/vtotal values"). Googling around we end up in
https://bugs.launchpad.net/ubuntu/hardy/+source/xserver-xorg-video-intel/+bug/297245
where we find an EDID for a Dell Studio 15, which reports:
(II) VESA(0): clock: 65.0 MHz Image Size: 331 x 207 mm
(II) VESA(0): h_active: 1280 h_sync: 1328 h_sync_end 1360 h_blank_end 1337
h_border: 0
(II) VESA(0): v_active: 800 v_sync: 803 v_sync_end 809 v_blanking: 810
v_border: 0
Note that if we use the hblank size (as opposed of the hsync_end)
from the DTD to determine htotal we get exactly 60Hz refresh rate in
both cases, whereas using hsync_end to determine htotal we get a
slightly lower refresh rates. This makes me believe the using the
hblank size is what was intended even in those cases.
Also note that in case of the HP Onmi 120 the VBIOS boots with these:
crtc timings: 108000 1600 1780 1860 1800 900 910 913 1000, type: 0x40 flags:
0x5
ie. it just blindly stuffs the bogus hsync_end and htotal from the DTD
into the transcoder timing registers, and the display works. I believe
the (at least more modern) hardware will automagically terminate the hsync
pulse when the timing generator reaches htotal, which again points that we
should use the hblank size to determine htotal. Unfortunatley the old bug
reports for the Dell machines are extremely lacking in useful details so
we have no idea what kind of timings the VBIOS programmed into the
hardware :(
Let's just flip this quirk around and reduce the length of the sync
pulse instead of extending the blanking period. This at least seems
to be the correct thing to do on more modern hardware. And if any
issues crop up on older hardware we need to debug them properly.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8895
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 39dd3f694544..0c5563b4d21e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3497,11 +3497,11 @@ static struct drm_display_mode
*drm_mode_detailed(struct drm_connector *connecto
mode->vsync_end = mode->vsync_start + vsync_pulse_width;
mode->vtotal = mode->vdisplay + vblank;
- /* Some EDIDs have bogus h/vtotal values */
+ /* Some EDIDs have bogus h/vsync_end values */
if (mode->hsync_end > mode->htotal)
- mode->htotal = mode->hsync_end + 1;
+ mode->hsync_end = mode->htotal;
if (mode->vsync_end > mode->vtotal)
- mode->vtotal = mode->vsync_end + 1;
+ mode->vsync_end = mode->vtotal;
drm_mode_do_interlace_quirk(mode, pt);
--
2.41.0
Re: [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately
On Thu, Sep 14, 2023 at 01:51:16PM +0300, Luca Coelho wrote:
> On Thu, 2023-09-14 at 12:55 +0300, Imre Deak wrote:
> > On Thu, Sep 14, 2023 at 12:33:59PM +0300, Luca Coelho wrote:
> > > On Thu, 2023-08-24 at 11:04 +0300, Imre Deak wrote:
> > > > A follow-up patch will need to limit the output link bpp both in the
> > > > non-DSC and DSC configuration, so track the pipe and link bpp limits
> > > > separately in the link_config_limits struct.
> > > >
> > > > Use .4 fixed point format for link bpp matching the 1/16 bpp granularity
> > > > in DSC mode and for now keep this limit matching the pipe bpp limit.
> > > >
> > > > v2: (Jani)
> > > > - Add to_bpp_int(), to_bpp_x16() helpers instead of opencoding them.
> > > > - Rename link_config_limits::link.min/max_bpp to min/max_bpp_x16.
> > > >
> > > > Cc: Jani Nikula
> > > > Signed-off-by: Imre Deak
> > > > ---
> > > > .../drm/i915/display/intel_display_types.h| 10
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 25 +++
> > > > drivers/gpu/drm/i915/display/intel_dp.h | 9 ++-
> > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 -
> > > > 4 files changed, 44 insertions(+), 17 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index 731f2ec04d5cd..5875eff5012ce 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > >
> > > [...]
> > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> > > > b/drivers/gpu/drm/i915/display/intel_dp.h
> > > > index 788a577ebe16e..ebc7f4e60c777 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > > > @@ -26,7 +26,14 @@ struct intel_encoder;
> > > > struct link_config_limits {
> > > > int min_rate, max_rate;
> > > > int min_lane_count, max_lane_count;
> > > > - int min_bpp, max_bpp;
> > > > + struct {
> > > > + /* Uncompressed DSC input or link output bpp in 1 bpp
> > > > units */
> > > > + int min_bpp, max_bpp;
> > > > + } pipe;
> > > > + struct {
> > > > + /* Compressed or uncompressed link output bpp in 1/16
> > > > bpp units */
> > > > + int min_bpp_x16, max_bpp_x16;
> > > > + } link;
> > > > };
> > >
> > > It's not clear to me from the commit message (nor from the code, for
> > > that matter) why you need to store the values in both formats. Can you
> > > clarify?
> >
> > For DSC configuration two separate limits need to be considered:
> >
> > One is the bpp value which is a property of the pixel format input to
> > the DSC engine, for this the DSC state computation should use the
> > pipe.min/max_bpp limits and this functionality of the DSC HW block can
> > be configured in 1 bits per pixel granularity.
> >
> > The other one is the bpp value which is the format of pixels output from
> > the DSC engine (and is the actual pixel format on the link), for which
> > the DSC state computation should use link.min/max_bpp_x16. The DSC HW
> > block can be configure this pixel format in 1/16 bits per granularity.
> >
> > For instance pipe.min/max_bpp will be 16 .. 30 bpp range (in 1 bpp
> > units), link.min/max_bpp_x16 in the 8 .. 27 bpp range (in 1/16 bpp
> > units).
>
> Okay, but you're storing these two limits in the link structure. So
> the important difference between them is not x16 vs non-x16. If it
> were, you wouldn't have to store both, because you can easily convert
> them with your new to_*() functions.
>
> So, isn't there a better name for these? Maybe input_max/min_bpp and
> output_max/min_bpp? You could keep the _x16 in the relevant one, but I
> think the main difference between the two should be reflected in the
> symbol names.
They are part of a pipe/link sub-structure, so the names are in effect
pipe.min/max_bpp and link.min/max_bpp_x16. pipe and link in turn are the
terms used for these same types of bpps elsewhere in DSC and non-DSC
code, hence I used them here as well for clarity. Maybe the comments
in the struct could be improved how the limits are used?
> --
> Cheers,
> Luca.
Re: [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately
On Thu, 2023-09-14 at 12:55 +0300, Imre Deak wrote:
> On Thu, Sep 14, 2023 at 12:33:59PM +0300, Luca Coelho wrote:
> > On Thu, 2023-08-24 at 11:04 +0300, Imre Deak wrote:
> > > A follow-up patch will need to limit the output link bpp both in the
> > > non-DSC and DSC configuration, so track the pipe and link bpp limits
> > > separately in the link_config_limits struct.
> > >
> > > Use .4 fixed point format for link bpp matching the 1/16 bpp granularity
> > > in DSC mode and for now keep this limit matching the pipe bpp limit.
> > >
> > > v2: (Jani)
> > > - Add to_bpp_int(), to_bpp_x16() helpers instead of opencoding them.
> > > - Rename link_config_limits::link.min/max_bpp to min/max_bpp_x16.
> > >
> > > Cc: Jani Nikula
> > > Signed-off-by: Imre Deak
> > > ---
> > > .../drm/i915/display/intel_display_types.h| 10
> > > drivers/gpu/drm/i915/display/intel_dp.c | 25 +++
> > > drivers/gpu/drm/i915/display/intel_dp.h | 9 ++-
> > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 -
> > > 4 files changed, 44 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 731f2ec04d5cd..5875eff5012ce 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >
> > [...]
> >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> > > b/drivers/gpu/drm/i915/display/intel_dp.h
> > > index 788a577ebe16e..ebc7f4e60c777 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > > @@ -26,7 +26,14 @@ struct intel_encoder;
> > > struct link_config_limits {
> > > int min_rate, max_rate;
> > > int min_lane_count, max_lane_count;
> > > - int min_bpp, max_bpp;
> > > + struct {
> > > + /* Uncompressed DSC input or link output bpp in 1 bpp units */
> > > + int min_bpp, max_bpp;
> > > + } pipe;
> > > + struct {
> > > + /* Compressed or uncompressed link output bpp in 1/16 bpp units
> > > */
> > > + int min_bpp_x16, max_bpp_x16;
> > > + } link;
> > > };
> >
> > It's not clear to me from the commit message (nor from the code, for
> > that matter) why you need to store the values in both formats. Can you
> > clarify?
>
> For DSC configuration two separate limits need to be considered:
>
> One is the bpp value which is a property of the pixel format input to
> the DSC engine, for this the DSC state computation should use the
> pipe.min/max_bpp limits and this functionality of the DSC HW block can
> be configured in 1 bits per pixel granularity.
>
> The other one is the bpp value which is the format of pixels output from
> the DSC engine (and is the actual pixel format on the link), for which
> the DSC state computation should use link.min/max_bpp_x16. The DSC HW
> block can be configure this pixel format in 1/16 bits per granularity.
>
> For instance pipe.min/max_bpp will be 16 .. 30 bpp range (in 1 bpp
> units), link.min/max_bpp_x16 in the 8 .. 27 bpp range (in 1/16 bpp
> units).
Okay, but you're storing these two limits in the link structure. So
the important difference between them is not x16 vs non-x16. If it
were, you wouldn't have to store both, because you can easily convert
them with your new to_*() functions.
So, isn't there a better name for these? Maybe input_max/min_bpp and
output_max/min_bpp? You could keep the _x16 in the relevant one, but I
think the main difference between the two should be reflected in the
symbol names.
--
Cheers,
Luca.
Re: [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately
On Thu, Sep 14, 2023 at 12:33:59PM +0300, Luca Coelho wrote:
> On Thu, 2023-08-24 at 11:04 +0300, Imre Deak wrote:
> > A follow-up patch will need to limit the output link bpp both in the
> > non-DSC and DSC configuration, so track the pipe and link bpp limits
> > separately in the link_config_limits struct.
> >
> > Use .4 fixed point format for link bpp matching the 1/16 bpp granularity
> > in DSC mode and for now keep this limit matching the pipe bpp limit.
> >
> > v2: (Jani)
> > - Add to_bpp_int(), to_bpp_x16() helpers instead of opencoding them.
> > - Rename link_config_limits::link.min/max_bpp to min/max_bpp_x16.
> >
> > Cc: Jani Nikula
> > Signed-off-by: Imre Deak
> > ---
> > .../drm/i915/display/intel_display_types.h| 10
> > drivers/gpu/drm/i915/display/intel_dp.c | 25 +++
> > drivers/gpu/drm/i915/display/intel_dp.h | 9 ++-
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 -
> > 4 files changed, 44 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 731f2ec04d5cd..5875eff5012ce 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>
> [...]
>
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> > b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 788a577ebe16e..ebc7f4e60c777 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -26,7 +26,14 @@ struct intel_encoder;
> > struct link_config_limits {
> > int min_rate, max_rate;
> > int min_lane_count, max_lane_count;
> > - int min_bpp, max_bpp;
> > + struct {
> > + /* Uncompressed DSC input or link output bpp in 1 bpp units */
> > + int min_bpp, max_bpp;
> > + } pipe;
> > + struct {
> > + /* Compressed or uncompressed link output bpp in 1/16 bpp units
> > */
> > + int min_bpp_x16, max_bpp_x16;
> > + } link;
> > };
>
> It's not clear to me from the commit message (nor from the code, for
> that matter) why you need to store the values in both formats. Can you
> clarify?
For DSC configuration two separate limits need to be considered:
One is the bpp value which is a property of the pixel format input to
the DSC engine, for this the DSC state computation should use the
pipe.min/max_bpp limits and this functionality of the DSC HW block can
be configured in 1 bits per pixel granularity.
The other one is the bpp value which is the format of pixels output from
the DSC engine (and is the actual pixel format on the link), for which
the DSC state computation should use link.min/max_bpp_x16. The DSC HW
block can be configure this pixel format in 1/16 bits per granularity.
For instance pipe.min/max_bpp will be 16 .. 30 bpp range (in 1 bpp
units), link.min/max_bpp_x16 in the 8 .. 27 bpp range (in 1/16 bpp
units).
>
> --
> Cheers,
> Luca.
